Packet Telephony Development Kit PSTN Card User`s Guide
Contents
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7. OG v IL 201 9 Z 39euuo 107 Z 9 0 ALON t 5 0 45 30i 08H SION H d ENOO 8 S 0241 8 m t t l tn tn a 2 5 99 8 0841035 083 5 4H 8 i yrr 054 lt 98010 SILEN v e 1 SZ de 307 779 ST oan gt 4 sta bg een ad 110191 SION ponos 8 Kv 80 10 979 dS 2 5 30 924 lt is z ASX NOQX ZX WAX Hozr lt u3wvud 10 797 0 9141 L SUT 10dX star vid het gt lt 21 0 dS SUZ lt E ozin smy P A za SION E28 ENQO 21M0 dS 3c H e E 2 229 lt 21 0 dS SHZ 19945 SL 10 OL 002 21 eunr Aepsinug 24 oz 8 JequinN ezig 91 avno SXHOMLUN enu IL 201 9 3 201 4 9 T 205 4591 asin
8. HOLOSNNOO OL 22 NNOO 61 61 8 SOLOSNNOO uso Lal SL 20 WAL 616148 US NNOD 57 NNOD SY zd NNOD Y NNOD 97 NNOD SY NNOD YY 90 NNOD tv 28 07 NNOD 6 6 NNOD 9 010 NNOD 9 210 NNOO NNOD YE NNOD NNOD 97 __ NNOO Sc __ NNOO pe lt 2 NNOO Ec 9zdv NNOO ee z V NNOO TC 8zdv_NNOO 02 620 NNOO 8T NNOO TALON TE 54 2 x GL 616148 oiosNNOO auvosasva SL 10 F3 2002 21 eun 24 lt 000 gt a 9215 5 SNHOMLSUN TWHNW l gt fo 299999 00000000 ec 1 sta ou b SION zia sng 4M ou g 72H48 NYM WOE gp ugWvHdM LOX 30 7219 3 na AE 8 91 NYM crono 2 6 sng ig ou g ouez Hug NVM USWYHALS 10 5 aum 5 od 960 NYM v d XION gr 544 u 3 9av 1 sav N eday ONG
9. k Loopback gt gt TXO Output Transmit RX1 Serial m Data Memory gt Multiplex c Serial TX1 Data Data RX2 gt Streams Streams gt 2 RX3 gt Internal Connection Registers Memory Timing Unit Microprocessor Interface src Il 4x CLK FE WFPS 5 DS Ccs R W A 0 7 DTA D 8 15 HCLK ALE RD WR AD 0 7 Figure 4 TSI Module In the PSTN card the TSI connects to the codec Duslic analog part of the PSTN card QUADFALC digital part of the PSTN card and CPLD Figure 5 shows an overview of all PSTN modules that connect to the TSI Table 2 shows how the TSI connects the TDM streams Table 2 TSI Connections TSI Stream Connects to 0 Baseboard connector 1 E1 T1 PSTN card interface 3 Plain Old Telephone Service POTS Analog Telephony PSTN card interface 4 Baseboard connector Packet Telephony Development Kit PSTN Card Rev 1 Freescale Semiconductor 5 PSTN Card Components Duslic RJ11 SLIC Infineon Codec Infineon RJ11 SLIC Infineon Duslic RJ11 SLI
10. 66H dS 992 Si P z 6002721 Sunr AepSMUL Tare 02 lt oog gt 8 JequinN 1ueuinooq 9219 ovd avno en SXHOMINN TWHNW IL 303 6 9 Z JoOsuUOD 101 ALON 051 0091 E M M SION dS 301 uvas ovo aec x zen gt os ENOO E 7 T E a 3 t m E AEQGAV 52 ie Ns sia P 051 009 1 ho XNbZOS dSOL gt HSIN 9 H __ MOWLSP Str NNOO gen 4 PUN GSG s gg voad m Loe o Leg ES Lge 49 pees eT 091 0091 ENOJ 1 049732 d 2 4 2 W3X NOQX ZYX 7c p Vor lt 10 Loe Sen nr V dX bg uvais anaq lt 21 0 49 GHZ ven ozava t ec er E a 3 t vid 3210 smy WF EZ BT 0S1 00981 SION XNbZOS dSOL 2 Noora ENO 21M0 dS sen 2 or 19949
11. ALON ES 081 0091 2 gen 0891 00991 8 e 16 Spr NNOO ven ons oTt 949 4 0 7 051 0091 ezn uvas zen 081 0091 lan g XNpZOS dS9L cuxToSs 2084 codd eXxXIoS T T SZiMO 45 30i 688 ALON t a ES y or a M E a smy D 2 B 2825 B gr SEM dS 30i m ALON N tNOO Z1M0 49 32 p E f ap om Ww 68H 921 0 dS 982 A ozava t i A peno S azin sa A QGAV fo ALON Z8 d 32 E 2 lt 21 0 dS 992 30 lt u3Wvud 10 19945
12. Figure 1 PSTN Hardware Overview The PSTN card architecture consists of five main functional blocks as shown in Figure 2 e Time slot switch 3 3 V time slot interchange TSI digital switch IDT72V70800 e Digital EI TI interface Quad E1 T1 J1 framer and line interface component for long haul and short haul applications PEB22554 V1 3 e PLL synchronization module WAN PLL with single reference input IDT82V30001A e Complex programmable logic device CPLD A low power 3 3V 32 macro cell device XCR3032XL used for PLL control reset and chip select management e Plain Old Telephone Service POTS Two dual channel subscriber line interfaces PEB3264 2 for analog telephone access Packet Telephony Development Kit PSTN Card Rev 1 Freescale Semiconductor Packet Telephony Development Kit Serial Peripheral Interface SPI Analog POTS Analog Lines POTS Time Reset Slot 4 gt Switch Microprocessor IDF70800 Bug CPLD Chip Digital melee T1 E1 Lines E1 T1 li Interface Pulse Code Modulation PCM Bus 1 PCM System Configuration PLL Synchronization Module IDT 82V3001A Figure 2 PSTN Card Architecture 1 Packet Telephony Development Kit The Packet Telephony Development kit PDK is a platform for evaluating and developing voiceover packet appl
13. PUT SMYOMLAN IVH V 8 0 Wai anyo anyo anyo anyo anyo anyo anyo WI 19250 v 589 80 189 080 60 8 0 9 0 EH auod auod 2 SSA miog SSA 27 2 SSA TOT SSA rs 2 SS anyo anyo anyo anyo anyo anyo anyo SSA SSA 8 0 0 210 042 690 Ur vUSSA o SUSSA LSet ZUSSA LASSA yndjno YXSS 8 E XSS ZXSSA gaegang T4 XSS 34014711950 32012 S ES v8EIN9L 408 280 ALIA az n _ 30 30 0 H 11 lt ey ON OGL err wat err ON SNL SWL quvogasva MOL HT MOL L OYL 3 105 OS g Lido SVEL ZHOIO3NNOO duvodasva XION RS WAL Si gr z90198NN05 quvosssva OW or sta Mad Se gor 719 Lye HINI ZOJ OL Wal t COT eld 29 T 9241 HOLOHNNOO quvoddsvH OL so LWGL SO 20d H
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15. 2 721 on on Nar SO 204 SANNOO quvouasve WOW 095 SOW 46 57 lt lt lt lt gt gt awvu4 oO vl 60 260 160 060 8888 zy NNOO N zen lt NNOO 84 5 5 How to Reach Us Home Page www freescale com E mail support freescale com USA Europe or Locations not listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 1 800 521 6274 or 1 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GMBH Technical Information Center Schatzbogen 7 81829 M nchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 441 2447 or 303 675 2140 Fax 30
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33. 5 lt 30 eu x pz 801 oe aaa swon 5 901 589 gt SWA s yg axa H 30 19 3 gt 5 NYM 1 30 59 xX x VOL T vit bs 1 521 0 OME su f TWOA 1 lt 2 019 90 10 1047104 VLINOA Her 294 Log ze TS 401 39089 60 iih ie 921 0 di 3027 SZLMO di 3089 ZIN ZOd OL lt lt 5 _ dor 30021 u zu L 0SO 148 80 81 mE gt We 5 a 9r OL 5 5 3o VET sr 190 81 gt 89 OSOWIdS Wal lt Lnoaina YNOGO ISONIdS gt 9 081 VZO 20 5 VIO Lee 5 Hey 5 L vd90 77 VI 5 gg 10198 gt VL NOV S ze ZWOVWOd VdOV beg dov 5 lt Ss lt lt lt s SoG P E 9 2 9 ka E EN AOS 401 iH gt AOS 901730001 AOS 901730001 AOS 01 4900 zu n n 42 90 anyo T 9 zo WAAAY HUQ OT 19909
34. 0891 00991 8 e 16 Spr NNOO ven ons oTt 949 4 0 7 051 0091 ezn uvas zen 081 0091 lan g XNpZOS dS9L cuxToSs 2084 codd eXxXIoS T T SZiMO 45 30i 688 ALON t a ES y or a M E a smy D 2 B 2825 B gr SEM dS 30i m ALON N tNOO Z1M0 49 32 p E f ap om Ww 68H 921 0 dS 982 A ozava t i A peno S azin sa A QGAV fo ALON Z8 d 32 E 2 lt 21 0 dS 992 30 lt u3Wvud 10 19945 Si m 6002721 SUN 19120 oz og JequinN 1ueuin2oq 9219 avno enu SNHOMLNN
35. Eid Ur 44 20d OL 60 NNOO 27 7 E 7 St NNOD UF 7 7 sg Teqv NNOD YE 7 t X PEE ec rr 4 1 1 NNOD 2 70 NNOD 9t et TE 05 52 90 NNOD t w b Ez NNOO 2 ze M Fan ety 820 NNOO SG NNOO 9 57 v 89 12 5 6 T errno 82 4 ve c 220 NNOO _ 22 TC z d AS e i 920 NNOO 02 sr d NNOO NNOO zz BT 10 Say NNOS 91 ST gt gt 13938 war 98 02 1 NNOO YF BT 4 YT ET 4 or TT Id NNOD AS 9r er TT gt OF 5 1 rd r vir 89 NNOO UT 0 1 er T T SWL OWLS 8 UT 8 ats _ he 8 1641 SvIrX amp z T 180 146 v EE L T AS vie AS uo EST ST TEY sir dmi eir uo 957 ST OW qr eR Ag Et 6 01 SleNeadAa K Td NVM Qd 91 3GOW SL 29 wes oles 4 91 22 uesd qi 91 6 lt owJdO 053 6 eubTS 2S4 ZH
36. GND 34 NC 35 NC 36 Vcc 5 0 V 37 NC 38 GND 39 NC 40 NC 41 NC 42 Voc 5 0 V Freescale Semiconductor Packet Telephony Development Kit PSTN Card Rev 1 19 PSTN Card Interface Table 15 PTMC 14 Header Continued Pin Signal Pin Signal 43 NC 44 GND 45 GND 46 NC 47 NC 48 NC 49 NC 50 NC 51 GND 52 NC 53 NC 54 NC 55 CT_D4 56 GND 57 Voc 5 0 V 58 D5 59 60 61 CT_DO 62 GND 63 GND 64 CT D1 Table 16 PTMC 13 Header Pin Signal Pin Signal 1 NC 2 NC 3 GND 4 NC 5 NC 6 NC 7 NC 8 Voc 5 0 V 9 NC 10 NC 11 GND 12 NC 13 NC 14 GND 15 GND 16 NC 17 NC 18 Voc 5 0 V 19 8 3 V 20 21 22 23 24 GND 25 GND 26 NC 27 NC 28 NC 29 NC 30 Voc 5 0 V 31 NC 32 NC 33 NC 34 GND 35 GND 36 NC 37 NC 38 Voc 5 0 V 20 Packet Telephony Development Kit PSTN Card Rev 1 Freescale Semiconductor Default TDM Interface Timing Table 16 PTMC 13 Header Continued Pin Signal Pin Signal 39 GND 40 NC 41 42 43 NC 44 GND 45 Voc 3 3 V 46 NC 47 NC 48 NC 49 NC 50 5 0 V 51 GND 52 NC 53 NC 54 NC 55 TDM GPIO2 56 GND 57 Voc 3 3 V 58 TO 2 INT2 59 GPIO1 60 TO 2 INT3 61 TDM GPIOO 62 5 0 V 63 GND 64 NC 7 Default TDM Interface Timi
37. Power comes from power connector J17 Shunt pins 2 3 Power comes from the baseboard Selects source of VHR Ringing power supply Baseboard power Pins 2 3 connected J20 Shunt pins 1 2 Power comes from power connector J17 Shunt pins 2 3 Power comes from the baseboard 5 Power Connector Table 13 lists all power supplies used in the PSTN card from J17 The 48 V battery supply must be sourced through this connector All other supplies can come either from the baseboard or through J17 by using jumpers 118 720 Table 13 PSTN Power Supply Distribution Pin Value Description 1 3 3V power By default the 3 3 V power comes from the baseboard See Table 12 2 45V 5 V power By default the 5 V power comes from the baseboard See Table 12 3 48 V Ringing voltage for telephones 4 48 V Battery supply for telephones 5 GND 6 GND 6 PSTN Card Interface The baseboard and the PSTN card share common signals such as address data and control lines The signals travel through PTMC connectors that connect the PDK baseboard to the PSTN card as shown in Figure 12 Packet Telephony Development Kit PSTN Card Rev 1 Freescale Semiconductor 17 PSTN Card Interface P13 P15 P14 Figure 12 Baseboard PTMC Connected Table 14 15 Header Pin
38. Signal Pin Signal 1 TDM_SPI_CS1 2 JTAG_TRST 3 JTAG_TMS 4 TDM_TDO 5 TDM_TDI 6 GND 7 GND 8 JTAG_TCK 9 CONN_DO 10 CONN_AD23 11 CONN_D1 12 Vcc 5 0 v 13 TDM_RESET 14 CONN_AD24 15 Vcc 5 0 v 16 CONN_AD25 17 CONN_D2 18 GND 19 CONN_D3 20 CONN_AD26 21 GND 22 CONN_AD27 23 CONN_D4 24 Vcc 3 3 v 25 CONN_D5 26 CONN_AD28 27 Vcc 3 3 v 28 CONN AD29 29 CONN D6 30 GND 31 CONN D7 32 CONN AD30 33 GND 34 CONN AD31 35 CONN D8 36 Vcc 3 3 v 37 GND 38 2 39 CONN_D9 40 GND 41 3 3 42 PQ2 CS TDM1 43 CONN D10 44 GND 45 CONN D11 46 TDM GPL2 Packet Telephony Development Kit PSTN Card Rev 1 18 Freescale Semiconductor Table 14 15 Header Continued PSTN Card Interface Pin Signal Pin Signal 47 GND 48 TDM GPL1 49 CONN D12 50 Vcc 3 3 v 51 CONN D13 52 PQ2 CS TDM2 53 Vcc 3 3 v 54 SPI 50 55 CONN_D14 56 GND 57 CONN_D15 58 TDM_SPIMOSO 59 GND 60 TDM_SPIMOSI 61 CONN_AD22 62 Vcc 3 3 v 63 GND 64 TDM SPICLK Table 15 PTMC 14 Header Pin Signal Pin Signal 1 NC 2 GND 3 GND 4 Voc 5 0 V 5 NC 6 NC 7 Voc 5 0 V 8 GND 9 NC 10 Voc 5 0 V 11 Vcc 5 0 V 12 NC 13 NC 14 GND 15 GND 16 NC 17 CT FRAME A 18 Voc 5 0 V 19 NC 20 GND 21 NC 22 NC 23 NC 24 5 0 V 25 CT C8 A 26 GND 27 GND 28 NC 29 NC 30 NC 31 NC 32 GND 33
39. end of CPLD address decoder Following process is to implement the two bit latch for mode select signals for WAN PLL Default mode is NORMAL MODE i e both signals are 0 WAN PLL mode can be changed by writing into latch at address CONN AD 22 30 1XXXX0000 using CONN D 14 15 process signal cpld dec 0 TDM RESET CONN D15 CONN 14 5 1 bar begin if TDM RESET 0 then PLD MODE SELO 0 PLD MODE SEL1 lt 0 elsif signal cpld dec 0 0 and signal w bar 0 then PLD MODE SELO lt CONN D15 PLD MODE SEL1 CONN D14 end if end process implementation of two bit latch for Input reference frequency select signals for WAN PLL Default Input reference frequency is 1 544 MHz 1 mode WAN PLL Input reference frequency can be changed by writing into latch at address CONN AD 22 30 1XXXX0001 using CONN D 14 15 process signal cpld dec 1 CONN D15 CONN Di4 signal bar TDM RESET begin if TDM RESET 0 then LD F SELO 0 PLD SEL1 lt 1 elsif signal cpld dec 1 0 and signal bar 0 then PLD SELO lt CONN D15 Packet Telephony Development Kit PSTN Card Rev 1 Freescale Semiconductor 23 X Default TDM Interface Timing PLD SEL1 lt CONN D14 end if end process implementation of status read signal NORMAL PLD of WAN PLL at ADDRESS CONN AD 22 3
40. the timing reference source This is a QUADFALC software configuration feature Packet Telephony Development Kit PSTN Card Rev 1 12 Freescale Semiconductor PSTN Card Components SCLKR1 1 1 1 1 1 XPA1 22554 T1 E1 QUADFALC 1 1 ______ 1 ____________ gt F ref 8 192M 4 1 544 2 048 MHz C8 d PCM System F8 gt 8K Bus MCLK IDT82V3001 16 384 MHz Sync C4 gt 4 096 XTAL Osc TSI 20 ppm C16 16 384M Switch Figure 10 WAN PLL Device in Support of Slave Clocking Mode To operate the PLL device in Normal mode the Mode_sel_0 signal must be set to 0 and the Mode_sel_1 signal must be set to 0 through the CPLD as shown in Table 7 To complete the PLL configuration the input reference frequency into the PLL must also be selected In this case the PRI frequency is 1 544 MHz in North America or 2 048 MHz in Europe Frequency selection of 1 544 MHz North America is achieved by setting Freq_sel_0 0 Freq_sel_1 1 via the CPLD For Europe the values are Freq sel 0 1 and Freq_sel_1 1 via the CPLD Table 7 ID72V3001 Normal Mode Configuration Mode Select Frequency Select Comment mode sel 1 mode sel 0 Freq sel 1 Freq sel 0 0 0 1 0 North America 1 1 Europe If the PDK is operating in Master c
41. 0 1 0010 using CONN_D 15 process Signal r NORMAL PLD HOLDOVER PLD LOCK PLD signal cpld dec 2 signal cpld dec 8 signal cpld dec 3 begin if signal cpld dec 2 0 and signal r 1 then CONN D13 NORMAL PLD implementation of status read signal HOLDOVER PLD of WAN PLL at ADDRESS CONN AD 22 30 1XXXX1000 using CONN D 15 elsif signal cpld dec 8 0 and signal r 1 then CONN D13 HOLDOVER PLD implementation of status read signal LOCK PLD of WAN PLL at ADDRESS CONN AD 22 30 1XXXX0011 using CONN D 15 elsif signal cpld dec 3 0 and signal r 1 then CONN D13 LOCK PLD else CONN D13 Z end if end process implementation of one bit latch for signal PLD TCLRn of WAN PLL at ADDRESS CONN AD 22 30 1XXXX0100 using CONN D 15 default PLD TCLRn 1 process signal cpld dec 4 TDM RESET CONN D15 signal bar begin if TDM RESET 0 then PLD TCLRn 1 elsif signal cpld dec 4 0 and signal w bar 0 then PLD TCLRn lt CONN 15 end if end process implementation of one bit latch for signal PLD TIE en of WAN PLL at ADDRESS CONN AD 22 30 1XXXX0101 using CONN D 15 default PLD TIE en 1 process signal cpld dec 5 TDM RESET CONN 15 1 bar begin if TDM RESET 0 then PLD TIE en 1 elsif signal cpld dec 5 0 and signal w bar 0 then PLD TIE en CONN D15 end if end process impleme
42. 0x202 PLD SELO D 14 R W 1 Determine the input reference frequency of the PLD F SEL1 D 15 R W 1 0 204 NORMAL_PLD D 15 R Goes high when the WAN PLL goes into Normal mode 0 206 LOCK PLD D 15 R Goes high when the WAN PLL is locked to the input reference frequency 0x208 PLD TCLRn D 15 R W 1 Logic low at this signal resets the TIE control block of the WAN PLL resulting in a realignment of the output phase with the input phase 0 20 PLD_TIE_en D 15 R W 1 Logic high at this signal enables the TIE block of the WAN PLL Ox20C PLD DUSLIC TSI RST D 15 R W 1 Logic low at this signal resets the DuSLIC U1 n amp U2 and TSI switch 0 20 LOS D 15 RAN 1 Logic low at this signal lights an LED 0x210 HOLDOVER PLD D 15 R Goes to a logic high when the WAN PLL goes to Holdover mode 0x212 PLD WAN PLL RSTn D 15 R W 1 Logic low at this signal resets the WAN PLL 3 4 3 JTAG The J16 header is used for programming the CPLD The PSTN card comes programmed and use of this header should not be needed Note Do not reconfigure the Xilinx chip in the PSTN card Attempts to do so may lead to instability in the system Table 10 Xilinx JTAG Signals Pin JTAG Signal 1 5V 2 GND 3 NC 4 TCK Packet Telephony Development Kit PSTN Card Rev 1 Freescale Semiconductor 15 PSTN Card LEDs and Jumpers Table 10 Xilinx JTAG Signals Continued Pin JTAG Signal 5
43. 1 aun AepsnyL aed oz oog JequinN ezg AHOLSIH NOISIA3H enu SMHOMLZUN IVH V HSVH ou g 9 04 epou 504 165 ur 151 243 1037 11d NYM 9 4 2 15 ISI TId NVM OTwapend lt 002 90 90 141 OSOWIdS pue ISONWNIdS y o z 2002 8 UOTSTASY uorsaeA snorAead uotstasy 54104 TM a3exoeqdq Si pP 2 EE 8002721 19120 5 2 oz JequinN 9219 PID Sod enu SNHOMLSUN TANE 2 067786 44 CREPES ZHWPSE OT S uoeurgur
44. 3 gt pend spre ZIS X ZIS Luosurgur 3 HOLIMS 2115 a TICH 29 OIISnGg Cp NE Sid TVIUdS OI ISnq a 19949 SL 10 002 21 eunr Aepsinup 19120 oz lt oog gt 8 JequinN 9219 eur Jequosqns Boyeuy enu SMXHOMLUN IVH V fe 0 2 ae gt oo oo 39 22 gt 8r 5 59 521 0 91 re TWOA 2 401 44089 iaa SdL E T BLINDA Hyg 01091 SE b 2 b UT aul zan _ amh 2 m fo 931 1 tal 191 4017 44089 3055 3055 SE ero eae S T 921 0 di 307v SZLMO 3089 5 AS 801 30021 6 OviH 4 8 5 T zio gt 5 ONASH x t azo n 8 5 Nod
45. 3 675 2150 LDCForFreescaleSemiconductor hibbertgroup com Document Order No PTKITPSTNUG Rev 1 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body
46. 30001 Ls Wi ko kn 9 620 820 n KGB a 422 ASQGAV HIVSA L 2 SL 002 21 eunr Aepsinug 24 02 JequinN ezig eur jequosqng Dojeuy enu SNHOMLSNN v di 302 lt e b 4991 E m gt w XOVISP NNOO 5 90 o o oto a ON race ku B 821 44022 2 AO0Z doz 40022 90 540 306 921 599 290 SMO 540 30 Ove 2 zo sz zo dJa ib LLL s E 2 2 neraorauzp 81 on 5 dOL 3491 doa 92 404 HHA 18061 20401 090 1x39 92457
47. 66 1050 lt lt lt lt lt 051 S NETE 550 0050 88888 30 LOOSAZ81LAI 2 ovn 30 v 550 39 lt o o anyo 6en sory 32 044 780 3 2 5 St 19949 SL 10 6002 eyeq 02 a LWA HLVEA JequinN ezig pue qndo YOOTNI 5 SNHOMLSUN TANE Aoz ai diodi YOOTNI YOOTNI 6 Za oer ane XHLVaA HOIOHNNOO Asvd HHA H fo fo fo 2 A A A 4 A Edd x 1 1031 9331 6zdL Ord HOIOHNNOO Asvd 9 ASQGAG AS H H H H 5 v XOL 3058 3058 3058 M eir 02184 ZH 2 4 4 4 4 d Zr Aj ddngjeMod 9NOO 4 XH1V8A lt XHLVEA HOIOSNNOO
48. C Infineon Codec Infineon RJ11 SLIC Infineon piso RJ45 1 1 QUADFALC Infineon RJ45 T1 E1 RJ45 T1 E1 Li BE 8 KHz PLL 8 192 MHz PCM2 Switch 512 x 512 IDT POM1 PCMS PCMO WAN 16 384 MHz 4096 MHz IDT_CSA Figure 5 TSI Connections with Other PSTN Card Modules Serial Bus PCM2 Microprocessor Bus ee ee PCMO Microprocessor Bus TESS Sed Microprocessor Bus The TSI is part of the PDK memory map The MPC8260 device which resides in the PDK baseboard can access the TSI via chip select 9 Refer to Table 3 andTable 4 for TSI Base and Option Register settings as well as UPM programming MPC8260 memory controller programming to access the TSI Table 3 TSI Option and Base registers Registers Values TSI Base Register OxF8010C1 9 TSI Option Register OxFFFF8106 Packet Telephony Development Kit PSTN Card Rev 1 Freescale Semiconductor Table 4 Initializing the TSI PSTN Card Components Operations Instructions Single Read MCMR 0x10008800 Ox8FFFF000 80 OxOFFCF300 OxOFFCF300 OxOFFCF300 80 0x0FFCF004 Ox1FFFFO001 Single Write MCMR 0x10008818 0 OxOFF
49. CCO5 Run MBMR 0x00015400 3 3 PLL Synchronization Module The IDT 82V3001 PLL device generates timing clock and synchronization framing signals for the PCM bus The IDT82V3001A is a WAN PLL with single reference input It contains a Digital Phase Lock Loop DPLL which generates clock and framing signals that are phase locked to a 2 048 MHz 1 544 MHz or 8 kHz input reference The PLL circuitry generates all TDM synchronization clocks used in the PDK including the PCM interface clocks These clocks can either be generated locally via the QUADFALC device if the PDK is operating in Master mode or be derived from any one of the T1 E1 lines by the QUADFALC if the PDK is operating in Slave mode The two relevant modes of operation for the IDT82V3001 are Free Run mode and Normal mode 3 3 1 Free Run Mode In Free Run mode the PLL device uses its local clock as opposed to the reference frequency to synthesize the system clock The Free Run clocking mode for IDT 82V3001 is not used only the Normal clocking mode is used as described in the following section 3 3 2 Normal Mode When the PLL device is configured in Normal mode the frequency reference is received from the QUADFALC as illustrated in Figure 10 The timing reference fed into the PLL device is derived from one of the T1 E1 lines In this case the second line is used as the timing reference source However any of the four digital lines terminated on the PSTN card can be used as
50. Card Components T1 E1 22554 QUADFALC T1 E1 T1 E1 4 gt 1 1 RCLK1 F ref To WAN PLL Device lt gt 1 544 2 048 MHz MCLK 16 384 MHz XTAL Osc 20 ppm Figure 9 QUADFALC Slave Clocking Mode Configuration 3 2 2 QUADFALC Default Operating Mode The QUADFALC is part of the PDK memory map and the MPC8260 device which resides in the PDK baseboard can access the QUADFALC via chip select 8 Refer to Table 5 and Table 6 for QUADFALC Base and Option Register values as well as UPM programming Table 5 QUADFALC Option and Base Registers Registers Values BR8 QUADFALC Base Register OxF70008A1 OR8 QUADFALC Option Register OxFFFF8106 Table 6 QUADFALC UPM Programming Operations Instructions MBMR 0x10015400 Ox8FFFF000 OxOFFCF300 OxOFFCF300 OxOFFCF004 OxOFFFF300 OxOFFFF300 Ox3FFFFO001 Single Read Packet Telephony Development Kit PSTN Card Rev 1 Freescale Semiconductor 11 PSTN Card Components Table 6 QUADFALC UPM Programming Continued Operations Instructions MBMR 0x10015418 Ox0OFF3F000 0OxOFFOFS300 Ox0OFFOF300 IN MT 0OxOFFOFO004 0 0 Ox3FF3F001 Exception MBMR 0x1001543C MDR OxFFFF
51. Freescale Semiconductor User s Guide PTKITPSTNUG Rev 1 9 2005 Packet Telephony Development Kit PSTN Card The public switched telephone network PSTN card in the Packet Telephony Development Kit PDK connects directly to the PDK baseboard and provides four narrow band T1 E1 time division multiplexing TDM ports that interface to the PSTN network The PSTN subsystem also supports four analog telephony ports for direct interface to standard analog voice terminals It provides a TDM stream for the DSP array that is MSC810xPFC card Figure 1 shows a snapshot of the PSTN card hardware Freescale Semiconductor Inc 2005 All rights reserved CONTENTS 1 Packet Telephony Development Kit 3 2 Getting Started With the PSTN Card 4 3 PSTN Card Components sse 4 3 1 Time Slot Switch sss 5 3 2 Digital E1 T1 Interface sss 9 3 3 PLL Synchronization Module 12 3 4 Complex Programmable Logic Device 14 4 PSTN Card LEDs and Jumpers 16 5 Power Connector 17 6 PSTN Card Interface 2 17 7 Default TDM Interface Timing 21 2 freescale semiconductor CLPD JTAG Power Connector m 3 jo amp
52. L device and generates the Loss of Synchronization signal for the operation status indicator or LED 3 4 1 Chip Select Logic The CPLD uses address line 22 to select between assertion of the IDT time slot switch and accesses to its own internal registers as shown in Table 8 Table 8 Chip Select Truth Table Chip Select input Address Line Input 107 Time Slot Switch Internal CPLD Chip From the Baseboard From the Baseboard 1 X 1 1 0 0 0 1 1 1 0 Packet Telephony Development Kit PSTN Card Rev 1 Freescale Semiconductor PSTN Card Components 3 4 2 Output Signals Writes to the memory mapped registers control the output signals on the CPLD Table 9 lists and describes the registers The address column refers to the address from which to write over the bus A 22 31 The physical address pins to the CPLD are only 22 30 The data bus bit is latched on to the output signal Thus to turn off the LED for example one would write a value of 0x01 to address Ox20E The physical address lines CONN_AD 22 30 would be 100000111 and the 1 from D 15 would be latched causing the PLD LOS FALC signal to go high Table 9 CPLD Memory Map Data Bus Read Default Address Output Signal Name Bit Write Value Description 0x200 PLD_MODE_SELO D 14 R W 0 Determine the state Normal Holdover or PLD MODE SEL1 D 15 R W 0 Free Run of the WAN PLL
53. MHOMLZUN IVH V HSVH ou g 9 04 epou 504 165 ur 151 243 1037 11d NYM 9 4 2 15 ISI TId NVM OTwapend lt 002 90 90 141 OSOWIdS pue ISONWNIdS y o z 2002 8 UOTSTASY uorsaeA snorAead uotstasy 54104 TM a3exoeqdq Si pP 2 EE 8002721 19120 5 2 oz JequinN 9219 PID Sod enu SNHOMLSUN TANE 2 067786 44 CREPES ZHWPSE OT S uoeurgur 3 gt pend spre
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55. NC 6 TDO 7 TDI 8 9 NC TMS The only module that connects to the baseboard JTAG chain is the QUADFALC PIMC connector J15 enables the JTAG chain between the baseboard and the PSTN card 4 Note The baseboard JTAG chain must be configured to add the PSTN JTAG with the baseboard JTAG chain Refer to the baseboard user s manual for details on JTAG chain configuration PSTN Card LEDs and Jumpers This section describes the LEDs and jumpers of the PSTN card Table 11 PSTN Card LEDs LED Description 1 Indicates the Hook Status of the analog subscriber line 1 P1 B1 LED1 is controlled by the port 1018 of the PEB3265 It can be programmed to show the ON OFF hook status for the corresponding subscriber line 2 Indicates the Hook Status of the analog subscriber line 2 P1 B1 LED2 is controlled by the port IO1A of the PEB3265 It can be programmed to show the ON OFF hook status for the corresponding subscriber line 3 Indicates the Hook Status of the analog subscriber line 3 P1 D1 LED3 is controlled by the port IO1B of the PEB3265 It can be programmed to show the ON OFF hook status for the corresponding subscriber line 4 Indicates the Hook Status of the analog subscriber line 4 1 1 LED4 is controlled by the port IO1A of the PEB3265 It can be programmed to show the ON OFF hook status for the corresponding subscriber line Shows the Loss Of Signal Synchronization statu
56. OFS380 0x0FFOF300 OxOFFOFS300 MDR OxOFFOF380 OxOFFOF004 OxOFFOFS300 Ox3FF3F001 Exception MCMR 0x1000883C OxFFFFCCOS OxFFFFFFFF OxFFFFFFFF OxFFFFFFFF Run MCMR 0x00008800 3 1 1 Duslic Module The analog PSTN interface supports four loop start telephone subscriber ports The Infineon Dual Channel Subscriber Line Interface Concept Duslic PEB 3265 and PEB 4265 devices on the card form the interface between the TDM interface to the TSI and the physical twisted copper pair There are four RJ 11 physical connectors on the PSTN card as shown in Figure 6 Packet Telephony Development Kit PSTN Card Rev 1 Freescale Semiconductor PSTN Card Components Duslic Serial Bus SLIC Infineon Codec PCM2 Infineon 2 PCM3 RJ11 SLIC Infineon Switch Duslic 512 x 512 RJ11 SLIC Infineon Codec IDT Infineon RJ11 SLIC Microprocessor Bus Infineon 2 Figure 6 Duslic Connections to other Sub modules of the PSTN Card The Duslic requires that reset be applied when all the external clocks are stable The CPLD ensures that the Duslic reset signal is asserted only after the clocks generated by the PLL device are stable approximately 300 ns or lon
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58. S E m a z gt m 399157 NNOO 2 ausa 90 9 9 9 1 9 qi H9 ore n d zd 402 40022 9 002 402 30022 ou oTt 5770 340 30 SO tvo SMO 30 zed 2 zo arzo 8 iS 2 8 39 9H lt r ON ad 49027 Sg on 9 A001 901 3091 dod aapa 8 006 805 59 nod 8I g 19091 20401 HLVEA evo 1x30 dov 8L g 9n NOV 91 NOV 8 g SWOA 8 diL 5 0 302 299 ana 5 38 anaa auod 39001 dO 49001 A00Z 44001 sn ER 30 7 o AOS 901 30001 09 EE 7 1 0 T HWOOT g ASQGAV 4 ASQQAV i IM uem 5 0 1 302 053 PONTE 3 ce fo b A001 3091 m d gt w AOYLSH NNOO 2 _ 989 620 o 1 8 LEX YER 4 A002 022 9 002 402 59022 SMO 540 306 2 Ov veo 559 SMO 540 306 2 zo d 38 2 ON Vid et 901 49027 Sag on EU A001 901 3091 rax doa viaoa 8 HHA 006 805 zeo Nod g 18091 20401 HL JA 19 gr 1x30 widow 8 NOV VI NOV 5 lt SWOA 8 Idil 5 0 302 228 E lt gt lt r439 AECH ana 401 49001 002 44001 002 401
59. TDM2 0 and CONN AD22 1 then PLD CSn lt 1 Signal main dec 0 else Packet Telephony Development Kit PSTN Card Rev 1 22 Freescale Semiconductor Ol Default TDM Interface Timing PLD CSn lt 1 Signal main dec lt 71 end if end process end of two bit decoder Following process is to implement the CPLD address decoder which will be enabled by output signal signal main dec of two bit decoder Inputs for this decoder are AD 27 30 out put will be nine enable signals for internal latchs process signal main dec CONN begin if signal main dec 0 then case CONN AD is when 0000 gt signal cpld dec lt 111111111110 when 0001 gt signal cpld dec lt 111111111101 when 0010 gt signal cpld dec lt 111111111011 when 0011 gt signal cpld dec lt 111111110111 when 0100 gt signal cpld dec lt 111111101111 when 0101 gt signal cpld dec lt 111111011111 when 0110 gt signal cpld dec lt 111110111111 when 0111 gt signal cpld dec lt 111101111111 when 1000 gt signal cpld dec lt 111011111111 when 1001 gt signal cpld dec lt 110111111111 when 1010 gt signal cpld dec lt 101111111111 when 1011 gt signal cpld dec lt 011111111111 when others signal cpld dec 111111111111 end case else signal cpld dec 111111111111 end if end process
60. age of this user s guide Software Packet Telephony Development Kit Software User s Guide PTKITSOFTUG CAUTION The Packet Telephony Development Kit includes open construction printed circuit boards that contain static sensitive components These boards are subject to damage from electrostatic discharge ESD To prevent such damage you must use static safe work surfaces and grounding straps as defined ANSI EOS ESD S6 1 and ANSI EOS ESD 54 1 All handling of these boards must be in accordance with ANSI EAI 625 2 Getting Started With the PSTN Card This section presents unpacking instructions hardware preparation and installation instructions for bringing up the PSTN card First unpack the equipment from the shipping carton Refer to the packing list and verify that all items are present Save the packing material for storing and reshipping the equipment If the shipping carton is damaged upon receipt request the carrier s agent to be present during unpacking and inspection of equipment Most systems have a PSTN card already attached to the baseboard If you have purchased a PSTN card separately you must plug it in The PSTN card cannot operate as a stand alone unit The procedure for bringing up the PSTN is as follows Ensure that the PDK baseboard power supply is turned OFF Ensure that the stands off are connected to the PSTN card Gently connect the PSTN card PTMC connectors to the PDK baseboard Twist and tighten the PSTN card st
61. al oF NNOS 05 57 EE tv oe t44 807704 lt 15 910 NNO9 97 7 zy 7 0 Eid Ur 44 20d OL 60 NNOO 27 7 E 7 St NNOD UF 7 7 sg Teqv NNOD YE 7 t X PEE ec rr 4 1 1 NNOD 2 70 NNOD 9t et TE 05 52 90 NNOD t w b Ez NNOO 2 ze M Fan ety 820 NNOO SG NNOO 9 57 v 89 12 5 6 T errno 82 4 ve c 220 NNOO _ 22 TC z d AS e i 920 NNOO 02 sr d NNOO NNOO zz BT 10 Say NNOS 91 ST gt gt 13938 war 98 02 1 NNOO YF BT 4 YT ET 4 or TT Id NNOD AS 9r er TT gt OF 5 1 rd r vir 89 NNOO UT 0 1 er T T SWL OWLS 8 UT 8 ats _ he 8 1641 SvIrX amp z T 180 146 v EE L T AS vie AS uo EST ST TEY sir dmi eir uo 957 ST OW qr eR Ag Et 6 01 SleNeadAa K Td NVM Qd 91 3GOW SL 29 wes oles 4
62. ands off to baseboard Ensure that the PSTN card is properly placed on top of the PDK baseboard OU GO UNES If you plan to use the analog telephones connect the J17 power connector see Section 5 Power nector on page 17 7 Turnon the power supply 3 PSTN Card Components This section discusses the main components of the PSTN card which are the time slot switch the digital E1 T1 interface the PLL synchronization module and the complex programmable logic device Packet Telephony Development Kit PSTN Card Rev 1 4 Freescale Semiconductor PSTN Card Components 3 1 Time Slot Switch The TSI performs time slot switching to set up and tear down voice connections between communicating entities IDT 72V70800 is a 4 port switch that is dedicated to switch pulse code modulation PCM data between any two ports during call control It is a non blocking digital switch that has a capacity of 512 x 512 channels at a serial bit rate of 8 192 Mb s Figure 4 shows an overview of the TSI module Key features of the IDT 72V70800 TSI switch include e 64 kbit s PCM channel switching e Freely programmable streams and time slot control e Data rate of 8 192 Mb s equivalents to 128 PCM channels per port e Transmit to receive channel loop back for diagnostics Microprocessor control mode High impedance output control GND RESET
63. cking configuration and the WAN PLL device clocking configuration jointly determine the timing mode Two timing modes are supported master and slave clocking The combination of master or slave options provides maximum flexibility for telecommunications equipment developers using the PSTN card In master clocking mode the QUADFALC derives its timing from its local free running 16 384 MHz free running clock as shown in Figure 8 The derived clock is either 1 544 MHz for operation in North America or 2 048 MHz for E1 operation in Europe This derived clock becomes the timing reference for WAN PLL device which generates all the system clocks including the PCM clocks for the PDK T1 E1 22554 QUADFALC T1 E1 1 1 WAN PLL Device gt 1 544 2 048 MHz MCLK 16 384 MHz XTAL Osc 20 ppm Sync Source Figure 8 QUADFALC Master Clocking Mode Configuration In slave clocking mode QUADFALC derives its timing reference from one of the four T1 E1 line terminated directly on the QUADFALC device as illustrated inFigure 9 The 1 544 MHz or 2 048 MHz derived clock is fed into the WAN PLL device which generates the system PCM clocks Clocking for the QUADFALC is supplied through the MCLK pin for the PDK this clock has a frequency of 16 384 MHz Packet Telephony Development Kit PSTN Card Rev 1 10 Freescale Semiconductor PSTN
64. g for the PDK is The reset value for Duslic is A law can be programmed to by changing bit 7 of register BCR3 Hybrid 2 to 4 wire conversions H A special network balancing circuit performs this function to match the line impedance so echo generation can be avoided Hybrid balancing is a Duslic program mable option Testing Allows access to the loop so that regular diagnostic tests can be performed including loop resistance measurement line capacitance leakage current ringing voltage line feed current and trans versal and longitudinal current Packet Telephony Development Kit PSTN Card Rev 1 Freescale Semiconductor PSTN Card Components 3 1 2 Duslic Configuration and Operation The Duslic devices are configured directly by the baseboard host processor through the SPI interface Specific values are written to Duslic registers to configure for example a given line into a specific mode of operation Refer to the Duslic user s manual for detains on the functions of all registers supported During normal operation specific Duslic registers must be read to determine the signaling exchanged between the subscriber telephone set and the PDK Dynamic conditions that are constantly monitored by the host processor and appropriate action taken include ON hook OFF hook signaling and DTMF signaling The host processor can also command the Duslic through the SPI interface to generate ringing voltage or tones such a
65. ger after the PLL device undergoes reset The Duslic performs all the line interface functions generally known in the industry as the BORSCHT functions as follows 1 Battery feed B Represents the voltage and current required to power the telephone equipment con nected to the line Battery voltage of 48 to 24 volts is fed directly into the Duslic devices from the PDK power supply Over voltage protection O Protects the PDK from damage to accidental exposure to high voltage such as those resulting from lightning Ringing R The high voltage low frequency signal activated to ring the telephone equipment Two programmable ringing modes are supported balanced ringing where ringing voltage is applied differ entially between tip and ring and unbalance ringing in which the ringing voltage is applied single ended to either tip or ring The ringing voltage of 30 to 60 volts is fed directly into the Duslic devices from the PDK power supply Signaling or Supervision S Detects ON hook and OFF hook states for the telephone equipment con nected to the line ON OFF hook can be detected while a station is ringing which is referred to as Ring Trip Detection or it may can detected while the station is not ringing which is referred to as Switch Hook Detection Coding C Converts the analog signals into PCM and vice versa Two software configurable standard conversion algorithms are supported A law and The default codin
66. gic PLD TCLRn out std logic PLD TIE en out std logic PLD DuSLIC TSI RSTn out std logic PLD WAN PLL RSTn out std logic PLD LOS FALC out std logic PLD IDT CSn out std logic CT FRAME A out std logic PLD QFALC FRAME out std logic end pdk cpld architecture pdk cpld of pdk cpld is signal signal main dec std logic internal signal whic enables address decoder Signal signal cpld dec std logic vector 11 downto 0 internal signals which are out from address decoder Signal signal r w bar std logic signal signal w bar Std logic signal signal std logic signal sel muxl std logic vector 1 downto 0 select signals to select frame sync for Base card connectors Signal sel mux2 std logic vector 1 downto 0 select signals to select frame sync for QuadFALC optional begin two bit decoder which selects IDT switch or address decoder of CPLD process PQ2 CS TDM2 CONN AD22 begin the selection between IDT switch and cpld address decoder is done depending upon status of PQ2 CS TDM2 and CONN AD22 If PQ2 CS TDM2 is O the selection between IDT switch and CPLD address decoder is done based on CONN AD22 if CONN AD22 is 0 then IDT switch is selected or if CONN AD22 is 1 then CPLD address decoder is selected else if PQ2 CS TDM2 1 then both IDT switch and CPLD address decoder will be disabled if 2 CS TDM2 0 and CONN AD22 0 then PLD IDT CSn 0 signal main dec 1 elsif PQ2 CS
67. ications The PDK has an MPC8260 host network processor that runs Linus StarCore DSP resource cards that run DSP code and a Public Switched Telephone Network PSTN card with interfaces such as E1 T1 and analog telephone lines see Figure 3 Telephone Managed Network Packet Network icd PSTN StarCore DSP 5 ontro Ethernet Resource rocessor Daughtercard Baseboard Figure 3 Components of the Packet Telephony Development Kit PTK The documentation for the kit components is as listed in Table 1 Packet Telephony Development Kit PSTN Card Rev 1 Freescale Semiconductor Getting Started With the PSTN Table 1 PTK Components and Their Associated Documents Component Document Document ID Baseboard Packet Development Kit Baseboard Hardware User s Guide PTKITBASEUG MPC8260 Control MPC8260 PowerQUICC II Family Reference Manual MPC8260UM Processor Available at the website listed on the back page of this document PSTN Card Packet Development Kit PSTN Card User s Guide PTKITPSTNUG StarCore DSP MSC8102 Packet Telephony Farm Card 5 8102 User s Guide PTKIT8101UG Resource Daughtercard MSC8101 Packet Telephony Farm Card 5 8101 User s Guide PTKIT8102UG StarCore DSP Reference manuals and other documentation for the MSC81xx products are Resource located at the website listed on the back p
68. locking mode the frequency reference is generated locally by the QUADFALC and fed directly into the PLL device Software can configure the QUADFALC to source a free running clock from it local 16 384 MHz oscillator fed through the MCLK pin This clock has a stability of 20 ppm as illustrated in Figure 11 Packet Telephony Development Kit PSTN Card Rev 1 Freescale Semiconductor 13 PSTN Card Components SCLKR 1 1 1 4 1 1 XPA1 22554 T1 E1 QUADFALC T1 E1 gt 1 _________ ies Mb 1 544 2 048 MHz C8 8 PCM System F8 gt 8 KHz Bus MCLK IDT82V3001 16 384 MHz Sunc C4 4 096 MHZ XTAL Osc 20 C16 36 384 MHz Switch Figure 11 WAN PLL in support of Master Clocking Mode The default clocking option for the PDK is Master synchronization as illustrated in Figure 11 The default reference clock fed into the PLL device from the QUADFALC is 1 544 MHZ representing the North American digital transmission line standard 3 4 Complex Programmable Logic Device CLPD The glue logic to help control access and configuration of all devices on the PSTN card is implemented on a CPLD The CPLD decodes the addresses to generate the chip select for the TSI device and the control signals for the PLL device The CPLD also monitors the PL
69. ng Figure 13 diagrams the PSTN default TDM interface to the DSP daughter card The default is 128 channels per frame 8 bits per channel This yields 8 192 Mbps with an 8 K Hz frame synchronization signal 122 0 ns 8 192 2 C8 A Clock 125 us 122 8 2 FRAME A Frame 4 gt 4 10 8 ns CT Rx Data Bit 1 Bit 2 Bit 3 Bit 4 gt 22 8ns CT D1 Tx Data Bit 1 Bit 2 Bit 3 Bit 4 Figure 13 PSTN Card Default TDM Interface Packet Telephony Development Kit PSTN Card Rev 1 Freescale Semiconductor 21 Default TDM Interface Timing Appendix A CPLD Source library IEEE use IEEE STD LOGIC 1164 ALL use IEEE STD LOGIC ARITH ALL use IEEE STD LOGIC UNSIGNED ALL declaration of INPUT and OUTPUT ports entity pdk_cpld is Port PO2 CS TDM2 in std logic CONN AD22 in std logic CONN AD in std logic vector 27 to 30 CONN D13 out std logic CONN D14 in std logic CONN D15 in std logic std_logic GPL2 std_logic HOLDOVER PLD in std logic LOCK PLD in std logic NORMAL PLD in std logic CT C8 A in std logic TDM RESET in std logic CT FRAME in std logic CT STFRAMEn in std logic CT WFRAMEn in std logic PLD MODE SELO out std logic PLD MODE SEL1 out std logic PLD F SELO out std logic PLD SEL1 out std lo
70. ntation of one bit latch for signal PLD DuSLIC TSI RSTn for DuSLIC and TSI reset at ADDRESS CONN AD 22 30 1XXXX0110 using CONN D 15 default PLD DuSLIC TSI RSTn 1 process signal cpld dec 6 TDM RESET CONN 15 1 bar begin if TDM RESET 0 then PLD DuSLIC TSI RSTn 1 Packet Telephony Development Kit PSTN Card Rev 1 24 Freescale Semiconductor Default TDM Interface Timing elsif signal cpld dec 6 0 and signal bar O then PLD DuSLIC RSTn lt CONN 15 end if end process implementation of one bit latch for signal PLD LOS FALC for FALC at ADDRESS CONN AD 22 30 1XXXX0111 using CONN D 15 default PLD LOS FALC 1 process signal cpld dec 7 TDM RESET CONN 15 1 bar begin if TDM RESET 0 then PLD LOS FALC lt 1 elsif signal cpld dec 7 0 and signal w bar 0 then PLD LOS FALC CONN D15 end if end process implementation of one bit latch for signal PLD WAN PLL RSTn for WAN PLL reset at ADDRESS CONN AD 22 30 1XXXX1001 using CONN D 15 default PLD WAN PLL RSTn 1 process signal cpld dec 9 TDM RESET CONN D15 signal bar begin if TDM RESET 0 then PLD WAN PLL RSTn 1 elsif signal cpld dec 9 0 and signal bar O then PLD PLL RSTn lt CONN D15 end if end process Following process is to implement the two bit internal latch for select signals of MUX1 u
71. o WI 19250 v 589 80 189 080 60 8 0 9 0 EH auod auod 2 SSA miog SSA 27 2 SSA TOT SSA rs 2 SS anyo anyo anyo anyo anyo anyo anyo SSA SSA 8 0 0 210 042 690 Ur vUSSA o SUSSA LSet ZUSSA LASSA yndjno YXSS 8 E XSS ZXSSA gaegang T4 XSS 34014711950 32012 S ES v8EIN9L 408 280 ALIA az n _ 30 30 0 H 11 lt ey ON OGL err wat err ON SNL SWL quvogasva MOL HT MOL L OYL 3 105 OS g Lido SVEL ZHOIO3NNOO duvodasva XION RS WAL Si gr z90198NN05 quvosssva OW or sta Mad Se gor 719 Lye HINI ZOJ OL Wal t COT eld 29 T 9241 HOLOHNNOO quvoddsvH OL so LWGL SO 20d HOIOSNNOO GquvogdsVH uu 39 gt 13538 Wal GLSL HOLIOSNNOO 5 Wows OOF 56
72. or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc StarCore is a trademark of StarCore LLC All other product or service names are the property of their respective owners Freescale Semiconductor Inc 2005 2 freescale semiconductor
73. rd Rev 1 Freescale Semiconductor 25 MEET ae IK A E Default TDM Interface Timing begin if TDM RESET 0 then sel mux2 0 0 sel mux2 1 1 elsif signal cpld dec 11 0 and signal bar 0 then sel mux2 0 lt D15 sel mux2 1 lt CONN 14 end if end process 4 to 1 multiplexer design with case construct to select frame sync to QuadFALC optional process sel mux2 CT FRAME CT STFRAMEn CT WFRAMEn begin case sel mux2 is when 00 gt PLD QFALC FRAME lt CT WFRAMEn when 01 gt PLD QFALC FRAME lt CT STFRAMEn when 10 gt PLD QFALC FRAME CT FRAME when others NULL end case end process internal read write signal generation from TDM GPL1 and TDM GPL2 process GPL2 TDM GPL1 begin if GPL2 0 and TDM GPL1 0 then bar lt 0 Signal bar lt 0 signal r lt 10 elsif GPL2 0 and GPL1 1 then signal r w bar 1 signal bar lt 1 signal r lt 11 else Signal w bar lt 56 signal lt 707 end if end process end pdk cpld end of code Packet Telephony Development Kit PSTN Card Rev 1 26 Freescale Semiconductor eee Default TDM Interface Timing Appendix B Schematics The following pages present the schematics for the PSTN card as well as the board tha
74. s dial tone busy tone and reorder or fast busy tone 3 2 Digital E1 T1 Interface The digital E1 T1 interface supports four E1 T1 ports that can connect to central office CO lines such as ISDN PRI or PBX trunks The Infineon QUADFALC FEB 22554 device forms the interface between the TDM interface to the TSI and the physical twisted copper pair The QUADFALC recovers the PCM signal on the copper pairs and multiplexes them on the TDM bus to the TSI switch There are four RJ 45 physical connectors on the PSTN card see Figure 7 Each of the four digital interfaces of the QUADFALC includes a framer and a Line Interface Unit LIU a PLL circuit for clock recovery an HDLC controller for signaling and an 8 bit microprocessor interface for configuration PCM2 PCM2 PCM3 Switch Microprocessor Bus Se 512 x 512 RJ45 T1 E1 PCMO ae Ul QUADFALC PCMO Infineon Microprocessor Bus RJ45 T1 E1 5 LI RJ45 T1 E1 Li xi O 8 KHz CPLD Xilinx Microprocessor Bus WAN 16 384 MHz PLL 8 192 MHz 4 096 MHz Figure 7 QUADFALC Connecting to Other Sub modules of the PSTN Card Packet Telephony Development Kit PSTN Card Rev 1 Freescale Semiconductor 9 PSTN Card Components 3 2 1 QUADFALC Clocking Options The QUADFALC clo
75. s of the QUADFALC device It connects to a GPIO pin no 23 of the 5 CPLD It is illuminated when the processor determines the Loss of Signal status after reading the Frame Receive Status Register 0 FRSO of the QUADFALC 6 3 3V power indication on PSTN It is illuminated when 3 3V power rail is active 7 5V power indication on PSTN card It is illuminated to indicate that the 3 3V voltage is available on the board 8 VHR Ringing Voltage power indication on PSTN card It is illuminated to indicate ringing voltage is available 9 VBATHX Battery Voltage power indication on PSTN It is illuminated to indicate that the battery or line voltage is available on the board 16 Note For the jumper settings ON means place jumper and OFF means no jumper Packet Telephony Development Kit PSTN Card Rev 1 Freescale Semiconductor Power Connector Table 12 summarizes all jumper settings in the PSTN card Jumper settings are verified before they are shipped to customers Table 12 Jumper Settings Jumper Meaning Default Setting Switches between T1 and E1 termination T1 Pins 2 3 connected J1 J11 Shunt pins 1 2 E1 Shunt pins 2 3 T1 Selects source of 3 3V power supply Baseboard power Pins 2 3 connected J18 Shunt pins 1 2 Power comes from power connector J17 Shunt pins 2 3 Power comes from the baseboard Selects source of 5V power supply Baseboard power Pins 2 3 connected J19 Shunt pins 1 2
76. sed to to select frame sync for base card connectors Default mode is 1 1 0 lt 0 and sel muxl 1 lt 1 i e CT FRAME CT FRAME A F80 from WAN PLL MUX1 enable signals can be changed by writing into latch at address CONN AD 22 30 1XXXX1010 using CONN D 14 15 process signal cpld dec 10 CONN D15 CONN D14 signal bar TDM RESET begin if TDM RESET 0 then sel mux1 0 lt 0 sel muxl 1 1 elsif signal cpld dec 10 0 and signal w bar 0 then Sel mux1 0 lt CONN 15 sel muxl 1 CONN D14 end if end process 4 to 1 multiplexer design with case construct to select frame sync to base card connectors process sel muxi CT FRAME CT STFRAMEn CT WFRAMEn begin case sel is when 00 gt CT FRAME A lt WFRAMEn when 01 gt CT FRAME A lt CT STFRAMEn when 10 gt CT FRAME A lt CT FRAME when others NULL end case end process Following process is to implement the two bit internal latch for select signals of MUX2 used to to select frame sync for the QuadFALC optional Default mode is sel mux2 0 0 and sel mux2 1 1 i e PLD QFALC FRAME CT FRAME A F80 from WAN PLL MUX2 enable signals can be changed by writing into latch at address CONN AD 22 30 1XXXX1011 using CONN D 14 15 process signal cpld dec 11 CONN D15 CONN D14 signal bar TDM RESET Packet Telephony Development Kit PSTN Ca
77. t provides power to the PSTN card Packet Telephony Development Kit PSTN Card Rev 1 Freescale Semiconductor 27 2 Y 5 19905 7002 01 Aemugej Repson seq VO Jamo piy 002 1 5 Sesion 25 amd 5104 385 IM 3exoed qzews 943 jo NLSd esodand S d 00739 sava 3903 L T NIAS 5 NO HMd sn 8 AE E 0 99962 2 LNANI NIASF N 7 t ii 1 NIAS 02 oF Aver NIAS or 6 ol 8 8T 8 ZL Z zr 9r 5 ZS A 5 44O UO OL 0I 6 SUId amd H 8 9 zi 7 sut b bo b h bo UN bo 8 ER Neer TT 1 NE Er pte NLSd OL 4 524901014 524901014 524901014 524901014 Tre 8 8688 85 sn zn en 5 19909 8002721 aun AepsnyL aed oz oog JequinN ezg AHOLSIH NOISIA3H enu S
78. v 550 39 lt o o anyo 6en sory 32 044 780 3 2 5 St 19949 SL 10 6002 eyeq 02 a LWA HLVEA JequinN ezig pue qndo YOOTNI 5 SNHOMLSUN TANE Aoz ai diodi YOOTNI YOOTNI 6 Za oer ane XHLVaA HOIOHNNOO Asvd HHA H fo fo fo 2 A A A 4 A Edd x 1 1031 9331 6zdL Ord HOIOHNNOO Asvd 9 ASQGAG AS H H H H 5 v XOL 3058 3058 3058 M eir 02184 ZH 2 4 4 4 4 d Zr Aj ddngjeMod 9NOO 4 XH1V8A lt XHLVEA HOIOSNNOO
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