SmartModel Products Application Notes Manual
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1. Figure 8 Non design Verification Pin Example For example if you wanted to detect when conditions were ready for a cache write your C testbench 1 could contain code similar to the following if IO 0 1 amp amp IO 1 0 IO 2 0 sync8 set pin Inst 1 SYNC8 IO3 PIN 1 b1 amp status flex fprintf stdout Condition set for cache write b STATUS sd n pin rslt amp status 38 Synopsys Inc August 2001 SmartModel Application Notes Chapter 2 Interfacing with Non FlexModels Then your C testbench 2 could use a while loop that looks for the detected condition and reads the cache with code similar to the following cache write done false while cache write done sync8 pin req Inst 1 SYNC8 IO3 PIN FLEX WAIT F amp status Sync8 pin rslt Inst 1 SYNC8 IO3 PIN pin rslt amp status if pin rslt 1 read_cache cache_write_done false flex_wait 1 amp status Wait for One Clock Cycle You can control the direction of the I O bus or pins using the sync8_output_enable command For example if you have a while loop looking for a trigger condition in your C testbench you can enable a pin on the sync8 fx model for output and set the pin value when your trigger condition is met using code similar to the following found pattern false while found pattern sync8 pin req Inst 1 SYNC8_IO1_PIN FLEX WAIT F amp status s2. LSC SwiftModel ModelCommand U3 ReportStatus LSC SwiftSession SessionCommand trace off The typical access to the command channel through the LMC COMMAND environment variable is available Fault Simulation SystemC SWIFT does not support fault simulation Save and Restore SystemC does not support Save Restore Checkpoint Restart Reset and Reconfigure SystemC does not support reset or reconfigure Model Status Report The model status report is available through the model command channel and also through the 1sc SwiftModel static member function Report It takes the model s InstanceName as an argument as shown in the following report status example LSC SwiftModel Report U2 Dumping Memory Contents The SystemC SWIFT integration provides access to the memory dump capability through the DumpMemory static member function LSC Swi ft Model and through the model command channel The following are dump memory examples LSC_SwiftModel DumpMemory U1 dump2 LSC SwiftModel ModelCommand U1 DumpMemory dump1 August 2001 Synopsys Inc 43 Chapter 3 SystemC SmartModel Library SmartModel Products Application Notes Manual Model Logging The standard model logging support works in SystemC SWIFT Most models use the standard SWIFT model logging triggered from the presence of a mlog cfg file in the working directory or by using the Set LogFile and TraceEvents model commands
3. Note that the model configuration attributes that are supported in the SystemC framework are provided as parameters to the model class constructor The following lists pertinent information for the supported model configuration attributes e All models must have the InstanceName attribute e The timing attributes TimingVersion and DelayRange are not available since they are not supported in SystemC e All file attributes are available for non FlexModels e FlexModels automatically set the command stream ID attributes based on the model instance name Timing SystemC is a cycle simulator Therefore timing in the event simulation sense is not supported FlexModels run in no timing mode in SystemC Other SWIFT models use a settling out technique to permit them to function adequately in the SystemC cycle environment Timing Check Control Timing checks are not applicable for the SystemC environment and are disabled 42 Synopsys Inc August 2001 SmartModel Products Application Notes Manual Chapter 3 SystemC SmartModel Library Command Channel SmartModel Library users send session commands by calling the SessionCommand static member function in the LSC_SwiftSession class Model commands are available through the 1sc SwiftModel static member function ModelCommand It takes the model s InstanceName and the command string as arguments as shown in the following example LSC SwiftSession SessionCommand trace on
4. Advanced users may wish to use the model command channel to control the mlog file as well The following are model logging command examples LSC SwiftModel ModelCommand U1 SetLogFile mlog 1log LSC SwiftModel ModelCommand U1 TraceEvents On Tracing Tracing works through the usual settings of the LMC COMMAND environment variable and the session command channel as shown in the following example LSC SwiftSession SessionCommand trace on SmartModel Windows SmartModel Windows are not supported at this time Wrapper Generation The wrapper generator scsg resides in LMC HOME bin To generate a SystemC wrapper for any installed models enter the model names as arguments to scsg separated by white space as in the following example Scsg cake fz usbhost fz scsg writes the wrapper files into the working directory To generate wrappers for all installed models use the a or a11 options as shown in the following example Scsg all The following sections describe the generated wrappers for the cake z model 44 Synopsys Inc August 2001 SmartModel Products Application Notes Manual Model Header File The model header file is just like the standard for SystemC models except that the model constructor is in a separate file A notable part of the model header file is the representation of logic values Note that for high performance SystemC documentation strongly encourages the use of inte
5. CakeCmd cntclk 5 wai wai t0 tt CakeCmd cntclk RegReq true s Sc lv 16 CntClk CakeCmd cn tatus tclk RegRslt status The following is an example of a complete thread process performing pin commands Cake Pin Command example SC MODULE CAKEPins 52 Synopsys Inc August 2001 SmartModel Products Application Notes Manual Chapter 3 SystemC SmartModel Library sc in bool gt CLK sc_inout lt sc_lv lt 32 gt gt CmdAD sc_out lt sc_logic gt CmdHOLD void eval SC_CTOR CAKEPins SC_THREAD eval sensitive CLK CAKEPins void CAKEPins eval int status cake_fz_cmd CakeCmd CakeCmd ModelInstanceName for int i 0 i lt 12 i wait CakeCmd cmdAD SetPin XOXOXOX0X0X0X0X0X0X0X0XO0XOXOXO0X0 while true CakeCmd cmdAD PinReq false status CakeCmd cmdHOLD PinReq true status CmdAD CakeCmd cmdAD PinRslt status sc logic HOLDValue CakeCmd cmdHOLD PinRslt status CmdHOLD HOLDValue Make Files The Makefile must be arranged to compile and link the models and link the associated runtime support files You would add the model cpp files to the SRCS variable add the SWIFTINC variable to INCDIR and define EXTRA LIBS as shown in the Makefile example EXTRA LIBS arranges for Libscswift a to be available in case SWIFT models are used in the design It also adds the 1d1 library so 1ibswift will be loaded dynamically
6. 1 on cell port U879 clkio buf OUT net 0 0 ns X 1 on model port FCLOCK v gt Show Trace Close P ao O O ww Report completed K Note Currently the VSB Causal Trace window is only available on the Intel NT platform 30 Synopsys Inc August 2001 SmartModel Application Notes Chapter 1 Verifying FPGA Designs For more information on causal tracing refer to Using Traces from a Simulation Run in Causal Trace in the NT version of the Visual SmartBrowser User s Manual Targeting Unsupported Devices You may come across an FPGA device package type that Synopsys does not support This does not mean that you cannot simulate that device If there is a Synopsys device model in the same FPGA family that has the same number of pins or more you can still simulate the device For example you might have a package type called sqt 208 whereas you might find a model for only the sqt 240 device The 208 240 nomenclature specifies the number of device pins You can use the model for the 240 pin device to simulate the 208 pin device To learn how to use unsupported device types in your design refer to Using Unsupported Devices in the SmartModel Library User s Manual Interactive SmartBrowser Commands This application note provides lots of information about how you can use the Visual SmartBrowser VSB to debug your FPGA design There is also an interactive tool called SmartBrowser that enables you to debug an interna
7. August 2001 Synopsys Inc 27 Chapter 1 Verifying FPGA Designs SmartModel Application Notes The command set cause full enables a full causal report The full switch generates a report that lists all the nets and cells in that path The nofull switch generates a report that lists only the start and end points The start_time and end time specify the window in which the causal tracing on the selected net is turned on Typically you would only want to turn on causal tracing around a particular problem that you are seeing such as a glitch or an X on a pin You can also turn on the causal tracing feature around all timing violations To do this add the following line to your MCF file set cause constraint Causal Trace Report Example The following causal trace report is triggered on a user specified event and then traces that event back through time to the parent event In this case the parent event occurred on the CLOCK EN port As you can see causal tracing has tracked the output event all the way back to the causal event on an input pin You can see the X traveling through the design to the output SmartModel TRACE Instance TESTBENCH DUT SMART SmartCircuit at time 586 3 NS Beginning cause report from DBUS lt 6 gt 586 3 ns 1 gt X on model port DBUS lt 6 gt 586 3 ns 1 gt X on cell port CELL4 0 net DBUS lt 6 gt 586 3 ns 1 gt X
8. Introduction Custom logic implemented in an FPGA is often the most critical part of a system and must be extensively tested As many designers have discovered however there is a difference between testing the functionality of a stand alone device and testing a device installed in a system While a designer can add flexibility and speed to the early stages of design using text based high level design methods and synthesis the device can later appear as a black box to an engineer Additionally designs are now typically too large and complex to rely on manual debugging methods This dilemma results in the need for a different approach to verifying and debugging FPGA designs This application note explains how to use the debug features associated with SmartModel FPGA models known as SmartCircuit models to verify designs that contain FPGA devices What Are SmartCircuit Models SmartCircuit models are essentially templates of unconfigured devices These models provide designers with advanced verification and debugging features that enable them to verify in the shortest timeframe a design incorporating a complex FPGA device The models are programmed by a design netlist in a standard format produced by vendor place and route tools SmartCircuit FPGAs increase productivity by enabling designers to focus on the design and system verification tasks rather than on simulation details For general information on SmartCircuit models refer to
9. SUN SC5 0 compiler 48 Support Center 9 SWIFT integration 41 SWIFT models 51 53 sync8 fx as non design verification pin 37 as user pin 37 model interface 35 synchronizing non FlexModels 34 Synchronizing with non FlexModels 34 Synopsys website 9 SystemC 41 class library 41 design 51 distribution 53 module 49 scheduling 49 SystemC SWIFT 43 System on Chip SoC 41 T testbenches 42 49 Timing 42 timing check control 42 typographical and symbol conventions 8 U unsupported devices simulating 31 User pin sync8 fx as 37 V Solaris 48 Verilog command 46 SOLV IT 9 Visual SmartBrowser VSB 15 SourceModels Visual SmartBrowser interactive symchronizing with FlexModels 36 commands 31 VSB August 2001 Synopsys Inc 57 Index SmartModel Application Notes Causal Trace window 30 causal tracing example 28 causal tracing report 28 Connection View 18 effect trace report example 30 effect tracing example 29 enabling causal tracing 27 event tracing 22 Examine View 18 global select tool 18 Hierarchy View 18 monitor feature 25 timing form timing form for VSB 22 using Visual SmartBrowser 15 W Windows 15 windows including in model command file 25 wrapper generation 44 51 58 Synopsys Inc August 2001
10. For the NT version only If you exit VSB but then want to view the last window you used you can restart the VSB using the r og file argument in the vsb command VSB Tools There are several tools within the VSB environment some of which are discussed in this application note e Main Window e Hierarchy View e Connection View e Examine View e Timing Form e Windows August 2001 Synopsys Inc 17 Chapter 1 Verifying FPGA Designs SmartModel Application Notes Main Window When the VSB invokes it displays the Main window The Main window is the starting point for debugging your design giving you access to specialized views that contain different types of information Hierarchy View Windows amp Monitors Examine View Selection stance TOP Type i TOP Tape eee Global Select Connection View Net Tags Causal Trace From the Main Window you can e Examine the post routed netlist at a number of different levels e Look at the design hierarchy using the Hierarchy View e Create an on demand schematic of the design using the Connection View e Examine the timing of any cell using the Examine View e Search through the netlist for a particular cell net or port instance using the Global Select tool e View a causal path using the Causal Trace Tool causal tracing is discussed in Event Tracing on page 26 e Create a windows declaration file windows are discussed in Windows on pa
11. I HER 0 EFIE Rd RE ERR 26 Causal and Ev nt Tracing kn een 4 desea ode dada 27 PlexModel Command Core sccas caskcasichhh sa 4 RA na Es 34 syncs Ix Model IAI aas sch dg er PIC FERRARI PRA RES 25 PCI SourceModel Coordinated with FlexModel 36 Non design Verification Pia Example 2 4 cecaccsaysccadvaasicaeica 38 Testbench CONDEDUVIDE uud d Eee gn Ke d d d ERR ERE ET ese sees 49 Installing SystemC SmartModel Support 00 50 Synopsys Inc 5 Figures SmartModel Application Notes 6 Synopsys Inc August 2001 SmartModel Application Notes Preface Preface About This Manual This manual contains application notes for the SmartModel Library of simulation models and other compatible products Topics include different ways to use multiple Synopsys products or tools in combination to solve verification problems Related Documents For general information about SmartModel Library documentation or to navigate to a different online document refer to the Guide to SmartModel Documentation For the latest information on supported platforms and simulators refer to SmartModel Library Supported Simulators and Platforms For detailed information about specific models in the SmartModel Library use the Browser tool SLMC HOME bin sl browser to access the online model datasheets Manual Overview This manual contains the following chapters Preface Describes the manual and lists the typographical convention
12. Inc 19 Chapter 1 Verifying FPGA Designs SmartModel Application Notes Connection View As FPGA designs have grown larger it has become possible to create designs of 250K gates and more Trying to debug a 100 250K gate schematic is nearly impossible The VSB Connection View helps by enabling you to view your design schematic in an on demand fashion Connection View Ti Connection View CLOCK_IR Zoom Actions View Window Help Buttons Ja Detail d TDO DPISS vo CLOCK IR I va Bi OUTBUF u Hide Find H Cells Hier Hide Sel k 4 View Design Schematic on Demand VSB enables you to navigate around a schematic by clicking on a cell port which causes VSB to generate the associated net You can then track backward or forward moving through the design from one cell port to another If you unintentionally expand a route you can simply select the net and hide it using the Hide Selected button You can also create hardcopy of the section of schematic displayed in a Connection View 20 Synopsys Inc August 2001 SmartModel Application Notes Chapter 1 Verifying FPGA Designs When tracking back into a design you can use an Event Tracing algorithm called causal tracing which expands to only the net or cell that directly affects the value on the original cell When expanding forward in the design schematic you can fan out to all connected nets and cells These features enable you to quic
13. LMC_HOME would typically come from the corresponding shell environment variable Makefile defs is from the examples directory in the SystemC distribution TARGET ARCH linux MODULE cake tb SRCS cake tb cpp cake fz cpp cake fz cmd cpp OBJS S SRCS cpp o include Makefile defs SWIFTINC IS LMC HOME sim systemc src NCDIR S SWIFTINC August 2001 Synopsys Inc 53 Chapter 3 SystemC SmartModel Library SmartModel Products Application Notes Manual EXTRA LIBS L S LMC HOME lib x86 linux lib 1scswift 1dl Simulation With the above in place you can proceed as described in the SystemC documentation and release notes For more information on SystemC you can obtain documentation from http www systemc org 54 Synopsys Inc August 2001 SmartModel Application Notes A attributes 42 command stream ID 42 configuration 42 cycle simulator framework 45 DelayRange 42 files 42 InstanceName 42 model configuration 42 Timing Version 42 C C class library 41 keywords 45 cake model command declarations 47 cake pin declarations 47 cake register declarations 47 cake_fz_cmd class 46 Causal Trace VSB window 30 causal tracing enabling 27 MCF example 28 report example 28 CFlex model 49 class command 46 51 constructor 42 46 template 47 class library C 41 command channel 43 command channel session 44 Command Co
14. SmartCircuit FPGA Models in the SmartModel Library User s Manual You can navigate to other SmartModel manuals from the Guide to SmartModel Documentation August 2001 Synopsys Inc 11 Chapter 1 Verifying FPGA Designs SmartModel Application Notes SmartCircuit Design Flow Figure 1 provides a conceptual overview of the FPGA design flow using SmartCircuit models in system verification Design Entry Synthesize Design Place and route using vendor tools Create post routed netlist System verification using SmartModel Library FPGA configured using netlist Program device Figure 1 SmartCircuit FPGA Design Flow 12 Synopsys Inc August 2001 SmartModel Application Notes Chapter 1 Verifying FPGA Designs SmartCircuit Models Some Basics Before you can start simulating with a SmartCircuit model you need to configure it using a netlist generated from your vendor s tools Refer to the individual model datasheet for an explanation of how to generate the netlist in the correct format The model extracts all of the design s function and timing information from this netlist You can access datasheets for all Synopsys models through this link http www synopsys com products Im modelDir html Each SmartCircuit model has a property called SCFFILE associated with it Depending on which simul
15. more information on MCF files as they relate to SmartCircuit models refer to Using SmartCircuit Models in the SmartModel Library User s Manual Debugging Tools SmartCircuit models operate with a set of advanced debugging tools that enable you to efficiently and quickly identify the root cause of a problem You can use the following debugging tools on your design e Visual SmartBrowser VSB e Windows e Event Tracing August 2001 Synopsys Inc 15 Chapter 1 Verifying FPGA Designs SmartModel Application Notes Visual SmartBrowser VSB With today s very large and complex FPGA designs designers typically are interested in only a small section of a netlist A good starting point for debugging any project is with the design schematic The Visual SmartBrowser VSB tool enables you to visually display an FPGA netlist ccn file using an on demand viewing technique which enables you to concentrate on only the portions of the design in which you are interested VSB comes with a self paced tutorial that introduces you to all of the VSB features Since this discussion cannot address hands on learning you might want to refer to Learning Visual SmartBrowser in the UNIX version or NT version of the Visual SmartBrowser User s Manual You can also access the tutorial document from the VSB help pull down menu Using the VSB To start the VSB on your FPGA design execute one of the following commands as appropriate for your pla
16. on cell port CELL4 T net DBUS_ENABLE lt 0 gt 569 4 ns 1 gt X on cell port CELL40 O net DBUS_ENABLE lt 0 gt 564 9 ns 0 gt X on cell port CELL44 0 net ENABLEBUS SIG 562 6 ns 1 gt X on cell port CELL43 0 net U2 N735 560 6 ns 0 gt X on cell port CELL42 0 net YSIG2 558 1 ns 0 gt X on cell port U2 MODE 1 Q net U2 MODE lt 1 gt 555 3 ns 0 gt X on cell port U2 MODE lt 1 gt C net CLOCK EN 553 9 ns 0 gt X on cell port BUFGS TL O net CLOCK EN 550 0 ns 0 gt Z on model port CLOCK EN Report completed MCF Example for Causal Tracing Around Timing Violations Suppose you want to turn on causal tracing around timing violations in a design called ducks alpha ccn You would place the following in your MCF file load source d projects flying ducks mcf files ducks alpha ccn set cause constraint The set cause command defaults to noconstraint so you must specify constraint as the set cause argument in order to constrain causal tracing around timing violations 28 Synopsys Inc August 2001 SmartModel Application Notes Chapter 1 Verifying FPGA Designs Causal Trace Timing Constraint Violation Example In the following example you can see a causal trace that was triggered by a timing constraint violation where a pulse on the RESET port was too small SmartModel ERROR Violated pulsewidth time 12 1 ns constraint PW CLR on CLR for cell U2 MODE 1 at Actual pulsewidth time 3 0ns specified minimum
17. tightly However you may find that by reducing the delay on that path you cause hold violations In that case you can go back to the original ccn file and try something else to fix the problem As you can see using SmartCircuit debugging processes to modify a ccn file in much quicker than a repetitive iterative process of going back to the source re synthesizing and re doing the place and route 22 Synopsys Inc August 2001 SmartModel Application Notes Chapter 1 Verifying FPGA Designs For more information on the timing form in the Examine View refer to Examine View in the UNIX version or NT version of the Visual SmartBrowser User s Manual Windows Visibility into the FPGA design during simulation is another critical success factor The ability to trace the contents of an internal net or register helps you debug your overall design SmartCircuit models also have the ability to look inside the FPGA design using a windows feature which means that the FPGA is no longer a black box within the simulation as illustrated in Figure 2 In lt 1 gt XC D1 XC Q Figure 2 Waveform Viewing Through Windows Windows enable you to use the simulation waveform window to trace all nets ports or states that are internal to the FPGA design This gives you full visibility into the FPGA design at a level that you can easily understand Having this visib
18. 1 Verifying FPGA Designs Finally when you have all the windows that you want in a simulation you can save a new or partial MCF for use in a later simulation Here is an example that shows how to specify windows in an MCF file bus SEGS7 u2 segs1333 lt 7 gt window SEGS7 bus SEGS2 u2 segs1332 2 window SEGS2 The bus command aliases the internal signal in this example the internal net u2 segs1333 lt 7 gt is aliased to SEGS7 The window command makes the signal available in the simulator You can include this new file into your main MCF by using a do command as shown in the following example load source d projects flying ducks mcf files ducks alpha ccn do d projects flying ducks mcf files windows do The windows file tells the SmartCircuit model which extra signals should be available within the simulation To access a designated window from a simulator you should use the trace and assign commands appropriate for that simulator For the exact command to access windows refer to your simulator documentation The VSB tool also has a monitor feature that enables you to create a text printout of the values on the nets ports or states in the selected portions of the FPGA design that are within the simulator transcript window For example to enable the monitors feature for the OE and DBUS signals you would add the following line to your MCF file monitor OE DBUS You can put monitor commands into an MCF do fi
19. Application Notes L Linux x86 48 load command switches 14 M MCF commands 15 MCF do file 25 MCF See also model command file memory contents 43 MemPro models 42 Microsoft Windows NT 48 model cake fz h 45 cake fz cmd h 46 CFlex 49 class constructor 42 command channel 43 command class 46 command declarations 47 commands 43 SetLogFile 44 TraceEvents 44 configuration attributes 42 constructor 45 46 Flex 42 46 header file 51 instance 46 instance name 42 45 46 51 logging 44 MemPro 42 non Flex 42 pin 46 ports 45 49 status report 43 model command channel 43 model command file MCF for SmartCircuit model 13 model command header file 46 model directory 9 model status report 43 monitor feature for VSB 25 August 2001 SmartModel Application Notes N Non design verification pin using sync8_fx as 37 no timing mode 42 P pins commands 46 declarations 46 name 46 read only 46 writable 46 ports connected 49 driver 49 naming convention 45 R reset 43 runtime support files 53 S SCFFILE property for SmartCircuit models 13 session commands 43 settling out technique 42 smartccn command 14 SmartCircuit model basic information 13 debugging tools 15 definition 11 design flow 12 model command file MCF 13 SCFFILE property 13 SmartModel library 41 SmartModel Library documentation 7 SmartModel windows 44 Index static member function LSC SwiftModel status report 43 stream name 46
20. File The model has a separate command class for each of its command streams A command header for the model contains a class constructor destructor and declarations for a method for each of the stream commands The parameters for the constructor include the required SystemC instance name and the name of the corresponding model instance The model instance name ModelInstance must be the instance name of the model and must be the same as the Name parameter to the model constructor In other FlexModel HDL wrappers the commands have model name prefixes For example in Verilog there is a cake read req command for this model while in this wrapper the command is called read req Note that there is no potential for name conflicts since the command is a member function of the cake z cmd class In outline the command class for a FlexModel is a subclass of LSC FlexCommands It contains register declarations constructor and destructor and declarations for the model command member functions The constructor requires a SystemC instance name and it also requires the model instance name so the commands will be directed to the correct model instance cake fz cmd h difndef CAKE FZ CMD H define CAKE FZ CMD H include lsc_FlexCommands h class cake_fz_cmd public LSC_FlexCommands public Cake Pin Declarations Cake Register Declarations cake fz cmd const string const string amp ModelInstance cake fz cmd C
21. SYNOPSYS SmartModel Products Application Notes Manual SmartModel Application Notes Copyright O 2001 Synopsys Inc All rights reserved Printed in USA Information in this document is subject to change without notice SmartModel ModelAccess ModelTools SourceModel Library LM 1200 and Synopsys Eaglei are registered trademarks MemPro MemSpec MemScope FlexModel LM family LM 1400 Logic Model ModelSource and SourceModel are trademarks of Synopsys Inc All company and product names are trademarks or registered trademarks of their respective owners Synopsys Inc August 2001 SmartModel Application Notes Contents Contents Prelate eP 7 wu do 0 ACER DP 5550S G45 6450554555940 48S 4 ee Sends es DOSUENDE uaa bh ee ba a ERR ed ea 7 harmi e Kea aae e Ere EENET e E kee EE EE ae E E E T Typographical and Symbol Conventions cocuoooaro ek uu ERRAT RR EET Y 8 CN ech baeo ie pl dlc ba io edd i or equ diac eles 9 The Synopsys Websil cuasecsskuwesxxexR WRadbuV KU E DE RR MH IE OUR RR 9 Synopsys Common Licensing SCL Document Set 4 10 EODEM wanes ci 6 ee dodi ee oe ee eee 10 Chapter 1 Verifying FPGA Dee k ceadednwwniais ned wnaduddauaaeuweweweed pad ed wed 11 i i ee ee ee ERGO DRE pir 11 What Are SmartCircuit Models bso bce ead d HER ERS CRY de R Ra RR 11 SmatCircuit Design Flw Lus eua ee ERRREAXXOZARASRVRAD EH Rare RR REA ERR a 12 Sm
22. ake Model Command Declarations endif CAKE FZ CMD H The pin declarations provide access to the FlexModel pin commands Each model pin has a corresponding member in this structure Each pin name has the stream name as a prefix to help avoid confusion with the normal pin operations These members are automatically initialized when the model command class is constructed The read only pins support PinReq and PinRslt operations Writable pins also support the SetPin operation SetPin is also available through an operator See 1sc_CommandPin h and lsc CommandPinTemplates hin LMC HOME include for the details of using these member functions 46 Synopsys Inc August 2001 SmartModel Products Application Notes Manual Cake Pin Declarations LSC CommandBus 32 cmdAD LSC CommandPin cmdADS LSC CommandPin cmdCLK LSC CommandPin cmdDC LSC CommandPin cmdHOLD LSC CommandPin cmdHOLDA LSC CommandPin cmdINT LSC CommandBus 3 cmdINTB LSC CommandPin cmdNMI LSC CommandPin cmdPEND LSC CommandPin cmdRDY LSC CommandPin cmdRST LSC CommandPin cmdRW Chapter 3 SystemC SmartModel Library There is a member for each model register The parameter for the LSC Register class template is the register width LSC Register provides member functions RegReq RegRsl1t and SetReg also available as the operator LSC RegisterReadOnly does not have the Set Reg operation See 1sc Register
23. apper generator puts the wrapper files in the working directory Code Examples A SystemC design is a set of SystemC C files that you construct Note that the set of files includes an associated Makefile To use the SWIFT models you must include the model header file in the files that refer to it as shown in the following include example include cake fz h Here are fragments from a testbench that uses the cake z model illustrating how it is set up Since the model instance name must agree between the model and its command class it is worth defining a global constant for it as shown in the following example const char const ModellInstanceName instance Modules that use the testbench commands must include the command header as shown in the following example include cake fz cmd h Command Stimulus The following example shows the clock and signal declarations and how they connect to a SWIFT model int sc main int ac char av sc clock CLK CLK sc_signal lt sc_lv lt 32 gt gt AD SC signal sc logic gt ADS Sc signal sc logic gt DC Sc signal sc logic gt HOLD SC signal sc logic gt HOLDA Sc signal sc logic INT Sc signal sc lv 3 INTB Sc signal sc logic gt NMI SC signal sc logic gt PEND August 2001 Synopsys Inc 51 Chapter 3 SystemC SmartModel Library Sc signal sc logic gt RDY Sc signal sc l
24. artCircuit Models Some Basics 00 cee eee eee eee eee 13 Load Command SWEERS sparred rakin EEEE ANENE edo Rad 14 Other General MCF Commands occ inst Cine sade saw sae en wi ER 15 Debuseing LONE 63 44 54540 ong SS adima oA ARRA IRR Aa E A E D HERO 15 Visual SmartBrowser VSB usua REA d EAR ATCRACR ACA Wee 16 TUMORS ihe tin he deua td wed Rus dw RP dd db ddr dor I e a dean 23 dec DAC M R 26 Targeting Unsupported DOO irrerirprrni SIR RE Ra AR ER RC Rd ERR 3l Interactive SmartBrowser Commands 4 0s4c4see0 nh veuebaseesecaan 31 Chapter 2 Interfacing with Non FlexModels eee nnn 33 sr n cio aeaa a a a a a e RGA 33 Synchronizing with Non FlexModels ilassas uk RR RR EAR 34 Synes Dc Model nerna 4 dae hh4 46 S40 ee eee Jennie EQUES RI ICPES 25 Using PCI SourceModels and ppc603 fx FlexModel in Same Design 36 Sync8 as Non dester Verification Pin s csai dsc esos masses REA RR RE ea 37 Chapter 3 SystemC SmartModel Library ind cowed waxued uk wi exec e x doe RR ORC c 41 Supported SmartModel Library Capabilities 4 4 ssawsves RR 42 August 2001 Synopsys Inc 3 Contents SmartModel Application Notes dos usb o0 MCCC T 42 ti T RS 42 Ch ulxagam xR Red E EUMD EE ERU ee ERU CREER CIO AC ER 42 Timings ile LUUD ee eee eee eee ae eae eee ere rr eps td RC 42 Command Channel rrr 43 Fonli Simulation 5 ooh nd ees obs PT 43 Pe ON OS Amp
25. ator you are using this may be one of the following e Property on the symbol e VHDL generic e Verilog defparam The SCFFILE property must be set to point to a model command file MCF which is a text file that you use to tell the model which netlist to load and to enable disable the simulator interactive model debugging features SCFFILE gt Model Command File MCF The following is an example of a basic MCF Ht at ae at aE aE AE HE aE aE HE AE HE aE aE AE EE HE aE aE aE EE aE PE EHE EHE EHE EE E HtPHH Model Command File MCF HHH H f at ae aE aE at aE HE aE AE HE AE HE aE aE AE aE AE HE a EAE HEE Ea Ea EEE EE EEE EE Load netlist design file ccn load source d projects flying ducks edif ducks edo There are several reasons to configure a SmartCircuit model through an MCF file During a simulation you will typically turn on and off the debugging features you are using If you have to change a property on the model to do this you might have to recompile the design Setting the SCFFILE property once and then changing values in the MCF means changes won t require you to recompile your design Configuring the model in this fashion also means that you only have to learn how to use the SmartCircuit models once irrespective of which simulator you are using This process enables you to develop a clean and easy simulation design flow for all your FPGA vendors August 2001 Synopsys Inc 19 Chapter 1 Verifying FPGA Desig
26. c int 32 VVV NV SmartModel Products Application Notes Manual xfer_attr wait_mode amp status addr bv xfer attr data wait mode amp status addr bv xfer attr wai t mode amp status addr v d xfer attr data0 datal data2 data3 wait mode amp status Tag cmd tag amp data amp status tesxt amp status Synopsys Inc August 2001 SmartModel Products Application Notes Manual Chapter 3 SystemC SmartModel Library Product Usage The overall flow of a testbench for a CFlex model in SystemC is shown in Figure 9 Each box in the figure represents a separate SystemC module The solid arrows in the diagram represent global signals in the testbench to which all the ports of the model are connected The dotted arrows indicate command activity In more realistic designs the SWIFT models will be nested inside other SystemC processes Since the command interactions do not depend on SystemC scheduling they are not required to be in separate modules but can be interleaved with port activity Port Driver Stream 1 Command gt Model Driver Stream N Command 4 Driver Figure 9 Testbench Connectivity SystemC enforces a one cycle delay on the propagation of signals between SC THREAD modules so if the port driver sets a value at time T the model will not see it until time 7 1 There is a corresponding delay between
27. c r 43 R set and Boconl BIB oe cock deed or xe sean HER Rak RE E RR EE 43 Model Status Report 5 s dee oo eG ede xs dS SSG RUE XR OO EROR CR SEH 43 Damp Memoty Contents 4 is ieee hier VERA REGXG COE eed ee ese CR A 43 Model LOUSRINWEE cine cad pane RERO RO RE AH dE endedeand er RA Ac RS 4 WC ei 4 x ie OUS Qe A A EVO OES KE UP ROSE CEG od NOR 44 SmartModel WiINdOwWS 4 keh bn eee deeb en deneseseieeunt deere deed ends 44 Wrapper Generation auecsq4soe bres perpe ERA Eq ad db bad bands cowed 44 Model Header PU 2404050 ad eee ERRARE RRA EDEN AARTEEN OR ESO CR EROR A 45 Model Command Header DIE 2s sce ketuietie denice duteseedeneese sec 46 PRIBOHS Support uiuis ee ee paadi en ee er eee eee eae er eee 48 Product Usag oosdus 4E VI CURE I PCR KY nb VR CREAR KT Re CR Ren 49 eccl oro Meme rrr PE 49 Using SWIFT Models in SystemC Designs ccc cece cece ee eens 51 Wrapper Files ee a ee ee rob ee AC ICE ERA 51 Lolo FOUNDER eubexedebp ereXbextadicbp e d dubi ER ee eed ee bene see 51 Il roo vTc rrerrrrrervrrPEPC a 53 e coo bok E mnm 54 i oer rer err Te Terr eT Ter Te Tr T T 55 Synopsys Inc August 2001 SmartModel Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 August 2001 Application Notes Figures Figures SmartCircuit FPGA Design Flow uses aea ra Rr EROR aes 12 Waveform Viewing Through Windows eese 23 Even INC LLossmec RR oS
28. chronization possible when you are using non FlexModels in any of the testbenches Sync8 as Non design Verification Pin One of the drawbacks of using C testbenches is limited visibility into the DUV and testbench registers that are easily accessed in the top level HDL For example if you are designing an ASIC and need to decode the state of multiple output pins for event synchronization in the testbench or to drive a microprocessor reset you can hook up an instance of the sync8 fx model to those ASIC pins You can then write some combinational logic in the C testbench to decode the states of those pins and drive a signal on one of the sync8 fx bidirectional pins Suddenly an event of interest in the top level HDL is visible to your C testbench You can create complex verification triggers this way and start or stop testbench processes based on the states of those triggers at any point in the simulation In this way the sync8 fx model helps make up for the lack of a clock in the C testbench August 2001 Synopsys Inc 37 Chapter 2 Interfacing with Non FlexModels SmartModel Application Notes With the addition of the non design verification pin provided by the sync8 fx model you can also more easily track trigger events in the simulation waveform viewer There is now one decoded signal to view rather than multiple independent signals One example for how to use the sync8_fx model as a non design verification pin is illustrated in Figure 8
29. correct a problem with minimal impact on simulation performance Event tracing uses an automated history mechanism that operates from user specified trigger points to e Trace back to locate the root cause of any logic event error e Trace forward to find the effects of any specific logic event e Identify the root cause of any timing constraint violation 26 Synopsys Inc August 2001 SmartModel Application Notes Chapter 1 Verifying FPGA Designs Event tracing reports identify the root of logic or timing errors by generating a list of events internal to the FPGA that are causally related to the problem event You can control the scope of the report as well as target multiple events and simulation times as shown in Figure 4 Logic Event Flow Parent Event O Child Event gt Figure 4 Causal and Event Tracing For more information on SmartCircuit debugging tools refer to SmartCircuit FPGA Models in the SmartModel Library User s Manual Causal Tracing To turn on causal tracing add the following lines to your MCF file set cause full report cause net name start time end time For a complete example suppose you want to turn on causal tracing for a design called ducks alpha ccn You would place the following in your MCF file load source d projects flying ducks mcf files ducks alpha ccn set cause full report cause net CE 150 300
30. d system level designs For more information on SystemC refer to the SystemC User s Guide You can obtain SystemC documentation from http www systemc org SystemC provides a cycle simulation environment as part of its class library The SmartModel Library is designed to work with event driven logic simulators and has extensive support for modeling device timing accurately For more information on the SmartModel Library refer to the SmartModel Library User s Manual The SystemC class library provides a SWIFT Integration for SystemC gt Note Because of the mismatch between the cycle simulation capabilities of SystemC and the event simulation bias of the SmartModel Library there are some restrictions for SystemC users of the SmartModel Library This chapter contains information about the following topics Supported SmartModel Library Capabilities on page 42 Wrapper Generation on page 44 Product Usage on page 49 e e e Platform Support on page 48 e e Using SWIFT Models in SystemC Designs on page 51 August 2001 Synopsys Inc 41 Chapter 3 SystemC SmartModel Library SmartModel Products Application Notes Manual Supported SmartModel Library Capabilities Command Control All FlexModels and MemPro models support command control FlexModels provide HDL and C command control SystemC users of FlexModels will typically call commands from SystemC testbenches thus using HDL control Attributes
31. ge 23 For more information on the Main Window refer to Main Window in the UNIX version or NT version of the Visual SmartBrowser User s Manual 18 Synopsys Inc August 2001 SmartModel Application Notes Hierarchy View Chapter 1 Verifying FPGA Designs The best place to start navigating your design is with the Hierarchy View Hierarchy View Zoom Buttons Design Hierarchy E Hierarchy View TOP j instruction_register TOP 13 IZO CLOCK IR DPO55 IZO INST_BITO DP042 Design Ports The Hierarchy View displays the hierarchy of the post routed netlist By default the top level of the design is selected so that you can see the external ports of the FPGA design in the bottom half of the window A port icon identifies a port as an input output or I O pin Next to the icon you can see your design port name followed by the model pin name If you double click on any of the cells in the upper part of the Hierarchy View the VSB will display an Examine View for the cell The zoom in and zoom out buttons enable you to select the amount of detail that you want to see in the Hierarchy View If you double click on the port icons in the lower section of the Hierarchy View the VSB will display the schematic Connection View For more information on the Hierarchy View refer to Hierarchy View in either the UNIX version or NT version of the Visual SmartBrowser User s Manual August 2001 Synopsys
32. ger and bit vector values for models Since the models in the SmartModel Library already support four state logic the wrappers provide access to four 4 states through the use of sc 1ogic and sc 1v types for the model ports Chapter 3 SystemC SmartModel Library The only parameter to the model constructor is the model instance name The command instance name is derived automatically from the model instance name None of the other attributes for this model are applicable in a cycle simulator framework and therefore are handled automatically Note that the port names are in upper case to avoid conflict with C keywords cake fz h difndef CAKE FZ H define CAKE FZ H include lsc FlexModel h class cake fz public sc_in sc_in sc_in sc_in sc_in sc_in sc_in SC ou SC ou SC ou SC ou SC ou Sc in bool SC SC SC SC SC t sc E lt SCL SC t sc public LSC FlexModel x lt E lt SC lt lt lt gt CLK logic gt HOLD logic gt INT lv lt 3 gt gt INTB logic gt NMI logic gt RDY logic gt RST logic gt ADS logic gt DC logic gt HOLDA logic gt PEND logic gt RW t SC out sc lv 32 gt AD cake fz const string amp Name cake fz endif CAKE FZ H August 2001 Synopsys Inc 45 Chapter 3 SystemC SmartModel Library SmartModel Products Application Notes Manual Model Command Header
33. gh the design to the U3 I 6 instance net SmartModel TRACE Instance TESTBENCH DUT SMART SMartCircuit at time 1087 1 NS Triggering effect report from DBUS lt 6 gt at 1087 1 ns 1087 1 ns Effect 0 gt X on cell port CELL3 O net U3 N163 1090 9 ns Effect 0 gt X on cell port CELL50 O net YSIG6 1090 9 ns Effect 0 gt X on cell port U3 I 6 D net YSIG6 Report completed For more information on effect tracing refer to Visualizing an Effect Report from a Simulation Run in the UNIX version or NT version of the Visual SmartBrowser User s Manual Causal Trace Report You can enable both causal and effect tracing on any internal net or port within the FPGA design You can control the scope of the report and target multiple events and simulation times You can also cut a causal report from the simulator transcript and paste it into the VSB Causal Trace window The VSB will then graphically display the path in which you are interested Causal Trace Window YSB Causal Trace Iof x Enter Trace Text from Simulation uc Model Trace in TB DUT CFPGA SMARTMODEL at 16100 ps Beginning cause report from JDOE FSRAMCE 16 1 ns 0 gt X on cell port U1287 1120 GTS TRI OUT net 16 1 ns 0 gt X on cell port U1287 1120 0UT net U1287 ns 0 gt X on cell port FSRAMCE INT reg OUT net ns X 1 on cell port FSRAMCE INT reg CIK net ns X 1 on cell port U879 clkbuf OUT net n2468 ns X
34. gust 2001 Synopsys Inc 33 Chapter 2 Interfacing with Non FlexModels SmartModel Application Notes Synchronizing with Non FlexModels The command streams for one or more FlexModels are synchronized by the FlexModel Command Core But there is an issue if your design includes SourceModels user developed models or 3rd party models these models are not visible to the FlexModel Command Core This means that you cannot coordinate testbench processes for FlexModels with non FlexModels To solve this problem instantiate the sync8 fx model in your design and hook it up to the non FlexModel that you want to coordinate with FlexModels The central role of the Command Core is illustrated in Figure 5 HDL Testbench DUV C Testbench Figure 5 FlexModel Command Core 34 Synopsys Inc August 2001 SmartModel Application Notes Chapter 2 Interfacing with Non FlexModels You can connect the sync8 fx model to pins on your non FlexModel using the model s 8 bit I O bus and four I O pins Then you can use sync8_fx FlexModel commands to sample the values on any of those pins If you want to use a sync8 fx pin as an output just enable the pin using the sync8 output enable command You can also use the flex synchronize command to synchronize the activity of your non FlexModel with the other FlexModels in your design For detailed information on the all of the model specific commands supported by the sync8 fx model refer to the model data
35. hand sc RegisterTemplates h in SLMC_HOME include for usage details Cake Register Declarations LSC_Register lt 16 gt cntclk LSC_RegisterReadOnly lt 4 gt state LSC_Register lt 4 gt eagle_trattr The model command declarations provide access to all the model commands The generic FlexModel commands are available in the LSC_FlexCommands parent class Cake Model Command Declarations void set msg level const int int void set timing control const int const bool int void idle const int const bool int void read req const sc int 32 gt mode amp status index S amp S idle_count wait_mode amp status addr bv August 2001 Synopsys Inc tate tatus 47 Chapter 3 SystemC SmartModel Library const int const bool void write const const const const void burst_read_req const int sc_int int sc int bool int lt 32 gt lt 32 gt const int const bool int void burst_write const sc_int lt 32 const int const sc_int lt 32 const sc_int lt 32 const sc_int lt 32 const sc_int lt 32 const bool int void read_rslt const int const int sc_int lt 32 gt int void print_msg const ch int Platform Support Currently SystemC is available for Linux x86 Solaris HPUX and Microsoft Windows NT SystemC on Solaris works best with gcc but also works with limitations with the SUN SC5 0 compiler 48 s
36. ility substantially eases the FPGA verification and subsequent debug process You can also trace designated nets ports or states and force values on them which enables you to recreate corner cases and evaluate the functionality of a design August 2001 Synopsys Inc 23 Chapter 1 Verifying FPGA Designs SmartModel Application Notes You can use the VSB Windows amp Monitors tool to view nets and states Windows amp Monitors Windows amp Monitors B ysb_tutorial ccn View Window Help Ba Windows Select Global Ef Monitors JP Nets Clear Selection Window States Names 5 A Buses Ceat a a N7 Bus Preview File J A 13 N 7 gt _I 13_N 7 JF 4 12 N 7 gt I 12 N 7 Save to File Alias Name r Element Editor Partial MCF Add Bus N B Window ove Element Illegal Chars Save MCF Monitor Up B Auip Add r Selection Adder Selected Object Net N Scope 1 12 Add Global Sel v Automaticaly Add New Selections Object Type Add To IV Nets windows Iv Bus States Iv HAGnitars N7_Bus Monitor Close Help Modified Z Selection Net N 7 Scope 1 127 For Help press F1 When you select anything in other VSB windows the selected object is added to the windows You can also alias names in order to make them easier to understand in a simulation 24 Synopsys Inc August 2001 SmartModel Application Notes Chapter
37. is 4 0 ns Instance TESTBENCH DUT SMART SmartCircuit at time 12 1 NS SmartModel TRACE Constraint causal report for event on CLR at 12 1 ns 12 1 ns 1 gt 0 on cell 10 5 ns 1 50 on cell port CELL72 0 net YSIG27 port CELL37 0 net U2 N658 5 5 ns 0 51 on cell 3 0 ns 0 1 on model Report completed port CELL33 O net N4 port RESET For more information on causal tracing refer to Visualizing a Cause Report from a Simulation Run in the UNIX version or NT version of the Visual SmartBrowser User s Manual Effect Tracing Example You can also perform effect tracing that enables you to track forward into an FPGA design Effect tracing is a technique that shows you what effect an input change has on the design To turn on effect tracing add the following line to your MCF file Report effect net name start time end time For a complete example s uppose you want to turn on effect tracing for a design called ducks alpha ccn You would place the following in your MCF file load source d projects flying ducks mcf files ducks alpha ccn set cause full report effect IN DATA 4500 6000 August 2001 Synopsys Inc 29 Chapter 1 Verifying FPGA Designs SmartModel Application Notes Effect Trace Report Example The following report traces the effect that a 0 to X transition has on the DBUS lt 6 gt port You can see that the X propagates throu
38. kly look at the path in which you are actually interested which saves time in searching through the entire schematic for a design problem For more information on the Connection View refer to Connection View in the UNIX version or NT version of the Visual SmartBrowser User s Manual Examine View Since the VSB is run on a SmartCircuit netlist that contains all of a design s specific delay and timing information extracted from the original vendor netlist you can access this delay and timing information through the VSB Examine View by double clicking on any of the cells in the Connection View This enables you to view the net names connected to the cell and change the timing that applies to that cell Examine View Examine View 1 12 View Window Help Name 1 12 Type DFPC Scope l 12 Documentation N 7 _ 3 LIBET N 21 gt T iming N 14 p CLR Highlighted es Timing Form W State Form v Close Help o For Help press F1 Unmodified 4 Tinie p p 7 button displays timing information For more information on the Examine View refer to Examine View in the UNIX version or NT version of the Visual SmartBrowser User s Manual August 2001 Synopsys Inc 21 Chapter 1 Verifying FPGA Designs SmartModel Application Notes Timing Form Model timing includes timing check values and cell routing delay values which contain all of the functional and timing information extracted from yo
39. l FPGA from the simulator command line of a testbench For more information on the interactive SmartBrowser refer to Browsing Your Design Using SmartBrowser in the SmartModel Library User s Manual August 2001 Synopsys Inc 31 Chapter 1 Verifying FPGA Designs SmartModel Application Notes 32 Synopsys Inc August 2001 SmartModel Application Notes Chapter 2 Interfacing with Non FlexModels 2 Interfacing with Non FlexModels Introduction One of the most useful FlexModels isn t a real model at all The sync8 fx FlexModel does not represent any physical device or bus protocol Instead it acts as an interface to other models in the testbench and simplifies complex verification processes You can use the sync8_fx model to e Make SourceModels user developed models and 3rd party models visible to the FlexModel Command Core so that you can synchronize those models with the FlexModels in your design e Serve as a non design verification pin that makes design under verification DUV signals visible to C testbenches and easier to trace in the simulator waveform viewer This chapter explains how to use the sync8 fx model to solve these and other common verification problems in the following major sections e Synchronizing with Non FlexModels on page 34 e Sync8 fx Model Interface on page 35 e Using PCI SourceModels and ppc603 fx FlexModel in Same Design on page 36 e Sync8 as Non design Verification Pin on page 37 Au
40. le just as you can the window and bus commands For more information on SmartModel windows refer to SmartModel Windows and SmartCircuit Monitor in the SmartModel Library User s Manual For more information on the VSB Windows amp Monitors refer to Windows amp Monitors Tool in the UNIX version or NT version of the Visual SmartBrowser User s Manual August 2001 Synopsys Inc 25 Chapter 1 Verifying FPGA Designs SmartModel Application Notes Event Tracing A key factor in successfully verifying an FPGA design is the ability to debug functional and timing errors If you encounter functional or timing errors during a simulation run it is important to quickly trace the event back to the parent event that is the root cause of the problem In a large design this can be a very complex task For example suppose you have a violation of setup constraints like those illustrated in Figure 3 Manually analyzing hundreds of possible paths to identify a logic or timing error would be very time consuming 242 0 0 to 1 on port A1 cK r Al zr A2 Violated setup constraint L on D at time 260 0ns A3 Tsu Was 2ns specified minimum is 5 0ns A5 REG1 CLK c 258 0 0 to 1 on port CLK Figure 3 Event Tracing Event tracing helps you identify the source of a functional error or timing constraint violation so that you can quickly
41. ns SmartModel Application Notes Load Command Switches The load command specifies the netlist to load for the model when you start the simulator The following are switches you can use with the load command source nocheck scale The source switch tells the model to auto compile the netlist The netlist is compiled into the SmartCircuit internal ccn format The netlist is compiled only if the ccn file is out of date with respect to the source netlist which can happen if you overwrite the vendor netlist with a new one Compiling like this saves time at simulation startup To configure the full functional full timing model in your simulator you need a minimum of one line in the MCF load source netlist pathname The nocheck switch disables reports of all timing constraint violations You should use this switch only if you do not care about timing violations during the simulation The following MCF example incorporates the nocheck switch load source netlist pathname nocheck The scale switch scales all of the timing that is extracted from the netlist This switch enables you to experiment with how a change in the timing characteristics would affect on your design As an example a factor of 0 9 will up rate the timing whereas a factor of 1 1 will de rate the timing The following MCF example incorporates the scale switch load source netlist pathname scale 1 1 You can also pass switches from the load command t
42. o a compiler called smartccn which is called to compile the vendor netlist into the ccn format of the netlist design file For more information on smartccn and smartccn switches refer to smartccn Command Reference in the SmartModel Library User s Manual 14 Synopsys Inc August 2001 SmartModel Application Notes Chapter 1 Verifying FPGA Designs Other General MCF Commands The following are other commands that you can use in conjunction with an MCF echo string The echo command enables you to print a message to the simulator transcript window when the model reads the MCF file This is useful in identifying which netlist you have loaded at simulation startup The following example combines a load command and an echo command load source netlist pathname echo Loaded Design 1 of Project Flying Ducks do filename The do command executes MCF commands that are stored in another file Storing MCF commands in this manner enables you to partition the debugging feature commands into separate files which makes them easier to manage if you intend to enable all of the debugging features The following example combines a load command an echo command and two do commands that reference two separate files containing different sets of MCF commands load source netlist_pathname echo Loaded Design 1 of Project Flying Ducks do d projects flying ducks mcf files windows do do d projects flying ducks mcf files causal trace do For
43. ogic RST Sc signal sc logic RW cake fz Ca Cake Ca Ca Ca Ca Ca Ca Ke Ke Ke Ke KE Ke Cake Ca Kc Cake Ca Ca Ca SC IG ke ke ke Ot st tur ADS ADS DC DC HOLD HOLD HOLDA HOLDA INT INT INTB INTB NMI NMI PEND PEND RDY RDY RST RST RW RW AD AD art 1 n 0 SmartModel Products Application Notes Manual ke Wrapper ModelInstanceName CLK CLK signal her initializations here Note that preceding sc_main there is usually a module containing command and possibly port stimulus The following shows an example of command stimulus ca Ca Ca Ca Ca Ca Ca Ca keCmd keCmd keCmd keCmd keCmd keCmd Cake Register Operations idle 0x1 fal ke fz cmd CakeCmd CakeCmd keCmd ModelInstanceName set msg level Ox4fffffff status se read req 0xf00 write 0xf08 write Oxf0c read req 0xf04 0x3 0x3 0X3 0x3 status flex_print_msg Hello World status false status false status 0x76543210 false status OxfOf0 false status The following fragment illustrates how to set and get values from a cake z register It first sets the value of the cnt c1k model register to waits two cycles then gets the value back Cake Register Operations int status
44. re FlexModel 34 commands channel 43 class 46 do 15 echo 15 Flex model pins 46 August 2001 Index Index general for MCF 15 header 46 51 instance name 45 interactive for Visual SmartBrowser 31 load 14 member functions 46 model 44 model name prefixes 46 session 43 smartccn 14 stream ID 42 streams 46 testbench 51 Verilog 46 comments submitting 10 configuration attributes 42 constructor class 46 conventions typographical and symbol 8 cycle simulation environment 41 cycle simulator 42 D datasheets accessing 13 debugging tools for SmartCircuit models 15 declarations constructor 46 register 46 design flow for SmartCircuits 12 destructor class 46 devices simulating unsupported 31 do command 15 do file for MCF 25 E echo command 15 effect tracing MCF example 29 report example 30 Synopsys Inc 55 Index environment variables LMC COMMAND 43 44 LMC HOME 44 53 event simulation 41 42 event tracing 15 event tracing for VSB 22 examples model logging command 44 session command channel 44 F fault simulation 43 file attributes 42 Flex models 42 46 51 HDL wrapper 46 FlexModel Command Core 34 four state logic 45 FPGA design flow 12 SmartModels 11 verifying designs 11 G global signals 49 H HDL 42 help about Synopsys products 9 HPUX 48 instance name 46 command 45 model 45 interactive SmartBrowser commands 31 K keywords C 45 56 Synopsys Inc SmartModel
45. s and symbols used in it Tells how to get technical assistance Chapter 1 Different ways that you can use SmartModel FPGA Verifying FPGA Designs models to debug programmable designs Chapter 2 How to use the special sync8 fx FlexModel to Interfacing with Non FlexModels interface with non FlexModels and simplify complex verification processes August 2001 Synopsys Inc 7 Preface SmartModel Application Notes Typographical and Symbol Conventions Default UNIX prompt Represented by a percent sign User input text entered by the user Shown in bold type as in the following command line example cd SLMC_HOME hd1 System generated text prompts messages files reports Shown as in the following system message No Mismatches 66 Vectors processed 66 Possible Variables for which you supply a specific value Shown in italic type as in the following command line example setenv LMC HOME prod dir In this example you substitute a specific name for prod_dir when you enter the command Command syntax Choice among alternatives is shown with a vertical bar as in the following syntax example effort level low medium high In this example you must choose one of the three possibilities low medium or high Optional parameters are enclosed in square brackets as in the following syntax example pinl pin2 pinN In this example you must enter at least one pin name pin but others are op
46. sheet Like all FlexModel datasheets you can access the latest version of the sync8 fx datasheet using the Model Directory http www synopsys com products Im ds s sync8 fx pdf For information about using global FlexModel commands such as flex synchronize refer to the FlexModel User s Manual Sync8 fx Model Interface The sync8 fx is a simple model with just the 8 bit bus and four I O pins mentioned above and four 8 bit internal registers as shown in Figure 6 io BUSTA V y lO 0 8 jhe lO 1 88 We lO 2 8 lO 3 8 CLK RESET Figure 6 sync8_fx Model Interface If you need to hook up a wider bus just instantiate the sync8_fx model multiple times to achieve the desired configuration For example you could use four instances of the sync8_fx 8 bit bus to expose all lanes of a 32 bit bus to the FlexModel environment In many cases one model instance is sufficient to get the desired results but that depends on your testing requirements August 2001 Synopsys Inc 35 Chapter 2 Interfacing with Non FlexModels SmartModel Application Notes The sync8 fx model also provides four 8 bit registers that you can use to save and compare data patterns using the FlexModel commands documented in the sync fx FlexModel Datasheet Using PCI SourceModels and ppc603 fx FlexModel in Same Design For illustration purposes con
47. sider a PCI bridge DUV being verified with the help of the PCI SourceModels and the ppc603e fx processor FlexModel You can use the sync8 fx model to bring the PCI SourceModel under the control of the FlexModel Command Core Then use flex synchronize commands to coordinate the command streams for the two different types of models Figure 7 provides a high level overview of the process read 7 I Memory A write PCI Master PCI Slave PCI Monitor SourceModel SourceModel SourceModel Memory Figure 7 PCI SourceModel Coordinated with FlexModel 36 Synopsys Inc August 2001 SmartModel Application Notes Chapter 2 Interfacing with Non FlexModels For example a bus cycle can occur when the PCI Master is writing a block of video data to local memory and the processor is simultaneously trying to read the same block of video data from memory Even though the processor has to arbitrate for the bus to read from memory what if you want to wait until four packets of video data are available before reading them all To solve this problem use flex synchronize commands to coordinate the command streams of the two different model types in your testbench You can also use the sync8 fx to coordinate model processes across multiple testbenches This works for any combination of HDL and C but is particularly useful for multiple C testbenches that have model processes running in parallel The sync8 fx model is the tool that make this syn
48. tform e UNIX LMC HOME bin vsb CCN file pathname e NT LMC_HOME bin vsb CCN file pathname For example if you are on a UNIX platform you would issue the following command on a netlist design file called ducks alpha ccn LMC HOME bin vsb d projects flying ducks mcf files ducks alpha ccn The ccn file exists only if you have already run a simulation If you want to view the netlist with VSB before you run the simulation you must compile the netlist with the smartccn netlist compiler To run smartccn from the command line execute the following as appropriate for your platform e UNIX LMC HOME bin smartccn m model name netlist pathname e NT LMC HOMESMbinNsmartccn m model name netlist pathname You must use the m model name argument to designate to smartccn which model to target 16 Synopsys Inc August 2001 SmartModel Application Notes Chapter 1 Verifying FPGA Designs The smartccn compiler generates a ccn file in the current working directory after which you can invoke the VSB on the new file The smartccn compiler also generates a pmp file which you can use to see which internal port names have been mapped to the SmartCircuit model SmartCircuit pin names are generic for the configurable pins whereas all the dedicated FPGA device pins are set by the vendor For more information on smartccn and smartccn switches refer to smartccn Command Reference in the SmartModel Library User s Manual gt Note
49. the model and the results checker There are no delays associated with the command interactions that do not use SystemC for scheduling but instead go directly to the model If you place input commands with port inputs and result commands with port outputs these effects can be avoided Installation SystemC SWIFT is a standard part of the SmartModel Library delivery Its components are installed by way of the conventional installation process For more information about the installation process refer to the SmartModel Library Installation Guide The check box to install the SystemC support is outlined in Figure 10 from the SmartModel Administration tool s1 admin August 2001 Synopsys Inc 49 Chapter 3 SystemC SmartModel Library SmartModel Products Application Notes Manual X Select Platforms for SmartModel Library Installation COIR i casas kona oN fo rc REE Figure 10 Installing SystemC SmartModel Support 50 Synopsys Inc August 2001 SmartModel Products Application Notes Manual Chapter 3 SystemC SmartModel Library Using SWIFT Models in SystemC Designs Wrapper Files After the SmartModel Library is installed you must generate wrapper files for the desired models as shown in the following wrapper generation example SLMC HOME bin scsg cake fz For most models there are two wrapper files with h and cpp suffixes For FlexModels there are also h and cpp files for the command interface Note that the wr
50. tional pin2 pinN Synopsys Inc August 2001 SmartModel Application Notes Preface Getting Help If you have a question while using Synopsys products use the following resources Start with the available product documentation installed on your network or located at the root level of your Synopsys CD ROM Every documentation set contains overview information in the intro pdf file Additional Synopsys documentation is available at this URL http www synopsys com products Im doc Datasheets for models are available using the Model Directory http www synopsys com products Im modelDir html 2 Visit the online Support Center at this URL http www synopsys com support Im support html This site gives you access to the following resources o SOLV IT the Synopsys automated problem resolution system o product specific FAQs frequently asked questions o lists of supported simulators and platforms o the ability to open a support help call o the ability to submit a delivery request for some product lines 3 If you still have questions you can call the Support Center North American customers Call the Synopsys Eaglei and Logic Modeling Products Support Center hotline at 1 800 445 1888 or 1 503 748 6920 from 6 30 AM to 5 PM Pacific Time Monday through Friday International customers Call your local sales office The Synopsys Website General information about Synopsys and its products is available at this URL http
51. ur place and route tool You can access timing information through the VSB Timing Form which enables you to change any timing parameter on the cell and experiment with different scenarios to identify a fix to a timing problem These changes do not affect the source netlist but enable you to identify exactly where the problem lies so that you can then fix the problem in the source Timing Form P Timing Form A State Form wi Close Help Timing Selected Timing Accent Modiicatan H D CLKNLI Name ene D ificatior H CLR CLKNI frre TS CLR CLKNI Setup on D before CLK TH PRE CLKN TS PRE CLKNI PwLMIN CLKN 2 PwHMIN CLKN Timing Value Units ps C ns C us C ms Timing PWLMIN CLAN ARENA PwWwHMIN PREF alues in ccn File Values 1300 3600 5200 TPB CLKLH Current Values TPD CLKHL 300 3600 5200 CLRLH TPD GpHL 1 Min Typ Max For Help press F1 Unmodified 7 As an example suppose you have encountered some sort of timing violation You can use VSB Event Tracing discussed on page 26 to identify the critical path which enables you to look at the timing used for the cells on that path If you identify a large delay on that path you can use the timing form to decrease a small amount of time from the path re save the ccn file and re simulate the modified design If this fixes the problem you know that you have to return to the source and constrain that path more
52. www synopsys com August 2001 Synopsys Inc 9 Preface SmartModel Application Notes Synopsys Common Licensing SCL Document Set Synopsys common licensing SCL software is delivered on a CD that is separate from the tools that use this software to authorize their use The SCL documentation set includes the following publications which are located in root docs scl on the SCL CD and also available on the Synopsys FTP server ftp ftp synopsys com e Licensing QuickStart 142K PDF file This booklet provides instructions for obtaining an electronic copy of your license key file and for installing and configuring SCL on UNIX and Windows NT e Licensing Installation and Administration Guide 2 08M PDF file This guide provides information about installation and configuration key concepts examples of license key files migration to SCL maintenance and troubleshooting You can find general SCL information on the Web at http www synopsys com keys Comments To report errors or make suggestions please send e mail to doc synopsys com To report an error that occurs on a specific page select the entire page including headers and footers and copy to the buffer Then paste the buffer to the body of your e mail message This will provide us with information to identify the source of the problem 10 Synopsys Inc August 2001 SmartModel Application Notes Chapter 1 Verifying FPGA Designs 1 Verifying FPGA Designs
53. ync8 pin rslt Inst 1 SYNC8 IOl PIN pin rslt amp status if pin rslt 1 found_pattern true sync8 output enable Inst 1 SYNC8 IO3 PIN FLEX ENABLE amp status flex wait 2 amp status Wait for 2 clock cycles sync8 set pin Inst 1 SYNC8 IO3 PIN b0 amp status flex fprintf stdout The value of pin PCI FRAME SYNC8 IO3 PIN is b STATUS Sd n pin rslt amp status You can set or clear individual or group timing checks for any pin on the sync8 fx using the model s controllable timing shell For example to disable all setups in the model use the following command sync8 set timing control Inst 1 SYNC8 SETUP FLEX DISABLE amp status To enable all holds in the model use the following command Sync8 set timing control Inst 1 SYNC8 HOLD FLEX ENABLE amp status For more information about the sync8 set timing control command and the predefined constants you can use to control model timing refer to the sync fx FlexModel Datasheet August 2001 Synopsys Inc 39 Chapter 2 Interfacing with Non FlexModels SmartModel Application Notes 40 Synopsys Inc August 2001 SmartModel Products Application Notes Manual Chapter 3 SystemC SmartModel Library 3 SystemC SmartModel Library SystemC is a C class library used for creating cycle accurate models of software algorithms hardware architecture and interfaces for System on Chip SoC an
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