PLD-FPGA`s design software, IP`s and hardware
Contents
1. b h DE 1 DP 0 sS 7 1 dowd wot dr se Wee ORI s Pe Be un 551 DW lt e L memi Rd ir i J MTM QE EDS OER ete EL ate ate EOM DEMO lt Ro we LC UA QB ae a H mee he 2 ar SE te x ase tie dee fee WEISEN PEPE et E Physical Lattice WRQW EEE edi EE Floorplan 21 21 gemiconductor Bringing the Best Together Place amp Route Setup Properties Normal Design Properties 22 Placernent Effort Level 1 5 Routing Passes 1 30 Remove previous design directory Disable Timing Create Delay Statistic File Ignore Preference Errors Routing Optians U 1 Advanced Options Placement Iterations U run until solved Placement Iteration Start Pt Placement Save Best Run Routing Resource O2. k OO Es n na E ry T HHWH da gt Lope u E 7 Lee T W DM pi e mibi x ma ciini mmn p Tn T fh m rm BE 1 99e ron papi FP usa i uim agn gt aio spi M us TEE az qi E E i Bind mu 1 L 2 19 IO ESO N wee Du L gt i LILIAN 4 1234567 zn an mjm m s P HE rie aANT T 21 m m dr Pim sia iden pa inen u et iiil HTTEETEI E IE i MES wai m m m m m mi ee 50 E S 1 ji Prototype RS 232 area 33 33 MHz RJ 45 S oed Fa EA Oscillator Lattice Semiconductor Corporation Copyright Lattice Semiconductor 2006 Bringing the Best Together Page 71 LatticeECP2 Advanced Evaluation Board Features Dual DDR2 SO DIMM memory sockets 10 100 1G Ethernet PHY with RJ 45 interface 5 14 2 TX Rx Connectors RS232 Driver Receiver USB Transceiver LCD panel interface TI EMIF Interface Connector On b
3. A v X tutor 12 Input Ports 1 Clock Input output Ports 1 2 Output Port id 3 output Port 4 Output Port 5 Output Port 6 Output Port 7 Output Port 8 Input Port 9 Input Port 4 l Pin Attributes xi Loading Lattice Preference File pre map PE is connected to Dispatcher Signal Group Name out Data outi O Data outi 1 Data outi 2 Data outi 3 Data out validi Loading device for application basnpdevice from file Grouped By ep5g49x58 nph amp pDesigns tutorl2 tutorl2 prf P DRC Cell Attributes Global Constraints Period Frequen In Qut Clock Multicycle done in environment C IO Type LVCMOS12 LVCMOS12 LVCMOS12 LVCMOS12 LVCMOS12 LVCMOS12 LVCMOS12 LVCMOS12 x On Demand Webcasts Software and IP Design Methods and Techniques Attend Live Broadcasts and Interact with Presenter Hear Archives Anytime ES Incremental and Modular Design Methods for High Density FPGAs Microsoft Internet Explorer File Edit View Favorites Tools Help Back v gt v 9 A QSearch Favorites 522 SSI Address http www latticesemi com corporate web
4. 33333 3333 om gt Sea ivider Step Sequencer Instruction Comment Step 0 Begin Startup Sequence yes ispPAC POWR 1208 reset 8 66 667 66 666 0 01 m MHz Step 1 Wait for SoftStarted_S AND SoftStarted 33 yes Wait For soft started 5 and 3 3 to stabilize AG Dieta 3 n nx yes Tum on the Lowest Voltage gt ei ut yes Wait For the Lowest Voltage to stabilize yes Turn 3 3 amp 2 5V for all remaining devices 4 aaa y yes Wait For All Supplies to stabilize ze yes Begin Reset pulse stretch yes Release Reset to the card and CPLI yes Monitor For Power Supply Faults yes Inform Processor About Supply Fault yes Wait For Processor to Take action yes Remove all Supplies yes Wait for 3 3 and 2 59 to drop below 1 5 yes SHorting FET ensures the CPU supply track during turn off no or Comment Card edge Reset signal Over rides PM generated Reset SS cell Configuration Comment It registered D Softstart 5Y amp 3 3V Bus after the card is enabled amp Isolate Card Under Fault It registered D flip Rop Enable 12V after the card is enabled and 12 supplies are stable it combinatorial non registered PCI Monitor signal indicating Faulty input supply 145 2 Lattice Semiconductor Corporation Bringing the Best Together PAC Designer
5. Boy dar FEF T 7 2 t i 1 Lb LES 4 EMIT J OLE lp 8 T By ort Jm 7 fag a LB i fa d Ej PITE SW E anni Tm 8 E Lu Fos 1 POWER ZI MERI a 1 zi EL rem x 1 d EE mpm ehh eee Tun e ina ate 4 N T s ____ E zT ie 100 4 I zr fac RO Fy NC Lg Treen 4 r b 2 ie Ao 5 Y rr REIS IRE JRFRESTREFREATATE ine sss nim TUTO TE cales 5 5 T B 3 K H H H 5 MW F t os l E csse MM iu ID hs SLT Iz Sh tatl aod EEEE E E 0 I a T x R KA L K K K K 2 a al GE GI SE CI RI GI AE TEG K Se eee leg Lipe uL mE Y KEELA RK KA
6. prcject largat device and add HOC er VDL source He the using he Pra ect Nev gator Generate a ys C PLL module add to your project wd refer to 1 fom your source P espimss and the Geter All interface ports must be of Standard SSTL25 For information about assigning standards see T1055 LatticeECP EC and LatticeXP syslO Web site links LOS Signals to device package pers ana deles a per od oF and cleck ho out Sring usmg the Preterence Edi the desig te mapping und fouling processes and view te ux n the Nav gat D Summary B Glossary D Recommended Reference Material Fats a a ee L L 2 at the DQ DQS group LaticwEC wiid ipi EVER 1 upport htm 2 Al 4 Q Lattice sss Copyright Lattice Semiconductor 2006 gt z Semiconductor Page 9 Corporation Bringing the Best Together Documentation How To Help Topics on FPGA functions Memories syslO Buffers SysCLOCK PLL sysCONFIG sysDSP Blocks DDR More Copyright Lattice Semiconductor 2006 Page 10 fispLEVER 5 1 FPGA Design Mozilla Firefox Edit view Go Bookmarks Tools Help Contents Inde
7. NN MT S eO a AE RIL Re Oe K S886 MURS aA LIT E FE 7 m 3 uc v jaaa ESI 1111 Loader i I m E LatticeEC Advanced Evaluation Board Copyright Lattice Semiconductor 2006 Latti 7 conductor 69 orporation Bringing the Best Together LatticeECP2 Standard Evaluation Board Features 64 bit PCI PCI x edge connector and form factor RS 232 amp RJ 45 Connectors Compact Flash Connector On board Flash configuration memory Prototype area kit w LEDs switches connectors headers and on board power supply Includes ispDOWNLOAD Cable for device programming Includes AC power supply International wall plug in 484 fpBGA Device ECP2 50 LFE2 50E 6F484C Availability Available Now On the web User guide including schematics sample program Copyright Lattice Semiconductor 2006 Se 70 Corporation LatticeECP2 Standard Evaluation Board SMA Flash 8 bit Connector switch and On board power LEDs supply iy r LI di Seu m n Ea saq ama ap y 1 LII cT L
8. Semiconductor Corporation Bringing the Best Together Power Calculator for FPGA Allows User to Determine Power Supply Requirements Toggle Rate Estimate Input VCD Import Total Power Summary Table Power and lcc Views XML Summary Parameters Airflow Heatsink Ambient temperature Operating condition Frequency Copyright Lattice Semiconductor 2006 Page 39 Power Calculator n Vpublic access schnettler designs top level schematicWwerilog hierarchical hierarchical design pep E a X File Edit Help D Family LatticeEC Device LFEC1E Part Name 1 20 viv Heat Sink Airflow 0 Operating Conditions Junction Temperature Ambient Temperature 25 0 LFEC1E 3T100C Total Estimated Estimated Estimated Estimated Estimated Estimated Estimated Estimated Design Design Design Design Design Design Power mW 18 800 Icc 115 Design xD Utilization x1 Utilization 0 0000 08 0 0000 1 2009 0 0000 x2 Utilization x6 Utilization UU 0000 DC mA Icc mA Freg MHz _ A Rd 96 AF 9 Rd 95 DC DC lec AC lcc AC lcc Input TR MHz Output TR 95 Block Inputs Outputs Bidir lO Registers Average Out Loading design
9. UR j ge 014 MachXO LCMXO256C 4T100C E COE E KS E T iru 1 ua ATO Pr 8 1 i Umi ae 130 1190 ht 2005 Power input On board jack oscillator Push button Switches Copyright Lattice Semiconductor 2006 Page 86 Wit LA CH nm i J D p LI ge w Starter Evaluation Board Off board expansion Proto area amp 89 0 99 5920 ti 9 LEDs Lans H 510 I unir a a d ad _ j 8 bit input switch JTAG programming Semiconductor Corporation Bringing the Best Together MachXO Standard Evaluation Board Features MachXO device Power input jack 3 3V 1 2V and adjustable power planes Adjustable oscillator Lattice ispClock5610 Clock Manager ispPAC CLK5610V 01T48C Status LEDs and 8 LEDs 8 bit input switch Access to all device I O Prototyping area Landing pads for LCD display AC Adapter included 256 BGA device MachXO 640 LCMXO640C 4F256C MachXO 2280 LCMXO2280C 4F256C Availability MachXO 640 version Available Now MachXO 2280 version Available Now On th
10. AE W Ole 13 2 gt s un 4 m al 1235456 28 5 3 oh j E oscillator LatticeEC LFEC20E 5F484C PCI interface SPI Flash Copyright Lattice Semiconductor 2006 Semiconductor Page 78 Corporation Bringing the Best Together LatticeEC Advanced Evaluation Board Features FCRAM on board DDR socket 5 14 2 interface RJ 45 interface PCI slot Multiple voltage planes SPI Flash on board SMA connectors for high speed signals clocks On board ext clock etc 6 2 ball device EC20 20 List Price 1295 ECP20 LFECP20E H EV List Price 1295 Availability Contact your Lattice Representative On the web PCI evaluation bitstream available FCRAM evaluation bitstream available DDR evaluation bitstream available User manual w schematics Copyright Lattice Semiconductor 2006 Semiconductor Page 79 LatticeEC Advanced Evaluation Board LatticeEC DDR Memory slot LFEC20E 5F672C SPI Flash Prototype area On board oscillator Ext Clock in RJ 45 x CAT 5 cable SPI 4 2 PLL PCI interface Voltage plane selection Copyright Lattice Semiconductor 2006 Page 80 Power Circuitry Lattice Semiconductor o
11. MATLAB Simulink ispLeverDSP Auto generates HDL from Simulink design ispLeverDSP Created HDL testbench matches Simulink testbench Design Entry and Featu res Simulation Subsystem parameterization Propagation of synthesis properties Logic Synthesis Datatype propagation without simulation Generate special modules using 5 LatticeECP2 ECP Pass parameters through hierarchy in Simulink Design Flow Tutorials and design examples Copyright Lattice Semiconductor 2006 5 Semiconductor 17 I O Assistant Method ispLEVER Process Flow for Planning Supports Early PCB Handoff Select Check Lock Pins Before Design is Complete Output to CSV Formatted File Comprehensive Design Rule Checks for I O Compatibility before Map Place and Route Module Generation for Complex Interfaces LatticeECP2 ECP EC XP DDR_GENERIC DDR_MEM LatticeSC DDR SDR DQS Copyright OLatticeSemiconducter 2606 4 F amp P 3 L F L F d d y PG 1 P wee Page 18 Block Modular Design Method ispLEVER Process Flow for Modular Design Team member A System Engineer TL G Copyright Lattice Semiconductor 2006 5 Semiconductor 19 Corporation ispLEVER Schematic Editor Block Diagrams Gate Level FPGA Library Import HDL Modules from RTL or IP
12. P3 1 1 wee Page 47 LatticeECP2 50 ECP2 12 in 5 1 Preliminary Timing LatticeSC15 25 and 80 Contact Lattice Web Interface Design Planner Easier and faster I O planning Advanced floorplanning and preference editing Schematic Library For FPGA DSP Design Enhancements Device support for ECP2 SC SCM EC XP and XO MATLAB Simulink reference designs Floating to Fixed point conversion tutorial Aldec Cadence and Synopsys simulators qualified Copyright Lattice Semiconductor 2006 Page 48 ispLEVER 6 0 Plus SP1 What s New Expanded Precision RTL and Synplify Controls TCL Format project files Easier report access Expanded tool controls CPLD Pin Export for OrCAD Capture Project Navigator Top Level HDL Schematic Module Selector Text Editor HDL Template Preview Power Calculator Command line interface Updated in SP1 to improve Precision RTL Synthesis 2005C Update 2 ModelSim LATTICE 6 10 Synplify for Lattice 8 6A Lattice xe er ho Thr Agenda ispLEVER Software Feature Overview ispLeverCORE Overview PAC Designer Software Feature Overview Development Hardware How to Learn More Copyright GiLattice Semicend ctgr 20061 4 4 Ci i E p E F L F d E L Y P3 1 L d gt Page 49 Soflware Orientation Pr
13. 8 bit switch and LEDs Lattice Semiconductor Corporation Bringing the Best Together LatticeSC Communications Board Features 300 pin MSA transponder for SFI 4 1 XSBI applications Molex VHDM interconnection for 5 4 2 200 pin DDR SODIMM socket SMA test points for high speed SERDES 4 channels 4 SMA each and Clock I O On board power control On board oscillator On board clock management Various high speed layout structures On board flash configuration memory Various LEDs switches connectors headers etc 900 ball device LatticeSC LFSC3GA25E 6F900C Availability Contact your Lattice Representative On the web Copyright Lattice Semiconductor 2006 Sem 74 User Guide and general info LatticeSC Communications Board SMA for SERDES 300 pin MSA LatticeSC FPGA SMA for clock DDR DIMM ji 1 HHOH rb d nh ispCLOCK and Power BE M e LA O a EL Tum ee Manager tt a ee E zzi x 5 5 E Ph E oS Fh Oscillator On board power control Copyright Lattice Semiconductor 2006 conductor 75 orporation Bringing the Best Together LatticeSC Standard Board Features X8 PClexpress edge connector form factor On board DDR2 Memory SMA Connectors for SERDES LVDS evaluation and ext
14. Complete Clock Net Design in 5 Steps 2 pris un y 8 a a E Output Type LVTTL LVCMOS33 SSTL 3 gt sipasap xw x Lattice PAC Designer Software lt E ConeoliedbySGATE LEE Lo om om 1 Specify EST LE CT m Interface and Susah E c op Divi d er 7 5 Print Summary aqu Report Apply these settings to output banks x n Ae Requested Accapinbig ES DOC MHz 1 1 gt SkewMode gt 133 333 l wi Dnadar Bugge ipul Da Frequency 8 55 557 01 MH 2 533 333 Dradaer I gt 256 666 M 1 3338 inm 4 adu 4 Download Design Configuration to CLK5520 for E Feedback Source x NM e x r WI Verification men Show lt is Ue Write ta amp chematc INTERFACE CEE ft Tm L Tas PRESE 2 Synthesize Counter From Tal Output Frequencies Banke om a m Pama 4 Banki
15. ran Dusi Logis 15 Chage Pure HWQUT3 HvDurs Source umen TEE n Dian Logs zZH ERR Chig Pump oan 1 1 oa 3 HOUTA HyGUT4 Sauce n5 P Dian Loses PAC Designer Design1 PAC Sequence Controller File Edit View Tools Options Window Help 0049 Sequencer Instruction Step Begin Startup Sequence ispPAC PWR1208 reset Step 1 Begin Shutdown Sequence lt end of program gt WHOM File Edit View Object Tools Options Jump PPP Bls 41 9 Insert a Sequence Controller Step 114 000 000 0 ns 0 40 000 000 80 000 000 120 000 000 mem 1 Wait for Boolean condition Cancel gGUGOUGOOUGOOUGOOOOOO __ __ _ _ _ IK IN Exception ID Boolean Expression Output for lt timeout y yuyu Cy iy y Cy ty yG CY Ch Gy Da Q Q RESET lt end of exception table gt ao Then Else DEV 1V8 OVERIV stem Program the Design Through JTAG 2 5 OVER2V4 m 3 Complete Sequencing Monitoring Design ed Using LogiBuilder 4 Verify Using CPU RESET step Waveform Simulator Lattice Copyright Lattice Semiconductor 2006 Semiconductor Page 66 Corporation Bringing the Best Together
16. Advanced Options NOM Attri bute In Register Retiming True _ Defaults Overnap device if design does nat Fit T F False Verilog VHDL Added to each IO register where retiming is not desired Help Double click the selected item ta cycle through possible choices or use the combo in the edit region for list of choices Online Help is available if you highlight the option and press F1 Lattice Copyright LaiticeSemiconductey 20007 4 E d P LF P F j waspa emiconductor on ee Page DT LS S SSE Gs RF EK S SE GST SE SER WS KS WS KS pO Corporati Nodal Control for CPLD Constraints Added to Critical Nodes to Increase fmax Decreases Levels of Logic gt Improves Fmax Limits PTERM usage Limits Fanin Takes advantage of XOR function File Pin Attribute Device View Window Help X Loc Grp Res De 2 hierarchical design 5ignall aroup Max pterm collapse Max_pterm_ split Max Fanin xor synthesis Fmax logic level Input Pins 1 Node reg8 1 reg q 0_ 1 0 Pins 2 Node 1 reg q 1 B ets 3 Node reg8 1 reg q _ 4 Node reg8 1 reg q 3_ 5 Node reg8 1 reg q 4_ v 4 gt Pin Attributes Nodal Constraints Global Constraints 4 Loading Lattice Constraint File C isptoolzs
17. Hacen you Sow Io use senti processes boi and posts the EVER sute to RTL er VHDL design n a device You wil prepare the deasga for Sema whom seio iming analysa and pwcement and routing you make prog ess Yus wi cossen the deson lp meet the signal and requirements of your wyslern casyn You wil modiy end conwhais the design lo leverage wichdectura scuro of the 2 Inthe HDL file instantiate the input and output DDR software primitives These primitives provide the 90 degree phase delay of the data strobe 005 with respect to the DDR data across process voltage temperature They also implement the DDR registers and adjust the system clock polarity to assure correct clock domain transfer in the registers device lo gve you hgh perfomasos The covers he commos procedure and wc you wil heve base of usderstending before you ce more Srmisg cri cw designs Mote nemert to meet your gerienmmance and us cation When you heve completed thes hilon ad you would Se alte lo do the Use ap EVER to create a new Veri p HDL of
18. How To interfaces capture data on both the rising and falling edges of the clock thus doubling the performance 22152 Semiconductor 385225 Corporation How to Achieve Timing Closure This How to topic applies to the LatticeECP EC and LatticeXP device families How to Design with syscLOCK PLLs More detailed information is available in technical notes on the Lattice website and 8 How To Design with syslO Buffers in the online Help These references are listed at the end of this topic E E LatticeEC FPGA Design with ispLEVER Tutorial How to Design with sysDSP The following steps briefly describe the typical flow for using the DDR to How to Set Configuration Options interface to a DDR memory device How to Use GSR PUR and TSALL for How to Use the Assistant 1 Using the Project Navigator create a project that targets a LatticeECP EC or How to Perform Logic Analysis LatticeXP device Design Tools Design Entry HDL Attributes Design Simulation Design Implementation Design Verification Device Programming For more information about connecting software primitives see 1050 Seana E ys LE LatticeECP EC and LatticeXP DDR Usage Guide ock Modular Design Step Guide Assistant Design Step G Tutorials and Examples Software Manug Troubleshoq Lattice Webs 4 Jisp TOO Ths tetera fer new ssar or a mat who uses EVER
19. Synthesis and Translation Build Database Physical Mapping Place amp Route Design 2 Map TRACE Report Static Timing Place amp Route TRACE Report Analysi S Copyright Lattice Semiconductor 2006 Migrating FPGA Designs FPGA Design Guide Chapter 2 FPGA Design for Altera Users Chapter 3 FPGA Design for Xilinx Users Replace Library Replace Specific Primitives in Source with Equivalent Primitives Replace Modules Replace Constraints with Preferences Optimize HDL Inferred Modules Copyright OLatticeSemiconducter 2606 4 F ER F L y PG Io 1 P wee Page 53 LatticeECP 2 Performance Advantage Fmax Index LUT Index 97 oo 9 100 98 80 0 60 50 40 10 20 0 EC 5 ECP2 7 Spartan3 5 Cyclone2 6 EC 5 ECP2 7 Spartan3 5 Cyclone2 6 130nm 90nm 90nm 90nm 130nm 90nm 90nm 90nm Average of benchmark designs using high effort Tools used ispLEVER 6 0 00 24 Synplify 8 5d OEM Xilinx ISE 8 1SP1 SynplifyPro 8 2 Altera Quartus 5 0SP1 SynplifyPro 8 2 Command line Map Place Route and Timing Report Machine used Pentium4 2 8 GHz 2 GB Windows 2000 ECP2 7 EC 5 Spartan3 5 Cyclone2 6 Lattice Copyright Lattice Semiconductor 2006 Semiconductor Corporation Page 5
20. Copyright Lattice Semiconductor 2006 Sem 57 IP Core Portfolio Downloadable Reference Designs www latticesemi com ispLeverCORE IP ispLever Lattice Semiconductor Corp ispLeverCORE Connection Partners CAST Digital Core Design DCD Elliptic Eureka Technologies Northwest Logic Copyright Lattice Semiconductor 2006 5 Semiconductor 58 Corporation ispLeverCORE IP Available for Purchase from Lattice Evaluation version available for download from the Lattice website Netlist or Source available Board or Site licenses Includes Description Features summary Configurations available User s Guide Evaluation capability Tech Note Brochure selected functions Where to Find the List of IP Available Search screen http www latticesemi com products intellectualproperty ispLever 43 Unique Functions Copyright Lattice Semiconductor 2006 5 Semiconductor 59 ion Reference Designs Available for Download from Lattice Website Free of charge Includes Description Features summary Configurations Available User s Guide Source Code Tech Note Brochure selected functions Demonstration design selected functions Where to Find the List of Reference Designs Search screen http www latticesemi com product
21. Design Tool Features Easy to use GUI SPICE model export Design Entry LogiBuilder Hierarchical design entry High level design entry power management Standard circuit generation library Design Utilities Clock frequency synthesis Graphical skew editing Frequency calculators Simulation Create stimulus graphically Digital Waveform simulation View both gain and phase plots graphically Simultaneously view inputs and outputs Cross hair cursors to directly read any gain or phase magnitude Facilitates Manufacturing Automation Library of automation functions Circuit board for different Example program and documentation Copyright Lattice Semiconductor 2006 Se du Page 65 Corporation VMENT HUME WMS VHNS YHINE Vea VMIONS VHMONTI VWI Analog Input 5e Complete Power Management Design in 5 Steps Lattice PAC Designer Software PAC Designer CPU FPGA Example PAC Schematic 10 File Edit View Tools Options Window Help 8 x 1 Set Power Supply Threshold For Each Analog Input 2 Set Power Supply Ramp Rate for Each FET Driver RIT 1 min esa asan Loge Duf 5 35455 m ias k Sp T E Sus Ek Source ZEE AT
22. HVOUT PULS UE VDD VOL J7 D 3 VDD OUT 5 8 IHvOuT 1 4 VDDINP VDDINP vooine ce P5 R4 R5 VMON QE 2 A wd VMON3 Q VMONA m VMONS U VMONG A VMON7 Up w Q VMON16 1 ct M HOUTA ap HVOUTS m LU d HVOUT1 IN2 uf INS T 2 DE d RESET VDDINP GND GND 2 4 sa tay COMPS COMPS COMPS COUPA COMPS COMP2 UW 1 POR I O access sa NE OUTS 7 OUT6 1075 RESET Eh a Vue 1 RZ C4 C2 Prototype area E RK K RK RK 0 K K KK K K E BRP KE RE K K KE W RO N amp KR KK K K K K K RK W L KA k K K K K K K T L R L K KK K RK RK K K K K K K K K K K K R K Rk RK K K K K K Kh LIL LLLI UR F eee amp LA KR K K R RK K K K K KRE eg AERE LE K K R K K KE OE K K K KR R K KK RIN K K 2 K KKR K K R K 5113 F r A I I K M KM 5 Lj y Sg F 222222 Semiconductor ispPAC PWR 1208 EVAL
23. LI PAC POWR1208P1 Programming interface Lattice Copyright Lattice Semiconductor 2006 Semiconductor Page 92 Corporation Bringing the Best Together Programming Hardware Cables Parallel and USB Compatible Programming Cables Model 300 Desktop Programmers Programming Adapters _ s 1 i do Copyright Lattice Semiconductor 2006 Page 93 Agenda ispLEVER Software Feature Overview ispLEVER Versus the Competition ispLeverCORE Overview PAC Designer Software Feature Overview Development Hardware E Semiconductor Corporation Copyright Lattice Semiconductor 2006 Page 94 Web Site Content Your Account b Your Account Home Products Solutions Support Documents Downloads Sales Corporate j 2 implement Advanced Implementation Tools x gt Design Software CPLD and FPGA Design Software In Detail ispLEVER includes a full suite of tools 22 Subscribe to this page at give you as much control over the In Detail ispLEVER Design Software that gi h control th P ispLEVER Starter i Flash Demo P ispLEVER implementation of your design as you a Explore design softwar E want or need All of these tools are optional If you prefe
24. Pe i i Banke abit Rw gt Tu E Bankga 58 Banke 1 attic 3 Graphically em gt ce Adjust Skew ispPAC CLKSS20 EV1 E TM Each Clock Output LJ E c Enna 0 Tu 1BTU Cana Bankai kt li ILE Sm dm uss ge gt Copyright Lattice Semiconductor 2006 Semiconductor Page 67 Corpor Dnran Han Bringing the Best Together Agenda ispLEVER Software Feature Overview ispLEVER Versus the Competition ispLeverCORE Overview PAC Designer Software Feature Overview How to Learn More E Semiconductor Corporation Copyright Lattice Semiconductor 2006 Page 68 Evaluation Boards Wide Range of Evaluation Boards LatticeSC ECP2 ECP DSP EC XP XPGA FPGAs Lattice MachXO Crossover PLD Lattice ORCA FPSCs ispMACH 4000 ispXPLD CPLDs ispPAC ispCLOCK ispCLOCK Evaluation Board GND LI i Lt 1 Er 23 Pe AME L i 5 z z z z attic z L ON
25. Power Calculator and power consumption Simulation data VCD import Configure power supply requirements Verify Function Timing and Power Copyright Lattice Semiconductor 2006 LEETE ductor Page 34 Corporation Bringing the Best Together isoLEVER Design Flow Verification Tools for Device and Board Level Design Analysis Static Timing Analysis STA Preference driven STA tCO tH Multi cycle Timing exceptions Timing Simulation Functional verification based on switching vectors to check for timing violations Logic Analyzer Embedded logic analyzer with external probe points and triggers to capture internal otherwise unobservable signals Power Estimation Accurately models device power consumption so that board power budgets may be checked IBIS Modeling Signal integrity models to perform board level evaluation of noise and crosstalk generated on board level traces Copyright Lattice Semiconductor 2006 Semiconc 35 die Corporation TRACE Report Static Timing Analysis TRACE Timing Report and Circuit Evaluator Check Physical Design Delays Compares Against Timing Preferences Issues Timing Errors if Delays are Exceeded Used in Pre Route and Post Route Design Phases TRACE Timing Checkpoints May be Set This ts done in Pro
26. for application Power Calculator from file nipublic accessischnettleridesiqnsitop level schematicterilog hierarchical designtverilog hierarchical design ncd se test is an NCD version 3 0 vendor LATTICE device LFEC1E package QFP100 speed 3 Loading device for application Power Calculator from file ep5g15x18 nph in environment CvispTOOLS5_0 Build42 ispfpga Package Version 1 9 Status PRELIMINARY Speed Hardware Data version 1 119 Finish loading n public accessischnettleridesignsttop level schematiciwerilog hierarchical designwerilog hierarchical design ncd Status preliminary Lattice Semiconductor Corporation Bringing the Best Together ModelSim LATTICE ModelSim RTL and Gate Level Simulation VHDL and Verilog Language Support gt However mixed languages NOT supported gt Customer must buy mixed language support De facto Standard for FPGA Design NO RTL Line Limit in the Lattice OEM Version Very good performance Included With ispLEVER Windows Package isoLEVER Automates File Creation Makes the simulation easier to set up and use Copyright Lattice Semiconductor 2006 TETT Page 40 ModelSim Integration Simulation related File View Source Process Options Tools Window Help Jeze processes BB Df lu gr r mm al xl Processes for current source d Verilog Hierarc
27. the tools Analysis all Lattice programmable products in system Lage features of ispLEVER Accessible via the Analysis preference editor and or ORCAstra Provides a graphical interface that allows Features and Tools floorplanner tools this s 5 What s New M configure many Lattice programmable devices during lis spLEVER Project Management intuitive GUI helps you Device is intended to speed the design iteration process by lett CAF Support Min perform tasks such as Programming try various device settings on the fly Design Entry IspLEVER HDL deat drag and drop 1 0 Dacumants L Synthesis UNES gt 20 assignments identify Software archive Check here for information and 40 pamnloads dA specific I Os and visually picture how the pins for older versions of Lattice developrnent tools M ncs Mur E ispLEYER ispLEVER Donnisadabls EA Simulation Advanced programmable and Analysis Implementation logie Toole Optimize Your Ordering Designs with General Information ispLEVER Gunes Wanderers iaspLL YLH Device In system Logit Unix LEAD Programming Analysis Lease Product Brochures L _ u the anline k Release Notes whore SPICE Find your boral sales selector Guides represent ative Lattice Semiconductor Cor
28. webcast and learn how to design with an 8 bit microcontroller opefi IP core solution that is Safe to Use gt Flexible Easy Silicon Efficient Home Corporate Webcasts Address ei http www latticesemi com corporate webcasts embeddeddesignswithopenip cfm gt Go Links Copyright Lattice Semiconductor 2006 Page 97 Lattice Semiconductor a Corporation Bringing the Best Together Conclusion Complete Solutions for All Your Needs Powerful Full Featured Solutions Easy to Learn and Use Only Lattice s Design Tools Offer Leading 3 d party tools Performance leadership The best software prices and value PAC Designer Mixed Signal Design Solutions A Complete Library of ispLeverCORE IP Complete Programming Hardware amp Software Evaluation Boards FPGA FPSC CPLD Mixed Signal Devices Copyright OLatticeSemiconducter 2606 4 F P j L F L F d d Io 1 P wee Page 98
29. 4 Bringing the Best Together LatticeSC Family Performance Advantage Fmax Index 100 80 60 40 20 0 SC 7 Virtex4 12 Stratix2 4 90nm 90nm 90nm Average of benchmark designs using high effort 100 80 60 40 20 100 LUT Index SC 7 90nm Virtex4 12 90nm Stratix2 4 90nm e Tools used ispLEVER 6 0 00 24 Synplify 8 5d OEM Xilinx ISE 8 1SP1 SynplifyPro 8 2 Altera Quartus 5 0SP1 SynplifyPro 8 2 Command line Map Place Route and Timing Report Machine used Pentium4 2 8 GHz 2 GB Windows 2000 ECP2 7 EC 5 Spartan3 5 Cyclone2 6 Copyright Lattice Semiconductor 2006 Page 55 Lattice Semiconductor Corporation Bringing the Best Together Conclusion Complete Solutions for All Your Needs Industry Leading Synthesis and Simulation Tools From Mentor Graphics and Synplify Easy to Use and Easy to Learn Familiar Flow and File Extensions Unsurpassed Performance and Productivity Industry s Best Value Ep LEVEL pLEVE The Simple Machine for Complex Designs Copyright OLatticeSemiconducter 2606 4 F E F P y PG 1 P wee Page 56 Agenda ispLEVER Software Feature Overview ispLEVER Versus the Competition PAC Designer Software Feature Overview Development Hardware How to Learn More
30. 4 2 ispcpld examples LatticeEC veriloq verilog hierarchical design teady MUM Copyright Lattice Semiconductor 2006 Page 32 Semiconductor Corporation Bringing the Best Together EPIC Device Editor Tools for Device and Board Level Design Analysis ioj xl File wiew Layer Tools Help Make Changes to NCD E and route critical components before PAR Place and route critical signals after PAR Manually complete unrouted signals Perform Physical DRC Examine TRACE results Route buried signals to unused pins Copyright Lattice Semiconductor 2006 5 Semiconductor Tr 79 Corporation Simulation and Analysis ModelSim for Lattice VHDL Verilog SystemVerilog language simulation IspLEVER Praject Tight script based integration Management Pre compiled Lattice device library resources Mentor Graphics Questa support available HDL Synthesis Timing Report and Evaluator Constraints driven Static Timing Analysis STA una Supports multi cycle relationships and timing exceptions heals Performance Analyst Simulation and Easy to use tabular view for static timing analysis
31. A results Copyright Lattice Semiconductor 2006 Semiconductor Page 37 Corporation Bringing the Best Together Mentor Graphics ModelSim Timing Simulation Critical for Checking Design Function as Signals Switch During Operation Tests dynamic input vectors and validates against expected output Critical for finding setup and hold time violations ModelSim is De facto Standard for FPGA Design BIMPLICI SIMPLICI FINITIAL INITIAL BINITIAL 32000 45 33001 46 93201 47 34000 47 35001 47 35201 48 85000 48 37001 48 37201 43 38000 43 33001 43 33201 50 tt tt tt tt tt tt tt tt tt tt t 59 gt Now 1us Delta Copyright Lattice Semiconductor 2006 Page 38 Instance Design unit Design unit type acc lt fu x tcounter ln test_counter Module 1 ff Module tacc lt fu 2 Copyright Mentor Graphics Corporation 2004 test_counter Process 3 test counter Process 4 11 Rights Reserved test counter Process 2 ZZ THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH D x ET INI 4 jtest counter clk fi 4 test_counter reset 0 test_counter count 00110010 GSFC FSGS GSES SSCS 4 7 50 4 AXE Now 1000 ns Cursor 1 ns 11 B 2
32. AST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST FAST DOWN DOWN CORAN DOWN DOWN CALA uP up up up up up 4 Pin Attributes Cell Attributes Global Constraints Block Period Frequency In Qut Clock Multicycle pug 2 OFF OFF OFF OFF OFF Hy himrarGhical dwsign pri bone NUM FREQUENCY NET 11 nclk 133 000000 MHz FREQUENCY NET 11 mclk 133 000000 MHz FREQUENCY NET clk c 133 000000 MHz FREQUENCY PORT clk 133 000000 MHz DEFINE PORT GROUP group dq ddr dq 0 CLO CK TO OUT GROUP group dq 10 000000 ns CLKPORT clk PROHIBIT SITE EBR 19 10 PROHIBIT SITE EBR R19C8 PROHIBIT SITE EBR R19C6 Lattice Semiconductor Corporation Bringing the Best Together Design Planner Spreadsheet View Define Types Pin Assignments Power Options Signal Groups Timing Objectives Multi Cycle and False Paths Excel Like Features Sorting and Pin Type Filters Context Sensitive Menus Fill Up Down Editing CSV export ASCII Data Reports 3 Party Schematic Symbols Copyright O Lattice Semiconductor 2006 Page 28 Group Members GLB Macrocel Pin Power Types Sort by Types f Ascending 2 Descending Then bu Ascending GLE f Descending The
33. Control Ul Save and restore process state and related files Advanced Implementation Tools HTML Reporting and Help Hyperlinked navigation and search of reports and help simuiation ana Analysis TcI Tk Tools Record and playback process sequences cioe iN In system Logic Analysis Organize Design Files and Processes Lattice Copyright 200027 4 E d P LF P F L et Se ondu ictor Page 12 i ispLEVER Project Navigator ispLEYER Project Navigator CispTOOLS5 0 verilog hierarchical design syn File View Source Process Options Tools Window Help gt Normal o s f She Sources Project Processes For current source 5 Verilog Hierarchical Design lt Build Database Toolbar Documents lt Pre Map Logical Design Floorplan E LFEC20E 5F672C Pre Map Preference Editor verilog hierarchical design tb tf Design El verilog hierarchical design verilog_hierarchic Map Report hierarchical design mrp So verilog_hierarchical_design v Map TRACE Report verilog_hierarchical_design tw1 Post Map Physical Design Floorplan El m regs Areg amp lreg8 v lt Edit Preferences WI n d OW 8 e Map T
34. DSP Frinting Topics Updating ispLEVER ff 205 FPGA Design Flow for Xilinx Users Contacting Lattice Se Search the Lattice 05 Migrating Xilinx Spartan Designs to LatticeEC ECP DSP Lattice ISpLEVER Software for Xilinx ISE Users 03 Project Setup Management HEIL What s New at Lattice FPGA Flow ispXPGA Flow ispXPLD Flow Da CPLD Flow Programming and Logic ispGDX Flow Design Entry Analysis Tutorial How T HA Design Implementation Software User Manuals Third Party Manuals Example Projects On the Web Simulation Timing Analysis 03 Frogramming amp Configuration On Chip Debugging Lattice DIDI Design Guide ispTOOLS5 process flow help htm Tutorials FPGA Design Guide Migration Advice Hardware Feature How To Guides It s Easy to Get Started Copyright Lattice Semiconductor 2006 z Semiconductor Page 8 Corporation Bringing the Best Together Help Tutorials and Design Advice Jispleverdsp tutorial pdf application pdf Object Mozilla Firefox File Edit View Go Bookmarks Tools 5 1 ispepld tutorial ispleverdsp tutori 9 Go HTML based Help 2 60 FPGA Design Guide Tutorials Index amp Search Opt
35. LEVER Design Tools Products SPLD GDX 2 CPLD Precision RTL Synplify ModelSim License Part Number MachXO FPSC Synthesis Synthesis Simulation Eval Board Type LatticeE CP2 50 LatticeE CP2 12 Downloadable All All LatticeEC Yes Yes Node Locked All LatticeECP LatticeXP3 XP6 Floating License Upgrade LS FLOAT PC Floating for Windows ispLEVER for Windows Copyright Lattice Semiconductor 2006 Semiconductor 6 Corporation Bringing the Best Together ispLEVER Easy and Quick to Learn Highlights FPGA Design Guide gt Migrating Xilinx and Altera Designs Synthesis Guidelines Timing Closure Advice On Chip Debug Overview Numerous Design Tutorials HTML Based Help Topics with Hyperlinks to Lattice Website Online Help Organized by Lattice Device Category FPGA CPLD etc and Design Tool Power Calculator Design Planner etc FAST Search Copyright Lattice Semiconductor 2006 5 Semiconductor 7 ion Rich Educational Materials File Edi View Go Bookmarks Tools Help Back Forward Reload Stop Home file c fispTOOLSS ispcpld webhelp flow flow Lattice Contents Index Search Glossary 2 IspLEVER Process Flow Help 405233 214 System Design Using Using Help Hel _ ispLEVER Help Organization Pp ispLever
36. Lattice Semiconductor Corporation Design Software Intellectual Property Development Hardware Includes ispLEVER FPGA CPLD Devices ispLeverCORE IP PAC Designer Power Manager and ispCLOCK Devices Development Hardware Evaluation Boards Copyright Lattice Semiconductor 2006 Sem Page 1 p ag ispLEVER Overview Comprehensive Design Solutions Easy to Learn Familiar Flows LED 2 the Tools Required The Most Choice Best Performance Designs Best Value Best Programming Tools Copyright OLatticeSemiconducter 2606 4 F P i j L F L F d y PG Io 1 d 1 wee Page 2 Agenda ispLEVER Versus the Competition ispLeverCORE Overview PAC Designer Software Feature Overview Development Hardware How to Learn More Copyright Lattice Semiconductor 2006 Semiconductor 3 ispLEVER Digital Design Tools i 1 modules gt IP Cores MATLAB lt i ispLeverDSP Simulink 60 blockset functions Modules ModelSim integration iso TRACY LA core integration Text Editor Schematic Editor Waveform Editor Mentor Graphics ModelSim 39 Party Simulators Design Entry and Simulation Power Esltimation Power Calculator Power estimation Free form utilization or design VCD import Logic Synthesis Design Planning Mentor Graphics Precision RTL Synpli
37. TO12 INST nnn 012 INST 22 mmn 2 INST is nnn ci Trace Mode Post Synthesis EDIF E Sample After Trigger Samples Per Trigger integration of IP cores EVO is defined as Trigger Bus Pattern 0 m m 1 Samples 1 255 Multiple device analysis Mo Contiguous Trigger Condition C For 0 Improved signal markers New TRST settings E p Trigger setup Copyright O Lattice Semiconductor 2006 Page 44 D 5 8 5 F E evi 2 Zl F Zl Trigger Output Polarity nn ispTRACY Logic zer c isptracy jtagconsole deve bi File Bus Signal Data Device Window Help gt nnn Device0 LAO Trace Width 40 Trace Depth 512 Trigger vvidth 8 nnn cc Tigger Setup Event Patterns Signal Analysis EV1 is defined as Trigger Bus Pattern_1 1 Samples 1 255 Mon contiguous Contiguous Semiconductor Corporation Bringing the Best Together CAE Tool Support Tools ModelSim ModelSim for Lattice Synplify for Lattice Precision RTL Synthesis for Lattice Key 3 Party Interface Options MathWorks MATLAB Simulink cadence Mentor Graphics Questa Sim Cadence NC Verilog Sim The MathWorks SYTIUPSYS Synopsys VCS Sim 3 Party Options _ Ald
38. amp Route Timing driven map place and route Easy to configure GUI or command line driven Easy to Control and Optimize Copyright Lattice Semiconductor 2006 Page 25 IspLEVER Praject Management Design Entry HDL Synthesis Advanced Implementation Tools Simulation and Analysis Device Programming In system Logic Analysis Lattice 26 er i Timing Closure Design Flow Timing Closure Tools Aid In Tuning Design Performance 1 Set Controls To Achieve Timing Goals HDL Source gt ispLEVER Preferences gt Floorplan gt MPAR gt Static timing analysis 2 Analyze Critical Paths 3 Modify Constraints and Options 4 Herate As Necessary Copyright Lattice Semiconductor 2006 5 Semiconductor EELE or ion Page 26 ispLEVER Preference Language The Nexus Between Design and Performance Flexible ASCII Language for Timing Driven MPAR and STA Graphical Spreadsheet Like UI Entry Easy Assign Globals Period Frequency I O Timing Timing Exceptions k Premia Preterence Editor CtuispTODLSA E Fe Gece s Window K oe op verilog hierarchical design a nput Ports Bale mAJ 1 22 8A Ea 3 A20 19 Ais Ea 6 Ai 7 A15 b 08 A16 Bb 1 14 2 8 A13 Bb3gA12 Eb 5 1 i
39. b 6 AS Bb amp AB E dk AS AG E rst 4 E col Outpul Ports B 4 7 0 6q_08 2 Ba 50 55 Baten Group __ Members Misc milosding device for application bssnpdevice rom lile epogijr5 nph im environment 4 Loading Lattice Preference File Ci imspTO pre map PE is congected to Dispatcher 7 Input Port 8 Input Port 9 Input Port 10 Input Port 11 Input Port 12 Input Port 13 Input Port 14 Input Port 15 Input Port 16 Input Port 17 Input Port 18 Input Port 19 Input Port 20 Input Port 21 Input Port Wr b h h 4 b3 b_ b_i bo a a a 22 Output Port 47 23 Output Port 4 6 24 Output Port 45 25 Output Port q 4 26 Output q 3 27 Output 42 28 Output 1 OLZ4 2 39 Prod nager izpcpld d axamples LatticeECvo BG Copyright Lattice Semiconductor 2006 Page 27 1 _31 _ Cer hierarchical pef LvCMOS12 LEMOSI Z 2 LVCMOS14 LVCMOS 1J LEMOSI LVCMOS12 LVCMOS12 LyCMOS12 LvCMOS12 LVCMOS12 LVCMOS12 LVCMOS12 LVCMOS 12 LVCMOS12 LVCMOS12 LVCMOS12 LVCMOS12 LVCMOS12 LVCMOS12 sp pga 6 6 5 6 Loe log hierarchical designe ril FAST FAST F
40. casts incrementalmodulardesignm index cfm gt Go Links ES Embedded Designs with Open IP Cores Microsoft Internet Explorer 551151 Corporation File Edit View Favorites Tools Help Back gt 9 QSearch Favorites Media 542 4 c Home Products Solutions Support Documents Dow Incremental and Modular Design Meth Lattice Semiconductor Corporation The original event was broadcast on Your Account Date Tuesday February 7 2006 Home Products Solutions Support Documents Downloads Sales Corporate Embedded Designs with Open IP Cores e Q Register Today Overview Free Webcast High density FPGA devices and the applications that target them nd more and more require devide and conquer approach to design this presentation Lattice Semiconductor examines incremental and modular design methods that help solve problems facing multi designer development groups and allow easier collaboration more predictable design results and faster design cycles Have you wanted to use Open Source IP for your FPGAs but were nervous about licensing complications Learn how to use Lattice s new and innovative open IP core license during this fre WWW aan Register Now The original event was broadcast on Tuesday September 13 Legal Privacy Policy Contact Uy Attend this
41. city Synplify Design Planner Timing Driven Timing Constraints Map Place and Route Package Pin Floorplan View TRACE Path Tracer Performance Analyst Gtatic Timing Analysis ispVM System SPI Embedded uP support Preferences Additional Design support Device Programming Project Manager Revision Control HTML Reporting e isp TRACY Logic Analyzer Embedded LA core HTML Help CSV pin export IBIS model export On Chip Logic Analysis Verification Copyright Lattice Semiconductor 2006 Semiconductor TT 440114 4 1131411134 1 Corporation Bringing the Best Together ispLEVER Overview Two simple software configurations ispLEVER Starter is a modular download from Lattice s website After 6 months software is non operational IspLEVER includes all devices and 3rd party tools Windows 695 US List Price Contact your local Lattice Distributor or visit the Lattice online store for offers ispLEVER includes Industry Leading 39 Party Tools Competitors do NOT Synplify and Precision RTL synthesis ModelSim simulation isoLEVER includes MATLAB interface for DSP design Competitors do NOT ispLEVER includes logic analyzer for on chip debug ispLEVER Available for Windows Linux and UNIX age 5 Corporation Copyright Lattice Semiconductor 2006 TL isp
42. e SCHEMATIC edf ORCA Preference File Critical path 51 Transcript B Design De Tech nology view Ready Input Directory precisian_ rtl tutors Copyright Lattice Semiconductor 2006 Page 22 GT Lattice E Semiconductor Corporation Bringing the Best Together Precision RTL Synthesis Mentor s Latest Synthesis Tool Much better fmax and area utilization than LeoSpec Performance very close to Synplicity s Synplify More user friendly than LeoSpec No Differences vs Mentor s Full Up System Fully Integrated in ispLEVER Includes Schematic viewer RAM inferencing ROM inferencing Register retiming Copyright OLatticeSemiconducter 2606 4 F P L F Po P d d P3 Io 1 1 wee Page 23 Synplify for Lattice Synplicity s RTL Synthesis Tool OEM Version for Lattice Included With ispLEVER Synplify Pro support now Copyright Lattice Semiconductor 2006 Page 24 Implementation Tools Design Planner Spreadsheet View Excel like Ul to define timing and location Preferences Package View Ideal for planning and PCB documentation Floorplan View View placement critical paths congestion and groups Path Tracer Highlight critical paths Pin CSV Export EPIC Device Editor Powerful device database editor for ECOs Place
43. e way from concept to firished product ispLEVER includes x complete set of powerful tools for all easy to use and power graphical interface that helps you quickly customize your design preferences Tasks such Documents amp HDL Synthesis Downloads T ispLEVER CPLD and FPGA design software providing the ispLEVER tools augn baiki bragect defini imi management IP device as defining timing Advanced Other Lattice Software Products HDL Synthesis mapping piace and route in zyrte constraints frequency period I O timing implementation PAC Designer Intuitive software to facilitate design a Advanced logie analysis and more assigning I O types setting global attributes Tools Teal defining PLL specifications and more can ispLEVER Windows also includes industry leading Jrd party tools from our partners Synplicity and development with Lattice s programmable analog device 5 x P prog 9 easily be accornplished at various stages in analai and the design process isp M System ispvM System is Lattice s device progr AR Furia giis management software tool isp M System is included Graphics far Synthese and Simulation Packade View Simulation and ispLEVER options or available as a stand alone tool isp 9 7 lt 3 Programmeng Click the block diagram below to learn more about
44. e web User Manual and sample program Lattice Copyright Lattice Semiconductor 2006 Sem 87 MachXO Standard Evaluation Board JTAG programming MachXO Device I O access LCD Panel LCMXO640C landing 4F256C _ DE E R J CELEJ i we tees Wa m s g Je m BOR B K E K B K H K b 1 E 1 Fi S m H 1 HE lt T DT me ispClock 5610 4 HIE s 53222555 FREER IIIS T W Si a En K m supply circuitry On board Push button oscillator 8 bit input Switches Prototype area switch 8 I O LEDs Lattice Semiconductor Corporation Copyright Lattice Semiconductor 2006 Page 88 _ Bringing the Best Together PAC CLK5620 Evaluation Board Features General purpose header for user SMA connectors to selected high speed I O signals LEDs for status indication Switches for added flexibility JTAG interface 100 TQFP device ispPAC CLK5620V 01T100C 20 outputs 100 pin package Board Only PACCLK5620 EV List Price 225 Development Kit PAC SYSTEMCLK5620 List Price 295 gt Kit Includes PAC Designer software amp Download cable Avai
45. ec Active HDL Capture and Sim 7 Aldec Riviera Sim Altium Altium Nexar Capture and Sim Outstanding 3 Party Support Copyright OLatticeSemiconducter 20061 4 F P 3 L F L F d d P3 Io 1 P wee Page 45 PCB CAD Tool Support Lattice Model Resources 1815 Buffer Information Specification gt EDA tools Mentor Graphics HyperLynx Zuken etc Signal integrity SI simulation lt 1GHz SPICE Signal integrity SI simulation gt 1GHz Requires factory NDA and Synposys HSPICE BSDL Boundary Scan Description Language Boundary scan chain models describe devices in a JTAG compatible scan chain ispLEVER File Exports Comma Separated Value CSV pin reports EDA tools OrCAD Protel etc Design specific IBIS export OrCAD Capture CPLD pin reports Outstanding 39 Party Support Lattice Copyright LaiticeSemiconductey 200027 4 E Pb LF FP F OS DO PG et Se ondu ictor Page 46 dh M IBIS Model Generation Design Specific Signal Integrity Model Uses a base template IBIS model for each family Generates specific model of user s design based on resources used Useful For Board Level Signal Integrity Verification Crosstalk Noise Signal loss over long traces Copyright OLatticeSemiconducter 20061 4 F P L F L F d d
46. ecision Synplify Synplify pene RTL OEM Pro Design Entry HDL Synthesis Verilog Advanced SystemVerilog Tools Constraints Editor Simulation and PAR Analysis Integration i Device RTL Technology View Programming In system Logic DSP RAM ROM Inferencing industry s Best FPGA Synthesis Copyright O Lattice Semiconductor 2006 Lattice mmnm Corporation Bringing the Best Together Precision RTL Synthesis for Lattice scompare Mentor Graphics Precision RTL Synthesis File View Tools Window Help WEAN summis Center s Lattice LaticeEC LFECTE 3 0 Frequency Fraject Files Design Project Design Design Analysis E DATOS gt 01 0 Schematic i Project compare eT 2 ispLEVER ORCA Ea Impl compare impl 1 E 4 SEL 0 COMP EG m 51 423 Input Files ax 5 NOCO en o 9 0 RST UM 113 0 COMP GT BO 0 gt x IMO X D 01 Launc 3 3 0 Script Files LT 0 Macro Files B Output Files Log File Infos 3 RTL Schematic Technology Schematic Area Report 1 Timing Report Integration Timing Violation Report pe Re Net Information Report Rr RTL Constraints Report be Ri Tech Constraints Report Missing Constraints Report b
47. ernal clock BNC edge connectors for Digital Video Interface On board Flash configuration memory ree LEDs switches connectors headers and on board power contro 1152 ball device LatticeSC LESC3GA80E 6FF1152C Availability 3Q 2006 On the web Related info coming soon Copyright Lattice Semiconductor 2006 Sem 76 Corporation LatticeEC Standard Evaluation Board Features PCI connector oscillator socket ext clock 1 2V amp 3 3V on board power banana jacks also available SPI flash on board Pads for high speed SMA connectors not populated 484 ball device EC6 LFEC6E L EV List Price 149 EC20 LFEC20E L EV List Price 175 ECP20 LFECP20E L EV List Price 175 Availability Available Now On the web evaluation bitstream available Note there are both Rev A and Rev B PCBs each has unique user manual schematics Copyright Lattice Semiconductor 2006 Semiconc 77 die Corporation LatticeEC Standard Evaluation Board Prototype area vio Power Circuitry O K K T E NM ANA T i LI i M _ gt SMA Pads Clocks PLL A NM KR KR LM NM EN E ZEN R R K KRK R m E IL
48. express VHDL or Verilog HDL Export Schematic related processes D gt Normal M yo E E zh f vx Text Editor rotateVrotate v xui E Edit View Templates Tools Options Window Help ispLEVER Project Navigator verilog hierarchical design syn Sources in Project Processes for current source B Verilog Hierarchical Design Navigate Hierarchy BEC 21 8 Documents Generate Schematic Symbol module rotate q data clk l rst ZZ rotates bits or loads LFEC1E 3T100C Verilog Functional Simulation Model Ey verilog hierarchical design tb tf Verilog Test Fixture Declarations Dd BIRD ros 2 se test se test sch VHDL Test Bench Template reg 7 0 q 21 mux mux mux v 4 reg8 reg8 reg8 v rotate rotate rotate v when 1 is high it rotates if low it loads data always posedge clk or posedge rst begin ri 5 LE rst 8 Verilog Variables 65 else if 1 i q q 6 D q 7 2 Schematic Editor SE TEST Sheet 1 q data Delal S 220 zie Ln 1 Col 1 20 WR Rec Off No wrap Revision Controls lt Select A Command 005 INS NUM Document 1 of 1 Lattice Semiconductor Corporation Bringing the Best Together HDL Synthesis Simply Better ispLEVER Project Pr
49. ging the Best Together Project Navigator Project Wizard Project Wizard Project Narne Untitled r C Location Design setup 60s Schematicv4BEL Schematic HOL VHDL e Wizard Choices Select Device Device Information Name the project Dee EDIF LFECBE Density Select project type Select device Project Wizard Add Source Add Source Source verlag hierarchical design Module mu Module Select source files When Finished User Is Designing CU Look in C rotate mem E rotate t tf Import Source Type File Name Motate rotate v Type of Source Cancel Verilog Module Help Verilog Test Fixture Copy Source File name Files of type lt Back gt Cancel Help Lattice Copyright Lattice Semiconductor 2006 Semiconductor Page 14 Corporation Bringing the Best Together Design Entry Tools Browse configure and generate IP cores HDL Text Editor Keyword highlighting for HDL and other native files MATLAB Simulink DSP Blocks DSP function blocks tailored for Lattice devices I O Assistant method Flow enables early PCB handoff Comprehensive design rule checks Block Modular Design method Parallel development of sub modules Non invas
50. hical Design Verilog Functional simulation 9 Documents x Verilog Post Raute Simulation erus 3FB72C Verilog Post Route Timing N Ek Revision Controls OFF N N N N N ON N N LATTICE 6 0 Custom Lattice Version File Edit Compile Simulate Add T hierarchical asign v _t tf Debugging views e rega wv EL ttt D rotate Arotate atate v X Um EA Wotatewotate ttf verlag Variables INCLUDED FILE View Format fee Ob 01 Lf 000 ns Cursor 1 ns ri mimi ui wave F x Finished recording TCL s starting C ispIOO0LS5 Original vlog2jhd tfi Done generics Precompiled Verilog VHDL Now 131us Delta 0 sim verlog hierarchical design TAEIMPLICIT ANTIREQC BS Lattice Copyright Lattice Semiconductor 2006 Semiconductor Corporation Page 41 Bringing the Best Together Device Programming Supports Lattice Devices IEEE 1149 1 in system programming SPI Flash programming support s TransFR support Design Entry Multiple programming format support ISC 5 SVF IEEE 1532 etc HDL Synthesis Format translatio
51. iming Checkpoint gt rotate rotatelrotate v Q Place amp Route Design Arotatelrotate Place amp Route Report verilog hierarchical design par Variables PAD Specification File verilog hierarchical design pad 59 INCLUDED FILE Place amp Route TRACE Report verilog hierarchical design twr Post PAR Preference Editor I O Timing Report verilog hierarchical design ior Performance Analyst HTML Place amp Route Report verilog hierarchical design htrnl Reentrant Route Design lt Post PAR Design Floorplan EPIC Device Editor Dockable Windows IBIS Model Memory Initialization R I A a C j Place amp Route Timing Checkpoint O r 5 x S Revision Controls OFF gt ispLEVER Log File 4 4 Revision Control Starting C ispTOOLS5 1 ispcpld bin checkini exe Done completed successfully Starting C ispTOOLS5 1 ispfpga bin nt lci2prf ex Done completed successfully Automakelog Tl x Lattice 22 57 Semiconductor orporation b Your Account N Products Solutions Support Documents Downloads Sales Corporate What s New at Lattice LY Y 4 Design Entry Schematic Verilog HDL Synthesis Type Precision 2 Lattice Copyright Lattice Semiconductor 2006 Semiconductor Page 13 Corporation Brin
52. ions A System Design Using ispLeverDSP 04 Introduction D Lesson 1 Building a Simple Mode Lesson 2 Building a Complex arporslion System Design Using ispLeverDSP File Edit Go Bookmarks Tools n ispLEYEK gt D xj lt gt Lg M X FileJ c fispTOOLSS 1 ispcpldjtutorial Fpga design tutor pdf Y File Edit arks Tools Help Qa Y 1 55 1 ispcpld webhelp flow mergedProjects fpga Y Q Go e Options gt x 4 3232 es Bookmarks Contents Index Search Glossar How to Use Dedicated DDR Memory Support Release Compatibility Notice DS LatticeEC FPGA Design with ispLEW Learning Objectives DS Time to Complete This Tutorial F System Requirements 5 Accessing Online Help About the Tutorial Design About the Tutorial Data Flow B Task 1 Create a New or V H Task 2 Assign Location and Timir Task 3 Design Synthesis and B Task 4 Place Route and Post Re 8 4 Task 5 Viewing the Device Implerr J Task B Improving PAR Results F LatticeECP EC and LatticeXP devices support various Double Data Rate DDR Pip interfaces using the logic built into the Programmable PIO The DDR
53. ive incremental design Schematic Editor Hierarchical block diagram editor ntegrated FPGA libraries ABEL for CPLD and SPLD Copyright Lattice Semiconductor 2006 Page 15 IspLEVER Praject Management Design Entry HDL 5ynthesis Advanced Implementation Tools Simulation and Analysis Device Programming In system Logic Analysis HT IPexpress IPexpress USER CONFIGURABLE Cockpit for Parameterization of Lattice IP Core and Modules View IP cores available for download Configure and manage IP cores Only device compatible cores made visible Module Generation Memories Common digital macro functions sysCLOCK PLL and DLL DDR interfaces Evaluate in Hardware Includes hardware timeout circuitry 111 d 4928 TIERE TE x Very Easy For Users No intimate architectural knowledge required Copyright Lattice Semiconductor 2006 Lattice Rage la tf 4 1114 113149 ispLeverDSP MATLAB Simulink Interface The MathWorks MATLAB de facto standard language for math functions Simulink graphical design editor for DSP design MathWorks Partner Lattice Simulink Blockset Common DSP function blocks Total of 60 blocks
54. ject Navigator Saves processing time by checking before long processing runs TRACE Report Provides Design statistics Timing errors and warnings and their associated nets Number of paths analyzed and percent coverage Paths that cannot be analyzed Copyright Lattice Semiconductor 2006 Sem mm muu Performance Analyst Static Timing Analyzer Analysis options AGE Performance A nalyst Static Timing Analysis Looks at path delays without for signal switching Facility for identifying condire critical paths View Met Control Pref DELAY TABLE ACE LIST DESTINATION DELANY MAK Mz LOGIC LEVEL E 155 CLK SLICE 122 1 357 A4ll 736 920 All 141 CLK SLICE 108 0 1 357 4ll 73592 ho SLICE 148 CLK SLICE 115 MU 1 357 All 735 820 AII Speed grade Analysis 1 _108 5 SLICE_156 CLK SLICE_136 CLK Orton SLICE_160 CLK SLICE 134 1 1 Search Facility Easily find specific signals Humber af 21400 SLICE 154 CLK 1587 SLICE 125 54D Delay path SLICE 118 CLK SLICE 42 011 9 Filtering Features Unwanted nets signals etc are not displayed 1 358 A 730 460 All 1 15 41 46 Supports Devices Spreadsheet GUI of ST
55. k Modular Design Step Guide performing design entry simulation synthesis and Assistant Design Step Guide place and route of designs that incorporate embedded Tutorials and Examples or distributed RAM memories Software Manuals 1 Using the Project Navigator create a project that Troubleshooting targets LatticeECP ECor LatticexP device Lattice Website Design Flow Generate a specific configuration of a memory module using IPexpress Embedded sysMEM modules are collected into the Components module folder and distributed RAM modules are collected in the Storage Components module folder of the module branch main window Memory module behavior port descriptions and configuration details are documented 1051 4 4 Done 2 Lattice Semiconductor Corporation Bringing the Best Together Software Overview ispLEVER Project Management Features and Tools Design Entry HDL Synthesis T p M S ul 47 Advanced Implementation Tools Simulation and Analysis Device Programming In system Logic Analysis Copyright Lattice Semiconductor 2006 Semiconductor Page ee IUOS 4 4 4 YU Corporation Bringing the Best Together Project Project Navigator Design Entry Source management and process control Revision
56. lability Available now On the web Applications note including schematics PAC Designer Software Copyright Lattice Semiconductor 2006 Sem 89 i PAC CLK5620 Evaluation Board Configuration DIP switches SMA connectors Power input s Em e ET ct ed ial CC e JTAG INTERFACE E SE POWER ahh Ezz TOO Fe i Rees LIED IspPAC CLK 5520 Copyright Lattice Semiconductor 2006 Page 90 ispClock 5620 Oscillator JTAQ interface i SMA connectors Lattice Semiconductor Corporation Bringing the Best Together PAC POWR1208 P1 Evaluation boards Features Large prototype area Access to all device LEDs for status indication JTAQ interface 100 TQFP device ispPAC POWR1208 44 pin TQFP package also available with 1208P1 Board Only PACPOWR1208 EV List Price 99 Development Kit PAC SYSTEMPOWR1208 List Price 125 Includes PAC Designer software amp Download cable Availability 1208 and 1208P1 boards Available now web Applications note including schematics PAC Designer Software s Copyright Lattice Semiconductor 2006 TEETE ductor Page 91 Corporation Bringing the Best Together PAC POWR1208 P1 Evaluation Board Power input Q
57. n Corporati LatticeXP Standard Evaluation Board Features Multiple power planes external sources available On board oscillator SMA pads for high speed signaling SMA pads not populated LEDs amp switches for feedback amp configuration Generous prototype area On board power supply Note Initial Rev A boards did not include this 256 ball device XP10 LFXP10C L EV Availability Rev B boards now including AC adapter and download cable On the web User manual sample program Copyright Lattice Semiconductor 2006 Sem 91 LatticeXP Standard Evaluation Board Prototype area LatticeXP LFXP10C 5F256C LEDs Power Circuitry SMA pads A 1B gt ys On board w oscillator Prototype area Copyright Lattice Semiconductor 2006 Lattice Page 82 Corporation Bringing the Best Together LatticeXP Advanced Evaluation Board Features LFXP10C 5F388C FPGA Device DDR memory interface socket 10 100 1G E net MAC interface PCI interface On board FCRAM On board oscillator Various LEDs SMA connections for external clocking and on board power control 388 ball device XP10 LFXP10C H EV List Price 1295 Availability Contact your Lattice Representative On the web Evaluation bitstreams when available User manual w schema
58. n Universal File Writer UFW Advance d isoVM Embedded Device programming via embedded processors VME source code provided Serial Vector Format SVF Debugger ATE Programming Vector Generator USB Gang Programming DLxConnect Industry s Best Programming Solution In system Logic Analysis Copyright Lattice Semiconductor 2006 Page 42 In System Logic Analyzer IspLEVER Praject Management Embedded Logic Analyzer Core Design Entry Configure trigger logic and trace buffer via IPexpress Easy LA to logic connection GUI Non invasive HDL post synthesis core integration EDIF ispTRACY Logic Analyzer CUTS User defined triggers and capture modes NE List or wave format analyzer GUI Integration with ispVM Device Programming In system Logic Analysis Real Time Logic Analysis ROADMAP ITEM Lattice Copyright LaiticeSemiconducter 2006 4 E d P LF P F DO PG 1 wach Se ondu ictor Page 43 Uh e ispTRACY Logic Analyzer Embedded Logic Analyzer IP core Logic Analyzer UI Set triggers Select capture modes alyispTRACY Core ispTRACY Core LA core Enable external trigger input and output Run or stop the triggers Waveform and List Display mn CNT012_INST nnn 012 INST mmn CNTO12 INST nnn CNTO12 INST nmn CN
59. n bu Macrocell IO Types Then bu QD Q B LVTTL G3 en LYCMOS33_OD LYCMOS25 OD Then bu Ly MOSS 7 Lw MOS op Fes Lattice Semiconductor on mmnm Corporati Design Planner Floorplan amp Package Views e Graphical Design Viewer and Editor Used for Timing Location and Buffer Constraints Used for pin assignment grouping signals placement critical path analysis routing analysis more TET in performance optimization and timing closure x X 5 ate Display Grouping Help File View Lever Mones Tools Help BS QQQ 8 2 Se e EE Logical RP setup me 095 Floorplan Timing Path 0 469 0 287 0 287 CLK Q1 FO B1 3 BER mm a 9 sel had R13C21C R12C2 3 WEE R13C21A Path Tracer File Edit View Too Help Pre Mapped View K n Post Mapped View Loading de Package View rom file c ispdesiqns vhdlhdesignr See Tons SEIS elp pl n sas vendor LATTICE device LIE Loading de gt rom file ep5g49x556 nph in environ a RAA ukt 2 ackage DUCTION 0X Ms E 3 03 b b
60. nce Design Peripheral Source Documentation Everything Needed for Design Copyright Lattice Semiconductor 2006 Semiconc 62 Corporation Agenda ispLEVER Software Feature Overview ispLEVER Versus the Competition ispLeverCORE Overview Development Hardware How to Learn More Copyright Lattice Semiconductor 2006 Sem 63 PAC Designer Mixed Signal Design Tool Complete Mixed Signal Design Tool Self Contained Support for ispPAC Devices Fully Integrated Design and Simulation Environment High Level Logic Design Mechanism ISPPAC CLK5620 Configuration Synthesizer Profile 0 Input Frequency MHz M Divider 33 33 1 Skew Mode Suggest Input Fine Frequency C Coarse N Divider Frequency 8 53333 Feedback Source V4 Divider Use External m Feedback Only find configurations with output duty cycles from 47 to 53 Done Solution found within specified tolerances Frequency Synthesizer Copyright O Lattice Semiconductor 2006 Page 64 LogiBuilder for PAC Designer GUI for ispPAC Power Manager PAC Designer cPCI Mangement PAC mi File Edit View Tools Options Window Help x TA G PINS lt gt Actual Output Requested Output Acceptable ivider Frequency frequency Tolerance
61. oard SPI Flash configuration memory Various LEDs switches connectors headers SMAs on board power supply Lattice PAC POWR1220AT8 Power Manager 672 ball device LFE2 50E 6F672C Availability Available Now On the web User guide including schematics sample program Copyright Lattice Semiconductor 2006 Sem 72 LatticeECP2 Advanced Evaluation Board E net PHY RJ 45 33 33 MHz Oscillator DDR SO DIMMs LatticeECP2 FPGA Copyright Lattice Semiconductor 2006 Page 73 Fj E T ad Eu saf m k ria PTT Y CUT Y T Pa FI ere Lab ETFI wile m w m EIN I 1241 3 pe ane Lele EJ A REL I T 4 v Er s s rr ES BEER Prototype area dd H 2 i m Eli H 7 segment LED 5 oU s H 1 d ak 1 E vom d NIE On board power supply Compact Flash Connector SPIA connectors
62. oject Navigator Block Modular Design Text Editor ochematic Editor IPexpress Design Planner Design Planner T ModelSim or party simulation tools UE Waveform Editor Power Power Calculator Estimation ispLEVER Copyright Lattice Semiconductor 2006 Page 50 Project Navigator Modular Design HDL Editor ECS CORE Generator Constraints Editor Floorplanner ModelSim or 3 party simulation tools ISE Project Navigator LogicLock Text Editor Block Editor MegaWizard Plug In Mgr Assignment Editor Floorplan Editor Simulator or 3 party simulation tools Waveform Editor PowerPlay Quartus II Lattice 26 er i e Soflware Orientation Precision RTL or XST or 3 d party Integrated Synplify Synthesis or 39 party Design NGDBUILD NGDBUILD MAP MAP PAR PAR Fitter Timing TRACE and TRACE and Timing Analyzer Analysis Performance Analyst Timing Improve Wiz Programming BITGEN BITGEN Assembler Configuration ispV M IMPACT Programmer On Chip isoTRACY ChipScope SignalTap I Debugging ispLEVER ISE Quartus II Lattice Copyright LatticeaSemiconducter 2006 4 P F Ff P L F P F t L Se ondu ictor Page 51 dh M Migrating a Xilinx ISE User to ispLEVER Includes industry standard synthesis tools Includes ModelSim Many similarities MAP PAR TRACE and EPIC 8 Module IP Manager
63. poration Bringing the Best Together Copyright Lattice Semiconductor 2006 Page 95 ispLEVER Flash Demo Self Running Narrative and Demo Movies Updated each release Getting Started Best of Class Tools and a Familiar Design Flow and FPGA Design Software Mozilla Firefox x File Edit Go Eaokmaks Back Reload 1 Home la ticeserncorrulegacyfleverllash E ispLEVER Movies OVERVIEW GETTING STARTED DESIGN ENTRY TOOLS etscape VISUALIZE Go Bookmarks Tools Window Help file C Documents 20and 20Settings tschnett Desktop ispLEVERFlashDemo_ 0309052 lt 5 REPORTS SIMULATE R Flash Demo Qattice K ispLEVER tting Started Flash Demo Lattice Project Wizard dule IP Manager eference Editor 2st of Class FPGA Tools for Lattice TEREST amp Route Setup orplanner wer Calculator imiliar Design Flow oject Navigator Transferring data from wes lalticezen nA 20 T Designs with Copyright View Now Page 96 59 Ox EJ Done fail Home 62 Radio Netscape Bookmarks pre map Preference Editor C NispDesigns tutor12 tutor12 prf j Edit Preference Device View Window
64. ptimization Routing Delay Reduction Passes box the edit regian far a list of choices Copyright Lattice Semiconductor 2006 Page 30 List Num THF List Double click the selected item to cycle through possible choices or use the combo Online Help is available if yu highlight the option and press F1 Placement effort Close a True False True True n Detaults Routing passes Lattice Semiconductor Corporation Bringing the Best Together Register Retiming Project TUE EET BAR Balances Combinational Logic Across Register Pairs Maximizes fmax according to the O Normal dy Ree 10 76 Z Sources in Project Processes For current source f 7 Untitled gt Build Database CO n st ra n ts s toy 9 O r MAX n Ea Documents B Pre Map Logical Design Floorplan E 45 LFECZOE 3F amp 72CES A Pre Map Preference Editor preference file count Eb tf C3 Design count teaunt v Report counter mrp i ik mis 1 ambo 53 Properties Normal Design Typically Improves fmax by 5 10 Controllable Option for Users Jem _ Pack Logic Black Util blank 0 ta 100 Hid Hierarchical Mapping T F False 4 93
65. r you can let gt System features and tools gt I z m 4 Design Entry S ispLEVER determine optimal placement ORCAstra Bonn oad ispLEYER tarter Hm s 4 5 and routing But if you have special design software u B HDL Synthesis requirements or need detailed control p PAC Designer What s new in ispLEVERN 5 x r i over your design implementation IspLEVER has the advanced tools you b Software Archive View ispLEVER flash demo Tasa u aaAm i ass YFY need Simulation and P Licensing ispLEVER version 5 0 SP1 is the latet Analysis Click the items below to learn more Optimize Your CPLD and FPGA design software a about these powerful features and tools Designs with supporting all Lattice Programmable p Devica Programming included WIGFISBEEVER ispLEVER logic devices ispLEVER includes tools dev lopd by bo P In system Logic ispLEVER Project leaders the industry for Design Home Products Solutions Support Documents Sales Corpa Analysis Management Verification Simulation Fitting Place amp Route 13214 Programming R Design Software Preference Editor Design Entry CAES rt yy a s r E Our ispLEVER 5 0 1 CPLD and FPGA design soft ERES citt ispLEVER includes an ULEVER r and FRA design software taal helping take your design all th
66. s intellectualproperty 28 Unique Functions Copyright Lattice Semiconductor 2006 Semiconductor 60 ion ispLeverCORE Connections Partners 3rd Party Developed Sold and Supported Augments The Lattice Portfolio Adds functions for applications for which we have little experience or expertise Leverage 3rd Party Expertise Experts create and support complex functions Faster Time to Market 3rd Parties act as resources to port and support AC ADIG AL gt NORTHWEST CAS CORE DESIGN y Locic Elliptic 27 Eureka Technology Semiconductor artO silicon Look for this Approved logo all ispLeverCORE Connection IP Products Copyright OLatticeSemiconducter 2606 4 F P L F P d y P3 1 wem age 61 LatticeMico8 8 Bit Microcontroller Optimized For Lattice Leading Edge Families LatticeECP EC LatticeXP and MachXO Targeted Towards Wide Variety Of Applications Consumer Computation Communications Medical Industrial Auto Innovative Open IP Core License Key Architectural Features 8 Bit Data Path 18 Bit Wide Instructions Two Cycles Per Instruction 32 General Purpose Registers 32 Bytes Of Internal Scratch Pad Memory Input Output Is Performed Using Ports Up To 256 Port Numbers Optional 256 Bytes Of External Scratch Pad RAM Lattice UART Refere
67. tics when available Copyright Lattice Semiconductor 2006 Sem 93 LatticeXP Advanced Evaluation Board LatticeXP Tu LEXP10C 5F3g8c PPR Memory slot Power Circuitry FCRAM N On board oscillator Ext Clock in E net connector E net Voltage plane PHY PCI interface selection Copyright Lattice Semiconductor 2006 84 Bringing the Best Together MachXO Starter Evaluation Board Features MachXO device Power input jack 33MHz oscillator Status LEDs and 9 LEDs 8 bit input switch Access to all device I O Prototyping area Landing pads for off board expansion connectors AC adapter Included International plugs Download Cable Included HW DL 3C 100 TQFP device MachXO 256 LCMXO256C 4T100C Availability Shipping today order via on line store or through your Distributor Board AC Adapter Download Cable 99 An incredible value On the web User Manual available for download includes schematics Copyright Lattice Semiconductor 2006 Sem 95 Device I O access x Allen isum eum lt eta Ba P er LI fe Li T HH SHEER ETE LOMXDPSGD 9
68. x Search Glossary How to Design with FPGA FPGA Design Release Compatibility Notice Memories qb using Help bow Ta The Lattice FPGA memory technology helps you easily How to Design with FPGA Memories Create and implement a variety of memory How ta Use Dedicated DDR Memory Sug organizations including single port dual port pseudo How to Achieve Timing Closure RAMs ROMs or FIFOs You can contral Howto Design with sysCLOCK PLLs ane what FPGA resources will be employed to implement 1 How To Design with sysIO Buffers the memory as either sysMEM embedded block RAM How to Design with sysDSP ar distributed RAM across programmable function units PFUs The ispLEVER software helps automate the implementation of memories from design entry through creation of a programming file This How to topic applies to the Lattice ECPR EC and LatticesP device families For FPGA memory feature support by device family as well as 18 SODDINT and ispAPGAyispAP s4 E device families see the references listed at the end of this topic How to Set Configuration Options How ta Use GSR PUR and TSALL for FF How to Use the Assistant How to Perform Logic Analysis Design Tools Design Entry b HDL Attributes Design Simulation Design Implementation gb Design Verification Device Programming Running FPGA Tools from the Command L The following steps describe the typical flow for Bloc
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