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M68360QUADS Hardware User`s Manual

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5. Pin Pin Name Description 0 Ethernet This pin is connected to the receive data output of the EEST It is configured as the receive data of SCC1 in the slave QUICC 1 Ethernet TX This pin is connected to the transmit data input of the EEST It is configured as the transmit data of SCC1 in the slave QUICC 2 AppleTalk RX This pin is connected to the receive data output of the AppleTalk transceiver U29 It is configured as the receive data of SCC2 in the slave QUICC 3 AppleTalk TX This pin is connected to the transmit data input of the AppleTalk transceiver U29 It is configured as the transmit data of SCC2 in the slave QUICC 4 RS 232 RX This pin is connected to the receive data output of the RS 232 transceiver U23 It is configured as the receive data of in the slave QUICC 5 RS 232 TX This pin is connected to the transmit data input of the RS 232 transceiver U23 It is configured as the transmit data of SCC3 in the slave QUICC 6 Enable DRAM This pin is connected to switch 3 in dip switch U52 It is configured as input pin in the slave QUICC and its level indicates to the CPU32bug software if it should enable accesses to the DRAM on the QUADS If the level is 0 the DRAM is enabled 7 Enable Flash This pin is connected to switch 4 in dip switch U52 It is configured as input pin in the slave QUICC and its level indicates to the CPU32bug software if it should enable a
6. Freescale Semiconductor Inc 9 5 d 2 g y 9140530 20031 1 30 553400 2078 VDHSOH3A NINV 9N3 40 5 133 5 10114 A38 50 9 193 089 cen ONI 1 E 10 n im ino 8 LL 919 rez 8 950 5 zi 819 ias 27 ZHNOS 250 Iv 10170 v YLIONVL T oD vLIOVVL 15 014 lt son Len vin Wu 6 88 91 ocn 26 f 2 19 LT 26391 TIS 198 8 lt 2010 Evz wk 898 NE Fn 198 ovh tev ory orv 91 8 Bev 91041 ezv 1 8 ezv Bitat thie ezv 8 8 Len vVCLOWEL 737 1 2 T HISS 70371 t ul v azn on in 9 57 57 6 MIO MIO 98 Sie 279 11198 9 6 11198 86 111988 36 n PY zzv 21 a LY 8 viv 4 2 N 8
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10. amp 5 ENABLE ISDSKO amp A DIR 8 RSTH IMDSKO 5 5 amp B32 16 4 AS ISDSKO amp 2 16 amp AS amp DSK1 ENABLE SDSKO0 IMDSKO amp IA DIR RSTH ISDSKO IMDSKO amp B32 16 amp AS IMDSKO IB32 16 amp IAS amp DSK1 ENABLE D DIR ID DIR amp S CS7 8 1 28 31 1 DIR amp R ENABLE LO EN B32 16 amp 5 amp RSTH For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 5 User s Manual SUPPORT INFORMATION ENABLE SWAP ISWAP 2 16 amp 5 amp RSTH amp A DIR amp R B32 16 amp 5 amp RSTH DIR amp 5 57 amp 1 28 31 A1 amp IDSK1 8 ISDSKO B32 16 amp 5 amp RSTH DIR amp 5 CS7 amp 1 28 31 amp A1 amp IDSK1 amp IMDSKO ENABLE HI EN H B32 16 amp IAS amp RSTH 1832 16 amp IAS 8 RSTH amp DIR 1832 16 amp IAS amp RSTH DIR R B32 16 amp IAS RSTH amp DIR amp 5 CS7 amp 1 28 31 amp 1 B32 16 IAS amp RSTH amp DIR amp S 57 amp 28 31 amp A1 amp IDSK1 amp 505 amp MDSKO B32 16 amp IAS amp RSTH amp A DIR amp S CS7 amp 28 31 amp A1 amp DSK1 amp ISDSKO 1832 16 amp IAS RSTH DIR amp S 57 amp 28 31 am
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13. pin selects the operating port TPAPCE This pin is connected to the TPAPCE input of the EEST and it is configured as output in the slave QUICC If this pin is 1 automatic polarity correction is enabled on the TP port TPSQEL This pin is connected to the TPSQEL input of the EEST and it is configured as output in the slave QUICC If this pin is 0 it enables testing the EEST internal collision detect circuitry 10 TPFULDL This pin is connected to the TPFULDL input of the EEST and it is configured as output pin in the slave QUICC If this pin is 0 it allows simultaneous transmit and receive operation on the TP port without an indicated collision 11 LOOP This pin is connected to the LOOP input of the EEST and it is configured as output pin in the slave QUICC This pin enables diagnostic loopback in the EEST 34 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 5 Users Manual FUNCTIONAL DESCRIPTION 4 7 9 4 Slave QUICC Port E Port E pins can be configured to operate in one of two dedicated peripheral functions The PEPAR register configures the operation mode as described in section 3 5 5 on page 19 4 8 LOCAL BUS ARBITER Sheet 9 The local bus master can be one of the following The master QUICC An External Bus Master connected to the QUADS through the expansion connectors The slave
14. 36 80 RAS1 0110 MCM36256S80 256K x 36 80 51 0111 36200580 2 36 80 RAS1 1000 36100570 1M x 36 70 51 1001 36512570 512 36 70 51 RAS2 1010 36256570 256 36 70 RAS1 1011 36200570 2M 36 70 RAS1 1100 Not Valid 1101 Not Valid 1110 Not Valid 1111 Not Valid For More Information On This Product Go to www freescale com 25 Freescale Semiconductor NaesoqQuaADs Users Manual FUNCTIONAL DESCRIPTION The DRAM is controlled by the slave QUICC device using its DRAM Controller function for normal accesses page mode accesses and refresh accesses The DRAM can be accessed by the master QUICC the slave QUICC the IDMA and the SDMA are not disabled and external bus master connected to the expansion connectors of the QUADS The user may indicate to the CPU32bug software not to initialize BR1 OR1 BR2 and OR2 registers in the slave QUICC by setting the Enable DRAM switch in U52 to OFF This setting is used to disable accesses to the DRAM after hard reset and its address space may be used by the user Note The CPU32bug software requires 8 KByte of RAM space located at address 00400000 If the DRAM is disabled the user must connect external RAM to the QUADS for the software to run properly 4 7 Slave QUICC During normal operation the CPU of the slave QUICC U4 in sheet 3 is disabled and the device is used to implement the following functions
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19. The host computer can reset soft or hard the M68360QUADS If more than one M68360QUADS is connected to the same ADI board the host computer can perform the following operations simultaneously on all M68360QUADS boards Abort all boards interrupt level 7 Resetall boards 58 For More Information On This Product Go to www freescale com M68360QUADS Users Manual Freescale Semiconductor Inc ADI PORT HANDSHAKE DESCRIPTION B 3 Handshake Description Every action between the M68360QUADS and the host is asynchronous and is implemented by asserting and negating handshake signals by software All signals have TTL levels A control signal is asserted if it is driven to logic 1 TTL level and it is negated if it is driven to logic 707 level The connection between the host computer and the M68360QUADS is shown in FIGURE B 1 below FIGURE B 1 Host Computer ADI to M68360QUADS Connection HOST REQ ADS ADS REQ 5 gt gt ADS BRK HOST BRK HOST ADS INT M68360QUADS COMPUTER lt gt gt ADS RESET gt ADS ALL gt gt ADS SEL 0 2 PD 0 7 HOST ENABLE HOST VCC gt gt 59 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 5 Users Manual ADI PORT HANDSHAKE DESCRIPTION B 3 1 Write C
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23. 4 Address line 4 of the master QUICC unbuffered 16 A3 Address line 3 of the master QUICC unbuffered 17 A2 Address line 2 of the master QUICC unbuffered 18 A1 Address line 1 of the master QUICC unbuffered 19 Address line 0 of the master QUICC unbuffered 20 GND Ground signal of the M68360QUADS 5 2 2 Connector PD2 Interconnect Signals Connector PD2 is a double row 20 pin male connector The higher 16 address lines of the master QUICC appear on this connector for easy monitoring of the bus by a logic analyzer Table 5 1 describes the connector signals Table 5 2 Connector PD2 Interconnect Signals Pin No Signal Name Description 1 Not connected 2 Not connected 3 DSACKO DSACKO line of the master QUICC 4 A31 Address line 31 of the master QUICC unbuffered 5 A30 Address line 30 of the master QUICC unbuffered 6 A29 Address line 29 of the master QUICC unbuffered 7 A28 Address line 28 of the master QUICC unbuffered 8 A27 Address line 27 of the master QUICC unbuffered 9 A26 Address line 26 of the master QUICC unbuffered 10 A25 Address line 25 of the master QUICC unbuffered 11 A24 Address line 24 of the master QUICC unbuffered 12 A23 Address line 23 of the master QUICC unbuffered 13 A22 Address line 22 of the master QUICC unbuffered 14 A21 Address line 21 of the master QUICC unbuffered 15 A20 Address line 20 of t
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26. EEPROM MC68160 EEST Ethernet Port Ethernet Port BDM Controller Port ADI Port RS 232 Port AppleTalk Port RJ 45 Connector AUI Connector P9 5 6 P8 P7 4 4 Flash Memory Four Flash Memory devices the 28F010 128 KByte 120 nsec access time are used to form 512 Kbyte program storage memory The devices U72 to U75 in sheet 2 are organized as long word 32 bits wide The Flash Memory devices are soldered to the board and program code updates will be done on board without the need for external EPROM programmer The programming software is stored in the boot EPROM which loads the new code through one of the QUADS ports erases the Flash Memory and programs the new code For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 5 Users Manual FUNCTIONAL DESCRIPTION The slave QUICC device provides the CS signal to the Flash Memory The user must connect external 12v power supply to connector P12 to program the devices The user may indicate to the CPU32bug software not to initialize and ORG registers the slave QUICC by setting the Enable Flash Memory switch in U52 to OFF This setting is used to disable accesses to the Flash Memory after hard reset and its address space may be used by the user 4 5 EEPROM The EEPROM used in the QUADS is Motorola 2814 256 byte serial EEPROM 033 in sheet 2 The slave QUICC SPI port port B pins 0 to 3 is us
27. N C TPRX N C N C gt C The list below describes the signals The directions O and 1 are relative to the QUADS board LE means input to the QUADS Transmit Data positive TPTX Transmit Data negative TPRX 1 Receive Data positive e TPRX 1 Receive Data negative 4 7 8 Serial EEPROM Interface Sheet 2 The MCM2814 serial EEPROM 033 in sheet 2 is 256 bytes EEPROM with SPI interface It is controlled by the SPI port of the slave QUICC pins 1 2 and of port B and by a general purpose output pin pin 0 of port B The SPI port operates in master mode 4 7 9 Slave QUICC General Purpose 1 Pins The slave QUICC has three ports A B and C whose pins can be individually configured by software to be general purpose pin or dedicated peripheral function The QUICC also has another port E whose pins are not general purpose I O but they can be configured to operate one of two possible modes The following subsections describe the slave QUICC ports Refer to section 3 5 on page 18 for the required programming information For More Information On This Product Go to www freescale com 31 4 7 9 1 Freescale Semiconductor 1 36500005 Users Manual FUNCTIONAL DESCRIPTION Slave QUICC Port A Port A is 16 pins port Table 4 2 describes the configuration of port A Table 4 2 Port A Pins Description
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29. local area network that connects multiple Maclntosh computers and printers The AppleTalk port connector P6 is 8 pin MINI DIN JACK connector as shown in FIGURE 4 4 FIGURE 4 4 AppleTalk Connector 29 For More Information On This Product Go to www freescale com Freescale Semiconductor NaesoquaADs Users Manual FUNCTIONAL DESCRIPTION 4 7 5 1 AppleTalk Port Signal Description In the list below the directions O and 1 are relative to the QUADS board I E l means input to the QUADS e 45 5 output from the QUADS through 100 ohm resistor e HSKI 1 Hand Shake Input TX O Transmit Data negative e RX I Receive Data negative Transmit Data positive RX 1 Receive Data positive 4 7 6 BDM Controller Sheet 16 The slave QUICC enables the M68360QUADS to become controller to control other QUICC devices on the user application The BDM feature enables the user to download code and provides hardware and software debugging capability of the user application The 8 pin BDM connector P9 utilizes five pins of the slave QUICC port B These pins are configured as general purpose 1 pins 4 7 7 Ethernet Controller Sheet 10 The slave QUICC provides Ethernet port for the M68360QUADS by connecting SCC1 to Motorola MC68160 EEST device 035 in sheet 10 The MC68160 provides two Ethernet interfaces twisted pair on P8 and AUI on P7 The LEDs LD3 LD8 are cont
30. 24 of the master QUICC unbuffered 12 D23 Data line 23 of the master QUICC unbuffered 13 D22 Data line 22 of the master QUICC unbuffered 14 D21 Data line 21 of the master QUICC unbuffered 15 D20 Data line 20 of the master QUICC unbuffered 16 D19 Data line 19 of the master QUICC unbuffered 17 D18 Data line 18 of the master QUICC unbuffered 18 D17 Data line 17 of the master QUICC unbuffered 19 D16 Data line 16 of the master QUICC unbuffered 20 GND Ground signal of the M68360QUADS 5 2 5 Connector PD5 Interconnect Signals Connector PD5 is a double row 20 pin male connector The master QUICC bus control signals appear on this connector for easy monitoring of the bus by logic analyzer Table 5 1 describes the connector signals Table 5 5 Connector PD5 Interconnect Signals Pin No Signal Name Description 1 Not connected 2 Not connected 3 AS Address Strobe 4 Bus Error 5 Parity Error 6 IFETCH Instruction Fetch 7 IPIPEO Instruction Pipe 0 8 IPIPE1 Instruction Pipe 1 9 FREEZE Freeze 10 FC3 Function Code 3 11 DSACK1 Data and Size Acknowledge 1 12 DSACKO Data and Size Acknowledge 0 13 FC2 Function Code 2 14 FC1 Function Code 1 15 FCO Function Code 0 16 SIZ1 Transfer Size 1 17 SIZO Transfer Size 0 18 R W Read Write 19 BGACK Bus Grant Acknowledge 20 GND Ground signal of the M68360QUADS 42 For More Inform
31. 3400070 401070 o Y Y 90 699 83 169 ior qug ili 19 Ma e err 2 ddA j 3503 ani A 8C 5 6422 050918 9 6d ISOG8 5 68 158108 5 5x6 5 183108 WOE 1 6d gt 8 2 Z 9 Dem HO IN Z 158 VES 73383N 2 14 8 71 H 9 3 3 2 8 V oje 555 914 26 CC 4 991 0 106 ewou Go to www freescale com 080530 A0031 5 N3MOd S X208 5 9N3 E LV 133 5 10119 SOVNOOSSBOW 103lONd 30117072 30117072 30117072 30117072 31117072 3 17072 3 17072 31079 3 17072 Ho 982 892 219 560 810 872 299 199 652 192 5 5 5 e 30117072 30117072 3117079 3117079 30170792 jnre o 30117072 30170792 3017072 31017072 31017072 31017072 30170792 30170792 30117072 o 1
32. in the slave QUICC It should be connected to the FREEZE pin of the external QUICC device 5 BDMRST This signal is connected to Port B pin 5 in the slave QUICC It should be connected to the Hard reset pin of the external QUICC device 6 BDMDSI This signal is connected to Port B pin 7 in the slave QUICC It should be connected to the Instruction fetch pin of the external QUICC device 7 VCC 5V 8 BDMDSO This signal is connected to Port B pin 6 in the slave QUICC It should be connected to the Instruction pipe 0 pin of the external QUICC device 5 2 16 Connector P10 Interconnect Signals Connector P10 is a double row 16 pin wire holes on the M68360QUADS It provides all the signals between the slave QUICC and the EEST This connector is used for internal factory testing of the board Table 5 1 describes the P10 connector signals Table 5 16 Connector P10 Interconnect Signals Pin No Signal Name Description 1 Ethernet TX This pin is connected to Port A pin 1 in the slave QUICC and to the transmit data input of the EEST 2 TENA This pin is connected to Port C pin 0 in the slave QUICC and to the TENA input of the EEST 3 Ethernet TCLK This pin is connected to Port A pin 8 in the slave QUICC and to the TCLK output of the EEST 4 Ethernet RX This pin is connected to Port A pin 0 in the slave QUICC and to the receive data output of the EEST 5 RENA This pin is connected to Port C pin 5 in the sl
33. master QUICC are driven by open collector devices so that the user application connected to the expansion connectors P1 and P2 may assert them along with the interrupt logic on the QUADS board It is possible to disable 070 from driving the IRQ signals so that the master QUICC can only be interrupted by its internal peripherals or by the user application This is done by setting the Enable Interrupt switch in 052 to OFF FIGURE 4 7 Interrupt Logic Configuration ABORT Switch IRQ7 Host 741505 slave 2 0 74 538 IRQ 7 1 master M urs QUICC Decoder Open Collector QUICC ADI Port IRQ2 Device Activity Enable Interrupt U52 Dip Switch Expansion Connectors P1 and P2 The slave QUICC accepts interrupts from the ABORT switch the Host NMI register and the ADI port logic These interrupt sources are encoded by the slave QUICC along with interrupts from its internal peripherals and highest interrupt level is driven on the IOUT 2 0 pins The slave QUICC may supply interrupt vector during interrupt acknowledge cycle for its internal interrupts but it can not do that for the external interrupts Therefore the master QUICC must be programmed to provide auto vector for interrupts in levels 2 and 7 If the QUADS is configured to operate in 16 bit mode the master QUICC can not read the interrupt vector generated by the slave QUICC du
34. negated high level The PLD device drives configuration pin 0 of the slave QUICC to high level for 64 clocks and then the signal CONF2 drives it to low level as long as the hard reset signal is asserted low level When the hard reset signal is negated the CONF2 is in three state and it stops driving the configuration pin 0 TITLE DISCPU PATTERN dis_cpu pds Revision A AUTHOR Yair Liebman COMPANY MOTOROLA SEMICONDUCTOR ISRAEL LTD DATE 14 3 93 CHIP DIS CPU PAL22V10 CLK NC NC NC NC NC NC NC CIN NC RESETH GND 11 2 4 15 6 17 18 9 HO 111 12 NC 05 04 02 Q1 00 CONF2 S RST DD_RST D_RST VCC 13 O14 O15 O16 O17 O18 O19 O20 O21 O22 O23 24 GLOBAL EQUATIONS D_RST RESETH D RST TRST DD RST D RST DD RST TRST VCC S 0 DD RST QO 00 5 RST CIN Q0 5 RST CIN QO TRST VCC 70 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 5 User s Manual Q1 01 Q0 S RST CIN Q1 Q0 5 RST CIN Q1 5 CIN Q1 TRST VCC Q2 Q2 Q1 S RST CIN 02 00 5 RST CIN Q2 Q1 Q0 5 CIN Q2 5 RST CIN Q2 TRST VCC Q3 Q2 5 RST CIN Q1 5 RST CIN Q0 5 RST CIN Q3 Q2 Q1 Q0 S RST CIN Q3 5 RST CIN Q3 TRST VCC Q4 Q4 Q3 S RST CIN Q4 Q2 5 RST CIN
35. on the QUADS 1 DRAM Controller Chip Select and DSACK generator Parallel port ADI UART for terminal or host computer connection AppleTalk controller for Macintosh computer connection BDM controller to other QUICC devices Ethernet controller Serial EEPROM interface 9 General Purpose 1 signals The address of the MBAR register is configured to be at 0033FF04 The master QUICC must write the MBARE register at address 0033FF08 before each access to the slave MBAR register The slave QUICC is essential to make the master QUICC pins available for the user implementations QUICC peripherals such as the IDMA and SDMA can request the bus and become bus master while the CPU is disabled 4 7 1 DRAM Controller The slave QUICC device provides the necessary control signals for the DRAM module The software on the QUADS reads the presence detect pins of the SIMM and sets the DRAM Controller parameters according to the DRAM module and the access time of the DRAM The hardware connection of the slave QUICC to the DRAM module is straight forward External address multiplexers 067 062 and 053 in sheet 1 are used to drive the DRAM address lines to enable external bus masters to access the DRAM The CPU32bug software programs the PEPAR so that the OE AMUX pin of the slave QUICC is configured as AMUX to drive the address multiplexers The RAS1 RAS2 pins of the slave QUICC drive the DRAM SIMM The double drive sign
36. 00009 for 100 nsec DRAM If the DRAM SIMM type is MCM36200 BR2 must be initialized to 00800005 OR2 must be initialized to 2FC00009 for 70 nsec or 80 nsec DRAM and to 3FC00009 for 100 nsec DRAM Note The CPU32bug software does not access BR2 and OR2 after reset if the Enable DRAM switch in U52 is in OFF position The software must perform 8 accesses to the RAS2 address space after initialization for proper operation of the DRAM 3 5 11 Base Register and Option Register 3 Base register 3 BR3 and Option register 3 OR3 control the operation of CS3 pin of the slave QUICC The Flash Memory on the M68360QUADS is connected to this pin BR3 must be initialized to 00080009 and must be initialized to SFF80000 to obtain the memory map as described in Table 3 2 Note The CPU32bug software does not access and after reset if the Enable Flash Memory switch in U52 is in OFF position 3 5 12 Base Register 4 and Option Register 4 Base register 4 BR4 and Option register 4 OR4 control the operation of CS4 pin of the slave QUICC The M68360QUADS Status Register is connected to this pin BR4 must be initialized to 00024003 and OR4 must be initialized to OFFFEO02 to obtain the memory map as described in Table 3 2 3 5 13 Base Register 5 and Option Register 5 Base register 5 BR5 and Option register 5 OR5 control the operation of CS5 pin of the slave QUICC The M68360QUADS has Abort Register that is
37. 2 in the expansion connectors 7 Enable Interrupt When this switch is set to ON it enables the slave QUICC interrupt ON generator to drive the master QUICC interrupt input pins If the switch is set to OFF the interrupts to the master QUICC are disabled The master QUICC internal interrupt sources are not affected by the position of this switch The user application can drive the master QUICC interrupt pins through the expansion connectors When the switch is set to OFF all external interrupts to the master QUICC can only be generated by the user application 10 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 5 User s Manual HARDWARE PREPARATION AND INSTALLATION Table 2 2 Dip Switch U52 Description Switch Function setting 8 Data Bus Configuration This switch is connected to signal of the master OFF QUICC The level of this signal during hard reset determines the data bus size of the master QUICC If the switch is set to OFF the bus size is 32 bits If it is set to ON the bus size is 16 bits In 16 bit mode interrupt vectors from the slave QUICC do not pass to the master QUICC and the auto vector function must be used Note Power off the QUADS before setting this switch to ON 11 For More Information On This Product Go to www freescale com Freescale Semiconductor NaesoQuADs Users Manual HARDWARE PREPARATIO
38. 3 5 15 Base Register 7 and Option Register 7 Base register 7 BR7 and Option register 7 OR7 control the operation of CS7 pin of the slave QUICC 50 and CS7 are used to distinguish between accesses to the board internal resources and external devices that may be attached to the board For proper operation of the board BR7 must be initialized to 00000001 and must be initialized to F0000006 3 5 16 Port A Open Drain Register Port A of the slave QUICC is 16 pins port and each pin may be configured as general purpose l O pin or as dedicated peripheral interface The port A open drain register PAODR configures the drivers of port A pins as open drain or as active drivers The PAODR must be initialized to 0000 to select the active drivers configuration 3 5 17 Port A Data Register Port A data register PADAT can be read to check the data at the pin If a port pin is configured as general purpose output pin the value in the PADAT for that pin is driven onto the pin It is recommended to initialize PADAT to FFFF before configuring the other port registers 3 5 18 Port A Data Direction Register The port A data direction register PADIR has different functions according to the configuration of the port pins If a pin is general purpose 1 pin the value in the PADIR for that pin defines the direction of the pin If a pin is dedicated peripheral interface pin the value in the PADIR for that pin may select one of two de
39. 36100 the must be initialized to 17440380 For 80 nsec DRAM type MCM36512 or MCM36200 the GMR must be initialized to 0AA40380 For 100 nsec DRAM type MCM36256 or MCM36100 the GMR must be initialized to 17 44380 e For 100 nsec DRAM type MCM36512 or MCM36200 the GMR must be initialized to OAA44380 The GMR defines the following parameters The refresh period is 15 36 The DRAM refresh cycle length depends on the DRAM access time and it is either 3 clocks or 4 clocks long The DRAM module port size is 32 bits The parity is disabled The CS RAS lines of the slave QUICC will not assert when accessing the CPU space Internal address multiplexing for the DRAM is disabled 3 5 8 Base Register 0 and Option Register 0 Base register 0 BRO and Option register 0 ORO control the operation of CSO pin of the slave QUICC This pin has no connection on the M68360QUADS but 50 and CS7 are used to distinguish between accesses to the board internal resources and external devices that may be attached to the board BRO must be initialized to 00000003 and ORO must be initialized to 0006 for proper operation of the board 19 For More Information On This Product Go to www freescale com 20 Freescale Semiconductor 1 36500005 Users Manual OPERATING INSTRUCTIONS 3 5 9 Base Register 1 and Option Register 1 Base register 1 BR1 and Option register 1 OR1 control the opera
40. 5 SMD 04 U8 1 68360 QUICC Socket mounted U5 U7 74F245 SMD U11 U15 U18 U20 U25 U28 U32 U9 U16 74LS240 SMD U10 741585 SMD U17 U26 U34 Resistor Network 14 pins 4700 ohm SMD 036 038 049 050 055 060 069 U21 74ACT244 SMD U22 74 74 SMD U23 MC145407 SMD U24 Factory testing socket U27 50 MHz Clock Oscillator socket mounted U29 4050 SMD 030 PE64503 DIP U31 U68 741574 SMD U33 MCM2814 serial EEPROM DIP 035 MC68160 EEST TQFP U39 U61 74LS373 SMD 040 LAF10T 3B Ethernet filter SIL U41 LAF10T 7B Ethernet filter SIL U42 Programmed PAL16R4 7 socket mounted U43 Programmed PAL22V10 25 socket mounted U44 PE65263 DIP U45 PE65260 DIP U46 Dip Switch SPSTA 8 pin SMD U47 74F04 SMD U48 27010 20 Socket mounted U51 Programmed GAL22V10 7 Socket mounted U52 Dip Switch 5 5 8 16 pin SMD 053 062 067 74F157A SMD 51 For More Information On This Product Go to www freescale com Freescale Semiconductor Na6s0QuADs Users Manual Table 5 19 Parts List SUPPORT INFORMATION Part Description Notes 054 741500 SMD 056 058 059 74F32 SMD U57 U65 74F08 SMD 063 74700 SMD 064 066 741505 SMD U70 74F
41. 538 SMD U71 SIMM DRAM MCM36256S80 with SIMM socket U72 U75 28F010 120 Flash Memory PLCC SP1 Programmed PAL22V10 25 T H C1 C2 Capacitor 390 pF ceramic T H C3 C6 Capacitor 10 uF electrolytic SMD C7 C8 Capacitor 100 uF electrolytic T H C9 C35 Capacitor 0 1 uF SMD C40 C41 C43 C51 C55 C57 C95 CTO C36 C37 Capacitor 100 pF SMD C38 Capacitor 680 pF SMD C39 Capacitor 22 pF SMD C42 Capacitor 4700 pF SMD C52 Capacitor 3900 pF SMD C53 C54 Capacitor 68 pF SMD C56 Capacitor 0 039 uF SMD CA1 CA5 Capacitor 150 pF SMD CX1 CX4 Not mounted Used for factory testing R2 R25 Resistor 100 ohm SMD R3 Resistor 3 Kohm SMD R4 Resistor 510 ohm SMD R5 R7 Resistor 39 ohm SMD R11 R23 R26 R1 R8 R10 Resistor 25 ohm SMD R12 R16 R18 R17 Resistor 294 ohm SMD R19 R20 R22 Resistor 332 ohm SMD R24 R27 R21 Resistor 22 Kohm SMD R28 Resistor 243 ohm SMD R29 R30 Resistor 150 ohm SMD RS1 RS2 Resistor 1 Kohm SMD 52 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 5 User s Manual SUPPORT INFORMATION Table 5 19 Parts List 22 Part Description Notes RTO Resistor 51 ohm SMD RX1 RX4 Not mounted Used for factory testing P1 P2 Connector 96 pin DIN female 90 degrees Compatible wire wrap connectors are supplied with the M68360QUADS P3 P9 Connector
42. 598 zo 918 fV 20 sca 7118 2 2198 60 8 ro 7729 veo 911 8 97 910 09 88 oo 8 18 00 696 491 572371 572371 696 491 3 8 V LZiCL 380 26 vc 9 5910 Aauu0 Go to www freescale com H 9 3 3 2 8 9140539 40031 von Len S3HOLIMS NOLVN3N3O ADON MINV 9N3 ec lt L IZ 30 L 133 5 10d A38 SOVnoO9 89W 193 0 8 _ 4 80 3 WDCS s cost 0351 ONI V IONOLON von 2 T 5 ER 808191 8371 C Lus ERI an A 427702 1 107 Hg 5 ES 091 091 e CSE RES osy 9 lt 5 5 T _ 12 n LON 255075 23H 1HOBV 61 45177 5 con MT f C 9 B di 6 803 8154 Bgn 2 1 d 08811 a MIINNTH von ocn 51584 lt 25158 t 8 5 8 2 1 6 WW c C
43. 6 pin 6 7 8 9 S 57 28 31 R pin 10 11 13 EN SWAP LO EN D DIR pin 14 15 16 17 MDSKO0 SDSKO0 pin 18 19 2 20 21 22 23 reset preset Node 25 26 H L X Z C 1 0 4 equations reset L preset L ENABLE IBEO A0 amp 1 amp AS amp 5 ENABLE BE1 H IBE1 A1 amp AO amp AS 1 1 amp 171 amp 5 A1 815120 amp 5 amp 5 63 For More Information On This Product Go to www freescale com 64 Freescale Semiconductor NaesoQuADs Users Manual SUPPORT INFORMATION ENABLE BE2 H IBE2 A1 amp A0 amp 5 A1 amp SIZO amp 15171 amp IAS amp IA DIR A1 815120 amp 15171 amp IAS amp B32 16 1 amp SIZO amp 5141 amp AS amp DIR 81 1 amp SIZO amp SIZ1 amp AS amp B32 16 A1 amp amp 15120 amp AS amp DIR 1 amp amp 15120 amp AS amp B32 16 amp 5 ENABLE A0 amp Al amp 5 A1 amp A0 amp 5121 81 5 8 DIR amp B32_16 A1 amp 0 8 15120 amp 1 5 DIR amp 2 16 AO amp 5120 amp SIZ1 amp 5 amp IA DIR amp 6170 amp SIZ1 amp 5 amp B32 16 15120 amp 5121 amp 5 amp IA DIR 151 0 amp 5121 5 8 B32 16 A1 8 5121 amp AS amp DIR A1 amp 5121 8 AS amp 832 16
44. 7 1 Instruction pipe 1 of the master QUICC C28 VPP 12 C29 GND Ground signal of the M68360QUADS C30 CLKO2 System clock out 2 pin of the master QUICC 50 MHz C31 GND Ground signal of the M68360QUADS C32 CLK2 The operating clock of the M68360QUADS 25 MHz 45 For More Information On This Product Go to www freescale com 5 2 9 Freescale Semiconductor 36500005 Users Manual SUPPORT INFORMATION Connector P3 Interconnect Signals Connector P3 is a double row 8 pin male connector It provides the BDM signals of the master QUICC so that it can be controlled by external BDM controller Table 5 1 describes the P3 connector signals Table 5 9 Connector P3 Interconnect Signals Pin No Signal Name Description 1 GND Ground signal of the M68360QUADS 2 BKPT Breakpoint pin of the master QUICC 3 GND Ground signal of the M68360QUADS 4 FREEZE FREEZE pin of the master QUICC 5 RESETH Hard reset pin of the master QUICC 6 IFETCH Instruction fetch pin of the master QUICC 7 VCC 5V 8 IPIPEO Instruction pipe 0 pin of the master QUICC 5 2 10 Connector Interconnect Signals Connector P4 is a 37 pin male D type connector It is the ADI port of the M68360QUADS Table 5 1 describes the P4 connector signals Table 5 10 Connector P4 Interconnect Signals Pin No Signal Name Description 1 INT ACK Int
45. 8 e NHISH 195 SC 0 IACZ Wd no JAVA 05733 15733 2733 135 33 HD 315 00195 00 o W 00 o sr 00 7 508 INY yl 1 Zin For More Information On This Product 3513 388 5 5273 5 5 2 NOJAVS 1215 0715 8 o oo N 00 7 508 INY 2 9 3 3 q 2 8 V teyopdn 150 294 6 4 30 5 00 10 940 euou oj e 55531 Go to www freescale com H 9 4 j 4 V 9140539 A003l Alddfl5 SBHOLO3NNOO 2078 5 0 E IZ dO 9 13365 10118 A38 SOVnOO9 89W 103 VIOSOLON 1 5 9 za 23503 220 e snoor o me 9
46. 8 pin 2 row pins P4 Connector 37 pin D type male P5 Connector 9 pin D type female P6 Connector 8 pin mini DIN jack P7 Connector 15 pin D type female P8 Connector 8 pin RJ 45 P10 16 wire holes for EEST signals P11 Power connector 3 pin with plug power supply P12 Power connector 2 pin with plug 12v power supply PD1 PD5 Connector 20 pin DIN male Compatible with HP logic analyzers PD6 Connector 96 pin DIN male straight LD1 LD5 LED RED SMD LD7 LD8 LD2 104 LED GREEN SMD LD6 LED YELLOW SMD D1 D2 MBRD620CT diode SMD DZ1 1SMC5 0AT3 SMD DZ2 1SMC12AT3 SMD F1 F2 Fuse block with 5A Fuse Fuse for 5v supply F3 F4 Fuse block with 2A Fuse Fuse for 12v supply SW1 Switch push button SPDT with Red cap SW2 Switch push button SPDT with Orange cap SW3 Switch push button SPDT with Black cap XT1 XT2 Not mounted Used for factory testing XT3 XT4 20 MHz SMD For More Information On This Product Go to www freescale com 53 Freescale Semiconductor Inc 5 User s Manual ADI BOARD INSTALLATION APPENDIX A ADI BOARD INSTALLATION A 1 INTRODUCTION This appendix describes the hardware installation of the ADI board into various host computers The installation instructions cover the following host computers 1 IBM PC XT AT 2 SUN 4 SBus interface A 2 IBM PC XT AT to M68360QUADS Interface The ADI board should be installed in one of the IBM PC XT AT motherboard system expansion slots A singl
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49. ADS 4 GND Ground signal of the M68360QUADS 5 RX Receive Data negative input to the M68360QUADS 6 Transmit Data positive output from the M68360QUADS 7 Not connected 8 Receive Data positive input to the M68360QUADS 47 For More Information On This Product Go to www freescale com 5 2 13 Freescale Semiconductor 36500005 Users Manual SUPPORT INFORMATION Connector P7 Interconnect Signals Connector P7 is 15 pin female D type connector It is the AUI Ethernet port of the M68360QUADS board Table 5 1 describes the P7 connector signals Table 5 13 Connector P7 Interconnect Signals Pin No Signal Name Description 1 GND Ground signal of the M68360QUADS 2 Collision detect positive input to the M68360QUADS 3 Transmit Data positive output from the M68360QUADS 4 GND Ground signal of the M68360QUADS 5 ARX Receive Data positive input to the M68360QUADS 6 GND Ground signal of the M68360QUADS 7 Not connected 8 GND Ground signal of the M68360QUADS 9 ACX Collision detect negative input to the M68360QUADS 10 ATX Transmit Data negative output from the M68360QUADS 11 GND Ground signal of the M68360QUADS 12 ARX Receive Data negative input to the M68360QUADS 13 VPP 412 power supply from the M68360QUADS 14 GND Ground signal of the M68360QUADS 15 Not connected 5 2 14 Connector P8 Interconnect Signals Connector P8 is 8
50. BG 8 BGACK 815 BG 5 EXTBG amp IM BG ENABLE M CS0 L ENABLE E 5 L ENABLENC H ENABLE A28_31 H For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 5 User s Manual 1 28 31 A28 amp 29 amp A30 amp IA31 amp M 50 28 amp A29 amp amp IA31 amp IE 5 28 amp 29 8 A30 amp A31 8 M 50 A28 amp A29 amp A30 amp A31 amp 5 end ARBITER For More Information On This Product Go to www freescale com SUPPORT INFORMATION 67 Freescale Semiconductor NasesoquaADs Users Manual SUPPORT INFORMATION 3 ADI PORT CONTROLLER 043 The PLD chip U43 on schematic sheet 12 is a PAL22V10 25 device used for controlling the ADI port module ADI title ADI AMIR YEHOSHUA MOTOROLA SEMICONDUCTOR ISRAEL LTD 12 12 92 043 device 22 10 ADS_G RSTS HSVCC ADRST 1 2 3 4 ADALL ADBRK HSTEN HSACK 5 6 7 8 HSREQ INACK ADSSEL pin 9 10 13 ADIRD CK_NMI BKCLR pin 14 15 16 ADIAC pin 19 H_RSTH H_RSTS ADI_G ADIDIR pin 20 21 22 23 reset preset Node 25 26 H L X Z C 1 0 X 2 C equations reset L preset L ENABLE ADIDIR H ENABLE ADI_G H ENABLE H_RSTS H ENABLE H_RSTH H ENABLE ADIAC H ENABLE CK_NMI H ENABLE BKCLR H ENABLE ADIRD H RSTS HSTEN amp HSVCC 8 IADRST amp ADSSEL HSTEN amp IHSVCC amp IADR
51. C Table 5 1 describes the P2 connector signals Table 5 8 Connector P2 Interconnect Signals Pin No Signal Name Description A1 A16 15 Port A pins 0 to 15 of the master QUICC A17 VCC 5V 18 21 Parity lines 0 to A22 A23 GND Ground signal of the M68360QUADS 24 A30 IRQ1 IRQ7 Interrupt request signals 1 to 7 of the master QUICC A31 Auto vector pin of the master QUICC A32 GND Ground signal of the M68360QUADS B1 B18 PBO PB17 Port B pins 0 to 17 of the master QUICC B19 GND Ground signal of the M68360QUADS B20 B31 PCO PC11 Port C pins 0 to 11 of the master QUICC B32 GND Ground signal of the M68360QUADS C1 C4 50 CAS3 CAS signals 0 to of the master QUICC C5 VCC 5V C6 C13 CS0 CS7 Chip select signals 0 to 7 of the master QUICC C14 GND Ground signal of the M68360QUADS C15 FREEZE FREEZE pin of the master QUICC C16 TCK TCK pin of the master QUICC C17 TMS TMS pin of the master QUICC C18 TDI TDI pin of the master QUICC C19 TDO TDO pin of the master QUICC C20 TRST TRST pin of the master QUICC C21 Breakpoint pin of the master QUICC C22 RESETH Hard reset pin of the master QUICC C23 RESETS Soft reset pin of the master QUICC C24 IFETCH Instruction fetch pin of the master QUICC C25 VCC 5V C26 IPIPEO Instruction pipe 0 pin of the master QUICC C2
52. ED DOCUMENTATION The following publications are applicable to the M68360QUADS and may provide additional helpful information e MC68360 QUICC User s Manual e MC68160 EEST User s Manual 1 7 ABBREVIATIONS USED IN THE DOCUMENT QUICC QUad Integrated Communications Controller MC68360 device e EEST Enhanced Ethernet Serial Transceiver MC68160 device QUADS Application Development System for the QUICC device ADI Application Development Interface UART Universal Asynchronous Receiver Transmitter Background Debug Mode e SIMM Single In line Memory Module Attachment Unit Interface TP Twisted Pair spec Engineering specification document nsec nano second e usec micro second NMI Non Maskable Interrupt 1 8 REQUIRED EQUIPMENT The M68360QUADS can operate in two working environments Host controlled Stand alone In both operating modes it is possible to use only 5V power supply The 12V power supply is required only if desired on the AUI port or when programming the Flash Memory Most AUI Hubs do not require 12 V supplies to be provided by the network termination equipment For More Information On This Product Go to www freescale com Freescale Semiconductor Inc y68360QUADS User s Manual GENERAL INFORMATION 1 8 1 Host controlled setup FIGURE 1 1 describes the setup of the host controlled mode of operation The required equipment in this mode is
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54. Freescale Semiconductor Inc 5 User s Manual M68360QUADS Hardware User s Manual Revision 1 August 16 1993 For More Information On This Product Go to www freescale com 1 1 Freescale Semiconductor NaesoQuADs Users Manual GENERAL INFORMATION CHAPTER 1 GENERAL INFORMATION INTRODUCTION This manual provides general information preparation for use and installation instructions operating instructions functional description and support information for the M68360QUADS QUICC Application Development System board 1 2 FEATURES The main features of the QUADS board are as follows Master QUICC MC68360 with 32 bit address 32 or 16 bit data 25 MHz 1 Mbyte Dynamic RAM 36 bits wide data and parity SIMM 128 Kbyte boot EPROM 8 bits wide 512 Kbyte Flash Memory 32 bits wide 256 byte serial EEPROM Application Development Interface ADI port connector Serial port with RS 232 connector to terminal or to host computer AppleTalk serial connector BDM Controller capability for external QUICC device Ethernet interface twisted pair and AUI using Motorola MC68160 Expansion connectors providing all the signals of the master QUICC Logic analyzer connectors compatible with HP logic analyzers BDM connector for the master QUICC Slave QUICC core disabled providing the following functions 1 DRAM Controller Chip Select and DSACK generator Parallel port ADI UART for terminal or host computer conn
55. ICC unbuffered 14 D5 Data line 5 of the master QUICC unbuffered 15 4 Data line 4 of the master QUICC unbuffered 16 D3 Data line 3 of the master QUICC unbuffered 17 D2 Data line 2 of the master QUICC unbuffered 18 D1 Data line 1 of the master QUICC unbuffered 19 DO Data line 0 of the master QUICC unbuffered 20 GND Ground signal of the M68360QUADS 5 2 4 Connector PD4 Interconnect Signals Connector PD4 is a double row 20 pin male connector The higher 16 data lines of the master QUICC appear on this connector for easy monitoring of the bus by a logic analyzer Table 5 1 describes the connector signals Table 5 4 Connector 4 Interconnect Signals 1 Not connected 2 Not connected 3 DS Data Strobe line of the master QUICC 4 031 Data line 31 of the master QUICC unbuffered 5 D30 Data line 30 of the master QUICC unbuffered 6 D29 Data line 29 of the master QUICC unbuffered 7 D28 Data line 28 of the master QUICC unbuffered 8 D27 Data line 27 of the master QUICC unbuffered 41 For More Information On This Product Go to www freescale com Freescale Semiconductor NaesoquaDs Users Manual SUPPORT INFORMATION Table 5 4 Connector PD4 Interconnect Signals Pin No Signal Name Description 9 D26 Data line 26 of the master QUICC unbuffered 10 D25 Data line 25 of the master QUICC unbuffered 11 D24 Data line
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57. N AND INSTALLATION 2 4 INSTALLATION INSTRUCTIONS When the M68360QUADS has been configured as desired by the user it can be installed according to the required working environment as follows 2 4 1 5V Power Supply Connection The M68360QUADS requires 5 Vdc 5 A max power supply for operation The QUADS has fuses on the 5V and its ground and it is protected against reverse connection of the power supply Connect the 5V power supply to connector P11 as shown below FIGURE 2 3 P11 5V Power Connector VCC 109 Gnd 203 Gni SS P11 is a terminal block power connector with power plug The plug is designed to accept 14 to 22 AWG wires It is recommended to use 14 to 18 AWG wires To insure solid ground two Gnd terminals are supplied It is recommended to connect both Gnd wires to the common of the power supply while VCC is connected with a single wire NOTE Since hardware applications can be connected to the M68360QUADS using the expansion connectors P1 and P2 the additional power consumption should be taken into consideration when a power supply is connected to the QUADS 2 4 2 12V Power Supply Connection The M68360QUADS requires 12 Vdc 1 A max power supply for the Ethernet AUI port and for programming the Flash Memory devices The QUADS can work properly without the 12 power supply if the AUI port is not in use or if the AUI port is used with an AUI hub that does not requ
58. Q4 Q1 5 RST CIN Q4 Q0 5 RST CIN Q4 Q3 Q2 Q1 QO 5 RST CIN Q4 5 RST CIN Q4 TRST VCC Q5 Q5 Q4 S RST CIN Q5 Q3 S_RST CIN Q5 Q2 S_RST CIN Q5 Q1 S_RST CIN Q5 Q0 S_RST CIN Q5 04 Q2 Q1 Q0 5 RST CIN Q5 S_RST CIN Q5 TRST VCC For More Information On This Product Go to www freescale com SUPPORT INFORMATION 71 72 Freescale Semiconductor NaesoQuADs Users Manual SUPPORT INFORMATION CONF2 00 Q1 Q2 037 Q4 Q5 CONF2 TRST RESETH GLOBAL SETF GND GLOBAL RSTF GND For More Information On This Product Go to www freescale com H 9 j 9142539 A0031 X09008 5 ban L iZ 30 133HS 10114 SOVNOOISBOW 9500 0 144 VIONOLON 28 4 5700 050 29 zeo 0 620 _ 09 200 t d 820 BS 2 5 n 201 99 5000 OLON 920 vg 8200 920 29 szo 4290 BON P 9200 5 Ald 9750 M 5 200 10 Ly zzo 527290 o 120 5008 NESY2 Ey 059 x 6200 2592 E 020 18 1599 50 6
59. QUICC peripherals One of the DMA channels DRAM refresh etc The master QUICC is the local bus master during normal operation The Local Bus Arbiter 042 in sheet 9 is PAL16R4 device that uses the master QUICC arbitration logic to transfer the bus mastership to other masters The M68360QUADS has provision for the user to connect External Bus Master device to the local bus through the Expansion Connectors P1 and P2 The relevant control signals EXTBR EXTBG and BGACK appear on connector P1 The arbitration priority from highest to lowest is slave QUICC External Bus Master and master QUICC The Bus Arbiter output signal DIR controls the direction of the address bus transceivers 07 06 05 U28 U14 and U21 in sheet 5 between the master QUICC and the other devices on the QUADS 042 also generates the output signal A28 31 which is used by the data bus controller to determine the direction of the data bus transceivers 4 9 DATA BUS CONTROLLER Sheet 8 The data and parity bus transceivers U20 U15 U32 U12 U25 U13 U11 U18 and U19 in sheet 6 are controlled by a GAL22V10 device U51 in sheet 8 U51 also generates the Byte Enable signals according to the accessed address and the data size The signals CS7 of the slave QUICC and A28 31 of U42 are used to indicate if the current access is to one of the devices on the QUADS The CS7 signal is programmed for the address range 00000000 to OFFFFFFF hexadecimal with its DSACK g
60. ST amp IADALL RSTH HSTEN amp IHSVCC amp IADRST amp ADSSEL amp INACK HSTEN amp IHSVCC amp IADRST amp IADALL amp CK HSTEN IHSVCC amp IADBRK amp ADSSEL HSTEN amp IHSVCC amp IADBRK amp ADALL 68 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 5 User s Manual SUPPORT INFORMATION IBKCLR IRSTS amp HSTEN amp 5 amp ADSSEL IADIRD HSTEN amp ADSSEL amp IHSVCC IADI G IHSTEN HSVCC 8 ADSSEL ADALL amp IHSACK ADS IADIAC HSTEN HSVCC amp IHSREQ amp ADALL HSTEN amp 5 amp IHSREQ amp ADSSEL HSTEN HSVCC amp IHSACK ADSSEL IADIDIR IHSTEN ADS G ADSSEL HSACK end ADI 69 For More Information On This Product Go to www freescale com Freescale Semiconductor NaesoQuADs Users Manual SUPPORT INFORMATION C 4 Disable CPU Configuration for Slave QUICC SP1 The PLD chip SP1 on schematic sheet 15 is a PAL22V10 25 device that operates during hard reset and it is used to configure the slave QUICC in disable CPU operation mode To disable the CPU in the QUICC device the encoding of its configuration pins must enable the CPU for more than 32 clocks during hard reset and then they must be encoded according to the required operation mode before the hard reset signal is
61. ST TRST pin of the master QUICC C21 Breakpoint pin of the master QUICC C22 RESETH Hard reset pin of the master QUICC C23 RESETS Soft reset pin of the master QUICC C24 CONFIGO RMC CONFIGO pin of the master QUICC C25 CONFIG1 of the master QUICC C26 TRIS TRIS pin of the master QUICC C27 MODCKO Clock mode select 0 pin of the master QUICC C28 MODCK1 Clock mode select 1 pin of the master QUICC C29 GND Ground signal of the M68360QUADS C30 CLKO2 System clock out 2 pin of the master QUICC 50 MHz C31 GND Ground signal of the M68360QUADS C32 CLK2 The operating clock of the M68360QUADS 25 MHz 43 For More Information On This Product Go to www freescale com 5 2 7 Freescale Semiconductor NaesoQuADs Users Manual SUPPORT INFORMATION Connector P1 Interconnect Signals Connector P1 is a triple row 96 pin female DIN connector P1 and P2 expansion connectors provide all the signals of the master QUICC Table 5 1 describes the P1 connector signals Table 5 7 Connector P1 Interconnect Signals Pin No Signal Name Description A1 A32 A31 Address lines 0 to 31 of the master QUICC B1 B32 DO D31 Data lines 0 to 31 of the master QUICC 1 04 FCO FC3 Function code lines 0 to 3 of the master QUICC C5 AMUX AMUX OE pin of the master QUICC C6 C7 SIZO SIZ1 Transfer Size 0 and 1 lines of the
62. ST BRK Gnd 32 33 14 ADS 16 PD2 35 PD4 36 17 583 PDS 37 19 m NOTE Pin 26 on the ADI is connected to 12 v power supply but it is not used in the QUADS 2 4 5 Terminal to M68360QUADS RS 232 Connection In the stand alone operation mode a VT100 compatible terminal should be connected to the RS 232 connector P5 The RS 232 connector is a 9 pin female D type connector as shown in FIGURE 4 3 FIGURE 2 6 RS 232 Serial Port Connector 25 CD 1 R x tem 9 GND 5 NOTE The RTS line pin 7 is not connected in the M68360QUADS 13 For More Information On This Product Go to www freescale com Freescale Semiconductor NaesoquADs Users Manual OPERATING INSTRUCTIONS CHAPTER 3 OPERATING INSTRUCTIONS 3 1 INTRODUCTION This chapter provides necessary information to use the M68360QUADS in host controlled and stand alone configurations This includes controls and indicators memory map details and software initialization of the board 3 2 CONTROLS AND INDICATORS The M68360QUADS has the following switches and indicators 3 2 1 HARD RESET Switch SW1 The HARD RESET switch SW1 resets all QUADS devices and performs hard reset to the QUICC devices The switch signal is debounced and it is not possible to disable it by software This switch must be pressed along with the SOFT RESET switch to activate the hard reset mechanism No action is taken i
63. als RAS1DD and RAS2DD also drive the DRAM to decrease signal load 4 7 2 Chip Select and DSACK generator The slave QUICC device provides the Chip Select signals to the QUADS devices as follows 1 50 pin of the slave QUICC is not connected to any device on the QUADS but its function is used along with CS7 by the bus control logic to distinguish between accesses to the board devices and external devices that may be attached to the board 2 CS1 and CS2 are connected to the DRAM SIMM and they act as RAS1 and RAS2 3 CS3 is connected to the Flash Memory 972 073 074 and 075 in sheet 2 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc M68360QUADS User s Manual FUNCTIONAL DESCRIPTION 4 CS4 is connected to the M68360QUADS Status Register 061 and 039 in sheet 14 5 CSb5 is connected to the Abort and Host NMI registers 068 in sheet 7 and 031 in sheet 12 This signal is used to clear these registers after interrupt level 7 6 CS6 is connected to the Enable Address register U22 in sheet 5 This signal is used to enable using A 31 28 lines of the master QUICC as address lines on the QUADS 7 CS7 is connected to the Bus Controller 051 in sheet 8 If this signal is negated it indicates that the current access is to a device on the QUADS The DSACK generator is disabled for this signal 4 2 3 Port Sheet 12 The ADI parallel port supplie
64. ardware preparation and installation instructions for the M68360QUADS 2 2 UNPACKING INSTRUCTIONS NOTE If the shipping carton is damaged upon receipt request carriers agent be present during unpacking and inspection of equipment Unpack equipment from shipping carton Refer to packing list and verify that all items are present Save packing material for storing and reshipping of equipment CAUTION AVOID TOUCHING AREAS OF INTEGRATED CIRCUITRY 5 DISCHARGE DAMAGE CIRCUITS 2 3 HARDWARE PREPARATION To select the desired configuration and ensure proper operation of the M68360QUADS board changes of the Dip Switch settings may be required before installation The location of the switches LEDs Dip Switches and connectors is illustrated in FIGURE 2 1 The board has been factory tested and is shipped with Dip Switch settings as described in the following paragraphs Parameters can be changed for the following conditions ADI port address Dip Switch 046 Enable Disable of the following devices on the QUADS Dip Switch 052 Slave QUICC EPROM DRAM Flash Memory Clock Generator Interrupt Generator Operation mode of the Master QUICC Dip Switch U52 Configuring A 31 28 as address lines or write enables Data bus width 32 or 16 bits For More Information On This Product Go to www freescale com HARDWARE PREPARATION AND INSTALLATION Freescale Semiconductor NaesoqQuADs Users Manua
65. as follows e 45V 5A power supply e 12V power supply optional Host Computer one of the following o Sun 4 SBus interface o IBM PC XT AT ADI board compatible with the host computer 37 line flat cable with female 37 pin D type connectors on each end FIGURE 1 1 Host Controlled Configuration 12 5 power supply power supply HOST COMPUTER P12 P11 M68360QUADS P4 Ee 37 LINE FLAT CABLE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc y68360QUADS User s Manual GENERAL INFORMATION 1 8 2 Stand alone setup FIGURE 1 2 describes the setup of the stand alone mode of operation The required equipment in this mode are as follows e 45V 5A power supply e 12 power supply optional e VT100 compatible terminal e RS 232 cable with male 9 pin D type connector the QUADS side FIGURE 1 2 Stand alone Configuration 12 5 power supply power supply VT100 compatible terminal C P12 P11 M68360QUADS RS 232 CABLE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc y68360QUADS User s Manual HARDWARE PREPARATION AND INSTALLATION CHAPTER 2 HARDWARE PREPARATION AND INSTALLATION 2 1 INTRODUCTION This chapter provides unpacking instructions h
66. ates a host to QUADS write cycle ADS ACK O This signal is the QUADS response to the HOST REQ signal indicating that the QUADS board has detected the assertion of HOST REQ ADS REQ O This signal initiates an QUADS to host write cycle e This signal serves as the host s response to the ADS REQ signal HOST BRK O This open collector signal generates an interrupt to the host This signal is common to all QUADS boards that are connected to the same ADI ADS INT O This line is polled by the host computer during its interrupt acknowledge cycle to determine which QUADS board has generated the interrupt INT This line is asserted by the host at the end of its interrupt acknowledge cycle This signal is used by the QUADS hardware to negate the HOST signal The software the QUADS must negate the ADS INT signal upon detecting the assertion of INT ACK to support the daisy chain interrupt structure This line is also used by the host to generate either hard reset or soft reset In this case this line is used in conjunction with ADS RESET and with either the addressing lines or with the ADS ALL line For More Information On This Product Go to www freescale com 4 7 4 Freescale Semiconductor Inc 5 Users Manual FUNCTIONAL DESCRIPTION HOST three lines These lines are power lines from the host computer In the QUADS these lines are used by th
67. ation On This Product Go to www freescale com 5 2 6 Freescale Semiconductor Inc M68360QUADS User s Manual SUPPORT INFORMATION Connector PD6 Interconnect Signals Connector PD6 is a triple row 96 pin male DIN connector The remaining signals of the master QUICC appear on this connector Table 5 1 describes the connector signals Table 5 6 Connector PD6 Interconnect Signals Pin No Signal Name Description A1 A16 15 Port A pins 0 to 15 of the master QUICC A17 VCC 5V 18 21 Parity lines 0 to A22 A23 GND Ground signal of the M68360QUADS 24 A30 IRQ1 IRQ7 Interrupt request signals 1 to 7 of the master QUICC A31 Auto vector pin of the master QUICC A32 GND Ground signal of the M68360QUADS B1 B18 PBO PB17 Port B pins 0 to 17 of the master QUICC B19 GND Ground signal of the M68360QUADS B20 B31 PCO PC11 Port C pins 0 to 11 of the master QUICC B32 GND Ground signal of the M68360QUADS C1 C4 50 CAS3 CAS signals 0 to of the master QUICC C5 VCC 5V C6 C13 50 CS7 Chip select signals 0 to 7 of the master QUICC C14 HALT HALT pin of the master QUICC C15 AMUX AMUX OE pin of the master QUICC C16 TCK TCK pin of the master QUICC C17 TMS TMS pin of the master QUICC C18 TDI TDI pin of the master QUICC C19 TDO TDO pin of the master QUICC C20 TR
68. au Kxo o5 Go to www freescale com P H 9 4 j 4 V 9140539 20031 YSLdNYYSINI 40018 5 1 IZ dO 13365 10118 A38 SOVnOO9 89W 193 0 8 V IOSOLON 5 oon 3 5 n 5 SOS v7 9 gon C oan 7 H a cost 6 120 09197 5190 8 50 oon o 8 5 61150 Lg 605191 79 5 710 00 1180 lt 1 B ov 01101 SOS tee 888381 99 C oun 1 z lt S05 17 a yon 2 C Tun zi G0 WA o Lu e ksi led ss e E n 004 1 H 9 8 V oje 555 5 0 71 6 CC 1018 28 8 0 991 0 106 Go to www freescale com
69. ave QUICC and to the RENA output of the EEST 6 Ethernet RCLK This pin is connected to Port A pin 9 in the slave QUICC and to the RCLK output of the EEST 7 CLSN This pin is connected to Port C pin 4 in the slave QUICC and to the CLSN output of the EEST 8 EEST CSO This pin is connected to the EEST CSO input pin This signal is not driven by the slave QUICC and it is connected to pull up resistor 9 EEST CS1 This pin is connected to the EEST CS1 input pin This signal is not driven by the slave QUICC and it is connected to pull up resistor 49 For More Information On This Product Go to www freescale com Freescale Semiconductor 36500005 Users Manual SUPPORT INFORMATION Table 5 16 Connector P10 Interconnect Signals Pin No Signal Name Description 10 EEST CS2 This pin is connected to Port C pin 2 in the slave QUICC and to the CS2 input of the EEST 11 TPEN This pin is connected to Port C pin in the slave QUICC and to the I O pin of the EEST 12 APORT This pin is connected to Port C pin 7 in the slave QUICC and to the APORT input of the EEST 13 TPAPCE This pin is connected to Port C pin 8 in the slave QUICC and to the TPAPCE input of the EEST 14 TPSQEL This pin is connected to Port C pin 9 in the slave QUICC and to the TPSQEL input of the EEST 15 TPFULDL This pin is connected to Port C pin 10 in the slave QUICC and to the TPFULDL input of the EEST 16 LOOP This pin is conne
70. board P10 is 16 wire holes on the board The signals between the slave QUICC and the EEST appear on P10 for internal factory debugging purposes P11 is 3 pin connector for 5v power supply input GND x2 and 5V P12 is 2 pin connector for 12v power supply input GND and 12V Connector PD1 Interconnect Signals Connector PD1 is a double row 20 pin male connector The lower 16 address lines of the master QUICC appear on this connector for easy monitoring of the bus by a logic analyzer Table 5 1 describes the connector signals Table 5 1 Connector PD1 Interconnect Signals Pin No Signal Name Description 1 Not connected 2 Not connected 4 A15 Address line 15 of the master QUICC unbuffered 5 Address line 14 of the master QUICC unbuffered 6 A13 Address line 13 of the master QUICC unbuffered 8 A11 Address line 11 of the master QUICC unbuffered 39 For More Information On This Product Go to www freescale com Freescale Semiconductor NaesoquaADs Users Manual SUPPORT INFORMATION Table 5 1 Connector PD1 Interconnect Signals Pin No SignalName Description 10 A9 Address line 9 of the master QUICC unbuffered 11 A8 Address line 8 of the master QUICC unbuffered 12 Address line 7 of the master QUICC unbuffered 13 Address line 6 of the master QUICC unbuffered 14 A5 Address line 5 of the master QUICC unbuffered 15
71. ccesses to the Flash Memory on the QUADS If it is 0 the Flash is enabled 8 Ethernet TCLK This pin is connected to the transmit clock output of the EEST It is configured as the transmit clock of in the slave QUICC 9 Ethernet RCLK This pin is connected to the receive clock output of the EEST It is configured as the receive clock of SCC1 in the slave QUICC 10 ADS G This pin is connected to the ADI port logic It is configured as output pin in the slave QUICC and it is used by the ADI logic to control the ADI data transceiver 11 ADS INT This pin is connected to the ADI port signal ADS INT through the buffer U16 It is configured as output pin in the slave QUICC and it is also used by the ADI logic to interrupt the host computer 12 ADS ACK This pin is connected to the ADI port signal ADS through the buffer 016 It is configured as output pin in the slave QUICC 13 ADS REQ This pin is connected to the ADI port signal 05 REQ through the buffer 016 It is configured as output pin in the slave QUICC 14 VPP ON This pin is configured as input pin and it is used to sense the 12 power supply If it is 1 12V is applied to the QUADS 15 Spare This pin is connected to switch 4 of dip switch U46 and it is configured as input pin in the slave QUICC It has no function on the ADS and it is reserved for future applications 32 For More Information On This Product Go to www freescale com Freescale Semicon
72. ct Go to www freescale com lost updote 25 95 15 58 22 APR 93 14 59 goloxy amiry QUICC ods schem pilot 4 drw Freescale Semiconductor Inc D g 0 A 2 1 E 5 doge gt gt gt 5 wuja gt amp 51518919185 ilz i amp a cE ce ce OTS be 23333352 9722 A 92 2 2 22 2 RI gt 5 222 2 i uci 5138 SP 524252452 44444 1515 renont 555 gt gu Lo qus O amp a 8 m uggg m 56 SESVO 517 5141 6590 in 12507 9 8 SEXOVI 1592 MM gig 1 Bald 9 wOSVO 915 0507 0344 45 875452 5 gin 587 134 95 875 952 EE fig 323384 95 8 952 HIE wVSVE 0752 2151 eg ON 650 112 xus LON NCSVU 252 5 zu L ZON 15 87 152 acu eve iei 05074 22 uio 11087 70
73. cted to Port C pin 11 in the slave QUICC and to the LOOP input of the EEST 5 2 17 Connector P11 Interconnect Signals Connector P11 is 3 pin connector for 5v power supply The connector is supplied with 3 pin plug for convenient connection to the power supply Table 5 1 describes the P11 connector signals Table 5 17 Connector P11 Interconnect Signals Pin No Signal Name Description 1 VCC 5V connection to the power supply 2 GND Ground connection to the power supply 3 GND Ground connection to the power supply 5 2 18 Connector P12 Interconnect Signals Connector P12 is 2 pin connector for 12v power supply The connector is supplied with 2 pin plug for convenient connection to the power supply Table 5 1 describes the P12 connector signals Table 5 18 Connector P12 Interconnect Signals Pin No Signal Name Description 1 VPP 12V connection to the power supply 2 GND Ground connection to the power supply 50 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc y68360QUADS User s Manual SUPPORT INFORMATION 5 3 M68360QUADS Parts List The components of the M68360QUADS and their reference designation are listed in Table 5 19 Table 5 19 Parts List 2 Part Description Notes U1 U3 Resistor Network 16 pins 22 ohm SMD U2 74LS24
74. dicated functions of the pin The PADIR must be initialized to 3CO0 3 5 19 Port A Pin Assignment Register The port A pin assignment register PAPAR configures the function of the port pins If the value in the PAPAR for a pin is 0 the pin is general purpose otherwise the pin is dedicated peripheral interface pin The PAPAR must be initialized to 3 5 20 Port B Open Drain Register Port B of the slave QUICC is 18 pins port and each pin may be configured as general purpose pin or as dedicated peripheral interface pin The port B open drain register PBODR configures the drivers of port B pins as open drain or as active drivers The PBODR must be initialized to 0000 to select the active drivers configuration 3 5 21 Port B Data Register Port B data register PBDAT can be read to check the data at the pin If a port pin is configured as general purpose output pin the value in the PBDAT for that pin is driven onto the pin It is recommended to initialize PBDAT to 3FFFF before configuring the other port registers 21 For More Information On This Product Go to www freescale com Freescale Semiconductor 1 36500005 Users Manual OPERATING INSTRUCTIONS 3 5 22 Port B Data Direction Register The port B data direction register PBDIR has different functions according to the configuration of the port pins If a pin is general purpose 1 pin the value in the PBDIR for that pin defines the direction of t
75. driving the CONFIGO pin For More Information On This Product Go to www freescale com 5 1 Freescale Semiconductor Inc 5 User s Manual SUPPORT INFORMATION CHAPTER 5 SUPPORT INFORMATION INTRODUCTION This chapter provides the interconnection signals parts list and schematic diagrams of the M68360QUADS board 5 2 INTERCONNECT SIGNALS The M68360QUADS board interconnects with external devices through the following connectors 5 2 1 PD1 PD5 are five 20 pin male connectors compatible with HP logic analyzer connectors that provides the bus signals of the master QUICC for bus monitoring PD6 is 96 pin male logic analyzer connector providing the remaining signals of the master QUICC P1 and P2 are two 96 pin female expansion connectors providing all the signals of the master QUICC for connection to the user hardware application is 8 pin male connector connected to the BDM pins of the master QUICC P4 is 37 pin male D type connector for the ADI port P5 is 9 pin female D type connector for the RS 232 port P6 is 8 pin MINI DIN JACK connector for the AppleTalk port P7 is 15 pin female D type connector for AUI connection to the Ethernet port P8 is 8 pin RJ 45 connector for twisted pair connection to the Ethernet port P9 is 8 pin male connector It is the BDM controller connector that enables the QUADS to control the activity of external QUICC mounted on the user application
76. ductor Inc 5 Users Manual FUNCTIONAL DESCRIPTION 4 7 9 2 Slave QUICC Port B Port B is 18 pins port Table 4 2 describes the configuration of port B Table 4 3 Port B Pins Description Pin Pin Name Description 0 This pin is connected to the select input of the EEPROM and it is configured as Select output pin in the slave QUICC 1 EEPROM CLK This pin is connected to the clock input of the EEPROM and it is configured as the SPI clock of the slave QUICC 2 EEPROM This pin is connected to the serial data input of the EEPROM and it is configured as Serial In the SPI MOSI of the slave QUICC 3 EEPROM This pin is connected to the serial data output of the EEPROM and it is configured as Serial Out the SPI MISO of the slave QUICC 4 BDM CLK This pin is connected to the BDM Controller connector P9 It is configured as output pin in the slave QUICC 5 BDM Reset This pin is connected to the BDM Controller connector P9 It is configured as output pin in the slave QUICC 6 BDM Data Out This pin is connected to the BDM Controller connector P9 It is configured as output pin in the slave QUICC 7 BDM Data In This pin is connected to the BDM Controller connector P9 It is configured as input pin in the slave QUICC 8 This pin is not connected on the QUADS board 9 BDM Freeze This pin is connected to the BDM Controller connector P9 It is configured as input pin i
77. e software to determine if the host computer is powered on The QUADS does not use these lines for power supply PD 0 7 These eight I O lines are the parallel data bus This bus is used to transmit and receive data from the host computer RS 232 Serial Port Sheet 11 The serial port is provided by the slave QUICC SCC3 serial channel The M68360QUADS can be connected to a VT100 compatible terminal or to a host computer through the serial port The RS 232 serial port connector P5 is a 9 pin female D type connector as shown in FIGURE 4 3 4 7 4 1 FIGURE 4 3 RS 232 Serial Port Connector CD TX RX DTR GND DSR RTS CTS N C ak WD ON RS 232 Port Signal Description In the list below the directions O and I O are relative to the QUADS board I E l means input to the QUADS 4 7 5 CD Data Carrier Detect This line is always asserted by the QUADS TX Transmit Data RX 1 Receive Data DTR 1 Data Terminal Ready This signal is used by the software in the QUADS to detect if terminal is connected to the QUADS board DSR Data Set Ready This line is always asserted by the QUADS RTS 1 Request To Send This line is not connected in the QUADS CTS O Clear To Send This line is always asserted by the QUADS AppleTalk Port Sheet 11 The AppleTalk port is provided by the slave QUICC SCC2 serial channel The AppleTalk is the 230 4 kbps
78. e ADI can control up to eight M68360QUADS boards The ADI address in the computer is configured to be at I O memory addresses 100 102 hex but it may be reconfigured for an alternate address space CAUTION BEFORE REMOVING OR INSTALLING ANY EQUIPMENT IN THE IBM PC XT AT COMPUTER TURN THE POWER OFF AND REMOVE THE POWER CORD 2 1 ADI Installation IBM PC XT AT Refer to the appropriate Installation and Setup manual of the IBM PC XT AT computer for instructions on removing the computer cover The ADI board address block should be configured at a free 1 address space in the computer The address must be unique and it must not fall within the address range of another card installed in the computer The ADI board address block can be configured to start at one of the three following addresses e 100 This address is unassigned in the IBM PC 200 This address is usually used for the game port e 300 This address is defined as a prototype port The ADI board is factory configured for address decoding at 100 102 hex in the IBM PC XT AT address map These are undefined peripheral addresses 54 For More Information On This Product Go to www freescale com M68360QUADS Users Manual Freescale Semiconductor Inc ADI BOARD INSTALLATION FIGURE A 1 Physical Location of jumper JG1 and JG2 JG1 JG2 NOTE Jumper JG2 should be left unconnected The following figure shows the required jumpe
79. e TP P8 port or a jabber condition is detected in TP mode For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 5 User s Manual OPERATING INSTRUCTIONS 3 2 9 Ethernet TPLIL Indicator LD6 The yellow LED Ethernet Twisted Pair Link Integrity indicator LD6 lights to indicate good link integrity on the TP P8 port The LED is off when the link integrity fails or when the AUI port is selected 3 2 10 Ethernet TPPLR Indicator LD7 The red LED Ethernet TP Polarity indicator LD7 lights if the wires connected to the receiver input of TP P8 port are reversed The LED is lit by the EEST and remains on when the EEST has automatically corrected for the reversed wires 3 2 11 Ethernet TPJABB Indicator LD8 The red LED Ethernet TP Jabber indicator LD8 lights whenever a jabber condition is detected on the TP P8 port 3 3 MEMORY MAP At the beginning of each cycle the chip select generators of the master QUICC and the slave QUICC determine what kind of memory cycle takes place and which device is selected Cycle types and address spaces are determined by the function code lines FC3 FCO The cycle types and the devices that respond are described in Table 3 1 Table 3 1 Cycle Types and Responding Devices FC3 FCO Address Space Responding Devices 0000 Reserved None 0001 User Data All 0010 User Program All 0011 Reserved None 0100 Reserved None 0101 Supervisor Data Al
80. ection AppleTalk controller for Macintosh computer connection BDM controller to other QUICC devices Ethernet controller Serial EEPROM interface General Purpose I O signals HARD RESET SOFT RESET and ABORT switches Status LEDs for RUN HALT and Ethernet interface 5Vdc and 12Vdc power supply For More Information On This Product Go to www freescale com Freescale Semiconductor Inc y68360QUADS User s Manual GENERAL INFORMATION 1 3 SPECIFICATIONS The M68360QUADS specifications are given in Table 1 1 Paragraph 1 4 details the cooling requirements Table 1 1 M68360QUADS Specifications CHARACTERISTICS SPECIFICATIONS Power requirements no other boards attached 5Vdc 3 5 A typical 5 A maximum 12Vdc 1 A maximum Microprocessor MC68360 25 MHz Addressing Total address range on and off board 4 gigabytes Boot EPROM 128 KByte 8 bits wide Flash Memory 512 KByte 32 bits wide Dynamic RAM 1 MByte 36 bits wide SIMM 32 bit data 4 bit parity option to use higher density SIMM up to 8 MByte EEPROM 256 Byte serial EEPROM Operating temperature 0 degrees to 30 degrees C ambient air temperature Storage temperature 25 degrees to 85 degrees C Relative humidity 59610 9096 non condensing Dimensions Height 9 173 inches 233 mm Depth 7 087 inches 180 mm Thickness 0 063 inches 1 6 mm 1 4 COOLING REQUIREMENTS The M68360QUADS is specified designed and tes
81. ed location in KO0OSFFO04 in the CPU space Before accessing the MBAR the software must write to the module base address register enable MBARE which resides at fixed location in 0003 8 in the CPU space The MBARE pin of the slave QUICC is connected to data line D30 therefore the MBARE register must be initialized to BFFFFFFF before initializing the MBAR The MBAR must be initialized to 00022001 to obtain the memory map as described in Table 3 2 Note If the master QUICC data bus is configured to operate 16 bit mode the MBARE must be written with BFFF before each word access to the MBAR 3 5 2 Module Configuration Register The module configuration register MCR controls the SIM60 configuration in the slave QUICC The BSTM bit in the MCR must be set to 0 This setting will enable using asynchronous timing on the bus signals 3 5 3 CLKO Control Register The CLKO control register CLKOCR controls the operation of the CLKO 0 1 pins This register must be initialized to AF so that the CLKO 0 1 pins of the slave QUICC are disabled 3 5 4 PLL Control Register The PLL control register PLLCR controls the operation of the PLL There is no need to program the PLLCR after hard reset because the configuration of the MODCK 0 1 pins on the QUADS determines its value It is recommended to set the PLLWR bit to prevent accidental writing For More Information On This Product Go to www freesca
82. ed to control accesses 10 the EEPROM The 2814 has internal hardware protection against inadvertent writes to the EEPROM that might happen at power up or power down time 4 6 DRAM The QUADS is supplied with 1 Mbyte of Dynamic RAM which is implemented by the 36256580 DRAM module The module U71 in sheet 1 is a 72 lead SIMM 80 nsec access time organized as 256K x 36 bit for data and parity signals It is possible to replace the supplied DRAM SIMM with a higher density module in order to increase the DRAM memory space up to 8 Mbyte The higher density modules such as the MCM36200 may require using RAS1 and RAS2 signals of the slave QUICC because they are organized as two memory banks These signals are supplied to the DRAM socket in the QUADS so that the user does not need to do any wiring The SIMM has four presence detect signals SIMM1 to 51 4 which can be read by the software through the Status Register 961 and 039 in sheet 14 The CPU32bug software determines the DRAM memory space and access time according to these signals as described in Table 4 1 Table 4 1 DRAM SIMM Types SIMM 4 1 SIMM Type SIMM Organization 0000 MCM36100S10 1M x 36 100 51 0001 MCM36512S10 512K x 36 100 RAS1 RAS2 0010 36256510 256 36 100 51 0011 36200510 2 36 100 RAS1 0100 36100580 1 36 80 RASI 0101 36512580 512
83. enerator disabled The signal CS0 of the slave QUICC is programmed to cover the address range of the Boot EPROM so that CS7 is not asserted if the EPROM is accessed CS7 is asserted if none of the slave QUICC chip select signals is asserted so If CS7 is asserted low this indicates that the accessed device is not on the QUADS board The A28 31 signal is high if any of the upper four address bits A28 to A31 is high or if external EPROM is accessed instead of the M68360QUADS Boot EPROM If A28 31 is high it indicates that the accessed device is not on the QUADS board The GAL22V10 device also control the data bus swapping if the master QUICC is configured to operate in 16 bits mode 4 10 Status Register Sheet 14 M68360QUADS Status Register consists of two 7415373 devices 061 039 in sheet 14 that form 16 bit read only device The register in controlled by CS4 of the slave QUICC For More Information On This Product Go to www freescale com 35 Freescale Semiconductor 36500005 Users Manual FUNCTIONAL DESCRIPTION The Status Register bits are described in Table 4 5 below Table 4 5 Status Register Description Description 0 Data Bus Configuration This bit indicates the operation mode of the master QUICC data bus If it is the data bus is in 32 bit mode If it is 0 the data bus is in 16 bit mode 1 Interrupt Enable This bit indicates if
84. er QUICC The master QUICC internal registers must be programmed after hardware reset as described in the following paragraphs The addresses and programming values are in hexadecimal base Please refer to the MC68360 QUICC User s Manual for more information 3 4 1 Module Base Address Register The master QUICC s module base address register MBAR controls the location of its internal memory and registers and their access space The master QUICC MBAR resides at a fixed location in 0003FFO00 in the CPU space The MBAR must be initialized to 00020001 to obtain the memory map as described in Table 3 2 3 4 2 Module Configuration Register The MCR controls the SIM60 configuration in the master QUICC The BSTM bit in the MCR must be set to 0 This setting will enable using asynchronous timing on the bus signals 3 4 3 Auto Vector Register The auto vector register AVR contains 8 bits that correspond to external interrupt levels that require an auto vector response The AVR must be initialized to 84 to generate auto vectors for interrupt levels 7 and 2 These interrupts are generated through the slave QUICC without supplying interrupt vectors during an IACK cycle 3 4 4 Reset Status Register The reset status register RSR indicates the source of the last reset that occurred when the relevant bit is set This register must be cleared after every reset so that when the next reset occurs its source can be easily determined The register i
85. errupt Acknowledge input signal from the host 2 Not connected 3 HST ACK Host Acknowledge input signal from the host 4 ADS ALL QUADS AII input signal from the host 5 ADS RESET QUADS Reset input signal from the host 6 ADS SEL2 QUADS Select 2 input signal from the host 7 ADS SEL1 QUADS Select 1 input signal from the host 8 ADS SELO QUADS Select 0 input signal from the host 9 HOST REQ HOST Request input signal from the host 10 ADS REQ QUADS Request output signal from the M68360QUADS to the host 11 ADS ACK QUADS Acknowledge output signal from the M68360QUADS to the host 12 ADS INT QUADS Interrupt output signal from the M68360QUADS to the host 13 HOST BRK HOST Break open collector output signal from the M68360QUADS to the host 14 ADS BRK QUADS Break input signal from the host 15 Not connected 16 PD1 Bit 1 of the ADI port data bus 17 PD3 Bit 3 of the ADI port data bus 18 PD5 Bit 5 of the ADI port data bus 19 PD7 Bit 7 of the ADI port data bus 20 25 GND Ground signal of the M68360QUADS 26 Not connected The host supplies 12V on this pin but it is not connected on the M68360QUADS 46 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc M68360QUADS User s Manual SUPPORT INFORMATION Table 5 10 Connector P4 Interconnect Signals Pin No Signal Name Description 27 29 HOST VCC HOST input from the host The M68360QUADS does not use these inputs for power su
86. f this switch is pressed alone This feature is intended to protect the QUICC devices from accidental hard reset 3 2 2 SOFT RESET Switch SW2 The SOFT RESET switch SW2 resets all QUADS devices and performs soft reset to the QUICC devices The switch signal is debounced and It is not possible to disable it by software 3 2 3 ABORT Switch SW3 The ABORT switch is normally used to abort program execution and return control to the CPU32bug The slave QUICC provides the ABORT switch interface and it should be programmed as described in section 3 4 The ABORT switch signal is debounced and if it is enabled by software it causes a level 7 interrupt to the master QUICC 3 2 4 HALT Indicator LD1 The red LED HALT indicator LD1 is lit whenever the master QUICC HALT pin is low asserted 3 2 5 RUN Indicator LD2 The green LED RUN indicator is connected to the address strobe AS signal It is lit if the AS signal is low asserted and it indicates the activity on the bus 3 2 6 Ethernet TX Indicator LD3 The green LED Ethernet Transmit indicator LD3 blinks whenever the EEST is transmitting data through one of the Ethernet ports P7 or P8 3 2 7 Ethernet RX Indicator LD4 The green LED Ethernet Receive indicator LD4 blinks whenever the EEST is receiving data from one of the Ethernet ports P7 or P8 3 2 8 Ethernet CLSN Indicator LD5 The red LED Ethernet Collision indicator LD5 blinks whenever a collision is detected in the AUI P7 port or th
87. gister GMR contains selections for the memory controller of the master QUICC The SYNC bit must be set and the EMWS bit must be cleared to obtain synchronous operation of the memory controller when the DMA in the slave QUICC is active 3 4 10 Base Register 0 and Option Register 0 Base register 0 BRO and Option register 0 ORO control the operation of CSO pin of the master QUICC The Boot EPROM in the M68360QUADS is connected to this pin BRO must be initialized to 00000003 and ORO must be initialized to 5FFE0004 to obtain the memory as described in Table 3 2 3 5 Programming the slave QUICC The slave QUICC core disabled provides the following functions on the M68360QUADS 1 DRAM Controller Chip Select and DSACK generator Parallel port ADI UART for terminal or host computer connection AppleTalk controller for Macintosh computer connection BDM controller to other QUICC devices Ethernet controller Serial EEPROM interface 9 General Purpose 1 signals The slave QUICC internal registers must be programmed after hardware reset as described in the following paragraphs The addresses and programming values are in hexadecimal base Please refer to the MC68360 QUICC User s Manual for more information 3 5 1 Module Base Address Register The slave QUICC s module base address register MBAR controls the location of its internal memory and registers and their access space The slave QUICC MBAR resides at a fix
88. he master QUICC unbuffered 16 A19 Address line 19 of the master QUICC unbuffered 17 A18 Address line 18 of the master QUICC unbuffered 18 A17 Address line 17 of the master QUICC unbuffered 19 A16 Address line 16 of the master QUICC unbuffered 20 GND Ground signal of the M68360QUADS 40 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 5 User s Manual SUPPORT INFORMATION 5 2 3 Connector PD3 Interconnect Signals Connector PD3 is a double row 20 pin male connector The lower 16 data lines of the master QUICC appear on this connector for easy monitoring of the bus by a logic analyzer Table 5 1 describes the connector signals Table 5 3 Connector PD3 Interconnect Signals Pin No Signal Name Description 1 Not connected 2 Not connected 3 DSACK1 DSACK1 line of the master QUICC 4 D15 Data line 15 of the master QUICC unbuffered 5 D14 Data line 14 of the master QUICC unbuffered 6 D13 Data line 13 of the master QUICC unbuffered 7 D12 Data line 12 of the master QUICC unbuffered 8 D11 Data line 11 of the master QUICC unbuffered 9 D10 Data line 10 of the master QUICC unbuffered 10 D9 Data line 9 of the master QUICC unbuffered 11 D8 Data line 8 of the master QUICC unbuffered 12 D7 Data line 7 of the master QUICC unbuffered 13 D6 Data line 6 of the master QU
89. he pin If a pin is dedicated peripheral interface pin the value in the PBDIR for that pin may select one of two dedicated functions of the pin The PBDIR must be initialized to 0007F Pins 10 to 17 are connected to the ADI port data bus therefore their direction must be changed by software according to the data flow 3 5 23 Port B Pin Assignment Register The port B pin assignment register PBPAR configures the function of the port pins If the value in the PBPAR for pin is 0 the pin is general purpose otherwise the pin is dedicated peripheral interface pin The PBPAR must be initialized to 0000 3 5 24 C Data Register Port C of the slave QUICC is 12 pin port and each pin may be configured as general purpose pin or as dedicated peripheral interface pin with interrupt capability Port C data register PCDAT can be read to check the data at the pin If a port pin is configured as general purpose output pin the value in the PCDAT for that pin is driven onto the pin It is recommended to initialize PCDAT to 0740 before configuring the other port registers 3 5 25 C Data Direction Register The port C data direction register PCDIR has different functions according to the configuration of the port pins If a pin is general purpose pin the value in the PCDIR for that pin defines the direction of the pin If a pin is dedicated peripheral interface pin the value in the PCDIR for that pin may selec
90. he user hardware application The BDM pins of the master QUICC are also available for the user through connector P3 Sheet 16 This connector can be used to download code and to monitor functions 4 3 Boot EPROM The boot EPROM is the 27C010 device 048 in sheet 2 200 nsec access time 128K x 8 bit and is used to store the debug and the boot programs The EPROM is accessed as 8 bit device using the Global CS port of the master QUICC It is possible for the user to disable accesses to the EPROM on the QUADS and to use the Global CS port to access his own EPROM on his application board after reset This is done by setting the Enable EPROM switch U52 to OFF thus disconnecting the M CSO signal from E CS signal For More Information On This Product Go to www freescale com 23 Freescale Semiconductor 1 36500005 Users Manual FUNCTIONAL DESCRIPTION FIGURE 4 1 HARDWARE BLOCK DIAGRAM P3 QUICC PD1 PD6 P1 and P2 BDM a gt master Logic Analyzer Connectors Expansion Connectors 128 KByte Boot EPROM 8 bits wide Transceivers 4 Bus Controller Local Bus Arbiter Status 512 KByte 1 a ao Flash Memory QUICC with parity Register 82 bits wide 36 bits wide SIMM 256 Byte 1 Serial P
91. interrupts from the QUADS devices to the master QUICC are enabled If this bit is 0 the master QUICC may be interrupted by the QUADS resources such as the ABORT switch and the slave QUICC peripherals 2 Clock Source This bit indicates the source of the clock on the QUADS If it is 1 the clock is supplied to the QUADS through the expansion connector P1 If the bit is 0 the clock is supplied by the QUADS clock generator 3 A 31 28 Pins Configuration These bits indicates to the CPUS2bug software the required configura tion of the master QUICC A 31 28 pins If it is 1 the pins are configured as write enable signals If it is 0 the pins are configured as address lines 4 SIMM1 This bit is connected to the DRAM SIMM presence detect signals Refer to Table 4 1 for complete description of the available DRAM types and their SIMM 4 1 codes 5 SIMM2 This bit is connected to the DRAM SIMM presence detect signals Refer to Table 4 1 for complete description of the available DRAM types and their SIMM 4 1 codes 6 51 3 This bit is connected to the DRAM SIMM presence detect signals Refer to Table 4 1 for complete description of the available DRAM types and their SIMM 4 1 codes 7 SIMM4 This bit is connected to the DRAM SIMM presence detect signals Refer to Table 4 1 for complete description of the available DRAM types and their SIMM 4 1 codes 8 Host VCC This bit is connected to the ADI port If it is 0 it indicates that
92. into any available SBus expansion slot on the motherboard Refer to the appropriate Installation and Setup manual for the Sun 4 computer for instructions on removing the computer cover and installing the board in an expansion slot FIGURE A 3 ADI board for SBus SBus Connector ADI Connector Following is a summary of the Instructions in the Sun manual 1 Turn off power to the system but keep the power cord plugged in Be sure to save all open files and then the following steps should shut down your system e hostname bin su Password mypasswd hostname usr etc halt wait for the following messages Syncing file systems done Halted Program Terminated Type b boot c continue command mode When these messages appear you can safely turn off the power to the system unit 2 Openthe system unit Be sure to attach a grounding strap to your wrist and to the metal casing of the power supply Follow the instructions supplied with your system to gain access to the SBus slots 56 For More Information On This Product Go to www freescale com M68360QUADS Users Manual Freescale Semiconductor Inc ADI BOARD INSTALLATION 57 Remove the SBus slot filler panel for the desired slot from the inner surface of the back panel of the system unit Note that the ADI board is a slave only board and thus will function in any available SBus slot Slide the ADI board at an angle into the back panel
93. ion of the QUICC internal memory The device appears repeatedly in multiples of its size For example the Status Register appears at memory locations 00024000 00024002 00024004 etc The DRAM SIMM installed in the M68360QUADS is MCM36256 256Kx36 bit The user may replace the DRAM module with higher density SIMM and increase the DRAM space up to 8 MByte The master QUICC can not read the interrupt vector generated by the slave QUICC if it is configured to work in 16 bit mode The auto vector function must be used in this mode External interrupting devices connected to the QUADS must use the auto vector function because the interrupt acknowledge address space is occupied by the slave QUICC 3 3 2 CPU Address Space The master QUICC can generate four types of CPU space cycles Breakpoint Acknowledge LPSTOP broadcast MBAR access and Interrupt Acknowledge IACK The Breakpoint Acknowledge cycle is not supported in the M68360QUADS The LPSTOP broadcast cycle can be generated because it does not need a response from an external device The slave and master QUICCs respond when their MBAR accessed The IACK cycle is supported in the M68360QUADS by the slave QUICC which functions as the interrupt handler on the board and it responds to the IACK cycle 16 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 5 User s Manual OPERATING INSTRUCTIONS 3 4 Programming the mast
94. ire 12 V to be provided by the network termination equipment and if there is no need to reprogram the Flash Memory The QUADS has 2A fuses on the 12 and its ground and it is protected against reverse connection of the 12V power supply Connect the 12V power supply to connector P12 as shown below FIGURE 2 4 P12 12 Power Connector VPP 1 Gnd 20 12 is a 2 terminal block power connector with power plug The plug is designed to accept 1410 22 AWG wires It is recommended to use 14 to 18 AWG wires For More Information On This Product Go to www freescale com Freescale Semiconductor Inc y68360QUADS Users Manual HARDWARE PREPARATION AND INSTALLATION 2 4 3 ADI Installation For ADI installation on various host computers refer to APPENDIX A on page 54 2 4 4 Host computer to M68360QUADS Connection The M68360QUADS ADI interface connector P4 is a 37 pin male D type connector The connection between the M68360QUADS and the host computer is by a 37 line flat cable supplied with the ADI board FIGURE 2 5 below shows the pin configuration of the connector FIGURE 2 5 ADI Port Connector Gnd 20 1 INT ACK Gnd 21 2 NC Gnd 3 HST Gnd 25 4 ADS ALL Gnd 24 5 ADS RESET Gnd 25 6 ADS SEL2 512111 0 128 7 66 HOST 78 AMDSDEED 9 HOST REQ HOST VCC 28 HOST VCG f9 Do 11 ADS ACK 12 ADS INT 13 HO
95. l 0110 Supervisor Program All 0111 Supervisor CPU MBAR registers in both QUICC devices and slave QUICC during interrupt acknowledge cycle 1XXX DMA All For More Information On This Product Go to www freescale com 15 Freescale Semiconductor NaesoqQuaADs Users Manual OPERATING INSTRUCTIONS 3 3 1 Main Memory Map The memory map of devices that respond in User Data User Program Supervisory Data Supervisory Program and DMA spaces is shown in Table 3 2 Table 3 2 M68360QUADS Main Memory Map ADDESS RANGE Accessed Device Data Size NOTES 00000000 0001FFFF Boot EPROM 8 00020000 00021FFF Master QUICC Internal Memory 32 1 00022000 00023FFF Slave QUICC Internal Memory 32 1 00024000 00024001 M68360QUADS Status Register 16 2 00024002 00025FFF The Status Register appears repeatedly here 00026000 00026000 Clear NMI Status Registers 8 2 00026001 00027FFF This function is repeated here 00028000 00028000 Enable A 31 28 8 2 00028001 00029FFF This function is repeated here 00080000 000FFFFF Flash Memory 32 00400000 OO4FFFFF DRAM SIMM MCM36256 32 Parity 3 00400000 005FFFFF DRAM SIMM MCM36512 00400000 007FFFFF DRAM SIMM 36100 00400000 OOBFFFFF DRAM SIMM 36200 F0000000 FFFFFFFF Slave QUICC during interrupt acknowledge cycle 32 4 5 1 NOTES Refer to the MC68360 QUICC User s Manual for complete descript
96. l FIGURE 2 1 M68360QUADS Location diagram lof n __ 10 ed EA sa e 1HOd IgV 222 54 INY 19419413 dad 1101 201 2 op 0 op 3AV IS m E 1 wag Er youms diq lt D vn 0 3AV1S P 8 09 890lN INOHd3 YouUMs diq an Lin ININIS 4n 74 SZN OINO H3LSVIN 4 24 4 SB SB SB SB 096999 yse 4 yse 4 yse 4 lo 9 Lld Zid oH To 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc y68360QUADS User s Manual HARDWARE PREPARATION AND INSTALLATION 2 3 1 ADI Port Address Selection Dip Switch U46 Each M68360QUADS can have eight possible slave addresses set for its ADI port enabling up to eight M68360QUADS boards to be connected to the same ADI board in the host computer The selection of the slave address is done by setting switches 1 2 and 3 in the Dip Switch Switch 4 is reserved for future use and it should be in OFF state Switch 3 stands for the most significan
97. le com Freescale Semiconductor Inc 5 User s Manual OPERATING INSTRUCTIONS 3 5 5 Port E Pin Assignment Register Port E pins can be programmed by the port E pin assignment register PEPAR The PEPAR must be initialized to 3760 to configure Port E of the slave QUICC as follows The output of the slave QUICC interrupt request is on IOUT 0 2 pins e RAS1 and RAS2 double drive function is used to drive the DRAM The A 31 28 pins of the slave QUICC are configured as address lines The OE AMUX pin is configured as AMUX to drive the external multiplexers of the DRAM The CAS 0 3 output function is used for the DRAM e CS7 output function is enabled 3 5 6 System Protection Control The system protection register SYPCR controls the system monitors the software watchdog and the bus monitor timing This register must be initialized to 37 to disable the software watchdog and to enable the bus monitor function in the slave QUICC 3 5 7 Global Memory Register The global memory register GMR contains selections for the memory controller of the slave QUICC The GMR must be initialized according to the size and the access time of the DRAM SIMM installed on the M68360QUADS as follows For 70 nsec DRAM type MCM36256 or MCM36100 the must be initialized to 17840380 e For 70 nsec DRAM type MCM36512 or 36200 the GMR must be initialized to 0 840380 For 80 nsec DRAM type MCM36256 or MCM
98. master QUICC C8 EXTBR External master bus request input to the Local Bus Arbiter C9 EXTBG External master bus grant output from the Local Bus Arbiter C10 BGACK Bus grant acknowledge line C11 5 Address strobe line C12 GND Ground signal of the M68360QUADS C13 DS Data strobe line C14 R W Read Write line C15 VCC 5V C16 CONFIGO RMC CONFIGO pin of the master QUICC C17 CONFIG1 CONFIG1 pin of the master QUICC C18 DSACKO Data and size acknowledge 0 line of the master QUICC C19 DSACK1 Data and size acknowledge 1 line C20 BERR Bus error line of the master QUICC C21 HALT HALT pin of the master QUICC C22 RESETH Hard reset pin of the master QUICC C23 RESETS Soft reset pin of the master QUICC C24 PERR Parity error pin of the master QUICC C25 VCC 5V C26 TRIS TRIS pin of the master QUICC C27 MODCKO Clock mode select 0 pin of the master QUICC C28 MODCK1 Clock mode select 1 pin of the master QUICC C29 GND Ground signal of the M68360QUADS C30 CLK1 The operating clock of the M68360QUADS 25 MHz C31 GND Ground signal of the M68360QUADS C32 CLK2 The operating clock of the M68360QUADS 25 MHz 44 For More Information On This Product Go to www freescale com 5 2 8 Freescale Semiconductor Inc M68360QUADS User s Manual SUPPORT INFORMATION Connector P2 Interconnect Signals Connector P2 is a triple row 96 pin female DIN connector P1 and P2 expansion connectors provide all the signals of the master QUIC
99. n the slave QUICC 10 ADI Data 0 This pin is connected to the ADI port signal PDO through the data bus transceiver U2 and it is configured as pin 11 ADI Data 1 This pin is connected to the ADI port signal PDO through the data bus transceiver U2 and it is configured as pin 12 ADI Data2 This pin is connected to the ADI port signal PDO through the data bus transceiver U2 and it is configured as pin 13 ADI Data 3 This pin is connected to the ADI port signal PDO through the data bus transceiver U2 and it is configured as pin 14 ADI Data 4 This pin is connected to the ADI port signal PDO through the data bus transceiver U2 and it is configured as pin 15 ADI Data 5 This pin is connected to the ADI port signal PDO through the data bus transceiver U2 and it is configured as pin 16 ADI Data 6 This pin is connected to the ADI port signal PDO through the data bus transceiver U2 and it is configured as pin 17 ADI Data 7 This pin is connected to the ADI port signal PDO through the data bus transceiver U2 and it is configured as pin 33 For More Information On This Product Go to www freescale com Freescale Semiconductor 1 36500005 Users Manual FUNCTIONAL DESCRIPTION 4 7 9 3 Slave QUICC Port C Port C is 12 pins port Table 4 2 describes the configuration of port C Table 4 4 Port C Pins Description Pin Pin Name Description TENA This pin is connected
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101. of the system unit Make sure that the mounting plate on the ADI board hooks into the holes on the back panel of the system unit Push the ADI board against the back panel and align the connector with its mate and gently press the corners of the board to seat the connector firmly Close the system unit Connect the 37 pin interface flat cable to the ADI board and secure Turn power on to the system unit and check for proper operation For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 5 Users Manual ADI PORT HANDSHAKE DESCRIPTION APPENDIX B ADI PORT HANDSHAKE DESCRIPTION B 1 INTRODUCTION In this appendix the ADI port signals and the handshake procedure are explained The M68360QUADS ADI port can be connected to an ADI board mounted in a host computer There are ADI boards for the following host computers 1 IBM PC XT AT 2 SUN 4 SBus interface B 2 ADI Port Concept and Operation Description Each ADI board can be connected to up to 8 M68360QUADS boards Each M68360QUADS has its own address which is fixed by setting Dip Switch U46 on the board Refer to section 2 3 1 on page 9 The following operations can be performed using the ADI port The host computer can write a byte to the M68360QUADS The M68360QUADS can write a byte to the host computer M68360QUADS can interrupt the host computer The host computer can interrupt the M68360QUADS interrupt level 7
102. p A1 amp DSK1 amp IMDSKO end BUS CNTL 65 For More Information On This Product Go to www freescale com 66 Freescale Semiconductor NaesoQuADs Users Manual SUPPORT INFORMATION C 2 BUS ARBITER U42 The PLD chip U42 on schematic sheet 9 is a PAL16R4 7 device This device uses the master QUICC arbitration logic to transfer the bus mastership to the slave QUICC or to external master The Bus Grant signals to the slave QUICC and to the external master are asserted after the BGACK signal is negated This is to ensure that the address bus transceivers are opened correctly before the requesting master takes control of the bus This device also generates the signal A28_31 which is used by the Data Bus Controller to determine if the current access is to a device on the QUADS board module ARBITER title BUS ARBITER AMIR YEHOSHUA MOTOROLA SEMICONDUCTOR ISRAEL LTD 18 3 93 042 device P16R4 SCLKO1 OC pin 1 11 EXTBR M_BG S_BR BGACK pin 2 3 4 5 28 29 0 1 50 CS 6 7 8 9 12 13 M 5 28 31 pin 14 15 16 17 18 19 H L X Z C 1 0 2 equations DIR 5 BG 8 amp IM S_BR EXTBG amp 5 _ amp BG amp IM BG amp BGACK IEXTBG 8 IEXTBR amp S BG amp IM IS BG 5 BG amp 15 BR amp IM BR amp
103. pin RJ 45 connector It is the twisted pair Ethernet port of the M68360QUADS board Table 5 1 describes the P8 connector signals Table 5 14 Connector P8 Interconnect Signals Pin No Signal Name Description 1 Twisted Pair Transmit Data positive output from the M68360QUADS 2 TPTX Twisted Pair Transmit Data negative output from the M68360QUADS 3 Twisted Pair Receive Data positive to the M68360QUADS 4 Not connected 5 Not connected 6 TPRX Twisted Pair Receive Data negative input to the M68360QUADS 7 Not connected 8 Not connected 48 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 5 User s Manual SUPPORT INFORMATION 5 2 15 Connector P9 Interconnect Signals Connector P9 is a double row 8 pin male connector It is the BDM controller port that enables the M68360QUADS to control external QUICC devices The slave QUICC general purpose 1 pins are connected to P9 Table 5 1 describes the P9 connector signals Table 5 15 Connector P9 Interconnect Signals Pin No Signal Name Description 1 GND Ground signal of the M68360QUADS 2 BDMCLK This signal is connected to Port B pin 4 in the slave QUICC It should be connected to the breakpoint pin of the external QUICC device 3 GND Ground signal of the M68360QUADS 4 BDMFRZ This signal is connected to Port B pin 9
104. pply 30 HOST ENABLE HOST Enable input signal from the host 31 33 GND Ground signal of the M68360QUADS 34 PDO Bit 0 of the ADI port data bus 35 PD2 Bit 2 of the ADI port data bus 36 PD4 Bit 4 of the ADI port data bus 37 PD6 Bit 6 of the ADI port data bus 5 211 Connector P5 Interconnect Signals Connector is a 9 pin female D type connector It is the RS 232 serial port of the M68360QUADS Table 5 1 describes the P5 connector signals Table 5 11 Connector P5 Interconnect Signals Pin No Signal Name Description 1 CD Carrier Detect output from the M68360QUADS 2 TX Transmit Data output from the M68360QUADS 3 RX Receive Data input to the M68360QUADS 4 DTR Data Terminal Ready input to the M68360QUADS 5 GND Ground signal of the M68360QUADS 6 DSR Data Set Ready output from the M68360QUADS 7 RTS N C Request To Send This line is not connected in the M68360QUADS 8 CTS Clear To Send output from the M68360QUADS 9 5 5 2 12 Connector Interconnect Signals Connector P6 is 8 pin MINI DIN JACK connector It is the AppleTalk port of the M68360QUADS board Table 5 1 describes the P6 connector signals Table 5 12 Connector P6 Interconnect Signals Pin No Signal Name Description 1 VCC 5V output from the M68360QUADS through 100 ohm resistor 2 HSKI Hand Shake Input signal 3 TX Transmit Data negative output from the M68360QU
105. r connection for each address configuration Address 0 hex is not recommended and its usage might cause problems FIGURE A 2 JG1 Configuration Options QOO O 0 hex 100 hex 200 hex 300 hex To properly install the ADI board position its front bottom corner in the plastic card guide channel at the front of the IBM PC XT AT chassis Keeping the top of the ADI board level and any ribbon cables out of the way lower the board until its connectors are aligned with the computer expansion slot connectors Using evenly distributed pressure press the ADI board straight down until it seats in the expansion slot Secure the ADI board to the computer chassis using the bracket retaining screw Refer to the computer Installation and Setup manual for instructions on reinstalling the computer cover 55 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 5 User s Manual ADI BOARD INSTALLATION A 3 SUN 4 to M68360QUADS Interface The ADI board should be installed one of the SBus expansion slots in the Sun 4 SPARCstation computer A single ADI can control up to eight M68360QUADS boards CAUTION BEFORE REMOVING OR INSTALLING ANY EQUIPMENT IN THE SUN 4 COMPUTER TURN THE POWER OFF AND REMOVE THE POWER CORD A 3 1 ADI Installation in the SUN 4 There are no jumper options on the ADI board for the Sun 4 computer The ADI board can be inserted
106. ring interrupt acknowledge cycles In this case the auto vector function must be used If an external interrupting device is connected to the QUADS the auto vector function must be used to handle its interrupts This is because the interrupt acknowledge address space is occupied by the slave QUICC and the external interrupter may not drive data during interrupt acknowledge cycles 4 12 Disable CPU Logic for the Slave QUICC Sheet 15 The slave QUICC must be configured to work with its CPU disabled its global CS disabled and its MBAR to reside at address SFF04 For this the encoding of its configuration pins CONFIG 2 0 must enable the CPU for more than 32 clocks during hard reset and then they must be encoded to 110 before the hard reset signal is negated high level The CONFIG2 and pins are connected to pull up resistors on the QUADS The CONFIGO pin is driven by a PAL22V10 25 device SP1 in sheet 15 during hard reset SP1 drives CONFIGO to high level for 64 clock cycles after the hard reset signal is asserted This makes the encoding of CONFIG 2 0 pins equals 111 which enables the CPU After 64 clocks the CONFIGO pin is driven low as long as the hard reset signal is asserted 37 For More Information On This Product Go to www freescale com 38 Freescale Semiconductor NaesoqQuaADs Users Manual FUNCTIONAL DESCRIPTION When the hard reset signal is negated the CPU of the slave QUICC is disabled and SP1 stops
107. rolled by the EEST and they provide indications about the status of the Ethernet ports activity The signals between the slave QUICC and the MC68160 appear on connector P10 for debugging purposes P10 is a set of wire holes The socket U24 is installed for internal factory testing only For proper operation of the EEST this socket must be empty 4 7 7 4 Ethernet AUI Port Signal Description The AUI port connector P7 is a 15 pin female D type connector as shown in FIGURE 4 3 FIGURE 4 5 Ethernet AUI Port Connector 1777 2 3 3 GND 4 2 ARX 5 2 T TING 22 22 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc M68360QUADS User s Manual FUNCTIONAL DESCRIPTION The list below describes the port signals The directions O and I O are relative to the QUADS board LE means input to the QUADS e 1 Collision Input positive e Transmit Data positive ARX 1 Receive Data positive e ACX 1 Collision Input negative e ATX O Transmit Data negative ARX 1 Receive Data negative 12V O 412V power supply from the QUADS 4 7 7 2 Ethernet Twisted Pair Port Signal Description The twisted pair port connector P8 is a 8 pin RJ 45 connector as shown in FIGURE 4 3 FIGURE 4 6 Ethernet Twisted Pair Port Connector 1 N C
108. s cleared by writing 3 4 5 CLKO Control Register The CLKO control register CLKOCR controls the operation of the CLKO 0 1 pins This register must be initialized to AB so that the CLKO1 pin is disabled and the CLKO2 pin is enabled with 1 3 strength output buffer 3 4 6 PLL Control Register The PLL control register PLLCR controls the operation of the PLL There is no need to program the PLLCR after hard reset because the configuration of the MODCK 0 1 pins on the QUADS determines its value It is recommended to set the PLLWR bit to prevent accidental writing 3 4 7 Port E Pin Assignment Register Port E pins can be programmed by the port E pin assignment register PEPAR The A 31 28 pins of the master QUICC can be programmed as address lines or as write enable W 0 3 lines Bit 7 in the PEPAR must be cleared to select address lines function and it must be set to select the write enable function Until this bit is written the A 31 28 pins are three stated 3 4 8 System Protection Control The system protection register SYPCR controls the system monitors the software watchdog and the bus monitor timing This register must be initialized to 37 to disable the software watchdog and to enable the bus monitor function For More Information On This Product Go to www freescale com 17 18 Freescale Semiconductor yn6esoouADs Users Manual OPERATING INSTRUCTIONS 3 4 9 Global Memory Register The global memory re
109. s parallel link from the QUADS to various host computers This port is connected via a 37 line cable to a special board called ADI Application Development Interface installed in the host computer It is possible to connect the QUADS board to an IBM PC XT AT or to SUN 4 SPARC station provided that they have an ADI board with the appropriate software drivers installed on them Each QUADS can have 8 possible slave addresses set for its ADI port enabling up to 8 QUADS boards to be connected to the same ADI board The QUADS address is selected by U46 in sheet 9 The ADI port connector P4 is a 37 pin male D type connector The connection between the QUADS and the host computer is by a 37 line flat cable supplied with the ADI board FIGURE 4 2 below shows the pin configuration of the connector FIGURE 4 2 ADI Port Connector Gnd Gnd Gnd Gnd Gnd Gnd 12 v HOST VCC HOST VCC HOST VCC HOST Gnd Gnd Gnd PDO PD2 PD4 PD6 aa 20 2 21 55 24 2 25 25 26 28 21 29 30 12 31 13 32 14 33 15 34 16 35 17 36 37 19 INT N C HST ACK ADS ALL ADS RESET ADS SEL2 ADS SEL1 ADS SELO HOST REQ ADS REQ ADS ACK ADS INT HOST BRK ADS BRK N C PD1 PD3 PD5 PD7 NOTE Pin 26 on the ADI is connected to 12 v power supply but it is not used in the QUADS 27 For More Information On This Product Go to www freescale com 28 Free
110. scale Semiconductor NaesoqQuaADs Users Manual FUNCTIONAL DESCRIPTION 4 7 3 1 ADI Port Signal Description The ADI port on the M68360QUADS was slightly modified to generate either hard reset or soft reset This feature was added to comply with the QUICC reset mechanism The host software written for the M68360QUADS should be able to work properly with existing QUADS boards such as the M68302ADS In the list below the directions O and I O are relative to the QUADS board I E l means input to the QUADS e ADS SEL 02 l These three input lines determine the slave address of the QUADS being accessed by the host computer Up to 8 boards can be addressed by one ADI board ADS This input line is used to reset or abort program execution on all QUADS development boards that are connected to the same ADI board HOST ENABLE l This line is always driven low by the ADI board The QUADS software uses this line to determine if a host is connected to the ADI port e ADS When a host is connected this line is used in conjunction with the addressing lines or with the ADS ALL line to generate a non maskable interrupt interrupt level 7 to the QUICC e ADS When host is connected this line is used in conjunction with the addressing lines or with the ADS ALL line to reset the QUADS board The type of the reset hard or soft is determined by INT ACK signal HOST REQ This signal initi
111. sequence of events is as follows 1 ADS REQ PD 0 7 The M68360QUADS places a data byte on the parallel port data bus buffer disabled and asserts the ADS REQ signal the ADS REQ signal will not appear on the port until the board is selected by the Host The Host polls each M68360QUADS address and detects the ADS REQ signal from the requesting board The Host asserts the 5 signal in response which enables the data buffer in the M68360QUADS The M68360QUADS negates the ADS signal The data appears on the bus as long as 5 signal is asserted The Host reads the data The Host negates the signal to end the cycle The M68360QUADS ends the cycle FIGURE B 3 M68360QUADS Write Cycle to Host 1 3 1 4 DATA VALID ADS SEL 02 ADDRESS VALID HST ACK 2 B 3 3 M68360QUADS Interrupt to the Host The M68360QUADS can generate an interrupt to the Host The interrupt request and acknowledge sequence is shown in FIGURE B 4 The sequence is as follows 1 C gn oi 269 The M68360QUADS places a service request code on the parallel port data bus buffer disabled and asserts the ADS INT and the HOST BRK signals The HOST signal is an open collector signal asserted low common to all M68360QUADS boards which will appear immediately on the port The ADS INT signal will not appear on the port until the board is selected by
112. set by the Abort switch and Host NMI Register that is set by the host computer connected to the ADI port Setting either register generates a level 7 interrupt to the master QUICC The CS5 signal is used the M68360QUADS by the interrupt handling routine to clear these registers BR5 must be initialized to 00026001 and OR5 must be initialized to OFFFEO004 to obtain the memory map as described in Table 3 2 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 5 User s Manual OPERATING INSTRUCTIONS 3 5 14 Base Register 6 and Option Register 6 Base register 6 BR6 and Option register 6 OR6 control the operation of CS6 pin of the slave QUICC The A 31 28 pins of the master QUICC can be configured as address lines or as write enable lines After hard reset these lines are in three state condition until the PEPAR of the master QUICC is written If the A 31 28 Configuration switch 052 is the CPU32bug software initializes the PEPAR in the master QUICC and asserts the CS6 signal to enable using the A 31 28 as address lines on the board BR6 must be initialized to 00028001 and OR6 must be initialized to OFFFEO04 to obtain the memory as described in Table 3 2 Note If the A 31 28 pins are used as write enable lines CS6 must never be asserted It is recommended to initialize BR6 to 00028000 to avoid accidental accesses to the address space of CS6
113. t be set to ON during normal operation 3 Enable DRAM This switch indicates to the master QUICC whether to initialize the ON DRAM control registers or not If the switch is ON the DRAM on the QUADS is enabled If the switch is OFF the DRAM is disabled and its memory space is free for the user This is useful if the user needs to connect his application to the QUADS expansion connectors and use the DRAM memory space in the application 4 Enable Flash Memory This switch indicates to the master QUICC whether to initialize ON the Flash Memory control registers or not If the switch is ON the Flash Memory on the QUADS is enabled If the switch is OFF the Flash Memory is disabled and its memory space is free for the user This is useful if the user needs to connect his application to the QUADS expansion connectors and use the Flash Memory space in the application 5 A 31 28 Configuration This switch indicates to the CPU32bug software whether to ON configure the master QUICC A 31 28 pins as address lines or as write enable signals If the switch is ON the pins are configured as address lines If the switch is set to OFF the pins are configured as write enable signals 6 Enable Clock This switch enables the clock generator on the QUADS If it is set to ON ON the 25 MHz clock generator is enabled If it is set to OFF the clock generator driver is disabled and the user must supply clock to the QUADS through pins CLK1 and
114. t bit of the address and switch 1 stands for the least significant bit If the switch is in the state it stands for logical 1 FIGURE 2 2 Dip Switch configuration for address 0 U46 Table 2 1 describes the switch settings for each slave address Table 2 1 ADI Address Selection ADDRESS Switch 3 Switch 2 Switch 1 OFF OFF OFF OFF OFF ON 2 OFF ON 3 4 5 6 ON ON OFF 7 ON ON ON For More Information On This Product Go to www freescale com Freescale Semiconductor NaesoquaADs Users Manual HARDWARE PREPARATION AND INSTALLATION 2 3 2 QUADS Operation Mode Configuration Dip Switch U52 Dip Switch U52 has 8 switches which are responsible for configuring the operation mode of the master QUICC on the M68360QUADS and they also enable devices on the QUADS Table 2 2 describes the function of each switch Table 2 2 Dip Switch U52 Description Default Switch Function setting 1 Enable EPROM This switch connects between the EPROM chip select input and the ON master QUICC CSO signal If the signal 50 is used by external logic connected to the expansion connectors the switch must be set to OFF to disable the EPROM on the QUADS The switch must be set to ON otherwise 2 Enable slave QUICC This switch connects between the slave QUICC input pin ON and data signal D30 This switch is for factory testing of the QUADS and it mus
115. t one of three dedicated functions of the pin The PCDIR must be initialized to OF8C 3 5 26 C Pin Assignment Register The port C pin assignment register PCPAR configures the function of the port pins along with PCDIR and PCSO The PCPAR must be initialized to 0003 3 5 27 C Special Options Register The port C special options register PCSO configures the CDx and CTSx pins Port C can detect changes on the CTS and CD lines and assert the corresponding interrupt while the SCC simultaneously uses those lines The must be initialized to 70030 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 5 User s Manual FUNCTIONAL DESCRIPTION CHAPTER 4 FUNCTIONAL DESCRIPTION 4 1 INTRODUCTION This chapter details the hardware design of the M68360QUADS and describes each module 4 2 Master QUICC The CPU of the master QUICC device U8 in sheet 4 is the main processor on the QUADS The working frequency of the QUICC is 25 Mhz but the user can change the frequency by replacing the oscillator U27 in sheet 5 The frequency of the oscillator is twice the working frequency of the board The master QUICC can be configured to operate either in 32 bit mode or 16 bit mode according to the level of MPRTYS signal during hard reset The user can drive this signal low 16 bit mode either by selecting this mode in Dip Switch U52 Sheet 14 or by driving it thro
116. tch is cleared by the interrupt handling software on the M68360QUADS B 3 5 Host Reset to the M68360QUADS The Host can perform either hard reset or soft reset on the M68360QUADS Soft reset is done by selecting the address of the required board and asserting the ADS RESET signal for more than 26 microseconds Hard reset is done by selecting the address of the required board asserting INT signal and asserting the ADS RESET signal for more than 26 microseconds B 3 6 Addressing M68360QUADS The Host can reset or interrupt all M68360QUADS boards that are connected to the same ADI The Host should assert the ADS ALL signal in conjunction with either ADS RESET ADS The contents of the ADS SEL 0 2 lines have no affect 62 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 5 User s Manual SUPPORT INFORMATION APPENDIX C PLDs DESCRIPTION C 1 DATA BUS CONTROLLER U51 The PLD chip U51 on schematic sheet 8 is a GAL22V10 7 device This device generates the required byte enable signals according to the data bus width of the master QUICC the accessed address and the data size The device also controls the operation of the data bus transceivers and the data bus swapping module BUS CNTL title BUS CONTROL AMIR YEHOSHUA MOTOROLA SEMICONDUCTOR ISRAEL LTD 12 12 92 U51 device 22 10 RSTH AS DSK1 A0 A1 1 2 3 4 5 SIZO SIZ1 A DIR B32 1
117. ted to operate reliably withan ambient air temperature range from 0 degrees C to 70 degrees C Dynamic Burn in is performed while the board is table mounted with no other boards attached to it Test software is executed as the board is subjected to temperature variations If the board is attached to other boards the thermal conditions may get worse and it is recommended that the operating temperature should not exceed 30 degrees C For More Information On This Product Go to www freescale com Freescale Semiconductor Inc y68360QUADS User s Manual GENERAL INFORMATION 1 5 GENERAL DESCRIPTION The M68360QUADS is a development tool for the MC68360 QUICC device This board is used for hardware and software development of applications using the QUICC device such as Ethernet interface or other communication boards The M68360QUADS has logic analyzer connectors and expansion connectors providing physical connection to all pins of the master QUICC on the board The logic analyzer connectors enablethe user to monitor the bus activity and the I O pins of the QUICC by providing direct connection to HP or other logic analyzers The expansion connectors enable to attach user applications to the board and use the board hardware and software resources to check the user application The M68360QUADS has Ethernet and LocalTalk ports which enable the user to develop and test the software on the board before integrating it on the application 1 6 RELAT
118. the Host The Host detects the HOST BRK signal and polls each M68360QUADS address to determine the interrupting board The Host asserts the 5 signal enabling the data buffer in the M68360QUADS The Host reads the service request code on the data bus The Host negates the signal The Host asserts the INT ACK signal which resets the HOST BRK latch in the M68360QUADS and negates the HOST BRK signal the HOST BRK signal still be low asserted if another M68360QUADS board is driving it low For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 5 Users Manual ADI PORT HANDSHAKE DESCRIPTION 7 The selected M68360QUADS detects the INT ACK signal and negates the ADS INT signal 8 The Host negates the INT ACK signal and ends the cycle FIGURE 4 M68360QUADS Interrupt to Host HOST BRK N hardware 1 7 ADSINT _ software 4 PD 0 7 DATAVALID 2 ADS SEL 0 2 lt ADDRESS VALID 3 5 5 8 INT 3 4 Host Interrupt to the M68360QUADS The Host can interrupt the M68360QUADS interrupt level 7 to abort the execution of programs running on the board This is done by selecting the address of the required M68360QUADS and momentarily asserting the ADS signal which sets a latch in the M68360QUADS The output of the latch interrupts the master QUICC on the M68360QUADS The la
119. the host computer is powered on 9 Host Enable This bit is connected to the ADI port If it is 1 it indicates that the ADI is connected to a host computer 10 Host Ack This bit is connected to the ADI port If it is 0 it indicates that the host has responded to the ADS REQ signal 11 Host Req This bit is connected to the ADI port If it is 0 it indicates that the host is requesting to write to the QUADS 12 ADS Select This bit is connected to the ADI port If it is 1 it indicates that the host computer has selected the QUADS for the current data transfer 13 Interrupt Ack This bit is connected to the ADI port If it is 40 it indicates that the host has responded to the interrupt signal from the QUADS 14 Host NMI This bit is connected to the ADI port If it is 0 it indicates that the host has generated level 7 interrupt to the QUADS 15 Data Terminal Ready indication This bit indicates if a terminal is connected to the RS 232 Serial Port 36 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 5 Users Manual FUNCTIONAL DESCRIPTION 4 11 Interrupt Logic The slave QUICC is configured by the CPU32bug software to assert its interrupt requests on its IOUT 2 0 pins The 74F538 decoder U70 in sheet 13 accepts the IOUT signals and decodes them to select one of the master QUICC IRQ 7 1 signals The IRQ signals of the
120. tion of RAS1 pin of the slave QUICC This pin is connected to the DRAM module These registers must be initialized according to the type of the DRAM SIMM installed on the M68360QUADS as follows e OR1 must be initialized to 2FF00009 for 70 nsec or 80 nsec DRAM types MCM36256 or MCM36512 OR1 must be initialized to 3FFO0009 for 100 nsec DRAM types MCM36256 or MCM36512 e OR1 must be initialized to 2FC00009 for 70 nsec or 80 nsec DRAM type MCM36100 or MCM36200 OR1 must be initialized to 3FC00009 for 100 nsec DRAM type MCM36100 MCM36200 must be initialized to 00400005 disregarding the type and the access time of the DRAM Note The CPU32bug software does not access BR1 and 1 after reset if the Enable DRAM switch in U52 is in OFF position The software must perform 8 accesses to the RAS1 address space after initialization for proper operation of the DRAM 3 5 10 Base Register 2 and Option Register 2 Base register 2 BR2 and Option register 2 OR2 control the operation of RAS2 pin of the slave QUICC This pin is connected to the DRAM module These registers must be initialized if the type of the DRAM SIMM installed on the M68360QUADS is MCM36512 MCM36200 because these two types contain two DRAM banks and RAS1 can not be connected to both banks If the DRAM SIMM type is 36512 BR2 must be initialized to 00500005 OR2 must be initialized to 2FF00009 for 70 nsec 80 nsec DRAM and to SFF
121. to the TENA input of the EEST It is configured as the RTS signal of SCC1 in the slave QUICC AppleTalk Enable This pin is connected to the enable input of the AppleTalk transceiver U29 It is configured as the RTS signal of SCC2 of the slave QUICC If this pin is 40 the transceiver output to the AppleTalk port P6 is enabled EEST CS2 This pin is connected to the CS2 input of the EEST and it is configured as output pin in the slave QUICC If this pin is 1 the EEST operates in standby mode and if it is 0 the EEST is in normal operation mode TPEN This pin is connected to the I O pin of the EEST and it is configured as I O pin in the slave QUICC The TPEN Twisted Pair Port Enable pin in the EEST determines which port is selected to operate AUI or CLSN This pin is connected to the CLSN output of the EEST It is configured as the CTS signal of SCC1 in the slave QUICC RENA This pin is connected to the RENA output of the EEST It is configured as the CD signal of SCC1 in the slave QUICC HSKI This pin is connected to the signal of the AppleTalk port through the transceiver U29 It is configured as the CTS signal of SCC2 of the slave QUICC APORT This pin is connected to the APORT input of the EEST and it is configured as output pin in the slave QUICC If this pin is 1 the EEST automatically select the TP or AUI port based on the TP receive input If it is 0 the
122. ugh the expansion connector P2 Sheet 21 In 16 bit mode the data transceivers Sheet 6 and the data bus controller Sheet 8 control the data flow between the 16 bit data bus of the master QUICC and the 32 bit devices on the QUADS by directing the data to the proper lines There is one restriction on the software so that it can support both operating modes provided that it uses the auto vector function of the master QUICC If the slave QUICC interrupts the master QUICC the master can read the interrupt vector only in 32 bit mode When programming the MBAR register in the slave QUICC it must access it in two 16 bit transfers and it must write to the MBARE register before each access This restriction is due to the design of the QUICC which requires writing to the MBARE register before accessing the MBAR register therefore when the QUICC operates in 16 bit mode it can not access the MBAR in 32 bit transfers All the pins of the master QUICC device are available unbuffered to the user through the expansion connectors P1 and P2 Sheets 20 and 21 and the logic analyzer connectors PD1 to PD6 Sheets 18 and 19 The user can monitor the QUICC activity and connect the QUADS to his own hardware application during its development stage The logic analyzer connectors PD1 to PD5 can be connected directly to HP logic analyzers The master QUICC pins are buffered from all the devices on the QUADS to minimize their load and to enable easy connection to t
123. ycle from Host to M68360QUADS The application software in the Host uses the handshake signals to coordinate data transfer across the parallel link The CPU32bug software in the M68360QUADS is responsible for accepting the data and responding to the handshake signals The signals are shown in FIGURE B 2 The sequence of events during a byte write to the M68360QUADS is as follows 1 The Host selects the M68360QUADS board by putting the board s address on the ADS SEL 0 2 signals 2 The Host places a data byte in the data bus latch buffer is in high impedance state 3 The Host asserts the HOST REQ signal the data buffer is enabled data appears on the bus 4 The M68360QUADS detects the HOST REQ signal and reads the data byte 5 The M68360QUADS asserts the ADS signal The Host detects the ADS signal and negates the HOST REQ signal data buffer is disabled 7 The M68360QUADS detects the negation of HOST REQ signal and negates ADS to end the cycle FIGURE B 2 Host Write to M68360QUADS 1 ADS SEL 0 2 lt ADDRESS VALID 3 6 HOST REQ 7 ADS 2 4 PD 0 7 DATA VALID For More Information On This Product Go to www freescale com 60 M68360QUADS Users Manual Freescale Semiconductor Inc ADI PORT HANDSHAKE DESCRIPTION 61 B 3 2 Write Cycle from M68360QUADS to Host The signal handshake during an M68360QUADS to Host write cycle is shown in FIGURE B 3 The

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