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1. 16 17 PCERSVD __ Groumd _ s 19 PPMCADOO0 PMCAD29 Nag 20 21 X PGond UL PMCADR6 M7 22 23 Me J PMCADZA J 33V _ 24 25 X PPMCIDSE PMCAD23 N5 26 27 P99V i po PMCAD20 Pi 28 29 Ni J JPMCADI8 J Gruwd so 33 X don PMCRSVD 34 35 G5 PMCTIRDY J 33V _ 306 37 Ground jjL PMCSTOP N3 S38 39 P5 PMC PERR Grud 40 po por PMCSERR P4 42 43 T2 PMC CBE Ground 44 49 K PMG ADR 33V 50 51 Ja P PMCAD7 PMG RSD 5 53 por PMCRSVD J 54 55 PMCRSVD Grouwd se 57 X PPMCRSVD PMCRSVD 58 59 Ground j _ PMCRSVD 60 601 ACKes _ __ jj aw 6 63 Grud PMCRSVD 64 Table 23 PMC Connector P7 Pin out Copyright 2003 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc All other trademarks are property of their respective owners Avnet Electronics Marketing Released 27 of 33 Rev 1 0 04 18 2006 Literature ADS 003704 3 7 JP16 Header 20x2 FPGA Signal Signal FPGA Pin 2 4 o vv 88037 He o nc BLOM 39 Ground Ground
2. 19 Tableto Control Register Bit Wap TET ITE T I T 20 LEZIT Status Redi Ster BIE IVa cE 21 Table 17 AvBus Connectors Available by Virtex ll Pro Density eee 22 Fable 18 s AvBus Connector PS PINOUT urn acte aen ra a karn d Cobre kc Ak eo ka 23 Table 19 AvBus Connector P TO PIDSOUL sl sa di kra ar oboe n tance eng euey hay dlke ene Goal as te ebe Rae Dee cial peus euey dav dO a xelk celal an ores 24 Table ANA TR COMNECtO PIL PIN OU ND MN DD DO ca Ro d RM aen sa o a oe at dnd AS 25 Table 27 AvBus Connector P T2 PITIsOUE scias utbs Gcr ta Esta f sid bia dibir twa abra e Race fessa Ew Vr kul laa Ua ke adi tiles 26 Table 22 PMC Connector Po PIBSOBE toas dt io ia 27 Table 23 PMC Gonnector PT Pin OU s oco caeso pa aa Cac recu eo caet ecu eh ea bcp ecce acp rg Ca ce neca peru ra e RR CR Exe 27 Table 24 Header JP 16 PIQUE duci optio SU Erde dest qu uio oet ioo A a Pepe es r rl ra ararara ae e da 28 Table 25 JTAG Chain Selection JP T5 sy ub a aya Sees KD Bra dis kay ot tta Ef enan N KENA a 29 Table 26 PLB Memory Project Memory Map lt x t j 2 a55y 542 bel hekan i zi AD adan n KE De A xudaye E n y he bal kelekela dalekot ka ed D ck 2e sa assis nans 30 Table 27 OPB Memory Project Memory Map 5ia 8 24 250 22214 yanan bany He ane k n ud QEME dal na c n He ula ed aia a k n Sk kO del we k n e Van bawan e kk e ERIN isis ne k n n be Kn ke 31 Copyright
3. et AER BMAI3 Jj BMAt5 Ac21 82 12 AGi7 BMAi4 BMM6 AF24 83 13 5VDC GND 84 14 AK23 BMAI7Z 9 BMAig9 AF23 85 15 AJ233 BMAI8 BMA20 AF22 86 s GND GND 87 r AD BMA BMA233 AD 2 88 18 AF21 BMA2 nc j 9 MN 9 GN 3 33VDC 900 MN vo ne Oo n nve PR J a pm 2 nc 1 nc j 9 MEME 2 GND GND j 9 MEM k ne 9 nc j MM ii ne M BMD0 a o 95 25 5VDC GND 96 26 AEi0 BMD BMD3 AGt4 97 27 Acta J BMD BMD4 ACIS e J 23 GND GND 99 29 ABIR BMD5 BMD7 AEt7 100 30 ADi7 BMD6 BMDS ADf2 101 3 GND 33VDC 102 32 ADOT X BMD9 BMD _AE14 103 33 AFi4 BMDI0 BMDI2 acio 104 34 GND P GND 1 35 AD14 BMD BMDi5 Acie 106 36 ABiG6 BMDi4A BMDI6 AK8 107 37 _ 5VDC GND 108 38 AH BMD1i7 BMDig AF9 109 39 AG7 BMDi8 BMD AJ 10 4 GND GND J 4 AD BMD BMD23 AGIO 112 42 AR9 BMD2 BMD24 AH 113 43 GND 33VDC tt4 44 AE7 X BMD2 BMD277 AF8 115 45 AJ8 BMD26 BMD28 aes e
4. AVAIO U9 71 MM 1 5vDC GND 72 2 us Avali AvAIO T8 73 3 TO Avalo AVAJO w 74 MM 4 GND V GND 5 MEM 5 uz _av A los __av A lor 7 76 6 ve AVAIO AVAJO w 77 7 GND 33VDO 78 8 ve AVAIO Avalo Te 79 9 v avalo AvVAJO12 AAG so MEM o GND 9 GND J j et MM ws _ av A lo 8 P AVAIOIS v5 82 12 We CAV A lo a AVAIO6 AAS 83 j 45VDC GND J 84 14 U2 AV A lo AVAIJOI0 Ut 85 s vs _ av A lo a AVAJO0 75 86 MEME e GND GND e MEM r v2 AVAIO AVAIOB Vi 88 18 U5 AVAIO2 AVAJOM 174 89 j 19 GND __ _ 33vDC 90 20 w2 AVAIO25 AVAIO7 w se 21 TS AV A026 Avalos U4 92 MEME 2 GND GND 9 MEM 3 v AVAIO9 AVAIOSI aa 94 24 U3 AVAIOS0 AVAIJO2 V4 95 25 445VDC GND 96 26 AA AVAIOSS AVAIOS AB2 97 27 va AVAIOSM4 AVAJO6 w 98 28 GND GND 99 MEME 2 B AVAIOS AV AJO39 AC2 100 30 w3 AVAIOS38 AVAIJO0 Ya 100 3 OGND O 33VDC 102 32 ape AVAIO4 AV AJOd3 ADB 103 33 Y2 AVAIO42 AVAjJO44 AM 104 MN 34 GND GND 10
5. s yyy yl n sekan r x Kn ay HEKE MEN kol yaya e y k ki x V nn nn kk kn balad sen e h asas a MER r kek 28 Figure 7 Barrel nel Ree al Tee QA ai 29 tables Ordering Into ye TTT 5 Table 2 JTAG Headers d TAGS S d TAGAV PI OD Utorrent till 6 Table 3 Virtex ll Pro Attributes by Density Speed Grade 10 Table 4 HSSDG2 Connector Pin outs P2 amp PO ed ao 10 Table S SPP Connectors Pin Outs PA S PD cus tme eu neka ew Dem e ua diem me RU vas Ve cnn bus cuia P Hom VOR AN ARP cam t AER EN Pan ERN URS 11 Table XPAIS Elost Connection anota io T etucep adir PUN tut ea da 12 Table 7 Timing Parameters tor SDRAM Peripheral aes ito oerte BINAL lea dela W n ese s dod e kn suas ved te doas ABA Dre Me Doe KENE YA WEN 14 Table 8 Timing Parameters for Flash Peripheral u i kk KEK EKE KE KK KEKE KAKA KK KAKA siis nass risa assis sa KK A KK KK kk 14 Table 9 System AGE MPU nterface Conn GilOn Sia 16 Tablest0 e Ethernet PHY Strap Oi Ole lea sies sedc utet umts ve mae eot Odes te uetag curren qu Ea EA Dd vb vsu VR datas S eee 17 TaBe Bal a e n 7220 E ORICISOUL Lc cadat xL eu N eer Pace E Va uM Eam DEM T 18 Tabl 12 9 H9292 Connector INOUE Lar pe asi c MR EPOR LPrIPEE rrr 18 Table 13 Custom Serial GableBIFHSOUE a k c EQ n wines a Cn h Al nln uet WE bke n PAR OC e a kk a ania uade a Rue W pk e ak in W En fupe Ea Aon 18 pex cd eMe c
6. 115 J JL 45 Mz AN DSR Av p28 mMm e 46 OND GND tt7 47 _ Ne AVD29 AVD381 R9 118 48 P9 AV DBO AV CTIO H1 e j 49 VDO GND 12 so E14 AN CTL Av cria Di4 121 fJ s C AV CTL AV CTA _p s 12 MM 52 OND GND 12933 MM 53 G2 AV CTS AVT Gti 124 54 Dt AvCTL6_ Avcris E1 05 MEME 55 GOND 33VDC 16 se Gio Av CT AV CTLI1 DiO 127 57 Eto Av CILi0 Av CTLI12 Fio 183 MEME 55 GND GND 129 MMN se _ ro av CTLI3 AVOTLI5 A8 130 60 BB AV CTLi4 Avcrite C8 131 j s 5wDc0 GND a 6 C7 AVOT7 Av cCrita D8 s MN 63 D7 Av cr i8 Avcrieo G9 134 64 OND GND s MM 65 G8 AV CTL Av CTL23 C15 136 66 B15 AV CTL22 AVBUSTMS 17 67 OND ____ 93VDC 138 MM 68 AVBUS TDO AVBUS TDI 139 69 AVBUS TCK JTAG_TRST 10 dj 70 OND Table 19 AvBus Connector P10 Pin out Copyright 2003 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc All other trademarks are property of their respective owners Avnet Electronics Marketing 24 of 33 Rev 1 0 04 18 2006 Released Literature ADS 003704 Name FPGA Connector PIN FPGA Name PIN PIN
7. 14 15 Gond PMCGNTO Cil s 17 C5 PMCREQI OV 18 19 r 83V po PMC ADT R9 20 21 me PMCADO8 PMCAD27 N7 22 28 N6 PMCAD2 k Grud 2 25 Ground ___ _ __ 2 1 PMCCBES R2 26 29 N2 PMCADI9 r b jii ov r so _ 31 o a PMC ADI M2 32 33 J8 PMC FRAME U U Ground 34 35 r Ground _ J A4 2H d PMCIRDY J7 se 37 D5 PMCDEVSEL 50V 38 39 Ground Tr Dos nen X 40 41 PCHFRSVD PCHRSVD 42 43 N4 PMCPAH _ Ground 44 _ 45 fav po PMCADIS M 46 49 J3 PMCADO p j 50V BU 51 Goma X _ 3 PMCCBEO P2 52 55 Ja PMCAD4A _ _ Ground X 56 57 u PMCAD3 K4 58 59 K5 PMCAD PMC ADI ke so 61 L5 PMCADO 50V 89 63 Ground _____ REQe4 64 Table 22 PMC Connector P6 Pin out P7 PMC Connector 2 Pin FPGA Signal Signal FPGA Pin 1 ev EPCH TRSTR 2 A TMS mO 4 A TD Ground f J 6 O7 PGownd PORS 8 9 PPCHPSVD PCHKRSVD 10 1 BUSMODE2 J MZ bav _ 13 D3 PMCRSTO _ BUSMODESK 14 15 33V BUSMODEAK
8. 35 AG3 AVAIO45 AV A JO47 AG2 106 36 AAS AVAIO46 AV A IlOd8 AB4 107 37 5vDO GND 10 38 AG AVAIO49 AV AJO5 1 AH4 109 39 ABS AVAIOS0 AVAIJO2 AC4 10 40 GND GND 111 MEME 4 n AVAJlO53 AVAJO55 AH 112 42 AC3 AVAIO54 vs3 O8 L7 113 MM 42 GND 33vDC 1144 44 s _ves_ ose AVCTL20 Ho 15 45 H9 Av CTL24 AvCT27 H2 116 MEME 46 9wGND __ GND t7 MEM 4 J5 AVCT 5 va3al0 Ji4 118 48 Js vg3_loo vaalo2 Hi4 19 49 SDC GND 12 50 Je V33103 V 33I105 J Gl4 121 51 HS V33104 v83Il66 Fita 12 5 GND GND 1f23 53 H4 V88IO7 V 3 109 H3 124 54 Gt V881O8 V3 O10 _e s 15 55 OGND __ 33VDC 120 se es _ vas o 1 X V8 3 1013 E13 127 57 G4 vas o e Vas 1014 Fiz 128 J 5 GND 9 GND 12 59 Ft _ vas o s V8 3 1017 E12 130 60 F3 V33 1016 vsasjiola Fit 131 EAM s 5vbC GND 13 62 F4 _ves o o V 3 O21 Cil 133 63 Et _ V831O20 X V83 1022 Aito 134 64 GND GND J 135 MEME 65 E3 _ vas ozs va3l025 Bio 136
9. 46 GND GND tt 47 ADM BMD29 BMD31 Ac9 118 48 ACi BMD30 GPIO BCS AG5 e 49 9 9 5VDC GND 4 4320 MM 5 ne BWE X AG25 121 51 AHS BOER nc j 122 MEM s2 GN GND j 123 MEM 5 gt i M Te a A Qs e awe ae Bz TT x po nc 17 857 vo nc 1 2 5 r 5 ep O ND 19 59 _ ne o nc i 1 30 6 wc nc t MN o vc DO ND 82 6 nme nc 13 ss ne pov _ _ 134 GND A GOD J 135 65 ne nc 9 MW oo vc J L n6 c T o 0 67 GND 83VDC J 138 68 me lo nc o i 19 6 ne nc J 10 MN 7 OOND O Table 18 AvBus Connector P8 Pin out Copyright 2003 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc All other trademarks are property of their respective owners Avnet Electronics Marketing 23 of 33 Rev 1 0 04 18 2006 Released Literature ADS 003704 Name FPGA PIN Connector i FPGA Name PIN Ava a 71 PA VC GND 72 MM 2 v ANA c2 73 3 Ci AA Aam D3 74 4 GND _ GND 75 HH D5 v AVA7 amp 76 6 G6 Aava ANAR 0 77 7 4 GND 33VDC o 78 8 J8
10. 2003 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc All other trademarks are property of their respective owners Avnet Electronics Marketing 3 of 33 Rev 1 0 04 18 2006 Released Literature ADS 003704 1 0 Introduction The purpose of this manual is to describe the functionality and contents of the Virtex Il Pro Development Kit from Avnet Electronics Marketing This document includes instructions for operating the board descriptions of the hardware features and explanations of the example projects 1 1 Description The Virtex Ill Pro Development Kit provides a development platform for engineers designing with the Xilinx Virtex Il Pro FPGA The board provides the necessary hardware to not only evaluate the advanced features of the Virtex II Pro but also to implement complete user applications Example projects are provided to help the user understand the design tool flow of the Xilinx Embedded Development Kit EDK software environment 1 2 Features FPGA Xilinx Virtex Il Pro XC2VP7 20 30 FF896 High speed Serial Communication Two HSSDC2 connectors InfiniBand user may replace with Fibre Channel Pads for a XPAK module 10Gb Ethernet OC 192 Receptacles for two SFP modules Gigabit Ethernet Fibre Channel InfiniBand Memory Micron DDR SDRAM SODIMM 128MB expandable to 1GB Micron Mobile SDRAM two 8Mbit x 16 devices 32MB total Cypress Asynchronous SRAM 512Kbit x 32 2MB total Intel StrataFlash 1
11. R S P Re 29 4 0 SOWAS D gl n We VA EN d dadas betont MD Di lan Na 29 4 1 WEIS Tete De o MERE 30 4 2 PLB MEMNON PO OC ES No r r DO m 30 4 3 OPB Memory miele E EL rsen 31 4 4 TIERE K gt l ela s pol sere cie T m eee I 31 4 5 Einemetrenpnetal DISCUSSION REI 31 4 6 AYVMOM DeDUO INO MILO CET Oo oo S t Tem 33 4 7 Board Support Package tor LIL us ues Kik ee tiui oie tete a Rae iit tef en tite omae indita fuia ade w le iia 33 5 0 l Si OI DANNES E Y UI um N Ne 33 Copyright 2003 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc All other trademarks are property of their respective owners Avnet Electronics Marketing 2 of 33 Released Rev 1 0 04 18 2006 Literature ADS 003704 Figures Fig r 1 Virtex ll Pro Development Board PIGIU cor qu ote duod oer acacia ien bead cada k da ek l k d ka w u ewa da resta kk ka b dal eku w daka bad kulak k l xaka 5 Figure 2 Botridary S an Ghain in iMPAQ T outside da Kal ka x ara keda 6 Figure 3 Virtex 1l Pro Development Board Block Diagram e sees kk kk kk ak kk a nennen nnne nnn kK kk K KK K KK K KK KK KK nans 9 pelle Ol k le Rad PAUL E ere teste ee ener nr ee Va 17 rigure s Bridge DESIGN Block DIA NM PN ita 19 Figure 6 High Current Power Connector n TO
12. The Bridge design allows both the Virtex II Pro and the PCI host to access the SRAM and Flash memory The Bridge acts like a bus switch either connecting the Virtex ll Pro shared memory bus or the PCI bus to the memory The SRAM and Flash busses are separate and individually selectable The Bridge makes the bus selection based on the ownership bits in the Control Register Bit 4 of the Control Register SRAM OWNER indicates the owner of the SRAM bus Bit 6 of the Control Register FLASH OWNER indicates the owner of the Flash bus For both ownership bits logic 0 means the Virtex ll Pro bus has control and logic 1 means the PCI bus has control Ownership must be given by the current owner of the bus to the other client and cannot be taken away by the non owner The Bridge design gives the Virtex Il Pro ownership during reset the Virtex Il Pro is the default owner of both the SRAM and Flash busses A PCI transaction to SRAM BARO or Flash BAR1 when the PCI bus is not the owner will result in a disconnect without data or retry condition A Virtex Ill Pro read transaction to SRAM or Flash when the Virtex II Pro is not the owner returns OXBADDFEED as the data The Virtex 1l Pro cannot access the PCI Control Register directly Instead the Virtex 1l Pro accesses the ownership bits through a command status register in the shared bus memory map referred to as the Virtex Il Pro Status Register The Virtex Il Pro Status Register is a read w
13. The user can make a change to the software re compile and re generate a bit file without having to run through synthesis and implementation over again To do this select Compile Program Sources and then Update Bitstream Finally just download the bit file to the board using the Download option The zero bit is the left most or most significant bit on a PowerPC bus Therefore busses in the hardware description file are defined as 0 to 31 for example To align the busses properly with the external memory the bus signals were swapped end for end or mirrored in the user constraint file system ucf file in the data folder of the PLB Memory Project This is transparent to the software A datasheet has been created for each example project See the PLB External Memory Example datasheet for more information on how to the use the PLB Memory Project Copyright 2003 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc All other trademarks are property of their respective owners Avnet Electronics Marketing 30 of 33 Rev 1 0 04 18 2006 Released Literature ADS 003704 4 3 4 4 4 5 OPB Memory Project This example provides a PowerPC interface to external SRAM SDRAM Flash and UART using the On chip Peripheral Bus OPB The PLB to OPB Bridge peripheral is used to provide access to the OPB from the Processor Local Bus PLB The opb sdram peripheral handles all transactions between the OPB and the off c
14. 0 Hardware This section of the manual describes the hardware of the Virtex Il Pro Development board The hardware was designed with the Virtex Il Pro FPGA as the focal point The block diagram is shown in Figure 3 XPAK m R RRR RRR 898 MESSEN NN N N WW mm 10GE or 00192 H A Single XPAK Rocket I O amp a combination of 2 SFP amp 2 HSSDC2 SFP SFP HSSDC2 HSSDC2 PMC 32 bit 50 Kit does not include modules SODIMM Nwe Clocks AvBus DDRSDRAM ce 4 Micron LL L MT8VDDT1664HDG 265B2 lt gt Console DMOS SDRAM CRAS 10 100 1000 Ethernet PHY MT48V8M16LFFF 8 alert il Bulles SelectMAP System ACE cres AvBus sa Sd R232 gt VER PCI Memory Space Right Angle Cypress CY7C1062AV33 12BGC EN PROM Ek gt Xilinx seg debes XC18V02VQ44C row of 8 FLASH E 16MBytes Clock Voltage Clamp PCI Edge Connector Figure 3 Virtex 1l Pro Development Board Block Diagram Copyright 2003 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc All other trademarks are property of their respective owners Avnet Electronics Marketing 9 of 33 Rev 1 0 04 18 2006 Released Literature ADS 003704 3 1 Virtex ll Pro FPGA The Virtex ll Pro Development board was designed to support the Virtex Il Pro FPGA in the 896 pin flip chip BGA package FF896 T
15. AF9 V25 A1025 V25 A IlO27 AE20 91 21 ADI8 V25A1IO26 V25A 1028 AHi8 92 22 GND GND 9 23 AF20 V25 A1029 V25 A1031 AH21 94 24 AEt9 V25A1O30 V25 A 1032 AH20 95 25 5VDC GND J 96 26 AJ V25A1O33 V25 A 1035 AK21 97 27 AG20 V25A1O34 V25A O36 AF28 98 28 GND GND 99 29 AF27 V25 A1037 V25 A 1039 AE28 100 30 AF30 V25A10O38 V25 A 1040 AF29 101 31 X GND J 33VDC 102 32 AE27 V25 A1041 V25 A IO43 AD28 103 33 AE30 V25 A1042 V25 A 104 AE2 104 34 GND GND J 1 MEN 35 D V25 A1045 V25 A IO47 AC26 106 36 AD30 V25 A1046 V25 A 1048 AD29 107 37 5VDC GND 108 38 AC25 V25 A1049 V25 A IO51 AB24 109 39 AB26 V25A1050 V25A 1052 AB2 110 40 GND GND m 41 AB23 V25 A1053 V25 A 1055 Y23 112 42 AA24 V25A1054 V25A 1056 AA23 13 43 X GND 33VDC 44 Y24 V25 A1057 V25 A 1059 123 115 45 23 V25A 1058 V25A 1060 K24 e 46 4OGND 997g GND 117 MEM 47 24 A I061 V25 A 1063 J25 118 48 H26 V25A1062 V25A 1064 H27 119 J 49 5VDC GND 120 50 J26 V25 A1065 V25 A 1067 _H25 1
16. BAR1 PCI Core 64 bit 66MHz BAR2 Xilinx PCI LogiCORE Virtex Il Pro Shared Memory Bus P m BA PCI Bus Signals Figure 5 Bridge Design Block Diagram The block diagram in Figure 5 shows the functionality of the Bridge design that will be implemented Check the readme file in the documents folder bridge_readme txt for information about the supported functions per release version Contact your local Avnet FAE to get new versions when available The Bridge design implements a target only PCI interface using the PCI LogiCORE from Xilinx The full range of the SRAM and Flash memories are mapped in the PCI memory space The system registers for the Bridge design are also mapped in the PCI memory space The memory map for the Bridge design is shown in the table below Base Address Register BAR Offset Memory Register BARO 0x00000000 0x001FFFFF SRAM 2MB BAR1 0x00000000 OxOOFFFFFF Flash 16MB BAR 0x00000000 Control Register 0x00000008 LED Register Table 14 PCI Memory Map Both the SRAM and Flash have a one to one mapping so that address 0x0 of the memory is offset OxO in the corresponding Base Address Register BAR While the Bridge design uses the
17. II Pro Development Kit on the CD labeled Xilinx Virtex ll Pro Development Kit Board Support Package 4 2 XPS Example Projects o Processor Local Bus PLB Memory Project o On chip Peripheral Bus OPB Memory Project o Rocket I O MGT Peripheral Project Ethernet Peripheral Discussion Avmon Debug Monitor Board Support Package for Linux The implementation of an Ethernet peripheral is also discussed including an example Microprocessor Hardware Specification MHS file The Virtex Il Pro development board is set to program the Virtex Il Pro FPGA with a demo application stored in the CompactFlash card when the board is powered up out of the box This demo application is a boot loader that loads our Avnet debug monitor Avmon software stored in the Flash memory See the Avmon section for more information The Virtex ll Pro Development Kit CD contains all of the example projects and bit files PLB Memory Project This example uses the Processor Local Bus PLB to interface with the PLB SDRAM peripheral which is a standard peripheral included in the EDK The peripheral handles all transactions between the PLB and the off chip SDRAM memory allowing the PowerPC access to the 32MB memory The timing parameters of the SDRAM peripheral have been specifically set up for the Micron Mobile SDRAM devices on the Virtex Il Pro shared memory bus The PLB clock frequency is set for 100 MHz since the 100MHz oscillator input is being used The timi
18. board are used as reset signals to the Bridge and the Virtex Il Pro Bit O of the Control Register BRG RESET indicates the status of the Bridge reset which is set by the pushbutton labeled SW2 Bit 1 of the Control Register TRGT_RESET indicates the status of the Virtex ll Pro reset The Bridge provides an active low reset signal to the Virtex 1l Pro FPGA when pushbutton SW1 is pressed or when the user writes a 0 to bit 1 of the Control Register The user must then clear the reset by writing a 1 to bit 1 The reset signal is on Virtex ll Pro pin AH8 labeled CLKEN on the schematic RCFG SRAM RCFG TIMEOUT TRGT DONE Setting bit 2 of the Control Register RCFG SRAM enables the configuration controller which programs the Virtex ll Pro with the contents of the SRAM memory starting from offset 0x0 BARO The controller uses the SelectMAP interface of the Virtex Il Pro to configure the FPGA with a bit file stored in the SRAM memory The FPGA must be put in SelectMAP mode by installing a jumper on JP8 before booting the PC containing the board The SelectMAP interface requires the bit file to be generated with CCLK as the startup clock CCLK is the default option in the Project Navigator software of the Xilinx ISE The configuration controller clears bit 2 in the Control Register upon completion of the configuration process The controller sets bit 8 of the Control Register RCFG_TIMEOUT if the D
19. in the boundary scan chain using the Xilinx iMPACT software and a download cable Section 2 2 2 describes how to generate System ACE configuration files and load them onto a CompactFlash device for System ACE configuration of the Virtex Ill Pro FPGA Section 2 2 3 goes through the steps to use the PCI Utility to reconfigure the Virtex Ill Pro FPGA when the development board is installed in the PCI slot of a PC Software BSP This section of the manual describes the example EDK projects included in the kit Copyright 2003 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc All other trademarks are property of their respective owners Avnet Electronics Marketing 29 of 33 Rev 1 0 04 18 2006 Released Literature ADS 003704 4 1 What is included All of the example projects included in the Virtex Il Pro Development Kit were created in the Xilinx Embedded Development Kit EDK version 3 2 The examples include the Xilinx Platform Studio XPS project files and supporting directory structures all of the required files to run the XPS projects The user must have both the Xilinx Integrated Software Environment ISE version 5 2 and the EDK version 3 2 software installed to utilize the example projects The following list provides an outline of the Board Support Package section The XPS example projects are included on the Virtex ll Pro Development Kit CD The board support package for Linux is included in the Virtex
20. of the features in Avmon see the document titled A user s guide to Avmon on the development kit CD Board Support Package for Linux The BSP for the Virtex Ill Pro Development board is for the Linux kernel version 2 4 and the distribution RAM disk etc is ELDK from www denx de labeled Xilinx Virtex Il Pro Development Kit Board Support Package See the Virtex 1l Pro Development Kit Board Support Package document for user information 5 0 List of partners P cron The future of memory National Semiconductor The board support package for Linux is included in the Virtex Il Pro Development Kit on the CD XILINX Copyright 2003 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc All other trademarks are property of their respective owners Avnet Electronics Marketing Released 33 of 33 Rev 1 0 04 18 2006 Literature ADS 003704
21. phy CI LOC GAI NET phy EXOCKT LOC DI NET phy_rxdy LOC E20 NET phy rxer LOC D23 NET phy_txd lt 0 gt LOG E24 NET phy_txd lt 1 gt LOG p21 NET phy txd 2 LOC e C24 NET phy txd 3 LOG e Ug NET phy Exck LOC T NET phy_txen LOC G23 NET phy_txer LOC G22 NET phy txck TNM NET phy txck TIMESPEC TS phy txck PERIOD phy txck NET phy rxck INM NET phy rxck TIMESPEC IS phyorxck PERIOD phy rxok 25 MHz GBE_RST GMII_COL GMII_CRS GMII_RXDO GMII_RXD1 F GMII_RXD2 GMII_RXD3 GMII_RX_CLK GMII_RX_DV GMII_RX_ER GMII_TXDO GMII_TXD1 GMII_TXD2 F GMII_TXD3 f GMII TX CLK GMII_TX_EN GMII_TX_ER 25 MHz HIGH 50 At this point the Ethernet peripheral has been added and mapped to the hardware system In order to implement the system the user must have a license for the Ethernet peripheral core Otherwise XPS will get most of the way through place and route and then error out when it cannot find the license Check the Xilinx web site for availability of demo licenses or to purchase the Ethernet MAC core 4 6 4 7 Avmon Debug Monitor The Virtex Il Pro Development board is set to load the Avmon debug monitor when the board powers up out of the box The primary purpose of Avmon is to perform hardware level testing of the memory and communication ports on the development board For a complete description
22. receiver buffer ownership bit enables the receiver The example C code provided in the code folder contains functions to transmit a single packet transmit multiple test packets transmit received packets multiple times fill the transmit buffer with pseudo random data and provide network statistics The OPB Simple MGT Peripheral document in the MGT Peripheral Project directory discusses the memory map and use of the MGT peripheral in greater detail Ethernet Peripheral Discussion The purpose of this discussion is to help the user implement a system using the lite version of the Ethernet MAC peripheral from Xilinx The emac lite peripheral is a subset of the full version of the Ethernet MAC core that has an OPB user interface Including the emac lite peripheral in one of the above projects requires adding the Ethernet peripheral instance and port mapping to the Microprocessor Hardware Specification MHS file adding the software settings to use the Ethernet MAC driver and adding the Ethernet PHY connections to the user constraint file Two items need to be added to the MHS file the Ethernet peripheral instance and the port mapping of the PHY signals The process can more easily be demonstrated by adding the Ethernet peripheral to an existing project like the PLB Memory Project discussed above Open the PLB Memory Project in the XPS software Open the MHS file from the project tree Add the following peripheral instance at the bottom of
23. should be used in applications requiring over 4 Amps There is no protection for reverse power supply polarity so take the necessary precautions to ensure that the center pin is 4 75V 5 25V and the ring is ground Copyright O 2003 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc All other trademarks are property of their respective owners Avnet Electronics Marketing 28 of 33 Rev 1 0 04 18 2006 Released Literature ADS 003704 3 8 4 0 o 0 076 in 1 93 mm pin diameter 4 0 25 in 6 3 mm housing diameter 5 Volts GND Figure 7 Barrel Power Connector J7 See Section 2 1 for information on how to get started using the AC DC Converter and the power supply daughter board Configuration The Virtex Il Pro Development board supports multiple methods of configuring the Virtex Il Pro FPGA including Boundary scan System ACE CompactFlash and PCI All of the JTAG enabled devices on the board are a part of the boundary scan chain In addition the expansion connectors may be added to the development board boundary scan chain to incorporate the boundary scan chain of an expansion board These expansion connectors include the PCI edge connector the PMC connectors and the AvBus connector P10 The header labeled JP15 is used to select which connectors belong to the chain The standalone position a jumper installed across pins 2 3 has only the JTAG enabled devices on the development board in
24. supply daughter board Do not force the card in the socket If having trouble with insertion just turn the card over and try it The card is keyed and will only fit one way Before applying power to the board set the following switches Set the CFG MODE switch on the dipswitch labeled S1 to the default position OFF This will set the System ACE controller to load the Virtex I Pro on power up when released out of reset Next set the CFG ADDR switches to the address of the bit file to be loaded Switch 3 is the MSB and switch 1 is the LSB A switch in the OFF position is a low or binary 0 all CFG ADDR switches off is address 0x0 Finally set switch 1 on the dipswitch labeled S2 to the ON position to release the System ACE from reset and apply power to the board The DONE LED for the Virtex Il Pro FPGA D22 should be illuminated to indicate a successful configuration Also the System ACE Status LED labeled D8 will illuminate upon a successful System ACE configuration of the Virtex Il Pro The System ACE Error LED labeled D9 will illuminate if an error occurs The Error LED will also blink if the CompactFlash card is not plugged in To re load the FPGA with a bit file at a different address change the CFG ADDR switches to the desired address and then toggle switch 1 on dipswitch S2 OFF then ON to reset the System ACE controller PCI The Virtex Ill Pro FPGA can be configured over PCI by running the Avnet Elect
25. to discharge static build up insert the development board into an open PCI slot The Virtex ll Pro Development board requires two PCI slots since the daughter board protrudes over the adjacent slot The power supply daughter board must be connected to the development board since it supplies the 2 5VDC rail Do not plug the AC DC converter into the daughter board Power is derived from the PCI slot when plugged in Make sure the Copyright 2003 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc All other trademarks are property of their respective owners Avnet Electronics Marketing 7 of 33 Rev 1 0 04 18 2006 Released Literature ADS 003704 2 3 development board is firmly seated in the PCI slot and that it is not touching any bare metal components in the computer case Replace the cover and turn on the computer Copy the PCI Utility folder from the CD that comes with the kit to the local drive of the computer containing the Virtex Il Pro Development board The ADS PCI Utility User Manual inside the folder contains the installation instructions After installation is complete run the PCI Utility program In the PCI Utility window the Open Board field should indicate the Virtex 1l Pro Development board has been detected To configure the Virtex Il Pro FPGA click the downward arrow to expand the Mode menu and select Configure from the list A browse window will open to prompt the user to browse to t
26. 21 51 H28 V25AIO66 V25A 1068 G20 122 52 _ GND GND 123 53 G27 _v25 A_ I069 V25A 1071 Ges 124 54 F27 V25 A1070 V25 A1072 F23 125 55 GND 33VDC ze 56 G30 V25 A1073 V25A 1075 F29 127 57 E28 V25AIO74 V25A 1078 E29 128 58 GND GND 19 MN se F30 V25 A1077 V25 A1079 E27 130 Jl J 60 E30 V25 A1078 V25A 108 C22 131 s 5VDC GND J 132 6 B22 _v25 A_ I081 V25 A J O83 A21 133 63 B21 V25 A1082 V25A 1084 C21 134 64 X GND GND s es C20 V25 A1085 V25 A 1087 F19 136 66 F20 V25A1O86 c 1 y 137 67 GND 33VDC 1388 68 e nc 959 MEM 69 ne h c j vo MM 7 GND Table 21 AvBus Connector P12 Pin out Copyright 2003 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc All other trademarks are property of their respective owners Avnet Electronics Marketing 26 of 33 Rev 1 0 04 18 2006 Released Literature ADS 003704 P6 PMC Connector 1 Pin FPGA Signal Signal FPGA Pin ee E AMO TOR sce ee ee ee 3 po Goma ______ ks PMCINTAI C2 4 5 J o o INBE ITCH vr 6 LT BUSMODEIR OV 8 9 tI PCRSVD f 10 On J Ground ____ i iu _PCERSVD 12 13 C4 CLKPMC CLK Daund
27. 64 bit PCI core only 32 bit transactions are supported to access the SRAM Flash and registers The upper 32 bits of address data AD 63 32 are ignored by the Bridge design All addressing is on a four byte boundary All of the base address registers are set up in the memory space versus I O space BARO supports both reads and writes to the SRAM memory BAR1 supports only read transactions to the Flash memory BAR2 supports both reads and writes to the Control and LED registers Copyright 2003 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc All other trademarks are property of their respective owners Avnet Electronics Marketing 19 of 33 Rev 1 0 04 18 2006 Released Literature ADS 003704 The Control Register provides the user with the ability to initiate a reconfiguration of the Virtex ll Pro put the Virtex ll Pro in reset and assign ownership of the SRAM and Flash busses The Control register also provides status information The bit mapping of the Control Register is shown in the following table Register Name PCI Control Register BAR Space BAR2 Address Offset 0x00000000 Power Up Value 0x00000000 E H N E Mao vere TIT E CO CC mme mor pone MORADO COPIAN AO Torna Table 15 Control im Bit Map L u a E E HN E j fi El The upper 16 bits of the 32 bit Control Register are not used and always have a value of zero BRG RESET TRGT RESET The two pushbuttons on the
28. 66 E4 vas 1024 X V83 O26 B9 137 ez OGND ___ 33VDC 138 68 Di _ vas 1027 V833 O29 Cito 139 69 D2 vas O28 vssioo co vo MM 7 GND Table 20 AvBus Connector P11 Pin out Copyright 2003 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc All other trademarks are property of their respective owners Avnet Electronics Marketing 25 of 33 Rev 1 0 04 18 2006 Released Literature ADS 003704 Name FPGA Connector PIN FPGA Name PIN PIN V25AJO0 AHto 71 1 _ _ 5vpc GND J 72 2 ak o V25A101 V25 A103 AGI 73 3 AJO V25AIO2 V25A 104 AA7 74 4 OOND p k GND 75 MEN 5 u _v25 A lO5 V25 A107 _AEt2 76 6 Aag V25AIO6 Vv25A 108 AF 7 MN 7 _ OND 9 33VDC 78 8 AFi2 V25AIO9 V25 A 1011 Aia 79 MN 9 AE V25A 1010 Vv25A 1012 Y7 80 o OON GND 898 MEM 11 AH s _ v25_A_ IO13 V25A 1015 ABI4 82 12 va _v25 A_ I014 V25 A JO016 AF13 83 s 5VDC GND J _ 84 14 Ac 4 V25A1017 V25 A1019 ACtg 85 15 AD13 V25A10t8 V25A 1020 AC13 86 16 X GND GND J 87 17 AFi8 V235 A1021 V25 A1023 AGI8 88 18 AB r V25 A1022 V25 A 1024 ACct7 89 19 GND 9 33VDC 90 20
29. 6MB total CompactFlash Card Communication National 10 100 1000 Mbit s Ethernet PHY RS 232 serial ports PCI PCI Bridge Xilinx Spartan IIE XC25300E FG456 FPGA Windows based GUI interface Configuration or File Transfer amp System Control Universal PCI Connector 32 bit or 64 bit slot compatible Support for both 3 3V and 5 0V PCI signaling Board I O Connectors 32bit PCI Mezzanine Card PMC Connectors Four 140 pin general purpose l O expansion connectors AvBus Power Power Supply Daughter card 3 3V and 2 5V rails 14A total 50 Watt AC DC 5 0V power supply National Linear regulators Configuration u Bridge Spartan llE o Xilinx PROM XC18V02 VQ44 Target Virtex ll Pro o Xilinx System ACE CF o FLASH or SRAM via PCI and Windows Application 1 9 Demo Applications The Virtex Ill Pro Development Kit from Avnet Electronics Marketing comes with example projects designed in Xilinx Platform Studio XPS XPS is a software tool in the Xilinx Embedded Development Kit that provides the user with a single tool flow for creating both hardware and software systems The example projects help the user to more quickly learn the XPS tool and develop user specific applications by leveraging already tested and functional designs The example projects that will be discussed in detail later in this document are listed below Memory Projects o Two memory projects OPB memory project and PLB memory project o OPB memory project is a
30. Ava9s AV AM N 79 o M _ Av AIO AV AIS Pa j so MN 0 OND GND 8 J PAV A AV A15 72 8 amp MN 12 P2 AVA PAV AIG rs 835 a 13 _ 5vpc GND 84 44 R2 AVAt7 O AV Ai RA 85 s R AVAB AV A20 R6 se j s GND GND 87 MEME r RAV A AV A23 R7 88 Jl s P7 AVAR AV A24 R 89 19 GND 33VDC 90 p 20 PB AVA5 Aver Ee o MEME 23 E15 AVA AVAR E7 0o MN 2 GND GND 9 MEME zaza Bs AVA CAVAS HHR 94 24 A3 AVA3X AvVDpo _ s 9 B8 25 9 _ 5vpc GND 96 20 K6 AvD AD K 9 27 K5 AV aD 4 os MEME 3 GND GND 9 MEME zo H2 Aav D5 AV DT J32 10 so Ji avD Avos K to MN s J 3 COND 9 33VDC o2 32 Ja AVDO Aa Dn t2 10 3 k2 AV TO ADIS K 104 34 OND GND 10 f s j ti ADIS PAV DIS M 106 se M3 AV D 4 ADe 14 107 MM 37 5vpc CO GND 108 3 M2 AV AV Dio N2 109 J 3 M AV AV D20 Pm 10o 40 OND GND 111 MM 4 ma _ av p21 ADS Ns 112 42 M5 AVD22 Aa p24 m m 43 OND 33VDC 44 Ne AVD25 AV p2z N7
31. FP host connectors Typically both the transmit and receive pairs are AC coupled inside the SFP module The SFP module is powered by the 3 3VDC supply with separate filtering networks for the transmit and receive supplies VccT and VccR The transmit and receive ground terminals VeeT and VeeR are both connected to the same AGND reference XPAK The XPAK is a small form factor pluggable transceiver module for 10 Gbps serial data transmission The XPAK interface on the Virtex Il Pro Development board was designed to run at the IEEE 10GBASE R optical rate of 10 3125 Gbps with a four lane electrical interface at 3 125 Gbps XAUI interface This interface requires a 6 or 7 speed grade Virtex Ill Pro device and has not been fully tested Furthermore the 10 Gigabit Ethernet MAC core from Xilinx takes up considerable resources and may not fit in the 2VP7 density The 5 speed grade part cannot be expected to run at 10 3125 Gbps since the MGTs are only rated at 2 0 Gbps The XPAK interface on the Virtex ll Pro Development board was designed to comply with the XPAK MSA Revision 2 1 with some exceptions to be discussed later The XPAK MSA closely resembles the XENPAK MSA and makes frequent references to it The XPAK form factor was used because its half the size of a XENPAK it does not require a large cut out in the PCB and it has a mid board mounting option allowing the module to be placed anywhere on the board instead of on the faceplate The XPAK connect
32. GA pin numbers of F16 and G16 respectively The transmit pairs on both connectors are DC coupled but have 0 ohm 0603 resistors that could be replaced with capacitors to AC couple the lines The receive pairs are AC coupled by default 3 2 2 SFP The SFP host connector and EMI cages can be used to implement a high speed serial protocol over optical fiber or copper depending on the module used These connectors support data rates up to 2 5 Gbps and can be used for Gigabit Ethernet Infiniband or Fibre Channel The connectors are labeled P4 and P5 on the board The pin outs are shown below Copyright 2003 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc All other trademarks are property of their respective owners Avnet Electronics Marketing 10 of 33 Rev 1 0 04 18 2006 Released Literature ADS 003704 Pin P4 SFP 1 P5 SFP 0 Signal V2Pro Pin Pin Signal V2Pro Pin Pin Signal V2Pro Pin Pin Signal V2Pro Pin 3 2 3 n AGND AGND AGND AGND TX FAULT F8 RX N A4 2 TX FAULT E9 RX N A11 RX P A5 RX P A12 TX P A6 8 LOS E8 TX P A13 TX N A7 9 AGND TX N A14 Table 5 SFP Connectors Pin outs P4 amp P5 Table 5 shows the actual pin numbers in parenthesis of the MGT pins on the Virtex Il Pro FPGA Two of the control signals Transmit Fault and Loss Of Signal are connected directly to the FPGA The FPGA pin numbers for these signals are shown
33. JP17 Sets the mode of the dual purpose pin on the JTAG3 header The center pin is the TRST signal that is connected to the TRST pin of the Ethernet PHY and also pin 1 of the JTAG3 header Install a jumper across pins 1 2 to set pin 1 of JTAG3 to VCC 8 3VDO and tie the TRST signal high used during boundary scan programming with JTAG3 header Do not install a jumper to float the TRST signal for external control used with boundary scan tools that require control of TRST Install a jumper across pins 2 3 to pull the TRST signal low used to put the Ethernet PHY in normal operation Default Installed across pins 2 3 normal operation of Ethernet PHY JTAG CHAIN JP15 Copyright 2003 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc All other trademarks are property of their respective owners Avnet Electronics Marketing 8 of 33 Rev 1 0 04 18 2006 Released Literature ADS 003704 Selects the JTAG chain configuration Install a jumper across pins 2 3 for standalone mode 4 devices in chain System ACE Virtex ll Pro XC18V02 PROM and Spartan IIE FPGA Install jumpers across pins 1 2 and pins 4 5 to add the PMC connectors on to the standalone chain Install jumpers across pins 1 2 pins 3 4 and pins 5 6 to add the AvBus connector labeled P10 on to the standalone chain These settings are described in detail in the Hardware section of this manual Default Installed across pins 2 3 standalone chain mode 3
34. N position to bring the XPAK module out of the reset state The Virtex 1l Pro Development board was designed to comply with the XPAK MSA Revision 2 1 with the major exception being the design of the Adjustable Power Supply APS The fully adjustable supply detailed in the XPAK MSA was not implemented Instead an adjustable voltage regulator is used to supply two of the most common APS voltages based on a jumper setting Place a jumper on JP5 across pins 1 2 to generate an APS voltage of 1 2VDC Copyright 2003 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc All other trademarks are property of their respective owners Avnet Electronics Marketing 12 of 33 Rev 1 0 04 18 2006 Released Literature ADS 003704 3 3 or place the jumper across pins 2 3 for 1 8VDC The user must select the APS voltage level based on the voltage requirements of the module being used It is possible to generate an APS voltage other than the default levels of 1 2VDC and 1 8VDC by replacing either R112 or R113 with a different resistance value See the datasheet for National s LP3966ES ADJ Linear Regulator for the equation to calculate acceptable resistor values The minimum output voltage of the regulator is 1 2VDC The shutdown pin of the APS regulator U12 is driven by the XPAK module detect signal This keeps the regulator in shutdown mode to save power when a module is not installed The APS Sense and APS Set signals on the XPAK module a
35. ONE pin on the Virtex 1l Pro FPGA fails to go high indicating a successful configuration within the allotted time The user may read the DONE pin which is represented as bit 5 of the Control Register TRGT DONE Selecting the Configure mode in the PCI Utility automatically writes the bit file to SRAM starting at offset 0x0 then sets bit 2 in the Control Register to start the configuration and finally responds with the outcome of the configuration based on whether the DONE pin went high success or the timeout flag was set failure RCFG SYSACE Setting bit 3 of the Control Register RCFG_SYSACE resets the System ACE controller causing it to reconfigure the Virtex ll Pro with a bit file stored in the CompactFlash A valid CompactFlash card must be installed and the System ACE controller must be set to load after reset by setting switch 4 of the dipswitch labeled S1 to the OFF position The CompactFlash card can contain up to 8 different bit files The bit file to be programmed is selected by the setting the address binary 000 to 111 with switches 1 through 3 on the dipswitch labeled S1 switch 3 is the MSB switch 1 is the LSB Copyright 2003 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc All other trademarks are property of their respective owners Avnet Electronics Marketing 20 of 33 Rev 1 0 04 18 2006 Released Literature ADS 003704 SRAM OWNER FLASH OWNER TRGT IRQ
36. RO DEVP30 6 Virtex Ill Pro Development Kit with a XC2VP30 6 Speed Grade Table 1 Ordering Information 2 0 User Information This section provides the user with information on how to get started using the Virtex 1l Pro Development board It discusses how to power the board configure the FPGA devices and set up the jumpers 2 1 Power The Virtex ll Pro Development Kit includes a 50 Watt AC DC Converter that plugs into the power supply daughter board on the backside of the Virtex 1l Pro Development board The daughter board is labeled 14A Programmable Power Supply and the AC DC Converter plugs into the high current connector labeled J9 The high current connector is keyed to protect the board therefore it is only possible to insert the power connector the correct way When the plug is inserted into the daughter board and the AC power cord is plugged in to an outlet power is applied to the board It is recommended to plug the AC power cord of the Converter into a power strip with an On Off switch to more easily cycle power to the board 2 2 Configuration The Virtex Il Pro Development board supports three different methods for configuring programming the Virtex 1l Pro FPGA These methods include Boundary scan System ACE CompactFlash and PCI 2 2 4 Boundary scan Programming the Virtex Il Pro FPGA via Boundary scan requires a JTAG download cable not included in the kit The Virtex Il Pro Development board has connectors to supp
37. Table 24 Header JP16 Pin out 2 RIO co co co Co o ND TN N N O 00 O gt N O j 9 O j gt gt O Le sl O J gt J NN La Pin LR m uM 39 Power The Virtex Il Pro Development board uses the National Semiconductor LM2636 Programmable Power Supply designed by Avnet Electronics Marketing Contact your local Avnet sales office to purchase additional supplies separately Avnet part number ADS NSC XP The Programmable Power Supply daughter board mates with the Virtex 1l Pro Development board via the 54 pin header labeled J1 The supply has been programmed to deliver 3 3VDC on VO1 and 2 5V on VO2 The daughter board also passes the 5 0V input from the AC DC Converter to the development board to power the 5 0V rail The 2 5V and 3 3V voltage rails are then regulated to the necessary voltages by on board linear regulators National s LP3966 ADJ Adjustable Linear Regulator is primarily used to regulate the required voltages Separate and isolated regulators are provided to supply the Virtex Il Pro MGT power and termination supplies to limit power supply noise The high current connector that the AC DC Converter plugs into on the daughter board is shown in the following illustration Neu Q 5 Ya Y Figure 6 High Current Power Connector J19 The barrel connector J7 may be used as alternative to the high current connector J19 however the high current connector
38. VEC 0 3 PORT pny col s pm Col DIR ENPUT PORT phy_rxer phy_rxer DIR INPUT PORT phy_txen phy_txen DIR OUTPUT PORT phy_txd phy_txd DIR OUTPUT VEC 0 3 PORT phy reset n sys rst DIR OUTPUT not driven by core PORT phy_txer net_gnd not driven by core active low at phy The MHS file has now been updated to include the Ethernet peripheral Click on the Save All button and then the Save and Resynch Project to incorporate the additions into the system Next add the Ethernet driver by right clicking on the peripheral instance in the project tree it should be called emac_lite and selecting the S W Settings Scroll through the drop menu for the device drivers and choose the emaclite driver and then click OK The last step is adding the pin location constraints to use the on board Ethernet PHY Open the system ucf file in a text editor the file is located in the data folder in the project directory Add the following constraints to the file Copyright 2003 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc All other trademarks are property of their respective owners Avnet Electronics Marketing Released 32 of 33 Rev 1 0 04 18 2006 Literature ADS 003704 NET phy reset n LOC HIS NEL ohy col LOG BAJT NET phy crs LOG esc SU NET phy xxg U LOC D20 NET phy_rxd lt 1 gt LOC H22 NET phy Tl LOC H20 NET
39. Xilinx Virtex XEZA nun HA Ss ANNE T Table of Contents 1 0 Tah cole U le ej tn e 4 1 1 Bere do bo DM DD e 4 1 2 ND DD AEAEE cL r EM n TTT 4 1 3 Eac ADDICANOA SNN a iaa 4 1 4 Ordering A A ES 5 2 0 Sci qil la ier an alo a PH 5 2 1 A 5 2 2 ea nil any ont TT ui E SAIS EID M MEUSE uU EI ME Mu E n E E ere 5 2 2 1 o A A 5 2 2 2 System AGE CompacitlaSi m iia 6 2 2 3 O EE E E N uM E EI ELM I ee I Eu d a I a ee ee eee 7 2 3 A O cA ERE M iinglar 8 3 0 milio i Pe a 9 3 1 o Me I e cs 10 3 2 Highspeed senal COmmunica OM a a N lisis iso 10 3 2 1 A L YE DN N ae oe eee rt tee ee 10 3 2 2 A A S E ERA 10 3 2 3 APAR TTT 11 3 3 MEMON RE e Te Rx rer 19 3 3 1 Mese TTT 13 3 9 2 ASynchrenols SAM lili 14 3 9 9 mcer 14 3 3 4 DDR SDRAM SODIMM scrire sae a Dese _ V _ _ _ _ _ _ _ r_ _ _ _eo r r rrDrr r AE e 14 3 3 5 System ACE CompacirlaS TTT 15 3 4 ein nes aT 16 3 4 1 A uia D RR EE REED RS I T TM cC 16 3 4 2 RS232 Man D TEE 17 3 5 eger Dr ance 18 3 5 1 e a aE A 18 3 5 2 EIH A EEE EA E EE ATE EPEN OE A EE E E AAE E O E EEE E E EET EA oxir 21 3 6 VOC e eio CREE TE E E 21 3 6 1 ANBUS CONNECT E mE EM 22 3 6 2 meses dee ep p A M 22 3 6 3 aisi JUPI sete rA EE T E ET eM 22 3 7 FOS QE PYD AS DD orale e adhe LM eu LU Mi Ru e E M UE Me ME 28 3 8 GOnMOUPAU mM
40. art adding bit files Click on Add File and browse to the location of your first bit file address 0 Click on No when prompted to add another design file to the address only use one bit file per address Repeat the process to add the rest of the bit files and then click Finish to start generating the System ACE files After generating the files the user needs to set up their CompactFlash card reader or PCMCIA adapter to connect the CompactFlash card to a PC or laptop Remove the CompactFlash card from the development board by pulling it out by the top edge There is no release mechanism Follow the instructions that came with the card reader or adapter for set up Once the CompactFlash card is detected should show up as another drive become familiar with the System ACE file structure by looking at the demo files already on the CompactFlash card After looking at the files delete them so they do not conflict with the files about to be added to the card Do not worry about losing the System ACE demo files they are on the CD that came with the kit Finally copy the files generated by iMPACT from the location specified during file preparation and paste them in the CompactFlash directory The CompactFlash card is now ready to be inserted in the Virtex 1l Pro Development board Plug the CompactFlash card into the socket labeled P9 The socket is located on the backside of the Virtex Il Pro Development board underneath the power
41. d to plug JS1 into a standard PC serial port male DB9 The secondary channel is only available with the 2VP20 or 2VP30 devices and connects to the 3 pin header labeled JP6 The secondary channel can also be accessed on the Mini DIN connector by using a Y adapter The adapter should have keyboard mouse split wiring and a male 6 pin Mini DIN connector breaking out into two female 6 pin Mini DIN connectors The following tables show the pin outs for the FPGA interface the Mini DIN connector and the custom serial cable ADS DB9 MD6 CABLE FPGA Xcvr Signal Name pin pin Primary channel Transmit TRGT_TXD1 Primary channel Receive TRGT_RXD1 Secondary channel Transmit TRGT_TXD2 p30 8 Secondary channel Receive TRGT_RXD2 Table 11 RS232 FPGA Pin out Mini DIN Header Xcvr Signal Name JS1 JP6 U33 TXD1 Signal Name DB9pin MD6 pink Table 13 Custom Serial Cable Pin out PCI The primary purpose of the Spartan IIE Bridge FPGA is to provide the user with a PCI interface for development and communication without requiring the purchase of a PCI core The Spartan llE Bridge design enables the Virtex 1l Pro FPGA to read and write memory mapped in the PCI memory space The Bridge also has the ability to reconfigure the Virtex ll Pro with bit files loaded over PCI using the Avnet Electronics Marketing PCI Utility The PCI Utility is a Windows based program that provides the user with a way to read write and load f
42. design meet timing without the slice constraints The development board provides the option of either driving the PCI clock with the FPGA or the 33MHz clock driver by installing R227 The default method with R227 removed is for the FPGA to drive the clock out to the PMC connectors Header JP16 The 40 pin header labeled JP16 on the Virtex 1l Pro Development board is connected to 35 I O pins on the Virtex ll Pro FPGA when a 2VP20 30 is installed None of the pins are connected when the 2VP7 device is used Pin 38 on the header provides either 3 3V or 5 0V depending on the jumper pad installation on JT24 3 3V is the default The tables on the following pages show pin outs for the AvBus connectors the PMC connectors and the header Copyright 2003 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc All other trademarks are property of their respective owners Avnet Electronics Marketing 22 of 33 Rev 1 0 04 18 2006 Released Literature ADS 003704 Name FPGA Connector PIN FPGA Name PIN PIN BMao AH24 71 1 VDC GND 72 2 AG 4 BMA BMa3 AC2 73 3 AE BMA BMM AGa 74 4 GN GND 75 5 A22 BMA5 BMA7 AH222 76 6 ADHIR BMA6 p BMAS ac20 77 MN 7 GN V 33VDC 78 8 ACiO X BMA9 BMA1 ADO0 79 9 AF7 BMA 0 9 BMM2 AEM 80 o GND GND
43. ensure the connections are made correctly Table 2 also shows the pin out of the JTAG4 connector The Virtex 1l Pro Development board provides the user with the ability to add remove devices from the JTAG chain By the default settings the chain includes the System ACE controller the Virtex ll Pro FPGA the XC18V02 PROM and the Spartan IIE FPGA The header labeled JP15 allows the user to select what devices are in the chain This will be discussed in greater detail in the hardware section of this manual Most users will only use the JTAG chain in standalone mode with a jumper installed across pins 2 3 on JP15 It is recommended to start with standalone mode The configuration modes of the FPGAs must be selected before applying power to the board The Virtex 1l Pro FPGA is set to boundary scan mode by default no jumper installed on JP8 To program the Spartan IIE FPGA directly via boundary scan place a jumper on JP9 to set for boundary scan mode Remove the jumper on JP9 to set for master serial mode to load the Spartan llE from the PROM on power up After the download cable chain and modes have been set apply power to the board and open run the iMPACT software to configure the boundary scan devices It is recommended to use the version of iMPACT in the Xilinx ISE 5 1i or later tools Earlier versions of the tools may work but the user will have to add the chain manually instead of using the automatic chain initialization untitled Config
44. er directly or indirectly through the Spartan IIE FPGA Mobile SDRAM Asynchronous SRAM DDR SDRAM SODIMM Flash and System ACE CompactFlash To maximize the number of Virtex ll Pro I O pins available for user applications a single memory bus was used to access the SDRAM SRAM Flash and System ACE CompactFlash This shared bus provides an individual chip select to each memory device but shares the data and address busses The shared bus has three elements that contribute to the loading i e the direct connections to the Virtex ll Pro the Mobile SDRAM the Spartan IIE FPGA and the 32 bit buffer transceiver The Spartan IIE design provides an almost transparent connection from the shared bus to the SRAM and Flash The System ACE CompactFlash resides on the other side of the address control buffer and data bus transceiver The DDR SODIMM bus is separate from the shared bus and dedicated to the SODIMM 3 3 1 Mobile SDRAM Two Micron Mobile SDRAM devices part number MT8V8M16LFFF 8 make up the 32 bit data bus Mobile SDRAM devices were used to accommodate the low voltage requirement of the shared memory bus 2 5V These devices support 2 5V core and I O supplies VDD and VDDQ Attributes of the Mobile SDRAM interface are listed below 32MB total two 8 Meg x 16 devices board supports addressing for up to 64MB u 54 ball FBGA 8mm x 9mm Board supplies 2 5V to VDD and VDDQ BnS access time CL 3 O 125 MHz CL 2 100 MHz The following table
45. erted The direction of the data bus is controlled by the output enable control signal OE of the shared bus During a write the active low output enable should be set high to allow the Virtex ll Pro to drive the bus During a read the output enable should be set low to allow the System ACE to drive read data on the bus The CompactFlash card supplied with the board is a 64 MB Type l card from Toshiba The part number is THNCFO64MMA The System ACE controller supports CompactFlash cards of up to 1 GB The following table shows the connections for the System ACE MPU interface to the shared bus Copyright 2003 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc All other trademarks are property of their respective owners Avnet Electronics Marketing 15 of 33 Rev 1 0 04 18 2006 Released Literature ADS 003704 3 4 Shared Memory Bus to System ACE Controller Connections buffers treated as transparent Shared Bus Signal Name V2Pro pin System ACE pin name ACE pin 70 DO JA _AFto MPDO Dis Table 9 System ACE MPU Interface Connections w NM 69 68 60 Communication The Virtex Il Pro FPGA has access to Ethernet and RS232 physical layer transceivers for communication purposes Network access is provided by a 10 100 1000 Mb s Ethernet PHY which is connected to the Virtex Il Pro via a standard GMII interface The PHY connects to the outside world with a standard RJ45 connector
46. fers and only contains a subset of the shared memory bus control signals The P8 connector is an exception to the other connectors since the voltage level of the I O is 2 5V instead of 3 3V The main purpose of P8 is for debug and not as I O connector for expansion cards The address control signal buffer is always enabled The data bus transceiver is enabled when either the System ACE chip select is asserted or the GPIO chip select is asserted active low The GPIO chip select signal is only connected to P8 and is the select signal for the P8 connector The direction of the data bus is controlled by the output enable signal of the shared bus OE Virtex Il Pro pin AH23 To write data out to the P8 connector set the output enable high the output enable is pulled up on the board To read data from the P8 connector set the output enable low and also disable the System ACE chip select AvBus P10 The AvBus connector labeled P10 is directly connected to 88 I O of the Virtex 1l Pro FPGA that are available in all densities 2VP7 and 2VP20 30 Due to the limited number of I O some of these I Os are also connected to the two PMC connectors This allows either P10 or the PMC connectors be used but not both at the same time The P10 connector supports 3 3V I O expansion cards The actual Vcco voltage for the Virtex 1l Pro 3 3V banks is 3 0V Setting the Vcco voltage to 3 0V instead of 3 3V effect
47. for Flash Peripheral 3 3 4 DDR SDRAM SODIMM The DDR SDRAM interface provides a socket for a 200 pin SODIMM The part number for the Micron memory module is MT8VDDT1664HDG 265B2 B3 This module is organized as 16 Meg x 64 or 128 MB and has an operating voltage of 2 5V The dual bank module HD option is used but the interface supports both the single and Copyright 2003 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc All other trademarks are property of their respective owners Rev 1 0 04 18 2006 Avnet Electronics Marketing 14 of 33 Literature ADS 003704 Released 3 3 5 dual bank modules The 265 speed grade has an access time of 7 5 ns and a CL of 2 5 The maximum data rate is 266 MHz DDR The DDR memory bus is a dedicated bus which adheres to particular routing guidelines The trace lengths for all the DDR signals are matched The clock lines are routed as differential pairs The signals were placed on particular I O sites according to clock domain For example data and control signals do not share an I O pair P N pair I O pairs are clocked out on the same clock so two signals requiring different clock domains should not make up a pair P N specified site see the Pin out section of the Virtex Il Pro datasheet All of the essential DDR memory signals are connected to Banks 6 and 7 on the Virtex Il Pro device Banks 6 and 7 make up the side of the chip that faces the DDR socket Since every
48. ge labeled P5 Remove the jumper to disable transmit Default Open TX disabled TRGT CFG MODE JP8 Sets the configuration mode of the Virtex ll Pro FPGA Remove the jumper for boundary scan mode Install a jumper for SelectMAP mode which is used by the PCI Utility during configuration Default Open boundary scan mode BRIDGE CFG MODE JP9 Sets the configuration mode of the Spartan IIE FPGA Remove the jumper for master serial mode and the PROM will load the Spartan IlE on power up Install a jumper for boundary scan mode to program the Spartan llE directly via boundary scan Default Open master serial mode HSWAP EN JP1 1 Enables pull ups on the Virtex Il Pro I O pins during configuration Install a 0 ohm 0603 resistor to disable the configuration pull ups I Os will be floating Do not install a resistor to enable the configuration pull ups Default Open pull ups enabled APS VOLTAGE JP5 Allows the user to select the voltage level for the APS supply to the XPAK module The Virtex Il Pro Development board does not implement a fully adjustable power supply for the XPAK module Instead the board supplies two of the common voltages used by XPAK modules Install a jumper across pins 1 2 to set the APS voltage to 1 2VDC Install a jumper across pins 2 3 to set the APS voltage to 1 8VDC The APS regulator is in shutdown mode until an XPAK mode is present Default Open when XPAK module not installed OVDC output TRST VCC
49. hange the settings by moving the resistors The strapping options are shown in the table below The dual function pins that are used for a strapping option and to drive an LED have a set of two jumpers per pin The dual function pins are indicated by an asterisk in the Table 10 below Copyright 2003 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc All other trademarks are property of their respective owners Avnet Electronics Marketing 16 of 33 Rev 1 0 04 18 2006 Released Literature ADS 003704 Function Jumper Installation Resistor Mode Enabled JT7 pins 2 3 0 ohm JT7 pins 1 2 0 ohm JT11 pins 2 3 0 ohm JT11 pins 1 2 0 ohm Speed 1 JT14 pins 2 3 0 ohm Speed Selection Auto Neg enabled JT15 pins 1 2 0 ohm Speedi SpeedO Speed Advertised 1 1000BASE T 10BASE T Speed1 0 0 1000BASE T 1 1000BASE T 100BASE TX JT3 pins 2 3 0 ohm 0 1000BASE T 100BASE TX 10BASE T JT4 pins 1 2 0 ohm Default 1000BASE T 100BASE TX 10BASE T SpeedO 0 PHY address 0 PHY Address 0b00001 default JT17 pins 2 3 0 ohm JT17 pins 1 2 0 ohm Manual MDIX Setting Auto MDIX Enable Set to manual preset Manual MDIX Setting JT12 Multiple Node Enable Clock to MAC Enable JT5 pins 2 3 Table 10 Ethernet PHY Strapping Options The default options as indicated in Table 10 are Auto Negotiation enabled Full Duplex mode Speed advertised as 10 100 1000 Mb s PHY address 0500001 IEEE Comp
50. hardware system for PowerPC access to SRAM Flash and SDRAM o PLB memory project is a hardware system for PowerPC access to SDRAM via the PLB Rocket I O MGT Peripheral Project o Custom peripheral that enables PowerPC access to a Multi Gigabit Transceiver o Uses generic protocol to send receive data at up to 3 125 Gbps o Includes control interface for SFP modules Copyright 2003 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc All other trademarks are property of their respective owners Avnet Electronics Marketing 4 of 33 Rev 1 0 04 18 2006 Released Literature ADS 003704 ee e yh a B T Y 21 48 sj ui j HI r TTA ro inm rper Lm Parm f FUT TITI Va TEX PRO DEYELOPM BOARD d m z E T AA RAVA TET T Lu aum LK r E T E IE E 1 RE 1 l 5 sir THITEITI PHTETETTTEITTEETHITETEITSITIT 7 TE M EAEAN EEE EH FH meme TE il 73 j gt 1 al lt L h 1 Lia ure EE E b E 4 LE si L Zu Mr H TITO L G RAW RAE T An a LE lt a m JI LI IIIIII lI Figure 1 Virtex ll Pro Development Board Picture 1 4 Ordering Information The following table lists the development system part numbers and available software options Internet link at http www em avnet com ads Part Number ADS XLX V2PRO DEVP7 6 Virtex Il Pro Development Kit with a XC2VP7 6 Speed Grade ADS XLX V2PRO DEVP20 6 Virtex Ill Pro Development Kit with a XC2VP20 6 Speed Grade ADS XLX V2P
51. he flip chip package provides superior multi gigabit transceiver MGT performance over the wire bond package providing data rates up to 3 125 Gbps in the 6 and 7 speed grades The FF896 package is a versatile package with three mid range densities providing eight MGTs and up to 556 I Os and two embedded PowerPC processors The board was designed to support all three densities the 2VP7 2VP20 and 2VP30 The schematic symbol used for the Virtex Il Pro device indicates the specific I O pins available in each density 396 I Os with 2VP7 and 556 I Os with the 2VP20 30 The Virtex ll Pro Development board is available with different device options Table 3 describes the attributes of the Virtex Il Pro device based on density and speed grade Virtex Il Pro Part I O MGT PowerPC MGT PowerPC Performance by Speed Grade FF896 pkg Cores 7 6 5 XC2VP7 396 8 1 3 125 Gbps 400MHz 3 125 Gbps 350MHz 2 0 Gbps 300MHz XC2VP20 556 8 2 3 125 Gbps 400MHz 3 125 Gbps 350MHz 2 0 Gbps 300MHz XC2VP30 556 8 2 3 125 Gbps 400MHz 3 125 Gbps 350MHz 2 0 Gbps 300MHz Table 3 Virtex Ill Pro Attributes by Density Speed Grade 3 2 High speed Serial Communication The MGTs of the Virtex Il Pro FPGA are connected to two HSSDC2 connectors two Small Form Pluggable SFP connectors with EMI cages and pads for a XPAK host connector with mounting holes for the mid board module holder In the case of the two HSSDC2 and two SFP connections the MGTs were t
52. he location of the bit file to be programmed into the Virtex Il Pro Select a bit file and then click on Execute to start the programming operation A window will pop up in a moment indicating the result of the configuration There is no need to look at the DONE LED since the Utility reads the level of the DONE pin to determine if the configuration was successful When generating a bit file to be used with the PCI Utility use CCLK as the startup clock Configuration will fail to complete if a bit file was used with the startup clock set to JTAG clock CCLK is the default setting in the Xilinx ISE tools To set the startup clock in Project Navigator right click on Generate Programming File in the Processes for Current Source window and select Properties Next click on the Startup options tab and select CCLK under the FPGA Start Up Clock field Then run the programming file generation step Jumper Settings This section provides a description of the jumper settings for the development board The jumpers are listed by the silkscreen labels on the board The board is ready to use out of the box with the default jumper settings SFPO TX EN JP3 Install a jumper on JP3 to enable transmission of SFP module 0 in the EMI cage labeled P4 Remove the jumper to disable transmit Default Open TX disabled SFP1 TX EN JP2 Install a jumper on JP2 to enable transmission of SFP module 1 in the EMI ca
53. hip SDRAM memory allowing the PowerPC access to the 32MB memory There are two instances of the opb memcon peripheral in this design one each for SRAM and Flash Note that a Spartan lIIE device separates the SRAM and Flash from the Virtex Il Pro on the development board In this design the Spartan IlE is simply used as a pass through to this memory and should be programmed with either the Bridge Design or pass thru design A GPIO peripheral is included which shares the external data bus with the memory devices This allows the Virtex Ill Pro to communicate with the Spartan IIE and in this example is used to drive LEDs which reside on the opposite side of the Spartan IIE FPGA The memory map for the peripherals in the project is shown below OPB peripherals must be mapped in the OPB address range specified by the PLB to OPB Bridge Processor Bus Peripheral Address Location OPB SRAM 0x85000000 0x851FFFFF GPIO 0x88000200 0x880002FF UART lite 0xA0000000 0xA00000FF Table 27 OPB Memory Project Memory Map The OPB Memory Project flow also requires Project Navigator in the Xilinx ISE tool set The XPS project is exported to Project Navigator so that a top level VHDL wrapper can be added to the system The wrapper is necessary to do the address and data multiplexing for the shared memory bus since all three memory peripherals use the same bus The extra control logic for the multiplexing was not necessary in the PLB Memory Project exa
54. iles to the PCI memory space The board was designed with a universal PCI connector for 32 bit or 64 bit operation at 3 3V or 5V The board is PCI functional but not completely PCI compliant due the height of the card and the bus switches The board is 600 mils 0 6 inches taller than the PCI requirement but still fits in most PC cases Bus switches were used for level shifting to support both 3 3V and 5V signaling environments since the Spartan IIE I O are not 5V tolerant The PCI interface was designed with PCI X support in mind however the PCI X core is not currently available for the Spartan llIE architecture and only standard PCI frequencies were tested The Spartan llE Bridge design is provided in mcs format for the XC18V02 configuration PROM 3 5 1 Bridge Design The following diagram shows the data flow between the sub modules that make up the Bridge design Copyright 2003 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc All other trademarks are property of their respective owners Avnet Electronics Marketing 18 of 33 Rev 1 0 04 18 2006 Released Literature ADS 003704 Status Register Bus SelectMAP Control Controller Logic A A A i 5 Flash Flash y SN PD N A Controller 16MB RS232 i T Simplified Vertical 4 gt UART Flash DB9 Bus Switch SRAM Bus Switch v MIN SRAM SRAM Control Register gt 2 ox Controller 2MB a BARO BER lt LED Register j 8
55. in Table 5 The Transmit Disable pins are connected to two pin headers for jumper selection These pins are pulled high to disable transmission as the default Install jumpers on JP2 and or JP3 to enable transmission of the SFP module s The remaining control signals were not connected to the FPGA due to pin limitations These signals are brought out to test pads for the user to probe or solder test wires To implement a high speed serial protocol at 2 5 Gbps use the 125 MHz differential clock input for the reference clock to the MGT macro This clock is brought in on a BREF clock site which has optimized routing to the MGT clock PLL The clock net names are GIGE CLK P and GIGE CLK N with FPGA pin numbers of F16 and G16 respectively Since the PLL of the MGT always multiplies by a factor of 20 using the 125 MHz clock results in a transmission rate of 2 5 Gbps To run at a slower rate the user may divide the clock using a Digital Clock Manager DCM and run the input into the reference clock on the MGT macro This will introduce jitter however and is not recommended for data rates above 1 25 Gbps A better approach would be to find an alternate oscillator with a lower frequency to replace the 125 MHz oscillator on the board Care must be taken in device selection for output voltage 2 5VDC and pin out compatibility LVPECL LVDS differential output Both the transmit and receive pairs are directly connected or DC coupled to the S
56. ively extends the overshoot rating on the Virtex ll Pro I O AvBus P11 The AvBus connector labeled P11 is connected to 60 I O with the 2VP7 and all 93 I O with the 2VP20 30 device Some of the I O that are in 2 5V banks on the Virtex ll Pro were connected through bus switches to level shift the I O from to 3 3V to support 3 3V expansion cards AvBus P12 The AvBus connector labeled P12 is only connected with the 2VP20 30 density All of the I O connected to the P12 connector are in 2 5V banks on the Virtex Il Pro FPGA Therefore all of these I O go through bus switches to level shift the I O from to 3 3V to support 3 3V expansion cards PMC Connectors PMC connectors are provided to support the implementation of PCI in the Virtex Ill Pro FPGA The PMC interface supports 32 bit PCI at 33MHz The user must instantiate the necessary pull ups in the user constraint file for the PCI control signals to adhere to the PCI system motherboard specification While the Xilinx PCI LogiCORE has support for Virtex 1l Pro devices the only package that has been targeted so far is the FF672 not the FF896 If using the Xilinx PCI LogiCORE the user constraint file for the FF672 package could be modified to work on the development board by changing the pin locations moving the clock buffer and removing the slice constraints It may be necessary to adjust the timing constraints or try different place and route effort levels to make the
57. liant and Non compliant support straight cable in non MDIX mode auto MDIX mode enabled Single node NIC and CLK TO MAC disabled The pin out for a jumper pad is shown below Figure 4 Jumper Pad Pin out The auto MDIX mode provides automatic swapping of the differential pairs This allows the PHY to work with either a straight through cable or crossover cable Use a CAT 5e or CAT 6 Ethernet cable when operating at 1000 Mb s Gigabit Ethernet The boundary scan Test Access Port TAP controller of the PHY must be in reset for normal operation Place a jumper shunt on JP17 across pins 2 3 for normal operation of the PHY This will pull the active low reset pin of the TAP TRST low putting the TAP in reset 3 4 2 RS232 Transceiver The RS232 transceiver is a Maxim MAX3388ECUG U33 This transceiver is a low power device with an operating voltage of 2 5V The internal charge pump creates the RS232 compatible output levels The FPGA transmit receive signals are connected to a 2 5V bank on the Virtex 1l Pro Two channels are supported by the interface The primary Copyright 2003 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc All other trademarks are property of their respective owners Avnet Electronics Marketing 17 of 33 Rev 1 0 04 18 2006 Released Literature ADS 003704 3 5 channel is brought out on the Mini DIN connector labeled JS1 The custom serial cable included in the kit should be use
58. lists the timing parameters required to set up the SDRAM peripheral in EDK for 100 MHz operation parameters are entered in the MHS file If a timing parameter is left out of the peripheral instantiation a default value is automatically used The Software BSP section of this manual has more information about setting up peripherals in EDK Copyright 2003 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc All other trademarks are property of their respective owners Avnet Electronics Marketing 13 of 33 Rev 1 0 04 18 2006 Released Literature ADS 003704 3 3 2 3 3 3 SDRAM peripheral Timing Parameter Time ps or Number C SDRAM COLAWIDITH 1 9 Table 7 Timing Parameters for SDRAM Peripheral Asynchronous SRAM A single Cypress Asynchronous SRAM device part number CY7C1062AV33 12BGC makes up the 32 bit data bus The Cypress device provides 2 MB of SRAM memory on a single IC and is organized as 512K x 32 The device has an operating voltage of 3 3V and a 12 speed grade for 80 MHz operation The SRAM is connected to the Spartan IIE FPGA via a dedicated bus The Bridge design in the Spartan IIE FPGA essentially connects the shared bus to the SRAM bus during Virtex Il Pro transactions to SRAM The Bridge design also maps the SRAM into the BARO memory space and arbitrates transactions by the Virtex Il Pro and the PCI The default timing parameters can be used to set up the external memory c
59. located on the PCI faceplate Serial port communication to the embedded PowerPC processor or FPGA fabric is provided through a dual channel RS232 transceiver A six pin Mini DIN connector on the faceplate is used for the Virtex Ill Pro serial port connector A custom serial cable is included in the kit to connect the Mini DIN connector to a standard DB9 serial port connector 3 4 1 Ethernet PHY The PHY is a National DP83865BVH Gig PHYTER V The DP83865 is a low power version of National s Gig PHYTER V with a 1 8V core voltage and 2 5V I O voltage The PHY also supports 3 3V I O but the 2 5V option is used on the board The PHY is connected to a Pulse RJ 45 jack with integrated magnetics part number JK0654218Z The jack also integrates two LEDs to show Link and Activity External logic was used to logically OR the three link indicators for 10 100 and 1000 Mb s to drive the Link LED on the RJ 45 jack The external logic is for the default strap options and may not work if the strap options are changed Four more LEDs are provided on the board for status indication These LEDs indicate Link at 10 Mb s Link at 100 Mb s Link at 1000 Mb s and Full Duplex operation The PHY clock is generated from its own 25 MHz crystal The PHY address is set to 0000001 by default PHY address 0b00000 is reserved for a test mode and should not be used Three pad resistor jumpers were used to set the strapping options These jumper pads provide the user with the ability to c
60. mple therefore the entire flow was contained in XPS The top level VHDL wrapper file is called system top vhd and is located in the hdl folder of the OPB Memory Project directory While the other source files in the hdl folder are auto generated wrapper files for the standard peripherals the system top vhd source was custom designed and added to the folder This file is deleted when performing a Clean operation so the user will have to copy the system top vhd file from the CD back to the hdl folder after a Clean operation A datasheet has been created for each example project See the OPB External Memory Example datasheet for more information on how to the use the OPB Memory Project including information about exporting projects to Project Navigator MGT Peripheral Project This example provides a PowerPC interface to a Multi Gigabit Transceiver MGT This project makes use of a custom OPB peripheral designed by Avnet Electronics Marketing to enable the PowerPC to control a MGT The MGT peripheral uses the GI CUSTOM protocol primitive which is completely customizable The primary purpose of the MGT peripheral is to provide an example of how to implement and test a MGT on the Virtex Ill Pro Development board To transmit a packet the PowerPC fills the transmit buffer with a payload and sets up the start of frame end of frame and packet length followed by the assertion of the transmit buffer ownership bit Asserting the
61. n the board Copyright 2003 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc All other trademarks are property of their respective owners Avnet Electronics Marketing 21 of 33 Rev 1 0 04 18 2006 Released Literature ADS 003704 3 6 1 3 6 2 3 6 3 AvBus Connectors The Virtex ll Pro FPGA is connected to four 140 pin board to board AvBus standard connectors The 2VP7 density device does not have enough O to fill up all four of the AvBus connectors The AvBus connectors that are populated per Virtex II Pro density are shown in the table below Virtex Il Pro Device Av Bus l O Connected by Density P8 P10 P11 P12 XC2VP7 XC2VP20 30 Table 17 AvBus Connectors Available by Virtex 1l Pro Density In the Table 17 Full means that all of the I O pins for that AvBus connector type are connected to the Virtex ll Pro FPGA 88 I O for a JTAG type 93 I O for non JTAG Partial means that some of the I O are not connected with the smaller density FPGA and None means that none of the I O are connected with the smaller density The AvBus connector P8 is a special case where not all of the I O pins were connected but all of the connected pins are available for all densities AvBus P8 The primary purpose of the AvBus connector labeled P8 is to make the Virtex Il Pro shared memory bus available for debug purposes This connector is located on the other side of the shared memory bus buf
62. ng parameters stay the same for the Mobile SDRAM regardless of the bus frequency The peripheral automatically generates the specified timing using the specified bus frequency The memory map for the peripherals in the project is shown below OPB peripherals must be mapped in the OPB address range specified by the PLB to OPB Bridge Processor Bus Peripheral Address Location SDRAM 0x00000000 0x01FFFFFF PLB to OPB Bridge 0x80000000 0xBFFFFFFF OPB UARTIIte 0xA0000000 0xAO0000FF Table 26 PLB Memory Project Memory Map The Spartan IIE FPGA is connected to the Virtex Il Pro shared memory bus so care must be taken to tri state the bus from the Spartan IlE side to avoid corrupting the SDRAM bus The pass thru design included on the kit CD provides an example of how to tri state the bus and provide the Virtex ll Pro with access to the Flash and SRAM The Bridge Design which is loaded from the PROM on power up automatically takes care of the bus control so the user does not have to do anything if the Bridge Design hasn t been erased from the PROM The PLB Memory Project flow is entirely within the XPS tool The user may generate a netlist for the hardware system compile the test software and create a bit file updated with the software all from within XPS The user can even download the bit file to the development board from XPS using a download cable See Section 2 2 1 for instructions on how to set up a download cable for configuration
63. ontroller peripheral for the SRAM device It is only necessary to specify the address location OPB clock frequency and the port mappings See the Software BSP section of this manual for more information Flash The board has a dual footprint allowing either Intel StrataFlash or AMD Uniform Sector Flash to be used based on availability Two 64 Mbit devices 4M x 16 make up the 32 bit Flash data bus The part number for the Intel StrataFlash device is E28F640J3A 120 The part number for the AMD Uniform Sector Flash device is AM29LV641DL90REI Both devices have an operating voltage of 3 3V and provide 16 MB total of Flash memory The Flash is connected to the Spartan IIE FPGA via a dedicated bus The Bridge design in the Spartan llIE FPGA essentially connects the shared bus to the Flash during Virtex ll Pro transactions to Flash The Bridge design also maps the Flash into the BAR1 memory space and arbitrates transactions by the Virtex II Pro and the PCI The timing parameters to set up the external memory controller EMC peripheral for the Flash devices are shown below If a timing parameter is left out of the peripheral instantiation a default value is automatically used The Software BSP section of this manual has more information about setting up peripherals in EDK EMC peripheral Timing Parameter Time ps C READ ADDR TO OUT SLOW PS 0 100000 C WHITE ADDR TO OUT SLOW PS 0 99000 C WHITE MIN PULSE WIDTH PS 0 0000 Table 8 Timing Parameters
64. or is labeled P1 and is located on the backside solder side of the board The pin out of the host connector is shown below Copyright 2003 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc All other trademarks are property of their respective owners Avnet Electronics Marketing 11 of 33 Rev 1 0 04 18 2006 Released Literature ADS 003704 P1 XPAK host connector Signal FPGA pin Pin Signal FPGA pin AGND AGND RXO P AK5 RXO N AK4 es ag AND XAULLASI AH5 44 RX1_P AK12 XAUILRESET 45 RX N AKM E 46 zm AGND TXONOFF RX2 P AKI8 RX2 N AKI7 pL AGND ______ RX8 P AK25 RX3 N AK24 ____ XAUL MDIO F21 AGND XAUL MDC H21 OAGND PRTAD4 _____ AGND_____ ______PRTAD3 TXO P AK6 PRTAD2_ TXO AK AGND TX1_P AK13 ____ _____TxX1_N AK14 eo AND TX2 P AKI9 APS SENSE TX2 N AK20 e AGND __ ____ TX3 P AK260 TX8 N AK27 Lm LOT pg NICE 5 REK SEN E NE XN pr 10 wok E EET EN DE 15 16 Lj 18 EEE ER 20 ei E E ___28__ NE NE 2 26 AE 28 2208 30 EA 32 38 394 35 Table 6 XPAK Host Connector Pin out P1 Table 6 gives the actual pin numbers in parenthesis of the MGT pins on the Virtex Il Pro FPGA The management interface
65. ort both the flying leads connection of the Parallel Cable Ill and MultiLINX cables and the ribbon cable connection of the Parallel Cable IV These connectors are labeled JTAG3 JP14 and JTAG4 JP12 respectively For more information about JTAG download cables see the Xilinx web page http www xilinx com Click on the Products tab and then click on the Configuration link Scroll down to Desktop Programmers and Download Cables and select the download cable of interest When using the flying leads connection of the Parallel Cable Ill or MultiLINX connect the leads according to the silkscreen labels on JTAG3 JP14 These connections are shown in Table 2 below Pin 1 of JTAG3 is a dual Copyright 2003 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc All other trademarks are property of their respective owners Avnet Electronics Marketing 5 of 33 Rev 1 0 04 18 2006 Released Literature ADS 003704 purpose pin that can either be used as VCC when using a cable that requires a VCC input or as TRST the TAP reset line for cables requiring access to TRST Place a jumper shunt on JP17 across pins 1 2 to connect the dual purpose pin to VCC Signal Name JTAG3 JP14 pin JTAG4 JP12 pin 9 6 O 2 4 6 8 or 10 1 3 5 7 9 11 or 13 Table 2 JTAG Headers JTAG3 amp JTAG4 Pin Out If the Parallel Cable IV is used the ribbon cable connector mates with the JTAG4 JP12 connector The connectors are keyed to
66. pin in Bank 6 and 7 was used for the 2VP7 device exceptions had to be made to the lO placement rules to make everything fit The exception was placing some of the data mask and data strobe signals on the same P N pair forcing them to be in the same clock domain Since the data strobe and mask signals require different clock domains the data mask signals have limited functionality with this pin placement The data mask signals can be set during the de assertion state prior to asserting the strobe for the first data transfer but the mask must stay the same for all the data in the burst The interface fully supports 64 bit wide transfers where the data mask signals are all statically set to zero All of the outputs to the DDR memory module should use the SSTL2 Il I O standard Double data rate flops were used to clock in out the data The 125 MHz clock input was used for the single rate clock during testing resulting in a data rate of 250 MHz System ACE CompactFlash The Virtex Il Pro FPGA can access the CompactFlash through the MPU interface on the System ACE controller The MPU interface is a set of registers in the System ACE controller that provide the ability to read write sectors of the CompactFlash card The MPU interface is connected to the shared memory bus through the address control buffer and data bus transceiver The address control buffer is always enabled while the data bus transceiver is only enabled when the System ACE chip select is ass
67. re not used and brought out to test pads for user access The Port Address signals PRTAD O0 4 are not used since the board only supports one module The 156 25 MHz differential clock input is used for the reference clock to the MGT macro This clock is brought in on a BREF clock site which has optimized routing to the MGT clock PLL The clock net names are XAUI CLK P and XAUI CLK N with FPGA pin numbers of AH16 and AJ16 respectively Since the PLL of the MGT always multiplies by a factor of 20 using the 156 25 MHz clock results in a transmission rate of 3 125 Gbps The transmit and receive signals are directly connected to the XPAK host connector or DC coupled However all XPAK compliant modules have AC coupling on both the transmit and receive signals inside the module itself The transmit differential pairs are routed on the solder side of the board while the receive pairs are routed on the component side This keeps the signals from crossing on the way to the XPAK connector Return paths are provided by the analog ground planes in the layers directly adjacent to the outer layers The analog ground planes are separate from the digital ground used for the rest of the components on the board but are referenced to digital ground in several locations through ferrite beads Memory The Virtex Il Pro Development board has several types of volatile and non volatile memory The Virtex Il Pro FPGA has access to the following memory devices eith
68. reated individually This means the lengths of the transmit and receive signals were matched per MGT but not matched to any other MGT However in the case of the XPAK interface four MGT channels were bonded together to create the 10 Gigabit Attachment Unit Interface XAUI The four transmit pairs have matched lengths and the four receive pairs have matched lengths Each high speed connector is described in greater detail in the following sub sections 3 2 1 HSSDC2 The HSSDC2 connectors are used to implement high speed serial communication over copper These connectors support data rates up to 2 5 Gbps and are typically used for the Infiniband or Fibre Channel communication standards The connectors are labeled P2 and P3 on the board The pin outs are shown below The connectors installed on the board are keyed for Infiniband cables The user may replace them with connectors keyed for Fibre Channel cables if desired since they have the same footprint P2 P3 Pin Signal V2Pro pin Pin Signal V2Pro pin 7 Table 4 HSSDC2 Connector Pin outs P2 amp P3 Table 4 gives the actual pin numbers in parenthesis of the MGT pins on the Virtex Il Pro FPGA To implement a high speed serial protocol at 2 5 Gbps use the 125MHz differential clock input for the reference clock to the MGT macro This clock is brought in on a BREF clock site which has optimized routing to the MGT clock PLL The clock net names are GIGE CLK P and GIGE CLK N with FP
69. rite register at physical address 0x01000000 Performing either a SRAM or Flash transaction to address 0x01000000 will access the Status Register Status Register transactions are qualified by the shared bus address and the write enable output enable control signals WE and OE The Status Register is outside the address range of the SRAM and Flash memory The Virtex Il Pro Status Register bit map is shown in Table 16 The PCI application may issue an interrupt request to Virtex II Pro by asserting bit 9 of the PCI Control Register TRGT_IRQ This may be used to request bus ownership The Virtex Il Pro pin AD23 is used for the TRGT IRQ signal The Virtex Ill Pro may clear the request after servicing by writing to bit 2 of the Status Register Register Name Virtex Il Pro Status Register Memory Space Virtex II Pro Shared Memory Bus Address Offset 0x01000000 Width 82 bits Power Up Value 0x00000000 else ltleletz le s a io A njw TT T T pf i tt i i E Swnt FLASH OWNER Ci E C E pal 3 6 3 5 2 Table 16 Status Register Bit Map COPY SRAM FL Setting bit 7 of the Control Register COPY SRAM _ FL enables the Flash controller to program the contents of the SRAM memory to the Flash The full range of SRAM is copied to the Flash starting at Flash address 0x0 The Flash controller clears the COPY_SRAM_FL bit upon completion of the transfer PCI Utility The Avnet PCI Utility is a Windows based graphical
70. ronics Marketing PCI Utility a graphical user interface that allows the user to read write and download files to the PCI memory space in addition to configuring the Virtex Ill Pro FPGA The purpose of the configuration over PCI is to allow the user to put the board into the PCI slot of their development PC close the lid to the PC chassis and be able to work with the board without it taking up counter space It is also a very fast way of reconfiguring the Virtex Il Pro device Place a jumper shunt on JP8 to put the Virtex Il Pro FPGA in SelectMAP mode This is required for configuration over PCI Also make sure the System ACE controller is in reset by putting switch 1 of the dipswitch labeled S2 in the OFF position The PROM file for the PCI bridge design must be programmed into the XC18V02 PROM the board comes with the PROM already programmed with the bridge design Finally make sure the Spartan llE is set for master serial mode to load from the PROM on power up remove jumper on JP9 The Virtex 1l Pro Development board was designed to fit into the majority of computer cases with PCI support The board is 600 mils 0 6 inches taller than the PCI specification requirement and may not fit in all cases To install the development board into a computer case turn the power off to the computer and remove the cover on the case Leave the power cord connected to the outlet Next using a static strap or touching the bare metal of the computer chassis
71. signals MDIO and MDC are connected to the Virtex Il Pro FPGA through level shifting logic It is necessary to shift the voltage level of the XPAK outputs from the APS voltage level 1 2V or 1 8V to 2 5VDC to meet the minimum input level of the FPGA Likewise the outputs of the FPGA are shifted down to the APS supply voltage Since the MDIO signal is a bi directional data line it was necessary to add a direction control signal This signal is called XAUI MDIO DIR and is connected to pin D15 of the Virtex Il Pro FPGA Setting the direction pin low logic 0 enables the FPGA output buffer and disables the XPAK output buffer allowing the FPGA to drive the MDIO line The opposite is true when setting the direction pin high logic 1 the XPAK is able to drive the MDIO line The user should set the direction pin low to write to the MDIO line and high to read from the MDIO line The Link Alarm Status Interrupt LASI pin is connected to the FPGA to allow detection of whether a module is installed The Transmit On Off pin is connected to a two pin header for jumper selection This pin is pulled down by default to disable transmission Install a jumper on JP1 to enable transmission The Reset pin on the XPAK module is connected to the Spartan IIE FPGA due to pin limitations on the Virtex Il Pro The Bridge design in the Spartan IIE FPGA sets the XPAK reset pin based on the setting of switch 2 on the dipswitch labeled S2 Turn switch 2 to the O
72. switch on the dipswitch labeled S1 to the OFF position set the CFG ADDR with the three switches switch 1 is the LSB and set switch 1 on the dipswitch labeled S2 to the ON position and then apply power to the board The DONE LED labeled D22 will light to indicate a successful configuration of the Virtex ll Pro FPGA The iMPACT software in the Xilinx ISE 5 1i or later tool set is used to prepare the System ACE files After opening the iMPACT program select the option for Prepare Configuration Files Next select System ACE File and then choose the target device on the next window to be System ACE CF Start with the Novice user mode and try the expert mode after becoming familiar with the process Set the card size to Generic since the CompactFlash card is a non Xilinx card and larger than the density options Set the Reserve Space to 0 initially The reserve space is the space leftover on the CompactFlash card after storing the bit files which can be used by the Virtex Il Pro FPGA as non volatile memory Next give the Flash card build a name and specify a location for the generated files this can be the CompactFlash card itself or a directory to save the files before copying to the card Next select the address locations to be used based on the number of bit files being used Give each address location a name corresponding to the bit file for that location limit 8 characters on names Click next to st
73. the MHS file Copyright 2003 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc All other trademarks are property of their respective owners Avnet Electronics Marketing 31 of 33 Rev 1 0 04 18 2006 Released Literature ADS 003704 tat at Ht He TEE TT EE TT EE TEE TEE EE t ethernetlite it it tH HHH AE H HHH HH FE FE AF BEGIN opb_ethernetlite PARAMETER PARAMETER PARAMETER PARAMETER PARAMETER PARAMETER PARAMETER HW_VER PORE Ob Sek emac signals PORT PHY EX CK PORE PHY rx cIk PORI PHY CYS PORT PHY dv PORT PHY_rx_data PORT PHY COL PORT PHY rx er PORT PHY tx en PORE PHY tx data INSTANCE DUR LEX C_BASEADDR C_HIGHADDR CODEB CLR PERIOD PS C FAMILY BUS INTERFACE SOPB sys emac_lite 1 00 a 0 0x87000000 TODOO d TONS virtex2 opb bus AS phy_txck phy csxok phy crs phy rxdv phy xdg phy col phy tzer add this to top phy txen phy txd need to drive these at upper level phy_reset_n phy_txer END 0x87003FFF MIN_SIZE 0x4000 note below 50MHz can only rum LOMbps Then go to the top of the MHS file and add the following port mappings just after the SDRAM ports or the user specific ports opb_ethernetlite signals PORT phy_txck phy_txck DIR INPUT PORT phy_rxck phy PxckR DIR INPUT PORT phy crs phy Crs DIR INPUT PORT phy_rxdv phy_rxdv DIR INPUT PORT phy_rxd phy_rxd DIR INPUT
74. the chain and removes all of the expansion connectors from the chain This is the default setting that most users will use The other jumper settings are shown below JP15 JTAG Chain Selection Jumper Settings Standalone Mode System ACE Virtex ll Pro XC18V02 PROM Spartan lIE and PCI in chain PCI bypassed by default Pins 1 2 and 4 5 Add PMC Connector to standalone Pins 2 3 Pins 1 2 3 4 and 5 6 Add AvBus Connector to standalone Pins 1 2 and 5 6 Add both PMC and AvBus to standalone Table 25 JTAG Chain Selection JP15 The Ethernet PHY is also part of the standalone chain but it is bypassed by default Bypass resistors are provided to enable the user to bypass any device in the chain The System ACE Virtex Il Pro bypass resistor is labeled R293 The XC18V02 PROM bypass resistor is labeled R297 The Spartan IIE bypass resistor is labeled R300 The PHY bypass resistor is R301 The PHY is completely disconnected from the chain by removing the series resistors on PHY_TDI and PHY TDO R137 and R303 respectively The default installation options put the System ACE Virtex Ill Pro PROM and Spartan llE devices in the boundary scan in standalone mode Specific instructions on how to use the three different methods of configuration are included in Section 2 2 of this manual Descriptions of the sub sections in 2 2 are given below Section 2 2 1 provides information on how to configure the devices
75. uration Mode iMPACT File Edit Mode Operations Output View Help LD us de E IP ZZ BE uu na IE Lm E Kz Boundary Scan Slave Serial SelectMAP Desktop Configuration TOI wocace tgl44 xccace tg1l44 bed TOG Figure 2 Boundary scan Chain in iMPACT The iMPACT software will auto detect the Spartan IIE FPGA as a Virtex E device When the user assigns a bit file targeting the Spartan IlE device iMPACT will bring up a warning about the part assignment change that can safely be ignored 2 2 2 System ACE CompactFlash Configuring the Virtex ll Pro FPGA with the System ACE CompactFlash is an easy and convenient way of transferring bit files from the design environment to the development board The user will need a CompactFlash card reader or PCMCIA to CompactFlash card adapter to be able to copy files from a PC laptop computer to the CompactFlash card The configuration process involves three steps preparing the System ACE files copying the files to the CompactFlash card and running the System ACE controller Copyright 2003 Avnet Inc AVNET and the AV logo are registered trademarks of Avnet Inc All other trademarks are property of their respective owners Avnet Electronics Marketing 6 of 33 Rev 1 0 04 18 2006 Released Literature ADS 003704 2 2 3 If the user wants to skip the process of preparing their own card the CompactFlash card is initially programmed with demo test files Set the CFG MODE
76. user interface that uses a PCI device driver to communicate with the board The main purpose of the PCI Utility is to aid in the debug process of a PCI design The device driver was designed using a driver development tool from Jungo called WinDriver www jungo com Most of the source code for the PCI Utility is provided as an example of how to interface to the driver However the user would require the WinDriver development tool to modify the driver The Avnet PCI Utility User Manual included on the CD under the PCI Utility folder provides instructions for installation and use of the utility program I O Connectors The Virtex Il Pro Development board is a compatible motherboard that incorporates board to board connectors to support expansion boards The connection between the Virtex 1l Pro Development board and the compliant daughter boards is via the Avnet standard AvBus connectors P8 P10 P11 and P12 The connectors on the development board are the host connectors AMP part number 179031 6 The host connectors mate with AMP part number 5 179010 6 When interfacing to other boards care most be taken to tri state any signals that could interfere with those of the other board The Virtex ll Pro Development board also has PCI Mezzanine Card PMC connectors The Virtex Il Pro FPGA is connected to two standard PMC connectors according to the PMC specification for 32 bit PCI spec connectors Pn1 Pn2 The connectors are labeled P6 and P7 o

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