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73S8014R/RN/RT 20SO Demo Board User Manual

1. 11 73S8014R RN RT 2050 Demo Board User Manual UM_8014_010 3 2 73S8014R RN RT Pin Description Table 2 7358014R RN RT Pin Description Card Interface Name Description 14 Card I O Data signal to from card Includes a pull up resistor to Vcc RST 15 Card reset provides reset RST signal to card Card clock provides clock signal CLK to card The rate of this clock is CLK 17 determined by crystal oscillator frequency or external clock input and CLKDIV selections PRES 19 Card Presence switch active high indicates card is present Should be tied to GND when not used but it Includes a high impedance pull down resistor VCC 18 Card power supply logically controlled by sequencer output of LDO regulator Requires an external filter capacitor to the card GND GND 16 Card ground Table 0 7388014R RN RT Pin Description Miscellaneous and Outputs Name Pin Description Crystal oscillator input can either be connected to the crystal or driven as a XTALIN 9 source for the card clock XTALOUT 10 Crystal oscillator output connected to the crystal Left open if XTALIN is being used as external clock input VDDF ADJ 12 fault threshold adjustment input this pin can be used to adjust the Vppr a values that controls deactivation of the card Must be left open if unused Table 4 7388014R RN RT Pin Description Power Supply and Ground
2. 2H SEMICONDUCTOR CORP Simplifying System Integration 7358014R RN RT 20SO Demo Board User Manual July 2008 Rev 1 0 UM 8014 010 7358014R RN RT 2050 Demo Board User Manual UM 8014 010 O 2008 Teridian Semiconductor Corporation All rights reserved Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation Simplifying System Integration is a trademark of Teridian Semiconductor Corporation All other trademarks are the property of their respective owners Teridian Semiconductor Corporation makes no warranty for the use of its products other than expressly contained in the Company s warranty detailed in the Teridian Semiconductor Corporation standard Terms and Conditions The company assumes no responsibility for any errors which may appear in this document reserves the right to change devices or specifications detailed herein at any time without notice and does not make any commitment to update the information contained herein Accordingly the reader is cautioned to verify that this document is current by comparing it to the latest version on http www teridian com or by checking with your sales representative Teridian Semiconductor Corp 6440 Oak Canyon Suite 100 Irvine CA 92618 TEL 714 508 8800 FAX 714 508 8877 http www teridian com 2 Rev 1 0 8014 010 73S8014R RN RT 2050 Demo Board User Manual Table of Contents 1 OO CA kuy uka ILLE aha te nn 4 151
3. J6 CONN SMART CARD SIM SAM 6PIN SMD CCMO3 3013 401 1691 1 ND CCMO03 3754 ITT Industries J5 CONN SMART CARD 8PIN SMD 02 2504 401 1715 ND 2 2504 ITT Industries 4 5 7 HEADER 2 2pins 2 54 JP1 JP3 HEADER 3 3pins 2 54mm pich S1011E 36 ND PZC36SAAN Sullins J1 J3 SSM 110 L SV SSM 110 L SV N A 55 110 L SV Samtec J2 J4 TSM 110 01 L SV TSM 110 01 L SV N A TSM 110 0115 V Samtec Y1 CRYSTAL 12 000 MHZ 20PF 49US HC 49US X190 ND ECS 120 20 4DN ENGYA U1 7358014R RN RT 7358014R RN RT Teridian Semiconductor Note The resistors and capacitors marked DNI are not populated on the board They can be implemented to adjust the features of the smart card reader 18 Rev 1 0 8014 010 7358014R RN RT 205 Demo Board User Manual Figure 5 TERIDIAN 73S8014R RN RT 20SO Demo Board Top View GND GND GND J4 SN 65 BO14R RN RT DEMOBOARD PND jo Rev 1 0 19 7358014R RN RT 2050 Demo Board User Manual UM 8014 010 Figure 7 TERIDIAN 73S8014R RN RT 2050 Demo Board Top Signal Layer 20 Rev 1 0 8014 010 7358014R RN RT 2050 Demo Board User Manual Figure 9 TERIDIAN 7358014R RN RT 20SO Demo Board Middle Layer 2 Supply Plane Rev 1 0 21 8014 010 73580
4. Name Pin Description VDD 13 System interface supply voltage and supply voltage for internal circuitry VPC 4 LDO regulator power supply source GND 8 11 Digital ground 12 Rev 1 0 UM 8014 010 73S8014R RN RT 2050 Demo Board User Manual Table 5 7388014R RN RT Pin Description Microcontroller Interface Name Pin Description R Command VCC negative assertion Logic low on this pin causes the LDO regulator to ramp the Vcc supply to the card and initiates a card activation sequence if a card is present RN RT Logic low on one or both of these pins will cause the LDO to ramp the Vcc supply to the smart card and smart card interface to the value described in the following table CMDVCC CMDVCC5 CMDVCC3 Vcc Output Voltage CMDVCC 6 RN RT 0 1 5 0V 1 0 3 0V 1 1 LDO Off Note In order to set VCC to 1 8V both CMDVCC5 and CMDVCC3 must be asserted low within 400ns of each other See the Data Sheet for further details 5 volt 3 volt card selection Logic one selects 5 volts for Vec and card interface logic low selects 3 volt operation When the part is to be 5V 3V used with a single card voltage this pin should be tied to either GND or CMDVCC 7 Vpp However it includes a high impedance pull up resistor to default this RN RT pin high selection of 5V card when not connected RN RT See pin 6 above CLKDIV1 20 Sets the divide ratio from the XTAL oscillator or
5. SO Demo Board 1 2 Safety and ESD Notes Connecting live voltages to the Demo Board system will result in potentially hazardous voltages on the boards Extreme caution should be taken when handling the Demo Boards after connection to live voltages The Demo Boards are ESD sensitive ESD precautions should be taken when handling these boards 4 Rev 1 0 8014 010 73S8014R RN RT 2050 Demo Board User Manual 1 3 Getting Started The Figure 1 1 shows the basic connections of the Demo Board e Power Supplies Apply 3 3V to pin 10 of J4 and 5V to pin 10 of J2 e Control signals to the device can be connected through J2 and J4 see Figure 1 1 and the electrical schematic Figure 4 1 e Setting the clock frequency with an external clock source o Set JP1 to the SCLK setting o Apply clock source to pin 1 of J2 o Apply 3 3V 1 or 0 to CLKDIV1 and CLKDIV2 pins allows the following CLKDIV1 CLKDIV2 0 7358014R clock frequency SCLK 8 7388014RN RT clock frequency SCLK 6 CLKDIV1 0 CLKDIV2 1 clock frequency 5 4 all CLKDIV1 1 CLKDIV2 50 clock frequency SCLK all CLKDIV1 CLKDIV2 1 clock frequency SCLK 2 all e Setting the clock frequency using crystal Y1 o Crystal included in the Demo Board is 12MHz NDS applications can use 27 2 o Set JP1 to XTAL position o Apply 3 3V 1 or GND 0 to CLKDIV1 and CLKDIV2 pins allows the following CLKDIV1 CLKDIV2 O Y 12MHz XTAL clock freq
6. XTALOUT eno E sy SELECT 2 iL 1 0 1uF T 3 3V 1 SSM 110 x d 12 000MHz 7358014R N RT 9 5 T R7 22pF 22pF ran JP1 XTALIN When using an external clock SELECT source C7 should be removed Y R8 to R13 and C36 to be placed within lcm of E C12 VDD 27pF J5 Smart Card Connector SIM SAM Connector JT VCC TP3 to TP8 to be placed RST very close to the pads of 25 CLK Rev 1 0 17 73S8014R RN RT 2050 Demo Board User Manual UM 8014 010 Reference C1 10 Table 6 TERIDIAN 73S8014R RN RT 2050 Demo Board Bill of Material 10UF 6 3V CERAMIC X5R 0805 PCB Footprint see attached zip file 805 Digikey Part Number PCC2225CT ND Part Number ECJ 2FB0J106M Manufactuer Panasonic C11 CAP 1 0UF 6 3V CERAMIC X5R 0603 603 PCC1915CT ND ECJ 1VB0J105K Panasonic C2 C8 CAP 1UF 16V CERAMIC X7R 0603 C12 C9 CAP CERAMIC 27PF 50V 0603 SMD 603 603 PCC1762CT ND PCC270ACVCT ND ECJ 1VB1C104K ECJ 1VC1H270J Panasonic Panasonic C5 CAP CERAMIC 22PF 50V 0603 SMD 603 PCC220ACVCT ND ECJ 1VC1H220J Panasonic R7 RES ZERO OHM 1 10W 5 0603 SMD 603 PO OGCT ND ERJ 3GEYOROOV Panasonic R6 RES 20K OHM 1 10W 5 0603 SMD 603 P20KGCT ND ERJ 3GEYJ203V Panasonic
7. 14R RN RT 2050 Demo Board User Manual 6 Contact Information For more information about Teridian Semiconductor products or to check the availability of the 7388014R RN RT contact us at 6440 Oak Canyon Road Suite 100 Irvine CA 92618 5201 Telephone 714 508 8800 FAX 714 508 8878 Email scr support teridian com For a complete list of worldwide sales offices go to http www teridian com 23 Rev 1 0 73S8014R RN RT 2050 Demo Board User Manual UM 8014 010 Revision History Revision Date Description 1 0 7 3 2008 First publication 24 Rev 1 0
8. 7388014R RN RT Demo Board is a platform for evaluating the TERIDIAN 7388014R RN RT smart card interface ICs It incorporates either the 7358014 the 73S8014RN or the 7358014RT integrated circuit and it has been designed to operate either as a standalone platform to be used in conjunction with an external microcontroller or as a daughter card to be used in conjunction with the 73512xxF evaluation platform The three parts differ only slightly with regard to the control signals and the control function These differences involve the VCC and the clock divider control signals The 7388014R and 73S8014RN use the CMDVCC and 5V 3V control signals to generate VCC smart card supply voltage at either or 5V The 7358014 redefines the CMDVCC pin as CMDVCC5 and 5V 3V as CMDVCC3 These redefined signals allow the selection of 5V and 1 8V for VCC See the applicable data sheet for further detail The 7388014R uses the clock divider signals CLKDIV1 and CLKDIV2 to select between a divide by 1 2 4 and 8 for the smart card CLK output The 73S8014RN and 73S8014RT have been redefined to select between divide by 1 2 4 and 6 to support NDS applications The board has been designed to comply with the NDS specification BND B iwi 1 a ly Ll 9 8 8 SEMICONDUCTOR CORP wo 16 24 Y 2 4 Amo e CS 8014 DEMOBOARD ENPI yo Figure 1 7388014R RN RT 20
9. General et 4 1 2 Safety and ESD NORS uuu u ba o la e 4 1 3 Getting Started id 5 1 4 Recommended Operating Conditions and Absolute Maximum Ratings 6 1 4 1 Recommended Operating Conditions 6 1 41 Absolute Maximum Ratings 4e itc tiran 6 2 Design 00 0 u uu u u 9 2 1 General Layout Rules p Mee tet iaa 9 2 2 Optimization for Compliance with 5 1188 9 3 Useofthe Board Hardware 4 lt 10 3 1 Board Description Jumpers Switches and Test 10 3 2 7358014R RN RT Pin 12 3 3 7358014R RN Pinout 5020 Top 14 3 4 7358014RT PINOUT 2050 Top View 15 4 A eem i duc iA 16 6 Contact Information Iri nde cea See cune S a oC Da asa usss 23 Rev 1 0 3 7388014R RN RT 2050 Demo Board User Manual UM 8014 010 1 Introduction 1 1 General The TERIDIAN Semiconductor Corporation TSC
10. V power supply pin can be left open when JP3 is in position 5V 7 TP1 PIN12 VDD voltage fault adjustment Pin to the left is connected to the VDDF ADJ VDDF ADJ pin of the 7358014R RN RT and the pin to the right is GND When either a resistor R3 or a resistor network R1 is populated on the board it adjusts the VDD fault level that internally triggers a card deactivation sequence By default the resistors R1 and R3 are not connected It provides a VDD fault level of 2 3V typical internally set to the 7388014R RN RT Refers to the 7388014R RN RT Data Sheet for further information about VDD fault level and determination of these resistor values 8 J6 Smart Card SIM SAM smart card format connector Connector Note that J6 is wired is parallel to the smart card connector J5 underneath the PCB No SIM SAM should be inserted when using the credit card size connector J5 10 JP1 Clock Jumper to select between a crystal and external clock as the selection frequency reference to the device The default setting is for a crystal 11 J5 Smart Card Smart card connector Connector When inserting a card credit card size format contacts must face up 10 Rev 1 0 8014 010 73S8014R RN RT 2050 Demo Board User Manual DN ox 611 Ril o gt lt R7 u gt GND 169 BE B014R RN RT DEMOBOARD ENPL Figure 3 TERIDIAN 7358014R RN RT Demo Board Board Description Rev 1 0
11. external clock input to CLKDIV2 5 the card clock These pins include pull down resistors CLKDIV1 CLKDIV2 CLOCK RATE 0 0 XTALIN 8 R XTALIN 6 RN RT 0 1 XTALIN A 1 1 XTALIN 2 1 0 XTALIN Interrupt signal to the processor Active Low Multi function indicating OFF 1 fault conditions or card presence Open drain output configuration It includes an internal 22kQ pull up to Vpop RSTIN 2 Reset Input This signal is the reset command to the card System controller data I O to from the card Includes a pull up resistor to 3 V DD Rev 1 0 13 7358014R RN RT 2050 Demo Board User Manual UM 8014 010 3 3 73S8014R RN Pinout SO20 Top View TI I JCLKDIV1 CLKDIV2 II 15 73S8014R LITIGND CMDVCCLII je 73S8014RN I Tr3nsT XTALINI 11 Jo TI IVDDF ADJ XTALOUTL lo TI IGND 14 Rev 1 0 8014 010 73S8014R RN RT 2050 Demo Board User Manual 3 4 73S8014RT PINOUT 2050 Top View OFFL II I RSTINL 2 TI IPRES TT IVCC VPCLTT CLKDIV2L TT 7358014RT CMDVCC5L TT RST XTALINL I Jo 1 IVDDF ADJ XTALOUTL L JGND Rev 1 0 7358014R RN RT 2050 Demo Board User Manual UM 8014 010 4 Appendix This appendix includes the following tables and drawings of the PCB of the Evaluation Board Electrical Schematic Bill of Materials Silk Screen Layer Top side S
12. ilk Screen Layer Bottom side Metal Layer Top side Metal Layer Middle 1 ground plane Metal Layer Middle 2 supply plane Metal Layer Bottom 16 Rev 1 0 8014 010 73S8014R RN RT 2050 Demo Board User Manual Figure 4 TERIDIAN 7358014R RN RT 2050 Demo Board Electrical Schematic 33V 1 610 TSM 1107071 5 Jl J3 are placed the bottom 42 and J4 are placed on the top side 21 must be aligned with 22 and J3 must be aligned with J4 in order for this daughter board to be stacked on another TP4 Ji SCLK 519 1 VDD OFFB Ri GND VDDF ADJ GND DNI 5V 5 0V TET 5 1 SSM 11017 C1 10uF R3 E Cl C2 C8 and C5 must be J2 placed within 5mm of the Ul 62 0 1uF DNI 1 pins and connected by thick 2 TI track wider than 0 5mm 3 3 x 5 c6 6 CLKDIV1 8 T DNI 9 10 Y i OFF CLKDIV1 20 PRES 7 RSTIN PRES VOUC 4 50V 33V CLKDIV1 CLKDIV2 5 VPC CLK s CLKDIV2 coN ve GND 15 RST VDD 3 JP3 ZV3VE CMDVCC3B 7 CMDVCCIEMDVCCS 14 TO 5V3VB CMDVCC3 8 5 3V CMDVCC3 73 VDD XTALIN 9 GND VDD 5 2 VDD XTALIN VDDF ADJ CMDVCCB CMDVCC5 Yi 10
13. nd CLK Keep RST trace away from VCC and CLK traces Up to 30pF to ground is allowed for filtering Keep 0 1uF close to the VDD pin of the device and directly take other end to ground Keep 0 1uF and 10uF close to the VPC pin of the device and directly take other end to ground Keep 1 0uF close to the VCC pin of the smart card connector and directly take other end to ground 2 2 Optimization for Compliance with NDS Default configuration of the Demo Board contains a 27pF capacitor C12 from the CLK pin of the smart connector to ground and a 27pF capacitor C9 from the RST pin of the smart connector to ground These capacitors serve as filters for the CLK and RST signals in the case of long traces or test equipment perturbations The capacitor on CLK reduces ringing on the trace reduces coupling to other traces and slows down the edge of the CLK signal The capacitor on RST helps the perturbation specification in a noisy environment The filter capacitors can be useful in the EMV test environment and have no effect on NDS testing C12 and C9 are represented on both the schematic and BOM These capacitors are optional filter capacitors on the smart card lines CLK and RST respectively for each card interface These capacitors may be adjusted value not to exceed 30pF or removed to optimize performance in each specific application PCB card clock frequency compliance with applicable standards etc Rev 1 0 9 73S8014R RN RT 2050 Demo Boa
14. rd User Manual UM 8014 010 3 Use of the Board Hardware 3 1 Board Description Jumpers Switches and Test Points The items described in the following tables refer to the flags in Figure 2 1 Table 1 Demo Board Description Item Schemati A 8 PCB Figure _ Silk print Name 2 1 Reference 1 J2 Board 5V Connector that gathers the 5V supply of the board the supply and 7358014 data interface IOUC external clock SCLK host digital and interrupt OFF pins Note that the external clock SCLK can interface be left open when JP1 is in position XTAL Also note that the 5V power supply pin can be left open when JP2 is in position 3 3V support of cards only 2 JP3 VDD Select Jumper to select the digital voltage between 5V or 3 3V This setting defines the interfacing voltage with the host microcontroller It also provides internal supply voltage for internal circuitry to the 7388014R RN RT The default setting is in the 3 3V position Test Points 3 TP7 CLK 2 pin test points for each respective smart card signal The pin 4 TP5 RST label name is the respective signal i e VCC CLK and the other 5 TP3 VCC pin is GND 9 TP4 6 J4 Board 3 3V Connector that gathers the 3 3V supply of the board the supply and 7358014 host control signal pins RSTIN CMDVCC digital control CMDVCCS 5V 3V CMDVCC3 CLKDIV2 CLKDIV1 signals Note that the 3 3
15. ther pins 2kV Note ESD testing on Card pins is HBM condition 3 pulses each polarity referenced to ground 6 Rev 1 0 8014 010 73S8014R RN RT 2050 Demo Board User Manual External clock source JP1 must be in position SCLK when use of an external clock Otherwise pin SCLK can be left open Vpc Power Supply 4 5V to 5 5V 5V Typ 200mA 20 M VDDF ADJ m TERA DIAN E e SEMICONDUCTOR J 14 Se X gpi 1 1 0 E NO 2 gt 68 8014R RN RT DEMOBOARD ENP Figure 2 7358014R RN RT Demo Board Basic Connections Vpp Power Supply 2 7V to 3 6V 3 3V 50mA VDD GND RSTIN CMDVCC CMDVCC5 5V 3V CMDVCC3 CKDIV2 CKDIV1 Rev 1 0 8014 010 7358014 2050 Demo Board User Manual 2 Design Considerations 2 1 General Layout Rules Keep the CLK signal as short as possible and with few bends in the trace Keep route of the CLK trace to one layer avoid vias to other plane Keep CLK trace away from other traces especially RST and VCC Filtering of the CLK trace is allowed for noise purpose Up to 30pF to ground is allowed at the CLK pin of the smart card connector Also the 00 series resistor R7 can be replaced for additional filtering no more than 1000 Keep the VCC trace as short as possible Make trace a minimum of 0 5mm thick Also keep VCC away from other traces especially RST a
16. uency 1 5MHz 27MHz XTAL clock frequency 4 5MHz CLKDIV1 0 CLKDIV2 1 clock frequency 3MHz Y 12MHz XTAL clock frequency 3MHz 27MHz XTAL clock frequency 6 75MHz CLKDIV1 1 CLKDIV2 0 clock frequency 12MHz 12MHz XTAL clock frequency 12MHz 27MHz XTAL Illegal setting Clock is not guaranteed to be stable as the device spec max CLK frequency is 20MHz CLKDIV1 CLKDIV2 1 clock frequency 6MHz Y 12MHz XTAL clock frequency 6MHz Y 27MHz XTAL clock frequency 13 5MHz Rev 1 0 7358014R RN RT 2050 Demo Board User Manual UM_8014_010 1 4 Recommended Operating Conditions and Absolute Maximum Ratings 1 4 1 Recommended Operating Conditions Parameter Rating Supply Voltage 2 7 to 5 5 VDC 4 75 to 5 5 VDC ISO 7816 and EMV applications Supply Voltage V 4 85V to 5 5 VDC NDS applications Ambient Operating Temperature 40 C to 85 C Input Voltage for Digital Inputs OV to Vpp 0 3V 1 4 4 Absolute Maximum Ratings Operation outside these rating limits may cause permanent damage to the device Parameter Rating Supply Voltage Vpp 0 5 to 6 0 VDC Supply Voltage Vpc 0 5 to 6 0 VDC Input Voltage for Digital Inputs 0 3 to VDD 0 5 VDC Storage Temperature 60 to 150 Pin Voltage 0 3 to VDD 0 5 VDC Pin Current 100mA ESD Tolerance Card interface pins 6kV ESD Tolerance O

73S8014R/RN/RT 20SO Demo Board User Manual

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