78K0R/Fx3 - Renesas Electronics
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1. Operating Precautions for 78KOR Fx3 E Revision History 1 Update Added the A Version Products July 15 2011 RO1TU0003ED0101 For No 1 Added a comment to the Workaround for the A version Added item No 2 for all products 2n Update November 10 2011 01 0003 00102 Added item No 3 for all products 3 Update Modified and improved the workaround description for No 3 Added Remark on page 11 November 21 2011 RO1TU0003ED0103 ESAS RO1TUOOOSEDO 103 November 201 1 Renesas Electronics Europe2. SUB A ES HL SUB A ES HL byte SUB A ES HL B SUB ES HL C SUBC ES laddr16 SUBC ES HI SUBC ES HL byte SUBC ES HL B SUBC ES HL C AND A ES addr16 AND A ES HI AND A ES HL byte AND ES HL B AND ES HL C OR A ES addr16 OR A ES HL OR A ES HL byte OR A ES HL B OR ES HL C Operating Precautions for 78KOR Fx3 List of possible Data Flash Read Instructions cont d XOR A ES l addr16 ES HL XOR ES HL byte XOR A ES HL B XOR A ES HL C CMP A ES addr16 CMP A ES HL ES HL byte A ES HL B CMP A ES HL C CMP ES addr16 4byte CMPS ES addrl16 CMPS X ES HL byte ADDW ES addr16 ADDW ES HL byte SUBW ES addr16 SUBW ES HL byte CMPW AX ES addr16 CMPW ES HL byte 1 ES HL bit AND1 ES HL bit OR1 CY ES HL bit XOR1 ES HL bit BT ES HL bit Saddr20 BF ES HL bit Saddr20 Operating Precautions for 78KOR Fx3 D Valid Specification Date published Document Title July 2011 or later R01UH0007EJ0500 or later User s Manual Hardware
3. UPD78F1808AK8A2 uPD78F1809AK8A2 uPD78F1810AK8A2 uPD78F1811AK8A2 Non A version Products UPD78F1812GAA yPD78F1813GAA yPD78F1814GAA pPD78F1815GAA uyPD78F1816GAA 78 1817 uPD78F1826GAA yPD78F1827GAA pPD78F1828GAA uPD78F1829GAA UPD78F1830GAA UPD78F1812GAA2 uPD78F1813GAA2 uPD78F1814GAA2 yPD78F1815GAA2 uPD78F1816GAA2 78 1817 2 uPD78F1826GAA2 uPD78F1827GAA2 uyPD78F1828GAA2 uPD78F1829GAA2 78 1830 2 A Version Products pPD78F1812AGAA 78 181 pPD78F1814AGAA yPD78F1815AGAA pgPD78F1816AGAA yPD78F1817AGAA pPD78F1826AGAA uPD78F1827AGAA UPD78F1828AGAA yPD78F1829AGAA yPD78F1830AGAA uPD78F1812AGAA2 pPD78F1813AGAA2 yPD78F1814AGAA2 puPD78F1815AGAA2 yPD78F1816AGAA2 pPD78F1817AGAA2 yPD78F1826AGAA2 uPD78F1827AGAA2 yPD78F1828AGAA2 78F1829AGAA2 pPD78F1830AGAA2 Non A version Products UPD78F1812K8A uPD78F1813K8A uPD78F1814K8A UPD78F1815K8A uPD78F1816K8A UPD78F1817K8A uPD78F1826K8A uPD78F1827K8A uPD78F1828K8A uPD78F1829K8A pPD78F1830K8A UPD78F1812K8A2 uUPD78F1813K8A2 uUPD78F1814K8A2 uUPD78F1815K8A2 pPD78F1816K8A2 UPD78F1817K8A2 uPD78F1826K8A2 uPD78F1827K8A2 uPD78F1828K8A2 pPD78F1829K8A2 UPD78F1830K8A2 A Version Products pgPD78F1812AK8A yPD78F1813AK8A uPD78F1814AK8A yPD78F1815AK8A yPD78F1816AK8A pPD78F1817AK8A yPD78F1826AK8A uyPD78F1827AK8A uyPD78F1828AK8A yPD78F1829AK8A pgPD78F1830AK8A pgPD78F1812AK8A2 UPD78F1813AK8A2 UPD78F181
4. means any product developed or manufactured by or for Renesas Electronics Operating Precautions for 78KOR Fx3 Table of Contents A Related Products enne nnne trennen entes tenerse 5 B Table of Operating Precautions for 78 7 C Description of Operating Precautions for 78 8 No C1 UARTF LIN Automatic Baudrate Mode Direction of use 8 No C2 UARTF LIN Automatic Checksum Function Direction of use 9 No Data Flash Read access during DMA Transfer Direction of use 11 DEM Free m 15 E Revision HIStory u oas tete ten ae d LE eter tu N 16 Operating Precautions for 78KOR Fx3 A Related Products List of related products 78KOR FB3 Non A Version Products UPD78F1804MCA pPD78F1805MCA yPD78F1806MCA pPD78F1807MCA UPD78F1804MCA2 uPD78F1805MCA2 uPD78F1806MCA2 yPD78F1807MCA2 A Version Products UPD78F1804AMCA yPD78F1805AMCA yPD78F1806AMCA yPD78F1807AMCA UPD78F1804AMCA2 uPD78F1805AMCA2 78 1806 2 uPD78F1807AMCA2 78KOR FC3 Non A Version Products UPD78F1808K8A uPD78F 1809K8A uPD78F1810K8A uPD78F1811K8A UPD78F1808K8A2 uPD78F1809K8A2 uPD78F1810K8A2 UPD78F1811K8A2 A Version Products UPD78F1808AK8A uPD78F1809AK8A UPD78F1810AK8A uPD78F 1811 AK8A
5. 6 RE 6 cycles Cautions 1 Before any read access to the Data Flash will be executed be sure to wait for minimum two CPU clocks after DWAITALL 1 2 Disable all interrupts DI before DWAITALL 1 to prevent the execution of any interrupt service routine during the time when all DMA transfers are kept pending In case an interrupt service would be executed during the time between DWAITALL 1 until DWAITALL 0 a pending DMA transfer would be maybe blocked for a relative long time until the interrupt service is finished 3 For the above described workaround it is assumed the user application software is always using DWAITALL O If this is not always true please refer to Note 3 Notes 1 Save the current PSW status especially the current interrupt status El or DI 2 Disable interrupt DI will be necessary to prevent any interrupt service to be executed during the time when any DMA transfer is kept pending Please refer to Caution 2 as well 3 In case the user application software would also modify the bit DWAITALL e g DWAITALL 1 the corresponding actions need to be taken e g store the current DWAITALL status before SET1 DWAITALL and restore it after DWAITALL 0 4 Be sure to wait for minimum two CPU clocks before any Data Flash read instruction is executed after DWAITALL 1 For all possible Data Flash read instructions please refer to the list below 5 The two instructions NOP could also be replaced
6. 0 00 0 00 0 00 0 00 0 00 Transmitted by master CKSM 0x00 Calculated CKSM OxFF CKSM transmitted by master OxFF The message will be treated to be good 2 Message received with incorrect checksum Transmitted by master 0 06 Transmitted by master DATA 0x2C 0x3A 0x93 0x00 0x00 0x00 0x00 0x00 Transmitted by master CKSM OxFF Not correct for this message Calculated OxFF CKSM transmitted by master 0x1FE An incorrect message will be treated to be good Result An incorrect checksum is not detected Operating Precautions for 78KOR Fx3 Workaround If Automatic Baud Rate mode is selected UFnMD1 UFnMDO 11B clear the bit UFnACE 0 to disable the Automatic Checksum Function and calculate the corresponding checksum by means of software However the following two cases should be taken under consideration Response reception Checksum must be calculated by software from the data stored into the buffer and must be compared with the checksum obtained via communication UFnACE 0 Response transmission Either the checksum is calculated by software UFnACE 0 added to the end of the response transmission data and transmitted or the checksum could also be calculated automatically by the hardware of UARTF UFnACE 1 but if this feature is used please take care for the following caution In case the software will change back to Response Reception a reconfiguration of the UFnOPT1 reg
7. 4AK8A2 uPD78F1815AK8A2 pPD78F1816AK8A2 pPD78F1817AK8A2 UPD78F1826AK8A2 uPD78F1827AK8A2 UPD78F1828AK8A2 pPD78F1829AK8A2 uPD78F1830AK8A2 Operating Precautions for 78KOR Fx3 78KOR FES3 Non A Version Products UPD78F1818GBA uPD78F1819GBA yPD78F1820GBA uPD78F1821GBA uyPD78F1822GBA UPD78F1831GBA uPD78F1832GBA yPD78F1833GBA pPD78F1834GBA 78 1835 pgPD78F1818GBA2 uPD78F1819GBA2 uPD78F1820GBA2 uyPD78F1821GBA2 uPD78F1822GBA2 UPD78F1831GBA2 yPD78F1832GBA2 uPD78F1833GBA2 yPD78F1834GBA2 uPD78F1835GBA2 A Version Products UPD78F1818AGBA yPD78F1819AGBA uPD78F1820AGBA yPD78F1821AGBA UPD78F1822AGBA yPD78F1831AGBA uPD78F1832AGBA yPD78F1833AGBA UPD78F1834AGBA yPD78F1835AGBA 78 1818 2 yPD78F1819AGBA2 yPD78F1820AGBA2 uPD78F1821AGBA2 78 1822 2 uPD78F1831AGBA2 yPD78F1832AGBA2 uPD78F1833AGBA2 pgPD78F1834AGBA2 yPD78F1835AGBA2 78KOR FF3 Non A Version Products UPD78F1823GKA 78 1824 yPD78F1825GKA pPD78F1836GKA uPD78F1837GKA UPD78F1838GKA uyPD78F1839GKA yPD78F1840GKA uPD78F1823GKA2 uPD78F1824GKA2 UPD78F1825GKA2 uPD78F1836GKA2 uPD78F1837GKA2 uPD78F1838GKA2 uPD78F1839GKA2 UPD78F1840GKA2 A Version Products UPD78F1823AGKA yPD78F1824AGKA uPD78F1825AGKA yPD78F1836AGKA UPD78F1837AGKA yPD78F1838AGKA uPD78F1839AGKA yPD78F1840AGKA 78 182 2 yPD78F1824AGKA2 yPD78F1825AGKA2 uPD78F1836AGKA2 78 1837 2 yPD78F1838AGKA2 yPD
8. 78F1839AGKA2 uPD78F1840AGKA2 78KOR FG3 Non A Version Products pgPD78F1841GCA uPD78F1842GCA yPD78F1843GCA uPD78F1844GCA uPD78F1845GCA pgPD78F1841GCA2 uPD78F1842GCA2 uPD78F1843GCA2 uPD78F1844GCA2 UPD78F 1845GCA2 A Version Products pgPD78F1841AGCA uPD78F1842AGCA uPD78F1843AGCA uPD78F1844AGCA 78 1845 uPD78F1841AGCA2 uPD78F1842AGCA2 uPD78F1843AGCA2 UPD78F1844AGCA2 uPD78F1845AGCA2 Operating Precautions for 78KOR Fx3 B Table of Operating Precautions for 78KOR Fx3 Table B 1 Summary of restrictions 78KOR Fx3 Non A Version A Version Outline Rank Note UARTF LIN Automatic Baudrate Mode Direction of use 1 2 UARTF LIN Automatic Checksum Function Direction of use 3 Data Flash Read access during DMA Transfer Direction of use Not applicable x Applicable Not checked Note The rank is indicated by the letter appearing at the 5 position from the left in the lot number marked on each product ES Engineering Samples CS Commercial Samples MP gt Mass Production Operating Precautions for 78KOR Fx3 C Description of Operating Precautions for 78KOR Fx3 Table C 1 No C1 UARTF LIN Automatic Baudrate Mode Direction of use General Using the Automatic Baud Rate Mode in LIN slave operation the Syncfield SF is automatically detected and checked If the SF fails no proper 0x55 received the UARTF will abort the automatic baudrate sequence and wait for th
9. Operating Precautions for 78KOR Fx3 24 NE S AS Customer Notification 78KOR Fx3 16 Bit Single Chip Microcontroller Operating Precautions 78KOR FB3 Series 78KOR FC3 Series 78KOR FE3 Series 78KOR FF3 Series 78KOR FG3 Series Renesas Electronics Document No RO1TU0003ED0103 www renesas com Date Published November 2011 Operating Precautions for 78KOR Fx3 Notice All information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is granted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits so
10. by any other instruction which do not perform a Read from the Data Flash e g MOV A C MOVES A However it is important to wait at least for two CPU clocks by these instructions after DWAITALL 1 6 Restore the PSW status to continue the application software with respect to the Interrupt status before any DMA transfer was kept pending El or Dl Operating Precautions for 78KOR Fx3 List of possible Data Flash Read Instructions MOV A ES addr16 MOV A ES DE MOV A ES DE byte MOV A ES HL MOV A ES HL byte MOV ES HL B MOV ES HL C MOV A ES word B MOV A ES word C MOV A ES word BC MOV B ES addr16 MOV C ES addr16 MOV X ES l addr16 MOVW ES addr16 MOVW AX ES DE MOVW AX ES DE byte MOVW AX ES HL MOVW ES HL byte AX ES word B MOVW ES word C MOVW AX ES word BC MOVW BC ES addrl6 MOVW ODE 5 1 H MOVW ES laddr16 ADD A ES addr16 ADD A ES HI ADD A ES HL byte ADD A ES HL B ADD ES HL C ADDC ES laddr16 ADDC ES HL ADDC ES HL byte ADDC ES HL B ADDC ES HL C SUB A ES addr16
11. e classified according to the following three quality grades Standard High Quality and Specific The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application categorized as Specific without the prior written consent of Renesas Electronics Further you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots High Quality Transportation equipment automobiles trains ships etc traffic control s
12. e next Syncbreakfield SBF to restart the sequence If the duty cycle of the SF bits deviates from a nominal 50 duty cycle the internal circuit may not detect the 0x55 pattern of the SF anymore and therefore would abort the automatic baudrate detection sequence In case of an aborted baudrate detection sequence the UARTF receive interrupt INTLRx after the PID is not generated However there is no issue if the duty cycles of the SF on LRxDO LRxD1 is in the range of 4896 SF duty lt 52 Details Mechanism of SF detection Transmission reception stopped A B 55H eT based ONCE based on C Received low level widths are always measured Cx11 lt B gt BF successful However the SF will be checked based on the low level width of the Start bit If the low level width of the SF will become gt 52 the baudrate for the successful SF detection will be changed based on C and no valid SF 0x55 can be received anymore Due to this the UARTF does not generate the INTLRx and the slave will not respond v nett HT Start I i i bit E gt a EI Usecase The above described phenomenon with a duty cycle shift on LRxDO LRxD1 pin could be caused by the LIN transceivers For example LIN Master and LIN Slave are operating on different voltage levels Workaround For the Non A version products If baudrate detection of the SF is required the countermeasure will be the user has
13. ftware and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations Renesas Electronics has used reasonable care in preparing the information included in this document but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics products ar
14. ister becomes necessary change UFnACE from 1 to 0 But before changing UFnACE be sure to clear the bits UFnTXE and UFnRXE beforehand UFnTXE 0 UFnRXE 0 Operating Precautions for 78KOR Fx3 Table C 3 No C3 Data Flash Read access during DMA Transfer Direction of use General In case a Data Flash Read access will be performed exactly at the same timing while any DMA transfer is triggered there is a possibility for an internal bus conflict between CPU bus and Data Flash bus Such kind of bus conflict can cause a wrong data to be read from the Data Flash Workaround First of all the user must keep in mind that a Data Flash Read access can be done on two different manners Case 1 Data Flash Read access directly executed in the user software The workaround for the direct Data Flash Read access is described on the next page s Case 2 Data Flash Read access via the Data Flash Access Library FDL and or EEPROM Emulation Library EEL Both libraries are developed under the responsibility of Renesas Workaround for Case 2 The current FDL version V1 0 2 will be updated to take the aforementioned phenomena under consideration The current EEL version V1 0 6 will be updated to take the aforementioned phenomena under consideration Please contact your local Renesas sales support team to get the target schedules for the updated versions Remark However there will be no internal bus conflic
15. nics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you Operating Precautions for 78KOR Fx3 10 Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations 11 This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics 12 Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s
16. t as described above during any of the following Data Flash accesses Data Flash Write access via FDL Verify command via FDL Blank Check command via FDL In other words these Data Flash access commands can be executed without taking care of any workaround Operating Precautions for 78KOR Fx3 Workaround for Case 1 To prevent a DMA transfer during any of the below listed Data Flash Read instructions see the list on the next two pages the user has to suspend the DMA transfer for all DMA channels To suspend or to release any DMA transfer can be controlled by the DMCALL register in particular by the bit DWAITALL In case DWAITALL 1 all DMA channels are forced to wait until DWAITALL becomes 0 again Remark To keep the DMA suspension as short as possible we would recommend to perform the corresponding software modifications direct in Assembler language Software example before modification dataflash read asm MOVW HL AX 1 cycle MOV A 1 cycle MOV ES A 1 cycle MOV A ES HL 4 cycles RET 6 cycles Software example after modification dataflash_read_asm MOVW HL AX 1 cycle MOV A 1 cycle MOV ES A 1 cycle PUSH PSW 1 cycle Note 1 DI 4 cycles Note 2 SET1 DWAITALL 2 cycles Note 3 NOP 1 cycle Note 4 5 NOP 1 cycle Note 4 5 MOV A ES HL 4 cycles DWAITALL 2 cycles Note 3 POP PSW 3 cycles Note
17. to switch off the Automatic Baudrate Mode and perform the SF baudrate detection by means of software For the A Version Products The Automatic Baud Rate Mode UFnMD1 UFnMDO 11B can be used as described in the User s Manual But please take care for the item No 2 Operating Precautions for 78KOR Fx3 Table C 2 No C2 UARTF LIN Automatic Checksum Function Direction of use General Using the UARTF in Automatic Baud Rate Mode UFnMD1 UFnMDO 11 an Automatic Checksum Function UFnACE 1 is supported to calculate the checksum during response transmission or response reception automatically However some messages received with a specific data pattern including an incorrect checksum will not be detected as incorrect by the UARTF in Automatic Checksum Function mode m The issue applies to both classic amp enhanced PID included checksum It applies to response reception case It applies only to a very specific data checksum pattern When the checksum calculation result is 0x00 OxFF before inversion no carry 9th bit position has been added to the LSB and the received checksum is 0x00 LIN message frame Data i Bbyte header response To get a better understanding for the phenomena please refer to the below given data pattern examples for the enhanced checksum 1 Message received with correct checksum Transmitted by master 0 06 Transmitted by master 0 2 0 0 93
18. ystems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems medical equipment or systems for life support e g artificial life support devices or systems surgical implantations or healthcare intervention e g excision etc and any other applications or purposes that pose a direct threat to human life You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electro
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