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iSBC 86/12 Single Board Computer Hardware Reference Manual

1. Address hold time from command 05 Data setup to write CMD toHw Data hold time from write CMD CPU cycle time lCMOR Read command width No wait states tcMDW Write command width With 1 wait state lcswR Read to write command separation In override mode tcsRR Read to read command separation In override mode tcsww Write to write command separation In override mode Write to read command separation override mode Command to sample point In override mode Time between XACK samples In override mode AACK to valid read data When AACK is used lACKWT AACK or write command inactive When AACK is used Read data hold time tox Read data setup to XACK XACK hold time tDXL AACK to XACK turn off delay taws Bus low or high intervals Supplied by system 85 BPRN to BCLK setup time tDBY BCLK to BUSY delay BPRN to BPRO delay BCLK to bus request BCLK to bus priority out tacy Bus clock period BCLK From iSBC 86 12 when terminated taw Bus clock fow or high interval From iSBC 86 12 when terminated liNIT Initialization width After all voltages have stabilized Table 2 12 iSBC 86 12 AC Characteristics Slave Mode Address setup to command From address to command Write data setup to command Note 1 On board memory cycle delay No refresh Command to XACK Notes 1 and 2 Command width Note 1 Address h
2. ee 4 250 J 645 3 Figure 2 2 Simplified Master Slave PIC Interconnect Example 2 8 iSBC 86 12 NBV interrupt the master PIC generates the restart address or bus vectored BV interrupt the slave PIC generates the restart address Thus the master PIC can handle eight on board or single Multibus interrupt lines an interrupt line that is not driven by a slave PIC or up to 64 interrupts with the implemention of slave PIC s The iSBC 86 12 can also generate an interrupt to another interrupt handler via the Multibus This is accomplished by using one of the bits of the 8255A PPI to drive the BUS INTR OUT signal The BUS INTR OUT signal is ground true at jumper post 142 as footnoted in table 2 5 Default jumper 87 89 grounds the NMI nonmaskable interrupt input to the CPU to prevent the possibility of false interrupts being generated by noise spikes Since the NMI is not maskable cannot be disabled by the program and has the highest priority it should only be used to detect a power failure For this purpose disconnect de fault jumper 87 89 and connect 86 89 The Power Fail Interrupt PFI is an externally generated signal that is input via auxiliary connector P2 Refer to paragraph 2 20 Preparation for Use 2 14 SERIAL PORT CONFIGURATION Table 2 6 lists the signals signal functions and the jumpers required if necessary to input or output a particula
3. 2 7 3 12 PPI Control Word Format 3 15 2 2 Simplified Master Slave PIC 3 13 PPI Port C Bit Set Reset Control Interconnect Example 2 8 Word abet ARR Lue del 2 3 Bus Exchange Timing Master Mode 2 19 3 14 PIC Initialization Command 2 4 Bus Exchange Timing Slave 2 20 Word Formats 3 18 2 5 Serial Priority Resolution Scheme 2 21 3 15 PIC Operation Control Word Formats 3 20 2 6 Parallel Priority Resolution Scheme 2 2 4 iSBC 86 12 Input Output and Interrupt 3 1 Dual Port RAM Addressing Simplified Logic Diagram 4 15 A Multibus 3 2 4 2 ISBC 86 12 ROM EPROM and Dual Port RAM 3 2 USART Synchronous Mode Instruction Simplified Logic Diagram 4 17 Word Formal uve xc sak awka 3 4 4 3 Internal Bus 4 3 3 3 USART Synchronous Mode Transmission 4 4 CPU Read Timing i e Im es 4 5 la nir 3 4 4 5 CPU Write Timing 4 6 3 4 USART Asynchronous Mode Instruction 4 6 CPU Interrupt Acknowledge Word 3 5 Cycle Timing ssa deo tae cere sees 4 7 3 5 USART Asynchronous Mode Transmission 4 7 Dual Port Control Multibus Access FORMA E 3 5 Timing With CPU Lockout 4 9 3 6 USART Command Instruction 4 8 Dual Por
4. 1 CPU CONTROL MULTIBUS CONTROL 8086 CPU CONTROL 0 FOR REMAINDER OF MULTIBUS ACCESS TIMING SEE F G 4 7 BEGINNING WITH P3 645 14 Figure 4 8 Dual Port Control CPU Access Timing With Multibus Lockout 4 10 iSBC 86 12 The ON BD CMD signal is asserted at the same time as the ON BD RAM signal since A49 14 is high The ADV MEM RD or MEM signal from the Status Decoder is ORed with the ON BD RAM RQT signal to prevent A50 5 and A50 6 from changing states when ALE goes false at the end of T1 in the instruction A49 10 is allowed to go high on the next rising edge of the clock after ALE goes false The subsequently generated DP RD or DP WRT signal gated by the asserted ON BD CMD EN signal is trans mitted to RAM Controller A70 10ZB6 When the read or write is completed the RAM Controller asserts RAM XACK and A49 10 goes low at the end of P12 Atthe end of P13 the CPU terminates the instruction and the ON BD RAM RQT DP RD or DP WRT and ADV MEM MEM WRT signals go false The RAM signal is then terminated and A49 10 goes high at the end of PO At the end of P1 the SLA VE MODE is entered when A50 5 goes high and A50 6 goes low The foregoing discussion pertains only to the operation of the Dual Port Control Logic for CPU access of on board RAM The actual addressing and transfer of data are discussed in paragraph 4 34 4 26 MULTIBUS INTERFACE The Multibus inte
5. DD are invalid The IO AACK signal is driven through A32 8 and 8 respectively to develop PROM IO and ON BD ADR PROM IO EN enables Data Buffer A44 45 4ZD4 and ON BD ADR inhibits the Bus Arbiter and Bus Command Decoder The DT R output of Status De coder 81 is inverted to select the proper direction of data transfer through the Data Buffer After the proper I O device is enabled the specific func tion for the device is selected by address bits ABO ABI and the IORC or IOWC output of Status Decoder 81 4 29 SYSTEM OPERATION Address bits are decoded by I O Address Decoder as described in paragraph 4 27 If the address is not for an on board I O device the ON BD signal is false high and enables the Bus Arbiter Assembly and Bus Command Decoder A53 Refer to figure 5 2 sheet 3 The Bus Arbiter and Bus Command Decoder which are clocked by the 5 MHz clock to latch in and decode status signals 50 52 then acquire control of the Multibus as described in paragraph 4 26 4 30 ROM EPROM OPERATION The four ROM EPROM chips are installed by the user in IC sockets A28 29 46 47 Refer to figure 5 2 sheet 6 The ROM EPROM addresses are assigned from the top down in the 1 megabyte address space the bottom ad dress is determined by the user configuration of chips as follows FFO00 FFFFF FEO00 FFFFF FCO00 FFFFF Jumper posts 94 through 99 and switch S1 must be prop
6. BPRO BPRO BPRO iSBC 604 BACKPLANE BOTTOM 484 2 Figure 2 5 Serial Priority Resolution Scheme NO 1 NO 2 PRIORITY PRIORITY HIGHEST J2 J3 BREQ INPUTS B FROM MASTERS IN iSBC 614 mmacoozm lt 00 22 0 NOTE REFER TO TEXT REGARDING THE DISABLING OF BPRO OUTPUT 484 1 PRIORITY RESOLVER NO 8 NO 7 PRIORITY PRIORITY LOWEST J4 NOTE BREQ IO NOTE 7 6 5 OUTPUTS TO MASTERS IN iSBC 614 2 1 0 mmocooormo lt 2 9 Figure 2 6 Parallel Priority Resolution Scheme 1 isBC 604 BACKPLANE 2 21 Preparation for Use iSBC 86 12 Table 2 13 Auxiliary Connector P2 Pin Assignments Signal Definition GND GND 5V AUX 5V AUX 5V AUX sie 5V AUX Auxiliary backup battery supply 12V AUX 12V AUX Auxiliary common Power Fail interrupt This externally generated signal which is input to the priority interrupt jumper matrix should normally be connected to the 8086 CPU NMI input MEM PROT Memory Protect This externally generated signal prevents access to the dual port RAM during backup battery operation GND Auxili GND Common ALE Address Latch Enable The iSBC 86 12 activates ALE during T of every CPU machine cycle This signal may be used as an auxiliary address latch AUX
7. 2 9 Signal Characteristics 2 13 Serial Priority Resolution 2 13 Parallel Priority Resolution 2 13 Power Fail Memory Protect Configuration 2 13 Parallel I O Cabling 2 23 Serial VO Cabling ce Esteve Do oos bep 2 23 Board Installation 2 23 CHAPTER 3 PROGRAMMING INFORMATION IntfOdUC HOT occid b ce aS Cow 3 1 Failsafe T Ier ea kh ay Som Ps Memory Addressing RM 3 1 CPU ACCESS eti up ege URP S be Susa 3 1 Multibus Access gud a uM 3 2 UO Addiessillg v som aie V rex ER 3 3 System 3 3 8251A USART Programming 3 4 Mode Instruction Format 3 4 SYNC Characters Cc bc d 3 5 Command Instruction Format 3 5 Reset ae 3 5 55 y yu Seta tens 3 5 3 6 Operati b wid 3 7 Data gt 3 7 Status 3 7 5 PAGE 8253 PIT Programming 3 8 Mode Control Word and 3 8 B wa ob Goo eae ia 3 12 Initt liZatlo
8. State 3 State 1 is the idle state of the dual port bus and is left in control of the on board bus to minimize delays when the CPU needs it When the on board bus requires the dual port bus to access RAM the dual port bus control logic will go from State to State 2 If the dual port bus is busy it will wait until it is not busy Activity at this level requires a minimum of bus overhead and the Principles of Operation RAM performance is designed to equal that of on board activity if the dual port bus is not busy when the on board bus requests it The dual port bus control logic returns to State 1 when the CPU completes its operation This level of bus activity operates independently of Multi bus activity if the Multibus does not need the dual port bus When the Multibus requests the dual port bus the control logic goes from State 1 to 3 it will wait if busy in about 150 nanoseconds and upon completion returns to State 1 The Multibus use of the dual port bus is independent of the on board activity When the on board bus needs the Multibus it must go through the dual port bus to the Multibus The on board bus uses the dual port bus only to communicate with the Multibus and leaves the dual port bus in State 1 Activity at this level requires a minimum 200 nanosecond over head for Multibus exchange 4 12 MULTIBUS INTERFACE The 15 86 12 is completely Multibus compatible and supports both 8 bit and 16 bit op
9. Before programming the 8253 PIT ascertain the input clock frequency and the output function of each of the three counters These factors are determined and estab lished by the user during the installation 3 8 CHECK FOR TXRDY TRUE ENTER HERE IF TXRDY IS TRUE 3 19 MODE CONTROL WORD AND COUNT All three counters must be initialized prior to their use The initialization for each counter consists of two steps a mode control word figure 3 9 is written to the control register for each individual counter b down count number is loaded into each counter the down count number is in one or two 8 bit bytes as determined by mode control word The mode control word figure 3 9 does the following a Selects counter to be loaded b Selects counter operating mode Selects one of the following four counter read load functions 1 Counter latch for stable read operation 2 Read or load most significant byte only iSBC 86 12 Programming Information Lo 03 D 0 Ds D4 DVERRUN ERROR The OE flag is set when the CPU does not read a character before the next one becomes available it is reset by the ER bit of the Command instruction OE does not inhibit operation of the 8251 however the previously overrun character is tost 02 01 00 TRANSMITTER READY Indicates USART is ready to accept a data character or command RECEIVER READY indicates USART has rec
10. See figure A 6 b Disconnect brown wire shown in figure A 7 from plastic connector Connect this brown wire to ter minal L2 on mode switch Brown wire will have to be extended c Refer to figure A 4 and connect a wire Wire B from relay circuit board to terminal L1 on mode switch A 3 EXTERNAL CONNECTIONS Connect a two wire receive loop a two wire send loop and a two wire tape reader control loop to the external device as shown in figure A 4 The external connector pin numbers shown in figure A 4 are for interface with an RS232C device 4 iSBC 530 TTY ADAPTER The iSBC 530 which converts RS232C signal levels to an optically isolated 20 mA current loop interface provides signal translation for transmitted data received data and a paper tape reader relay The iSBC 530 interfaces an Intel iSBC 80 computer system to a teletypewriter as shown in figure A 8 The iSBC 530 requires 12V at 98 mA and 12V at 98 mA An auxiliary supply must be used if the iSBC 80 system does not supply this power A schematic diagram of the iSBC 530 15 supplied with the unit The following auxiliary power connector or equivalent must be procured by the user Connector Molex 09 50 7071 Pins Molex 08 50 0106 Polarizing Key Molex 15 04 0219 Teletypewriter Modifications 9 MODE SWITCH TOP VIEW MOUNT CIRCUIT CARD PRINTER UNIT CURRENT DISTRIBUTOR TR
11. The eight Multibus interrupt lines INTO INT7 can be connected to the master PIC to provide 8 to 64 bus interrupt levels The user can map interrupt sources into interrupt levels by hardware jumpers The iSBC 86 12 can also generate one Multibus interrupt that is controlled by an 8255A PPI output bit 4 9 ROM EPROM CONFIGURATION IC sockets A28 A29 A46 and A47 are provided for user installation of ROM or EPROM chips jumpers are provided to accommodate either 2K 4K or 8K chips The ROM EPROM address space is located at the top of the 1 megabyte memory space because the 8086 CPU branches to FFFFO after a reset Starting addresses for the different ROM EPROM configurations FF000 using 2K chips using 4K chips and 000 using 8K chips 4 2 iSBC 86 12 4 10 RAM CONFIGURATION The iSBC 86 12 includes 32K bytes of read write memory composed of sixteen 2117 Dynamic RAM chips and an 8202 RAM Controller The Dual Port Control Logic interfaces the RAM with the Multibus so that the iSBC 86 12 can perform as a slave RAM device when not acting as a bus master This dual port is designed to maximize the CPU throughput by de faulting control to the CPU when not in demand Each time a bus master generates a memory request to the dual port RAM via the Multibus the RAM must be taken away from the CPU when the CPU is not using it When the slave request is completed the control of the RAM retums to the
12. Vin 2 4V mA Capacitive Load pF ADRO ADRF ADR10 ADR13 Output Low Voltage Output High Voltage Input Low Voltage Input High Voltage Input Current at Low V input Current at High V Output Leakage High Output Leakage Low Capacitive Load BCLK Output Low Voltage V Output High Voltage V input Low Voltage V Input High Voltage V Input Current at Low V mA Input Current at High V pA Capacitive Load pF BHEN Output Low Voltage V Output High Voltage V input Low Voltage V Input High Voltage V Input Current at Low V mA Input Current at High V pA Capacitive Load pF BPRN Input Low Voltage V Input High Voltage V Input Current at Low V 0 5 mA Input Current at High V 50 pA Capacitive Load 18 pF Output 0 45 V Output High Voltage V Capacitive Load 15 pF Output Low Voltage Output High Voltage Capacitive Load lo 20 mA 0 4 mA BREQ Voi VoH BUSY CBRQ INTROUT OPEN COLLECTOR 0 45 V 2 4 V 10 pF lo 20 mA 20 pF Output Low Voltage Capacitive Load gt lt Capacitive load values approximations 2 16 iSBC 86 12 Signals CCLK 1 SYSTEM RESET INTO INT7 IORC INTA MWTC Preparation for Use Table 2 10 iSBC 86 12 DC Characteristics Continued Test Conditions Parameter De
13. erly configured to accommodate the type of ROM EPROM installed Refer to table 2 4 iSBC 86 12 IC sockets A29 and A47 accommodate the top of IC sockets A28 and A46 accommodate the ROM EPROM space directly below that installed in A29 and A47 The low order bytes bits DBO DB7 are in stalled A29 and A28 the high order bytes bits DB8 DBF are installed in A47 and A46 When ADV IO ADR is false a custom ROM 68 6ZB6 decodes address bits 12 If the address 15 within the limit specified above the O4 and O3 output pins will be low and the O2 and O1 output pins will depend on whether the address is in the upper half or lower half of the address block For instance 1f 2758 EPROM chips are installed and the address is in the range FFOOO FF7FF the O2 and O1 pins will be high and low respec tively if the address is in the range FF800 FFFFF the O2 and pins will both be high The O4 and output pins are compared with address bit AB13 If AB13 is high the PROM signal is asserted if AB13 is low the ON BD RAM RQT signal is asserted When ALE goes false Decoder A18 6ZC4 is enabled and decodes the inputs presented by the O2 and O1 output of A68 If O2 O1 10 PCS2 is asserted and enables A28 and A46 if O2 and O1 11 PS3 is asserted and enables A29 and A47 Each chip of the selected pair of chips are individually addressed by AB1 ABA Thus when the associated enable
14. the fly The recommended procedure is to use a mode control word to latch the contents of the count register this ensures that the count reading is accurate and stable The latched value of the count can then be read NOTE If a counter is read during the down count it is mandatory to complete the read procedure that is if two bytes were programmed to the counter then two bytes must be read before any other operations are performed with that counter read the count of a particular counter proceed as follows a typical counter read subroutine is given in table 3 10 Programming Information a Write counter register latch control word figure 3 11 00006 Control word specifies desired counter and selects counter latching operation b Perform a read operation of desired counter refer to table 3 2 for counter addresses NOTE Be sure to read one two bytes whichever was specified in the initializa ton mode control word For two bytes read in the order specified 3 24 CLOCK FREQUENCY DIVIDE RATIO SELECTION Table 2 4 lists the default and optional timer input frequencies to Counters 0 through 3 The timer input frequencies are divided by the counters to generate TMRO INTR OUT Counter 0 TMRI INTR OUT Counter 1 and the 8251 A Baud Rate Clock Counter 2 exe DIETS T Don t Care Selects Counter Latching Operation Specifies Counter to be Latched Figure 3 11 PIT Counter Register Latch
15. 000C2 If no slave PIC s are used omit ICW3 and write ICW4 only to 000 2 c Initialize each slave PIC by writing ICW s in the following sequence ICW1 ICW2 and ICW4 d Enable system interrupts by executing an STI Set Interrupt Flag instruction NOTE Each PIC independently operates in the nested mode paragraph 3 38 after initial ization and before an Operation Control Word OCW programs it otherwise 3 49 OPERATION After initialization the master PIC and slave PIC s can independently be programmed at any time by an Opera tion Command Word OCW for the following operations Auto rotating priority Specific rotating priority Status read of Interrupt Request Register IRR Status read of In Service Register ISR Interrupt mask bits are set reset or read Special mask mode set or reset 3 19 Programming Information iSBC 86 13 INTERRUPT MASK 1 MASK SET 0 MASK RESET OCW2 D D D D D DO D D BCD LEVEL TO BE RESET OR PUT INTO LOWEST PRIORITY NON SPECIFIC END OF INTERRUPT 1 RESET THE HIGHEST PRIORITY BIT OF ISR 0 NO ACTION SPECIFIC END OF INTERRUPT 1 12 L3 Lo BITS ARE USED 0 NO ACTION ROTATE PRIORITY 1 ROTATE 0 NOT ROTATE OCW3 Dj D D D D D D D READ IN SERVICE REGISTER DON T CARE NO ACTION POLLING A HIGH ENABLES THE NEXT RD PULSE READ THE BCO CODE OF THE HIGH EST LEVEL REQUESTING INTERRUPT SPECIAL MAS
16. C closed switch position O open switch position Default jumpers and switch settings accommodate Intel 2316E 2716 chips Disconnect existing configuration jumpers if necessary and reset switch 51 if reconfiguration is required Dual Port RAM Multibus Access 287 286 The dual port RAM permits access by the local on board CPU and any system bus master via the Multibus For local CPU access the dual port RAM address space is fixed beginning at location 00000 For access via the Multibus one jumper and one switch can configure the dual port RAM on any 8K boundary within the 1 megabyte address space Refer to paragraph 2 12 for configuration details 3286 3287 10242 Default jumper 105 106 routes Bus Clock signal BCLK to the Multibus Refer to table 2 9 Remove this jumper only if another bus master supplies this signal Default jumper 103 104 routes Constant Clock signal CCLK to the Multibus Refer to table 2 9 Remove this jumper only if another bus Bus Clock master supplies this signal Constant Clock Bus Priority Out 3ZD2 Default jumper 151 152 routes Bus Priority Out signal BPRO to the Multibus Refer to table 2 9 Remove this jumper only in those systems employing a parallel priority bus resolution scheme Refer to paragraph 2 19 Bus Arbitration 288 207 3202 3ZC3 The Common Bus Request signal CBRQ from the Multibus and the ANYROST input to the Bus Arbiter chip are not presen
17. Connect RESET input to P2 pin 38 This signal is usually supplied by a momentary closure switch mounted on the system enclosure f Connect ALE output signal to P2 pin 32 2 21 PARALLEL I O CABLING Parallel ports C8 and CC controlled by the Intel 8255 Programmable Peripheral Interface PPI are interfaced via edge connector J1 Refer to figure 1 1 Pin assignments for connector J1 are listed in table 2 15 dc characteristics of the parallel I O signals are given in table 2 16 Table 2 2 lists some 50 pin edge connectors that can be used for interface to J1 and J2 flat crimp solder and wirewrap connector types are listed The transmission path from the I O source to the iSBC 86 12 should be limited to 3 meters 10 feet maximum The following bulk cable types or equivalent are recom mended for interfacing with the parallel I O ports a Cable flat 50 conductor 3M 3306 50 b Cable flat 50 conductor with plane 3M 3380 50 c Cable woven 25 pair 3M 3321 25 An Intel iSBC 956 Cable Set consisting of two cable assemblies is recommended for parallel I O interfacing Both cable assemblies consist of a 50 conductor flat cable with a 50 pin PC connector at one end When attaching the cable to J1 be sure that the connector is oriented properly with respect to pin 1 on the edge connector Refer to the footnote in table 2 15 2 22 SERIAL I O CABLING Pin assignments and signal definitions f
18. Data CYCLE TIME MEMORY CAPACITY On Board ROM EPROM On Board Dynamic RAM Off Board Expansion MEMORY ADDRESSING On Board ROM EPROM On Board RAM CPU Access On Board RAM Multibus Access SERIAL COMMUNICATIONS Synchronous Asynchronous Sample Baud Rate 1 4 iSBC 86 12 Table 1 1 Specifications 8 16 24 or 32 bits 8 16 bits 800 nanosecond for fastest executable instruction assumes instruction is in the queue 1 2 microseconds for fastest executable instruction assumes instruction is not in the queue Up to 16K bytes user installed in 1K 2K or 4K byte increments 32K bytes Integrity maintained during power failure with user furnished batteries Up to 1 megabyte of user specified combination of RAM ROM and EPROM FFOOO FFFFFy using 2758 EPROM s FEOOO FFFFF using 2316E ROM s or 2716 EPROM s and FCOOO FFFFF using 2332 ROM s 00000 07FFF Jumpers and switches allow board to act as slave RAM device for access by another bus master Addresses may be set within any 8K boundary of any 128K segment of the 1 megabyte system address space Access is selectable for 8K 16K 24K or 32K bytes 5 6 7 or 8 bit characters intemal 1 or 2 sync characters Automatic sync insertion 5 6 7 or 8 bit characters Break character generation 1 1 or 2 stop bits False start bit detection Baud Rate Hz Frequency Notes 1 Frequency selected by write
19. NMI TERT 3 25 Maskable Interrupt INTR 3 25 Master PIC Byte 3 25 Slave PIC Byte Identifier 2 3 25 4 PRINCIPLES OPERATION Introduction y dats Ra RE E a 4 1 Functional Description 4 1 Clock nd 4 1 Central Processor Unit 4 1 Interval Tuners ay z y teer ERO RU RE RENS 4 1 Seral VO os aa 4 1 Parallel UO onte KOK Sucua a 4 1 Interrupt 4 2 ROM EPROM Configuration 4 2 RAM Configuration 4 2 Bus EIER aac Whee qu es 4 2 Multibus Interface Re ade ope 4 3 PAGE Circuit Aa YSIS xa sed a Sie ean Ante os 4 3 222 ade tons wa naa ae 4 4 Clock sop dites th to Dice 4 4 Central Processor Unit 4 4 ssec tenore ER e POE ER x 4 4 BUS TIMIDE 55 Send eta x Dabo EN 4 4 Address BUS cogo 4 6 Dara BUS asses 4 6 BUS TNS 91 PT 4 6 Internal Control Signals 4 8 Dual Port Control oet uus iuc cae eddie a 4 8 Multibus Access Timing 4 8 CPU Aecess THWIn
20. Reset The externally generated signal initiates a power up sequence i e initializes the iSBC 86 12 and resets the entire system to a known internal state odd numbered pins 1 3 5 59 on component side of the board Pin 1 is the left most pin when viewed from the component side of the board with the extractors at the top Table 2 14 Auxiliary Signal Connector P2 DC Characteristics Parameter Test Output Low Voltage lo 8 mA Output High Voltage lou 1 0 mA 2 4 Capacitive Load Input Current at High V Input Low Voltage Input High Voltage MEM PROT Capacitive Load RESET Input Low Voltage Input High Voltage Input Current at Low V Vin 0 45V Input Current at High V Vin 5 25V _ Capacitive Load Input Current at Low V Capacitance load values are approximations Input Current at High V Capacitive Load Input Low Voltage Input High Voltage Input Current at Low V Vin 0 45V Vin 5 25V 2 22 jSBC 86 12 b Connect 5 battery input to 2 pins 3 and 4 5 battery input to P2 pins 7 and 8 and 12V battery input to P2 pins 11 and 12 Remove jumpers W4 W5 and W6 c Connect MEM PROT input to P2 pin 20 Connect PFI input to P2 pin 19 this signal is inverted and applied to the priority jumper matrix To assign the PFI input the highest priority 8086 NMI input remove jumper 87 89 and connect jumper 86 89 e
21. Two of these individual switches are used for ROM EPROM configuration Two switches 6 11 and 5 12 are configured to allow 8K 16K 24K or 32K bytes of dual port RAM to be accessed Four switches 1 16 2 15 3 14 and 4 13 are configured to displace the addresses from the top of the selected 128K byte segment of memory Figure 2 1 provides an example of 8K bytes of dual port RAM being made accessible from the Multibus and how the addresses are established Note in figure 2 1 that the Multibus accesses the dual port RAM from the top down Thus as shown for 8K byte access via the Multibus the bottom 24K bytes of the iSBC 86 12 on board RAM is reserved strictly for on board CPU access Table 2 3 Line Driver and I O Terminator Locations 8255A PPI Interface 0 3 A12 204 4 7 13 204 0 3 11 205 9703 4 7 10 205 9283 Figure 5 2 is the schematic diagram Grid reference 9ZA3 for example denotes sheet 9 Zone 5 2 Grid Ref 92 92 iSBC 86 12 Preparation for Use Table 2 4 Jumper and Switch Selectable Options Fig 5 1 Grid Ref Fig 5 2 Grid Ref Description ROM EPROM ZC3 ZB6 Configuration ZD7 6283 62 7 2286 Jumpers 94 through 99 and switch 51 may be configured to accommodate four types of ROM EPROM chips ROM EPROM Type 94 95 97 98 94 96 97 98 94 96 97 99 2758 2316E 2716 2332 Reserved
22. 0 in the control word Then load the count value N which is derived by N TC where N 15 the count value for Counter 2 T is the desired interrupt time interval in seconds and C is the internal clock frequency Hz Table 3 13 shows the count value N required for several time intervals T that can be generated for Counters 0 and 1 3 29 8255A PPI PROGRAMMING The three parallel I O ports interfaced to connector J1 are controlled by an Intel 8255A Programmable Peripheral Interface Port A includes bidirectional data buffers and Ports B and C include IC sockets for installation of either input terminators or output drivers depending on the user s application iSBC 86 12 Programming Information Table 3 12 PIT Rate Generator Frequencies and Timer Intervals Single Timer2 Counter 1 Dual Timer3 0 and 1 in Series 76 8 kHz 0 00029 Hz 307 2 kHz Single Timer Counter 0 Minimum Rate Generator frequency 18 75 Hz 614 4 kHz 2 344 Hz 13 psec Real Time Interrupt interval 1 63 psec 53 3 msec NOTES 1 Assuming a 1 23 MHz clock input 2 Assuming a 153 6 kHz clock input 3 Assuming Counter 0 has 1 23 MHz clock input Table 3 13 PIT Time Intervals Vs Timer Counts CONTROL WORD ae 1 5 10 msec 50 5 Count Values assume clock is 1 23 MHz Count Values N are in decimal GROUP B PORT C LOWER 1 INPU
23. 3 Interrupt request on level 0 interrupt request on level 1 iSBC 86 12 Address bus Ground Power input Ground odd numbered pins 1 3 5 85 are on component side of the board Pin 1 is the left most pin when viewed from the component side of the board with the extractors at the top All unassigned pins are reserved 2 14 iSBC 86 12 Signal ADRO ADRF ADR10 ADR13 BCLK BHEN BPRN BREQ BUSY CBRQ CCLK DATO DATF INH1 INIT INTA INTO INT7 IORC lOWC MRDC MWTC XACK Preparation for Use Table 2 9 Multibus Signal Functions Functional Description Address These 20 lines transmit the address of the memory location or VO port to be accessed For memory access ADRO when active low enables the even byte bank DATO DAT 7 on the Multibus i e ADRO is active low for all even addresses ADR13 is the most significant address bit Bus Clock Used to synchronize the bus contention logic on all bus masters When generated by the iSBC 86 12 BCLK has a period of 108 5 nanoseconds 9 22 MHz with a 35 65 percent duty cycle Byte High Enable When active low enables the odd byte bank DAT8 DATF onto the Multibus Bus Priority In Indicates to a particular bus master that no higher priority bus master is requesting use of the bus BPRN is synchronized with BCLK Bus Priority Out In serial daisy chain priority re
24. 3 1 Dual Port RAM Addressing 645 4 Multibus Access iSBC 86 12 3 6 1 0 ADDRESSING The CPU communicates with the on board programmable chips through a sequence of I O Read and Write Commands As shown in table 3 2 each of these chips recognizes four separate hexadecimal I O addresses that are used to control the various programmable functions The address decoder operates on the lower eight bits and all addresses must be on an even byte boundary Where two hexadecimal addresses are listed for single function either address may be used For example an I O Read Command to 000DA OOODE will read the status of the 8251A USART Programming Information 3 7 SYSTEM INITIALIZATION When power is initially applied to the system a reset signal is automatically generated that performs the following a The 8086 CPU internal registers are set as follows PSW 0000 IP 0000 DS 0000 ES 0000 Code Relocation Register FFFF This effectively causes a long JMP to FFFFO Table 3 2 I O Address Assignments Address Select Function 000 0 Write ICW1 OCW2 OCW3 or Read Status and 000C4 8259A 000C2 PIC Write ICW2 ICW3 ICW4 OCW1 Mask Or Read 1 Mask 000C6 000C8 Write Port A J1 Read Port A J1 000 8255 Write Port B J1 PPI Read Port B J1 000 Write Port C J1 Read Port C Status 000 Write Control Read None 00000 Write Cou
25. 8 pin 5 2W OBD COML 1 RP2 Res pack 14 pin 1K 2 1 5W PP OBD COML 1 RP3 Res pack 16 pin 10K 5 2W PP OBD COML 1 RP4 Res pack 6 pin 2 2K 5 1W PP OBD COML 1 R1 11 16 17 Res fxd comp 10K 5 OBD COML 4 R2 22 Res fxd comp 20K 5 VAW OBD COML 2 R3 5 13 20 Res fxd comp 5 1K 5 VAW OBD COML 5 R7 8 10 14 18 19 21 23 Res fxd comp 1K 5 1 4W OBD COML 8 H9 Res fxd comp 100K 5 VaW OBD COML 1 R12 Res fxd comp 330 ohm 5 VaW OBD COML 1 R15 Res fxd comp 270 ohm 5 OBD COML 1 51 Switch 8 position DIP 206 8 CTS 1 Voltage regulator 79105 1 15 86 12 Service Information Table 5 1 Replaceable Parts Continued Reference Designation Description Mfr XA8 9 Socket 16 pin DIP C 93 16 02 XA10 13 Socket 14 pin DIP C 93 14 02 XA27 socket 28 pin DIP C 93 28 02 XA28 29 46 47 Socket 24 pin DIP C 93 24 02 9 70 Socket 40 pin DIP 540 A37D XA67 68 Socket 18 pin DIP C 93 18 02 71 91 Socket 20 DIP C 93 20 02 NN NN NN Crystal 22 1184 MHz fundamental OBD Crystal 15 MHz fundamental OBD Crystal 18 432 2 fundamental OBD Extractor Card 5 203 Post Wire Wrap 89531 6 Plug Shorting 2 position 530153 1 Table 5 2 List of Manufacturers Codes ADDRESS MANUFACTURER ADDRESS Harrisburg PA NAT National Santa Clara CA Semiconductor
26. CPU The dual port consists of CPU address and data buffers and decoder bidirectional address and data bus Multibus drivers slave RAM address decoder translator control logic and the RAM and RAM controller The CPU address and data buffers separate the on board bus I O and ROM EPROM from the dual port bus On board RAM addresses as seen by the CPU are assigned from the bottom up 00000 07FFF The address bus drivers and data bus drivers separate the dual port bus from the Multibus The slave RAM address decoder is separate from the CPU RAM address decoder to provide independent Multibus address selection that can be located throughout the 1 megabyte address space The slave RAM address is selected by specifying the base address and memory size The base address can be on any 8K boundary with the exception that the memory space cannot extend across a 128K boundary The memory size specifies the amount of Dual Port RAM accessible by the Multibus and is switch selectable in 8K increments This provides the capability to reserve sec tions of the dual port RAM for ie only by the CPU and frees up the address space Regardless of what base address is selected the slave RAM address is mapped into an on board RAM address as seen by the CPU Refer to figure 2 1 4 11 BUS STRUCTURE The iSBC 86 12 architecture is organized around a three bus hierarchy the on board bus the dual port bus and the Multibus Refer to figure
27. CPU The 8086 CPU includes four 16 bit general purpose regis ters that may also be addressed as eight 8 bit registers In addition the CPU contains two 16 bit pointer registers and two 16 bit index registers Four 16 bit segment regis ters allow extended addressing to a full megabyte of memory The CPU instruction set supports a wide range of addressing modes and data transfer operations signed and unsigned 8 bit and 16 bit arithmetic including hardware multiply and divide and logical and string oper ations The CPU architecture features dynamic code relo cation reentrant code and instruction lookahead The iSBC 86 12 has an internal bus for all on board memory and operations and accesses the system bus Multibus for all external memory and I O operations Hence local on board operations do not involve the Multibus making the Multibus available for true parallel processing when several bus masters e g DMA devices and other single board computers are used in a multimas ter scheme Dual port control logic is included to interface the dynamic RAM with the Multibus so that the iSBC 86 12 can function as a slave RAM device when not in control of the Multibus The CPU has priority when accessing on board RAM After the CPU completes its read or write PARALLEL yo SERIAL AUXILIARY 645 1 Figure 1 1 iSBC 86 12 Single Board Computer 1 1 General Information operation the controlling bus ma
28. Control Word Format 450 19A Table 3 10 Typical PIT Counter Read Subroutine READ1 READS COUNTER 1 ON THE FLY INTO D amp E MSB IN D LSB IN E DESTROYS AD E PUBLIC READ1 READ1 MOV AL 40H OUT OD2H MOV WORD FOR LATCHING COUNTER 1 VALUE LSB OF COUNTER OF COUNTER 3 13 Programming Information Each counter must be programmed with a down count number or count value N When count value N is loaded into a counter it becomes the clock divisor To derive N for either synchronous or asynchronous RS232C operation use the procedures described in following paragraphs 3 25 Synchronous Mode the synchronous mode the TXC and or RXC rates equal the Baud rate Therefore the count value is determined by N C B where N is the count value B is the desired Baud rate and C is 1 23 MHz the input clock frequency Thus for a 4800 Baud rate the required count value N 15 _ 1 23 10 _ N 400 If the binary equivalent of count value N 256 is loaded into Counter 2 then the output frequency is 4800 Hz which is the desired clock rate for synchronous mode operation 3 26 Asynchronous Mode the asynchronous mode the TXC and or RXC rates equal the Baud rate times one of the following multipliers X1 X16 or X64 Therefore the count value is determined by where is the c
29. MODE NESTED MODE 645 6 Figure 3 14 PIC Initialization Command Word Formats 15 86 12 b For programming a slave PIC code bits 3 5 with a slave identification ID number Do not use 000 unless there are eight PIC s slaved to the on board master PIC These ID bits are retained and returned by the slave PIC in response to a CPU interrupt acknowledge The third Initialization Control Word ICW3 is required only if bit 1 ICW1 specifying that multiple PIC s are used 1 e one or more PIC s are slaved to the on board master PIC The 5 57 bits correspond to the IRO IR7 bits of the master PIC For example if a slave PIC is connected to the master PIC IR3 input code bit 3 1 The fourth Initialization Control Word IC W4 which 15 required for all modes of operation consists of the following a Bits O and 3 are both 1 5 to identify that the word is ICW4 for 8086 CPU and that the hardware is configured for buffered operation b Bit programs the End of Interrupt EOI function Code bit 1 1 if an EOI is to be automatically executed hardware Code bit 1 0 if an EOI com mand is to be generated by software before returning from the service routine Bit2specifies if ICW4 is addressed to a master PIC or a slave PIC Forexample code bit 2 in ICW4 for the master PIC d Bit 4 programs the nested or fully nested mode Refer to paragraphs 3 38 and 3 39 In summary three or four ICW s a
30. PIC which on demand provides an 8 bit identifier of the interrupting source The CPU multiplies the 8 bit identifier by four to derive a pointer to the service routine for the interrupting device Interrupt requests may originate from 18 sources without the necessity of external hardware Two jumper selectable interrupt requests can be automatically gener ated by the Programmable Peripheral Interface PPI when a byte of information is ready to be transferred to the 8086 CPU i e input buffer is full or a byte of informa tion has been transferred to a peripheral device i e output buffer is empty Two jumper selectable interrupt requests can be automatically generated by the USART when a character is ready to be transferred to the 8086 CPU receive channel buffer is full or when character is ready to be transmitted i e transmit channel data buffer is empty A jumper selectable interrupt request can be generated by two of the programmable counters and eight additional interrupt request lines are available to the user for direct interfaces to user designated peripheral devices via the Multibus One interrupt request line may be jumper routed directly from a peripheral via the parallel I O driver terminator section and one power fail interrupt may be input via auxiliary connector P2 The iSBC 86 12 includes the resources for supporting a variety of OEM system requirements For those applica tions requiring additional pro
31. Terminator Locations 2 4 Jumper and Switch Selectable Options 2 5 Priority Interrupt Jumper Matrix 2 8 Serial I O Connector J2 Pin Assignments Vs Configuration Jumpers 2 9 Parallel Port Configuration Jumpers 2 10 Multibus Connector Pin Assignments 2 14 Multibus Signal Functions 2 15 iSBC 86 12 DC Characteristics 2 16 iSBC 86 12 AC Characteristics Master Mode 2 18 ISBC 86 12 AC Characteristics Slave Mode ciis 2 18 Auxiliary Connector P2 Pin Assignments vind 2d Auxiliary Signal Connector P2 DG Characteristics vet teres 2 22 Parallel I O Connector J1 Pin Assignments 2 23 Parallel Signal Connector J1 DC rre ter d 2 24 Connector J2 Vs RS232C Pin COMeSPONdENCE ea gee 2 24 On Board Memory Addresses CPU ACCESS sss bos QE tee 3 2 Address Assignments 3 3 Typical USART Mode or Command Instruction Subroutine 3 7 Typical USART Data Character Read Z Kop 3 8 Typical USART Data Character Write SUDLOULING ed ews 3 8 3 12 3 13 3 14 3 15 3 16 3 17 TABLES TITLE PAGE Typical USART Status Read Subroutine 3 9 PIT Counter Operation Vs Gate Inputs 3 12 Typical PIT Control Word Subr
32. board CPU or by another bus master via the Multibus When not acting as a bus master or when not accessing the dual port RAM the iSBC 86 12 can act as a slave RAM device in a multiple bus master system When accessing the dual port RAM the on board CPU has priority over any at tempt to access the dual port RAM via the Multibus In this situation the bus access is held off until the CPU has completed its particular read or write operation When a bus access is in progress the Dual Port Control Logic enters the slave mode and any subsequent CPU request will be held off until the slave mode is terminated Figures 4 7 and 4 8 are timing diagrams for the Dual Port Control Logic 4 8 iSBC 86 1988 4 24 MULTIBUS ACCESS TIMING Figure 4 7 1 lustrates the Dual Port Control Logic timing for dual port RAM access via the Multibus P periods PO through P17 are used only for descriptive purposes and have no rela tionship to the 22 12 MHz clock signal When the OFF BD RAM CMD signal goes high A49 10 goes high and A49 7 goes low on the next rising edge of the clock at the end of PO assuming that ON BD RAM RQT and RAM are both high At the end of P1 A50 5 goes high and A50 6 goes low 50 6 asserts the SLA VE signal The outputs of A50 6 and A49 7 are ANDed to hold A50 5 in the preset high state At the end of P2 A49 14 goes low and asserts the SLA VE CMD EN signal which gates DP R
33. can be accessed by the on board 8086 micro processor CPU or by another bus master via the Multibus The ROM EPROM can be accessed only by the CPU The dual port RAM can be accessed by another bus master that currently has control of the Multibus It should be noted that even though another bus master may be con tinually accessing the dual port RAM this does not pre vent the CPU from also accessing the dual port RAM When this situation occurs memory accesses by the CPU and controlling bus master are interleaved Such inter leaved access will of course impose a longer wait state both for the CPU and for the controlling bus master Dual port RAM access by another bus master does not interfere with the CPU while it is accessing the on board ROM EPROM and I O devices 3 4 CPU ACCESS Addresses for CPU access of ROM EPROM and on board RAM are provided in table 3 1 Note that the ROM EPROM addresses are assigned from the top down of the 1 megabyte address space with the bottom address being determined by the user ROM EPROM configura tion The on board RAM addresses are assigned from the bottom up of the 1 megabyte address space When the CPU is addressing on board memory RAM ROM or an internal acknowledge signal is automatically generated and imposes one wait state for each CPU operation When the CPU is addressing system memory via the Multibus the CPU must first gain control of the Multibus and after the Memory
34. changing the direction of the bus during read operations In the event that a not ready indication is given by the addressed device wait states TW are inserted between and T4 Each inserted TW state is of the same duration as a CLK cycle Periods can occur between CPU driven bus cycles these periods are referred to as idle states TI or inactive CLK cycles The processor uses TI states for internal housekeeping 4 18 BUS TIMING The CPU generates status signals SO S1 and S2 during T1 of every machine cycle These status signals are used by Status Decoder 81 Bus Arbiter Assembly and Bus Command Decoder A83 to identify the following types of machine cycles Interrupt Acknowledge Read Write Halt Code Access Memory Read Memory Write Passive O O A read cycle begins with the assertion of the Address Latch Enable ALE signal and the emission of the address Refer to figure 4 4 The trailing edge of ALE signal latches the address into Address Latch 40 41 57 2ZB2 The BHEN signal and address bit ADO address the low byte high byte or both bytes The Data Transmit Receive DT R signal which is asserted at the end of T1 is used to set up the various data buffer and data bus drivers for a CPU read operation The Memory Read Command MRDC or Read Com mand IORC is asserted from the beginning of T2 to the beginning
35. for each 8 bit parallel input port iSBC 86 12 Preparation for Use Table 2 2 User Furnished Connector Details Centers Connector intel inches Type Vendor Vendor Part No Part No Parallel I O 25 50 0 1 Flat Crimp Connector Parallel AMP 25 50 0 1 Soldered VIKING Connector 3415 0000 WITH EARS 3415 0001 W O EARS 88083 1 609 5015 506750 SERIES iSBC 956 Cable Set 2 583485 6 3VH25 1JV5 N A H312125 H311125 Parallel VIKING 3VH25 1JND5 S AN 24 50 e Wirewrap VPBO1B25D00A1 NS ITT CANNON EC4A050A1A 3462 0001 88106 1 609 2615 SD6726 SERIES iSBC 955 Cable Set Serial 13 26 0 1 Flat Crimp Connector 13 26 Soldered 1 a Multibus Connector 43 86 0 156 Soldered Multibus Connector 43 86 po Wirewrap H312113 1 583485 5 N A CDC VPBO1E43D00A1 MICRO PLASTICS MP 0156 43 BW 4 ARCO AE443WP1 LESS EARS VIKING 2VH43 1AV5 CDC VFB01E43D00A1 or CDC VPB01E43A00A1 MDS 985 VIKING 2VH43 1AV5 Auxiliary H312130 Connector 30 60 Soldered VIKING 3VH30 1JN5 N A VPBO01B30A00A2 N A H311130 Auxiliary Connector heights are not guaranteed to conform to OEM packaging equipment Wirewrap pin lengths are not guaranteed to conform to OEM packaging equipment CDC 02 4 e
36. for port control Refer to table 3 2 3 15 Programming Information 3 32 INITIALIZATION To initialize the PPI write a control word to OOOCE Refer to figure 3 12 and table 3 14 and assume that the control word is 92 hexadecimal This initializes the PPI as follows Mode Set Flag active Port A C8 set to Mode 0 Input Port CC upper set to Mode Output Port B CA set to Mode 0 Input Port C CC lower set to Mode 0 Output Ok p om iSBC 86 12 3 33 OPERATION After the PPI has been initialized the operation is simply performing a read or a write to the appropriate port 3 34 READ OPERATION A typical read subroutine for Port A is given in table 3 15 3 35 WRITE OPERATION A typical write sub routine for Port C is given in table 3 16 As shown in figure 3 13 any of the Port C bits can be selectively set or cleared by writing a control word to 000CE Table 3 14 Typical PPI Initialization Subroutine INTPAR INITIALIZES PARALLEL PORTS 3DESTROYS A PUBLIC INTPAR INTPAR MOV A 92H OUT RET END MODE WORD TO PPI PORT A amp B OUT Table 3 15 Typical PPI Port Read Subroutine _ AREAD READS A BYTE FROM PORT A INTO REG DESTROYS A AREAD IN RET BYTE END Table 3 16 Typical PPI Port Write Subroutine COUT OUTPUTS A BYTE FROM REG A PORT USES A DESTROYS NOTHING PUBLIC COUT OUT OCCH RET BYTE END
37. freezes the internal state of its priority resolution logic The first INTA signal also sets flip flop A63 5 8ZA2 which generates the Ist ACK signal to drive the CPU READY input high The CPU then proceeds with the second INTA cycle On receipt of the second INTA signal the master PIC places an 8 bit identifier for IR5 on the data bus and drives its DEN output low The resultant LOCAL INTA DEN signal enables Data Buffer A44 and drives the CPU READY input high The second INTA signal clears 4 14 flip flop A63 5 The CPU then inputs the 8 bit identifies and terminates the interrupt timing cycle The CPU multiplies the 8 bit identifier by four to derive the restart address of the interrupting device After the service routine is completed the CPU automatically re sets all its affected flags and returns to the main program 4 39 BV INTERRUPT As far as the CPU is con cerned BV interrupts are handled exactly the same as NBV interrupts Assume that the IR6 line to the master PIC is driven by a slave PIC on the Multibus When IR6 goes high the master PIC drives the CPU INTR input high as previously described On receipt of the first INTA signal the master PIC generates BUS INTA DEN via its DEN output and places the interrupt address code for IR6 on its 0 2 pins since QMCE is enabled by the MCE output of the Status Decoder the CO C2 is transferred to the Address Latch via address lines AD8 ADA These bits are
38. latched when the ALE signal goes false The BUS INTA DEN signal enables the Data Bus Driver in prep aration to receive the 8 bit identifier from the slave PIC The interrupt address code is now on Multibus address lines ADR8 ADRA The first INTA signal sets flip flop A63 5 to drive the CPU READY input high The CPU then proceeds with the second INTA cycle When the second INTA signal is driven onto the Multibus and the slave PIC recognizes its address it outputs an 8 bit identifier onto the DATO DAT7 lines and drives the Multibus XACK line low The second INTA also toggles and clears flip flop A63 5 The CPU then inputs the 8 bit identifier and terminates the interrupt timing cycle The CPU multiplies the 8 bit identifier by four to derive the restart address of the interrupting device After the service routine is completed the CPU automatically re sets all its affected flags and returns to the main program 1 INTRODUCTION This appendix provides information required to modify a Model ASR 33 Teletypewriter for use with certain Intel iSBC 80 computer systems A 2 INTERNAL MODIFICATIONS Hazardous voltages are exposed when the top cover of the teletypewriter is removed To prevent accidental shock disconnect the teleprinter power cord before proceeding beyond this point Remove the top cover and modify the teletypewriter as follows a Remove blue lead from 750 ohm tap on current source register reconne
39. of command or data words The TXRDY bit 15 inactive until initialization has been completed do not check TXRDY until after the command word which concludes the initialization proce dure has been written TXRDY TXRDY MUST TRUE ENTER HERE FOR INITIALIZATION Prior to any operating change anew command word must be written with command bits changed as appropriate Refer to figure 3 6 and table 3 3 3 16 DATA INPUT OUTPUT For data receive or transmit operations perform a read or write respectively to the USART Table 3 4 and 3 5 provide examples of typical character read and write subroutines During normal transmit operation the USART generates a Transmit Ready TXRDY signal that indicates that the USART is ready to accept a data character for transmis sion TXRDY is automatically reset when the CPU loads a character into the USART Similarly during normal receive operation the USART generates a Receive Ready RXRDY signal that indicates that a character has been received and is ready for input to the CPU RXRDY is automatically reset when a character is read by the CPU The TXRDY and RXRDY outputs of the USART are available at the priority interrupt jumper matrix If for instance TXRDY and RXRDY are input to the 8259A PIC the PIC resolves the priority and interrupts the CPU TXRDY and RXRDY are also available in the status word Refer to paragraph 3 16 3 17 STATUS READ The CPU can deter
40. of T4 At the beginning of T3 the ADO ADI5 lines of the local bus are switched to the data mode and the Data Enable DEN signal is asserted The DEN signal enables the data buffers The CPU examines the state of its READY input during the last half of T3 If its READY input is high signifying that the addressed device has placed data on the data lines the CPU proceeds into T4 if its READY input is low the CPU enters a wait TW state and stays there until READY iSBC 86 12 T1 2 5 2 CLK 52 51 0 VALID BHEN AD16 AD19 E ALE ADDRESS ADO AD15 DT R MRDC DEN NOTE AMWC MWTC AIOWC IOWC VOH DENOTES CPU INPUT OR OUTPUT DENOTES STATUS DECODER A81 OUTPUT SIGNAL mie Principles of Operation 4 FLOAT ii DATA IN BN FLOAT 645 10 Figure 4 4 CPU Read Timing goes high The external effect of using the READY input is to preserve the exact state of the CPU at the end of T3 for an integral number of clock periods before finishing the machine cycle This stretching of the system timing in effect increases the allowable access time for memory or devices By inserting TW states the CPU can accommodate slower memory or slower I O devices CPU accepts the data and terminates the command in T4 the DEN signal then goes false and the data buffers are tristated A write cycle begins
41. one or more interrupts are masked If for any reason an input is masked while it is being serviced the lower priority interrupts are disabled However it is possible to enable the lower priority interrupt with the Special Mask Mode In this mode the lower priority lines are enabled until the Special Mask Mode is reset Higher priorities are not affected 3 43 POLL MODE In this mode the CPU internal Interrupt Enable flip flop is clear interrupts disabled and a software subroutine is used to initiate a Poll command In the Poll Mode the addressed PIC treats an I O Read Command as an interrupt acknowledge sets its In Service flip flop if there is a pending interrupt request and reads the priority level This mode is useful if there is acommon service routine for several devices 3 44 STATUS READ Interrupt request inputs is handled by the following two internal PIC registers a Interrupt Request Register IRR which stores all interrupt levels that are requesting service b In Service Register ISR which stores all interrupt levels that are being serviced Either register can be read by writing a suitable command word and then performing a read operation 3 45 INITIALIZATION COMMAND WORDS The on board master PIC and each slave PIC requires a Separate initialization sequence to work in a particular mode The initialization sequence depending on the hardware configuration requires either three or four of the Initializ
42. options to allow the user to configure the board for his particular application Table 2 4 summarizes these options and lists the grid reference locations of the jumpers and switches as shown in figure 5 1 parts location diagram and figure 5 2 schematic diagram Because the schematic diagram consists of 11 sheets grid iSBC 86 12 references to figure 5 2 may be either four or five alpha numeric characters For example grid reference 3ZB7 signifies sheet 3 Zone B7 Study table 2 4 carefully while making reference to fig ures 5 1 and 5 2 If the default factory configured jumpers and switch settings are appropriate for a partic ular function no further action is required for that function If however a different configuration is re quired reconfigure the switch settings and or remove the default jumper s and install an optional jumper s as specified For most options the information in table 2 4 is sufficient for proper configuration Additional information where necessary for clarity is described in subsequent paragraphs 2 12 RAM ADDRESSES MULTIBUS ACCESS The dual port RAM can be shared with other bus masters via the Multibus One jumper wire connected between a selected pair of jumper posts 113 through 128 places the dual port RAM in one of eight 128K byte segments of the 1 address space Switch S1 is dual inline package DIP composed of eight individual single pole single throw switches
43. read the chip status and check for the TXRDY bit prior to writing either data or com mand words to the USART This ensures that any prior input is not overwritten and lost Note that issuing a Programming Information GENERATED BY 8251A PARITY BIT TRANSMITTER OUTPUT 0001 START 3 A TxC MARKING BIT DATA BITS M STOP BITS DOES NOT APPEAR RECEIVER INPUT 4 ON E dd BUS START PARITY lt 5 a PROGRAMMED CHARACTER LENGTH TRANSMISSION FORMAT CPL BYTE 58 BITS CHAR 4 DATA CHARACTER 4 ASSEMBLED SERIAL DATA OUTPUT TxD PARITY STOP DATA CHARACTER 4 RECEIVE FORMAT SEFIAL DATA INPUT RxD f PARITY STOP C 4 CPU BYTE 58 BITS CHAR DATA CHARACTER NOTE IF CHARACTER LENGTH IS DEFINED AS 5 6 OR 7 BITS THE UNUSED BITS ARE SET TO ZERO Figure 3 5 USART Asynchronous Mode Transmission Format Command instruction with bit 6 IR set will ret rn the USART to the Mode instruction format 3 12 RESET To change the Mode instruction word the USART must receive a Reset command The next word written to the USART after a Reset command 15 assumed to be a Mode instruction Similarly for sync mode the next word after a Mode instruction is assumed to be one or more sync characters All control words written into the USART after the Mode instruction and or the sync character are assumed to be C
44. the Clock Generator is prepared to recognize the ensuing acknowledge signal AACK or XACK transmitted by the addressed system device To ensure adequate setup for the address and data counter A4 2ZB5 is held in the clear state as long as ALE is asserted When ALE goes false A4 3 is clocked low by the 5 MHz clock to generate T21 This signal 21 is driven through gate A2 11 to enable the Bus Command Decoder The false ON BD ADR signal also enables the Bus Command Decoder which decodes 50 52 and drives the appropriate command low on the Multibus when 21 occurs The Bus Command Decoder also drives BUS DEN high to enable Data Bus Driver A69 89 The Data Bus Driver is switched to the appropriate transmit or receive mode depending on the state of the DT R output of Status Decoder 81 After the command is acknowledged signified by the addressed device driving the Multibus XACK line low the CPU terminates the appropriate command The Bus Arbiter and Bus Command Decoder respectively termi nate BUS ADEN and BUS DEN the Bus Arbiter also relinquishes control of the Multibus by driving BREQ high and BPRO low and then raising BUSY It should be noted that after gaining control of the Mul tibus the iSBC 86 12 can invoke bus lock condition to prevent losing control at a critical time For instance it may be desired to execute several consecutive commands without having to contend for the
45. these three 1 3 SYSTEM SOFTWARE DEVELOPMENT The development cycle of iSBC 86 12 based products may be significantly reduced using an Intel Intellec Mic rocomputer Development System The resident text editor and system monitor greatly simplify the design develop ment and debug of iSBC system software optional diskette operating system provides a relocating loader and linkage editor and a library manager Intel s high level programming language PL M 86 is also available as a resident Intellec Microcomputer Develop ment System option PL M 86 provides the capability to program in a natural algorithmic language and eliminates the need to manage register usage or allocate memory PL M 86 programs can be written in a much shorter time than assembly language programs for a given application 1 4 EQUIPMENT SUPPLIED The following are supplied with the iSBC 86 12 Single Board Computer a Schematic diagram dwg no 2002259 b Assembly drawing dwg no 1001801 1 5 EQUIPMENT REQUIRED Because the iSBC 86 12 is designed to satisfy a variety of applications the user must purchase and install only those components required to satisfy his particular needs A list of components required to configure all the intended ap plications of the iSBC 86 12 is provided in table 2 1 1 6 SPECIFICATIONS Specifications of the iSBC 86 12 Single Board are listed table 1 1 General Information WORD SIZE Instruction
46. to the interrupt jumper matrix 87121 4 22 INTERNAL CONTROL SIGNALS Status Decoder A81 3ZB3 receives the 5 MHz CLK signal from Clock Generator A38 and status signals 50 52 from CPU A39 The CLK signal establishes when the command signals are generated as a result of decoding 50 52 The following signals are output from Status De coder A81 m omm Address Latch Enable Strobes address into Ad dress Latch A40 41 57 Advanced Write An VO Write Command that is issued earlier than IOWC in an attempt to avoid imposing a CPU wait state Advanced Memory Write Command A Memory Write Command that is issued earlier than in an attempt to avoid imposing a CPU wait state Data Enable Enables Data Buffers A44 and A60 61 Data TransmitiReceive Establishes direction of data transfer through Data Buffers A44 45 and A60 61 and Data Bus Buffers A69 89 90 Read Command to on board PPI USART PIT and PIC Write Command to on board PPI USART PIT and PIC Interrupt Acknowledge Provides on board trol during INTA cycle Master Cascade Enable Enable cascade ad dress from master 8259A PIC onto local bus so that slave address be latched Memory Read Command AMWC Memory Write Command 4 23 DUAL PORT CONTROL LOGIC The Dual Port Control Logic figure 5 2 sheet 11 allows the dual port RAM facilities to be shared by the on
47. 122 123 124 125 126 127 128 MEM AVAIL TO BUS Uff 2222 16 24 Z a L9 gt ose ASK EXPLANATION A SELECTS X PARAMETER 128K BYTE SEGMENT SELECTS Z PARAMETER MEMORY AVAILABLE TO BUS SELECTS PARAMETER LOCATION WITHIN 128K SEGMENT ADDRESS UPPER ADDRESS LOWER X Y Z IN THE EXAMPLE SHOWN IN THE SHADED PATH X C0000 Y OBFFF AND Z 1 THUS C0000 Y CBFFF ADDRESS UPPER 01FFF 2 8K CA000 ADDRESS LOWER IMPORTANT THE SELECTED MEMORY SPACE CANNOT EXTEND ACROSS A 128K BYTE BOUNDARY THAT IS X Y Z MUST BE EQUAL TO OR GREATER THAN THE ABSOLUTE VALUE OF X 7 Y PARAMETER ADDRESS Yj DISPLACEMENT 29696355 2 e rele oo om Yom berate Zig LLL ZZ CA000 CBFFF OFFFF whl O7FFF none Lo C C 13FFF SELL 2 o 17FFF 04000 UT 1DFFF Gi NN ME 00000 PARAMETER 645 2 Figure 2 1 Dual Port RAM Address Configuration Multibus Access 2 7 Preparation for Use iSBC 86 12 Table 2 5 Priority Interrupt Jumper Matrix Interrupt Request From Interrupt Request To 73 Multibus 2 Multibus 2 INTO 1 67 8259A PIC 6 86 88 84 85 142 8086 CPU 5 Requires positive true signal at associ
48. 2 write a command word in the following format to 000 0 ror vo os es oe 9 1 1 0 0 0 2 L1 LO BCD of bottom priority IR line 3 22 iSBC 86 12 Operation Interrupt Request Register IRR Status In Service Register ISR Status interrupt Mask Register Special Mask Mode NOTE Programming Information Table 3 20 PIC Operation Procedures Continued Procedure The IRR stores a 1 in the associated bit for each IR input line that is requesting an interrupt To read the IRR refer to footnote 1 Write OAH to 00000 2 Read 000 0 Status is as follows gt os 7 6 5 4 3 2 1 0 P M J M M M IR Line The ISR stores a 1 in the associated bit for priority inputs that are being serviced The ISR is updated when an EO command is issued To read the ISR refer to footnote 1 Write OBH to 000 0 2 Read 000 0 Status is as follows GOL 7 6 5 4 3 2 1 0 Be sure to reset ISR bit at end of interrupt when in the following modes Auto Rotating both types and Special Mask To reset ISR OCW2 write or os os or oo 0 1 1 0 0 L2 L1 LO SN ee BCD identifies bit to be reset WM r n n T n OU I VT l To set mask bits in OCW1 write the following mask byte to 000C2 or os os os os IR Bit Mask M7 6 5
49. 2 00 inches b Height 17 15 6 75 inches c Thickness 1 78 cm 0 70 inch 2 8 COMPONENT INSTALLATION Instructions for installing optional ROM EPROM and parallel VO port line drivers and or line terminators are given in following paragraphs When installing these chip components be sure to orient pin 1 of the chip adjacent to the white dot located near pin 1 of the associated IC socket The grid zone location on figure 5 1 parts location diagram is specified for each component chip to be installed 2 9 ROM EPROM CHIPS IC sockets A28 A29 A46 and A47 figure 5 1 zone C3 accommodate 24 pin ROM EPROM chips Because the CPU jumps to location FFFFO on a power up or reset the address space resides in the topmost por tion of the 1 megabyte address space and must be loaded from the top down sockets A29 and A47 accom modate the top of the ROM EPROM address space and must always be loaded IC sockets A28 and A46 accom modate the ROM EPROM space directly below that in stalled in A29 and A47 2 1 Preparation for Use iSBC 86 12 Table 2 1 User Furnished and Installed Components iSBC 604 Connector mates with P1 Modular Backplane and Cardcage In cludes four slots with bus terminators See figure 5 3 Provides power input pins and Multibus signal interface between iSBC 86 12 and three additional boards in a multiple board system Modula
50. 2 to function ina master slave relationship with the Multibus to allow another bus master to access the on board dual port RAM 4 2 FUNCTIONAL DESCRIPTION A brief description of the functional blocks of logic comprising the iSBC 86 12 is given in following para graphs A operational circuit analysis is given beginning with paragraph 4 13 4 3 CLOCK CIRCUITS The clock circuit composed of 16 17 and A18 is stabilized by 22 1184 MHz crystal This circuit pro vides nominal 153 7 kHz 1 23 MHz and 2 46 MHz optional clock frequencies to the 8253 Programmable Interval Timer PIT 2 46 MHz Baud rate clock to the 8251 Universal Synchronous Asynchronous Receiver lransmitter USART and a 22 12 MHz clock frequency to the Dual Port Control Logic and RAM Controller The clock circuit composed of A80 and A63 is stabilized by an 18 432 MHz crystal This circuit divides the crystal frequency by two to provide the nominal 9 22 MHz Bus Clock BCLK and Constant Clock CCLK signals to the Multibus The BCLK signal is also used by the Bus Arbiter Assembly Remove able jumpers are provided to allow this clock circuit to be disabled if some other source supplies BCLK and CCLK to the Multibus Clock A38 is stabilized by a 15 MHz crystal and provides a nominal 5 MHz clock to CPU A39 Status Decoder A81 the Bus Arbiter Assembly and Bus Command Decoder A83 Clock A38 also provides a reset signal on power up and when commanded t
51. 28 29 46 47 623 to on board RAM address recognition gate A53 6 6ZD6 4 20 DATA BUS At the beginning of clock cycle T2 the CPU ADO ADI5 pins become the source or destination of data bus ADO ADF Datacan be sourced to or input from the following a Data Buffer A44 45 AZD4 b Data Buffer 60 61 4705 4 21 BUS TIME OUT Bus Time Out one shot A5 10ZA6 is triggered by the leading edge of the ALE signal If the CPU halts or is hung up in a wait state for approximately 6 2 15 nanoseconds 5 times out and asserts the TIMEOUT signal If jumper 5 6 is installed the TIMEOUT signal iSBC 86 12 T1 5 MHZ CLK 52 S1 SO BHEN AD16 AD19 gt ALE Principles of Operation FLOAT FLOAT CASCADE ADDRESS FLOAT FLOAT NOTE 2 AB A10 NOTE 2 AD8 AD15 FLOAT NOTE 2 POINTER FLOAT ADO AD7 NE MCE DT R INTA DEN w NOTES 1 MRDC IORC AMWC MWTC AIOWC IOWC VoL 2 THE TWO INTA CYCLES RUN BACK TO BACK THUS THE LOCAL BUS IS FLOATING WHEN THE SECOND INTA CYCLE IS ENTERED DENOTES CPU INPUT OR OUTPUT DENOTES STATUS DECODER A81 OUTPUT Figure 4 6 CPU Interrupt Acknowledge Cycle Timing ES 4 7 Principles of Operation drives the CPU READY line high through 7 12 and A38 5 to allow the CPU to exit the wait state The TIMEOUT signal is also routed as a TIMEOUT INTR signal
52. 4 3 Each bus can com municate only within itself and an adjacent bus and each bus can operate independently of each other The per formance of the iSBC 86 12 is directly related to which bus it must go to perform an operation that is the closer the bus to the on board bus the better the performance iSBC 86 12 MULTIBUS EMT E A DUAL PORT SRY BUS N ON BOARD BUS 645 9 Figure 4 3 Internal Bus Structure 15 86 12 operates at 5 MHz CPU cycle and requires one wait state for all on board system accesses Exception a RAM write requires two wait states However the pipeline effect of the 8086 CPU effectively hides these wait states The core of the iSBC 86 12 series bus architecture is the on board bus which connects the CPU to all on board devices ROM EPROM and the dual port RAM bus Activity on this bus does not require control of the outer buses thus permitting independent execution of on board activities Activities at this level require no bus overhead and operate at maximum board performance The next bus in the hierarchy is the dual port bus This bus controls the dynamic RAM and communicates with the on board bus and the Multibus The dual port bus can be in one of three states a State 1 On board bus is controlling it but not using it not busy b State 2 On board bus ts controlling it and using it busy Multibus is controlling it and using it busy
53. 425 Dual 4 Input Positive NOR Gate w Strobe SN7425 TI 1 64 748140 Dual 4 Input Positive NAND Gate SN74S140 TI 1 A65 8097 3 State Hex Buffers 8097 1 66 Intel 8205 1 of 8 Decoder 8205 COML 1 A67 PROM Address Decoder INTEL 9100134 1 A68 PROM Address Decoder INTEL 9100129 1 Intel 8287 8 Bit inverting Transceiver 8287 COML 5 Intel 8202 Dynamic RAM Controller 8202 COML 1 A72 79 92 99 Intel 2117 4 Dynamic RAM 2117 4 COML 16 A81 83 Intel 8288 Bus Controller for 8086 8288 COML 2 A86 745240 Octal Buffer Line Driver Line Receiver 5 745240 1 CR1 2 Diode 1N9148 OBD COML 2 C1 2 4 11 13 15 19 Cap mono 0 1uF 80 20 0 50V OBD COML 57 21 25 28 51 65 75 91 C3 Cap mono 1 04 F 10 o 50V OBO COML 1 12 27 64 mica 10pF 5 500 OBD COML 3 C20 98 Cap mono 0 0014 F 20 50V OBD COML 2 C26 Cap tant 10uF 10 20V OBD COML 1 52 54 55 57 58 60 61 Cap mono 0 33 80 20 50V COML 17 63 76 78 79 81 82 84 85 87 92 C53 56 59 62 77 80 Cap mono 0 01uF 80 20 50V OBD COML 8 83 86 C88 90 93 97 Cap tant 22uF 10 15V OBD COML 8 J12 Assembly Bus Arbiter 1001794 INTEL 1 Bus Controller INTEL 1 C 74500 Quad 2 Input Positive NAND Gate SN74S00 Resistor fxd comp 270 ohm 5 VaW OBD COML 1 Resistor fxd comp 2 2K 5 VAW OBD COML 1 Capacitor mono 0 14nF 80 20 50V OBD COML 1 Capacitor mono 220pF 5 o 500V OBD COML 1 Res pack
54. 49 7 has been clocked low Flip Flop A50 9 is preset high when the Status Decoder asserts the ALE signal at the beginning of T1 in the CPU instruction cycle When the ON BD RAM RQT signal is asserted the EXT ALE signal goes low and since 51 6 is now low A49 10 goes low on the next rising edge of the clock Flip flop A50 5 is thus prevented from being clocked high and therefore keeps the DP ON BD ADR signal asserted A50 6 remains high and suppresses the SLAVE signal SBC 86 12 Principles of Operation P14 DUAL PORT CLK P PERIODS PO P1 P2 P15 P16 P17 OFF BD RAM CMD 0 1 A49 10Q 0 f gt 1 FF A50 5 Q 0 _ 50 6 4 0 1 FF A49 14 Q 0 1 FF A49 7 Q 0 1 SLAVE CMD EN 0 DP RD OR DP 0 0 1 8086 CPUCONTROL 0 CPU CONTROL MULTIBUS CONTROL Figure 4 7 Dual Port Control Multibus Access Timing 645 13 With CPU Lockout 4 9 Principles of Operation ISBC DUAL PORT CLK P PERIODS PO P12 P13 P1 P2 P3 4 22 12 MHZ CLK OFF BD RAM CMD 0 P 1 ons FF A49 10 Q 0 DP ON BD CMD EN 50 5 0 SLAVE FF 50 6 1 N TS x FF A49 14 Q k 2 1 49 7 0 SLAVE CMD 0 x DP RD OR DP WRT 0 1 ADV MEM RD OR MEM WRT 0 RAM 0
55. Bit 0 Can only be used for jumper option see figure 5 2 zone 92 6 Bits 1 2 Can be used for input or output if Port CC is in Mode O Connects J1 26 to 5 input Connects IBFa output to J1 24 Connects J1 30 to input Bit 3 Port C8 Inter rupt PA INTR to inter rupt jumper matrix Connects a output to J1 18 Bit 4 Port C8 Strobe STB input Connects INT output to interrupt matrix Bit 5 Port C8 Input Buffer Full IBF output Bit 6 Port C8 Ac knowledge ACK input Bit 7 Port C8 Output Buffer Full OBF output C8 None Port CC can be in Mode 0 input or output if Port C8 is also in Mode 0 0 12 13 latched Bit 2 Port CA Strobe 1 Input 10 12 A13 Connects output strobed D A11 to J1 22 13 14 Connects J1 32 to 30 31 STBp input Connects INTg output interrupt matrix _ NM STB input Default jumper connected at the factory 2 11 None Port CC can be in Mode 0 input or output if Port C8 is also in Mode 0 8 8 Port CC bits perform the following Bit 0 Port CA Inter rupt PB INTR to inter rupt jumper matrix Bit 1 Port CA Input Buffer Full IBF output Preparation for Use iSBC 86 12 Table 2 7 Parallel I O Port Configuration Jumpers Continued Jumper Configuration Dr
56. C Intel 8224 Clock Generator and Driver IC 748139 Decoder Multiplexer IC 74508 Quad 2 Input Positive AND Gate IC 7432 Quad 2 Input Positive OR Gate IC 74S02 Quad 2 Input Positive NOR Gate IC Intel 8259A Programmable interrupt Controller SN74125 SN74S32 5 74510 5 745175 9602 5 74511 8226 5 75189 5 75188 5 74163 8224 5 745139 5 74508 5 74504 SN7432 5 74502 8259 N n2 gt 5 1 Service Information iSBC 86 12 Table 5 1 Replaceable Parts Continued 5 2 4 Mfr Reference Designation Description Code 25 Intel 8255A Programmable Peripheral Interface 8255A COML 1 A26 Intel 8253 Programmable Interval Timer 8253 COML 1 27 Intel 8251A Programmable Comm Interface 8251A COML 1 A30 57 74LS75 4 Bit Bistable Latch SN74LS75 2 A31 33 43 52 74500 Quad 2 Input Positive NAND Gate SN74S00 TI 4 A35 84 85 74LS04 Hex Inverters 5 741504 3 A36 7400 Quad 2 Input Positive NAND Gate SN7400 Tl 1 A38 Intel 8284 18 Pin Clock Generator 8284L COML 1 A39 Intel 8086 16 Bit Microprocessor 8086 COML 1 A40 41 71 91 745373 Octal D Type Latches 5 745373 TI 4 A42 44 45 58 60 61 Intel 8286 8 Bit Non Inverting Transceiver 8286 COML 6 A48 7438 Quad 2 Input Positive NAND Gate SN7438 TI 1 A50 63 74874 Dual D type Edge Triggered Flip Flop 5 74574 2 55 74530 8 Input Positive NAND Gate SN74S30 1 56 7
57. Counter 2 Count Register Byte Counter 2 Count Register Byte Counter 0 Count Register Byte PSP Counter 0 Figure 3 10 PIT Programming Sequence Examples Mode 4 Software triggered strobe After this mode is set the output will be high When the count is loaded the counter begins counting On terminal count the output will go low forone input clock period and then go high again If the count register is reloaded be tween output pulses the present count will not be affected but the subsequent period will reflect the new value The count will be inhibited while the gate input is low Reloading the count register will restart the counting for the new value Mode 5 Hardware triggered strobe Counter 0 and or Counter will start counting on the rising edge of the gate input and the output will go low for one clock period when the terminal count is reached The counter 15 retriggerable The output wil not go low until the full count after the rising edge of the gate input Table 3 7 provides a summary of the counter operation versus the gate inputs The gate inputs to Counters 0 and 1 are tied high by default jumpers these gates may option ally be controlled by Port CC The gate input to Counter 2 is not optionally controlled Programming Information Table 3 7 PIT Counter Operation Vs Gate Inputs Low Or Going Disables counting 1 Disables counting 2 Sets output immediately high Signal Statu
58. D or DP WRT to RAM Controller A70 10ZB6 SLAVE CMD EN also gates the subsequently generated RAM XACK to the CPU READY input RAM XACK is generated by the RAM Controller when data has been read from or written into RAM The RAM Controller asserts RAM during P13 and 49 10 goes low on the next rising edge of the clock The bus master then terminates the DP RD or DP WRT signal and the OFF BD CMD signal The RAM controller next terminates RAM and then A49 7 goes high on the next rising edge of the clock At the end of P16 A50 5 goes low and A50 6 goes high terminating the SLAVE signal At the end of P17 A49 14 goes high and terminates the SLA VE CMD EN signal The foregoing discussion pertains only to the operation of the Dual Port Control Logic for Multibus access of the dual port RAM The actual addressing and transfer of data are discussed in paragraph 4 35 4 25 CPU ACCESS TIMING Figure 4 8 illustrates the Dual Port Control Logic timing for dual port RAM access by the on board 8086 CPU P periods PO through P13 are used only for descriptive purposes and have no relationship to the 22 12 MHz clock signal demonstrate that the CPU has priority in the access of the dual port RAM figure 4 8 shows the OFF BD RAM CMD signal active when the CPU access is initiated by the ON BD RQT signal The timing has progressed through PO during which time A49 10 has been clocked high and A
59. D WRITE OPERATION When another bus master has control of the Multibus that bus master can address the iSBC 86 12 as a slave RAM device The bus master first places the address on the Multibus and then asserts MRDC or MWTC Address bits ADRD ADR10 and switch S1 present a 10 bit ad dress to a special ROM A67 3ZB6 address bits ADRD ADR13 are decoded by A66 The switch set tings of S1 represent the base address and memory bus size the O1 O3 outputs of A67 are ATRD ATRF which are multiplexed by A86 5ZC4 into memory dress bits AMC AMF when the SLA VE signal is subsequently activated by the Dual Port Control Logic The O4 output of A67 is driven through A23 4 when the 128K byte matches to develop the OFF BD RAM ADR RQT signal which is applied to the Dual Port Control Logic If no CPU access is in progress the Dual Port Control Logic then enters the slave mode and when Bus Control Data Bus Driver Memory Block Lines Chip Select Chip Select Principles of Operation 49 10 goes low develops the RAMCS and SLAVE CMD EN signals RAMCS enables RAM Controller A70 and SLAVE CMD EN gates DPRD or DPWT to the RAM Controller The RAM Controller then multiplexes the address to RAM and depending on which input com mand is true DPRD or DPWT drives its WE output high or low The WE output is driven low for a write it remains high for a read The SACK and signals are generated by the RAM Control
60. ES END OF INTERRUPT TO NON SPECIFIC EOI When INTR goes active the CPU pertorms the following assuming the Interrupt Flat 1s set a Issues two acknowledge signals upon receipt of the second acknowledge signal the interrupting device master or slave PIC will respond with a one byte interrupt identifier b Pushes the Flag registers onto the stack same as a PUSHF instruction c Clears the Interrupt Flag thereby disabling further maskable interrupts d Multiplies by four 4 the binary value X contained in the one byte identifier from the interrupting device e Transfers control with an indirect call through 4X Upon completion of the service routine the CPU automat ically restores its flags and returns to the main program 3 53 MASTER PIC BYTE IDENTIFIER The mas ter on board PIC responds to the second acknowledge signal from the CPU only if the interrupt request is from a non slaved device i e a device that is connected directly to one of the master PIC IR inuts The master PIC has eight inputs numbered IRO through IR7 which are identified by a 3 bit binary number Thus if an interrupt request occurs on IR5 the master PIC responds to the second acknowledge signal from the CPU by outputting the byte 000001012 05 5 The CPU multiplies this value by four and transfers control with an indirect call through 00010100 141 3 54 SLAVE PIC BYTE IDENTIFIER Each slave PIC is initialized
61. ION When power is applied in a start up sequence the contents of the 8086 CPU program counter program status word interrupt enable flip flop etc are subject to random factors and cannot be predicted For this reason a power up sequence is used to set the CPU Bus Arbiter and I O ports to a known internal state When power is initially applied to the iSBC 86 1X capacitor C26 2ZD6 begins to charge through resistor 9 The charge developed across C26 is sensed by a Schmitt trigger which is internal to Clock Generator A38 The Schmitt trigger converts the slow transition appearing at pin 12 into a clean fast rising synchronized RESET signal at pin 11 The RESET signal is inverted by A48 6 to develop RESET and INIT The RESET signal auto matically sets the 8086 CPU program counter to FFFFO and clears the interrupt enable flip flop resets the parallel ports to the input mode resets the serial port to the idle mode and resets the Bus Arbiter outputs are tristated The INIT signal is transmitted over the Multibus to set the entire system to a known internal state The initialization described above can be performed at any time by inputting a RESET signal via auxiliary connector P2 4 15 CLOCK CIRCUITS The 5 MHz CLK is developed by Clock Generator A38 2ZC6 in conjunction with crystal Y2 This clock is the time base for CPU A39 Status Decoder A81 the Bus Arbiter Assembly and Bus Command Decode
62. IP MAGNET ASSEMBLY J IJ LI LI POWER cano SUPPLY TERMINAL BLOCK TELETYPE MODEL 33TC Figure A 1 Teletype Component Layout Figure A 2 Current Source Resistor Figure A 3 Terminal Block A 2 Teletypewriter Modifications TERMINAL BLOCK 151411 25 EXTERNAL CONNECTOR BLK GRN WHT BRN RED GRN WHT YEL C 2 WHT BLK fies WHT BLU FULL DUPLEX RECEIVE g GRY WHT RED BLK BLK WHT 117V DISTRIBUTOR TRIP CONNECTOR CIRCUIT 1A JR 1005 4 NORMAL CONTACTS MAGNET WIRE A VEL GE BRN 117 VAC eee SX eRs20 COMMON CONTROL SP4B4 0 114 4700 POTTER amp BRUMFIELD RELAY __ ALTERNATE CONTACT PROTECTION 12VDC 600Q COIL x 470 2 OPEN RELAY CIRCUIT CARD MODE SWITCH T 9 1 200v FRONT VIEW WIRE B Figure A 4 Teletypewriter Modifications Figure A 5 Relay Circuit Figure A 6 Mode Switch A 3 Teletypewriter Modifications ERE Figure A 7 Distributor Trip Magnet J1 FROM iSBC 530 TO TERMINAL BLOCK SERIAL IN OUT P3 TTY ADAPTER J3 PORT SEE FIGURES A 3 AND A 4 CINCH 08 255 CINCH DB 25P Figure A 8 TTY Adapter Cabling 5 1 INTRODUCTION This chapter provides a list of replaceable parts service diagrams and service and repair assistance instructions for the iSBC 86 12 Single Board Computer 5 2 REPLACEABLE PARTS Table 5 1 prov
63. K MODE Figure 3 15 PIC Operation Control Word Formats SBC 86 12 Programming Information Table 3 17 Typical PIC Initialization Subroutine NBV Mode jINT59 INITIALIZES THE 64 BYTE ADDRESS BLOCK BEGINNING WITH 00000 IS SET UP FOR INTERRUPT SERVICE ROUTINES MASK IS SET DISABLING ALL PIC INTERRUPTS IS FULLY NESTED MODE NON AUTO EOI 1 5 5 5 SMASK DESTROYS A PUBLIC INT59 EXTRN SETI SMASK INT59 CALL SETI AL 13H OUT OCOH TO PIC MOV AL OOH OUT OC6H 2 TO PIC MOV AL 1DH OUT 0C2H ICW4 PIC MOV AL OFFH CALL SMASK RET END an aa INITIALIZES MASTER WITH SINGE SLAVE ATTACHED THE LEVEL INTERRUPT MASK IS SET WITH ALL PIC INTERRUPTS DISABLED IS FULLY NESTED NON AUTO SUSES SETI SMASK PUBLIC INTMA EXTRN SETI SMASK INTMA CALL SETI AL 11H OUT AL 00H 2 OUT OC2H MOV AL 01H OUT OC2H MOV AL 1DH 4 OUT OC2H MOV AL OFFH CALL SMASK RET END Table 3 20 lists details of the above operations Note that a IRR table 3 21 an End Of Interrupt EOT or a Special End Of Interrupt command is required at the end of each interrupt b Read ISR table 3 22 service routine to reset the ISR The EOI command is used in the fully nes
64. M4 2 M1 MO 1 Mask Set Mask Reset read mask bits read 000 2 The Special Mask Mode enables desired bits that have been previously masked lower priority bits are also enabled To set write 68H to 000CO To reset write 48H to 000 0 If previous operation was addressed to same register it is not necessary to rewrite the OCW Programming Information iSBC 86 12 Table 3 21 Typical PIC Interrupt Request Register Read Subroutine RRO READS PIC INTERRUPT REQUEST USES SETI DESTROYS A PUBLIC RRO EXTRN RRO CALL AL OAH RR INSTRUCTION TO PIC OUT OCOH IN END Table 3 22 Typical PIC In Service Register Read Subroutine RISO READS IN SERVICE REGISTER USES SETI DESTROYS A PUBLIC RISO EXTRN SETI CALL SETI MOV AL 08H RIS INSTRUCTION TO PIC OUT Table 3 23 Typical PIC Set Mask Register Subroutine SMASK STORES REG INTO PIC MASK REG A ONE MASKS OUT AN INTERRUPT A ZERO ENABLES IT USES A SETI DESTROYS NOTHING PUBLIC SMASK EXTRN SETI CALL SETI OUT OC2H RET END Table 3 24 Typical PIC Mask Register Read Subroutine READS PIC MASK REG INTO A REG USES SETI DESTROYS A PUBLIC RMASK EXTRN SETI SETI OC2H 5 86 12 Programming Information Table 3 25 Typical PIC End of Interrupt Command Subroutine USES SETI DE
65. MANUFACTURER AMP Inc CD Mt View CA OBD Order by Description available from any commercial COML source Augat Inc Fairchild Semiconductor Motorola Semiconductor 5 3 5 4
66. PUT SYNC SYNC CHAR 2 DATA CHARACTERS RECEIVE FORMAT SERIAL DATA INPUT RxD SYNC SYNC ATACHA CPU BYTES 5 8 BITS CHAR DATA CHARACTERS Figure 3 3 USART Synchronous Mode Transmission Format iSBC 86 12 D D D D 0 D Dy BAUD RATE FACTOR KERA ie x 6 7 BITS BITS PARITY ENABLE 1 ENABLE 0 DISABLE EVEN PARITY GENERATION CHECK 1 EVEN 0 NUMBER OF STOP BITS ONLY EFFECTS Tx Rx NEVER REQUIRES MORE THAN ONE STOP BIT Figure 3 4 USART Asynchronous Mode Instruction Word Format 3 10 SYNC CHARACTERS Sync characters are written to the USART in the syn chronous mode only The USART can be programmed to either one or two sync characters the format of the sync characters is at the option of the programmer 3 11 COMMAND INSTRUCTION FORMAT The Command instruction word shown in figure 3 6 con trols the operation of the addressed USART A Command instruction must follow the mode and or sync words Once the Command instruction is written data can be transmitted or received by the USART lt is not necessary for a Command instruction to precede all data transactions only those transmissions that require a change in the Command instruction An example is a change in the enable transmit or enable receive bus Command instructions can be written to the USART at any time after one or more data operations After initialization always
67. Read or Memory Write Command is given must wait for a Transfer Acknowledge XACK to be received from the addressed memory device The Failsafe Timer if enabled will prevent a CPU hang up in the event of a memory device equipment failure or a bus failure It should be noted in table 3 1 that it is possible to config ure ROM EPROM such as to create addresses If an illegal address is used in conjunction with a Memory Write Command to ROM EPROM an internal acknowl edge signal is generated as though the address was legal and the CPU will continue executing the program How ever in this case erroneous data will be returned 3 1 Programming Information iSBC 86 12 Table 3 1 On Board Memory Addresses CPU Access Configuration EPROM 3 5 MULTIBUS ACCESS Two 2758 chips Four 2758 chips Two 2716 chips Four 2716 chips Two 2316E chips Four 2316E chips Two 2332 chips Four 2332 chips Sixteen 2117 chips As described in paragraph 2 12 the iSBC 86 12 can be configured to permit Multibus access of 8K 16K 24K or 32K bytes of on board RAM The Multibus allows both 8 bit and 16 bit masters to reside in the same system and to accomplish this the memory is divided into two 8 bit data banks to form one 16 bit word The banks are organized such that all even bytes are in one bank DATO DAT7 and all odd bytes are in the other bank DAT8 DATF The Byte High Enable BHEN signal controls the odd d
68. STROYS A PUBLIC SETI CALL SEJ MOV A 20H QUT OCOH RET END 3 50 HARDWARE INTERRUPTS The 8086 CPU includes two hardware interrupts inputs NMI and INTR classified as non maskable and mask able respectively 3 51 NON MASKABLE INTERRUPT NMI The NMI input has the higher priority of the two interrupt inputs A low to high transition on the NMI input will be serviced at the end of the current instruction or between whole moves of a block type instruction Worst case re sponse to NMI is during a multiply divide or variable shift instruction When the NMI input goes active the CPU performs the following a Pushes the Flag registers onto the stack same as a instruction b If not already clear clears the Interrupt Flag same as a CLI instruction this disables maskable interrupt c Transfers control with an indirect call through 00008 The NMI input is intended only for catastrophic error handling such as a system power failure Upon comple tion of the service routine the CPU automatically restores the flags and returns to the main program 3 52 MASKABLE INTERRUPT INTR The INTR input has the lower priority of the two interrupt inputs high level on the INTR input will be serviced at the end of the current instruction or at the end of a whole move for a block type instruction n n Y Q n DS r y _ WT ISSU
69. T 0 OUTPUT Default jumpers set the Port A bidirectional data buffers to the input mode Optional jumpers allow the bidirectional data buffers to be set to the output mode or allow any one of the eight Port C bits to selective set the Port A bidirec tional data buffers to the input or output mode PORT B 1 0 OUTPUT MODE SELECTION 0 MODE 1 MODE 1 Table 2 11 lists the various operating modes for the three PPI parallel I O ports Note that Port A C8 can be operated in Modes 0 1 or 2 Port B CA and Port C CC can be operated in Mode 0 or 1 GROUP A PORT UPPER 1 INPUT 0 OUTPUT 3 30 CONTROL WORD FORMAT The control word format shown in figure 3 12 is used to initialize the PPI to define the operating mode of the three ports Note that the ports are separated into two groups Group A control word bits 3 through 6 defines the operating mode for Port A C8 and the upper four bits of Port C CC Group B control word bits 0 through 2 defines the operating mode for Port B CA and the lower four bits of Port C CC Bit 7 of the control word controls the mode set flag PORTA 1 0 MODE SELECTION 00 MODE 0 01 MODE 1 1X MODE 2 MODE SET FLAG 1 ACTIVE 3 31 ADDRESSING The PPI uses four consecutive even addresses 000 8 Figure 3 12 PPI Control Word Format through OOOCE for data transfer obtaining the status of Port C CC and
70. T OPERATION DESTROYS A PUBLIC MOV OUT MOV OUT MOV OUT INTTMR AL 30H OD6H AL 70H OD6H AL B6H OD6H RET END CONTROL WORD FOR COUNTER 0 CONTROL WORD FOR COUNTER 1 CONTROL WORD FOR COUNTER 2 Table 3 9 Typical PIT Count Value Load Subroutine LOADO LOADS COUNTER 0 FROM D amp E D IS MSB E IS LSB USES D E DESTROYS A PUBLIC MOV OUT MOV OUT RET AL EL AL DL ODOH END LOADO LSB MSB iSBC 86 12 sure to enter downcount in two bytes if the counter was programmed for a two byte entry in the mode control word Similarly enter the downcount value in BCD if the counter was so programmed d Repeat steps b c and d for Counters and 2 3 22 OPERATION The following paragraphs describe operating procedures for a counter read clock frequency divide ratio selection and interrupt timer counter selection 3 23 COUNTER READ There are two methods that can be used to read the contents of a particular counter The first method involves a simple read of the desired counter The only requirement with this method is that in order to ensure stable count reading the desired counter must be inhibited by controlling its gate input Only Counter 0 and Counter can be read using this method because the gate input to Counter 2 is not controllable The second method allows the counter to be read
71. Y 000DA SYNC CHARACTER 2 000DA COMMAND INSTRUCTION 000D8 DATA 1 0 0000 COMMAND INSTRUCTION 00008 DATA 1 0 0000A COMMAND INSTRUCTION The second sync character is skipped if Mode instruction has programmed USART to single character internal sync mode Both sync characters are skipped if Mode instruction has programmed USART to async mode Figure 3 7 Typical USART Initialization 645 5 and Data I O Sequence To avoid spurious interrupts during USART initialization disable the USART interrupt This can be done by either masking the appropriate interrupt request input at the 8259A PIC or by disabling the 8086 microprocessor inter rupts by executing DI instruction First reset the USART chip by writing a Command in struction to location 000DA or 000DE The Command instruction must have bit 6 set IR 1 all other bits are immaterial NOTE This reset procedure should be used only if the USART has been completely initialized or the initialization procedure has reached the point that the USART is ready to receive a Command word For example if the reset command is written when the initialization sequence calls for a sync character then subsequent program ming will be in error Next write a Mode instruction word to the USART See figures 3 2 through 3 5 A typical subroutine for writing both Mode and Command instructions is given in table 3 3 If the USART is programmed for the synchronous mode write one
72. ad or write starts the RAM Controller drives its SACK output low when the memory cycle is complete it drives its XACK output low The SACK and XACK go high when the RD or WR input goes high 4 33 RAM CHIPS Even bytes of data are stored in A72 A79 and odd bytes of data are stored in A92 A99 The WE input pin to A72 A79 is controlled by ANDing the RAM Controller WE output and memory address bit AMO The WE input pin to A92 A99 is controlled by ANDing the RAM Controller WE output AMO and MBHEN Memory Byte High Enable 4 34 ON BOARD READ WRITE OPERATION When the 04 output of A68 6ZB6 and address bit AB13 are both low the output of A53 6 goes low and asserts the ON BD RQT signal When ON BD RAM RQT goes low A52 3 117 3 is enabled and generates ON BD CMD EN to generate RAMCS via A52 11 and to gate DPRD or DRWT to the RAM Controller See Figure 4 8 The RAM Controller then multiplexes the address to RAM and depending on which input command it true DPRD or DPWT drives its WE output high or low The WE output is driven low for a write it remains high for a read The SACK and signals are generated by the RAM Controller as described in paragraph 4 33 The CPU completes the read or write operation when is asserted During the CPU access of on board RAM the Address Bus Drivers and Data Bus Drivers are disabled and the Address Buffer and Data Buffer are enabled 4 35 BUS REA
73. ata byte and when active enables the high byte DAT8 DATF onto the Multibus Address bit ADRO controls the even data byte and when active enables the low byte DATO DAT7 onto the Multibus For maximum efficiency 16 bit word operations must occur on an even byte boundary with BHEN active Address bit is active for all even byte addresses Odd byte addressing requires two operations to form a 16 bit word Byte operations can occur in two ways The even byte can be accessed by controlling ADRO which places the data on the DATO DAT7 lines See figure 3 1A To access the odd data bank which normally is placed on the DATS8 DATF lines new data path is defined The Inactive state of ADRO and enable a swap byte buffer that places the odd data bank on DATO DAT7 See figure 3 1B This permits an 8 bit bus master to access both bytes of a data word by controlling only ADRO Figure 3 1C illustrates how a 16 bit bus master obtains a 16 bit word by a single address on an even byte boundary Figure 3 1A illustrates how a 16 bit bus master may selectively address an even low data byte 3 2 Legal Addresses illegal Addresses FF800 FFFFF FFOOO FF7FF FFOOO FFFFF FFOOO FFFFF FEO000 FEFFF FEO00 FFFFF FFOOO FFFFF 000 FEOOO FFFFF S 0000 07FFF poe FEO00 FFFFF FCO00 FDFFF FCOO0 FFFFF USED BY MASTERS MEMORY BLOCKS MEMORY BLOCKS MEMORY BLOCKS Figure
74. ated jumper post 6 IRO is highest priority IR7 is lowest priority 7 Default jumper 87 89 disables grounds input The NMI input is highest priority non maskable and is both level and edge sensitive 8 INTR is connected directly to output of 8259A PIC 9 Used to generate an interrupt on Muitibus External Via 41 50 Power Fail Logic Via P2 19 Failsafe Timer 8255A PPI Port A Port C8 Port B Port CA Any Unused Bit EXT INTO TIME OUT INTR 1 PA INTR 1 PB INTR 1 BUS INTR OUT 3 9 8251A USART Trans Buffer Empty Rec Buffer Empty 51TX INTR 1 51RX INTR 8253 PIT Timer 0 Out Timer 1 Out TMRO INTR 1 1 INTR 1 90 82 83 91 NOTES 1 Signal is positive true at associated jumper post 2 INTO is highest priority INT7 is lowest priority 3 Signal is ground true at associated jumper post 4 Requires ground true signal at associated jumper post dp rl CE M CLE E LE cue AU 8086 porai WIR CPU PIC 1 81 70 0 0 K INTR 80 lt 79 7 78 SLAVE Oe P nds Ju INPUTS FROM d oF gt 76 INTERRUPT e SOURCES A INTR 75 74 16 BUS BV INTERRUPT SOURCES Mec
75. ation Command Words ICW s shown in figure 3 14 first Initialization Command Word ICW1 which is required in all modes of operation consists of the following a Bits 0 and 4 are both 175 and identify the word is ICW1 for an 8086 CPU operation b Bit 1 denotes whether or not the PIC is employed in a multiple PIC configuration In other words code bit 1 if no slave PIC s is interfaced to the master PIC via the Multibus iSBC 86 12 Bits 2 5 6 and 7 don t care and are normally coded as 0 s d 3 establishes whether the interrupts are requested by a positive true level intput or requested by a low to high transition input This applies to all input re quests handled by the PIC In other words if bit 3 1 a low to high transition is required to request an interrupt on any of the eight levels handled by the PIC The second Initialization Command Word IC W2 which is also required in all modes of operation consists of the following a For programming the master PIC write OOH in ICW2 Although in this case ICW2 conveys no in formation it is required to prepare the master PIC for either ICW3 or ICWA or both to follow ICW1 D7 D6 D5 D4 02 D1 TII ICw2 07 06 05 04 03 02 D1 DO SLAVE ID ICW3 07 06 05 D4 03 02 D1 00 R INPUT 15 SLAVE R INPUT IS NOT SLAVE 4 07 06 05 04 03 02 01 00 THIS PIC IS MASTER THIS PIC IS SLAVE FULLY NESTED
76. ations and the effects on transceiver control and memory block chip select ee ee ee 1 1 Off Yes 1 0 on ve 0 1 On On Off Yes Yes 0 0 Yes Principles of Operation 4 37 INTERRUPT OPERATION The 8259A PIC can support both bus vectored BV and non bus vectored NBV interrupts For both BV and NBV interrupts the on board PIC A24 8ZB6 serves as the master PIC Refer to paragraph 2 13 The master PIC drives the CPU INTR input high to initiate an inter rupt request and the CPU then enters the interrupt timing cycle in which two INTA cycles occur back to back The NBV and BV interrupts are described in following paragraphs 4 38 NBV INTERRUPT Assume that a NBV inter rupt is initiated by an on board function driving the IR5 line high to the on board PIC if no higher interrupt is in progress the PIC then drives the CPU INTR input high Assuming that the NMI interrupt is inactive and that the CPU interrupt enable flip flop is set the CPU suspends the current operation and proceeds with the first of two back to back INTA cycles Refer to figure 4 6 for sig nals activated during the first and subsequent INTA cycle The Bus Arbiter acquires control of the Multibus and the MCE signal drives the LOCK signal low to ensure Mul tibus control until the second INTA cycle is complete The Bus Command Decoder drives the INTA signal low On receipt of the first INTA signal the master PIC
77. ble be sure that the cable makes contact with pins 1 and 2 of the mating connector and not with pin 26 Table 2 17 provides pin correspondence between connector J2 and an RS232C connector When attaching the cable to J2 be sure that the PC connector is oriented properly with respect to pin 1 on the edge connector Refer to the footnote in table 2 6 2 23 BOARD INSTALLATION Always turn off the computer system power supply before installing or removing the ISBC 86 12 board and before installing or 2 23 Preparation for Use iSBC 86 12 Table 2 16 Parallel I O Signal Connector J1 DC Characteristics Si Parameter Test Description Conditions Port C8 Output Low Voltage lou 20 mA Bidirectional Output High Voltage 12 5 Input Low Voltage Input High Voltage Input Current at Low V Capacitive Load ViN 0 45 8255 Driver Receiver Output Low Voltage Output High Voltage Input Low Voltage Input High Voltage Input Current at Low V Input Current at High V Capacitive Load EXT INTRO Input Low Voltage Input High Voltage Input Current at Low V Input Current at High V Capacitive Load Capacitive load values are approximations removing device interface cables Failure to take NOTE these precautions can result in to board Inspect the modular backplane and cardcage and ensure that pull up registors hav
78. bus after each command is executed The bus lock condition 15 invoked by driving the Bus Arbiter LOCK input low in one of two ways a By executing a software LOCK XCNG command b By clearing an option bit via I O Port CC During an interrupt from the 8259A PIC the LOCK input is automatically driven low by the first of two INTA signals issued by Status Decoder 81 Refer to paragraphs 4 37 through 4 39 4 27 OPERATION The following paragraphs describe on board and system I O operations The actual functions performed by specific read and write commands to on board devices are described in Chapter 3 4 28 ON BOARD OPERATION Address bits are applied to the I O Address Decoder com posed of A54 55 56 67 7 The ADV ADR signal is developed by flip flop A63 5 2ZA2 when the ALE signal latches the CPU inverted S2 signal When ADV I O ADR is true the Address Decoder develops IO AACK when are false AB6 AB7 are true Principles of Uperation and ABS is either true or false The I O AACK signal enables decoder A54 which then decodes AB3 AB4 The I O AACK signal also drives the CPU READY input high Assuming AB8 ABF are false AB3 AB7 de coded to generate the following chip select signals Bits Chip Select CO C2 8259 5 CA CC 8255 5 DO D2 D4 06 8253CS D8 DA DC DE 8251CS Odd address i e C1
79. cessing capacity and the benefits of multiprocessing i e several CPU s and or controllers logically sharing systems tasks with com munication over the Multibus the iSBC 86 12 provides full bus arbitration control logic This control logic allows up to three bus masters e g combination of iSBC 86 12 DMA controller diskette controller etc to share the Multibus in serial daisy chain fashion or up to 16 bus masters to share the Multibus using an external parallel priority resolving network The Multibus arbitration logic operates synchronously with the bus clock which is derived either from the iSBC 86 12 or can be optionally generated by some other bus master Data however is transferred via a handshake between the controlling master and the addressed slave module This arrangement allows different speed control General Information lers to share resources on the same bus and transfers via the bus proceed asynchronously Thus the transfer speed is dependent on transmitting and receiving devices only This design prevents slower master modules from being handicapped in their attempts to gain control of the bus but does not restrict the speed at which faster modules can transfer data via the same bus The most obvious applica tions for the master slave capabilities of the bus are mul tiprocessor configurations high speed direct memory access DMA operations and high speed peripheral control but are by no means limited to
80. ct this lead to 1450 ohm tap Refer to figures and A 2 b On terminal block change two wires as follows to create an internal full duplex loop refer to figures and 3 1 Remove brown yellow lead from terminal 3 reconnect this lead to terminal 5 2 Remove white blue lead from terminal 4 reconnect this lead to terminal 5 c On terminal block remove violet lead from terminal 8 reconnect this lead to terminal 9 This changes the receiver current level from 60 mA to 20 mA A relay circuit card must be fabricated and connected to the paper tape reader driver circuit The relay cir cuit card to be fabricated requires a relay a diode a thyractor a small vector board for mounting the components and suitable hardware for mounting the assembled relay card A circuit diagram of the relay circuit card is included in figure A 4 this diagram also includes the part numbers of the relay diode and thyractor Note that a 470 ohm resistor and a 0 1 uF capacitor may be TELETYPEWRITER MODIFICATIONS APPENDIX A substituted for the thyractor After the relay circuit card has been assembled mount it in position as shown in figure A 5 Secure the card to the base plate using two self tapping screws Connect the relay cir cuit to the distributor trip magnet and mode switch as follows a Refer to figure A 4 and connect a wire Wire A from relay circuit card to terminal L2 on mode switch
81. cycle is similar to a read cycle The basic difference is that an INTA signal is asserted instead of an MRDC or IORC signal and the address bus is floated In the second 4 5 Principles of Operation ISBC 86 487 T1 5 MHZ CLK 2 51 SO it y VALID BHEN AD16 AD19 ALE ADDRESS iJ ADO AD15 DEN AMWT AIOWC MWTC IOWC NOTES 1 INTA IORC MRDC DT R 2 FLOATS ONLY IF ENTERING A HOLD CONDITION DENOTES CPU INPUT OR OUTPUT DENOTES STATUS DECODER A81 OUTPUT T3 T4 gt FLOAT 645 11 Figure 4 5 CPU Write Timing INTA cycle a byte of information supplied by the 8259A is read from data lines ADO AD7 This byte which identifies the interrupting source is multiplied by four by the CPU and used as a pointer into an interrupt vector look up table 4 19 ADDRESS BUS The address bus is shown in weighted lines in figures 4 and 4 2 The 20 bit address ADO AD19 is output by CPU A39 during the first clock cycle T1 of the memory or I O instruction The trailing edge of the Address Latch Enable ALE signal output by Status Decoder A81 dur ing strobes and latches the address into Latch A40 41 57 The latched address is distributed as follows a AB3 ABF to I O Address Decoder A54 55 56 67 7 b ABB ABI3 to PROM Address Decode Logic A18 68 6ZB6 4 6 c ABI ABC PROM A
82. d because of damage sustained during shipment from Intel or if the product 18 out of warranty a purchase order is necessary in order for the MCD Technical Support Center to initiate the repair In preparing the product for shipment to the MCD Techni cal Support Center use the original factory packaging material if available If the original packaging is not available wrap the product in a cushioning material such as Air Cap TH 240 or equivalent manufactured by the Sealed Air Corporation Hawthorne N J and enclose in a heavy duty corrugated shipping carton Seal the carton securely mark it FRAGILE to ensure careful han dling and ship it to the address specified by MCD Techni cal Support Center personnel NOTE Customers outside of the United States should con tact their sales source Intel Sales Office or Au thorized Intel Distributor for directions on obtain ing service or repair assistance Table 5 1 Replaceable Parts Reference Designation 1 37 62 2 21 53 7 75188 Quad Line Drivers 74163 Sync 4 Bit Counter IC 74504 Hex Inverters Description 74125 Quad Bus Buffer 3 state 74532 Quad 2 Input Positive OR Gate IC 74810 Triple 3 Input Positive NAND Gate IC 748175 Hex Quad D Type Flip Flop IC 9602 Dual One Shot Multivibrator IC 74511 Triple 3 Input Positive AND Gate IC Intel 8226 4 Bit Bidirectional Bus Driver 75189 Quad Line Receivers I
83. e been included Table 2 17 Connector J2 Vs RS232C for pins 27 28 30 32 33 and 34 Earlier Pin Correspondence backplanes did not include pull ups on these pins In an iSBC 80 Single Board Computer based system install the iSBC 86 12 in any slot that has not beep wired for a dedicated function In an Int llec System install the iSBC 86 12 in any odd numbered slot except slot 1 If another module in the Intellec System is to supply the BCLK and CCLK signals disconnect 105 106 and 103 104 jumpers on the iSBC 86 12 Make sure that auxiliary connector P2 if used mates with the user installed mating connector Attach the appropriate cable assemblies to connectors J1 and J2 2 24 3 1 INTRODUCTION This chapter lists the dual port ROM EPRON and I O address assignments describes the effects of a hardware initialization power up and reset and pro vides programming information for the following pro grammable chips a Intel 8251A USART Universal Synchronous Asyn chronous Receiver Transmitter that controls the serial I O port b Intel 8253 PIT Programmable Interval Timer that controls various frequency and timing functions c Intel 8255A PPI Programmable Peripheral Inter face that controls the three parallel I O ports d Intel 8259A PIC Programmable Interrupt Con troller that can handle up to 64 vectored priority interrupts for the on board microprocessor This chapter also discusse
84. e intended for Multibus access of the dual port RAM must not cross a 128K boundary If it is desired to reserve all the dual port RAM strictly for local CPU access connect jumper 112 114 2 13 PRIORITY INTERRUPTS Table 2 5 lists the source from and destination to of the priority interrupt jumper matrix shown in figure 5 2 sheet 8 The INTR output of the on board Intel 8259A Pro grammable Interrupt Controller PIC is applied directly to the INTR input of the 8086 CPU The on board PIC which handles up to eight vectofed priority interrupts provides the capability to expand the number of priority interrupts by cascading each interrupt line with another 8259A PIC Figure 2 2 shows as an example the on board PIC master with two slave PIC s interfaced by the Multi bus This arrangement leaves the master PIC with six inputs IR2 through IR that can be used to handle the various on board interrupt functions The master slave PIC arrangement illustrated in figure 2 2 is implemented by programming the master PIC to handle IRO and as bus vectored interrupt inputs For example if the Multibus INT3 line is driven low by slave PIC 1 the master PIC will let slave PIC 1 send the restart address to the 8086 CPU Each interrupt input through to the master PIC can be individually programmed to be a non bus vectored iSBC 86 12 Preparation for Use C exe os X PARAMETER 119 120 121
85. ed by a programmable baud rate time generator These clocks may optionally be supplied from an external source The RS232C command lines serial data lines and signal ground lines are brought out to a 50 pin edge connector J2 that mates with flat or round cable Three independent fully programmable 16 bit interval timer event counters are provided by an Intel 8253 Pro _ grammable Interval Timer PIT Each counter is capable of operating in either BCD or binary modes two of these counters are available to the systems designer to generate accurate time intervals under software control Routing for the outputs and gate trigger inputs of two of these counters may be independently routed to the 8259A Prog rammable Interrupt Controller PIC The gate trigger in puts of the two counters may be routed to I O terminators associated with the 8255A PPI or as input connections from the 8255A PPI The third counter is used as a programmable baud rate generator for the serial I O port In utilizing the iSBC 86 12 the systems designer simply configures via software each counter independently to meet system requirements Whenever a given time delay or count is needed software commands to the 8253 PIT select the desired function The contents of each counter may be read at any time during system operation with simple operations for event counting applications and special commands are included so that the contents of each counter be
86. eived a char acter on its serial input and is ready to transfer it to the CPU FRAMING ERROR ASYNC DNLY FE flag is set when a valid stop bitis not detected at end of every character It is is reset by ER hit of Command instruc tion FE does not inhibit operaton of 8251 TRANSMITTER EMPTY Indicates that parallel to serial con verter in transmitter is empty PARITY ERROR PE flag is set when a parity error is detected It is reset by ER bit of Com SYNC DETECT When set for internal sync detect indi cates that character sync has been ach eved and 8251 is ready for data mand instruction PE does not inhibit operation of 8251 DATA SET READY DSR is genera purpose Normally used to test modem conditions such as Data Set Ready 450 14 Figure 3 8 USART Status Read Format 3 Read or load least significant byte only 4 Read or load least significant byte first then most significant byte d Sets counter for either binary or BCD count The mode control word and the count register bytes for any given counter must be entered in the following sequence a Mode control word b Least significant count register byte Most significant count register byte As long as the above procedure is followed for each counter the chip can be programmed in any convenient sequence For example mode control words can be loaded first into each of three counters per chip followed by the least signi
87. erations The Multibus interface includes the Bus Arbiter Assembly Bus Command Decoder 83 bidirectional address bus and data bus drivers and interrupt drivers and receivers The Bus Arbiter allows the iSBC 86 12 to operate as a bus masters in the system in which the 8086 CPU can request the Multibus when a bus resource is needed The Bus Arbiter Assembly mounts on the iSBC 86 12 and is electrically interfaced to the board via connector J12 4 13 CIRCUIT ANALYSIS The schematic diagram for the iSBC 86 12 is given in figure 5 2 The schematic diagram consists of 11 sheets each of which includes grid coordinates Signals that traverse from one sheet to another are assigned grid coordinates at both the signal source and signal des tination For example the grid coordinates 2ZB1 locate a signal source or signal destination as the case may be on sheet 2 Zone Both active high active low signals used A signal mnemonic that ends with a virgule e g DAT7 denotes that the signal is active low 0 4 Conversely a signal mnemonic without a virgule e g ALE denotes that the signal is active high 2 0V Figures 4 and 4 2 at the end of this chapter are simplified logic diagrams of the input output interrupt and memory sections These diagrams will be helpful in understanding both the addressing scheme and the in ternal bus structure of the board 4 3 Principles of Operation 4 14 INITIALIZAT
88. ese two bytes can be programmed at any time following the mode control word as long as the correct number of bytes is loaded in order The count mode selected the control word controls the counter output As shown in figure 3 9 the PIT chip can operate in any of six modes Mode 0 Interrupt on terminal count In this mode Counters and 2 can be used for auxiliary functions such as generating real time interrupt intervals After 3 10 the count value is loaded into the count register the counter output goes low and remains low until the terminal count is reached The output then goes high until either the count register or the mode control register is reloaded b Mode 1 Programmable one shot In this mode the output of Counter 1 and or Counter 2 will go low on the count following the rising edge of the GATE input from Port CC assuming Port CC jumpers are so configured The output will go high on the terminal count If a new count value is loaded while the output is low it will not affect the duration of the one shot pulse until the succeeding trigger The current count can be read at any time without affecting the iSBC 86 12 450 18 PROGRAMMING FORMAT Mode Control Word Counter n Count Register Byte Counter n Count Register Byte Counter n one shot pulse The one shot is retriggerable hence the output will remain low for the full count after any ri
89. ficant byte etc Figure 3 10 shows the two programming sequences described above Since all counters in the PIT chip are downcounters the value loaded in the count registers is decremented Load ing all zeroes into a count register results in a maximum count of 216 for binary numbers of 10 for BCD numbers Table 3 6 Typical USART Status Read Subroutine nT Is TF READS STATUS FROM USART DESTROYS A PUBLIC STATO STATO IN ODEH RET END STATUS 3 9 Programming Information iSBC 86 12 07 Dg 05 04 03 02 01 Do BINARY BCD Binary Counter 16 bits Binary Coded Decimal BCD Counter 4 Decades SC1 RL1 Read Load most significant byte only Read Load least significant byte only 1 1 Read Load least significant byte first then most significant byte amp Use Mode 3 for Baud Rate Generator RLO X READ LOAD Counter Latching operation refer to paragraph 3 29 SCO SELECT COUNTER 0 0 SeldCounterO 0 1 1 o Select Counter 1 611 7 Figure 3 9 PIT Mode Control Word Format When a selected count register is to be loaded it must be loaded with the number of bytes programmed in the mode control word One or two bytes can be loaded depending on the appropriate down count Th
90. g dled eed aed RID 4 8 Multibus interface 4 11 uos doen PR S SCR LES beds 4 11 On Board Operation 4 11 System I O 4 12 ROM EPROM Operation 4 12 CONTENTS Continued PAGE KAV Operation nce uu dee 4 12 RAM COnlroller os XS EA Shan neret 4 12 SAND CDS eta wea ease eee died 4 13 On Board Read Write Operation 4 13 Bus Read Write Operation 4 13 Byte Operation 4 13 Interrupt Operation Rr 4 14 NBV UD the oou a adl nate wie Sed a 4 14 Dv IBntenmupbu verte tert uwa 4 14 CHAPTER 5 SERVICE INFORMATION Ent FoU DOG o donee oe ord a ep 5 1 Replaceable s su 5 1 Service Diagrams 5 1 Service and Repair Assistance 5 1 APPENDIX TELETYPEWRITER MODIFICATIONS t t CON CA 2 t2 GO lt TITLE PAGE SPEC HICAUONS 1 4 User Furnished and Installed Components 2 2 User Furnished Connector Details 2 3 Line Driver and I O
91. gate control lines bus override strobed port interrupts and one Multibus interrupt 4 8 INTERRUPT CONTROLLER The 8259A Programmable Interrupt Controller PIC handles up to eight vectored priority interrupts The 8259A PIC provides the capability to expand the number of priority interrupts by cascading each interrupt line with another 8259A PIC Refer to figure 2 2 This is done by programming the master PIC the one on the iSBC 86 12 that an interrupt line e g IR3 is connected to a slave PIC the one interfaced to the master PIC via the Multibus If an IR3 interrupt is sensed by the master PIC it will allow the slave PIC to send the restart vector address to the CPU Each interrupt line into the master PIC can be individually programmed to be a non bus vectored NB V interrupt line master PIC generates the restart address or a bus vectored BV interrupt cascaded to a slave PIC which generates the restart ad dress The iSBC 86 12 can handle eight on board or single Multibus interrupt lines an interrupt line which does not have a slave PIC connected to it or with the aid of eight slave PIC s expand the number of inter rupts to 64 All 64 interrupts must be processed through the slave PIC s and must therefore be external to the iSBC 86 12 There are nine jumper selectable interrupt sources serial port 2 parallel I O interface 2 timers 2 ex ternal via 1 power fail 1 and Multibus time out 1
92. holes c Install a flat washer lock washer and star type nut on each screw then tighten the nuts When the mating connector for P2 is in place wire the power fail signals to the appropriate pins of the connector as listed in table 2 13 The dc characteristics of the signals interfaced via P2 are given in table 2 14 In a typical system these signals would be wired as follows a Connect auxiliary signal common and returns for 5V 5 and 12V backup batteries to P2 pins 1 2 21 and 22 2 13 Preparation for Use O O e ADR10 Q N SRB ADR11 CCLK ADR12 INTA ADR13 INT6 INT7 INT4 INT5 INT2 INT3 INTO INT 1 ADRE a 2 CBRQ Table 2 8 Multibus Connector P1 Pin Assignments Power input Ground Bus Clock System Initialize Bus Priority In Bus Priority Out Bus Busy Bus Request Memory Read Command Memory Write Command Read Command Write Command Transfer Acknowledge Inhibit RAM Byte High Enable Address bus bit 10 Common Bus Request Address bus bit 11 Constant Clock Address bus bit 12 Interrupt Acknowledge Address bus bit 13 Interrupt request on level 6 Interrupt request on level 7 Interrupt request on level 4 Interrupt request on level 5 Interrupt request on level 2 interrupt request on level
93. iSBC 86 12 CONTROL WORD 0j0 0jo 1 1 1 1182 BIT SET RESET FLAG Q ACTIVE Figure 3 13 PPI Port C Bit Set Reset Control Word Format 3 36 8259A PIC PROGRAMMING The on board master 8259A PIC handles up to eight vectored priority interrupts and has the capability of ex panding the number priority interrupts by cascading one or more of its interrupt input lines with slave 8259A PIC s Refer to paragraph 2 13 The basic functions of the PIC are to 1 resolve the prionty of interrupt requests 2 issue a single interrupt request to the CPU based on that priority and 3 send the CPU a vectored restart address for servicing the interrupt ing device 3 37 INTERRUPT PRIORITY MODES The PIC can be programmed to operate in one of the following modes Nested Mode Fully Nested Mode Automatic Rotating Mode Specific Rotating Mode Special Mask Mode Poll Mode Qo gd P 3 38 NESTED MODE In this mode the PIC input signals are assigned a priority from 0 through 7 The PIC operates in this mode unless specifically programmed otherwise Interrupt IRO has the highest priority and IR7 has the lowest priority When an interrupt is acknow ledged the highest priority request is available to the Programming Information CPU Lower priority interrupts are inhibited higher prior ity interrupts will be able to generate an interrupt that will be acknowledged if the CPU has enabled its own interrupt
94. iSBC 86 12 SINGLE BOARD COMPUTER HARDWARE REFERENCE MANUAL Manual Order Number 9800645A Copyright C 197 Intel Corporation Intel Corporation 3065 Bowers Avenue Santa Clara California 95051 il The information in this manual is subject to change without notice Intel Corporation makes no warranty of any kind with regard to this manual including but not limited to the implied warranties of merchantability and fitness for a particular purpose Intel Corporation assumes no responsibility for any errors that may appear in this manual Intel Corporation makes no commitment to update nor to keep current the information contained in this manual No part of this manual may be copied or reproduced in any form or by any means without the prior written consent of Intel Corporation The following are trademarks of Intel Corporation and may be used only to describe Inte products 30 iSBC MULTIBUS 80 LIBRARY MANAGER PROMPT INSITE MCS UPI INTEL MEGACHASSIS RMX INTELLEC MICROMAP PREFACE This manual provides general information installation programming information principles of operation and service information for the Intel iSBC 86 12 Single Board Computer Additional information is available in the following documents 8086 Assembly Language Reference Manual Order No 9800640 Intel MCS 85 User s Manual Order Nc 98 366 Intel 82554 Programmable Peripheral interface Application Note AP 15 Intel 8251 Un
95. ides a list of replaceable parts for the iSBC 86 12 Table 5 2 identifies and locates the manufacturers specified in the MFR CODE column in table 5 1 Intel parts that are available on the open market are listed in the MFR CODE column as COML every effort should be made to procure these parts from a local commercial distributor 5 3 SERVICE DIAGRAMS The iSBC 86 12 parts location diagram and schematic diagram are provided in figures 5 1 and 5 2 respectively On the schematic diagram a signal mnemonic that ends with a slash e g IOWC is active low Conversely a signal mnemonic without a slash e g INTR is active high 5 4 SERVICE AND REPAIR ASSISTANCE United States customers can obtain service and repair assistance from Intel by contacting the MCD Technical Support Center in Santa Clara California at one of the following numbers CHAPTER 5 SERVICE INFORMATION Telephone From Alaska or Hawaii call 408 987 8080 From locations within California call toll free 800 672 3507 From all other U S locations call toll free 800 538 8014 TWX 910 338 0026 TELEX 34 6372 Always contact the MCD Technical Support Center be fore returning a product to Intel for service or repair You will be given a Repair Authorization Number ship ping instructions and other important information which will help Intel provide you with fast efficient service If the product is being returne
96. igurations IC sockets are provided for interchangeable I O line drivers and terminators Hence the flexibility of the parallel I O interface is further enhanced by the capability of selecting the appropriate combination of optional line drivers and terminators to provide the required sink current polarity and drive termination characteristics for each application The 24 programmable lines and signal ground lines are brought out to a 50 pin edge connector JT that mates with flat woven or round cable The RS232C compatible serial port is controlled and interfaced by an Intel 8251 USART Universal Syncronous Asynchronous Receiver Transmitter chip The USART is individually programmable for operation in most synchronous or asynchronous serial data trans mission formats including In the synchronous mode the following are programma ble a Character length b Sync character or characters and c Parity 1 2 iSBC 86 12 In the asynchronous mode the following are program mable a Character length b Baudrate factor clock divide ratios of 1 16 or 64 Stop bits and d Panty In both the synchronous and asychronous modes the serial I O port features half or full duplex double buf fered transmit and receive capability In addition USART error detection circuits can check for parity overrun and framing errors The USART transmit and receive clock rates are suppli
97. in with the assertion of the ALE signal and the emission of the address Refer to figure 4 5 The trailing edge of ALE latches the address into the address latch as described for a write cycle The DT R signal remains high throughout the entire read cycle to set up the data buffers and data bus buffers for a CPU write operation Status Decoder A81 provides two types of write strobe signals advanced AMWT and AIOWC and nornal MWTC and IOWC As shown in figure 4 5 the advanced memory and I O write strobes are Issued one clock cycle earlier than the normal memory and I O write strobes The iSBC 86 12 doesn t use advanced write strobe AIOWC At the beginning of 2 the advance write and DEN signals are asserted and the ADO ADIS lines of the local bus are switched to the mode The DEN signal enables the data buffers The CPU then places the data on the ADO ADIS lines and at the beginning of T3 the normal write strobe is issued The CPU examines the state of its READY input during the last half of T3 When READY goes high signifying that the addressed device has accepted the data the CPU enters T4 and terminates the write strobe DEN then goes false and the data buffers are tristated The CPU interrupt acknowledge INTA cycle timing is shown in figure 4 6 Two back to back INTA cycles are required for each interrupt initiated by the 8259A PIC or by a slave 8259A PIC cascaded to the master PIC The INTA
98. input through software The End Of Interrupt EOD command from the CPU is required to reset the PIC for the next interrupt 3 39 FULLY NESTED MODE This mode is used only when one or more PIC s are slaved to the master PIC in which case the priority is conserved within the slave PIC s The operation in the fully nested mode is the same as the nested mode except as follows a When an interrupt from a slave PIC is being serviced that particular PIC is not locked out from the master PIC priority logic That is further interrupts of higher priority within this slave PIC will be recognized and the master PIC will initiate an interrupt to the CPU b When exiting the interrupt service routine the soft ware must check to determine if another interrupt is pending from the same slave PIC This is done by sending an End of Interrupt EOI command to the slave PIC and then reading its In Service IS register If the IS register is clear empty an EOI command 15 sent to the master PIC If the IS register is not clear interrupt pending no EOI command should be sent to the master PIC 3 40 AUTOMATIC ROTATING MODE In this mode the interrupt priority rotates Once an interrupt on a given input is serviced that interrupt assumes the lowest priority Thus if there are a number of simultaneous interrupts the priority will rotate among the interrupts in numerical order For example if interrupts IR4 and IR6 request service simultaneous
99. iver D Restrictions Terminator T Delete Bit 3 if Port C8 is in Mode 0 bit 3 can in put or output Other wise bit 3 is reserved Bits 4 5 Depends on Port C8 mode Bits 6 7 Input or out put both must be in same direction 1 Output latched Connects OBF g output output 1 22 D A11 A12 A13 Port CC bits perform the following Bit 0 Port CA inter rupt PB INTR to inter rupt jumper matrix Connects 1 32 to ACKg input Bit 1 Port CA Out put Buffer Full OBF output Connects INTg output to interrupt matrix Bit 2 Port CA Ac knowledge input Bit 3 If Port C8 is in Mode 0 bit 3 can be in put or output Other wise bit 3 is reserved Bits 4 5 Input or out put both must be in same direction Bit 6 7 Depends on Port C8 mode Connects bit 4 to J1 26 Connects bit 5 to J1 28 Connects bit 6 to J1 30 Connects bit 7 to J1 32 Port C8 must be in Mode 0 for four bits to be available upper Port CA must be in Mode 0 for all four bits to be available T A11 lower available 0 Output D A10 Same as for Por CC HE latched upper Mode 0 Input 0 Output D A11 Same as for Port CC lower Mode Same as for Port CC ee 0 input lower Mode 0 Input Detault jumper connected at the factory T Port C8 must be in Mode 0 for all four bit
100. iversal Synchronous Asynchronous Receiver Transmitter Application Note AP 16 Intel MULTIBUS Interfacing Application Note AP 28 Intel 8259 Programmable Interrupt Cortroller Application Note AP 31 ii 1 GENERAL INFORMATION PAGE s oc end ceo n oes 1 1 DESCHIPUON dores Ea d oc ede ae REESE REO ihn 1 1 System Software Development 1 3 Equipment Supplied 1 3 REQUIRED sya PRM ra RE eee 1 3 SDECIDCAUOIlS BOs KS NOE 1 3 CHAPTER 2 PREPARATION FOR USE Introduction 2v eui SH eee ida tat Me tide ens 2 Unpacking and Inspection 2 1 Installation Considerations 2 1 User Furnished Components 2 1 Power Requirement 2 1 Cooling Requirement 2 1 Physical 2 1 Component Installation 2 1 ROM EPROM Chips 2 1 Line Drivers and I O Terminators 2 4 Jumper Switch Configuration 2 4 RAM Addresses Multibus 2 4 Priority tak pats 2 6 Serial I O Port Configuration 2 9 Parallel I O Port Configuration 2 9 Multibus Configuration
101. l Port Configuration Parallel Port Configuration Input frequencies to the 8253 Programmable Interval Timer are jumper selectable as follows Counter 0 TMRO INTR 57 58 153 6 kHz 57 56 1 23 MHz 57 53 2 46 MHz 57 62 External Clock to from Port CC terminator driver Counter 1 TMR1 INTR 59 60 153 6 kHz 59 56 1 23 MHz 59 53 2 46 MHz 59 62 Extemal Clock to from Port CC terminator driver 59 61 Jumper 59 61 effectively connects Counter 0 and Counter 1 in series in which the output of Counter 0 serves as the input clock to Counter 1 This permits programming the clock rates to Counter 1 and thus provide longer TMR1 INTR intervals Counter 2 8251 Baud Rate Clock 55 58 153 6 kHz 55 54 1 23 MHz 55 53 2 46 MHz 55 62 Ciock to from Port CC terminator driver A jumper matrix provides a wide selection of interrupts to be interfaced to the 8086 CPU and the Multibus Refer to paragraph 2 13 for configuration Description Counter 0 output Sheet 7 Jumpers posts 38 through 52 are used to configure the 8251A USART as described in paragraph 2 14 Jumper posts 7 through 37 are used to configure 8255A PPI as scribed in paragraph 2 15 Default jumper connected at the factory The configuration for 16K 24K or 32K access is done in a similar manner Always observe the IMPORTANT note in figure 2 1 in that the address spac
102. l usuy u esse s ERE Rr ad 3 12 ciae awa bo ic dvd 3 13 Counter Read s uet vi aos Rees 3 13 Clock Frequency Divide Ratio Selection 3 13 Rate Generator Interval 3 14 Interrupt Timer 3 14 8255A PPI Programming 3 14 Control Word 3 15 Addiessilig whe he BE Rd RAS 3 15 WAN ZAC ON xe see easel wa ER ae CR Pes 3 16 iio da o UA Sa 3 16 Read 3 16 Write Operation 3 16 8259A PIC 3 17 Interrupt Priority 3 17 Nested Mod cad cig e eec WGN ae as 3 17 Fully Nested Mode 3 17 Automatic Rotating Mode 3 17 Specific Rotating Mode 3 17 Special Mask Mode 3 18 Poll 3 3 3 18 Status Redd 4 s 3 18 Initialization Command Words 3 18 Operation Command 3 19 Addressing aene as 3 19 Initialization uqa bua 3 19 Operon DP bore A e een 3 19 Hardware Interrupts 3 25 Non Maskable Interrupt
103. ler as described in paragraph 4 34 The CPU completes the read or write operation when is asserted During the Multibus access of on board RAM the SLA VE MODEJ signal enables the Address Bus Drivers A86 87 88 the ON BD ADR signal is false and enables the Data Bus Drivers A69 89 4 36 BYTE OPERATION For Multibus operation the on board RAM is organized as two 8 bit data banks all even byte data is in one bank DATO DAT7 and all odd byte data is in the other bank DAT8 DATF Refer to figure 3 1 which shows the data path for Multibus operation by 8 bit and 16 bit bus masters The Byte High Enable BHEN signal when asserted access the high odd byte address bit ADRO when low access the low even hyte All word operations must occur on an even byte address boundary with BHEN asserted Byte operations can occur in one of two ways a The even bank can be accessed by controlling ADRO which places the data on the DATO lines Refer to figure 3 1 b access the odd bank which is normally placed on DAT8 DATF the data path shown in figure 3 1B is implemented This requires that BHEN be false and ADRO to be low These operations permit the access of both bytes of the 16 bit data word by controlling ADRO In other words therefore specifies a unique byte and is not a part of a 16 bit word operation Shown below are the states of BHEN and ADRO for 8 bit and 16 bit oper
104. low a reset internal or external The control words are either a Mode instruction or a Command instruction 3 9 MODE INSTRUCTION FORMAT The Mode instruction word defines the general charac teristics of the USART and must follow a reset operation Once the Mode instruction word has been written into the USART sync characters or command instructions may be inserted The Mode instruction word defines the following a For Sync Mode 1 Character length 2 Parity enable 3 Even odd parity generation and check 4 External sync detect not supported by 86 1X 5 Single or double character sync b For Async Mode 1 Baud rate factor X1 X16 or X64 2 Character length 3 Parity enable 4 Even odd parity generation and check 5 Number of stop bits Instruction word and data transmission formats for syn chronous and asynchronous modes are shown in figures 3 2 through 3 5 iSBC 86 12 DU D De Wn 16 Ds 10 sfo e CHARACTER LENGTH PARITY ENABLE 1 ENABLE 0 DISABLE EVEN PARITY GENERATION CHECK EVEN 0 ODD EXTERNAL SYNC DETECT 1 SYNDET 15 AN INPUT 0 SYNDET IS AN OUTPUT SINGLE CHARACTER SYNC 1 SINGLE SYNC CHARACTER 0 DOUBLE SYNC CHARACTER NOTE IN EXTERNAL SYNC MODE PROGRAMMING DOUBLE CHARACTER SYNC WILL AFFECT ONLY THE Tx Figure 3 2 USART Synchronous Mode Instruction Word Format CPU BYTES 5 8 BITS CHAR DATA CHARACTERS ASSEMBLED SERIAL DATA OUT
105. ly IR4 will receive the high est priority After service the priority level rotates so that IR4 has the lowest priority and IR5 assumes the highest priority In the worst case seven other interrupts are serviced before IR4 again has the highest priority Of course if IR4 is the only request it 1s serviced promptly The priority shifts when the PIC receives an End of Interrupt EOD command 3 41 SPECIFIC ROTATING MODE In this mode the software can change interrupt priority by specifying the bottom priority which automatically sets the highest priority For example if IR5 is assigned the bottom prior ity IR6 assumes the highest priority In specific rotating mode the priority can be rotated by writing a Specific Rotate at EOI SEOI command to the PIC This com mand contains the BCD code of the interrupt being ser viced that interrupt is reset as the bottom priority In addition the bottom priority interrupt can be fixed at any time by writing a command word to the appropriate PIC Programming Information 3 42 SPECIAL MASK MODE One or more of the eight interrupt request inputs can be individually masked during the PIC initialization or at any subsequent time If an interrupt is masked while it is being serviced lower priority interrupts are inhibited There are two ways to enable the lower priority interrupts a Write an End of Interrupt EOD command b Set the Special Mask Mode The Special Mask Mode is useful when
106. minal Ready Secondary CTS Request to Send Transmit Clock Receive Clock Transmit Data Can support only one 24 programmable lines 8 lines per port one port includes bidirectional bus driver IC sockets included for user installation of line drivers and or terminators as required for interface ports Refer to table 2 1 8086 CPU includes non maskabie interrupt NMI and maskable interrupt INTR interrupt is provided for catastrophic event such as power failure NMI vector address is 00008 INTR interrupt is driven by on board 8259A PIC which provides 8 bit identifier of interrupting device to CPU CPU multiplies identifier by fourto derive vector address Jumpers select interrupts from 18 sources without necessity of extemal hardware PIC may be programmed to accommodate or level sensitive inputs Refer to table 2 2 for compatible connector details Refer to paragraphs 2 21 and 2 22 for recommended types and lengths of I O cables 0 to 55 C 32 to 131 F To 90 without condensation 30 48 cm 12 00 inches 17 15 cm 6 75 inches 1 78 cm 0 7 inch 539 gm 19 ounces iSBC 86 12 General Information Table 1 1 Specifications Continued POWER REQUIREMENTS 5Vt5 VDD 12V 5 VBB 5V 5 VAA 12V 5 Does not include power for optional ROM EPROM I O drivers and VO terminators Does not include power required for optional ROM EPROM I O drivers and I O terminator
107. mine the status of a serial I O port by issuing an Read Command to the upper address 000DA or 000DE of the USART chip The format of the status word is shown in figure 3 8 A typical status read subroutine is given in table 3 6 3 7 Programming Information iSBC 86 12 Table 3 4 Typical USART Data Character Read Subroutine RX1 READS DATA CHARACTER FROM USART USES STATO DESTROYS A FLAGS RX1 RXA1 STATO PUBLIC EXTHN CALL STATO AND AL 2 RX1 ODCH CHECK FOR RXRDY TRUE ENTER HERE IF RXRDY IS TRUE Table 3 5 Typical USART Data Character Write Subroutine 1 WRITES DATA CHARACTER FROM REG USART USES STATO DESTROYS FLAGS PUBLIC TX1 TXA1 STATO PUSH AX CALL STATO AND AL 1 JZ TX11 POP AX OUT OD8H RET END 3 18 8253 PIT PROGRAMMING 22 1184 MHz crystal oscillator supplies the basic clock frequency for the programmable chips This clock fre quency is divided by 9 18 and 144 to produce three jumper selectable clocks 2 46 MHz 1 23 MHz and 153 6 kHz These clocks are available for input to Counter 0 Counter 1 and Counter 2 of the 8253 PIT The default factory connected and optional jumpers for selecting the clock inputs to the three counters are listed in table 2 4 Default jumpers connect the output of Counter 2 to the TXC and RXC inputs of the 8251A USART Jumpers are included so that Counters 0 and 1 can provide real time interrupts to the 8259A PIC
108. nter 0 Load Count Read Counter 0 000D2 Write Counter 1 Load Count N 8253 Read Counter 1 00004 Write Counter 2 Load Count Read Counter 2 00006 Write Control Read None 000D8 Write Data J2 Or Read Data J2 7 8251A OOODA USART Write Mode or Command or Read Status OOODE addresses i e 000 1 000 3 00002 illegal AE 3 3 Programming Information b The 8251A USART serial I O port is set to the idle mode waiting for a set of Command Words to pro gram the desired function c The 8255A PPI parallel I O ports are set to the input mode The 8253 PIT and the 8259 PIC are not affected by the power up sequence The reset signal is also gated onto the Multibus to initialize the remainder of the system components to a known internal state The reset signal can also be generated by an auxiliary RESET switch Pressing and releasing the RESET switch produces the same effect as the power up reset described above 3 8 8251A USART PROGRAMMING The USART converts parallel output data into virtually any serial output data format including IBM Bi Sync for half or full duplex operation The USART also converts serial input data into parallel data format Prior to starting transmitting or receiving data the USART must be loaded with a set of control words These control words which define the complete functional op eration of the USART must immediately fol
109. o do so by an optional signal supplied via auxiliary connector P2 The RESET signal initializes the system as well as certain iSBC 86 12 components to a known internal state CHAPTER 4 PRINCIPLES OF OPERATION 4 4 CENTRAL PROCESSOR UNIT The 8086 Microprocessor CPU A39 which is the heart of the single board computer performs the system pro cessing functions and generates the address and control signals required to access memory and devices Con trol signals 50 S1 and S2 are driven by the CPU and decoded by Status Decoder A81 to develop the various signals required to control the board The CPU ADO ADIS pins are used to multiplex the 16 bit input output data and the lower 16 bits of the address During the first part of a machine cycle for example the lower 16 bits ADO AD15 and the upper 4 bits AD16 AD19 are strobed into Address Latch A40 41 57 by the Address Latch Enable ALE signal The ALE signal is derived by decoding 50 51 and 52 The Address Latch out puts form the 20 bit address bus ABO ABI3 i e and 10 13 During the remainder of the machine cycle the ADO ADIS pins of the CPU are used to form the 16 bit data bus ADO ADF 4 5 INTERVAL TIMER The 8253 PIT provides three independently controlled counters that derive their optional basic timing inputs from the clock circuit composed of 16 17 18 Counter 2 provides timing for the serial I O port 8251A USART This counter in c
110. oard Pin 1 is the right most pin when viewed from the component side of the board with the extractors at the top Only one of these signal outputs pin 5 21 or 26 may be selected 3 Optional jumper selected output of 8255A PPI Refer to figure 5 2 sheet 9 4 Default jumpers 39 40 and 42 43 connect 8253 CTR2 output to 8251A RXC and inputs respectively See Timer Input Frequency Counter 2 in table 2 4 Forthose applications without CTS capability connect jumper 51 52 This routes 8251A RTS output to 8251A CTS input Default jumpers connected at the factory 2 9 Preparation for Use iSBC 86 12 Table 2 7 Parallel I O Port Configuration Jumpers Jumper Configuration Driver D terminator P Delete Add effect ui 8226 A8 A9 21 25 24 25 0 Output 8226 21 25 latched Restrictions 8226 input enabled CA None can be in mode 0 or 1 input or output None can be in Mode 0 input or output unless Port CA is in Mode None can be in Mode 0 1 input or output None can be in Mode 0 input or output unless Port CA is in Mode 1 None can be in Mode 0 or 1 input or output Port CC bits perform the following C8 8226 output enabled 8 1 Input strobed 8226 A8 9 T A10 D A11 8226 input enabled Connects J1 26 to STBa input Bits 0 1 2 Control for Port CA if Por
111. old time Write data hold time Read data hold time Acknowledge hold time Acknowledge turnoff delay Read to data valid Note 3 Inhibit hold time Blocks AACK if tis gt tis min Inhibit pulse width Cycle time of board Refresh delay time Read data setup to XACK Command separation Inhibit setup time 1 No refresh dual port RAM not busy 2 Maximum tap togp tack Maximum access tacc trp 2 18 SBC 86 12 Preparation for Use wef BCLK tDBQ BREQ BPRN BUSY L gt sN tDBY tDBY tDBO WRITE DATA WRITE COMMAND TACKWT WRT tXKH READ CMDR READ DATA STABLE DATA V4 txKD READ XACK a tACKRD READ AACK 611 4 Figure 2 3 Bus Exchange Timing Master Mode 2 19 Preparation for Use iSBC 86 12 m tAS tX KH lt i tDH tos DATA STABLE DATA DUAL PORT RAM WRITE 611 5 tAH tAS ADDRESS A STABLE ADDRESS MRDC 2 A WO tis tH DUAL PORT RAM READ tDHR INH 1 Figure 2 4 Bus Exchange Timing Slave Mode 2 20 iSBC 86 12 Preparation for Use pr onem HIGHEST LOWEST PRIORITY PRIORITY MASTER MASTER J2 J4 BPRO AND BPRN PINS 15 BPRN 15 BPRN 15 BPRN USED BY 9 MASTERS 16 16 EN
112. ommand instructions 3 13 ADDRESSING The USART chip uses address 000D8 or 000DC to read and write data address 000DA or 000DE is used to write mode and command words and read the USART status Refer to table 3 2 Programming Information D 1 TRANSMIT ENABLE 1 enable 0 disable DATA TERMINAL READY 22 high will force Output to zero RECEIVE ENABLE 1 enable disable SEND BREAK CHARACTER 1 forces TxD low normal operation ERROR RESET 1 reset error fiags FE REQUEST TO SEND high will force RTS output to zero INTERNAL RESET high returns 8251A to Mode Instruction Format ENTER HUNT MODE 1 enable search for Sync Characters HAS NO EFFECT ASYNC MODE Note Error Reset must be performed whenever HxEnable and Enter Hunt are programmed Figure 3 6 USART Command Instruction Word Format 3 14 INITIALIZATION A typical USART initialization and data sequence is presented in figure 3 7 The USART chip is initialized in four steps a Reset USART to Mode instruction format b Write Mode instruction word One function of mode word is to specify synchronous or asynchronous operation c If synchronous mode is selected write one or two sync characters as required d Write Command instruction word 3 6 iSBC 86 12 RESET ADDRESS 0000 MODE INSTRUCTION 000DA SYNC CHARACTER 1 SYNC MOOE ONL
113. onjunction with the USART can provide programmable Baud rates from 110 to 9600 Counter 0 can be used in one of two ways 1 asa clock generator it can be buffered to provide an external user defined clock or 2 as an interval timer to generate a CPU interrupt Counter 1 which is the system interval timer and can also generate an interrupt has a range of 1 6 microseconds to 853 3 milliseconds If longer times are needed Counters 0 and 1 can be cascaded to provide a single timer with a maximum delay of over 50 hours 4 6 SERIAL I O The 8251A USART provides RS232C compatibility and is configured as a data terminal Synchronous or ansyn chronous mode character size parity bits stop bits and Baud rates are all programmable Data clocks and control lines to and from connector J2 are buffered 4 7 PARALLEL The 8255A Programmable Peripheral Interface provides 24 programmable I O lines Two IC sockets are provided so that depending on the application TTL drivers or I O 4 1 Principles of Operation terminators may be installed to complete the interface to connector J1 The 24 lines are grouped into three ports of eight lines each these ports can be programmed to be simple I O ports strobed I O ports with handshaking or one port can be programmed as a bidirectional port with control lines The iSBC 86 12 includes various optional functions controlled by the parallel I O lines such as RS232C interface line timer
114. or RS232C serial I O interface are listed in table 2 6 An Intel iSBC 955 Cable Set is recommended for RS232C interfacing One cable assembly consists of a 25 conductor flat cable with a 26 pin PC connector at one end and an RS232C inter face connector at the other end The second cable assem bly includes an RS232C connector at one end and has spade lugs at the other end the spade lugs are used to interface to a teletypewriter See Appendix A for ASR33 TTY interface instructions Preparation for Use Table 2 15 Parallel Connector J1 Pin Assignments Port CA bit 7 Port CA bit 6 Port bit 5 Port bit 4 Port CA bit 3 Port bit 2 Port CA bit 1 Port CA bit O Port CC bit 3 Port CC bit 2 Port CC bit 1 Port CC bit 0 Port CC bit 4 Port CC bit 5 Port CC bit 6 Port CC bit 7 Port C8 bit 7 Port C8 bit 6 Port C8 bit 5 Port C8 bit 4 Port C8 bit 3 Port C8 bit 2 Port C8 bit 1 Ground Port C8 bit O s m 1 odd numbered pins 1 3 5 49 are on component side of the board Pin 1 is the right most pin when viewed from the component side of the board with the extractors at the top Ground Ground Ground Ground For OEM applications where cables will be made for the iSBC 86 12 it is important to note that the mating con nector for J2 has 26 pins whereas the RS232C connector has 25 pins Consequently when connecting the 26 pin mating connector to 25 conductor flat ca
115. or two sync characters depending on the trans mission format SBC 86 12 Programming Information Table 3 3 Typical USART Mode or Command Instruction Subroutine 2 OUTPUTS CONTROL WORD TO USART USES A STAT2 DESTROYS NOTHING PUBLIC CMD2 EXTRN STAT2 CMD2 LAHF PUSH AX LP CALL STAT2 AND AL 1 JZ LP POP AX SAHF STINT OUT ODAH RET END Finally write a Command instruction word to the USART Refer to figure 3 6 and table 3 3 IMPORTANT During initialization the 8251 USART requires a minimum recovery time of 3 2 microseconds 16 clock cycles between back to back writes in order to set up its internal registers This recovery time can be satisfied by the CPU performing two byte reads and a NOP between the back to back writes to the 8251A USART as follows OUT ODAH USART WRITE READ ADDED WAIT OUT ODAH SECOND USART WRITE This precaution applies only to the USART initialization and does not apply otherwise 3 15 OPERATION Normal operating procedures use data I O read and write Status read and Command instruction write operations Programming and addressing procedures for the above are summarized in following paragraphs NOTE After the USART has been initialized always check the status of the TXRDY bit prior to writing data or writing a new command word to the USART The TXRDY bit must be true to prevent overwriting and subsequent loss
116. ount value B is the desired Baud rate M is the Baud rate multiplier 1 16 or 64 and C is 1 23 MHz the input clock frequency Thus for a 4800 Baud rate the required count value N IS 1 23 x 105 N 16 716 If the binary equivalent of count value N 16 is loaded into Counter 2 then the output frequency is 4800 x 16 Hz which is the desired clock rate for asynchronous mode operation Count values N versus rate multiplier M for each Baud rate are listed in table 3 11 NOTE During initialization be sure to load the count value N into the appropriate counter and the Baud rate multiplier M into the 8251A USART iSBC 86 12 Table 3 11 PIT Count Value Vs Rate Multiplier for Each Baud Rate Baud Rate Count Value N For Count Values N assume clock is 1 23 MHz Double Count Values N for 2 46 MHz clock Count Values N and Rate Multipliers M are in decimal 3 27 RATE GENERATOR INTERVAL TIMER Table 3 12 shows the maximum and minimum rate generator frequencies and timer intervals for Counters 0 and 1 when these counters respectively have 1 23 MHz and 153 6 kHz clock inputs The table also provides the maximum and minimum generator frequencies and time intervals that may be obtained by connecting Counters 0 and in series 3 28 INTERRUPT TIMER To program an interval timer for an interruption terminal count program the appropriate timer for the correct operating mode Mode
117. outine 3 12 Typical PIT Count Value Load SUDIOULIIIG 3 12 Typical PIT Counter Read Subroutine 3 13 PIT Count Value Vs Rate Multiplier for Bach Baud Rate os chs te cee 3 14 PIT Rate Generator Frequencies and imer INtervalS tts e ERR US 3 15 PIT Time Intervals Vs Timer Counts pL 3 15 Typical PPI Initialization Subroutine 3 16 Typical PPI Port Read Subroutine 3 16 Typical PPI Port Write Subroutine 3 16 Typical PIC Initialization Subroutine NBV ex queso 3 21 Typical Master PIC Initialization Subroutine MOO Mee dedu d eeu 3 21 Typical Slave PIC Initialization Subroutine Ey S 2 Gite DO 3 22 Operation Procedures 3 22 Typical PIC Interrupt Request Register Read Subroutine 3 24 Typical PIC In Service Register Read Subroutine 3 24 Typical PIC Set Mask Register Subroutine 3 24 Typical PIC Mask Register Read DUDFOULUHIE Suet oio es Dax eacus 3 24 Typical PIC End of dos Command DUDFOUD aoe ee 3 25 Replaceable Parts uae i rioria raa 5 1 List of Manufacturers Codes 5 3 ILLUSTRATIONS FIGURE TITLE PAGE FIGURE TITLE PAGE 1 1 15 86 12 Single Board Computer 1 1 3 11 PIT Counter Register Latch Control 2 1 Dual Port RAM Address Configuration Word Format 3 13 Multibus 5
118. r A83 The time base for Bus Clock BCLK and Constant Clock CCLK is provided by Clock Generator A80 10ZA5 and crystal Y3 The 18 432 MHz crystal frequency is divided by A63 and driven onto the Multibus through jumpers 105 106 and 103 104 signal is also used as a clock input to the Bus Arbiter Assembly The time base for the remaining functions on the board is provided by clock Generator A17 7ZA7 and crystal The nominal 22 12 MHz crystal frequency appearing at the OSC output of A17 is buffered and supplied to the Dual Port Control Logic and to RAM Controller A70 Clock Generator A17 also divides the crystal frequency by nine to develop a 2 46 MHz clock at its d2TTL output The 2 46 MHz clock is applied directly to the clock input of the 8251A USART and applied through 18 to provide a selectable clock for the 8253 PIT Divider A16 also divides the 2 46 MHz clock by two and by nine respectively to produce 1 23 MHz and 153 6 kHz selectable clocks for the 8253 PIT 4 4 ISBC 86 12 4 16 CENTRAL PROCESSOR UNIT The 8086 CPU uses the 5 MHz clock input to develop the timing requirements for various time dependent func tions described in following paragraphs 4 17 BASIC TIMING Each CPU bus cycle consists of at least four clock CLK cycles referred to as T2 T3 and T4 The address is emitted from the CPU during and data transfer occurs on the bus during T3 and T4 T2 is used primarily for
119. r Backplane and Cardcage cludes four slots without bus terminators See figure 5 4 Provides four slot extension of iSBC 604 Power inputs and Multibus signal inter face Not required if iSBC 86 12 is in stalled in an iSBC 604 614 See Multibus Connector details in table 2 2 Connector See Auxiliary Connector details in Auxiliary backup battery and 550 mates with P2 table 2 2 ciated memory protect functions Connector See Parallel V O Connector details in Interfaces parallel port with Intel 8255A mates with J1 table 2 2 Interfaces serial I O port with Intel 8251A USART Connector See Serial connector details in mates with J2 table 2 2 Two or four each of the following types ROM or EPROM ROM EPROM Chips Ultraviolet Erasable PROM EPROM for development Masked ROM for dedi cated program 2758 2316E 2716 2332 SN7403 SN7400 SN7408 Ni SN7409 OC Interface parallel O ports CA and CC with Intel 8255A PPI Requires two line driver IC s for each 8 bit parallel output port Types selected as typical invert ing NI noninverting and OC open collector Intel iSBC 901 Divider or iSBC 902 Pull Up 5V PM P iSBC 901 330 Line Terminators Interface parallel ports CA and CC with Intel 8255A PPI Requires two 901 s or two 902 s
120. r signal to or from the serial I O port Intel 8251A USART 2 15 PARALLEL PORT CONFIGURATION Table 2 7 lists the jumper configuration for three parallel I O ports Note that each of the three ports C8 CA and CC can be configured in a variety of ways to suit the individual requirement 2 16 MULTIBUS CONFIGURATION For systems applications the iSBC 86 12 is designed for installation in a standard Intel iSBC 604 614 Modular Backplane and Cardcage Refer to table 2 1 items 1 and 2 Alternatively the iSBC 86 12 can be interfaced to a user designed system backplane by means of an Table 2 6 Serial Connector J2 Pin Assignments Vs Configuration Jumpers CHASSIS GND TRANSMITTER DATA SEC REC SIG RECEIVER DATA REC SIG ELE TIMING RQT TO SEND CLEAR TO SEND DATA SET RDY DATA TERMINAL RDY GND 12V TRANS SIG ELE TIMING 4 12V 5V GND SEC CTS Protective ground 8251A RXD Same as 8261A TXC in or 8255A STXD out Note 3 8251A TXD out 8251A in Note 4 8251A TXC in Note 4 8251A CTS in Note 5 8251A RTS out Note 5 8251A DTR out 8251A DSR in Ground 12V out Same as 8251A TXC inor 8255A STXD out Note 3 t 12V out 5V out Ground Same as 8251A TXC in or 8255A STXD out Note 3 48 49 45 46 49 50 45 46 38 39 41 42 W3A B 48 49 44 45 49 50 44 45 W2A B W1A B 48 49 45 47 49 50 45 47 Ail odd numbered pins 1 3 5 25 are on component side of the b
121. re required to initialize the master and each slave PIC Specifically Master PIC No Slaves ICW2 4 Master PIC With Slave s ICW2 ICW3 ICW4 Each Slave PIC ICW ICW2 ICW4 3 46 OPERATION COMMAND WORDS After being initialized the master and slave be programmed at any time for various operating modes The Operation Command Word OCW formats are shown in figure 3 15 and discussed in paragraph 3 49 Programming Information 3 47 ADDRESSING The master PIC uses addresses 000 0 000 2 to write initialization and operation command words ad dresses 000C4 or 000C6 to read status poll and mask bytes Addresses for the specific functions are provided in table 3 2 Slave PIC s if employed are accessed via the Multibus and their addresses are determined by the hardware designer 3 48 INITIALIZATION To initialize the PIC s master and slaves proceed as follows table 3 17 provides a typical PIC initialization subroutine for a PIC operated in the non bus vectored mode tables 3 18 and 3 19 are typical master PIC and slave PIC initialization subroutines for the bus vectored mode a Disable system interrupts by executing a CLI Clear Interrupt Flag instruction b Initialize master PIC by writing ICW s in the follow ing sequence 1 Write ICW1 to 000 0 and IC W2 to 000C2 2 If slave PIC s are used write IC W3 and ICW4 to
122. re shown in stalled in the iSBC 604 In the scheme shown in figure 2 6 the priority encoder is a 74148 and the priority decoder is an Intel 8205 Input connections to the priority encoder determine the bus priority with input 7 having the highest priority and input 0 having the lowest priority Here the J3 bus master has the highest priority and the J5 bus master has the lowest priority IMPORTANT In a parallel priority resolution scheme the BPRO output must be disabled on all bus masters On the iSBC 86 12 disable the BPRO output signal by removing jumper 151 152 If a similar jumper cannot be removed on the other bus masters either clip the IC pin that supplies the BPRO output signal to the Multibus or cut the signal trace 2 20 POWER FAIL MEMORY PROTECT CONFIGURATION A mating connector must be installed in the iSBC 604 604 Modular Cardcage and Backplane to accom modate auxiliary connector P2 Refer to figure 1 1 Table 2 2 lists some 60 pin connectors that can be used for this purpose flat crimp solder and wirewrap con nector types are listed Table 2 13 correlates the signals and pin numbers on the connector Procure the appropriate mating connector for P2 and secure it in place as follows a Position holes in P2 mating connector over mounting holes that are in line with corresponding P1 mating connector b From top of connector insert two 0 5 inch 4 40 pan head screws down through connector and mounting
123. read the iSBC 86 12 provides vectoring for bus vectored non bus vectored NBV interrupts An on board Intel 8259A Programmable Interrupt Controller PIC handles up to eight NBV interrupts By using external PIC s slaved to the on board PIC master the interrupt structure can be expanded to handle and resolve the prior ity of up to 64 BV sources The PIC which can be programmed to respond to edge sensitive or level sensitive inputs treats each true input signal condition as an interrupt request After resolving the interrupt priority the PIC issues a single interrupt request to the CPU Interrupt priorities are independently programmable under software control The program mable interrupt priority modes are iSBC 86 12 a Fully Nested Priority Each interrupt request has a fixed priority input 0 is highest input 7 is lowest b Auto Rotating Priority Each interrupt request has equal priority Each level after receiving service becomes the lowest priority level until the next inter rupt occurs c Specific priority Software assigns lowest priority Priority of all other levels is in numerical sequence based on lowest priority The CPU includes a non maskable interrupt NMI and a maskable interrupt INTR The NMI interrupt is intended to be used for catastrophic events such as power outages that require immediate action of the CPU The INTR interrrupt is driven by the 8259A
124. request Interrupt Request These eight lines transmit Interrupt Requests to the appropriate interrupt handler INTO has the highest priority Read Command Indicates that the address of an VO port is on the Multibus address lines and that the output of that port is to be read placed onto the Multibus data lines Write Command Indicates that the address of an port is on the Multibus address lines and that the contents on the Multibus data lines are to be accepted by the addressed port Memory Read Command Indicates that the address of a memory location is on the Multibus address lines and that the contents of that location are to be read placed on the Multibus data lines Memory Write Command indicates that the address of a memory location is on the Multibus address lines and thatthe contents onthe Multibus data lines are to be written into that location Transfer Acknowledge Indicates that the address memory location has completed the specified read or write operation That is data has been placed onto or accepted from the Multibus data lines 2 15 Preparation for Use iSBC 86 12 AACK XACK Table 2 10 iSBC 86 12 DC Characteristics Test Conditions loL 16 3mA Description Output Low Voltage Output High Voltage Input Low Voltage Input High Voltage ME Input Current at Low Vin 0 4V mA Input Current at High V
125. rface consists of the Bus Arbiter Assembly 37 03 Bus Command Decoder A83 3ZC3 bidirectional Address Bus Driver A87 88 5ZC3 bi directional Data Bus Driver A69 89 90 4ZB3 and the Slave RAM Decode Logic figure 5 2 sheet 3 The falling edge of BCLK provides the bus timing refer ence for the Bus Arbiter which allows the iSBC 86 1X to assume the role of a bus master When the ON BD ADR signal is false high and the 50 52 status signals indicate either a read or write operation the Bus Arbiter drives BREQ low and BRPO high The BREQ output from each bus master in the system is used by the Multibus when the bus priority is resolved by a parallel priority scheme as described in paragraph 2 19 The BPRO out put is used by the Multibus when the bus priority is resolved by a serial priority scheme as described in paragraph 2 18 The iSBC 86 12 gains control of the Multibus when the BPRN input to the Bus Arbiter is driven low On the next falling edge of BCLK the Bus Arbiter drives BUSY and BUS ADEN low The BUSY output indicates that the bus is in use and that the current bus master in control will not relinquish control until it raises its BUSY signal The BUS ADEN output which can be thought of as a master bus control signal is applied to the AEN2 input of Clock Generator A38 2ZC6 the Bus Address Driver sheet 5 and the input of gate A2 11 3ZC4 Principles of Operation With AEN2 enabled
126. rtons and pack ing material be saved for future use in the event the pro duct must be reshipped 2 3 INSTALLATION CONSIDERATIONS The iSBC 86 12 is designed for use in one of the follow ing configurations a Standalone single board system b Bus master in a single bus master system c Bus master in a multiple bus master system Important criteria for installing and interfacing the iSBC 86 12 in these configurations are presented in following paragraphs 2 4 USER FURNISHED COMPONENTS The user furnished components required to configure the iSBC 86 12 for a particular application are listed in table 2 1 Various types and vendors of the connectors speci fied in table 2 1 are listed in table 2 2 2 5 POWER REQUIREMENT The iSBC 86 12 requires 5 5 12V and 12 V power The 5 power which is required only for the dual port RAM can be supplied by the system 5V supply an auxiliary battery or by the on board 5 V regulator The 5V regulator operates from the system 12V supply 2 6 COOLING REQUIREMENT The iSBC 86 12 dissipates 451 gram calories minute 1 83 Btu minute and adequate circulation of air must be provided to prevent a temperature rise above 55 C 131 F The System 80 enclosures and the Intellec Sys tem include fans to provide adequate intake and exhaust of ventilating air 2 7 PHYSICAL DIMENSIONS Physical dimensions of the iSBC 86 12 are as follows a Width 30 48 cm 1
127. s RAM chips powered via auxiliary power bus Does not include power for optional ROM EPROM drivers and terminators Power for iSBC 530 is supplied via serial port connector Includes power required for four ROM EPROM chips and terminators installed for16 I O lines all terminator inputs low 2 PREPARATION FOR USE 2 1 INTRODUCTION This chapter provides instructions for the iSBC 86 12 Single Board Computer in the user defined environment It is advisable that the contents of Chapters 1 and 3 be fully understood before beginning the configuration and installation procedures provided in this chapter 2 2 UNPACKING AND INSPECTION Inspect the shipping carton immediately upon receipt for evidence of mishandling during transit If the shipping carton is severely damaged or waterstained request that the carrier s agent be present when the carton is opened If the carrier s agent is not present when the carton is opened and the contents of the carton are damaged keep the carton and packing material for the agent s inspection For repairs to a product damaged in shipment contact the Intel Technical Support Center see paragraph 5 3 to obtain a Return Authorization Number and further instructions A purchase order will be required to com plete the repair A copy of the purchase order should be submitted to the carrier with your claim It is suggested that salvageable shipping ca
128. s 1 Disables counting 2 Sets output immediately high Disables counting 1 initiates counting 2 Resets output after next clock Initiates counting Initiates counting Enables counting Initiates counting iSBC 86 12 3 20 ADDRESSING As listed in table 3 2 the PIT uses four I O addresses Addresses 00000 00002 and 00004 respectively are used in loading and reading the count in Counters 0 1 and 2 Address 000D6 is used in writing the mode control word to the desired counter 3 21 INITIALIZATION To initialize the PIT chip perform the following a Write mode control word for Counter 0 00006 Note that all mode control words are written to 000D6 since mode control word must specify which counter is being programmed Refer to figure 3 9 Table 3 8 provides a sample subroutine for writing mode control words to all three counters b Assuming mode control word has selected a 2 byte load load least significant byte of count into Counter 0 at 000DO Count value to be loaded is described in paragraphs 3 23 through 3 25 Table 3 9 provides a sample subroutine for loading 2 byte count value c Load most significant byte of count into Counter O at 00000 Table 3 8 Typical PIT Control Word Subroutine INITIALIZES COUNTERS 0 1 2 COUNTERS 0 1 ARE INITIALIZED AS INTERRUPT TIMERS COUNTER 2 IS INITIALIZED AS BAUD RATE GENERATOR ALL THREE COUNTERS ARE SET UP FOR 16 BI
129. s of appropriate 16 bit frequency factor to Baud Rate Register 2 Baud rates shown here are only a sample subset of possible software programmable rates available Any frequency from 18 75 Hz to 613 5 kHz may be generated utilizing on board crystal oscillator and 16 bit Program mabie Interval Timer used here as frequency divider iSBC 86 12 INTERVAL AND BAUD RATE GENERATOR Input Frequency selectable Output Frequencies SYSTEM CLOCK 8086 CPU ADDRESSING INTERFACE COMPATIBILITY Serial I O Parallel INTERRUPTS COMPATIBLE CONNECTORS CABLES ENVIRONMENTAL REQUIREMENTS Operating Temperature Relative Humidity PHYSICAL CHARACTERISTICS Width Height Thickness Weight General Information Table 1 1 Specifications Continued 2 46 MHz 0 1 0 41 usec period nominal 1 23 MHz 0 196 0 82 period nominal and 153 6 kHz 0 1 6 5 usec period nominal Dual Timers Function Single Timer Two Timers Cascaded 466 5 minutes Real Time 427 1 3 26 Interrupt Interval Rate Generator Frequency 613 5 kHz 0 000036 Hz 306 8 kHz 5 0 MHz 0 1 All communication to Parallel I O and Serial Ports Timer and Interrupt Controller is via read and write commands from on board 8086 CPU Refer to table 3 2 EIA Standard RS232C signals provided and supported Clear to Send Receive Data Data Set Ready Secondary Receive Data Data Ter
130. s the Intel 8086 Microprocessor CPU interrupt capability A complete descript on of programming with Intel s assembly language is given in the 8086 Assembly Language Reference Manual Manual Order No 9800640 3 2 FAILSAFE TIMER The 8086 CPU expects an acknowledge signal to be re turned from the addressed I O or memory device in re sponse to each Read or Write Command The iSBC 86 12 includes a Failsafe Timer that is triggered during T1 of every machine cycle If the Failsafe Timer is enabled by hardwire jumper as described in table 2 4 and no acknowledge signal is received within approximately 6 milliseconds after the command is issued the Failsafe Timer will time out and allow the CPU to exit the wait state As described in Chapter 2 provision is made so that the Failsafe Timer output TIME OUT can optionally be used to interrupt the CPU If the Failsafe Timer is not enabled by hardwire jumper and an acknowledge signal is not returned for any reason the CPU will hang up in a wait state In this situation the only way to free the CPU is to initialize the sys em as described in paragraph 3 7 3 3 MEMORY ADDRESSING The iSBC 86 12 includes 32K bytes of dynamic random access memory RAM and four IC sockets to accom PROGRAMMING INFORMATION CHAPTER 3 modate up to 16K bytes of user installed read only memory ROM or EPROM The iSBC 86 12 features a dual port RAM access arrangement in which the on board RAM
131. s to be available Connects bit to J1 24 Connects bit 1 to J1 22 Connects bit 2 to J1 20 Connects bit 3 to J1 18 Port must be Mode 0 for all four bits to be P iSBC 86 12 86 pin connector Refer to table 2 1 item 3 Multibus signal characteristics and methods of implementing a serial or parallel priority resolution scheme for resolving bus contention in a multiple bus master system are de scribed in following paragraphs Always turn off the system power supply be fore installing or removing any board from the backplane Failure to observe this pre caution can cause damage to the board 2 17 SIGNAL CHARACTERISTICS As shown in figure 1 1 connector interfaces the 185 86 12 to the Multibus Connector P1 pin assignments are listed in table 2 8 and descriptions of the signal functions are provided in table 2 9 The dc characteristics of the iSBC 86 12 bus interface signals are provided in table 2 10 The ac character istics of the iSBC 86 12 when operating in the master mode and slave mode are provided in tables 2 11 and 2 12 respectively Bus exchange timing diagrams are provided in figures 2 3 and 2 4 2 18 SERIAL PRIORITY RESOLUTION In a multiple bus master system bus contention can be resolved in an iSBC 604 Modular Backplane and Card cage by implementing a serial priority resolution scheme as shown in figure 2 5 Due to the propagation delay of the BPRO signal pa
132. scription lol 60 mA lou 3mA Output Low Voltage Output High Voltage Capacitive Load loL lou 5 mA Output Low Voltage Output High Voltage Input Low Voitage input High Voltage Input Current at Low V Output Leakage High Capacitive Load Input Low Voltage Input High Voltage Vin 0 5V Vin Input Current at Low Input Current at High Capacitive Load Output Low Voltage lo 44 mA OPEN COLLECTOR Output High Voltage Input Low Voltage Input High Voltage Input Current at Low V Input Current at High V Capacitive Load Input Low Voltage Input High Voltage Input Current at Low V Input Current at High V Capacitive Load Vin 0 4V Vin 2 4V Output Low Voltage lo 32 mA lon 5 mA Vo 5 25V Vo 0 45V Output High Voltage Output Leakage High Output Leakage Low Capacitive Load lou 30 mA 5 Output Low Voltage Output High Voltage Input Low Voltage Input High Voltage Input Current at Low V Vin 0 45V ViN 7 5 25 Input Current at High V Capacitive Load Capacitive load values are approximations 2 17 Preparation for Use iSBC 86 12 Table 2 11 iSBC 86 12 AC Characteristics Master Mode Parameter Minimum Maximum Description ns ns Address setup time to command
133. signal PCS2 or PCS3 is asserted the contents of the address specified by ABI ABA are transferred to the CPU via Data Buffer A44 45 4 31 RAM OPERATION As described in paragraph 4 22 the Dual Port Control logic allows the on board RAM facilities to be shared by the 8086 CPU and another bus master via the Multibus The following paragraphs describe the RAM Controller RAM chip arrays and the overall operation of how the RAM is addressed for read write operation 4 32 RAM CONTROLLER address and control inputs to the on board RAM is supplied by RAM Control ler A70 10ZB6 The RAM Controller automatically provides a 64 cycle RAS CAS refresh timing cycle to the dynamic RAM composed of RAM chips A72 79 and 92 99 The RAM Controller when enabled by low input to its PCS pin multiplexes the address to the RAM chips Low order address bits are presented at the RAM address lines and RAS is driven low at the beginning of the first memory clock cycle High order address bits 7 13 are presented at the RAM address lines and CAS is driven low during the second memory clock cycle The RAM Controller drives its WE output pin according to whether the CPU instruction is a read or write For a write operation the WT input is low to the RAM Controller in iSBC 86 12 which case the WE output is driven low For a write operation the WR input is low and the WE output remains high When the memory cycle re
134. sing edge of the gate input Mode 2 Rate generator In this mode the output of Counter and or Counter 2 will be low for one period of the clock input The period from one output pulse to the next equals the number of input counts in the count register If the count register is reloaded be tween output pulses the present period will not be affected but the subsequent period will reflect the new value The gate input when low will force the output high When the gate input goes high the counter will start from the initial count Thus the gate input can be used to synchronize the counter When Mode 2 15 set the output will remain high until after the counter register is loaded thus the count can be synchronized by software Mode 3 Square wave generator Mode 3 which 15 the primary operating mode for Counter 2 is used for generating Baud rate clock signals In this mode the counter output remains high until one half of the count value in the count register has been dec remented for even numbers The output then goes low for the other half of the count If the value in the count register is odd the counter output is high for N 172 counts and low for 1 2 counts Programming Information ALTERNATE PROGRAMMING FORMAT Mode Conal Word Counter 0 Mode Control Word Counter 1 Mode Contro Word Counter 2 Counter Register Byte Counter 1 Count Register Byte Counter 1 Count Register Byte
135. solution schemes BPRO must be connected to the BPRN input of the bus master with the next lower bus priority Bus Request in parallel priority resolution schemes BREQ indicates that a particular bus master requires control of the bus for one or more data transfers BREQ is synchronized with BCLK Bus Busy indicates that the bus is in use and prevents all other bus masters from gaining control of the bus BUSY is synchronized with BCLK Common Bus Request indicates that a bus master wishes control of the bus but does not presently have control As soon as control of the bus is obtained the requesting bus controller raises the CBRQ signal Constant Clock Provides a clock signal of constant frequency for use by other system modules When generated by the iSBC 86 12 CCLK has a period of 108 5 nanoseconds 9 22 MHz with a 35 65 percent duty cycle Data These 16 bidirectional data lines transmit and receive data to and from the addressed memory location or port DATF is the most significant bit For data byte operations DATO DAT 7 is the even byte and DAT8 DATF is the odd byte Inhibit RAM For system applications allows iSBC 86 12 dual port RAM addresses to be overlayed by ROM PROM or memory mapped I O devices This signal has no effect of CPU access of its dual port RAM Initialize Resets the entire system to a known internal state Interrupt Acknowledge This signal is issued in response to an interrupt
136. ster is allowed to access RAM and complete its operation Where both the CPU and the controlling bus master have the need to write or read several bytes or words to or from on board RAM their operations are interleaved For CPU access the on board RAM addresses are assigned from the bottom up of the 1 megabyte address space i e 00000 07 The slave RAM address decode logic includes jumpers and switchers to allow partitioning the on based RAM into any 128K segment of the 1 megabyte system address space The slave RAM can be configured to allow either SK 16K 24K or 32K access by another bus master Thus the RAM can be configured to allow other bus masters to access a segment of the on board RAM and still reserve another segment strictly for on board use The addressing scheme accommodates both 16 bit and 20 bit addressing Four IC sockets are included to accommodate up to 16K bytes of user installed read only memory Configuration jumpers allow read only memory to be installed in 2K 4K or 8K increments The iSBC 86 12 includes 24 programmable parallel I O lines implemented by means of an Intel 8255A Pro grammable Peripheral Interface PPI The system software is used to configure the I O lines in any combina tion of unidirectional input output and bidirectional ports The interface may be customized to meet specific peripheral requirements and in order to take full advan tage of the large number of possible I O conf
137. t CA is in Mode 1 Bit 3 Port C8 Inter rupt PA INTR to inter rupt jumper matrix Bit 4 Port C8 Strobe STB input Bit 5 Port C8 In put Buffer IBF output Bits 6 7 Port CC in put or output both must be in same direction Connects output to 41 18 Connects INT output to interrupt matrix 21 Output latched 8226 A8 9 T A10 D A11 8226 output enabled Connects J1 30 to input Connects output to J1 18 Port EA bits perform the following xe Bits 0 1 2 Control for Port CA if Port CA is in Mode 1 Bit 3 Port C8 Inter rupt PA INTR to inter rupt jumper matrix Bits 4 5 Port CC in put oroutput both must be in same direction Bit 6 Port C8 Ac knowledge ACK input Bit 7 Port C8 Output Buffer Full OBF output Default jumper connected at the factory 2 10 Connects output to interrupt matrix iSBC 86 12 Preparation for Use Table 2 7 Parallel O Configuration Jumpers Continued Jumper Configuration LEER Allows input to control 8226 in out direction Driver Dy Terminator T Restrictions 8226 8 9 10 D A11 None can be in Mode 0 or 1 input or output Port CC bits perform the following
138. t Control CPU Access Timing Word ka abre bte gs 3 6 With Multibus Lockout 4 10 3 7 Typical USART Initialization and 5 iSBC 86 12 Parts Location Diagram 5 6 Data Sequence 3 6 5 2 iSBC 86 12 Schematic Diagram 5 7 3 8 USART Status Read Format 3 9 5 3 iSBC 604 Schematic Diagram 5 29 3 9 PIT Mode Control Word Format 3 10 5 4 ISBC 614 Schematic Diagram 5 31 3 10 PIT Programming Sequence Examples 3 11 vii viii 1 GENERAL INFORMATION 1 1 INTRODUCTION The iSBC 86 12 Single Board Computer which is a member of Intel s complete line of iSBC 80 86 computer products is a complete computer system on a single printed circuit assembly The iSBC 86 12 includes a 16 bit central processing unit CPU 32K bytes of dynamic RAM a serial communications interface three programmable parallel I O ports programmable timers priority interrupt control Multibus control logic and bus expansion drivers for interface with other Multibus compatible expansion boards Also included is dual port control logic to allow the iSBC 86 12 to act as a slave RAM device to other Multibus masters in the system Provision is made for user installation of up to 16K bytes of read only memory 1 2 DESCRIPTION The iSBC 86 12 Single Board Computer figure 1 1 is controlled by an Intel 8086 16 Bit Microprocessor
139. tc are identical connectors with different electroplating thicknesses or metal surfaces Preparation for Use The low order byte bits 0 7 of ROM EPROM must be installed in sockets A29 and A28 the high order byte bits 8 15 must be installed in sockets A47 and A46 Assuming that 2K bytes of EPROM are to be installed using two Intel 2758 chips the chip containing the low order byte must be installed in IC socket A29 and the chip containing the high order byte must be installed in IC socket A47 In this configuration the usable ROM EPROM address space is FF800 FFFFF Two ditional Intel 2758 chips may be installed later in IC sockets A28 and A46 and occupy the address space FF000 FF7FF Even addresses read the low order bytes and odd addresses read the high order bytes The default factory connected jumpers and switch 51 are configured for 2K by 8 bit ROM EPROM chips e g two or four Intel 2716 s If different type chips are installed reconfigure the jumpers and switch S1 as listed in table 2 4 2 10 LINE DRIVERS AND TERMINATORS Table 2 3 lists the ports and the location of associated 14 pin IC sockets for installing either line drivers or I O terminators Refer to table 2 1 items 8 and 9 Port 8 is factory equipped with Intel 8226 Bidirectional Bus Drivers and requires no additional components 2 11 JUMPER SWITCH CONFIGURATION The iSBC 86 12 includes a variety of jumper and switch selectable
140. ted and auto rotating priority modes and Set mask register table 3 23 the SEOI command which specifies the bit to be reset 1s used in the specific rotating priority mode Tables 3 21 d Read mask register table 3 24 through 3 25 provide typical subroutines for the following e Issue EOI command table 3 25 3 2 Programming Information 15 86 12 Table 3 19 Typical Slave PIC Initialization Subroutine BV Mode INITIALIZES A SLAVE PIC LOCATED AT ADDRESS BLOCK BEGINNING WITH 0200H IS FULLY NESTED NON AUTO USES SETI DESTROYS A PUBLIC INTSL EXTRN SETI CALL SETI MOV AL 11H OUT OCOH MOV AL O8H OUT 0C2H MOV AL 19H OUT 0C2H RET END Table 3 20 PIC Operation Procedures Auto Rotating To set Priority Mode In OCW2 write a Rotate Priority at EO command to 000 0 Terminate interrupt and rotate priority In OCW2 write EOI command 20H to 000 0 Specific Rotating To set Priority Mode OCW2 write a Rotate Priority at SEOI command in the following format to 000 0 57 os oz o1 oo 1 1 1 0 0 2 L1 LO ue BCD of IR line to be reset and or put into lowest priority To terminate interrupt and rotate priority In OCW2 write an SEOI command in the following format to 000CO or os 05 os os 02 01 00 0 1 1 0 0 2 C1 LO w V BCD of ISR flip flop to be reset To rotate priority without EOI In OCW
141. th this scheme is limited to a maxi mum of three bus masters capable of acquiring and con trolling the Multibus In the configuration shown in figure 2 5 the bus master installed in slot J2 has the highest priority and is able to acquire control of the Multibus at any time because its BPRN input is always enabled tied to ground through jumpers B and N on the back plane See figure 5 3 If the bus master in slot J2 desires control of the Multibus it drives its BPRO output high and inhibits the BPRN input to all lower priority bus masters When finished using the Multibus the J2 bus master pulls its BPRO output low and gives the J3 bus master the opportunity to take control of the Multibus If the J3 bus master does not desire to control the Multibus at this time it pulls its BPRO output low and gives the lowest priority bus master in slot J4 the opportunity to assume control of the Multibus The serial priority scheme can be implemented in a user designed system bus if the chaining of BPRO and BPRN signals are wired as shown in figure 5 3 Preparation for Use 2 19 PARALLEL PRIORITY RESOLUTION A parallel priority resolution scheme allows up to 16 bus masters to acquire and control the Multibus Figure 2 6 illustrates one method of implementing such a scheme for resolving bus contention in a system containing eight bus masters installed in an iSBC 604 614 Notice that the two highest and two lowest priority bus masters a
142. tly used Auxiliary Backup 2 286 12 7 12 6 lf auxiliary backup batteries are used to sustain the dual port RAM conterits Batteries during ac power outages remove default jumpers W4 A B WS A K and W6 A B 12 6 dua port RAM requires 5 AUX input which be supplied by the system 5V supply an auxiliary backup battery or by the on board 5V regulator The 5V regulator operates from the system 12V supply system 5V supply is available and auxiliary backup bat teries are not used disconnect default jumper W5 A B and connect On Board 5 Regulator jumper W5 B C If auxiliary backup batteries are used disconnect de fault jumper W5 A B do not connect W5 B C 2286 If the on board CPU addresses either a system an on board memory or I O device and that device does not return an acknowledge signal the CPU will hang up in a wait state A failsafe timer is triggered during T1 of every machine cycle and if not retriggered within 6 2 milliseconds Failsafe Timer the resultant time out pulse can be used to allow the CPU to exit the wait state If this feature is desired connect jumper 5 6 Default jumper connected at the factory 2 5 Preparation for Use iSBC 86 12 Table 2 4 Jumper and Switch Selectable Options Continued Fig 5 1 Fig 5 2 Grid Ref Grid Ref Timer Input Frequency ZD3 7ZB5 203 Nu Priority Interrupts Seria
143. with a 3 bit identifier ID in ICW2 These three bits will form a part of the byte identifier transferred to the CPU response to the second acknowledge signal Programming Information The slave PIC requests an interrupt by driving the as sociated master PIC IR line The master PIC in turn drives the CPU INTR input high and the CPU outputs the first of two acknowledge signals In response to the first acknowledge signal the master PIC outputs a 3 bit binary code to slaved PIC s this 3 bit code allows the appro priate slave PIC to respond to the second acknowledge signal from the CPU 3 26 iSBC 86 1 Assume that the slave PIC has the ID code 1115 assigned in ICW2 and that the device requesting service is driving the IR2 line 010 Thus in response to the second acknowledge signal the slave PIC outputs 001110103 The CPU multiplies this value by four and trans fers control with an indirect call through 11101000 E8g te 4 1 INTRODUCTION This chapter provides a functional description and a circuit analysis of the iSBC 86 12 Single Board Com puter Figures 4 1 and 4 2 located at the end of this chapter are simplified foldout logic diagrams that illustrate the functional interface between the 8086 microprocessor CPU and the on board facilities and between the CPU and the system facilities via the Multibus Also shown in figure 4 2 is the Dual Port Control Logic that allows the iSBC 86 1

iSBC 86/12 Single Board Computer Hardware Reference Manual

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