"TAS3001 EVM Application Note"
Contents
1. JMP SW_DONE jump to end of SW routine MOV Vol Pntr Tbl Pntr set table pointer current Volume CALL OOP call I2C send routine CALL NOP 9 CALL NOP 9 MOV 1655 Tbl Pntr set table pointer to unmute mix data CALL OOP call I2C send routine JMP SW_DONE jump to end of SW routine turn mute on MOV 1645 Tbl Pntr set table pointer mute location CALL OOP call I2C send routine CALL NOP 9 CALL NOP 9 OV 1662 Tbl Pntr set table pointer to mute mix data CALL OOP call I2C send routine RET return from call sj send EQ BIT b SW2 amp SW1_3I1F SW2 pressed JZ SW3_EQ NO jump to next SW BIT b ED amp LED OUT LED on shift mode JNZ SW2 FUNC NO jump to SW2 function CALL UTE ON mute before sending EQ CALL NOP9 delay before sending EQ MOV 560 Tbl Pntr set table pointer to start of SW2 EQ CALL OOP jump to I2C send routine CALL DELAYO MOV 415 Tbl Pntr set table pointer to startup bass CALL OOP jump to I2C send routine MOV 510 Tbl Pntr set table pointer to startup treb CALL OOP jump to I2C send routine CALL DELAY JMP MUTE OFF jump to reset volume BIC b ED amp LED_OUT turn LED on CALL DELAY delay before testing SW again BIC SW2 amp SW1 3IF clear SW2 flag P 0 Vol Pntr volume minimum JEQ SW2_TEST Yes jump to SW2 test SUB 10 Vol Pntr decrease poin2. T SDIN SDOUT RESET MCLK e TLC3001 IIC DB25 Connector GUI Interface 4 2 PCB Silkscreen 4 2 PCB Silkscreen Figure 4 2 shows the printed circuit board silkscreen Figure 4 2 PCB Silk Screen TASS 1 EVME d With 25 Posar AME g e Ls D 1 Ze en C Sr man amp E F IM IHH Top Silkscreen TAS3001 EVM Block Diagram 4 4 _ set 5 copy STD DEF ASM MSP430 to Digital TAS3001 H Brian Merritt SP430 Applications rev 2 4G 10 99 Purpose of program to initialize Start up of the equalizer board key switches and Digital Speaker DS part Space data rev 2 4G unchanged delay changes in rev F back to rev C additional delay0 added in F ID11X link standard definitions file cc ck ck ck k ck ck Ck kk ck Ck ck KK KKK kk Ck kk ck k qe KKK sk Ck k kk ck KKK KKK KKK Ck sc ook kek ck ok kk ko sk qe ke L ko ko sk RK KK other than acknowledge Chapter 5 MSP430 Microcode Example EVM board SCH xx xx kx xx xx Digital Speaker part via 12C betw perform and act as interfac part Arbitration also deleted since 430 is the only part transmitting including after finding typo in rev F so read routines deleted to save memory Kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk n multifunction 430 does not have to read data fro
3. by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by 9 28 by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt 07F 0A5 01C DOC 011 068 016 010 000 000 000 000 000 000 000 000 000 000 QQ QQ vd D vd vd vd vd vd D vd Q D D D vd vd Q D D vd vd vd D vd vd O D D D P vd vd vd D vd vd DD vd vd vd vd DD DD vd vd vd vd MSP430 Microcode Example 5 29 5 30 by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by byt by by by by by by by te te te te te H H k oO OD so 00 00 ka N UJ Joa d PP ddd P d P P 2 d PD D dd dd P PP JO JO d P d d 22 2 0 d d
4. byt byt byt byt 00B 035 OOF OF5 0D6 011 068 016 010 000 o E E i o W o U HJ JN EO O O O O OO O O O 0 CH 1 o D o Hj O L H U ml d a OO ux X io e VED me E a A So E E EE e e Oh es d A l EK Ae ae A d d age IR A kd o HJ H D o R H 068 017 045 04C 047 OFA 08B by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt 000 000 000 000 000 000 000 000 011 068 00A 00F 025 0D4 00F ODA 043 011 068 00B 00F 08B 038 00 OD 012 OE1 u p QQ vd vd vd D D D vd vd vd vd vd vd vd vd vd vd vd O B D O B vd DD vd vd p vd DP DO PDP vd D vd 099 00E 06B DCH 011 068 DOC J vd 5 2 2 end of right EQ for SW4 EREEREER EREE EREEREER tO S Ae E s IMPORTANT this line must be included E RR line 1211 X XXXKKKKKKKKKKKAKKAK start of EQs for SW5 ROCK MSP430 Microcode Example 5 35 5 36 byt byt byt byt byt byt byt byt by byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt
5. byt byt byt byt byt byt byt 010 000 000 000 000 000 000 000 000 000 000 000 000 000 000 011 068 DOC 010 000 000 000 000 000 000 000 000 000 000 000 000 000 000 011 068 00D 010 000 000 000 000 000 000 000 000 000 000 000 000 000 J vd vd vd vd vd vd PP vd vd vd D vd vd vd vd vd vd vd vd DP vd vd vd D vd J J vd vd vd vd DP vd vd vd vd DO vd vd D vd vd hex number of bytes before next stop cmd hex number of bytes before next stop cmd MSP430 Microcode Example 5 45 5 46 byt byt byt byt DS E byt byt by byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt 000 011 068 00E 003 085 07 OB D5 03 85 EA M00 oO e e 014 036 003 003 076 011 068 013 010 000 000 000 000 000 000 000 000 Q Q P d ddd PP p vd d d p p vd Q P 40 ddd ddd d PD P d d d p Q Q dd p PD 2 hex number of bytes before next stop cmd hex number of bytes before next stop cmd end of left eq s hex number of bytes before next stop cmd by by by by by by by by by by by
6. byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte 000h 000h 000h 000h 000h 000h 005h 068h 007h 002h 0D8h 062h 000h 005h 068h 007h 000h 000h 000h 000h 003h 068 001 069 011 068 OOA 010 000 000 000 000 000 000 000 000 000 000 000 000 000 000 011 068 00B Q Q P 43 P PP PD 2 P P P d P P JO dd dd J D d J s IMPORTANT this line must be included EROS line 1655 Kkkkkkkkkkkkkkkkkkkkkkkk data for unmute of mixl mixl 15 dB s IMPORTANT this line must be included PARE line 1662 KKK KKK KKK lt x k lt k lt k k KKK KKK data for unmute of mixl mixl 15 dB s IMPORTANT this line must be included PER line 1669 cock ck k k k k k k kk k lt k k lt lt x ck lt KK beginning of data to be sent at start up hex number of bytes before next stop cmd normal mode I2S 18 bit hex number of bytes before next stop cmd hex number of bytes before next stop cmd by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by byt byt byt byt byt byt byt byt byt
7. byte 0B4 byte 0DF end of right eq s byte 003h treble 0 dB byte 068h byte 005h byte 072h byte 003h bass 0 dB byte 068h byte 006h CO OO 0 Boa d ddd dd vs P S vw P P ddd Jd P B vd d dd J PD d P P dd dd ddd d d dd P d d J 5 48 byte 03Eh byte 008h volume 18 dB byte 068h byte 004h byte 000h byte 020h byte 03Ah byte 000h byte 020h byte 03Ah byte 005h mixl 15 dB byte 068h byte 007h byte 002h byte 0D8h byte 062h byte 005h mix2 mute byte 068h byte 008h byte 000h byte 000h byte 000h byte 000h IMPORTANT this 000h indicates end of data table it MUST be included for program to fuction correctly PATINES KK TIEN ARATE DE ARR RUKIA ON OK KC SEN OEOK UON UK RAN KR BRAT FORGET RN ARR RO RESTE RRR IIA Interrupt vectors t SSS a IOT NS DS E SRR GO ROK AI RN RUDA SET KAA usut NRA AOR RE REO R even Following section must be evenly aligned sect Int Vect I vectors 31 word RESE no source word RESE no source word SW ISR s EST Se word SW ISR P P2 x word RESE no source word RESE no source word RESE no source word RESE no source word RESE Timer AX word RESE Timer AO word RESET Watchdog Timer Timer mode word RESE no source word R
8. by by by by by by by by by byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt 080 04 00 08 04 000 008 068 004 000 08F UF G 000 08F B o O m QQ DO oO vd D D vd vd D D D vd Q D D vd p vd vd vd vd vd vd vd vd D Q O D D D vd vd vd vd vd vd vd DD BO D vd vd B vd DP vd vd vd vd gg 000 008 068 004 000 0A1 086 000 OA1 086 000 008 068 004 000 0B5 03C 000 0B5 03C 000 008 068 004 000 OCB 059 000 OCB 059 000 008 068 004 029 IMPORTANT this line must be included vol setting IMPORTANT this line must be included vol setting 32 line 320 IMPORTANT this line must be included vol setting IMPORTANT this line must be included vol setting 34 line 340 IMPORTANT this line must be included vol setting MSP430 Microcode Example 5 17 by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by 000 029 000 008 068 004 001 000 000 001 000 000 000 003 068 006 05D 000 003 068 006 05A 000 003 068 006 058 000 003 068 006 055 000 003 0
9. byt byt byt byt 010 000 o k Pl o D o P ol O U H 4 N Gl o Ww o Hj IN oo i E SS SS E SS SS 7 U 0090 20000 00000 3 Dei 011 068 00E 045 04C 047 OFA 08B 011 068 OOF 010 000 000 000 000 000 000 000 000 000 000 000 000 000 Q d dd dd D PP PP dd P dQ d d d J Q Qd dd ddd 20 o P d d 2 by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt 000 011 068 013 00F 08B 038 OE 00 OD 012 OE1 U p ty QQ D vd B O B B vd vd vd DD vd D vd vd 099 00E 06B DCH 011 068 014 OOF 011 08B 024 072 00D 015 00B 034 OOF QQ vd vd vd D D DD vd D D DD vd O B vd D vd B O B vd vd p vd DP p p p vd J end of left EQ for SW4 MSP430 Microcode Example 5 33 5 34 byt byt byt byt byt ByE byt byt by byt byt byt byt byt byt byt byt byt byt byt byt byt by byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt by byt byt byt byt byt byt byt byt
10. IMPORTANT this line must be included vol setting 2 line 20 IMPORTANT this line must be included line 30 IMPORTANT this line must be included vol setting 4 MSP430 Microcode Example 5 11 byte 06E byte 000 byte 006 byte 06E byte 000 byte 008 byte 068 byte 004 byte 000 byte 007 byte 037 byte 000 byte 007 byte 037 byte 000 byte 008 byte 068 byte 004 byte 000 byte 008 byte 018 byte 000 byte 008 byte 018 byte 000 byte 008 byte 068 byte 004 byte 000 byte 009 byte 015 byte 000 byte 009 byte 015 byte 000 byte 008 byte 068 byte 004 byte 000 byte 00A byte 031 byte 000 byte 00A byte 031 byte 000 byte 008 byte 068 byte 004 byte 000 byte 00B byte 06F byte 000 s IMPORTANT th is line must be included vol setting line 50 s IMPORTANT th is line must be included vol setting 6 s IMPORTANT th is line must be included vol setting s IMPORTANT this line must be included vol setting 8 line 80 s IMPORTANT this line must be included vol setting Q Q Do P P dQ B P P P d JO P JO dd d JD ddd D P ddd d P dd PP P PD PD d YP PD P PP P dd Pp PD dd d d p 5 12 by by by by by by by by by by by by by by by by by by by by by by by by by by by by by
11. by byt byt byt byt byt byt byt byt byt byt byt byt 099 00E 06B oco 011 068 015 OOF 011 08B 024 072 015 I o J D d e dd D P P P P P d JO P P dd P P ddd dd JD J dd P Pp PD 2 P P D ddd P ddd d 23 D 3 dd d 3 p DO OO Oo c c X o 9 1 es rr leal Hy H HJ o El Di o VO D 011 068 017 010 00E 098 010 066 OOF by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt 011 068 00A 010 000 000 000 000 000 000 000 000 000 000 000 000 000 000 011 068 00B 11 tr D vd vd Q vd vd vd vd vd vd vd Q vd B vd BD DD vd PP vd Q vd PP p vd J J vd vd vd oO O vd vd vd vd vd vd B vd vd vd vd D vd vd end of right EQ for SW5 QUECKOK a E ARAKI ROR RR AER s IMPORTANT this line must be included 7 AAR line 1428 KKK k k k lt lt k k KKK ck ck ck KKK start of EQs for SW6 VOICE MSP430 Microcode Example 5 39 5 40 byt byt byt byt byt DS E byt byt by byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt
12. by by by by by by by by by by by by by by by by by by by by by by by byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt 000 000 000 000 000 000 011 068 014 010 000 000 000 000 000 000 000 000 000 000 000 000 000 000 011 068 015 010 000 000 000 000 000 000 000 000 000 000 000 000 000 000 011 068 016 010 000 000 000 000 000 J D oO D vd QQ vd vd D vd vd vd vd QQ vd vd vd vd vd vd vd vd vd vd vd vd vd vd vd BO BDP O vd vd vd vd DO vd vd BP vd DO DP D vd J hex number of bytes before next stop cmd hex number of bytes before next stop cmd hex number of bytes before next stop cmd MSP430 Microcode Example 5 47 byte 000 byte 000 byte 000 byte 000 byte 000 byte 000 byte 000 byte 000 byte 000 byte 011 byte 068 byte 017 byte 003 byte 085 byte OEA 07 OB D5 03 hex number of bytes before next stop cmd byte byte byte byte byte 085 byte OEA byte 0FB byte 014 byte 036 byte 003 byte 003 byte 076 byte 011 byte 068 byte 018 byte OOF byte ODA byte 043 byte OEO byte 04B byte 07A byte 00F byte ODA 43 EO 4B D3 oooooo hex number of bytes before next stop cmd byte byte byte byte byte
13. byt byt byt byt byt byt byt by byt byt byt byt byt byt byt byt byt byt byt byt OOF 011 08B 024 072 00D 015 012 028 00C 039 0D2 DA E o m H H o U o oo EEG D E A gt AE E er E 25 iiO D 0 9 00 OOO OO H HJ Fi s Hj H o HE o Ko D 011 068 PP P 42 P 2 PP d p Q Q PP o a2 si PD 20 Pp PD P 2 2 by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt OF2 011 068 OOF 045 04C 047 OFA 08B 06D 04E 061 DOC 02A OBE 002 OFB 055 o SO O 3 C2 O O H El wW o T QQ SH vd vd B vd vd vd DD vd vd vd vd J vd vd vd vd vd vd vd DO BP vd vd vd vd vd vd vd P vd vd vd vd vd vd end of left EQ for SW5 MSP430 Microcode Example 5 37 5 38 byt byt byt byt byt DS E byt byt by byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt
14. byt byt byt byt byt by byt byt byt byt byt byt byt byt byt byt byt byt 000 000 000 000 000 000 011 068 014 010 000 000 000 000 000 000 000 000 000 000 000 000 000 000 011 068 015 010 000 000 000 000 000 000 000 000 000 000 000 000 000 000 011 068 016 OOF 09A 01F OCB 0C2 D YP V J Q 4o Pp X3 vw 2 20 P P d P P O dd P p P P dd P P 2 d d P P P dd PD P PP J PP PP PP P d d d by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt 09A 01F OEO OCE 04A 00F 036 0C7 011 068 017 001 01D 002 03B 0A5 098 02A 00A 08C 09F I I T D D vd vd J vd D D vd Q vd vd vd vd Q vd D vd O vd vd D DD vd vd vd D vd vd vd vd vd vd vd BO DDD vd vd O BP DO vd PP B vd oo 000h 008h 068h 004h 000h end of right EQ for SW6 EE IMPORTANT this line must be included L REGE line 1645 lt Kk K x x lt k lt k k lt ck ck ck k ck ck ck ck ck x x vol setting MUTE MSP430 Microcode Example 5 43 5 44 byte byte byte byte byte byte byte byte byte byte
15. byte 000 line 578 Q Q dd OG P B PP J dd dd J Qd dd dd P P DD d D P P P J PD J PD Pp 232 d byte 011 byte 068 byte 00C byte 010 byte 000 byte 000 byte 000 byte 000 line 596 Q Qd d d 5 22 by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt 000 000 000 000 000 000 000 000 000 000 011 068 00D 010 000 000 000 000 000 000 000 000 000 000 000 000 000 000 011 068 OOF QQ vd vd vd B B B vd vd vd DD vd p p p J vd D D vd QQ L vd vd vd vd vd vd vd vd vd vd vd p 9 5 MSP430 Microcode Example 5 23 5 24 byt byt byt byt byt b t byt byt by byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt by byt byt byt byt byt byt byt byt byt byt byt byt 011 068 013 010 000 000 000 000 000 000 000 000 000 000 000 000 000 000 011 068 014 010 000 000 000 000 000 000 000
16. R14 used to track last manual setting of bass needed since bass reset to original with 2 EQs EE E Ke BE KC RIOR ERRE EREKE AER KR RRA ERA RRL SEE Ue OK RUE RAR I ARR al ee ain Program Sg OR IR APR OR AGREE PTR AIR RIE RIK RRR ERR IR AIK RRR ARIK R EE e e IK BOR KER AK RRR initialize stackpointer call device setup routine sw calibration of DCO set pointer to start of set up data call routine to send I2C b 4EXP amp P20UT set shutdown pin low after I2C code sent interrupts nabled after setup complete go into low pwr mode 3 after DS part is set up sect MAIN Main RESET MOV Stack SP CALL Setup CALL set DCO Begin MOV 1669 Tbl Pntr CALL Loop Finish BIC EINT LPM BIS LPM3 SR JMP LPM 5 2 back to low power mode after interrupt serviced E RR AIK E E GR KU OK UK NO UE ON AGUA IK KK ED A Set Up 11x ES Sa AR AE ARORA OE Kok e cour BBN UK oso ps ok kie seo Kk OR Kap ok aee edo Koo KD ot eoe oe ee Setup MOV WDTPW WDTHOLD amp WDTCTL stop watchdog timer MOV TASSEL1 CLR amp TACTL clock source for 16 bit timer of Timer_A SMCLK MOV b XTOFF DIVA1 RSEL2 RSELO amp BCSCTL1 ACLK 4 for DCO cal current in
17. last al setting 12C send routine SW4_FUNC SW4_TEST SW5_EQ Gl SW5 FUNC MOV Trbl Setpnt Trbl Pntr MOVTrbl Pntr Tbl Pntr CALL OOP CALL DELAY JMP MUTE_ OFE BIC b ED amp LED OUT CALL DELAY BIC b SWA amp SWA4 6IF P 370 Bass Pntr JEQ SW4 TEST SUB 5 Bass Pntr OV Bass Pntr Bass Setpnt OV Bass Pntr Tbl Pntr CALL Loop BIT b 4SW4 amp P2IN JZ SW4_FUNC BIS b ED amp LED OUT JMP SW DONE BIT b SW5 amp SW4 6IF JZ SW6 EO CALL DELAY2 BIT b SW6 amp SW4 6IF JNZ TRBL RST BIT b LED SLED OUT JNZ SW5 FUNC CALL MUTE ON CALL NOP9 OV 1211 Tbl Pntr CALL Loop CALL DELAYO OV Bass Setpnt Bass Pntr OV Bass Pntr Tbl Pntr CALL Loop OV Trbl Setpnt Trbl Pntr OV Trbl Pntr Tbl Pntr CALL OOP CALL DELAY JMP MUTE OFF BIC b ED amp LED OUT CALL DELAY BIC b SW5 amp SW4 6IF P 555 Trbl Pntr JEQ SW5 TEST ADD 5 Trbl Pntr MOV Trbl Pntr Trbl Setpnt set treb pointer back to last manual setting call I2C send routine jump to reset volume turn LED on delay before checking switch again clear SW4 flag minimum bass Yes jump to SW4 test decrease pointer to lower setting bass set point bass pointer tracks last manual bass setting set table pointer bass down data Call I2C send routine SW4 st
18. line must be included vol setting 22 line 220 IMPORTANT this line must be included vol setting s IMPORTANT th is line must be included vol setting 24 line 240 IMPORTANT this line must be included vol setting MSP430 Microcode Example 5 15 byte 004 byte 000 byte 048 byte 027 byte 000 byte 048 byte 027 byte 000 byte 008 byte 068 byte 004 byte 000 byte 050 byte OF4 byte 000 byte 050 byte OF4 byte 000 byte 008 byte 068 byte 004 byte 000 byte 05A byte 0D5 byte 000 byte 05A byte 0D5 byte 000 byte 008 byte 068 byte 004 byte 000 byte 065 byte OEA byte 000 byte 065 byte OEA byte 000 byte 008 byte 068 byte 004 byte 000 byte 072 byte 05A byte 000 byte 072 byte 05A byte 000 byte 008 byte 068 byte 004 byte 000 IMPORTANT th is line must be included vol setting 26 line 260 IMPORTANT this line must be included vol setting s IMPORTANT this line must be included vol setting 28 line 280 s IMPORTANT this line must be included vol setting s IMPORTANT this line must be included vol setting 30 line 300 Q Q 4 D P P wl P d ddd vw d P vd dd P P P P P ss vs dd P dd D P P PD PD d P P P PP 2 d P D PD PD Pp d d p by by by by by by by by by by by by by by by by by by by by by by by by by by
19. 0 03A 000 008 068 004 000 024 029 000 024 029 000 Boa P o dd B PD P dd ddd a Pp PD PP P P PD PP JD d vd 2 ppp J Boa dd P P vw vw d P P P d d d s IMPORTANT th is line must be included vol setting s IMPORTANT this line must be included vol setting 16 line 160 s IMPORTANT this line must be included vol setting s IMPORTANT th is line must be included PERERA line 180 c lt k k ck ck k lt lt k lt k lt k k KKK KKK vol setting 18 starting point IMPORTANT this line must be included vol setting IMPORTANT this line must be included by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt 008 068 004 000 028 093 000 028 093 000 008 068 004 000 02D 086 000 02D 086 000 008 068 004 000 033 014 000 033 014 000 008 068 004 000 039 050 000 039 050 000 008 068 004 000 040 04 00 04 04 000 008 068 DH o o tH QQ DO vd vd D D vd vd D D DD vd Q vd vd D Q vd vd vd vd vd vd vd vd vd Q Q D D D vd O O vd D vd D DD vd vd O vd d DD vd DD vd vd vd vd vol setting 20 line 200 s IMPORTANT this line must be included vol setting IMPORTANT this
20. 000 000 000 000 000 000 Q Q dQ P P PP 23 43 3 23 d d J Q d a2 P PD 2 PD 2 OQ PD PD PD d d p Q Qd dd PD vw PD 20 PD P d d 2 end of left EQ for SW2 by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt 000 011 068 015 010 000 000 000 000 000 000 000 000 000 000 000 000 000 000 011 068 016 010 000 000 000 000 000 000 000 000 000 000 000 000 000 000 011 068 017 003 085 007 00B 0D5 003 085 OFB 014 036 QQ QQ vd D D vd vd D D D vd Q D D D Q vd vd vd vd vd vd vd D vd Q O D D D vd O D vd D vd vd D vd vd O vd B PDP DP vd p vd vd vd MSP430 Microcode Example 5 25 5 26 by by by by by by by by by by by by by by by by by by by by by byt by by by by by by by by by by by by by by by by by by by by by by by by by by Boo 42 dd dd d dd P P d P dd d d p Q Qd we a P wl 23 42 p PP P p p PD PD P 2 dd PD PD 3 23 d p end of right EQ for SW2 SK R KEK
21. 68 006 053 000 003 068 006 04F 000 003 068 006 04B 000 003 vd vi o D D J 2 Q Qd dd P aX P ddd p JO P P P D p Pp P P P D P PD p P dd PD PD ppp d IMPORTANT this line must be included vol setting 36 max 0 dB line 360 IMPORTANT this line must be included AA END OF VOLUM E DATA x x TEREFE line 370 lt lt k k k k lt k k k x lt k lt k lt x lt x lt k bass setting 0 IMPORTANT this bass setting IMPORTANT this bass setting 2 IMPORTANT this bass setting IMPORTANT this bass setting 4 IMPORTANT this bass setting IMPORTANT this bass setting 6 IMPORTANT this bass setting minimum 9 db line must be included line must be included line 380 line must be included line must be included line 390 line must be included line must be included line 400 line must be included 068 006 046 000 003 068 006 042 000 IMPORTANT this line must be included bass setting 8 line 410 J vd IMPORTANT this line must be included ARRE line 415 KKRKKKKKKKKKKKKKKKKKKKKKKKKKKKK 003 068 006 03E 000 003 068 006 03B 000 003 068 006 038 000 003 068 006 035 000 003 068 006 031 000 003 068 006 02E 000 003 068 006 02B 000 003 068 006 028 000 003 068 006 bass setting 9 mid point starting point
22. 7 serial input option is set to MODE 5 24 bit 12S operation 2 4 TAS3001 Digital Equalization The TAS3001 stereo audio digital equalizer is a 32 bit digital audio signal processor It provides parametric equalization bass treble and volume control and dynamic range compression On the speaker equalization board the TAS3001 operates in slave mode at a 48 kHz sampling frequency As with the TLC320AD77 the serial audio format is 12S 2 5 Clock Generation A crystal oscillator provides the master clock for the speaker equalization board The oscillator runs at 12 288 MHz and provides a 50 duty cycle square wave at 3 3 V peak amplitude The other IIS timing signals are provided by circuitry in the TAS3001 2 6 System Microcontroller 2 2 An EPROM version of the MSP430E112 with 4K bytes of memory is used to control the system because it can be erased and reprogrammed Future versions of this board will contain the flash memory version of the MSP430 Chapter 2 Board Operation This chapter describes the equalization board operation Topic Page 3 1 Power Up Sequence o e 3 2 3 2 Switch Functions for Digital Equalization 3 2 3 3 Software GUI e da a 3 3 3 4 sofiwarelnstallatlon 5200020200000 3 3 3 1 Power Up Sequence 3 1 Power Up Sequence The following is the power up sequence for the speaker equalization board L Insert either the MSP430 microcontroller or the DB25 PC interfac
23. CL low CALL NOP9 delay low portion of clock BIC B SDA amp SDAEN set SDA high CALL NOP 9 delay BIC B SCL amp SCLEN set SCL high H jmp skip2 HEP DS busy2 BIT b 4SCL amp SCLIN test if DS part busy C 0 JNC DS busy2 yes loop again skip2 J gt gt gt D gt DD gt D gt DDD D gt DDD D gt DDD D gt D gt DDD DDD DDD DDD D gt DDD D gt DDD gt gt DDD DDD DDD DDD D gt DDD gt gt DDD gt gt gt gt gt gt gt gt gt PREKARAKKAEAAEAKAKKEKK Shift mask test for end of byte I2C Send3 CLRC clear carry bit RRC B Mask shift 0 into MSB shift 1 right JNCI2C Sendl 1 shifted into carry No Jump sendl CALL NOP9 extend SCL pulse before ackn JMP pointers gt gt gt pE Check acknowledge signal from DS part I2C Ackn BIS B SCL amp SCLEN set SCL low for Acknowledge Bit BIC B SDA amp SDAEN set SDA high master releases SDA CALL NOP8 extend SCL low before ackn BIC SCL amp SCLEN set SCL high master releases SCL Ackn_Test BIT l SDA amp SDAIN test for ackn in carry bit 0 Ackn JC Ackn_Test no ackn C 1 test again for acknowledge BIS b SDA amp SDAEN hold SDA line low after Ackn UJ UJ pE Change pointers check for end of string pointers J gt gt gt gt gt gt gt gt DDD D gt DDD D gt D gt DDD D gt DDD DD DDD DDD DD DDD DD D gt DDD D gt DDD D gt DDD D gt DDD gt g
24. ED OUT JNZ SW4 FUNC CAL MUTE ON CALL NOP9 OV 994 Tb1_Pntr CAL Loop CALL DELAYO OV Bass_Setpnt Bass_Pntr OV Bass_Pntr Tbl_Pntr CALL Loop jump SW3 function before sending EQ delay befor poet Jump manu call manu call jump turn delay befor sending EQ table pointer to start of SW3 1 to I2C send routine tpnt Bass Pntr set bass pointer back to last al setting I2C send routine tpnt Trbl Pntr set treb pointer back to last al setting I2C send routine to rest volume LED on checking switch again clea bass Yes incrf bass strac set Call SW3 YES turn Jump set set Jump Jump send SW4 iNO dela r SW3 flag maximum jump to SW3_test ease pointer to higher setting set point bass pointer ks last manual bass setting bass up data I2C send routine table pointer still pressed active low increase bass ED off to end of SW routine bass pointer to startup bass bass startup to I2C send routine to end of SW routine table pointer EQ pressed jump to next SW SW3 YES LED NO mute y before checking SW6 pressed also jump to reset bass shift mode jump SW4 function on before sending EQ dela set jump set manu call y before sending EO table pointer to start of SW4 1 to I2C send routine bass pointer back to
25. ESE no source word RESE no source word RESE NMI Osc fault word RESE POR ext Reset Watchdog MSP430 Microcode Example 5 49 5 50 Appendix A Schematics This appendix includes a schematic diagram of the TAS3001 EVM A 1 A 2
26. IMPORTANT this line must be included bass setting 10 line 420 IMPORTANT this line must be included bass setting IMPORTANT this line must be included bass setting 12 line 430 IMPORTANT this line must be included bass setting IMPORTANT this line must be included bass setting 14 line 440 IMPORTANT this line must be included bass setting IMPORTANT this line must be included bass setting 16 line 450 IMPORTANT this line must be included bass setting D vd vd vd vd vd vd D DD vd dd vd vd vd vd vd vd vd vd vd vd vd vd vd vd vd vd vd P vd DO vd vd vd vd vd vd BP vd vd vd MSP430 Microcode Example 5 20 by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by 025 000 003 068 006 021 000 003 068 005 084 000 003 068 005 082 000 003 068 005 080 000 003 068 005 07E 000 003 068 005 07C 000 003 068 005 07A 000 003 068 005 078 000 003 068 005 076 000 003 068 J J J 425 PP PP P P P P P d P P P 42 2 D dd dd d P PP B dd P P dd d d PD p Pp PD p P IMPORTANT this line must be included IRA line 460 KKRKKKKKKKKKKKKKKKKKKA A bass setting 18 IMPORTANT this line maximum 9 dB must be incl
27. M The user s guide contains descriptions and schematics for a stereo application How to Use This Manual This document contains the following chapters Chapter 1 Overview Chapter 2 System Components Chapter 3 Board Operation Chapter 4 TAS3001 EVM Block Diagram Chapter 5 MSP430 Microcode Example L U E U C L Appendix A Schematics Notational Conventions This document uses the following conventions Program listings program examples and interactive displays are shown ina special typeface similar to a typewriter s Here is a sample program listing RESET MOV Stack SP initialize stack pointer CALL Setup call device setup routine CALL Set_DCO sw calibration of DCO Related Documentation From Texas Instruments Related Documentation From Texas Instruments L TLC320AD77 Literature Number SLAS194 L TAS3001 Literature Number SLAS226 Y MSP430E112 Literature Number SLAS219 L TPS7233 Literature Number SLVS102F L TLV2362PWR Literature Number SLOS195B FCC Warning This equipmentis intended for use in a laboratory test environment only It gen erates uses and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules which are designed to provide reasonable protection against radio frequency interference Operation of this equipment in other en vironments may cause interference with radio communications in which ca
28. NK BARK NUR OE Oeo E OK Ree E KE UN IMPORTANT this line must be included QUE line 777 kk kk kk kk start of EOS for SW3 FLAT2 by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt 091 00F 0A1 020 07F 091 00F 081 09A 033 006 093 085 OFA 065 075 003 017 OE 011 068 00E T QQ SH DO vd P vd vd B DP p vd DD vd vd PD vd J Q vd D D vd vd vd vd DD vd B D vd vd vd DD vd p p p 9 MSP430 Microcode Example 5 27 n EQ for SW3 I end of left n e 010h e 001 F P e 098h e OE 0h e 010h e 066h e 00Fh e OE Elh EOh e 059h e OE e 010h e 066h e 00Fh e OE EFh e 0F2h Oh e Olih e 068h e 00Fh e 010h e 010h e 02Bh e OE I EOh Ah H e 015h e OF6h e 00Fh e ODAh e 070h e OE e 015h e OF6h e 00Fh e OE e 09Bh e Olih e 068h e 013h e 00Fh e 056h e OE E8h E2h e OE e 0A7h e 053h e 001 F B e 045h e OE E6h 2h D e OE e 0A7h e 053h e 00Dh e 09Ch by by by by by by by by by by
29. OR b LED amp LED_OUT LED switched back to original state off at start up on in shift EQ mode RET return from call PTE ROR IRENE Koc ue dp KB Sau RR OR KC HN Ra NER UR Kk osea RN v abe COLO INK SKK UD D oO arie coole A I2C subroutines T EE CAR AAR AK RRA de OE KOC NE SKK E AER E ARG ROK E IK PRI Nae Ke RIT SKA RIK E KO KEK BRAK send start set up mask I2C BIS B SDA amp SDAEN start Condition set SDA low INC Tbl Pntr increment to first data byte in string 5 4 CALL NOP 9 delay before SCL for start low I2C Send MOV b 80h Mask bit mask MSB bit first PERE KK RAIN E NURSE test Dat send SC low 12C Sendl BIT B Mask Data Tbl Pntr bit 1 JC 12C_Send2 jump if bit 1 BIS B SCL amp SCLEN data is 0 SCL low CALL NOP9 delay low portion of clock BIS B SDA amp SDAEN set SDA low BIC B SCL amp SCLEN set SCL clock high jmp skipl J gt gt gt gt gt gt gt gt D gt DDD DDD D gt D gt DDD D gt DDD DD DDD DD DDD DDD DDD DDD DDD DDD DDD DDD DD gt gt DD gt gt gt D gt gt gt gt gt gt gt gt gt gt DS_busy BIT b SCL amp SCLIN test if DS part busy C 0 JNC DS busy yes loop again skipl PPP AA DDD DD DDD DDD DD DDD DDD DDD DDD DDD DDD DDD DDD DDD DDD DDD DD gt gt gt gt gt gt JMP I2C Send3 IRA Kok RERE e RR S send high bit I2C Send2 BIS B 4SCL amp SCLEN data bit 1 set S
30. OV 1428 Tbl Pntr CALL OOP CALL DELAYO OV 415 Tb1_Pntr CA OOP OV 510 Tbl Pntr CALL oop CALL DELAY JMP MUTE OFF BIC b ED LED_OUT CALL DELAY BIC b SW6 amp SW4_6I1F CMD 465 Trbl Pntr JEO SW6 TEST SUB 5 Trbl Pntr OV Trbl Pntr Trbl Setpnt OV Trbl Pntr Tbl Pntr CALL Loop BIT b SW6 amp P2IN JZ SW6 FUNC BIS b ED LED_OUT CALL DELAY BIC b SW1 SW2 SW3 amp SW1_31F tracks last manual treble setting set table pointer treble up data Call I2C send routine SW5 still pressed YES active low turn LED off increase treble jump to reset volume set table pointer to startup treble set table pointer treb startup jump to I2C send routine jump to end of SW routine test for SW6 OR SW1 6 pressed SW6 pressed NO jump to SW ISR done delay befor testing 2nd SW SWl pressed also YES jump to toggle LED delay before checking SW5 SW5 pressed also Y L D ES LED on NO jump to reset treble shift mode jump SW6 function EQ EQ table pointer to s I2C send mute before sending delay befor sending of SW6 E set Cart call routine set table pointer to startup bass setting jump to I2C send routine set table pointer to s tartup treble setting jump to I2C send routine jump to reset volume turn LED on
31. a PC The cable must have all 25 wires connected not an RS232 extender cable and the parallel port on the PC must be set to the EPP mode If the EPP mode is not available the bidirectional or PS 2 mode will work in most cases The TAS3001 EVM is shipped with the 50 2 resistor installed If stand alone operation is desired an MSP430 microcontroller can be requested from the digital speaker group at Texas Instruments 214 480 3362 This system receives and transmits digital data at a 48 kHz sampling frequency Features 1 2 Features The speaker equalization board has the following features 12 V to 18 V V dc power supply operation Onboard 3 3 V regulator TAS3001 stereo audio digital equalizer Operation via either a preprogrammed MSP430 microcontroller or via a PC through a DB25 male male cable and software program O U C U Six switches used to control volume bass treble and equalization Mute control LED indicates mode of operation A 12 288 MHz master clock frequency 1 Vrms line input and output analog stereo signals sampled at 48 kHz 24 watts per channel stereo differential output audio power amplifier Diagnostic indicator CLIP LED L D D D U U U 1 3 Environmental Working Conditions The circuit is designed to operate in an office type environment 1 4 Description of Inputs The speaker equalization board uses a 3 5 mm stereo jack for its input It requires a stereo analog signal input The analog input ranges f
32. by by by by by by byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt 00B 06F 000 008 068 004 000 DOC 0D5 000 DOC 0D5 000 008 068 004 000 00E 065 000 00E 065 000 008 068 004 000 010 027 000 010 027 000 008 068 004 000 012 020 000 012 020 000 008 068 004 000 014 056 000 014 056 QQ QQ vd D vd DD vd vd vd D vd Q vd vd vd Q vd vd vd vd vd D vd D vd vd D vd vd O vd B vd vd DD vd vd vd vd IMPORTANT this line must be included vol setting 10 line 100 IMPORTANT this line must be included vol setting 11 25 dB IMPORTANT this line must be included vol setting 12 line 120 IMPORTANT this line must be included vol setting IMPORTANT this line must be included vol setting 14 line 140 MSP430 Microcode Example 5 13 5 14 by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by 000 008 068 004 000 016 0D1 000 016 0D1 000 008 068 004 000 019 09A 000 019 09A 000 008 068 004 000 01C 0B9 01C 0B9 000 008 068 004 000 020 03A 000 02
33. byt byt byt byt byt byt byt byt byt byt byt by byt byt byt byt byt byt byt byt byt byt byt byt 010 000 000 000 000 000 000 000 000 000 000 000 000 000 000 011 068 00C 010 000 000 000 000 000 000 000 000 000 000 000 000 000 000 Joa P 2 P JO D H Q d dd vw 2 PD PP PP dd PD PD PD 2 d Q Q d ooa o PD 2 20 ddd 2 2 2 by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt 0C7 011 068 00E 001 01D 0D2 002 03B 0A5 026 006 07D 023 011 068 00F 039 06E OCA 099 027 059 02E 08E 0A5 0E 098 02A 00A 08C 09F 011 068 013 010 000 000 000 000 000 000 000 000 QQ SH vd vd P vd B vd B vd vd vd DD vd vd vd vd J vd PP vd vd vd end of left EQ for SW6 MSP430 Microcode Example 5 41 5 42 byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt
34. c to power the operational amplifiers and a TPS7233 LDO to convert the 5 V power to 3 3 V to power the MSP430 the TAS3001 andthe TLC320AD77 All power input pins are decoupled with 0 1 uF capacitors Input Amp and Bias The input to the TLC320AD77 codec is a differential signal and the input to the speaker equalization board is a single ended stereo signal The analog front end buffers the input signal and provides 1 6 V dc for the ADC The section input amplifier and bias on the schematic Figure 4 1 describe the analog front end circuit and a single pole low pass antialiasing filter The antialiasing filter attenuates unwanted frequencies out of the range of the ADC The analog front end is independently preformed on the left and right channels via a TLV2362PWR dual high performance low voltage operational amplifier The antialiasing filter is created through a combination of resistors and capacitors on the input of the ADC 2 3 TLC320AD77 ADC DAC Functions The speaker equalization board takes an analog stereo audio input signal and converts it to digital so that digital equalization can be performed The digital signal is then converted back into analog and sent to an external device The analog to digital A D and digital to analog D A functions are performed by the TLC320AD77 stereo audio ADA The TLC320AD77 is a stereo A D and D A 24 bit delta sigma converter The TLC320AD77 operates at a 48 kHz sampling frequency The TLC320AD7
35. cill enable active high RST set 001h P1 0 functions as MIC board reset active low s RESET already used elsewhere in this program EXP set 008h P2 3 functions as expand active high j KKKKKKKKKKKKKKKKKKKA Key switch LED pins amp registers SW1 egu 08h P1 3 equates to switch 1 active low SW2 egu 04h FRU i 2 4 SW3 equ 02h SERA Nt NM 3 d Sw4 egu 01h P2 0 qe L 4 i SW5 egu 02h P2 1 rat 5 dd SW6 equ 04h P2 2 my OS 6 g SW1_3IF egu 023h SW1 3 int flags Pl int flag register P1IFG SW4_6IF egu 02Bh SW4 6 int flags P2 int flag register P2IFG SW1 3IE equ 025h SW1 3 int enables P1 int enable register P1IE SW4 GIE egu 02Dh SW4 6 int enables P2 int enable register PIIE SW1 31N egu 020h SW1 3 inputs Pl input register P11N SW4 GIN egu 028h SW4 6 inputs P2 input register P11N ED egu 020h P2 5 equates to LED pin active low JED OUT egu 029h LED data out P2 output register P20UT Vol Pntr egu R9 pointer for volume setting data table position Bass Pntr equ R10 pointer for bass setting data table position Trbl Pntr equ R11 pointer for treble setting data table position UTE equ R12 current mute setting O mute off l mute on Trbl Setpnt equ R13 used to track last manual setting of treble needed since treble reset to original with 2 EQs Bass Setpnt equ
36. d TEXAS INSTRUMENTS TAS3001 EVM User s Guide February 2001 Digital Speaker Products SLAU060 IMPORTANT NOTICE Texas Instruments and its subsidiaries Tl reserve the right to make changes to their products or to discontinue any product or service without notice and advise customers to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment including those pertaining to warranty patent infringement and limitation of liability Tl warrants performance of its products to the specifications applicable at the time of sale in accordance with T s standard warranty Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty Specific testing of all parameters of each device is not necessarily performed except those mandated by government requirements Customers are responsible for their applications using Tl components In order to minimize risks associated with the customer s applications adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards Tl assumes no liability for applications assistance or customer product design Tl does not warrant or represent that any license either express or implied is granted under any paten
37. dd P 3 JJ E o HJ H O U JU o p El Q QUO oO OO OO 0 EN 0 8 0 0 0 02 EN Ho t Lb p HJ H H L L L HJ Hj O U HE o VO D 000 J d end of ri ght EQ for SW3 EE e KAREE ES IMPORTANT this line must be included ERRER line 994 KAXKKKKKXKAKKKKXKKKKKXXk start of EQs for SW4 JAZZ by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt OE 00F 00 OD 012 DEI U HE J vd vd D oO vd vd vd vd vd vd vd vd vd vd vd vd vd vd vd PP vd vd vd PP vd HD p 099 00E 06B DCH 011 068 00B 00F 01 08 072 011 068 DOC 010 004 04D OEO 00B 034 OOF 08A 00B 035 00F DER 0D6 011 068 00D QQ SH vd vd vd vd vd vd vd vd DD vd D vd p 9 K MSP430 Microcode Example 5 31 5 32 byt byt byt byt byt ByE byt byt by byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt by byt byt byt byt byt byt byt byt
38. delay before checking switch again clear SW6 flag treble minimum Yes jump to SW6 test decrease pointer to lower setting treble set point trebl pointer tracks last manual treble setting treble down data call I2C send routine SW6 still pressed YES active low turn LED off complete interrupt sevice routine set table pointer decrease bass delay for switch debounc Clear SW1 3 interrupt flags when released P1IFG R ETI BIC b SW4 SW5 SW6 amp SW4_6IF clear SW4 6 interrupt flags P2IFG EINT enable interrupts return from ISR EE E ER ARR ROR A RA Data to be sent to Digital Speaker part via I2C E A E A A E Data EVE by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt 008 068 004 000 000 000 000 000 000 000 008 068 004 000 004 08D 000 004 08D 000 008 068 004 000 005 01C 000 005 01C 000 008 068 004 000 005 OBB 000 005 OBB 000 008 068 004 000 006 J DD Q D D DO QQ D vd Q D vd Q vd vd P vd vd D vd DD vd vd B B vd B vd vd DP vd Q vd vd vd vd vd Align following section on even address vol setting 0 mute IMPORTANT this line must be included line 10
39. e Original egualization Flat egualization Jazz egualization Rock egualization Voice egualization 3 3 Software GUI When the MSP430 microcontroller is replaced by the DB25 cable the programming of the TAS3001 egualization can now be done through the software GUI program via a PC In the software GUI operation mode the six onboard switches are disabled and the six bands of digital egualization volume control bass and treble are programmed via the software Refer to the software GUI user s manual for instructions on the use of this feature 3 4 Software Installation 1 Setthe parallel port on the PC to the EPP mode If the EPP mode is not available bidirectional or PS 2 mode works in most cases 2 Create a directory on the PC and install the contents of the supplied disk in it 3 Run the exe file and follow the steps on the screen Board Operation 3 3 3 4 Chapter 4 TAS3001 EVM Block Diagram This chapter presents the TAS3001 EVM block diagram and the printed circuit board PCB silk screen Topic Page 4 1 TAS3001 EVM Block Diagram 4 2 4 3 4 2 PCB Silkscreen 4 1 TAS3001 EVM Block Diagram 4 1 TAS3001 EVM Block Diagram Figure 4 1 shows the TAS3001 block diagram Figure 4 1 TAS3001 EVM Block Diagram 3 5 mm Line_Out TLC320AD77 E P D L Speaker_Out ifier f RCA Power Ampli D 3 5 mm pet Line In t1 VMID
40. e cable into the socket provided on the board verifying the position of pin 1 Connect 15 V dc to the positive terminal of the power supply jack and con nect a ground to the negative terminal L Turn on the power supply and verify that the board draws a current of less than 150 mA _j Turn off the power L Connecta 1 Vrms analog signal to the 3 5 mm stereo input jack This input can be provided either through a signal generator or through a CD player or other sound generation equipment some CD players provide up to 2 Vrms which causes distortion Connect the output to amplified stereo speakers via the 3 5 mm stereo output jack This output can be measured by a signal analysis or played through speakers Alternately connect passive speakers to the amplifier s output terminals RCA connectors Turnon the power to the speaker equalization board and verify again that it draws less than 150 mA of current after the board is initialized by the microcontroller or by the software GUI L Turn on the power to the input and output devices L Depending on the selected mode of operation either through the MSP430 microcontroller or through the software GUI program and the DB25 cable introduce equalization to the input analog signal The instructions for the microcontroller mode of operation are described in sec tion 3 2 and the instructions for the software are described in section 3 3 3 2 Switch Functions for Digital E
41. er equalization board contains a two channel 24 watt per channel audio power amplifier The output of the power amplifier is differential therefore there are no capacitors in its output circuit that could limit its low frequency response The output of the power amplifier is connected to RCA connectors Since the amplifier has a differential output both terminals of the connection contain the amplified signal Ensure that neither of these contacts is connected to ground The power amplifier also contains an LED labeled CLIP in the silkscreen on the PCB The LED illuminates when the maximum output power is exceeded or when one of the outputs is shorted to ground Six switches are used to program the digital equalization of the TAS3001 via the MSP430 microcontroller The microcontroller provided with this board is preprogrammed for five different EQ settings that can be selected via different combinations of the switches The switches and EQ settings are described in Section 3 2 This microcontroller in conjunction with the six switches can also adjust the volume bass and treble settings of the TAS3001 The settings for changing the volume bass and treble levels are described in Section 5 2 The MSP430 is placed in a socket so that it can be replaced with a 50 Q resistor between pins 7 and 13 to reset the board The board can then be controlled through the DB25 connector A 25 pin DB25 male at both ends is then connected between the EVM and
42. ill pressed YES active low turn LED off jump to end of SW routine send EQ SW5 pressed NO decrease bass jump to next SW delay before checking SW6 SW6 pressed also YES jump to reset treble LED on shift mode NO jump SW5 function mute before sending EQ delay befor EQ set table pointer to start of SW5 E jump to I2C send routine sending set bass pointer back to last manual setting call I2C send routine set treb pointer back to last manual setting call I2C send routine jump to reset volume curn LED on delay before checking clear SW5 flag treble switch again maximum Yes jump to SW5 test increase pointer to higher setting treble set point treble pointer MSP430 Microcode Example 5 9 SW5_TEST TRBL_RST SW6_EQ SW6_FUNC SW6_TEST SW_DON E 5 10 OV Trbl Pntr Tbl Pntr CALL Loop BIT b SW5 P2IN JZ SW5 FUNC BIS b ED SLED OUT JMP SW DONE OV 510 Trbl Pntr OV Trbl Pntr Tbl Pntr CALL Loop JMP SW DONE BIT b SW6 amp SWA4 GIE JZ SW_DONE CAL DELAY2 BIT b SW1 amp SW1 3IF JNZ OG LED CAL NOP9 BIT b SW5 amp SW4_6IF JNZ TRBL_RST BIT b ED amp LED_OUT JNZ SW6 FUNC CAL UTE ON CALL NOP9
43. lock Diagram 4 2 PCB Silkscreen Tables 3 1 Switch Functions for Speaker Equalization cn vi Chapter 1 Overview The TAS3001 EVM board demonstrates the operation of the digital equalization and the dramatic improvements that 32 bit digital audio signal processing can make on sound quality Topic Page Uer HEH 1 2 e Tee 1 3 1 3 Environmental Working Conditions 1 3 14 Descriptlon ot inputs Pie gne EE 1 3 1 5 S Descriptionrof Outputs mnn nn n n 1 3 16 Power Supply usss E 1 3 Description 1 1 Description This user s guide describes the operation of the TAS3001 EVM The user s guide contains descriptions and schematics for a stereo application The board described is an example design that can be customized for specific ap plications An analog stereo input signal is provided through a 3 5 mm stereo jack The left and right channels of the signal are filtered and converted into left and right digital signals via the TLC320AD77 s analog to digital converter The digital signals are then equalized by the TAS3001 and converted back to analog via the TLC320AD77 s digital to analog converter The analog left and right signals are amplified at the output stage and piped to the line output to drive amplified speakers via a 3 5 mm stereo jack The output stage is capable of driving internally amplified speakers or a stereo amplifier s line input Additionally the speak
44. luded treble setting 9 IMPORTANT this treble setting IMPORTANT this treble setting IMPORTANT this treble setting IMPORTANT this treble setting IMPORTANT this treble setting IMPORTANT this treble setting IMPORTANT this treble setting IMPORTANT this treble setting IMPORTANT this PEERKE ne 555 treble setting line line line line line line line line line BEINAR line 510 KKK KKK KKK KKK KK KK KK KKK KK KK KK KK starting point x must be included must be included line 520 must be included must be included line 530 must be included must be included line 540 must be included must be included line 550 must be included x K k ck k lt k k ck ck k lt lt lt ck lt kk k ck 18 maximum 9 dB MSP430 Microcode Example 5 21 byte 005h byte 055h byte 000h IMPORTANT this line must be included Se ee END OF TREBLE DATA KKKKKKKK KKK EROS line 560 KKK KKK KKK KK KK ck k KK KK byte 011 start of EQs for SW2 ORIGINAL byte 068 byte 00A byte 010 byte 000 byte 000 byte 000 byte 000 byte 000 byte 000 byte 000 byte 000 byte 000 byte 000 byte 000 byte 000 byte 000 byte 000 byte 011 byte 068 byte 00B byte 010 byte 000 byte 000 byte 000 byte 000 byte 000 byte 000 byte 000 byte 000 byte 000 byte 000 byte 000 byte 000 byte 000
45. m Ee Definitions eer E TS B RO EUR ER RR AIN Stack EQU 00210h I_vectors EQU OFFFFh Main EQU 0F000h PAR GE Pk ek oit e ok ATEN EKKA R SCL EQU 010h SDA EQU 020h SCLI EQU 020h SDAI EQU 020h SCLDA EQU 021h SDADA EQU 021h SCLE EQU 022h SDAE EQU 022h SCLFUNC EQU 026h SDAFUNC EQU 026h 11x standard locations stackpointer Interrupt vectors in ROM ROM start on x112 I2C pins and I O registers P1 4 functions as SCL line pull up required P1 5 functions as SDA line pull up required clock in Pl input register P1IN data in P1 input register P1IN clock out Pl output register P10UT data out P1 output register P10UT clock enable P1 direction register P1DIR data enable Pl direction register P1DIR fuction P1 function select register P1SEL fuction P1 function select register P1SEL 5 1 PR A I2C register Tbl Pntr EQU R4 pointer for position in total data table Strng Pntr EQU R5 pointer for position in current byte string Mask EQU R6 used to test level of bits in data byte PE k DCO calibration definitions Countl set R7 Counter for SW DCO calibration Count2 set R8 Counter for SW DCO calibration Delta set 150 SMCLK 1 228 800 Hz pER Speaker Equal board definitions OSC OE set 080h P1 7 functions as os
46. qualization 3 2 When the speaker equalization board is used with an MSP430 microcontroller the seven onboard switches allow users to adjust the digital equalization the volume the base and the treble of the audio input signal The MSP430 microcontroller is preprogrammed with five different equalization effects original or no EQ flat EQ jazz EQ rock EQ and voice EQ Since these equalizations are created for a specific type of speaker they must be reprogrammed for your speakers The microcontroller is also preprogrammed to increase or decrease the system volume bass and treble by 1 dB There is also a preprogrammed mode that independently resets the bass and the treble to O dB Users can toggle back and forth between EQ mode and volume bass treble mode by alternately depressing SW1 and SW6 simultaneously The LED is on when the board is in EQ mode and off when the board is in volume bass treble mode The first switch on the left performs the shift function It switches the microcontroller between volume bass treble and equalization modes Alternately the shift function can be performed by pressing switches 1 and 6 Software GUI Table 3 1 describes the operation of the switches and the LED Table 3 1 Switch Functions for Speaker Equalization VOL BASS TREBLE MODE Volume up 1 dB Volume down 1 dB Bass up 1 dB Bass down 1 dB Bass reset 0 dB Treble up 1 dB Treble down 1 dB Treble reset 0 dB EG MODE Mut
47. rom ground to a maximum of 1 Vrms 1 5 Description of Outputs 1 5 1 Line Output The line output uses a 3 5 mm stereo jack The output is a stereo analog audio signal with a 1 Vrms level The output can drive amplified speakers or the line input of a stereo amplifier 1 5 2 Power Amplifier Output The power amplifier output uses two RCA type connectors The power amplifier output signal is capable of driving 4 2 to 8 2 speakers The maximum power amplifier output is 24 watts per channel 1 6 Power Supply The power supply for the speaker equalization board is 12 V to 18 V 15 V nominal The board draws an average current of about 0 250 A when driving speakers and less than 100 mA with no speakers connected The board can draw greater than 2 5 A peak current when driving speakers at a high volume Overview 1 3 1 4 Chapter 2 System Components This chapter presents an overview of the system components Topic Page 2 1 Power Supplies and Decoupling 2 2 2 2 PUTA Mp ue Bda FF FF 2 2 2 3 TLC320AD77 ADC DAC Functions 2 2 2 4 TAS3001 Digital Equalization 2 2 2 5 K Clock Generations EE le ali E a 2 2 2 6 System Microcontroller 2 cece eee e eee nn 2 2 2 1 Power Supplies and Decoupling 2 1 Power Supplies and Decoupling 2 2 The system uses a TL78MO5 linear regulator to convert the 12 V dc input to 5 V d
48. se the user at his own expense will be required to take whatever measures may be required to correct this interference Contents OVER VIO e EE 1 1 1 1 DeSCrIptlOn cit A 1 2 1 2 GIE 1 3 1 3 Environmental Working Conditions akan 1 3 1 4 Description of Inputs 1 3 1 5 Description of Outputs 1 3 1 52 Bine Output xu eis ST ee AR aa epu aaa 1 3 1 5 2 Power Amplifier Output 1 3 1 0 Power Supply Mace Meee ye dae nese de mek pees ads ia 1 3 System Components xe e x x K e e x cece eee eee eee eee 2 1 2 1 Power Supplies and Decoupling kakan 2 2 2 2 nput Amp and Blas cuicos ci A 2 2 23 TLC320AD77 ADO DAC Functions kaka aaa 2 2 2 4 TAS3001 Digital Equalization 2 2 2 5 Clock Generation 2 2 2 6 System Microcontroller 2 2 Board Operation 221 5 a daa NY 3 1 3 1 Power Up Sequence asiaa siar San been cee dera dad 3 2 3 2 Switch Functions for Digital Equalization 3 2 K Software GUI ev fae i a a MUR Dr a Dn 3 3 3 4 Software Installation 3 3 TAS3001 EVM Block Diagram oooooocccccocon nnm nnn 4 1 4 1 TAS3001 EVM Block Diagram 00 ccc n 4 2 42 RG Beete shee Yoko re Lal aed mesa RE 4 3 MSP430 Microcode Example 5 1 Schematics a S 29 eater Men a dee A 1 Figures 4 1 TAS3001 EVM B
49. t DDD gt gt DDD gt gt gt gt gt gt gt gt gt INCTb1_Pntr increment table pointer next byte in table DECStrng_Pntr decrement string pointer JNZI2C Send if not 0 then send next byte A jmp tempend J D gt gt gt D gt gt gt DDD D gt DDD DDD DDD D gt DDD DDD DDD DDD D gt DDD D gt DDD DDD DD gt gt DDD D gt DDD DDD DD gt gt gt DD gt gt gt D gt gt gt gt gt MSP430 Microcode Example 5 5 R ET gt gt gt gt o gt gt gt gt PRR EE ER ERA EA IA stop Condition set SDA set SCL low low Delay 18 cycles before issuing stop set SCL test if ryes set SDA high DS part busy C 0 loop again high PPO gt gt gt gt gt gt gt OOP OP OP POP POOP OP OO OO PO OO OO OO OO OO OO PO OO OP PO OO PO OOO OO PO OO OOOO OO gt Oo gt gt gt gt 9 cycles delay I2C Stop BIS B SDA amp SDAE BIS B SCL amp SCLE CALL NOP9 CALL NOP9 BIC B SCL amp SCLE DS busy3 BIT b SCL amp SCLI JNCDS_busy3 CALL NOP 9 BIC B SDA amp SDAE tempend RET SIE KOK REE EK KK Oe Kk OR OK delays routines NOP9 NOP NOP8 RET F 8 cycles delay E A RS aki E RS Sai u Be ale koa UR Key switch interrupt service routine FORA BRK FRE E ba Ski kia u S akata oii Eo SRK KA SW ISR SW1 FUNC SW1 FUNC2 SW1 TE TOG LI E SW1 MOT 5 6 start of interrupt service routine for ke
50. t right copyright mask work right or other intellectual property right of Tl covering or relating to any combination machine or process in which such products or services might be or are used T s publication of information regarding any third party s products or services does not constitute Ts approval license warranty or endorsement thereof Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Representation or reproduction of this information with alteration voids all warranties provided for an associated TI product or service is an unfair and deceptive business practice and TI is not responsible nor liable for any such use Resale of T s products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service is an unfair and deceptive business practice and Tl is not responsible nor liable for any such use Also see Standard Terms and Conditions of Sale for Semiconductor Products www ti com sc docs stdterms htm Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright O 2001 Texas Instruments Incorporated Preface Read This First About This Manual This user s guide describes the operation of the TAS3001 EV
51. ter to lower setting OV Vol Pntr Tbl Pntr set table pointer Vol down data CALL OOP call I2C send routine BIT b SW2 amp Pl1IN SW2 still pressed JZ SW2 FUNC YES active low decrease volume BIS b ED amp LED_OUT turn LED off JMP SW DONE jump to end of SW routine send EQ BIT b SW3 amp SW1_3I1F SW3 pressed JZ SW4 EO NO jump to next SW CALL DELAY2 delay before testing 4th SW BIT b SW4 amp SW4_6IF SW4 pressed also JNZ BASS_RST YES jump to reset bass BIT b LED amp LED OUT LED on shift mode MSP430 Microcode Example 5 7 SW3_FUNC SW3 TI EST BASS RST Sw4 9 8 HE JNZ SW3 FUNC NO CAL MUTE ON mute CA NOP 9 OV 777 Tb1l_Pntr CAL Loop CALL DELAYO OV Bass_Se OV Bass_Pntr Tbl_Pntr CALL Loop OV Trbl_Se OV Trbli Pntr Tbl Pntr CAL oop CAL DELAY JMP MUTE OFF BIC b ED amp LED_OUT CALL DELAY BIC b SW3 amp SW1_3IF CMP 460 Bass_Pntr JEQ SW3_TEST ADD 5 Bass_Pntr OV Bass_Pntr Bass_Setpnt OV Bass_Pntr Tbl_Pntr CALL Loop BIT b SW3 amp P1IN JZ SW3_FUNC BIS b ED amp LED_OUT JMPSW DONE OV 415 Bass Pntr OV Bass Pntr Tbl Pntr CALL Loop JMP SW DONE BIT b 4SW4 amp SW4 6IF JZ SW5 EO CALL DELAY2 BIT b 4SW3 amp SW1 S3IF JNZ BASS RST BIT b LED amp L
52. ting for bass OV 415 Bass_Setpnt initial setting for bass OV 510 Trbl_Pntr initial setting for treble OV 510 Trbl_Setpnt initial setting for treble CLR MUTE set mute 0 initial state of mute off BIC b SW1 SW2 SW3 amp SW1_3IF clear SW1 3 interrupt flags P1IFG BIC b SW4 SW5 SW6 amp SW4_6IF clear SW4 6 interrupt flags P2IFG RET Delay routine DELAYO push 03000h JMP DELAY3 DELAY push 06000h JMP DELAY3 DELAY2 push 09000h DELAY3 dec 0 SP Kkkxkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk SW Delay using Stack SW Delay using Stack SW Delay using Stack F MSP430 Microcode Example 5 3 jnz DELAY3 incd SP RET E OK ON RORIS ORE UNE EVER OE RCRA N E PRK RRR ER A E I Set_DCO Subroutine Set DCO to selected frequency Countl R8 and Count2 R9 are used and not saved E NAAR RR kau S viole c T Set DCO JMP skipdco J gt gt gt gt gt gt gt gt DD gt gt gt D gt AAA AAA AAA AA AAA gt gt gt gt gt gt gt gt gt gt gt gt gt gt BIS MC1 amp TACTL start timer continous Mode CLR Count 1 clear counter MOV CCISO CMO CAP amp CCTL2 Define CCR2 capture input signal ACLK capture on rising edge set to capture mode Test_DCO BIT CCIFG amp CCTL2 intrpt flag set yes
53. to DCO Rsel 6 BIC b OFFh amp P1SEL set P1 function 1 0 BIC b OFFh amp P2SEL set P2 function 1 0 BIC b OFEh P10UT set Pl output data low except reset BIS b 0C1h amp P1DIR set P1 pins I2C amp switches inputs BIS b RST amp P1OUT set RESET data high BIS b OSC_OE amp P10UT set oscill enable data high BIC b OFFh P20UT set P2 output data low setting for Expand 0 off gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt CALL DELAY2 delay to let oscill stabilize BIC b RST amp P1OUT set RESET data low pin goes low since it is enabled CALL NOP9 delay RESET low to high BIS b RST amp P1OUT set RESET pin high PE TERR I UR cie RR BIR PI Key switch pins amp registers BIC b 5W1 5W2 5W3 SPIDIR switch pins on Pl set to inputs BIC b SW4 SW5 SW6 SP2DIR switch pins on P2 set to inputs BIS b SWI SW2 SW3 amp P1IES SW1 3 interrupt edge select HI to LO BIS b SW4 SW5 SW6 amp P2IES SW4 6 interrupt edge select HI to LO BIS b SWI SW2 SW3 amp SW1_3IE SW1 3 interrupts enabled BIS b SW4 SW5 SW6 6SW4 GIE SW4 6 interrupts enabled BIS b EXP LED amp P2DIR set expand amp LED pins to outputs BIS b ED amp LED_OUT LED initial state off active low OV 180 Vol_Pntr initial setting for volume OV 415 Bass_Pntr initial set
54. uded END OF TREBLE DATA X XXXXXX ERER EK line 465 Kkkkkkkkkkkkkkkkkkkkkk treble setting 0 IMPORTANT this line treble setting IMPORTANT this line treble setting 2 IMPORTANT this line treble setting s IMPORTANT this line treble setting 4 IMPORTANT this line treble setting IMPORTANT this line treble setting 6 IMPORTANT this line treble setting s IMPORTANT this line treble setting 8 minimum 9 dB must be included must be included line 475 must be included must be included line 485 must be included must be included line 495 must be included must be included line 505 by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by by byt byt byt byt byt byt byt byt byt byt byt byt byt byt byt te te te 005 074 000 te003h 068 005 072 000 003 068 005 070 000 003 068 005 06D 000 003 068 005 06B 000 003 068 005 068 000 003 068 005 065 000 003 068 005 062 000 003 068 005 05E 000 003 068 005 05A 000 003 068 2 2 QQ vd D vd vd Q vd vd D D vd dQ D D vd O vd vd vd D vd DD vd DD vd B vd D D O vd vd vd vd vd DO vd DP DO PDP p vd 5 5 IMPORTANT this line must be inc
55. value captured JZ Test_DCO flag not set loop again BIC CCIFG amp CCTL2 clear interrupt flag AdjDCO OV amp CCR2 Count2 contents of cap com reg2 gt Count2 SUB Count1 Count2 sCount2 Countl gt Count2 OV CCR2 Count 1 contents of cap com reg2 gt Countl CMP Delta Count 2 Delta Count2 Delta SMCLK 32768 4 JL IncDCO jump if Count2 lt Delta JEQ DoneDCO jump if Count2 Delta DecDCO DEC b DCOCTL decrease DCO frequency JMP Test_DCO jump to test new setting IncDCO INC b amp DCOCTL increase DCO frequency JMP Test_DCO jump to test new setting DoneDCO CLR amp CCTL2 DCO calibrated stop CCR2 skipdco PPP PPP gt gt gt gt gt gt gt gt AAA AAA AAA AAA AAA PO OO OO PO OP OO PO E AAA PO OO PO OOO PP OOO OO OOO OP OO SAA AAA gt gt gt gt RET return from setup cal routine Eh I2C send amp test for end of data SANA I RRR RRR KR ER IRR ROR RRR RAR BERR e Kk ege AER D KEE RRR RRR KK KK ARERR BR AH ROR AK IRR KR A AER RR REAR Loop XOR b LED SLED OUT LED momentarily swithed to indicate I2C data being sent Loop2 CMP b 0 Data Tbl_Pntr first byte in string is no of data bytes to follow before next stop is issued JZ LP_END if first byte in string 0 then end MOV b Data Tbl Pntr Strng Pntr set string pointer table pointer CALL 4I2C Call routine to send Dig Spkr data byte via I2C JMP Loop2 loop to send next data byte string LP END CALL DELAY X
56. y switches DINT disable interrupts CALL DELAY2 delay for switch debounce test for SW1 6 pressed shift EQ mode BIT b SW1 amp SW1_3IF SW1 pressed JZ SW2 EQ NO jump to next SW CALL DELAY2 delay before testing 2nd SW BIT b SW6 amp SWA4 GIE SW6 pressed also JNZ OG LED YES jump to toggle LED BIT b ED amp LED OU LED on shift mode JZ SW1_MUTE YES jump to mute BIC b ED amp LED_OU turn LED on CALL DELAY delay before testing SW again BIC b SW1 amp SW1_3IF clear SW1 flag CMP 360 Vol Pntr volume maximum JEQ SW1 TES Yes 5W1 test ADD 10 Vol Pntr increase pointer to higher setting OV Vol Pntr Tbl Pntr set table pointer Vol up data CALL OOP call I2C send routine BIT b SW1 P1IN s SW1 still pressed JZ SW1_FUNC2 YES active low increase volume BIS b ED amp LED_OU turn LED off JMP SW_DONE jump to end of SW routine XOR b ED SLED OU toggle LED when SWI1 amp 6 pressed shift mode on off JMP SW_DONE jump to end of SW routine XOR 1 MUTE toggle mute setting 0 mute off JZ MUTE_OFF jump if mute 0 turn mute off CALL MUTE_ON call mute function changed to function so it could be used elsewhere in program MUTE_OFF MUTE_ON SW2 EO SW2 FUNC SW2 TEST SW3 EO
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