4I24I PARALLEL PORT MANUAL
Contents
1. 41241 Aliased address W1 W2 0000H Power Option W3 Ground Page 6 41241 USER S MANUAL CONFIGURATION DEFAULT JUMPER SETTINGS RN7 z 25 cu RI RN9 RN10 RNI US C CI REV C9 Page 7 41241 USER S MANUAL CONFIGURATION BASE ADDRESS SELECTION The addresses of the four 82C55 s on 41241 are selected by placing shorting jumpers on jumper blocks W1 W2 W4 through W9 These jumper blocks have three pins and two valid shorting jumper locations up and down The position of the jumpers is a binary representation of the 4124I base address When a jumper is in the up position it matches a high address line The following table shows some example base address settings BASE ADDRESS WA W5 W6 W7 W8 W9 A9 A8 A7 A6 A5 A4 0200H Default up down down down down down 0290H up down up down down up 0360H up up down up up down ALIASED ADDRESS SELECTION If multiple 41241 5 are used in a single system I O address space can be conserved by using aliased address s Aliased addresses are an artifact caused by the partial only 10 bit address decoding used by most PC bus cards2. 41241 cards actually decode A15 and A14 in addition to AO through A9 This makes it possible to have to four 4I24T s located at what appears to other cards in the system to be single 16 byte block of I O addresses This is done by selecting the same base addresses on all cards butselecting differing high order aliased addresses The aliased address used by a 41241 is selected via shorting jumpers 1 and W2 Note that aliased addressing only makes sense when using multiple 41241 s in a single system and when all base address s used are the same The following table shows allfour ofthe possible aliased address settings ALIASED ADDRESS wi W2 A15 A14 BASE 0000H Default down down BASE 4000H down up BASE 8000H up down BASE C000H up up Page 8 41241 USER S MANUAL CONFIGURATION BASE AND ALIASED ADDRESS JUMPERS e 8 gt z Ae L mu W W2 r 4 LE WA4WS W8W9 WS U5 Lus 07 bug C10 ART REV A 09 Page 9 41241 USER S MANUAL CONFIGURATION 5 ENABLE JUMPER Pin 2 on all of the 41241 I O connectors can either be grounded or connected to system 5V through a fuse 5V is provided on pin 2
3. bit 2 21 CO bit 3 22 CO bit 4 23 CO bit 5 24 CO bit 6 25 CO bit 7 26 Ground Page 14 41241 USER S MANUAL OPERATION P1 CONNECTOR PIN SIGNAL 1 A0 bit 0 2 5V fused power or GND W3 option 3 A0 bit 1 4 A0 bit 2 5 AO bit 3 6 AO bit 4 7 A0 bit 5 8 Al bit 6 9 Al bit 7 10 B1 bit 0 11 B1 bit 1 12 B1 bit 2 13 B1 bit 3 14 B1 bit 4 15 B1 bit 5 16 B1 bit 6 17 B1 bit 7 18 Cl bit O 19 Cl bit 1 20 C1 bit 2 21 Cl bit 3 22 Cl bit 4 23 Cl bit 5 24 CI bit 6 25 Cl bit 7 26 Ground Page 15 41241 USER S MANUAL OPERATION P2 CONNECTOR PIN SIGNAL 1 A2 bit 0 2 5V fused power or GND W3 option 3 A2 bit 1 4 A2 bit 2 5 A2 bit 3 6 A2 bit 4 7 A2 bit 5 8 A2 bit 6 9 A2 bit 7 12 B2 bit 0 11 B2 bit 1 12 B2 bit 2 13 B2 bit 3 14 B2 bit 4 15 B2 bit 5 16 B2 bit 6 17 B2 bit 7 18 C2 bit 0 19 C2 bit 1 20 C2 bit 2 21 C2 bit 3 22 C2 bit 4 23 C2 bit 5 24 C2 bit 6 25 C2 bit 7 26 Ground Page 16 41241 USER S MANUAL OPERATION P4 CONNECTOR PIN SIGNAL 1 A3 bit 0 2 5V fused power or GND W3 option 3 A3 bit 1 4 A3 bit 2 5 A3 bit 3 6 A3 bit 4 7 A3 bit 5 8 A3 bit 6 9 A3 bit 7 12 B3 bit 0 11 B3 bit 1 12 B3 bit 2 13 B3 bit 3 14 B3 bit 4 15 B3 bit 5 16 B3 bit 6 17 B3 bit 7 18 C3 bit 0 19 C3 bit 1 20 C3 bit 2 21 C3 bit 3 22 C3 bit 4 23 C3 bit 5 24 C3 bit 6 25 C3 bit 7 26 Ground Page 17 41241 USER S MANUAL OPERATION PPLOOPBK A simple test program is supplied with th
4. 41241 PARALLEL PORT MANUAL Version 1 0 Copyright 1997 by MESA ELECTRONICS Richmond CA Printed in the United States of America All rights reserved This document and the data disclosed herein is not to be reproduced used disclosedin wholeorinpartto anyone without the writtenpermissionof MESA ELECTRONICS Mesa Electronics 4175 Lakeside Drive Suite 100 Richmond CA 94806 1950 Tel 510 223 9272 Fax 510 223 9585 E Mail tech mesanet com Website www mesanet com 41241 USER S MANUAL TABLE OF CONTENTS HANDLING PRECAUTIONS 0 INTRODUCTION Generali 00 CONFIGURATION General s w ka pi RI OY AURIS e Gu kw a k inde stew a YID n dee RAS Default ia indi il AEE Base Address selection RA uN Aliased address selection isyu uq d lk el k se e Rad A iia 35 V En ble EIER te Wa AA ve EISE IARE C MEE Eque INSTALLATION ose da a mult Deua dle i connectororientation OPERATION P rt Ma PPI A A AAA AA AA inst Connector ihOllt a A AA PPEQOPBK E EES O OTEN REFERENCE INFORMATION sina ak kesl lk k la kk delk k a RA a k n lt 01016 NA A di
5. 50 pin connectors each having 24 I O bits with interleaved grounds 5V power on the I O connectors is fused on the 4124 All 4124 models use the 16 bit stack through type PC 104 bus architecture Four layer circuit card construction is used to minimize radiated EMI and provide optimum ground and power integrity All CMOS design keeps power consumption to a minimum The 4124 requires only 5 V for operation The 4124 base address is set with jumpers and can be located anywhere in the 1024 byte I O address space of the PC 104 bus 4I24 cards use 16 contiguous I O address s but where multiple cards are used an aliased addressing capability allows up to four 4I24 cards to share the same 10 bit base address conserving I O address space A partially loaded 48 bit version of the 4124 and 4124 can be provided if needed contact MESA for availability Page 5 41241 USER S MANUAL CONFIGURATION GENERAL The 41241 port address and I O power connection options are set with jumpers Each group of jumpers will be discussed separately by function In the following discussions when the words up down right and left are used it is assumed that the 4I24I I O card is oriented with its bus connectors J1 and J2 at the bottom edge of the card nearest the person doing the configuration DEFAULT JUMPER SETTINGS Factory default 41241 jumpering is as follows FUNCTION JUMPER S SETTING 41241 Base address W4 W5 W6 W7 W8 W9 0200H
6. e 41241 for functional testing and verification This program is called PPLOOPBK EXE PPLOOPBK is what s called loopback test program It works by sending rotating bit patterns out on all 24 bits of a 8255 programmed for all outputs then checking to see that the same pattern has been received on a second 8255 programmed for all inputs After this is done PPLOOPBK reverses the roles ofthe input and output chips and repeats the test The connection between the two 8255 s is done with an external cable a loopback cable PPLOOPBK will detect most common I O port problems including stuck bits shorts and opens PPLOOPBK is not very smart about major problems like incorrect port addresses missing loopback cables etc and will cheerfully report bit errors even if no 41241 card is present To use PPLOOPBK you must have a 26 conductor flat cable with female headers on each end Because the 4I24I has four connectors you must run PPLOOPBK with 2 different cable arrangements First connect P1 and P2 together with the flat cable Make sure that the cable is properly polarized pinl to pin 1 Then run PPLOOPBK Next connect the loopback cable to P3 and P4 and run PPLOOPBK again PPLOOPBK is invoked with 2 hexadecimal addresses on the command line These are the addresses ofthe two 8255 s that will be tested If a 4I24I is set to its default 0200H address and has a good loopback cable installed the following sequence of commands will do a fairly th
7. orough test of the card Connect loopback cable to P land P2 PPLOOPBK 204 208 Connectloopback cable to and P4 PPLOOPBK 200 20C Page 18 41241 USER S MANUAL REFERENCE INFORMATION SPECIFICATIONS POWER SUPPLY Voltage Supply current BUS LOADING Input capacitance Input leakage current Output drive capability Output sink current I O PORT LOADING Input logic low Input logic high Output low Output high ENVIRONMENTAL Operating temperature range I version C version Relative humidity MIN 4 5 3 2 0 3 0 Page 19 MAX 5 5 50 85 70 90 UNIT V mA no ext load pF uA pF 2 5 mA sink 2 5 mA source lt lt lt lt C C Percent Non condensing 41241 USER S MANUAL REFERENCE INFORMATION WARRANTY Mesa Electronics warrants the products it manufactures to be free effects in material and workmanship under normal use and service for the period of 2 years from date of purchase This warranty shall not apply to products which have been subject to misuse neglect accident or abnormalconditions ofoperation In the event of failure of a product covered by this warranty Mesa Electronics will repair any product returned to Mesa Electronics within 2 years of original purchase provided the warrantor s examination discloses to its satisfaction that the product was defective The warrantor may at its option replace the product inlieu ofrepair With
8. regard to any product returned within 2 years of purchase said repairs or replacement will be made without charge If the failure has been caused by misuse neglect accident or abnormal conditions 01 operation repairs will be billed at a nominal cost lt V a I G lt MI THE FOREGOING WARRANTY 5 IN LIEU OF ALL OTHER WARRANTIES 55 IMPLIED INCLUDING BUT LIMITED ANY IMPLIED WARRANTY OF MERCHANTABILITY FITNESS OR ADEQUACY FOR ANY PARTICULAR PURPOSE OR USE MESA ELECTRONICS SHALL NOT BE LIABLE FOR ANY SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES WHETHER IN CONTRACT TORT OR OTHERWISE If any failure occurs the following steps should be taken 1 Notify Mesa Electronics giving full details of the difficulty On receipt of this information service data or shipping instructions will be forwarded to you 2 On receipt of the shipping instructions forward the product in its original protective packaging transportation prepaid to Mesa Electronics Repairs will be made at Mesa Electronics and the product returned transportation prepaid Page 20 41241 USER S MANUAL REFERENCE INFORMATION SCHEMATICS Page 21
9. rresponds with the colored stripe on typical flat cable assemblies If more positive polarization is desired center polarized IDC header connectors should be used These connectors will not fully mate with the pins on the 4124 if installed backwards A suggested center polarized 26 pin IDC header is AMP PN 746285 6 Page 12 41241 USER S MANUAL OPERATION PORT MAPPING The 41241 has four 82C55 chips Each 82C55 chip occupies four contiguous locations in I O space for a total of sixteen I O locations In the following table and I O connector pinout tables the letters A B and C refer to individual ports on a 8255 chip the standard 8255 port names while the numeric suffix 0 1 2 or 3 refers to the specific chip The 82C55 ports are addressed as follows ADDRESS PORT CONNECTOR BASE 0 AO P3 BASE 1 BO P3 BASE 2 CO P3 BASE 3 ControlO BASE 4 Al Pl BASE 5 Bl P1 BASE 6 Cl P1 BASE 7 Control1 BASE 8 A2 P2 BASE 9 B2 P2 BASE A C2 P2 BASE B Control2 BASE C P4 BASE D B3 P4 BASE E C3 P4 BASE F Control3 Page 13 41241 USER S MANUAL OPERATION CONNECTOR PIN OUT The 41241 26 pin I O connector pinouts are as follows P3 CONNECTOR PIN SIGNAL 1 AO bit 0 2 5V fused power or GND W3 option 3 AO bit 1 4 A0 bit 2 5 0 bit 3 6 0 bit 4 7 0 bit 5 8 A0 bit 6 9 AO bit 7 10 BO bit 0 11 BO bit 1 12 BO bit 2 13 BO bit 3 14 BO bit 4 15 BO bit 5 16 BO bit 6 17 BO bit 7 18 CO bit 0 19 CO bit 1 20 CO
10. sc ccc 20 Schematic diagrams 25er deter cine bea xelk sl RES ca dd kadan s elba a ka a 21 41241 USER S MANUAL HANDLING PRECAUTIONS STATIC ELECTRICITY The CMOS integrated circuits on the 4I24I can be damaged by exposure to electrostatic discharges The following precautions should be taken when handling the 41241 to prevent possible damage A Leavethe 4I24I in its antistatic bag until needed B All work should be performed at an antistatic workstation C Ground equipment into which 41241 will be installed D Ground handling personnel with conductive bracelet through 1 megohm resistor to ground E Avoid wearing synthetic fabrics particularly Nylon 41241 USER S MANUAL INTRODUCTION GENERAL The MESA 4124 series of cards are 96 bit parallel I O interfaces implemented on the PC 104 bus The 4124 uses 4 4124 41241 or 3 4124M socketed 82C55 PIO chips to give for a total of 96 I O bits 4124 41241 or 72 I O bits 4I24M 3 3K Pullup resistors are provided on all ports to simplify interfacing to contact closure opto isolators etc The 4I24 includes three models with different I O connectors The standard 4I24 uses two 50 pin headers for I O connections The 50 pin connectors each have 48 I O bits ground and power The 41241 uses four 26 pin headers with ISO standard pinout 24 I O bits per 26 pin connector pin 2 GND pin 26 5V The 4124M has I O module rack compatible pinouts with three
11. to supply power to I O module racks This option is selected by the position of the shorting jumper on jumper block W3 When the jumper is in the left hand position fused 5V power is routed to pin 2 on the I O connectors When W3 is in the right hand position pin 2 is used as an additional ground This is the default position ofthe 5 V enable jumper Note that the 5V fuse is rated at 1 Amp and can be replaced without soldering Replacement part number is LittleFuse PN 250001 Page 10 41241 USER S MANUAL CONFIGURATION POWER OPTION JUMPERS RN5 RN6 C4 RN7 RN8 RN9 0 gt 99 J W4W5 W8W9 Lus 07 gt gt ART REV A Page 11 41241 USER S MANUAL INSTALLATION GENERAL When the 41241 has been properly configured for its application it can be inserted into a PC 104 stack The standoffs should then be tightened to secure the 4I24I in its place When the 41241 is secured in the stack the 26 pin headers can be plugged in from the sides CONNECTOR ORIENTATION The 26 pin connectors on the 41241 have their pin one ends marked with a white square on the circuit card This co
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