User Manual - ARM DS-5 Development Studio
Contents
1. Incremental form encoder correspondence LVD POR Function 1 Unit Oscillation Frequency Detection 1 Unit External bus interface 1 unit separation multiplexer bus 8 bit 16 bit width chip select wait controller 4 channel Interruption function 112 kinds of insides a priority setup of 7 level is possible Watchdog timer interruption is excluded 16 kinds of exteriors a priority setup of 7 level is possible NMI is excluded Input output ports PORT I O port 101 pins Output port 1 pins Standby function Standby mode IDLE STOP1 STOP2 IDLE CPU stop 5 1 5 2 All the circuit stops except RTC and a remote control judging circuit STOP2 At the time of the mode in part a circuit power supply interception Clock Generator PLL built in 3 4 5 6 8 and 10times PLL frequency change is possible Clock gear function dividing is possible in a high speed clock to 1 1 1 2 1 4 1 8 and 1 16 Endian Little endian Debugging interface JTAG SWD SWV TRACE DATA 4bit Maximum operating frequency 80 MHz the time of external oscillator 8MHz 10 MHz or 16MHz use or built in oscillator 10MHz use The range of operating voltage 2 1V 3 6V at the time of USB functional disuse 3 0V 3 6V at the time of USB functional use Operating temperature range 40 C 85 Except the time of flash writing erase 0 70 C the time of flash writing era2. 20PIN JTAG BG 55 SIO UART DSUB 9PIN 56 JP4 S99 100 0 OOO X mm JP13 y 2 000 08 1 JPTO VOL2 VOLI JP12 9 oO CAN ost 73 U4 U5 g U3 LDO 2 ook Ox Ome El JP8 JP1 gE JP6 JP7 TMPM369FDFG TMPM369FYFG TOSHIBA LD1117S33CTR ST Microelectronics USB Transient Suppressor SN65220DBVT Digital Transistor PNP DTA123EE Digital Transistor NPN DTC123EE RS 232C Line Drivers Receivers ADM3202ARUZ Analog Devices Inc RS 232C Line Drivers Receivers ADM3202ARUZ Analog Devices Inc CAN TRANSCEIVER TJA1040T NXP Semiconductors LAN PHY LAN8710AI SMSC urrent Limited Power Distribution TPS2051CDBVT USB Transient Suppressor SN65220DBVT Page3 100 0 mm Full UART DSUB 9PIN o 3 U3 cos JP8 JP1 lege JP6JP7 20PIN Cortex SIO UART DebugtETM s 10PIN CN6 Cortex Debug 20PIN JTAG Eia EN JP2 oo U8 VOL2 VOL JP12 99 Fig 3 Evaluation for TOSHIBA TMPM369FDFG Jumper configration default gt Jumper CLOSE Default configuration JP1 OPEN Normal JP2 2 3 CLOSE X1 OSC select JP3 1 2 CLOSE OSC 16 3 JP4 2 3 CLOSE SIO BOOT JP5 CLOSE Target board power supply to CN6 1PIN JP6 CLOSE It supplies from a USB Devic
3. CLOSE It supplies 5V from an external connector CN1 or CN13 USB DP terminal 1 5KQ Compulsive pull up _ JP8 OPEN With no pull up uds ARIN JPS DE PUEL UR JP8 CLOSE USB DP terminal Compulsive pull up USB_DP terminal 1M Pulldown JP9 2PIN JP9 DP_PULL DOWN JP9 OPEN With no pull down JP9 CLOSE USB_DP terminal 1MQ pull down USB DM terminal 1MQ Pulldown JP10 2PIN JP10 DM_PULL DOWN JP10 0PEN PULL DOWN EL JP10 CLOSE USB DM terminal 1MQ pull down USB DP terminal Compulsive pull up control port PEO enabling JP1 1 2PIN JP11 PEO EN JP11 OPEN Control port PEO It is not used JP11 CLOSE Control port PEO It is used Page5 Chapter 2 Hardwar discription The TMPM369FDFG is a 32 bit RISC microprocessor series with ARM Cortex M3 microprocessor core The internal composition of CPU is shown in Fig 4 Fig 4 TMPM369FDFG CPU internal block diagram Cortex M3 JTAG SWD NVIC 2 2 Ether USB MAC Device 2 32 AHB Lite Bus Matrix FLASH__ROM Main__RAM Backup_RAM BOOT_ROM USB_HOST Ether_MAC LN USB_Device CAN SNY NY VY VY VY 21 sng 91 O I MPT PMD ENC Kee P
4. Fast conversion by interleave mode conversion time maximum of 0 5microsec 10bit DA Converter DAO 2 Unit 2 Channel VREFH cut function Power down mode Output current 1 mA Seduced time microsec Signal generation function USB2 0 Full Speed Device 1 Channel It is based on Universal Serial Bus Specification Rev2 0 End point 8 channel Control Bulk Interrupt Isochronus mode Full speed 12Mbps low speed is un supporting USB host controller 1 channel Universal serial bus Rev 2 0 standard Open HCI for USB Release 1 0a Control Bulk Interrupt Isochronus mode 12Mbps full speed Low speed is un supporting CAN 1 channel Version 2 0B supported 32 mail boxes Maximum transfer speed 1 Mbps Ethernet MAC 1 Channel IEEE802 3u conformity Flow control IEEE802 3x back pressure system 10Mbps 100Mbps correspondence MII Media Independent Interface correspondence High speed communication by exclusive DMA and a total of 8 K byte FIFO Magic packet detection function Remote Control Judging Function RMC 1 Channel t is package reception to 72bit Noise canceller function Reader code detection function Page8 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Multiple purpose timer MPT 4 channel motor control PMD 2 channel IGBT control 16 bit timer Encoder input function 2 channel
5. for ADC Input 2ch only AINAO AINB6 1Obit DAC 2ch DAO DA1 SIO UART chO ch3 Only the channel 0 equips DSUB 9pin connector with a 5 232 driver receiver Ful UART ch4 ch5 Only the channel 4 equips DSUB 9pin connector with a 5 232 driver receiver 5 LEDs and 6 push buttons LED1 LED4 Status display LED This LED is connected to PC7 PC4 of a port LED5 LED for power light S1 Push switch for reset S2 Push switch for NMI S3 S6 Push switch for a test Power via USB connector As an option An AC adaptor jack CN13 and an external 5V Power input connector CN1 are equipped However in order to usually perform electric supply from a USB connector CN1 and CN13 suppose un mounting Debug Interface Connectors 0 Cortex debug 0 05 inch connector W20 pin Cortex debug ETM Trace 0 05 inch connector 20 0 10inch connector ARM Standard JTAG Connector Page 3 3V 3 A TMPM369FDFG Fig 1 1 LAN8710AI Evaluation for TOSHIBA TMPM369FDFG m 10 100Base T whole_block_diagram Ethernet_ CN12 m CN10 Expantion Current Limited IC Connector USBHEON PK3 USBHPON SPODO SIO_SCLO PK1 USBOG SPOFSS INT8 TB6OUT 26520810 Bus Power USB Host reed 27 CN3 Host _ _ W USBHOP W 27 m VAA3 3 15K 15K 10K Volume input AINAO TRANSIENT SUPP
6. ORT WDT RTC 16bit TIMER SIO UART 4byte FIFO SBI imm OFD ED RMC AHB to APB Bridge 12bit ADC 10bit DAC Full UART SSP SPI External_BUS_I F Page6 CPU functional outline 1 ARM Cortex M3 microprocessor core a Improved code efficiency has been realized through the use of Thumb 2 instruction New 16 bit Thumb instructions for improved program flow New 32 bit Thumb instructions for improved performance New Thumb mixed 16 32 bit instruction set can produce faster more efficient code b Both high performance and low power consumption have been achieved High performance Both high performance and low power consumption have been achieved Division takes between 2 and 12 cycles depending on dividend and devisor Low Power consumption Optimized design using a low power consumption library Standby function that stops the operation of the micro controller core c High speed interrupt response suitable for real time control An interruptible long instruction Stack push automatically handled by hardware 2 High speed writing which demonstrates an effect at the time of high speed write in amp low power consumption and mass production by Toshiba NANO FLASH technology and development 3 Chip program memory and data memo
7. RESSORS PIO AINAO INT9 C9 f USP_PON PKo USBDPON INTD USBDP USB DDP ADC Input USBOM USB_DDM AGND 12bit USB ADC Device PIO AINAO INT9 16ch PJ2 AINB6 3 CAN transceiver i CN9 10K Volume input AINB6 DAC Output TE 120 CAN PJ2 AINB6 AGND CN8 Full UART External 5V power input CN1 J 3 3V User LED x4 no mount ai ADM3202ARU 3 3V CN7 User 5 X 4 RS 2320 J SIO UART 83 56 p AG adapter jack o C 3 3 3 3V 13 e r no mount Mod PB6 BELL SCOUT TB30UT BOOT E Filter 2 BS O NMI SW ono 4 Ir M PE2 TXDO A2 A18 TB10UT igri USB Device 7 PKO USBDPON INTD PE3 SCLK0 A3 A19 CTSO TBOOUT E CN2 4 ecol PES TXD1 A5 A21 RESET RESET SW 1 3 3V i nl A 4 USB PEO A0 A16 INT4 TBOIN itp Cortex debus 7 L CN6 USB miniB 0 05 inch connector CN5 TypeB 16MHz CN4 20 pin 0 10inch connector EET 20 pin Cortex debug ARM Standard JTAG Connector TRANSIENT ETM Trace SUPPRESSORS 05 i JP10 0 05 inch connector PE0 A0 A16 INT4 TBOIN 32 768 KHz Page2 Fig 2 Evaluation for TOSHIBA TMPM369FDFG PCB Main parts image 135 0 mm a e N e Full UART DSUB 9PIN o S3 20PIN Cortex DebugtETM 7 54 10PIN CN6 Cortex Debug _
8. The evaluation board for TOSHIBA TMPM369FDFG user s manuals Revision 1 2 0 2014 11 27 A product specification is an object of change without a preliminary announcement Introduction This manual is a user s manual of the evaluation board for Toshiba TMPM369FDFG Table of contents Chapter 1 Chapter 2 Outline Hardwar discription Revision history Date 2012 9 12 2013 4 25 2014 11 27 numbe Revision 1 OO NN First edition creation 5 default jumper configuration Revisioni a To 21 JP5 OPEN JPS CLOSE 7 5 16 bit timer TMRB 16 channels gt 8 channels 9 24 Interruption function 110 kinds of insides Revision 1 20 gt 112 kinds of insides 17 kinds of exteriors NMI is included gt 16 kinds of exteriors NMI is excluded 33 Package LQFP144 P 2020 0 5 gt LQFP144 Chapter 1 Outline Evaluation Board for TOSHIBA TMPM369FDFG enable you to create and test working programs based on the Toshiba TMPM360 family of ARM Cortex M3 processor based devices Features 80MHz ARM Cortex M3 processor based MCU in 144 pin LQFP On Chip Flash 512KB TMPM369FDFG On Chip Flash 256KB TMPM369FYFG On Chip RAM 128KB TMPM369FDFG On Chip RAM 64KB TMPM369FYFG USB 2 0 Host USB 2 0 Device CAN 2 0B Interface EterMAC 10 100Base T On a board LAN PHY made from SMSC LAN8710A is mounted 12bit ADC 16ch AINAO AINA3 AINBO AINB11 Multi rotation volume
9. e connector CN2 JP7 OPEN With no electric supply JP8 OPEN With no pull up JP9 CLOSE USB DP terminal 1MQ pull down JP10 CLOSE USB DM terminal 1MQ pull down JP11 CLOSE Control port PEO It is used JP12 OPEN Termination is not used JP13 CLOSE The regulator output on a board is used DSUB 9PIN Page4 Table 1 Evaluation Boardfor TOSHIBA TMPM369FDFG Jumper pin setting table The number S of pins Silk name Function Boot mode select JP1 2PIN JP1 BOOT JP1 OPEN Normal JP1 CLOSE BOOT Mode JP2 1 USBCLK Selection of a clock JP2 3PIN 2 JP2 1 2 CLOSE USBCLKI 3 X1 OSC JP2 2 3 CLOSE X1 OSC JP3 1 X1 osc 16 3 USB Clock selection JP3 2 JP3 1 2 5 X1 OSC 16 3 3 USBECLK JP3 2 3 CLOSE USB JP4 1 USB Boot mode kind selection JP4 3PIN 2 JP4 1 2 CLOSE USB BOOT 3 SIO BOOT JP4 2 3 CLOSE SIO BOOT 3 3V target supply source selection JP5 2PIN JP5 JTAG POWER JP5 OPEN With no target supply to CN6 1pin JP5 CLOSE It supplies target 3 3V power to JTAG CN6 1pin electric supply source selection JP6 OPEN gt With no electric supply dee JPGUHSB SV JP6 CLOSE It supplies from a USB Device connector CN2 5V electric supply source selection JP7 OPEN With no electric supply JP7 2PIN JP7 EXT SV JP7
10. ry On Chip Flash 512KB TMPM369FDFG On Chip Flash 256KB TMPM369FYFG On Chip RAM 128KB TMPM369FDFG On Chip RAM 64KB TMPM369FYFG 4 DMA controller DMAO 32 channel 2 unit The candidate for transmission A built in memory built in I O and an external memory 5 16 bit timer TMRB 8 channels 16 bit interval timer mode 16 bit event counter mode 16 bit PPG output 4channel timer can start synchronously Input capture function 6 Real time clock RTC 1channel Clock hour minute and second Calendar month week date and leap year Alarm Alarm output Alarm interrupt 7 Watchdog timer WDT 1 channel Watchdog timer WDT generates a reset or a non maskable interrupt NMD 26 Stage binary counter Watchdog timer out function 8 General purpose serial interface SIO UART 4 channels Either UART mode or synchronous mode can be selected 4byte FIFO equipped Page 9 10 11 12 13 14 15 16 17 18 Serial bus interface I2C SIO 3 channels Either I2C bus mode or synchronous mode can be selected Synchronous serial port SSP 3 channels Support SPI SSI Microwire Full UART 2 Channel 8 Line UART IrDA 1 0 Mode Select is Possible 10 bit AD converter ADC 16 channels Start by an internal timer trigger Fixed channel scan mode Single repeat mode AD monitoring 2 channels Conversion speed 1 0 4 sec 8 fsys 80 MHz Normal Mode
11. se Package LQFP144 20mm x 20mm 0 5mm pitch Page9
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