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VX3230

1. 32 Figure 11 Front Panel Connectors 32 Figure 12 Serial Connector 33 Figure 13 USB Connector ir epp epe ppc e dup ds 35 Figure 14 USB Onboard Connector 1 4 4 35 Figure 15 USB Flash Disk Overview 36 Figure 16 Dual Gigabit Ethernet 37 Figure 17 VPX Connectors 4 2 39 Figure 18 Connector Identification for VPX Board 39 Figure 19 COP Header corcel ape deeds ex Ee ax pU E 53 Figure 20 JTAG Connector cedex epe pu a Le ug hee 53 Figure 21 VX3230 Identification Top 57 Figure 22 VX3230 Identification Bottom Side 58 Figure 23 Board Configuration 59 Figure 24 USB Flash Disk Bottom View 63 Figure 25 USB Flash Installation 63 Figure 26 PMC Installation on PMC Site
2. 91 5 1 3 1 Start Up Requirement 91 5 1 3 2 Power Up Sequence 91 Page vii CA DT A63 1e VX3230 User s Guide Table Of Contents 5 1 3 3 Tolerance ii eie 92 5 1 3 4 hegulalla coc tiro iia A PR eT We Rmi a id 92 5 1 3 5 Rise Time 2222 2 12 124 ht RR 93 5 2 Power Consumption 20d o A iii 94 5 2 1 Real Applications 94 Chapter 6 VX3230 RTM Characteristics 95 0 1 OVeIVIGW score he dad age gia eR E ace ae 95 6 2 Technical Specifications 97 6 3 Configuration 98 GA Connectors eS X Ru ehe ERE ROSE DE P E EIC a a ae 99 6 4 1 RTM Connectors Identification 99 6 4 2 Front Panel Connectors 100 6 4 3 Onboard Connectors 101 6 5 Modules Interfaces Le v Rete err ave edie ee 104 6 5 1 iom mii uae lab be 104 65 2 USB Intertaces
3. 66 Figure 27 Example of Board 1 1 2 67 Figure 28 Installation on Site 67 Figure 29 Start Up Ramp of the CP3 SVE180 AC Power Supply 93 Figure 30 VX3230 RTM 2 2 2 4 3 1 2 96 Figure 31 VX3230 RTM MicroSwitch Location 98 Figure 32 Connector Identification for 99 Figure 33 VX3230 RTM Front Panel Connectors 100 Figure 34 VX3230 RTM Onboard Connectors PB VX3 001 101 Figure 35 VX3230 RTM Onboard Connectors PB VX3 000 102 Figure 36 Serial Port Connector 2 104 Figure 37 Front Panel USB Connector 2 2 105 Page ix CA DT A63 1e VX3230 User s Guide Table Of Contents Figure 38 Onboard USB Connector 0 2 106 Figure 39 USB Flash Disk Overview 1 106 Figure 40 USB Flash Disk
4. 126 Table 65 VX3230 RC11N 000 MTBF Data 126 Table 66 Peripheral Connectivity 127 CA DT A63 1e Page xii VX3230 User s Guide Introduction Chapter 1 Introduction The VX3230 is a member of the Kontron s VITA 46 VPX range of products lts 1 GHz 8544 PowerPC processor gives you coolest implementation of a E500 core with plenty of features With a requirement as low as 18 Watts between 40 and 85 C the VX3230 is a major breakthrough for small form factor rugged computers Applications targeting Vetronics and onboard UAV which operate on a tight power budget will welcome ts innovative design In this document the term VX3230 will be associated to the 3U VPX board VX3230 SA will be associated to the standard commercial version of the board VX3230 RC will be associated to the rugged conduction cooled version of the board gt VX3230 RTM will be associated to the 3U VPX Rear Transition Module RTM CA DT A63 1e Page 1 Introduction VX3230 User s Guide MELON E EJ 155551 L E XMC PMC Slot Manufacturing Option 6 kontron XMC PMC Slot Manufacturing Option Figure 1 VX3230 SA Overview Page 2 CA DT A63 1e VX3230 User s Guide Introduction 1 1 Manual Overview 1 1 1 Objectives This guide provides general information
5. 40 2 8 5 J11 Connector Pin Assignment 47 2 8 6 J12 Connector Pin Assignment 47 2 8 7 J14 Connector Pin Assignment 48 288 Signal eos exo ata cn EXEC wed 49 28 9 J15 Connector Pin Assignment 51 2 8 10 Signal Decription 52 28 11 COP Header oer ee coed ohne b EROR RR CR has 53 2 8 12 JTAG Connector 53 2 9 XMCIPMG Site aii a a A a aa 54 2 9 1 Signaling Voltage Keying Pin 22 55 Chapter 3 seur d det naaie oy ene Ra ex an rog da E Ronde 56 3 1 Safety 56 3 2 Board dernitification imitar a 57 3 3 Board Configuration 59 3 3 1 Switch SW1 Description 59 3 4 Package Content 2 o lupi ag iia Gee teks 60 3 5 Initial Installation Procedures
6. 444 Local I2C Command Register This register control the CPLD system 2 master module of the VX3230 board R R NA Local I2C Command NB B 0 000 0004 B A RIPTIO i A 7 Strobe Read Busy 0 R W Busy 0 Interface is idle 1 7 Interface is not idle no futher access allowed Write Strobe 0 Interface is idle 1 Interface generates condition defined by ModeBits 6 SetAck Read getAck 0 R W GetAck 0 last recept bit was no acknowledge bit 1 last recept bit was acknowledge bit Write setAck 0 NACK will be sent after next transferred bit 1 ACK will be sent after next transferred bit 5 2 Res Reserved 0 R 1 0 Mode 1 0 00 generate Stop Condition 0 R W 01 generate Start Condition 10 send byte 11 receive byte CA DT A63 1e Page 73 Programming Interface VX3230 User s Guide 4 4 5 Local 2 Data Register REGISTER NAME Local 2 data ADDRESS 0 000 0005 DESCRIPTION 55 I2C DATA Local I2C bus data 4 4 6 Interface Configuration Register REGISTER NAME Interface Configuration ADDRESS 0 000 0008 DESCRIPTION 55 Reserved 4 4 7 Firmware Configuration register REGISTER NAME Firmware Configuration ADDRESS 0 000 0280 DESCRIPTION 55 Reserved Page 74 CA DT A63 1e VX3230 User s Guide Programming Interfa
7. 14 1 5 Technical Specification 1 15 tol NTER ta eon aas iuto 17 1 6 Software Support I Ru Een EXPE la Ox X ted 18 17 Standard elk UU cR Rak 19 1 7 4 Environmental Specifications 19 1 8 Related Publications 2 20 Chapter 2 Functional Description 21 2 1 Processor and System Memory 23 24 1 POCOS cone xa eR A TENE ER cities RS 23 2 1 2 System Mamoy 2 A A AA e ef RR ce n ae ee 24 2 2 PCI Express BUS6S coeno ii a Rec mex Rr Ee a 25 2 2 1 MPC8544 PCI Express Links 25 2 2 2 Internal PCI Express Links 25 2 3 E m 26 2 9 1 Flash cir A eet RR ce e Don 26 2 32 Sernal EEPROMS Rae mre Rr uer e bees ire ur eie emite dA ded deg 26 2 3 3 EEPROM us ee Res Sh Renate ee RR UR ew o d d d Le GR e 26 234 NOVRAM I detener REOR Se dks dul edidit ot d ep Cada dil oe oe 26 2 39 Dual Sarnal ATA ad RAE Er ERES E dente det
8. Send DUE rexit USER DANCE 105 6 5 3 Gigabit Ethernet Interfaces 108 6 5 4 ATA Interfaces 82 ca iube GR ee CE Gli 109 6 0 9 GPIO Connector a dr eed 110 6 5 6 JTAG 7 4 111 6 5 7 12 System Management 112 6 0 ROSE oo gt e iiL DI dii 113 6 7 Power Consideration 113 6 8 Rear I O Interfaces 114 6 8 1 RP2 Connector 1 115 6 8 2 RPI Connector miii Lee ee ass ela detent ee ola ud ded 116 6 83 RPO GonnectOr 2v Rr die bed Bees 119 6 9 PCI64 PIM Connector 121 6 9 1 Conneclor 2 ici rr en eet dak 4 tia dea 121 6 9 2 122 Chapter 7 VX3230 RC Characteristics 123 7 1 VX3230 RC
9. 61 3 6 Standard Removal Procedure 62 3 7 Installation of Peripheral Devices 63 3 7 1 USB Device Installation 63 3 1 2 Battery Replacement a REDE RE aai ee ee daa 64 3 7 3 PMC Installation 65 3 7 4 Installation 2 67 3 8 Software Installation 68 CA DT A63 1e Page vi Table Of Contents VX3230 User s Guide Chapter 4 Programming 69 401 Jnterrupt Routing 225225244 CANO ied ad 69 42 Memory Mapping 2i 345444 veel dave aoe iad 70 4 3 CPLD System Registers 0 71 44 CPLD System Registers Description 72 44 1 Firmware POST Code Register 2 72 442 Debug POST Code Register 72 4 4 3 Memory Configuration Register 73 444 Local 12C Command
10. 107 Figure 41 Gigabit Ethernet Connectors 108 Figure 42 Onboard SATA Connectors 1 1 1 4 4 109 Figure 43 Onboard GPIO Connector 2 2 110 Figure 44 Onboard JTAG Connector 2 111 Figure 45 Onboard JTAG Connector 1 2 22 112 Figure 46 VX3230 RTM Reset Push Button 113 Figure 47 Rear I O VPX Connectors 2 2 2 114 Figure 48 VX3230 RC Overview 123 Figure 49 VX3230 RC Identification Top Side 125 Figure 50 Standard Anchorage Points on VX3230 RC Board 128 Figure 51 Additional Anchorage Point on VX3230 RC Board 129 Figure 52 Usage of Fastening Kit Ribs on VX3230 RC Board 130 CA DT A63 1e Page x Table Of Contents VX3230 User s Guide List Of Tables Table 1 Order Code e A ge eae ade eid bat ae 6 Table 2 Front I O Interfaces no PMC XMC slot Manufacturing 7 Table 3 Front I O Interfaces PMC XMC s
11. CA DT A63 1e Page 89 Power Considerations VX3230 User s Guide Chapter 5 Power Considerations 5 1 System Power The considerations presented in the ensuing chapters must be taken into account by system integrators when specifying the VX3230 system environment 5 1 1 VX3230 The VX3230 has been designed for optimal power input and distribution Still it is necessary to observe certain criteria essential for application stability and reliability The following table specifies the ranges for the different input power voltages within which the board is functional The VX3230 is not guaranteed to function if the board is not operated within the prescribed limits INPUT SUPPLY VOLTAGE ABSOLUTE RANGE 3 3V 3 2V min to 3 47V max 5V 4 85V min to 5 25V max 12V 11 4V min to 12 6V max Table 41 DC Operational Input Voltage Ranges 5 1 2 Backplane Backplanes to be used with the VX3230 must be adequately specified The backplane must provide optimal power distribution for the 3 3 V 5 V and 12 V power inputs It is recommended to use only backplanes which have at least two power planes for the 3 3 V and 5 V voltages Input power connections to the backplane itself should be carefully specified to ensure a minimum of power loss and to guarantee operational stability Long input lines under dimensioned cabling or bridges high resistance connections etc must be avoided Page 90 CA DT A63 1e VX32
12. 73 445 Local 126 Data Register cuisine Ai 74 446 Interface Configuration Register 74 447 Firmware Configuration register 74 4 4 8 CPLD Interrupt 75 4 4 9 Watchdog Timer Control Register 76 4 4 10 GPIO Interrupt Configuration Register 77 4 4 11 Logic Revision Register 77 4 4 12 Host Reset Status Register 78 4 4 13 Host I O Status Register 78 4 4 14 Host I O Configuration Register 79 4 4 15 Board ID Register 79 4 4 16 GPIO Status Command 80 444 17 GPIO Control Register ta tes 80 4 4 18 User Specific LED Configuration Register 81 4 4 19 User Specific LED Control 82 4420 PCI Mode Register 82 4 4 21 Timer MSB Byte Register NER ER hh E
13. VX3230 RTM PB VX3 000 VX3230 VPX Rear Transition Module with PIM connectors 10 100 1000BASE TX Ethernet interfaces VX3230 RTM PB VX3 001 VX3230 VPX Rear Transition Module no PIM connector 10 100 1000BASE TX Ethernet interfaces VX3230 RTM PB VX3 010 VX3230 VPX Rear Transition Module with PIM connectors 1000BASE BX Ethernet interfaces VX3230 RTM PB VX3 011 VX3230 VPX Rear Transition Module no PIM connector 1000BASE BX Ethernet interfaces Table 44 Order Code Regarding the Ethernet interfaces manufacturing option it is strongly recommended to the to use a RTM and a SBC compatible gt same ethernet manufacturing option CA DT A63 1e Page 95 VX3230 RTM Characteristics VX3230 User s Guide VX3230 RTM PB VX3 000 with PIM connectors Figure 30 VX3230 RTM Overview Page 96 CA DT A63 1e VX3230 User s Guide VX3230 RTM Characteristics 6 2 Technical Specifications PB VX3 000 SPECIFICATIONS PB VX3 010 PB VX3 001 PB VX3 011 One USB 2 0 interface 4 pin connector Ethernet Up to two Gigabit Ethernet interfaces Y x1 implemented as dual RJ 45 connector ETH1 only without LEDs Front Panel Interfaces com One serial port COM1 RS 232 simplified RJ 11 connector One Push Button SATA Three SATA interfaces SATA1 SATA2 and SATA3 on bottom face V VPX connector for connecting Rear I O to the backplane on bottom Onboard face X OM SB C Interfaces One serial port COM2 implemented as
14. edge mode or on level 1 in level mode 6 2 sensitivity 0 R W 0 IRQ is activated on a falling edge in edge mode or on level 0 in level mode 1 IRQ is activated on a rising edge edge mode or on level E 1 in level mode 5 GPIO1 sensitivity 0 R W 0 IRQ is activated on a falling edge in edge mode or on level 0 in level mode 1 IRQ is activated on a rising edge in edge mode or on level 1 in level mode 4 GPIOO sensitivity 0 R W 0 IRQ is activated on a falling edge in edge mode or on level 0 in level mode 1 IRQ is activated on a rising edge edge mode or on level 1 in level mode 3 GPIO3 Interrupt mode 0 R W 0 GPIO3 IRQ is in edge mode 1 GPIO3 IRQ is in level mode 2 GPIO2 Interrupt mode 0 R W 0 2 IRQ is in edge mode deta 1 GPIO2 IRQ is in level mode 1 GPIO1 Interrupt mode 0 R W 0 GPIO1 IRQ is in edge mode 1 GPIO1 IRQ is in level mode 0 GPIOO Interrupt mode 0 R W 0 IRQ is in edge mode 1 GPIOO IRQ is in level mode 4 4 11 Logic Revision Register REGISTER NAME Logic Revision Register ADDRESS 0 000 0284 D A RIPTIO A 7 0 LR 7 0 Logic Revision N A R Start Value 0x01 WN This revision value starts with 0x01 and will be incremented with each change in hardware as development continues CA DT A63 1e Page 77 Programming Interface VX
15. 12 L3 gt L4 CA DT A63 1e red green red green red green red green red green red green red green Reset Thermal Alert PCI Activity CPU Checkstop Local Bus Activity Factory Mode SATA Activity ETHO On ETHO On ETHO On ETH1 On ETH1 On ETH1 On Link 10 Link 1000 Link 100 Link 10 Link 1000 Link 100 Blink Activity Blink Activity Blink Activity Blink Activity Blink Activity Blink Activity Introduction Page 13 Introduction VX3230 User s Guide 1 4 3 VX3230 Components Layout PowerPC PCI E 8544 1 GHz Figure 6 VX3230 Components Layout Top View PHY PHY 8 ETH ETH USB Bridge Boot EEPROM Flash Figure 7 VX3230 Board Components Layout Bottom View Page 14 CA DT A63 1e VX3230 User s Guide Introduction 1 5 Technical Specification VX3230 SPECIFICATIONS Processor Freescale MPC8544 running at 1 GHz 32 bit PowerPC E500 Core Double precision embedded scalar and vector floating point APUs Memory Management Unit MMU Integrated Security Engine Cache Structure L1 cache 32 KB Data 32 KB Instruction L2 cache 256 KB 5000000 go Gigabit Ethernet Controller Two on chip triple speed Ethernet controllers supporting 10 Mbps 100 Mbps and 1 Gbps Ethernet IEEE 9802 3 networks with SGMII utilization Memory Controller Integrated DDR2 memory controllet with ECC support up to 533 MHz 7
16. 40 Table 19 VPX Connector PO Signal 41 Table 20 VPX Connector P1 Wafer Assignment 10 100 1000BASE6TX Ethernet Manufacturing Option 42 Table 21 VPX Connector P1 Wafer Assignment 1000BASE BX Ethernet Manufacturing Option 43 Table 22 VPX Connector P1 Signal 44 Table 23 USB Port Features 2 2 prod et el RET be RP pidge 45 Table 24 Ethernet Port Features 45 Table 25 SATA Port Features 45 Table 26 VPX Connector P2 Wafer 1 46 Table 27 VPX Connector P2 Signal 46 Table 28 PMC J11 Connector Pin Assignment 1 47 Table 29 PMC J12 Connector Pin Assignment 47 Table 30 PMC J14 Connector Pin Assignment 48 Table 31 PMC Signal Description 50 Table 32 J15 Connector Pin Assignment 51 Table 33 Signal Description 2 52 Tabl
17. page 9 for more information on the ethernet configuration depending on the ethernet board manufacturing option Refer to section 2 8 4 2 VPX Connectors Description page 40 for more information on the gigabit ethernet wafer assignment on P1 connector Front Panel Gigabit Ethernet Gigabit Ethernet ETHO ETH1 Figure 16 Dual Gigabit Ethernet Connector The Ethernet transmission can operate effectively using a CAT5 cable with a maximum length of 100 m LIN N The Ethernet connectors are realized as RJ 45 connectors The interfaces provide automatic detection and switching between 10Base T 100Base TX and 1000Base T data transmission Auto Negotiation Auto wire switching for crossed cables is also supported Auto MDI X CA DT A63 1e Page 37 Functional Description 2 8 3 1 ETHO and ETH1 Pinouts VX3230 User s Guide The ETHO ETH1 connectors supply the 10Base T 100Base TX and 1000Base T interfaces to the Ethernet controller 10BASE T 100BASE TX 1000BASE T SIGNAL SIGNAL SIGNAL 1 TX TX 1 0 BI_DA 2 TX 1 0 BI_DA 3 RX RX 1 0 BI_DB 4 1 0 BI_DC 5 1 0 BI_DC 6 TX RX 1 0 BI_DB 7 VO BI_DD 8 1 0 BI_DD Table 17 Gigabit Ethernet Connectors ETHO and ETH1 Pin Assignment CA DT A63 1e Page 38 VX3230 User s Guide Functional Description 2 8 4 VPX Bus Interface The complete VPX conne
18. 3 GND Ground 4 GND Ground COM2 COM2 RXD RXDa 1 EIA 232Receive Data EIA 485 Receive Data pair a o COM2 6 COM2 CTS RXDb 1 EIA 232 Clear To Send ElA 485 Receive Data pair 7 GPIO 1 General Purpose lO 1 A e 8 GND Ground 9 2 General Purpose lO 2 CN17 R 1 Pins 1 2 5 and 6 can be used to populate a specific differential termination for COM1 and COM2 when used in EIA 422 or EIA 485 Table 51 Onboard GPIO Connector Pin Assignment Figure 43 Onboard GPIO Connector Page 110 CA DT A63 1e VX3230 User s Guide VX3230 RTM Characteristics 6 5 6 JTAG Connector Routed from RPO to CN18 R connector right angle HE10 10 pin connector male PIN SIGNAL FUNCTION 1 TCK JTAG Test Clock 2 GND Ground 3 TDO JTAG Test Data Out 4 3 3V sense 5 TMS JTAG Test Mode Select o 6 N C Not Connected 2 7 Not Connected E 8 TRST JTAG Test Reset a a 9 TDI JTAG Test Data In 10 GND Ground CN18 R signal active when low Table 52 Onboard JTAG Connector Pin Assignment Figure 44 Onboard JTAG Connector CA DT A63 1e Page 111 VX3230 RTM Characteristics VX3230 User s Guide 6 5 7 12C System Management Connector Routed from RPO to CN20 R connector right angle HE10 10 pin connector male PIN SIGNAL FUNCTION 1 SMBO CLK SM Bus 0 Serial Clock 2 SMB1 CLK SM Bus 1 Serial Clock 3 GND Ground 4 GND Ground m N 5 SMBO DAT
19. 4 N C Not Connected 5 USBD Differential USB 10 9 6 Not Connected 7 GND GND 8 N C Not Connected 9 Not Connected ES 2 1 10 Not Connected CN21 R 4 Figure 38 Onboard USB Connector Table 48 Onboard USB Connector Pin Assignment The USB Flash module is fixed to the board by using on one side the CN21 R connector and on the other side standoff screwed to the VX3230 RTM board and to the USB Flash module to standoff 5 5 5 8 ij Figure 39 USB Flash Disk Overview Order Code for the USB flash disk FDM USB xGB 2MM IV industrial version with conformal coating for use with rugged versions x 4 or 8 GB N Contact Kontron for available capacity Page 106 CA DT A63 1e VX3230 User s Guide VX3230 RTM Characteristics USB Flash Disk Layout Maximum space reserved for USB flash disk is 36 9 mm x 26 6 mm LxW The distance between connector and screw hole is 27 3 mm 27 9mm Maximum allowable connector height is 3 68 mm 145 3 68 mm High 1 45 36 9 mm M 1 05 26 6 mm 24 6 0 mm 1 18 4 5 mm 1 08 27 5 mm 19 4 9 mm ON gt OFF c gt Figure 40 USB Flash Disk Layout CA DT A63 1e Page 107 VX3230 RTM Characteristics VX3230 User s Guide 6 5 3 Gigabit Ethernet Interfaces The Ethernet connectors are realized as RJ 45 connectors The interfaces provide automatic detecti
20. IRQ9 signal When a thermal interrupt occurs the temperature alert indicator LED1 in red is switcghed on until the bit TEMp_LED of the CPLD Interrupt register is cleared CA DT A63 1e Page 75 Programming Interface VX3230 User s Guide 4 4 9 Watchdog Timer Control Register REGISTER NAME Watchdog Timer Control ADDRESS 0 000 0282 RESET BIT NAME DESCRIPTION VALUE 55 7 WTE Watchdog timer expired status bit 0 R 6 5 WMD 1 0 Watchdog Mode 00 R W 00 Timer only mode 01 Reset mode 10 Interrupt mode 11 Cascaded mode dual stage mode 4 WEN WTR Watchdog enable Watchdog trigger control bit 0 RIW 0 Watchdog Timer not enabled 1 Watchdog Timer enabled Watchdog Trigger See also WDG bit register OXF000 0287 3 0 WTM Watchdog Timer timeout Time 0 R W 0000 0 125 s 0001 0 25 s 0010 0 5s 0011 1s 0100 26 0101 45 0110 86 0111 16s 1000 2 32s 1001 645 1010 128 s 1011 256 1100 reserved 1101 1110 reserved 1111 76 CA DT A63 1e VX3230 User s Guide Programming Interface 4 4 10 GPIO Interrupt Configuration Register REGISTER NAME GPIO Interrupt Configuration ADDRESS 000 0283 RESET BIT DESCRIPTION VALUE ACCESS 7 GPIO3 sensitivity 0 R W 0 IRQ is activated on a falling edge in edge mode or on level 0 in level mode 1 IRQ is activated on a rising edge
21. LIN N 4x VIS CZX M2X5 INOX For the ribs assembly on the board black marks below gt 10x VIS CZX M2 5X6 INOX For the PMC assembly on the ribs 6x For the PMC assembly on the board 4x red marks below gt 10x VIS CZX M2X6 INOX For PMC assembly on the board blue marks below THE 500000011601 Ns 1 Figure 52 Usage of Fastening Kit Ribs VX3230 RC Board Page 130 CA DT A63 1e G kontron MAILING ADDRESS TELEPHONE AND E MAIL Kontron Modular Computers S A S 33 0 4 98 16 34 00 150 rue Marcelin Berthelot BP 244 sales kontron com 21 TOULON EST support kom sa kontron com 83078 TOULON CEDEX France For further information about other Kontron products please visit our Internet web site www kontron com If it s embedded it s Kontron
22. Page 62 CA DT A63 1e VX3230 User s Guide Installation 3 7 Installation of Peripheral Devices VX3230 is designed to accommodate a variety of peripheral devices whose installation varies considerably The following chapters provide information regarding installation aspects and not detailed procedures 3 7 1 USB Device Installation The VX3230 supports all USB plug and play computer peripherals All USB devices may be connected or removed while the host or other peripherals are powered up gt gt USB Flash Disk Installation The USB Flash module is fixed to the board by using on one side the CN5 connector to screw c on the other side a screw 1 maintained on the VX3230 board allows the USB Flash module to be screwed with a nut 2 SG9EDS144GGCN DMK090306F07 m ASSEMBLED IN MALAYSIA 2 Nut G 6 mm 1 Screw Figure 25 USB Flash Installation CA DT A63 1e Page 63 Installation VX3230 User s Guide 3 7 2 Battery Replacement The lithium battery must be replaced with an identical battery or a battery type recommended by the manufacturer Thin plastic tool XX To replace the battery proceed as follows gt Turn off power gt Use a thin plastic tool to push the battery outside the safety cache Push from the right or left top side of the safety cache gt Remove the battery gt Place the new battery in the socket gt Make sure that you insert the battery the right
23. VPX reset 1 R W 0 Generate VPX reset 1 1 VPX2LOC Propagation of VPX reset SYSRESET to the local 1 R W reset 0 Reset not propagated 1 Reset propagated 0 LOC2VPX Propagation of local reset Toggle Switch to the VPX RAW reset SYSRESET SYSCON 0 Reset not propagated 2 1 Reset propagated fete VPX Reset generated only if LOC2VPX 1 UN Reset value 1 when System slot 0 when Peripheral slot N CA DT A63 1e Page 85 Programming Interface VX3230 User s Guide 4 4 29 Geographical Addressing Register REGISTER NAME Geographical Addressing ADDRESS 0 000 0297 RESET BIT DESCRIPTION VALUE ACCESS 7 SYSCON VPX System Controller N A R 0 System Controller 1 Not System Controller 6 Res Reserved 0 R 5 GAP Geographical Address Parity N A R 4 0 GA Geographical Address N A R 4 4 30 VPX Common Clock Register REGISTER NAME VPX Common Clock ADDRESS 000 0298 RESET BIT NAME DESCRIPTION VALUE 55 7 4 Reserved 0 R 3 CLK EN1 P1 PCle VPX Clock 7 4 Generation 1 R W 0 Enable 1 Disable 2 CLK_ENO P1 PCle VPX Clock 3 0 Generation 1 R W 0 Enable 1 Disable 1 OE PCle VPX Common Clock Activation 1 R W 0 Enable 1 Disable 0 CLK_SEL PCle VPX Common Clock Direction 1 R W 0 Enable 1 Disable Page 86 CA DT A63 1e VX3230 User s Guide Progr
24. 124 71 2 Board Identification iiis sis dou 125 7 3 Environmental Specifications 126 TA MTBF Data a edd 126 7 5 Peripheral Connectivity 127 76 Installation 128 CA DT A63 1e Page viii Table Of Contents VX3230 User s Guide List Of Figures Figure 1 VX3230 SA Overview 2 Figure 2 VX3230 Functional Block Diagram 1 11 Figure 3 VX3230 Functional Block Diagram Type 2 12 Figure 4 Front Panel Connectors 2 13 Figure 5 Reset Button and 13 Figure 6 VX3230 Components Layout View 14 Figure 7 VX3230 Board Components Layout Bottom View 14 Figure 8 MPC8544 Block Diagram 4 4 24 Figure 9 Location of Board and Processor Sensors 30 Figure 10 VX3230 Connectors Layout
25. 45 GND 46 N C 47 N C 48 N C 49 N C 50 GND 51 N C 52 N C 53 5V 54 N C 55 N C 56 N C 57 N C 58 3 3V 59 N C 60 N C 61 12V_AUX 62 N C 63 N C 64 N C Signal Description D RIPTIO 12V AUX Auxiliary Power Supplies 3 3V 3 3V Power Input 5V 5V Power Input GND Ground N C Not Connected CA DT A63 1e Page 121 VX3230 RTM Characteristics VX3230 User s Guide 6 9 2 414 Connector J14 Connector Pin Assignment SIGNAL FUNCTION 01 PMC64 IO 01 01 of the motherboard 64 PMC64 IO 64 64 of the motherboard Page 122 CA DT A63 1e VX3230 User s Guide VX3230 RC Characteristics Chapter 7 VX3230 RC Characteristics o e 1 Figure 48 VX3230 RC Overview Several manufacturing options are available gt 10 100 1000BASE TX or 1000BASE BX Ethernet interfaces Available order codes are listed in table below 0 513 4010 B DESCRIPTION 3U VPX Rugged Conduction Cooled Build SBC VX3230 RC VX3230 RCA1N 000 3230 Rugged Conduction Cooled Build 1GB SDRAM No User Flash slot 10 100 1000BASE TX Ethernet interfaces VX3230 RC VX3230 RCA1N 010 VX3230 Rugged Conduction Cooled Build 1GB SDRAM No User Flash XMC PNC slot 1000BASE BX Ethernet interfaces Associated Products Kit Rib PMC KIT RIBPMC1V01 1 Fastening kit for a rugged conduction cooled PMC Table 61 VX3230
26. Auto Selection Force 1000BASE T Auto Selection VX3230 User s Guide 10 100 1000BASE TX on front panel 10 100 1000BASE TX on front panel or 1000BASE BX on backplane 10 100 1000BASE TX on backplane 10 100 1000BASE TX on backplane or 1000BASE BX on backplane 1 Lan Switch configured via the Host Configuration register see section 4 4 14 page 79 2 Interface Mode configured via the Open VPX register see section 4 4 32 page 88 Page 10 CA DT A63 1e VX3230 User s Guide Introduction 1 4 Board Diagram The following diagrams provide additional information concerning board functionality and component layout 1 4 1 Functional Block Diagram Serial EIA 232 485 Dual SATA USB Dual ETH 2x GPIO 4x PCI E USB1 XMC PMC 1 2 1 to Front Panel Figure 2 VX3230 Functional Block Diagram Type 1 CA DT A63 1e Page 11 Introduction VX3230 User s Guide GPIOs User x 2 PHY ETH D DDR2 533 MHz DDR2 memory controller Local bus controller T EV sensor gt 2 02 EEPROM System Figure 3 VX3230 Functional Block Diagram Type 2 Page 12 CA DT A63 1e VX3230 User s Guide 1 4 2 Front Panel VX3230 H COM1 USB VX3230 Reset Button Reset L2 ETHO Gigabit Ethernet ETH1 TOS L3 L4 Figure 5 Reset Button and LEDs Status LEDs Default Settings L1
27. GND 3 VBAT GND PEX TXL2 PEX TXL2 GND PEX RXL2 PEX RXL2 4 GND PEX TXL3 PEX TXL3 GND PEX RXL3 PEX RXL3 GND 5 SYS_CON GND Reserved Reserved GND Reserved Reserved 6 GND Reserved Reserved GND Reserved Reserved GND 7 REFCLKO SE GND Reserved Reserved GND Reserved Reserved 8 GND Reserved Reserved GND Reserved Reserved GND 9 GND GND 10 GND GND GND 11 GND Reserved Reserved GND Reserved Reserved 12 GND GND GND 13 GND GND 14 GND GND GND 15 GND GND 16 GND GND GND CASE GND signal active when low Table 21 VPX Connector P1 Wafer Assignment 1000BASE BX Ethernet Manufacturing Option CA DT A63 1e Page 43 Functional Description VX3230 User s Guide P1 Signal Definition MNEMONIC SIGNAL DEFINITION ETHxBI_DA 10 100 1000BASE TX Ethernet First pair of Transmit Receive data ETHx BI_DB 10 100 1000BASE TX Ethernet x Second pair of Transmit Receive data ETHx BI_DC 10 100 1000BASE TX Ethernet x Third pair of Transmit Receive data ETHx BI_DD 10 100 1000BASE TX Ethernet x Fourth pair of Transmit Receive data ETHx RX 1000BASE BX Ethernet x Receive data ETHx TX 1000BASE BX Ethernet x Transmit data GND Ground GPIOx General Purpose x N C RFU Not Connected Reserved for Future Use PEX RXLy x4 PCI Express Link Receive Lane y PEX TXL y x4 PCI Express Link Transmit Lane y REFCLKO_SE Single Ended Re
28. PCI Express 2 I O 16 0000 6 2 PCI Express 1 I O 16 200 0000 3 0 PCI I O 16 100 0000 Unused 15 MB 0xE010_0000 CCSRBAR 1MB 0xE000 0000 2 0 PCI MEM 512 0 000 0000 Unused 224 MB 0 200 0000 9 3 PCI Express I O 16 0xB100_0000 9 3 PCI Express 3 MEM 16MB 0xB000 0000 7 1 PCI Express 2 MEM 512 0 9000 0000 5 2 1 256 0 8000 0000 1 DDR2 SDRAM 2GB 0 0000 0000 70 Table 38 Memory Mapping CA DT A63 1e VX3230 User s Guide 4 3 CPLD System Registers Mapping Addre Programming Interface Firmware POST Code 0xF000_0080 OxF000 0081 section 4 4 1 Debug POST Code 0 000 0084 OxF000_0085 section 4 4 2 Memory Configuration 0 000 0002 section 4 4 3 Local 2 Command 000 0004 section 4 4 4 Local 2 Data 0 000 0005 section 4 4 5 Reserved 0 000 0006 Interface Configuration 0 000 0008 section 4 4 6 Reserved 0 000 0009 Firmware Configuration 0 000 0280 section 4 4 7 CPLD Interrupt 000 0281 section 4 4 8 Watchdog Timer Control 0 000 0282 section 4 4 9 GPIO Interrupt Configuration 000 0283 section 4 4 10 Logic Revision 000 0284 section 4 4 11 Host Reset Status 000 0285 section 4 4 12 Host I O Status 0 000 0286 section 4 4 13 Host I O Conf
29. PCI Express 4 x1 PCI Express links connected to VPX backplane P1 or 1 x4 PCI Express link connected to VPX backplane P1 Front Interfaces Refer to section 1 3 3 I O Interfaces page 7 Rear Interfaces Refer to section 1 3 3 I O Interfaces page 7 PMC XMC Site 33 MHz 32 bit PCI or x4 XMC interface 3 3V only USB Mezzanine Card USB mezzanine card interface compatible with SMART MODULAR product family Debug Interface JTAG COP port for emulation probe connection Firmware U Boot Operating Systems Fedora 9 Mechanical 3U VPX compliant form factor Power Supply 3 3 V 5V 12V if required for mezzanine board Power Consumption 5 VDC Total Under U Boot typical 12 33 W 14 W maximal 13 55 W 15 23 W Under OS typical 15 74 W 17 7 W maximal 16 W 17 95 W Standard Commercial Refer to section 1 7 1 Environmental Specifications page 19 Environmental Specification Rugged Conduction Cooled Refer to section 1 7 1 Environmental Specifications page 19 Environmental Specification Dimensions 99 85 mm x 162 54 mm Board Weight SA environmental class 210g with heat sink RC environmental class 280g with ruggedizer MTBF Refer to section 1 5 1 MTBF Data page 17 Page 2 of 2 Table 6 VX3230 Main Specifications For a detailed description of the VX3230 RTM Rear Transition Module refer to the Technical 9 Specifications table in Chapter 6 VX3230 RTM Characteristics section 6 2 Tehcnical Speci
30. System Memory PCI Express Buses gt Section 2 2 1 page 25 MPC8544 PCI Express Links gt Section 2 2 2 page 25 Internal PCI Express Links Section 2 3 page 26 Storage gt Section 2 3 1 page 26 Flash Memory gt Section 2 3 2 page 26 Serial EEPROMs gt Section 2 3 3 page 26 SPI EEPROM gt Section 2 3 4 page 26 NOVRAM gt Section 2 3 5 page 26 Dual Serial ATA Section 2 4 page 27 Peripherals gt Section 2 4 1 page 27 Timer gt Section 2 4 2 page 27 Watchdog Timer Section 2 5 page 27 Section 2 6 page 28 System FPGA 12C Buses gt Section 2 6 1 page 28 Internal 2 Buses gt Section 2 6 2 page 28 RTC gt Section 2 6 3 page 28 VPD EEPROM gt Section 2 6 4 page 29 Thermal Sensor gt Section 2 6 5 page 31 Voltage Sensor gt Section 2 6 6 page 31 External SM bus Section 2 7 page 32 CA DT A63 1e Connectors Layout Page 21 Functional Description Section 2 8 page 33 gt Section 2 8 1 page 33 Section 2 8 2 page 34 Section 2 8 3 page 37 Section 2 8 4 page 39 Section 2 8 4 1 page 39 Section 2 8 4 2 page 40 Section 2 8 5 page 47 Section 2 8 6 page 47 Section 2 8 7 page 48 Section 2 8 8 page 49 Section 2 8 9 page 51 Section 2 8 10 page 52 Section 2 8 11 page 53 gt Section 2 8 12 page 53 V MV V V MV MV MV MV V V Section 2 9 page 54 Page 22 VX3230 User s Guide Board Interfaces Serial Interfaces USB Interfaces Gigabit Ethernet Interfaces VPX Bus Interface Board C
31. The 32 bit PCI bus of the VX3230 and the PMC plugged on the 32 bit PCI slot have to operate on the same signaling level The VX3230 sets the signaling level for the 32 bit PCI bus to 3 3V i e V 1 0 3 3V The V I O pins of the PCI 32 PMC are connected to 3 3V The distinction between PMC types is the signaling level they use not the power rails they connect to nor the component technology they contain On the VX3230 PCI 32 XMC PMC slot only two XMC PMC types must be intalled 3 3V PMC It is designed to work only in a 3 3V signaling level and will only have a keying hole Universal PMC It supports both voltages 5V and 3 3V This PMC is capable of detecting the signaling level in use and adapting itself to that environment It has two keying holes 5V and 3 3 V and can therefore be plugged into either signaling level 5V Key hole 3 3V Key hole As no PMC voltage selection key is provided on the board make sure not to insert a 5V PMC on the board Failture to observe this restriction may result in damage to the PMC or the VX3230 5V Key hole CA DT A63 1e Page 55 Installation VX3230 User s Guide Chapter 3 Installation The VX3230 has been designed for easy installation However the following standard precautions installation procedures and general information must be observed to ensure proper installation and to preclude damage to the board other system components or injury to pers
32. hardware preparation and installation instructions operating instructions and a functional description of the VX3230 board The onboard programming onboard firmware and other software e g drivers and BSPs are described in detail in separate guides see section 1 8 Related Publications As the standard policy for all the Kontron hardware technical documentation reflects the most recent version of our products Hardware Release Notes see section 1 8 Related Publications is to help to keep track of various evolutions that have happened during the early steps of the VX3230 ramp up or later in its lifetime Nota Functional changes that differ from previous version of the document are identified by a vertical bar in the Me margin 1 1 2 Audience This guide is written to cover as far as possible the range of people who will handle or use the VX3230 from unpackers inspectors through system managers and installation technicians to hardware and software engineers Most chapters assume a certain amount of knowledge on the subjects of single board computer architecture interfaces peripherals systems cabling grounding and communications 1 1 3 Scope This guide describes all variants of the VX3230 series It does not cover any PMC modules which are described in specific guides see section 1 8 Related Publications 1 1 4 Structure This guide is structured in a way that will reflect the sequence
33. site and to the VPX specification on the VITA web site http www vita com 5 1 3 1 Start Up Requirement Power supplies must comply with the following guidelines in order to be used with the VX3230 gt Beginning at 10 of the nominal output voltage the voltage must rise within gt 0 1 ms to lt 20 ms to the specified regulation range of the voltage Typically gt 5 ms to lt 15 ms gt There must be a smooth and continuous ramp of each DC output voltage from 10 to 90 of the regulation band gt The slope of the turn on waveform shall be a positive almost linear voltage increase and have a value from 0 V to nominal Vout gt Maximal power supplies needs during a system start up VCC 1 23A max during 1 6 milli sec VDD 2 21A max during 400 micro sec 5 1 3 2 Power Up Sequence The 5 VDC output level must always be equal to or higher than the 3 3 VDC output during power up and normal operation The time from 5 VDC until the output reaches its minimum in regulation level and from 3 3 VDC until the output reaches its minimum in regulation level must be 20 ms CA DT A63 1e Page 91 Power Considerations VX3230 User s Guide 5 1 3 3 Tolerance The tolerance of the voltage lines is described in the VITA specification VITA 46 0 The recommended measurement point for the voltage is the VPX connector on the CPU board The following table provides information regarding the required characteristics for each b
34. slot 3 3V signaling 5 LEDS reporting main interfaces activities Board Reset Button Table 3 Front I O Interfaces PMC XMC slot Manufacturing Option Rear Interfaces FUNCTION DESCRIPTION VPX standard on PO P1 P2 PMC I Os 64 bits of I Os PMC on P2 Gigabit Ethernet Depending on Ethernet interfaces manufacturing option Up to 2 1000BASE T on P1 VITA 46 9 configurable by firmware or Up to 2 1000BASE BX on P1 VITA 46 9 configurable by firmware GPIOs 2x user GPIOs on P1 SMB 2x System Management Bus on PO Table 4 Rear I O Interfaces CA DT A63 1e Page 7 Introduction VX3230 User s Guide Peripheral Connectivity VX3230 SA VX3230 SA VX3230 RTM FUNCTION no PMC XMC slot PMC XMC slot Front Panel Onboard Front Panel Onboard Front Panel Onboard USB1 Y Flash Y Flash Y Flash mod mod EM mod a ANNE _ p cL ECC um om Y X do Table 5 Peripheral Connectivity Page 8 CA DT A63 1e VX3230 User s Guide Introduction 1 3 4 Ethernet Connectivity Depending on the Ethernet interface manufacturing option and gt 10 100 1000BASE TX Ethernet interfaces The Ethernet channels of the MPC8544 can be routed either to the front panel RJ 45 connectors or to the VPX P1 connectors thanks to the use of the LAN Switch Texas instrument TS3L301 Front panel interface is connected to RJ 45 conne
35. 6 GND PMCIO 53 PMCIO 55 GND PMCIO 54 PMCIO 56 GND P2 w14 7 COM2 GND PMCIO 57 PMCIO 59 GND PMCIO 58 PMCIO 60 P2 w15 RXD RXDa 8 GND PMCIO 61 PMCIO 63 GND PMCIO 62 PMCIO 64 GND P2 w16 CASE GND Table 54 Rear I O VPX Connector RP2 Wafer Assignment RP2 Signal Definition MNEMONIC SIGNAL DEFINITION COM2 CTS RXDb Channel EIA 232 x Clear To Send EIA 485 Receive Data pair b COM2 RTS TXDb COM2 RXD RXDa Channel EIA 232 x Ready To Send EIA 485 Transmit Data pair b Channel EIA 232 x Receive Data ElA 485 Receive Data pair a COM2 TXD TXDa Channel EIA 232 x Transmit Data EIA 485 Transmit Data pair a GND Ground PMCIO 33 64 PCI PMC signals I Os signals from PMC connector J14 to RP2 connector Table 55 Rear I O VPX Connector RP2 Signal Definition CA DT A63 1e Page 115 VX3230 RTM Characteristics VX3230 User s Guide 6 8 2 RP1 Connector Wafer Assignment RP1 wafer pin assigment for wafers 5 up to 8 depends on the Ethernet manufacturing option Refer to Table 56 and Table 57 below gt Legend for Table 56 Gigabit Ethernet port GPIO COM1 Serial port Serial ATA port PMC I O USB port 2 RO RO ROWD RO ROWB ROW A i 1 GND GND P1 w09 2 GND GND GND P1 w10 3 GND GND P1 w11 4 GND GND GND P1 12 5 GND GND P1 w13 6 GND GND GND P1 w14 7 GND GND P1 15 8 GND GND GND 1 16 9 GND GND 2 01 10 GND GND GND P2 w02 11 GND
36. 7 2 SM Connector page 112 Reset See section 6 6 Reset page 113 RPO RP1 RP2 See section 6 8 Rear I O Interfaces page 114 gt J10 J14 See section 6 9 PCI 64 PIM Connector page 121 CA DT A63 1e Page 103 VX3230 RTM Characteristics VX3230 User s Guide 6 5 Modules Interfaces 6 5 1 COM Interfaces The VX3230 RTM provides two COM COM1 and COM2 ports for connecting devices to the VX3230 RTM COM1 serial port RJ 11 connector is located on the front panel of the RTM 2 serial port RJ 11 connector is located onboard gt COM1 ElA 232 ElA 485 Simplified COM2 ElA 232 ElA 485 Simplified The following figure and table provide pinout information for the 6 pin RJ 11 COM1 connector CN10 R located on the board front panel the 6 pin RJ 11 COM2 connector CN19 R located onboard SIGNAL FUNCTION ElA 232 Ready To Send RTS TXDb ElA 485 Transmit Data pair b Shell Chassis Ground EIA 232 Transmit Data TXD TXDa ElA 485 Transmit Data pair a ElA 232Receive Data RXD RXDa 485 Receive Data pair GND Ground ElA 232 Clear To Send CTS RXDb ElA 485 Receive Data pair b Table 46 Serial Port Connector Pin Assignment Figure 36 Serial Port Connector Page 104 CA DT A63 1e VX3230 User s Guide VX3230 RTM Characteristics 6 5 2 USB Interfaces There are two USB 2 0 ports available on the VX3230 RTM each with a maximum transfer rate of 480 Mb s provided for connec
37. BI_DC Table 49 Gigabit Ethernet Connectors Pin Assignment Page 108 CA DT A63 1e VX3230 User s Guide VX3230 RTM Characteristics 6 5 4 Serial ATA Interfaces The onboard Serial ATA connectors CN14 R CN15 R and CN16 R allow the connection of standard HDDs and other Serial ATA devices to the VX3230 Rear Transition Module The following figure and table provide pinout information for the SATA connectors CN14 R CN15 R and CN16 R SIGNAL FUNCTION 1 0 1 GND Ground signal 2 SATA_TX Differential Transmit O 1 3 SATA Differential Transmit O br 4 GND Ground signal 7 7 4 5 SATA RX Differential Receive 6 SATA_RX Differential Receive CN1 6 R En uh 7 GND Groudn Signal Table 50 Onboard SATA Connectors Pin Assignment Figure 42 Onboard SATA Connectors uu When using a Serial ATA cable it is recommended to use a special right angled Serial ATA cable due to possible space limitations within the system For further information contact Kontron s Technical Support CA DT A63 1e Page 109 VX3230 RTM Characteristics VX3230 User s Guide 6 5 5 GPIO Connector Routed from RP1 to CN17 R connector right angle HE10 10 pin connector male PIN SIGNAL FUNCTION COM1 COM1 RXD RXDa 1 EIA 232Receive Data ElA 485 Receive Data pair a COM1 2 COM1 CTS RXDb 1 EIA 232 Clear To Send ElA 485 Receive Data pair b
38. RC Order Code CA DT A63 1e Page 123 VX3230 RC Characteristics VX3230 User s Guide 7 1 WX3230 RC Specificities FUNCTION DESCRIPTION SEE ALSO Battery No battery available onboard Board Identification Specific ruggedizer identification Section 7 2 page 125 Environmental Environmental specifications depend on environmental class Section 7 3 page 126 Specifications Section 1 7 1 page 19 MTBF MTBF depends on the environmental class Section 7 4 page 126 Section 1 5 1 page 17 Peripheral No connector available on the board front panel Section 7 5 page 127 Connectivity Table 62 VX3230 RC Specificities Page 124 CA DT A63 1e VX3230 User s Guide VX3230 RC Characteristics 7 2 Board Identification The VX3230 RC boards are identified by labels fitted on top and bottom sides These labels are at the same location and have the same meaning as the VX3230 SA boards refer to section 3 2 Board Identification page 57 In addition the ruggedizer identified by AA Ruggedizer Identification printed on the ruggedizer AB Ruggedizzer dated from printed on the ruggedizer AC Ruggedizer Engineering Change Level E C Level label V N a ez om om om ez aS Figure 49 VX3230 RC Identification Top Side CA DT A63 1e Page 125 VX3230 RC Characteristics VX3230 User s Guide 7 3 Environmental Specifications ENVIRONMENTAL SPECIFICATION
39. To avoid ESD damage the board should be wear an antistatic wrist strap to discharge static electricity PMC Site can alternately be used as an XMC site with a x4 PCI Express link to the MPC864x processor A XMC card installed in this location uses its P5 J15 on the VX3230 for the Express Link The installed XMC should provide either front panel I O or utilize P4 J14 on the VX3230 for I O The following table sums up all information concerning the PCI 32 XMC PMC Site It gives information needed for software and hardware configuration FUNCTION VALUE DESCRIPTION Connects the signals for the 32 bit PCI bus PMC Connectors Connects the signals for the 32 bit PCI bus Connects the User Defines signals Connects the signals for the switched AME Connector communications The signaling voltage of the 32 bit PCI bus is 3 3V It is not 5V tolerant V I O Voltage Level The user must check that its PMC type is compatible with this signaling voltage refer to section 2 9 1 page 55 PCI Bus Mode 32 Bits The 32 bit PCI bus is in 32 bit mode The 32 bit PCI bus can run at 33 MHz refer to PCI Bus Rate 33 MHz the Hardware Release Notes for possible restrictions PCI Interrupts Connected to the Interrupt Controller REQ GNT 0 IDSEL AD 18 For single function PMC s Table 36 PCI 32 XMC PMC Site Information Page 54 CA DT A63 1e VX3230 User s Guide Functional Description 2 9 1 Signaling Voltage Keying Pin
40. a RJ 11 onboard connector RS 232 simplified GPIOs Two General Purpose I Os module installed Y mae yy uc Y Y Y PM PCI 64 PIM connector Temperature Operational 0 C to 55 C Range Storage 55 C to 85 C General Climatic Humidity 99 non condensing U 12 Dimensions 99 85 mm x 82 54 mm Board Weight 120g Table 45 VX3230 RTM Main Specifications CA DT A63 1e Page 97 VX3230 RTM Characteristics 6 3 Configuration VX3230 User s Guide Figure 31 VX3230 RTM MicroSwitch Location MicroSwitch SW2 FUNCTION NVMRO Non Volatile Memory Read Only COM Differential Termination 2 Differential Termination Page 98 DESCRIPTION ON 0 OFF 1 Set NVMRO VPX signal to Ground No action on NVMRO VPX signal Default setting Reserved ON 0 Connect a 100 Ohms parallel termina tion between RXD and RXD OFF 1 No differential termination mode Default setting ON 0 tion between RXD and RXD Connect a 100 Ohms parallel termina OFF 1 No differential termination mode Default setting CA DT A63 1e VX3230 User s Guide VX3230 RTM Characteristics 6 4 Connectors 6 4 1 RTM Connectors Identification Alignment Keying Pins Alignment Keying Sockets Figure 32 Connector Identification for 3U RTM CA DT A63 1e Page 99 VX3230 RTM Characteristics V
41. for more information on P1 wafer assignment Page 26 CA DT A63 1e VX3230 User s Guide Functional Description 2 4 Peripherals The following standard peripherals are available on the VX3230 board 2 4 1 Timer The VX3230 is equipped with the following timers Real Time Clock RTC The VX3230 is equipped with an onboard high precision real time clock RV 8564 C2 it provides a very tight frequency tolerance at low power consumption This RTC provides a programmable clock output interrupt output and voltage low detector All address and data are transferred serially via the 2 bus The is connected to the second 2 controller of the MPC8544 at 12C address 0x51 Read 2 slave address A3h Write 12C slave address A2h Nominal operating voltage 3 3V Minimal clock operating voltage 1 2V A 3V RTC backup battery can be equipped in a keystone socket This battery supports extended temperature range 40 85 C gt Hardware delay timer for short reliable delay times 2 4 2 Watchdog Timer The VX3230 provides a Watchdog Timer that is programmable for a timeout period ranging from 125 ms to 256 s in 12 steps Failure to trigger the Watchdog Timer in time results in an interrupt or a system reset In the dual stage mode a combination of both interrupt and reset is generated if the Watchdog is not serviced A hardware status flag will be provided to determine if the Watchdog Timer generated the r
42. in input mode 1 R W GPIO 2 Command in output mode 1 GPIO1 Status in input mode 1 R W GPIO1 Command in output mode 0 GPIOO Status in input mode 1 R W GPIOO Command in output mode 4 4 17 GPIO Control Register REGISTER NAME GPIO Control ADDRESS OxF000 028A B A D RIPTIO A 7 GPIO3 interrupt activation 0 RAW 0 GPIO3 interrupt mode is disabled 1 GPIO3 interrupt mode is enabled 6 GPIO2 interrupt activation 0 R W 0 GPIO2 interrupt mode is disabled 1 GPIC2 interrupt mode is enabled 5 GPIO1 interrupt activation 0 R W 0 GPIO1 interrupt mode is disabled 1 GPIO1 interrupt mode is enabled 4 GPIOO interrupt activation 0 R W 0 GPIOO interrupt mode is disabled 1 GPIOO interrupt mode is enabled 3 GPIO3 mode 0 R W 0 GPIO3 is configured in input 1 GPIO3 is configured in output 2 GPIO2 mode 0 R W 0 GPIO2 is configured in input 1 GPIO2 is configured in output 1 GPIO1 mode 0 R W 0 GPIO1 is configured in input 1 GPIO1 is configured in output 0 GPIOO mode 0 R W 0 GPIOO is configured in input 1 GPIOO is configured in output Page 80 CA DT A63 1e VX3230 User s Guide Programming Interface 4 4 18 User Specific LED Configuration Register The User Specific LED Configuration Register holds a series of bits defining the onboard configuration for the front panel User Specific LEDs REGISTER NAME User Specific LED
43. pack it as nearly as possible in the manner in which it was delivered Special care is necessary when handling or unpacking the product Please consult the special handling and unpacking instruction on the previous page of this manual CA DT A63 1e Page iv Table Of Contents VX3230 User s Guide Table Of Contents Chapter 1 Introduction 1 1 1 Manual sae Seas deme danas head eae E EUER 3 5 tesi da e 3 14 2 A eer ee 3 TES SCOPE A 3 1 4 A A da 3 1202 A A aaa 4 1 3 Board Overview 4 131 Main Features case re HR Eas 4 1 3 2 Order Code 6 133 NO Interfaces cio dad ddr bs VER DERNIER 7 1 3 4 Ethernet Connectivity 2 2 9 1 4 Board Diagrams bebe ny TERES aaa ed 11 1 4 1 Functional Block Diagram 1 4 11 1 4 2 Front Panel oov en eR a a ERRARE GG RA a Rope RR ee DAR dade 13 1 4 8 VX3230 Components Layout
44. to signal a system error STOP STOP Driven low by a PCI target to signal a disconnect or target abort TRDY Target Ready Driven low by the current target to signal its ability to complete the current data phase V I O Power supply delivered by the board On the PCI 64 PMC slots 3 3 Volts power is supplied 5 Volts signaling PMCs are not supported Contact Kontron for more information Page 1 of 2 CA DT A63 1e Page 49 Functional Description VX3230 User s Guide SIGNAL DESCRIPTION 3 3V 3 3 Volts DC power 5V 5 Volts DC power 12V 12 Volts DC power 12V 12 Volts DC power Page 2 of 2 Table 31 PMC Signal Description Page 50 CA DT A63 1e VX3230 User s Guide Functional Description 2 8 8 J15 Connector Pin Assignment One sites is provided to allow the installation of VITA 42 3 PCI Express mezzanine cards The signals assignments are as shown in the following table The encoding for GA 2 0 should not conflict with other SMbus IPMI devices Row Row Row D Row E 2 MRSTI 4 MRSTO s 6 7 8 12V 11 MBIST 12 GND GND GND GND MPRESENT 13 3 3V AUX 14 GND GND GND GND 15 N C 16 GND GND NVMRO GND GND MSCL o 1 VPWR is connected to 5V via a 0 ohm resistor The 12V option is available please contact Kontron for more information on this topic Signals active when low Table 32 XMC J15 C
45. 10 Not Connected Table 16 USB Onboard Pin Assignment Figure 14 USB Onboard Connector The USB Flash module is fixed to the board by using on one side the CN5 connector and on the other side a standoff screwed to the VX3230 board and to the USB Flash module Order Code for the USB flash disk FDM USB xGB 2MM IV industrial version with conformal coating for use with rugged versions x 4 or 8 GB Contact Kontron for available capacity LIN es CA DT A63 1e Page 35 Functional Description VX3230 User s Guide USB Flash Disk Layout Maximum space reserved for USB flash disk is 36 9 mm x 26 6 mm LxW The distance between connector and screw hole is 27 3 mm 27 9mm Maximum allowable connector height is 3 68 mm 145 3 68 mm High 1 45 36 9 mm M 1 05 26 6 mm 24 6 0 mm 1 18 4 5 mm 1 08 27 5 mm 19 4 9 mm ON gt OFF c gt Figure 15 USB Flash Disk Overview Page 36 CA DT A63 1e VX3230 User s Guide Functional Description 2 8 3 Gigabit Ethernet Interfaces The MPC8544 integrates two triple speed Ethernet controllers which are associated on the VX3230 board with two external Marvell 88E 1112 Ethernet PHY The Ethernet channels and 1 can either be routed to the front panel RJ 45 connectors the VPX P1 connector thanks to the use of a Texas Instrument TS3L301 LAN Switch Refer to section 1 3 4 Ethernet Connectivity
46. 2 bit UARTs 2x UART 16550 style 4 wires System memory 1 GB of DDR2 533 SDRAM 64 bit wide ECC support soldered Secure Boot Support Dual boot storage automatic boot failover safe on the field firmware upgrade Boot Device 32 Mb soldered NOR flash for U Boot redundant boot sector User Flash Up to 16 GB USB NAND flash with USB flash mezzanine card optional 1 serial 256 Kbit EEPROM dedicated to system data 1 serial 256 Kbit EEPROM dedicated to application data NvSRAM 128 kb autostore NvSRAM with hardware autostore Watchdog CPLD connected to the local bus Real Time Clock RV 8564 C2 from Micro Crystal Switzerland Temperature and Voltage LM95231 and 73 temperature sensors connected to the 2 bus Monitoring ADS7830I analog to digital converter for voltage monitoring Gigabit Ethernet PHY Two Marvell 88E1112 transceivers with SerDes and Copper media interfaces USB Controller Dual USB Controller 15 1562 SATA Controller Dual SATA Controller Silicon Image Sil3132 Page 1 of 2 oa7O T O 775 00279 O73 0 CA DT A63 1e Page 15 Introduction VX3230 User s Guide VX3230 SPECIFICATIONS P MPC8544 PCI Express x4 x4 PCI Express links connected to PLX PCI E swtich PEX 8608 MPC8544 PCI Express 4 x4 PCI Express links connected to XMC slot MPC8544 PCI Express 1 x1 PCI Express link connected to SATA Controller PEX 8608 Upstream PCI x4 PCI Express links connected to MPC8544 Express x4 PEX 8608
47. 230 RCA1N 000 VX3230 Rugged Conduction Cooled Build 1GB SDRAM No User Flash slot 10 100 1000BASE TX Ethernet interfaces VX3230 RCA1N 010 VX3230 Rugged Conduction Cooled Build 1GB SDRAM No User Flash XMC PMC slot 1000BASE BX Ethernet interfaces Associated Products PB VX3 000 VX3230 VPX Rear Transition Module with PIM connectors 10 100 1000BASE TX Ethernet interfaces PB VX3 001 VX3230 VPX Rear Transition Module no PIM connector 10 100 1000BASE TX Ethernet interfaces PB VX3 010 VX3230 VPX Rear Transition Module with PIM connectors 1000BASE BX Ethernet interfaces PB VX3 011 VX3230 VPX Rear Transition Module no PIM connector 1000BASE BX Ethernet interfaces FDM USB 4GB 2MM IV 4 GB Flash Device industrial version conformaly coated FDM USB 8GB 2MM IV 8 GB Flash Device industrial version with conformal coating COP PN3 B COP JTAG Equipment KIT RIBPMC1V01 1 Fastening kit for a rugged conduction cooled PMC Table 1 Order Code CA DT A63 1e VX3230 User s Guide Introduction 1 3 3 1 O Interfaces Front Interfaces FUNCTION DESCRIPTION Gigabit Ethernet Depenping on Ethernet interfaces manufacturing option Up to 2 1000BASE T on RJ 45 connectors 1x ElA 232 485 UART interface RJ 11 connector 1x USB 2 0 interface 5 LEDS reporting main interfaces activities Board Reset Button Table 2 Front I O Interfaces PMC XMC slot Manufacturing Option FUNCTION DESCRIPTION PMC XMC
48. 230 can operate under the following operating system gt Linux Please contact Kontron for further information concerning other operating systems and software support Page 18 CA DT A63 1e VX3230 User s Guide Introduction 1 7 Standard This Kontron product complies with the requirements of the following standards TYPE ASPECT DESCRIPTION Emission EN55022 61000 6 3 Immission EN55024 61000 6 2 Electrical Safety 60950 1 Mechanical Dimensions 1 1101 10 Environmental WEEE Waste electrical and electronic equipment RoHS Restriction of the use of certain hazardous substances in electrical and electronic equipment Table 9 Standards 1 7 1 Environmental Specifications ENVIRONMENTAL SPECIFICATIONS 2771 SA Standard Commercial RC Rugged Conduction Cooled Conformal Coating Optional Standard Temperature VITA 47 Class 1 VITA 47 Class CC4 Vibration Sine Operating 29 20 500 Hz 2g 22 2 000 Hz acceleration frequency range acceleration frequency range VITA 47 Class V1 VITA 47 Class V3 Shock Operating 20g 11ms 40g 11ms peak accel shock duration half sine peak accel shock duration half sine Altitude Operating 1 640 to 15 000 ft 1 640 to 50 000 ft Relative Humidity 90 non condensing 95 non condensing Table 10 Environmental Specifications CA DT A63 1e Page 19 Introduction VX3230 User s Guide 1 8 Related Publications The following publications contain infor
49. 2W 3 3V 1 68W 1 95W 1 95W 2 77W Total 15 23W 17 69W 17 95W 19W Table 43 Power Consumption Page 94 CA DT A63 1e VX3230 User s Guide VX3230 RTM Characteristics Chapter 6 VX3230 RTM Characteristics 6 1 Overview The VX3230 provides optional Rear I O connectivity for peripherals a feature which may be particularly useful in specialized CompactPCI systems Some standard PC interfaces are implemented and assigned to the front panel and to the Rear I O connector 2 on the VX3230 When the VX3230 RTM 15 used the signals of some of the main board front panel connectors may be routed to the module interface Thus the VX3230 Rear Transition Module makes it much easier to remove the CPU in the rack as there is practically no cabling on the CPU board For the system Rear feature a special backplane is necessary The CPU board with Rear I O is compatible with all standard CompactPCI passive backplanes with Rear I O support on the system slot The VX3230 RTM provides the following functions gt VPX Rear I O Two USB 2 0 ports Two Gigabit Ethernet ports without LED signals Two COM Serial ports Three SATA ports Two GPIOs One Reset Button One System Management Bus connector V MV MV M One JTAG connector Several manufacturing options are available PIM connectors or no PIM connector gt 10 100 1000BASE TX or 1000BASE BX Ethernet interfaces Available order codes are listed in table below
50. 30 User s Guide Power Considerations 5 1 3 Power Supply Units Power supplies for the VX3230 must be specified with enough reserve for the remaining system consumption In order to guarantee a stable functionality of the system it is recommended to provide more power than the system requires An industrial power supply unit should be able to provide at least twice as much power as the entire system requires An ATX power supply unit should be able to provide at least three times as much power as the entire system requires As the design of the VX3230 has been optimized for minimal power consumption the power supply unit shall be stable even without minimum load Where possible power supplies which support voltage sensing should be used Depending on the system configuration this may require an appropriate backplane The power supply should be sufficient to allow for die resistance variations Non industrial ATX PSUs may require a greater minimum load than a single VX3230 is capable of creating When a PSU of this type is used it will not power up correctly and the VX3230 may hangup The A solution is to use an industrial PSU or to add more load to the system The start up behavior of VPX power supplies is critical for all new CPU boards These boards require a defined power of sequence and start up behavior of the power supply For information on the required behavior refer to the power supply specifications on the formfactors org web
51. 30 and the XMC connector if available Press them together so that the friction from the pins holds them together Insert the standoff plug mounted on the VX3230 into the keyhole The module s bezel will fill the slot and provide a connection to the module As no PMC voltage selection key is provided on the board make sure not to insert a 5V PMC on the board Failture to observe this restriction may result in damage to the PMC or the VX3230 Refer to section 2 9 1 Signaling Voltage Keying Pin page 55 for more information on this topic 5V Key hole 5 Screw the XMC PMC in place using the 4 mounting points on the bottom side of the VX3230 You need a Phillips screwdriver for this stage 6 The XMC PMC attachment is now complete 7 Insert the VX3230 into the chassis making sure it is plugged into the backplane CA DT A63 1e Page 65 Installation VX3230 User s Guide Figure 26 PMC Installation on PMC Site Page 66 CA DT A63 1e VX3230 User s Guide Installation 3 7 4 XMC Installation The XMC board standard is based on the PMC mechanical definition and occupies the same board area The XMC board adds one new connector to the connectors already on a PMC The new connector supports high speed differential signals for fabric communications XMC connector E PPR RRR ERED DDI ene ere Figure 27 Example of XMC Board Figure 28 shows a XMC installation on the PMC XMC Site Figure 28 XMC Installation on XMC Site
52. 3230 User s Guide 4 4 12 Host Reset Status Register REGISTER NAME Host Reset Status ADDRESS 0 000 0285 DESCRIPTION VALUE ACCESS 7 PHRST Power on host reset detection N A R 0 System reset generated by software warm reset 1 System reset generated by power on cold reset 6 5 Res Reserved 00 R 4 SYRST System reset function 0 R W 0 VX3230 is running 1 A reset condition will be generated 3 Res Reserved 0 R 2 VPXRST VPX Controller reset function 0 R W 0 System reset generated by other reset sources 1 System reset generated by the VPX Writing a logical 1 clears the bit 1 MANRST Manual Button reset function 0 R W 0 System reset generated by other reset sources 1 System reset generated by the push button Writing a logical 1 clears the bit 0 HWRST Watchdog timer resets 0 R W 0 System reset generated by other reset source 1 System reset generated by Watchdog timer Writing a logical 1 clears the bit 4 4 13 Host I O Status Register REGISTER NAME Host I O Status ADDRESS 000 0286 RESET BIT NAME DESCRIPTION VALUE 55 7 Factory Mode 0 R 0 Factory mode enabled 1 Factory mode is disabled 6 F LOC Flash Location in Normal Mode 0 R W 0 Lower location 1 Upper location 5 BFC Boot Flash Configuration N A R 0 Boot from Rescue Mode 1 Boot from Normal Mode 4 0 Res Rese
53. 6 kbit onboard serial EEPROMS gt One is used for the CPU boot sequencing and is connected to the CPLD I2C address 0xA8 gt One is used to store the Operating System boot parameters and user data and is connectd to the 2 controller 12C address OxAO 2 3 8 SPI EEPROM A serial EEPROM using the Serial Peripheral Interface SPI is available and contains the PCI Express switch configuration 2 34 128 Volatile Random Access Memory provides fast nin volatile storage of mission state data not to be lost when the power is removed During standard operations software applications read and write in the autostore NOVRAM just like in a standard SRAM Upon detection of a power loss an autostore cycle is performed and all the 128 KB are automatically moved from the onchip SRAM to the onchip EEPROM using the energy stored in an onboard capacity At the next system power up a recall cycle is performed to dump the EEPROM contents back to the SRAM The number of recall cycles is unlimited The maximum of store cycles is 500 000 and the data retention period is 20 years at maximum temperature 85 C 2 3 5 Dual Serial ATA The VX3230 provides two Serial ATA 1 0 1 5 Gbps interfaces based on the Silicon Image Sil3132 component a two port PCI Express to Serial ATA controller The two SATA ports are available on P1 connector Refer to section 2 8 4 2 VPX Connector Description page 40
54. CA DT A63 1e Page 67 Installation VX3230 User s Guide 3 8 Software Installation The installation of all onboard peripheral drivers is described in detail in the relevant Driver Kit files or Board Support Packages BSP Installation of an operating system is a function of the OS software and is not addressed in this manual Refer to appropriate OS software documentation for installation Page 68 CA DT A63 1e VX3230 User s Guide Chapter 4 4 1 Interrupt Routing Programming Interface Programming Interface The MPC8544 controller has twelve dedicated interrupt inputs These inputs are used on the VX3230 board according to the following table Pin Description IRQO Reserved PCle1 INT1 IRQ1 PCI INTCZ PCle1 INTB IRQ2 PCI INTDZ PCle1 INTC IRQ3 PCI INTA PCle1 INTD IRQ4 PCI INTB Z PCle2 INTA IRQ5 Reserved PCle2 INTB IRQ6 Reserved PCle2 INTC IRQ7 Reserved PCle2 INTD IRQ8 Watchdog Timer PCle3 INTA IRQ9 Thermal Alert Timer PCle3 INTB IRQ10 GPIO Interrupt PCle3 INTC IRQ11 Reserved PCle3 INTD Table 37 Interrupt Routing CA DT A63 1e Page 69 Programming Interface 4 2 Memory Mapping VX3230 User s Guide ptio e art Adare CSO NOR Flash 0 8 OxFF80_0000 Unused 120 800 0000 54 NvSRAM 64 0 400 0000 CS3 Onboard Registers 64 MB 0OxF000 0000 Unused 192 0 400 0000 8 1
55. Configuration ADDRESS 0 000 028B RESET NAME DESCRIPTION VALUE 55 7 4 Res Reserved 0000 R 3 0 ULCON User Specific LED Configuration 0001 R W 0000 Reserved 0001 Normal Mode 1 0010 User Mode 2 0011 1111 Reserved Table 40 User Specific LED Configuration Register Regardless of the selected configuration the User Specific LEDs are used to signal some fatal onboard hardware errors such as ULEDO Board or VPX over temperature alarm red ULED1 MPC8544 is stopped in CHECKSTOP state red ULED2 Factory mode is activated red 1 Configured for Normal Mode the User Specific LEDs are dedicated to functions as follows ULEDO PCI activity green ULED1 MPC8641 local bus activity green gt ULED2 LINK SATA activity green For further information on reading the 8 Bit POST Code refer to section 2 3 1 Front Panel LEDs 2 Configured for User Mode the User Specific LEDs are dedicated to functions as follows ULEDO Module LED 0 controlled by user green amber red ULED1 Module LED 1 controlled by user green amber red ULED2 Module LED 2 controlled by user green amber red CA DT A63 1e Page 81 Programming Interface 4 4 19 User Specific LED Control Register VX3230 User s Guide REGISTER NAME User Specific LED Control ADDRESS BIT 7 4 ULCMD 0 000 0280 User Specific LED command 0000 get Mod
56. D N C N C GND P1 w08 CASE GND signal active when low Table 59 Rear I O VPX Connector RPO Wafer Assignment CA DT A63 1e Page 119 VX3230 RTM Characteristics RPO Signal Definition SIGNAL DEFINITION VX3230 User s Guide 12 AUX Auxiliary Power Supplies 3V3 AUX 3 3V Auxiliary Power System Management 5V 5V Power Input GND Ground NVMRO Non Volatile Memory Read Only Not Connected SMB y CLK System Management Bus y 2 Bus Clock SMByDAT System Management Bus y IC Bus Data SYSRESET System Reset TCK JTAG signal Test Clock TDI JTAG signal Test Data Input TDO JTAG signal Test Data Output TMS JTAG signal Test Mode Select TRST JTAG signal Test Reset signal active when low Page 120 Table 60 Rear VPX Connector Signal Definition CA DT A63 1e VX3230 User s Guide VX3230 RTM Characteristics 6 9 PCI 64 PIM Connector 6 9 1 410 Connector J10 Connector Pin Assignment A A A A 01 N C 02 12V AUX 03 N C 04 N C 05 5V 06 N C 07 N C 08 N C 09 N C 10 3 3V 11 N C 12 N C 13 GND 14 N C 15 N C 16 N C 17 N C 18 GND 19 N C 20 N C 21 5V 22 N C 23 N C 24 N C 25 N C 26 3 3V 27 N C 28 N C 29 GND 30 N C 31 N C 32 N C 33 N C 34 GND 35 N C 36 N C 37 5V 38 N C 39 N C 40 N C 41 N C 42 3 3V 43 N C 44 N C
57. E Timer Middle LSB Register ADDRESS 000 0291 DESCRIPTION ACCESS Counter value 4 4 24 Timer LSB Byte Register REGISTER NAME Timer LSB Register ADDRESS 0 000 0292 DESCRIPTION ACCESS Counter value 4 4 25 Logic Sub Reviision Register REGISTER NAME Logic Sub Revision ADDRESS 0 000 0293 B A D RIPTIO A A 7 0 LSR Logic Sub Revision N A R Start Value 0x00 CA DT A63 1e Page 83 Programming Interface VX3230 User s Guide 4 4 26 1 2 Configuration Register REGISTER NAME COM1 2 Configuration ADDRESS OxF000 0294 RESET NAME DESCRIPTION VALUE ACCESS 7 Res Reserved 0 R 6 4 COM2 COM2 Port Function 001 RAW 000 interface is off 001 231 full duplex 010 011 232 half duplex RTS controlled 1 0 send receive In the following s slew rate 1 0 slow fast Also if the port is configured for full duplex mode the receiver is always on 10s 485 full duplex RTS controlled 1 0 trans mitter off on 11s 485 half duplex RTS controlled 1 0 send receive 3 Res Reserved 0 R 2 0 COM1 1 COMI Port Function 001 R W 000 interface is off 001 231 full duplex 010 011 232 half duplex RTS controlled 1 0 send receive In the following s slew rate 1 0 slow fast Also if the port is configured for full duplex mode the receiver is always on 10s 485 full duple
58. G kontron VX3230 VPX SBC User s Guide CA DT A63 1e September 2010 If it s embedded it s Kontron Preface VX3230 User s Guide Revision History Copyright O 2010 Kontron AG All rights reserved All data is for information purposes only and not guaranteed for legal purposes Information has been carefully checked and is believed to be accurate however no responsibility is assumed for inaccuracies Kontron and the Kontron logo and all other trademarks or registered trademarks are the property of their respective owners and are recognized Specifications are subject to change without notice Page CA DT A63 1e VX3230 User s Guide Preface Proprietary Note This document contains information proprietary to Kontron It may not be copied or transmitted by any means disclosed to others or stored in any retrieval system or media without the prior written consent of Kontron or one of its authorized agents The information contained in this document is to the best of our knowledge entirely correct However Kontron cannot accept liability for any inaccuracies or the consequences thereof or for any liability arising from the use or application of any circuit product or example shown in this document Kontron reserves the right to change modify or improve this document or the product described herein as seen fit by Kontron without further notice Trademarks This document may include names company l
59. GND P2 w03 12 GND GND GND P2 w04 13 GND GND P2 w05 14 GND GND GND P2 w06 GND CASE GND Table 56 Rear I O VPX Connector RP1 Wafer Assignment 10 100 1000BASE TX Ethernet Manufacturing Option Page 116 CA DT A63 1e VX3230 User s Guide VX3230 RTM Characteristics gt Legend for Table 57 Gigabit Ethernet port GPIO COM1 Serial port Serial ATA port PMC I O USB port RO RO RO ROW D RO ROW B ROW A 3 1 GND GND P1 w09 2 GND GND GND P1 w10 3 GND GND P1 w11 4 GND GND GND P1 12 5 GND GND P1 w13 6 GND GND GND P1 w14 7 GND GND P1 w15 8 GND GND GND P1 w16 9 GND GND P2 w01 10 GND GND GND P2 w02 11 GND GND P2 w03 12 GND GND GND P2 w04 13 GND GND P2 w05 14 GND GND GND P2 w06 15 GND GND P2 w07 16 GND GND GND P2 w08 CASE GND Table 57 Rear I O VPX Connector RP1 Wafer Assignment 1000BASE BX Ethernet Manufacturing Option CA DT A63 1e Page 117 VX3230 RTM Characteristics VX3230 User s Guide Signal Definition SIGNAL DEFINITION COM1 CTS RXDb Channel EIA 232 x Clear To Send EIA 485 Receive Data pair b COM1 RTS TXDb Channel EIA 232 x Ready To Send EIA 485 Transmit Data pair b COM1 RXD RXDa Channel EIA 232 x Receive Data ElA 485 Receive Data pair a COM1 TXD TXDa Channel ElA 232 x Transmit Data ElA 485 Transmit Data pair a ETHxBI_DA Ethernet First pair of Transmit receive
60. Local temperature accuracy 2 40 C to 150 C gt Operating temperature 40 C 150 C CA DT A63 1e Page 29 Functional Description VX3230 User s Guide Board Sensor 1 Top Processor Sensor Bottom Board Sensor 2 Bottom Figure 9 Location of Board and Processor Sensors Page 30 CA DT A63 1e VX3230 User s Guide 2 6 5 Voltage Sensors Functional Description The ADS78301 at I2C hardware address Ox4b is an Analog to Digital Converter with 12C interface used to measure the internal and external power supplies of the VX3230 board Key features 2 6 6 VPX backplane supports two SMB buses gt SMB 5 0 5 1 with SMO the clock line SM1 the data line SMB two SM2 SM3 with SM2 the clock line and SM3 the data line The SMB one is directly connected to the internal 2 one bus Accuracy Analog Input 0 Analog Input 1 Analog Input 1 Analog Input 3 Analog Input 3 Analog Input 5 Analog Input 6 Analog Input 7 8 bits VCC VDD P3V3 P2V5 P1V8 P1V2 P1VO Not Used Analog Input COM GND External SMB Bus The SMB two is connected to the internal 2 two bus through a buffer which is no activated to allow all the local devices to be disconnected from the backplane Enabling the buffer may cause an 2 address conflict with the local devices if several VX3230 are plugged CA DT A63 1e Page 31 Functional D
61. ON ACK64 BUSMODE1 CLK DEVSEL FRAME EREADY GNT IDSEL INTA to INTD IRDY AD 00 to AD 31 to C BE1 Address Data bits Multiplexed address and data bus Acknowledge 64 bit Transfer Driven low by the device to indicate that the target is willing to transfer data using 64 bits Bus Mode 1 Driven low by a PMC module to indicate that it supports the current bus mode Command Byte Enables During the address phase these signals specify the type of cycle to carry out on the PCI bus During the data phase the signals are byte enables that specify the active bytes on the bus Clock Except RST the 64 bit PCI bus signals are synchronous to 33 or 66 MHz clock Device Select Driven low by a PCI agent to signal that it has decoded its address as the target of the current access FRAME Driven low by the current master to signal the start and duration of an access EREADY Output of non monarch PPMCs that indicates it has completed its onboard initialization and can respond to PCI bus enumeration by the monarch via configuration cycles Input to the monarch PPMC that indicates all non monarch PPMCs have completed their onboard initializa tion and can respond to PCI bus enumeration by the monarch via configuration cycles Grant Driven low by the arbiter to grant PCI bus ownership to a PCI agent GNT is provided for use by dual function PMC modules or processor PMC modules Initialization Devic
62. R E 7 V I O RIEN EE e E 0000 09 ACI 1 V I O is 3 3V only Neither PMC site provides a 3 3V keying pin PCI signals active when low Table 28 PMC J11 Connector Pin Assignment 2 8 6 J12 Connector Pin Assignment Pin Signal Pin Signal Pin Signal Pin Signal _ MEMES BEAT Pulled to 3 3V via 10K BINE E L L se L mre NEC GUN ae wo e pm oem a pe mero EREADY par ss e se foj wc _ wc 1 IDSEL B and GNT B are provided for use by dual function PMC modules or processor PMC modules PCI signals active when low Table 29 PMC J12 Connector Pin Assignment CA DT A63 1e Page 47 Functional Description VX3230 User s Guide 2 8 7 PMC J14 Connector Pin Assignment Pin Signal Pin Signal Pin Signal Pin Signal f nf wow f s wo f f woe weow PMC IO 03 PMC IO 19 PMC IO 35 PMC IO 51 PMC IO 04 20 PMC IO 20 36 PMC IO 36 52 PMC IO 52 8 mee _ 7 meor _ mene PMC IO 09 PMC IO 25 PMC IO 41 PMC IO 57 meos meor meos mos PMC IO 14 PMC IO 30 PMC IO 46 PMC IO 62 Ls meos a meos e meos Table 30 PMC J14 Connector Pin Assignment Page 48 CA DT A63 1e VX3230 User s Guide 2 8 8 Functional Description PMC Signal Description MNEMONIC SIGNAL DESCRIPTI
63. S RC Rugged Conduction Cooled Conformal Coating Storage 45 C to 85 Vibration Sine Operating 29 22 2 000 Hz acceleration frequency range Random VITA 47 Class V3 Shock Operating 40g 11ms peak accel shock duration half sine Altitude Operating 1 640 to 50 000 ft Relative Humidity 95 non condensing Table 63 Environmental Specifications 7 4 MTBF Data Calculations are made according to the standard MIL HDBK217F 2 for following types of environment gt Ground Benign GB gt Air Inhabited Cargo AIC gt Naval Sheltered NS gt Air Rotary Wing ARW VX3230 RCA1N 000 AIC ARW Hours XD Goue Hours 25 C 40 C 40 C 25 C 40 C 55 C GB Hours 582 211 434 888 82 223 106 714 89 796 21 154 Order Code VX3230 RCA1N 000 Table 64 VX3230 RC11N 000 MTBF Data Page 126 CA DT A63 1e VX3230 User s Guide 7 5 Peripheral Connectivity VX3230 RC FUNCTION slot Front Panel Onboard Gigabit Ethernet USBO Wes ET Bm pop o O E um Table 65 Peripheral Connectivity CA DT A63 1e VX3230 RC Characteristics Page 127 VX3230 RC Characteristics VX3230 User s Guide 7 6 XMC PMC Installation Standard Anchorage Points Attach the XMC PMC XMC ETH2 RC for example to the VX3230 RC according to the following steps 1 Check that the standoffs are attached to the XMC PMC Align the s
64. SM Bus 0 bi directional serial data 6 SMB1 DAT SM Bus 1 bi directional serial data 7 3V3_AUX 3 3V auxiliary power supply P 9 o 8 3V3 AUX 3 3V auxiliary power supply 9 N C Not Connected CN20 R SMB1 ALERT 1 System Management Bus 1 Alert signal active when low 1 SMB1 ALERT is not defined in the VPX standard and is connected default to RESBUS SE VPX signal Table 53 Onboard I2C Connector Pin Assignment Figure 45 Onboard JTAG Connector Page 112 CA DT A63 1e VX3230 User s Guide VX3230 RTM Characteristics 6 6 Reset SERIAL USB A As T HOT w 1 RST spe 6 Reset Push Button Figure 46 VX3230 RTM Reset Push Button Reset SW1 Reset Switch The VX3230 RTM generates a system reset signal on the VPX bus at each 5V power on for a duration of 140 ms to 560 ms In addition the front panel reset push button of the VX3230 RTM is used to generate a VPX bus reset with the same minimum duration LEDs The five LEDs are not connected and unused 6 7 Power Consideration Only the 5V main power from the VPX 15 used The 3 3V and 12V VPX main power are not used in order to accomodate 6U VPX backplane Auxiliary VPX voltages 3 3V I2C connector 12V PIM J10 connector are used The 3 3V on the J10 connector is regulated from the 5V input through a 1 5A max linear regulators CA DT A63 1e Page 113 VX3230 RTM Characteristics VX3230 User s Guide 6 8 Rear I O Interfac
65. TS RXDb ElA 232 Clear To Send ElA 485 Receive Data pair b RTS TXDb ElA 232 Ready To Send ElA 485 Transmit Data pair b RXD RXDa ElA 232Receive Data ElA 485 Receive Data pair a TXD TXDa ElA 232 Transmit Data EIA 485 Transmit Data pair a GND Ground Shell Chassis Ground Table 14 Serial Connector Signal Description CA DT A63 1e Page 33 Functional Description VX3230 User s Guide Serial Cable Designation Serial cable is gt RJ 14 6 4 conductor for a simple EIA 232 without handshake support gt RJ 12 6 pin 6 conductor for EIA 232 with handshaking A RJ 12 to DB9 DB25 male or DB9 DB25 female adapter is available from multiple sources such as Kontron Order Code KIT RJ12DB9 Triangle Cable http www trianglecables com db9m rj12 html Pin Connector Signal Pin Connector DB9 RJ 12 1 RTS 1 2 TXD 3 3 RXD 4 4 CTS 6 5 GND 5 2 8 2 USB Interfaces The VX3230 incorporates one PCI to USB bridge NXP Philips ISP1562 that provides up to two USB 2 0 ports One USB port is available on the front panel or on P1 connector and selectable by an hardware configuration MUX gt One USB portis available on P1 connector or on an onboard 2 mm pitch HE10 connector dedicated to low profile USB flash mezzanine card like Intel Zepher card and selectable by an hardware configuration MUX Each port provides a 5V output to power external USB devices such as keyboards Those USB devices are on the PCI bu
66. V3 3V3 2 12V 12V 12V N C 3V3 3V3 3V3 3 5V 5V 5V N C 5V 5V 5V 4 SMB1 CLK SMB1 DAT GND 12V AUX GND SYSRESET NVMRO 5 GAP GA4 GND 3V3 AUX GND SMBO CLK SMBO DAT 6 GA2 GND 12V_AUX GND GA1 7 TCK GND TDO TDI GND TMS TRST 8 GND REF_CLK REF_CLK GND N C RFU N C RFU GND CASE GND signal active when low Table 18 VPX Connector PO Wafer Assignment Page 40 CA DT A63 1e VX3230 User s Guide Functional Description PO Signal Definition SIGNAL DEFINITION 12V 12 Volts DC power 12 AUX 12 Volts auxiliary power 3V3 3 3 Volts DC power 5V 5 Volts DC power to GA4 Geographical Address Inputs 0 4 GAP Geographical Address Parity GND Ground N C Not Connected Not Connected Reserved for Future Use NVMRO Non Volatile Memory Read Only When asserted prevents any non volatile memory from being updated REF_CLK Reference Clock bussed differentail pair It enables the entire system to synchronize to a common clock if desired SMBx System Management Bus x SYSRESET System Reset TCK JTAG signal Test Clock TDI JTAG signal Test Data Input TDO JTAG signal Test Data Output TMS JTAG signal Test Mode Select TRST JTAG signal Test Reset Table 19 VPX Connector PO Signal Definition CA DT A63 1e Page 41 Functional Description P1 Wafer Assignment P1 wafer pin assigment for wa
67. X3230 User s Guide 6 4 2 Front Panel Connectors ETH1 SERIAL USB 2 0 Gigabit Ethernet CN10 R 11 CN12 R CN13 R HOT 1 RS am 9 e Reset Button Reset Button VX3230 RTM PB VX3 000 Figure 33 VX3230 RTM Front Panel Connectors tig LED 1 to LED 5 are not connected Page 100 CA DT A63 1e VX3230 User s Guide VX3230 RTM Characteristics 6 4 3 Onboard Connectors RP2 RP1 RPO 444040440 AS DAI sn 1100161140798 PB VX3 001 1 ETHO ETH1 SERIAL USB 2 0 Gigabit Ethernet CN10 R CN11 R CN12 R CN13 R VX3230 RTM PB VX3 001 Figure 34 VX3230 RTM Onboard Connectors PB VX3 001 CA DT A63 1e Page 101 VX3230 RTM Characteristics VX3230 User s Guide RP2 RP1 RPO 2 CN20 R GPR TAG one CNSR 39 99009 00000 P 9 VX3230 RTM PB VX3 000 o SATA3 CN16 R Figure 35 VX3230 RTM Onboard Connectors PB VX3 000 Page 102 CA DT A63 1e VX3230 User s Guide VX3230 RTM Characteristics CN10 R CN19 R See section 6 5 1 COM Interfaces page 104 CN11 R CN21 R See section 6 5 2 USB Interfaces page 105 CN12 R CN13 R See section 6 5 3 Gigabit Ethernet Interfaces page 108 CN14 R CN15 R CN16 R See section 6 5 4 Serial ATA Interfaces page 109 CN17 R See section 6 5 5 GPIO Connector page 110 CN18 R See section 6 5 6 JTAG Connector page 111 CN20 R See section 6 5
68. amming Interface 4 4 31 VPXPCle Switch Register REGISTER NAME ADDRESS 000 0298 RESET NAME DESCRIPTION VALUE 55 7 5 Res Reserved 0 R 4 FREQ Maximum Link Speed 0 R W 0 2 5 5 1 5GT s 3 UPSTRM Transparent Upstream Port Selection 1 R 0 Port 1 1 Port 9 2 1 CFG 1 0 Port Configuration 01 R W 00 Reserved 01 x4 x1 x1 x1 x1 10 x4 x4 11 Reserved 0 SSC VPX PCle Switch Dual Clocking Operation 1o R W 0 Enable 1 Disable 2 CLK_SEL must be set to input whn asserting the dual clock mode UPSTRM 0 when CFG 1 0 10 UPSTRM 1 when CFG 1 0 01 LIN N CA DT A63 1e Page 87 Programming Interface VX3230 User s Guide 4 4 32 Open VPX Register REGISTER NAME Open VPX Register ADDRESS 0 000 0298 RESET BIT DESCRIPTION VALUE 55 7 P1G1 VPX P1G1 Connector VPX P1 pin G1 Status in input 1 R W mode VPX P1G1 Connector VPX P1 pin G1 Command in output mode 6 1615 5 VPX P1G1 Connector VPX P1 pin G1 sensitivity 0 R W 0 IRQ is activated on a falling edge in edge mode or on level 0 in level mode 1 IRQ is activated on a rising edge in edge mode or on level 1 in level mode 5 P1G1MODE VPX 161 Connector VPX P1 pin G1 interrupt mode 0 R W activation 0 P1G1 IRQ is in edge mode 1 P1G1 IRQ is in level mode 4 P1G1IRQ VPX P1G1 Connector VPX P1 pin G1 interruption 0 R W activation 0 P1G1 IRQ i
69. ata risk of personal injury ESD This banner indicates Electrostatic Sensitive Device All numbers are expressed in decimal except addresses and memory or register data which are expressed in hexadecimal The prefix shows a hexadecimal number following the C programming language convention The multipliers and have their conventional scientific and engineering meanings of 103 106 and 109 respectively The only exception to this is in the description of the size of memory areas when and G mean 210 220 and 230 respectively When describing transfer rates and G mean 103 106 and 109 not 270 220 and 230 UN N In PowerPC terminology multiple bit fields are numbered from 0 to n where 0 is the MSB and n is the LSB PCI and terminology follows the more familiar convention that bit O is the LSB and n is the MSB Signal names ending with an asterisk or a hash denote active low signals all other signals are active high Signal names follow the PICMG 2 0 R3 0 CompactPCI Specification and the Local Bus 2 3 Specification For Your Safety Your new Kontron product was developed and tested carefully to provide all features necessary to ensure its compliance with electrical safety requirements It was also designed for a long fault free life However the life expectancy of your product can be drastically reduced by improper tre
70. atment during unpacking and installation Therefore in the interest of your own safety and of the correct operation of your new Kontron product you are requested to conform with the following guidelines High Voltage Safety Instructions Warning All operations on this device must be carried out by sufficiently skilled personnel only Caution Electric Shock Before installing a not hot swappable Kontron product into a system always ensure that your mains power is switched off This applies also to the installation of piggybacks Serious electrical shock hazards can exist during all installation repair and maintenance operations with this product Therefore always unplug the power cable and any other cables which provide external voltages before performing work Page iii CA DT A63 1e VX3230 User s Guide Preface Special Handling and Unpacking Instructions ESD Sensitive Device Electronic boards and their components are sensitive to static electricity Therefore care must be taken during all handling operations and inspections of this product in order to ensure product integrity at all times Do nat handle this product out of its protective enclosure while it is not used for operational purposes unless it is otherwise protected Whenever possible unpack or pack this product only at EOS ESD safe work stations Where a safe work station is not guaranteed it is important for the user to be electrically discharged before touching th
71. board is engaged 4 Fasten the front panel retaining screws 5 Connect all external interfacing cables to the board as required 6 Ensure that the board and all required interfacing cables are properly secured The VX3230 is now ready for operation For operation of the VX3230 refer to appropriate VX3230 specific software application and system documentation CA DT A63 1e Page 61 Installation VX3230 User s Guide 3 6 Standard Removal Procedure To remove the board proceed as follows 1 Ensure that the safety requirements indicated in Chapter 3 1 are observed Particular attention must be paid to the warning regarding the heat sink Care must be taken when applying the procedures below to ensure that neither the VX3230 nor system boards are physically damaged by the application of these procedures Ensure that no power is applied to the system before proceeding Disconnect any interfacing cables that may be connected to the board Unscrew the front panel retaining screws a A OQ N Disengage the board from the backplane by first unlocking the board ejection handles and then by pressing the handles as required until the board is disengaged 6 After disengaging the board from the backplane pull the board out of the slot Due care should be exercised when handling the board due to the fact that the heat sink can get very hot Do not touch the heat sink when changing the board 7 Dispose of the board as required
72. ce JTAG Data In Power pins These signals carry either 12V or 5V power from the carrier to the XMC Table 33 XMC Signal Description Page 52 CA DT A63 1e VX3230 User s Guide 2 8 11 COP Header Pin Signal Pin Signal 9 Pros so PPC_TDI SRESET 4 TRSTb 12 N C e meer e 96 Signals active when low Table 34 COP Header Pin Assignment 2 8 12 JTAG Connector Functional Description 2 4 6 8 10 12 14 16 1 3 5 7 9 11 13 15 Figure 19 COP Header The CPLD is programmed via the JTAG CN3 connector The CPLD is the only device on the JTAG chain Pin Signal Pin Signal Signals active when low Table 35 JTAG Connector Pin Assignment CA DT A63 1e 9 E CN3 Figure 20 JTAG Connector Page 53 Functional Description VX3230 User s Guide 29 XMC PMC Site The VX3230 provides one XMC PMC site gt The PCI 32 XMC PMC site 32 bit wide operates at 33 MHz Kontron products include standard XMCs PMCs such as Graphics XMC XMC G72 Ethernet XMC XMC ETH2 Refer to the Release Notes associated with your operating system for more information about the supported PMC XMCs For EMC protection reasons when not used the PMC slots are fitted with a blanking plate kept in its protective antistatic packaging until it is ready to be installed During installation make sure to Electrostatic Discharge ESD can damage components
73. ce 4 4 8 CPLD Interrupt Register REGISTER NAME CPLD Interrupt ADDRESS 0xF000_0281 RESET BIT DESCRIPTION VALUE 55 7 TIM Timer interrupt 0 R W 1 Timer interrupt is occured 0 No interrupt occurs Writing 1 to this bit clears the bit 6 TEMP_LED Temperature Alert indicator 0 R W 1 Temperature Alert indicator is on 0 Temperature Alert indicator is off Writing 1 to this bit clears the bit 5 SMB SMB_ALERT interrupt 1 R 1 No interrupt occurs 0 SMB ALERT is activated Writing to this bit clears the bit 4 TEMP ALERT interrupt 1 R 1 No interrupt occurs 0 TEMP ALERT is activated Writing to this bit clears the bit 3 GPIO3 GPIO3 interrupt 0 RAW 1 Interrupt occurs on GPIO1 signal 0 No interrupt occurs Writing 1 to this bit clears the bit 2 GPIO2 GPIC2 interrupt 0 R W 1 Interrupt occurs on GPIO1 signal 0 No interrupt occurs Writing 1 to this bit clears the bit 1 GPIO1 IRQ GPIO1 interrupt 0 R W 1 Interrupt occurs on GPIO1 signal 0 No interrupt occurs Writing 1 to this bit clears the bit 0 GPIOO IRQ GPIOO interrupt 0 RAW 1 Interrupt occurs on GPIOO signal 0 No interrupt occurs Writing 1 to this bit clears the bit uu GPIOx interrupt causes a rising edge or a high level on IRQ10 signal 4 A thermal interrupt SMB ALERT or TEMP ALERT causes a rising edge or a high level
74. ctor configuration comprises three connectors named P1 and 2 gt PO one 8 7 row connector gt P1 one 16 wafer 7 row connector gt 2 16 wafer 7 row connector The VX3230 is not hot swappable but supports the addition or removal of other boards whilst in a powered up state The VX3230 is designed for a VPX bus architecture Figure 17 VPX Connectors 2 8 4 1 Board Connectors Identification Alignment Keying Sockets di HHE 1 n RII P2 Alignment Keying Pins Figure 18 Connector Identification for 3U VPX Board CA DT A63 1e Page 39 Functional Description 2 8 4 2 Connectors Description The VX3230 is provided with three VPX bus connectors PO P1 and P2 The VX3230 board provides Rear I O connectivity for special compact systems VX3230 User s Guide When the Rear I O module is used the signals may be routed to the Rear I O module interface Thus the Rear module makes it much easier to remove the CPU in the rack as there is practically no cabling on the CPU board The VX3230 Rear provides the following interfaces Two USB 2 0 ports P1 Two Gigabit Ethernet ports without LED signals P1 Two SATA ports P1 Two GPIOs P1 gt x4 or 4x1 PCI Express P1 gt Two EIA 232 COM ports P2 PO Wafer Assignment Wafer ROW G ROW F ROW E ROW D ROW C ROW B ROW A 1 12V 12V 12V N C 3V3 3
75. ctors with magnetics and LEDs Backplane copper goes to P1 complying with VITA 46 9 standard through onboard magnetics The configuration front panel or backplane for each port or ETH1 is set up via the Host I O Configuration register see section 4 4 14 page 79 gt and LAN Switch 1 ETHO or ETH1 10 100 1000BASE TX on front panel 10 100 1000BASE TX on backplane gt 1000BASE BX Ethernet interfaces The PHY Marvell 88E1112 transceiver can also be used in 1000 BASE BX serdes mode to comply with the Open VPX specification In this mode The 10 100 1000BASE TX copper interface not available anymore on 1 backplane and ETH1 1000BASE BX serdes interfaces are routed to P1 backplane instead of ETHO copper interface The PHY has a patented feature to automatically detect and switch between 1000BASE BX serdes and 1000BASE T copper cable detection It can also be forced to 1000BASE T copper mode via the Open VPX register see section 4 4 32 page 88 Thereof several configurations are available depending on the LAN Switch and PHY configurations ETHO LAN Switch 1 Interface Mode 2 ETHO Auto Selection 10 100 1000BASE TX on front panel or 1000BASE BX on backplane Force 1000BASE T 1000BASE BX on backplane Auto Selection 1000BASE BX on backplane CA DT A63 1e Page 9 Introduction ETH1 LAN Switch 1 Interface Mode 2 Force 1000BASE T
76. data ETHxBI_DB Ethernet x Second pair of Transmit receive data ETHx BI_DC Ethernet x Third pair of Transmit receive data ETHx BI_DD Ethernet Fourth pair of Transmit receive data ETHx RX 1000BASE BX Ethernet x Receive data ETHx TX 1000BASE BX Ethernet x Transmit data GND Ground GPIO x General Purpose x PMCIO 01 32 SATAx RX Serial ATA x Receive SATAx TX Serial ATA x Transmit USBx DA Differential Data Pair of USB Line x USBx PWR USB Line x Table 58 Rear I O VPX Connector RP1 Signal Definition Page 118 CA DT A63 1e VX3230 User s Guide VX3230 RTM Characteristics 6 8 3 RPO Connector gt gt RPO Wafer Assignment ee ROW G ROW F ROW E ROW D ROW C ROW B ROWA seta 2 N C N C N C N C N C N C N C P0 w02 3 5V 5V 5V 5V 5V 5V 5V PO w03 4 SMB1 CLK SMB1 DAT GND 12V_AUX GND SYSRESET NVMRO PO w04 5 N C N C GND 3V3_AUX GND SMBO CLK SMBO DAT PO w05 6 N C N C GND 12V_AUX GND N C N C PO w06 7 TCK GND TDO TDI GND TMS TRST PO w07 8 GND N C N C GND N C N C GND PO w08 9 RESBUS_SE GND N C N C GND N C N C P1 w01 10 GND N C N C GND N C N C GND P1 w02 11 N C GND N C N C GND N C N C P1 w03 12 GND N C N C GND N C N C GND P1 w04 13 N C GND N C N C GND N C N C P1 w05 14 GND N C N C GND N C N C GND P1 w06 15 N C GND N C N C GND N C N C P1 w07 16 GND N C N C GN
77. e 34 COP Header Pin Assignment 53 Table 35 JTAG Connector Pin Assignment 53 Table 36 PCI 32 XMC PMC Site 54 Table 37 Interrupt Routing oet dd ERR RE PERRA NR 69 Page xi CA DT A63 1e VX3230 User s Guide Table Of Contents Table 38 Memory Mapping 70 Table 39 CPLD System Registers 71 Table 40 User Specific LED Configuration 81 Table 41 DC Operational Input Voltage Ranges 90 Table 42 Input Voltage Characteristics 92 Table 43 Power Consumption 1 94 Table 45 Order Gode di Ae ee Bee oodles 95 Table 46 VX3230 RTM Main Specifications 97 Table 47 Serial Port Connector Pin 104 Table 48 Front Panel USB Connector Pin Assignment 105 Table 49 Onboard USB Connector Pin 1 106 Tab
78. e Select Device chip select during configuration cycles IDSEL B is provided for use by dual function PMC modules or processor PMC modules Interrupt lines Level sensitive active low interrupt requests Initiator Ready Driven low by the initiator to signal its ability to complete the current data phase LOCK LOCK Driven low to indicate an atomic operation that may require multiple transactions to complete M66EN 66 MHZ Enable Indicates to a device if the bus segment is operating at 66 or 33 MHz If it is high then the bus speed is 66 MHz and if it is low then the bus speed is 33 MHz N C This pin is not connected PAR Parity Parity protection bit for ADO to AD31 and C BEO to C BE3 PERR Parity Error Driven low by a PCI agent to signal a parity error PMC IO 01 to 64 bit PCI bus PMC 64 signals Used to transmit I O signals from PCI 64 PMC connector J14 to P2 PMC IO 64 connector PMC RSVD Reserved Do not connect this pin REQ Request Driven low by a PCI agent to request ownership of the PCI bus REQ B is provided for use by dual function PMC modules or processor PMC modules REQ64 sey 64 bit Transfer Driven low by the current bus master indicates that it desires to transfer data using its RST Reset Driven low to reset the PCI bus SBO Snoop Backoff Indicates a hit of a modified line asserted SDONE Snoop Done Indicates the status of the snoop for the current access SERR System Error Driven low by a PCI agent
79. e product with his her hands or tools This is most easily done by touching a metal part of your system housing It is particularly important to observe standard anti static precautions when changing piggybacks ROM devices jumper settings etc If the product contains batteries for RTC or memory backup ensure that the board is not placed on conductive surfaces including anti static plastics or sponges They can cause short circuits and damage the batteries or conductive circuits on the board General Instructions on Usage In order to maintain Kontron s product warranty this product must not be altered or modified in any way Changes or modifications to the device which are not explicitly approved by Kontron and described in this manual or received from Kontron s Technical Support as a special handling instruction will void your warranty This device should only be installed in or connected to systems that fulfill all necessary technical and specific environmental requirements This applies also to the operational temperature range of the specific board version which must not be exceeded If batteries are present their temperature restrictions must be taken into account In performing all necessary installation and application operations please follow only the instructions supplied by the present manual Keep all the original packaging material for future storage or warranty shipments If itis necessary to store or ship the board please re
80. enhanced three speed Ethernet controllers eTSECs OCeaN Switch Fabric Integrated DMA controller PCI controller PCI Express interfaces Power Management System performance monitor System access port IEEE 1149 1 compliant JTAG boundary scan V V V V V V V V V V V NV V CA DT A63 1e Page 23 Functional Description VX3230 User s Guide DDR DDR2 Memory Controller DDR SDRAM Flash GPIO Local Bus Controller e500 IRQs Programmable Interrupt Coherency Controller PIC Module Core Complex Instruction Bus Cache Serial DUART 2 IC c Controller PCI Express dual x4 and 2c Interfaces single x1 Controller OceaN Switch GMII TBI eTSEC RGMI lt gt E 3 Fabric PCI 32 bit RMII SGMII 32 bit PCI Bus Interface 66 MHz MII GMII TBI eTSEC Ea RGMII 4 Channel DMA Ext 10 100 1Gb ernal Figure 8 MPC8544 Block Diagram 2 1 2 System Memory The VX3230 supports a single channel 72 bit registered Doble Data Rate DDR2 memory with Error Checking and Correcting ECC gt The DDR2 interface operates at a rate up to 266 MHz resulting in a peak bandwidth of 4 2 GB s gt The available memory configuration is 1 GB gt ECC is able to correct single bit errors and detect multiple bit errors Page 24 CA DT A63 1e VX3230 User s Guide Functional Description 2 2 PCI Express Buses 2 2 1 MPC8544 PCI Express Links The MPC8544 provides three flexible high speed int
81. erfaces fully complaint with PCI Express standard gt Two 4 links gt One x1 link PCI Express bus interface operates at 2 5 Gbps on each lane resulting in a peak bandwith of 250 MB s per lane 250 MS s on RX way and 250 MB S on TX way As an example the bandwidth of a x4 PCI Express link is 1 GB s 4 x 250 MB s per way The first MPC8544 x4 PCI Express link is routed to P1 connector through a PCI Express Switch PEX8608 The second MPC8544 x4 PCI Express link is connected to the XMC connector The first MPC8544 x1 PCI Express link is connected to the dual SATA bridge Sil3132 2 2 2 Internal PCI Express Links The 8608 is height lanes 8 ports PLX PCI Express switch Port Number Link Width Max Link Rate Connected to up down 0 upstream x4 1GB 1GB MPC8544 PCi Express 1 1 x1 250 MB 250 MB P1 VPX connector port 4 5 x1 250 MB 250 MB P1 VPX connector port 3 7 x1 250 MB 250 MB P1 VPX connector port 2 9 x1 250 MB 250 MB P1 VPX connector port 1 Table 12 Ports Configuration of the PCI Express Switch CA DT A63 1e Page 25 Functional Description VX3230 User s Guide 2 3 Storage 2 3 1 Flash Memory The VX3230 provides one 4 MB flash device This flash device NOR flash is organized in two partitions of 2 MB which operate as redundant boot devices The selection of the active boot flash partitions is controlled by a DIP switch 2 3 2 Serial EEPROMs There are two 25
82. ers significant bandwidth and performance Soldered DDR2 Memories with the Support of ECC The MPC8544 provides DDR2 memory controller operating at a rate up to 266 MHz with 72 bit wide DDR2 SRAM configured with 8 bits for Error Correcting Code ECC The resulting peak memory bandwidth is 4 2 GB s Page 4 CA DT A63 1e VX3230 User s Guide Introduction Numerous Storage Interface 128 kb of Auto store Non volatile Random Access Memory alllows backup of critical dta when power is removed Dual redundant 32 Mb NOR Flash is used to store firmware code and two serial 256 Kbit EEPROMs are dedicated to system and application data storage An USB 2 0 Flash drive slot is availble onboard supporting low profile USB 2 0 Flash disk modules up to 4 GB Two SATA Il and one USB 2 0 ports available on the P1 backplaen connector Backplane Switch Available on P1 connector gt Two compliant VITA 31 1 Gigabit Ethernet links One 4x PCI Express link Extensive I O Connectivity The VX3230 provides up to two 10 100 1000BASE TX or 1000BASE BX Ethernet interfaces two ElA 232 ElA 485 serial lines two general purpose I Os three USB 2 0 links two SATA interfaces and one 4x PCI Express link Software The VX3230 is delivered with the OpenSource U Boot firmware The VX3230 supports Linux Fedora 9 distribution Contact Kontron for other Operating Systems support Harsh Environments The VX3230 has been designed using the sa
83. es The VX3230 Rear Transition Module conducts a wide range of I O signals through the Rear I O connectors RPO RP1 and RP2 gt RPO one 15 wafer 7 row connector gt RP1 one 16 wafer 7 row connector gt RP2 one 8 wafer 7 row connector in non system slot Rear I O backplane Failure to comply with the above may result in damage to your board AN To support the Rear I O feature a special backplane is necessary Do not plug a Rear I O configured board RPO 2 Figure 47 Rear VPX Connectors The VX3230 RTM provides the following interfaces Two USB 2 0 ports USB1 and USB2 via RP1 connector Two Gigabit Ethernet ports without LED signals ETHO and ETH1 via RP1 connector Three SATA ports SATAO SATA1 and SATA2 via RP1 connector Two GPIOs GPIO1 and GPIO2 via RP1 connector Two ElA 232 ElA 485 COM ports COM1 via RP1 connector COM2 via RP2 connector V V MV MV Page 114 CA DT A63 1e VX3230 User s Guide 6 8 1 RP2 Connector RP2 Wafer Assignment VX3230 RTM Characteristics i ROW ROW ROW E ROW D ROW ROW B ROW A Poan Wafer Wafer 1 COM2 GND PMCIO 33 PMCIO 35 GND PMCIO 34 PMCIO 36 P2 w09 RTS TXDb 2 GND PMCIO 37 PMCIO 39 GND PMCIO 38 PMCIO 40 GND P2 w10 3 COM2 GND PMCIO 41 PMCIO 43 GND PMCIO 42 PMCIO 44 P2 w11 TXD TXDa 4 GND PMCIO 45 PMCIO 47 GND PMCIO 46 PMCIO 48 GND P2 w12 5 COM2 GND PMCIO 49 PMCIO 51 GND PMCIO 50 PMCIO 52 P2 w13 CTS RXDb
84. escription VX3230 User s Guide 2 7 VX3230 Connectors Layout P2 P1 PO Figure 10 VX3230 Connectors Layout top Serial Gigabit Ethernet 1 USB ETHO ETH1 Figure 11 Front Panel Connectors Layout Page 32 CA DT A63 1e VX3230 User s Guide Functional Description 2 8 Board Interfaces 2 8 1 Serial Interfaces The VX3230 integrates two 16550 style serial communications ports SO and S1 SO and S1 are also called COM1 and COM2 in PC parlance COM1 and are available via the VPX P2 connector COMI is also available via the front panel connector gt COM1 232 485 simplified RX TX port on RJ 11 front panel connector on the rear P2 connector gt COM2 232 485 simplified RX TX port on the rear P2 connector Each serial port is configurable via the CPLD as EIA 232 or EIA 485 Each port operates in full or half duplex mode Slow slew rate is also CPLD programmable in EIA 485 mode The signaling level of EIA 485 is compatible with EIA 422 so full duplex EIA 485 may also be used for point to point communications with an EIA 422 serial port Refer to section 2 8 3 VPX Bus Interface page 37 for more information on the serial lines wafer assignment on P2 connector Serial Front Panel 1 RTS TXDb 2 Shell Pin 1 Pin 6 3 TXD TXDa sd 4 RXD RXDa 5 GND CTS RXDb Table 13 Serial Connector Pin Assignment Figure 12 Serial Connector DESCRIPTION C
85. eset 25 System FPGA The following functions are implemented in the CPLD device CPU reset configuration Power supply monitoring and board reset control Board registers LED control port Watchdog timer Delay timer Serial hardware debug port V V V MV V V VM V 12C master interface CA DT A63 1e Page 27 Functional Description VX3230 User s Guide 26 12 Buses 2 6 1 Internal I2C Slaves The 2 buses controller allows interfacing to a wide number of 2 wire serial standards based on the original 2 concepts The controller has two multi master I2C buses Master and Slave The master interface is used to drive commands on to the 2 and get responses from other devices The slave section monitors the 2 and will accept commands that are addressed to it The slave section can also be put in a monitoring mode where it will report all activity on the bus but not respond 12C BUS NAME FUNCTION 2 one VPX SMB 1 Switch 12C two RTC EEPROM Thermal Sensor Voltage Sensor 2 6 2 The VX3230 is based on ther RV 8564 C2 CMOS real time clock calendar optimized for low power consumption 40 85 This provides a programmable clock output interrupt output and voltage low detector An internal timer 5 also available All address data are transferred serially via the 12C bus at a maximal spped of 400 Kbit s The built in word address register is incremented auto
86. fault POST code output low byte 0 00 R W Firmware Post Code register high REGISTER NAME POST CODE low ADDRESS 000 0081 DESCRIPTION ACCESS Default POST code output high byte 4 4 2 Debug POST Code Register Debug Post Code register low REGISTER NAME DEBUG POST CODE low ADDRESS 000 0084 A D RIPTIO 2 A A 7 0 PST Debug POST code output low byte 0x00 R W Debug Post Code register high REGISTER NAME DEBUG POST CODE low ADDRESS 0 000 0085 DESCRIPTION ACCESS Debug POST code output high byte Page 72 CA DT A63 1e VX3230 User s Guide Programming Interface 4 4 3 Memory Configuration Register This register is used to inform the formware about the characteristics of the memory on the VX3230 board REGISTER NAME Memory Configuration ADDRESS OxF000 0002 RESET NAME DESCRIPTION VALUE 55 7 Res Reserved 0 R 6 5 MEM_SP DDR2 memory speed N A R 00 DDR2 333 MHz CPU 667 MHz 01 DDR2 400 MHz CPU 800 MHz 10 DDR2 533 MHz CPU 1067 MHz 11 DDR2 400 MHz CPU 1000 MHz 4 ECC Error Checking and Correcting N A R 0 ECC not enabled 1 ECC enabled 3 Res Reserved 0 R 2 1 MEM_SZ Memory size N A R 00 reserved 01 reserved 10 Chip size 1 Gb 11 Chip size 2 Gb 0 MEM_BK Memory bank N A R 0 one physical Bank is equipped 1 two physical banks are populated
87. ference Clock Reserved Reserved SATA x RX Serial ATA xReceive SATAx TX Serial ATA x Transmit SMB ALERT System management Bus Alert SYS CON System Controller USBx DA Differential Data Pair of USB Line x USBx PWR USB Line x Power VBAT Battery Voltage Page 44 Table 22 VPX Connector P1 Signal Definition CA DT A63 1e VX3230 User s Guide Functional Description gt USB Interfaces There are up to two independent USB interfaces available as described below USB PORT CONNECTOR USAGE USBO USB on the VX3230 front panel External USB devices or CN11 R on the VX3230 RTM front panel USB1 CN5 on the VX3230 onboard USB Flash or CN21 R on the VX3230 RTM onboard Table 23 USB Port Features All USB ports may be used at the same time It is strongly recommended to use cables less than 3 metres UN in length for the Rear I O interfaces N gt Ethernet Interfaces Gigabit Ethernet signals are available on the Rear I O interface and ETH1 in above Table ETHO ETHO on the VX3230 front panel or CN12 R on the VX3230 RTM front panel ETH1 1 on the VX3230 front panel or CN13 R on the VX3230 RTM Table 24 Ethernet Port Features gt SATA Interface The VX3230 provides two SATA interfaces SATAO and SATA1 in above Table The two SATA ports SATAO SATA1 can be used only on the Rear interface All SATA ports can be used sim
88. fers 13 up to 16 depends on the Ethernet manufacturing option Refer to Table 20 and Table 21 below 10 100 1000BASE TX Ethernet Manufacturing Option gt Legend for Table 20 VX3230 User s Guide Gigabit Ethernet port GPIO 4 or 4x1 PCI Express Serial ATA port 4 or 4x1 PCI Express USB port Wafer ROW G ROW F ROWE ROW D ROW C ROW B ROWA 1 SMB ALERT GND PEX TXLO PEX TXLO GND PEX RXLO PEX RXLO 2 GND PEX TXL1 PEX TXL1 GND PEX RXL1 PEX RXL1 GND 3 VBAT GND PEX TXL2 PEX TXL2 GND PEX RXL2 PEX RXL2 4 GND PEX TXL3 PEX TXL3 GND PEX RXL3 PEX RXL3 GND 5 SYS_CON GND Reserved Reserved GND Reserved Reserved 6 GND Reserved Reserved GND Reserved Reserved GND 7 REFCLKO SE GND Reserved Reserved GND Reserved Reserved 8 GND Reserved Reserved GND Reserved Reserved GND 9 16 CASE GND GND GND Reserved signal active when low Table 20 VPX Connector P1 Wafer Assignment 10 100 1000BASE6TX Ethernet Manufacturing Option Page 42 CA DT A63 1e VX3230 User s Guide 1000BASE BX Ethernet Manufacturing Option gt Legend for Table 21 Functional Description Gigabit Ethernet port GPIO 4 or 4x1 PCI Express Serial ATA port 4 or 4x1 PCI Express USB port afe RO RO RO ROW D RO ROW B ROW A 1 SMB ALERT GND PEX TXLO PEX TXLO GND PEX RXLO PEX RXLO 2 GND PEX TXL1 PEX TXL1 GND PEX RXL1 PEX RXL1
89. fications page 97 16 CA DT A63 1e VX3230 User s Guide Introduction 1 5 1 MTBF Data Calculations are made according to the standard MIL HDBK217F 2 for following types of environment gt Ground Benign GB gt Air Inhabited Cargo AIC gt Naval Sheltered NS gt Air Rotary Wing ARW VX3230 SAA1N 000 AIC ARW Hours ME Hours 40 40 40 55 C On 307179 230620 41416 55116 47092 11151 Order Code VX3230 SAA1N 000 Table 7 VX3230 SAA1N 000 MTBF Data GB Hours VX3230 RCA1N 000 AIC ARW Hours XS Hours 40 C 40 C 40 C 55 C GB Hours 582211 434 888 82 223 106 714 89 796 21 154 Order Code VX3230 RCA1N 000 Table 8 VX3230 RC1N 000 MTBF Data CA DT A63 1e Page 17 Introduction VX3230 User s Guide 1 6 Software Support Kontron is one of the few VME and VPX vendors providing inhouse support for most of the industry proven real time operating systems that are currently available Due to its close relationship with the software manufacturers Kontron is able to produce and support BSPs and drivers for the latest operating system revisions thereby taking advantage of the changes in technology Finally customers possessing a maintenance agreement with Kontron can be guaranteed hotline software support and are supplied with regular software updates A dedicated web site is also provided for online updates and release downloads The VX3
90. iguration 0 000 0287 section 4 4 14 Board ID 000 0288 section 4 4 15 GPIO Status Command 000 0289 section 4 4 16 GPIO Control 0 000 028A section 4 4 17 User Specific LED Configuration 0 000 028 section 4 4 18 0 000 028 User Specific LED Control 0 000 0280 section 4 4 19 OxF000 028 section 4 4 20 Timer MSB Byte 0 000 028F section 4 4 21 Timer Byte 0 000 0290 section 4 4 22 Timer MLB Byte 0 000 0291 section 4 4 23 Timer LSB Byte 000 0292 section 4 4 24 Logic Sub Revision 000 0293 section 4 4 25 COM1 2 Configuration 0 000 0294 section 4 4 26 VPX 0 000 0295 section 4 4 27 VPX Reset 0 000 0296 section 4 4 28 Geographical Addressing 0 000 0297 section 4 4 29 VPX Common Clock 000 0298 section 4 4 30 VPX PCle Switch 000 0299 section 4 4 31 Open VPX OxF000_029A section 4 4 32 GPIO4 0 000 029 section 4 4 33 Table 39 CPLD System Registers Mapping CA DT A63 1e Page 71 Programming Interface VX3230 User s Guide 44 CPLD System Registers Description 4 4 1 Firmware POST Code Register Firmware Post Code register low REGISTER NAME POST CODE low ADDRESS 0 000 0080 A D RIPTIO 5 A 7 0 PST De
91. le 50 Gigabit Ethernet Connectors Pin 108 Table 51 Onboard SATA Connectors Pin 109 Table 52 Onboard GPIO Connector Pin 110 Table 53 Onboard JTAG Connector Pin 111 Table 54 Onboard 2 Connector Pin 112 Table 55 Rear I O VPX Connector RP2 Wafer Assignment 115 Table 56 Rear I O VPX Connector RP2 Signal Definition 115 Table 57 k Connector RP1 Wafer Assignment 10 100 1000BASE TX Ethernet eor Table 58 Rear I O VPX Connector RP1 Wafer Assignment 1000BASE BX Ethernet Manufacturing Option 117 Table 59 Rear I O VPX Connector RP1 Signal Definition 118 Table 60 Rear I O VPX Connector RPO Wafer Assignment 119 Table 61 Rear I O VPX Connector RPO Signal Definition 120 Table 62 VX3230 RC Order 123 Table 63 VX3230 RC 124 Table 64 Environmental Specifications
92. lot Manufacturing Option 7 Table 4 Rear I O Interfaces 7 Table 5 Peripheral Connectivity 8 Table 6 VX3230 Main Specifications 16 Table 7 VX3230 SAA1N 000 MTBF Data 2 17 Table 8 VX3230 RC1N 000 MTBF Data 17 Table 9 Standards snide donde iud EC SNP 3 19 Table 10 Environmental Specifications 19 Table 11 Related Publications 1 1 222 20 Table 12 Ports Configuration of the PCI Express Switch 25 Table 13 Serial Connector Pin Assignment 1 33 Table 14 Serial Connector Signal Description 33 Table 15 USB Connector Pin Assignment 35 Table 16 USB Onboard Pin Assignment 35 Table 17 Gigabit Ethernet Connectors and ETH1 Pin Assignment 38 Table 18 VPX Connector PO Wafer
93. matically after each writing or read data byte The VX3230 includes a built in crystal oscillating at 32 768 MHz Crystal accuracy accross temperature 160 ppm at 40 C 0 ppm at 25 C 140 ppm at 85 The will be connected to the second 2 controller inside the MPC8544 at I2C address 0 51 Nominal operating voltage 3V3 Minimal clock operating voltage 1 2V A 3V RTC backup battery BR1225 can be equipped in a keystone socket This battery support extended temperature range 2 6 3 VPD EEPROM One M24C256 eeprom 256 kb serial eeprom contains Vital Product Data This memory is organized as 8192x8 bits Page 28 CA DT A63 1e VX3230 User s Guide Functional Description 2 6 4 Thermal Sensors Four thermal sensors located on the I2C bus are available on the VX3230 gt LM95231 CPU sensor the CPU core temperature is monitored by a LM95231CIMM device at 12C hardware address 0x2b This devices uses remote sensing on CPU thermal diode and also indicates local board temperature This sensor temperature is dedicated to junction processor temperature and check only maximal Tj temperature Key features Local temperature accuracy 3 C Remote temperature accuracy 0 75 C gt Operating temperature 0 125 C gt LM73 board sensor the board temperature is monitored by three LM73 devices at I2C hardware addresses 0x48 1 top 0x49 2 bottom and Ox4a 3 top Key features gt
94. mation relating to this product PRODUCT PUBLICATION VX3230 Boards VX3230 Hardware Release Notes CA DT A64 VX3230 U Boot User Manual SD DT F46 VX3230 PBIT User s Guide SD DT F48 VX3230 Releases Notes Fedora 9 SD DT F47 VX3230 VxWorks B S P User s Guide SD DT F56 EZ3 VX3230 Systems EZ3 VX3230 00 L Quick Start SD DT F53 EZ3 VX3230 0P V Quick Start SD DT F61 EZ3 VX3230 Getting Started EZ3 VX3230 00 L EZ3 VX3230 00 V EZ3 VX3230 0P V SD DT F52 EZ3 VX3230 Getting Started EZ3 VX3230 00 1K Wind River VxWorks Live USB Evaluation SD DT F68 MPC8544 MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual MPC8544ERM Rev 1 10 2007 Serial ATA Serial ATA 1 0a Specification VITA 38 System Management for VME ANSI VITA 38 2003 VITA 46 0 VPX Base Standard ANSI VITA 46 0 2007 VITA 46 4 PCI Express on VPX Fabric Connector VITA Draft Standard VITA 46 6 Gigabit Ethernet Control Plane on VPX VITA Draft Standard VITA 46 9 PMC XMC Ethernet Signal Mapping to 3U 6U on VPX Modules VITA Draft Standard VITA 46 10 Rear Transition Module on VPX ANSI VITA 46 10 2009 Table 11 Related Publications Page 20 CA DT A63 1e VX3230 User s Guide Functional Description Chapter 2 Functional Description Refer to following sections for detailed information Section 2 1 page 23 gt gt Section 2 1 1 page 23 Section 2 1 2 page 24 Section 2 2 page 25 Processor and System Memory Processor
95. me PCB for both air and conduction cooled boards Builds variants span a complete range of temperature shock and vibration requirements as specified in the VITA 47 standards Rear Transition Module The VX3230 supports the VX3230 RTM a 3U VPX rear Transition Module compliant to Rear Transition Module on VPX standard VITA 46 10 CA DT A63 1e Page 5 Introduction VX3230 User s Guide 1 3 2 Order Code Table Several manufacturing options are available gt Air cooled or rugged conduction cooled builds XMC PMC slot or no XMC PMC slot 10 100 1000BASE TX or 1000BASE BX Ethernet interfaces Available order codes are listed in table below VX3230 SA VX3230 SA VX3230 SA VX3230 SA VX3230 RC VX3230 RC VX3230 RTM VX3230 RTM VX3230 RTM VX3230 RTM FLASH Module FLASH Module COP JTAG Module Kit Rib PMC Page 6 3U VPX Air Cooled Commercial Build SBC VX3230 SAA1N 000 VX3230 Air Cooled Commercial Build 1GB SDRAM No User Flash XMC PNC slot 10 100 1000BASE TX Ethernet interfaces VX3230 SAA1N 001 VX3230 Air Cooled Commercial Build 1GB SDRAM No User Flash no XMC PMC slot 10 100 1000BASE TX Ethernet interfaces VX3230 SAA1N 010 VX3230 Air Cooled Commercial Build 1GB SDRAM No User Flash XMC PMC slot 1000BASE BX Ethernet interfaces VX3230 SAA1N 01 1 VX3230 Air Cooled Commercial Build 1GB SDRAM No User Flash no XMC PMC slot 1000BASE BX Ethernet interfaces 3U VPX Rugged Conduction Cooled Build SBC VX3
96. oard input voltage OLTA O AL VA OLERA REMAR 5V 5 0 VDC 5 2 5 50 Main voltage 3 3V 3 3 VDC 4 5 1 5 50 mV Main voltage 12V 12 VDC 5 5 50 Required for slot 12V 12 VDC 5 5 50 Required for slot GND Ground nat directly connected to potential earth PE Table 42 Input Voltage Characteristics The output voltage overshoot generated during the application load changes or during the removal of the input voltage must be less than 5 of the nominal value No voltage of reverse polarity may be present on any output during turn on or turn off 5 1 3 4 Regulation The power supply shall be unconditionally stable under line load unload and transient load conditions including capacitive loads The operation of the power supply must be consistent even without the minimum load on all output lines If the main power input is switched off the supply voltages will not go to OV instantly It will take a couple of Note seconds until capacitors are discharged If the voltage rises again before it went below a certain level the circuits may enter a latch up state where even a hard RESET will not help any more The system must be Switched off for at least 3 seconds before it may be switched on again If problems still occur turn off the main power for 30 seconds before turning it on again Page 92 CA DT A63 1e VX3230 User s Guide Power Conside
97. of operations from receipt of the board up to getting it working in your system Each topic is covered in a separate chapter and each chapter begins with a brief introduction that tells you what the chapter contains In this way you can skip any chapters that are not applicable or with which you are already familiar The chapters are Chapter 1 Introduction this chapter Chapter 2 Functional Description Chapter 3 Installation Chapter 4 Programming Interface Chapter 5 Power and Thermal Considerations Chapter 6 VX3230 RTM Characteristics Chapter 7 VX3230 RC Characteristics V V M MV V CA DT A63 1e Page 3 Introduction VX3230 User s Guide 1 2 Overview VPX VITA 46 specifications establish a new direction for the next revolution in bus boards VPX is a proposed ANSI standard which breaks out from the traditional connector scheme of VMEbus to merge the latest in connector and packaging technology with the latest in bus and serial fabric technology VPX combines best in class technologies to assure a very long technology cycle similar to that of the original VMEbus solutions Traditional parallel VMEbus will continue to be supported by VPX through bridging schemes that assure a solid migration pathway For further information regarding this standards and its use visit the home page of the VITA Open Standards Open Markets 1 3 Board Overview 1 3 1 Main Features Freescale MPC8544 PowerPC Architect
98. ogos and trademarks which are registered trademarks and therefore proprietary to their respective owners Environmental Protection Statement This product has been manufactured to satisfy environmental protection requirements where possible Many of the components used structural parts printed circuit boards connectors batteries etc are capable of being recycled Final disposition of this product after its service life must be accomplished in accordance with applicable country state or local laws or regulations Environmental protection is a high priority with Kontron Kontron follows the DEEE WEEE directive You are encouraged to return our MO products for proper disposal The Waste Electrical and Electronic Equipment WEEE Directive aims to gt reduce waste arising from electrical and electronic equipment EEE make producers of EEE responsible for the environmental impact of their products especially when they become waste gt encourage separate collection and subsequent treatment reuse recovery recycling and sound environmental disposal of EEE improve the environmental performance of all those involved during the lifecycle of EEE CA DT A63 1e Page ii VX3230 User s Guide Preface Conventions This guide uses several types of notice Note Caution ESD Note this notice calls attention to important features or instructions UN Caution this notice alert you to system damage loss of d
99. on and Switching between 10Base T 100Base TX and 1000Base T data transmission Auto Negotiation Auto wire switching for crossed cables is also supported Auto MDI X Refer to section 1 3 4 Ethernet Connectivity page 9 for more information on the ethernet configuration depending on the ethernet board manufacturing option Regarding the Ethernet interfaces manufacturing option it is strongly recommended to the to use a RTM and SBC compatible gt same ethernet manufacturing option PB VX3 000 PB VX3 010 PB VX3 001 PB VX3 011 Ethernet Front Panel Up to two Gigabit Ethernet interfaces implemented Y x1 Interfaces as dual RJ 45 connector without LEDs ETH1 only CN12 R CN13 R 1 8 1 8 VX3230 RTM SPECIFICATIONS ETHO ETH1 Figure 41 Gigabit Ethernet Connectors The two RJ 45 ethernet ports have identical signal assigment The Ethernet transmission can operate effectively using a CAT5 cable or higher specifications ANDARD R AB RO D R AB OBA OOBA DOOBA OBA OOBA OOOBA O O A O 9 TX TX BILDA 1 RX RX lO BI DB TX TX BI_DA 2 RX RX BI DB RX RX BI_DB 3 O TX TX BI_DA BI DC 4 BI_DD BI DC 5 gt BI_DD TX RX BI DB 6 TX TX BI DA z BI_DD 7 BI_DC BI DD 8
100. onnector Pin Assignment CA DT A63 1e Page 51 Functional Description VX3230 User s Guide 2 8 10 Signal Decription LEGEND SIGNAL DESCRIPTION GA 0 2 12C channel select These signals allow a carrier to address a specific XMC slot an IPMI I2C bus shared by multiple XMCs GND XMC Built In Self Test This signal allows the carrier to determine whether an XMC has completed its built in self test MPRESENT Module present This signal allows the carrier to determine whether an XMC is present MRSTI XMC Reset In When this signal is asserted low by the carrier the mezzanine card shall initialize itself into a known state XMC Reset Out As input to the carrier this optional signal provides an input to the carrier s reset logic in order to support a reset button or other reset source on the XMC 2 serial clock 2 serial data XMC Write Prohibit When this signal is asserted high the XMC shall disable writes to non volatile memory on the XMC Not Connected Do not Used PETOp n 0 7 Link O Differential Transmit These signals are used by the XMC to receive high speed protocol specific data TO the carrier over the PCI Express inter face PEROp n 0 7 Link O Differential Receive These signals are used by the XMC to receive high speed protocol specific data FROM the carrier over the PCI Express interface REFCLK 0 Differential reference clock for Link O PCI Express interfa
101. onnectors Identification VPX Connectors Description PMC J11 Connector PMC J12 Connector PMC J14 Connector PMC Signal Description XMC J15 Connector XMC Signal Description COP Connector JTAG Connector PMC Site CA DT A63 1e VX3230 User s Guide Functional Description 2 1 Processor and System Memory 2 1 1 Processor The VX3230 15 build around the Freescale MPC8544 e500 processor The following list provides an overview of the MPC8544 feature set gt High performance 32 bit 500 core that implements resources for embedded processors defined by the Power ISA 32 Kbyte L1 instruction cache and 32 Kbyte L1 data cache with parity protection Caches can be locked entirely or on a per line basis with separate locking for instructions and data Signal processing engine SPE instructions Extensive instruction set for vector 64 bit integer and fractional operations Double precision 64 bit floating point instructions that use the 64 bit GPRs Embedded vector and scalar single precision 32 bit floating point instructions 36 bit real addressing up to 64 Gbytes of memory Memory management unit MMU especially designed for embedded applications that support 4 Kbyte 4 Gbyte page sizes 256 Kbyte L2 cache SRAM Address translation and mapping unit ATMU DDR DDR2 memory controller Programmable interrupt controller PIC Dual 12C controllers Boot sequencer DUART Local bus controller LBC Two
102. onnel 3 1 Safety Requirements The following safety precautions must be observed when installing or operating the VX3230 Kontron assumes no responsibility for any damage resulting from failure to comply with these requirements Due care should be exercised when handling the board due to the fact that the heat sink can get very hot ANS not touch the heat sink when installing or removing the board In addition the board should not be placed on any surface or in any form of storage container until such time as the board and heat sink have cooled down to room temperature avoid damage to your board Discharge your clothing before touching the assembly Tools must be discharged before use Do not touch components connector pins or traces If working at an anti static workbench with professional discharging equipment please do not omit to use it This board contains electrostatically sensitive devices Please observe the necessary precautions to Page 56 CA DT A63 1e VX3230 User s Guide Installation 3 2 Board Identification The VX3230 boards are identified by labels fitted to the top and bottom sides Top Side Order Code label B Serial Number label Functional Identification label Variant E C level CPLD Identification label a Figure 21 VX3230 Identification Top Side CA DT A63 1e Page 57 Installation VX3230 User s Guide Bottom Side E GbE1 Ethernet Numbe
103. or the initial installation of the VX3230 in a system Procedures for standard removal and hot swap operations are found in their respective chapters To perform an initial installation of the VX3230 in a system proceed as follows 1 Ensure that the safety requirements indicated in Chapter 3 1 are observed Failure to comply with the instruction below may cause damage to the board or result in improper System operation 2 Ensure that the board is properly configured for operation in accordance with application requirements before installing For information regarding the configuration of the VX3230 refer to Chapter 4 For the installation of VX3230 specific peripheral devices and Rear I O devices refer to the appropriate chapters in Chapter 3 Care must be taken when applying the procedures below to ensure that neither the VX3230 nor other system boards are physically damaged by the application of these procedures 3 To install the VX3230 perform the following 1 Ensure that no power is applied to the system before proceeding When performing the next step DO NOT push the board into the backplane connectors Use the ejector handles to seat the board into the backplane connectors 2 Carefully insert the board into the slot designated by the application requirements for the board until it makes contact with the backplane connectors 3 Using the ejector handle engage the board with the backplane When the ejector handle is locked the
104. r label This number is in hexadecimal GbE2 Ethernet Number label This number is hexadecimal a U Boot Firmware label MA Figure 22 VX3230 Identification Bottom Side Page 58 CA DT A63 1e VX3230 User s Guide Installation 3 3 Board Configuration Figure 23 Board Configuration One 4 bit DIP switches are available on the VX3230 SW1 3 3 1 DIP Switch SW1 Description DIP Switch SW1 Function Description Not used 2 Flash Boot ON 0 Boot in Rescue Mode OFF 1 Boot in Standard Mode 3 Boot Flash WP ON 0 Boot Flash Write Protected OFF 1 Boot Flash Write Enabled Factory ON 0 Factory Mode OFF 1 Normal Mode CA DT A63 1e Page 59 Installation VX3230 User s Guide 3 4 Package Content The VX3230 is packaged with several components The packing contents of the VX3230 Series may vary depending on customer requests gt CPU Module Order Code refer to section 1 3 2 Order Code Table page 6 Processor specifications differ depending on Order Code Heat sink assembled on the board gt Rear Transition Module Order Code refer to section 1 3 2 Order Code Table page 6 gt USB Flash Disk Module Order Code refer to section 1 3 2 Order Code Table page 6 gt CD ROM Technical Documentation Page 60 CA DT A63 1e VX3230 User s Guide Installation 3 5 Initial Installation Procedures The following procedures are applicable only f
105. rations 5 1 3 5 Rise Time Diagram The following figure illustrates an example of the recommended start up ramp of a VPX power supply for all Kontron boards delivered up to now pu 5 i 2 2 a LAR EP S a d A E EE 5 4 Vce5 1V 2 V 25 mS 2 Vcc 33V 1 V 25mS Figure 29 Start Up Ramp of the CP3 SVE180 AC Power Supply CA DT A63 1e Page 93 Power Considerations VX3230 User s Guide 5 2 Power Consumption The goal of this description is to provide a method to calculate the power consumption for the VX3230 and for additional configurations The processor dissipates the majority of the thermal power The power consumption tables below list the voltage and power specifications for the VX3230 board The values were measured using an 5 slot passive VPX backplane The operating system used was Linux Fedora 9 All measurements were conducted at a temperature of 25 The measured values varied because the power consumption was dependent on processor activity 5 2 1 Real Applications The following tables indicate the power consumption using real applications with soldered DDR2 SDRAM The Power Consumption was measured under gt the BIOS Linux IDLE Mode Linux with 100 processor load MPC8544 1 GHz MPC85441 GHz MPC85441 GHz MPC85441 GHz BIOS Linux IDEL Mode Linux 100 Proc Load Linux 100 Proc Load measured at 25 C measured at 25 measured at 25 C measured at 85 C 5V 13 55W 15 74W 16 00W 16 2
106. rved 0 R Re F LOC is writable only if BFC is in Normal Mode LIN N Page 78 CA DT A63 1e VX3230 User s Guide 4 4 14 Host I O Configuration Register Programming Interface REGISTER NAME Host I O Configuration ADDRESS 000 0287 DESCRIPTION VALUE 55 7 WDG_LOCK Lock Unlock Watchdog 0 R WO 0 watchdog is unlocked and can be stopped for test mode 1 watchdog is locked after setting WEN bit register 0 000 0282 Only a board reset can clear WDG LOCK bit 6 4 Res Reserved 0 R 3 USB1 DIR USB1 Direction 0 R W 0 USB Flash 1 Rear panel 2 USBO DIR USB1 Direction 0 R W 0 Front panel 1 Rear panel 1 ETH1_LS ETH1 Lan Switch 0 R W 0 Front panel 1 Rear panel 0 ETHO_LS ETHO Lan Switch 0 R W 0 Front panel 1 Rear panel 4 4 15 Board ID Register REGISTER NAME Board ID ADDRESS 0 000 0288 DESCRIPTION Board Identification O VM6250 board 1 VX3230 board 55 CA DT A63 1e Page 79 Programming Interface VX3230 User s Guide 4 4 16 GPIO Status Command Register REGISTER NAME GPIO Status Command ADDRESS 000 0289 RESET BIT DESCRIPTION VALUE ACCESS 7 4 Res Reserved 0 R 3 GPIO3 Status in input mode 1 R W GPIO3 Command in output mode 2 GPIO2 Status
107. s forced to 32 bits 33 MHz On the USB 2 0 Rear I O ports it is strongly recommended to use a cable below 3 meters in length for USB 2 0 devices The USB 2 0 ports are high speed full speed and low speed capable Hi speed USB 2 0 allows data transfers of up to 480 Mb s 40 times faster than a full speed USB USB 1 1 Refer to section 2 8 3 VPX Bus Interface page 37 for more information on the USB interfaces wafer assignment on P1 connector Page 34 CA DT A63 1e VX3230 User s Guide Functional Description gt gt USB Front Panel PIN SIGNAL FUNCTION o 1 VCC vcc E 4 2 USB_D Differential USB VO 1 3 USB Differential USB IO 4 GND GND Table 15 USB Connector Pin Assignment A UU 5V protected power up to 720 mA continuous short circuit current limited 1 2 max with thermal JN shutdown and automatic restart when short is removed USB onboard The onboard USB device CN5 connector is used to connect an USB Flash Disk low profile USB flash mezzanine like Intel Zepher card The following figure and table provide pinout information for the onboard USB connector CN5 PIN SIGNAL FUNCTION I O 46810 1 PWR VCC 3 Data Differential USB 1 4 Not Connected 5 Data Differential USB 6 Not Connected 1357 7 GND GND 8 Not Connected 5
108. s disabled 1 P1G1 IRQ is enabled 3 P1G1CTRL VPX P1G1 Connector VPX P1 pin G1 mode 0 R W 0 P1G1 is configured in input 1 PIG1 is configured in output 2 MSKR2LOC propagation of VPX Maskable Reset MaskableReset 0 R W to the local reset 0 Reset not propagated 1 Reset propagated 1 ETH1_SRDS ETH1 Interface Mode 0 RAW 0 Force 1000BASE T 1 Auto Selection 0 ETHO_SRDS ETHO Interface Mode 0 R W 0 Force 1000BASE T 1 Auto Selection Page 88 CA DT A63 1e VX3230 User s Guide Programming Interface 4 4 33 GPIO4 Register REGISTER NAME 4 Register ADDRESS 000 0298 RESET DESCRIPTION VALUE 55 7 5 Res Reserved 0 R 4 4 IRQ GPIO4 Interrupt 0 R W 1 Interrupt is occurred on 4 signal 0 No interrupt occurs Writing 1 to this bit clears the bit 3 IRQSENS 4 GPIO4 sensitivity 0 R W 0 IRQ is activated on a falling edge in edge mode or on level 0 in level mode 1 IRQ is activated on a rising edge in edge mode or on level 1 in level mode 2 IRQMODE 4 GPIOA Interrupt mode 0 R W 0 GPIO4 IRQ is in edge mode 1 GPIO4 IRQ is in level mode 1 GPIOIRQ 4 GPIOA interrupt activation 0 RAW 0 GPIOA interrupt mode is disabled 1 GPIOA interrupt mode is enabled 0 GPIO4 mode 0 R W 0 GPIO4 is configured in input 1 GPIO4 is configured in output
109. tandoffs and the holes at the front the middle and the rear of the PMC with the matching holes on the VX3230 RC board 2 Lower the XMC PMC component side down fitting the mezzanine board connectors into their mating connectors on the VX3230 RC Press them together so that the friction from the pins holds the mezzanine board in place 3 Screw the XMC PNC in place using mounting screws 5 at front of the board 5 in the middle of the board and 2 at the rear of the board Screws dimension M2x6mm Tighten with a torque of 0 383 Nm 0 233 Ibf ft Figure 50 shows the location of the standard anchorage points on an VX3230 RC board e 2522 e 3 Sa em oS a Figure 50 Standard Anchorage Points on VX3230 RC Board Page 128 CA DT A63 1e VX3230 User s Guide VX3230 RC Characteristics Additional Anchorage Point In order to satisfy the shock and vibration specifications foresee an additional anchorage point that could either be the 3 3V keying pin hole Figure 51 shows the location for an additional anchorage A point on an VX3230 RC board V NLIVS DEZEXA e e e e e e e e e Figure 51 Additional Anchorage Point on VX3230 RC Board CA DT A63 1e Page 129 VX3230 RC Characteristics VX3230 User s Guide Fastening Kit Order Code KIT RIBPMC1V01 1 2x 1 01 Two additional ribs Only one rib can be installed on the VX3230 RC board
110. ting USB devices gt One interface is available on the VX3230 RTM front panel One USB peripheral may be connected to this port To connect more USB devices an external hub is required The second USB interface is onbard and used to connect a Flash disk USB Front Panel The following figure and table provide pinout information for the CN11 R connector located on the front panel PIN SIGNAL FUNCTION yo 1 VCC VCC CN11 R 2 UVO Differential USB 1 0 3 UVO Differential USB 1 0 1 4 GND GND 1 Table 47 Front Panel USB Connector Pin Assignment Figure 37 Front Panel USB Connector The USB host interfaces on the VX3230 RTM can be used with maximum 500 mA continuous load current as specified the Universal Serial Bus Specification Revision 2 0 Short circuit protection is provided All the signal lines EMI filtered Zz The Rear interface supports the USB 1 1 and USB 2 0 standards For USB 2 0 it is strongly recommended to use a cable length not exceeding 3 meters 7 CA DT A63 1e Page 105 VX3230 RTM Characteristics VX3230 User s Guide USB Onboard The onboard USB device CN21 R connector is used to connect an USB flash disk module The following figure and table provide pinout information for the onboard USB connector PIN SIGNAL FUNCTION 1 USB_PWR VCC 2 N C Not Connected 3 USB_D Differential USB 1 0
111. uh ena bees 83 4 4 22 Timer Middle Upper Byte Register 83 4 4 23 Timer Middle Lower Byte Register 83 4 4 24 Timer LSB Byte Register 1 83 4 4 25 Logic Sub Reviision Register 83 4 4 26 COM1 2 Configuration Register 84 44 2 VPX RegISIGE ore eh aoe sir bed npe eco ee beu ooa ie 85 4 4 28 VPX Reset Register 2 85 44 29 Geographical Addressing 86 4 4 30 VPX Common Clock Register 86 44 31 WPXPCle Switch Register 87 44 32 Open VPX Register a id M EVERY MER Rb 88 44 33 GPIO4 REGISICN rs cer cudnt a giebt d in ze 89 Chapter 5 Power Considerations 90 5 1 System dirias did beads 90 230 tne ves 90 5 1 2 90 5 1 3 Power Supply Units
112. ule LED O 0001 get Module LED 1 0010 get Module LED 2 0111 Reserved 1000 set Module LED 0 1001 set Module LED 1 1010 set Module LE 2 1111 Reserved RESET DESCRIPTION VALUE 55 0000 R W 3 0 ULCOL User Specific LED color 0000 off 0001 green 0010 red 0011 amber reserved 1001 green fast blinking 1010 red fast blinking 1011 amber fast blinking 0000 R W 4 4 20 PCI Mode Register REGISTER NAME PCI Mode ADDRESS 0 000 028 RESET DESCRIPTION VALUE 55 7 4 Reserved 0000 R 3 PCI FREQ PCI Frequency 0 R 0 PCI frequency equal to 33 MHz 1 PCI frequency equal to 66 MHz 2 PCI PCI BUSMODE1 1 R BUSMODE1 0 PMCB board is connected 1 PPMCB board is not present 1 MPRES MPRES 1 R 0 XMC board is connected 1 XMC board is not present 0 PCI RST PCI Reset 0 R 0 PCI Reset activated 1 PCI Reset deactivated Page 82 CA DT A63 1e VX3230 User s Guide Programming Interface 4 4 21 Timer MSB Byte Register REGISTER NAME Timer MSB Byte Register ADDRESS OxF000 028 DESCRIPTION ACCESS Counter value 4 4 22 Timer Middle Upper Byte Register REGISTER NAME Timer Middle Upper Byte Register 5 5 0 000 0290 DESCRIPTION ACCESS Counter value 4 4 23 Timer Middle Lower Byte Register REGISTER NAM
113. ultaneously SATA PORT CONNECTOR USAGE SATAO CN14 R on the VX3230 RTM External SATA HDD drives e g 2 5 or 3 5 SATA HDDs SATA1 CN15 R on the VX3230 RTM External SATA HDD drives e g 2 5 or 3 5 SATA HDDs Table 25 SATA Port Features CA DT A63 1e Page 45 Functional Description VX3230 User s Guide P2 Wafer Assignment gt Legend for Table 26 COM port PMC I O Wafer Row G Row F Row E Row D Row C Row B Row A 1 GND GND 2 GND GND GND 3 GND GND 4 GND GND GND 5 GND GND 6 GND GND GND 7 GND GND 8 GND GND GND 9 GND GND 10 GND GND GND 11 GND GND 12 GND GND GND 13 GND GND 14 GND GND GND 15 GND GND 16 GND GND GND CASE GND Table 26 VPX Connector P2 Wafer Assignment P2 Signal Definition COMx CTS RXDb Channel ElA 232 x Clear To Send EIA 485 Receive Data pair b COMx RTS TXDb Channel EIA 232 x Ready To Send EIA 485 Transmit Data pair b COMx RXD RXDa Channel EIA 232 x Receive Data ElA 485 Receive Data pair a COMx TXD TXDa Channel EIA 232 x Transmit Data EIA 485 Transmit Data pair a GND Ground PMCIO 01 64 01 through 64 Table 27 VPX Connector P2 Signal Definition Page 46 CA DT A63 1e VX3230 User s Guide Functional Description 2 8 5 J11 Connector Pin Assignment Pin Signal Pin Signal Pin Signal Pin Signal al one up mo po mee ia fe wp a se ow V 1 0 1 AD 31 36 8 NOE BUSHODE
114. ure The VX3230 3U VPX SBC is based on the Freescale MPC8544 integrated host processor clocked at 1 GHz The MPC8544 integrates an e500v2 core built on Power Architecture technology with system logic required for networking telecommunications and wireless infrastructure applications The MPC8544 is a member of the PowerQUICC I family of devices that combine system level support for industry standard interfaces with processors that implement Power Architecture technology The MPC8544 uses the e500 core and high speed interconnect technology to balance processor performance with system throughput The e500 core implements embedded resources defined by the Power ISA and provides unprecedented levels of hardware and software debugging support Additionally the MPC8544 offers a double precision floating point auxiliary processing unit APU 256 Kbytes of level 2 cache two integrated 10 100 1Gb enhanced three speed Ethernet controllers eTSECs with TCP IP acceleration and classification capabilities a DDR DDR2 SDRAM memory controller a 32 bit PCI controller a programmable interrupt controller two 12C controllers a four channel DMA controller a general purpose port and dual universal asynchronous receiver transmitters DUART For high speed interconnect the MPC8544 provides a set of multiplexed pins that support up three PCI Express interfaces The high level of integration in the MPC8544 helps simplify board design and off
115. way round The plus pole must be on the top Care must be taken to ensure that the battery is correctly replaced 2 The battery should be replaced only with an identical equivalent type recommended by the N manufacturer Dispose of used batteries according to the manufacturer s instructions Page 64 CA DT A63 1e VX3230 User s Guide Installation 3 7 3 Installation PMC modules are delivered with a full kit of parts for mounting them and the user guide for the module normally contains instructions on how to fit the module The installation of the PMC on the VX3230 conforms to the IEEE P1386 1 standard To install the XMC PMC module refer to Figure 26 to Figure 28 and follow the steps below A To avoid ESD damage wear an antistatic wrist strap to discharge static electricity while performing any part of the installation that involves touching the VX3230 board or the XMC PMC If you can t wear an antistatic wrist strap touch one hand to the bare metal surface to provide grounding 1 Place carefully the VX3230 with the backplane connectors facing you on a static dissipative surface connected to a common ground by a low resistance connection Do not slide the board over any surface 2 Remove the blanking plate from the appropriate XMC PMC slot of the VX3230 3 Check that the standoffs are attached to the XMC PMC 4 Install the XMC PMC component side down aligning the connectors with their mating connectors on the VX32
116. wee dnd de o 26 24 Perpherals p ERR a A AA 27 2 4 4 E 27 2 4 2 Watchdog Timer 2 22 24 Ra 27 2 5 System FPGA a ete KR 27 CA DT A63 1e VX3230 User s Guide Table Of Contents 260 ZC A A 28 2 6 1 Internal 2 Slaves 28 202 rat edd dan back abans d 28 2 63 VPD EEPROM oade eaaa e dace dat e ii ci bar 28 264 Thermal Sensors 2 29 2 0 5 Voltage Sensors ei da 31 2 6 6 External SMB 31 27 VX3230 Connectors 4 32 2 8 Board Interfaces cios ee ead a DX qu ee 33 2 8 4 Serial Interfaces 33 280 2 USB Interaces i i oes i ete ddr dee bad woes 34 2 8 3 Gigabit Ethernet Interfaces 2 37 2 8 3 1 Pinoufs 38 264 WPXBuslnteiface csset Rex re RR da RA Ad ened oad 39 2 8 4 1 Board Connectors Identification 39 2 8 4 2 Connectors Description
117. x RTS controlled 1 0 trans mitter off on 11s 485 half duplex RTS controlled 1 0 send receive Re In Rescue Mode in Host I O Status Register 0 COM1 is forced in EIA 232 full duplex mode LIN N Page 84 CA DT A63 1e VX3230 User s Guide Programming Interface 44 27 VPX Register REGISTER NAME VPX register ADDRESS 000 0295 RESET BIT DESCRIPTION VALUE 55 7 SW NT PCle Switch Non Transparent port activation 0 R W 0 Non Transparent port activated 1 Non Transparent port deactivated 6 SW INT1 PCle Switch Interrupt 1 R 5 SMB1_ENA SMBUS 1 Activation 0 R W 0 SMB 1 not used 1 12C two connected to SMB 1 4 SW ERR PCle Switch Fatal Error 1 R 0 Fatal Error generated 3 NT RST Transparent PCle Switch reset 1 R 0 Non Transparent reset activated 2 Res Reserved 0 R 1 NVMRO VPX NVMRO N A R W 1 0 All non volatile memory is write enabled 1 All non volatile memory is write protected 1 NVMRO VPX NVMRO N A R W 0 all non volatile memory is write protected 1 12C two connected to SMB 1 0 SPI CS PCle Switch SPI EEPROM N A R W 0 Read allowed 1 Read not allowed fete NVMRO is writable when System controller UN N 4 4 28 VPX Reset Register REGISTER NAME VPX Reset ADDRESS 000 0296 B A D RIPTIO A 7 3 Res Reserved 0 R 2 VPX RST

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