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PCA9685

1. 12 4 APPLICATIONS INFORMATION cccsssssccssscssccsssccccssssccscssscccsssssccessscccsssccssessececcssnscsscnsncsssssocccesscesscssscsseeses 13 4 1 PIN OUTAND SIGNAL DESCRIPTION eoe ore tate rero Ente vore E aUe e PER e PEU 13 4 2 TYPICAL OPERATING CIREUIT 14 4 3 BILL OF MATERIALS FOR EXTERNAL COMPONENTS 222 r rtr r 14 4 4 RECOMMENDED POWER ON PROCEDURE ssssseeseseseseseseseseceseceveceveseseseeesesesesecesesesesesesesesecesesesesecereceseseneeenees 15 5 FUNCTIONAL OVERVIEW 16 5 1 BLOCK DIAGRAM 16 5 2 16 5 3 THREE AXIS MEMS GYROSCOPE WITH 16 BIT ADCS AND SIGNAL 2 22222 16 5 4 SERIAL COMMUNICATIONS AD n Aan nA E EAn EAS EI En Ean aranana 17 5 5 CLOCKING 009 17 5 6 SENSOR DATA REGISTER 17 5 7 INTERRUPTS N en 17 5 8 DIGITAL OUTPUT TEMPERATURE SENSOR 4 17 5 9 BIAS AND EDO er
2. 40 20 0 20 40 60 80 100 120 TEMPERATURE C Figure 27 Z Axis Sensitivity vs Temperature Eight Parts Soldered to PCB Vs 3 3 V Full Resolution 07925 225 07925 226 07925 227 ADXL345 60 25 50 40 30 20 PERCENT OF POPULATION PERCENT OF POPULATION o a 3 a 8 10 0 0 2 0 5 0 8 1 1 1 4 1 7 2 0 100 110 120 130 140 150 160 170 180 190 200 amp SELF TEST RESPONSE g 2 CURRENT CONSUMPTION pA 2 Figure 28 X Axis Self Test Response at 25 Vs 2 5 V Figure 31 Current Consumption at 25 100 Hz Output Data Rate Vs 2 5 V 60 160 140 _ 50 L 120 z 9 40 5 amp 100 3 2 Q 30 80 o B 9 E 60 z 20 tc R 40 u o 10 20 0 9 0 2 0 5 0 8 1 1 1 4 1 7 2 0 8 1 60 3 12 6 2512 50 25 50 100 200 400 800 1600 3200 SELF TEST RESPONSE g OUTPUT DATA RATE Hz 5 Figure 29 Y Axis Self Test Response at 25 Vs 2 5 V Figure 32 Current Consumption vs Output Data Rate at 25 C 10 Parts Vs 2 5V 60 200 _ 50 5 150 z o 40 3 E 2 5 9 30 E 100 gt
3. ALLAN DEVIATION ug 07925 251 AVERAGING PERIOD T s Figure 52 Root Allan Deviation PERCENTAGE OF NORMALIZED NOISE 70 2 0 2 2 2 4 2 6 2 8 3 0 3 2 3 4 SUPPLY VOLTAGE Vs V o 07925 252 Figure 53 Normalized Noise vs Supply Voltage Vs OPERATION AT VOLTAGES OTHER THAN 2 5 V The ADXL345 is tested and specified at a supply voltage of Vs 2 5 V however it can be powered with Vs as high as 3 6 V or as low as 2 0 V Some performance parameters change as the supply voltage changes offset sensitivity noise self test and supply current Due to slight changes in the electrostatic forces as supply voltage is varied the offset and sensitivity change slightly When operating at a supply voltage of Vs 3 3 V the x and y axis offset is typically 25 mg higher than at Vs 2 5 V operation The z axis is typically 20 mg lower when operating at a supply voltage of 3 3 V than when operating at Vs 2 5 V Sensitivity on the x and y axes typically shifts from a nominal 256 LSB g full resolution or 2 g 10 bit operation at Vs 2 5 V operation to 265 LSB g when operating with a supply voltage of 3 3 V The z axis sensitivity is unaffected by a change in supply voltage and is the same at Vs 3 3 V operation as itis at Vs 2
4. 38 10 2 QUALIFICATION TEST PLAN nnne nnne 38 3 39 Document Number PS ITG 3200A 00 01 4 5 Z Revision 1 4 InvenSense ITG 3200 Product Specification Rose Dare acta 1 Document Information 1 1 Revision History Revision Date Revision Description 10 23 09 1 0 Initial Release 10 28 09 1 1 Edits for readability e Changed full scale range and sensitivity scale factor Sections 2 3 1 5 3 and 8 3 e Changed sensitivity scale factor variation over temperature Section 3 1 e Changed total RMS noise spec Section 3 1 e Added range for temperature sensor Section 3 1 e Updated VDD Power Supply Ramp Rate specification Sections 3 2 and 4 4 e Added VLOGIC Voltage Range condition Section 3 2 e Added VLOGIC Reference Voltage Ramp Rate specification Sections 3 2 and 4 4 e Updated Start Up Time for Register Read Write specification Section 3 2 e Updated Input logic levels for ADO and CLKIN Section 3 2 e Updated Level Io specifications for the I C interface Section 3 3 Updated Frequency Variation Over Temperature specification for internal clock source Section 3 4 e Updated VLOGIC conditions for Characterization Section 3 5 e Updated ESD specification Section 3 6 e Added termination requirements for CLKIN if unused Section 4 1 e Added recommended po
5. DLPF_CFG DLPF_CFG Low Pass Filter Bandwidth Internal Sample Rate 0 256Hz 8kHz 1 188Hz 1kHz 2 98Hz 1kHz 3 42 Hz 1kHz 4 20Hz 1kHz 5 10Hz 1kHz 6 5Hz 1kHz 7 Reserved Reserved Parameters FS_SEL Full scale selection for gyro sensor data DLPF_CFG Digital low pass filter configuration and internal sampling rate configuration 24 of 39 Z lt 5 N e e E ur Dn 8 5 E o E 5 o A ITG 3200 Product Specification Revision 1 4 7 ense InvenSi Release Date 03 30 2010 DLPF Characteristics The gain and phase responses of the digital low pass filter settings DLPF_CFG are shown below Bode Diagram AAA f EE Ho TV t ET A E o1 p m 1 j jot o d O E e pen peaa Tresen men TEE HA po 1 1 pepe po d ATAR eal e o o LO e wow oe wo Y epnyubeyy Frequency Hz ing tal Filter Setti Gain and Phase vs Bode Diagram ia maa pi
6. Limit Parameter Test Conditions Min Max Unit Digital Input Low Level Input Voltage Vu 0 3 X VoD vo V High Level Input Voltage Vin 0 7 X V Low Level Input Current l Vin 0 1 uA High Level Input Current liu 0 0 1 uA Digital Output Low Level Output Voltage Voi lt 2 V lo 3 mA 0 2 X Von vo Vooo gt 2 V lo 3 mA 400 mV Low Level Output Current lot Vor VoL max 3 mA Pin Capacitance fiw 1 MHz Vin 2 5 V 8 pF Limits based on characterization results not production tested SINGLE BYTE WRITE MASTER START SLAVE ADDRESS WRITE REGISTER ADDRESS DATA STOP SLAVE ACK ACK ACK MULTIPLE BYTE WRITE MASTER START SLAVE ADDRESS WRITE REGISTER ADDRESS DATA DATA STOP SLAVE ACK ACK ACK ACK SINGLE BYTE READ MASTER START SLAVE ADDRESS WRITE REGISTER ADDRESS START SLAVE ADDRESS READ NACK STOP SLAVE DATA MULTIPLE BYTE READ MASTER START SLAVE ADDRESS WRITE REGISTER ADDRESS START SLAVE ADDRESS READ ACK STOP SLAVE ACK ACK DATA DATA NOTES 1 THIS START IS EITHER A RESTART OR A STOP FOLLOWED BY A START 2 THE SHADED AREAS REPRESENT WHEN THE DEVICE IS LISTENING 07925 033 Figure 41 Device Addressing Rev D Page 18 of 40 Table 12 PC Timing Ta 25 C Vs 2 5 V 1 8 V Limit Parameter Min Max Unit Description
7. 230 234 238 242 246 250 254 258 262 266 270 274 278 282 Figure 18 Z Axis Sensitivity at 25 Vs 2 5 V Full Resolution SENSITIVITY LSB g 07925 216 07925 217 07925 218 Rev Page 10 of 40 2B e a e N a E a PERCENT OF POPULATION 3 8 0 02 Figure 19 X Axis Sensitivity Temperature Coefficient Vs 2 5 V 40 e a e 0 01 0 0 01 SENSITIVITY TEMPERATURE COEFFICIENT C 0 02 N a E o PERCENT OF POPULATION 0 02 Figure 20 Y Axis Sensitivity Temperature Coefficient Vs 2 5 V 40 0 01 0 0 01 SENSITIVITY TEMPERATURE COEFFICIENT 0 02 e a e N a E a o PERCENT OF POPULATION 0 02 0 01 0 0 01 SENSITIVITY TEMPERATURE COEFFICIENT 0 02 07925 219 07925 220 07925 221 Figure 21 Z Axis Sensitivity Temperature Coefficient Vs 2 5 V SENSITIVITY LSB g SENSITIVITY LSB g SENSITIVITY LSB g 280 275 270 265 260 255 250 245 240 235 230 40 20 0 20 40 60 80 100 120 280 275 270 265 260
8. correcionPI_Acc h Variables utilizadas en correcionPI_Acc c 11 06 2014 Eugenio Alcal Baselga Hinclude cosme h include giroscopo h include ficheroprueba h define ID_correcionPI_Acc correcionPI_Acc Hdefine MAX correcionPI Acc 16 struct correcionPI Acc char nombre MAX LONG NOMBRE int orden byte habilitado byte finalizado int t ciclo RT int t ciclo RT min int t ciclo max int t ciclo noRT int t ciclo noRT min int t ciclo noRT max variables float Kp ROLLPITCH En adelante estas dos constantes meterlas en variables para asi poder modificarlas en tiempo real float Ki ROLLPITCH float Kd ROLLPITCH float Omega P MAX EJES float Omega IIMAX EJES float derivative MAX EJES float errorRollPitch MAX EJES float errorRollPitch old MAX EJES float Scaled Omega EJES entradas float Facc MAX EJES float Wgyr MAX EJES float dcm_matriz_renorm_1 MAX_EJES MAX_EJES int calibracion giro salidas float Wgyr EJES correcionPl Acc c correcionPI Acc c Calcula el error entre el vector de aceleraciones y el vector de los datos corregidos en el ciclo anterior este error se utiliza en un PID 11 06 2014 Eugenio Alcal Baselga ftinclude lt stdio h gt include lt string h gt include lt math h gt include runtime h include correcionPI_Acc h
9. 900 25 1250 1200 F 20 1150 2 5 1100 gt 15 E 1050 E 9 z 1000 u O 10 a 950 E tc 850 a 800 0 750 20 15 10 05 0 05 10 15 205 460 40 20 0 20 40 60 80 100 5 ZERO OFFSET TEMPERATURE COEFFICIENT mg C TEMPERATURE 8 Figure 12 Z Axis Zero g Offset Temperature Coefficient Vs 2 5 V Figure 15 Z Axis One g Offset vs Temperature 45 Parts Soldered to PCB Vs 2 5 V Rev D Page 9 of 40 ADXL345 PERCENT OF POPULATION PERCENT OF POPULATION PERCENT OF POPULATION 55 50 45 40 35 30 25 20 15 10 5 0 Fig 55 50 45 40 35 30 25 20 15 10 5 0 230 234 238 242 246 250 254 258 262 266 270 274 278 282 SENSITIVITY LSB g ure 16 X Axis Sensitivity at 25 Vs 2 5 V Full Resolution 230 234 238 242 246 250 254 258 262 266 270 274 278 282 Fig 55 50 45 40 35 30 25 20 15 10 5 0 SENSITIVITY LSB g ure 17 Y Axis Sensitivity at 25 Vs 2 5 V Full Resolution i
10. Figure 37 SPI 4 Wire Write 07925 017 SCLK HOLD serup a gt ia gt i SDI i itsno ADDRESS BITS C lt J H DATA Figure 38 SPI 4 Wire Read TQUIET e e tos Dis SDIO X DO ADDRESS BITS DATA BITS SDO NOTES 1 tspo IS ONLY PRESENT DURING READS 07925 019 Figure 39 SPI 3 Wire Read Write Rev D Page 16 of 40 Table 9 SPI Digital Input Output ADXL345 Limit Parameter Test Conditions Min Max Unit Digital Input Low Level Input Voltage Vu 0 3 x Vooo V High Level Input Voltage Vin 0 7 X VoD vo V Low Level Input Current Ii Vin 0 1 uA High Level Input Current liu 0 0 1 uA Digital Output Low Level Output Voltage Voi lo 10 mA 0 2 X Vpop vo V High Level Output Voltage Vou lou 4 mA 0 8 X VoD vo V Low Level Output Current loi Vor Vol max 10 mA High Level Output Current lou min 4 mA Pin Capacitance fin 1 MHz Vin 2 5 V 8 pF Limits based on characterization results not production tested Table 10 SPI Timing Ta 25 C Vs 2 5 V 1 8 V Limit Parameter Min Max Unit Description 5 MHz SPI clock frequency tscik 200 ns 1 SPI clock frequency mark space ratio for the SCLK input is 40 60 to 60 40 5 ns CS falling edge to SCLK falling edge 5 ns SCLK rising edge to CS rising edge tois 10 ns CS rising edge to SDO disable
11. Table 10 Mode Register Location Name Description MR7 to Set this pin to enable High Speed I2C 3400kHz HS MR2 MR1 to MD1 to Mode Select Bits These bits select the operation mode of MRO MDO this device Table 11 Mode Register Bit Designations MD1 MDO Operating Mode Continuous Measurement Mode In continuous measurement mode the device continuously performs measurements and places the result in the data register RDY goes high when new data is placed 0 0 in all three registers After a power on or a write to the mode or configuration register the first measurement set is available from all three data output registers after a period of 2 fpo and subsequent measurements are available at a frequency of fpo where fpo is the frequency of data output Single Measurement Mode Default When single measurement mode is selected device performs a single measurement sets RDY 0 1 high and returned to idle mode Mode register returns to idle mode bit values The measurement remains in the data output register and RDY remains high until the data output register is read or another measurement is performed 1 0 Idle Mode Device is placed in idle mode 1 1 Idle Mode Device is placed in idle mode Table 12 Operating Modes 14 www honeywell com HMC5883L Data Output X Registers A and B The data output X registers are two 8 bit registers data output register A and
12. HMC5883 Land Pad Pattern All dmensios are mm LAYOUT CONSIDERATIONS Besides keeping all components that may contain ferrous materials nickel etc away from the sensor on both sides of the PCB it is also recommended that there is no conducting copper under near the sensor in any of the PCB layers See recommended layout below Notice that the one trace under the sensor in the dual supply mode is not expected to carry active current since it is for pin 4 pull up to VDDIO Power and ground planes are removed under the sensor to minimize possible source of magnetic noise For best results use non ferrous materials for all exposed copper coding LI 0 22uf HMC5883L Dual Supply www honeywell com C3 B Luf UDD UDDIO HMC5883L _ Sinale Supply HMC5883L PCB Pad Definition and Traces The HMC5883L is a fine pitch LCC package Refer to previous figure for recommended PCB footprint for proper package centering Size the traces between the HMC5883L and the external capacitors C1 and C2 to handle the 1 ampere peak current pulses with low voltage drop on the traces Stencil Design and Solder Paste A 4 mil stencil and 10096 paste coverage is recommended for the electrical contact pads Reflow Assembly This device is classified as MSL 3 with 260 C peak reflow temperature A baking process 125 C 24 hrs is required if device is not kept continuously in a dry 1096 RH environment before assembly
13. k k k k kK K k void funcionNormalNoRT IN void funcion_normal_noRT_conversor_angulos void instancia int t ciclo f struct conversor angulos este struct conversor angulos instancia ifdef LOG sprintf msgLog Normal function 6s este gt nombre logPrint msgLog 6 endif struct timespec ts crononsec 1 amp ts principio c digo espec fico funcion normal noRT conversor angulos fin c digo espec fico funcion normal noRT conversor angulos este 5t ciclo noRT 0 amp ts if este t ciclo noRT gt gt ciclo noRT max gt ciclo noRT max este 5t ciclo noRT else if este gt t_ciclo_noRT lt este gt t_ciclo_noRT_min este gt t_ciclo_noRT_min este gt t_ciclo_noRT k k k k K K k void funcionFinaliza EEEE 2 o lt k k k k k k k k K k k KK K void funcion_finaliza_conversor_angulos void instancia struct conversor_angulos este struct conversor_angulos instancia ifdef LOG sprintf msgLog Finalizing 96s este gt nombre logPrint msgLog 3 endif principio c digo espec fico funcion finaliza conversor_angulos fin c digo espec fico funcion finaliza conversor angulos j k k k k k KK k void inicilizaconversor_angulos II int inicializa_conversor_angulos Hifdef LOG sprintf msgLog Initializing s ID
14. sse 20 Changes to Self Test Section and Table 15 to Table 18 21 Added Figures 42 and Table 14 sse 21 Changes to Table iii 22 Changes to Register OxX1D THRESH Read Write Section Register Ox1E Register Ox1E Register 0x20 OFSX OFSY OSXZ Read Write Section Register 0x21 DUR Read Write Section Register 0x22 Latent Read Write Section and Register 0x23 Window Read Write Section 23 Changes to X Enable Bits and INACT X Enable Bit Section Register 0x28 THRESH FF Read Write Section Register 0x29 TIME FF Read Write Section Asleep Bit Section and AUTO SLEEP Bit 24 Changes to Sleep Bit Section Changes to Power Supply Decoupling Section Mechanical Considerations for Mounting Section and Tap Detection SECON 22s 27 Changes to Threshold Section 28 Changes to Sleep Mode vs Low Power Mode Section 29 Added Offset Calibration Section sss 29 Changes to Using Self Test Section sss 30 Added Data Formatting of Upper Data Rates Section Figure 48 and Figur 49 iu 31 Added Noise Performance Section Figure 50 to Figure 52 and Operation at Voltages Other Than 2 5 V 32 Added Offset Performance at Lowest Data Rat
15. sss 31 Changes to Axes of Acceleration Sensitivity Section 35 11 10 Rev A to Rev B Change to 0 g Offset vs Temperature for Z Axis Parameter Table Lian ias Changes to Figure 10 to Figure 15 Changes to Ordering 0 22 00 0 4 10 Rev 0 to Rev A Changes to Features Section and General 1 Changes to Specifications 3 Changes to Table 2 and Table 3 sss 5 Added Package Information Section Figure 2 and Table 4 Renumbered Sequentially 5 Changes to Pin 12 Description Table 5 6 Added Typical Performance Characteristics Section 7 Changes to Theory of Operation Section and Power Sequencing SECOND 12 Changes to Powers Savings Section Table 7 Table 8 Auto Sleep Mode Section and Standby Mode Section 13 Changes to SPI Section serene 14 Changes to Figure 36 to Figure 38 sse 15 Changes to Table 9 and Table 10 sss 16 Changes to Section and Table 11 sss 17 ADXL345 Changes to Table t ERROR 18 Changes to Interrupts Section Activity Section Inactivity Section and FREE FALL Section eee 19 Added Table 13 e ineo RU ene 19 Changes to FIFO Section
16. 6 Tap Detection us caet eer t ehe e denis 28 Thermal Resistance T 6 29 Package Information cc 6 Link Modernas 29 6 i Pin Configuration and Function Descriptions 7 Offset Calibrations e rS 30 Typical Performance Characteristics 8 Using Self Test irc o RICE RR een 31 Theory of Operations cient ihe eed ede tits 13 Data Formatting of Upper Data Rates 22 Power Sequencing 13 Noise Power SAVINGS esee rete ttt iria idad 14 Operationat Voltages Other 25 33 Serial Communications eese 15 Offset Performance at Lowest Data Rates 34 DID 15 Axes of Acceleration Sensitivity di oM 18 Layout and Design Recomm nda tons ic sis eae 39 Irsa sae eet 20 Outline Dimensions 37 e R 21 37 Rev D Page 2 of 40 REVISION HISTORY 2 13 Rev C to Rev D Changes to Figure 13 Figure 14 and Figure 15 9 Change to Table 15 5 11 Rev B to Rev C Added Preventing Bus Traffic Errors Section 15 Changes to Figure 37 Figure 38 Figure 39 16 Ghanges to Table 12 ina 19 Changes to Using Self Test Section
17. Componente el que se definen y se varian las referencias de los angulos pitch y roll 11 06 2014 Eugenio Alcal Baselga ftinclude stdio h include lt string h gt include lt math h gt include runtime h include referencias h ifdef ID_LISTAS struct lista instancias_referencias else define MAX_referencias 16 struct referencias instancias referencias MAX referencias endif struct componente clase_referencias extern char msgLog 46 gt e gt lt o a k e ls ds ls ls ls ls void inicializa_propiedades IO void inicializa propiedades referencias void instancia char nombre int orden unsigned char habilitado struct referencias este struct referencias instancia strcpy este gt nombre nombre este gt orden orden este gt habilitado habilitado este gt finalizado 0 principio inicializaci n de propiedades espec ficas referencias fin inicializaci n de propiedades espec ficas referencias polo ol o ol o k k os os os ls ls ls ds ls ls ls k le k k k k k k k K k gt e void registra_propiedades IO registra propiedades referencias void instancia struct referencias este struct referencias instancia char saux MAX_LONG_NOMBRE insertarNombre2 este gt nombre este emStrcpy saux ID SISTEMA ID referencias NO MODIFICABLE insertarPropiedad3 este gt nombre amp e
18. inverted LED current formulas andLED required formulas and LED required limiting R output state output state values values apply inverted LED current formulas andLED not required formulas and LED limiting R output state output state values required values inverted apply 1 When OE 1 LED output state is controlled only by OUTNE 1 0 bits MODE2 register 2 Correct configuration when LEDs directly connected to the LEDn outputs connection to Vpp through current limiting resistor 3 Optimum configuration when external N type NPN NMOS driver used 4 Optimum configuration when external P type PNP PMOS driver used 002aad169 INVRT 0 OUTDRV 1 Fig 13 External N type driver 002aad170 INVRT 1 OUTDRV 1 Fig 14 External P type driver A 4 LEDO Vpp 002aad171 INVRT 1 OUTDRV 0 Fig 15 Direct LED connection PCA9685 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Product data sheet Rev 3 2 September 2010 28 of 51 Semiconductors 9685 16 channel 12 bit PWM 2 LED controller 8 Characteristics of the I2C bus PCA9685 8 1 8 2 The I C bus is for 2 way 2 line communication between different ICs or modules The two lines are a serial data line SDA and a serial clock line
19. LED controller decimal hex 62 63 64 65 66 67 68 69 250 251 252 253 254 Register summary continued Register Register D7 D6 D5 D4 D3 D2 D1 DO 3E 00 1 1 1 1 0 1 014 3F 0 0 1 1 1 1 1 LED14 ON H 40 0 1 0 0 0 0 0 1 014 OFFL 41 0 1 0 0 0 0 1 LED14 OFF H 42 0 1 0 0 0 1 O LED15 ONL 43 0 1 0 0 0 1 1 LED15 ON H 44 0 1 0 0 1 0 0 LED15 OFFL 45 0 1 0 0 1 0 1 1 015 OFF H reserved for future use FA 1 1 1 1 0 1 0 ALLLED ONL FB 1 1 1 1 0 1 1 ALL LED ONH FC 1 1 1 1 1 0 ALLLED OFFL FD 1 1 1 1 1 0 1 ALL LED OFF H FE 1 1 1 1 1 1 0 SCALEl FF 1 1 4 1 1 1 1 TestModel2l 255 Type read write read write read write read write read write read write read write read write write read zero write read zero write read zero write read zero read write read write Function LED14 output and brightness control byte 0 LED14 output and brightness control byte 1 LED14 output and brightness control byte 2 LED14 output and brightness control byte 3 LED15 output and brightness control byte 0 LED15 output and brightness control byte 1 LED15 output and brightness control byte 2 LED15 output and brightness control byte 3 load all the LEDn ON registers byte 0 load all the LEDn ON registers byte 1 load all the LEDn OFF registers byte 0 load all the LEDn OFF registers byte 1 prescaler for output frequency defines the t
20. System configuration Acknowledge Bus transactions Application design in information Limiting Static characteristicS Dynamic characteristics Test Package Handling information Soldering of SMD packages 24 25 25 26 26 27 28 29 29 29 29 30 31 37 37 39 42 43 45 45 17 1 17 2 17 3 17 4 18 19 20 20 1 20 2 20 3 20 4 21 22 Introduction to soldering 45 Wave and reflow soldering 45 Wave soldering 45 Reflow soldering 46 Abbreviations 47 Revision history 48 Legal information 49 Data sheet 49 Definitions 49 Disclaimers 49 Trademarks 50 Contact information 50 Contents 2 53 6 tenes caw eee RR 51 Please be aware that important notices concerning this document and the product s described herein have been included in section Legal information NXP B V 2010 All rights reserved For more information please visit http Awww nxp com For sales office addresses please send an e
21. Variables utilizadas magnetometro c Eugenio Alcal Baselga Hinclude cosme h define ID_magnetometro magnetometro define MAX magnetometro 16 define HMC5883L ADDR Oxle define MAX MSG 100 define EJES 3 define HMC5883L READ ADDR 0x3D define HMC5883L WRITE ADDR 0x3C define Config Reg A 0x00 define Config Reg B 0x01 define Mode Reg 0x02 define X MSB Reg 0x03 define X LSB Reg 0x04 define Z MSB Reg 0x05 define Z LSB Reg 0x06 define Y MSB Reg 0x07 define Y 5 Reg 0x08 define Status Reg 0x09 define ID Reg A Ox0A define ID Reg B Ox0B define ID Reg C 0x0C define RADIANES GRADOS 57 29577951 define GRADOS RADIANES 0 017453293 define pi 3 141592654 define hmc5883 calib x 91 define hmc5883 calib y 128 Hdefine hmc5883 calib z 163 struct magnetometro char nombre MAX LONG NOMBRE int orden byte habilitado byte finalizado int t ciclo RT int t ciclo RT min int t ciclo max int t ciclo noRT int t ciclo noRT min int t ciclo noRT max variables de Calibracion char error msg mag MAX MSG short 2 unsigned char buf 8 float minx miny minz maxx maxy maxz float xScale yScale zScale float compassXoffset compassYoffset compassZoffset float offsetRoll offsetPitch offsetYaw entradas int bus ok fd salidas float Vmag 3 Vector datos magnetometro magnetometro c magnetometro c 11 06
22. gt ciclo noRT min 0x10000000 gt ciclo noRT max 0 principio c digo espec fico funcion inicializa renormalizar este gt error 0 este gt renorm 0 fin c digo espec fico funcion inicializa renormalizar 46 gt e gt lt H lt ol o o k os k k k ls ls ds ls ls ds ls le le le k k k k k k k kk k kK k k K K k K K K void funcionNormal IO void funcion normal renormalizar void instancia int t ciclo 1 struct renormalizar este struct renormalizar instancia ifdef LOG sprintf msgLog Normal function 96s este gt nombre logPrint msgLog 6 endif struct timespec ts crononsec 1 amp ts principio c digo espec fico funcion normal renormalizar int float acumul 0 for c 0 c lt MAX 5 c acumul acumul este gt DCM_Matriz 0 c este gt DCM_Matriz 1 c este gt error acumul 5 for c 0 c lt MAX EBJES c este gt dcm_matriz_1 0 c este gt DCM_Matriz 1 c este gt error este gt dcm_matriz_1 1 c este gt DCM_Matriz 0 c este gt error for c 0 c lt MAX 5 c este dcm matriz 1 0 c este dcm matriz 1 0 c este gt Matriz 0 c este gt dcm_matriz_1 1 c este dcm matriz 1 1 c este gt DCM_Matriz 1 c este gt dcm_matriz_1 2 0 este gt dcm_matriz_1 0 1 este gt dcm_matriz_1 1 2 este gt dcm_matriz
23. k k K k k K K K void funcionCrea k k k k k k k k f lt k k k int funcion_crea_cambio_magnitud void instancia char nombre int orden unsigned char habilitado struct cambio_magnitud este struct cambio_magnitud instancia ifdef LOG sprintf msgLog Creating s nombre logPrint msgLog 3 endif inicializa_propiedades_cambio_magnitud instancia nombre orden habilitado if registra propiedades cambio magnitud instancia 0 ifdef LOG sprintf msgLog 46s V Registering properties of s ID ERROR este gt nombre logPrint msgLog 1 endif if registrarInstancia instancia nombre amp clase_cambio_magnitud orden amp este gt habilitado amp este gt finalizado 0 ifdef LOG sprintf msgLog s V Registering instance s ID ERROR este gt nombre logPrint msgLog 1 endif void funcionInicializa IO void funcion_inicializa_cambio_magnitud void instancia struct cambio magnitud este struct cambio magnitud instancia fifdef LOG sprintf msgLog Initializing s este gt nombre logPrint msgLog 3 endif este gt t_ciclo_RT_min 0x 10000000 este 5t ciclo RT max 0 gt ciclo noRT min 0x10000000 gt ciclo noRT max 0 principio c digo espec fico funcion inicializa cambio magnitud este pwm motor grisl 0 este pwm motor gris2 0 este
24. 3200 1600 1111 140 1600 800 1110 90 800 400 1101 140 400 200 1100 140 200 100 1011 140 100 50 1010 140 50 25 1001 90 25 12 5 1000 60 12 5 6 25 0111 50 6 25 3 13 0110 45 3 13 1 56 0101 40 1 56 0 78 0100 34 0 78 0 39 0011 23 0 39 0 20 0010 23 0 20 0 10 0001 23 0 10 0 05 0000 23 Output Data Rate Hz Bandwidth Hz Rate Code Ipo 400 200 1100 90 200 100 1011 60 100 50 1010 50 50 25 1001 45 25 12 5 1000 40 12 5 6 25 0111 34 Auto Sleep Mode Additional power can be saved if the ADXL345 automatically switches to sleep mode during periods of inactivity To enable this feature set the INACT register Address 0x25 and the TIME INACT register Address 0x26 each to a value that signifies inactivity the appropriate value depends on the application and then set the AUTO SLEEP bit Bit D4 and the link bit Bit D5 in the POWER register Address 0x2D Current consumption at the sub 12 5 Hz data rates that are used in this mode is typically 23 uA for a Vs of 2 5 V Standby Mode For even lower power operation standby mode can be used In standby mode current consumption is reduced to 0 1 uA typical In this mode no measurements are made Standby mode is entered by clearing the measure bit Bit D3 in the POWER register Address 0x2D Placing the device into standby mode preserves the contents of FIFO Rev D Page 14 of 40 SERIAL COMMUNICATIONS PC and SPI digital
25. Product data sheet Rev 3 2 September 2010 31 of 51 Semiconductors 9685 16 channel 12 bit PWM 2 LED controller slave address control register 1 register register EXER E d Ed d E E EA A ER eee NE t START condition R W acknowledge acknowledge AI bit set acknowledge from slave from slave from slave slave address data from MODE1 data from MODE2 tt ReSTART R W acknowledge acknowledge condition from slave from master cont acknowledge from master data from LED15_OFF_H register not acknowledge STOP from master condition 002aad188 Fig 22 Read all registers using the Auto Increment feature Al initially clear control register slave address ALL LED ON L register ALL LED ON L register ALL LED register EDS E MEME t START condition R W acknowledge acknowledge acknowledge acknowledge from slave from slave from slave from slave ALL_LED_OFF_L register ALL_LED_OFF_H register la s pup ME eee acknowledge acknowledge STOP condition from slave from slave 002aad189 Fig 23 Write to ALL LED ON and ALL LED OFF registers using the Auto Increment feature Al initially set control register slave address ALL LED OFF H register A ALL_LED_OFF_H register eo Se B t t START condition R W acknowledge acknowledge ack
26. address of 0x53 followed by the R W bit can be chosen by grounding the ALT ADDRESS pin Pin 12 This translates to 0xA6 for a write and 0xA7 for a read There are no internal pull up or pull down resistors for any unused pins therefore there is no known state or default state for the CS or ALT ADDRESS pin if left floating or unconnected It is required that the pin be connected to and that the ALT ADDRESS pin be connected to either or GND when using Table 11 PC Digital Input Output Due to communication speed limitations the maximum output data rate when using 400 kHz is 800 Hz and scales linearly with a change in the PC communication speed For example using at 100 kHz would limit the maximum ODR to 200 Hz Operation at an output data rate above the recommended maxi mum may result in undesirable effect on the acceleration data including missing samples or additional noise Vop yo 07925 008 Figure 40 PC Connection Diagram Address 0x53 If other devices are connected to the same bus the nominal operating voltage level of these other devices cannot exceed Vppyo by more than 0 3 V External pull up resistors Rp are necessary for proper I C operation Refer to the UM10204 Specification and User Manual Rev 03 19 June 2007 when selecting pull up resistor values to ensure proper operation
27. tei 76 referencias Dou pilla 82 A ds E er etus 82 DINI A PE 88 pid piteh Cursi A EI E ORE ESR 89 PA 96 ee 97 cambio maondo aed ose II ea 104 cambio O Fog TE 104 MICtOPWM ON 112 iitec ufi 113 CONEXIONES DE LOS COMPONENTES 121 MAKBEPILE 505 odi aged 144 2 12c h 11 06 2014 Variables utilizadas en i2c c Eugenio Alcal Baselga include cosme h include runtime h define ID 12 12c define MAX_i2c 16 struct i2c char nombre MAX_LONG_NOMBRE int orden byte habilitado byte finalizado int t_ciclo int t_ciclo_min int t_ciclo_max variables entradas salidas int bus_ok int fd i2c c 12 Abre el bus I2C 11 06 2014 Eugenio Alcal Baselga Xe EA 3 include lt stdio h gt include lt string h gt include lt math h gt ftinclude lt time h gt include lt stdlib h gt include lt fentl h gt include lt unistd h gt include lt sys ioctl h gt include lt sys types h gt include lt sys stat h gt include lt linux i2c dev h gt include runtime h include i2c h ifdef ID_LISTAS struct lista instancias_i2c else define MAX_1
28. 17 3 10 CHARGE PUMP 17 6 DIGITAL INTERFACE 18 61 PC SERIAL Nan i a 0 0 6 nana 18 T 5 0 E 22 8 REGISTER DESCRIPTION scsssscsscssssccsssssccosesssscssscssssossccoscovssssaseaassessstessvesssssisccnscossectsceseessisvseocssecssssedcecssseisceossees 23 8 1 REGISTER Q 23 8 2 REGISTER 21 SAMPLE RATE 4 4 23 8 3 REGISTER 22 DLPF FULL SCALE 24 8 4 REGISTER 23 INTERRUPT 2 26 8 5 REGISTER 26 INTERRUPT STATUS cccccccccseseeeseseseeeseseceseseseseeeceseseseceeeseseseseeeseceeeseeesesesetesesesereceseseseseeeseeeeerens 26 8 6 REGISTERS 27 TO 34 SENSOR REGISTERS ccce eene nennen nn nn r EEr eene nene nene nennen 27 8 7 REGISTER 62 POWER 27 9 ASSEMBLY 29 9 1 ORIENTATION 2 2 1 8 0 ds ts eed dede doeet uda nest doctus 29 9 2 PACKAGE DIMENSION G 0ssscecesesesese
29. E A N o 2 0 150 100 50 0 50 100 ZERO 0 OFFSET mg Figure 9 Z Axis Zero Offset at 25 Vs 3 3 V 150 07925 207 07925 208 07925 209 ADXL345 150 100 100 PERCENT OF POPULATION mb N N a o a o a OUTPUT mg M a 0 20 15 1 0 05 0 0 5 1 0 15 2 0 ZERO g OFFSET TEMPERATURE COEFFICIENT mg C 60 40 20 0 20 40 60 80 100 TEMPERATURE 07925 210 07925 213 Figure 10 X Axis Zero Offset Temperature Coefficient Vs 2 5 V Figure 13 X Axis Zero g Offset vs Temperature 45 Parts Soldered to PCB Vs 2 5 V 30 150 100 100 PERCENT OF POPULATION a o a o a OUTPUT mg h a o e 150 60 40 20 0 20 40 60 80 100 TEMPERATURE 0 20 15 10 05 0 0 5 1 0 1 5 2 0 ZERO g OFFSET TEMPERATURE COEFFICIENT mg C 07925 211 07925 214 Figure 11 Y Axis Zero g Offset Temperature Coefficient Vs 2 5 V Figure 14 Y Axis Zero g Offset vs Temperature 45 Parts Soldered to PCB Vs 2 5 V
30. This value is calculated as te max tio tsmin SDA SCL START REPEATED STOP CONDITION START CONDITION CONDITION 07925 034 Figure 42 PC Timing Diagram Rev D Page 19 of 40 ADXL345 INTERRUPTS The ADXL345 provides two output pins for driving interrupts INT1 and INT2 Both interrupt pins are push pull low impedance pins with output specifications shown in Table 13 The default configuration of the interrupt pins is active high This can be changed to active low by setting the INT INVERT bit in the DATA FORMAT Address 0x31 register functions can be used simultaneously with the only limiting feature being that some functions may need to share interrupt pins Interrupts are enabled by setting the appropriate bit in the INT ENABLE register Address Ox2E and are mapped to either the INTI pin or the INT2 pin based on the contents of the INT MAP register Address Ox2F When initially configuring the interrupt pins it is recommended that the functions and interrupt mapping be done before enabling the interrupts When changing the configuration of an interrupt it is recommended that the interrupt be disabled first by clearing the bit corresponding to that function in the INT ENABLE register and then the function be reconfigured before enabling the interrupt again Configuration of the functions while the interrupts are disabled helps to prevent the accidental generation of an interrupt be
31. 9685 also has a built in oscillator for the PWM control However the frequency used for PWM control in the PCA9685 is adjustable from about 40 Hz to 1000 Hz as compared to the typical 97 6 kHz frequency of the PCA9635 This allows the use of PCA9685 with external power supply controllers All bits are set at the same frequency The Power On Reset POR default state of LEDn output pins is LOW in the case of PCA9685 It is HIGH for PCA9635 Semiconductors 9685 16 channel 12 bit PWM 2 LED controller The active LOW Output Enable input pin OE allows asynchronous control of the LED outputs and can be used to set all the outputs to a defined 2 programmable logic state The OE can also be used to externally pulse width modulate the outputs which is useful when multiple devices need to be dimmed or blinked together using software control Software programmable LED All Call and three Sub Call I12C bus addresses allow all or defined groups of PCA9685 devices to respond to a common I C bus address allowing for example all red LEDs to be turned on or off at the same time or marquee chasing effect thus minimizing IZC bus commands Six hardware address pins allow up to 62 devices on the same bus The Software Reset SWRST General Call allows the master to perform a reset of the 9685 through the I C bus identical to the Power On Reset POR that initializes the registers to their defa
32. Based on characterization of 30 pieces over temperature on evaluation board or in socket Based on design through modeling and simulation across PVT Typical Randomly selected part measured at room temperature on evaluation board or in socket Based on characterization of 5 pieces over temperature 10 of 39 InvenSens ITG 3200 Product Specification Document Number PS ITG 3200A 00 01 4 Revision 1 4 Release Date 03 30 2010 3 5 Timing Characterization Typical Operating Circuit of Section 4 2 VDD 2 5V VLOGIC 1 8V 5 2 5V45 3 0V 5 or 3 3V 5 Ta 25 C Parameters TIMING SCL Clock Frequency tup sta Repeated START Condition Hold Time tLow SCL Low Period SCL High Period tsusrA Repeated START Condition Setup Time tup pat SDA Data Hold Time tsupat SDA Data Setup Time SDA and SCL Rise Time tr SDA and SCL Fall Time tsusto STOP Condition Setup Time teur Bus Free Time Between STOP and START Condition C Capacitive Load for each Bus Line tvpDAT Data Valid Time tvp Ack Data Valid Acknowledge Time Notes Conditions FAST MODE 1 3 0 6 0 6 0 100 20 0 1Cb 20 0 1Cb 0 6 Cb bus cap from 10 to 400pF Cb bus cap from 10 to 400pF 1 3 1 Based on characterization of 5 pieces over temperature on evaluation board or in socket 2 Guaranteed by design SDA SCL 1st clock cycle SDA tsu sTA SCL tr tSU DAT
33. amp fdummy este gt dcm_matriz_renorm_1 1 1 amp fdummy este gt dcm_matriz_renorm_1 1 2 amp fdummy este gt dcm_matriz_renorm_1 2 0 amp fdummy este gt dcm_matriz_renorm_1 2 1 amp fdummy 121 este gt dcm_matriz_renorm_1 2 amp fdummy este gt Vmag 0 amp fdummy este gt Vmag 1 amp fdummy este gt Vmag 2 amp fdummy este gt W gyr_modif_prom 0 amp fdummy este gt W gyr_modif_prom 1 amp fdummy este gt W gyr_modif_prom 2 amp fdummy fin inicializaci n de propiedades espec ficas correccionPL_ Mag k k k k k k k k k k k k k k k k k kk k k kk k k K k k K K k void registra_propiedades k k k k k 2 k 2 kk k k k K f lt K K gt lt K K int registra_propiedades_correccionPI_Mag void instancia struct correccionPI_Mag este struct correccionPI_Mag instancia char saux MAX_LONG_NOMBRE int Z i j insertarNombre2 este gt nombre este emStrcpy saux ID SISTEMA ID correccionPI Mag NO MODIFICABLEB insertarPropiedad3 este gt nombre amp este gt nombre ID VAR TEXT PUBLICO nombre insertarPropiedad3 este gt nombre amp este gt orden ID VAR INT PUBLICO MODIFICABLE orden insertarPropiedad3 este gt nombre amp este gt habilitado ID VAR BYTE PUBLICO MODIFICABLE habilitado insertarPropiedad3 este gt nombre amp este gt finalizado ID VAR BYTE PUBLICO MODIFICABLE finalizado
34. output capacitance 5 8 pF PCA9685 All information provided in this document is subject to legal disclaimers B V 2010 All rights reserved Product data sheet Rev 3 2 September 2010 37 of 51 NXP Semiconductors PCA9685 16 channel 12 bit PWM 2 LED controller Table 13 Static characteristics continued Vpp 2 3 V to 5 5 V Vss 0 V Tamp 40 C to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Address inputs OE input EXTCLK VIL LOW level input voltage 0 5 0 3Vpp V HIGH level input voltage 0 7Vpp 5 5 V lii input leakage current 1 1 Ci input capacitance 3 5 pF 1 Vpp must be lowered to 0 2 V in order to reset part 2 Each bit must be limited to a maximum of 25 mA and the total package limited to 400 mA due to internal busing limits 10 002aad877 60 002aad878 Ipp mA lot 8 mA Vpp 4 5 V Vpp 5 5V 20 3 0V 23V 4 3 3V 20 2 23V 0 0 50 0 50 100 50 0 50 100 Tamb Tamb C Fig 28 Ipp typical values with OSC on and Fig 29 lo typical drive LEDn outputs versus 1 MHz versus temperature temperature 5 002aad879 Ist uA 4 3 Vpp 5 5 V 2 DLL 33V cpm O S 23V 0 50 0 50 100 Tamb Fig 30 Standby supp
35. sequence name connection type connection connection input correccionPI Magl dcm matriz renorm 1 0 1 input input resending input type ID ENT FLOAT input type input dimensions output resending output renormalizarl dcm matriz renorm 1 0 1 output sequence name connection type connection connection input correccionPI Magl dcm matriz renorm 1 0 2 input input resending input type ID ENT FLOAT input type input dimensions output resending output renormalizarl dcm matriz renorm 1 0 2 output sequence name connection type connection connection input correccionPI Magl dcm matriz renorm 1 1 0 input input resending input type ID ENT FLOAT input type input dimensions output resending lt output gt renormalizar1 dcm_matriz_renorm_1 1 0 lt output gt lt sequence_name gt lt connection_type gt lt connection gt lt connection gt lt input gt correccionPI_Magl dem_matriz_renorm_1 1 1 lt input gt lt input_resending gt input type ID ENT FLOAT input type input dimensions output resending output renormalizarl dcm matriz renorm 1 1 1 output sequence name connection type lt connection gt lt connection gt lt input gt correccionPI_Mag1 dcm_matriz_renorm_1 1 2 lt input gt lt input_resending gt lt input_type gt ID
36. 9685 All information provided this document is subject to legal disclaimers B V 2010 All rights reserved Product data sheet Rev 3 2 September 2010 4 of 51 NXP Semiconductors PCA9685 6 Pinning information 16 channel 12 bit PWM 2 LED controller PCA9685 6 1 Pinning AO A1 A2 A3 A4 LEDO LED1 LED2 LED3 LED4 LEDS LED6 LED7 Vss Fig 2 PCA9685PW PCA9685PW Q900 002 825 Pin configuration for 55 28 Vop d terminal 1 8 5 E SCL index area Sh gt D 0 r co AS A3 A5 OE m OE HEDIS LEDO LED15 LEDI LED1 PCA9685BS LED14 FED 12 LED2 LED13 LED3 6 LED12 LED11 LEDIA LED10 s LED9 O N 8 8 2 LEDS 9 gt 002 236 jan cm Transparent top view Fig 3 Pin configuration for HVQFN28 6 2 Pin description Table 2 Pin description Symbol Pin Type Description TSSOP28 HVQFN28 0 1 26 address input 0 1 2 27 address input 1 A2 3 28 address input 2 A3 4 1 address input 3 4 5 2 address input 4 LEDO 6 3 O LED driver 0 LED1 7 4 LED driver 1 LED2 8 5 O LED driver 2 LED3 9 6 O LED driver 3 LED4 10 7 O LED driver 4 LED5 11 8 LED driver 5 LED6 12 9 LED driver 6 LED7 13 10 LED driver 7 Vss 14 11 power supply supply ground LED8 15 12 LED driver 8 LE
37. insertarPropiedad3 este gt nombre gt ciclo RT ID VAR INT PUBLICO MODIFICABLE t ciclo RT insertarPropiedad3 este gt nombre gt ciclo min ID VAR INT PUBLICO MODIFICABLE t ciclo RT min insertarPropiedad3 este gt nombre amp gt ciclo max ID VAR INT PUBLICO MODIFICABLE t ciclo max insertarPropiedad3 este gt nombre gt ciclo noRT ID VAR INT PUBLICO MODIFICABLE t ciclo noRT insertarPropiedad3 este gt nombre amp este t ciclo min ID VAR INT PUBLICO MODIFICABLE t ciclo noRT min insertarPropiedad3 este gt nombre amp este 5t ciclo noRT max ID VAR INT PUBLICO MODIFICABLE t ciclo noRT max principio registro de propiedades espec ficas correccionPI_Mag for z 0 z lt MAX_EJES z insertarPropiedad3 este gt nombre amp este gt Wegyr_fin z ID SAL FLOAT PUBLICO MODIFICABLE Weyr_fin d z for z 0 z lt MAX_EJES z insertarPropiedad3 este gt nombre amp este Vmag z ID ENT FLOAT PUBLICO MODIFICABLE Vmag d z for z 0 z lt MAX_EJES z insertarPropiedad3 este gt nombre amp este gt W gyr_modif_prom z ID ENT FLOAT PUBLICO MODIFICABLE Weyr_modif_prom d z for z 0 z lt MAX_EJES z insertarPropiedad3 este gt nombre amp este errorYaw z ID VAR FLOAT PUBLICO MODIFICABLE errorYaw d z for i 0 i lt MAX EJES
38. void funcionNormal O void funcion normal giroscopo void instancia int t ciclo struct giroscopo este struct giroscopo instancia ifdef LOG sprintf msgLog Normal function 96s este gt nombre logPrint msgLog 6 endif struct timespec ts crononsec 1 amp ts principio c digo espec fico funcion normal giroscopo if ioctl este gt fd DC SLAVE ITG3200 DC ADDR lt 0 strcpy este error msg giro Acelerometer is not present if este gt calibracion_giro 1 if read este gt fd este gt flag 1 0 if read este gt fd este gt buf 6 6 La funcion read intenta leer 6 strcpy este gt error_msg_giro Unable to read from ITG3200 Jelsef este gt flagg 12c_smbus_read_byte_data este gt fd 0x 1a if este gt flagg 1 este gt x 12c_smbus_read_word_data este gt fd ITG3200_GYRO_XOUT_H este gt y i2c_smbus_read_word_data este gt fd ITG3200_GYRO_YOUT_H este gt z 12c_smbus_read_word_data este gt fd ITG3200_GYRO_ZOUT_H Radianes segundo este gt W gyr 0 float este gt x offsetGyro_x LSB 17 8 GRADOS_RADIANES este gt W gyr 1 float este gt y offsetGyro y LSB 17 8 GRADOS_RADIANES este gt W gyr 2 float este gt z offsetGyro_z LSB 17 8 GRADOS_RADIANES else if este gt flagg 0 strcpy este gt error_msg_giro El flagg fn vale 0 if este
39. 1 all six bytes have been read 2 the mode register is changed 3 the measurement configuration CRA is changed 4 power is reset Ready Bit Set when data is written to all six data registers Cleared when device initiates a write to the data output registers and after one or more of the data output registers SRO are written to When RDY bit is clear it shall remain cleared for a 250 us DRDY can be used as an alternative to the status register for monitoring the device for measurement data Table 17 Status Register Bit Designations www honeywell com HMC5883L Identification Register A The identification register A is used to identify the device IRAO through IRA7 indicate bit locations with denoting the bits that are in the identification register A IRA7 denotes the first bit of the data stream The number in parenthesis indicates the default value of that bit The identification value for this device is stored in this register This is a read only register Register values ASCII value H IRA7 6 5 4 2 1 IRAO 0 1 0 0 1 0 0 0 Table 18 Identification Register A Default Values Identification Register B The identification register is used to identify the device IRBO through IRB7 indicate bit locations with RB denoting the bits that in the identification register A 7 denotes the first bit of the da
40. 400kHz serial interface On chip timing generator clock frequency is accurate to 2 over full temperature range Optional external clock inputs of 32 768kHz or 19 2MHz to synchronize with system clock MEMS structure hermetically sealed and bonded at wafer level RoHS and Green compliant 6 of 39 InvenSens Document Number PS ITG 3200A 00 01 4 ITG 3200 Product Specification Revision 1 4 Release Date 03 30 2010 3 Electrical Characterist 3 1 Sensor Specifications Typical Operating Circuit of Section ics 4 2 VDD 2 5V VLOGIC 1 71V to VDD T4225 C Typical GYRO SENSITIVITY Full Scale Range Gyro ADC Word Length Sensitivity Scale Factor Sensitivity Scale Factor Tolerance Sensitivity Scale Factor Variation Over Temperature Nonlinearity Cross Axis Sensitivity GYRO ZERO RATE OUTPUT ZRO Initial ZRO Tolerance ZRO Variation Over Temperature Power Supply Sensitivity 1 10Hz Power Supply Sensitivity 10 250Hz Power Supply Sensitivity 250Hz 100kHz Linear Acceleration Sensitivity GYRO NOISE PERFORMANCE Total RMS noise Rate Noise Spectral Density 2000 5 16 Bits 14 375 LSB s Best fit straight line 25 40 C to 85 C Sine wave 100mVpp VDD 2 2V Sine wave 100mVpp VDD 2 2V Sine wave 100mVpp VDD 2 2V Static FS_SEL 3 100Hz LPF DLPFCFG 2 P s rms At 10Hz s NHz GYRO MECHANICAL FREQUENCIES X Axis Y Axis Z Axis Frequency Separation
41. 60 sec to 150 sec 240 0 5 10 sec to 30 sec 6 C sec maximum 6 minutes maximum 3 C sec maximum 150 C 200 C 60 sec to 180 sec 3 C sec maximum 217 C 60 sec to 150 sec 260 0 5 C 20 sec to 40 sec 6 C sec maximum 8 minutes maximum 1 Based on JEDEC Standard J STD 020D 1 For best results the soldering profile should be in accordance with the recommendations of the manufacturer of the solder paste used Rev D Page 36 of 40 OUTLINE DIMENSIONS 3 00 PAD A1 BSC CORNER 0 813 x 0 50 5 00 BSC TOP VIEW 1 00 978 0 95 END VIEW 0 74 a TELLE P SEATING PLANE 03 16 2010 A Figure 61 14 Terminal Land Grid Array LGA CC 14 1 Solder Terminations Finish Is Au over Ni Dimensions shown in millimeters ORDERING GUIDE Measurement Specified Package Model Range g Voltage V Temperature Range Package Description Option ADXL345BCCZ 2 4 8 16 2 5 40 85 14 Terminal Land Grid Array LGA 14 1 ADXL345BCCZ RL 2 4 8 16 2 5 40 C to 85 14 Terminal Land Grid Array LGA CC 14 1 ADXL345BCCZ RL7 2 4 8 16 2 5 40 to 85 14 Terminal Land Grid Array LGA 14 1 EVAL ADXL345Z EVAL ADXL345Z DB EVAL ADXL345Z M EVAL ADXL345Z S Evaluation Board Evaluation Board Analog Devices Inertial Sensor Evaluation System Includes ADXL345 Satellite ADXL345 Sa
42. 9685 16 channel 12 bit PWM 2 LED controller Table 6 LED ON LED OFF control registers address 06h to 45h bit description continued Legend default value Address Register Bit Symbol Access Value Description 18h LED4 OFF L 7 0 LED4 OFF 7 0 R W 0000 0000 LEDn OFF count for LED4 8 LSBs 19h LED4 OFF 7 5 reserved R 000 non writable 4 LED4 OFF H 4 R W 1 LEDA full OFF 3 0 1 04 OFF_H 3 0 R W 0000 LEDn_OFF count for LED4 4 MSBs 1Ah LED5 ON L 7 0 1 05 ON 7 0 R W 0000 0000 LEDn_ON count for LED5 8 LSBs 1Bh LED5 ON H 7 5 reserved R 000 non writable 4 LED5 ON H 4 R W 0 LED5 full ON 3 0 LED5 ON H 3 0 R W 0000 LEDn ON count for LED5 4 MSBs 1Ch LED5 OFF L 7 0 LED5_ OFF 7 0 R W 0000 0000 LEDn OFF count for LED5 8 LSBs 1Dh LED5 OFF H 7 5 reserved R 000 non writable 4 LED5_OFF_HI 4 R W 1 LED5 full OFF 3 0 LED5 OFF H 3 R W 0000 LEDn OFF count for LED5 4 MSBs 1Eh LED6 ON L 7 0 1 06 ON 17 0 R W 0000 0000 LEDn_ON count for LED6 8 LSBs 1Fh LED6_ON_H 7 5 reserved R 000 non writable 4 LED6 ON H 4 R W 0 LED6 full ON 3 0 LED6 ON H 3 0 R W 0000 LEDn ON count for LED6 4 MSBs 20h LED6_OFF_L 7 0 LED6_OFF_L 7 0 R W 0000 0000 LEDn OFF count for LED6 8 LSBs 21h LED6 OFF 7 5 reserved R 000 non writable 4 LED6_OFF_HI 4 R W 1 LED6 full OFF 3 0 LED6_OFF_H 3 0 R W 0000 LEDn OFF count for LED6 4 MSBs 22h LED7_ON_L 7 0 LED7_ON_L 7 0 R W 0000 0000 LEDn ON count for LED7
43. Access R W R R W R W R W R R W R W R W R R W R W R W R R W R W R W R R W R W R W R R W R W R W R R W R W R W R R W R W R W R R W R W Value 0000 0000 000 0 0000 0000 0000 000 1 0000 0000 0000 000 0 0000 0000 0000 000 1 0000 0000 0000 000 0 0000 0000 0000 000 1 0000 0000 0000 000 0 0000 0000 0000 000 1 0000 0000 0000 000 0 0000 All information provided in this document is subject to legal disclaimers Description LEDn ON count for LEDO 8 LSBs non writable LEDO full ON LEDn ON count for LEDO 4 MSBs LEDn OFF count for LEDO 8 LSBs non writable LEDO full OFF LEDn ON count for LED1 8 LSBs non writable LED1 full ON LEDn ON count for LED1 4 MSBs LEDn OFF count for LED1 8 LSBs non writable LED1 full OFF LEDn OFF count for LED1 4 MSBs LEDn ON count for LED2 8 LSBs non writable LED2 full ON LEDn_ON count for LED2 4 MSBs LEDn_OFF count for LED2 8 LSBs non writable LED2 full OFF LEDn_OFF count for LED2 4 MSBs LEDn_ON count for LED3 8 LSBs non writable LEDS full ON LEDn_ON count for LED3 4 MSBs LEDn_OFF count for LED3 8 LSBs non writable LEDS full OFF LEDn_OFF count for LED3 4 MSBs LEDn_ON count for LED4 8 LSBs non writable LED4 full ON LEDn_ON count for LED4 4 MSBs NXP B V 2010 All rights reserved Product data sheet Rev 3 2 September 2010 20 of 51 Semiconductors
44. InvenSense Part number ITG 3200 Lot traceability code XXXXXX XX XX YYWW X Foundry code Rev Code Year Code WW Work Week Package Vendor Code Package Marking Specification 9 4 Tape amp Reel Specification e 5 0 1 0 0 om r 8 00 2 00 05 SEE NOTE 3 1 50 MIN 0 30 05 4 00 SEE NOTE ES 1 75 4 10 4 092 0400000 10 R 0 3 MAX 5 50 05 i SEE NOTE 3 Bo Cp 5 12 0 3 Ko S NOTES SECTION A A 4 1 10 SPROCKET HOLE PITCH CUMULATIVE TOLERANCE 40 2 Bo 4 35 2 CAMBER IN COMPLIANCE WITH ETA 481 Kos 111 3 POCKET POSITION RELATIVE TO SPROCKET HOLE MEASURED TOLERANCES UNLESS VET IA xd AS TRUE POSITION DF POCKET NOT POCKET HOLE NOTED IPL 1 2 2L 1 10 IMENSTONS IN MILLIMETER Tape Dimensions 31 of 39 Document Number PS ITG 3200A 00 01 4 2 ITG 3200 P ifi 4 Revision 1 4 InvenSense Release Date 03 30 2010 w p V M 2 Reel Outline Drawing Reel Dimensions and Package Size PKG REEL mm SIZE L V 7 4 4 330 100 13 2 22 User Direction of Package Orientation Feed Cover Tape Pin 1 Reel Specifications Anti Static Carrier Tape Anti Static Terminal Tape Reel Tape and Reel Specification Quantity Per Reel 5 000 Reels per Box 1 Boxe
45. deni 4 AAA poses A V e q _ A O O gt 4 4 EUN Mmm V c qe T sisse pice pee H AAA es 1 12 22 I 4 SEMI de al pi ess d AAA 4 La OQ AAA TAN qu V rd codd rcr ur ME gt decer p poem cp FA NE CA ge il uu lo 28 VS LC A t Rl VE Re a Ol 2 4 gp 5 10 eseug 10 10 Frequency Hz 10 10 Gain and Phase vs Digital Filter Setting Showing Passband Details 25 of 39 Document Number PS ITG 3200A 00 01 4 y Z He Revision 1 4 InvenSense ITG 3200 Product Specification Rose Dare 08 50P010 8 4 Register 23 Interrupt Configuration Type Read Write Register Register A A 3 5 E A Default Hex Decimal Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bitl Bit0 Value LATCH n ITG_RDY RAW 17 23 ACTL OPEN m ANYRD_ 0 0 00h INT_EN CLEAR EN RDY_ EN Description This register configures the interrupt operation of the device The interrupt output pin INT configuration can be set the interrupt
46. gt ciclo 0x10000000 este gt t_ciclo_RT_max 0 este gt t_ciclo_noRT_min 0x10000000 este gt t_ciclo_noRT_max 0 principio c digo espec fico funcion inicializa conversor_angulos este gt primerDatoY aw 1 este gt contador 0 este gt primerYaw 0 fin c digo espec fico funcion inicializa conversor_angulos 346 gt e gt lt a A 2 2 k ol o k k k k k le ls ls ds ls ds ls ls le le void funcionNormal IN void funcion_normal_conversor_angulos void instancia int t ciclo struct conversor angulos este struct conversor angulos instancia ifdef LOG sprintf msgLog Normal function 96s este gt nombre logPrint msgLog 6 endif struct timespec ts crononsec 1 amp ts principio c digo espec fico funcion normal conversor angulos este gt contador este gt pitch asin este dcm matriz renorm 2 0 este gt roll atan2f este gt dcm_matriz_renorm 2 1 este gt dcm_matriz_renorm 2 2 este gt pitch este gt pitch RADIANES_ GRADOS este gt roll este gt roll RADIANES GRADOS fin c digo espec fico funcion normal conversor_angulos este gt t_ciclo_RT crononsec 0 amp ts if este gt t_ciclo_RT gt este gt t_ciclo_RT_max este gt t_ciclo_RT_max este gt t_ciclo_RT else if este gt t_ciclo_RT lt este gt t_ciclo_RT_min este gt t_ciclo_RT_min este gt t_ciclo_RT
47. insertarPropiedad3 este gt nombre amp este gt z ID VAR SHORT PUBLICO MODIFICABLE z insertarPropiedad3 este gt nombre amp este gt cont ID_VAR_INT PUBLICO MODIFICABLE Contador insertarPropiedad3 este gt nombre amp este calibracion giro ID SAL INT PUBLICO MODIFICABLE calibracion giro fin registro de propiedades espec ficas giroscopo j 346 gt e gt lt kk k k k o lt kkk k kk k k K K k K K k void funcionCrea gt lt 2 2 k k 2 k k k k k o lt kkk k ee k k k k fe int funcion_crea_giroscopo void instancia char nombre int orden unsigned char habilitado struct giroscopo este struct giroscopo instancia ifdef LOG sprintf msgLog Creating s nombre logPrint msgLog 3 endif inicializa_propiedades_giroscopo instancia nombre orden habilitado if registra_propiedades_giroscopo instancia 0 ifdef LOG sprintf msgLog s V Registering properties of s ID ERROR este gt nombre logPrint msgLog 1 endif if registrarInstancia instancia nombre amp clase_giroscopo orden amp este gt habilitado amp este gt finalizado 0 ifdef LOG sprintf msgLog s V Registering instance s ID ERROR este gt nombre logPrint msgLog 1 endif void writeto giro int int reg int val char buf 2 buf 0 reg buf 1 val if write fd buf 2 2 fprintf stderr
48. 400 kHz SCL clock frequency ti 2 5 us SCL cycle time t 0 6 us SCL high time ts 1 3 us tiow SCL low time ta 0 6 us tup sta Start repeated start condition hold time ts 100 ns tsu par data setup time t 34 5 6 0 0 9 us tup par data hold time t7 0 6 us tsu sta Setup time for repeated start ts 0 6 us tsu sto stop condition setup time to 1 3 us teur bus free time between a stop condition and a start condition tio 300 ns tr rise time of both SCL and SDA when receiving 0 ns tr rise time of both SCL and SDA when receiving or transmitting tu 300 ns tr fall time of SDA when receiving 250 ns tr fall time of both SCL and SDA when transmitting Cb 400 pF Capacitive load for each bus line 1 Limits based on characterization results with 400 kHz and a 3 mA sink current not production tested 2 All values referred to the and the Vi levels given in Table 11 3 te is the data hold time that is measured from the falling edge of SCL It applies to data in transmission and acknowledge A transmitting device must internally provide an output hold time of at least 300 ns for the SDA signal with respect to of the SCL signal to bridge the undefined region of the falling edge of SCL 5The maximum ts value must be met only if the device does not stretch the low period ts of the SCL signal maximum value for te is a function of the clock low time ts the clock rise time tio and the minimum data setup time
49. 500 1000 hours Steady State Temperature JEDEC JESD22 A101C 85 C 85 RH 3 7 0 1 Humidity Bias Life read points 168 500 hours Information Only 1000 hours High Temperature Storage JEDEC JESD22 A103C Cond A 125 C Non Bias Bake 3 77 0 1 Life read points 168 500 1000 hours Device Component Level Tests ape Acc TEST Method Condition m Reject Criteria ESD HBM JEDEC JESD22 A114F Class 2 1 5 1 3 0 1 ESD MM JEDEC JESD22 A115 A Class B 200V 1 3 0 1 Latch Up JEDEC JESD78B Level 2 125C 100mA 1 6 0 1 Mechanical Shock JEDEC JESD22 B104C Mil Std 883 method 2002 Cond D 3 5 0 1 reet 10 000g s 0 3ms X Y Z 6 directions 5 times direction JESD22 B103B Variable Frequency random Vibradon Cond B 5 500Hz X Y Z 4 times direction 3 3 011 JEDEC JESD22 A104D Condition N 40 C to 85 ing D Temperature Cycling Soak Mode 2 100 cycles 3 77 0 1 Board Level Tests 8 Method Condition Lot sample Reject Quantity Lot Criteri riteria Board Mechanical Shock JEDEC JESD22 B104C Mil Std 883 method 2002 Cond D 1 5 0 1 10 0000 0 3ms X Y Z 6 directions 5 times direction JEDEC JESD22 A104D Condition 409 to 85 Board TC Soak Mode 2 100 cycles l 40 0 1 1 Tests are preceded by MSL3 Preconditioning in accordance with JEDEC JESD22 A113F 38 of 39 Document Number PS ITG 3200A 00 01 4 7 Z Revision 1 4
50. Cioap 150 pF 210 ns Fall Time tr 150 pF 150 ns Limits based on characterization results not production tested Rise time is measured as the transition time from Vo max to min Of the interrupt pin 3 Fall time is measured as the transition time from Vou min to Vo max Of the interrupt pin Rev D Page 20 of 40 Overrun The overrun bit is set when new data replaces unread data The precise operation of the overrun function depends on the FIFO mode In bypass mode the overrun bit is set when new data replaces unread data in the DATAX DATAY and DATAZ registers Address 0x32 to Address 0x37 In all other modes the overrun bit is set when is filled The overrun bit is automatically cleared when the contents of FIFO are read FIFO The ADXL345 contains patent pending technology for an embedded memory management system with 32 level FIFO that can be used to minimize host processor burden This buffer has four modes bypass FIFO stream and trigger see FIFO Modes Each mode is selected by the settings of the FIFO_MODE bits Bits D7 D6 in the FIFO_CTL register Address 0x38 Bypass Mode In bypass mode FIFO is not operational and therefore remains empty FIFO Mode In FIFO mode data from measurements of the x y and z axes are stored in FIFO When the number of samples in FIFO equals the level specified in the samples bits of the FIFO register Address 0x38
51. E 2 6 22 of 39 Document Number PS ITG 3200A 00 01 4 y Z He Revision 1 4 InvenSense ITG 3200 Product Specification seo asia 8 Register Description This section details each register within the InvenSense ITG 3200 gyroscope Note that any bit that is not defined should be set to zero in order to be compatible with future InvenSense devices The register space allows single byte reads and writes as well as burst reads and writes When performing burst reads or writes the memory pointer will increment until either 1 reading or writing is terminated by the master or 2 the memory pointer reaches certain reserved registers between registers 33 and 60 8 1 Register 0 Who I Type Read Write Register Register Hex Decimal Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bitl Bit0 0 0 ID Description This register is used to verify the identity of the device Parameters ID Contains the address of the device which can also be changed by writing to this register The Power On Reset value of Bit6 Bitl is 110 100 8 2 Register 21 Sample Rate Divider Type Read Write Register Register A A A Default Hex Decimal Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Value 15 21 SMPLRT_DIV 00h Description This register determines the sample rate of the ITG 3200 gyros The gyros outputs are sampled internally at either 1kHz or 8kHz determined by the
52. El Z 20 amp 2 9 L 50 Q 10 0 0 2 0 3 0 9 1 5 2 1 2 7 8 2 0 2 4 2 8 3 2 3 6 8 SELF TEST RESPONSE 0 SUPPLY VOLTAGE V Figure 30 Z Axis Self Test Response at 25 C Vs 2 5 V Figure 33 Supply Current vs Supply Voltage Vs at 25 Rev D Page 12 of 40 THEORY OF OPERATION The ADXL345 is a complete 3 axis acceleration measurement system with a selectable measurement range of 2 g 4 g 8 g or 16 g It measures both dynamic acceleration resulting from motion or shock and static acceleration such as gravity that allows the device to be used as a tilt sensor The sensor is a polysilicon surface micromachined structure built on top silicon wafer Polysilicon springs suspend the structure over the surface of the wafer and provide a resistance against forces due to applied acceleration Deflection of the structure is measured using differential capacitors that consist of independent fixed plates and plates attached to the moving mass Acceleration deflects the proof mass and unbalances the differential capacitor resulting in a sensor output whose ampli tude is proportional to acceleration Phase sensitive demodulation is used to determine the magnitude and polarity of the acceleration Table 6 Power Sequencing ADXL345 POWER SEQUENCING Power can be applied to Vs or in any sequence without damaging the ADXL345 possible power on modes summarized in Table 6 The interfa
53. INT PUBLICO MODIFICABLE contador fin registro de propiedades espec ficas conversor angulos FR gt lt gt lt o lt 2 2 2 2 o k k k k k kkk k kk k k k k k Kk k void funcionCrea k E k k k 2 k k k k f lt k k k kkk k kk kk k k k kK k KK k k fe k k gt lt K K int funcion_crea_conversor_angulos void instancia char nombre int orden unsigned char habilitado f struct conversor angulos este struct conversor angulos instancia ifdef LOG sprintf msgLog Creating s nombre logPrint msgLog 3 endif inicializa_propiedades_conversor_angulos instancia nombre orden habilitado if registra_propiedades_conversor_angulos instancia 0 ifdef LOG sprintf msgLog s V Registering properties of s ID ERROR este gt nombre logPrint msgLog 1 endif if registrarInstancia instancia nombre amp clase_conversor_angulos orden amp este gt habilitado amp este gt finalizado 0 ifdef LOG sprintf msgLog s V Registering instance s ID ERROR este gt nombre logPrint msgLog 1 endif k k k k k K K K void funcionInicializa k k k k k kkk kkk k k k k void funcion_inicializa_conversor_angulos void instancia struct conversor_angulos este struct conversor_angulos instancia ifdef LOG sprintf msgLog Initializing 95 este gt nombre logPrint msgLog 3 endif
54. N O INT1 ADC m ELECTRONICS DIGITAL INTERRUPT 3 AXIS SENSOR GND Rev D Document Feedback Information furnished by Analog Devices believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners 2 LEVEL C SERIAL I O pi SDO ALT ADDRESS FILTER LOGIC O INT2 Tr O SDA SDI SDIO SCL SCLK 07925 001 One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 2009 2013 Analog Devices Inc All rights reserved Technical Support www analog com ADXL345 TABLE OF CONTENTS Features A 1 enne een 22 Applications iio 1 AR 25 General Description testi 1 Register Definitions nnne 2 Functional Block Diagram cc 1 Applications Information eerte tette 28 Revision History orisiirisii 3 Power Supply Decoupling eene 28 4 Mechanical Considerations for Mounting nvm 2 Absolute Maximum
55. No se puede escribir en el giroscopo n k k fe K k gt e K K void funcionInicializa IO void funcion inicializa giroscopo void instancia struct giroscopo este struct giroscopo instancia ifdef LOG sprintf msgLog Initializing 95 este gt nombre logPrint msgLog 3 endif este gt t_ciclo_RT_min 0x 10000000 este 5t ciclo RT max 0 gt ciclo noRT min 0x10000000 gt ciclo noRT max 0 este gt CalibGyroX 0 este gt CalibGyroY 0 este gt CalibGyroZ 0 este gt x 0 este gt y 0 este gt z 0 este gt buf 0 este gt buf 1 este gt buf 2 este gt buf 3 este gt buf 4 este gt buf 5 0 0 0 0 0 0 LL l l gt este gt calibracion_giro 0 este gt cont 0 principio c digo espec fico funcion inicializa giroscopo if ioctl este gt fd I2C_SLA VE ITG3200_I2C_ADDR lt 0 strcpy este gt error_msg_giro Giroscopo is not present writeto_giro este gt fd ITG3200_PWR_MGM 0x00 reset writeto_giro este gt fd ITG3200_SMPLRT_DIV 0x00 1ms por muestra de aqui que T 1ms writeto_giro este gt fd ITG3200_DLPF_FS Oxle finterna 8KHz f muestreo 1000Hz writeto_giro este gt fd ITG3200_INT_CFG 0x01 fin c digo espec fico funcion inicializa giroscopo 46 gt lt gt lt f lt o k k k k k k k k k k k k kk k kk k k k k k kk k kK k k K k k K K k
56. PUBLICO MODIFICABLE t ciclo max insertarPropiedad3 este gt nombre amp este t ciclo noRT ID VAR INT PUBLICO MODIFICABLE t ciclo noRT insertarPropiedad3 este gt nombre amp este t ciclo min ID VAR INT PUBLICO MODIFICABLE t ciclo noRT min insertarPropiedad3 este gt nombre amp este gt t_ciclo_noRT_max ID VAR INT PUBLICO MODIFICABLE t ciclo noRT max principio registro de propiedades espec ficas renormalizar for 120 1 EJES i for j 0 j lt MAX 5 j insertarPropiedad3 este gt nombre gt Matriz i j ID ENT FLOAT PUBLICO MODIFICABLE DCM_Matriz d d i for i 0 i lt MAX_EJES i for j 0 j lt MAX 5 j insertarPropiedad3 este gt nombre amp este dcm matriz l i ID ENT FLOAT PUBLICO MODIFICABLE dcm matriz 1 96d 96d i j for i 0 i lt MAX EJES 1 for j 0 j lt MAX EJES j insertarPropiedad3 este gt nombre amp este dcm matriz renorm i j ID SAL FLOAT PUBLICO MODIFICABLE dcm matriz renorm 46d 96d i for G 0 i lt MAX_EJES i for j 0 j lt MAX EJES j insertarPropiedad3 este gt nombre amp este dcm matriz renorm 1 i j ID SAL FLOAT PUBLICO MODIFICABLE dcm matriz renorm 1 46d 96d i j insertarPropiedad3 este gt nombre amp este gt renorm ID_VAR_FLOAT PUBLICO MODIFICABLE renorm
57. Y Z axes In this configuration a positive current is forced across the resistive load for all three axes 1 0 Negative bias configuration for X Y and Z axes In this configuration a negative current is forced across the resistive load for all three axes 1 1 This configuration is reserved Table 6 Measurement Modes www honeywell com HMC5883L Configuration Register B The configuration register for setting the device gain CRBO through CRB7 indicate bit locations with CRB denoting the bits that are in the configuration register CRB7 denotes the first bit of the data stream The number in parenthesis indicates the default value of that bit CRB default is 0 20 CRB7 CRB6 CRB5 CRB4 CRB3 CRB2 CRB1 CRBO GN2 0 GN1 0 GNO 1 0 0 0 0 0 Table 7 Configuration B Register Location Name Description Gain Configuration Bits These bits configure the gain for CRB7 to CRB5 GN2 GNO the device The gain configuration is common for all channels CRB4 to CRBO 0 These bits must be cleared for correct operation Table 8 Configuration Register B Bit Designations The table below shows nominal gain settings Use the Gain column to convert counts to Gauss The Digital Resolution column is the theoretical value in term of milli Gauss per count LSb which is the inverse of the values in the Gain column The effective resoluti
58. and activity is enabled When the ADXL345 is in sleep mode the host processor can also be placed into sleep mode or low power mode to save significant system power When activity is detected the accelerometer automatically switches back to the original data rate of the application and provides an activity interrupt that can be used to wake up the host processor Similar to when inactivity occurs detection of activity events is disabled and inactivity is enabled OFFSET CALIBRATION Accelerometers are mechanical structures containing elements that are free to move These moving parts can be very sensitive to mechanical stresses much more so than solid state electronics The 0 g bias or offset is an important accelerometer metric because it defines the baseline for measuring acceleration Additional stresses can be applied during assembly of a system containing an accelerometer These stresses can come from but are not limited to component soldering board stress during mounting and application of any compounds on or over the component If calibration is deemed necessary it is recommended that calibration be performed after system assembly to compensate for these effects A simple method of calibration is to measure the offset while assuming that the sensitivity of the ADXL345 is as specified in Table 1 The offset can then be automatically accounted for by using the built in offset registers This results in the data acquired from the DAT
59. connection connection input conversor angulosl dcm matriz renorm 2 1 input input resending input type ID ENT FLOAT input type input dimensions output resending output renormalizarl dcm matriz renorm 2 1 output sequence name connection type connection connection input conversor angulosl dcm matriz renorm 2 2 input input resending input type ID ENT FLOAT input type input dimensions output resending output renormalizarl dcm matriz renorm 2 2 output sequence name connection type connection connection input pid pitchl reference pitch input input resending input type ID ENT FLOAT input type input dimensions output resending output referencias reference pitch output sequence name connection type connection connection input pid rolll reference roll input input resending input type ID ENT FLOAT input type input dimensions output resending lt output gt referencias 1 reference_roll lt output gt lt sequence_name gt lt connection_type gt lt connection gt lt connection gt lt input gt pid_pitch1 pitch lt input gt lt input_resending gt lt input_type gt ID_ENT_FLOAT lt input_type gt lt input_dimensions gt lt output_resending gt lt output gt conversor_angulos1 pitch lt output gt lt sequence_name
60. gt lt connection_type gt lt connection gt lt connection gt lt input gt pid_roll1 roll lt input gt lt input_resending gt lt input_type gt ID_ENT_FLOAT lt input_type gt lt input_dimensions gt lt output_resending gt lt output gt conversor_angulos1 roll lt output gt lt sequence_name gt connection type connection connection input cambio magnitudl out pitch input input resending input type ID ENT FLOAT input type input dimensions output resending output pid pitchl out pitch output sequence name connection type connection connection input cambio magnitudl out roll input input resending input type ID ENT FLOAT input type input dimensions output resending lt output gt pid_roll1 out_roll lt output gt lt sequence_name gt connection type lt connection gt connection input microPWMI fd input input resending input type ID ENT INT input type input dimensions output resending lt output gt i2c 1 fd lt output gt lt sequence_name gt lt connection_type gt lt connection gt lt connection gt lt input gt microPWM1 bus_ok lt input gt lt input_resending gt lt input_type gt ID_ENT_INT lt input_type gt lt input_dimensions gt lt output_resending gt lt output gt 12c1 bus_ok lt output gt lt sequence_name gt lt connection_type gt
61. gt continued below at K 9th clock cycle 9th clock cycle PC Bus Timing Diagram 11 of 39 InvenSens ITG 3200 Product Specification Document Number PS ITG 3200A 00 01 4 Revision 1 4 Release Date 03 30 2010 3 6 Absolute Maximum Ratings Stresses above those listed as Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these conditions is not implied Exposure to the absolute maximum ratings conditions for extended periods may affect device Absolute Maximum Ratings Parameter Supply Voltage VDD VLOGIC Input Voltage Level REGOUT Input Voltage Level CLKIN ADO SCL SDA INT reliability Electrostatic Discharge ESD Protection ed HBM 200V 12 of 39 InvenSens ITG 3200 Product Specification Document Number PS ITG 3200A 00 01 4 Revision 1 4 Release Date 03 30 2010 4 Applications Information 41 Pin Out and Signal Description Number Pin Pin Description 1 CLKIN Optional external reference clock input Connect to GND if unused 8 VLOGIC Digital IO supply voltage VLOGIC must be lt VDD at all times 9 ADO PC Slave Address LSB 10 REGOUT Regulator filter capacitor connection 12 INT Interrupt digital output totem pole or open drain 13 VDD Power supply voltage 18 GND Power supply ground 11 RESV G Reserved Connect to ground 6
62. gt calibracion_giro 0 if read este fd este gt flag 1 0 if read este gt fd este gt buf 6 6 La funcion read intenta leer 6 gt msg giro Unable to read from ITG3200 Jelsef este gt flagg 12 smbus read byte data este fd 0x 1a if este gt flagg 1 strcpy este error msg giro El flagg fn vale 1 este gt x 12 smbus read word data este fd O0x1d este gt y 12 smbus read word data este fd 0x 1f este gt z i2c read word data este fd 0x21 este gt W gyr 0 float este gt x 3845 LSB 17 8 GRADOS RADIANES este gt W gyr 1 float este gt y 784 LSB 17 8 GRADOS RADIANES este gt W gyr 2 float este gt z 281 LSB 17 8 GRADOS_RADIANES if este gt flagg 0 strcpy este gt error_msg_giro El flagg fn vale 0 este gt cont este gt cont este gt CalibGyroX este gt W gyr 0 este gt CalibGyroY este gt Weyr 1 este gt CalibGyroZ este gt W gyr 2 este gt varX este gt CalibGyroX este gt Calib_antX este gt varY este gt CalibGyroY este gt Calib_antY este gt varZ este gt CalibGyroZ este gt Calib_antZ este gt Calib_antX este gt varX este gt Calib_antY este gt varY este gt Calib_antZ este gt varZ if este gt cont gt 50 este gt offsetGyro_x este gt Calib_antX 50 0 este gt offsetGyr
63. gt dcm_matriz_1 1 1 amp fdummy 1 0 amp fdummy este gt dcm_matriz_1 1 amp fdummy este dcm matriz 1 2 0 amp fdummy este dcm matriz 1 2 1 amp fdummy este dcm matriz 1 2 2 amp fdummy fin inicializaci n de propiedades espec ficas renormalizar j k k k k k K K k void registra_propiedades E E E ole E 2 2 ope k k k k k k k kk k kk k k k k k k kk k int registra_propiedades_renormalizar void instancia struct renormalizar este struct renormalizar instancia char saux MAX_LONG_NOMBRE int i j insertarNombre2 este gt nombre este emStrcpy saux ID SISTEMA ID renormalizar NO MODIFICABLE insertarPropiedad3 este gt nombre amp este gt nombre ID VAR TEXT PUBLICO nombre insertarPropiedad3 este gt nombre amp este gt orden ID VAR INT PUBLICO MODIFICABLE orden insertarPropiedad3 este gt nombre amp este gt habilitado ID VAR BYTE PUBLICO MODIFICABLE habilitado insertarPropiedad3 este gt nombre amp este gt finalizado ID VAR BYTE PUBLICO MODIFICABLE finalizado insertarPropiedad3 este gt nombre gt ciclo RT ID VAR INT PUBLICO MODIFICABLE t ciclo RT insertarPropiedad3 este gt nombre amp gt ciclo min ID VAR INT PUBLICO MODIFICABLE t ciclo RT min insertarPropiedad3 este gt nombre gt ciclo max ID VAR INT
64. gt pwm_motor_gris1 lt 1800 este gt pwm_motor_grisl 1800 else if este gt pwm_motor_gris2 lt 1800 este gt pwm_motor_gris2 1800 if este gt pwm_motor_negrol gt 2800 este gt pwm_motor_negrol 2800 else if este gt pwm_motor_negro2 gt 2800 este gt pwm_motor_negro2 2800 else if este gt pwm_motor_negrol lt 1800 este gt pwm_motor_negrol 1800 else if este gt pwm_motor_negro2 lt 1800 este gt pwm_motor_negro2 1800 fin c digo espec fico funcion normal cambio_magnitud este gt t_ciclo_RT 0 418 if este 5t ciclo RT gt este gt t_ciclo_RT_max este 5t ciclo RT max este gt t_ciclo_RT else if este gt t_ciclo_RT lt este gt t_ciclo_RT_min este gt t_ciclo_RT_min este gt t_ciclo_RT k k k k k K K k void funcionNormalNoRT O void funcion normal noRT cambio magnitud void instancia int t ciclo f struct cambio magnitud este struct cambio magnitud instancia ifdef LOG sprintf msgLog Normal function 96s este gt nombre logPrint msgLog 6 endif struct timespec ts crononsec 1 amp ts principio c digo espec fico funcion normal noRT cambio magnitud fin c digo espec fico funcion normal noRT cambio magnitud gt ciclo noRT 0 amp ts if este 5t ciclo noRT gt gt ciclo noRT max este 5t ciclo noRT max este 5t ciclo n
65. gt t_ciclo_noRT_min este gt t_ciclo_noRT_min este gt t_ciclo_noRT RR gt lt a 2 2 2 2 o ol oe k k K k k K K k void funcionFinaliza IO void funcion_finaliza_pid_roll void instancia struct pid_roll este struct pid_roll instancia ifdef LOG sprintf msgLog Finalizing 96s este gt nombre logPrint msgLog 3 endif principio c digo espec fico funcion finaliza pid_roll fin c digo espec fico funcion finaliza pid roll j FRR gt lt a f lt o o k k as os k k k k k k k k kk kk k k k k kkk k kK k k K kk K K K void inicilizapid_roll IO int inicializa pid roll ifdef LOG sprintf msgLog Initializing s ID pid roll logPrint msgLog 3 endif clase_pid_roll funcionCrea funcion_crea_pid_roll clase_pid_roll funcionInicializa funcion_inicializa_pid_roll clase_pid_roll funcionNormal funcion_normal_pid_roll clase_pid_roll funcionNormalNoRT funcion_normal_noRT_pid_roll clase_pid_roll funcionFinaliza funcion_finaliza_pid_roll ifdef ID_LISTAS iniciarLista amp instancias pid roll else clase_pid_roll n 0 clase pid roll maxNumComp MAX pid roll endif clase_pid_roll instancias amp instancias_pid_roll clase_pid_roll longComponente sizeof struct pid roll return insertarPropiedad2 ID_ COMPONENTE ID pid roll amp clase pid roll ID COMPONENTE NO MODIFICABLE j INSTANCIA DE CAMBIO DE MAGNITUD ca
66. input type ID ENT FLOAT input type input dimensions output resending output correccionPI Magl Wgyr fin 2 output sequence name connection type connection connection lt input gt actualizar_matrizl calibracion_giro lt input gt lt input_resending gt lt input_type gt ID_ENT_INT lt input_type gt lt input_dimensions gt lt output_resending gt lt output gt giroscopol calibracion_giro lt output gt lt sequence_name gt connection type connection connection input actualizar matrizl dcm matriz renorm 1 0 0 input input resending input type ID ENT FLOAT input type input dimensions output resending output renormalizarl dcm matriz renorm 1 0 0 output sequence name connection type connection connection input actualizar matrizl dcm matriz renorm 1 0 1 input input resending input type ID ENT FLOAT input type input dimensions output resending output renormalizarl dcm matriz renorm 1 0 1 output sequence name connection type connection connection input actualizar matrizl dcm matriz renorm 1 0 2 input input resending input type ID ENT FLOAT input type input dimensions output resending lt output gt renormalizar1 dcm_matriz_renorm_1 0 2 lt output gt lt sequence_name gt lt connection_
67. int funcion_crea_acelerometro void instancia char nombre int orden unsigned char habilitado f struct acelerometro este struct acelerometro instancia ifdef LOG sprintf msgLog Creating s nombre logPrint msgLog 3 endif inicializa_propiedades_acelerometro instancia nombre orden habilitado if registra_propiedades_acelerometro instancia 0 ifdef LOG sprintf msgLog s V Registering properties of s ID ERROR este gt nombre logPrint msgLog 1 endif if registrarInstancia instancia nombre amp clase acelerometro orden amp este gt habilitado amp este gt finalizado 0 1 ifdef LOG sprintf msgLog 96s V Registering instance s ID ERROR este gt nombre logPrint msgLog 1 endif void writetodisp int fd int reg int val char buf 2 buf 0 reg buf 1 val if write fd buf 2 2 fprintf stderr No se puede escribir en el dispositivo 12c n j j k k k k k kk kk K k k K K k K K K void funcionInicializa 2 o lt k k k k k k k k o lt kkk k k k k k he k CCP void funcion_inicializa_acelerometro void instancia struct acelerometro struct acelerometro instancia ttifdef LOG sprintf msgLog Initializing s este gt nombre logPrint msgLog 3 endif este gt t_ciclo_RT_min 0x10000000 este gt t_ciclo_RT_max 0 este gt t_ciclo_noRT_min 0x 10000000
68. int t ciclo struct pid pitch struct pid pitch instancia floatt ciclo preciso ns 0 int t ciclo rt int devolverElemento SISTEMA tiempo ciclo rt ftifdef LOG sprintf msgLog Normal function 96s este gt nombre logPrint msgLog 6 endif struct timespec ts crononsec 1 amp ts principio c digo espec fico funcion normal pid pitch if t ciclo rt gt t ciclo 1e6 0 95 amp amp t ciclo rt t ciclo 1e6 1 05 este error pitch este reference pitch este gt pitch este variacion error pitch este error pitch este error oldl pitch este proportional pitch este kp pitch este error pitch este integral pitch este gt integral_pitch este gt error_pitch float t_ciclo_rt 1e9 if este integral pitch gt 150 este integral pitch 150 else if este gt integral_pitch 150 este integral pitch 150 este gt derivative_pitch este gt variacion_error_pitch float t ciclo rt 1e9 este out pitch 0 8 0 04 este gt error_pitch este gt proportional_pitch este gt ki_pitch este gt integral_pitch este gt kd_pitch este gt derivative_pitch if este gt out_pitch gt 50 este gt out_pitch 50 else if este gt out_pitch lt 50 este gt out_pitch 50 este gt error_old1_pitch este gt error_pitch este gt out_old_pitch este gt out_pitch f
69. lt connection gt connection lt input gt microPWM1 pwm_motor_gris1 lt input gt lt input_resending gt lt input_type gt ID_ENT_INT lt input_type gt lt input_dimensions gt lt output_resending gt output cambio magnitudl pwm motor grisl output sequence name connection type connection connection input microPWMl pwm motor gris2 input input resending input type ID ENT INT input type input dimensions output resending output cambio magnitudl pwm motor gris2 output sequence name connection type connection connection input microPWMI l pwm motor negrol input input resending input type ID ENT INT input type input dimensions output resending output cambio magnitudl pwm motor negrol output sequence name connection type lt connection gt connection input microPWMl pwm motor negro2 input input resending input type ID ENT INT input type input dimensions output resending output cambio magnitudl pwm motor negro2 output sequence name connection type connection lt connections gt lt grafcets gt lt registers gt lt stubs gt lt resendings gt lt cosme gt MAKEFILE CC gcc RUNTIME PATH COSME_HOME runtime LIB PATH COSME_HOME lib all lib 12c 0 V acelerometro o giroscopo o magnetometro o corr
70. output sequence name connection type connection connection input correcionPI Accl Wgyr 1 input input resending input type ID ENT FLOAT input type input dimensions output resending output giroscopol Wgyr 1 output sequence name connection type connection connection input correcionPI Acc1 Wgyr 2 input input resending input type ID ENT FLOAT input type input dimensions output resending output giroscopol Wgyr 2 output sequence name connection type lt connection gt lt connection gt input correcionPI Accl dcm matriz renorm 1 0 0 input input resending input type ID ENT FLOAT input type input dimensions output resending output renormalizarl dcm matriz renorm 1 0 0 output sequence name connection type lt connection gt lt connection gt lt input gt correcionPI_Accl dem_matriz_renorm_1 0 1 lt input gt lt input_resending gt input type ID ENT FLOAT input type input dimensions output resending output renormalizarl dcm matriz renorm 1 0 1 output sequence name connection type lt connection gt lt connection gt input correcionPI Accl dcm matriz renorm 1 0 2 input input resending input type ID ENT FLOAT input type input dimensions output resending output renor
71. t ciclo noRT max principio registro de propiedades espec ficas microPWM insertarPropiedad3 este gt nombre amp este bus ok ID ENT INT PUBLICO IMODIFICABLE bus ok insertarPropiedad3 este gt nombre amp este gt fd ID ENT INT PUBLICO IMODIFICABLE fd insertarPropiedad3 este gt nombre amp este pwm motor grisl ID ENT INT PUBLICO IMODIFICABLE pwm motor 61151 insertarPropiedad3 este gt nombre amp este pwm motor gris2 ID ENT INT PUBLICO IMODIFICABLE pwm motor gris2 insertarPropiedad3 este gt nombre amp este pwm motor negrol ID ENT INT PUBLICO IMODIFICABLE pwm motor negrol insertarPropiedad3 este gt nombre amp este pwm motor negro2 ID ENT INT PUBLICO IMODIFICABLE pwm motor negro2 insertarPropiedad3 este gt nombre amp este gt condicion ID VAR INT PUBLICO IMODIFICABLE condicion insertarPropiedad3 este gt nombre amp este gt ciclo_pwm ID INT PUBLICO IMODIFICABLE ciclo insertarPropiedad3 este gt nombre amp este gt freq ID VAR INT PUBLICO IMODIFICABLE frecuencia fin registro de propiedades espec ficas microPWM j void funcionCrea IN int funcion_crea_microPWM void instancia char nombre int orden unsigned char habilitado struct microPWM este struct microPWM instancia ifdef LOG sprintf msgLog Creating s nombre logPrint msgLog 3 endif inicializa propiedades
72. the bus master must output the address of the slave it is accessing There are a maximum of 64 possible programmable addresses using the 6 hardware address pins Two of these addresses Software Reset and LED All Call cannot be used because their default power up state is ON leaving a maximum of 62 addresses Using other reserved addresses as well as any other subcall address will reduce the total number of possible addresses even further Regular slave address The I2C bus slave address of the PCA9685 is shown in Figure 4 To conserve power no internal pull up resistors are incorporated on the hardware selectable address pins and they must be pulled HIGH or LOW Remark Using reserved I C bus addresses will interfere with other devices but only if the devices on the bus and or the bus will be open to other I2C bus systems at some later date In a closed system where the designer controls the address assignment these addresses can be used since the PCA9685 treats them like any other address The LED All Call Software Reset and PCA9564 PCA9665 slave address if on the bus can never be used for individual device addresses e PCA9685 LED All Call address 1110 000 and Software Reset 0000 0110 which are active on start up All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Product data sheet Rev 3 2 September 2010 6 of 51 Semi
73. 0 este gt Vmag 1 gt matriz renorm 1 1 2 este gt Vmag 2 este 2 dcm matriz renorm 1 1 1 este errorY aw 1 este gt Vmag 2 gt matriz renorm 1 1 0 este 2 Vmag 0 este 2 dcm matriz renorm 1 1 2 este gt errorY aw 2 este gt Vmag 0 gt matriz renorm 1 1 1 este gt Vmag 1 este 2 dcm matriz renorm 1 1 0 for c 0 c 3 este Omega P Compass c este gt errorYaw c este gt Kp_Yaw j for c 0 c 3 este Scaled Omega I Compass c este gt errorYaw c este gt Ki_Yaw j for c 0 c 3 este Omega I Compass c este Omega Compass c este 2Scaled Omega I Compass c for 1 0 1 lt 3 1 este gt W gyr_fin 2 este gt W gyr_modif_prom 2 este gt Omega_I_Compass 2 este gt Omega_P_Compass 2 este gt W gyr_fin 0 este gt Wgyr_modif_prom 0 este gt W gyr_fin 1 este gt Wgyr_modif_prom 1 fin c digo espec fico funcion normal correccionPI Mag este gt t_ciclo_RT 0 416 if este 5t ciclo RT gt este gt t_ciclo_RT_max este 5t ciclo RT max este gt t_ciclo_RT else if este gt t_ciclo_RT lt este gt t_ciclo_RT_min este gt t_ciclo_RT_min este 5t ciclo RT 46 gt lt gt lt k k k kk k k kk k k k k k K K k void funcionNormalNoRT O void funcion_normal_noRT_correcci
74. 00000000 Data format control 0x32 50 DATAXO R 00000000 X Axis Data 0 0x33 51 DATAX1 R 00000000 X Axis Data 1 0x34 52 DATAYO R 00000000 Y Axis Data 0 0x35 53 DATAY1 R 00000000 Y Axis Data 1 0x36 54 DATAZO R 00000000 Z Axis Data 0 0x37 55 DATAZ1 R 00000000 Z Axis Data 1 0x38 56 FIFO_CTL R W 00000000 FIFO control 0x39 57 FIFO_STATUS R 00000000 FIFO status Rev D Page 23 of 40 ADXL345 Register OxOO DEVID Read Only D7 D6 D5 D4 D3 D2 D1 DO 1 1 1 0 0 1 0 1 The DEVID register holds a fixed device ID code of OxE5 345 octal Register OX1D THRESH TAP Read Write The THRESH register is eight bits and holds the threshold value for tap interrupts The data format is unsigned therefore the magnitude of the tap event is compared with the value in THRESH for normal tap detection The scale factor is 62 5 mg LSB that is 16 g A value of 0 may result in undesirable behavior if single tap double tap interrupts are enabled Register Ox TE Register Ox F Register Ox20 OFSX OFSY OFSZ Read Write The OFSX OFSY and OFSZ registers are each eight bits and offer user set offset adjustments in twos complement format with a scale factor of 15 6 mg LSB that is Ox7F 2 g The value stored in the offset registers is automatically added to the acceleration data and the resulting value is stored in the output data registers For additional information regarding offset c
75. 1Cpl l 300 120 ns signals tsp pulse width of spikes that must Ul 50 50 50 ns be suppressed by the input filter LOW to OFF state propagation to LEDn 40 40 40 ns delay OUTNE 1 0 10 or 11 in MODE2 register OFF state to LOW propagation to LEDn 60 60 60 ns delay OUTNE 1 0 10 or 11 in MODE2 register tPuz HIGH to OFF state propagation OE to LEDn 60 60 60 ns delay OUTNE 1 0 10 or 11 in MODE2 register 131 Snq 2z 16 21 Jouueyo 9L S896VOd SIOJONPUODIWIS dXN jonpoid 0102 1 z sieuire osip 129146 si jueuunoop uoneuuojur LG JO Ot S896VOd pamuasau syu 70102 AB dXN O Table 14 Dynamic characteristics continued Symbol Parameter Conditions Standard mode Fast mode 2 Fast mode Plus Unit 12C bus 12C bus Min Max Min Max Min Max OFF state to HIGH propagation to LEDn 40 E 40 40 ns delay OUTNE 1 0 10 or 11 in MODE2 register tPLH LOW to HIGH propagation delay to LEDn a 40 40 40 ns OUTNE 1 0 01 in MODE2 register tpHL HIGH to LOW propagation delay to LEDn 60 60 60 ns OUTNE 1 0 00 in MODE2 register 1 Minimum SCL clock frequency is limited by the bus time out feature which resets the serial bus interface if either SDA or SCL is held LOW for a minimum of
76. 2014 Obtencion de medidas del sensor HMC5883L ok Eugenio Alcala Baselga include lt stdio h gt include lt string h gt include lt math h gt include lt sys time h gt include lt sys select h gt include lt sys ioctl h gt include lt sys stat h gt include lt linux 12c dev h gt include runtime h include magnetometro h ifdef ID LISTAS struct lista instancias magnetometro else define MAX_magnetometro 16 struct magnetometro instancias_magnetometro MAX_magnetometro endif struct componente clase_magnetometro extern char msgLog extern int dummy FRR gt lt A A k o o a o o os k k k k k k k k k k kk k k k k k k k kk k kK k k K k k K K k void inicializa_propiedades E k k k k k k k k k k k k kk kk k k k k k k kk k kk void inicializa_propiedades_magnetometro void instancia char nombre int orden unsigned char habilitado struct magnetometro este struct magnetometro instancia strcpy este gt nombre nombre este gt orden orden este gt habilitado habilitado este gt finalizado 0 principio inicializaci n de propiedades espec ficas magnetometro este gt fd amp dummy este gt bus_ok amp dummy strcpy este gt error_msg_mag no error fin inicializaci n de propiedades espec ficas magnetometro void registra_propiedades NO int registra_propiedades_magnetometro void in
77. 25 ms Disable bus time out feature for DC operation 2 tvo ack time for Acknowledgement signal from SCL LOW to SDA out LOW 3 tvp par minimum time for SDA data out to be valid following SCL LOW 4 master device must internally provide a hold time of at least 300 ns for the SDA signal refer to the Vi of the SCL signal in order to bridge the undefined region of SCL s falling edge 5 The maximum t for the SDA and SCL bus lines is specified at 300 ns The maximum fall time t for the SDA output stage is specified at 250 ns This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA SCL bus lines without exceeding the maximum specified t 6 Cp total capacitance of one bus line in pF 7 Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns 19 03u02 G37 Snq 2 WMd 114 21 91 S896VOd SJOJONPUODIWISS dXN NXP Semiconductors 9685 16 channel 12 bit PWM 2 LED controller Fig 31 Definition of timing tSU STA tsu sTO tHD DAT tHIGH tsu DAT Sr 002 986 9685 START bit 1 acknowledge STOF protocol condition D1 A condition S P tSU STA tow tHIGH SCL SDA tHD STA tSU DAT tvD DAT tvp ack tsu sTO 002aab285 Rise fall times refer to Vi and Fig 32 I C bus timin
78. 255 250 245 240 235 230 TEMPERATURE C Figure 22 X Axis Sensitivity vs Temperature Eight Parts Soldered to PCB Vs 2 5 V Full Resolution 40 20 0 20 40 60 80 100 120 280 275 270 265 260 255 250 245 240 235 230 TEMPERATURE C Figure 23 Y Axis Sensitivity vs Temperature Eight Parts Soldered to PCB Vs 2 5 V Full Resolution 40 20 0 20 40 60 80 100 120 TEMPERATURE Figure 24 Z Axis Sensitivity vs Temperature Eight Parts Soldered to PCB Vs 2 5 V Full Resolution SENSITIVITY LSB g 07925 222 SENSITIVITY LSB g 07925 223 SENSITIVITY LSB g 07925 224 Rev D Page 11 of 40 280 275 270 265 260 255 250 245 240 235 230 ADXL345 40 20 0 20 40 60 80 100 120 280 275 270 265 260 255 250 245 240 235 230 TEMPERATURE Figure 25 X Axis Sensitivity vs Temperature Eight Parts Soldered to PCB Vs 3 3 V Full Resolution 40 20 0 20 40 60 80 100 120 280 275 270 265 260 255 250 245 240 235 230 TEMPERATURE C Figure 26 Y Axis Sensitivity vs Temperature Eight Parts Soldered to PCB Vs 3 3 V Full Resolution
79. 27 xlabel Ciclo PWM ylabel Empuje 2 syms abc a b c solve 3025 a 55 b c 220 4900 a 70 b c 280 9025 a 95 b c 470 for i 1 11 parabola ideal i funcion _parabola Ciclo_trabajo 1 96 end 96 96 trabajo parabola ideal k Funci n parabola m function y parabola x y 9 100 x 2 29 4 x 693 2 end INDICE DEL ANEXO TAG C TO EH 3 O 3 kou dotes eoa 9 oe COSO etes tn ES Sa Festa esu de Geen pe uus 10 PINOSCODO TI co Sut etudes du ea E CM 17 UI A e e a cid 18 O 27 magnetometro C 28 ACC a odii 35 AA a a 36 MM I dancans 43 ptomedriador CA D R E 44 correccionPI usc Cite ee REX TR C SUPRA ERN R 51 DD 52 actualizar litis 59 actualizar malta ed collie 60 TOO A A eet ass 67 tenormaltzate A ANA AA aep 264 68 GOD VerSOE ceo 75 CONVErSOr
80. 5 V operation Simple linear interpolation can be used to determine typical shifts in offset and sensitivity at other supply voltages Rev D Page 33 of 40 ADXL345 Changes in noise performance self test response and supply current are discussed elsewhere throughout the data sheet For noise performance the Noise Performance section should be reviewed The Using Self Test section discusses both the operation of self test over voltage a square relationship with supply voltage as well as the conversion of the self test response in gs to LSBs Finally Figure 33 shows the impact of supply voltage on typical current consumption at a 100 Hz output data rate with all other output data rates following the same trend OFFSET PERFORMANCE AT LOWEST DATA RATES The ADXL345 offers a large number of output data rates and bandwidths designed for a large range of applications However at the lowest data rates described as those data rates below 6 25 Hz the offset performance over temperature can vary significantly from the remaining data rates Figure 54 Figure 55 and Figure 56 show the typical offset performance of the ADXL345 over temperature for the data rates of 6 25 Hz and lower All plots are normalized to the offset at 100 Hz output data rate therefore a nonzero value corresponds to additional offset shift due to temperature for that data rate When using the lowest data rates it is recommended that the operating temperature rang
81. 8 LSBs 23h LED7_ON_H 7 5 reserved R 000 non writable 4 LED7_ON_HI 4 R W 0 LED7 full 3 0 1 07 ON H 3 0 R W 0000 LEDn_ON count for LED7 4 MSBs 24h LED7_OFF_L 7 0 1 07 7 0 R W 0000 0000 LEDn_OFF count for LED7 8 LSBs 25h LED7_OFF_H 7 5 reserved R 000 non writable 4 LED7_OFF_HI 4 R W 1 LED7 full OFF 3 0 LED7_OFF_H 3 0 R W 0000 LEDn OFF count for LED7 4 MSBs 26h LED8_ON L 7 0 1 08 7 0 R W 0000 0000 LEDn ON count for LED8 8 LSBs 27h LED8 ON H 7 5 reserved R 000 non writable 4 LED8 ON H 4 R W 0 LED8 full 3 0 LED8 ON H 3 0 R W 0000 LEDn ON count for LED8 4 MSBs 28h LED8 OFF L 7 0 1 08 OFF 7 0 R W 0000 0000 LEDn OFF count for LED8 8 LSBs 29h LED8 OFF H 7 5 reserved R 000 non writable 4 LED8 OFF H 4 R W 1 LED8 full OFF 30 LED8_OFF_H 3 0 R W 0000 LEDn OFF count for LED8 4 MSBs 9685 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Product data sheet Rev 3 2 September 2010 21 of 51 Semiconductors 9685 16 channel 12 bit PWM 2 LED controller Table 6 LED ON LED OFF control registers address 06h to 45h bit description continued default value Address Register Bit Symbol Access Value Description 2Ah LED9 ON L 7 0 LED9 ON 7 0 R W 0000 0000 LEDn ON count for LED9 8 LSBs 2Bh LED9 ON H 7 5 reserved R 000 non writable 4 LED9 ON H 4 R W 0 L
82. InvenSense ITG 3200 Product Specification Rose Dare 08 50 0106 This information furnished by InvenSense is believed to be accurate and reliable However no responsibility is assumed by InvenSense for its use or for any infringements of patents or other rights of third parties that may result from its use Specifications are subject to change without notice InvenSense reserves the right to make changes to this product including its circuits and software in order to improve its design and or performance without prior notice InvenSense makes no warranties neither expressed nor implied regarding the information and specifications contained in this document InvenSense assumes no responsibility for any claims or damages arising from information contained in this document or from the use of products and services detailed therein This includes but is not limited to claims or damages based on the infringement of patents copyrights mask work and or other intellectual property rights Certain intellectual property owned by InvenSense and described in this document is patent protected No license is granted by implication or otherwise under any patent or patent rights of InvenSense This publication supersedes and replaces all information previously supplied Trademarks that are registered trademarks are the property of their respective companies InvenSense sensors should not be used or sold in the development storage production or utilization of any
83. No special reflow profile is required for HMC5883L which is compatible with lead eutectic and lead free solder paste reflow profiles Honeywell recommends adherence to solder paste manufacturer s guidelines Hand soldering is not recommended Built in self test can be used to verify device functionalities after assembly External Capacitors The two external capacitors should be ceramic type construction with low ESR characteristics The exact ESR values are not critical but values less than 200 milli ohms are recommended Reservoir capacitor C1 is nominally 4 7 pF in capacitance with the set reset capacitor C2 nominally 0 22 uF in capacitance Low ESR characteristics may not be in many small SMT ceramic capacitors 0402 so be prepared to up size the capacitors to gain Low ESR characteristics INTERNAL SCHEMATIC DIAGRAM HMC5883L HMC5883L HOST CPU OFF SET STRAP DRIVER SET RESET 5 5 eras DRIVER SLAVE 2 MASTER 6 www honeywell com HMC5883L DUAL SUPPLY REFERENCE DESIGN HMC5883L HOST CPU 2 2 161 to 3 64 I2C CLK I2C DATA SLAVE I C MASTER SINGLE SUPPLY REFERENCE DESIGN HMC5883L HOST CPU 2 16V to 3 6V SCL 2 spate J Tic pata SLAVE 2 MASTER www honeywell com HMC5883L PERFORMANCE The following graph s highlight HMC5883L s performance Typical Noise Floor Field Resolution HMC588
84. OFF registers is via the 12C bus and asynchronous to the internal oscillator we want to ensure that we do not see any visual artifacts of changing the ON and OFF values This is achieved by updating the changes at the end of the LOW cycle PWM frequency PRE SCALE The hardware forces a minimum value that can be loaded into the PRE SCALE register at 3 The PRE SCALE register defines the frequency at which the outputs modulate prescale value is determined with the formula shown in Equation 1 prescale value round osc clock 2 1 4096 x update rat where the update rate is the output modulation frequency required For example for an output frequency of 200 Hz with an oscillator clock frequency of 25 MHz 25 MHZ 30 2 prescale value round F x 200 The PRE SCALE register can only be set when the SLEEP bit of register is set to logic 1 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Product data sheet Rev 3 2 September 2010 24 of 51 NXP Semiconductors PCA9685 7 3 6 7 3 7 PCA9685 16 channel 12 bit PWM 2 LED controller SUBADR1 to SUBADR3 I2C bus subaddress 1 to 3 Table 8 SUBADR1 to SUBADR3 I2C bus subaddress registers 0 to 3 address 02h to 04h bit description Legend default value Address Register Bit Symbol Access Value Description 02h SUBADR1 7 1 1 7 1 R W
85. PATH raspi h RUNTIME_PATH raspi c CC c referencias c IS RUNTIME PATH Im cambio magnitud o cambio magnitud h cambio magnitud c V RUNTIME PATH utiles h RUNTIME_PATH utiles c RUNTIME_PATH cosme h RUNTIME_PATH runtime h S RUNTIME_PATH runtime c V RUNTIME PATH runtime esp h S RUNTIME_PATH runtime_esp c RUNTIME_PATH raspi h RUNTIME PATH raspi c CC c cambio magnitud c ISIRUNTIME PATH Im microPWM o microPWM h microPWM c RUNTIME_PATH utiles h RUNTIME_PATH utiles c RUNTIME_PATH cosme h RUNTIME_PATH runtime h S RUNTIME_PATH runtime c V RUNTIME PATH runtime esp h S RUNTIME_PATH runtime_esp c RUNTIME_PATH raspi h RUNTIME_PATH raspi c CC c microPWM c I RUNTIME_PATH Im miniCosmeApp miniCosmeApp c RUNTIME_PATH cosme h S RUNTIME_PATH utiles o RUNTIME_PATH listas o S RUNTIME_PATH servidorNombres o V RUNTIME_PATH pasarela o S RUNTIME_PATH runtime_esp o RUNTIME_PATH raspi o RUNTIME_PATH runtime o 12c 0 V acelerometro o giroscopo o magnetometro o correcionPI_Acc o promediador o correccionPI_Mag o actualizar matriz o renormalizar o conversor angulos o pid pitch o pid roll o referencias o cambio magnitud o microPWM o CC o miniCosmeApp miniCosmeApp c lrt Ipthread Im IS RUNTIME PATH IS LIB PATH RUNTIME PATH utiles o SSRUNTIME PATH listas o RUNTIME_PATH servidorNombres o V RUNTIME_PATH pasarela o S RUNTIME_PATH run
86. PUBLICO MODIFICABLE t ciclo max insertarPropiedad3 este gt nombre gt ciclo noRT ID VAR INT PUBLICO MODIFICABLE t ciclo noRT insertarPropiedad3 este gt nombre amp este t ciclo min ID VAR INT PUBLICO MODIFICABLE t ciclo noRT min insertarPropiedad3 este gt nombre amp este 5t ciclo noRT max ID VAR INT PUBLICO MODIFICABLE t ciclo noRT max principio registro de propiedades espec ficas promediador for z 0 z lt MAX_EJES z insertarPropiedad3 este gt nombre amp este gt Wgyr_modif_prom z ID SAL FLOAT PUBLICO MODIFICABLE Wgyr modif prom 96d z for z 0 z lt z insertarPropiedad3 este gt nombre amp este gt W gyr_modif z ID ENT FLOAT PUBLICO MODIFICABLE Weyr_modif d z insertarPropiedad3 este gt nombre amp este gt acumula_filtrado_pitch ID_VAR_FLOAT PUBLICO MODIFICABLE acumula_filtrado_pitch insertarPropiedad3 este gt nombre amp este acumula filtrado roll ID VAR FLOAT PUBLICO MODIFICABLE acumula filtrado roll fin registro de propiedades espec ficas promediador j 346 gt lt gt e k k k k k kk k kk k k K k k K K k void funcionCrea k k f lt k k gt e K k int funcion_crea_promediador void instancia char nombre int orden unsigned char habilitado struct promediador este struct promediador instancia
87. RUNTIME_PATH utiles c RUNTIME_PATH cosme h RUNTIME_PATH runtime h RUNTIME_PATH runtime c RUNTIME_PATH runtime_esp h RUNTIME_PATH runtime_esp c RUNTIME PATH raspi h RUNTIME_PATH raspi c CC c renormalizar c PATH Im conversor_angulos o conversor angulos h conversor angulos c RUNTIME PATH utiles h RUNTIME_PATH utiles c RUNTIME_PATH cosme h RUNTIME_PATH runtime h S RUNTIME_PATH runtime c V RUNTIME PATH runtime esp h S RUNTIME_PATH runtime_esp c RUNTIME PATH raspi h RUNTIME_PATH raspi c CC c conversor angulos c IS RUNTIME PATH Im pid pitch o pid pitch h pid pitch c RUNTIME_PATH utiles h RUNTIME PATH utiles c RUNTIME_PATH cosme h RUNTIME_PATH runtime h S RUNTIME_PATH runtime c V RUNTIME PATH runtime esp h S RUNTIME_PATH runtime_esp c RUNTIME PATH raspi h RUNTIME_PATH raspi c CC c pid pitch c I RUNTIME_PATH Im pid roll o pid roll h pid roll c RUNTIME PATH utiles h RUNTIME PATH utiles c RUNTIME_PATH cosme h RUNTIME_PATH runtime h S RUNTIME_PATH runtime c V RUNTIME PATH runtime esp h S RUNTIME_PATH runtime_esp c RUNTIME_PATH raspi h RUNTIME_PATH raspi c CC c pid_roll c IS RUNTIME_PATH Im referencias o referencias h referencias c RUNTIME_PATH utiles h RUNTIME_PATH utiles c RUNTIME_PATH cosme h RUNTIME_PATH runtime h RUNTIME_PATH runtime c RUNTIME_PATH runtime_esp h RUNTIME_PATH runtime_esp c RUNTIME
88. STOP Conditions 18 of 39 Document Number PS ITG 3200A 00 01 4 5 Z Revision 1 4 InvenSense ITG 3200 Product Specification Rasa asta Data Format Acknowledge data bytes are defined to be 8 bits long There is no restriction to the number of bytes transmitted per data transfer Each byte transferred must be followed by an acknowledge signal The clock for the acknowledge signal is generated by the master while the receiver generates the actual acknowledge signal by pulling down SDA and holding it low during the HIGH portion of the acknowledge clock pulse If a slave is busy and cannot transmit or receive another byte of data until some other task has been performed it can hold SCL LOW thus forcing the master into a wait state Normal data transfer resumes when the slave is ready and releases the clock line see figure below DATA OUTPUT BY 7 TRANSMITTER SDA _ acknowledge DATA OUTPUT BY RECEIVER SDA acknowledg SCL FROM MASTER 2 N 4 clock pulse for START acknowledgement condition Acknowledge on the Bus Communications After beginning communications with the START condition S the master sends a 7 bit slave address followed by an 8 bit the read write bit The read write bit indicates whether the master is receiving data from or is writing to the slave device Then the master releases the SDA line and waits for the acknowledge signal ACK from the sl
89. The 800 Hz output data rate is recommended only for communication speeds greater than or equal to 400 kHz and the remaining data rates scale proportionally For example the minimum recommended communication speed for a 200 Hz output data rate is 100 KHz Operation at an output data rate above the recommended maximum may result in undesirable effects on the acceleration data including missing samples or additional noise Preventing Bus Traffic Errors The ADXL346 CS pin is used both for initiating SPI transactions and for enabling C mode When the ADXL346 is used on a SPI bus with multiple devices its CS pin is held high while the master communicates with the other devices There may be conditions where a SPI command transmitted to another device looks like a valid PC command In this case the ADXL346 would interpret this as an attempt to communicate in PC mode and could interfere with other bus traffic Unless bus traffic can be adequately controlled to assure such a condition never occurs it is recommended to add a logic gate in front of the SDI pin as shown in Figure 36 This OR gate will hold the SDA line high when CS is high to prevent SPI bus traffic at the ADXL346 from appearing as an start command ADXL345 PROCESSOR 07925 104 Figure 36 Recommended SPI Connection Diagram when Using Multiple SPI Devices on a Single Bus Rev D Page 15 of 40 a tspo ADDRESS BITS DATA BITS tos gt i e
90. Tpmin tgo lt 30 I TPmax TLiquidus 4 x TPmax 5 C 250 C 60 lt lt 120 Troom 36 of 39 Document Number PS ITG 3200A 00 01 4 Release Date 03 30 2010 y InvenSense ITG 3200 Product Specification Revision 1 4 ar 9 13 Storage Specifications The storage specification of the ITG 3200 gyroscope conforms to IPC JEDEC J STD 020C Moisture Sensitivity Level MSL 3 Storage Specifications for ITG 3200 Calculated shelf life in moisture sealed bag 12 months Storage conditions lt 40 C and lt 90 RH After opening moisture sealed bag 168 hours Storage conditions ambient lt 30 C at 60 RH 37 of 39 InvenSens 10 Reliability 10 1 Document Number PS ITG 3200A 00 01 4 ITG 3200 Product Specification Revision 1 4 Release Date 03 30 2010 Qualification Test Policy InvenSense s products complete a Qualification Test Plan before being released to production The Qualification Test Plan follows the JEDEC 47D Standards Stress Test Driven Qualification of Integrated Circuits with the individual tests described below 10 2 Qualification Test Plan Accelerated Life Tests S Acc TEST Method Condition m Reject y Criteria High Temperature JEDEC JESD22 A108C Dynamic 3 63V biased Tj gt 125 C 3 77 0 1 Operating Life HTOL LFR read points 168
91. Used in Strong Magnetic Field Environments with a 1 to 2 Degree Compass Heading Accuracy Compassing Heading Hard Iron Soft Iron and Auto Calibration Libraries Available Enables Pedestrian Navigation and LBS Applications HMC5883L SPECIFICATIONS Tested at 25 except stated otherwise Characteristics Conditions Min Typ Max Units Power Supply Supply Voltage VDD Referenced to AGND 2 16 2 5 3 6 Volts VDDIO Referenced to DGND 1 71 1 8 VDD 0 1 Volts Average Current Draw Idle Mode 2 pA Measurement Mode 7 5 Hz ODR 100 uA No measurement average MA1 MAO 00 VDD 2 5V VDDIO 1 8V Dual Supply VDD VDDIO 2 5V Single Supply Performance Field Range Full scale FS 8 8 gauss Mag Dynamic Range 3 bit gain control E 8 gauss Sensitivity Gain VDD 3 0V GN 0 to 7 12 bit ADC 230 1370 LSb gauss Digital Resolution VDD 3 0V GN 0 to 7 1 LSb 12 bit ADC 0 73 4 35 milli gauss Noise Floor VDD 3 0V GN 0 No measurement 2 milli gauss Field Resolution average Standard Deviation 100 samples See typical performance graphs below Linearity 2 0 gauss input range 0 1 FS Hysteresis 2 0 gauss input range 25 ppm Cross Axis Sensitivity Test Conditions Cross field 0 5 gauss 0 2 FS gauss Happlied 3 gauss Output Rate ODR Continuous Measurment Mode 0 75 75 Hz Single Measurement Mode 160 Hz Measurement Period From re
92. accurate measurement of magnetic field in any orientation Self Test To check the HMC5883L for proper operation a self test feature in incorporated in which the sensor is internally excited with a nominal magnetic field in either positive or negative bias configuration This field is then measured and reported This function is enabled and the polarity is set by bits MS n in the configuration register A An internal current source generates DC current about 10 mA from the VDD supply This DC current is applied to the offset straps of the magneto resistive sensor which creates an artificial magnetic field bias on the sensor The difference of this measurement and the measurement of the ambient field will be put in the data output register for each of the three axes By using this built in function the manufacturer can quickly verify the sensor s full functionality after the assembly without additional test setup The self test results can also be used to estimate compensate the sensor s sensitivity drift due to temperature For each self test measurement the ASIC 1 Sends a Set pulse 2 Takes one measurement M1 3 Sends the 10 mA offset current to generate the 1 1 Gauss offset field and takes another measurement M2 4 Puts the difference of the two measurements in sensor s data output register Output M2 M1 i e output offset field only See SELF TEST OPERATION section later in this datasheet for additional
93. any of the partici pating axes exceeds the threshold For inactivity detection all participating axes are logically ANDed causing the inactivity function to trigger only if all participating axes are below the threshold for the specified time Register 0x28 THRESH FF Read Write The THRESH FF register is eight bits and holds the threshold value in unsigned format for free fall detection The acceleration on all axes is compared with the value in THRESH to determine if a free fall event occurred The scale factor is 62 5 mg LSB Note that a value of 0 mg may result in undesirable behavior if the free fall interrupt is enabled Values between 300 mg and 600 mg 0x05 to 0x09 are recommended Register 0x29 TIME FF Read Write The TIME FF register is eight bits and stores an unsigned time value representing the minimum time that the value of all axes must be less than FF to generate a free fall interrupt The scale factor is 5 ms LSB A value of 0 may result in undesirable behavior if the free fall interrupt is enabled Values between 100 ms and 350 ms 0x14 to 0x46 are recommended Register OX2A TAP AXES Read Write ADXL345 Asleep Bit A setting of 1 in the asleep bit indicates that the part is asleep and a setting of 0 indicates that the part is not asleep This bit toggles only if the device is configured for auto sleep See the AUTO SLEEP Bit section for more information on autosleep mode Regis
94. basing on the gain setting used See an example below Then All 3 axes pass positive self test Write CRA 00 send Ox3C 0x00 0x70 Exit self test mode and this procedure NANA Else If Gain lt 7 Write CRB 01 send Ox3C 0x01 Ox 0 Increase gain setting and retry skip the next data set Else At least one axis did not pass positive self test Write CRA 00 send 0x3C 0 00 0 70 Exit self test mode and this procedure End If Below is an example of how to adjust the positive self test limits basing on the gain setting 1 If Gain 6 self test limits are Low Limit 243 330 390 206 High Limit 575 330 390 487 2 f Gain 7 self test limits are Low Limit 243 230 390 143 High Limit 575 230 390 339 www honeywell com 19 HMC5883L SCALE FACTOR TEMPERATURE COMPENSATION The built in self test can also be used to periodically compensate the scaling errors due to temperature variations A compensation factor can be found by comparing the self test outputs with the ones obtained at a known temperature For example if the self test output is 400 at room temperature and 300 at the current temperature then a compensation factor of 400 300 should be applied to all current magnetic readings A temperature sensor is not required using this method Below is an example of a temperature compensation process using positive self test method 1 If self test measurement at a temperature when the last m
95. capable of delivering a large but brief pulse to the Set Reset strap of the sensor This strap is largely a resistive load There is no need for an external Set Reset circuit The controlling of the Set Reset function is done automatically by the ASIC for each measurement One half of the difference from the measurements taken after a set pulse and after a reset pulse will be put in the data output register for each of the three axes By doing so the sensor s internal offset and its temperature dependence is removed cancelled for all measurements The set reset pulses also effectively remove the past magnetic history magnetism in the sensor if any For each measurement the ASIC Sends a Set pulse Takes one measurement Mset Sends a Reset pulse Takes another measurement Mreset Puts the following result in sensor s data output register UE CO Nose Output Mset Mreset 2 Charge Current Limit The current that reservoir capacitor C1 can draw when charging is limited for both single supply and dual supply configurations This prevents drawing down the supply voltage VDD MODES OF OPERATION This device has several operating modes whose primary purpose is power management and is controlled by the Mode Register This section describes these modes Continuous Measurement Mode During continuous measurement mode the device continuously makes measurements at user selectable rate and places measured data i
96. ciclo noRT min int t ciclo noRT max variables float proportional roll float integral roll float derivative roll float error roll float variacion error roll float error old1 roll float error old2 roll float error old3 roll float out old roll float kp roll float ki roll float kd roll entradas float reference roll float roll salidas float out roll pid_roll c pid_roll c 11 06 2014 Regulador PID para el angulo roll Eugenio Alcal Baselga Hinclude lt stdio h gt include lt string h gt include lt math h gt include runtime h include pid_roll h ifdef ID LISTAS struct lista instancias pid roll else define MAX_pid_roll 16 struct pid_roll instancias_pid_roll MAX_pid_roll endif struct componente clase_pid_roll extern char msgLog extern float fdummy 46 gt lt gt lt a k ls ls ls ds ls ls ls ls le le k kk k k k K k k f lt K k gt e void inicializa_propiedades O void inicializa propiedades pid roll void instancia char nombre int orden unsigned char habilitado struct pid roll este struct pid roll instancia strcpy este gt nombre nombre este gt orden orden este gt habilitado habilitado este gt finalizado 0 principio inicializaci n de propiedades espec ficas pid_roll este gt reference_roll amp fdummy este gt roll amp fdu
97. control applications The part features enhanced bias and sensitivity temperature stability reducing the need for user calibration Low frequency noise is lower than previous generation devices simplifying application development and making for more responsive remote controls The ITG 3200 features three 16 bit analog to digital converters ADCs for digitizing the gyro outputs a user selectable internal low pass filter bandwidth and a Fast Mode re 400kHz interface Additional features include an embedded temperature sensor and a 2 accurate internal oscillator This breakthrough in gyroscope technology provides a dramatic 67 package size reduction delivers a 50 power reduction and has inherent cost advantages compared to competing multi chip gyro solutions By leveraging its patented and volume proven Nasiri Fabrication platform which integrates MEMS wafers with companion CMOS electronics through wafer level bonding InvenSense has driven the ITG 3200 package size down to a revolutionary footprint of 4x4x0 9mm while providing the highest performance lowest noise and the lowest cost semiconductor packaging required for handheld consumer electronic devices The part features a robust 10 000g shock tolerance as required by portable consumer equipment For power supply flexibility the ITG 3200 has a separate VLOGIC reference pin in addition to its analog supply pin VDD which sets the logic levels of its interface The VLOGIC
98. control is possible when the oscillator is off 4 When the oscillator is off Sleep mode the LEDn outputs cannot be turned on off or dimmed blinked 9685 All information provided this document is subject to legal disclaimers NXP B V 2010 All rights reserved Product data sheet Rev 3 2 September 2010 13 of 51 Semiconductors 9685 7 3 1 1 16 channel 12 bit PWM 2 LED controller Restart mode Ifthe PCA9685 is operating and the user decides to put the chip to sleep setting MODE1 bit 4 without stopping any of the PWM channels the RESTART bit MODE 1 bit 7 will be set to logic 1 at the end of the PWM refresh cycle The contents of each PWM register are held valid when the clock is off To restart all of the previously active PWM channels with a few I C bus cycles do the following steps 1 Read register 2 Check that bit 7 RESTART is a logic 1 If itis clear bit 4 SLEEP Allow time for oscillator to stabilize 500 us 3 Write logic 1 to bit 7 of MODE1 register All PWM channels will restart and the RESTART bit will clear Remark The SLEEP bit must be logic 0 for at least 500 us before a logic 1 is written into the RESTART bit Other actions that will clear the RESTART bit are 1 Power cycle 2 12C Software Reset command 3 If the MODE2 OCH bit is logic 0 write to any PWM register then issue an 2 STOP 4 If the MODE2 OCH bit
99. controlled by the SPI master This line must go low at the start of a transmission and high at the end of a transmission as shown in Figure 37 SCLK is the serial port clock and is supplied by the SPI master SCLK should idle high during a period of no transmission SDI and SDO are the serial data input and output respectively Data is updated on the falling edge of SCLK and should be sampled on the rising edge of SCLK ADXL345 To read or write multiple bytes in a single transmission the multiple byte bit located after the R W bit in the first byte transfer MB in Figure 37 to Figure 39 must be set After the register addressing and the first byte of data each subsequent set of clock pulses eight clock pulses causes the ADXL345 to point to the next register for a read or write This shifting continues until the clock pulses cease and CS is deasserted To perform reads or writes on different nonsequential registers CS must be deasserted between transmissions and the new register must be addressed separately The timing diagram for 3 wire SPI reads or writes is shown in Figure 39 The 4 wire equivalents for SPI writes and reads are shown in Figure 37 and Figure 38 respectively For correct operation of the part the logic thresholds and timing parameters in Table 9 and Table 10 must be met at all times Use of the 3200 Hz and 1600 Hz output data rates is only recommended with SPI communication rates greater than or equal to 2 MHz
100. conventional or mass destructive weapons or for any other weapons or life threatening applications as well as in any other life critical applications such as medical equipment transportation aerospace and nuclear instruments undersea equipment power plant equipment disaster prevention and crime prevention equipment InvenSense InvenSense logo ITG and ITG 3200 are trademarks of InvenSense Inc 2009 InvenSense Inc rights reserved 39 of 39 3 Axis Digital Compass HMC5883L Honeywell Advanced Information The Honeywell HMC5883L is a surface mount multi chip module designed for low field magnetic sensing with a digital interface for applications such as low cost compassing and magnetometry The HMC5883L includes our state of the art high resolution HMC118X series magneto resistive sensors plus an ASIC containing amplification automatic degaussing strap drivers offset cancellation and a 12 bit ADC that enables 1 to 2 compass heading accuracy The C serial bus allows for easy interface The HMC5883L is a 3 0x3 0x0 9mm surface mount 16 pin leadless chip carrier LCC Applications for the HMC5883L include Mobile Phones Netbooks Consumer Electronics Auto Navigation Systems and Personal Navigation Devices The HMC5883L utilizes Honeywell s Anisotropic Magnetoresistive AMR technology that provides advantages over other magnetic sensor technologies These anisotropic directional sensors feature pre
101. data output register B These registers store the measurement result from channel X Data output X register A contains the MSB from the measurement result and data output X register B contains the LSB from the measurement result The value stored in these two registers is a 16 bit value 2s complement form whose range is OxF800 to 0 07 DXRAO through DXRA7 and DXRBO through DXRB7 indicate bit locations with and DXRB denoting the bits that are in the data output X registers DXRA7 and DXRB7 denote the first bit of the data stream The number in parenthesis indicates the default value of that bit In the event the ADC reading overflows or underflows for the given channel or if there is a math overflow during the bias measurement this data register will contain the value 4096 This register value will clear when after the next valid measurement is made DXRA7 DXRA6 DXRA5 DXRA4 DXRA3 DXRA2 DXRA1 DXRAO Table 13 Data Output X Registers A and B Data Output Y Registers A and B The data output Y registers are two 8 bit registers data output register A and data output register B These registers store the measurement result from channel Y Data output Y register A contains the MSB from the measurement result and data output Y register B contains the LSB from the measurement result The value stored in these two registers is 16 bit value 2s complement form whose range is O
102. during reflow soldering see Figure 38 PCA9685 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Product data sheet Rev 3 2 September 2010 46 of 51 NXP Semiconductors PCA9685 16 channel 12 bit PWM 2 LED controller temperature maximum peak temperature MSL limit damage level minimum peak temperature minimum soldering temperature peak temperature time 001 844 MSL Moisture Sensitivity Level Fig 38 Temperature profiles for large and small components For further information on temperature profiles refer to Application Note AN10365 Surface mount reflow soldering description 18 Abbreviations 9685 Table 18 Abbreviations Acronym CDM DUT EMI ESD HBM 12C bus LCD LED LSB MM MSB NMOS PCB PMOS POR PWM RGB RGBA SMBus Description Charged Device Model Device Under Test ElectroMagnetic Interference ElectroStatic Discharge Human Body Model Inter Integrated Circuit bus Liquid Crystal Display Light Emitting Diode Least Significant Bit Machine Model Most Significant Bit Negative channel Metal Oxide Semiconductor Printed Circuit Board Positive channel Metal Oxide Semiconductor Power On Reset Pulse Width Modulation Pulse Width Modulator Red Green Blue Red Green Blue Amber System Management Bus Alli information provided i
103. este gt t_ciclo_noRT_max 0 este gt offset_acc_x 0 08 este gt offset_acc_y 0 04 este gt offset_acc_z 0 02 principio c digo espec fico funcion inicializa acelerometro if ioctl este gt fd 2 SLAVE ADXL345_I2C_ADDR lt 0 fprintf stderr Acelerometer is not present n writetodisp este gt fd ADXL345 POWER CTL 0x00 writetodisp este gt fd ADXL345 POWER 0x08 Habilitamos el modo de medicion continua writetodisp este gt fd ADXL345 DATA FORMAT 0x00 writetodisp este gt fd ADXL345 DATA FORMAT 0x01 Configuramos el modo de 10 bits y 4g fin c digo espec fico funcion inicializa acelerometro j polo ol fe o o k k k gt lt K k void funcionNormal NO void funcion normal acelerometro void instancia int t ciclo struct acelerometro este struct acelerometro instancia ttifdef LOG sprintf msgLog Normal function 96s este gt nombre logPrint msgLog 6 endif struct timespec ts crononsec 1 amp ts principio c digo espec fico funcion normal acelerometro if ioctl este gt fd I2C SLAVE ADXL345 DC ADDR lt 0 fprintf stderr Acelerometer is not present n este gt buf 0 0x32 del primer registro if write este gt fd este gt buf 1 1 fprintf stderr Error al escribir en el esclavo 12c n if read este gt fd este gt buf 6 6 fprintf stderr Unabl
104. este 5t ciclo RT k k K K k K K K void funcionNormalNoRT O void funcion normal noRT microPWM void instancia int t ciclo struct microPWM este struct microPWM instancia ifdef LOG sprintf msgLog Normal function 96s este gt nombre logPrint msgLog 6 endif struct timespec ts crononsec 1 amp ts principio c digo espec fico funcion normal noRT microPWM fin c digo espec fico funcion normal noRT microPWM gt ciclo noRT 0 amp ts if este 5t ciclo noRT gt gt ciclo noRT max este 5t ciclo noRT max este t ciclo noRT else if este gt t_ciclo_noRT lt gt ciclo noRT min gt ciclo noRT min este 5t ciclo noRT k k k k k K k k void funcionFinaliza IO void funcion_finaliza_microPWM void instancia struct microPWM este struct microPWM instancia ifdef LOG sprintf msgLog Finalizing 96s este gt nombre logPrint msgLog 3 endif principio c digo espec fico funcion finaliza microPWM if ioctl este gt fd DC SLAVE PCA9685 DC ADDR lt 0 strcpy este error msg micro PWM 9685 15 not present n setPWM este gt fd 4 0 1710 setPWM este gt fd 2 0 1710 setPWM este gt fd 8 0 1710 setPWM este gt fd 10 0 1710 close este gt fd fin c digo espec fico funcion finaliza microPWM ol o o
105. for LED12 4 MSBs 38h LED12 OFF_L 7 0 LED12 OFF 7 0 R W 0000 0000 LEDn OFF count for LED12 8 LSBs 39h LED12 OFF H 7 5 reserved R 000 non writable 4 LED12 OFF 4 R W 1 LED12 full OFF 30 1 012 OFF_H 3 0 R W 0000 LEDn OFF count for LED12 4 MSBs 3Ah LED13 ON L 70 1 013 ON 7 0 R W 0000 0000 LEDn ON count for LED13 8 LSBs 3Bh LED13_ON_H 7 5 reserved R 000 non writable 4 LED13 ON H 4 R W 0 LED13 full ON 3 0 1 013 ON H 3 0 R W 0000 LEDn_ON count for LED13 4 MSBs PCA9685 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Product data sheet Rev 3 2 September 2010 22 of 51 NXP Semiconductors PCA9685 16 channel 12 bit PWM 2 LED controller LED ON LED OFF control registers address 06h to 45h bit description continued Table 6 Legend default value Address Register Bit 3Ch LED13 OFF L 7 0 3Dh LED13 OFF 7 5 4 3 0 3Eh LED14 ON L 7 0 3Fh LEDI4 ON H 75 4 3 0 40h LED14 OFF L 7 0 41h LED14 OFFH 7 5 4 3 0 42h LED15 ON L 7 0 43h LED15_ON_H 7 5 4 3 0 44h LED15_OFF_L 7 0 45h LED15 7 5 4 3 0 Symbol Access LED13_OFF_L 7 0 R W reserved R LED13 OFF H 4 R W LED13_OFF_H 3 0 R W LED14 ON _L 7 0 R W reserved R LED14 ON H 4 R W LED14 ON H 3 0 R W LED14 OFF L 7 0 R W reserved R LED14 OFF H 4 R W LED14_OFF_H 3 0 R W LED15 ON 7 0 R W reserved R LED15 ON H 4 R W LED15 ON H 3
106. funcionFinaliza funcion_finaliza_acelerometro ifdef ID_LISTAS iniciarLista amp instancias_acelerometro else clase_acelerometro n 0 clase_acelerometro maxNumComp MAX_acelerometro endif clase_acelerometro instancias amp instancias_acelerometro clase_acelerometro longComponente sizeof struct acelerometro return insertarPropiedad2 ID_ COMPONENTE ID_acelerometro amp clase acelerometro ID COMPONENTE NO MODIFICABLE j GIROSCOPO giroscopo h giroscopo h 11 06 2014 Eugenio Alcal Baselga Variables utilizadas en giroscopo c Hinclude cosme h define ID_giroscopo giroscopo define MAX_giroscopo 16 define ITG3200_I2C_ADDR 0x68 define ITG3200 PWR MGM 0x3e define ITG3200_SMPLRT_DIV 0x15 define ITG3200 DLPF FS 0x16 define ITG3200 INT 0x17 define ITG3200 GYRO Oxld define ITG3200 GYRO YOUT H Ox1f define ITG3200 GYRO ZOUT 0x21 define ERR MSG 100 define EJES 3 define LSB 14 375 define GRADOS_RADIANES 0 017453293 define ID_SAL_GIRO 0 define ID ENT GIRO 1 struct giroscopo char nombre MAX LONG NOMBRE int orden byte habilitado byte finalizado int t ciclo RT int t ciclo RT min int t ciclo max int t ciclo noRT int t ciclo noRT min int t ciclo noRT max variables int cont char error msg giro MAX ERR MSG float offsetGyro_x offsetGyro_y offsetGyro_z short x y 2 unsi
107. i for j 0 j lt MAX EJES j insertarPropiedad3 este gt nombre amp este dcm matriz renorm 1 i j ID ENT FLOAT PUBLICO MODIFICABLE dcm matriz renorm 1 946d 96d i j insertarPropiedad3 este gt nombre amp este Omega P Compass 2 ID VAR FLOAT PUBLICO MODIFICABLE Omega P Compass insertarPropiedad3 este gt nombre amp este Omega I Compass 2 ID VAR FLOAT PUBLICO MODIFICABLE Omega I Compass insertarPropiedad3 este gt nombre amp este gt Kp_Yaw ID VAR FLOAT PUBLICO MODIFICABLE Kp Yaw insertarPropiedad3 este gt nombre amp este gt Ki_Yaw ID VAR FLOAT PUBLICO MODIFICABLE Ki Yaw fin registro de propiedades espec ficas correccionPI Mag j 46 gt e gt lt void funcionCrea IO int funcion crea correccionPI Mag void instancia char nombre int orden unsigned char habilitado f struct correccionPI Mag este struct correccionPI Mag instancia ifdef LOG sprintf msgLog Creating s nombre logPrint msgLog 3 endif inicializa_propiedades_correccionPI_Mag instancia nombre orden habilitado if registra_propiedades_correccionPI_Mag instancia 0 ifdef LOG sprintf msgLog 46s V Registering properties of s ID ERROR este gt nombre logPrint msgLog 1 endif if registrarInstancia instancia nombre amp clase correccionPI Mag orden amp este gt habilitado amp este
108. i lt MAX EJES i for 0 0 j lt MAX_EJES j insertarPropiedad3 este gt nombre amp este gt Matriz_Cambio 1 j ID VAR FLOAT PUBLICO MODIFICABLE Matriz_Cambio d d i j for i 0 i lt MAX EJES i for j 0 j lt MAX EJES j insertarPropiedad3 este gt nombre amp este matriz temporal i j ID VAR FLOAT PUBLICO MODIFICABLE matriz temporal 96d 96d i j for i 0 i lt MAX_EJES i insertarPropiedad3 este gt nombre amp este gt W gyr_fin i ID_ENT_FLOAT PUBLICO MODIFICABLE Weyr_fin d 1 for 0 i lt MAX EJES i insertarPropiedad3 este gt nombre amp este gt acumula i ID VAR FLOAT PUBLICO MODIFICABLE acumula d i insertarPropiedad3 este gt nombre amp este time muestreo ID FLOAT PUBLICO MODIFICABLE time muestreo insertarPropiedad3 este gt nombre amp este calibracion giro ID ENT INT PUBLICO MODIFICABLE calibracion giro fin registro de propiedades espec ficas actualizar matriz 46 gt lt gt lt k k k k k k k k k k kk k k k k k k k k kk k KK k k K k k K K K void funcionCrea IO int funcion crea actualizar matriz void instancia char nombre int orden unsigned char habilitado struct actualizar matriz este struct actualizar matriz instancia ifdef LOG sprintf msgLog Creating s nombre logPrint msgLog 3 endif inicializa_
109. in FIFO Access to collect the data from FIFO is provided through the DATAX DATAY and DATAZ registers FIFO reads must be done in burst or multiple byte mode because each FIFO level is cleared after any read single or multiple byte of FIFO FIFO stores a maximum of 32 entries which equates to a maximum of 33 entries available at any given time because an additional entry is available at the output filter of the device Rev D Page 27 of 40 ADXL345 APPLICATIONS INFORMATION POWER SUPPLY DECOUPLING 1 uF tantalum capacitor Cs at Vs and a 0 1 uF ceramic capacitor Cro at placed close to the ADXL345 supply pins is recommended to adequately decouple the accelerometer from noise on the power supply If additional decoupling is necessary a resistor or ferrite bead no larger than 100 in series with Vs may be helpful Additionally increasing the bypass capacitance on Vs to a 10 uF tantalum capacitor in parallel with a 0 1 uF ceramic capacitor may also improve noise Care should be taken to ensure that the connection from the ADXL345 ground to the power supply ground has low impedance because noise transmitted through ground has an effect similar to noise transmitted through Vs It is recommended that Vs and Vop vo be separate supplies to minimize digital clocking noise on the Vs supply If this is not possible additional filtering of the supplies as previously mentioned may be necessary Vs Vpp vo Vpp 1
110. insertarPropiedad3 este gt nombre amp este gt error ID_VAR_FLOAT PUBLICO MODIFICABLE error fin registro de propiedades espec ficas renormalizar 8 gt e gt lt A A 2 2 2 2 o o oe 2 gt lt 2 k os os ls ls ls ls ls ls ls ls void funcionCrea II int funcion_crea_renormalizar void instancia char nombre int orden unsigned char habilitado f struct renormalizar este struct renormalizar instancia ifdef LOG sprintf msgLog Creating s nombre logPrint msgLog 3 endif inicializa_propiedades_renormalizar instancia nombre orden habilitado if registra propiedades renormalizar instancia 0 ifdef LOG sprintf msgLog 46s V Registering properties of s ID ERROR este gt nombre logPrint msgLog 1 endif if registrarInstancia instancia nombre amp clase renormalizar orden amp este gt habilitado amp este gt finalizado 0 1 ifdef LOG sprintf msgLog 96s V Registering instance s ID ERROR este gt nombre logPrint msgLog 1 endif 346 gt e gt lt k k k k kkk kkk k k k K k K K k void funcionInicializa O void funcion_inicializa_renormalizar void instancia struct renormalizar este struct renormalizar instancia ttifdef LOG sprintf msgLog Initializing 95 este gt nombre logPrint msgLog 3 endif este gt t_ciclo_RT_min 0x 10000000 este 5t ciclo RT max 0
111. interrupt is enabled Register 0x25 THRESH_INACT Read Write The THRESH_INACT register is eight bits and holds the threshold value for detecting inactivity The data format is unsigned so the magnitude of the inactivity event is compared with the value in the THRESH_INACT register The scale factor is 62 5 mg LSB A value of 0 may result in undesirable behavior if the inactivity interrupt is enabled Register 0 26 Read Write The TIME_INACT register is eight bits and contains an unsigned time value representing the amount of time that acceleration must be less than the value in the THRESH_INACT register for inactivity to be declared The scale factor is 1 sec LSB Unlike the other interrupt functions which use unfiltered data see the Threshold section the inactivity function uses filtered output data At least one output sample must be generated for the inactivity interrupt to be triggered This results in the function appearing unresponsive if the TIME_INACT register is set to a value less than the time constant of the output data rate A value of 0 results in an interrupt when the output data is less than the value in the THRESH_INACT register Register 0x27 ACT_INACT_CTL Read Write D7 D6 D5 D4 ACT ac dc ACT_X enable ACT_Y enable ACT_Z enable D3 D2 D1 DO INACT ac dc INACT_X enable INACT Y enable INACT_Z enable ACT AC DC and INACT AC DC Bits A setting of 0 selects
112. is required devices may be baked for 48 hours at 125 5 C Note If device containers cannot be subjected to high temperature or shorter bake times are desired reference IPC JEDEC J STD 033 for bake procedure Bag Seal Date blank bar code Note Level and body temperature defined by IPC JEDEC J STD 020 Moisture Sensitive Caution Label 33 of 39 Document Number PS ITG 3200A 00 01 4 5 Z Revision 1 4 InvenSense ITG 3200 Product Specification Ras ise asia 9 7 Soldering Exposed Die Pad 3200 has very low active and standby current consumption The exposed die pad is not required for heat sinking and should not be soldered to the PCB since soldering to it contributes to performance changes due to package thermo mechanical stress 9 8 Component Placement Testing indicates that there are no specific design considerations other than generally accepted industry design practices for component placement near the ITG 3200 multi axis gyroscope to prevent noise coupling and thermo mechanical stress 9 9 Mounting and Cross Axis Sensitivity Orientation errors of the gyroscope mounted to the printed circuit board can cause cross axis sensitivity in which one gyro responds to rotation about another axis for example the X axis gyroscope responding to rotation about the Y or Z axes The orientation mounting errors are illustrated in the figure below Package Gyro
113. k k K k k gt e K K void inicilizamicroPWM NON int inicializa_microPWM ifdef LOG sprintf msgLog Initializing s ID_microPWM logPrint msgLog 3 endif clase_microPWM funcionCrea funcion_crea_microPWM clase microPWM funcionlnicializa funcion inicializa microPWM clase microPWM funcionNormal funcion normal microPWM clase microPWM funcionNormalNoRT funcion normal noRT microPWM clase microPWM funcionFinaliza funcion finaliza microPWM ifdef ID LISTAS iniciarLista amp instancias microPWM else clase microPWM n 0 clase microPWM maxNumComp MAX_microPWM endif clase microPWM instancias amp instancias_microPWM clase_microPWM longComponente sizeof struct microPWM return insertarPropiedad2 ID COMPONENTE ID_microPWM amp clase microPWM ID COMPONENTE NO MODIFICABLE CONEXIONES DE LOS COMPONENTES lt xml version 1 0 encoding UTF 8 standalone no gt lt cosme version 3 2 gt lt date gt lt author gt lt version gt lt description gt lt VERSION_IDE gt lt cicle_time gt lt project_constants gt lt project_variables gt lt exec_sequences gt lt layers gt lt tabs gt lt instances gt lt instance gt instance name i2cl instance name component SISTEMA COMPONENTE i2c component specific component creation date order 1 order collapsed default location lt tabs gt lt enabled gt true lt enab
114. k k k k k k k k k kK K k K K K k K K K void funcionNormal O void funcion_normal_microPWM void instancia int t_ciclo struct microPWM este struct microPWM instancia ifdef LOG sprintf msgLog Normal function 96s este gt nombre logPrint msgLog 6 endif struct timespec ts crononsec 1 amp ts principio c digo espec fico funcion normal microPWM if ioctl este gt fd I2C SLAVE PCA9685 I2C ADDR lt 0 strcpy este error msg micro PWM 9685 is not presenti j if este gt condicion 0 setPWM este gt fd 4 0 1710 setPWM este gt fd 2 0 1710 setPWM este gt fd 8 0 1710 setPWM este gt fd 10 0 1710 else if este gt condicion 1 setPWM este gt fd 4 0 este gt pwm_motor_grisl setPWM este gt fd 2 0 este gt pwm_motor_gris2 setPWM este fd 8 0 este pwm motor negrol setPWM este fd 10 0 este pwm motor negro2 else if este gt condicion 2 setPWM este gt fd 4 0 este gt ciclo_pwm setPWM este gt fd 2 0 este gt ciclo_pwm setPWM este gt fd 8 0 este gt ciclo_pwm setPWM este gt fd 10 0 este gt ciclo_pwm fin c digo espec fico funcion normal microPWM gt ciclo RT 0 amp ts if este 5t ciclo RT gt este t ciclo max gt ciclo RT max este 5t ciclo RT else if este gt t_ciclo_RT lt este gt t_ciclo_RT_min este gt t_ciclo_RT_min
115. logPrint msgLog 3 endif clase correccionPI Mag funcionCrea funcion crea correccionPI Mag clase correccionPI Mag funcionlInicializa funcion inicializa correccionPI Mag clase correccionPI Mag funcionNormal funcion normal correccionPI Mag clase correccionPI Mag funcionNormalNoRT funcion normal noRT correccionPI Mag clase correccionPI Mag funcionFinaliza funcion finaliza correccionPI Mag ifdef ID LISTAS iniciarLista amp instancias correccionPI Mag else clase correccionPI Mag n 0 clase correccionPI Mag maxNumComp MAX correccionPI Mag endif clase correccionPI Mag instancias amp instancias correccionPI Mag clase correccionPI Mag longComponente sizeof struct correccionPI Mag return insertarPropiedad2 ID COMPONENTE ID correccionPI Mag amp clase correccionPI Mag ID COMPONENTE NO MODIFICABLEB j INSTANCIA QUE ACTUALIZA LA MATRIZ DE ROTACI N actualizar_matriz h actualizar_matriz h Variables utilizadas en actualizar_matriz c 11 06 2014 Eugenio Alcal Baselga Hinclude cosme h define ID_actualizar_matriz actualizar matriz Hdefine MAX_actualizar_matriz 16 define MAX_EJES 3 struct actualizar matriz char nombre MAX LONG NOMBRE int orden byte habilitado byte finalizado int t ciclo RT int t ciclo RT min int t ciclo max int t ciclo noRT int t ciclo noRT min int t ciclo noRT max variables float Matriz Cambio MAX EJES MAX EJES float
116. ls ls ds ls ls ls le le le k k k k k k k kk k kK k k fe K k gt e K K void funcionNormal O void funcion_normal_promediador void instancia int t_ciclo struct promediador este struct promediador instancia fifdef LOG sprintf msgLog Normal function 96s este gt nombre logPrint msgLog 6 endif struct timespec ts crononsec 1 amp ts principio c digo espec fico funcion normal promediador int nj if gt dato pitch 1 for n 0 n lt MAX_PROMEDIO n Llenamos la matriz con el primer dato recibido este gt vector_filtro_roll n este gt Wgyr_modif 0 este gt vector_filtro_pitch n este gt Wgyr_modif 1 este gt primer_dato_pitch 0 Para que no vuelva a entrar en el bucle anterior Promediado Pitch este gt acumula_filtrado_pitch 0 for 1 0 i lt MAX PROMEDIO 1 1 Movemos solo los 7 primeros este gt vector_filtro_pitch i este gt vector_filtro_pitch i 1 este gt acumula_filtrado_pitch este gt acumula_filtrado_pitch este gt vector_filtro_pitch i Suma los 8 valores que hay en el filtro este vector filtro pitch MAX PROMEDIO 1 este gt Wegyr_modif 1 Aniadimos el ULTIMO este gt acumula_filtrado_pitch este gt acumula_filtrado_pitch este vector filtro pitch MAX PROMEDIO 1 este acumula filtrado pitch este acumula filtrado pitch MAX PROMEDIO este gt W gy
117. lt creation_date gt lt order gt 6 lt order gt lt collapsed gt lt default_location gt lt tabs gt lt enabled gt true lt enabled gt lt instance gt lt instance gt lt instance_name gt correccionPI_Mag1 lt instance_name gt lt component gt SISTEMA COMPONENTE correccionPI_Mag lt component gt lt specific_component gt lt creation_date gt lt order gt 7 lt order gt lt collapsed gt lt default_location gt lt tabs gt lt enabled gt true lt enabled gt lt instance gt lt instance gt lt instance_name gt actualizar_matriz1 lt instance_name gt lt component gt SISTEMA COMPONENTE actualizar_matriz lt component gt lt specific_component gt lt creation_date gt lt order gt 8 lt order gt lt collapsed gt lt default_location gt lt tabs gt lt enabled gt true lt enabled gt lt instance gt lt instance gt instance name renormalizarl instance name component SISTEMA COMPONENTE renormalizar component specific component creation date lt order gt 9 lt order gt lt collapsed gt lt default_location gt lt tabs gt lt enabled gt true lt enabled gt lt instance gt lt instance gt instance name conversor angulosl instance name component SISTEMA COMPONENTE conversor angulosc component specific component creation date order 10 order collapsed default location lt tabs gt lt enabled gt true lt enable
118. lt input_resending gt lt input_type gt ID_ENT_FLOAT lt input_type gt lt input_dimensions gt lt output_resending gt lt output gt actualizar_matriz1 DCM_Matriz 2 1 lt output gt lt sequence_name gt lt connection_type gt lt connection gt lt connection gt lt input gt renormalizar1 DCM_Matriz 2 2 lt input gt lt input_resending gt lt input_type gt ID_ENT_FLOAT lt input_type gt lt input_dimensions gt lt output_resending gt lt output gt actualizar_matrizl DCM_Matriz 2 2 lt output gt lt sequence_name gt connection type connection connection input conversor angulosl dcm matriz renorm 0 0 input input resending input type ID ENT FLOAT input type input dimensions output resending output renormalizarl dcm matriz renorm 0 0 output sequence name connection type lt connection gt lt connection gt lt input gt conversor_angulos1 dcm_matriz_renorm 0 1 lt input gt lt input_resending gt lt input_type gt ID_ENT_FLOAT lt input_type gt lt input_dimensions gt lt output_resending gt lt output gt renormalizar1 dcm_matriz_renorm 0 1 lt output gt lt sequence_name gt lt connection_type gt lt connection gt lt connection gt lt input gt conversor_angulos1 dcm_matriz_renorm 0 2 lt input gt lt input_resending gt lt input_type gt ID_ENT_FLOAT lt input_type gt lt input_dimensions gt lt output_r
119. microPWM instancia nombre orden habilitado if registra propiedades microPWM instancia 0 ifdef LOG sprintf msgLog 96s V Registering properties of s ID ERROR este gt nombre logPrint msgLog 1 endif if registrarInstancia instancia nombre amp clase microPWM orden amp este gt habilitado amp este gt finalizado 0 1 ifdef LOG sprintf msgLog 96s V Registering instance s ID ERROR este gt nombre logPrint msgLog 1 endif void writeto_PCA9685 int fd int reg int val char buf 2 buf 0 reg buf 1 val if write fd buf 2 2 fprintf stderr No se puede escribir en el dispositivo 12c n void setPWM int fd int channel int on int off i2c smbus write byte data fd LEDO_ON_L 4 channel on amp OxFF 12 smbus write byte data fd LEDO 4 channel on gt gt 8 12 smbus write byte data fd LEDO OFF L 4 channel off amp OxFF 12 write byte data fd LEDO OFF 4 channel off gt gt 8 2 2 2 o o o gt lt k k k ls ls ls ds ls ls ls ls le le k kk k k k kkk f lt k k K void funcionInicializa E gt lt k k k k k void funcion_inicializa_microPWM void instancia struct microPWM este struct microPWM instancia fifdef LOG sprintf msgLog Initializing 95 este gt nombre logPrint msgLog 3 endif est
120. of 51 Semiconductors 9685 16 channel 12 bit PWM 2 LED controller SDA SCL MASTER MASTER MASTER TRANSMITTER RECEIVER TRANSMITTER TRANSMITTER RECEIVER RECEIVER RECEIVER 002 966 Fig 18 System configuration PCA9685 8 3 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited Each byte of eight bits is followed by one acknowledge bit The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse A slave receiver which is addressed must generate an acknowledge after the reception of each byte Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse set up time and hold time must be taken into account A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition data output 77 X by transmitter not acknowledg
121. or completing a design 2 The term short data sheet is explained in section Definitions 3 The product status of device s described in this document may have changed since this document was published and may differ in case of multiple devices The latest product status information is available on the Internet at URL http www nxp com 20 2 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information Short data sheet A short data sheet is an extract from a full data sheet with the same product type number s and title A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information For detailed and full information see the relevant full data sheet which is available on request via the local NXP Semiconductors sales office In case of any inconsistency or conflict with the short data sheet the full data sheet shall prevail Product specification The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer unless NXP Semiconductors and c
122. pickoff The resulting signal is amplified demodulated and filtered to produce a voltage that is proportional to the angular rate This voltage is digitized using individual on chip 16 bit Analog to Digital Converters ADCs to sample each axis The full scale range of the gyro sensors is preset to 2000 degrees per second s The ADC output rate is programmable up to a maximum of 8 000 samples per second down to 3 9 samples per second and user selectable low pass filters enable a wide range of cut off frequencies 16 of 39 Document Number PS ITG 3200A 00 01 4 y Z Revision 1 4 InvenSense ITG 3200 Product Specification Raso asia 5 4 Serial Communications Interface The ITG 3200 communicates to a system processor using the I C serial interface and the device always acts as a slave when communicating to the system processor The logic level for communications to the master is set by the voltage on the VLOGIC pin The LSB of the of the slave address is set by pin 9 ADO 5 5 Clocking The ITG 3200 has a flexible clocking scheme allowing for a variety of internal or external clock sources for the internal synchronous circuitry This synchronous circuitry includes the signal conditioning ADCS and various control circuits and registers An on chip PLL provides flexibility in the allowable inputs for generating this clock Allowable internal sources for generating the internal clock are e internal relaxatio
123. pwm motor negrol 0 este pwm motor negro2 0 este gt potencia 1800 fin c digo espec fico funcion inicializa cambio_magnitud void funcionNormal O void funcion normal cambio magnitud void instancia int t ciclo struct cambio magnitud este struct cambio magnitud instancia ifdef LOG sprintf msgLog Normal function 96s este gt nombre logPrint msgLog 6 endif struct timespec ts crononsec 1 amp ts principio c digo espec fico funcion normal cambio magnitud if este gt out_pitch gt 0 005 Il este out pitch lt 0 005 este pwm motor 91151 floor este gt potencia este out pitch 0 95 1 0 5 este pwm motor gris2 floor este gt potencia este out pitch 1 0 1 0 5 else este gt pwm_motor_gris1 este gt potencia este gt pwm_motor_gris2 este gt potencia if este gt out_roll gt 0 005 Il este gt out_roll lt 0 005 este gt pwm_motor_negrol floor este gt potencia este gt out_roll 0 98 1 0 5 este gt pwm_motor_negro2 floor este gt potencia este gt out_roll 1 02 1 0 5 else este gt pwm_motor_negrol este gt potencia este gt pwm_motor_negro2 este gt potencia if este pwm motor grisl gt 2800 este pwm motor grisl 2800 else if este gt pwm_motor_gris2 gt 2800 este gt pwm_motor_gris2 2800 else if este
124. range the test is considered successful Generally a part is considered to pass if the minimum magnitude of change is achieved However a part that changes by more than the maximum magnitude is not necessarily a failure Another effective method for using the self test to verify accel erometer functionality is to toggle the self test at a certain rate and then perform an FFT on the output The FFT should have a corresponding tone at the frequency the self test was toggled Using an FFT like this removes the dependency of the test on supply voltage and on self test magnitude which can vary within a rather wide range Rev D Page 31 of 40 ADXL345 DATA FORMATTING OF UPPER DATA RATES Formatting of output data at the 3200 Hz and 1600 Hz output data rates changes depending on the mode of operation full resolution or fixed 10 bit and the selected output range When using the 3200 Hz or 1600 Hz output data rates in full resolution or 2 g 10 bit operation the LSB of the output data word is always 0 When data is right justified this corresponds to Bit DO of the DATAxO register as shown in Figure 49 When data is left justified and the part is operating in 2 g 10 bit mode the LSB of the output data word is Bit D6 of the DATAXO register In full resolution operation when data is left justified the location of the LSB changes according to the selected output range DATAx1 REGISTER For a range of 2 g the LSB is Bit D6 of t
125. regular 2 slave address or as an LED All Call or LED Sub Call address Control register Following the successful acknowledgement of the slave address LED All Call address or LED Sub Call address the bus master will send a byte to the PCA9685 which will be stored in the Control register This register is used as a pointer to determine which register will be accessed 6756 0 54 oT oo 002aac826 reset state 00h Remark The Control register does not apply to the Software Reset 2 address Fig 6 Control register All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Product data sheet Rev 3 2 September 2010 8 of 51 Semiconductors 9685 16 channel 12 bit PWM 2 LED controller 7 3 Register definitions Table 3 Register summary Register Register D7 06 D5 D4 D3 D2 D DO Name Type Function decimal hex 0 00 0 0 0 0 0 O O 0 MODE1 read write Mode register 1 1 01 0 0 0 0 0 O O 1 MODE2 read write Mode register 2 2 02 0 0 0 0 0 O 1 0 SUBADRI read write subaddress 1 3 03 0 0 0 0 0 O 1 1 SUBADR2 read write 12C bus subaddress 2 4 04 0 0 0 0 0 1 O 0 SUBADR3 read write 12C bus subaddress 5 05 0 0 0 0 0 1 O 1 ALLCALLADR read write LED All Call 12 address 6 06 o 0 0 0 0 1 1 0 LEDO ONL read write LEDO output and brightness control byte 0 7 07 0 0 0 0 0
126. resending input type ID ENT FLOAT input type input dimensions output resending lt output gt renormalizar1 dcm_matriz_renorm_1 2 1 lt output gt lt sequence_name gt lt connection_type gt lt connection gt lt connection gt lt input gt actualizar_matriz1 dcm_matriz_renorm_1 2 2 lt input gt lt input_resending gt lt input_type gt ID_ENT_FLOAT lt input_type gt lt input_dimensions gt lt output_resending gt lt output gt renormalizar1 dcm_matriz_renorm_1 2 2 lt output gt lt sequence_name gt lt connection_type gt lt connection gt lt connection gt lt input gt renormalizar1 dcm_matriz_1 0 0 lt input gt lt input_resending gt lt input_type gt ID_ENT_FLOAT lt input_type gt lt input_dimensions gt lt output_resending gt lt output gt actualizar_matriz1 dcm_matriz_1 0 0 lt output gt lt sequence_name gt lt connection_type gt lt connection gt lt connection gt lt input gt renormalizar1 dcm_matriz_1 0 1 lt input gt lt input_resending gt lt input_type gt ID_ENT_FLOAT lt input_type gt lt input_dimensions gt lt output_resending gt lt output gt actualizar_matriz1 dcm_matriz_1 0 1 lt output gt lt sequence_name gt lt connection_type gt lt connection gt lt connection gt input renormalizarl dcm matriz 1 0 2 input input resending input type ID ENT FLOAT input type input dimensions output resend
127. setting of 0 selects right justified mode with sign extension Range Bits These bits set the g range as described in Table 21 Table 21 g Range Setting Table 22 FIFO Modes Setting D7 D6 Mode Function 0 0 Bypass FIFO is bypassed 0 1 FIFO FIFO collects up to 32 values and then stops collecting data collecting new data only when FIFO is not full 1 0 Stream FIFO holds the last 32 data values When FIFO is full the oldest data is overwritten with newer data 1 1 Trigger When triggered by the trigger bit FIFO holds the last data samples before the trigger event and then continues to collect data until full New data is collected only when FIFO not full Setting D1 DO g Range 0 0 29 0 1 49 1 0 89 1 1 169 Register 0x32 to Register 0x37 DATAXO DATAX1 DATAYO DATAY1 DATAZO DATAZ1 Read Only These six bytes Register 0x32 to Register 0x37 are eight bits each and hold the output data for each axis Register 0x32 and Register 0x33 hold the output data for the x axis Register 0x34 and Register 0x35 hold the output data for the y axis and Register 0x36 and Register 0x37 hold the output data for the z axis The output data is twos complement with DATAXO as the least significant byte and DATAx1 as the most significant byte where x represent X Y or 7 The DATA FORMAT register Address 0x31 controls the format of the data It is recommended that a multiple byte
128. specific_component gt lt creation_date gt lt order gt 15 lt order gt lt collapsed gt lt default_location gt lt tabs gt lt enabled gt true lt enabled gt lt instance gt lt instances gt lt instance_components gt lt connections gt lt connection gt lt input gt acelerometro l fd lt input gt lt input_resending gt lt input_type gt ID_ENT_INT lt input_type gt lt input_dimensions gt lt output_resending gt lt output gt i2c 1 fd lt output gt lt sequence_name gt lt connection_type gt lt connection gt lt connection gt lt input gt acelerometro 1 bus_ok lt input gt lt input_resending gt lt input_type gt ID_ENT_INT lt input_type gt lt input_dimensions gt lt output_resending gt lt output gt 12c1 bus_ok lt output gt lt sequence_name gt lt connection_type gt lt connection gt connection input giroscopol fd input input resending input type ID ENT INT input type input dimensions output resending output i2c fd output sequence name connection type connection connection input giroscopol bus ok input input resending input type ID ENT INT input type input dimensions output resending lt output gt 12c1 bus_ok lt output gt lt sequence_name gt connection type connection connection input magnetometrol fd lt input gt input resending in
129. the SLEEP bit is set This bit is a sticky bit that is it cannot be cleared by writing a logic 0 to it The EXTCLK bit can only be cleared by a power cycle or software reset EXTCLK range is DC to 50 MHz EXTCLK refresh rate gt 4096 x prescale 1 0 Use internal clock 1 Use pin clock 5 Al R W 0 Register Auto Increment disabledl 1 Register Auto Increment enabled 4 SLEEP R W 0 Normal model l 1 Low power mode Oscillator off 3 4 3 SUB1 R W 0 9685 does not respond to I C bus subaddress 1 1 PCA9685 responds to 12 subaddress 1 2 SUB2 R W 0 PCA9685 does not respond to I C bus subaddress 2 1 PCA9685 responds to 12 subaddress 2 1 SUB3 R W 0 9685 does not respond to I C bus subaddress 3 9685 responds to 12 subaddress 3 0 ALLCALL R W 0 9685 does not respond to LED All Call 2 address 1 9685 responds to LED All Call 12C bus address When the Auto Increment flag is set Al 1 the Control register is automatically incremented after a read or write This allows the user to program the registers sequentially 2 It takes 500 us max for the oscillator to be up and running once SLEEP bit has been set to logic 0 Timings on LEDn outputs are not guaranteed if PWM control registers are accessed within the 500 us window There is no start up delay required when using the EXTCLK pin as the PWM clock 3 No PWM
130. to 3 6V 3 NC Not to be Connected 4 51 Tie to VDDIO 5 NC Not to be Connected 6 NC Not to be Connected 7 NC Not to be Connected 8 SETP Set Reset Strap Positive S R Capacitor C2 Connection 9 GND Supply Ground 10 C1 Reservoir Capacitor C1 Connection 11 GND Supply Ground 12 SETC S R Capacitor C2 Connection Driver Side 13 VDDIO IO Power Supply 1 71V to VDD 14 NC Not to be Connected 15 DRDY Data Ready Interrupt Pin Internally pulled high Optional connection Low for 250 usec when data is placed in the data output registers 16 SDA Serial Data Master Slave Data www honeywell com Table 1 Pin Configurations HMC5883L DRDY NC VDDIO lt Uu SCL SETE VDD GND C1 31 GND 8 O D O A Z 2 2 I 72 TOP VIEW looking through Arrow indicates direction of magnetic field that generates a positive output reading in Normal Measurement configuration PACKAGE OUTLINES PACKAGE DRAWING HMC5883L 16 PIN LPCC dimensions in millimeters 7 exe PIN 1 MARKER 0 325X0 250 16X 21 0 625 6 0 625 xe 0 90 L 3 00 _ d SIDE VIEW BOTTOM VIEW Dimensions in mm MOUNTING CONSIDERATIONS The following is the recommend printed circuit board PCB footprint for the HMC5883L 4 www honeywell com HMC5883L 0 450 gt 1 275 m E 0 500 12 m J 3 000 0 100 x 8
131. ts crononsec 1 amp ts principio c digo espec fico funcion normal noRT promediador I fin c digo espec fico funcion normal noRT promediador este gt t_ciclo_noRT 0 amp ts if este gt t_ciclo_noRT gt este gt t_ciclo_noRT_max este gt t_ciclo_noRT_max este gt t_ciclo_noRT else if este gt t_ciclo_noRT lt este gt t_ciclo_noRT_min este gt t_ciclo_noRT_min este gt t_ciclo_noRT 346 gt e gt lt k k k k kk k k k k k k k kkk k k k k k k k k kK k KK k k K K k K K K void funcionFinaliza EEEE he he f lt EE 2 k k K k k gt lt K K void funcion_finaliza_promediador void instancia struct promediador este struct promediador instancia ifdef LOG sprintf msgLog Finalizing 96s este gt nombre logPrint msgLog 3 endif principio c digo espec fico funcion finaliza promediador fin c digo espec fico funcion finaliza promediador k k fe K k K K K void inicilizapromediador 2 2 2 k k 2 k k k k k kkk k kk k k k k k kk k kk k k K K k K K K int inicializa_promediador ifdef LOG sprintf msgLog Initializing s ID_promediador logPrint msgLog 3 endif clase_promediador funcionCrea funcion_crea_promediador clase_promediador funcionInicializa funcion_inicializa_promediador clase_promediador funcionNormal funcion_normal_promediador clase_prome
132. underflows for the given channel or if there is a math overflow during the bias measurement this data register will contain the value 4096 This register value will clear when after the next valid measurement is made www honeywell com 15 HMC5883L Table 15 Data Output Z Registers A and B Data Output Register Operation When one or more of the output registers are read new data cannot be placed in any of the output data registers until all six data output registers are read This requirement also impacts DRDY and RDY which cannot be cleared until new data is placed in all the output registers Status Register The status register is an 8 bit read only register This register is used to indicate device status SRO through SR7 indicate bit locations with SH denoting the bits that are in the status register SR7 denotes the first bit of the data stream 16 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SRO 0 0 0 0 0 0 LOCK 0 RDY 0 Table 16 Status Register Location Name Description SR7 to SR2 0 These bits are reserved Data output register lock This bit is set when 1 some but not all for of the six data output registers have been read 2 Mode register has been read When this bit is set the six data output registers are locked SR1 LOCK and any new data will not be placed in these register until one of these conditions are met
133. voltage may be anywhere from 1 71V min to VDD max 1 4 Applications Motion enabled game controllers Motion based portable gaming Motion based 3D mice and 3D remote controls No Touch UI Health and sports monitoring 5 of 39 Document Number PS ITG 3200A 00 01 4 Release Date 03 30 2010 InvenSense ITG 3200 Product Specification Revision 1 4 a 2 Features The ITG 3200 triple axis MEMS gyroscope includes a wide range of features Digital output X Y and Z Axis angular rate sensors gyros on one integrated circuit with a sensitivity of 14 375 LSBs per sec and a full scale range of 2000 sec Three integrated 16 bit ADCs provide simultaneous sampling of gyros while requiring no external multiplexer Enhanced bias and sensitivity temperature stability reduces the need for user calibration Low frequency noise lower than previous generation devices simplifying application development and making for more responsive motion processing Digitally programmable low pass filter Low 6 5mA operating current consumption for long battery life Wide VDD supply voltage range of 2 1V to 3 6V Flexible VLOGIC reference voltage allows for interface voltages from 1 71V to VDD Standby current Su A Smallest and thinnest package for portable devices 4x4x0 9mm QFN No high pass filter needed Turn on time 50ms Digital output temperature sensor Factory calibrated scale factor 10 000 g shock tolerant Fast Mode
134. 0 ADXL345 INTERRUPT 3 98 4 MIRE SPI OR PC CONTROL INTERFACE 07925 016 Figure 44 Application Diagram MECHANICAL CONSIDERATIONS FOR MOUNTING The ADXL345 should be mounted on the PCB in a location close to a hard mounting point of the PCB to the case Mounting the ADXL345 at an unsupported PCB location as shown in Figure 45 may result in large apparent measurement errors due to undampened PCB vibration Locating the accelerometer near a hard mounting point ensures that any PCB vibration at the accelerometer is above the accelerometer s mechanical sensor resonant frequency and therefore effectively invisible to the accelerometer Multiple mounting points close to the sensor and or a thicker PCB also help to reduce the effect of system resonance on the performance of the sensor ACCELEROMETERS YN MEN MOUNTING POINTS Figure 45 Incorrectly Placed Accelerometers 07925 036 TAP DETECTION The tap interrupt function is capable of detecting either single or double taps The following parameters are shown in Figure 46 for a valid single and valid double tap event e The tap detection threshold is defined by the THRESH register Address 0x1D e The maximum tap duration time is defined by the DUR register Address 0x21 e The tap latency time is defined by the latent register Address 0x22 and is the waiting period from the end of the first tap until the start of the time window when a second tap can be
135. 0 R W LED15 OFF L 7 0 R W reserved R LED15 OFF H 4 R W LED15 OFF 3 0 R W Value 0000 0000 000 1 0000 0000 0000 000 0 0000 0000 0000 000 1 0000 0000 0000 000 0 0000 0000 0000 000 1 0000 Description LEDn_OFF count for LED13 8 LSBs non writable LED13 full OFF LEDn OFF count for LED13 4 MSBs LEDn ON count for LED14 8 LSBs non writable LED14 full ON LEDn ON count for LED14 4 MSBs LEDn OFF count for LED14 8 LSBs non writable LED14 full OFF LEDn OFF count for LED14 4 MSBs LEDn ON count for LED15 8 LSBs non writable LED15 full ON LEDn ON count for LED15 4 MSBs LEDn OFF count for LED15 8 LSBs non writable LED15 full OFF LEDn OFF count for LED15 4 MSBs 9685 The LEDn ON output control bit 4 when set to logic 1 causes the output to be always ON The turning ON of the LED 15 delayed by the amount in the LEDn_ON registers LEDn_OFF 11 0 are ignored When this bit 0 then the LEDn ON and LEDn OFF registers are used according to their normal definition The LEDn OFF H output control bit 4 when set to logic 1 causes the output to be always OFF In this case the values in the LEDn ON registers are ignored Remark When all LED outputs are configured as always OFF the prescale counter and all associated PWM cycle timing logic are disabled If LEDn ON H 4 and LEDn OFF H 4 are set at the same time the LEDn OFF H 4 function takes precedence All inform
136. 0 g Any Axis Powered 10 000 g Vs 0 3V to 3 9 V Vop vo 0 3V to 43 9V Digital Pins 0 3 V to Voo vo 0 3 V or 3 9 V whichever is less All Other Pins 0 3 V to 3 9 V Output Short Circuit Duration Indefinite Any Pin to Ground Temperature Range Powered 40 C to 105 C Storage 40 C to 105 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability THERMAL RESISTANCE Table 3 Package Characteristics PACKAGE INFORMATION The information in Figure 2 and Table 4 provide details about the package branding for the ADXL345 For a complete listing of product availability see the Ordering Guide section 07925 102 Figure 2 Product Information on Package Top View Table 4 Package Branding Information Package Type Osa Device Weight 14 Terminal LGA 150 C W 85 C W 30mg Branding Key Field Description 345B Part identifier for ADXL345 RoHS compliant designation yww Date code VVVV Factory lot code CNTY Country of origin ESD CAUTION ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge
137. 002aad811 Table 15 Test data for enable disable switching times Test tro 2 tpzL 2 PZH Load Switch CL 50 pF 50 pF 50 pF RL 500 Q 500 Q 500 Q open Vop x 2 PCA9685 All information provided in this document is subject to legal disclaimers B V 2010 All rights reserved Product data sheet Rev 3 2 September 2010 42 of 51 NXP Semiconductors PCA9685 15 Package outline 16 channel 12 bit PWM 2 LED controller TSSOP28 plastic thin shrink small outline package 28 leads body width 4 4 mm DIMENSIONS mm are the original dimensions SOT361 1 4 1 gt detail UNIT A max A1 A2 As bp c EC mm 1 1 0 15 0 05 0 95 0 80 0 30 0 19 0 2 0 1 9 8 4 5 9 6 4 3 Notes 1 Plastic or metal protrusions of 0 15 mm maximum per side are not included 2 Plastic interlead protrusions of 0 25 mm maximum per side are not included OUTLINE VERSION REFERENCES EUROPEAN IEC JEDEC JEITA PROJECTION ISSUE DATE SOT361 1 MO 153 Ee 99 12 27 03 02 19 Fig 36 Package outline SOT361 1 TSSOP28 9685 All i
138. 0g a wil Xour 09 Your 19 o Your 19 Zour 09 p T Zour 09 dOL 19 Your 04 Zour 0g Xour 0g Xour 0g 3 Your 00 Your 00 2 Zour 19 Zout 19 Figure 58 Output Response vs Orientation to Gravity Rev D Page 35 of 40 LAYOUT AND DESIGN RECOMMENDATIONS Figure 59 shows the recommended printed wiring board land pattern Figure 60and Table 24 provide details about the recommended soldering profile 1 0500 j 0 5500 3 0500 F a 5 3400 0 2500 j lt gt 1 1450 Figure 59 Recommended Printed Wiring Board Land Pattern Dimensions shown in millimeters TEMPERATURE RAMP DOWN 5 125 0 2500 07925 014 CRITICAL ZONE TO Tp 07925 015 Figure 60 Recommended Soldering Profile Table 24 Recommended Soldering Profile Profile Feature Condition Sn63 Pb37 Pb Free Average Ramp Rate from Liquid Temperature to Peak Temperature Preheat Minimum Temperature Maximum Temperature Tsmax Time from Tsmn to Tsmax ts Tsmax to T Ramp Up Rate Liquid Temperature Time Maintained Above T ti Peak Temperature Tp Time of Actual T 5 tp Ramp Down Rate Time 25 to Peak Temperature 3 C sec maximum 100 150 C 60 sec to 120 sec 3 C sec maximum 183 C
139. 1 Semiconductors 9685 16 channel 12 bit PWM 2 LED controller Table 3 Register summary continued Register Register D7 06 D5 D4 D3 D2 D1 DO Name Type Function decimal hex 22 16 0 0 0 1 0 1 1 0 LED4 ONL read write LED4 output and brightness control byte 0 23 17 0 0 0 1 1 1 1 LED4 ON H read write LED4 output and brightness control byte 1 24 18 0 0 0 1 1 0 0 0 LED4 OFFL read write LED4 output and brightness control byte 2 25 19 0 0 0 1 1 0 0 1 LED4 OFFH read write LED4 output and brightness control byte 3 26 1A 0 0 0 1 1 0 1 0 LED5 ONL read write LED5 output and brightness control byte 0 27 1B 0 0 0 1 1 0 1 1 LED5 ON H read write LED5 output and brightness control byte 1 28 1C 0 0 0 1 1 1 0 0 LED5 OFFL read write LED5 output and brightness control byte 2 29 1D 0 0 0 1 1 1 0 1 LED5 read write LED5 output and brightness control byte 3 30 1E 0 0 0 1 1 1 1 0 LED6 ONL read write LED6 output and brightness control byte 0 31 1F 0 0 0 1 1 1 1 1 LED6 ON H read write LED6 output and brightness control byte 1 32 20 00 1 0 0 0 0 0 LED6 OFFL read write LED6 output and brightness control byte 2 33 21 0 0 1 0 0 0 0 1 LED6 OFFH read write LED6 output and brightness control byte 3 34 22 0 0 1 0 0 0 1 0 LED7ONL read write LED7 output and brightness control byte 0 35 23 0 0 1 0 0 0 1 1 LED7 ONH read write LED7 output and brightness control byte 1 36 24 0 0 1 0 0 1 O 0 LED7_OFF_L r
140. 1 1 1 LEDO ON H read write LEDO output and brightness control byte 1 8 08 0 0 0 0 1 0 O 0 LEDO OFFL read write LEDO output and brightness control byte 2 9 09 0 0 0 O 1 0 0 1 LEDO read write LEDO output and brightness control byte 3 10 0 0 0 0 0 1 0 1 O LEDI ONL read write LED1 output and brightness control byte O 11 0B 0 0 0 0 1 0 1 1 LED1 ON H read write LED1 output and brightness control byte 1 12 0C 0 0 0 0 1 1 0 O LED OFFL read write LED1 output and brightness control byte 2 13 0D 0 0 0 0 1 1 0 1 LED1 read write LED1 output and brightness control byte 3 14 0 0 0 0 0 1 1 1 0 LED2ONL read write LED2 output and brightness control byte 0 15 0 0 0 0 1 1 1 1 LED2 ON H read write LED2 output and brightness control byte 1 16 10 0 0 01 0 0 O 0 LED2 OFFL read write LED2 output and brightness control byte 2 17 11 0 0 0 1 0 0 0 1 LED2 OFFH read write LED2 output and brightness control byte 3 18 12 0 0 0 1 0 0 1 O LEDSONL read write LED3 output and brightness control byte 0 19 13 0 0 0 1 0 0 1 1 LEDS ON H read write LED3 output and brightness control byte 1 20 14 0 0 0 1 0 1 O 0 LED3 OFFL read write LED3 output and brightness control byte 2 21 15 0 0 0 1 0 1 O 1 LED3 OFFH read write LED3 output and brightness control byte 3 PCA9685 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Product data sheet Rev 3 2 September 2010 9 of 5
141. 1110 001 subaddress 1 0 A1 0 R only 0 reserved 03h SUBADR2 7 1 2 7 1 R W 1110 010 subaddress 2 0 2 0 R only 0 reserved 04h SUBADR3 7 1 7 1 R W 1110 100 l C bus subaddress 3 0 A3 0 R only 0 reserved Subaddresses are programmable through the 2 Default power up values are E2h E4h E8h and the device s will not acknowledge these addresses right after power up the corresponding SUBx bit in MODE1 register is equal to 0 Once subaddresses have been programmed to their right values SUBx bits need to be set to logic 1 in order to have the device acknowledging these addresses MODE1 register Only the 7 MSBs representing the 12C bus subaddress are valid The LSB in SUBADRx register is a read only bit 0 When SUBx is set to logic 1 the corresponding I2C bus subaddress can be used during either an 12C bus read or write sequence ALLCALLADR LED All Call 12C bus address Table 9 ALLCALLADR LED All Call 12C bus address register address 05h bit description default value Address Register Bit Symbol Access Value Description 05h 7 1 AC 7 1 R W 1110 000 I2C bus address register 0 0 0 reserved The LED All Call I2C bus address allows all the PCA9685s in the bus to be programmed at the same time ALLCALL bit in register MODE1 must be equal to 1 power up default state This address is programmable t
142. 2 Write CRB 01 send 0x3C 0 01 0 0 Gain 5 or any other desired gain 3 For each measurement query Write Mode 02 send 0x3C 0x02 0x01 Single measurement mode Wait 6 ms or monitor status register or DRDY hardware interrupt pin Send 0x3D 0x06 Read all 6 bytes If gain is changed then this data set is using previous gain Convert three 16 bit 2 s compliment hex values to decimal values and assign to X Z Y respectively 18 www honeywell com HMC5883L SELF TEST OPERATION To check the HMC5883L for proper operation a self test feature in incorporated in which the sensor offset straps are excited to create a nominal field strength bias field to be measured To implement self test the least significant bits MS1 and 50 of configuration register A are changed from 00 to 01 positive bias or 10 negetive bias Then by placing the mode register into single or continuous measurement mode two data acquisition cycles will be made on each magnetic vector The first acquisition will be a set pulse followed shortly by measurement data of the external field The second acquisition will have the offset strap excited about 10 mA in the positive bias mode for X Y and Z axes to create about a 1 1 gauss self test field plus the external field The first acquisition values will be subtracted from the second acquisition and the net measurement will be placed into the data output registers Since self test adds 1 1 Gauss additional fiel
143. 250 2 2 2 2 2 2 4 2 5 Notes 2 Based on characterization of 5 pieces over temperature 4 Typical Randomly selected part measured at room temperature on evaluation board or in socket 5 Guaranteed by design 9 of 39 InvenSens ITG 3200 Product Specification Document Number PS ITG 3200A 00 01 4 Revision 1 4 Release Date 03 30 2010 3 4 Electrical Specifications continued Typical Operating Circuit of Section 4 2 VDD 2 5V VLOGIC 1 71V to VDD 252 Parameters INTERNAL CLOCK SOURCE Sample Rate Fast Sample Rate Slow Clock Frequency Initial Tolerance Frequency Variation over Temperature PLL Settling Time EXTERNAL 32 768kHz CLOCK External Clock Frequency External Clock Jitter Sample Rate Fast Sample Rate Slow PLL Settling Time EXTERNAL 19 2MHz CLOCK External Clock Frequency Sample Rate Fast Sample Rate Slow PLL Settling Time Charge Pump Clock Frequency Frequency Notes Tested in production pU Conditions CLKSEL 0 1 2 or 3 DLPFCFG 0 SAMPLERATEDIV 0 DLPFCFG 1 2 3 4 5 or 6 SAMPLERATEDIV 0 CLKSEL 0 25 C CLKSEL 1 2 3 25 C CLKSEL 0 CLKSEL 1 2 3 CLKSEL 1 2 3 CLKSEL 4 Cycle to cycle rms DLPFCFG 0 SAMPLERATEDIV 0 DLPFCFG 1 2 3 4 5 or 6 SAMPLERATEDIV 0 CLKSEL 5 DLPFCFG 0 SAMPLERATEDIV 0 DLPFCFG 1 2 3 4 5 or 6 SAMPLERATEDIV 0 1 Stage 25 C 2 Stage 25 C Over temperature Typical Max Notes 15 to 10 1
144. 2c 16 struct i2c instancias_i2c MAX_i2c endif struct componente clase_i2c extern char msgLog 78 gt e gt lt H lt A gt lt 2 ol ol oe k K k k K K K void inicializa_propiedades O void inicializa_propiedades_i2c void instancia char nombre int orden unsigned char habilitado struct 12 este struct i2c instancia strcpy este gt nombre nombre este gt orden orden este gt habilitado habilitado este gt finalizado 0 principio inicializaci n de propiedades espec ficas 12 fin inicializaci n de propiedades espec ficas 12c pl k k k o 2 fe K k gt e K K void registra_propiedades EE 2 o lt 2 2 2 2 ope k k k k kk k k k k kk k k k kk k kk k k k kk KK k int registra_propiedades_i2c void instancia struct 12 este struct i2c instancia char saux MAX_LONG_NOMBRE insertarNombre2 este gt nombre este emStrcpy saux ID SISTEMA ID 12c NO MODIFICABLE insertarPropiedad3 este gt nombre amp este gt nombre ID VAR TEXT PUBLICO nombre insertarPropiedad3 este gt nombre amp este gt orden ID VAR INT PUBLICO MODIFICABLE orden insertarPropiedad3 este gt nombre amp este gt habilitado ID VAR BYTE PUBLICO MODIFICABLE habilitado insertarPropiedad3 este gt nombre amp este gt finalizado ID VAR BYTE PUBLICO MODIFICABLE finalizado insertarPropiedad3 este gt nombre am
145. 3L Resolution _ HMC5883L Resolution a 3 i 9 25 s 7 i ecu UM o 1 5 ee 1Avg 2 lAvg S 4 A 2 8 206 4Avg 2 4Avg 0 5 8Avg 7 8Avg 5 5 8 0 1 2 3 4 5 6 7 91 2 3 4 5 6 7 Gain Gain Typical Measurement Period in Single Measurement Mode 0 26 mS 0 7 mS 6 26 mS 6 mS Monitoring of the DRDY Interrupt pin is only required if maximum output rate is desired 8 www honeywell com HMC5883L BASIC DEVICE OPERATION Anisotropic Magneto Resistive Sensors The Honeywell HMC5883L magnetoresistive sensor circuit is a trio of sensors and application specific support circuits to measure magnetic fields With power supply applied the sensor converts any incident magnetic field in the sensitive axis directions to a differential voltage output The magnetoresistive sensors are made of a nickel iron Permalloy thin film and patterned as a resistive strip element In the presence of a magnetic field a change in the bridge resistive elements causes a corresponding change in voltage across the bridge outputs These resistive elements are aligned together to have a common sensitive axis indicated by arrows in the pinout diagram that will provide positive voltage change with magnetic fields increasing in the sensitive direction Because the output is only proportional to the magnetic field component along its axis additional sensor bridges are placed at orthogonal directions to permit
146. 5 16 channel 12 bit PWM 2 LED controller LEDn_ON LEDn_OFF LEDn_ON LEDn_OFF STOP 0 511 2047 LEDn_ON 1023 example 4 off LEDn ON 1023 LEDn OFF 1023 gt 4095 3071 0 511 A ra 2047 767 Fig 9 Example 1 LEDn_ON lt LEDn_OFF Example 2 LEDn_ON gt LEDn_OFF Example 3 LEDn_ON 12 1 LEDn_ON 11 0 1022 LEDn_OFF 12 0 LEDn_OFF 11 0 don t care gt 4095 3071 0 example 1 511 4095 0 example 2 A 2047 767 example 3 Example 4 LEDn_ON 12 0 LEDn_OFF 12 0 LEDn_ON 11 0 LEDn_OFF 11 0 Output example is 002aad193 9685 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Product data sheet Rev 3 2 September 2010 17 of 51 NXP Semiconductors PCA9685 16 channel 12 bit PWM 2 LED controller STOP example 1 LEDn ON LEDn OFF example 2 LEDn ON LEDn OFF example 3 LEDn ON LEDn OFF example 4 LEDn ON LEDn OFF 0 4095 r register s updated in this cycle _ gt 511 13071 511 Y 3071 511 gt 3071 511 gt 3071 0 4095 lt 7 output s updated in this cycle L511 1023 767 L 1023 3071 Example 1 LEDn_ON unchanged and LEDn_OFF decreased Exam
147. 5 16 channel 12 bit PWM 2 LED controller 7 7 Using the PCA9685 with and without external drivers The PCA9685 LED output drivers are 5 5 V only tolerant and can sink up to 25 mA at 5 V If the device needs to drive LEDs to a higher voltage and or higher current use of an external driver is required bit MODE2 register can be used to keep the LED PWM control firmware the same independently of the type of external driver This bit allows LED output polarity inversion non inversion only when OE 0 OUTDRV bit MODE2 register allows minimizing the amount of external components required to control the external driver N type or P type device Table 11 Use of INVRT and OUTDRV based on connection to the LEDn outputs when OE 011 INVRT OUTDRV Direct connection to LEDn Firmware formulas and LED output state values inverted formulas and LED output state values inverted formulas and LED output state values apply formulas and LED output state values apply External N type driver External P type driver External Firmware External Firmware External pull up pull up pull up resistor resistor resistor LED current formulas andLED required formulas and LED required limiting R21 output state output state values values inverted apply LED current formulas and LED formulas and LED not required limiting R21 output state required output state values values
148. 5 is a small thin ultralow power 3 axis accelerometer with high resolution 13 bit measurement at up to 16 g Digital output data is formatted as 16 bit twos complement and is acces sible through either a SPI 3 or 4 wire or digital interface The ADXL345 is well suited for mobile device applications It measures the static acceleration of gravity in tilt sensing appli cations as well as dynamic acceleration resulting from motion or shock Its high resolution 3 9 mg LSB enables measurement of inclination changes less than 1 09 Several special sensing functions are provided Activity and inactivity sensing detect the presence or lack of motion by comparing the acceleration on any axis with user set thresholds Tap sensing detects single and double taps in any direction fall sensing detects if the device is falling These functions can be mapped individually to either of two interrupt output pins An integrated patent pending memory management system with a 32 level first in first out FIFO buffer can be used to store data to minimize host processor activity and lower overall system power consumption Low power modes enable intelligent motion based power management with threshold sensing and active acceleration measurement at extremely low power dissipation The ADXL345 is supplied in a small thin 3 mm x 5 mm x 1 mm 14 lead plastic package FUNCTIONAL BLOCK DIAGRAM Vs Vppvo L 1 POWER MANAGEMENT
149. 5s are used and the same sequences A B above are sent to each of them 2 Acknowledge from all the slave devices configured for the new LED All Call 12C bus address in sequence B Fig 25 LED All Call 12C bus address programming and LED All Call sequence example PCA9685 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Product data sheet Rev 3 2 September 2010 33 of 51 Semiconductors 9685 16 channel 12 bit PWM 2 LED controller 10 Application design in information 12 Vpp 2 5 V 3 3 V or 5 0 V 10ko 2 I C BUS SMBus E V NV NN V MASTER Yo F A H Y R ic 177 a 12V t t PCA9685 NN Ns 4 T H V e me R 177 T 12V t 1 Wn VW V V 744 A mm Y E 777 i 54 t 1 HH AO Al A2 NO NE NO NO T A3 Y A4 Y EA A5 TH E 177 177 002 827 12C bus address 1010 101x All 16 of the LEDn outputs configurable as either open drain or totem pole Mixing of configuration is not pos
150. 7 19 21 22 RESV Reserved Do not connect 20 CPOUT Charge pump capacitor connection 23 SCL PC serial clock 24 SDA PC serial data 2 3 4 5 14 15 16 17 NC Not internally connected May be used for PCB trace routing Top View O o o m m X NCC ITG 3200 Big lt gt 8 Q O 2 D om gt m m m 45 Oo lt O lt QFN Package Orientation of Axes of Sensitivity 24 pin 4mm x 4mm x 0 9mm and Polarity of Rotation 13 of 39 Document Number PS ITG 3200A 00 01 4 y m Revision 1 4 InvenSense ITG 3200 Product Specification RD 09 30 2010 4 2 Typical Operating Circuit GND 8 P a C1 CLKIN 2 VLOGIC GND o GND GND Typical Operating Circuit 4 3 Bill of Materials for External Components Component Label Specification Quantity Charge Pump Capacitor CI Ceramic X7R 2 2nF 1046 50V 1 VDD Bypass Capacitor C2 Ceramic X7R 0 1 10 4V 1 Regulator Filter Capacitor Ceramic X7R 0 1 10 2V 1 VLOGIC Bypass Capacitor C4 Ceramic X7R 10nF 10 4V 1 14 of 39 InvenSens Document Number PS ITG 3200A 00 01 4 ITG 3200 Product Specification Revision 1 4 Release Date 03 30 2010 4 4 Recommended Power On Procedure VDD VLOGIC All Voltages at OV e Tvc voo i Power Up Sequencing 1 is VDD rise time Time for VDD to rise from 10 to 90 of its final value 2 Tvppr is lt 5
151. 8 if este 5t ciclo RT gt este gt t_ciclo_RT_max este 5t ciclo RT max este gt t_ciclo_RT else if este gt t_ciclo_RT lt gt ciclo min gt ciclo min este 5t ciclo Eo Eo k k k k k k k k k k k k k k k k k kkk k kk k k k k k gt e k k void funcionNormalNoRT IO void funcion_normal_noRT_renormalizar void instancia int t ciclo struct renormalizar este struct renormalizar instancia ifdef LOG sprintf msgLog Normal function 96s este gt nombre logPrint msgLog 6 endif struct timespec ts crononsec 1 amp ts principio c digo espec fico funcion normal noRT renormalizar fin c digo espec fico funcion normal noRT renormalizar este 5t ciclo noRT 0 amp ts if este t ciclo noRT gt gt ciclo noRT max este 5t ciclo noRT max este 5t ciclo noRT else if este gt t_ciclo_noRT lt este gt t_ciclo_noRT_min este gt t_ciclo_noRT_min este gt t_ciclo_noRT k k k k k k k le ls ls ds ds ls ls ls le le k k k k k k k k kk k kK k k k k k K K k void funcionFinaliza E E E k k K k k K K k void funcion_finaliza_renormalizar void instancia struct renormalizar este struct renormalizar instancia ifdef LOG sprintf msgLog Finalizing 96s este gt nombre logPrint msgLog 3 e
152. A registers already compensating for any offset In a no turn or single point calibration scheme the part is oriented such that one axis typically the z axis is in the 1 g field of gravity and the remaining axes typically the x and y axis are in a 0 g field The output is then measured by taking the average of a series of samples The number of samples averaged is a choice of the system designer but a recommended starting point is 0 1 sec worth of data for data rates of 100 Hz or greater This corresponds to 10 samples at the 100 Hz data rate For data rates less than 100 Hz it is recommended that at least 10 samples be averaged together These values are stored as Xog and 71 for the 0 g measurements on the x and y axis and the 1 g measurement on the z axis respectively The values measured for and Yog correspond to the x and y axis offset and compensation is done by subtracting those values from the output of the accelerometer to obtain the actual acceleration XAcrvaL Xurzas Xog Yacruat Ymeas Yog Because the z axis measurement was done in a 1 g field a no turn or single point calibration scheme assumes an ideal sensitivity Sz for the z axis This is subtracted from 2 to attain the z axis offset which is then subtracted from future measured values to obtain the actual value Log Zug 5 ZACTUAL ZMEAS ADXL345 can automatically compensate the output for offset by using the offset
153. A without detection Although this product features patented or proprietary protection circuitry damage A may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Rev D Page 6 of 40 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 5 Pin Function Descriptions ADXL345 TOP VIEW Not to Scale SCL SCLK Vpp vo 13 i SDA SDI SDIO GND SDO ALT ADDRESS RESERVED RESERVED GND NC GND INT2 Vs INT1 07925 002 Figure 3 Pin Configuration Top View Pin No Mnemonic Description 1 Von vo Digital Interface Supply Voltage 2 GND This pin must be connected to ground 3 RESERVED Reserved This pin must be connected to Vs or left open 4 GND This pin must be connected to ground 5 GND This pin must be connected to ground 6 Vs Supply Voltage 7 CS Chip Select 8 Interrupt 1 Output 9 INT2 Interrupt 2 Output 10 NC Not Internally Connected 11 RESERVED Reserved This pin must be connected to ground or left open 12 SDO ALT ADDRESS Serial Data Output SPI 4 Wire Alternate Address Select 13 SDA SDI SDIO Serial Data PC Serial Data Input SPI 4 Wire Serial Data Input and Output SPI 3 Wire 14 SCL SCLK Serial Communications Clock SCL is the clock for PC and SCLK is the clock for SPI Rev D Page 7 of 40 ADXL345 TYPIC PERCENT OF POPULATION 3
154. ANEXO B DATASHEET DE LOS SENSORES Y EL MICROCONTROLADOR INDICE DE CONTENIDOS e Datasheet ADXL345 aceler metro e Datasheet ITG3200 gir scopo e Datasheet HMC5883L magnet metro e Datasheet PCA9685 microcontrolador ANALOG DEVICES FEATURES Ultralow power as low as 23 pA in measurement mode and 0 1 pA in standby mode at Vs 2 5 V typical Power consumption scales automatically with bandwidth User selectable resolution Fixed 10 bit resolution Full resolution where resolution increases with g range up to 13 bit resolution at 16 g maintaining 4 mg LSB scale factor in all g ranges Patent pending embedded memory management system with FIFO technology minimizes host processor load Single tap double tap detection Activity inactivity monitoring Free fall detection Supply voltage range 2 0 V to 3 6 V 1 0 voltage range 1 7 V to Vs SPI 3 and 4 wire and PC digital interfaces Flexible interrupt modes mappable to either interrupt pin Measurement ranges selectable via serial command Bandwidth selectable via serial command Wide temperature range 40 C to 85 C 10 000 g shock survival Pb free RoHS compliant Small and thin 3 mm x 5 mm x 1 mm LGA package APPLICATIONS Handsets Medical instrumentation Gaming and pointing devices Industrial instrumentation Personal navigation devices Hard disk drive HDD protection 3 Axis 2 9 4 9 8 g 16 2 Digital Accelerometer ADXL345 GENERAL DESCRIPTION The ADXL34
155. Axes Relative to PCB Axes with Orientation Errors and The table below shows the cross axis sensitivity as a percentage of the specified gyroscope s sensitivity for a given orientation error Cross Axis Sensitivity vs Orientation Error Orientation Error Cross Axis Sensitivity 0 or sin0 or sino 0 0 0 59 0 87 19 1 75 The specification for cross axis sensitivity in Section 3 includes the effect of the die orientation error with respect to the package 34 of 39 Document Number PS ITG 3200A 00 01 4 gt Z Revision 1 4 InvenSense ITG 3200 Product Specification se asia 9 10 MEMS Handling Instructions MEMS Micro Electro Mechanical Systems are a time proven robust technology used in hundreds of millions of consumer automotive and industrial products MEMS devices consist of microscopic moving mechanical structures They differ from conventional IC products even though they can be found in similar packages Therefore MEMS devices require different handling precautions than conventional ICs prior to mounting onto printed circuit boards PCBs The ITG 3200 gyroscope has a shock tolerance of 10 000g InvenSense packages its gyroscopes as it deems proper for protection against normal handling and shipping It recommends the following handling precautions to prevent potential damage e Individually packaged or trays of gyroscopes should not be dropped onto hard surfac
156. B Sensitivity Change Due to Temperature 0 01 C 0 4 OFFSET Each axis O g Output for Xour Your 150 0 4150 mg O g Output for Zour 250 0 250 mg 0 g Output Deviation from Ideal Xour Your 35 mg 0 g Output Deviation from Ideal Zour 40 mg 04 Offset vs Temperature for X Y Axes 0 4 mg C 0 g Offset vs Temperature for Z Axis 1 2 mg C NOISE X Y Axes ODR 100 Hz for 2 g 10 bit resolution or 0 75 LSB rms all g ranges full resolution Z Axis ODR 100 Hz for 2 g 10 bit resolution or 1 1 LSB rms all g ranges full resolution OUTPUT DATA RATE AND BANDWIDTH User selectable Output Data Rate ODR 5 0 1 3200 Hz SELF TEST Output Change in X Axis 0 20 2 10 g Output Change in Y Axis 2 10 020 g Output Change in Z Axis 0 30 3 40 g POWER SUPPLY Operating Voltage Range Vs 2 0 2 5 3 6 V Interface Voltage Range Vooo 1 7 1 8 Vs V Supply Current ODR gt 100 Hz 140 uA ODR lt 10 Hz 30 uA Standby Mode Leakage Current 0 1 uA Turn On and Wake Up Time ODR 3200 Hz 1 4 ms Rev D Page 4 of 40 ADXL345 Parameter Test Conditions Min Unit TEMPERATURE Operating Temperature Range 40 85 WEIGHT Device Weight 30 mg 1 The typical specifications shown are for at least 68 of the population of parts and are based on the worst case of mean 1 o except for O g output and sensitivity which represents the target value For 0 offset and sensitivity the deviation from the
157. CKISI 2 OUTDRVIII R W 0 The 16 LEDn outputs are configured with an open drain structure 1 The 16 LEDn outputs are configured with a totem pole structure 1100 OUTNE 1 0 4 R W 00 When OE 1 output drivers not enabled LEDn 0 01 When OE 1 output drivers not enabled LEDn 1 when OUTDRV 1 LEDn high impedance when OUTDRV 0 same as OUTNE 1 0 10 1X When OE 1 output drivers not enabled LEDn high impedance 1 See Section 7 7 Using the PCA9685 with and without external drivers for more details Normal LEDs can be driven directly in either mode Some newer LEDs include integrated Zener diodes to limit voltage transients reduce EMI protect the LEDs and these must be driven only in the open drain mode to prevent overheating the IC 2 Change of the outputs at the STOP command allows synchronizing outputs of more than one PCA9685 Applicable to registers from 06h LEDO_ON_L to 45h LED15_OFF_H only 1 or more registers can be written any order before STOP 3 Update on ACK requires all 4 PWM channel registers to be loaded before outputs will change on the last ACK 4 See Section 7 4 Active LOW output enable input for more details 7 3 3 LED output and PWM control The turn on time of each LED driver output and the duty cycle of PWM can be controlled independently using the LEDn_ON and LEDn_OFF registers There will be two 12 bit registers per LED output These registers will be programme
158. CO MODIFICABLE roll insertarPropiedad3 este gt nombre amp gt roll ID SAL FLOAT PUBLICO MODIFICABLE out roll fin registro de propiedades espec ficas pid roll j LEE void funcionCrea IO int funcion_crea_pid_roll void instancia char nombre int orden unsigned char habilitado struct pid_roll este struct pid_roll instancia ifdef LOG sprintf msgLog Creating s nombre logPrint msgLog 3 endif inicializa_propiedades_pid_roll instancia nombre orden habilitado if registra_propiedades_pid_roll instancia 0 ifdef LOG sprintf msgLog s V Registering properties of s ID ERROR este gt nombre logPrint msgLog 1 endif if registrarInstancia instancia nombre amp clase pid roll orden amp este gt habilitado amp este gt finalizado 0 1 ifdef LOG sprintf msgLog s V Registering instance s ID ERROR este gt nombre logPrint msgLog 1 endif k k f lt k k K K k void funcionlnicializa IO void funcion inicializa pid roll void instancia struct pid roll este struct pid roll instancia ifdef LOG sprintf msgLog Initializing 95 este gt nombre logPrint msgLog 3 gt ciclo 0x10000000 gt ciclo RT max 0 gt ciclo noRT min 0x10000000 gt ciclo noRT max 0 principio c digo espec f
159. CO MODIFICABLE Ki ROLLPITCH insertarPropiedad3 este gt nombre amp este gt Kd_ROLLPITCH ID VAR FLOAT PUBLICO MODIFICABLE ROLLPITCH insertarPropiedad3 este gt nombre amp este errorRollPitch 0 ID VAR FLOAT PUBLICO MODIFICABLE errorRollPitch 0 insertarPropiedad3 este gt nombre amp este gt errorRollPitch 1 ID VAR FLOAT PUBLICO MODIFICABLE errorRollPitch 1 insertarPropiedad3 este gt nombre amp este gt errorRollPitch 2 ID VAR FLOAT PUBLICO MODIFICABLE errorRollPitch 2 fin registro de propiedades espec ficas correcionPI_Acc CLE void funcionCrea O int funcion_crea_correcionPI_Acc void instancia char nombre int orden unsigned char habilitado f struct correcionPI Acc este struct correcionPI Acc instancia fifdef LOG sprintf msgLog Creating s nombre logPrint msgLog 3 endif inicializa_propiedades_correcionPI_Acc instancia nombre orden habilitado if registra propiedades correcionPI Acc instancia 0 ifdef LOG sprintf msgLog 96s V Registering properties of s ID ERROR este gt nombre logPrint msgLog 1 endif if registrarInstancia instancia nombre amp clase Acc orden amp este gt habilitado amp este gt finalizado 0 ifdef LOG sprintf msgLog s V Registering instance s ID ERROR este gt nombre logPrint msgLog 1 endif FR AR gt
160. D9 16 13 LED driver 9 LED10 17 14 LED driver 10 LED11 18 15 LED driver 11 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Product data sheet Rev 3 2 September 2010 5 of 51 Semiconductors 9685 7 Functional 16 channel 12 bit PWM 2 LED controller Table 2 Pin description continued Symbol Pin Type Description TSSOP28 HVQFN28 LED12 19 16 O LED driver 12 LED13 20 17 O LED driver 13 LED14 21 18 LED driver 14 LED15 22 19 LED driver 15 OE 23 20 active LOW output enable A5 24 21 address input 5 EXTCLK 25 22 external clock input 2 SCL 26 23 serial clock line SDA 27 24 y o serial data line Vpp 28 25 power supply supply voltage 1 HVQFN28 package die supply ground is connected to both Vss pin and exposed center Vss pin must be connected to supply ground for proper device operation For enhanced thermal electrical and board level performance the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board thermal vias need to be incorporated in the PCB in the thermal pad region 2 This pin must be grounded when this feature is not used description 7 1 9685 Refer to Figure 1 Block diagram of PCA9685 Device addresses Following a START condition
161. DLPF_CFG setting see register 22 This sampling is then filtered digitally and delivered into the sensor registers after the number of cycles determined by this register The sample rate is given by the following formula Esample Finternar divider 1 where Finternar is either 1kHz or 8kHz As an example if the internal sampling is at 1kHz then setting this register to 7 would give the following Esample 1KHz 7 1 125Hz 8ms per sample Parameters SMPLRT DIV Sample rate divider 0 to 255 23 of 39 InvenSens ITG 3200 Product Specification Document Number PS ITG 3200A 00 01 4 Revision 1 4 Release Date 03 30 2010 8 3 Type Read Write Register 22 DLPF Full Scale Register Hex 16 Register Decimal 22 Bit7 Bit6 Bit5 Bit4 Bit3 FS SEL Bit2 Bitl DLPF_CFG Bit0 Default Value 00h Description This register configures several parameters related to the sensor acquisition The FS_SEL parameter allows setting the full scale range of the gyro sensors as described in the table below The power on reset value of FS SEL is 00h Set to 03h for proper operation FS_SEL FS_SEL Gyro Full Scale Range 0 Reserved 1 Reserved 2 Reserved 3 2000 sec The DLPF_CFG parameter sets the digital low pass filter configuration It also determines the internal sampling rate used by the device as shown in the table below
162. EDO full ON 3 0 LED9 ON H 3 0 R W 0000 LEDn_ON count for LED9 4 MSBs 2Ch LED9 OFF L 7 0 LED9 OFF 7 0 R W 0000 0000 LEDn OFF count for LED9 8 LSBs 2Dh LED9 OFF H 7 5 reserved R 000 non writable 4 LED9 OFF H 4 R W 1 LED9 full OFF 3 0 LED9 OFF H 3 0 R W 0000 LEDn OFF count for LED9 4 MSBs 2Eh LED10_ON_L 7 0 1 010 7 0 R W 0000 0000 LEDn ON count for LED10 8 LSBs 2Fh LED10_ON_H 7 5 reserved R 000 non writable 4 LED10 ON H 4 R W 0 LED10 full ON 3 0 1 010 ON 3 0 R W 0000 LEDn ON count for LED10 4 MSBs 30h LED10 OFFL 7 0 LED10 OFF 7 0 R W 0000 0000 LEDn OFF count for LED10 8 LSBs 31h LED10 OFF H 7 5 reserved R 000 non writable 4 LED10 OFF 4 R W 1 LED10 full OFF 3 0 LED10_OFF_H 3 0 R W 0000 LEDn OFF count for LED10 4 MSBs 32h LED11 ON L 70 LED11 ON L 70 R W 0000 0000 LEDn ON count for LED11 8 LSBs 33h LED11 ON H 7 5 reserved R 000 non writable 4 LED11 ON H 4 R W 0 LED11 full ON 3 0 LED11_ON_H 3 0 R W 0000 LEDn ON count for LED11 4 MSBs 34h LED11 OFF L 7 0 LED11 OFF 7 0 R W 0000 0000 LEDn OFF count for LED11 8 LSBs 35h LED11 OFF H 7 5 reserved R 000 non writable 4 LED11 OFF H 4 R W 1 LED11 full OFF 3 0 LED11_OFF_H 3 0 R W 0000 LEDn OFF count for LED11 4 MSBs 36h LED12 ON L 7 0 1 012 ON 7 0 R W 0000 0000 LEDn ON count for LED12 8 LSBs 37h LED12 ON H 7 5 reserved R 000 non writable 4 LED12 ON H 4 R W 0 LED12 full ON 3 0 LED12 ON 3 0 R W 0000 LEDn ON count
163. G NOMBRE int orden byte habilitado byte finalizado int t ciclo RT int t ciclo RT min int t ciclo max int t ciclo noRT int t ciclo noRT min int t ciclo noRT max variables int primer dato pitch float vector filtro PROMEDIO float vector filtro PROMEDIO float acumula filtrado pitch float acumula filtrado roll entradas float Wgyr modif MAX EJES float pitch salidas float Wgyr modif prom MAX EJES promediador c promediador c 11 06 2014 promedian los datos corregidos anteriormente Eugenio Alcal Baselga Hinclude lt stdio h gt include lt string h gt include lt math h gt include runtime h include promediador h ifdef ID_LISTAS struct lista instancias_promediador else define MAX_promediador 16 struct promediador instancias_promediador MAX_promediador endif struct componente clase_promediador extern char msgLog extern float fdummy FR AR gt lt H lt ole k ol o o o k k k k k k k k k k k k k kk k k k k kk k k kk k k k k k K K k void inicializa_propiedades k k k f lt k k k fe k k KK K void inicializa_propiedades_promediador void instancia char nombre int orden unsigned char habilitado struct promediador este struct promediador instancia strcpy este gt nombre nombre este gt orden orden este gt
164. GYRO START UP TIME ZRO Settling kHz kHz kHz Between any two axes kHz DLPFCFG 0 to 1 s of Final TEMPERATURE SENSOR Range Sensitivity Temperature Offset Initial Accuracy Linearity 30 to 85 C 280 LSB C 35 C 13 200 LSB 35 C TBD C Best fit straight line 30 C to 85 C TEMPERATURE RANGE Specified Temperature Range Notes 1 Tested in production 2 4 Typical Randomly selected 35 6 Based on characterization of 30 pieces over temperature on evaluation board or in socket Based on design through modeling and simulation across PVT part measured at room temperature on evaluation board or in socket Based on characterization of 5 pieces over temperature Tested on 5 parts at room temperature 7 of 39 Document Number PS ITG 3200A 00 01 4 e Z T Revision 1 4 InvenSense ITG 3200 Product Specification e is asia 3 2 Electrical Specifications Typical Operating Circuit of Section 4 2 VDD 2 5V VLOGIC 1 71V to VDD 252 VDD POWER SUPPLY Operating Voltage Range 2 1 3 6 Power Supply Ramp Rate Monotonic ramp Ramp rate 0 5 is 10 to 90 of the final value see Figure in Section 4 4 Normal Operating Current 7 Sleep Mode Current ee EG REGISTER READ WRITE ADDRESS ADO 1101000 DIGITAL INPUTS ADO CLKIN Vin High Level Input Voltage 0 9 VLOGIC Low Level Input Voltage 0 1 VLOGIC Ci Input Capacitance 5 DIGITAL OUTPU
165. IFICABLE t ciclo noRT insertarPropiedad3 este gt nombre amp este t ciclo min ID VAR INT PUBLICO MODIFICABLE t ciclo noRT min insertarPropiedad3 este gt nombre amp este 5t ciclo noRT max ID VAR INT PUBLICO MODIFICABLE t ciclo noRT max principio registro de propiedades espec ficas correcionPI Acc for z 0 z lt MAX BJES z insertarPropiedad3 este gt nombre amp este gt Facc z ID_ENT_FLOAT PUBLICO MODIFICABLE Facc d z for z 0 z lt MAX_EJES z insertarPropiedad3 este gt nombre amp este gt W gyr z ID ENT FLOAT PUBLICO MODIFICABLE Weyr d 2 for z 0 z lt MAX_EJES z insertarPropiedad3 este gt nombre amp este gt W gyr_modif z ID SAL FLOAT PUBLICO MODIFICABLE Weyr_modif d z for i 0 i lt MAX_EJES i for j 0 j lt MAX EJES j insertarPropiedad3 este gt nombre amp este dcm matriz renorm 1 i j ID ENT FLOAT PUBLICO MODIFICABLE dcm matriz renorm 1 46d 96d i j insertarPropiedad3 este gt nombre amp este gt Omega_P 2 ID VAR FLOAT PUBLICO MODIFICABLE Omega P 2 insertarPropiedad3 este gt nombre amp este gt Omega_I 2 ID VAR FLOAT PUBLICO MODIFICABLE Omega I 2 insertarPropiedad3 este gt nombre amp este gt Kp_ROLLPITCH ID VAR FLOAT PUBLICO MODIFICABLE ROLLPITCH insertarPropiedad3 este gt nombre amp este gt Ki_ROLLPITCH ID VAR FLOAT PUBLI
166. LE t ciclo max principio registro de propiedades espec ficas acelerometro insertarPropiedad3 este gt nombre amp este bus ok ID ENT INT PUBLICO IMODIFICABLE bus ok insertarPropiedad3 este gt nombre amp este gt fd ID ENT INT PUBLICO IMODIFICABLE fd for i 0 i lt MAX EJES i insertarPropiedad3 este gt nombre amp este gt Facc i ID SAL FLOAT PUBLICO MODIFICABLE Facc d 1 insertarPropiedad3 este gt nombre amp este gt buf 0 ID VAR FLOAT PUBLICO NO MODIFICABLE buf 0 insertarPropiedad3 este gt nombre amp este gt buf 1 ID VAR FLOAT PUBLICO NO MODIFICABLE buf 1 insertarPropiedad3 este gt nombre amp este gt buf 2 ID VAR FLOAT PUBLICO NO MODIFICABLE buf 2 insertarPropiedad3 este gt nombre amp este gt buf 3 ID VAR FLOAT PUBLICO NO MODIFICABLE buf 3 insertarPropiedad3 este gt nombre amp este offset acc x ID VAR FLOAT PUBLICO MODIFICA BLE offset acc x insertarPropiedad3 este gt nombre amp este offset y ID FLOAT PUBLICO MODIFICA BLE offset acc y insertarPropiedad3 este gt nombre amp este offset z ID VAR FLOAT PUBLICO MODIFICA BLE offset z fin registro de propiedades espec ficas acelerometro j k k fe K k gt e K K void funcionCrea 2 k k k k k k k k kk k k kk k k k k k kk k kk k k f lt kk gt lt K k
167. ME WINDOW FOR SECOND M DUR TIME LATENT TAP WINDOW Figure 47 Double Tap Event Invalid Due to High g Event When the Suppress Bit Is Set A double tap event can also be invalidated if acceleration above the threshold is detected at the start of the time window for the second tap set by the window register This results in an invalid double tap at the start of this window as shown in Figure 48 Additionally a double tap event can be invalidated if an accel eration exceeds the time limit for taps set by the DUR register resulting in an invalid double tap at the end of the DUR time limit for the second tap event also shown in Figure 48 INVALIDATES DOUBLE TAP AT START OF WINDOW E ae TIME LIMIT i d E FOR TAP Hj DUR TIME LIMIT z Di LATENCY TIME WINDOW FOR TIME SECOND TAP WINDOW LATENT FOR TAPS Xui BW INVALIDATES DOUBLE TAP AT END OF DUR 07925 039 Figure 48 Tap Interrupt Function with Invalid Double Taps Single taps double taps or both can be detected by setting the respective bits in the INT ENABLE register Address Ox2E Control over participation of each of the three axes in single tap double tap detection is exerted by setting the appropriate bits in the AXES register Address 0x2A For the double tap function to operate both the latent and window registers must be set to a nonzero value Every mechanical system has somewhat different sing
168. O mode descriptions in the FIFO section Other bits and the corresponding interrupts are cleared by reading the INT_SOURCE register Register 0x31 DATA_FORMAT Read Write D7 D6 D5 D4 D3 D2 D1 DO SELF_TEST SPI INT_INVERT O FULL_RES Justify Range Setting D1 DO Frequency Hz 0 0 8 0 1 4 1 0 2 1 1 1 The DATA_FORMAT register controls the presentation of data to Register 0x32 through Register 0x37 All data except that for the 16 g range must be clipped to avoid rollover SELF_TEST Bit A setting of 1 in the SELF TEST bit applies a self test force to the sensor causing a shift in the output data A value of 0 disables the self test force SPI Bit A value of 1 in the SPI bit sets the device to 3 wire SPI mode and a value of 0 sets the device to 4 wire SPI mode Rev D Page 26 of 40 ADXL345 INT_INVERT Bit A value of 0 in the INT_INVERT bit sets the interrupts to active high and a value of 1 sets the interrupts to active low FULL_RES Bit When this bit is set to a value of 1 the device is in full resolution mode where the output resolution increases with the g range set by the range bits to maintain a 4 mg LSB scale factor When the FULL_RES bit is set to 0 the device is in 10 bit mode and the range bits determine the maximum g range and scale factor Justify Bit A setting of 1 in the justify bit selects left justified MSB mode and a
169. RESOLUTION MODE LSB FOR 380 FULL RESOLUTION MODE LSB FOR 16g FULL RESOLUTION MODE LEFT JUSTIFIED FOR 3200Hz AND 1600Hz OUTPUT DATA RATES THE LSB IN THESE MODES IS ALWAYS 0 ADDITIONALLY ANY BITS TO THE RIGHT OF THE LSB ARE ALWAYS 0 WHEN THE OUTPUT DATA IS LEFT JUSTIFIED 07925 146 Figure 50 Data Formatting of Full Resolution and 2 10 Bit Modes of Operation When Output Data Is Left Justified Rev D Page 32 of 40 NOISE PERFORMANCE The specification of noise shown in Table 1 corresponds to the typical noise performance of the ADXL345 in normal power operation with an output data rate of 100 Hz LOW POWER bit D4 0 rate bits D3 D0 in the BW RATE register Address 0x2C For normal power operation at data rates below 100 Hz the noise of the ADXL345 is equivalent to the noise at 100 Hz ODR in LSBs For data rates greater than 100 Hz the noise increases roughly by a factor of V2 per doubling of the data rate For example at 400 Hz ODR the noise on the x and y axes is typically less than 1 5 LSB rms and the noise on the z axis is typically less than 2 2 LSB rms For low power operation LOW POWER bit D4 1 in the BW RATE register Address 0 2 the noise of the ADXL345 is constant for all valid data rates shown in Table 8 This value is typically less than 1 8 LSB rms for the x and y axes and typically less than 2 6LSB rms for the z axis The trend of noise performance for both normal powe
170. Release Date 03 30 2010 ITG 3200 Product Specification Revision 1 4 Document Number PS ITG 3200A 00 01 4 5 Z Revision 1 4 InvenSense ITG 3200 Product Specification Rasa 08 50 0010 CONTENTS 1 DOCUMENT INFORMATION ccccccccccccccccccocccccocccccocccococccooccocosccoesocosocososecosseccosesesescosossccossesessescssecosssocosuus 4 1 1 REVISION HISTORY da 4 12 PURPOSE AND SCOPE II 5 1 3 PRODUCTOVERVIE WA A A A E AE E E E A E EE 5 1 4 APPLICATIONS UID 5 2 6 6 3 ELECTRICAL CHARACTERISTICS cvsssccccsotsssesescsccocsovsssnscesccsosssssesescesecossevs sovesssosssesdedecsesssessoesesecosssdsvscoveceveosees 7 3 1 SENSOR SPECIFICATIONS comcel dida 7 3 2 6 2 0 8 3 3 ELECTRICAL SPECIFICATIONS CONTINUED 2 2042 01 10 000000000000000000000 setate dass dessen 9 3 4 ELECTRICAL SPECIFICATIONS CONTINUED 1 2 2200 1 0 000000000000000000000000000000000 10 3 5 PC TIMING CHARACTERIZATION N EAD 2202202202200000 00 11 3 6 ABSOLUTE MAXIMUM RATINGS
171. SCL Both lines must be connected to a positive supply via a pull up resistor when connected to the output stages of a device Data transfer may be initiated only when the bus is not busy Bit transfer One data bit is transferred during each clock pulse The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals see Figure 16 SDA N SCL N data line change stable of data data valid allowed mba607 Fig 16 Bit transfer START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy A HIGH to LOW transition of the data line while the clock is HIGH is defined as the START condition S A LOW to HIGH transition of the data line while the clock is HIGH is defined as the STOP condition P see Figure 17 m SCL 522 N S k Ll c START condition STOP condition mba608 Fig 17 Definition of START and STOP conditions System configuration A device generating a message is a transmitter a device receiving is the receiver The device that controls the message is the master and the devices which are controlled by the master are the slaves see Figure 18 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Product data sheet Rev 3 2 September 2010 29
172. T INT Von High Level Output Voltage OPEN 0 Rload 1MQ 0 9 VLOGIC Vor Low Level Output Voltage OPEN 0 Rload 1MQ 0 1 VLOGIC 1 INT Low Level Output OPEN 1 0 3mA sink current 0 1 Output Leakage Current OPEN 1 100 tmr INT Pulse Width LATCH_INT_EN 0 VOLTAGE Voltage Range VLOGIC must be lt VDD at all times VLOGIC Ramp Rate Monotonic ramp Ramp rate is 10 to 90 of the final value see Figure in Section 4 4 Normal Operating Current 1 5 EE 5 5 7 2 2 2 4 4 Notes 1 Tested in production 2 Based on characterization of 30 pieces over temperature on evaluation board or in socket 4 Typical Randomly selected part measured at room temperature on evaluation board or in socket 5 Based on characterization of 5 pieces over temperature 6 Guaranteed by design 8 of 39 Document Number PS ITG 3200A 00 01 4 y Z He Revision 1 4 InvenSense ITG 3200 Product Specification e is asia 3 3 Electrical Specifications continued Typical Operating Circuit of Section 4 2 VDD 2 5V VLOGIC 1 71V to VDD 252 PC I O SCL SDA LOW Level Input Voltage 0 5 to 0 3 VLOGIC Vin HIGH Level Input Voltage 0 7 VLOGIC to VLOGIC 0 5V Vnyss Hysteresis 0 1 VLOGIC Voui LOW Level Output Voltage 3mA sink current 0 to 0 4 Tot LOW Level Output Current Vor 0 4V 3 Vor 0 6V 6 Output Leakage Current 100 tor Output Fall Time from Via to ViLmax Capacitance for Each I O pin 10 Cb bus cap in pF 20 0 1Cb to
173. UBLE_TAP Activity D3 D2 D1 DO Inactivity FREE_FALL Watermark Overrun Setting bits in this register to a value of 1 enables their respective functions to generate interrupts whereas a value of 0 prevents the functions from generating interrupts The DATA_READY watermark and overrun bits enable only the interrupt output the functions are always enabled It is recommended that interrupts be configured before enabling their outputs Register 0x2F INT_MAP R W D7 D6 D5 D4 DATA_READY SINGLE_TAP DOUBLE_TAP Activity D3 D2 D1 DO Inactivity FREE_FALL Watermark Overrun Any bits set to 0 in this register send their respective interrupts to the pin whereas bits set to 1 send their respective interrupts to the INT2 pin All selected interrupts for a given pin are ORed Register 0x30 INT SOURCE Read Only D7 D6 D5 D4 DATA_READY SINGLE_TAP DOUBLE_TAP Activity D3 D2 D1 DO Inactivity FREE_FALL Watermark Overrun Bits set to 1 in this register indicate that their respective functions have triggered an event whereas a value of 0 indicates that the corresponding event has not occurred The DATA_READY watermark and overrun bits are always set if the corresponding events occur regardless of the INT_ENABLE register settings and are cleared by reading data from the DATAX DATAY and DATAZ registers The DATA_READY and watermark bits may require multiple reads as indicated in the FIF
174. Wgyr modif 2 output sequence name connection type connection connection input promediadorl pitch lt input gt input resending input type ID ENT FLOAT input type input dimensions output resending lt output gt conversor_angulos1 pitch lt output gt lt sequence_name gt lt connection_type gt lt connection gt connection input correccionPI Mag1 Vmag 0 lt input gt input resending input type ID ENT FLOAT input type input dimensions output resending output magnetometrol Vmag 0 output sequence name connection gt lt connection gt connection input correccionPI Magl Vmag 1 input input resending input type ID ENT FLOAT input type input dimensions output resending output magnetometrol Vmag 1 output sequence name connection type lt connection gt connection input correccionPI Magl Vmag 2 input input resending input type ID ENT FLOAT input type input dimensions output resending output magnetometrol Vmag 2 output sequence name connection type connection connection input correccionPI Magl dcm matriz renorm 1 0 0 input input resending input type ID ENT FLOAT input type input dimensions output resending output renormalizarl dcm matriz renorm 1 0 0 output
175. YTE PUBLICO MODIFICABLE finalizado insertarPropiedad3 este gt nombre gt ciclo RT ID VAR INT PUBLICO MODIFICABLE t ciclo RT insertarPropiedad3 este gt nombre gt ciclo min ID VAR INT PUBLICO MODIFICABLE t ciclo min insertarPropiedad3 este gt nombre gt ciclo max ID VAR INT PUBLICO MODIFICABLE t ciclo max insertarPropiedad3 este gt nombre gt ciclo noRT ID VAR INT PUBLICO MODIFICABLE t ciclo noRT insertarPropiedad3 este gt nombre amp este t ciclo min ID VAR INT PUBLICO MODIFICABLE t ciclo noRT min insertarPropiedad3 este gt nombre amp este 5t ciclo noRT max ID VAR INT PUBLICO MODIFICABLE t ciclo noRT max principio registro de propiedades espec ficas pid pitch insertarPropiedad3 este gt nombre amp este proportional pitch ID VAR FLOAT PUBLICO MODIFICABLE proportional pitch insertarPropiedad3 este gt nombre amp este integral pitch ID VAR FLOAT PUBLICO MODIFICABLE integral pitch insertarPropiedad3 este gt nombre amp este derivative pitch ID VAR FLOAT PUBLICO MODIFICABLE derivative pitch insertarPropiedad3 este gt nombre amp este error pitch ID VAR FLOAT PUBLICO MODIFICABLE error pitch insertarPropiedad3 este gt nombre amp este variacion error pitch ID VAR FLOAT PUBLICO MODIFICABLE variacion error pitc
176. _1 0 2 este gt dcm_matriz_1 1 1 este gt dcm_matriz_1 2 1 este gt dcm_matriz_1 0 2 este gt dcm_matriz_1 1 0 este gt dcm_matriz_1 0 0 este gt dcm_matriz_1 1 2 este gt dcm_matriz_1 2 2 este gt dcm_matriz_1 0 0 este gt dcm_matriz_1 1 1 este gt dcm_matriz_1 0 1 este gt dcm_matriz_1 1 0 acumul 0 for c 0 c lt MAX_EJES c acumul acumul este gt dcm_matriz_1 0 c este gt dcm_matriz_1 0 c este gt renorm 5 3 acumul for c 0 c lt MAX_EJES c este gt dcm_matriz_renorm 0 c este gt dcm_matriz_1 0 c este gt renorm acumul 0 for c 0 c lt MAX_EJES c acumul acumul este gt dcm_matriz_1 1 c este gt dcm_matriz_1 1 c este gt renorm 5 3 acumul for c 0 c lt MAX_EJES c este gt dcm_matriz_renorm 1 c este gt dcm_matriz_1 1 c este gt renorm acumul 0 for c 0 c lt MAX EBJES c acumul acumul este gt dcm_matriz_1 2 c este gt dcm_matriz_1 2 c este gt renorm 5 3 acumul for c0 c lt MAX 5 c este dcm matriz renorm 2 c este dcm matriz 1 2 c este gt renorm j for x 0 x lt MAX EJES x for y Z0 y MAX EJES este dcm matriz renorm l x y este dcm matriz renorm x y fin c digo espec fico funcion normal renormalizar este gt t_ciclo_RT 0 41
177. _ENT_FLOAT lt input_type gt lt input_dimensions gt lt output_resending gt lt output gt renormalizar1 dcm_matriz_renorm_1 1 2 lt output gt lt sequence_name gt lt connection_type gt lt connection gt lt connection gt lt input gt correccionPI_Mag1 dcm_matriz_renorm_1 2 0 lt input gt lt input_resending gt lt input_type gt ID_ENT_FLOAT lt input_type gt lt input_dimensions gt lt output_resending gt output renormalizarl dcm matriz renorm 1 2 0 output sequence name connection type lt connection gt lt connection gt lt input gt correccionPI_Mag1 dcm_matriz_renorm_1 2 1 lt input gt lt input_resending gt lt input_type gt ID_ENT_FLOAT lt input_type gt lt input_dimensions gt lt output_resending gt output renormalizarl dcm matriz renorm 1 2 1 output sequence name connection type lt connection gt lt connection gt lt input gt correccionPI_Mag1 dcm_matriz_renorm_1 2 2 lt input gt lt input_resending gt lt input_type gt ID_ENT_FLOAT lt input_type gt lt input_dimensions gt lt output_resending gt lt output gt renormalizar1 dcm_matriz_renorm_1 2 2 lt output gt lt sequence_name gt lt connection_type gt lt connection gt lt connection gt lt input gt correccionPI_Magl Wgyr_modif_prom 0 lt input gt lt input_resending gt lt input_type gt ID_ENT_FLOAT lt input_type gt lt input_dimensions gt lt output_re
178. _ciclo_RT 0 416 if este gt t_ciclo_RT gt este gt t_ciclo_RT_max este 5t ciclo RT max este gt t_ciclo_RT else if este 5t ciclo RT lt este 5t ciclo RT min este 5t ciclo RT min este 5t ciclo RT 46 gt lt gt lt o lt 2 ope 2 E ol f lt 2 k k k k k k k k kK k k k k k K K k void funcionNormalNoRT O void funcion normal noRT correcionPI Acc void instancia int t ciclo struct correcionPI Acc este struct correcionPI Acc instancia ifdef LOG sprintf msgLog Normal function 96s este gt nombre logPrint msgLog 6 endif struct timespec ts crononsec 1 amp ts principio c digo espec fico funcion normal noRT correcionPI Acc fin c digo espec fico funcion normal noRT correcionPI_Acc gt ciclo noRT 0 amp ts if este 5t ciclo noRT gt gt ciclo noRT max este 5t ciclo noRT max este 5t ciclo noRT else 1 gt ciclo noRT lt gt ciclo noRT min este 5t ciclo noRT min este gt t_ciclo_noRT 2 2 k k ld k k kk k k K k k K void funcionFinaliza ON void funcion finaliza correcionPI_Acc void instancia struct correcionPI_Acc este struct correcionPI_Acc instancia ifdef LOG sprintf msgLog Finalizing 96s este gt nombre logPrint msgLog 3 endif principio c digo es
179. a bimodal behavior However the limits shown in Table 1 and Table 15 to Table 18 are valid for both potential self test values due to bimodality Use of the self test feature at data rates less than 100 Hz or at 1600 Hz may yield values outside these limits Therefore the part must be in normal power operation LOW POWER bit 0 in BW RATE register Address 0x2C and be placed into a data rate of 100 Hz through 800 Hz or 3200 Hz for the self test function to operate correctly X HIGH X LOW SELF TEST SHIFT LIMIT Y HIGH Y LOW Z HIGH Z LOW 07925 242 Vs V Figure 43 Self Test Output Change Limits vs Supply Voltage Table 14 Self Test Output Scale Factors for Different Supply Voltages Vs Supply Voltage Vs V X Axis Y Axis Z Axis 2 00 0 64 0 8 2 50 1 00 1 00 3 30 1 77 1 47 3 60 2 11 1 69 Table 15 Self Test Output in LSB for 2 g 10 Bit or Full Resolution Ta 25 C Vs 2 5 V 1 8 V Axis Min Max Unit X 50 540 LSB Y 540 50 LSB 7 75 875 15 Table 16 Self Test Output in LSB for 4 g 10 Bit Resolution Ta 25 C Vs 2 5 V Vovo 1 8 V Axis Min Max Unit X 25 270 LSB Y 270 25 LSB 7 38 438 LSB Table 17 Self Test Output in LSB for 8 g 10 Bit Resolution Ta 25 C Vs 2 5 V Vppyo 1 8 V Axis Min Max Unit X 12 135 LSB Y 135 12 15 7 19 219 15 Table 18 Self Test Outp
180. abilitado este gt finalizado 0 principio inicializaci n de propiedades espec ficas conversor_angulos este gt dcm_matriz_renorm 0 0 amp fdummy este gt dcm_matriz_renorm 0 1 amp fdummy amp fdummy este gt dcm_matriz_renorm 1 0 amp fdummy 110 101 este dcm matriz renorm 0 2 0 101 este gt dcm_matriz_renorm 1 1 amp fdummy este gt dcm_matriz_renorm 1 2 amp fdummy este gt dcm_matriz_renorm 2 0 amp fdummy este gt dcm_matriz_renorm 2 1 amp fdummy este gt dcm_matriz_renorm 2 2 amp fdummy fin inicializaci n de propiedades espec ficas conversor_angulos po o al o o k K K k K void registra_propiedades O int registra_propiedades_conversor_angulos void instancia struct conversor angulos este struct conversor angulos instancia char sauX MAX LONG NOMBRE int i j insertarNombre2 este gt nombre este emStrepy saux ID_SISTEMA ID_conversor_angulos NO_MODIFICABLE insertarPropiedad3 este gt nombre amp este gt nombre ID_VAR_TEXT PUBLICO nombre insertarPropiedad3 este gt nombre amp este gt orden ID_VAR_INT PUBLICO MODIFICABLE orden insertarPropiedad3 este gt nombre amp este gt habilitado ID_VAR_BYTE PUBLICO MODIFICABLE habilitado insertarPropiedad3 este gt nombre amp este gt finalizado ID_VAR_BYTE PUBLICO MODIFICABLE finalizado insertarPropiedad3 este gt nombre amp
181. agnetic calibration was done X_STP 400 Y STP 410 2 STP 420 2 If self test measurement at a different tmperature X STP 300 Lower than before Y 310 Lower than before 2 STP 320 Lower than before Then X TempComp 400 300 Y TempComp 410 310 Z TempComp 420 320 3 Applying to all new measurements X2X X TempComp Y Y Y_TempComp Z Z Z_TempComp Now all 3 axes are temperature compensated i e sensitivity is same as when the last magnetic calibration was done therefore the calibration coefficients can be applied without modification 4 Repeat this process periodically or for every At degrees of temperature change measured if available ORDERING INFORMATION Ordering Number Product _____ Caution This part is sensitive to damage by electrostatic discharge Use ESD HMC5883L T Cut Tape precautionary procedures when HMC5883L TR Tape and Reel 4k pieces reel touching removing or inserting CAUTION ESDS CAT 1B FIND OUT MORE For more information on Honeywell s Magnetic Sensors visit us online at www magneticsensors com or contact us at 1 800 323 8295 763 954 2474 internationally The application circuits herein constitute typical usage and interface of Honeywell product Honeywell does not warranty or assume liability of customer designed circuits derived from this description or depiction Honeywell reserves the right to make changes to improve reliability function or d
182. al the master can continue outputting data rather than transmitting a stop signal In this case the ITG 3200 device automatically increments the register address and loads the data to the appropriate register The following figures show single and two byte write sequences Single Byte Write Sequence Master S AD W RA DATA P Slave ACK ACK ACK Burst Write Sequence Master S AD W RA DATA DATA P Slave ACK ACK ACK ACK To read the internal ITG 3200 device registers the master first transmits the start condition S followed by the PC address and the write bit 0 At the 9 clock cycle when clock is high the ITG acknowledges the transfer The master then writes the register address that is going to be read Upon receiving the ACK signal from the ITG 3200 the master transmits a start signal followed by the slave address and read bit As a result the ITG 3200 sends an ACK signal and the data The communication ends with a not acknowledge NACK signal and a stop bit from master The NACK condition is defined such that the SDA line remains high at the 9 clock cycle To read multiple bytes of data the master can output an acknowledge signal ACK instead of a not acknowledge NACK signal In this case the ITG 3200 automatically increments the register address and outputs data from the appropriate register The following figures show single and two byte rea
183. al clock reference that provides blinking period and the duty cycle The OE pin can also be used as an external dimming control signal The frequency of the external clock must be high enough not to be seen by the human eye and the duty cycle value determines the brightness of the LEDs Power on reset When power is applied to Vpp an internal power on reset holds the PCA9685 in a reset condition until Vpp has reached At this point the reset condition is released and the 9685 registers and I2C bus state machine are initialized to their default states Thereafter must be lowered below 0 2 V to reset the device All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Product data sheet Rev 3 2 September 2010 26 of 51 Semiconductors 9685 16 channel 12 bit PWM 2 LED controller 7 6 Software reset The Software Reset Call SWRST Call allows all the devices in the 12C bus to be reset to the power up state value through a specific formatted 12C bus command To be performed correctly it implies that the 12C bus is functional and that there is no device hanging the bus The SWRST Call function is defined as the following 1 A START command is sent by the I2C bus master 2 The reserved SWRST I C bus address 0000 000 with the R W bit set to 0 write is sent by the I2C bus master 3 The 9685 de
184. alibration and the use of the offset registers refer to the Offset Calibration section Register 0x21 DUR Read Write The DUR register is eight bits and contains an unsigned time value representing the maximum time that an event must be above the THRESH threshold to qualify as a tap event The scale factor is 625 us LSB A value of 0 disables the single tap double tap functions Register 0x22 Latent Read Write The latent register is eight bits and contains an unsigned time value representing the wait time from the detection of a tap event to the start of the time window defined by the window register during which a possible second tap event can be detected The scale factor is 1 25 ms LSB A value of 0 disables the double tap function Register 0x23 Window Read Write The window register is eight bits and contains an unsigned time value representing the amount of time after the expiration of the latency time determined by the latent register during which a second valid tap can begin The scale factor is 1 25 ms LSB A value of 0 disables the double tap function Register 0x24 THRESH ACT Read Write The THRESH ACT register is eight bits and holds the threshold value for detecting activity The data format is unsigned so the magnitude of the activity event is compared with the value in the THRESH ACT register The scale factor is 62 5 mg LSB A value of 0 may result in undesirable behavior if the activity
185. ation provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Product data sheet Rev 3 2 September 2010 23 of 51 Semiconductors 9685 7 3 4 16 channel 12 bit PWM 2 LED controller ALL_LED_ON and ALL_LED_OFF control ALL LED ON and ALL LED OFF registers allow just four 2 write sequences to fill all the ON and OFF registers with the same patterns Table 7 ALL LED ON and ALL LED OFF control registers address FAh to FEh bit description Legend default value Address Register Bit Symbol Access Value Description FAh ALL LED ON 7 0 ALL LED 7 0 Wonly 0000 0000 LEDn ON count for ALL LED 8 MSBs FBh ALL LED ON H 7 5 reserved R 000 non writable 4 ALL LED ON W only 1 ALL_LED full 3 0 ALL LED ON H 3 0 W only 0000 LEDn ON count for ALL LED 4 MSBs FCh ALL LED OFF L 7 0 ALL LED OFF L 7 0 Wonly 0000 0000 LEDn OFF count for ALL LED 8 MSBs FDh ALL LED OFF H 7 5 reserved R 000 non writable 4 ALL LED OFF H4 Wonly 1 ALL_LED full OFF 3 0 ALL LED OFF H 3 0 W only 0000 LEDn OFF count for ALL LED 4 MSBs FEh PRE SCALE 7 0 SCALE 7 0 R W 0001 1110 prescaler to program the output frequency 7 3 5 PCA9685 The LEDn ON and LEDn OFF counts can vary from 0 to 4095 The LEDn ON and LEDn OFF count registers should never be programmed with the same values Because the loading of the LEDn ON and LEDn
186. ave device Each byte transferred must be followed by an acknowledge bit To acknowledge the slave device pulls the SDA line LOW and keeps it LOW for the high period of the SCL line Data transmission is always terminated by the master with a STOP condition P thus freeing the communications line However the master can generate a repeated START condition Sr and address another slave without first generating a STOP condition P A LOW to HIGH transition on the SDA line while SCL is HIGH defines the stop condition All SDA changes should take place when SCL is low with the exception of start and stop conditions Ar A AA E S START ADDRESS R W ACK DATA ACK DATA ACK STOP condition condition Complete C Data Transfer 19 of 39 Document Number PS ITG 3200A 00 01 4 5 Z Revision 1 4 InvenSense ITG 3200 Product Specification aser To write the internal ITG 3200 device registers the master transmits the start condition 5 followed by the address and the write bit 0 At the 9 clock cycle when the clock is high the ITG 3200 device acknowledges the transfer Then the master puts the register address RA on the bus After the ITG 3200 acknowledges the reception of the register address the master puts the register data onto the bus This is followed by the ACK signal and data transfer may be concluded by the stop condition P To write multiple bytes after the last ACK sign
187. bio_magnitud void instancia char nombre int orden unsigned char habilitado struct cambio magnitud este struct cambio magnitud instancia strcpy este gt nombre nombre este gt orden orden este gt habilitado habilitado este gt finalizado 0 principio inicializaci n de propiedades espec ficas cambio_magnitu este out pitch amp fdummy este out roll amp fdummy fin inicializaci n de propiedades espec ficas cambio magnitud void registra_propiedades II int registra propiedades cambio magnitud void instancia struct cambio magnitud este struct cambio magnitud instancia char saux MAX_LONG_NOMBRE insertarNombre2 este gt nombre este emStrcpy saux ID SISTEMA ID cambio magnitud NO MODIFICABLE insertarPropiedad3 este gt nombre amp este gt nombre ID VAR TEXT PUBLICO nombre insertarPropiedad3 este gt nombre amp este gt orden ID VAR INT PUBLICO MODIFICABLE orden insertarPropiedad3 este gt nombre amp este gt habilitado ID VAR BYTE PUBLICO MODIFICABLE habilitado insertarPropiedad3 este gt nombre amp este gt finalizado ID VAR BYTE PUBLICO MODIFICABLE finalizado insertarPropiedad3 este gt nombre amp este 5t ciclo RT ID VAR INT PUBLICO MODIFICABLE t ciclo RT insertarPropiedad3 este gt nombre gt ciclo min ID VAR INT PUBLICO MODIFICABLE t ciclo min in
188. cas microPWM j pool o o o o k k k k gt lt K k void registra_propiedades O int registra_propiedades_microPWM void instancia struct microPWM este struct microPWM instancia char sauX MAX LONG NOMBRE insertarNombre2 este gt nombre este emStrcpy saux ID_SISTEMA ID_microPWM NO_MODIFICABLE insertarPropiedad3 este gt nombre amp este gt nombre ID_VAR_TEXT PUBLICO nombre insertarPropiedad3 este gt nombre amp este gt orden ID VAR INT PUBLICO MODIFICABLE orden insertarPropiedad3 este gt nombre amp este gt habilitado ID VAR BYTE PUBLICO MODIFICABLE habilitado insertarPropiedad3 este gt nombre amp este gt finalizado ID VAR BYTE PUBLICO MODIFICABLE finalizado insertarPropiedad3 este gt nombre amp este gt t_ciclo_RT ID VAR INT PUBLICO MODIFICABLE t ciclo RT insertarPropiedad3 este gt nombre amp gt ciclo min ID VAR INT PUBLICO MODIFICABLE t ciclo RT min insertarPropiedad3 este gt nombre gt ciclo max ID VAR INT PUBLICO MODIFICABLE t ciclo max insertarPropiedad3 este gt nombre amp este t ciclo noRT ID VAR INT PUBLICO MODIFICABLE t ciclo noRT insertarPropiedad3 este gt nombre amp este t ciclo min ID VAR INT PUBLICO MODIFICABLE t ciclo noRT min insertarPropiedad3 este gt nombre amp este 5t ciclo noRT max ID VAR INT PUBLICO MODIFICABLE
189. cas referencias RR gt lt H lt 2 2 2 fe o 2 k ls ls ds ds ds ls ls ls le void funcionCrea IO int funcion crea referencias void instancia char nombre int orden unsigned char habilitado struct referencias este struct referencias instancia ifdef LOG sprintf msgLog Creating s nombre logPrint msgLog 3 endif inicializa_propiedades_referencias instancia nombre orden habilitado if registra_propiedades_referencias instancia 0 ifdef LOG sprintf msgLog s V Registering properties of s ID ERROR este gt nombre logPrint msgLog 1 endif if registrarInstancia instancia nombre amp clase referencias orden amp este gt habilitado amp este gt finalizado 0 1 ifdef LOG sprintf msgLog s V Registering instance s ID ERROR este gt nombre logPrint msgLog 1 endif k k fe k k K void funcionInicializa k k k k k k k k k k k k k k k kk k kk k k f lt k k gt e K k void funcion_inicializa_referencias void instancia struct referencias este struct referencias instancia ifdef LOG sprintf msgLog Initializing 95 este gt nombre logPrint msgLog 3 endif este gt t_ciclo_RT_min 0x10000000 este 5t ciclo RT max 0 gt ciclo noRT min 0x10000000 gt ciclo noRT max 0 principio c digo espec fico funcion inicializa referen
190. cations are sent from the master to this slave device and succeed the 7 bit address 0x1E plus 1 bit read write identifier i e OX3D for read and Ox3C for write To minimize the communication between the master and this device the address pointer updated automatically without master intervention The register pointer will be incremented by 1 automatically after the current register has been read successfully The address pointer value itself cannot be read via the 2 bus Any attempt to read an invalid address location returns 075 and any write to an invalid address location or an undefined bit within a valid address location is ignored by this device To move the address pointer to a random register location first issue a write to that register location with no data byte following the commend For example to move the address pointer to register 10 send 0x3C 0x0A www honeywell com 11 HMC5883L Configuration Register A The configuration register is used to configure the device for setting the data output rate and measurement configuration CRAO through CRA7 indicate bit locations with CRA denoting the bits that are in the configuration register CRA7 denotes the first bit of the data stream The number in parenthesis indicates the default value of that bit CRA default is 0x10 CRA7 6 CRA5 CRA4 CRA3 CRA2 CRA1 0 0 MA1 0 MAO 0 1 DO1 0 DOO 0 MS1 0 MSO 0 Tabl
191. ccl dem_matriz_renorm_1 2 1 lt input gt lt input_resending gt lt input_type gt ID_ENT_FLOAT lt input_type gt lt input_dimensions gt lt output_resending gt lt output gt renormalizar1 dcm_matriz_renorm_1 2 1 lt output gt lt sequence_name gt lt connection_type gt lt connection gt lt connection gt lt input gt correcionPI_Acc1 dcm_matriz_renorm_1 2 2 lt input gt lt input_resending gt lt input_type gt ID_ENT_FLOAT lt input_type gt lt input_dimensions gt lt output_resending gt lt output gt renormalizar1 dcm_matriz_renorm_1 2 2 lt output gt lt sequence_name gt lt connection_type gt lt connection gt lt connection gt lt input gt promediadorl Wgyr_modif 0 lt input gt lt input_resending gt input type ID ENT FLOAT input type input dimensions output resending output correcionPI Accl Wgyr modif 0 output sequence name connection type connection connection input promediadorl Wgyr modif 1 input input resending input type ID ENT FLOAT input type input dimensions output resending output correcionPI Accl Wgyr modif 1 output sequence name connection type connection connection lt input gt promediadorl Wgyr_modif 2 lt input gt lt input_resending gt input type ID ENT FLOAT input type input dimensions output resending output correcionPI Accl
192. ce voltage level is set with the interface supply voltage Vono which must be present to ensure that the ADXL345 does not create a conflict on the communication bus For single supply operation Von yo can be the same as the main supply Vs In a dual supply application however can differ from Vs to accommodate the desired interface voltage as long as Vs is greater than or equal to After Vsis applied the device enters standby mode where power consumption is minimized and the device waits for Vppyo to be applied and for the command to enter measurement mode to be received This command can be initiated by setting the measure bit Bit D3 in the POWER CTL register Address 0x2D In addition while the device is in standby mode any register can be written to or read from to configure the part It is recommended to configure the device in standby mode and then to enable measurement mode Clearing the measure bit returns the device to the standby mode Condition Vs Vooo Description Power Off Off Off Bus Disabled On Off prevent a conflict Bus Enabled Off On Standby or Measurement On On The device is completely off but there is a potential for a communication bus conflict The device is on in standby mode but communication is unavailable and creates a conflict on the communication bus The duration of this state should be minimized during power up to No functions are available b
193. ceiving command to data ready 6 ms Turn on Time Ready for 2 commands 200 us Analog Circuit Ready for Measurements 50 ms Gain Tolerance All gain dynamic range settings 5 IC Address 8 bit read address 0x3D hex 8 bit write address 0x3C hex C Rate Controlled by Master 400 kHz Hysteresis Hysteresis of Schmitt trigger inputs on SCL and SDA Fall VDDIO 1 8V 0 2 VDDIO Volts Rise VDDIO 1 8V 0 8 VDDIO Volts Self Test X amp Y Axes 1 16 gauss Z Axis 1 08 X 8 Y 8 Z Axes GN 5 Positive Bias 243 575 LSb X 8 Y 8 Z Axes GN 5 Negative Bias 575 243 Sensitivity Tempco Ta 40 to 125 C Uncompensated Output 0 3 General ESD Voltage Human Body Model all pins 2000 Volts Charged Device Model all pins 750 Operating Temperature Ambient 30 85 Storage Temperature Ambient unbiased 40 125 www honeywell com HMC5883L Characteristics Conditions Min Typ Max Units Reflow Classification MSL 3 260 C Peak Temperature Package Size Length and Width 2 85 3 00 3 15 mm Package Height 0 8 0 9 1 0 mm Package Weight 18 mg Absolute Maximum Ratings Tested at 25 except stated otherwise Characteristics Min Max Units Supply Voltage VDD 0 3 4 8 Volts Supply Voltage VDDIO 0 3 4 8 Volts PIN CONFIGURATIONS Pin Name Description 1 SCL Serial Clock Master Slave Clock 2 VDD Power Supply 2 16V
194. ched devices can be a master or a slave The master device puts the slave address on the bus and the slave device with the matching address acknowledges the master The ITG 3200 always operates as a slave device when communicating to the system processor which thus acts as the master SDA and SCL lines typically need pull up resistors to VDD The maximum bus speed is 400kHz The slave address of the ITG 3200 devices is b110100X which is 7 bits long The LSB bit of the 7 bit address is determined by the logic level on pin 9 This allows two ITG 3200 devices to be connected to the same bus When used in this configuration the address of the one of the devices should be b1101000 pin 9 is logic low and the address of the other should be b1101001 pin 9 is logic high The address is stored in register 0 WHO I register Communications Protocol START S and STOP P Conditions Communication on the bus starts when the master puts the START condition S on the bus which is defined as a HIGH to LOW transition of the SDA line while SCL line is HIGH see figure below The bus is considered to be busy until the master puts a STOP condition P on the bus which is defined as a LOW to HIGH transition on the SDA line while SCL is HIGH see figure below Additionally the bus remains busy if a repeated START Sr is generated instead of a STOP condition C 1 e RR AAA START condition STOP condition START and
195. cias este reference pitch 0 este reference roll 0 fin c digo espec fico funcion inicializa referencias 46 gt lt gt lt H lt ol 2 gt lt k k k K K k void funcionNormal O void funcion normal referencias void instancia int t ciclo struct referencias este struct referencias instancia ifdef LOG sprintf msgLog Normal function 96s este gt nombre logPrint msgLog 6 endif struct timespec ts crononsec 1 amp ts principio c digo espec fico funcion normal referencias fin c digo espec fico funcion normal referencias este t ciclo RT 0 amp ts if este t ciclo RT gt este t ciclo RT max este 5t ciclo RT max este 5t ciclo RT else if este gt t_ciclo_RT lt este gt t_ciclo_RT_min este gt t_ciclo_RT_min este gt t_ciclo_RT k k k k k gt lt void funcionNormalNoRT II void funcion_normal_noRT_referencias void instancia int t ciclo 1 struct referencias este struct referencias instancia ifdef LOG sprintf msgLog Normal function 96s este gt nombre logPrint msgLog 6 endif struct timespec ts crononsec 1 amp ts principio c digo espec fico funcion normal noRT referencias I fin c digo espec fico funcion normal noRT referencias este gt t_ciclo_noRT 0 amp ts if este gt t_ciclo_noRT gt este g
196. cision in axis sensitivity and linearity These sensors solid state construction with very low cross axis sensitivity is designed to measure both the direction and the magnitude of Earth s magnetic fields from milli gauss to 8 gauss Honeywell s Magnetic Sensors are among the most sensitive and reliable low field sensors in the industry FEATURES 3 Axis Magnetoresistive Sensors and ASIC in a 3 0x3 0x0 9mm LCC Surface Mount Package 12 Bit ADC Coupled with Low Noise AMR Sensors Achieves 2 milli gauss Field Resolution in 8 Gauss Fields Built In Self Test Low Voltage Operations 2 16 to 3 6V and Low Power Consumption 100 pA Built In Strap Drive Circuits Digital Interface Lead Free Package Construction Wide Magnetic Field Range 8 Oe Software and Algorithm Support Available Fast 160 Hz Maximum Output Rate BENEFITS Small Size for Highly Integrated Products Just Add Controller Interface Plus Two External SMT Capacitors Designed for High Volume Cost Sensitive OEM Designs Easy to Assemble amp Compatible with High Speed Assembly Enables 1 to 2 Degree Compass Heading Accuracy Enables Low Cost Functionality Test after Assembly in Production Compatible for Battery Powered Applications Set Reset and Offset Strap Drivers for Degaussing Self Test and Offset Compensation Popular Two Wire Serial Data Interface for Consumer Electronics RoHS Compliance Sensors Can Be
197. communications are available In both cases the ADXL345 operates as a slave mode is enabled if the CS pin is tied high to Vppyo The CS pin should always be tied high to or be driven by an external controller because there is no default mode if the CS pin is left unconnected Therefore not taking these precautions may result in an inability to communicate with the part In SPI mode the CS pin is controlled by the bus master In both SPI and C modes of operation data transmitted from the ADXL345 to the master device should be ignored during writes to the ADXL345 SPI For SPI either 3 or 4 wire configuration is possible as shown in the connection diagrams in Figure 34 and Figure 35 Clearing the SPI bit Bit D6 in the DATA FORMAT register Address 0x31 selects 4 wire mode whereas setting the SPI bit selects 3 wire mode The maximum SPI clock speed is 5 MHz with 100 pF maximum loading and the timing scheme follows clock polarity CPOL 1 and clock phase CPHA 1 If power is applied to the ADXL345 before the clock polarity and phase of the host processor are configured the CS pin should be brought high before changing the clock polarity and phase When using 3 wire SPI it is recommended that the SDO pin be either pulled up to or pulled down to GND via a 10 resistor ADXL345 PROCESSOR 07925 004 07925 003 Figure 35 4 Wire SPI Connection Diagram CS is the serial port enable line and is
198. conductors 9685 7 1 3 9685 16 channel 12 bit PWM 2 LED controller e PCA9564 0000 000 or PCA9665 1110 000 slave address which is active start up reserved for future use 2 addresses 0000 011 1111 1XX slave devices that use the 10 bit addressing scheme 1111 OXX slave devices that are designed to respond to the General Call address 0000 000 which is used as the software reset address High speed mode Hs mode master code 0000 1XX slave address OOOO 4 2 fixed hardware selectable 002aad168 Fig 4 Slave address The last bit of the address byte defines the operation to be performed When set to logic 1 a read is selected while a logic O selects a write operation LED All Call I2C bus address Default power up value ALLCALLADR register EOh or 1110 000 Programmable through I2C bus volatile programming At power up LED All Call 12C bus address is enabled PCA9685 sends ACK when EOh R W 0 or Eth R W 1 is sent by the master See Section 7 3 7 ALLCALLADR LED All Call 12C bus address for more detail Remark The default LED All Call 12C bus address EOh or 1110 000X must not be used as a regular 12C bus slave address since this address is enabled at power up All the PCA9685s on the 2 will acknowledge the address if sent by the 2 master LED Sub Call I2C bus addresses diffe
199. conversor angulos logPrint msgLog 3 endif clase_conversor_angulos funcionCrea funcion_crea_conversor_angulos clase_conversor_angulos funcionInicializa funcion_inicializa_conversor_angulos clase_conversor_angulos funcionNormal funcion_normal_conversor_angulos clase_conversor_angulos funcionNormalNoRT funcion_normal_noRT_conversor_angulos clase_conversor_angulos funcionFinaliza funcion_finaliza_conversor_angulos ifdef ID LISTAS iniciarLista amp instancias conversor angulos else clase_conversor_angulos n 0 clase_conversor_angulos maxNumComp MAX_conversor_angulos endif clase_conversor_angulos instancias amp instancias_conversor_angulos clase_conversor_angulos longComponente sizeof struct conversor_angulos return insertarPropiedad2 ID_ COMPONENTE ID_conversor_angulos amp clase conversor angulos ID COMPONENTE NO MODIFICABLE j INSTANCIA DE REFERENCIAS referencias h referencias h ok Variables utilizadas referencias c 11 06 2014 Eugenio Alcal Baselga ftinclude cosme h Hdefine ID referencias referencias Hdefine MAX referencias 16 struct referencias char nombre MAX LONG NOMBRE int orden byte habilitado byte finalizado int t ciclo RT intt ciclo RT min int t ciclo max int t ciclo noRT int t ciclo noRT min int t ciclo noRT max salidas float reference pitch float reference roll referencias c referencias c
200. cts planned as well as for the planned application and use of customer s third party customer s Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products NXP Semiconductors does not accept any liability related to any default damage costs or problem which is based on any weakness or default in the customer s applications or products or the application or use by customer s third party customer s Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer s NXP does not accept any liability in this respect Limiting values Stress above one or more limiting values as defined in the Absolute Maximum Ratings System of IEC 60134 will cause permanent damage to the device Limiting values are stress ratings only and proper operation of the device at these or any other conditions above those given in the Recommended operating conditions section if present or the Characteristics sections of this document is not warranted Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device Terms and conditions of commercial sale NXP Semiconductors products are sold subject to the general term
201. d tcspis 150 ns CS deassertion between SPI communications ts 0 3 ns SCLK low pulse width space 0 3 ns SCLK high pulse width mark tsetup 5 ns SDI valid before SCLK rising edge tHoLD 5 ns SDI valid after SCLK rising edge tspo 40 ns SCLK falling edge to SDO SDIO output transition tr 20 ns SDO SDIO output high to output low transition tr 20 ns SDO SDIO output low to output high transition The CS SCLK SDI and SDO pins are not internally pulled up or down they must be driven for proper operation Limits based on characterization results characterized with 5 MHz and bus load capacitance of 100 pF not production tested 3 The timing values are measured corresponding to the input thresholds Vi and given in Table 9 Output rise and fall times measured with capacitive load of 150 pF Rev D Page 17 of 40 ADXL345 PC With CS tied high to the ADXL345 is in mode requiring a simple 2 wire connection as shown in Figure 40 ADXL345 conforms to the UM10204 Specification and User Manual Rev 03 19 June 2007 available from NXP Semiconductor data transfer modes if the bus parameters given in Table 11 and Table 12 are met Single or multiple byte reads writes are supported as shown in Figure 41 With the ALT ADDRESS pin high the 7 bit address for the device is Ox1D followed by the R W bit This translates to 0x3A for a write and 0x3B for a read An alternate
202. d by the user Both registers will hold a value from 0 to 4095 One 12 bit register will hold a value for the ON time and the other 12 bit register will hold the value for the OFF time The ON and OFF times are compared with the value of a 12 bit counter that will be running continuously from 0000h to OFFFh 0 to 4095 decimal Update on ACK requires all 4 PWM channel registers to be loaded before outputs will change on the last ACK The ON time which is programmable will be the time the LED output will be asserted and the OFF time which is also programmable will be the time when the LED output will be negated In this way the phase shift becomes completely programmable The resolution for the phase shift is Y4g9g of the target frequency Table 6 lists these registers The following two examples illustrate how to calculate values to be loaded into these registers PCA9685 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Product data sheet Rev 3 2 September 2010 15 of 51 Semiconductors 9685 16 channel 12 bit PWM 2 LED controller Example 1 assumes that the LEDO output is used and delay time PWM duty cycle lt 100 Delay time 10 PWM duty cycle 20 LED on time 20 LED off time 80 Delay time 10 96 409 6 410 counts 19 Since the counter starts at O and ends at 4095 we will subtract 1 so d
203. d gt lt instance gt lt instance gt lt instance_name gt referencias1 lt instance_name gt lt component gt SISTEMA COMPONENTE referencias lt component gt lt specific_component gt lt creation_date gt lt order gt 1 1 lt order gt lt collapsed gt lt default_location gt lt tabs gt lt enabled gt true lt enabled gt lt instance gt lt instance gt lt instance_name gt pid_pitch1 lt instance_name gt lt component gt SISTEMA COMPONENTE pid_pitch lt component gt lt specific_component gt lt creation_date gt lt order gt 12 lt order gt lt collapsed gt lt default_location gt lt tabs gt lt enabled gt true lt enabled gt lt instance gt lt instance gt instance name pid rolll instance name lt component gt SISTEMA COMPONENTE pid_roll lt component gt lt specific_component gt lt creation_date gt lt order gt 13 lt order gt lt collapsed gt lt default_location gt lt tabs gt lt enabled gt true lt enabled gt lt instance gt lt instance gt instance name cambio magnitudl instance name component SISTEMA COMPONENTE cambio magnitud component specific component creation date order 14 order collapsed default location lt tabs gt lt enabled gt true lt enabled gt lt instance gt lt instance gt lt instance_name gt microPWM 1 lt instance_name gt lt component gt SISTEMA COMPONENTE microPWM lt component gt lt
204. d sequences Single Byte Read Sequence Master S AD W RA S AD R NACK Slave ACK ACK ACK DATA Burst Read Sequence Master S AD W RA S AD R ACK NACK Slave ACK ACK ACK DATA DATA 20 of 39 Document Number PS ITG 3200A 00 01 4 m Revision 1 4 InvenSense ITG 3200 Product Specification se o asia Terms Signal Description S Start Condition SDA goes from high to low while SCL is high AD Slave address W Write bit 0 R Read bit 1 ACK Acknowledge SDA line is low while the SCL line is high at the 9 clock cycle NACK Not Acknowledge SDA line stays high at the 9 clock cycle RA ITG 3200 internal register address DATA Transmit or received data P Stop condition SDA going from low to high while SCL is high 21 of 39 Document Number PS ITG 3200A 00 01 4 Z He Revision 1 4 InvenSense ITG 3200 Product Specification 03 30 2010 7 Register ade Register Name R W Bit7 Bit Bits Bit3 Bit2 Bitl Hex Decimal LATCH_ ITG_RDY RAW_ RAW_ INT_STATUS DATA_ ITG_RDY RDY TEMP_OUT_H TEMP_OUT_H TEMP_OUT_L TEMP_OUT_L GYRO_XOUT_H GYRO_ZOUT_H GYRO_ZOUT_L PWR_MGM H_RESET SLEEP STBY_XG STBY_YG STBY_ZG CLK_SEL GYRO_YOUT_H GYRO_YOUT_L 23 26 9 R H 2 x x 3 H R
205. d three LED Sub Call addresses allow groups of devices to be addressed at the same time in any combination for example one register used for Call so that all the PCA9685s on the I2C bus be addressed at the same time and the second register used for three different addresses so that 1 3 of all devices on the bus be addressed at the same time in a group Software enable and disable for these I2C bus address Software Reset feature SWRST General Call allows the device to be reset through the 12C bus All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Product data sheet Rev 3 2 September 2010 2 of 51 Semiconductors 9685 3 Applications 16 channel 12 bit PWM 2 LED controller 25 MHz typical internal oscillator requires no external components External 50 MHz max clock input Internal power on reset Noise filter on SDA SCL inputs Edge rate control on outputs No output glitches on power up Supports hot insertion Low standby current Operating power supply voltage range of 2 3 V to 5 5 V 5 5 V tolerant inputs 40 C to 85 C operation ESD protection exceeds 2000 V HBM per JESD22 A114 200 V MM per JESD22 A115 and 1000 V CDM per JESD22 C101 Latch up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Packages offered 55 28 HVQFN28 RGB or RGBA LED drivers LED status i
206. d to the existing field strength using a reduced gain setting prevents sensor from being saturated and data registers overflowed For example if the configuration register is set to 0 0 Gain 5 values around 452 LSb 1 16 Ga 390 LSb Ga will be placed in the X and Y data output registers and around 421 1 08 Ga 390 LSb Ga will be placed Z data output register To leave the self test mode change MS1 and MSO bit of the configuration register A back to 00 Normal Measurement Mode Acceptable limits of the self test values depend on the gain setting Limits for Gain 5 is provided in the specification table Below is an example of a positive self test process using continuous measurement mode Write CRA 00 send Ox3C 0x00 0x71 8 average 15 Hz default positive self test measurement Write CRB 01 send 0x3C 0x01 0xAO Gain 5 Write Mode 02 send 0x3C 0x02 0x00 Continuous measurement mode Wait 6 ms or monitor status register or DRDY hardware interrupt pin Loop Send Ox3D 0x06 Read all 6 bytes If gain is changed then this data set is using previous gain Convert three 16 bit 2 s compliment hex values to decimal values and assign to X Z Y respectively Send 0x3C 0x03 point to first data register 03 Wait about 67 ms if 15 Hz rate or monitor status register or DRDY hardware interrupt pin End loop 6 Check limits If all 3 axes X Y and 2 are within reasonable limits 243 to 575 for Gain 5 adjust these limits
207. dc coupled operation and a setting of 1 enables ac coupled operation In dc coupled operation the current acceleration magnitude is compared directly with 5 ACT and INACT to determine whether activity or inactivity is detected In ac coupled operation for activity detection the acceleration value at the start of activity detection is taken as a reference value New samples of acceleration are then compared to this reference value and if the magnitude of the difference exceeds the 5 ACT value the device triggers an activity interrupt Similarly in ac coupled operation for inactivity detection a reference value is used for comparison and is updated whenever the device exceeds the inactivity threshold After the reference value is selected the device compares the magnitude of the difference between the reference value and the current acceleration with THRESH INACT If the difference is less than the value in THRESH INACT for the time in TIME INACT the device is considered inactive and the inactivity interrupt is triggered Rev D Page 24 of 40 ACT_x Enable Bits INACT_x Enable Bits A setting of 1 enables x y or z axis participation in detecting activity or inactivity A setting of 0 excludes the selected axis from participation If all axes are excluded the function is disabled For activity detection all participating axes are logically ORed causing the activity function to trigger when
208. details Power Management This device has two different domains of power supply The first one is VDD that is the power supply for internal operations and the second one is VDDIO that is dedicated to IO interface It is possible to work with VDDIO equal to VDD Single Supply mode or with VDDIO lower than VDD allowing HMC5883L to be compatible with other devices on board Interface Control of this device is carried out via the IC bus This device will be connected to this bus as a slave device under the control of a master device such as the processor This device is compliant with Specification document number 9398 393 40011 As an lC compatible device this device has a 7 bit serial address and supports FG protocols This device supports standard and fast modes 100kHz and 400kHz respectively but does not support the high speed mode Hs External pull up resistors are required to support these standard and fast speed modes Activities required by the master register read and write have priority over internal activities such as the measurement The purpose of this priority is to not keep the master waiting and the I C bus engaged for longer than necessary Internal Clock The device has an internal clock for internal digital logic functions and timing management This clock is not available to external usage www honeywell com 9 HMC5883L H Bridge for Set Reset Strap Drive The ASIC contains large switching FETs
209. detected which is determined by the value in the window register Address 0x23 e The interval after the latency time set by the latent register is defined by the window register Although a second tap must begin after the latency time has expired it need not finish before the end of the time defined by the window register FIRST TAP SECOND TAP THRESHOLD iE ce LU E Lu EN Ee CU Eau S L TRS URS TIME WINDOW FOR LATENCY SECOND TAP WINDOW LATENT eo ETE ED UT a z SINGLE DOUBLE x h INTERRUPT INTERRUPT 5 z Figure 46 Interrupt Function with Valid Single and Double Taps If only the single tap function is in use the single tap interrupt is triggered when the acceleration goes below the threshold as long as DUR has not been exceeded If both single and double tap functions are in use the single tap interrupt is triggered when the double tap event has been either validated or invalidated Rev D Page 28 of 40 Several events occur to invalidate the second tap of a double tap event First if the suppress bit in the TAP_AXES register Address 0x2A is set any acceleration spike above the threshold during the latency time set by the latent register invalidates the double tap detection as shown in Figure 47 INVALIDATES DOUBLE TAP IF SUPRESS BIT SET TIME LIMIT gt gt FORTAPS LATENCY TI
210. diador funcionNormalNoRT funcion_normal_noRT_promediador clase_promediador funcionFinaliza funcion_finaliza_promediador ifdef ID_LISTAS iniciarLista amp instancias_promediador else clase_promediador n 0 clase_promediador maxNumComp MAX_promediador endif clase promediador instancias amp instancias promediador clase promediador longComponente sizeof struct promediador return insertarPropiedad2 ID COMPONENTE ID_promediador amp clase promediador ID COMPONENTE NO MODIFICABLE INSTANCIA CON DATOS DEL MAGNETOMETRO correccionPI Mag h correccionPI Mag h Variables utilizadas en correccionPI_Mag c 11 06 2014 Eugenio Alcal Baselga ftinclude cosme h define ID correccionPI Mag correccionPI Mag define MAX correccionPI Mag 16 define MAX EJES 3 struct correccionPI Mag 1 char nombre MAX LONG NOMBRE int orden byte habilitado byte finalizado int t ciclo RT intt ciclo RT min int t ciclo max int t ciclo noRT int t ciclo noRT min int t ciclo noRT max float Kp Yaw En adelante estas dos constantes meterlas en varia float Ki Yaw float Omega P Compass MAX EJES float Omega I Compass MAX EJES float errorYaw MAX EJES float Scaled Omega Compass MAX EJES entradas float Vmag MAX EJES float Wgyr modif prom MAX EJES float matriz renorm EJES MAX EJES salidas float Wgyr fin MAX EJES corr
211. e 6 data output by receiver Y acknowledge 7 SCL from master 7 4 J BN fe 5 clock pulse for t START acknowledgement condition 002aaa987 Fig 19 Acknowledgement on the I2C bus All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Product data sheet Rev 3 2 September 2010 30 of 51 Semiconductors 9685 16 channel 12 bit PWM 2 LED controller 9 Bus transactions slave address control register data for register 0 7 0 1 o a orjos ne os Jefe t t START condition R W acknowledge acknowledge acknowledge from slave from slave from slave STOP condition 002aac829 1 See Table 3 for register definition Fig 20 Write to a specific register slave address control register MODE1 register MODE 1 register register RRC po e opone oo e t START condition R W acknowledge acknowledge Al bit set acknowledge acknowledge from slave from slave from slave from slave LED15 OFF L register LED15 OFF H register A A acknowledge acknowledge from slave from slave STOP condition 002aad187 Fig 21 Write to all registers using the Auto Increment feature Al initially clear 9685 All information provided this document is subject to legal disclaimers NXP B V 2010 All rights reserved
212. e AL PERFORMANCE CHARACTERISTICS 8 6 4 2 0 150 100 50 0 50 100 150 ZERO OFFSET mg PERCENT OF POPULATION 3 si Figure 4 X Axis Zero g Offset at 25 C Vs 2 5 V 8 6 4 2 0 150 100 50 0 50 100 150 ZERO g OFFSET mg PERCENT OF POPULATION 3 Figure 5 Y Axis Zero g Offset at 25 Vs 2 5 V 8 6 4 2 0 150 100 50 0 50 100 150 ZERO g OFFSET mg Figure 6 Z Axis Zero g Offset at 25 C Vs 2 5 V 07925 204 07925 205 07925 206 Rev D Page 8 of 40 PERCENT OF POPULATION 96 PERCENT OF POPULATION PERCENT OF POPULATION 96 E o E A E N o 2 0 150 100 50 0 50 100 ZERO OFFSET mg Figure 7 X Axis Zero Offset at 25 C Vs 3 3 V 150 2 0 150 100 50 0 50 100 ZERO OFFSET mg Figure 8 Y Axis Zero Offset at 25 Vs 3 3 V 150 o
213. e gt lt connection gt lt connection gt lt input gt renormalizar1 DCM_Matriz 1 0 lt input gt lt input_resending gt lt input_type gt ID_ENT_FLOAT lt input_type gt lt input_dimensions gt lt output_resending gt lt output gt actualizar_matriz1 DCM_Matriz 1 0 lt output gt lt sequence_name gt lt connection_type gt lt connection gt lt connection gt lt input gt renormalizar1 DCM_Matriz 1 1 lt input gt lt input_resending gt lt input_type gt ID_ENT_FLOAT lt input_type gt lt input_dimensions gt lt output_resending gt lt output gt actualizar_matrizl DCM_Matriz 1 1 lt output gt lt sequence_name gt connection type lt connection gt lt connection gt lt input gt renormalizar1 DCM_Matriz 1 2 lt input gt lt input_resending gt lt input_type gt ID_ENT_FLOAT lt input_type gt lt input_dimensions gt lt output_resending gt lt output gt actualizar_matriz1 DCM_Matriz 1 2 lt output gt lt sequence_name gt lt connection_type gt lt connection gt lt connection gt lt input gt renormalizar1 DCM_Matriz 2 0 lt input gt lt input_resending gt lt input_type gt ID_ENT_FLOAT lt input_type gt lt input_dimensions gt lt output_resending gt lt output gt actualizar_matrizl DCM_Matriz 2 0 lt output gt lt sequence_name gt connection type lt connection gt lt connection gt lt input gt renormalizar1 DCM_Matriz 2 1 lt input gt
214. e gt Vmag 1 hmc5883 calib y este gt Vmag 2 1 26 este gt Vmag 2 hmc5883 calib z fin c digo espec fico funcion normal magnetometro este gt t_ciclo_RT 0 amp ts gt ciclo RT gt este gt t_ciclo_RT_max este 5t ciclo RT max este gt t_ciclo_RT else if este gt t_ciclo_RT lt este gt t_ciclo_RT_min este gt t_ciclo_RT_min este 5t ciclo RT 346 gt lt gt lt lt ol ol a k k k k kkk k kk k k k k k K K k void funcionNormalNoRT O void funcion_normal_noRT_magnetometro void instancia int t_ciclo struct magnetometro este struct magnetometro instancia ifdef LOG sprintf msgLog Normal function 96s este gt nombre logPrint msgLog 6 endif struct timespec ts crononsec 1 amp ts principio c digo espec fico funcion normal noRT magnetometro I fin c digo espec fico funcion normal noRT magnetometro este gt t_ciclo_noRT crononsec 0 amp ts if este gt t_ciclo_noRT gt este gt t_ciclo_noRT_max este gt t_ciclo_noRT_max este gt t_ciclo_noRT else if este gt t_ciclo_noRT lt este gt t_ciclo_noRT_min este gt t_ciclo_noRT_min este gt t_ciclo_noRT k k fe K k gt e K K void funcionFinaliza k k k kk k kk k kk k k kkk k kk kk f lt k k gt e K k void funcion_finaliza_magnetometro void instancia struct magnetometro este st
215. e gt t_ciclo_RT_min 0x10000000 este 5t ciclo RT max 0 gt ciclo noRT min 0x10000000 gt ciclo noRT max 0 principio c digo espec fico funcion inicializa microPWM este gt condicion 0 if ioctl este gt fd DC SLAVE PCA9685_I2C_ADDR lt 0 strcpy este gt error_msg_micro_PWM 9685 is not present n writeto_PCA9685 este gt fd 0x00 0x00 Configuramos el registro MODEI este gt freq 333 este gt prescaleval 25000000 float 4096 este gt freq 1 if 1 printf Frecuencia PWM a i Hz n este gt freq printf Preescalado estimado 3 2f M este gt prescaleval este gt prescale floor este gt prescaleval 0 5 floor redondea hacia abajo if 1 printf Preescalado final 3 2f n este gt prescale oldmode 12c_smbus_read_byte_data este gt fd MODEL int newmode oldmode amp 0x7F 10 10 12c_smbus_write_byte_data este gt fd MODEI newmode 12 smbus write byte data este fd PRESCALE int floor este gt prescale 12 smbus write byte data este fd MODEI oldmode sleep 0 005 12 smbus write byte data este fd MODEI oldmode 0x80 setPWM este gt fd 4 0 1710 setPWM este gt fd 2 0 1710 setPWM este gt fd 8 0 1710 setPWM este gt fd 10 0 1710 fin c digo espec fico funcion inicializa microPWM k k k k k k k k k k k k k k kk k k
216. e 3 Configuration Register A Location Name Description CRA7 CRA7 Bit CRA7 is reserved for future function Set to 0 when configuring CRA CRA6 to CRA5 MA1 to MAO measurement output 00 1 Default 01 2 10 4 11 8 CRA4 to CRA2 DO2 to DOO Data Output Rate Bits These bits set the rate at which data is written to all three data output registers CRA1 to CRAO MS1 to MSO measurement flow of the device specifically whether or not Measurement Configuration Bits These bits define the to incorporate an applied bias into the measurement Table 4 Configuration Register A Bit Designations The Table below shows all selectable output rates in continuous measurement mode All three channels shall be measured within a given output rate Other output rates with maximum rate of 160 Hz can be achieved by monitoring DRDY interrupt pin in single measurement mode 12 DO2 DO1 DOO Typical Data Output Rate Hz 0 0 0 0 75 0 0 1 1 5 0 1 0 3 0 1 1 7 5 0 15 Default 0 75 1 Reserved Table 5 Data Output Rates MS1 MSO Measurement Mode Normal measurement configuration Default In normal measurement 0 0 configuration the device follows normal measurement flow The positive and negative pins of the resistive load are left floating and high impedance 0 1 Positive bias configuration for X
217. e of the device be limited to provide minimal offset shift across the operating temperature range Due to variability between parts it is also recommended that calibration over temperature be performed if any data rates below 6 25 Hz are in use 140 120 T 2 100 E a E 80 o 0 10Hz 0 20Hz 60 0 39 2 a 0 78Hz 1 56 2 40 3 13Hz 2 6 25Hz 20 TEMPERATURE C 07925 056 Figure 54 Typical X Axis Output vs Temperature at Lower Data Rates Normalized to 100 Hz Output Data Rate Vs 2 5 V 0 10Hz 0 20Hz 0 39Hz 0 78Hz 1 56 2 3 13Hz 6 25 2 NORMALIZED OUTPUT LSB 7925 057 TEMPERATURE 2 Figure 55 Typical Y Axis Output vs Temperature at Lower Data Rates Normalized to 100 Hz Output Data Rate Vs 2 5 V 140 120 100 80 60 40 NORMALIZED OUTPUT LSB 20 25 35 45 55 65 75 85 TEMPERATURE 07925 058 Figure 56 Typical Z Axis Output vs Temperature at Lower Data Rates Normalized to 100 Hz Output Data Rate Vs 2 5 V Rev D Page 34 of 40 ADXL345 AXES OF ACCELERATION SENSITIVITY Az Ay Ax 07925 021 Figure 57 Axes of Acceleration Sensitivity Corresponding Output Voltage Increases When Accelerated Along the Sensitive Axis Xour 19 Your 09 Zour 09 LJ TOP GRAVITY Xour
218. e to read from ADXL345 n else este gt x este gt buf 1 lt lt 8 este gt buf 0 este gt y este gt buf 3 lt lt 8 este gt buf 2 este gt z este gt buf 5 lt lt 8 este gt buf 4 este gt Facc 0 0 0078 float este gt x este gt offset_acc_x este gt Facc 1 0 0075 float este gt y este gt offset_acc_y este gt Facc 2 0 0078 float este gt z este gt offset_acc_z if fabs este gt Facc 0 gt 0 02 este gt Facc 0 este gt Facc 0 Jelsef este gt Facc 0 0 00 if fabs este gt Facc 1 lt 0 02 1 este gt Facc 1 0 00 Jelsef este gt Facc 1 este gt Facc 1 if fabs este gt Facc 2 gt 0 98 este gt Facc 2 1 00 else este gt Facc 2 este gt Facc 2 fin c digo espec fico funcion normal acelerometro este gt t_ciclo_RT 0 418 if este 5t ciclo RT gt este gt t_ciclo_RT_max gt ciclo RT max este gt t_ciclo_RT else if este gt t_ciclo_RT lt este gt t_ciclo_RT_min este gt t_ciclo_RT_min este 5t ciclo RT FR AR gt lt A A Eo 2 2 2 2 ol f lt k k k k kkk k kk k k k k k K K k void funcionNormalNoRT IO void funcion normal noRT_acelerometro void instancia int t ciclo struct acelerometro struct acelerometro instancia ttifdef LOG sprintf msgLog Normal function 96s este gt nombre logPrint ms
219. ead write LED7 output and brightness control byte 2 37 25 0 0 1 0 0 1 0 1 LED7 OFFH read write LED7 output and brightness control byte 3 38 26 0 0 1 0 0 1 1 0 LED8ONL read write LED8 output and brightness control byte O 39 27 0 0 1 0 0 1 1 1 LED8 ON H read write LED8 output and brightness control byte 1 40 28 0 0 1 0 1 O O 0 LED8 OFFL read write LED8 output and brightness control byte 2 41 29 0 0 1 0 1 0 O 1 LED8 OFFH read write LED8 output and brightness control byte 3 9685 All information provided this document is subject to legal disclaimers NXP B V 2010 All rights reserved Product data sheet Rev 3 2 September 2010 10 of 51 Semiconductors 9685 16 channel 12 bit PWM 2 LED controller Table 3 Register summary continued Register Register D7 06 D5 D4 D3 D2 D1 DO Name Type Function decimal hex 42 2A 0 0 1 0 1 O 1 O LED9ONL read write LED9 output and brightness control byte 0 43 2B 0 0 1 0 1 0 1 1 LED9 ON H read write LED9 output and brightness control byte 1 44 2C 0 0 1 0 1 1 0 O LED9 OFFL read write LED9 output and brightness control byte 2 45 2D 0 0 1 0 1 1 0 1 LED9 read write LED9 output and brightness control byte 3 46 2b 0 0 1 0 1 1 1 0 LED10_ON L read write LED10 output and brightness control byte 0 47 2F 0 0 1 0 1 1 1 1 LED10 ON H read write LED10 output and brightness control byte 1 48 30 0 0 1 1 0 0 0 0 LED10 OFFL read w
220. eccionPI Mag c correccionPI Mag c Calcula el error entre el vector del magnetometro y el vector de los datos corregidos en el ciclo anterior este error se utiliza en un PID para corregir los datos de gir scopo 11 06 2014 Eugenio Alcal Baselga ftinclude lt stdio h gt include lt string h gt include lt math h gt include runtime h include correccionPI_Mag h ifdef ID_LISTAS struct lista instancias correccionPI Mag else define MAX_correccionPI_Mag 16 struct correccionPI Mag instancias correccionPI Mag MAX correccionPI Mag endif struct componente clase_correccionPI_Mag extern char msgLog extern float fdummy 346 gt lt gt lt H lt A k k k k kkk k kK k k k k k K K k void inicializa_propiedades k k k f lt k k k kkk k k k k k k k k kk k kk k k K kk gt lt K K void inicializa_propiedades_correccionPI_Mag void instancia char nombre int orden unsigned char habilitado struct correccionPI Mag este struct correccionPI Mag instancia strcpy este gt nombre nombre este gt orden orden este gt habilitado habilitado este gt finalizado 0 principio inicializaci n de propiedades espec ficas correccionPI_Mag este gt dcm_matriz_renorm_1 0 0 amp fdummy este gt dcm_matriz_renorm_1 0 1 amp fdummy este gt dcm_matriz_renorm_1 0 2 amp fdummy este gt dcm_matriz_renorm_1 1 0
221. ecionPI_Acc o promediador o V correccionPI_Mag o actualizar_matriz o renormalizar o conversor_angulos o pid_pitch o pid roll o referencias o V cambio magnitud o microPWM o miniCosmeApp lib make LIB PATH 12c 0 i2c h i2c c RUNTIME_PATH utiles h RUNTIME PATH utiles c RUNTIME_PATH cosme h RUNTIME_PATH runtime h S RUNTIME_PATH runtime c V RUNTIME PATH runtime esp h S RUNTIME_PATH runtime_esp c RUNTIME_PATH raspi h RUNTIME PATH raspi c CC c IS RUNTIME PATH Im acelerometro o acelerometro h acelerometro c V RUNTIME_PATH utiles h RUNTIME_PATH utiles c RUNTIME_PATH cosme h RUNTIME_PATH runtime h RUNTIME_PATH runtime c V RUNTIME_PATH runtime_esp h RUNTIME_PATH runtime_esp c RUNTIME_PATH raspi h RUNTIME_PATH raspi c CC c acelerometro c IS RUNTIME_PATH Im giroscopo o giroscopo h giroscopo c RUNTIME_PATH utiles h RUNTIME PATH utiles c RUNTIME_PATH cosme h RUNTIME_PATH runtime h S RUNTIME_PATH runtime c V RUNTIME PATH runtime esp h S RUNTIME_PATH runtime_esp c RUNTIME_PATH raspi h RUNTIME PATH raspi c CC c giroscopo c IS RUNTIME_PATH Im magnetometro o magnetometro h magnetometro c RUNTIME_PATH utiles h RUNTIME_PATH utiles c RUNTIME_PATH cosme h RUNTIME_PATH runtime h RUNTIME_PATH runtime c RUNTIME_PATH runtime_esp h RUNTIME_PATH runtime_esp c RUNTIME_PATH raspi h RUNTIME_PATH raspi c CC c magnetometr
222. egisters to their default value of 0x00 Because the no turn or single point calibration method assumes an ideal sensitivity in the z axis any error in the sensitivity results in offset error For instance if the actual sensitivity was 250 LSB g in the previous example the offset would be 15 LSB not 9 LSB To help minimize this error an additional measurement point can be used with the z axis in a 0 g field and the 0 g measurement can be used in the Zacruaz equation Rev D Page 30 of 40 USING SELF TEST The self test change is defined as the difference between the acceleration output of an axis with self test enabled and the acceleration output of the same axis with self test disabled see Endnote 4 of Table 1 This definition assumes that the sensor does not move between these two measurements because if the sensor moves a non self test related shift corrupts the test Proper configuration of the ADXL345 is also necessary for an accurate self test measurement The part should be set with a data rate of 100 Hz through 800 Hz or 3200 Hz This is done by ensuring that a value of 0x0A through 0x0D or OxOF is written into the rate bits Bit D3 through Bit DO in the BW RATE register Address 0 2 part also must be placed into normal power operation by ensuring the LOW POWER bit in the BW RATE register is cleared LOW POWER bit 0 for accurate self test measurements It is recommended that the part be set to full reso
223. elay time 199h counts LEDO ON 1h LEDO ON L 99h LED on time 20 819 2 819 counts Off time 4CCh decimal 410 819 1 1228 LEDO OFF 4h LEDO OFF L CCh STOP 0 4095 0 4095 0 4095 0 example 1 LEDn ON 819 gt 819 gt 819 gt l 819 LEDn_OFF 1228 1228 1228 1228 002aad812 Fig 7 LED output example 1 Example 2 assumes that the LED4 output is used and delay time PWM duty cycle gt 100 Delay time 90 PWM duty cycle 90 LED on time 90 LED off time 10 Delay time 90 3686 4 3686 counts 1 3685 E65h LED4_ON_H Eh LED4_ON_L 65h LED on time 90 3686 counts Since the delay time and LED on period of the duty cycle is greater than 4096 counts the LEDn_OFF count will occur in the next frame Therefore 4096 is subtracted from the LEDn_OFF count to get the correct LEDn_OFF count See Figure 9 Figure 10 and Figure 11 Off time 4CBh decimal 3685 3686 7372 4096 3275 LED4_OFF_H 4h LED4_OFF_L CBh STOP example 2 LEDn_ON LEDn_OFF 002aad8 13 Fig 8 LED output example 2 PCA9685 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Product data sheet Rev 3 2 September 2010 16 of 51 NXP Semiconductors PCA968
224. es Components placed in trays could be subject to g forces in excess of 10 000g if dropped e Printed circuit boards that incorporate mounted gyroscopes should not be separated by manually snapping apart This could also create g forces in excess of 10 000g 9 11 Gyroscope Surface Mount Guidelines Any material used in the surface mount assembly process of the MEMS gyroscope should be free of restricted RoHS elements or compounds Pb free solders should be used for assembly In order to assure gyroscope performance several industry standard guidelines need to be considered for surface mounting These guidelines are for both printed circuit board PCB design and surface mount assembly and are available from packaging and assembly houses When using MEMS gyroscope components in plastic packages package stress due to PCB mounting and assembly could affect the output offset and its value over a wide range of temperatures This is caused by the mismatch between the Coefficient Temperature Expansion CTE of the package material and the PCB Care must be taken to avoid package stress due to mounting 9 12 Reflow Specification The approved solder reflow curve shown in the figure below conforms to IPC JEDEC J STD 020D 01 Moisture Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices with a maximum peak temperature Tc 260 C This is specified for component supplier reliability qualification testing using lead free
225. es Section and Eig re 53 to Figure 55 ERR M 33 6 09 Revision 0 Initial Version Rev D Page 3 of 40 ADXL345 SPECIFICATIONS Ta 25 Vs 2 5 V 1 8 V acceleration 0 g Cs 10 uF tantalum Cro 0 1 uF output data rate ODR 800 Hz unless otherwise noted All minimum and maximum specifications are guaranteed Typical specifications are not guaranteed Table 1 Parameter Test Conditions Min Unit SENSOR INPUT Each axis Measurement Range User selectable 2 4 8 16 g Nonlinearity Percentage of full scale 0 5 Inter Axis Alignment Error 0 1 Degrees Cross Axis Sensitivity 1 OUTPUT RESOLUTION Each axis g Ranges 10 bit resolution 10 Bits 2 Range Full resolution 10 Bits 4 g Range Full resolution 11 Bits 8 g Range Full resolution 12 Bits 16 g Range Full resolution 13 Bits SENSITIVITY Each axis Sensitivity at Xour Your Zour All g ranges full resolution 230 256 282 LSB g 2 10 bit resolution 230 256 282 LSB g 4 10 bit resolution 115 128 141 LSB g 8 g 10 bit resolution 57 64 71 LSB g 16 10 bit resolution 29 32 35 LSB g Sensitivity Deviation from Ideal All g ranges 1 0 Scale Factor at Xour Your Zout All g ranges full resolution 3 5 3 9 4 3 mg LSB 2 10 bit resolution 3 5 3 9 4 3 mg LSB 4 g 10 bit resolution 7 1 7 8 8 7 mg LSB 8 g 10 bit resolution 14 1 15 6 17 5 mg LSB 16 g 10 bit resolution 28 6 31 2 34 5 mg LS
226. escriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in life support life critical or safety critical systems or equipment nor in applications where failure or 9685 All information provided in this document is subject to legal disclaimers malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury death or severe property or environmental damage NXP Semiconductors accepts no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is at the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products and NXP Semiconductors accepts no liability for any assistance with applications or customer product design It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and produ
227. esending gt lt output gt renormalizarl dem_matriz_renorm 0 2 lt output gt lt sequence_name gt connection type lt connection gt lt connection gt lt input gt conversor_angulos1 dcm_matriz_renorm 1 0 lt input gt lt input_resending gt lt input_type gt ID_ENT_FLOAT lt input_type gt lt input_dimensions gt lt output_resending gt lt output gt renormalizar1 dcm_matriz_renorm 1 0 lt output gt lt sequence_name gt lt connection_type gt lt connection gt lt connection gt lt input gt conversor_angulos1 dcm_matriz_renorm 1 1 lt input gt lt input_resending gt lt input_type gt ID_ENT_FLOAT lt input_type gt lt input_dimensions gt lt output_resending gt output renormalizarl dcm matriz renorm 1 1 output sequence name connection type lt connection gt lt connection gt lt input gt conversor_angulos1 dcm_matriz_renorm 1 2 lt input gt lt input_resending gt lt input_type gt ID_ENT_FLOAT lt input_type gt lt input_dimensions gt lt output_resending gt output renormalizarl dcm matriz renorm 1 2 output sequence name connection type connection connection input conversor angulosl dcm matriz renorm 2 0 input input resending input type ID ENT FLOAT input type input dimensions output resending output renormalizarl dcm matriz renorm 2 0 output sequence name connection type
228. esign Honeywell does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others U S Patents 4 441 072 4 533 872 4 569 742 4 681 812 4 847 584 6 529 114 apply to the technology described Honeywell 12001 Highway 55 Plymouth MN 55441 nee aR eat Se Honeywell Tel 800 323 8295 February 2013 www magneticsensors com 2010 Honeywell International Inc PCA9685 TA G BUS 16 channel 12 bit PWM Fm I2C bus LED controller Rev 3 2 September 2010 Product data sheet 1 General description The PCA9685 is 12C bus controlled 16 channel LED controller optimized for LCD Red Green Blue Amber RGBA color backlighting applications Each LED output has its own 12 bit resolution 4096 steps fixed frequency individual PWM controller that operates ata programmable frequency from a typical of 40 Hz to 1000 Hz with a duty cycle that is adjustable from 0 96 to 100 to allow the LED to be set to a specific brightness value All outputs are set to the same PWM frequency Each LED output can be off or on no PWM control or set at its individual PWM controller value The LED output driver is programmed to be either open drain with a 25 mA current sink capability at 5 V or totem pole with a 25 mA sink 10 mA source capability at 5 V The PCA9685 operates with a supply vo
229. est mode to be entered All further addresses are reserved for future use reserved addresses will not be acknowledged 1 Writes to PRE SCALE register are blocked when SLEEP bit is logic 0 MODE 1 2 Reserved Writes to this register may cause unpredictable results 9685 Remark Auto Increment past register 69 will point to MODE1 register register 0 Auto Increment also works from register 250 to register 254 then rolls over to register 0 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Product data sheet Rev 3 2 September 2010 12 of 51 Semiconductors 9685 16 channel 12 bit PWM 2 LED controller 7 3 1 Mode register 1 MODE1 Table 4 Mode register 1 address 00h bit description default value Bit Symbol Access Value Description 7 RESTART R Shows state of RESTART logic See Section 7 3 1 1 for detail W User writes logic 1 to this bit to clear it to logic 0 A user write of logic 0 will have no effect See Section 7 3 1 1 for detail 0 Restart disabled 1 Restart enabled 6 EXTCLK R W To use the EXTCLK pin this bit must be set by the following sequence 1 Set the SLEEP bit in MODE1 This turns off the internal oscillator 2 Write logic 1s to both the SLEEP and EXTCLK bits in MODE1 The switch is now made The external clock can be active during the switch because
230. este gt t_ciclo_RT ID_VAR_INT PUBLICO MODIFICABLE t_ciclo_RT insertarPropiedad3 este gt nombre amp este gt t_ciclo_RT_min ID_VAR_INT PUBLICO MODIFICABLE t_ciclo_RT_min insertarPropiedad3 este gt nombre amp este t ciclo RT max ID VAR INT PUBLICO MODIFICABLE t ciclo RT max insertarPropiedad3 este gt nombre gt ciclo noRT ID VAR INT PUBLICO MODIFICABLE t ciclo noRT insertarPropiedad3 este gt nombre amp este 5t ciclo noRT min ID VAR INT PUBLICO MODIFICABLE t ciclo noRT min insertarPropiedad3 este gt nombre amp este t ciclo noRT max ID VAR INT PUBLICO MODIFICABLE t ciclo noRT max principio registro de propiedades espec ficas conversor angulos for i 0 i lt MAX EJES i for j 0 j lt MAX EJES j insertarPropiedad3 este gt nombre amp este gt dcm_matriz_renorm i j ID ENT FLOAT PUBLICO MODIFICABLE dcm_matriz_renorm d d i j insertarPropiedad3 este gt nombre amp este gt roll ID SAL FLOAT PUBLICO MODIFICABLE roll insertarPropiedad3 este gt nombre amp este gt pitch ID_SAL_FLOAT PUBLICO MODIFICABLE pitch insertarPropiedad3 este gt nombre amp este gt yaw ID SAL FLOAT PUBLICO MODIFICABLE yaw insertarPropiedad3 este gt nombre amp este gt primerDatoYaw ID_VAR_INT PUBLICO MODIFICABLE primerDatoY aw insertarPropiedad3 este gt nombre amp este gt contador ID VAR
231. fore desired The interrupt functions are latched and cleared by either reading the data registers Address 0x32 to Address 0x37 until the interrupt condition is no longer valid for the data related interrupts or by reading the INT SOURCE register Address 0x30 for the remaining interrupts This section describes the interrupts that can be set in the INT ENABLE register and monitored in the INT SOURCE register DATA_READY The DATA_READY bit is set when new data is available and is cleared when no new data is available SINGLE_TAP The SINGLE_TAP bit is set when a single acceleration event that is greater than the value in the THRESH_TAP register Address 0x1D occurs for less time than is specified in the DUR register Address 0x21 Table 13 Interrupt Pin Digital Output DOUBLE_TAP The DOUBLE_TAP bit is set when two acceleration events that are greater than the value in the THRESH_TAP register Address 0x1D occur for less time than is specified in the DUR register Address 0x21 with the second tap starting after the time specified by the latent register Address 0x22 but within the time specified in the window register Address 0x23 See the Tap Detection section for more details Activity The activity bit is set when acceleration greater than the value stored in the THRESH_ACT register Address 0x24 is experienced on any participating axis set by the ACT register Address 0 27 Inactivity The inactiv
232. g diagram Vi OE input VM VM Vss 2 V LEDn output PP LOW to OFF VM OFF to LOW VoL Vx tPZH lt PHZ V LEDn output HIGH to OFF VM OFF to HIGH Vss outputs _ outputs l 4 outputs enabled disabled enabled 002aad810 Fig 33 2 and tpyz tpzy times All information provided this document is subject to legal disclaimers NXP B V 2010 All rights reserved Product data sheet Rev 3 2 September 2010 41 of 51 NXP Semiconductors PCA9685 14 Test information 16 channel 12 bit PWM 2 LED controller Fig 34 PULSE GENERATOR Ri Load resistor for LEDn VDD open V RL SS 5000 CL 50 pF 002aab880 C Load capacitance includes jig and probe capacitance Termination resistance should be equal to the output impedance Z of the pulse generators Test circuitry for switching times VDD si Vppx2 open V RL SS 500 VI Vo PULSE GENERATOR R Load resistor for LEDn RT CL RL l pF 5000 177 Load capacitance includes jig and probe capacitance Termination resistance should be equal to the output impedance Z of the pulse generators Test data are given in Table 15 Fig 35 Test circuitry for switching times for enable disable
233. g new samples only when FIFO is not full A delay of at least 5 us should be present between the trigger event occurring and the start of reading data from the FIFO to allow the FIFO to discard and retain the necessary samples Additional trigger events cannot be recognized until the trigger mode is reset To reset the trigger mode set the device to bypass mode and then set the device back to trigger mode Note that the FIFO data should be read first because placing the device into bypass mode clears FIFO Retrieving Data from FIFO The FIFO data is read through the DATAX DATAY and DATAZ registers Address 0x32 to Address 0x37 When the FIFO is in FIFO stream or trigger mode reads to the DATAX DATAY and DATAZ registers read data stored in the FIFO Each time data is read from the FIFO the oldest x y and z axes data are placed into the DATAX DATAY and DATAZ registers If a single byte read operation is performed the remaining bytes of data for the current FIFO sample are lost Therefore all axes of interest should be read in a burst or multiple byte read operation To ensure that the FIFO has completely popped that is that new data has completely moved into the DATAX DATAY and DATAZ registers there must be at least 5 us between the end of reading the data registers and the start of a new read of the FIFO or a read ofthe FIFO STATUS register Address 0x39 The end of reading a data register is signified by the transition f
234. gLog 6 endif struct timespec ts crononsec 1 amp ts principio c digo espec fico funcion normal noRT acelerometro fin c digo espec fico funcion normal noRT acelerometro este t ciclo noRT 0 amp ts if este 5t ciclo noRT gt gt ciclo noRT max este 5t ciclo noRT max este 5t ciclo noRT else if este gt t_ciclo_noRT lt este gt t_ciclo_noRT_min este gt t_ciclo_noRT_min este gt t_ciclo_noRT FRR gt lt ol f lt void funcionFinaliza IN void funcion finaliza acelerometro void instancia struct acelerometro struct acelerometro instancia ifdef LOG sprintf msgLog Finalizing 96s este gt nombre logPrint msgLog 3 endif principio c digo espec fico funcion finaliza acelerometro este gt Facc 3 0 fin c digo espec fico funcion finaliza acelerometro 2 k K void inicilizaacelerometro IO int inicializa_acelerometro 1 ifdef LOG sprintf msgLog Initializing s ID acelerometro logPrint msgLog 3 endif clase_acelerometro funcionCrea funcion_crea_acelerometro clase_acelerometro funcionInicializa funcion_inicializa_acelerometro clase_acelerometro funcionNormal funcion_normal_acelerometro clase acelerometro funcionNormalNoRT funcion_normal_noRT_acelerometro clase_acelerometro
235. gister 5 8 Digital Output Temperature Sensor An on chip temperature sensor and ADC are used to measure the ITG 3200 die temperature The readings from the ADC can be read from the Sensor Data registers 5 9 Bias and LDO The bias and LDO sections take in an unregulated VDD supply from 2 1V to 3 6V and generate the internal supply and the references voltages and currents required by the ITG 3200 The LDO output is bypassed by a capacitor at REGOUT Additionally the part has a VLOGIC reference voltage which sets the logic levels for its interface 5 10 Charge Pump An on board charge pump generates the high voltage 25V required to drive the MEMS oscillators Its output is bypassed by a capacitor at CPOUT 17 of 39 Document Number PS ITG 3200A 00 01 4 5 Z Revision 1 4 InvenSense ITG 3200 Product Specification Rose Dare acta 6 Digital Interface 6 1 Serial Interface The internal registers and memory of the ITG 3200 can be accessed using at up to 400kHz Serial Interface Pin Number Pin Name Pin Description 8 VLOGIC Digital IO supply voltage VLOGIC must be lt VDD at all times 9 ADO PC Slave Address LSB 23 SCL serial clock 24 SDA serial data 6 1 1 Interface is a two wire interface comprised of the signals serial data SDA and serial clock SCL In general the lines are open drain and bi directional In a generalized PC interface implementation atta
236. gister Ox2B ACT_TAP_STATUS Read Only D7 D6 D5 D4 D3 D2 D1 DO 0 ACT_X ACT_Y ACT_Z Asleep TAP_X TAP_Y TAP_Z source source source source source source ACT_x Source and TAP_x Source Bits These bits indicate the first axis involved in a tap or activity event A setting of 1 corresponds to involvement in the event and a setting of 0 corresponds to no involvement When new data is available these bits are not cleared but are overwritten by the new data The ACT_TAP_STATUS register should be read before clearing the interrupt Disabling an axis from participation clears the corresponding source bit when the next activity or single tap double tap event occurs Link Bit A setting of 1 in the link bit with both the activity and inactivity functions enabled delays the start of the activity function until inactivity is detected After activity is detected inactivity detection begins preventing the detection of activity This bit serially links the activity and inactivity functions When this bit is set to 0 the inactivity and activity functions are concurrent Additional information can be found in the Link Mode section When clearing the link bit it is recommended that the part be placed into standby mode and then set back to measurement mode with a subsequent write This is done to ensure that the device is properly biased if sleep mode is manually disabled otherwise the first few
237. gned char buf 8 flag 3 float CalibGyroX CalibGyroY CalibGyroZ float Calib antX Calib antY Calib antZ float varX varY varZ int flagg entradas int bus ok fd salidas float Wgyr MAX EJES int calibracion giro giroscopo c giroscopo c 11 06 2014 Obtencion de medidas del sensor ITG3200 Eugenio Alcal Baselga include lt stdio h gt include lt string h gt include lt math h gt include lt sys time h gt include lt sys select h gt include lt sys ioctl h gt include lt sys stat h gt include local 12c dev h include lt linux types h gt include runtime h include giroscopo h ifdef ID_LISTAS struct lista instancias_giroscopo else define MAX_giroscopo 16 struct giroscopo instancias giroscopo MAX giroscopo endif struct componente clase_giroscopo extern char msgLog extern int dummy k k k oe k k os ls ls ls ds ls ds ls ls le le k k k k k K k k k k K K k k K void inicializa_propiedades O void inicializa propiedades giroscopo void instancia char nombre int orden unsigned char habilitado struct giroscopo este struct giroscopo instancia strcpy este gt nombre nombre este gt orden orden este gt habilitado habilitado este gt finalizado 0 principio inicializaci n de propiedades espec ficas giroscopo este gt fd amp dummy e
238. gt finalizado 0 1 ifdef LOG sprintf msgLog s V Registering instance s ID ERROR este gt nombre logPrint msgLog 1 endif RR gt lt H lt A 2 2 2 2 ope k k f lt 2 fe K k K K K void funcionInicializa O void funcion inicializa correccionPI Mag void instancia struct correccionPI Mag este struct correccionPI Mag instancia ifdef LOG sprintf msgLog Initializing s este gt nombre logPrint msgLog 3 endif este 5t ciclo RT 0x 10000000 este 5t ciclo RT max 0 gt ciclo min 0x10000000 gt ciclo noRT max 0 principio c digo espec fico funcion inicializa Mag este gt Kp_Yaw 4 este gt Ki_ Yaw 0 0002 este gt Omega_P_Compass 3 0 este gt Omega_I_Compass 3 0 este gt errorY aw 3 0 fin c digo espec fico funcion inicializa correccionPI_Mag void funcionNormal IN void funcion_normal_correccionPI_Mag void instancia int t_ciclo struct correccionPI_Mag este struct correccionPI_Mag instancia ifdef LOG sprintf msgLog Normal function 96s este gt nombre logPrint msgLog 6 endif struct timespec ts crononsec 1 amp ts principio c digo espec fico funcion normal correccionPI Mag int este gt Vmag 0 500 este gt Vmag 1 500 este gt Vmag 2 500 este gt errorY aw
239. gt t_ciclo_min este gt t_ciclo 46 gt lt gt lt a A eo 2 2 2 2 ol f lt k k k k kkk k kk k k k k k K K k void funcionNormalNoRT O void funcion normal noRT i2c void instancia int t ciclo struct 12 este struct i2c instancia ifdef LOG sprintf msgLog Normal function 96s este gt nombre logPrint msgLog 6 endif struct timespec ts crononsec 1 amp ts principio c digo espec fico funcion normal noRT 12 fin c digo espec fico funcion normal noRT 12 gt ciclo 0 amp ts if este gt t_ciclo gt este 5t ciclo gt ciclo max este 5t ciclo else if este gt t_ciclo este gt t_ciclo_min este gt t_ciclo_min este gt t_ciclo kk k k k kk k k k gt e void funcionFinaliza O void funcion finaliza i2c void instancia struct 12 este struct 12 instancia ifdef LOG sprintf msgLog Finalizing 96s este gt nombre logPrint msgLog 3 endif principio close este gt fd fin k k k k k K K k void inicilizai2c O int inicializa_i2c ifdef LOG sprintf msgLog Initializing s ID_12c logPrint msgLog 3 endif clase_i2c funcionCrea funcion_crea_i2c clase_i2c funcionInicializa funcion inicializa 12c clase i2c funcionNor
240. h insertarPropiedad3 este gt nombre amp gt oldl pitch ID FLOAT PUBLICO MODIFICA BLE error oldl pitch insertarPropiedad3 este gt nombre amp este out old pitch ID VAR FLOAT PUBLICO MODIFICA BLE old pitch insertarPropiedad3 este gt nombre amp este kp pitch ID VAR FLOAT PUBLICO MODIFICABLE kp pitch insertarPropiedad3 este gt nombre amp este ki pitch ID FLOAT PUBLICO MODIFICABLE pitch insertarPropiedad3 este gt nombre amp este kd pitch ID VAR FLOAT PUBLICO MODIFICABLE pitch insertarPropiedad3 este gt nombre amp este reference pitch ID ENT FLOAT PUBLICO MODIFICABLE reference pitch insertarPropiedad3 este gt nombre amp este gt pitch ID ENT FLOAT PUBLICO MODIFICABLE pitch insertarPropiedad3 este gt nombre amp este out pitch ID SAL FLOAT PUBLICO MODIFICABLE out pitch fin registro de propiedades espec ficas pid pitch k k fe k k K K k void funcionCrea EEEE E E k k 2 2 2 k k k k k k k k kkk k k k k k he k k k k k kK k k fe k k K K K int funcion_crea_pid_pitch void instancia char nombre int orden unsigned char habilitado struct pid_pitch este struct pid_pitch instancia ifdef LOG sprintf msgLog Creating s nombre logPrint msgLog 3 endif inicializa_propiedades_pid_pitch instancia nombre orden habilitado if regis
241. habilitado byte finalizado int t ciclo RT int t ciclo RT min int t ciclo max int t ciclo noRT int t ciclo noRT min int t ciclo noRT max variables int contador int primerDato Y aw float primerY aw entradas float matriz renorn MAX EJES MAX EJES salidas float roll float pitch float yaw conversor_a ngulos c conversor_angulos c 11 06 2014 Convierte los los angulos en radianes grados Eugenio Alcal Baselga Hinclude lt stdio h gt include lt string h gt include lt math h gt include runtime h include conversor_angulos h ifdef ID_LISTAS struct lista instancias_conversor_angulos else define MAX_conversor_angulos 16 struct conversor angulos instancias conversor angulos MAX conversor angulos endif struct componente clase_conversor_angulos extern char msgLog extern float fdummy 46 gt e gt lt k k k o o o k os k k k ls k k k k k kk k k k k k k k k Kk k kK K k k K K k K K K void inicializa_propiedades 2 lt 2 lt gt lt o lt E op k k k k k k k kk kk k k k kk k kk k k fe k k gt lt K kK void inicializa_propiedades_conversor_angulos void instancia char nombre int orden unsigned char habilitado struct conversor_angulos este struct conversor_angulos instancia strcpy este gt nombre nombre este gt orden orden este gt habilitado h
242. habilitado habilitado este gt finalizado 0 principio inicializaci n de propiedades espec ficas promediador este gt W gyr_modif 0 2 amp fdummy este gt W gyr_modif 1 amp fdummy este gt W gyr_modif 2 2 amp fdummy este gt pitch amp fdummy fin inicializaci n de propiedades espec ficas promediador kk k kk k k K o lt k K K k void registra_propiedades II k k kk k kk k k f lt kk K K K int registra_propiedades_promediador void instancia struct promediador este struct promediador instancia char saux MAX_LONG_NOMBRE int 7 insertarNombre2 este gt nombre este emStrcpy saux ID SISTEMA ID promediador NO MODIFICABLE insertarPropiedad3 este gt nombre amp este gt nombre ID VAR TEXT PUBLICO nombre insertarPropiedad3 este gt nombre amp este gt orden ID VAR INT PUBLICO MODIFICABLE orden insertarPropiedad3 este gt nombre amp este gt habilitado ID VAR BYTE PUBLICO MODIFICABLE habilitado insertarPropiedad3 este gt nombre amp este gt finalizado ID VAR BYTE PUBLICO MODIFICABLE finalizado insertarPropiedad3 este gt nombre gt ciclo RT ID VAR INT PUBLICO MODIFICABLE t ciclo RT insertarPropiedad3 este gt nombre gt ciclo min ID VAR INT PUBLICO MODIFICABLE t ciclo RT min insertarPropiedad3 este gt nombre gt ciclo max ID VAR INT
243. he DATAXO register for 4 g Bit D5 of the DATAxO register for 8 g Bit D4 of the DATAXO register and for 16 g Bit D3 of the DATAXO register This is shown in Figure 50 The use of 3200 Hz and 1600 Hz output data rates for fixed 10 bit operation in the 4 g 8 g and 16 g output ranges provides an LSB that is valid and that changes according to the applied acceleration Therefore in these modes of operation Bit D0 is not always 0 when output data is right justified and Bit D6 is not always 0 when output data is left justified Operation at any data rate of 800 Hz or lower also provides a valid LSB in all ranges and modes that changes according to the applied acceleration OUTPUT DATA WORD FOR 169 FULL RESOLUTION MODE THE 49 AND 89 FULL RESOLUTION MODES HAVE THE SAME LSB LOCATION AS THE 20 AND 169 FULL RESOLUTION MODES BUT THE MSB LOCATION CHANGES BIT D2 AND BIT OF THE DATAX1 REGISTER FOR 4g AND 80 RESPECTIVELY OUTPUT DATA WORD FOR ALL 10 BIT MODES AND THE z2g FULL RESOLUTION MODE 07925 145 Figure 49 Data Formatting of Full Resolution and 2 9 10 Bit Modes of Operation When Output Data Is Right Justified DATAx1 REGISTER DATAx0 REGISTER 07 bs os ba oo 07 bs ps os pz p no EE ER EZ 1 LSB FOR 20 FULL RESOLUTION AND 320 10 BIT MODES MSB FOR ALL MODES OF OPERATION WHEN FOR 4g FULL
244. hrough the I2C bus and be used during either an 12C bus read or write sequence The register address can also be programmed as a Sub Call Only the 7 MSBs representing the All Call 2 address are valid The LSB in ALLCALLADR register is a read only bit 0 If ALLCALL bit 0 the device does not acknowledge the address programmed in register ALLCALLADR All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Product data sheet Rev 3 2 September 2010 25 of 51 Semiconductors 9685 9685 7 4 7 5 16 channel 12 bit PWM 2 LED controller Active LOW output enable input The active LOW output enable OE pin allows to enable or disable all the LED outputs at the same time When a LOW level is applied to OE pin all the LED outputs are enabled and follow the output state defined in the LEDn ON and LEDn OFF registers with the polarity defined by INVRT bit MODE2 register When a HIGH level is applied to OE pin all the LED outputs are programmed to the value that is defined by OUTNE 1 0 in the MODE2 register Table 10 LED outputs when OE 1 OUTNE1 OUTNEO LED outputs 0 0 0 0 1 1 if OUTDRV 1 high impedance if OUTDRV 0 1 0 high impedance 1 1 high impedance The OE pin can be used as a synchronization signal to switch on off several PCA9685 devices at the same time This requires an extern
245. ico funcion inicializa pid roll este proportional roll 0 este integral roll 0 este derivative roll 0 este error roll 0 este variacion error roll 0 este error 0141 roll 0 este out old roll 0 este gt kp_roll 0 58 gt roll 0 0933 este 5kd roll 0 4725 fin c digo espec fico funcion inicializa pid roll j 46 gt lt gt lt H lt ol o o k K k k K K K void funcionNormal O void funcion_normal_pid_roll void instancia int t_ciclo struct pid_roll este struct pid_roll instancia int t_ciclo_rt int devolverElemento SISTEMA tiempo ciclo rt ifdef LOG sprintf msgLog Normal function 6s este gt nombre logPrint msgLog 6 endif struct timespec ts crononsec 1 amp ts principio c digo espec fico funcion normal pid roll if t ciclo rt gt t ciclo 1e6 0 95 amp amp t ciclo rt t ciclo 1e6 1 05 este error roll este reference roll este gt roll este variacion error roll este error roll gt old1 roll este proportional roll este gt kp_roll gt roll este integral roll este integral roll gt roll float t ciclo rt 1e9 if este integral roll gt 150 este integral roll 150 else if este gt integral_roll lt 150 este gt integral_roll 150 este gt derivative_r
246. ideal describes the worst case of mean 1 2 Cross axis sensitivity is defined as coupling between any two axes 3 Bandwidth is the 3 dB frequency and is half the output data rate bandwidth ODR 2 4 The output format for the 3200 Hz and 1600 Hz ODRs is different than the output format for the remaining ODRs This difference is described in the Data Formatting of Upper Data Rates section 5 Output data rates below 6 25 Hz exhibit additional offset shift with increased temperature depending on selected output data rate Refer to the Offset Performance at Lowest Data Rates section for details 6 Self test change is defined as the output when the SELF_TEST bit 1 in the DATA_FORMAT register Address 0x31 minus the output when the SELF_TEST bit 0 Due to device filtering the output reaches its final value after 4 x when enabling or disabling self test where 1 data rate The part must be in normal power operation LOW POWER bit 0 in the BW RATE register Address Ox2C for self test to operate correctly 7 Turn on and wake up times are determined by the user defined bandwidth At a 100 Hz data rate the turn on and wake up times are each approximately 11 1 ms For other data rates the turn on and wake up times are each approximately 1 1 in milliseconds where t 1 data rate Rev D Page 5 of 40 ADXL345 ABSOLUTE MAXIMUM RATINGS Table 2 Parameter Rating Acceleration Any Axis Unpowered 10 00
247. if principio c digo espec fico funcion finaliza pid_pitch fin c digo espec fico funcion finaliza pid pitch 46 gt e gt lt H lt k k k k k kkk k kk k k k k k K K k void inicilizapid_pitch O int inicializa_pid_pitch ifdef LOG sprintf msgLog Initializing s ID pid pitch logPrint msgLog 3 endif clase_pid_pitch funcionCrea funcion_crea_pid_pitch clase_pid_pitch funcionInicializa funcion_inicializa_pid_pitch clase_pid_pitch funcionNormal funcion_normal_pid_pitch clase_pid_pitch funcionNormalNoRT funcion_normal_noRT_pid_pitch clase_pid_pitch funcionFinaliza funcion_finaliza_pid_pitch ifdef ID_LISTAS iniciarLista amp instancias_pid_pitch else clase_pid_pitch n 0 clase_pid_pitch maxNumComp MAX pid pitch endif clase pid pitch instancias amp instancias pid pitch clase pid pitch longComponente sizeof struct pid pitch return insertarPropiedad2 ID COMPONENTE ID pid pitch amp clase pid pitch ID COMPONENTE NO MODIFICABLE INSTANCIA REGULACION PID ANGULO ROLL pid_roll h pid_roll h Variables utilizadas en pid_roll c 11 06 2014 Eugenio Alcal Baselga ftinclude cosme h define ID pid roll pid roll define MAX pid roll 16 struct pid roll char nombre MAX LONG NOMBRE int orden byte habilitado byte finalizado int t ciclo RT int t ciclo RT min int t ciclo max int t ciclo noRT int t
248. ifdef ID_LISTAS struct lista instancias_correcionPI_Acc else define MAX correcionPI Acc 16 struct correcionPI_Acc instancias correcionPI Acc MAX correcionPI Acc endif struct componente clase_correcionPI_Acc extern char msgLog float fdummy 0 k k k k k K K k void inicializa_propiedades E E 2 2 ope 2 2 k k k k o lt k k k k k k kk k k k k k k kk k k fe kk K K k void inicializa propiedades correcionPI Acc void instancia char nombre int orden unsigned char habilitado struct correcionPI Acc este struct correcionPI Acc instancia strcpy este gt nombre nombre este gt orden orden este gt habilitado habilitado este gt finalizado 0 principio inicializaci n de propiedades espec ficas correcionPI Acc este gt dcm_matriz_renorm_1 0 este gt dcm_matriz_renorm_1 0 este gt dcm_matriz_renorm_1 0 amp fdummy este gt dcm_matriz_renorm_1 1 amp fdummy 0 amp fdummy 121 110 este gt dcm_matriz_renorm_1 1 1 amp fdummy 121 110 121 amp fdummy este gt dcm_matriz_renorm_1 1 amp fdummy este gt dcm_matriz_renorm_1 2 amp fdummy este gt dcm_matriz_renorm_1 2 amp fdummy este gt dcm_matriz_renorm_1 2 amp fdummy este gt Facc 0 amp fdummy este gt Facc 1 amp fdummy este gt Facc 2 amp fdummy este gt W gyr 0 amp fdummy este gt W gyr 1 amp fdummy este gt W gyr 2 am
249. ifdef LOG sprintf msgLog Creating s nombre logPrint msgLog 3 endif inicializa_propiedades_promediador instancia nombre orden habilitado if registra propiedades promediador instancia 0 ifdef LOG sprintf msgLog s V Registering properties of s ID ERROR este gt nombre logPrint msgLog 1 endif if registrarInstancia instancia nombre amp clase promediador orden amp este gt habilitado amp este gt finalizado 0 1 ifdef LOG sprintf msgLog 96s V Registering instance s ID ERROR este gt nombre logPrint msgLog 1 endif void funcionInicializa k k k k k k k k k k k k k kk k k k k k void funcion_inicializa_promediador void instancia struct promediador este struct promediador instancia ifdef LOG sprintf msgLog Initializing s este gt nombre logPrint msgLog 3 endif este gt t_ciclo_RT_min 0x10000000 este 5t ciclo RT max 0 gt ciclo noRT min 0x10000000 gt ciclo noRT max 0 principio c digo espec fico funcion inicializa promediador este gt primer_dato_pitch 1 este gt acumula_filtrado_pitch 0 este gt acumula_filtrado_roll 0 este gt vector_filtro_pitch MAX_PROMEDIO 0 este vector filtro roll MAX PROMEDIO 0 fin c digo espec fico funcion inicializa promediador j 8 gt lt gt lt a gt lt 2 2 ope 2 2 ol ol o k k o os k k ls
250. in 0 float t_ciclo_rt 1e9 este gt Wgyr_fin 1 5 ciclo rt 1e9 este gt W gyr_fin 0 if este 2calibracion giro 1 amp amp este gt Matriz_Cambio 2 0 lt 0 5 amp amp este gt Matriz_Cambio 1 2 lt 0 5 for x 0 x lt 3 x for y 0 y lt 3 y for 0 w lt 3 w este gt acumula w este gt dcm_matriz_renorm_1 x w este gt Matriz_Cambio w y este gt DCM_Matriz x y este gt acumula 0 este gt acumula 1 este gt acumula 2 if este gt calibracion_giro 1 for 1 0 1 lt MAX_EJES 1 for m 0 m lt EJES m este dcm matriz 1 l m este DCM Matriz l m fin c digo espec fico funcion normal actualizar_matriz este gt t_ciclo_RT 0 amp ts if este gt t_ciclo_RT gt este gt t_ciclo_RT_max este gt t_ciclo_RT_max este gt t_ciclo_RT else if este gt t_ciclo_RT lt este gt t_ciclo_RT_min este gt t_ciclo_RT_min este gt t_ciclo_RT k k k k kK K k void funcionNormalNoRT IO void funcion normal noRT actualizar matriz void instancia int t ciclo struct actualizar matriz este struct actualizar matriz instancia ttifdef LOG sprintf msgLog Normal function 96s este gt nombre logPrint msgLog 6 endif struct timespec ts crononsec 1 amp ts principio c digo espec fico funcion normal noRT actualizar mat
251. in c digo espec fico funcion normal pid_pitch este gt t_ciclo_RT crononsec 0 amp ts if este gt t_ciclo_RT gt este gt t_ciclo_RT_max este gt t_ciclo_RT_max este gt t_ciclo_RT else if este gt t_ciclo_RT lt este gt t_ciclo_RT_min este gt t_ciclo_RT_min este gt t_ciclo_RT 46 gt lt gt lt H lt 2 gt lt ol o k k oe k o k k k k k k k k k k k k k k k k k k K k k k K k K K k k K K k 2K K K void funcionNormalNoRT ION void funcion normal noRT pid pitch void instancia int t ciclo f struct pid pitch struct pid pitch instancia ifdef LOG sprintf msgLog Normal function 96s este gt nombre logPrint msgLog 6 endif struct timespec ts crononsec 1 amp ts principio c digo espec fico funcion normal noRT pid pitch fin c digo espec fico funcion normal noRT pid pitch gt ciclo noRT 0 amp ts if este t ciclo noRT gt gt ciclo noRT max gt ciclo noRT max este 5t ciclo noRT else if este gt t_ciclo_noRT lt este gt t_ciclo_noRT_min este gt t_ciclo_noRT_min este gt t_ciclo_noRT FR gt lt gt lt A void funcionFinaliza II void funcion finaliza pid pitch void instancia struct pid pitch este struct pid pitch instancia ifdef LOG sprintf msgLog Finalizing 96s este gt nombre logPrint msgLog 3 end
252. ing output actualizar matriz1 dcm matriz 1 0 2 output sequence name connection type lt connection gt lt connection gt input renormalizarl dcm matriz 1 1 0 input input resending input type ID ENT FLOAT input type input dimensions output resending output actualizar matriz1 dcm matriz 1 1 0 output sequence name connection type lt connection gt lt connection gt input renormalizarl dcm matriz 1 1 1 input input resending input type ID ENT FLOAT input type input dimensions output resending output actualizar matriz1 dcm matriz 1 1 1 output sequence name connection type lt connection gt lt connection gt input renormalizarl dcm matriz 1 1 2 input input resending input type ID ENT FLOAT input type input dimensions output resending output actualizar matriz1 dcm matriz 1 1 2 output sequence name connection type lt connection gt lt connection gt input renormalizarl dcm matriz 1 2 0 input input resending input type ID ENT FLOAT input type input dimensions output resending output actualizar matriz1 dcm matriz 1 2 0 output sequence name connection type lt connection gt lt connection gt input renormalizarl dcm matriz 1 2 1 input input resending input type ID ENT FLOAT input ty
253. instancia ifdef LOG sprintf msgLog Finalizing s este gt nombre logPrint msgLog 3 endif principio c digo espec fico funcion finaliza giroscopo este gt W gyr 3 0 este gt offsetGyro_x este gt offsetGyro_y este gt offsetGyro_z 0 este gt x este gt y este gt z 0 este gt CalibGyroX este gt CalibGyro Y este gt CalibGyroZ 0 este gt Calib_antX este gt Calib_antY este gt Calib_antZ 0 este gt varX este gt var Y este gt varZ 0 fin c digo espec fico funcion finaliza giroscopo void inicilizagiroscopo IO int inicializa_giroscopo ifdef LOG sprintf msgLog Initializing s ID_giroscopo logPrint msgLog 3 endif clase_giroscopo funcionCrea funcion_crea_giroscopo clase_giroscopo funcionInicializa funcion_inicializa_giroscopo clase_giroscopo funcionNormal funcion_normal_giroscopo clase_giroscopo funcionNormalNoRT funcion normal noRT giroscopo clase_giroscopo funcionFinaliza funcion_finaliza_giroscopo ifdef ID LISTAS iniciarLista amp instancias giroscopo ftelse clase giroscopo n 0 clase giroscopo maxNumComp MAX giroscopo endif clase_giroscopo instancias amp instancias_giroscopo clase_giroscopo longComponente sizeof struct giroscopo return insertarPropiedad2 ID_COMPONENTE ID_giroscopo amp clase_giroscopo ID_COMPONENTE NO_MODIFICABLE MAGNETOMETRO magnetometro h magnetometro h 11 06 2014
254. io magnitud else clase_cambio_magnitud n 0 clase_cambio_magnitud maxNumComp MAX_cambio_magnitud endif clase cambio magnitud instancias amp instancias cambio magnitud clase cambio magnitud longComponente sizeof struct cambio magnitud return insertarPropiedad2 ID_ COMPONENTE ID_cambio_magnitud amp clase cambio magnitud ID COMPONENTE NO_MODIFICABLE j INSTANCIA GENERADORA DE LA SE AL PWM microPWM h microPWM h 11 06 2014 Variables utilizadas microPWM c Eugenio Alcal Baselga Hinclude cosme h define ID microPWM microPWM Hdefine MAX microPWM 16 define PCA9685 I2C ADDR 0x41 define SUBADRI 0x02 define SUBADR2 0x03 define SUBADR3 0x04 define MODEI 0x00 define PRESCALE OxFE define LEDO ON L 0x06 define LEDO ON 0x07 define LEDO OFF L 0x08 define LEDO OFF 0x09 define ALLLED ON L OxFA define ALLLED ON OxFB define ALLLED OFF OxFC define ALLLED OFF OxFD Hdefine APAGAR 0 define MAX ERR MSG 100 struct microPWM char nombre MAX_ LONG NOMBRE int orden byte habilitado byte finalizado int t_ciclo_RT int t_ciclo_RT_min int t ciclo max int t ciclo noRT int t ciclo noRT min int t ciclo noRT max variables char error msg micro PWM MAX ERR MSG float prescale float prescaleval int freq int condicion int ciclo pwm entradas int bus ok int fd int pwm motor grisl int pwm motor gris2 int pwm m
255. ip 750 pF which is intended to suppress some of the ground bounce The customer will need to determine if additional decoupling capacitance externally placed as close as physically possible to the device is required Question 3 Can really sink 400 mA through the single ground pin on the package and will this cause any ground bounce problem due to the PWM of the LEDs Yes you can sink 400 mA through a single ground pin on the package Although the package only has one ground pin there are two ground pads on the die itself connected to this one pin Although some ground bounce is likely it will not disrupt the operation of the part and would be reduced by the external decoupling capacitance Question 4 can t turn the LEDs on or off but their registers are set properly Why e Check the MODE1 register SLEEP bit 4 setting The bit needs to be 0 in order to enable the clocking If both clock sources internal osc and EXTCLK are turned OFF bit 4 2 1 the LEDs cannot be dimmed or blinked Question 5 I m using LEDs with integrated Zener diodes and the IC is getting very hot Why The IC outputs can be set to either open drain or push pull and default to push pull outputs In this application with the Zener diodes they need to be set to open drain since in the push pull architecture there is a low resistance path to GND through the Zener and this is causing the IC to overheat 9685 All information provided this doc
256. is logic 1 write to all four PWM registers any PWM channel Likewise if the user does an orderly shutdown of all the PWM channels before setting the SLEEP bit the RESTART bit will be cleared If this is done the contents of all PWM registers are invalidated and must be reloaded before reuse An example of the use of the RESTART bit would be the restoring of a customer s laptop LCD backlight intensity coming out of Standby to the level it was before going into Standby 1 Two methods can be used to do an orderly shutdown The fastest is to write a logic 1 to bit 4 in register ALL LED OFF H The other method is to write logic 1 to bit 4 in each active PWM channel LEDn OFF H register 9685 All information provided this document is subject to legal disclaimers NXP B V 2010 All rights reserved Product data sheet Rev 3 2 September 2010 14 of 51 Semiconductors 9685 16 channel 12 bit PWM 2 LED controller 7 3 2 Mode register 2 MODE2 Table 5 MODE2 Mode register 2 address 01h bit description Legend default value Bit Symbol Access Value Description 705 read only 000 reserved 4 INVRTIII R W 0 Output logic state not inverted Value to use when external driver used Applicable when OE 0 1 Output logic state inverted Value to use when no external driver used Applicable when OE 0 3 OCH R W 0 Outputs change on STOP command 1 Outputs change on A
257. ith the master device issuing the start sequence followed by the slave address byte The address byte contains the slave address the upper 7 bits bits7 1 and the Least Significant bit LSb The LSb of the address byte designates if the operation is a read LSb 1 or a write LSb 0 At the 9 clock pulse the receiving slave device will issue the ACK or NACK Following these bus events the master will send data bytes for a write operation or the slave will clock out data with a read operation All bus transactions are terminated with the master issuing a stop sequence bus control can be implemented with either hardware logic or in software Typical hardware designs will release the SDA and SCL lines as appropriate to allow the slave device to manipulate these lines In a software implementation care must be taken to perform these tasks in code OPERATIONAL EXAMPLES The HMC5883L has a fairly quick stabilization time from no voltage to stable and ready for data retrieval The nominal 56 milli seconds with the factory default single measurement mode means that the six bytes of magnetic data registers DXRA DXRB DZRA DZRB DYRA and DYRB are filled with a valid first measurement To change the measurement mode to continuous measurement mode after the power up time send the three bytes 0x3C 0x02 0x00 This writes the 00 into the second register or mode register to switch from single to continuous measurement mode setting With the data
258. ity bit is set when acceleration of less than the value stored in the THRESH_INACT register Address 0x25 is experienced for more time than is specified in the TIME_INACT register Address 0x26 on all participating axes as set by the ACT INACT CTL register Address 0x27 The maximum value for TIME INACT is 255 sec FREE FALL The FREE FALL bit is set when acceleration ofless than the value stored in the THRESH FF register Address 0x28 is experienced for more time than is specified in the TIME FF register Address 0x29 on all axes logical AND The FREE FALL interrupt differs from the inactivity interrupt as follows all axes always participate and are logically ANDed the timer period is much smaller 1 28 sec maximum and the mode of operation is always dc coupled Watermark The watermark bit is set when the number of samples in FIFO equals the value stored in the samples bits Register FIFO_CTL Address 0x38 The watermark bit is cleared automatically when FIFO is read and the content returns to a value below the value stored in the samples bits Limit Parameter Test Conditions Min Max Unit Digital Output Low Level Output Voltage Voi lo 300 pA 0 2 X VoD vo V High Level Output Voltage 150 0 8 x Voo vo V Low Level Output Current loi Vor Vol max 300 uA High Level Output Current lou Vou min 150 uA Pin Capacitance fin 1 MHz Vin 2 5 V 8 pF Rise Fall Time Rise Time
259. k k k k k k k k kk k k k k k k k k k kk k kK k k f lt kk gt lt K K int registra_propiedades_acelerometro void instancia struct acelerometro este struct acelerometro instancia char saux MAX_LONG_NOMBRE int 1 insertarNombre2 este gt nombre este emStrcpy saux ID SISTEMA ID acelerometro NO MODIFICABLE insertarPropiedad3 este gt nombre amp este gt nombre ID VAR TEXT PUBLICO nombre insertarPropiedad3 este gt nombre amp este gt orden ID VAR INT PUBLICO MODIFICABLE orden insertarPropiedad3 este gt nombre amp este gt habilitado ID VAR BYTE PUBLICO MODIFICABLE habilitado insertarPropiedad3 este gt nombre amp este gt finalizado ID VAR BYTE PUBLICO MODIFICABLE finalizado insertarPropiedad3 este gt nombre gt ciclo RT ID VAR INT PUBLICO MODIFICABLE t ciclo RT insertarPropiedad3 este gt nombre gt ciclo min ID VAR INT PUBLICO MODIFICABLE t ciclo RT min insertarPropiedad3 este gt nombre gt ciclo max ID VAR INT PUBLICO MODIFICABLE t ciclo max insertarPropiedad3 este gt nombre amp este t ciclo noRT ID VAR INT PUBLICO MODIFICABLE t ciclo noRT insertarPropiedad3 este gt nombre amp este 5t ciclo min ID VAR INT PUBLICO MODIFICABLE t ciclo noRT min insertarPropiedad3 este gt nombre amp este t ciclo noRT max ID VAR INT PUBLICO MODIFICAB
260. latching clearing method can be set and the triggers for the interrupt can be set Note that if the application requires reading every sample of data from the ITG 3200 part it is best to enable the raw data ready interrupt RAW RDY EN This allows the application to know when new sample data is available Parameters ACTL Logic level for INT output pin 1 active low O active high OPEN Drive type for INT output pin 1 open drain O push pull LATCH_INT_EN Latch mode 1 latch until interrupt is cleared 0 50us pulse INT ANYRD 2CLEAR Latch clear method 1 any register read O status register read only ITG RDY EN Enable interrupt when device is ready PLL ready after changing clock source RAW RDY EN Enable interrupt when data is available 0 Load zeros into Bits 1 and 3 of the Interrupt Configuration register 8 5 Register 26 Interrupt Status Type Read only Bit7 Bit6 Bits Bit4 Bit3 Bit2 Bitl pus RAW 1 26 i ITG_RDY DATA 00h RDY Description This register is used to determine the status of the ITG 3200 interrupts Whenever one of the interrupt sources is triggered the corresponding bit will be set The polarity of the interrupt pin active high low and the latch type pulse or latch has no affect on these status bits Use the Interrupt Configuration register 23 to enable the interrupt triggers If the interrupt is not enabled the a
261. le tap double tap responses based on the mechanical characteristics of the system Therefore some experimentation with values for the DUR latent window and THRESH registers is required In general a good starting point is to set the DUR register to a value greater than 0x10 10 ms the latent register to a value greater than 0x10 20 ms the window register to a value greater than 0x40 80 ms and the THRESH register to a value greater than 0x30 3 g Setting a very low value in the latent window or THRESH register may result in an unpredictable response due to the accelerometer picking up echoes of the tap inputs After a tap interrupt has been received the first axis to exceed the 5 level is reported in the STATUS register Address 0x2B This register is never cleared but is overwritten with new data THRESHOLD The lower output data rates are achieved by decimating a common sampling frequency inside the device The activity free fall and single tap double tap detection functions without improved tap enabled are performed using undecimated data Because the bandwidth of the output data varies with the data rate and is lower than the bandwidth of the undecimated data the high frequency and high g data that is used to determine activity free fall and single tap double tap events may not be present if the output of the accelerometer is examined This may result in functions
262. led gt lt instance gt lt instance gt instance name acelerometrol instance name component SISTEMA COMPONENTE acelerometro component specific component creation date lt order gt 2 lt order gt lt collapsed gt lt default_location gt lt tabs gt lt enabled gt true lt enabled gt lt instance gt lt instance gt instance name giroscopol instance name component SISTEMA COMPONENTE giroscopo lt component gt specific component creation date lt order gt 3 lt order gt lt collapsed gt lt default_location gt lt tabs gt lt enabled gt true lt enabled gt lt instance gt lt instance gt instance name magnetometrol instance name component SISTEMA COMPONENTE magnetometro component specific component creation date lt order gt 4 lt order gt lt collapsed gt lt default_location gt lt tabs gt lt enabled gt true lt enabled gt lt instance gt lt instance gt instance name correcionPI Accl instance name component SISTEMA COMPONENTE correcionPI Acc component specific component creation date lt order gt 5 lt order gt lt collapsed gt lt default_location gt lt tabs gt lt enabled gt true lt enabled gt lt instance gt lt instance gt lt instance_name gt promediador1 lt instance_name gt lt component gt SISTEMA COMPONENTE promediador lt component gt lt specific_component gt
263. ling information All input and output pins are protected against ElectroStatic Discharge ESD under normal handling When handling ensure that the appropriate precautions are taken as described in JESD625 A or equivalent standards 17 Soldering of SMD packages 17 1 17 2 This text provides a very brief insight into a complex technology A more in depth account of soldering ICs can be found in Application Note AN10365 Surface mount reflow soldering description Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards PCBs to form electrical circuits The soldered joint provides both the mechanical and the electrical connection There is no single soldering method that is ideal for all packages Wave soldering is often preferred when through hole and Surface Mount Devices SMDs are mixed on one printed wiring board however it is not suitable for fine pitch SMDs Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder The wave soldering process is suitable for the following Through hole components Leaded or leadless SMDs which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered Packages with solder bal
264. ls and some leadless packages which have solder lands underneath the body cannot be wave soldered Also leaded SMDs with leads having a pitch smaller than 0 6 mm cannot be wave soldered due to an increased probability of bridging The reflow soldering process involves applying solder paste to a board followed by component placement and exposure to a temperature profile Leaded packages packages with solder balls and leadless packages are all reflow solderable Key characteristics in both wave and reflow soldering are Board specifications including the board finish solder masks and vias Package footprints including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead free soldering versus SnPb soldering 17 3 Wave soldering 9685 Key characteristics wave soldering All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Product data sheet Rev 3 2 September 2010 45 of 51 Semiconductors 9685 16 channel 12 bit PWM 2 LED controller Process issues such as application of adhesive and flux clinching of leads board transport the solder wave parameters and the time during which components are exposed to the wave Solder bath specifications including temperature and impurities 17 4 Reflow soldering Key cha
265. lt H lt A 2 2 ol o o o k k k k K K k void funcionInicializa II void funcion inicializa correcionPI Acc void instancia 1 struct correcionPI Acc este struct correcionPI Acc instancia ifdef LOG sprintf msgLog Initializing 95 este gt nombre logPrint msgLog 3 endif este gt t_ciclo_RT_min 0x10000000 este 5t ciclo RT max 0 gt ciclo noRT min 0x10000000 gt ciclo noRT max 0 principio c digo espec fico funcion inicializa correcionPI Acc este Kp ROLLPITCH 10 este gt Ki_ROLLPITCH 0 4 este Kd ROLLPITCH 0 4 este gt Omega_P 3 0 este gt Omega_1 3 0 este gt errorRollPitch 0 0 este gt errorRollPitch 1 0 este gt errorRollPitch 2 0 T gt este gt errorRollPitch_old 0 0 este gt errorRollPitch_old 1 0 este gt errorRollPitch_old 2 0 gt fin c digo espec fico funcion inicializa correcionPI Acc RR gt lt H lt A o ol f lt o o gt lt os os os os k k k k k k k kk k k kk k k k kkk k k kk k k k k k K K k void funcionNormal IO void funcion normal correcionPI Acc void instancia int t ciclo struct correcionPI Acc este struct correcionPI Acc instancia floatt ciclo preciso ns 0 int t ciclo rt int devolverElemento SISTEMA ciclo rt ifdef LOG sprintf msgLog Normal function 96s este gt nombre logPrint m
266. ltage range of 2 3 V to 5 5 V and the inputs and outputs are 5 5 V tolerant LEDs can be directly connected to the LED output up to 25 mA 5 5 V or controlled with external drivers and a minimum amount of discrete components for larger current or higher voltage LEDs The PCA9685 is in the new Fast mode Plus Fm family Fm devices offer higher frequency up to 1 MHz and more densely populated bus operation up to 4000 pF Although the PCA9635 and PCA9685 have many similar features the PCA9685 has some unique features that make it more suitable for applications such as LCD backlighting and Ambilight The PCA9685 allows staggered LED output on and off times to minimize current surges The on and off time delay is independently programmable for each of the 16 channels This feature is not available in PCA9635 The PCA9685 has 4096 steps 12 bit PWM of individual LED brightness control The PCA9635 has only 256 steps 8 bit PWM When multiple LED controllers are incorporated in a system the PWM pulse widths between multiple devices may differ if PCA9635s are used The PCA9685 has a programmable prescaler to adjust the PWM pulse widths of multiple devices PCA9685 has an external clock input pin that will accept user supplied clock 50 MHz max in place of the internal 25 MHz oscillator This feature allows synchronization of multiple devices The PCA9635 does not have external clock input feature Like the PCA9635
267. lution 16 g mode to ensure that there is sufficient dynamic range for the entire self test shift This is done by setting Bit D3 ofthe FORMAT register Address 0x31 and writing a value of 0x03 to the range bits Bit D1 and Bit DO of the DATA FORMAT register Address 0x31 This results in a high dynamic range for measurement and a 3 9 mg LSB scale factor After the part is configured for accurate self test measurement several samples of x y and z axis acceleration data should be retrieved from the sensor and averaged together The number of samples averaged is a choice of the system designer but a recommended starting point is 0 1 sec worth of data for data rates of 100 Hz or greater This corresponds to 10 samples at the 100 Hz data rate For data rates less than 100 Hz it is recommended that at least 10 samples be averaged together The averaged values should be stored and labeled appropriately as the self test disabled data that is Xst_orr Ysr ore and Zsr orr ADXL345 Next self test should be enabled by setting Bit D7 SELF TEST of the DATA FORMAT register Address 0x31 The output needs some time about four samples to settle after enabling self test After allowing the output to settle several samples of the x y and z axis acceleration data should be taken again and averaged It is recommended that the same number of samples be taken for this average as was previously taken These averaged values should agai
268. ly a host microprocessor and the HMC5883L Pull up resistance values of about 2 2K to 10K ohms are recommended with a nominal VDDIO voltage Other resistor values may be used as defined in the IC Bus Specifications that can be tied to VDDIO The SCL and SDA lines in this bus specification may be connected to multiple devices The bus can be a single master to multiple slaves or it can be a multiple master configuration All data transfers are initiated by the master device which is responsible for generating the clock signal and the data transfers are 8 bit long All devices are addressed by I C s unique 7 bit address After each 8 bit transfer the master device generates a 9 clock pulse and releases the SDA line The receiving device addressed slave will pull the SDA line low to acknowledge ACK the successful transfer or leave the SDA high to negative acknowledge NACK www honeywell com 17 HMC5883L Per the IC spec all transitions in the SDA line must occur when SCL is low This requirement leads to two unique conditions on the bus associated with the SDA transitions when SCL is high Master device pulling the SDA line low while the SCL line is high indicates the Start S condition and the Stop P condition is when the SDA line is pulled high while the SCL line is high The I C protocol also allows for the Restart condition in which the master device issues a second start condition without issuing a stop All bus transactions begin w
269. ly current versus temperature PCA9685 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Product data sheet Rev 3 2 September 2010 38 of 51 1 ejep jonpoJd 0102 Jequiejdes z ay sieuire osip 129145 si jueuunoop uoneuuojur LG JO 6 S896VOd pemasal syfu 70102 dXN O 13 Dynamic characteristics Table 14 Dynamic characteristics Symbol Parameter Conditions Standard mode Fast mode I2C bus Fast mode Plus Unit 12C bus 12C bus Min Max Min Max Min Max fscL SCL clock frequency 1 0 100 0 400 0 1000 kHz frequency EXTCLK DC 50 DC 50 DC 50 MHz teur bus free time between a STOP 4 7 1 3 0 5 us and START condition THD STA hold time repeated START 4 0 0 6 0 26 us condition tsu sTA set up time for a repeated 4 7 0 6 0 26 us START condition tsu sTO set up time for STOP condition 4 0 0 6 0 26 us THD DAT data hold time 0 0 0 ns 1 data valid acknowledge time 2 0 3 3 45 0 1 0 9 0 05 0 45 us tvp DAT data valid time 3 0 3 3 45 0 1 0 9 0 05 0 45 us tsu DAT data set up time 250 100 50 ns tLow LOW period of the SCL clock 4 7 1 3 0 5 us tHIGH HIGH period of the SCL clock 4 0 0 6 0 26 us tr fall time of both SDA and SCL 415 300 20 0 1631 300 120 ns signals tr rise time of both SDA and SCL 1000 20 0
270. m_matriz_1 0 2 0 este gt dcm_matriz_1 1 0 0 este gt dcm_matriz_1 1 1 1 12 0 0 2 0 1 2 0 2 2 1 gt gt gt y este gt dcm_matriz_1 1 este gt dcm_matriz_1 2 este gt dcm_matriz_1 2 este gt dcm_matriz_1 2 gt 2 gt gt fin c digo espec fico funcion inicializa actualizar_matriz k k k k k K K k void funcionNormal O void funcion_normal_actualizar_matriz void instancia int t ciclo struct actualizar matriz este struct actualizar matriz instancia int t ciclo rt int devolverElemento SISTEMA tiempo ciclo rt ifdef LOG sprintf msgLog Normal function 96s este gt nombre logPrint msgLog 6 endif struct timespec ts crononsec 1 amp ts principio c digo espec fico funcion normal actualizar matriz int x y w l m if t_ciclo_rt gt t ciclo 1e6 0 95 amp amp t_ciclo_rt t ciclo 1e6 1 05 if este gt calibracion_giro 1 este gt Matriz_Cambio 0 0 1 este gt Matriz_Cambio 0 1 float t ciclo rt 1e9 este gt Wgyr_fin 2 z este gt Matriz_Cambio 0 2 float t_ciclo_rt 1e9 este gt Wgyr_fin 1 y este gt Matriz_Cambio 1 0 775 ciclo rt 1e9 este gt Wgyr_fin 2 7 este gt Matriz_Cambio 1 1 este gt Matriz_Cambio 1 2 este gt Matriz_Cambio 2 0 este gt Matriz_Cambio 2 1 este gt Matriz_Cambio 2 2 ciclo_rt 1e9 este gt Wgyr_f
271. mail to salesaddresses nxp com Date of release 2 September 2010 Document identifier PCA9685 ANEXO SCRIPT EN MATLAB PARA LA CALIBRACI N DE LOS MOTORES Graficas_potencia m Vectores contienen del 50 al 100 de potencia Empuje M gris 1 210 220 245 261 280 310 340 371 442 470 543 Empuje M negro 1 198 212 240 259 272 298 326 360 400 426 480 Empuje M gris 2 208 224 245 255 280 300 330 360 399 440 500 Empuje M negro 2 196 210 230 248 268 291 320 348 383 430 490 Empuje M gris 1 corr 210 220 245 261 280 310 340 371 442 470 543 1 06 Empuje M negro 1 corr 198 212 240 259 272 298 326 360 400 426 480 1 02 Empuje M gris 2 corr 208 224 245 255 280 300 330 360 399 440 500 1 03 Empuje M negro 2 corr 196 210 230 248 268 291 320 348 383 430 490 Ciclo trabajo 50 55 60 65 70 75 80 85 90 95 100 figure plot Ciclo trabajo Empuje M gris 1 g hold on plot Ciclo trabajo Empuje M negro 1 77 hold on plot Ciclo trabajo Empuje M gris 2 1 hold on plot Ciclo trabajo Empuje M negro 2 5 legend motor gris 1 motor negro 1 motor gris 2 motor negro 25 xlabel Ciclo PWM 96 ylabel Empuje g figure plot Ciclo trabajo Empuje M gris 1 corr g hold on plot Ciclo trabajo Empuje M negro 1 corr T hold on plot Ciclo trabajo Empuje M gris 2 hold on plot Ciclo trabajo Empuje M negro 2 corr b legend motor gris motor negro 1 motor gris 2 motor negro
272. mal funcion normal i2c clase 12c funcionNormalNoRT funcion normal noRT i2c clase i2c funcionFinaliza funcion finaliza 12 ifdef ID LISTAS iniciarLista amp instancias_i2c else clase_i2c n 0 clase_i2c maxNumComp 12 endif clase_i2c instancias amp instancias_i2c clase_i2c longComponente sizeof struct 12 return insertarPropiedad2 ID COMPONENTE ID_12c amp clase i2c ID COMPONENTE NO MODIFICABLE j ACELER METRO acelerometro h acelerometro h 11 06 2014 Variables ADXL345 Eugenio Alcal Baselga Hinclude cosme h define ID_acelerometro acelerometro define MAX_acelerometro 16 define MAX_EJES 3 define ADXL345_I2C_ADDR 0x53 define ADXL345_POWER_CTL 0x2d define ADXL345_DATA_FORMAT 0x31 struct acelerometro char nombre MAX LONG NOMBRE int orden byte habilitado byte finalizado int t_ciclo_RT int t_ciclo_RT_min int t ciclo max int t ciclo noRT int t ciclo noRT min int t ciclo noRT max variables short 2 unsigned char buf 8 int 1 Niveles de offset del acelerometro float offset acc x float offset acc y float offset acc z entradas int bus ok int fd salidas float Facc MAX_EJES Vector datos acelerometro acelerometro c acelerometro c Captura de mediciones del sensor ADXL345 11 06 2014 Eugenio Alcal Baselga X X X include lt stdio h gt i
273. malizarl dcm matriz renorm 1 0 2 output sequence name connection type lt connection gt lt connection gt input correcionPI Accl dcm matriz renorm 1 1 0 input input resending input type ID ENT FLOAT input type input dimensions output resending output renormalizarl dcm matriz renorm 1 1 0 output sequence name connection type lt connection gt lt connection gt lt input gt correcionPI_Acc1 dcm_matriz_renorm_1 1 1 lt input gt lt input_resending gt lt input_type gt ID_ENT_FLOAT lt input_type gt lt input_dimensions gt lt output_resending gt lt output gt renormalizarl dem_matriz_renorm_1 1 1 lt output gt lt sequence_name gt lt connection_type gt lt connection gt lt connection gt input correcionPI Accl dcm matriz renorm 1 1 2 input input resending input type ID ENT FLOAT input type input dimensions output resending output renormalizarl dcm matriz renorm 1 1 2 output sequence name connection type lt connection gt lt connection gt input correcionPI Accl dcm matriz renorm 1 2 0 input input resending input type ID ENT FLOAT input type input dimensions output resending output renormalizarl dcm matriz renorm 1 2 0 output sequence name connection type lt connection gt lt connection gt lt input gt correcionPI_A
274. matriz temporal MAX EJES MAX EJES float time muestreo float acumula MAX_EJES entradas float Wgyr fin MAX EJES int calibracion giro float dcm matriz renorm EJES MAX EJES salidas float dcm matriz EJES MAX EJES float DCM MatrizIMAX EJES MAX EJES actualizar_matriz c actualizar matriz c partir de las mediciones del giroscopo s las convierte y las almacena en la matriz de rotaci n 11 06 2014 Eugenio Alcal Baselga ftinclude lt stdio h gt include lt string h gt include lt math h gt include runtime h include actualizar_matriz h ifdef ID LISTAS struct lista instancias actualizar matriz else define MAX_actualizar_matriz 16 struct actualizar matriz instancias_actualizar_matriz MAX_actualizar_matriz endif struct componente clase_actualizar_matriz extern char msgLog extern float fdummy extern int dummy k k K K k K K K void inicializa_propiedades IO void inicializa_propiedades_actualizar_matriz void instancia char nombre int orden unsigned char habilitado struct actualizar matriz struct actualizar matriz instancia strcpy este gt nombre nombre este gt orden orden este gt habilitado habilitado este gt finalizado 0 principio inicializaci n de propiedades espec ficas actualizar_matriz este gt dcm_matriz_renorm_1 0 0 amp fdummy es
275. may have additional noise especially if the device was asleep when the bit was cleared Measure Bit A setting of 0 the measure bit places the part into standby mode and a setting of 1 places the part into measurement mode The ADXL345 powers up in standby mode with minimum power consumption Sleep Bit A setting of 0 in the sleep bit puts the part into the normal mode of operation and a setting of 1 places the part into sleep mode Sleep mode suppresses DATA READY stops transmission of data to FIFO and switches the sampling rate to one specified by the wakeup bits In sleep mode only the activity function can be used When the DATA READY interrupt is suppressed the output data registers Register 0x32 to Register 0x37 are still updated at the sampling rate set by the wakeup bits D1 D0 When clearing the sleep bit it is recommended that the part be placed into standby mode and then set back to measurement mode with a subsequent write This is done to ensure that the device is properly biased if sleep mode is manually disabled otherwise the first few samples of data after the sleep bit is cleared may have additional noise especially if the device was asleep when the bit was cleared Wakeup Bits These bits control the frequency of readings in sleep mode as described in Table 20 Table 20 Frequency of Readings in Sleep Mode Register OX2E INT ENABLE Read Write D7 D6 D5 D4 DATA_READY SINGLE_TAP DO
276. mbio_magnitud h cambio_magnitud h 11 06 2014 Variables utilizadas en cambio_magnitud c Eugenio Alcal Baselga Hinclude cosme h define ID cambio magnitud cambio magnitud define MAX cambio magnitud 16 struct cambio magnitud char nombre MAX LONG NOMBRE int orden byte habilitado byte finalizado int t ciclo RT intt ciclo RT min int t ciclo max int t ciclo noRT int t ciclo noRT min int t ciclo noRT max int potencia entradas float pitch float out roll salidas int pwm motor 91151 int pwm motor gris2 int pwm motor negrol int pwm motor negro2 cambio magnitud c cambio magnitud c Calcula el ciclo PWM cada motor partir de los reguladores PID s 11 06 2014 Eugenio Alcal Baselga Hinclude lt stdio h gt include lt string h gt include lt math h gt include runtime h include cambio_magnitud h ifdef ID_LISTAS struct lista instancias_cambio_magnitud else define MAX_cambio_magnitud 16 struct cambio magnitud instancias_cambio_magnitud MAX_cambio_magnitud endif struct componente clase_cambio_magnitud extern char msgLog extern float fdummy HR gt e gt lt ol ol o k k k k k kk k kK k k K k k K K K void inicializa_propiedades E k 2 o lt 2 k k k k k k k k k kk k k k k k k k k kk k kK k k fe k K K K K void inicializa_propiedades_cam
277. mmy fin inicializaci n de propiedades espec ficas pid_roll a A gt lt o lt 2 al ol k k k k kkk k kK k k K k k K K k void registra_propiedades IN int registra_propiedades_pid_roll void instancia struct pid roll struct pid roll instancia char LONG NOMBRE insertarNombre2 este gt nombre este emStrcpy saux ID SISTEMA ID pid roll NO MODIFICABLE insertarPropiedad3 este gt nombre amp este gt nombre ID VAR TEXT PUBLICO nombre insertarPropiedad3 este gt nombre amp este gt orden ID VAR INT PUBLICO MODIFICABLE orden insertarPropiedad3 este gt nombre amp este gt habilitado ID VAR BYTE PUBLICO MODIFICABLE habilitado insertarPropiedad3 este gt nombre amp este gt finalizado ID VAR BYTE PUBLICO MODIFICABLE finalizado insertarPropiedad3 este gt nombre gt ciclo RT ID VAR INT PUBLICO MODIFICABLE t ciclo RT insertarPropiedad3 este gt nombre amp gt ciclo min ID VAR INT PUBLICO MODIFICABLE t ciclo RT min insertarPropiedad3 este gt nombre gt ciclo max ID VAR INT PUBLICO MODIFICABLE t ciclo RT max insertarPropiedad3 este gt nombre gt ciclo noRT ID VAR INT PUBLICO MODIFICABLE t ciclo noRT insertarPropiedad3 este gt nombre amp este t ciclo min ID VAR INT PUBLICO MODIFICABLE t ciclo
278. msec 3 is VLOGIC rise time Time for VLOGIC to rise from 10 to 90 of its final value 4 Tv cr is lt Imsec 5 Tvie vpp is the delay from the start of VDD ramp to the start of VLOGIC rise 6 Tvic vpp is 20msec but VLOGIC amplitude must always be lt VDD amplitude 7 VDD and VLOGIC must be monotonic ramps 15 of 39 Document Number PS ITG 3200A 00 01 4 e Z T Revision 1 4 InvenSense ITG 3200 Product Specification RD 09 30 2010 5 Functional Overview 5 1 Block Diagram Optional La ITG 3200 X Gyro Interrupt Status ADC Signal Register Q INT Conditioning Config Signal Serial T Sensor Register Signal Temp Sensor ADC Factory Cal Charge Bias amp LDO Pump d 20 de dis CPOUT VDD VLOGIC GND REGOUT Z Gyro 5 2 Overview The ITG 3200 consists of the following key blocks and functions e Three axis MEMS rate gyroscope sensors with individual 16 bit ADCs and signal conditioning PC serial communications interface Clocking Sensor Data Registers Interrupts Digital Output Temperature Sensor Bias and LDO Charge Pump 5 3 Three Axis MEMS Gyroscope with 16 bit ADCs and Signal Conditioning The ITG 3200 consists of three independent vibratory MEMS gyroscopes which detect rotational rate about the X roll Y pitch and Z yaw axes When the gyros are rotated about any of the sense axes the Coriolis Effect causes a deflection that is detected by a capacitive
279. n be stored and labeled appropriately as the value with self test enabled that is Xsr Ysr ow and ox Self test can then be disabled by clearing Bit D7 SELF TEST ofthe DATA FORMAT register Address 0x31 With the stored values for self test enabled and disabled the self test change is as follows Xsr orr Ysr Ysr Ysr Zsr Zst_on Zst_OFF Because the measured output for each axis is expressed in LSBs Xsr Ysr and Zsr are also expressed in LSBs These values can be converted to g s of acceleration by multiplying each value by the 3 9 mg LSB scale factor if configured for full resolution mode Additionally Table 15 through Table 18 correspond to the self test range converted to LSBs and can be compared with the measured self test change when operating at a Vs of 2 5 V For other voltages the minimum and maximum self test output values should be adjusted based on multiplied by the scale factors shown in Table 14 If the part was placed into 2 g 10 bit or full resolution mode the values listed in Table 15 should be used Although the fixed 10 bit mode or a range other than 16 g can be used a different set of values as indicated in Table 16 through Table 18 would need to be used Using a range below 8 g may result in insufficient dynamic range and should be considered when selecting the range of operation for measuring self test If the self test change is within the valid
280. n data output registers Data can be re read from the data output registers if necessary however if the master does not ensure that the data register is accessed before the completion of the next measurement the data output registers are updated with the new measurement To conserve current between measurements the device is placed in a state similar to idle mode but the Mode Register is not changed to Idle Mode That is MD n bits are unchanged Settings in the Configuration Register A affect the data output rate bits DO n the measurement configuration bits MS n when in continuous measurement mode All registers maintain values while in continuous measurement mode I C bus is enabled for use by other devices on the network in while continuous measurement mode Single Measurement Mode This is the default power up mode During single measurement mode the device makes a single measurement and places the measured data in data output registers After the measurement is complete and output data registers are updated the device is placed in idle mode and the Mode Register is changed to idle mode by setting MD n bits Settings the configuration register affect the measurement configuration bits MS n when in single measurement mode registers maintain values while in single measurement mode The I C bus is enabled for use by other devices on the network while in single measurement mode Idle Mode During this mode the device i
281. n oscillator less accurate Anyofthe X Y or Z gyros MEMS oscillators with an accuracy of 2 over temperature Allowable external clocking sources are e 32 768kHz square wave e 19 2 square wave Which source to select for generating the internal synchronous clock depends on the availability of external sources and the requirements for clock accuracy There are also start up conditions to consider When the ITG 3200 first starts up the device operates off of its internal clock until programmed to operate from another source This allows the user for example to wait for the MEMS oscillators to stabilize before they are selected as the clock source 5 6 Sensor Data Registers The sensor data registers contain the latest gyro and temperature data They are read only registers and are accessed via the Serial Interface Data from these registers may be read at any time however the interrupt function may be used to determine when new data is available 5 7 Interrupts Interrupt functionality is configured via the Interrupt Configuration register Items that are configurable include the INT pin configuration the interrupt latching and clearing method and triggers for the interrupt Items that can trigger an interrupt are 1 Clock generator locked to new reference oscillator used when switching clock sources and 2 new data is available to be read from the Data registers The interrupt status can be read from the Interrupt Status re
282. n this document is subject to legal disclaimers NXP B V 2010 All rights reserved Product data sheet Rev 3 2 September 2010 47 of 51 Semiconductors 9685 16 channel 12 bit PWM 2 LED controller 19 Revision history Table 19 Revision history Document ID Release date Data sheet status Change notice Supersedes PCA9685 v 3 20100902 Product data sheet PCA9685 v 2 Modifications Table 1 Ordering information Topside mark for PCA9685BS changed from 9685 5 to P9685 PCA9685 v 2 20090716 Product data sheet PCA9685 v 1 PCA9685 v 1 20080724 Product data sheet 9685 Product data sheet All information provided in this document is subject to legal disclaimers Rev 3 2 September 2010 NXP B V 2010 All rights reserved 48 of 51 NXP Semiconductors PCA9685 20 Legal information 16 channel 12 bit PWM 2 LED controller 20 1 Data sheet status Document status 1 21 Product statusi3 Definition Objective short data sheet Development Preliminary short data sheet Qualification Product short data sheet Production This document contains data from the objective specification for product development This document contains data from the preliminary specification This document contains the product specification 1 Please consult the most recently issued document before initiating
283. nclude lt string h gt include lt math h gt include lt sys ioctl h gt include lt sys select h gt include lt sys time h gt include lt sys stat h gt include lt sys types h gt include lt fentl h gt include lt signal h gt include lt unistd h gt include lt termios h gt include runtime h include acelerometro h include linux i2c dev h ifdef ID_LISTAS struct lista instancias_acelerometro else define MAX_acelerometro 16 struct acelerometro instancias acelerometro MA X acelerometro endif struct componente clase_acelerometro extern char msgLog int dummy 0 FREE SE ol ok oe k k k ee he he k fe k k k k k k k k k kk k kK k k k k k K K K void inicializa_propiedades k k k k k k k kk k k kk k k k k k kk k kK k k f lt k k gt e K K void inicializa propiedades acelerometro void instancia char nombre int orden unsigned char habilitado struct acelerometro struct acelerometro instancia strcpy este gt nombre nombre este gt orden orden este gt habilitado habilitado este gt finalizado 0 principio inicializaci n de propiedades espec ficas acelerometro este gt fd amp dummy este gt bus_ok amp dummy fin inicializaci n de propiedades espec ficas acelerometro 78 gt lt gt lt k k k k k kk k kK k k K k k K K K void registra_propiedades k k k k
284. ndif principio c digo espec fico funcion finaliza renormalizar fin c digo espec fico funcion finaliza renormalizar void inicilizarenormalizar O int inicializa_renormalizar ifdef LOG sprintf msgLog Initializing s ID_renormalizar logPrint msgLog 3 endif clase renormalizar funcionCrea funcion crea renormalizar clase renormalizar funcionInicializa funcion inicializa renormalizar clase renormalizar funcionNormal funcion normal renormalizar clase renormalizar funcionNormalNoRT funcion normal noRT renormalizar clase renormalizar funcionFinaliza funcion finaliza renormalizar ifdef ID LISTAS iniciarLista amp instancias renormalizar else clase_renormalizar n 0 clase_renormalizar maxNumComp MAX_renormalizar endif clase_renormalizar instancias amp instancias_renormalizar clase_renormalizar longComponente sizeof struct renormalizar return insertarPropiedad2 ID_ COMPONENTE ID_renormalizar amp clase renormalizar ID COMPONENTE NO MODIFICABLE j INSTANCIA CONVERSORA ANGULOS conversor_angulos h conversor_angulos h Variables utilizadas en conversor_angulos c 11 06 2014 Eugenio Alcal Baselga Hinclude cosme h define ID conversor angulos conversor angulos define MAX conversor angulos 16 define MAX EJES 3 define RADIANES GRADOS 57 29577951 struct conversor angulos char nombre MAX LONG NOMBRE int orden byte
285. nformation LED displays LCD backlights Keypad backlights for cellular phones or handheld devices 4 Ordering information Table 1 Ordering information Type number PCA9685PW PCA9685PW Q900l1 9685 5 Topside mark Package Name Description Version PCA9685PW TSSOP28 plastic thin shrink small outline package SOT361 1 28 leads body width 4 4 mm PCA9685PW TSSOP28 plastic thin shrink small outline package SOT361 1 28 leads body width 4 4 mm P9685 HVQFN28 plastic thermal enhanced very thin quad flat SOT788 1 package no leads 28 terminals body 6 x 6 x 0 85 mm 1 PCA9685PW Q900 is AEC Q100 compliant Contact i2c support nxp com for PPAP 9685 All information provided this document is subject to legal disclaimers NXP B V 2010 All rights reserved Product data sheet Rev 3 2 September 2010 3 of 51 Semiconductors 9685 16 channel 12 bit PWM 2 LED controller 5 Block diagram AO A1 2 4 AS 9685 SCL Bn INPUT FILTER 12C BUS CONTROL v POWER ON pR RESET Vss LED STATE SELECT REGISTER PWM REGISTER X PRESCALE BRIGHTNESS LEDn CONTROL 25 MHz OSCILLATOR CLOCK SWITCH EXTCLK 0 permanently OFF 1 permanently ON OE 002 824 Remark Only one LED output shown for clarity Fig 1 Block diagram of PCA9685
286. nformation provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Product data sheet Rev 3 2 September 2010 43 of 51 Semiconductors 9685 16 channel 12 bit PWM 2 LED controller HVQFN28 plastic thermal enhanced very thin quad flat package no leads 28 terminals body 6 x 6 x 0 85 mm SOT788 1 terminal 1 index area A detail X unio DIMENSIONS mm are the original dimensions UNIT max A1 b Dh E En mm 1 0 05 0 35 02 6 1 425 6 1 4 25 0 00 0 25 59 3 95 5 9 3 95 Note 1 Plastic or metal protrusions of 0 075 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN VERSION JEDEC JEITA PROJECTION SOT788 1 MO 220 E 02 10 22 ISSUE DATE Fig 37 Package outline SOT788 1 HVQFN28 9685 All information provided this document is subject to legal disclaimers NXP B V 2010 All rights reserved Product data sheet Rev 3 2 September 2010 44 of 51 Semiconductors 9685 16 channel 12 bit PWM 2 LED controller 16 Hand
287. noRT min insertarPropiedad3 este gt nombre amp este t ciclo noRT max ID VAR INT PUBLICO MODIFICABLE t ciclo noRT max principio registro de propiedades espec ficas pid roll insertarPropiedad3 este gt nombre amp este proportional roll ID FLOAT PUBLICO MODIFICABLE proportional roll insertarPropiedad3 este gt nombre amp este integral roll ID VAR FLOAT PUBLICO MODIFICABLE integral roll insertarPropiedad3 este gt nombre amp este derivative roll ID VAR FLOAT PUBLICO MODIFICABLE derivative roll insertarPropiedad3 este gt nombre amp este error roll ID FLOAT PUBLICO MODIFICABLE error roll insertarPropiedad3 este gt nombre amp este variacion error roll ID VAR FLOAT PUBLICO MODIFICABLE variacion error roll insertarPropiedad3 este gt nombre amp gt _ old roll ID FLOAT PUBLICO MODIFICABLE out old roll insertarPropiedad3 este gt nombre amp este kp roll ID VAR FLOAT PUBLICO MODIFICABLE kp roll insertarPropiedad3 este gt nombre amp este ki roll ID VAR FLOAT PUBLICO MODIFICABLE ki roll insertarPropiedad3 este gt nombre amp este gt kd_roll ID VAR FLOAT PUBLICO MODIFICABLE kd roll insertarPropiedad3 este gt nombre amp este reference roll ID ENT FLOAT PUBLICO MODIFICABLE reference roll insertarPropiedad3 este gt nombre amp este gt roll ID ENT FLOAT PUBLI
288. nowledge from slave from slave from slave STOP condition 002aad190 Fig 24 Write to ALL LED OFF H to turn OFF all PWMs 9685 Product data sheet All information provided in this document is subject to legal disclaimers Rev 3 2 September 2010 B V 2010 All rights reserved 32 of 51 Semiconductors 9685 16 channel 12 bit PWM 2 LED controller slave address control register data for MODE register sequence f HE condition register selection Al enable ALL du ror acknowledge acknowledge acknowledge condition from slave from slave from slave slave address control register new LEDALLCALL I C bus address sequence jf a condition E ALLGALT ADA A PM register selection f f diti acknowledge rom slave rom slave condition from slave data for control register LEDALLCALL 12C bus address control register LED _ON_L cont sequen C Pa pm Pus condition Jn ALL_LED_ON_L e register selection f acknowledge 2 from all the Mid devices configured for the new LEDALLCALL I C bus address ALL LED OFF H 87 aa AAA ALL LED ON H data for ALL LED OFF L 2 control register control register acknowledge acknowledgel stor from slave from slave condition acknowledge 2 from slave 002aad192 1 In this example several PCA968
289. o c IS RUNTIME_PATH Im correcionPI_Acc o correcionPI_Acc h correcionPI_Acc c A RUNTIME_PATH utiles h RUNTIME_PATH utiles c RUNTIME_PATH cosme h RUNTIME_PATH runtime h RUNTIME_PATH runtime c RUNTIME_PATH runtime_esp h RUNTIME_PATH runtime_esp c RUNTIME_PATH raspi h RUNTIME_PATH raspi c CC c correcionPI Acc c I RUNTIME_PATH Im promediador o promediador h promediador c RUNTIME_PATH utiles h RUNTIME_PATH utiles c RUNTIME_PATH cosme h RUNTIME_PATH runtime h RUNTIME_PATH runtime c RUNTIME_PATH runtime_esp h RUNTIME PATH runtime esp c RUNTIME_PATH raspi h RUNTIME CC c promediador c ISIRUNTIME PATH Im correccionPI Mag o correccionPI Mag h correccionPI Mag c V RUNTIME_PATH utiles h RUNTIME PATH utiles c RUNTIME_PATH cosme h RUNTIME_PATH runtime h RUNTIME_PATH runtime c RUNTIME_PATH runtime_esp h S RUNTIME_PATH runtime_esp c RUNTIME PATH raspi h RUNTIME_PATH raspi c CC c correccionPI Mag c IS RUNTIME PATH Im actualizar matriz o actualizar matriz h actualizar matriz c RUNTIME_PATH utiles h RUNTIME_PATH utiles c RUNTIME_PATH cosme h RUNTIME_PATH runtime h RUNTIME_PATH runtime c RUNTIME_PATH runtime_esp h RUNTIME PATH runtime esp c RUNTIME_PATH raspi h RUNTIME CC c actualizar matriz c IS RUNTIME PATH Im renormalizar o renormalizar h renormalizar c RUNTIME_PATH utiles h
290. o the power up default settings SLEEP Enable low power sleep mode STBY_XG Put gyro X in standby mode 1 standby 0 normal STBY YG Put gyro Y in standby mode 1 standby 0 normal STBY ZG Put gyro Z in standby mode 1 standby O normal CLK SEL Select device clock source 28 of 39 Document Number PS ITG 3200A 00 01 4 y Z He Revision 1 4 InvenSense ITG 3200 Product Specification Rose Dare 08 50P010 9 Assembly 9 1 Orientation The diagram below shows the orientation of the axes of sensitivity and the polarity of rotation Orientation of Axes of Sensitivity and Polarity of Rotation 29 of 39 9 2 2 InvenSense gt ITG 3200 Product Specification Package Dimensions PIN 1 INDENT Top View SYMBOLS DIMENSIONS IN MILLIMETERS MIN NOM MAX A D A D NENNEN ls N N 030 035 25 t 0 30 L Es w 8 a o S 2 95 5 pa 0 0 02 0 05 0 95 90 k o 30 00 4 10 300 305 oso 0 45 o o 0 145 0 25 0 075 Package Dimensions Document Number PS ITG 3200A 00 01 4 Revision 1 4 Release Date 03 30 2010 Bottom View M On 4 corner lead di aN 30 of 39 Document Number PS ITG 3200A 00 01 4 ITG 3200 Product Specification Revision 1 4 Release Date 03 30 2010 gt InvenSense a 9 3 Package Marking Specification TOP VIEW
291. oRT else 1 gt ciclo noRT lt gt ciclo noRT min este 5t ciclo noRT min este gt t_ciclo_noRT o lt 2 2 f lt o o k ls ds ls ds ds ls ls ls le k k kk k k k k kk k k kk k k k k K void funcionFinaliza O void funcion_finaliza_cambio_magnitud void instancia 1 struct cambio magnitud este struct cambio magnitud instancia Hifdef LOG sprintf msgLog Finalizing 96s este gt nombre logPrint msgLog 3 endif principio c digo espec fico funcion finaliza cambio_magnitud este pwm motor gris 0 este pwm motor gris2 0 este pwm motor negrol 0 este pwm motor negro2 0 fin c digo espec fico funcion finaliza cambio magnitud j 2 2 2 f lt k k k k k kkk k k k gt lt void inicilizacambio_magnitud O int inicializa cambio magnitud ifdef LOG sprintf msgLog Initializing s ID cambio magnitud logPrint msgLog 3 endif clase_cambio_magnitud funcionCrea funcion_crea_cambio_magnitud clase_cambio_magnitud funcionInicializa funcion_inicializa_cambio_magnitud clase_cambio_magnitud funcionNormal funcion_normal_cambio_magnitud clase_cambio_magnitud funcionNormalNoRT funcion_normal_noRT_cambio_magnitud clase_cambio_magnitud funcionFinaliza funcion finaliza cambio magnitud ifdef ID LISTAS iniciarLista amp instancias camb
292. o_y este gt Calib_antY 50 0 este gt offsetGyro_z este gt Calib_antZ 50 0 este gt calibracion_giro 1 fin c digo espec fico funcion normal giroscopo este gt t_ciclo_RT 0 amp ts if este gt t_ciclo_RT gt este gt t_ciclo_RT_max este gt t_ciclo_RT_max este gt t_ciclo_RT else if este gt t_ciclo_RT lt este gt t_ciclo_RT_min este gt t_ciclo_RT_min este gt t_ciclo_RT kk k k k k k K void funcionNormalNoRT O void funcion normal noRT giroscopo void instancia int t ciclo struct giroscopo este struct giroscopo instancia ifdef LOG sprintf msgLog Normal function s este gt nombre logPrint msgLog 6 endif struct timespec ts crononsec 1 amp ts principio c digo espec fico funcion normal noRT giroscopo fin c digo espec fico funcion normal noRT giroscopo gt ciclo noRT 0 amp ts if este 5t ciclo noRT gt gt ciclo noRT max este 5t ciclo noRT max este 5t ciclo noRT else if este gt t_ciclo_noRT lt gt ciclo noRT min gt ciclo noRT min este 5t ciclo noRT k k k k k K void funcionFinaliza k k k k k k k k k k k kk k k k k k K k k kK k KK k k fe K k gt lt K K void funcion_finaliza_giroscopo void instancia struct giroscopo este struct giroscopo
293. oll este gt variacion_error_roll float t_ciclo_rt 1e9 este gt out_roll 0 8 0 04 este gt error_roll este gt proportional_roll este gt ki_roll este gt integral_roll este gt kd_roll este gt derivative_roll if este gt out_roll gt 50 este gt out_roll 50 else if este gt out_roll lt 50 este gt out_roll 50 este gt error_old1_roll este gt error_roll este gt out_old_roll este gt out_roll fin c digo espec fico funcion normal pid_roll este gt t_ciclo_RT 0 416 if este gt t_ciclo_RT gt este gt t_ciclo_RT_max este gt t_ciclo_RT_max este gt t_ciclo_RT else if este gt t_ciclo_RT lt este gt t_ciclo_RT_min este gt t_ciclo_RT_min este gt t_ciclo_RT k k K k k K K K void funcionNormalNoRT IO void funcion normal noRT pid roll void instancia int t ciclo struct pid roll este struct pid roll instancia ifdef LOG sprintf msgLog Normal function 96s este gt nombre logPrint msgLog 6 endif struct timespec ts crononsec 1 amp ts principio c digo espec fico funcion normal noRT pid roll fin c digo espec fico funcion normal noRT pid roll gt ciclo noRT 0 amp ts if este gt t_ciclo_noRT gt este gt t_ciclo_noRT_max este gt t_ciclo_noRT_max este gt t_ciclo_noRT else if este gt t_ciclo_noRT lt este
294. on of the usable signal also depends on the noise floor of the system i e Effective Resolution Max Digital Resolution Noise Floor Choose a lower gain value higher GN when total field strength causes overflow in one of the data output registers saturation Note that the very first measurement after a gain change maintains the same gain as the previous setting The new gain setting is effective from the second measurement and on Recommended Gain Digital GN2 GN1 GNO Sensor Field LSb Resolution Output Range Range Gauss mG LSb 0 o o 0 88 Ga 1370 0 73 2 o 1090 46 0 92 A 0 1 0 1 9 820 1 22 0 1 1 2 5 Ga 660 1 52 1 0 o 4 0 Ga 440 2 27 1 0 1 4 7 Ga 390 2 56 ole 0 1 1 0 5 6Ga 330 3 03 1 1 1 8 1 Ga 230 4 35 www honeywell com Table 9 Gain Settings 13 HMC5883L Mode Register The mode register is an 8 bit register from which data can be read or to which data can be written This register is used to select the operating mode of the device MRO through MR7 indicate bit locations with denoting the bits that are in the mode register MR7 denotes the first bit of the data stream The number in parenthesis indicates the default value of that bit Mode register default is 0 01 MR7 MR6 5 MR4 MR3 MR2 MR1 MRO HS 0 0 0 0 0 0 MD1 0 MDO 1
295. onPI_Mag void instancia int t ciclo struct correccionPI Mag este struct correccionPI Mag instancia ifdef LOG sprintf msgLog Normal function 96s este gt nombre logPrint msgLog 6 endif struct timespec ts crononsec 1 amp ts principio c digo espec fico funcion normal noRT correccionPI Mag fin c digo espec fico funcion normal noRT correccionPI Mag este t ciclo noRT 0 amp ts if este t ciclo noRT gt gt ciclo noRT max este 5t ciclo noRT max este 5t ciclo noRT else if este gt t_ciclo_noRT lt gt ciclo noRT min este 5t ciclo noRT min este 5t ciclo noRT void funcionFinaliza IO void funcion_finaliza_correccionPI_Mag void instancia struct correccionPI_Mag este struct correccionPI_Mag instancia ifdef LOG sprintf msgLog Finalizing 96s este gt nombre logPrint msgLog 3 endif principio c digo espec fico funcion finaliza correccionPI_Mag este gt Omega_P_Compass 3 0 este gt Omega_I_Compass 3 0 este gt errorY aw 3 0 fin c digo espec fico funcion finaliza correccionPI Mag 346 gt lt gt lt kk k k k k kkk k kk k k k k k K K k void inicilizacorreccionPI Mag E 2 o lt 2 ope k k k k int inicializa_correccionPI_Mag f ifdef LOG sprintf msgLog Initializing s ID correccionPI Mag
296. opiedad3 este gt nombre gt ciclo RT ID VAR INT PUBLICO MODIFICABLE t ciclo RT insertarPropiedad3 este gt nombre gt ciclo min ID VAR INT PUBLICO MODIFICABLE t ciclo min insertarPropiedad3 este gt nombre gt ciclo max ID VAR INT PUBLICO MODIFICABLE t ciclo max insertarPropiedad3 este gt nombre amp este t ciclo noRT ID VAR INT PUBLICO MODIFICABLE t ciclo noRT insertarPropiedad3 este gt nombre amp este 5t ciclo min ID VAR INT PUBLICO MODIFICABLE t ciclo noRT min insertarPropiedad3 este gt nombre amp este 5t ciclo noRT max ID VAR INT PUBLICO MODIFICABLE t ciclo noRT max principio registro de propiedades espec ficas actualizar matriz for i 0 i lt MAX EJES 1 for j 0 j lt MAX EJES j insertarPropiedad3 este gt nombre amp este gt dcm_matriz_1 i j ID_SAL_FLOAT PUBLICO MODIFICABLE dcm matriz 1 96d 96d 1 j for i 0 i lt 5 i for j 0 j lt MAX_EJES j insertarPropiedad3 este gt nombre amp este dcm matriz renorm 1 i j ID ENT FLOAT PUBLICO MODIFICABLE dcm matriz renorm 1 46d 96d i j for i 0 i lt MAX EJES i for j 0 j lt MAX EJES j insertarPropiedad3 este gt nombre amp este gt DCM_Matriz i j ID SAL FLOAT PUBLICO MODIFICABLE DCM_Matriz d d i for i 0
297. otor negrol int pwm motor negro2 salidas microPWM c microPWM c configura el microcontrolador PCA9685 y se escribe en sus registros el valor de PWM a generar 11 06 2014 Eugenio Alcal Baselga el include lt stdio h gt include lt string h gt include lt math h gt include lt sys time h gt include lt sys select h gt include lt sys ioctl h gt include lt sys stat h gt include local 12c dev h include lt linux types h gt include runtime h include microPWM h ifdef ID_LISTAS struct lista instancias microPWM else define MAX_microPWM 16 struct microPWM instancias_microPWM MAX_microPWM endif struct componente clase microPWM extern char msgLog extern int dummy po ol ol ol f lt o ade k k k k kK K k void inicializa_propiedades IO void inicializa_propiedades_microPWM void instancia char nombre int orden unsigned char habilitado struct microPWM este struct microPWM instancia strcpy este gt nombre nombre este gt orden orden este gt habilitado habilitado este gt finalizado 0 principio inicializaci n de propiedades espec ficas microPWM este gt fd amp dummy este gt bus_ok amp dummy este pwm motor gris amp dummy este pwm motor gris2 amp dummy este pwm motor negrol amp dummy este pwm motor negro2 amp dummy fin inicializaci n de propiedades espec fi
298. output current on pin LEDn 25 mA Iss ground supply current 400 mA Prot total power dissipation 400 mW Tstg storage temperature 65 150 C Tamb ambient temperature operating 40 85 C 12 Static characteristics Table 13 Static characteristics Vpp 2 3 V to 5 5 V Vss 0 V Tamp 40 C to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Supply Vpp supply voltage 2 8 5 5 V Ipp supply current operating mode no load 6 10 mA 1 MHz Vpp 2 3 V to 5 5 V Istb standby current no load 0 Hz Vpp or Vss 2 2 15 5 Vpp 2 3 V to 5 5 V Vpor power on reset voltage no load V Vpp or Vss 1 70 2 0 V Input SCL input output SDA Vit LOW level input voltage 0 5 0 3Vpp V Vin HIGH level input voltage 0 7 5 5 V lo LOW level output current 0 4 V Vpp 2 3 20 28 mA Vor 0 4 V 5 0 V 30 40 mA IL leakage current Vi Vpp or Vss 1 H1 C input capacitance Vi Vss 6 10 LED driver outputs LOW level output current Vo 0 5 V Vpp 2 3 V to 4 5 V 2 12 25 mA loL tot total LOW level output current Vo 0 5 V Vpp 4 5 V 400 mA lou HIGH level output current open drain Von Vpp 10 10 HIGH level output voltage lou 10 mA Vpp 2 3 V 1 6 V lou 10 mA Vpp 3 0 V 2 3 V 10 mA Vpp 4 5 V 4 0 V loz OFF state output current 3 state Vpp or Vss 10 10
299. p este bus ok ID ENT INT PUBLICO IMODIFICABLE bus ok insertarPropiedad3 este gt nombre amp este gt fd ID ENT INT PUBLICO IMODIFICABLE fd for z 0 z lt MAX 5 z insertarPropiedad3 este gt nombre amp este Vmag z ID SAL FLOAT PUBLICO MODIFICABLE Vmag d z insertarPropiedad3 este gt nombre amp gt msg mag ID VAR TEXT PUBLICO MODIFICABLE Msg error mag insertarPropiedad3 este gt nombre amp este gt x ID VAR SHORT PUBLICO MODIFICABLE x insertarPropiedad3 este gt nombre amp este gt y ID VAR SHORT PUBLICO MODIFICABLE y insertarPropiedad3 este gt nombre amp este gt z ID VAR SHORT PUBLICO MODIFICABLE z fin registro de propiedades espec ficas magnetometro j void funcionCrea O int funcion_crea_magnetometro void instancia char nombre int orden unsigned char habilitado struct magnetometro este struct magnetometro instancia ifdef LOG sprintf msgLog Creating s nombre logPrint msgLog 3 endif inicializa_propiedades_magnetometro instancia nombre orden habilitado if registra_propiedades_magnetometro instancia 0 ifdef LOG sprintf msgLog s V Registering properties of s ID ERROR este gt nombre logPrint msgLog 1 endif if registrarInstancia instancia nombre amp clase_magnetometro orden amp este gt habilitado amp este gt finali
300. p este 5t ciclo ID VAR INT PUBLICO MODIFICABLE t ciclo insertarPropiedad3 este gt nombre amp este t ciclo min ID VAR INT PUBLICO MODIFICABLE t ciclo min insertarPropiedad3 este gt nombre gt ciclo max ID VAR INT PUBLICO MODIFICABLE t ciclo max principio registro de propiedades espec ficas 12c insertarPropiedad3 este gt nombre amp este bus ok ID SAL INT PUBLICO MODIFICABLE bus ok insertarPropiedad3 este gt nombre amp este gt fd ID 5 INT PUBLICO MODIFICABLE fd fin registro de propiedades espec ficas 12 j 346 gt lt gt lt H lt gt lt o lt 2 2 ol ol k fe o ode k k k k k k k k he k k fe k k k k kk k k k k k k k k k K k k fe K k K K K void funcionCrea EEEE k k k kk k k kk k k k k kkk k kk k k f lt kk K K kK int funcion_crea_12c void instancia char nombre int orden unsigned char habilitado struct 12 este struct i2c instancia ifdef LOG sprintf msgLog Creating s nombre logPrint msgLog 3 endif inicializa_propiedades_i2c instancia nombre orden habilitado if registra propiedades i2c instancia 0 ifdef LOG sprintf msgLog 96s V Registering properties of s ID ERROR este gt nombre logPrint msgLog 1 endif if registrarInstancia instancia nombre amp clase_i2c orden amp este gt habilitado amp este gt finalizado 0 ifdef LOG s
301. p fdummy fin inicializaci n de propiedades espec ficas correcionPI_Acc RR gt lt H lt A gt lt o lt 2 ol o f lt k k k kk k k kK k k K k k K K k void registra_propiedades EEEE k 2 k k k k k k k kk k k kkk k k k k k k k k kk k KK k k f lt k k K K K int registra propiedades correcionPI Acc void instancia struct correcionPI Acc este struct correcionPI Acc instancia char sauX MAX LONG NOMBRE int Z i j insertarNombre2 este gt nombre este emStrcpy saux ID SISTEMA correcionPI Acc MODIFICABLE insertarPropiedad3 este gt nombre amp este gt nombre ID VAR TEXT PUBLICO nombre insertarPropiedad3 este gt nombre amp este gt orden ID VAR INT PUBLICO MODIFICABLE orden insertarPropiedad3 este gt nombre amp este gt habilitado ID VAR BYTE PUBLICO MODIFICABLE habilitado insertarPropiedad3 este gt nombre amp este gt finalizado ID VAR BYTE PUBLICO MODIFICABLE finalizado insertarPropiedad3 este gt nombre gt ciclo RT ID VAR INT PUBLICO MODIFICABLE t ciclo RT insertarPropiedad3 este gt nombre gt ciclo min ID VAR INT PUBLICO MODIFICABLE t ciclo RT min insertarPropiedad3 este gt nombre gt ciclo max ID VAR INT PUBLICO MODIFICABLE t ciclo RT max insertarPropiedad3 este gt nombre amp este t ciclo noRT ID VAR INT PUBLICO MOD
302. pe input dimensions output resending output actualizar matriz1 dcm matriz 1 2 1 output sequence name connection type lt connection gt lt connection gt input renormalizarl dcm matriz 1 2 2 input input resending input type ID ENT FLOAT input type input dimensions output resending output actualizar matriz1 dcm matriz 1 2 2 output sequence name connection type lt connection gt lt connection gt lt input gt renormalizar1 DCM_Matriz 0 0 lt input gt lt input_resending gt lt input_type gt ID_ENT_FLOAT lt input_type gt lt input_dimensions gt lt output_resending gt lt output gt actualizar_matriz1 DCM_Matriz 0 0 lt output gt lt sequence_name gt lt connection_type gt lt connection gt lt connection gt lt input gt renormalizar1 DCM_Matriz 0 1 lt input gt lt input_resending gt lt input_type gt ID_ENT_FLOAT lt input_type gt lt input_dimensions gt lt output_resending gt lt output gt actualizar_matrizl DCM_Matriz 0 1 lt output gt lt sequence_name gt connection type lt connection gt lt connection gt lt input gt renormalizar1 DCM_Matriz 0 2 lt input gt lt input_resending gt lt input_type gt ID_ENT_FLOAT lt input_type gt lt input_dimensions gt lt output_resending gt lt output gt actualizar_matrizl DCM_Matriz 0 2 lt output gt lt sequence_name gt lt connection_typ
303. pec fico funcion finaliza correcionPI Acc este gt Omega_P 3 2 0 este gt Omega_1 3 0 este gt errorRollPitch 3 0 fin c digo espec fico funcion finaliza correcionPI Acc void inicilizacorrecionPI_Acc O int inicializa_correcionPI_Acc ifdef LOG sprintf msgLog Initializing s ID correcionPI Acc logPrint msgLog 3 endif clase correcionPI Acc funcionCrea funcion crea correcionPI Acc clase correcionPI Acc funcionlInicializa funcion inicializa correcionPI Acc clase correcionPI Acc funcionNormal funcion normal correcionPI Acc clase correcionPI Acc funcionNormalNoRT funcion normal noRT correcionPI Acc clase correcionPI Acc funcionFinaliza funcion finaliza correcionPI Acc ifdef ID LISTAS iniciarLista amp instancias correcionPI Acc else clase_correcionPI_Acc n 0 clase_correcionPI_Acc maxNumComp MAX_correcionPI_Acc endif clase_correcionPI_Acc instancias amp instancias correcionPI Acc clase correcionPI Acc longComponente sizeof struct correcionPI Acc return insertarPropiedad2 ID COMPONENTE ID correcionPI Acc amp clase correcionPI Acc ID COMPONENTE NO MODIFICABLE INSTANCIA PROMEDIADORA promediador h promediador h Variables utilizadas en promediador c 11 06 2014 Eugenio Alcal Baselga Hinclude cosme h define ID_promediador promediador define MAX_EJES 3 define MAX PROMEDIO 8 struct promediador char nombre MAX LON
304. piedad3 este n utilizadas en actualizar matriz combre amp este gt ciclo noRT min ID VAR INT PUBLICO MODIFICABLE t ciclo noRT min insertarPropiedad3 este gt nombre amp este 5t ciclo noRT max ID VAR INT PUBLICO MODIFICABLE t ciclo noRT max principio registro de propiedades espec ficas giroscopo insertarPropiedad3 este gt nombre amp este bus ok ID ENT INT PUBLICO IMODIFICABLE bus ok insertarPropiedad3 este gt nombre amp este gt fd ID ENT INT PUBLICO IMODIFICABLE fd for i 0 i lt MAX EJES i insertarPropiedad3 este gt nombre amp este gt W gyr i ID SAL FLOAT PUBLICO MODIFICABLE Weyr d 1 insertarPropiedad3 este gt nombre amp este gt flagg ID VAR INT PUBLICO MODIFICABLE flagg insertarPropiedad3 este gt nombre amp este offsetGyro x ID VAR FLOAT PUBLICO MODIFICABLE Cte calib giro X insertarPropiedad3 este gt nombre amp este offsetGyro y ID VAR FLOAT PUBLICO MODIFICABLE Cte calib giro Y insertarPropiedad3 este gt nombre amp este gt offsetGyro_z ID VAR FLOAT PUBLICO MODIFICABLE Cte calib giro Z insertarPropiedad3 este gt nombre amp este error msg giro ID VAR TEXT PUBLICO MODIFICABLE Msg error giro insertarPropiedad3 este gt nombre amp este gt x ID VAR SHORT PUBLICO MODIFICABLE x insertarPropiedad3 este gt nombre amp este gt y ID VAR SHORT PUBLICO MODIFICABLE y
305. ple 2 LEDn_ON increased and LEDn_OFF decreased Example 3 LEDn_ON made gt LEDn_OFF Example 4 LEDn_OFF 12 set to 1 Fig 10 Update examples when LEDn_ON lt LEDn_OFF gt 511 1023 ET XE ep L 767 4 1023 LL L 1023 4095 0 002aad194 PCA9685 All inform ation provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Product data sheet Rev 3 2 September 2010 18 of 51 Jays Lep 19npoJd 0102 Jequiejdes z ay sieuire osip 12914165 si jueuunoop uoneuuojul 19 JO 61 S896VOd pamuasau siuBu 70102 718 dXN O STOP 0 4095 lt register s updated in this cycle 4095 0 4095 output s updated in this cycle gt 4095 0 example 1 LEDn_ON LEDn_OFF gt 3071 EN 13071 L Jou example 2 LEDn ON LEDn OFF gt 3071 1023 gt 3413 gt 3413 511 example 3 LEDn_ON LEDn_OFF gt 3071 REN 1023 13071 gt 3413 gt 3071 3413 example 4 off LEDn ON LEDn OFF Example 1 LEDn ON unchanged and LEDn OFF decreased but delay still gt LEDn OFF Example 2 LEDn ON changed and LEDn OFF changed but delay still gt LEDn OFF Example 3 LEDn ON unchanged and LEDn OFF increased whe
306. printf msgLog s V Registering instance s ID ERROR este gt nombre logPrint msgLog 1 endif RR gt lt H lt A 2 k 2 k ol o k k k k k k k k k k k k kkk k kk k k k k kk k kK k k k K k K K K void funcionInicializa k f lt k k f lt kk gt e K k void funcion_inicializa_i2c void instancia struct 12 este struct i2c instancia ifdef LOG sprintf msgLog Initializing s este gt nombre logPrint msgLog 3 endif este gt t_ciclo_min 0x10000000 este gt t_ciclo_max 0 este gt bus_ok 0 principio if este gt fd open dev i2c 1 O_RDWR lt 0 ifdef LOG sprintf msgLog s V Failed to open 12c bus ID ERROR logPrint msgLog 1 endif exit 1 fin 46 gt e gt lt ol o al o a os k k k k k k k k k k kkk k kk k k k kkk k kK k k K k k K K k void funcionNormal O void funcion normal i2c void instancia int t ciclo struct 12 este struct i2c instancia ifdef LOG sprintf msgLog Normal function 08 logPrint msgLog 6 endif struct timespec ts crononsec 1 amp ts este gt nombre principio funcion normal 12 fin funcion normal i2c gt ciclo 0 amp ts if este gt t_ciclo gt este gt t_ciclo_max gt ciclo max este gt t_ciclo else if este gt t_ciclo lt este gt t_ciclo_min este
307. propiedades_actualizar_matriz instancia nombre orden habilitado if registra_propiedades_actualizar_matriz instancia 0 ifdef LOG sprintf msgLog s V Registering properties of s ID ERROR este gt nombre logPrint msgLog 1 endif if registrarInstancia instancia nombre amp clase actualizar matriz orden amp este gt habilitado amp este gt finalizado 0 1 ifdef LOG sprintf msgLog 96s V Registering instance s ID ERROR este gt nombre logPrint msgLog 1 endif 2 E 2 o k k k k kk K K k void funcionInicializa II void funcion inicializa actualizar matriz void instancia struct actualizar matriz este struct actualizar matriz instancia ifdef LOG sprintf msgLog Initializing 95 este gt nombre logPrint msgLog 3 endif este gt t_ciclo_RT_min 0x 10000000 este 5t ciclo RT max 0 gt ciclo noRT min 0 10000000 gt ciclo noRT max 0 principio c digo espec fico funcion inicializa actualizar matriz este gt DCM_Matriz 0 0 este gt DCM_Matriz 0 1 este gt DCM_Matriz 0 2 1 0 0 gt este gt DCM_Matriz 1 este DCM Matriz 1 este DCM Matriz 1 este DCM Matriz 2 este DCM Matriz 2 este DCM Matriz 2 Ba N O 0 1 2 0 1 2 este gt dcm_matriz_1 0 0 1 este gt dcm_matriz_1 0 1 0 este gt dc
308. put type ID ENT INT input type input dimensions output resending output i2c fd output sequence name connection type connection connection input magnetometrol bus ok input input resending input type ID ENT INT input type input dimensions output resending lt output gt 12c1 bus_ok lt output gt lt sequence_name gt connection type lt connection gt connection input correcionPI Accl Facc 0 input input resending input type ID ENT FLOAT input type input dimensions output resending output acelerometrol Facc 0 output sequence name connection gt connection connection input correcionPI Accl Facc 1 input input resending input type ID ENT FLOAT input type input dimensions output resending output acelerometrol Facc 1 output sequence name connection type connection connection input correcionPI Accl Facc 2 input input resending input type ID ENT FLOAT input type input dimensions output resending output acelerometrol Facc 2 output sequence name connection type connection connection input correcionPI Acc1 Wgyr 0 input input resending input type ID ENT FLOAT input type input dimensions output resending output giroscopol Wgyr 0
309. r and low power modes of operation of the ADXL345 is shown in Figure 51 Figure 52 shows the typical Allan deviation for the ADXL345 The 1 of the device as shown in this figure is very low allowing absolute resolution of approximately 100 ug assuming that there is sufficient integration time Figure 52 also shows that the noise density is 290 ug VHz for the x axis and y axis and 430 ug VHz for the z axis Figure 53 shows the typical noise performance trend of the ADXL345 over supply voltage The performance is normalized to the tested and specified supply voltage Vs 2 5 V In general noise decreases as supply voltage is increased It should be noted as shown in Figure 51 that the noise on the z axis is typically higher than on the x axis and y axis therefore while they change roughly the same in percentage over supply voltage the magnitude of change on the z axis is greater than the magnitude of change on the x axis and y axis 5 0 45 X AXIS LOW POWER Y AXIS LOW POWER 4 0 77 Z AXIS LOW POWER s X AXIS NORMAL POWER Y AXIS NORMAL POWER 3 5 Z AXIS NORMAL POWER 3 0 2 5 2 0 1 5 OUTPUT NOISE LSB rms 1 0 0 5 0 3 13 6 25 12 50 25 50 100 200 400 800 1600 3200 OUTPUT DATA RATE Hz 07925 250 Figure 51 Noise vs Output Data Rate for Normal and Low Power Modes Full Resolution 256 LSB g
310. r_modif_prom 1 este gt acumula_filtrado_pitch TMM Promediado Roll este gt acumula_filtrado_roll 0 for G 0 i lt MAX PROMEDIO 1 i Movemos solo los 7 primeros este gt vector_filtro_roll i este gt vector_filtro_roll i 1 este gt acumula_filtrado_roll este gt acumula_filtrado_roll este gt vector_filtro_roll i Suma los 8 valores que hay en el filtro este gt vector_filtro_roll MAX_PROMEDIO 1 este gt Wgyr_modif 0 Aniadimos el ULTIMO este gt acumula_filtrado_roll este gt acumula_filtrado_roll este vector filtro roll MAX PROMEDIO 1 este acumula filtrado roll este acumula filtrado MAX PROMEDIO este 2 Wgyr modif prom 0 este acumula filtrado roll este 2Wgyr modif prom 2 este gt W gyr_modif 2 No se promedia el angulo yaw fin codigo especifico funcion normal promediador este 5t ciclo RT 0 amp ts if este 5t ciclo RT gt este t ciclo RT max este 5t ciclo RT max este 5t ciclo RT else if este gt t_ciclo_RT lt este gt t_ciclo_RT_min este gt t_ciclo_RT_min este gt t_ciclo_RT void funcionNormalNoRT O void funcion_normal_noRT_promediador void instancia int t_ciclo 1 struct promediador este struct promediador instancia ifdef LOG sprintf msgLog Normal function 96s este gt nombre logPrint msgLog 6 endif struct timespec
311. racteristics in reflow soldering are Lead free versus SnPb soldering note that a lead free reflow process usually leads to higher minimum peak temperatures see Figure 38 than a SnPb process thus reducing the process window Solder paste printing issues including smearing release and adjusting the process window for a mix of large and small components on one board Reflow temperature profile this profile includes preheat reflow in which the board is heated to the peak temperature and cooling down It is imperative that the peak temperature is high enough for the solder to make reliable solder joints a solder paste characteristic In addition the peak temperature must be low enough that the packages and or boards are not damaged The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 16 and 17 Table 16 SnPb eutectic process from J STD 020C Package thickness mm Package reflow temperature Volume mm lt 350 gt 350 lt 2 5 235 220 gt 2 5 220 220 Table 17 Lead free process from J STD 020C Package thickness mm _ Package reflow temperature C Volume mm 350 350 to 2000 E 2000 1 6 260 260 260 1 6 to 2 5 260 250 245 gt 2 5 250 245 245 Moisture sensitivity precautions as indicated on the packing must be respected at all times Studies have shown that small packages reach higher temperatures
312. rate at the factory default of 15Hz updates a 67 milli second typical delay should be allowed by the master before querying the HMC5883L data registers for new measurements To clock out the new data send Ox3D and clock out DXRA DXRB DZRA DZRB DYRA and DYRB located in registers 3 through 8 The HMC5883L will automatically re point back to register 3 for the next Ox3D query All six data registers must be read properly before new data can be placed in any of these data registers Below is an example of a power on initialization process for continuous measurement mode Write CRA 00 send Ox3C 0x00 0x70 8 average 15 Hz default normal measurement Write CRB 01 send Ox3C 0x01 0 0 Gain 5 or any other desired gain Write Mode 02 send Ox3C 0x02 0x00 Continuous measurement mode Wait 6 ms or monitor status register or DRDY hardware interrupt pin Loop Send 0x3D 0 06 Read all 6 bytes If gain is changed then this data set is using previous gain Convert three 16 bit 275 compliment hex values to decimal values and assign to 2 Y respectively Send 0x3C 0x03 point to first data register 03 Wait about 67 ms if 15 Hz rate or monitor status register or DRDY hardware interrupt pin End_loop Below is an example of a power on initialization process for single measurement mode 1 Write CRA 00 send 0x3C 0 00 0 70 8 average 15 Hz default or any other rate normal measurement
313. re LEDn_ON LEDn OFF Example 4 LEDn_ON 12 1 and LEDn OFF 12 changed from 0 to 1 Fig 11 Update examples when LEDn ON LEDn OFF 002aad195 131 Snq 2z 16 21 Jouueyo 9L S896VOd SIOJONPUODIWIS dXN NXP Semiconductors PCA9685 Table 6 default value 16 channel 12 bit PWM 2 LED controller LED ON LED OFF control registers address 06h to 45h bit description Address Register 06h ON L 07h LEDO ON H 08h LEDO OFF L 09h LEDO OFF H ON L OBh LED1_ON_H OCh LED1_OFF L LED1 OFF H OEh LED2 ON L OFh LED2_ON_H 10h LED2_OFF_L 11h LED2 OFF H 12h LED3 ON L 13h LED3 ON H 14h LED3 OFF L 15h LED3 OFF H 16h LED4 ON L 17h LED4 ON H 9685 Bit 7 0 7 5 4 3 0 7 0 7 5 3 0 7 0 7 5 3 0 7 0 7 5 3 0 7 0 7 5 3 0 7 0 7 5 3 0 7 0 7 5 3 0 7 0 7 5 3 0 7 0 7 5 3 0 Symbol LEDO ON L 7 0 reserved LEDO ON H 4 LEDO ON H 3 0 LEDO OFF 1 7 0 reserved LEDO OFF H 4 LEDO OFF H 3 0 LED1 ON L 7 0 reserved LED1 ON H 4 LED1 ON H 3 0 LED1 OFF 1 7 0 reserved LED1 OFF H 4 LED1 OFF H 3 0 LED2 ON L 7 0 reserved LED2 ON H 4 LED2 ON H 3 0 LED2 OFF 117 0 reserved LED2 OFF H 4 LED2 OFF H 3 0 LED3 ON L 7 0 reserved LED3 H 4 LED3 ON H 3 0 LED3 OFF 1 7 0 reserved LED3 OFF H 4 LED3 OFF H 83 0 LEDA ON L 7 0 reserved LED4 ON H 4 LED4 ON H 3 0
314. read of all registers be performed to prevent a change in data between reads of sequential registers Register 0x38 FIFO CTL Read Write Trigger Bit A value of 0 in the trigger bit links the trigger event of trigger mode to INT1 and a value of 1 links the trigger event to INT2 Samples Bits The function of these bits depends on the FIFO mode selected see Table 23 Entering a value of 0 in the samples bits immediately sets the watermark status bit in the INT SOURCE register regardless of which FIFO mode is selected Undesirable operation may occur if a value of 0 is used for the samples bits when trigger mode is used Table 23 Samples Bits Functions FIFO Mode Samples Bits Function Bypass None FIFO Specifies how many FIFO entries are needed to trigger a watermark interrupt Stream Specifies how many FIFO entries are needed to trigger a watermark interrupt Trigger Specifies how many FIFO samples are retained in the FIFO buffer before a trigger event 0x39 FIFO STATUS Read Only D7 D6 D5 4 D3 D2 D1 DO FIFO_TRIG 0 Entries D7 D6 D5 D4 D3 D2 D1 DO FIFO_MODE Trigger Samples FIFO_MODE Bits These bits set the FIFO mode as described in Table 22 FIFO_TRIG Bit A 1 in the FIFO_TRIG bit corresponds to a trigger event occurring and a 0 means that a FIFO trigger event has not occurred Entries Bits These bits report how many data values are stored
315. registers Register Ox1E Register Ox1F and Register 0x20 These registers contain an 8 bit twos complement value that is automatically added to all measured acceleration values and the result is then placed into the DATA registers Because the value placed in an offset register is additive a negative value is placed into the register to eliminate a positive offset and vice versa for a negative offset The register has a scale factor of 15 6 mg LSB and is independent of the selected g range As an example assume that the ADXL345 is placed into full resolution mode with a sensitivity of typically 256 LSB g The part is oriented such that the z axis is in the field of gravity and x and z axis outputs are measured as 10 LSB 13 LSB and 9 LSB respectively Using the previous equations Xog is 10 LSB Yo is 13 LSB and Zo is 9 LSB Each LSB of output in full resolution is 3 9 mg or one quarter of an LSB of the offset register Because the offset register is additive the 0 g values are negated and rounded to the nearest LSB of the offset register Xorrser Round 10 4 3 LSB Yorrser Round 13 4 3 LSB Zorrser Round 9 4 2 LSB These values are programmed into the OFSX OFSY and OFXZ registers respectively as OXFD 0x03 and OxFE As with all registers in the ADXL345 the offset registers do not retain the value written into them when power is removed from the part Power cycling the ADXL345 returns the offset r
316. rencias else clase_referencias n 0 clase_referencias maxNumComp MAX referencias endif clase_referencias instancias amp instancias_referencias clase_referencias longComponente sizeof struct referencias return insertarPropiedad2 ID_ COMPONENTE ID_referencias amp clase_referencias ID_ COMPONENTE NO_MODIFICABLE INSTANCIA ANGULO PITCH pid_pitch h pid_pitch h Variables utilizadas en pid_pitch c 11 06 2014 Eugenio Alcal Baselga Hinclude cosme h define ID_pid_pitch pid pitch define MAX pid pitch 16 struct pid pitch char nombre MAX LONG NOMBRE int orden byte habilitado byte finalizado int t ciclo RT intt ciclo RT min int t ciclo max int t ciclo noRT int t ciclo noRT min int t ciclo noRT max variables float proportional pitch float integral pitch float derivative pitch float error pitch float variacion error pitch float error oldl pitch float out old pitch float kp pitch float ki pitch float kd pitch entradas float reference pitch float pitch salidas float out pitch pid_pitch c pid_pitch c 11 06 2014 Regulador PID para el angulo pitch Eugenio Alcal Baselga Hinclude lt stdio h gt include lt string h gt include lt math h gt include runtime h include pid_pitch h ifdef ID_LISTAS struct lista instancias_pid_pitch else define MAX_pid_pitch 16 str
317. rent 12C bus addresses can be used Default power up values SUBADR1 register E2h or 1110 001X SUBADR2 register E4h or 1110 010X SUBADRS register E8h or 1110 100X Programmable through I C bus volatile programming e At power up Sub Call I C bus addresses are disabled PCA9685 does not send an ACK when E2h R W 0 or E3h R W 1 E4h R W 0 or E5h R W 1 or E8h R W 0 or E9h R W 1 is sent by the master See Section 7 3 6 SUBADR1 to SUBADR3 I2C bus subaddress 1 to 3 for more detail Remark The default LED Sub Call I2C bus addresses may be used as regular 2 slave addresses as long as they are disabled All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Product data sheet Rev 3 2 September 2010 7 of 51 Semiconductors 9685 16 channel 12 bit PWM 2 LED controller 7 1 4 Software Reset I2C bus address PCA9685 7 2 The address shown in Figure 5 is used when a reset of the PCA9685 needs to be performed by the master The Software Reset address SWRST Call must be used with R W logic 0 If R W logic 1 the PCA9685 does not acknowledge the SWRST See Section 7 6 Software reset for more detail R W y 002aab416 Fig 5 Software Reset address Remark The Software Reset 2 address is a reserved address and cannot be used as a
318. rite LED10 output and brightness control byte 2 49 31 0 0 1 1 0 0 0 1 LED10 OFFH read write LED10 output and brightness control byte 3 50 32 0 0 1 1 0 0 1 0 ONL read write LED11 output and brightness control byte 0 51 33 0 0 1 1 0 1 1 1 011 ON H read write LED11 output and brightness control byte 1 52 34 0 0 1 1 0 4 0 0 LED1I1_OFF_L read write LED11 output and brightness control byte 2 53 35 0 0 1 1 O 1 0 1 LED11 OFF H read write LED11 output and brightness control byte 3 54 36 0 0 1 1 O 1 1 O LED12 ON L read write LED12 output and brightness control byte 0 55 37 0 0 1 1 0 1 1 1 LED12 ON H read write LED12 output and brightness control byte 1 56 38 0 0 1 1 1 0 0 0 LED1 2 OFFL read write LED12 output and brightness control byte 2 57 39 0 0 1 1 1 0 0 1 LED12 OFF H read write LED12 output and brightness control byte 3 58 3A 0 0 1 1 1 0 1 0 LEDISONL read write LED13 output and brightness control byte 0 59 3B 0 0 1 1 1 0 1 1 1 013 ON H read write LED13 output and brightness control byte 1 60 3C 0 0 1 1 1 1 0 0 LED13 OFF L read write LED13 output and brightness control byte 2 61 3D 0 0 1 1 1 1 0 1 LED13 OFF H read write LED13 output and brightness control byte 3 PCA9685 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Product data sheet Rev 3 2 September 2010 11 of 51 NXP Semiconductors PCA9685 Table 3 16 channel 12 bit PWM 2
319. riz fin c digo espec fico funcion normal noRT actualizar matriz este t ciclo noRT 0 amp ts if este 5t ciclo noRT gt gt ciclo noRT max este gt t_ciclo_noRT_max este gt t_ciclo_noRT else if este gt t_ciclo_noRT lt este gt t_ciclo_noRT_min este gt t_ciclo_noRT_min este gt t_ciclo_noRT HR gt lt gt lt a A gt lt 2 2 2 o o o o k k k k K void funcionFinaliza O void funcion_finaliza_actualizar_matriz void instancia struct actualizar_matriz este struct actualizar_matriz instancia ifdef LOG sprintf msgLog Finalizing s este gt nombre logPrint msgLog 3 endif principio c digo espec fico funcion finaliza actualizar_matriz fin c digo espec fico funcion finaliza actualizar_matriz 46 gt lt gt lt H lt gt lt o lt 2 ope ole 2 k os k k k k k k k k k k kkk k kk k k k k k k k k kK k k K k k K K K void inicilizaactualizar matriz E E E k gt lt 2 2 k k 2 k k k k k kk k k k k kk k k k kk k kk k k f lt k k gt lt K K int inicializa_actualizar_matriz ifdef LOG sprintf msgLog Initializing s ID_actualizar_matriz logPrint msgLog 3 endif clase_actualizar_matriz funcionCrea funcion_crea_actualizar_matriz clase actualizar matriz funcionInicializa funcion inicializa actualizar matriz clase actualizar matriz funcionNo
320. rmal funcion normal actualizar matriz clase actualizar matriz funcionNormalNoRT funcion normal noRT actualizar matriz clase actualizar matriz funcionFinaliza funcion finaliza actualizar matriz ifdef ID LISTAS iniciarLista amp instancias actualizar matriz else clase_actualizar_matriz n 0 clase_actualizar_matriz maxNumComp MAX actualizar matriz endif clase_actualizar_matriz instancias amp instancias_actualizar_matriz clase_actualizar_matriz longComponente sizeof struct actualizar_matriz return insertarPropiedad2 ID_ COMPONENTE ID_actualizar_matriz amp clase actualizar matriz ID COMPONENTE NO MODIFICABLE INSTANCIA DE RENORMALIZACI N renormalizar h renormalizar h Variables utilizadas en renormalizar c 11 06 2014 Eugenio Alcal Baselga Hinclude cosme h Hdefine ID_renormalizar renormalizar Hdefine MAX_renormalizar 16 Hdefine MAX EJES 3 struct renormalizar char nombre MAX LONG NOMBRE int orden byte habilitado byte finalizado int t ciclo RT int t ciclo RT min int t ciclo max int t ciclo noRT int t ciclo noRT min int t ciclo noRT max variables float error float renorm entradas float matriz IIMAX EJES MAX EJES float DCM MatrizIMAX EJES MAX EJES salidas float dcm matriz renorn MAX EJES MAX EJES float dcm matriz renorm EJES MAX EJES renormalizar c renormalizar c 11 06 2014 Co
321. rom Register 0x37 to Register 0x38 or by the CS pin going high For SPI operation at 1 6 MHz or less the register addressing portion of the transmission is a sufficient delay to ensure that the FIFO has completely popped For SPI operation greater than 1 6 MHz it is necessary to deassert the CS pin to ensure a total delay of 5 us otherwise the delay is not sufficient The total delay necessary for 5 MHz operation is at most 3 4 us This is not a concern when using mode because the communication rate is low enough to ensure a sufficient delay between FIFO reads Rev D Page 21 of 40 ADXL345 SELF TEST The ADXL345 incorporates a self test feature that effectively tests its mechanical and electronic systems simultaneously When the self test function is enabled via the SELF TEST bit in the DATA FORMAT register Address 0x31 an electrostatic force is exerted on the mechanical sensor This electrostatic force moves the mechanical sensing element in the same manner as acceleration and it is additive to the acceleration experienced by the device This added electrostatic force results in an output change in the x y and z axes Because the electrostatic force is proportional to Vs the output change varies with Vs This effect is shown in Figure 43 The scale factors shown in Table 14 can be used to adjust the expected self test output limits for different supply voltages Vs The self test feature of the ADXL345 also exhibits
322. rrige la desviaci n producida por las aproximaciones Eugenio Alcal Baselga Hinclude lt stdio h gt include lt string h gt include lt math h gt include runtime h include renormalizar h ifdef ID LISTAS struct lista instancias renormalizar else define MAX_renormalizar 16 struct renormalizar instancias_renormalizar MAX_renormalizar endif struct componente clase_renormalizar extern char msgLog extern float fdummy HR AR gt lt A void inicializa_propiedades IO void inicializa propiedades renormalizar void instancia char nombre int orden unsigned char habilitado struct renormalizar este struct renormalizar instancia strcpy este gt nombre nombre este gt orden orden este gt habilitado habilitado este gt finalizado 0 principio inicializaci n de propiedades espec ficas renormalizar este gt DCM_Matriz 0 0 amp fdummy este gt DCM_Matriz 0 1 amp fdummy este gt DCM_Matriz 0 2 amp fdummy este gt DCM_Matriz 1 0 amp fdummy este gt DCM_Matriz 1 1 amp fdummy este gt DCM_Matriz 1 2 amp fdummy este gt DCM_Matriz 2 0 amp fdummy este gt DCM_Matriz 2 1 amp fdummy este gt DCM_Matriz 2 2 amp fdummy este gt dcm_matriz_1 0 este gt dcm_matriz_1 0 este gt dcm_matriz_1 0 2 amp fdummy este dcm matriz 1 l amp fdummy 0 2 amp fdummy 121 110 este
323. ruct magnetometro instancia ftifdef LOG sprintf msgLog Finalizing s este gt nombre logPrint msgLog 3 endif principio c digo espec fico funcion finaliza magnetometro este gt offsetRoll este gt offsetPitch este gt offsetY aw 0 0 este gt x este gt y este z 0 fin c digo espec fico funcion finaliza magnetometro 346 gt lt gt lt k k k k k kk k kK k k k k k K K k void inicilizamagnetometro k k K k k gt lt K K int inicializa_magnetometro ifdef LOG sprintf msgLog Initializing s ID magnetometro logPrint msgLog 3 endif clase_magnetometro funcionCrea funcion_crea_magnetometro clase_magnetometro funcionInicializa funcion_inicializa_magnetometro clase_magnetometro funcionNormal funcion_normal_magnetometro clase_magnetometro funcionNormalNoRT funcion_normal_noRT_magnetometro clase_magnetometro funcionFinaliza funcion_finaliza_magnetometro ifdef ID_LISTAS iniciarLista amp instancias_magnetometro else clase_magnetometro n 0 clase_magnetometro maxNumComp MAX_magnetometro endif clase_magnetometro instancias amp instancias_magnetometro clase_magnetometro longComponente sizeof struct magnetometro return insertarPropiedad2 ID_ COMPONENTE ID_magnetometro amp clase magnetometro ID COMPONENTE NO MODIFICABLE j CORRECCION DERIVA CON ACELEROMETRO correcionPI_Acc h
324. s Per Carton max 3 full pizza boxes packed in the center of the carton buffered by two empty pizza boxes front and back Pcs Carton max 15 000 32 of 39 7 InvenSense ITG 3200 Product Specification A Document Number PS ITG 3200A 00 01 4 Revision 1 4 Release Date 03 30 2010 9 5 Label InvenSense DEVICE 176 3200 P O REEL QTY 0 5000 LOT 1 1T 123456 A D C D 1234 QTY Q 5000 AA LT LOT 2 1T DC D QTY 0 TUI Reel Date 13 10 09 QC STAMP 9 6 Packaging Anti static Label Moisture Sensitive Caution Label 7 S CEN gt Tape amp Reel Label y NAV PS y eem Moisture Barrier Bag With Labels Reel in Box Box with Tape amp Reel Label Location of Label as Caution This bag contains MOISTURE SENSITIVE DEVICES wee adacent er code tal 1 Calculated shelf life in sealed bag 12 months at lt 40 C and lt 90 relative humidity RH 2 Peak package body temperature code 3 After bag is opened devices that will be subjected to reflow solder or other high temperature process must Mounted within hours of factory conditions esr spa reo abel lt 30 C 60 RH OR b Stored at lt 10 RH 4 Devices require bake before mounting if Humidity Indicator Card is gt 10 when read at 23 5 C b 3a or 3b not met 5 If baking
325. s accessible through the bus but major sources of power consumption are disabled Such as but not limited to the ADC the amplifier and the sensor bias current All registers maintain values while in idle mode The bus is enabled for use by other devices on the network while in idle mode 10 www honeywell com HMC5883L REGISTERS This device is controlled and configured via a number of on chip registers which are described in this section In the following descriptions set implies a logic 1 and reset or clear implies a logic 0 unless stated otherwise Register List The table below lists the registers and their access All address locations are 8 bits Address Location Name Access 00 Configuration Register A Read Write 01 Configuration Register B Read Write 02 Mode Register Read Write 03 Data Output X MSB Register Read 04 Data Output X LSB Register Read 05 Data Output Z MSB Register Read 06 Data Output Z LSB Register Read 07 Data Output Y MSB Register Read 08 Data Output Y LSB Register Read 09 Status Register Read 10 Identification Register A Read 11 Identification Register B Read 12 Identification Register C Read Table2 Register List Register Access This section describes the process of reading from and writing to this device The devices uses an address pointer to indicate which register location is to be read from or written to These pointer lo
326. s and conditions of commercial sale as published at http www nxp com profile terms unless otherwise agreed in a valid written individual agreement In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply NXP Semiconductors hereby expressly objects to applying the customer s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant conveyance or implication of any license under any copyrights patents or other industrial or intellectual property rights Export control This document as well as the item s described herein may be subject to export control regulations Export might require a prior authorization from national authorities NXP B V 2010 All rights reserved Product data sheet Rev 3 2 September 2010 49 of 51 NXP Semiconductors PCA9685 Non automotive qualified products Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified the product is not suitable for automotive use lt is neither qualified nor tested in accordance with automotive testing or application requirements NXP Semiconductors accepts no liability for inclusion and or use of non automotive qualified products in automoti
327. samples of data after the link bit is cleared may have additional noise especially if the device was asleep when the bit was cleared AUTO SLEEP Bit If the link bit is set a setting of 1 in the AUTO SLEEP bit enables the auto sleep functionality In this mode the ADXL345 auto matically switches to sleep mode if the inactivity function is enabled and inactivity is detected that is when acceleration is below the THRESH INACT value for at least the time indicated by TIME If activity is also enabled the ADXL345 automatically wakes up from sleep after detecting activity and returns to operation at the output data rate set in the BW RATE register A setting of 0 in the AUTO SLEEP bit disables automatic switching to sleep mode See the description of the Sleep Bit in this section for more information on sleep mode Rev D Page 25 of 40 ADXL345 If the link bit is not set the AUTO SLEEP feature is disabled and setting the AUTO SLEEP bit does not have an impact on device operation Refer to the Link Bit section or the Link Mode section for more information on utilization of the link feature When clearing the AUTO SLEEP bit it is recommended that the part be placed into standby mode and then set back to measure ment mode with a subsequent write This is done to ensure that the device is properly biased if sleep mode is manually disabled otherwise the first few samples of data after the AUTO SLEEP bit is cleared
328. sending gt output promediadorl Wgyr modif prom 0 output sequence name connection type connection connection input correccionPI Magl Wgyr modif prom 1 input input resending input type ID ENT FLOAT input type input dimensions output resending output promediadorl Wgyr modif prom l1 output sequence name connection type connection connection input correccionPI Magl Wgyr modif prom 2 input input resending input type ID ENT FLOAT input type input dimensions output resending output promediadorl Wgyr modif prom 2 output sequence name connection type connection connection lt input gt actualizar_matriz1 Wgyr_fin 0 lt input gt lt input_resending gt lt input_type gt ID_ENT_FLOAT lt input_type gt lt input_dimensions gt lt output_resending gt lt output gt correccionPI_Mag1 Wegyr_fin 0 lt output gt lt sequence_name gt lt connection_type gt lt connection gt lt connection gt lt input gt actualizar_matriz1 Wgyr_fin 1 lt input gt lt input_resending gt lt input_type gt ID_ENT_FLOAT lt input_type gt lt input_dimensions gt lt output_resending gt output correccionPI Magl Wgyr fin 1 output sequence name connection type connection connection input actualizar matriz Wgyr fin 2 input input resending
329. sertarPropiedad3 este gt nombre amp gt ciclo max ID VAR INT PUBLICO MODIFICABLE t ciclo max insertarPropiedad3 este gt nombre gt ciclo noRT ID VAR INT PUBLICO MODIFICABLE t ciclo noRT insertarPropiedad3 este gt nombre amp este t ciclo min ID VAR INT PUBLICO MODIFICABLE t ciclo noRT min insertarPropiedad3 este gt nombre amp este 5t ciclo noRT max ID VAR INT PUBLICO MODIFICABLE t ciclo max principio registro de propiedades espec ficas cambio magnitud insertarPropiedad3 este gt nombre amp este out pitch ID ENT FLOAT PUBLICO MODIFICABLE out pitch insertarPropiedad3 este gt nombre amp este out roll ID ENT FLOAT PUBLICO MODIFICABLE out roll insertarPropiedad3 este gt nombre amp este pwm motor grisl ID SAL INT PUBLICO MODIFICABLE pwm motor gris1 insertarPropiedad3 este gt nombre amp este pwm motor gris2 ID SAL INT PUBLICO MODIFICABLE pwm motor gris2 insertarPropiedad3 este gt nombre amp este pwm motor negrol ID SAL INT PUBLICO MODIFICABLE pwm motor negrol insertarPropiedad3 este gt nombre amp este pwm motor negro2 ID SAL INT PUBLICO MODIFICA BLE pwm motor negro2 insertarPropiedad3 este gt nombre amp este gt potencia ID VAR INT PUBLICO MODIFICABLE potencia fin registro de propiedades espec ficas cambio magnitud j
330. seseseseseseseseveseseseseceseseseseseseseseseseseseseseseseseseveseseseresereseseseresesesesesesesesenenens 30 9 3 PACKAGE MARKING SPECIFICATION 0 r r rer EEE EEE 31 9 4 TAPE 4 REEL SPECIFICATION i 2 64 1i cao eon ciet ean bas eso nea se e soo voe dana ao Tene e suse e Sese dee 31 Document Number PS ITG 3200A 00 01 4 InvenSense ITG 3200 Product Specification Revision 1 4 S Release Date 03 30 2010 9 7 SOLDERING EXPOSED DIE PAD s 220222222222 roe tno reae too Pena nee L on rena els owns TE 34 9 8 van tone dan 34 9 9 PCB MOUNTING AND CROSS AXIS SENSITIVITY eese nennen n nene enne rne nn e eere rne n ree 34 9 10 MEMS HANDLING INSTRUCTIONS eene nn 001000006 a a p p 35 9 11 GYROSCOPE SURFACE MOUNT GUIDELINES eeeeee enne en nennen nnn nnn nnn nnne n anu 35 9 12 dados 35 0 13 STORAGE SPECIFICATIONS HERE 37 10 YA 38 10 1 QUALIFICATION TEST POLICY 2 22 000000000000 en nnne nete ns sene tr sienne ese se nnns
331. sgLog 6 endif struct timespec ts crononsec 1 amp ts int 1 principio c digo espec fico funcion normal correcionPI Acc if t ciclo rt gt t ciclo 1e6 0 95 amp amp t ciclo rt t ciclo 1e6 1 05 Se filtran los ciclos que no interesan Calculo del error t ciclo en nanosegundos este gt errorRollPitch 0 este gt Facc 1 este 2dcm matriz renorm 1 2 2 este gt Facc 2 este dcm matriz renorm 1 2 1 este gt errorRollPitch 1 este gt Facc 2 este 2 dcm matriz renorm 1 2 0 este gt Facc 0 este dcm matriz renorm 1 2 2 este gt errorRollPitch 2 este gt Facc 0 este 2 dcm matriz renorm 1 2 1 este gt Facc 1 este dcm matriz renorm 1 2 0 for 120 1 lt 3 1 este Omega Pli este gt errorRollPitch i este gt Kp_ROLLPITCH for 120 1 lt 3 1 este Omega I i este gt Omega_I 1 este gt errorRollPitch 1 float t ciclo rt 1e9 for 120 1 lt 3 1 este gt derivative i este gt errorRollPitch i este gt errorRollPitch_old i float t ciclo rt 1e9 for 120 1 lt 3 1 este gt W gyr_modif i este 2Wgyr i este gt Omega_P i este gt Ki_ROLLPITCH este gt Omega_I 1 este Kd ROLLPITCH este derivative i for 120 1 lt 3 1 este errorRollPitch old i este gt errorRollPitch 1 fin c digo espec fico funcion normal correcionPI Acc este gt t
332. sible Remark Set INVRT 0 OUTDRV 1 OUTNE 01 register bits 1 Resistor value should be chosen by referencing section 7 of UM10204 specification and user manual 2 OE requires pull up resistor if control signal from the master is open drain Fig 26 Typical application 9685 All information provided this document is subject to legal disclaimers NXP B V 2010 All rights reserved Product data sheet Rev 3 2 September 2010 34 of 51 Semiconductors 9685 16 channel 12 bit PWM 2 LED controller Question 1 What kind of edge rate control is there on the outputs The typical edge rates depend on the output configuration supply voltage and the applied load The outputs can be configured as either open drain NMOS or totem pole outputs If the customer is using the part to directly drive LEDs they should be using it in an open drain NMOS if they are concerned about the maximum Iss and ground bounce The edge rate control was designed primarily to slow down the turn on of the output device it turns off rather quickly 71 5 ns In simulation the typical turn on time for the open drain NMOS was 14 ns Vpp 3 6 V C 50 pF 500 Question 2 15 ground bounce possible Ground bounce is a possibility especially if all 16 outputs are changed at full current 25 mA each There is a fair amount of decoupling capacitance on ch
333. solder for package thicknesses less than 1 6 mm The reliability qualification pre conditioning used by InvenSense incorporates three of these conforming reflow cycles temperatures refer to the topside of the QFN package as measured on the package body surface Customer solder reflow processes should use the solder manufacturer s recommendations making sure to never exceed the constraints listed in the table and figure below as these represent the maximum tolerable ratings for the device For optimum results production solder reflow processes should use lower temperatures reduced exposure times to high temperatures and lower ramp up and ramp down rates than those listed below 35 of 39 Document Number PS ITG 3200A 00 01 4 Release Date 03 30 2010 y InvenSense ITG 3200 Product Specification Revision 1 4 a Temperature C LEAD FREE IR CONVECTION REFLOW PROFILE TPmax Temin iguidus T smax Liquidus 60 1205 T smin Tramp up Tramp down Preheat lt 3 C sec lt 4 C sec 60 120sec Troom Pmax lt 4805 Time Seconds Approved IR Convection Solder Reflow Curve Temperature Set Points for IR Convection Reflow Corresponding to Figure Above CONSTRAINTS Toa 25 Tsmax 60 tgc 120 Triquidus T TLiquidus TPmax lt 3 Tpmin lt TPmax 5 C 250 C I TLiquidus TPmax 3 Tpmax tap lt 480 T TLiquidus TPmax lt 3 lt 260
334. ssociated status bit will not get set In normal use the RAW_DATA_RDY interrupt is used to determine when new sensor data is available in either the sensor registers 27 to 32 Interrupt Status bits get cleared as determined by INT_ANYRD_2CLEAR in the interrupt configuration register 23 Parameters ITG_RDY PLL ready RAW DATA RDY Raw data is ready 26 of 39 8 6 8 7 Document Number PS ITG 3200A 00 01 4 e Z T Revision 1 4 InvenSense ITG 3200 Product Specification RD 09 30 2010 Registers 27 to 34 Sensor Registers Type Read only SS Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bitl Decimal 27 TEMP OUT H 28 TEMP OUT L 1D 29 GYRO_XOUT_H IE 30 GYRO XOUT L IF 31 GYRO YOUT H 20 32 GYRO YOUT L 21 33 GYRO ZOUT H 22 34 GYRO ZOUT L Description These registers contain the gyro and temperature sensor data for the ITG 3200 parts At any time these values can be read from the device however it is best to use the interrupt function to determine when new data is available Parameters TEMP OUT H L 16 bit temperature data 2 s complement format GYRO XOUT H L 16 bit X gyro output data 2 s complement format GYRO YOUT H L 16 bit Y gyro output data 2 s complement format GYRO ZOUT H L 16 bit Y gyro output data 2 s complement format Register 62 Power Management Type Read Write Register Register x Defaul
335. stancia struct magnetometro este struct magnetometro instancia char saux MAX_LONG_NOMBRE int 7 insertarNombre2 este gt nombre este emStrcpy saux ID SISTEMA ID magnetometro NO MODIFICABLEB insertarPropiedad3 este gt nombre amp este gt nombre ID VAR TEXT PUBLICO nombre insertarPropiedad3 este gt nombre amp este gt orden ID VAR INT PUBLICO MODIFICABLE orden insertarPropiedad3 este gt nombre amp este gt habilitado ID VAR BYTE PUBLICO MODIFICABLE habilitado insertarPropiedad3 este gt nombre amp este gt finalizado ID VAR BYTE PUBLICO MODIFICABLE finalizado insertarPropiedad3 este gt nombre amp este gt t_ciclo_RT ID_VAR_INT PUBLICO MODIFICABLE t_ciclo_RT insertarPropiedad3 este gt nombre amp este gt t_ciclo_RT_min ID_VAR_INT PUBLICO MODIFICABLE t_ciclo_RT_min insertarPropiedad3 este gt nombre amp este gt t_ciclo_RT_max ID_VAR_INT PUBLICO MODIFICABLE t ciclo RT max insertarPropiedad3 este gt nombre gt ciclo noRT ID VAR INT PUBLICO MODIFICABLE t ciclo noRT insertarPropiedad3 este gt nombre amp este t ciclo noRT min ID VAR INT PUBLICO MODIFICABLE t ciclo noRT min insertarPropiedad3 este gt nombre amp este 5t ciclo noRT max ID VAR INT PUBLICO MODIFICABLE t ciclo noRT max principio registro de propiedades espec ficas magnetometro insertarPropiedad3 este gt nombre am
336. ste gt bus_ok amp dummy strcpy este gt error_msg_giro no error fin inicializaci n de propiedades espec ficas giroscopo lol ol o f lt o oe gt lt k k k ls ls ls ds ls ls ls ls le le k kk k k k kk k k kK k k k k K void registra_propiedades IO int registra propiedades giroscopo void instancia struct giroscopo este struct giroscopo instancia char sauX MAX LONG NOMBRE int 1 insertarNombre2 este gt nombre este emStrcpy saux ID SISTEMA ID giroscopo NO MODIFICABLE insertarPropiedad3 este gt nombre amp este gt nombre ID VAR TEXT PUBLICO nombre insertarPropiedad3 este gt nombre amp este gt orden ID VAR INT PUBLICO MODIFICABLE orden insertarPropiedad3 este gt nombre amp este gt habilitado ID VAR BYTE PUBLICO MODIFICABLE habilitado insertarPropiedad3 este gt nombre amp este gt finalizado ID VAR BYTE PUBLICO MODIFICABLE finalizado insertarPropiedad3 este gt nombre gt ciclo RT ID VAR INT PUBLICO MODIFICABLE t ciclo RT insertarPropiedad3 este gt nombre gt ciclo min ID VAR INT PUBLICO MODIFICABLE t ciclo RT min insertarPropiedad3 este gt nombre gt ciclo max ID VAR INT PUBLICO MODIFICABLE t ciclo RT max insertarPropiedad3 este gt nombre amp este t ciclo noRT ID VAR INT PUBLICO MODIFICABLE t ciclo noRT insertarPro
337. ste gt nombre ID VAR TEXT PUBLICO nombre insertarPropiedad3 este gt nombre amp este gt orden ID VAR INT PUBLICO MODIFICABLE orden insertarPropiedad3 este gt nombre amp este gt habilitado ID VAR BYTE PUBLICO MODIFICABLE habilitado insertarPropiedad3 este gt nombre amp este gt finalizado ID VAR BYTE PUBLICO MODIFICABLE finalizado insertarPropiedad3 este gt nombre gt ciclo RT ID VAR INT PUBLICO MODIFICABLE t ciclo RT insertarPropiedad3 este gt nombre gt ciclo min ID VAR INT PUBLICO MODIFICABLE t ciclo min insertarPropiedad3 este gt nombre gt ciclo max ID VAR INT PUBLICO MODIFICABLE t ciclo RT max insertarPropiedad3 este gt nombre amp este t ciclo noRT ID VAR INT PUBLICO MODIFICABLE t ciclo noRT insertarPropiedad3 este gt nombre amp este t ciclo noRT min ID VAR INT PUBLICO MODIFICABLE t ciclo noRT min insertarPropiedad3 este gt nombre amp este 5t ciclo noRT max ID VAR INT PUBLICO MODIFICABLE t ciclo noRT max principio registro de propiedades espec ficas referencias insertarPropiedad3 este gt nombre amp este reference pitch ID SAL FLOAT PUBLICO MODIFICABLE reference pitch insertarPropiedad3 este gt nombre amp este reference roll ID SAL FLOAT PUBLICO MODIFICABLE reference roll fin registro de propiedades espec fi
338. t Hex Decimal Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bitl Bit0 Value STBY STBY STBY 3E 62 H RESET SLEEP CLK_SEL 00h Description This register is used to manage the power control select the clock source and to issue a master reset to the device Setting the SLEEP bit in the register puts the device into very low power sleep mode In this mode only the serial interface and internal registers remain active allowing for a very low standby current Clearing this bit puts the device back into normal mode To save power the individual standby selections for each of the gyros should be used if any gyro axis is not used by the application The CLK_SEL setting determines the device clock source as follows CLK_SEL SEL Clock Source 0 Internal oscillator PLL with X Gyro reference PLL with Y Gyro reference PLL with Z Gyro reference PLL with external 32 768kHz reference PLL with external 19 2MHz reference Reserved Reserved aja J BR Lo rope On power up the ITG 3200 defaults to the internal oscillator It is highly recommended that the device is configured to use one of the gyros or an external clock as the clock reference due to the improved stability 27 of 39 Document Number PS ITG 3200A 00 01 4 yg Z Revision 1 4 InvenSense ITG 3200 Product Specification sr te Parameters H_RESET Reset device and internal registers t
339. t fd Config Reg B 0x20 instancia Modo de medicion continua writeto_mag este gt fd Mode Reg 0x00 instancia fin c digo espec fico funcion inicializa magnetometro k k K K k K K K void funcionNormal O void funcion_normal_magnetometro void instancia int t ciclo struct magnetometro este struct magnetometro instancia ifdef LOG sprintf msgLog Normal function 96s este gt nombre logPrint msgLog 6 endif struct timespec ts crononsec 1 amp ts principio c digo espec fico funcion normal magnetometro if ioctl este gt fd 2 SLAVE HMC5883L_I2C_ADDR strcpy este gt error_msg_mag Magnetometro NO presente n este gt buf 0 0x03 del primer registro de datos if write este gt fd este gt buf 1 1 strcpy este gt error_msg_mag Error escribiendo en el magnetometro n if read este gt fd este gt buf 6 6 strcpy este gt error_msg_mag No disponible para leer n este gt x este gt buf 0 lt lt 8 este gt buf 1 este gt y este gt buf 4 lt lt 8 este gt buf 5 este gt z este gt buf 2 lt lt 8 este gt buf 3 este gt Vmag 0 float este gt x 0 9229 este gt Vmag 1 float este gt y 0 9229 este gt Vmag 2 float este gt z 0 8593 este gt Vmag 0 1 0 este gt Vmag 0 hmc5883 calib x este gt Vmagl 1 1 07 est
340. t t_ciclo_noRT_max este gt t_ciclo_noRT_max este gt t_ciclo_noRT else if este gt t_ciclo_noRT lt este gt t_ciclo_noRT_min este gt t_ciclo_noRT_min este gt t_ciclo_noRT k k k k k gt e K k void funcionFinaliza k f lt k k k kkk k k k k k k k k kk k kk k k K k k KK K void funcion_finaliza_referencias void instancia struct referencias struct referencias instancia ifdef LOG sprintf msgLog Finalizing 96s este gt nombre logPrint msgLog 3 endif principio c digo espec fico funcion finaliza referencias fin c digo espec fico funcion finaliza referencias j HR gt lt gt lt A A 2 ol k o lt k k k k k k k k k he fe k k k k k k k k k gt lt o lt k K K k k fe k k gt lt K K void inicilizareferencias gt lt 2 2 2 k k k k k k k k k k k k kk k k k k k kk k kk k k f lt k k K K k int inicializa_referencias ifdef LOG sprintf msgLog Initializing s ID referencias logPrint msgLog 3 endif clase_referencias funcionCrea funcion_crea_referencias clase_referencias funcionInicializa funcion_inicializa_referencias clase_referencias funcionNormal funcion_normal_referencias clase_referencias funcionNormalNoRT funcion_normal_noRT_referencias clase_referencias funcionFinaliza funcion_finaliza_referencias ifdef ID_LISTAS iniciarLista amp instancias_refe
341. ta stream Register values ASCII value 4 IRB7 IRB6 IRB5 IRB4 IRB3 IRB2 IRB1 IRBO 0 0 1 1 0 1 0 0 Table 19 Identification Register B Default Values Identification Register C The identification register C is used to identify the device IRCO through IRC7 indicate bit locations with RC denoting the bits that are in the identification register A IRC7 denotes the first bit of the data stream Register values ASCII value 3 IRC7 IRC6 IRC5 IRC4 IRC3 IRC2 IRC1 IRCO 0 0 1 1 0 0 1 1 Table 20 Identification Register C Default Values 2 COMMUNICATION PROTOCOL The HMC5883L communicates via a two wire bus system as a slave device The HMC5883L uses a simple protocol with the interface protocol defined by the C bus specification and by this document The data rate is at the standard mode 100kbps or 400kbps rates as defined in the lC Bus Specifications The bus bit format is an 8 bit Data Address send and a 1 bit acknowledge bit The format of the data bytes payload shall be case sensitive ASCII characters or binary data to the HMC5883L slave and binary data returned Negative binary values will be in two s complement form The default factory HMC5883L 8 bit slave address is 0x3C for write operations or 0x3D for read operations The HMC5883L Serial Clock SCL and Serial Data SDA lines require resistive pull ups Rp between the master device usual
342. te gt dcm_matriz_renorm_1 0 1 amp fdummy este gt dcm_matriz_renorm_1 0 2 amp fdummy este gt dcm_matriz_renorm_1 1 0 amp fdummy este gt dcm_matriz_renorm_1 1 1 amp fdummy este gt dcm_matriz_renorm_1 1 2 amp fdummy este gt dcm_matriz_renorm_1 2 0 amp fdummy este gt dcm_matriz_renorm_1 2 1 amp fdummy este gt dcm_matriz_renorm_1 2 2 amp fdummy este gt W gyr_fin 0 amp fdummy este gt W gyr_fin 1 amp fdummy este gt W gyr_fin 2 amp fdummy este gt calibracion_giro amp dummy fin inicializaci n de propiedades espec ficas actualizar_matriz 78 gt lt gt lt k k k k kkk k kK k k k k k K K k void registra_propiedades II int registra_propiedades_actualizar_matriz void instancia struct actualizar_matriz este struct actualizar_matriz instancia char saux MAX_LONG_NOMBRE int i j insertarNombre2 este gt nombre este emStrcpy saux ID SISTEMA ID actualizar matriz MODIFICABLE insertarPropiedad3 este gt nombre amp este gt nombre ID VAR TEXT PUBLICO nombre insertarPropiedad3 este gt nombre amp este gt orden ID VAR INT PUBLICO MODIFICABLE orden insertarPropiedad3 este gt nombre amp este gt habilitado ID VAR BYTE PUBLICO MODIFICABLE habilitado insertarPropiedad3 este gt nombre amp este gt finalizado ID VAR BYTE PUBLICO MODIFICABLE finalizado insertarPr
343. tellite Standalone 17 RoHS Compliant Part Rev Page 37 of 40 ADXL345 NOTES Rev D Page 38 of 40 ADXL345 NOTES Rev Page 39 of 40 ADXL345 NOTES PC refers to a communications protocol originally developed by Philips Semiconductors now NXP Semiconductors Analog Devices offers specific products designated for automotive applications please consult your local Analog Devices sales representative for details Standard products sold by Analog Devices are not designed intended or approved for use in life support implantable medical devices transportation nuclear safety or other equipment where malfunction of the product can reasonably be expected to result in personal injury death severe property damage or severe environmental harm Buyer uses or sells standard products for use in the above critical applications at Buyer s own risk and Buyer agrees to defend indemnify and hold harmless Analog Devices from any and all damages claims suits or expenses resulting from such unintended use 2009 2013 Analog Devices Inc All rights reserved Trademarks and AN ALOG registered trademarks are the property of their respective owners D07925 0 2 13 D DEVICES www analo g com Rev D Page 40 of 40 2 InvenSense Inc InvenSense 1197 Borregas Ave Sunnyvale CA 94089 U S A Document Number PS ITG 3200A 00 01 4 Tel 1 408 988 7339 Fax 1 408 988 8104 Revision 1 4 Website www invensense com
344. ter OxX2C BW RATE Read Write D7 D6 D5 D4 D2 D1 DO 0 0 0 LOW_POWER Rate LOW_POWER Bit A setting of 0 in the LOW POWER bit selects normal operation and a setting of 1 selects reduced power operation which has somewhat higher noise see the Power Modes section for details Rate Bits These bits select the device bandwidth and output data rate see Table 7 and Table 8 for details The default value is which translates to a 100 Hz output data rate An output data rate should be selected that is appropriate for the communication protocol and frequency selected Selecting too high of an output data rate with a low communication speed results in samples being discarded Register Ox2D POWER_CTL Read Write D7 D6 D5 D4 D3 D2 D1 DO 0 0 Link AUTO SLEEP Measure Sleep Wakeup D7 D6 D5 4 D3 D2 D1 DO 0 0 0 0 Suppress TAP_X TAP_Y TAP_Z enable enable enable Suppress Bit Setting the suppress bit suppresses double tap detection if acceleration greater than the value in THRESH_TAP is present between taps See the Tap Detection section for more details TAP_x Enable Bits A setting of 1 in the X enable TAP_Y enable or TAP_Z enable bit enables x y or z axis participation in tap detection A setting of 0 excludes the selected axis from participation in tap detection Re
345. the watermark interrupt is set FIFO continues accumulating samples until it is full 32 samples from measurements of the x y and z axes and then stops collecting data After FIFO stops collecting data the device continues to operate therefore features such as tap detection can be used after FIFO is full The watermark interrupt continues to occur until the number of samples in FIFO is less than the value stored in the samples bits of the FIFO CTL register Stream Mode In stream mode data from measurements of the x y and z axes are stored FIFO When the number of samples in FIFO equals the level specified in the samples bits of the FIFO_CTL register Address 0x38 the watermark interrupt is set FIFO continues accumulating samples and holds the latest 32 samples from measurements of the x y and z axes discarding older data as new data arrives The watermark interrupt continues occurring until the number of samples in FIFO is less than the value stored the samples bits of the FIFO_CTL register ADXL345 Trigger Mode In trigger mode FIFO accumulates samples holding the latest 32 samples from measurements of the x y and z axes After a trigger event occurs and an interrupt is sent to the INT1 or INT2 pin determined by the trigger bit in the FIFO_CTL register FIFO keeps the last n samples where n is the value specified by the samples bits in the FIFO_CTL register and then operates in FIFO mode collectin
346. time_esp o RUNTIME_PATH raspi o V RUNTIME_PATH runtime o Y i2c o acelerometro o giroscopo o magnetometro o correcionPI_Acc o promediador o correccionPI_Mag o actualizar_matriz o renormalizar o conversor angulos o pid pitch o pid roll o referencias o cambio magnitud o microPWM o V
347. tra propiedades pid pitch instancia 0 ifdef LOG sprintf msgLog 96s V Registering properties of s ID ERROR este gt nombre logPrint msgLog 1 endif if registrarInstancia instancia nombre amp clase pid pitch orden amp este gt habilitado amp este gt finalizado 0 1 ifdef LOG sprintf msgLog s V Registering instance s ID ERROR este gt nombre logPrint msgLog 1 endif k k k k k K K k void funcionInicializa k k k k k fe k k K K K void funcion_inicializa_pid_pitch void instancia struct pid_pitch este struct pid_pitch instancia ifdef LOG sprintf msgLog Initializing 95 este gt nombre logPrint msgLog 3 endif este gt t_ciclo_RT_min 0x 10000000 este 5t ciclo RT max 0 gt ciclo noRT min 0x 10000000 gt ciclo noRT max 0 principio c digo espec fico funcion inicializa pid pitch este proportional pitch 0 este integral pitch 0 este derivative pitch 0 este error pitch 0 este variacion error pitch 0 este error oldl pitch 0 este out old pitch 0 este kp pitch 0 58 este 5ki pitch 0 0933 este kd pitch 0 4725 fin c digo espec fico funcion inicializa pid pitch j ole e ol k k k k k k kk kkk k k k k K void funcionNormal IN void funcion normal pid pitch void instancia
348. triggering when acceleration data does not appear to meet the conditions set by the user for the corresponding function LINK MODE The function of the link bit is to reduce the number of activity interrupts that the processor must service by setting the device to look for activity only after inactivity For proper operation of this feature the processor must still respond to the activity and inactivity interrupts by reading the INT SOURCE register Address 0x30 and therefore clearing the interrupts If an activity interrupt is not cleared the part cannot go into autosleep mode The asleep bit in the ACT STATUS register Address 0x2B indicates if the part is asleep Rev D Page 29 of 40 ADXL345 SLEEP MODE VS LOW POWER MODE In applications where a low data rate and low power consumption is desired at the expense of noise performance it is recommended that low power mode be used The use of low power mode preserves the functionality of the DATA_READY interrupt and the FIFO for postprocessing of the acceleration data Sleep mode while offering a low data rate and power consumption is not intended for data acquisition However when sleep mode is used in conjunction with the AUTO_SLEEP mode and the link mode the part can automatically switch to a low power low sampling rate mode when inactivity is detected To prevent the generation of redundant inactivity interrupts the inactivity interrupt is automatically disabled
349. troller 01 R 6 1 7 1 7 1 1 7 1 2 7 1 3 7 1 4 7 2 7 3 7 3 1 7 3 1 1 7 3 2 7 3 3 7 3 4 7 3 5 7 3 6 7 3 7 7 4 7 5 7 6 7 7 8 1 8 1 1 8 2 8 3 10 11 12 13 14 15 16 17 General description Features and benefits Ordering Block diagram Pinning PINNING 222224 a a aes Pin description Functional description Device Regular 12C bus slave address LED All Call 12C bus address LED Sub Call 12C bus addresses Software Reset I C bus address Control Register definitions Mode register 1 MODE1 Restart mode Mode register 2 MODE2 LED output PWM control ALL LED ON and ALL LED OFF control PWM frequency PRE SCALE SUBADR1 to SUBADRS subaddress 1103 ALLCALLADR LED All Call 12C bus e A Active LOW output enable input Power on Software Using the 9685 with and without external Characteristics of the I2C bus Bit transfer START and STOP conditions
350. type gt lt connection gt lt connection gt lt input gt actualizar_matriz1 dcm_matriz_renorm_1 1 0 lt input gt lt input_resending gt lt input_type gt ID_ENT_FLOAT lt input_type gt lt input_dimensions gt lt output_resending gt lt output gt renormalizar1 dcm_matriz_renorm_1 1 0 lt output gt lt sequence_name gt lt connection_type gt lt connection gt lt connection gt lt input gt actualizar_matriz1 dcm_matriz_renorm_1 1 1 lt input gt lt input_resending gt lt input_type gt ID_ENT_FLOAT lt input_type gt lt input_dimensions gt lt output_resending gt lt output gt renormalizarl dem_matriz_renorm_1 1 1 lt output gt lt sequence_name gt connection type lt connection gt connection input actualizar matrizl dcm matriz renorm 1 1 2 input input resending input type ID ENT FLOAT input type input dimensions output resending output renormalizarl dcm matriz renorm 1 1 2 output sequence name connection type lt connection gt connection input actualizar matrizl dcm matriz renorm 1 2 0 input input resending input type ID ENT FLOAT input type input dimensions output resending output renormalizarl dcm matriz renorm 1 2 0 output sequence name connection type lt connection gt connection input actualizar matrizl dcm matriz renorm 1 2 1 input input
351. uct pid_pitch instancias_pid_pitch MAX_pid_pitch endif struct componente clase_pid_pitch extern char msgLog extern float fdummy 46 gt lt gt lt a void inicializa_propiedades IN void inicializa propiedades pid pitch void instancia char nombre int orden unsigned char habilitado struct pid pitch struct pid pitch instancia strcpy este gt nombre nombre este gt orden orden este gt habilitado habilitado este gt finalizado 0 principio inicializaci n de propiedades espec ficas pid_pitch este gt reference_pitch 2 amp fdummy este gt pitch amp fdummy fin inicializaci n de propiedades espec ficas pid pitch kk k k k k k K K k void registra_propiedades E k k k k f lt k k gt lt K K int registra_propiedades_pid_pitch void instancia struct pid_pitch este struct pid_pitch instancia char saux MAX_LONG_NOMBRE insertarNombre2 este gt nombre este emStrcpy saux ID SISTEMA ID pid pitch NO MODIFICABLE insertarPropiedad3 este gt nombre amp este gt nombre ID VAR TEXT PUBLICO nombre insertarPropiedad3 este gt nombre amp este gt orden ID VAR INT PUBLICO MODIFICABLE orden insertarPropiedad3 este gt nombre amp este gt habilitado ID VAR BYTE PUBLICO MODIFICABLE habilitado insertarPropiedad3 este gt nombre amp este gt finalizado ID VAR B
352. ult state causing the outputs to be set LOW This allows an easy and quick way to reconfigure all device registers to the same condition via software 2 Features and benefits 9685 m 16 LED drivers Each output programmable at Off On Programmable LED brightness Programmable LED turn on time to help reduce EMI 1 MHz Fast mode Plus compatible 12C bus interface with 30 mA high drive capability on SDA output for driving high capacitive buses 4096 step 12 bit linear programmable brightness per LED output varying from fully off default to maximum brightness LED output frequency all LEDs typically varies from 40 Hz to 1000 Hz Default of 1Eh in PRE SCALE register results in a 200 Hz refresh rate with oscillator clock of 25 MHz Sixteen totem pole outputs sink 25 mA and source 10 mA at 5 V with software programmable open drain LED outputs selection default at totem pole No input function B Output state change programmable on the Acknowledge or the STOP Command to update outputs byte by byte or all at the same time default to Change on STOP Active LOW Output Enable OE input pin LEDn outputs programmable to logic 1 logic 0 default at power up or high impedance when OE is HIGH 6hardware address pins allow 62 PCA9685 devices to be connected to the same 12C bus Toggling OE allows for hardware LED blinking 4 software programmable I C bus addresses one LED All Call address an
353. ument is subject to legal disclaimers NXP B V 2010 All rights reserved Product data sheet Rev 3 2 September 2010 35 of 51 Semiconductors 9685 16 channel 12 bit PWM 2 LED controller LED supply CONSTANT CURRENT LC SWITCH MODE REGULATOR Iconstant LIGHT SENSOR Vpp 2 5 V 3 3 V or 5 0 V 1 1 10 ko 2 KW ASIC MICRO T SDA Rsense PCA9685 EXTCLK 002aac828 12C bus address 1010 101x Remark Set INVRT 0 OUTDRV 1 OUTNE 01 MODE2 register bits for this configuration 1 Resistor value should be chosen by referencing Section 7 of UM10204 specification and user manual 2 OE requires pull up resistor if control signal from the master is open drain Fig 27 LCD backlighting application 9685 All information provided this document is subject to legal disclaimers NXP B V 2010 All rights reserved Product data sheet Rev 3 2 September 2010 36 of 51 NXP Semiconductors PCA9685 16 channel 12 bit PWM 2 LED controller 11 Limiting values Table 12 Limiting values In accordance with the Absolute Maximum Rating System IEC 60134 Symbol Parameter Conditions Min Max Unit Vpp supply voltage 0 5 6 0 V Vio voltage on an input output pin Vss 0 5 5 5 V lo LEDn
354. ustomer have explicitly agreed otherwise in writing In no event however shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet 20 3 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information In no event shall NXP Semiconductors be liable for any indirect incidental punitive special or consequential damages including without limitation lost profits lost savings business interruption costs related to the removal or replacement of any products or rework charges whether or not such damages are based on tort including negligence warranty breach of contract or any other legal theory Notwithstanding any damages that customer might incur for any reason whatsoever NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product d
355. ut in LSB for 16 g 10 Bit Resolution Ta 25 Vs 2 5 V 1 8 V Axis Min Max Unit X 6 67 LSB Y 67 6 LSB 7 10 110 LSB Rev D Page 22 of 40 REGISTER ADXL345 Table 19 Address Hex Dec Name Type Reset Value Description 0 00 0 DEVID R 11100101 Device ID 0x01 to Ox1C 1to28 Reserved Reserved do not access 0 1 29 THRESH R W 00000000 Tap threshold Ox1E 30 OFSX R W 00000000 X axis offset Ox1F 31 OFSY R W 00000000 Y axis offset 0x20 32 OFSZ R W 00000000 Z axis offset 0x21 33 DUR R W 00000000 Tap duration 0x22 34 Latent R W 00000000 Tap latency 0x23 35 Window R W 00000000 Tap window 0x24 36 THRESH_ACT R W 00000000 Activity threshold 0x25 37 THRESH INACT R W 00000000 Inactivity threshold 0x26 38 TIME_INACT R W 00000000 Inactivity time 0x27 39 ACT_INACT_CTL R W 00000000 Axis enable control for activity and inactivity detection 0x28 40 THRESH FF R W 00000000 Free fall threshold 0x29 41 TIME FF R W 00000000 Free fall time 0x2A 42 TAP_AXES R W 00000000 Axis control for single tap double tap 0x2B 43 ACT_TAP_STATUS R 00000000 Source of single tap double tap 0x2C 44 BW_RATE R W 00001010 Data rate and power mode control 0x2D 45 POWER_CTL R W 00000000 Power saving features control 0x2E 46 INT_ENABLE R W 00000000 Interrupt enable control Ox2F 47 INT MAP R W 00000000 Interrupt mapping control 0x30 48 INT SOURCE R 00000010 Source of interrupts 0x31 49 DATA FORMAT R W
356. ut the device does not create a conflict on the communication bus At power up the device is in standby mode awaiting a command to enter measurement mode and all sensor functions are off After the device is instructed to enter measurement mode all sensor functions are available Rev D Page 13 of 40 ADXL345 POWER SAVINGS Power Modes The ADXL345 automatically modulates its power consumption in proportion to its output data rate as outlined in Table 7 If additional power savings is desired a lower power mode is available In this mode the internal sampling rate is reduced allowing for power savings in the 12 5 Hz to 400 Hz data rate range at the expense of slightly greater noise To enter low power mode set the LOW POWER bit Bit 4 in the BW RATE register Address 0 2 The current consumption in low power mode is shown in Table 8 for cases where there is an advantage to using low power mode Use of low power mode for a data rate not shown in Table 8 does not provide any advantage over the same data rate in normal power mode Therefore it is recommended that only data rates shown in Table 8 are used in low power mode The current consumption values shown in Table 7 and Table 8 are for a Vs of 2 5 V Table 7 Typical Current Consumption vs Data Rate Ta 25 Vs 2 5 V 1 8 V Low Power Mode Ta 25 C Vs 2 5 V Vppyo 1 8 V Output Data Rate Hz Bandwidth Hz Rate Code loo
357. ve equipment or applications In the event that customer uses the product for design in and use in automotive applications to automotive specifications and standards customer a shall use the product without NXP Semiconductors warranty of the product for such automotive applications use and specifications and b whenever customer uses the product for automotive applications beyond NXP Semiconductors specifications such use shall be solely at customer s 21 Contact information 16 channel 12 bit PWM 2 LED controller own risk and c customer fully indemnifies NXP Semiconductors for any liability damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors standard warranty and NXP Semiconductors product specifications 20 4 Trademarks Notice All referenced brands product names service names and trademarks are the property of their respective owners 12C bus logo is a trademark of NXP B V For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com 9685 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Product data sheet Rev 3 2 September 2010 50 of 51 NXP Semiconductors PCA9685 22 Contents 16 channel 12 bit PWM 2 LED con
358. vice s acknowledge s after seeing the General Call address 0000 0000 00h only If the R W bit is set to 1 read no acknowledge is returned to the 12C bus master 4 Once the General Call address has been sent and acknowledged the master sends 1 byte with 1 specific value SWRST data byte 1 a Byte 1 06h the PCA9685 acknowledges this value only If byte 1 is not equal to 06h the PCA9685 does not acknowledge it If more than 1 byte of data is sent the PCA9685 does not acknowledge any more 5 Once the correct byte SWRST data byte 1 has been sent and correctly acknowledged the master sends a STOP command to end the SWRST Call the PCA9685 then resets to the default value power up value and is ready to be addressed again within the specified bus free time tgur General Call address SWRST data byte 1 START condition acknowledge acknowledge from slave from slave 5 condition 002 900 Fig 12 SWRST Call 2 master must interpret a non acknowledge from the PCA9685 at any time as a SWRST Call Abort The PCA9685 does not initiate a reset of its registers This happens only when the format of the SWRST Call sequence is not correct PCA9685 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Product data sheet Rev 3 2 September 2010 27 of 51 NXP Semiconductors PCA968
359. wer on procedure diagram Section 4 4 e Changed DLPF_CFG setting 7 to reserved Section 8 3 Changed Reflow Specification description Section 9 12 02 12 2010 1 2 Removed errata specifications Updated temperature sensor linearity spec Section 3 1 e Updated VDD Power Supply Ramp Rate timing figure Sections 3 2 and 4 4 e Updated VLOGIC Reference Voltage timing figure Section 4 4 e Added default values to registers all of Section 8 e Updated FS SEL description Section 8 3 Updated package outline drawing and dimensions Section 9 2 Updated Reliability Section 10 1 and 10 2 03 05 2010 1 3 e Removed Environmental Compliance Section 11 03 30 2010 1 4 e Removed confidentiality mark 4 of 39 Document Number PS ITG 3200A 00 01 4 gt Z Revision 1 4 InvenSense ITG 3200 Product Specification Ras ise asia 1 2 Purpose and Scope This document is a preliminary product specification providing a description specifications and design related information for the ITG 3200 Electrical characteristics are based upon simulation results and limited characterization data of advanced samples only Specifications are subject to change without notice Final specifications will be updated based upon characterization of final silicon 1 3 Product Overview The ITG 3200 is the world s first single chip digital output 3 axis MEMS gyro IC optimized for gaming 3D mice and 3D remote
360. xF800 to 0 07 DYRAO through DYRA7 and DYRBO through DYRB7 indicate bit locations with DYRA and DYRB denoting the bits that are in the data output Y registers DYRA7 and DYRB7 denote the first bit of the data stream The number in parenthesis indicates the default value of that bit In the event the ADC reading overflows or underflows for the given channel or if there is a math overflow during the bias measurement this data register will contain the value 4096 This register value will clear when after the next valid measurement is made DYRA7 DYRA6 DYRA5 DYRA4 DYRA3 DYRA2 DYRA1 DYRAO Table 14 Data Output Y Registers A and B Data Output Z Registers A and B The data output Z registers are two 8 bit registers data output register A and data output register B These registers store the measurement result from channel Z Data output Z register A contains the MSB from the measurement result and data output Z register B contains the LSB from the measurement result The value stored in these two registers is a 16 bit value in 2 s complement form whose range is OxF800 to OxO7FF DZRAO through DZRA7 and DZRBO through DZRB7 indicate bit locations with DZRA and DZRB denoting the bits that in the data output Z registers DZRA7 and DZRB7 denote the first bit of the data stream The number in parenthesis indicates the default value of that bit In the event the ADC reading overflows or
361. zado 0 ifdef LOG sprintf msgLog s V Registering instance s ID ERROR este gt nombre logPrint msgLog 1 endif void writeto mag int fd int reg int val void instancia Funcion creada para escr struct magnetometro este struct magnetometro instancia char buf 2 De 128 a 127 buf 0 reg Asocio la primera posicion del vector creado buf 1 2 val Asocio la segunda posicion del vector creado if write fd buf 2 2 strcpy este error msg mag No se puede escribir en el magnetometro n j RR gt lt A A 2 o lt 2 2 o lt 2 2 fe 2 ode gt lt 2 2 k k k k k k k gt e K k void funcionInicializa O void funcion_inicializa_magnetometro void instancia struct magnetometro este struct magnetometro instancia ifdef LOG sprintf msgLog Initializing 95 este gt nombre logPrint msgLog 3 endif este 5t ciclo RT min 0x10000000 gt ciclo RT max 0 gt ciclo noRT min 0x 10000000 gt ciclo noRT max 0 este gt x 0 este gt y 0 este gt z 0 principio c digo espec fico funcion inicializa magnetometro if ioctl este gt fd I2C_SLA VE HMC5883L_I2C_ADDR lt 0 strcpy este error msg mag Magnetometer is not present n Promedio de 8 muestras cada 13 3 ms writeto_mag este gt fd Config Reg A 0x78 instancia Rango campo magnetico 1 3 Ga writeto_mag este g

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