Home

NXP LPC2104, LPC2105, LPC2106 User Manual

1. Prescale Counter ENABLE MAXVAL Timer Control Register Prescale Register Note that Capture Register 3 cannot be used on Timer 0 Figure 30 Timer block diagram Timer O and Timer 1 141 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Timer O and Timer 1 142 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 14 PULSE WIDTH MODULATOR PWM LPC2106 2105 2104 Pulse Width Modulator is based on standard Timer 0 1 described in previous chapter Application can choose among PWM and match functions available FEATURES Seven match registers allow up to 6 single edge controlled or 3 double edge controlled PWM outputs or a mix of both types The match registers also allow Continuous operation with optional interrupt generation on match Stop timer on match with optional interrupt generation Reset timer on match with optional interrupt generation An external output for each match register with the following capabilities Setlow on match Sethigh on match Toggle on match Do nothing on match Supports single edge controlled and or double edge controlled PWM outputs Single edge controlled PWM outputs all go high at the beginning of each cycle unless the output is a constant low Double edge controlled PWM outputs can have either edge occur at any
2. Figure 19 Format in the master transmitter mode Master Receiver Mode In the master receiver mode data is received from a slave transmitter The transfer is initiated in the same way as in the master transmitter mode When the START condition has been transmitted the interrupt service routine must load the slave address and the data direction bit to C Data Register I2DAT and then clear the SI bit When the slave address and data direction bit have been transmitted and an acknowledge bit has been received the SI bit is set and the Status Register will show the status code For master mode the possible status codes are 40H 48H or 38H For slave mode the possible status codes are 68H 78H or BOH Refer to Table 4 in 80C51 Family Derivatives 8XC552 562 Overview datasheet available on line at http www semiconductors philips com acrobat various 8XC552 5620VERVIEW 2 pdf for details Slave Address R DATA A M A P p m A Data Transferred A 1 Read n Bytes Acknowledge A Acknowledge SDA low From Master to Slave A Not Acknowledge SDA high From Slave to Master S START condition P STOP Condition Figure 20 Format of master receiver mode After a repeated START condition IC may switch to the master transmitter mode 12C Interface 113 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontrolle
3. 0c eee eee eee 165 Table 131 Time Counter Relationships and Values 1 0 0 0 00 c eee ees 166 Table 132 Time Counter registers cette teen ee 166 Table 183 Alarm Registers cies ake ade hea Ee ee tex a 167 Table 134 Reference Clock Divider registers 1 0 0 0 cect eh 168 Table 135 Prescaler Integer Register PREINT OxE0024080 200 cee eee 168 Table 136 Prescaler Fraction Register PREFRAC 0xE0024084 0 200 cece les 168 Table 137 Watchdog Register Map 1 0 ee I HH nee 172 Table 138 Watchdog Mode Register WDMOD OxEQ000000 020 eee eee 173 Table 139 Watchdog Feed Register WDFEED 0xE0000008 0222000 0 eee 174 Table 140 Watchdog Timer Value Register WDTV OXEQOOO00C 00 eee eee 174 Table 141 Sectors in a device with 128K bytes of Flash 0 0 0 cc ect 183 Table 142 ISP Command Summary nn 184 Table 143 ISP Unlock command description liiis eh 184 Table 144 ISP Set Baud Rate command descripti0N oooooocococcccococ eee 185 Table 145 Correlation between possible ISP baudrates and external crystal frequency in MHz 185 Table 146 ISP Echo command description liliis ns 186 Table 147 ISP Write to RAM command description a oa 0 0 0 ete ee 187 Table 148 ISP Read Memory command description ococococcococccco eere 187 Table 149 ISP Prepare sector s for write op
4. Divisor Latch The UARTO Divisor Latch MSB Register along with the UODLL register determines the MSB Register baud rate of the UARTO UART 0 87 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 UARTO Interrupt Enable Register UOIER OXE000C004 when DLAB 0 The UOIER is used to enable the four UARTO interrupt sources Table 63 UARTO Interrupt Enable Register Bit Descriptions UOIER OXE000C004 when DLAB 0 Function Description 0 Disable the RDA interrupt RBR Interrupt 1 Enable the RDA interrupt UOIERO enables the Receive Data Available interrupt for UARTO It also controls the Character Receive Time out interrupt 0 Disable the THRE interrupt THRE Interrupt 1 Enable the THRE interrupt Enable UOIER1 enables the THRE interrupt for UARTO The status of this interrupt can be read from UOLSR5 0 Disable the Rx line status interrupts 1 Enable the Rx line status interrupts UARTO Interrupt Identification Register UOIIR OXEO00CO008 Read Only The UOIIR provides a status code that denotes the priority and source of a pending interrupt The interrupts are frozen during an UOIIR access If an interrupt occurs during an UOIIR access the interrupt is recorded for the next UOIIR access Table 64 UARTO Interrupt Identification Register Bit Descriptions UOIIR OxE000C008 Read Only Function Description 0 At least one
5. Although multiple sources can be selected VICIntSelect to generate FIQ request only one interrupt service routine should be dedicated to service all available present FIQ request s Therefore if more than one interrupt sources are classified as FIQ the FIQ interrupt service routine must read VICFIQStatus to decide based on this content what to do and how to process the interrupt request However it is recommended that only one interrupt source should be classified as FIQ Classifying more than one interrupt sources as FIQ will increase the interrupt latency Following the completion of the desired interrupt service routine clearing of the interrupt flag on the peripheral level will propagate to corresponding bits in VIC registers VICRawintr VICFIQStatus and VICIRQStatus Also before the next interrupt can be serviced it is necessary that write is performed into the VICVectAddr register before the return from interrupt is executed This write will clear the respective interrupt flag in the internal interrupt priority hardware In order to disable the interrupt at the VIC you need to clear corresponding bit in the VICIntEnClr register which in turn clears the related bit in the VICIntEnable register This also applies to the VICSoftInt and VICSoftIntClear in which VICSoftIntClear will clear the respective bits in VICSoftInt For example if VICSoftInt 0x0000 0005 and bit O has to be cleared VICSoftIntClear 0x0000 0001 will acomplish this Befo
6. The ability to separately control rising and falling edge locations allows the PWM to be used for more applications For instance multi phase motor control typically requires three non overlapping PWM outputs with individual control of all three pulse widths and positions Two match registers can be used to provide a single edge controlled PWM output One match register PIWMMR0 controls the PWM cycle rate by resetting the count upon match The other match register controls the PWM edge position Additional single edge controlled PWM outputs require only one match register each since the repetition rate is the same for all PWM outputs Multiple single edge controlled PWM outputs will all have a rising edge at the beginning of each PWM cycle when an PWMMRO match occurs Pulse Width Modulator PWM 143 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Three match registers can be used to provide a PWM output with both edges controlled Again the PWMMRO match register controls the PWM cycle rate The other match registers control the two PWM edge positions Additional double edge controlled PWM outputs require only two match registers each since the repetition rate is the same for all PWM outputs With double edge controlled PWM outputs specific match registers control the rising and falling edge of the output This allows both positive going PWM pulses when the rising edge occur
7. oocococccocccoc nanan 45 Table 15 PLL Status Register PLLSTAT OXEO1FC088 sssssseseeeeee s 46 Table 16 PLL Control Bit Combinations l llllseleeee ee eee n eee 46 Table 17 PLL Feed Register PLLFEED OxEO1FCO8C 0 eee eee 47 Table 18 PLLE Divider Values 2 e bI Ree ROS FEE OP dd hee Die a mi epa he 48 Table 19 PLL Multiplier Values lille IIR RR IIR ene 48 Table 20 Power Control Registers oooococccoccooconr ee teens 49 Table 21 Power Control Register PCON OXEO1FC0CO0 ooococccocc ees 49 Table 22 Power Control for Peripherals Register PCONP OXEOTFCOC4 isses sees 50 Table 23 VPBDIV Register Map ooo ooccooocor e I re 52 Table 24 VPB Divider Register VPBDIV OxE01FC100 0 00 cece eee 52 Table 25 MAM Responses to Program Accesses of Various Types eese 57 Table 26 MAM Responses to Data and DMA Accesses of Various Types llle eese 57 Table 27 Summary of System Control Registers 0 00 cece eee 58 Table 28 MAM Control Register MAMCR OXxEO1FCODO ooccccccccoc rene 59 Table 29 MAM Timing Register MAMTIM OXEO1FC004 oocococcococcc ee 59 Table 30 VIC Register Map oococoococcococon Rm mehr 62 Table 31 Software Interrupt Register VICSoftInt OXFFFFF018 Read Write 64 Table 32 Software Interrupt Clear Register VICSoftlntClear OXFFFFF01C Write Only 64 Table 3
8. 0x0002 0000 Sector 15 Boot Block 0x0001 E000 Sector 14 0x0001 C000 Sector 13 0x0001 A000 Sector 12 0x0001 8000 Sector 11 0x0001 6000 Sector 10 0x0001 4000 Sector 9 0x0001 2000 Sector 8 0x0001 0000 Sector 7 0x0001 E000 Sector 6 0x0001 C000 Sector 5 0x0001 A000 Sector 4 0x0001 8000 Sector 3 0x0000 6000 Sector 2 0x0000 4000 Sector 1 0x0000 2000 Sector 0 0x0000 0000 Addresses shown do not reflect re mapping of the Boot Block Figure 36 Flash Sector Map Memory map after any reset The boot sector is 8 kB in size and resides in the top portion starting from 0x0001 E000 of the on chip flash memory After any reset the entire boot sector is also mapped to the top of the on chip memory space i e the boot sector is also visible in the memory region starting from the address Ox7FFF E000 The flash boot loader is designed to run from this memory area but both the ISP Flash Memory System and Programming 178 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 and IAP software use parts of the on chip RAM The RAM usage is described later in this chapter The interrupt vectors residing in the boot sector of the on chip flash memory also become active after reset i e the bottom 64 bytes of the boot sector are also visible in the memory region starting from the address 0
9. Counter Increment Interrupt Register CIIR the alarm registers and the Alarm Mask Register AMR Interrupts are generated only by the transition into the interrupt state The ILR separately enables CIIR and AMR interrupts Each bit in CIIR corresponds to one of the time counters If CIIR is enabled for a particular counter then every time the counter is incremented an interrupt is generated The alarm registers allow the user to specify a date and time for an interrupt to be generated The AMR provides a mechanism to mask alarm compares If all non masked alarm registers match the value in their corresponding time counter then an interrupt is generated Real Time Clock 160 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 MISCELLANEOUS REGISTER GROUP Table 122 summarizes the registers located from 0 to 7 of A 6 2 More detailed descriptions follow Table 122 Miscellaneous Registers Address Name Size Description Access Interrupt Location Reading this location indicates the source of an 0xE0024000 2 interrupt Writing a one to the appropriate bit at this location clears the associated interrupt ILR 0xE0024004 15 Clock Tick Counter Value from the clock divider 0xE0024008 4 Clock Control Register Controls the function of the clock divider AMR ES ivider RW peme AAA Fro NUR 6 iem Mesk Reser Conros wien ote alam registrare masked RW Consolidated Time Re
10. Figure 1 LPC2106 2105 2104 Block Diagram Introduction 18 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 LPC2106 2105 2104 REGISTERS Accesses to registers in LPC2106 2105 2104 is restricted in the following ways 1 user must NOT attempt to access any register locations not defined 2 Access to any defined register locations must be strictly for the functions for the registers 3 Register bits labeled 0 or 1 can ONLY be written and read as follows MUST be written with 0 but can return any value when read even if it was written with 0 It is a reserved bit and may be used in future derivatives 0 MUST be written with 0 and will return a 0 when read 1 MUST be written with 1 and will return a 1 when read The following table shows all registers available in LPC2106 2105 2104 microcontroller sorted according to the address Access to the specific one can be categorized as either read write read only or write only R W RO and WO respectively Reset Value field refers to the data stored in used accessible bits only It does not include reserved bits content Some registers may contain undetermined data upon reset In this case reset value is categorized as undefined Classification as NA is used in case reset value is not applicable Some registers in RTC are not affected by the chip reset Their reset value is mar
11. INTEGRATED CIRCUITS USER MANUAL LPC2106 2105 2104 USER MANUAL Preliminary 2003 Sep 17 Philips PHILIPS Semiconductors DH l LI DS Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 2 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Table of Contents List Of EIg res 101 is A A A er eg cae och bi 7 List Of Tables hago bai eer Made a a ee exe iar MER a E a aed 9 Document Revision History o ooooococooro eee 13 INtrOdUCHION 000 le ke im Re Ee a a a a A 15 IE ce C Goals eles DEW ok eR ae eA ae Rae ea ae vk ee ale tee Sate 15 Applications M PEE A a 15 Architectural Overview cc totali on a woe Re glen Linge EORR e ke ge GE ele 16 ARM7TDMI S Processor 0000 cece ete eens 16 On Chip Flash Memory System 00 cette tte 16 On Chip StatiG RAM ria g coset bi ee at sew a ed TR E ee el ies 17 Block Diagram sas rig ege EH pe ERE afe Ra beds ct 18 LPC2106 2105 2104 Registers oooooccocccccc en 19 LPC2106 2105 2104 Memory Addressing eee eee eee 29 Memory Maps eni ia e res sueco Darei ist ege 2k ee cieli ees ce le tae TOR et 29 LPC2106 2105 2104 Memory Re mapping and Boot Block oooococcocoocccococo 33 Prefetch Abort and Data Abort Exceptions ooooocoooccocrr ee 36 System Control Block ooooococcccon hn nnn 37 Summary of Sys
12. Phase Locked Loop OxEO1FCO80 PLLCON PLL control register RW o E EE EEN ECO PASTA pac 5 CT E ww mwecnmwme ELLE CO pwo VPB Divider 0xE01FC100 VPBDIV VPB divider control RW 0 Reset Value refers to the data stored in used bits only It does not include reserved bits content System Control Block 38 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 CRYSTAL OSCILLATOR The oscillator supports crystals in the range of 10 MHz to 25 MHz The oscillator output frequency is called F and the ARM processor clock frequency is referred to as cclk for purposes of rate equations etc elsewhere in this document Fog and celk are the same value unless the PLL is running and connected Refer to the PLL description in this chapter for details Onboard oscillator in LPC2106 2105 2104 can operate in one of two modes slave mode and oscillation mode In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF Cc in Figure 7 drawing a with an amplitude of at least 200 mVrms X2 pin in this configuration can be left not connected External components and models used in oscillation mode are shown in Figure 7 drawings b and c and in Table 6 Since the feedback resistance is integrated on chip only a crystal and the capacitances Cy and Cy need to be connected externally in case of fundamental mo
13. Table 7 External Interrupt Registers Address Name Description Access The External Interrupt Flag register contains interrupt flags for EINTO EINT1 and OxEO1FC140 EXTINT EINT2 See Table 8 R W The External Interrupt Wakeup register contains three enable bits that control 0xE01FC144 EXTWAKE whether each external interrupt will cause the processor to wake up from Power Down mode See Table 9 EXTINT Register EXTINT 0xE01FC140 When an external interrupt is mapped to its related pin the presence of a logic zero on that pin will set the corresponding interrupt flag in the EXTINT register This will cause the VIC to respond appropriately if that interrupt is enabled Once the logic level on external interrupt pin s is set to 1 software may clear the flag s by writing a 1 to the corresponding bit s in EXTINT Every attempt to reset EINT bit is futile as long as signal level on associated pin is 0 Table 8 External Interrupt Flag Register EXTINT 0xE01FC140 Reset EXTINT Function Description Value Set when external the EINTO pin goes low and EINTO is mapped to its related pin Can be cleared by writing a 1 to this bit after the logic 1 appears on the related pin 1 EINT Set when external the EINT1 pin goes low and EINT1 is mapped to its related pin Can be cleared by writing a 1 to this bit after the logic 1 appears on the related pin 0 EINTO 0 2 EINT2 Set when external the EINT2 pin goes low and EINT
14. of the VIC and it enables the DBGCommRX and DBGCommTx interrupts Default vector address register is programmed with the address of Vectored IRQs or FIQs here FER A A A AA A RA AAR A kCKCkCk k Ck k Ck kk kc k k ck k ck k ck k ck ck ckck ck ck ck ok ck ok kk ke ke x f A A F 0X x VICBaseAddr EQU OxFFFFFO000 VIC Base address VICDefVectAddrOffset EQU 0x34 LDR r0 VICBaseAddr LDR rl app irqDispatch STR rl xr0 VICDefVectAddrOffset BL rm_init_entry Initialize RealMonitor enable FIQ and IRQ in ARM Processor MRS rl CPSR get the CPSR BIC rl rl 0xCO enable IRQs and FIQs MSR CPSR c rl update the CPSR BRK IK RR Ck Ck Ck Ck RARA RARA k k k k k k kk k RR ARA A A ARA RAR k ck A A A ck ok sk ke kk Get the address of the User entry point FER KK A A Kk kk kk Kk kk A A A A A A AA A AA A A k Ck k ck kckckckok ckokckok ck ok sk sk ke e OO f LDR lr User Entry MOV pc lr KK IK kK kK KKK Kk Ck RARA kk kk kk k k k k k k RAR k k k k k k k k k Ck Ck k k ck k ck k ckckckokckok kok ko ke kk Non vectored irq handler app_irqDispatch A AREA app irqDispatch CODE VICVectAddrOffset EQU 0x30 app irqDispatch enable interrupt nesting STMFD sp r12 r14 MRS r12 spsr Save SPSR in to r12 MSR cpsr_c 0x1F Re enable IRQ go to system mode User should insert code here if non vectored Interrupt sharing is required Each non vectored shared irq handler must return to the interrupte
15. to its pin When a match occurs for MR2 this output of the timer can either toggle go low go high or do nothing Bits EMR 8 9 control the functionality of this output This bit reflects the state of output MATO 1 When a match occurs for MRS this output of the timer can either toggle go low go high or do nothing Bits EMR 10 11 control the functionality of this output Note In the case of Timer 0 this output cannot be connected to a device pin External Match Determines the functionality of External Match 0 Table 112 shows the encoding of Control 0 these bits External Match Determines the functionality of External Match 1 Table 112 shows the encoding of Control 1 these bits External Match Determines the functionality of External Match 2 Table 112 shows the encoding of Control 2 these bits 11 10 External Match Determines the functionality of External Match 3 Table 112 shows the encoding of e Control 3 these bits Table 112 External Match Control External Match 3 5 4 7 6 EMR 11 10 EMR 9 8 EMR 7 6 or EMR 5 4 Function Do Nothing Clear corresponding External Match output to 0 LOW if pinned out 00 Timer O and Timer 1 139 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 EXAMPLE TIMER OPERATION Figure 28 shows a timer configured to reset the count and generate an interrupt on match The prescaler is set to 2 and the m
16. 1 To give the FIQ handler in the Flash memory the advantage of not having to take a memory boundary caused by the re mapping into account 2 Minimize the need to for the SRAM and Boot Block vectors to deal with arbitrary boundaries in the middle of code space 3 To provide space to store constants for jumping beyond the range of single word branch instructions Re mapped memory areas including the Boot Block and interrupt vectors continue to appear in their original location in addition to the re mapped address LPC2106 2105 2104 Memory Addressing 34 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 0x8000 0000 2 0 GB 8K byte Boot Block Ox7FFF FFFF re mapped from top of Flash memory 2 0 GB 8K Boot Block interrupt vectors Reserved for On Chip Memory 0x4000 FFFF On Chip SRAM LPC2106 64K byte 0x4000 FFFF LPC2105 32K byte 0x4000 7FFF LPC2104 16K byte 0x4000 3FFF SRAM interrupt vectors 0x4000 0000 Ox3FFF FFFF 8k byte Boot Block re Mapped to higher address range 0x0001 FFFF Active interrupt vectors from Flash SRAM or Boot Block 0x0000 0000 Note memory regions are not drawn to scale Figure 6 Map of lower memory is showing re mapped and re mappable areas LPC2106 2105 2104 Memory Addressing 35 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 PREFETCH ABORT AND DA
17. ARM based Microcontroller LPC2106 2105 2104 12C Control Set Register IZCONSET 0xE001C000 AA is the Assert Acknowledge Flag When set to 1 an acknowledge low level to SDA will be returned during the acknowledge clock pulse on the SCL line on the following situations The address in the Slave Address Register has been received The general call address has been received while the general call bit GC in I2ADR is set A data byte has been received while the I C is in the master receiver mode 4 A data byte has been received while the 12C is in the addressed slave receiver mode Qo ccm The AA bit can be cleared by writing 1 to the AAC bit in the IZCONCLR register When AA is 0 a not acknowledge high level to SDA will be returned during the acknowledge clock pulse on the SCL line on the following situations 1 A data byte has been received while the 12C is in the master receiver mode 2 A data byte has been received while the 12C is in the addressed slave receiver mode Sl is the 12C Interrupt Flag This bit is set when one of the 25 possible IC states is entered Typically the Fe interrupt should only be used to indicate a start condition at an idle slave device or a stop condition at an idle master device if it is waiting to use the 12C bus Sl is cleared by writing a 1 to the SIC bit in I2CONCLR register STO is the STOP flag Setting this bit causes the 12C interface to transmit a STOP condition in master mode or recover fro
18. Pulse Width Modulator PWM 153 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Table 118 PWM Match Control Register PWMMCR 0xE0014014 PWMMCR Function Description When one the PWMTC and PWMPC will be stopped and PWMTCAR O will be set to 0 if PWMMR5 matches the PWMTC When zero this feature is disabled When one an interrupt is generated when PWMMR6 matches the value in the MIRE PWMTC When zero this interrupt is disabled 17 Stop on PWMMR5 19 Reset on PWMMR6 When one the PWMTC will be reset if PWMMR6 matches it When zero this feature is disabled When one the PWMTC and PWMPC will be stopped and PWMTCRIO will be set to Stop on PWMMR6 0 if PWMMR6 matches the PWMTC When zero this feature is disabled PWM Control Register PWMPCR 0xE001404C The PWM Control Register is used to enable and select the type of each PWM channel The function of each of the bits are shown in Table 119 Table 119 PWM Control Register PWMPCR 0xE001404C Reset Function Description Value Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined 2 PWMSEL2 When zero selects single edge controlled mode for PWM2 When one selects double edge controlled mode for the PWM2 output 3 PWMSEL3 When zero selects single edge controlled mode for PWM3 When one selects double edge controlled mode for the PWMS outp
19. Register Description oooooorocrororceo eee me eens 116 ArCOISCIUTO cst teenie REPRE ead Moke DE Me t aetna ad a m oe e ers 122 SPL Interfaces si ee arco eae a aie chee be RU ERR 123 Features i e aa A goad iy A de es ei Ru iy Ree am a 123 Description ansi EET 123 Pin Description sy oi ES oa ees ea A SEHR d a 127 Register Description uum Rice RR a Geto ca Gide eck NECEM tama B 128 Architecture o AA QE WE AA anra eR A eR PUER Bep A 131 Timer 0 and Timer 1 2 5 tii ee ur Ale IERI llb er xr 133 Features a a NUI Poet a Sadie o aida 133 Applications redee Reb ers ith pes O e REGI AA 133 Description pen ue ii IRE muore ead pere peer 134 Pin Description ee uo roi REIR er te oras 134 Register Description 0 00 00 cc lel me hr 135 Example Timer Operation ricse idene ini eiA a RII II III 140 Architecture x xo cR RISE EIER ae Rede dente ex E d erit eos 141 Pulse Width Modulator PWM ooooocococonooo ee 143 Feat re P le 143 Description 4 2 9 Du eeu ri D Pu ne repe ei uo e AA IN EXE ee E 143 Pin Descrption i e ue lia glee he pup Eg RE PATE none e IE tios 148 Register Description o oooooooroorrer RR Rm Ie 149 4 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Real Time Clock 00 io ii A hee A NIRE 157 i i RD UTE 157 Description ia aee eno roD per urbi dues ead EU RP IURE Ee ES 157 AtChitectire x aaa Rit mex M EE EORR ie outs ORLE ME
20. and EINTO It is possible for a chip Reset to occur during a Flash programming or erase operation The Flash memory will interrupt the ongoing operation and hold off the completion of Reset to the CPU until internal Flash high voltages have settled Reset to External Reset Flash Watchdog Memory Reset Reset to PCON PD Power Down A Wakeup Timer VPB Read EINTO Wakeup __ Start Count 2 EINT1 Wakeu Oscillator of PDbit gt Output Fosc gt in PCON EINT2 Wakeup Write 1 from VPB Reset Figure 10 Reset Block Diagram including Wakeup Timer System Control Block 51 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 VPB DIVIDER The VPB Divider determines the relationship between the processor clock cclk and the clock used by peripheral devices pclk The VPB Divider serves two purposes The first is to provides peripherals with desired pclk via VPB bus so that they can operate at the speed chosen for the ARM processor In order to achieve this the VPB bus may be slowed down to one half or one fourth of the processor clock rate Because the VPB bus must work properly at power up and its timing cannot be altered if it does not work since the VPB divider control registers reside on the VPB bus the default condition at reset is for the VPB bus to run at one quarter speed The second purpose of the VPB Divi
21. diagram of the PLL is shown in Figure 9 PLL activation is controlled via the PLLCON register The PLL multiplier and divider values are controlled by the PLLCFG register These two registers are protected in order to prevent accidental alteration of PLL parameters or deactivation of the PLL Since all chip operations including the Watchdog Timer are dependent on the PLL when it is providing the chip clock accidental changes to the PLL setup could result in unexpected behavior of the microcontroller The protection is accomplished by a feed sequence similar to that of the Watchdog Timer Details are provided in the description of the PLLFEED register The PLL is turned off and bypassed following a chip Reset and when by entering power Down mode PLL is enabled by software only The program must configure and activate the PLL wait for the PLL to Lock then connect to the PLL as a clock source Register Description The PLL is controlled by the registers shown in Table 12 More detailed descriptions follow Warning Improper setting of PLL values may result in incorrect operation of the device Table 12 PLL Registers Address Name Description 0xE01FC080 PLLCON Holding register for updating PLL control bits Values written to this register do not take effect until a valid PLL feed sequence has taken place Holding register for updating PLL configuration values Values written to this RED TEGO EE register do not take effect until a valid PLL fee
22. may generate interrupts to cause the processor to resume execution Idle mode eliminates power used by the processor itself memory systems and related controllers and internal buses In Power Down mode the oscillator is shut down and the chip receives no internal clocks The processor state and registers peripheral registers and internal SRAM values are preserved throughout Power Down mode and the logic levels of chip pins remain static The Power Down mode can be terminated and normal operation resumed by either a Reset or certain specific interrupts that are able to function without clocks Since all dynamic operation of the chip is suspended Power Down mode reduces chip power consumption to nearly zero Wakeup from Power Down or Idle modes via an interrupt resumes program execution in such a way that no instructions are lost incomplete or repeated Wake up from Power Down mode is discussed further in the description of the Wakeup Timer later in this chapter A Power Control for Peripherals feature allows individual peripherals to be turned off if they are not needed in the application resulting in additional power savings Register Description The Power Control function contains two registers as shown in Table 20 More detailed descriptions follow Table 20 Power Control Registers Address Description Power Control Register This register contains control bits that enable the two reduced power operating modes of the LPC210
23. the same as the Match channel 0 value have the same effect except as noted in rule 3 For example a request for a falling edge at the beginning of the PWM cycle has the same effect as a request for a falling edge at the end of a PWM cycle 3 When match values are changing if one of the old match values is equal to the PWM rate it is used again once if the neither of the new match values are equal to O or the PWM rate and there was no old match value equal to 0 4 If both a set and a clear of a PWM output are requested at the same time clear takes precedence This can occur when the set and clear match values are the same as in or when the set or clear value equals 0 and the other value equals the PWM rate 5 If a match value is out of range i e greater than the PWM rate value no match event occurs and that match channel has no effect on the output This means that the PWM output will remain always in one state allowing always low always high or no change outputs Pulse Width Modulator PWM 147 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 PIN DESCRIPTION Table 114 gives a brief summary of each of PWM related pins Table 114 Pin summary Pin name Pin direction Pin Description PWM1 Output Output from PWM channel 1 PWM2 Output Output from PWM channel 2 Output from PWM channel 3 Pulse Width Modulator PWM 148 September 17 2003 Phili
24. 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 JTAG FLASH PROGRAMMING INTERFACE There are three possibilities for this interface 1 Debug tools can write parts of the flash image to the RAM and then execute the IAP call Copy RAM to Flash repeatedly with proper offset 2 Debug tools can execute the flash programming code via JTAG port Flash Memory System and Programming 199 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Flash Memory System and Programming 200 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 18 EMBEDDEDICE LOGIC FEATURES No target resources are required by the software debugger in order to start the debugging session Allows the software debugger to talk via a JTAG Joint Test Action Group port directly to the core Inserts instructions directly in to the ARM7TDMI S core The ARM7TDMI S core or the System state can be examined saved or changed depending on the type of instruction inserted Allows instructions to execute at a slow debug speed or at a fast system speed APPLICATIONS The EmbeddedICE logic provides on chip debug support The debugging of the target system requires a host computer running the debugger software and an EmbeddedICE protocol convertor EmbeddedICE protocol convertor converts the Remote Debug P
25. 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 UARTO Line Control Register UOLCR 0xE000C00C The UOLCR determines the format of the data character that is to be transmitted or received Table 67 UARTO Line Control Register Bit Descriptions UOLCR 0xE000C00C Reset Function Description Value 00 5 bit character length Word Length 01 6 bit character length Select 10 7 bit character length 11 8 bit character length 0 1 stop bit Stop Bit Select 4 2 Stop bits 1 5 if UOLCR 1 0 00 0 Disable parity generation and checking Panty Enable 1 Enable parity generation and checking 0 0 Disable break transmission Break Control 1 Enable break transmission Output pin UARTO TxD is forced to logic O when UOLCRE is active high 7 Divisor Latch 0 Disable access to Divisor Latches Access Bit 1 Enable access to Divisor Latches UARTO Line Status Register UOLSR 0xE000C014 Read Only 00 Odd parity 01 Even parity Parity Select 10 Forced 1 stick parity 11 Forced 0 stick parity The UOLSR is a read only register that provides status information on the UARTO Tx and Rx blocks UART O 91 September 17 2003 Philips Semiconductors ARM based Microcontroller LPC2106 2105 2104 Preliminary User Manual Table 68 UARTO Line Status Register Bit Descriptions UOLSR 0xE000C014 Read Only Function Description UARTO Recei
26. 221 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 execute code buffer size Also refer to RM_OPT_EXECUTECODE option RM_OPT_GATHER_STATISTICS FALSE This option enables or disables the code for gathering statistics about the internal operation of RealMonitor RM_DEBUG FALSE This option enables or disables additional debugging and error checking code in RealMonitor RM_OPT_BUILDIDENTIFIER FALSE This option determines whether a build identifier is built into the capabilities table of RMTarget Capabilities table is stored in ROM RM_OPT_SDM_INFO FALSE SDM gives additional information about application board and processor to debug tools RM_OPT_MEMORYMAP FALSE This option determines whether a memory map of the board is built into the target and made available through the capabilities table RM_OPT_USE_INTERRUPTS TRUE This option specifies whether RMTarget is built for interrupt driven mode or polled mode RM FIFOSIZEZNA This option specifies the size in words of the data logging FIFO buffer CHAIN VECTORS FALSE This option allows RMTarget to support vector chaining through HAL ARM HW abstraction API RealMonitor 222 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Purchase of Philips 12 components conveys a license under the Philips 12C patent to use the components in the 12C system prov
27. ARM code while retaining most of the ARM s performance advantage over a traditional 16 bit processor using 16 bit registers This is possible because THUMB code operates on the same 32 bit register set as ARM code THUMB code is able to provide up to 65 of the code size of ARM and 160 of the performance of an equivalent ARM processor connected to a 16 bit memory system The ARM7TDMI S processor is described in detail in the ARM7TDMI S Datasheet that can be found on official ARM website ON CHIP FLASH MEMORY SYSTEM The LPC2106 2105 2104 incorporates a 128K byte Flash memory system This memory may be used for both code and data storage Programming of the Flash memory may be accomplished in several ways over the serial built in JTAG interface using In System Programming ISP and UARTO or by means of In Application Programming IAP capabilities The application program using the In Application Programming IAP functions may also erase and or program the Flash while the application is running allowing a great degree of flexibility for data storage field firmware upgrades etc Introduction 16 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 ON CHIP STATIC RAM The LPC2106 LPC2105 and LPC2104 provide a 64K byte 32K byte and 16K byte static RAM memory respectively that may be used for code and or data storage The SRAM supports 8 bit 16 bit and 32 bit accesses The SR
28. Bro MB H miso cPHA 1 M sit XBit2 XBit3 X Bit 4 XBit5 pio XBit7 X Bite Figure 26 SPI Data Transfer Format CPHA 0 and CPHA 1 The data and clock phase relationships are summarized in Table 97 This table summarizes the following for each setting of CPOL and CPHA When the first data bit is driven When all other data bits are driven When data is sampled Table 97 SPI Data To Clock Phase Relationship CPOL And CPHA Settings First Data Driven Other Data Driven Data Sampled CPOL 0 CPHA 0 Prior to first SCK rising edge SCK falling edge SCK rising edge CPOL 0 CPHA 1 First SCK rising edge SCK rising edge SCK falling edge CPOL 1 CPHA 0 Prior to first SCK falling edge SCK rising edge SCK falling edge CPOL 1 CPHA 1 First SCK falling edge SCK falling edge SCK rising edge The definition of when an 8 bit transfer starts and stops is dependent on whether a device is a master or a slave and the setting of the CPHA variable SPI Interface 124 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 When a device is a master the start of a transfer is indicated by the master having a byte of data that is ready to be transmitted At this point the master can activate the clock and begin the transfer The transfer ends when the last clock cycle of the transfer is complete When a device is a sla
29. Consolidated Time Register 0 a 0xE0024018 CTIME1 Consolidated Time Register 1 0xE002401C CTIME2 32 Consolidated Time Register 2 0xE0024020 Seconds Register 0xE0024024 ON E I RR Minutes Minutes Register ucro 0xE0024028 HOUR Hours Register RW 0xE002402C DOM 5 Day of Month Register RW 0xE0024030 DOW 3 Day of Week Register RW 0xE0024034 ESA ESO Day of Year Register naun 0xE0024038 MONTH EJ Months Register 0xE002403C YEAR 12 Years Register EUM 0xE0024060 ALSEC Alarm value for Seconds R W 0xE0024064 AMN 6 Alarm value for Minutes value for Minutes ees 0xE0024068 Eee A AA value for Hours Rw D UR 0xE002406C ALDOM Alarm value for Day of Month 0xE0024070 ALDOW Alarm value for Day of Week 0xE0024074 ALDOY inet Alarm value for Day of Year 0xE0024078 ALMON Alarm value for Months OxE002407C ALYEAR 12 Alarm value for Year R W 0xE0024080 PREINT 13 Prescale value integer portion R W 0 0xE0024084 PREFRAC Prescale value fractional portion RW 0 Registers in the RTC other than those that are part of the Prescaler are not affected by chip Reset These registers must be initialized by software if the RTC is enabled Real Time Clock 159 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 RTC INTERRUPTS Interrupt generation is controlled through the Interrupt Location Register ILR
30. Description Preliminary User Manual LPC2106 2105 2104 X o 0 o LSB Access Value T1 Capture 0xE0008038 Register 3 Name T1CR3 T1 External T1EMR Match Register UORBR DLAB 0 Holding 0xE000C000 UOTHR oo Register UODLL UO Divisor DLAB 1 Latch LSB UO Interrupt Enable Register 0xE000803C UART 0 UO Receiver Buffer Register UO Transmit UOIER DLAB 0 0xE000C004 UODLM DLAB 1 UO FIFO UOFCR Control Register UO Line OxE000C00C UOLCR Control Register UO Line 0xE000C014 UOLSR Status Register UART 1 Introduction UO Divisor Latch MSB 8 bit data R W uoi UO Interrupt FIFOs Enabled ms nee IIR1 ID Register OxE000C008 Set Stick Rx FIFO TEMT THRE FE PE OE Error oxEoooco1c uoscn YO Scratch 8 bit data R W Pad Register 32 bit data RO External Match Control 2 Ext Ext Mtch 1 Mtch 0 External Match 4 reserved bits Control 3 External Match Ext Ext Control 0 Mtch 3 Mtch2 8 bit data R W External Match Control 1 EE Z gt 8 bit data 8 bit data R W 0x01 Word Length Select Parity Enable Select 22 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Table 1 LPC2106 2105 2104 Registers Address Offset 8 bit data 1T 0xE0010000 U1THR oa 8 bit data am DLAB 0 9 Register ean U1 Divisor Latch LS
31. Input pin RxD1 has no effect on loopback and output pin TxD1 is held in marking state The four modem inputs CTS DSR RI and DCD are disconnected externally Externally the modem outputs RTS DTR are set inactive Internally the four modem outputs are connected to the four modem inputs As a result of these connections the upper four bits of the U1MSR will be driven by the lower four bits of the U1MCR rather than the four modem inputs in normal mode This permits modem status interrupts to be generated in loopback mode by writing the lower four bits of UTMCR Reserved user software should not write ones to reserved bits The value read from a Reserved hon reserved bit is not defined Loopback Mode Select UART 1 105 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 UART1 Line Status Register U1LSR 0xE0010014 Read Only The U1LSR is a read only register that provides status information on the UART1 Tx and Rx blocks Table 82 UART1 Line Status Register Bit Descriptions UTLSR 0xE0010014 Read Only Function Description 0 UTRBR is empty Receiver Data 1 UTRBR contains valid data Ready RDR U1LSRO is set when the U1RBR holds an unread character and is cleared when the UART1 RBR FIFO is empty 0 Overrun error status is inactive 1 Overrun error status is active Overrun Error The overrun error condition is set as soon as it occurs An
32. MN This command is used to program the flash memory The affected sectors should be prepared first by calling Prepare Sector for Write Operation command The affected sectors are automatically protected again once the copy command is successfully executed The boot sector can not be written by this command Description Erase Sector s Table 161 IAP Erase Sector s command description Command Erase Sector s Command code 52 Input Paramo Start Sector Number P Param1 End Sector Number Should be greater than or equal to start sector number Param2 System Clock Frequency CCLK in KHz CMD SUCCESS Status Code BUSTI SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION INVALID_SECTOR BELLNM MN This command is used to erase a sector or multiple sectors of on chip Flash memory The boot Description sector can not be erased by this command To erase a single sector use the same Start and End sector numbers Flash Memory System and Programming 196 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Blank check sector s Table 162 IAP Blank check sector s command description Command Blank check sector s Command code 53 Input Paramo Start Sector Number Param1 End Sector Number Should be greater than or equal to start sector number CMD SUCCESS BUSY SECTOR NOT BLANK INVALID SECTOR ResultO Offset of the first non blank word locati
33. Match output for Timer 0 channel 0 Serial Clock SPI clock output from master or input to slave Capture input for Timer 0 channel 1 Master In Slave Out Data input to SPI master or data output from SPI slave Match output for Timer 0 channel 1 Master Out Slave In Data output from SPI master or data input to SPI slave Capture input for Timer 0 channel 2 Slave Select Selects the SPI interface as a slave Pulse Width Modulator output 2 Transmitter output for UART 1 Pulse Width Modulator output 4 Receiver input for UART 1 Pulse Width Modulator output 6 73 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Table 46 Pin description and corresponding functions for LPC2106 2105 2104 LQFP 48 EU ice IIA RTS1 Request to Send output for UART 1 CAP1 0 Capture input for Timer 1 channel 0 CTS1 Clear to Send input for UART 1 CAP1 1 Capture input for Timer 1 channel 1 DSR1 Data Set Ready input for UART 1 MAT1 0 Match output for Timer 1 channel 0 DTR1 Data Terminal Ready output for UART 1 MAT1 1 Match output for Timer 1 channel 1 DCD1 Data Carrier Detect input for UART 1 EINT1 External interrupt 1 input RI Ring Indicator input for UART 1 EINT2 External interrupt 2 input EINTO External interrupt 0 input MATO 2 Match output for Timer 0 channel 2 CAP1 2 Capture input for Timer 1 channel 2 TRST Test Reset for JTAG
34. PWM1 P0 1 RxDO PWM3 14 P0 30 TRACEPKT3 TDI P0 31 EXTINO TDO 16 P0 2 SCL CAPO 0 18 71 Vss2 19 P0 3 SDA MATO O 21 P0 4 SCK CAPO 1 P0 5 MISO MATO 1 P0 6 MOSI CAPO 2 24 Preliminary User Manual LPC2106 2105 2104 P0 11 CTS1 CAP1 1 P0 10 RTS1 CAP1 0 P0 24 PIPESTAT1 P0 23 PIPESTATO P0 22 TRACECLK Vss3 P0 9 RxD1 PWM6 P0 8 TxD1 PWM4 P0 7 SSEL PWM2 DBGSEL RTCK NC September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 LPC2106 2105 2104 PIN FUNCTIONS Table 45 Pin description for LPC2106 2105 2104 Function Group DBGSEL and RTCK Override Pin Name Default Function Alternate Function 1 14 SCL CAPO 0 Timer 0 18 SCK CAPO0 1 Timer 0 22 MISO MATO 1 Timer 0 23 MOSI CAPO 2 Timer 0 24 SSEL 28 UART1 29 30 35 36 CAP1 0 Timer 1 CAP1 1 Timer 1 MAT1 0 Timer 1 MAT1 1 Timer 1 EINT1 EINT2 CAP1 2 Timer 1 CAP1 3 Timer 1 MAT1 2 Timer 1 MAT1 3 Timer 1 DBGSEL RTCK TRACECLK PIPESTATO PIPESTAT1 PIPESTAT2 TRACESYNC TRACEPKTO TRACEPKT1 TRACEPKT2 TRACEPKT3 EXTINO Pin Configuration 72 September 17 2003 Philips Semiconductors ARM based Microcontroller Preliminary User Manual LPC2106 2105 2104 1 There must be a low level at the DBGSEL input for normal operation The DBGSEL pin has a built in pulldown that will prov
35. RR RR RR B 158 Register Description oed eae oT wu wet eI ee AAA eeu os 158 RTE Interrupts its saws whe be GS E edy EE 160 Miscellaneous Register Group 0 eect tenet m n 161 Consolidated Time Registers ooocococcccccn n 164 Time Counter Group v cene Ere AAA Sea a eee AA 166 Alarm Register Group oooocccococc m mer 167 RTG Usage Notes uidet pri e nae M EU a ees gc a fe i nce e Maa 167 Reference Clock Divider Prescaler ooococoococoococo I 168 Watchdogs ns io ct iS ire ace ee A ieu SEE Meli xS ES TS 171 O DE 171 Applications tis ibs ne Se ee a i ee pM EI TR EO ee e es a 171 De SCrIPUON conta E 171 Register Description isca stene prenns RR no a 172 Block Diagram 2 ai ee ak ERVA UR DECR RO Je 175 Flash Memory System and Programming 00200s cece eee eens 177 Flash Memory System ica Hehe p UC RR RT ANA 177 Flash boot Loader cree ree ek Septet eem Y cb re e ee 177 Eeat les s yey ake wee eu A ie AAA ePi CI EV EROS 177 Applicatioris amp zu E ROUEN xe LEER Rp EET A 177 DO SCrIPUON sia fied x debe edu Bee ewe ak Sees Peele aS ele ae Al ghee early 177 Boot process FlowChart 0 0c cette eee 182 SectordN mb 6ts er tden a ae ee DURS we A le aes we 183 JTAG FLASH Programming interface 0 0 cect een 199 EmbeddedIlCE Logic tii dla 201 Eeat les cvs E RR 201 joe per EE 201 Description s omi Ree A AA A o RC REEF 201 Pin Description se a AAA A ge A d e aderit ee n 202 Register Descri
36. Raw Interrupt Status Register VICRawlntr OxFFFFF008 Read Only This register reads out the state of the 32 interrupt requests and software interrupts regardless of enabling or classification Table 33 Raw Interrupt Status Register VICRawintr OxFFFFFO08 Read Only ViCRawintr Function Reset Value 1 the interrupt request or software interrupt with this bit number is asserted 0 0 the interrupt request or software interrupt with this bit number is negated 31 0 Vectored Interrupt Controller VIC 64 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Interrupt Enable Register VICIntEnable OxFFFFF010 Read Write This register controls which of the 32 interrupt requests and software interrupts contribute to FIQ or IRQ Table 34 Interrupt Enable Register VICINtEnable OXFFFFF010 Read Write VICIntEnable Function Reset Value When this register is read 1s indicate interrupt requests or software interrupts that are enabled to contribute to FIQ or IRQ When this register is written ones enable interrupt requests or software interrupts to contribute to FIQ or IRQ zeroes have no effect See the VICIntEnClear register Table 46 below for how to disable interrupts 31 0 Interrupt Enable Clear Register VICIntEnClear OXFFFFF014 Write Only This register allows software to clear one or more bits in the Interrupt Enable register without
37. SPI Clock Counter Register SPCCR 0xE002000C Function Description Counter SPI Clock counter setting SPI Interface 129 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 The SPI rate may be calculated as PCLK rate SPCCR value The pclk rate is CCLK VPB divider rate as determined by the VPBDIV register contents SPI Interrupt Register SPINT 0xE002001C This register contains the interrupt flag for the SPI interface Table 104 SPI Interrupt Register SPINT 0xE002001C Function Description SPI interrupt flag Set by the SPI interface to generate an interrupt Cleared by writing SPI Interrupt a 1 to this bit Reserved user software should not write ones to reserved bits The value read from 7 1 Reserved A NA a reserved bit is not defined SPI Interface 130 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 ARCHITECTURE The block diagram of the SPI is shown in the Figure 27 MOSI in MOSI out MISO in MISO out SPI Shift Register lt lt Be I SPI Clock Generator amp Detector SPI Interrupt SPI Register Interface Y VPB Bus gt SPI State Control n SCK_out_en MOSI_out_en MISO_out_en Figure 27 SPI Block Diagram SPI Interface 131 Sept
38. Software can turn memory access acceleration on or off at any time This allows most of an application to be run at the highest possible performance while certain functions can be run at a somewhat slower but more predictable rate if more precise timing is required REGISTER DESCRIPTION All registers regardless of size are on word address boundaries Details of the registers appear in the description of each function Table 27 Summary of System Control Registers Address Description Access MAM Memory Accelerator Module Control Register Determines the MAM OxEO1FCO000 MAMCR functional mode that is to what extent the MAM performance R W enhancements are enabled See Table 28 OxEO1FCOO4 MAMTIM Memory Accelerator Module Timing control Determines the number of R W 0x07 clocks used for Flash memory fetches 1 to 7 processor clocks Reset Value refers to the data stored in used bits only It does not include reserved bits content Memory Accelerator Module MAM 58 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 MAM Control Register MAMCR 0xE01FC000 Two configuration bits select the three MAM operating modes as shown in Table 28 Following Reset MAM functions are disabled Changing the MAM operating mode causes the MAM to invalidate all of the holding latches resulting in new reads of Flash information as required Table 28 MAM Control Register
39. Table 1 LPC2106 2105 2104 Registers Address Jem Offset Description Access Watchdog OxE000000C WDTV timer value 32 bit data RO register Timer 0 oxE0004000 TOIR TO Interrupt CR2 CR1 CRO MR3 MR2 MR1 MRO R W Register Int Int Int Int Int Int Int 0xE0004004 ToTcR 1 Control CTR STR aw Register Enable Reset 0xE0004008 TOTC 32 bit data oxE000400c ToPR I Prescale 32 bit data R W Register oxE0004010 Topc 10 Prescale 32 bit data R W Counter Stop Reset Stop Int on 4 reserved bits on on MR3 on TO Match MR3 MR3 MR2 0xE0004014 TOMCR Control R W Register dh Stop Reset inton Stop Reset icon on on on on MR1 MP MRO ue oxE0004018 Tomro 19 Match 32 bit data R W Register O 0xE000401C Tomr1 10 Match 32 bit data R W Register 1 oxE0004020 Tomre 19 Match 32 bit data R W Register 2 oxE0004024 ToMRa 19 Match 32 bit data R W Register 3 it Int on 7 reserved bits TO Capture 0000 wos os 0xE0004028 TOCCR Control Int on Int on Int on Int on R W Register Cpt 2 Cpt 2 Cpt 1 Cpt 0 falling rising falling falling oxE000402c rocRo T0 Capture 32 bit data Register O oxE0004030 TocR1 I9 Capture 32 bit data Register 1 0xE0004034 Tocre I9 Capture 32 bit data Register 2 Introduction 20 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Table 1 LPC2106 2105 2104 Reg
40. Table 42 Vector Address Register VICVectAddr OXFFFFF030 Read Write VICVectAddr Function Reset Value If any of the interrupt requests or software interrupts that are assigned to a vectored IRQ slot is are enabled classified as IRQ and asserted reading from this register returns the address in the Vector Address Register for the highest priority such slot Otherwise it returns the address in the Default Vector Address Register Writing to this register does not set the value for future reads from it Rather this register should be written near the end of an ISR to update the priority hardware Protection Enable Register VICProtection OXFFFFF020 Read Write This one bit register controls access to the VIC registers by software running in User mode Table 43 Protection Enable Register VICProtection OXFFFFF020 Read Write VICProtection Function Reset Value 1 the VIC registers can only be accessed in privileged mode 0 0 VIC registers can be accessed in User or privileged mode 0 Vectored Interrupt Controller VIC 67 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 INTERRUPT SOURCES Table 37 lists the interrupt sources for each peripheral function Each peripheral device has one interrupt line connected to the Vectored Interrupt Controller but may have several internal interrupt flags Individual interrupt flags may also represent
41. The interrupt is cleared upon an UOLSR read The UARTO RDA interrupt UOIIR3 1 010 shares the second level priority with the CTI interrupt UOIIR3 1 110 The RDA is activated when the UARTO Rx FIFO reaches the trigger level defined in UOFCR7 6 and is reset when the UARTO Rx FIFO depth falls below the trigger level When the RDA interrupt goes active the CPU can read a block of data defined by the trigger level The CTI interrupt UOIIR3 12110 is a second level interrupt and is set when the UARTO Rx FIFO contains at least one character and no UARTO Rx FIFO activity has occurred in 3 5 to 4 5 character times Any UARTO Rx FIFO activity read or write of UARTO RSR will clear the interrupt This interrupt is intended to flush the UARTO RBR after a message has been received that is not a multiple of the trigger level size For example if a peripheral wished to send a 105 character message and the trigger level was 10 characters the CPU would receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5 CTI interrupts depending on the service routine resulting in the transfer of the remaining 5 characters Table 65 UARTO Interrupt Handling Interrupt Interrupt Interrupt UOIIR 3 0 Priority Type Source Reset 0001 none 0110 Highest P 25 OE or PE or FE or BI UOLSR Read UORBR Read or 0100 Second PX Pata Rx data available or trigger level reached in FIFO UOFCRO 1 VARTO FIFO Available drops below trigger level
42. Therefore data should only be written to this register when a transmit is not currently in progress Read data is buffered When a transfer is complete the receive data is transferred to a single byte data buffer where it is later read A read of the SPI data register returns the value of the read data buffer The SPI clock counter register controls the clock rate when the SPI block is in master mode This needs to be set prior to a transfer taking place when the SPI block is a master This register has no function when the SPI block is a slave The I Os for this implementation of SPI are standard CMOS I Os The open drain SPI option is not implemented in this design When a device is set up to be a slave its I Os are only active when it is selected by the SSEL signal being active Master Operation The following sequence describes how one should process a data transfer with the SPI block when it is set up to be the master This process assumes that any prior data transfer has already completed Set the SPI clock counter register to the desired clock rate Set the SPI control register to the desired settings Write the data to transmitted to the SPI data register This write starts the SPI data transfer Wait for the SPIF bit in the SPI status register to be set to 1 The SPIF bit will be set after the last cycle of the SPI data transfer Rony 5 Read the SPI status register 6 Read the received data from the SPI data register o
43. This register provides the value of the GPIO pins This value reflects any outside world influence on the pins Note for test purposes writing to this register stores the value in the output register bypassing the need to use both the IOSET and IOCLR registers This feature is of little or no use in an application because it is not possible to write to individual bytes in this register Table 53 GPIO Pin Value Register IOPIN 0xE0028000 Value after Description Reset GPIO pin value bits Bit O corresponds to P0 0 Bit 31 corresponds to P0 31 Undefined GPIO Output Set Register IOSET 0xE0028004 This register is used to produce a HIGH level output at the port pins if they are configured as GPIO in an OUTPUT mode Writing 1 produces a HIGH level at the corresponding port pins Writing O has no effect If any pin is configured as an input or a secondary function writing to IOSET has no effect Reading the IOSET register returns the value in the GPIO output register as determined by previous writes to IOSET and IOCLR or IOPIN as noted above This value does not reflect the effect of any outside world influence on the I O pins Table 54 GPIO Output Set Register IOSET 0xE0028004 Value after Description Reset Output value SET bits Bit O corresponds to P0 0 Bit 31 corresponds to P0 31 0 GPIO Output Clear Register IOCLR 0xE002800C This register is used to produce a LOW level at port pins if
44. UTLSR read clears U1LSR1 OE U1LSR1 is set when UART1 RSR has a new character assembled and the UART1 RBR FIFO is full In this case the UART1 RBR FIFO will not be overwritten and the character in the UART1 RSR will be lost 0 Parity error status is inactive 1 Parity error status is active Parity Error PE When the parity bit of a received character is in the wrong state a parity error occurs An U1LSR read clears U1LSR2 Time of parity error detection is dependent on U1FCRO A parity error is associated with the character being read from the UART1 RBR FIFO 0 Framing error status is inactive 1 Framing error status is active When the stop bit of a received character is a logic 0 a framing error occurs An U1LSR read clears this bit The time of the framing error detection is dependent on U1FCRO A framing error is associated with the character being read from the UART1 RBR FIFO Upon detection of a framing error the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit Framing Error FE 0 Break interrupt status is inactive 1 Break interrupt status is active When RxD1 is held in the spacing state all 0 s for one full character transmission start Break Interrupt data parity stop a break interrupt occurs Once the break condition has been detected Bl the receiver goes idle until RxD1 goes to marking state all 1 s An U1LSR read clears this status
45. User Manual LPC2106 2105 2104 Processor Clock cclk VPB Clock pclk September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 WAKEUP TIMER The purpose of the wakeup timer is to ensure that the oscillator and other analog functions required for chip operation are fully functional before the processor is allowed to execute instructions This is important at power on all types of Reset and whenever any of the aforementioned functions are turned off for any reason Since the oscillator and other functions are turned off during Power Down mode any wakeup of the processor from Power Down mode makes use of the Wakeup Timer The Wakeup Timer monitors the crystal oscillator as the means of checking whether it is safe to begin code execution When power is applied to the chip or some event caused the chip to exit Power down mode some time is required for the oscillator to produce a signal of sufficient amplitude to drive the clock logic The amount of time depends on many factors including the rate of Vdd ramp in the case of power on the type of crystal and its electrical characteristics if a quartz crystal is used as well as any other external circuitry e g capacitors and the characteristics of the oscillator itself under the existing ambient conditions Once a clock is detected the Wakeup Timer counts 4096 clocks then enables the Flash memory to initialize When the Fla
46. and the slave always sends a byte of data to the master SPI Data Transfers Figure 26 is a timing diagram that illustrates the four different data transfer formats that are available with the SPI This timing diagram illustrates a single 8 bit data transfer The first thing one should notice in this timing diagram is that it is divided into three horizontal parts The first part describes the SCK and SSEL signals The second part describes the MOSI and MISO signals when the CPHA variable is 0 The third part describes the MOSI and MISO signals when the CPHA variable is 1 In the first part of the timing diagram note two points First the SPI is illustrated wit CPOL set to both 0 and 1 The second point to note is the activation and de activation of the SSEL signal When CPHA 1 the SSEL signal will always go inactive between data transfers This is not guaranteed when CPHA 0 the signal can remain active SPI Interface 123 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 SCK CPOL 0 jt Ac SP ea aoe es wee SCK CPOL 1 P eae hee ee a hy SsEL A CPHA 0 Cycle CPHA 0 W 1X 2 X 3 X 4 X5X 6 X 7X 8 Am MOSI CPHA 0 Bit 1 XBit2 Xbits X Bit4 Bits XBite Bit Bro MUY MISO CPHA 0 Bit 1 XBit2 XBita X Bit4 XBits Bite Bit X Bite MB CPHA 1 Cycle CPHA 1 EB xe X aX aX 5X6x7 Xx MOSI CPHA 1 Misi pio XBit3 Bia XBit5 XBite XBit7
47. capable of generating an interrupt reset Until then the Watchdog will ignore feed errors Once OxAA is written to the WDFEED register the next operation in the Watchdog register space should be a WRITE 0x55 to the WDFFED register otherwise the Watchdog is triggered The interrupt reset will be generated during the second pelk following an incorrect access to a watchdog timer register during a feed sequence Table 139 Watchdog Feed Register WDFEED 0xE0000008 Reset Value 7 0 Feed Feed value should be OxAA followed by 0x55 undefined WDFEED Function Description Watchdog Timer Value Register WDTV 0xE000000C The WDTV register is used to read the current value of Watchdog timer Table 140 Watchdog Timer Value Register WDTV 0xE000000C Function Description Count Current timer value Watchdog 174 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 BLOCK DIAGRAM The block diagram of the Watchdog is shown below in the Figure 35 FEED ERROR FEED SEQUENCE WDFEED FEED OK ENABLE COUNT WDTV CURRENT WD REGISTER TIMER COUNT WDMOD REGISTER 1 Counter is enabled only when the WDEN bit is set and a valid feed sequence is done 2 WDEN and WDRESET are sticky bits Once set they can t be cleared until the Watchdog underflows INTERRUPT or an external reset occurs Figure 35 Watchdog Bloc
48. capture 3 Timer 1 only When one a sequence of 1 then 0 on capture 3 will cause CR3 falling edge to be loaded with the contents of TC When zero this feature is disabled Interrupt on capture 3 Timer 1 only When one a CR3 load due to a capture 3 event will generate an event interrupt When zero this feature is disabled 7 10 1 1 Timer O and Timer 1 138 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 External Match Register EMR Timer 0 TOEMR 0xE000403C Timer 1 T1EMR 0xE000803C The External Match Register provides both control and status of the external match pins M 0 3 Table 111 External Match Register EMR Timer 0 TOEMR 0xE000403C Timer 1 TTEMR 0xE000803C Function Description This bit reflects the state of output MATO 1 whether or not this output is connected External Match O to its pin When a match occurs for MRO this output of the timer can either toggle go low go high or do nothing Bits EMR 4 5 control the functionality of this output This bit reflects the state of output MATO 1 whether or not this output is connected External Match 1 to its pin When a match occurs for MR1 this output of the timer can either toggle go low go high or do nothing Bits EMR 6 7 control the functionality of this output This bit reflects the state of output MATO 1 whether or not this output is connected External Match 2
49. exception sharing they must provide function such as app IRQDispatch Depending on the nature of the exception this handler can either pass control to the RealMonitor processing routine such as rm irghandler2 claim the exception for the application itself such as app IRQHandler In a simple case where an application has no exception handlers of its own the application can install the RealMonitor low level exception handlers directly into the vector table of the processor Although the irq handler must get the address of the Vectored Interrupt Controller The easiest way to do this is to write a branch instruction address into the vector table where the target of the branch is the start address of the relevant RealMonitor exception handler Reset y Real Monitor supplied exception vector handlers Undef rm_undef_handler rm_prefetchabort_handler rm dataabort hanaler SWI rm irghandler Prefetch Abort Sharing irgs between RealMonitor and User IRQ handler Data Abort rm irghandler2 app irqDispatch 9 Reserved IRQ App IRQHandler Figure 46 Exception Handlers RealMonitor 216 September 17 2003 Preliminary User Manual LPC2106 2105 2104 Philips Semiconductors ARM based Microcontroller RMTarget initialization While the processor is in a privileged mode and IRQs are disabled user
50. flag is set when the Watchdog times out This flag is cleared when any reset occurs Table 138 Watchdog Mode Register WDMOD 0xE0000000 WDMOD Function Description Reset Value 0 WDEN Watchdog interrupt enable bit Set only 0 WDRESET Watchdog reset enable bit Set Only 09 WDTOF Watchdog time out flag bis an WDINT Watchdog interrupt flag Read Only BEEN Reserved user software should not write ones to reserved bits The value read 7 4 Reserved acia NA from a reserved bit is not defined Watchdog Timer Constant Register WDTC 0xE0000004 The WDTC register determines the time out value Every time a feed sequence occurs the WDTC content is reloaded in to the Watchdog timer It s a 32 bit register with 8 LSB set to 1 on reset Writing values below OxFF will cause OxFF to be loaded to the WDTC Thus the minimum time out interval is tpg x 256 x 4 Function Description Count Watchdog time out interval Watchdog 173 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Watchdog Feed Register WDFEED 0xE0000008 Writing OxAA followed by 0x55 to this register will reload the Watchdog timer to the WDTC value This operation will also start the Watchdog if it is enabled via the WDMOD register Setting the WDEN bit in the WDMOD register is not sufficient to enable the Watchdog A valid feed sequence must first be completed before the Watchdog is
51. for details Clock Tick Counter Real Time Clock 161 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Clock Control Register CCR 0xE0024008 The clock register is a 4 bit register that controls the operation of the clock divide circuit Each bit of the clock register is described in Table 125 Table 125 Clock Control Register Bits CCR 0xE0024008 Function Description Clock Enable When this bit is a one the time counters are enabled When it is a zero they are disabled so that they may be initialized CTC Reset When one the elements in the Clock Tick Counter are reset The elements remain CTCRST reset until CCR 1 is changed to zero 3 2 CTTEST Test Enable These bits should always be zero during normal operation Counter Increment Interrupt 0 4 The Counter Increment Interrupt Register CIIR gives the ability to generate an interrupt every time a counter is incremented This interrupt remains valid until cleared by writing a one to bit zero of the Interrupt Location Register ILR O Table 126 Counter Increment Interrupt Register Bits CIIR OXE002400C Function Description IMSEC When one an increment of the Second value generates an interrupt IMMIN When one an increment of the Minute value generates an interrupt IMHOUR When one an increment of the Hour value generates an interrupt IMDOM When one an increment of the Day
52. having to first read it Table 35 Software Interrupt Clear Register VICIntEnClear OXFFFFF014 Write Only VICIntEnClear Function Reset Value 1 writing a 1 clears the corresponding bit in the Interrupt Enable register thus disabling 31 0 interrupts for this request 0 writing a O leaves the corresponding bit in VICIntEnable unchanged Interrupt Select Register VICIntSelect OXFFFFFOOC Read Write This register classifies each of the 32 interrupt requests as contributing to FIQ or IRQ Table 36 Interrupt Select Register VICIntSelect OxFFFFFOOC Read Write VICIntSelect Function Reset Value 1 the interrupt request with this bit number is assigned to the FIQ category 0 the interrupt request with this bit number is assigned to the IRQ category 31 0 0 IRQ Status Register VICIRQStatus OXFFFFF000 Read Only This register reads out the state of those interrupt requests that are enabled and classified as IRQ It does not differentiate between vectored and non vectored IRQs Table 37 IRQ Status Register VICIRQStatus OXFFFFF000 Read Only VICIRQStatus Function Reset Value 31 0 1 the interrupt request with this bit number is enabled classified as IRQ and asserted 0 Vectored Interrupt Controller VIC 65 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 FIQ Status Register VICFIQStatus OXFFFFF004 Read Only Thi
53. interrupt is pending Interrupt 1 No pending interrupts Pending Note that UOIIRO is active low The pending interrupt can be determined by evaluating UOIER3 1 011 1 Receive Line Status RLS 010 2a Receive Data Available RDA Interrupt 110 2b Character Time out Indicator CTI Identification 001 3 THRE Interrupt UOIERS identifies an interrupt corresponding to the UARTO Rx FIFO All other combinations of UOIER3 1 not listed above are reserved 000 100 101 111 Reserved user software should not write ones to reserved bits The value read from a 5 Reserved is NA reserved bit is not defined 4 7 6 FIFO Enable These bits are equivalent to UOFCRO Interrupts are handled as described in Table 65 Given the status of UOIIR 3 0 an interrupt handler routine can determine the cause of the interrupt and how to clear the active interrupt Interrupts are handled as described in Table 65 The UOIIR must be read in order to clear the interrupt prior to exitting the Interrupt Service Routine UART 0 88 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 The UARTO RLS interrupt UOIIR3 1201 1 is the highest priority interrupt and is set whenever any one of four error conditions occur on the UARTO Rx input overrun error OE parity error PE framing error FE and break interrupt Bl The UARTO Rx error condition that set the interrupt can be observed via UOLSR4 1
54. is enabled classified as IRQ and asserted Vector Address Registers 0 15 VICVectAddr0 15 OXFFFFF100 13C Read Write These registers hold the addresses of the Interrupt Service routines ISRs for the 16 vectored IRQ slots Table 40 Vector Address Registers VICVectAddr0 15 OXFFFFF100 13C Read Write VICVectAddr0 15 Function Reset Value When one or more interrupt request or software interrupt is are enabled classified as IRQ asserted and assigned to an enabled vectored IRQ slot the value from this register for the highest priority such slot will be provided when the IRQ service routine reads the Vector Address register VICVectAddr 31 0 Default Vector Address Register VICDefVectAddr OxFFFFF034 Read Write This register holds the address of the Interrupt Service routine ISR for non vectored IRQs Table 41 Default Vector Address Register VICDefVectAddr OxFFFFF034 Read Write VICDefVectAddr Function Reset Value When an IRQ service routine reads the Vector Address register VICVectAddr and no IRQ slot responds as described above this address is returned 31 0 0 Vectored Interrupt Controller VIC 66 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Vector Address Register VICVectAddr OxFFFFF030 Read Write When an IRQ interrupt occurs the IRQ service routine can read this register and jump to the value read
55. is illustrated in Figure 44 The target component of RealMonitor RMTarget communicates with the host component RMHost using the Debug Communications Channel DCC which is a reliable link whose data is carried over the JTAG connection While user application is running RMTarget typically uses IRQs generated by the DCC This means that if user application also wants to use IRQs it must pass any DCC generated interrupts to RealMonitor To allow nonstop debugging the EmbeddedICE RT logic in the processor generates a Prefetch Abort exception when a breakpoint is reached or a Data Abort exception when a watchpoint is hit These exceptions are handled by the RealMonitor exception handlers that inform the user by way of the debugger of the event This allows user application to continue running without stopping the processor RealMonitor considers user application to consist of two parts aforeground application running continuously typically in User System or SVC mode a background application containing interrupt and exception handlers that are triggered by certain events in user system including IRQs or FIQs Data and Prefetch aborts caused by user foreground application This indicates an error in the application being debugged In both cases the host is notified and the user application is stopped Undef exception caused by the undefined instructions in user foreground application This indicates an error in the applicat
56. just the Day of Year value Table 130 Consolidated Time Register 2 Bits CTIME2 0xE002401C CTIME2 Function Description 11 0 Day of Year Day of year value in the range of 1 to 365 366 for leap years f Reserved user software should not write ones to reserved bits The value read from a reserved 31 12 Reserved ae bit is not defined Real Time Clock 165 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 TIME COUNTER GROUP The time value consists of the eight counters shown in Tables 131 and 132 These counters can be read or written at the locations shown in Table 132 Table 131 Time Counter Relationships and Values Counter Enabled by Min value Maximum value I 4 CIk1 see Figure 33 59 Wwe c sew v 9 me s Ww v 5 Lowswe 3 mw 5 RA emnt ra 9 8 Table 132 Time Counter registers Address Name Description Access 0xE0024020 SEC Seconds value in the range of 0 to 59 R W 0xE0024024 MIN i gee Minutes value in the range of 0 to 59 R W 0xE0024028 HOUR Hours value in the range of 0 to 23 R W OxE002402C DOM 5 Day of month value in the range of 1 to 28 29 30 or 31 depending R W on the month and whether it is a leap year 0xE0024030 DOW Day of week value in the range of 0 to 6 R W 0xE0024034 DOY m WS Day of year value in the range of 1 to 365 366 for leap years RAN 0xE002
57. master transmitter mode master receiver mode slave transmitter mode and slave receiver mode 12C Interface 111 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 B SDA SCL Other Device with I2C Other Device with 12C LPC2106 2105 2104 Interface Interface Figure 17 I C Bus Configuration C Operating Modes Master Transmitter Mode In this mode data is transmitted from master to slave Before the master transmitter mode can be entered I2CONSET must be initialized as shown in Figure 18 I2EN must be set to 1 to enable the 12C function If the AA bit is 0 the 12C interface will not acknowledge any address when another device is master of the bus so it can not enter slave mode The STA STO and SI bits must be 0 The SI Bit is cleared by writing 1 to the SIC bit in the I2CONCLR register I2CONSET Figure 18 Slave Mode Configuration The first byte transmitted contains the slave address of the receiving device 7 bits and the data direction bit In this mode the data direction bit RAW should be O which means Write The first byte transmitted contains the slave address and Write bit Data is transmitted 8 bits at a time After each byte is transmitted an acknowledge bit is received START and STOP conditions are output to indicate the beginning and th
58. mode fault MODF bit in the status register will be activated the SPI signal drivers will be de activated and the SPI mode will be changed to be a slave Slave Abort A slave transfer is considered to be aborted if the SSEL signal goes inactive before the transfer is complete In the event of a slave abort the transmit and receive data for the transfer that was in progress are lost and the slave abort ABRT bit in the status register will be activated SPI Interface 126 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 PIN DESCRIPTION Table 98 SPI Pin Description Pin Name Pin Description Serial Clock The SPI is a clock signal used to synchronize the transfer of data across the SPI SCK interface The SPI is always driven by the master and received by the slave The clock is programmable to be active high or active low The SPI is only active during a data transfer Any other time it is either in its inactive state or tri stated Slave Select The SPI slave select signal is an active low signal that indicates which slave is currently selected to participate in a data transfer Each slave has its own unique slave select signal input The SSEL must be low before data transactions begin and normally stays low for SSEL Input the duration of the transaction If the SSEL signal goes high any time during a data transfer the transfer is considered to be aborted In this e
59. more than one interrupt source Table 44 Connection of Interrupt Sources to the Vectored Interrupt Controller Block Flag s VIC Channel WDT Watchdog Interrupt WDINT Reserved for software interrupts only 1 ARM Core Embedded ICE DbgCommRx 2 ARM Core Embedded ICE DbgCommTx 3 Match 0 3 MRO MR1 MR2 MR3 Capture 0 3 CRO CR1 CR2 CR3 Match 0 3 MRO MR1 MR2 MR3 Capture 0 3 CRO CR1 CR2 CR3 Rx Line Status RLS Transmit Holding Register empty THRE Rx Data Available RDA Character Time out Indicator CTI Rx Line Status RLS Transmit Holding Register empty THRE Rx Data Available RDA Character Time out Indicator CTI Modem Status Interrupt MSI Match 0 6 MRO MR1 MR2 MR3 MR4 MR5 MR6 Capture 0 3 CRO CR1 CR2 CR3 SI state change Timer 0 Timer 1 PWMO SPIF MODF I P PLL Lock PLOCK RTC RTCCIF Counter Increment RTCALF Alarm System Control External Interrupt 0 EINTO System External Interrupt 1 EINT1 Control p System External Interrupt 2 EINT2 1 Control B 12C SPI LL 14 15 6 Vectored Interrupt Controller VIC 68 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 nVICFIQIN Interrupt Request Masking and Selection SoftintClear IntEnableClear 31 0 31 0 FIQStatus SoftInt IntEnable 31 0 FlOStatus 31 0 31 0 81 0 N
60. must include a line of code within the start up sequence of application to call rm_init_entry RealMonitor 217 September 17 2003 Philips Semiconductors ARM based Microcontroller Cod The vect e Example Preliminary User Manual LPC2106 2105 2104 following example shows how to setup stack VIC initialize RealMonitor and share non ored interrupts IMPORT rm init entry IMPORT rm prefetchabort handler IMPORT rm dataabort handler IMPORT rm irqhandler2 IMPORT rm undef handler IMPORT User Entry Entry point of user application CODE32 ENTRY Define exception table Instruct linker to place code at address 0x0000 0000 AREA exception table CODE LDR pc Reset Address LDR pc Undefined Address LDR pc SWI Address LDR pc Prefetch Address LDR pc Abort Address D OP Insert User code valid signature here LDR pc pc 0xFF0 Load IRQ vector from VIC LDR PC FIQ Address Reset Address DCD init Reset Entry point Undefined Address DCD rm undef handler Provided by RealMonitor SWI Address DCD 0 User can put address of SWI handler here Prefetch Address DCD rm prefetchabort handler Provided by RealMonitor Abort Address DCD rm dataabort handler Provided by RealMonitor FIQ Address DCD 0 User can put address of FIQ handler here AREA init code CODE ram end EQU 0x4000xxxx Top of on chip RAM in k it Ck ck ck Ck ck kk KKK kk ck C
61. non RealMonitor third party channel RM_OPT_STOPSTART TRUE This option enables or disables support for all stop and start debugging features RM_OPT_SOFTBREAKPOINT TRUE This option enables or disables support for software breakpoints RM_OPT_HARDBREAKPOINT TRUE Enabled for cores with EmbeddedICE RT This device uses ARM 7TDMI S Rev 4 with EmbeddedICE RT RM_OPT_HARDWATCHPOINT TRUE Enabled for cores with EmbeddedICE RT This device uses ARM 7TDMI S Rev 4 with EmbeddedICE RT RM OPT SEMIHOSTING FALSE This option enables or disables support for SWI semi hosting Semi hosting provides code running on an ARM target use of facilities on a host computer that is running an ARM debugger Examples of such facilities include the keyboard input screen output and disk I O RM OPT SAVE FIQ REGISTERS TRUE This option determines whether the FIQ mode registers are saved into the registers block when RealMonitor stops RM OPT READBYTES TRUE RM OPT WRITEBYTES TRUE RM OPT READHALFWORDS TRUE RM OPT WRITEHALFWORDS TRUE RM OPT READWORDS TRUE RM OPT WRITEWORDS TRUE Enables Disables support for 8 16 32 bit read write RM OPT EXECUTECODE FALSE Enables Disables support for executing code from execute code buffer The code must be downloaded first RM OPT GETPC TRUE This option enables or disables support for the RealMonitor GetPC packet Useful in code profiling when real monitor is used in interrupt mode RM EXECUTECODE SIZEZNA RealMonitor
62. one assertion of EINT2 will wake up the processor from Power Down mode 3 Reserved user software should not write ones to reserved bits The value read 7 Reserved e NA from a reserved bit is not defined Wakeup Enable one bit of EXTWAKE VPB Read of EXTWAKE EINTi to B Bus D XEDIBUSTIRId gt Wakeup Timer Figure 10 Interrupt Flag one bit of EXTINT to VIC VPB Read of EXTINT Reset Write 1 from VPB Bus Interface Figure 8 External Interrupt Logic System Control Block 41 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 MEMORY MAPPING CONTROL The Memory Mapping Control alters the mapping of the interrupt vectors that appear beginning at address 0x00000000 This allows code running in different memory spaces to have control of the interrupts Memory Mapping Control Register MEMMAP 0xE01FC040 Table 10 MEMMAP Register Address Name Description Access Memory mapping control Selects whether the ARM interrupt vectors are read from the Flash Boot Block User Flash or RAM SHY 0xE01FC040 MEMMAP Table 11 Memory Mapping Control Register MEMMAP 0xE01FC040 MEMMAP Function Description 00 Boot Loader Mode Interrupt vectors are re mapped to Boot Block 01 User Flash Mode Interrupt vectors are not re mapped and reside in Flash 10 User RAM Mode Interrupt vectors are re ma
63. place in order to clear the SPIF status bit Exception Conditions Read Overrun A read overrun occurs when the SPI block internal read buffer contains data that has not been read by the processor and a new transfer has completed The read buffer containing valid data is indicated by the SPIF bit in the status register being active When a transfer completes the SPI block needs to move the received data to the read buffer If the SPIF bit is active the read buffer is full the new receive data will be lost and the read overrun ROVR bit in the status register will be activated Write Collision As stated previously there is no write buffer between the SPI block bus interface and the internal shift register As a result data must not be written to the SPI data register when a SPI data transfer is currently in progress The time frame where data cannot be written to the SPI data register is from when the transfer starts until after the status register has been read when the SPIF status is active If the SPI data register is written in this time frame the write data will be lost and the write collision WCOL bit in the status register will be activated Mode Fault The SSEL signal must always be inactive when the SPI block is a master If the SSEL signal goes active when the SPI block is a master this indicates another master has selected the device to be a slave This condition is known as a mode fault When a mode fault is detected the
64. so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits standard cells and or software described or contained herein in order to improve design and or performance When the productis in full production status Production relevant changes will be communicated viaa Customer Product Process Change Notification CPCN Philips Semiconductors assumes no responsibility or liability for the use of any of these products conveys no license or title under any patent copyright or mask work right to these products and makes no representations or warranties that these products are free from patent copyright or mask work right infringement unless otherwise specified Contact information Q Koninklijke Philips Electronics N V 2003 For additional information please visit All rights reserved Printed in U S A http www semiconductors philips com Fax 31 40 27 24825 Date of release 09 03 Document order number 9397 750 12085 Lele make things beter ness S PHILIPS For sales offices addresses send e mail to sales addresses www semiconductors philips com
65. the correspondence between sector numbers and memory addresses for LPC2106 2105 2104 device s IAP ISP and RealMonitor routines are located in sector 15 boot sector The boot sector is present in all devices ISP and IAP commands do not allow write erase go operation on the boot sector In a device having 128K of Flash only 120K is available for the user program Table 141 Sectors in a device with 128K bytes of Flash Sector Number Memory Addresses 0x0001 2000 3FFF 0x0001 4000 5FFF 11 0x0B 0x0001 6000 7FFF 12 0x0C 0x0001 8000 9FFF 0x0D 0x0001 0000 1FFF 0 Ox0A 13 0x0D 0x0001 A000 BFFF 14 Ox0E 0x0001 C000 DFFF 15 0x0F 0x0001 E000 FFFF Flash Memory System and Programming 183 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 ISP Commands The following commands are accepted by the ISP command handler Detailed return codes are supported for each command The command handler sends the return code INVALID_ COMMAND when an undefined command is received Commands and return codes are in ASCII format CMD SUCCESS is sent by ISP command handler only when received ISP command has been completely executed and the new ISP command can be given by the host Exceptions from this rule are Set Baud Rate Write to RAM Read Memory and Go commands Table 142 ISP Command Summary ISP Command Usage Described in Unlock U
66. the desired processor operating frequency cclk This may be based on processor throughput requirements need to support a specific set of UART baud rates etc Bear in mind that peripheral devices may be running from a lower clock than the processor see the VPB Divider description in this chapter 2 Choose an oscillator frequency Fosp cclk must be an even multiple of Fose 3 Calculate the value of M to configure the MSEL bits M cclk Fose M must be in the range of 1 to 32 The value written to the MSEL bits in PLLCFG is M 1 see Table 19 4 Find a value for P to configure the PSEL bits such that Feco is within its defined frequency limits Figo is calculated using the equation given above P must have one of the values 1 2 4 or 8 The value written to the PSEL bits in PLLCFG is 00 for P 2 1 01 for P 2 2 10 for P 4 11 for P 2 8 see Table 18 Table 18 PLL Divider Values PSEL Bits PLLCFG bits 6 5 vais ere 00 DCI CI Table 19 PLL Multiplier Values MSEL Bits PLLCFG bits 4 0 Value ot M 00000 00011 System Control Block 48 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 POWER CONTROL The LPC2106 2105 2104 supports two reduced power modes Idle mode and Power Down mode In ldle mode execution of instructions is suspended until either a Reset or interrupt occurs Peripheral functions continue operation during Idle mode and
67. will clear all bytes in UART1 Rx FIFO and reset the pointer logic This bit is self clearing Tx FIFO Reset Writing a logic 1 to U1 FCR2 will clear all bytes in UART1 Tx FIFO and reset the pointer logic This bit is self clearing before an interrupt is activated The four trigger levels are defined by the user at compilation allowing the user to tune the trigger levels to the FIFO depths chosen 0 Reserved user software should not write ones to reserved bits The value read from a Reserved ED NA reserved bit is not defined 00 trigger level O default h1 01 trigger level 1 default n4 10 trigger level 2 default h8 7 6 ps Ei 11 trigger level 3 default he These two bits determine how many receiver UART1 FIFO characters must be written UART 1 103 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 UART1 Line Control Register U1LCR 0xE001000C The U1LCR determines the format of the data character that is to be transmitted or received Table 80 UART1 Line Control Register Bit Descriptions U1LCR 0xE001000C Reset Function Description Value 00 5 bit character length Word Length 01 6 bit character length Select 10 7 bit character length 11 8 bit character length 0 1 stop bit Stop Bit Select 2 Stop bits 1 5 if UILCR 1 0 00 0 Disable parity generation and checking Panty Enable 1 Enable parity generation and c
68. 0072A Also used during entry into debug mode EmbeddedICE Logic 202 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 REGISTER DESCRIPTION The EmbeddedICE logic contains 16 registers as shown in Table 168 below The ARM7TDMI S debug architecture is described in detail in ARM7TDMI S rev 4 Technical Reference Manual ARM DDI 0234A published by ARM Limited and is available via Internet at http www arm com Table 168 EmbeddedICE Logic Registers Address Name Description 00000 Debug Control Force debug state disable interrupts 00001 5 Debug status Status of debug 00100 32 Debug comms Sonig Debug communication control register Register 01100 01101 10000 oo s Wamon Cento Vale Ra watt habs 32 32 32 32 32 32 32 32 E ENT EO E EE BONN NEI ULOIGLILIILI 1 MEN RC fae ae RU EON EN EmbeddedICE Logic 203 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 BLOCK DIAGRAM The block diagram of the debug environment is shown below in Figure 40 Serial JTAG PORT Parallel EmbeddedICE Interface Protocol EmbeddedlCE Converter Bn oa oO HOST RUNNING i DEBUGGER ARM7TDMI S TARGET BOARD Figure 40 EmbeddedICE Debug Environment Block Diag
69. 014 Reset Function Description Value When one an interrupt is generated when MRO matches the value in the TC When zero this interrupt is disabled 1 Reset on MRO When one the TC will be reset if MRO matches it When zero this feature is disabled Stop on MRO When one the TC and PC will be stopped and TCR 0 will be set to 0 if MRO matches P the TC When zero this feature is disabled When one an interrupt is generated when MR1 matches the value in the TC When Interrupt on MR1 aes zero this interrupt is disabled Reset on MR1 When one the TC will be reset if MR1 matches it When zero this feature is disabled 0 Interrupt on MRO 0 Reset on MR2 When one the TC will be reset if MR2 matches it When zero this feature is disabled Stop on MR1 When one the TC and PC will be stopped and TCR O will be set to 0 if MR1 matches P the TC When zero this feature is disabled Stop on MR2 When one the TC and PC will be stopped and TCR O will be set to 0 if MR2 matches P the TC When zero this feature is disabled When one an interrupt is generated when MR2 matches the value in the TC When Interrupt on MR2 on UM zero this interrupt is disabled When one an interrupt is generated when MR3 matches the value in the TC When Interrupt on MR3 dis zero this interrupt is disabled 0 Reset on MR3 When one the TC will be reset if MR3 matches it When zero this feature is disabled T Stop on MR3 When one the TC and PC will be stopp
70. 106 Timer 0 and Timer 1 Register Map p Reset Address amp Address amp Description Access Value Interrupt Register The IR can be written to clear interrupts The IR 0xE0004000 0xE0008000 Can be read to identify which of eight Timer 1 or seven Timer 0 R W 0 possible interrupt sources are pending Timer Control Register The TCR is used to control the Timer MAE MOD PO Counter functions The Timer Counter can be disabled or reset RAN through the TCR TC 0xE0004008 0xE0008008 Timer Counter The 32 bit TC is incremented every PR 1 cycles of BW TOTC T1TC pclk The TC is controlled through the TCR OxE000400C OxE000800C Prescale Register The TC is incremented every PR 1 cycles of R W TOPR T1PR pclk Prescale Counter The 32 bit PC is a counter which is incremented 0x5 0004010 AE 0008010 to the value stored in PR When the value in PR is reached the TC R W is incremented MCR 0xE0004014 0xE0008014 Match Control Register The MCR is used to control if an interrupt R W TOMCR T1MCR is generated and if the TC is reset when a Match occurs Match Register 0 MRO can be enabled through the MCR to reset 0xE0004018 0xE0008018 the TC stop both the TC and PC and or generate an interrupt R W every time MRO matches the TC E DIAS Match Register 1 See MRO description RW oo 0xE0004020 0xE0008020 TOMR2 T1MR2 Match Register 2 See MRO description o 0xE0004024 0xE0008024 as MR3 TOMR3 T1MR3 Match Register 3 See MRO de
71. 127 MAM fetch cycles are 7 processor clocks cclks in duration Warning Improper setting of this value may result in incorrect operation of the device Reserved user software should not write ones to reserved bits The value read from a 7 3 Reserved A A NA reserved bit is not defined MAM USAGE NOTES When changing MAM timing the MAM must first be turned off by writing a zero to MAMCR A new value may then be written to MAMTIM Finally the MAM may be turned on again by writing a value 1 or 2 corresponding to the desired operating mode to MAMCR For system clock slower than 20 MHz MAMTIM can be 001 For system clock between 20 MHz and 40 MHz Flash access time is suggested to be 2 CCLKs while in systems with system clock faster than 40 MHz 3 CCLKs are proposed Memory Accelerator Module MAM 59 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Memory Accelerator Module MAM 60 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 5 VECTORED INTERRUPT CONTROLLER VIC FEATURES ARM PrimeCell Vectored Interrupt Controller 32 interrupt request inputs 16 vectored IRQ interrupts 16 priority levels dynamically assigned to interrupt requests Software interrupt generation DESCRIPTION The Vectored Interrupt Controller VIC takes 32 interrupt request inputs and programmably assigns the
72. 13 Set and Reset inputs for PWM Flip Flops lssseeeee RII 146 Table 114 Pin s mmlaty sr ruere A vC Ai epi A ee AR 148 Table 115 Pulse Width Modulator Register Map 0 eee II 149 Table 116 PWM Interrupt Register PWMIR 0xE0014000 oooooocococococoo ee 151 Table 117 PWM Timer Control Register PWMTCR 0xE0014004 0 0 0 0 eee 152 Table 118 PWM Match Control Register PWMMCR 0xE0014014 0 eee eee 153 Table 119 PWM Control Register PWMPCR 0xE001404C 1 0 2 0 eee ee 154 Table 120 PWM Latch Enable Register PWMLER 0xE0014050 0 0 eee eee eee 155 Table 121 Real Time Clock Register Map oococccoccocc eR mn 159 Table 122 Miscellaneous Registers 20 cece tte tenes 161 Table 123 Interrupt Location Register Bits ILR OxE0024000 0 eee eee ee 161 Table 124 Clock Tick Counter Bits CTC OxE0024004 0 0 cece eee 161 Table 125 Clock Control Register Bits CCR OxE0024008 0 cee een 162 Table 126 Counter Increment Interrupt Register Bits CIIR OXE002400C 0 000 162 Table 127 Alarm Mask Register Bits AMR OxE0024010 0 cee ee ee 163 Table 128 Consolidated Time Register 0 Bits CTIMEO OXE0024014 00 eee eee 164 Table 129 Consolidated Time Register 1 Bits CTIME1 OxE0024018 0 00 00 eee ee 164 Table 130 Consolidated Time Register 2 Bits CTIME2 OxE002401C
73. 2 is mapped to its related pin Can be cleared by writing a 1 to this bit after the logic 1 appears on the related pin 73 aser eH Reserved user software should not write ones to reserved bits The value read NA i from a reserved bit is not defined EXTWAKE Register EXTWAKE 0xE01FC144 Enable bits in the EXTWAKE register allow the external interrupts to wake up the processor if it is in Power Down mode The related EINTn function must be mapped to the pin in order for the wakeup process to take place It is not necessary for the interrupt to be enabled in the Vectored Interrupt Controller for a wakeup to take place This arrangement allows additional capabilities such as having an external interrupt input wake up the processor from Power Down mode without causing an interrupt simply resuming operation or allowing an interrupt to be enabled during Power Down without waking the processor up if it is asserted eliminating the need to disable the interrupt if the wakeup feature is not desirable in the application System Control Block 40 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Table 9 External Interrupt Wakeup Register EXTWAKE 0xE01FC144 EXTWAKE Function Description EXTWAKEO When one assertion of EINTO will wake up the processor from Power Down mode EXTWAKE1 When one assertion of EINT1 will wake up the processor from Power Down mode 0 EXTWAKE2 When
74. 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 GPIO 84 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 9 UART O FEATURES 16 byte Receive and Transmit FIFOs Register locations conform to 550 industry standard Receiver FIFO trigger points at 1 4 8 and 14 bytes Built in baud rate generator PIN DESCRIPTION Table 57 UART 0 Pin Description Pin Name Type Description RxDO Input Serial Input Serial receive data Output Serial Output Serial transmit data UART 0 85 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 REGISTER DESCRIPTION Table 58 UART 0 Register Map Address inti ser Name Description BIT 4 BIT3 Receiver OxEO00CO00 UorBR Buffer READ DATA DLAB 0 N Register Transmit DA o ds egeta dbi DLAB 0 Register Interrupt iai 5 a ED k e DLAB 0 Register xEooocoos voir ierruptID FIFOs Enabled IIR Register Interrupt Enable THRE Interrupt Enable Rx Line Enable Rx Data Available oxEooocooc uoLcn Hne Control 29 Eg g Word Length Register o Select 0 FIFO 0xE000C008 UOFCR Control Rx Trigger Reserved Register oxEo00co14 UoLsn ine Status Eo TemT THRE PE OE 0x60 Register Error oxeoooco1c UoscR Scratch Pad Msg LSB mw n Register 0xE000C000 Di
75. 3 Raw Interrupt Status Register VICRawlntr OXFFFFF008 Read Only 64 Table 34 Interrupt Enable Register VICINtEnable OXFFFFF010 Read Write 65 Table 35 Software Interrupt Clear Register VICIntEnClear OXFFFFF014 Write Only 65 Table 36 Interrupt Select Register VICIntSelect OxFFFFFOOC Read Write 65 Table 37 IRQ Status Register VICIRQStatus OXFFFFF000 Read Only ssseseseseeess 65 Table 38 IRQ Status Register VICFIQStatus OXFFFFF004 Read Only lslseseesess 66 Table 39 Vector Control Registers VICVectCntl0 15 OxFFFFF200 23C Read Write 66 Table 40 Vector Address Registers VICVectAddr0 15 OxFFFFF100 13C Read Write 66 Table 41 Default Vector Address Register VICDefVectAddr OXFFFFF034 Read Write 66 Table 42 Vector Address Register VICVectAddr OXFFFFFO30 Read Write 67 Table 43 Protection Enable Register VICProtection OXFFFFF020 Read Write 67 Table 44 Connection of Interrupt Sources to the Vectored Interrupt Controller 68 Table 45 Pin description for LPC2106 2105 2104 oooooocooocooor lee 72 Table 46 Pin description and corresponding functions for LPC2106 2105 2104 oo ooooooo 73 Table 47 Pin Connect Block Register Map 0 0 0 cece teen e eens 77 Table 48 Pin Function Select Register 0
76. 4 registers as shown in Table 137 below Table 137 Watchdog Register Map A Reset Address Name Description Access Value 0xE0000000 WDMOD Watchdog mode register This register contains the basic mode and Read Set 0 status of the Watchdog Timer OxE0000004 WDTC ME timer constant register This register determines the time out Read Write OxE0000008 WDFEED Watchdog feed sequence register Writing AAh followed by 55h to this Write Only NA register reloads the Watchdog timer to its preset value OxE000000C WDTV Watchdog timer value register This register reads out the current value Read Only of the Watchdog timer Reset Value refers to the data stored in used bits only It does not include reserved bits content Watchdog 172 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Watchdog Mode Register WDMOD 0xE0000000 The WDMOD register controls the operation of the Watchdog as per the combination of WDEN and RESET bits WDEN WDRESET 0 X Debug Operate without the Watchdog running 1 0 Debug with the Watchdog interrupt but no WDRESET 1 1 Operate with the Watchdog interrupt and WDRESET Once the WDEN and or WDRESET bits are set they can not be cleared by software Both flags are cleared by an external reset or a Watchdog timer underflow WDTOF The Watchdog time out flag is set when the Watchdog times out This flag is cleared by software WDINT The Watchdog interrupt
77. 4038 MONTH Month value in the range of 1 to 12 R W 0xE002403C YEAR Year value in the range of 0 to 4095 Notes 1 These values are simply incremented at the appropriate intervals and reset at the defined overflow point They are not calculated and must be correctly initialized in order to be meaningful Leap Year Calculation The RTC does a simple bit comparison to see if the two lowest order bits of the year counter are zero If true then the RTC considers that year a leap year The RTC considers all years evenly divisible by 4 as leap years This algorithm is accurate from the year 1901 through the year 2099 but fails for the year 2100 which is not a leap year The only effect of leap year on the RTC is to alter the length of the month of February for the month day of month and year counters Real Time Clock 166 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 ALARM REGISTER GROUP The alarm registers are shown in Table 133 The values in these registers are compared with the time counters If all the unmasked See Alarm Mask on page 162 alarm registers match their corresponding time counters then an interrupt is generated The interrupt is cleared when a one is written to bit one of the Interrupt Location Register ILR 1 Table 133 Alarm Registers Address Name Description Access 0xE0024060 ALSEC Alarm value for Seconds R W 0xE0024064 ALMIN 6 Alarm va
78. 6 2105 2104 See Table 21 Power Control for Peripherals Register This register contains control bits that OxEO1FCOCA PCONP enable and disable individual peripheral functions Allowing elimination of power consumption by peripherals that are not needed See Table 22 PCON Register PCON 0xE01FCOCO OxEO1FCOCO The PCON register contains two bits Writing a one to the corresponding bit causes entry to either the Power Down or Idle mode If both bits are set Power Down mode is entered Table 21 Power Control Register PCON 0xE01FCOCO PCON Function Description Idle mode when set this bit causes the processor clock to be stopped while on chip 0 IDL peripherals remain active Any enabled interrupt from a peripheral or an external interrupt source will cause the processor to resume execution Power Down mode when set this bit causes the oscillator and all on chip clocks to be 1 stopped A wakeup condition from an external interrupt can cause the oscillator to re start the PD bit to be cleared and the processor to resume execution Reserved user software should not write ones to reserved bits The value read from a Reserved s i reserved bit is not defined System Control Block 49 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Power Control for Peripherals Register PCONP 0xE01FC0C4 The PCONP register allows turning off selected peripheral fun
79. 8 Pin Function Select Register 0 PINSELO 0xE002C000 PINSELO ls Function when 00 Function when 01 Function when 10 Function when 11 1 0 P0 0 GPIO Port 0 0 TxD UART 0 PWM1 Reserved 3 2 GPIO Port 0 1 RxD UART 0 PWM3 5 4 GPIO Port 0 2 SCL 12C Capture 0 0 Timer 0 6 GPIO Port 0 3 SDA IC Match 0 0 Timer 0 Ti GPIO Port 0 4 SCK SPI Capture 0 1 Timer 0 11 10 GPIO Port 0 5 MISO SPI Match 0 1 Timer 0 2 Ti 7 13 12 POS GPIO Port 0 6 MOSI SPI Capture 0 2 Timer 0 15 14 GPIO Port 0 7 SSEL SPI PWM2 17 16 GPIO Port 0 8 TxD UART 1 PWM4 19 18 Pos GPIO Port 0 9 RxD UART 1 PWM6 21 20 P0 10 GPIO Port 0 10 RTS UART1 Capture 1 0 Timer 1 23 22 P0 11 GPIO Port 0 11 CTS UART1 Capture 1 1 Timer 1 25 24 P0 12 GPIO Port 0 12 DSR UART1 Match 1 0 Timer 1 27 26 P0 13 GPIO Port 0 13 DTR UART 1 Match 1 1 Timer 1 29 28 P0 14 GPIO Port 0 14 CD UART 1 EINT1 31 30 P0 15 GPIO Port 0 15 RI UART1 EINT2 Pin Connect Block 78 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Pin Function Select Register 1 PINSEL1 0xE002C004 The PINSEL1 register controls the functions of the pins as per the settings listed in Table 49 The direction control bit in the IODIR register is effective only when the GPIO function is selected for a pin For other functions direction is controlled automatically Function control for the pins P0 17 P0 31
80. AM controller incorporates a write back buffer in order to prevent CPU stalls during back to back writes The write back buffer always holds the last data sent by software to the SRAM This data is only written to the SRAM when another write is requested by software lf a chip reset occurs actual SRAM contents will not reflect the most recent write request Any software that checks SRAM contents after reset must take this into account A dummy write to an unused location may be appended to any operation in order to guarantee that all data has really been written into the SRAM Introduction 17 September 17 2003 Philips Semiconductors ARM based Microcontroller BLOCK DIAGRAM ARM7 Local Bus Internal Flash Controller 128 kB FLASH External Interrupts Capture Compare Timer 0 Capture Compare Timer 1 General OPIO 10 pins Purpose I O Real Time Clock Shared with GPIO Test Debug Interface ARM7TDMI S AHB Bridge Preliminary User Manual LPC2106 2105 2104 System Functions Vectored Interrupt Controller AHB Decoder System Clock Emulation Trace Module AMBA AHB Advanced High performance Bus AHB to VPB VPB Bridge Divider VPB VLSI Peripheral Bus 12C Serial Interface SPI Serial Interface Modem Control 6 pins Watchdog Timer System Control When Test Debug Interface is used GPIO other functions sharing these pins are not available
81. AT 0xE001C004 I2STAT Function Description Status These bits are always 0 12C Data Register I2DAT 0xE001C008 This register contains the data to be transmitted or the data just received The CPU can read and write to this register while it is not in the process of shifting a byte This register can be accessed only when SI bit is set Data in I2DAT remains stable as long as the SI bit is set Data in I2DAT is always shifted from right to left the first bit to be transmitted is the MSB bit 7 and after a byte has been received the first bit of received data is located at the MSB of I2DAT Table 90 I C Data Register I2DAT 0xE001C008 I2DAT Function Description 7 0 Data Transmit Receive data bits 12C Slave Address Register I2ADR 0xE001C00C This register is readable and writable and is only used when the 12C is set to slave mode In master mode this register has no effect The LSB of I2ADR is the general call bit When this bit is set the general call address 00h is recognized Table 91 I C Slave Address Register IZADR 0xE001C00C I2ADR Function Description General Call bit 12C Interface 119 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 12C SCL Duty Cycle Registers I2SCLH 0xE001C010 and I2SCLL 0xE001C014 Software must set values for registers I2SCLH and I2SCLL to select the appropriate data rate I2SCLH def
82. B 8 bit data R W U1 Interrupt E Enable AB 0 0xE0010004 Register E U1 Divisor E 1 Latch MSB 8 bit data uma D interrupt eros Enabled ms m2 Rt ID Register 0xE0010008 U1 FIFO U1FCR Control Rx Trigger Register U1 Line Even OxE001000C U1LCR Control DLAB Stick arity Word Length E Parity Select Register Select U1 Modem 0xE0010010 OE Control B RTS Register U1 Line Rx 0xE0010014 U1LSR Status FIFO TEMT THRE FE PE OE Register Error 0xE001001C u1sca Y Scratch 8 bit data Pad Register U1 Modem Trailing U1 Delta Delta Delta 0xE0010018 Status DCD DSR CTS Edge TS Register GORE Ri PWM Int Int Int 0xE0014000 PAMI Interrupt IR Register MR3 MR2 MRt d Int Int Int d PWM Timer PWM PWM CTR CTR Register 0xE0014008 PWM PWM Timer 32 bit data TC Counter Introduction 23 September 17 2003 g Y g 2 2 2 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Table 1 LPC2106 2105 2104 Registers Address ors Reset Offset Description LSB Access Value PWM 0xE001400C Prescale 32 bit data R W Register PR oxEo014010 PWM prescale 32 bit data PC Counter Reset 11 reserved bits on MR6 PWM Match Stop 0xE0014014 SEE Control o on Register MR3 Int on MR1 0xE001401C ae OxE0014020 OxE0014024 OxE0014040 0xE0014044 ME OxE001404C CH PWM Latch 0xE0014050 Enable LER Register 2c I2CON IFC Control 2 Register 2
83. CEPKT3Trace Packet bit 3 Standard l O port with internal pullup TDI Test Data In for JTAG interface secondary JTAG pin group f EXTINO External Trigger Input Standard I O port with internal pullup TDO Test Data Out for JTAG interface secondary JTAG pin group Returned Test Clock output Extra signal added to the JTAG port Assists debugger RTCK 26 synchronization when processor frequency varies Also used during debug mode entry to enable primary JTAG pins Bi directional pin with internal pullup Debug Select When low the part operates normally When high debug mode is entered Input DBGSEL 27 ipM pin with internal pulldown RST External Reset input A low on this pin resets the device causing l O ports and peripherals to take on their default states and processor execution to begin at address 0 za px Input to the oscillator circuit and internal clock generator circuits Xx 42 e Output from the oscillator amplifier 7 Pr ER Ground OV reference Voie 5 1 8V Core Power Supply This is the power supply voltage for internal circuitry 17 40 BE 3 3V Pad Power Supply This is the power supply voltage for the I O ports 4 x E Not Connected These pins are not connected Pin Configuration 75 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Pin Configuration 76 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcont
84. DULE MAM INTRODUCTION Simply put the Memory Accelerator Module MAM attempts to have the next ARM instruction that will be needed in its latches in time to prevent CPU fetch stalls The method used is to split the Flash memory into two banks each capable of independent accesses Each of the two Flash banks has its own prefetch Buffer and Branch Trail Buffer The Branch Trail Buffers for the two banks capture two 128 bit lines of Flash data when an Instruction Fetch is not satisfied by either the Prefetch buffer nor Branch Trail buffer for its bank and for which a prefetch has not been initiated Each prefetch buffer captures one 128 bit line of instructions from its Flash bank at the conclusion of a prefetch cycle initiated speculatively by the MAM Each 128 bit value includes four 32 bit ARM instructions or eight 16 bit Thumb instructions During sequential code execution typically one Flash bank contains or is fetching the current instruction and the entire Flash line that contains it The other bank contains or is prefetching the next sequential code line After a code line delivers its last instruction the bank that contained it begins to fetch the next line in that bank Timing of Flash read operations is programmable and is described later in this section as well as in the System Control Block section Branches and other program flow changes cause a break in the sequential flow of instruction fetches described above When a backward bra
85. Description Value MRO Interrupt Interrupt flag for match channel 0 0 1 MR1 Interrupt Interrupt flag for match channel 1 MR2 Interrupt Interrupt flag for match channel 2 BE PS A UN MI UN RI A UN 7 ere erin O MIS Timer Control Register TCR Timer 0 TOTCR 0xE0004004 Timer 1 T1 TCR 0xE0008004 The Timer Control Register TCR is used to control the operation of the Timer Counter Table 108 Timer Control Register TCR Timer 0 TOTCR 0xE0004004 Timer 1 T1 TCR 0xE0008004 Reset Function Description Value When one the Timer Counter and Prescale Counter are enabled for counting When Counter Enable 0 zero the counters are disabled 1 Counter Reset When one the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of pclk The counters remain reset until TCR 1 is returned to zero Timer Counter TC Timer 0 TOTC 0xE0004008 Timer 1 T1TC 0xE0008008 The 32 bit Timer Counter is incremented when the Prescale Counter reaches its terminal count Unless it is reset before reaching its upper limit the TC will count up through the value OXFFFFFFFF and then wrap back to the value 0x00000000 This event does not cause an interrupt but a Match register can be used to detect an overflow if needed Prescale Register PR Timer 0 TOPC 0xE000400C Timer 1 T1PC 0xE000800C The 32 bit Prescale Register specifies the maximum value for the Prescale Count
86. EmbeddedICE Logic 201 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 PIN DESCRIPTION Table 167 EmbeddedlCE Pin Description Pin Name Type Description TMS Input Test Mode Select The TMS pin selects the next state in the TAP state machine TCK bot Test Clock This allows shifting of the data in on the TMS and TDI pins It is a positive edge P triggered clock with the TMS and TCK signals that define the internal state of the device Test Data In This is the serial data input for the shift register Test Data Output This is the serial data output from the shift register Data is shifted out of the TDO Output device on the negative edge of the TCK signal nTRST Test Reset The nTRST pin can be used to reset the test logic within the EmbeddedICE logic Debug Select When low at Reset the P0 17 P0 21 pins are configured for alternate functions DBGSEL Input via the Pin Connect Block When high at Reset debug mode is entered For functionality provided by DBGSEL see Debug Mode section of this chapter Returned Test Clock Extra signal added to the JTAG port Required for designs based on ARMT7TDMI S processor core Multi ICE Development system from ARM uses this signal to RTCK Output maintain synchronization with targets having slow or widely varying clock frequency For details refer to Multi ICE System Design considerations Application Note 72 ARM DAI
87. FIFO depth 10 bytes 1 For details refer to ARM documentation Embedded Trace Macrocell Specification ARM IHI 0014E PIN DESCRIPTION Table 171 ETM Pin Description Pin Name Description Trace Clock The trace clock signal provides the clock for the trace port PIPESTAT 2 0 TRACESYNC and TRACEPKT 3 0 signals are referenced to the rising edge of the trace clock This clock is not generated by the ETM block It is to be derived from the system clock The clock should be balanced to provide sufficient hold time for the trace data signals Half TRACECLK rate clocking mode is supported Trace data signals should be shifted by a clock phase from TRACECLK Refer to Figure 3 14 page 3 26 and figure 3 15 page 3 27 in ETM7 Technical Reference Manual ARM DDI 0158B for example circuits that implements both half rate clocking and shifting of the trace data with respect to the clock For TRACECLK timings refer to section 5 2 on page 5 13 in Embedded Trace Macrocell Specification ARM IHI 0014E PIPESTAT 2 0 Output Pipe Line status The pipeline status signals provide a cycle by cycle indication of what is happening in the execution stage of the processor pipeline Trace synchronization The trace sync signal is used to indicate the first packet of a group JRAGESTNE Output of trace packets and is asserted HIGH only for the first packet of any branch address Trace Packet The trace packet signals are used to output packaged address and d
88. I O default to inputs after reset APPLICATIONS General purpose I O Driving LEDs or other indicators Controlling off chip devices Sensing digital inputs PIN DESCRIPTION Table 51 GPIO Pin Description Pin Name Description General purpose input output The number of GPIOs actually available depends on the use of Resin alternate functions REGISTER DESCRIPTION The GPIO contains 4 registers as shown in Table 52 Table 52 GPIO Register Map Address Name Description Access GPIO Pin value register The current state of the port pins can always be read MXEDUEODE ISFIN from this register regardless of pin direction and mode Read Only GPIO 0 Output set register This register controls the state of output pins in 0xE0028004 IOSET conjunction with the IOCLR register Writing ones produces highs at the Read Set corresponding port pins Writing zeroes has no effect GPIOO Direction control register This register individually controls the direction Read Write of each port pin 0xE0028008 GPIO 0 Output clear register This register controls the state of output pins 0xE002800C IOCLR Writing ones produces lows at the corresponding port pins and clears the Clear Only corresponding bits in the IOSET register Writing zeroes has no effect GPIO 81 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 GPIO Pin Value Register IOPIN 0xE0028000
89. IRQ OxFEFF F014 VICIntEnCIr Interrupt Enable Clear Register This register allows software to clear W one or more bits in the Interrupt Enable register OxFFFF F018 VICSoftlnt Software Interrupt Register The contents of this register are ORed with R W the 32 interrupt requests from various peripheral functions OxFFFF F01C VICSoftIntClear Software Interrupt Clear Register This register allows software to clear w one or more bits in the Software Interrupt register OXFFFF F020 VICProtection Protection enable register This register allows limiting access to the VIC R W registers by software running in privileged mode OxFEFF F030 viCVectAddr Vector Address Register When an IRQ interrupt occurs the IRQ service R W routine can read this register and jump to the value read OxFFFF F034 VICDefVectAddr Default Vector Address Register This register holds the address of the R W Interrupt Service routine ISR for non vectored IRQs Vector address 0 register Vector Address Registers 0 15 hold the OxFFFF F100 VICVectAddrO addresses of the Interrupt Service routines ISRs for the 16 vectored R W IRQ slots OxFFFF F104 VICVectAddr1 Vector address 1 register RW o OxFFFF F108 VICVectAddr2 Vector address 2 register RW 0 OxFFFF F10C VICVectAddr3 Vector address 3 register RW o OxFFFF F110 VlCVectAddr4 Vector address 4 register RW 0 OxFFFF F114 VICVectAddr5 Vector address 5 register RW o OxFFFF F118 V
90. It compresses the trace information and exports it through a narrow trace port An external Trace Port Analyzer captures the trace information under software debugger control Trace port can broadcast the Instruction trace information Instruction trace or PC trace shows the flow of execution of the processor and provides a list of all the instructions that were executed Instruction trace is significantly compressed by only broadcasting branch addresses as well as a set of status signals that indicate the pipeline status on a cycle by cycle basis Trace information generation can be controlled by selecting the trigger resource Trigger resources include address comparators counters and sequencers Since trace information is compressed the software debugger requires a static image of the code being executed Self modifying code can not be traced because of this restriction ETM Configuration The following standard configuration is selected for the ETM macrocell Table 170 ETM Configuration Resource number type Small Pairs of address comparators 1 Data Comparators 0 Data tracing is not supported Memory Map Decoders Counters Sequencer Present External Inputs Embedded Trace Macrocell 207 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Table 170 ETM Configuration Resource number type Small External Outputs 0 FIFOFULL Present Yes Not wired
91. LPC2106 2105 2104 2 LPC2106 2105 2104 MEMORY ADDRESSING MEMORY MAPS The LPC2106 2105 2104 incorporates several distinct memory regions shown in the following figures Figure 2 shows the overall map of the entire address space from the user program viewpoint following reset The interrupt vector area supports address re mapping which is described later in this section AHB Peripherals VPB Peripherals Reserved for External Memory Boot Block re mapped from On Chip Flash memory Reserved for On Chip Memory On Chip Static RAM 128 kB On Chip Non Volatile Memory Figure 2 System Memory Map LPC2106 2105 2104 Memory Addressing 29 OxFFFF FFFF OxF000 0000 OxE000 0000 0xC000 0000 0x8000 0000 0x4000 FFFF LPC2106 64 kB 0x4000 7FFF LPC2105 32 kB 0x4000 3FFF LPC2104 16 kB 0x4000 0000 0x0002 0000 0x0001 FFFF 0x0000 0000 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 4 0 GB OxFFFF FFFF AHB Peripherals OxFFEO 0000 SoBe Mp OxFFDF FFFF Notes AHB section is 128 x 16 kB blocks totaling 2 MB Reserved VPB section is 128 x 16 kB blocks totaling 2 MB OxF000 0000 OxEFFF FFFF Reserved 0xE020 0000 OxEO1F FFFF 3 5 GB 2 MB VPB Peripherals 3 5 GB 0xE000 0000 Figure 3 Peripheral Memory Map Figures 3 through 5 show different views of the peripheral address space Both the AHB an
92. MAMCR 0xE01FC000 Function Description These bits determine the operating mode of the MAM as follows 0 0 MAM functions disabled 0 1 MAM functions partially enabled 10 MAM functions fully enabled 11 reserved Reserved user software should not write ones to reserved bits The value read from a Reserved v 5 reserved bit is not defined MAM Timing Register MAMTIM 0xE01FC004 MAM mode control The MAM Timing register determines how many cclk cycles are used to access the Flash memory This allows tuning MAM timing to match the processor operating frequency Flash access times from 1 clock to 7 clocks are possible Single clock Flash accesses would essentially remove the MAM from timing calculations In this case the MAM mode may be selected to optimize power usage Table 29 MAM Timing Register MAMTIM 0xE01FC004 MAMTIM Function Description These bits set the duration of MAM Flash fetch operations as follows 0 0 0 0 Reserved 00121 MAM fetch cycles are 1 processor clock cclk in duration 01022 MAM fetch cycles are 2 processor clocks cclks in duration 01123 MAM fetch cycles are 3 processor clocks cclks in duration 4 MAM fetch cycles are 4 processor clocks cclks in duration MAM Fetch MAM fetch cycles are 5 processor clocks cclks in duration cclks cclks Cycle timing 1 1 1 1 00 01 25 1026 MAM fetch cycles are 6 processor clocks cclks in duration 1
93. Minimum of one character in the Rx FIFO and no character input or removed during a time period depending on how many Character Time characters are in FIFO and what the trigger level is set at 3 5 1100 Second PEG to 4 5 character times UO RBR Read out Indication A The exact time will be word length X 7 2 X 8 trigger level number of characters X 8 1 RCLKs UOIIR Read if 0010 Third THRE THRE Source of interrupt or THR write note values 0000 0011 0101 0111 1000 1001 1010 1011 1101 1110 1111 are reserved The UARTO THRE interrupt UOIIR3 1 001 is a third level interrupt and is activated when the UARTO THR FIFO is empty provided certain initialization conditions have been met These initialization conditions are intended to give the UARTO THR FIFO a chance to fill up with data to eliminate many THRE interrupts from occurring at system start up The initialization conditions implement a one character delay minus the stop bit whenever THRE 1 and there have not been at least two characters in the UOTHR at one time since the last THRE 1 event This delay is provided to give the CPU time to write data to UOTHR without a THRE interrupt to decode and service A THRE interrupt is set immediately if the UARTO THR FIFO has held two or more characters at one time and currently the UOTHR is empty The THRE interrupt is reset when a UOTHR write occurs or a read of the UOIIR occu
94. Mode A Execute program in ARM mode CMD_SUCCESS ADDR_ERROR Return Code ADDR_NOT_MAPPED CMD_LOCKED PARAM_ERROR This command is used to execute call a program residing in RAM or Flash memory lt may not be Description possible to return to ISP command handler once this command is successfully executed If executed code has ended with return instruction ISP handler will resume with execution Example G 0 A lt CR gt lt LF gt branches to address 0x0000 0000 in ARM mode Erase sector s start sector number end sector number gt Table 152 ISP Erase sector command description Command E Start Sector Number End Sector Number Should be greater than or equal to start sector number CMD SUCCESS BUSY asia INVALID_SECTOR SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION CMD_LOCKED PARAM_ERROR Input This command is used to erase a sector or multiple sectors of on chip Flash memory The boot Description sector can not be erased by this command To erase a single sector use the same Start and End sector numbers Example E 2 3 lt CR gt lt LF gt erases the flash sectors 2 and 3 Flash Memory System and Programming 189 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Blank check sector s lt start sector number gt lt end sector number gt Table 153 ISP Blank check sector s command description Command I input Sta
95. PC2106 2105 2104 Pin functions 0 0 cect teeta 72 Pin Description for LPC2106 2105 2104 2 1 tte eens 73 3 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Pin Connect Block 222m ii a levied ia 77 EStdt m cR FU Rr eee tec duet d 77 Applications cdt a A A A I ee IH 77 Description eco ia td 77 Register Description 2 sere orae A A A al 77 GPIO ia it a A A A et ee ee 81 Features sni rea A A A UE A a ee kas ee ER 81 Applications a tr die at ee ee toh UR A Ke o lea 81 Pin D scriptioti aso See hs A eR ae BE a C SER ER 81 Register Descriptiori o ver Re EE e e I wed baa A 81 GPIO Usage Notes ien ERR RR Wem easi e eb dev ek Eus 83 VART O EEE A A le ei ace Rosie URINE NN d DE 85 FOIS it a A Sie tend AE Aa A AR de 85 Pin Description eic cU REPE awe hae A e es eco RIO See 85 Register Descriptio usn RT E O AB RS eh x UR RUE Ei Ra RR wee 86 Architect re ego ELOIL Ae A COSE FRU Me eR at A de or RO 94 DUARTE te eaten ea gerd cote ED oS 97 Feat les it A ete e ike itd pag dation Sag Rien An De ere 97 Pin Description nib bk a tine cor 97 Register Description ur Ree Ste Mets RR RERER date e g oe RAO EORR pled 98 AtChitect re unto A A Shee ee es ee ek Ge eye A 109 2C Interlace iii A A eae 111 Features o a A Boas a iia 111 Applications v A A AA A E NA O 111 D6eScrIptiOnt ai a e e e Ree e le talar tte 111 Pin DescrptiOn cio eem aka PER a are Pe ee TA coa 115
96. PINSELO OxEOO2C000 000 c eee eee 78 Table 49 Pin Function Select Register 1 PINSEL1 OxE002C004 0 0 0 ee eee 79 Table 50 Pin Function Select Register Bits liliis 79 Table 51 GPIO Pin Description 0 0 0 0 ccc tenets 81 Table 52 GPIO RegisteriMap x ea tii et iR Ree oad Song eas neni eee ea 81 Table 53 GPIO Pin Value Register IOPIN OXE0028000 0 cece eae 82 Table 54 GPIO Output Set Register IOSET OXE0028004 2 0 00 cee 82 Table 55 GPIO Output Clear Register IOCLR OXE002800C anaran 82 9 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Table 56 GPIO Direction Register IODIR 0xE0028008 oocococcoccccco ees 82 Table 57 UART O Pin Desctiption ases ios a A E Oe te ce A 85 Table 58 UART 0 Register Map ooo ooocooocorrr e I 86 Table 59 UARTO Receiver Buffer Register UORBR OXE000C000 when DLAB 0 Read Only 87 Table 60 UARTO Transmit Holding Register UOTHR OXE000C000 when DLAB 0 Write Only 87 Table 61 UARTO Divisor Latch LSB Register UODLL OXE000C000 when DLAB 1 87 Table 62 UARTO Divisor Latch MSB Register UODLM OxE000C004 when DLAB 1 87 Table 63 UARTO Interrupt Enable Register Bit Descriptions UOIER OXE000C004 when DLAB 0 88 Table 64 UARTO Interrupt Identification Register Bit Description
97. RM based Microcontroller LPC2106 2105 2104 Echo lt setting gt Table 146 ISP Echo command description Command A Input Setting ON 1 OFF 0 CMD_SUCCESS 2 o The default setting for echo command is ON When ON the ISP command handler sends the Description E received serial data back to the host Example A 0 lt CR gt lt LF gt turns echo off Flash Memory System and Programming 186 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Write to RAM lt start address gt lt number of bytes gt The host should send the data only after receiving the CMD_SUCCESS return code The host should send the check sum after transmitting 20 UU encoded lines The length of any UU encoded line should not exceed 61 characters bytes i e it can hold 45 data bytes When the data fits in less then 20 UU encoded lines then the check sum should be of actual number of bytes sent The ISP command handler compares it with the check sum of the received bytes If the check sum matches then the ISP command handler responds with OK lt CR gt lt LF gt to continue further transmission If the check sum does not match then the ISP command handler responds with RESEND lt CR gt lt LF gt In response the host should retransmit the bytes Table 147 ISP Write to RAM command description Command W Start Address RAM address where data bytes are to be written This address should be a wo
98. Register Introduction 24 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Table 1 LPC2106 2105 2104 Registers Address Reset Offset Description MSB LSB Access Value C Slave 0xE001C00C Address 7 bit data GC R W 0 Register SCL Duty 12 Cycle 0xE001C010 SCLH Register High 16 bit data R W 0x04 Half Word SCL Duty 12 Cycle 0xE001C014 SCLL Register Low 16 bit data R W 0x04 Half Word IPCON 12C Control 0xE001C018 CLR Clear I2ENC STAC SIC AAC WO NA Register oxE0020000 sper SP Contro Spie spE MsrR CPOL CPHA Ei Register oxE0020004 SPSR Rd SPIF WCOL ROVR MODF ABRT Dannu 0xE0020008 sppr SPF Data e ee Register SP SPI Clock 0xE002000C Counter 8 bit data R W CCR Register oxeoo20010 spint SP Interrupt SPI aw Flag Int Interrupt 0xE0024000 Location RTC RTC pyw ALF CIF Register 0xE0024004 Glock Tick 15 bit data Counter Clock Control CTC ER Counter Increment IM IM IM IM IM IM IM IM su E Interrupt YEAR MON DOY DOW DOM HOUR MIN SEC Register Alarm Mask AMR AMR AMR AMR AMR AMR AMR AMR Introduction 25 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Table 1 LPC2106 2105 2104 Registers Address eos Reset Offset Description LSB Access Value 3 bit Day of Week Consolidated aaa 5 bit Hour
99. Source address is not on word boundary 3 DST ADDR ERROR Destination address is not on a correct boundary Source address is not mapped in the memory map SRC ADDR NOT MAPPED Count value is taken in to consideration where applicable Destination address is not mapped in the memory DST ADDR NOT MAPPED map Count value is taken in to consideration where applicable COUNT ERROR Byte count is not multiple of 4 or is not a permitted value INVALID SECTOR Sector number is invalid or end sector number is greater than start sector number SECTOR NOT BLANK Sector is not blank SECTOR NOT PREPARED FOR WRITE OPERATION MU prepare Sector dar write operation was COMPARE ERROR Source and destination data not equal BUSY Flash programming hardware interface is busy PARAM ERROR Insufficient number of parameters or invalid parameter ADDR ERROR Address is not on word boundary ADDR NOT MAPPED Address is not mapped in the memory map Count value is taken in to consideration where applicable CMD LOCKED Command is locked INVALID CODE Unlock code is invalid INVALID BAUD RATE Invalid baud rate setting INVALID STOP BIT Invalid stop bit setting Code 0 EE Mrd Ere ES EGET ET KA EI Ey 7 10 11 12 13 14 15 16 17 18 Flash Memory System and Programming 192 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 IAP Commands For in application programming th
100. Standard modem interface signals included PIN DESCRIPTION Table 70 UART1 Pin Description Pin Name Type Description RxD1 Input Serial Input Serial receive data Output Serial Output Serial transmit data Clear To Send Active low signal indicates if the external modem is ready to accept transmitted CTS1 Input data via TxD1 from the UART1 In normal operation of the modem interface U1MCR4 0 the complement value of this signal is stored in U1MSR4 State change information is stored in U1MSRO and is a source for a priority level 4 interrupt if enabled U1IER3 1 Data Carrier Detect Active low signal indicates if the external modem has established a communication link with the UART1 and data may be exchanged In normal operation of the DCD1 Input modem interface U1MCR4 0 the complement value of this signal is stored in U1MSR7 State change information is stored in Uf MSR3 and is a source for a priority level 4 interrupt if enabled U1IER3 1 Data Set Ready Active low signal indicates if the external modem is ready to establish a communications link with the UART1 In normal operation of the modem interface DSR1 Input U1 MCR4 0 the complement value of this signal is stored in UT MSR5 State change information is stored in U1MSR1 and is a source for a priority level 4 interrupt if enabled U1IER3 1 DTR1 Output Data Terminal Ready Active low signal indicates that the UART1 is ready to establish P connection with externa
101. TA ABORT EXCEPTIONS The LPC2106 2105 2104 generates the appropriate bus cycle abort exception if an access is attempted for an address that is in a reserved or unassigned address region The regions are Areas of the memory map that are not implemented for a specific ARM derivative For the LPC2106 2105 2104 this is Address space between On Chip Non Volatile Memory and the Special registers Labelled Reserved for On Chip Memory in Figure 2 and Figure 6 Address space between On Chip Static RAM and External Memory Labelled Reserved for On Chip Memory in Figure 2 External Memory since no external bus interface is implemented on the LPC2106 2105 2104 Reserved regions of the AHB and VPB spaces See Figure 3 Unassigned AHB peripheral spaces See Figure 4 Unassigned VPB peripheral spaces See Figure 5 For these areas both attempted data access and instruction fetch generate an exception In addition a Prefetch Abort exception is generated for any instruction fetch that maps to an AHB or VPB peripheral address Within the address space of an existing VPB peripheral a data abort exception is not generated in response to an access to an undefined address Address decoding within each peripheral is limited to that needed to distinguish defined registers within the peripheral itself For example an access to address OxXE000D000 an undefined address within the UARTO space may result in an access to the register defined at addre
102. Types MAM Mode Program Memory Request Type 0 1 2 Sequential access data in MAM latches Initiate Fetch 2 Use Latched Data Use Latched Data Sequential access data not in MAM latches Initiate Fetch Initiate Fetch Initiate Fetch Non Sequential access data in MAM latches Initiate Fetch Initiate Fetch Use Latched Data Non Sequential access data not in MAM latches Initiate Fetch Initiate Fetch Initiate Fetch Table 26 MAM Responses to Data and DMA Accesses of Various Types MAM Mode Data Memory Request Type 0 1 2 Sequential access data in MAM latches Initiate Fetch 2 Initiate Fetch 2 Use Latched Data Sequential access data not in MAM latches Initiate Fetch Initiate Fetch Initiate Fetch Non Sequential access data in MAM latches Initiate Fetch 2 Initiate Fetch Use Latched Data Non Sequential access data not in MAM latches Initiate Fetch Initiate Fetch Initiate Fetch Instruction prefetch is enabled in modes 1 and 2 2 The MAM actually uses latched data if it is available but mimics the timing of a Flash read operation This saves power while resulting in the same execution timing The MAM can truly be turned off by setting the fetch timing value in MAMTIM to one clock Memory Accelerator Module MAM 57 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 MAM CONFIGURATION After reset the MAM defaults to the disabled state
103. Unlock Code Table 143 s Unlock Unlock code Table 143 ISP Unlock command description Command U Input Unlock code 23130 CMD SUCCESS Return Code INVALID CODE PARAM ERROR This command is used to unlock flash Write Erase amp Go commands Example X U 23130 lt CR gt lt LF gt unlocks the flash Write Erase amp Go commands Flash Memory System and Programming 184 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Set Baud Rate lt Baud Rate gt lt stop bit gt Table 144 ISP Set Baud Rate command description Command B MR Baud Rate 9600 19200 38400 57600 115200 230400 P Stop bit 1 2 CMD SUCCESS Retin Gods INVALID BAUD RATE INVALID STOP BIT PARAM ERROR This command is used to change the baud rate The new baud rate is effective after the command handler sends the CMD SUCCESS return code Example B 57600 1 lt CR gt lt LF gt sets the serial port to baud rate 57600 bps and 1 stop bit Table 145 Correlation between possible ISP baudrates and external crystal frequency in MHz ISP Baudrate VS 9600 19200 38400 57600 External Crystal Frequency 10 0000 11 0592 12 2880 14 7456 lio T A px wm A SL cem o 1 SL A ee ja s a o 9 oL mes o pp Flash Memory System and Programming 185 September 17 2003 Philips Semiconductors Preliminary User Manual A
104. When the two values are equal actions can be triggered automatically The action possibilities are to generate an interrupt reset the PWM Timer Counter or stop the timer Actions are controlled by the settings in the PWMMCR register Pulse Width Modulator PWM 152 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 PWM Match Control Register PWMMCR 0xE0014014 The PWM Match Control Register is used to control what operations are performed when one of the PWM Match Registers matches the PWM Timer Counter The function of each of the bits is shown in Table 118 Table 118 PWM Match Control Register PWMMCR 0xE0014014 Reset PWMMCR Function Description Value When one an interrupt is generated when PWMMRO matches the value in the PWMTC When zero this interrupt is disabled 1 Reset on PWMMRO When one the PWMTC will be reset if PWMMRO matches it When zero this feature is disabled When one the PWMTC and PWMPC will be stopped and PWMTCRT O0 will be set to 2 Stop on PWMMRO 0 if PWMMRO matches the PWMTC When zero this feature is disabled When one an interrupt is generated when PWMMR 1 matches the value in the intemupt on Pyy MMP PWMTC When zero this interrupt is disabled 4 Reset on PWMMR1 E the PWMTC will be reset if PWMMR1 matches it When zero this feature 0 Interrupt on PWMMRO 0 5 Stop on PWMMR1 When one the PWMTC and PWMPC will be stopped and PWMTCR 0
105. al 14 VPB peripheral 13 VPB peripheral 12 Pin Connect Block VPB peripheral 11 GPIO VPB peripheral 10 RTC VPB peripheral 9 SPI VPB peripheral 8 Fe VPB peripheral 7 VPB peripheral 6 PWMO VPB peripheral 5 UART1 VPB peripheral 4 UARTO VPB peripheral 3 Timer1 VPB peripheral 2 TimerO VPB peripheral 1 Watchdog Timer VPB peripheral 0 Figure 5 VPB Peripheral Map LPC2106 2105 2104 Memory Addressing 32 OxEO1F FFFF OxEO1F C000 OxE01F 8000 0xE004 4000 0xE004 0000 0xE003 C000 0xE003 8000 0xE003 4000 0xE003 0000 0xE002 C000 0xE002 8000 0xE002 4000 0xE002 0000 OxE001 C000 OxE001 8000 OxE001 4000 OxE001 0000 OxE000 C000 0xE000 8000 0xE000 4000 0xE000 0000 Preliminary User Manual LPC2106 2105 2104 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 LPC2106 2105 2104 MEMORY RE MAPPING AND BOOT BLOCK Memory Map Concepts and Operating Modes The basic concept on the LPC2106 2105 2104 is that each memory area has a natural location in the memory map This is the address range for which code residing in that area is written The bulk of each memory space remains permanently fixed in the same location eliminating the need to have portions of the code designed to run in different address ranges Because of
106. aram1 End Sector Number Should be greater than or equal to start sector number CMD SUCCESS Status Code BUSY INVALID SECTOR AR LA Q 2222 This command must be executed before executing Copy RAM to Flash or Erase Sector s command Successful execution ofthe Copy RAM to Flash or Erase Sector s command causes relevant sectors to be protected again The boot sector can not be prepared by this command To prepare a single sector use the same Start and End sector numbers Description Flash Memory System and Programming 195 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Copy RAM to Flash Table 160 IAP Copy RAM to Flash command description Command Copy RAM to Flash Command code 51 ParamO DST Destination Flash address where data bytes are to be written The destination address should be a 512 byte boundary Input Param1 SRO Source RAM address from which data bytes are to be read This address should be on word boundary Param2 Number of bytes to be written Should be 512 1024 4096 8192 Param3 System Clock Frequency CCLK in KHz CMD SUCCESS SRC ADDR ERROR Address not on word boundary DST ADDR ERROR Address not on correct boundary SRC ADDR NOT MAPPED Status Code DST ADDR NOT MAPPED COUNT ERROR Byte count is not 512 1024 4096 8192 SECTOR NOT PREPARED FOR WRITE OPERATION BUSY A
107. as 0 0 combination This prevents the possibility of the PLL being connected without also being enabled The PLL is active and has been connected as the system clock source PLLFEED Register PLLFEED 0xE01FC08C A correct feed sequence must be written to the PLLFEED register in order for changes to the PLLCON and PLLCFG registers to take effect The feed sequence is 1 Write the value OxAA to PLLFEED 2 Write the value 0x55 to PLLFEED System Control Block 46 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 The two writes must be in the correct sequence and must be consecutive VPB bus cycles The latter requirement implies that interrupts must be disabled for the duration of the PLL feed operation If either of the feed values is incorrect or one of the previously mentioned conditions is not met any changes to the PLLCON or PLLCFG register will not become effective Table 17 PLL Feed Register PLLFEED 0xE01FC08C Reset PLLFEED Function Description Value The PLL feed sequence must be written to this register in order for PLL configuration and control register changes to take effect 7 0 PLLFEED undefined PLL and Power Down Mode Power Down mode automatically turns off and disconnects the PLL Wakeup from Power Down mode does not automatically restore the PLL settings this must be done in software Typically a routine to activate the PLL wait
108. as been given see PLLFEED Register PLLFEED 0xE01FC08C description Calculations for the PLL frequency and multiplier and divider values are found in the PLL Frequency Calculation section Table 14 PLL Configuration Register PLLCFG 0xE01FC084 PLLCFG Function Description 4 0 MSEL4 0 PLL Multiplier value Supplies the value M in the PLL frequency calculations PSEL1 0 PLL Divider value Supplies the value P in the PLL frequency calculations Reserved user software should not write ones to reserved bits The value read from a 7 Reserved Sn NA reserved bit is not defined PLLSTAT Register PLLSTAT 0xE01FC088 The read only PLLSTAT register provides the actual PLL parameters that are in effect at the time it is read as well as the PLL status PLLSTAT may disagree with values found in PLLCON and PLLCFG because changes to those registers do not take effect until a proper PLL feed has occurred see PLLFEED Register PLLFEED 0xE01FC08C description System Control Block 45 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Table 15 PLL Status Register PLLSTAT 0xE01FC088 PLLSTAT Function Description MSEL4 0 Read back for the PLL Multiplier value This is the value currently used by the PLL PSEL1 0 Read back for the PLL Divider value This is the value currently used by the PLL Reserved user software should not write ones to reserved bit
109. ata information related to the pipeline status All packets are eight bits in length A packet is output over two cycles In the first cycle Packet 3 0 is output and in the second cycle Packet 7 4 is output EXTIN 0 External Trigger Input TRACEPKTT 3 0 Output Embedded Trace Macrocell 208 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 REGISTER DESCRIPTION The ETM contains 29 registers as shown in Table 172 below They are described in detail in the ARM IHI 0014E document published by ARM Limited which is available via the Internet at http www arm com Table 172 ETM Registers Register encoding 000 0000 ETM Control Controls the general operation of the ETM Read Write 000 0001 ETM Configuration Code Allows a debugger to read the number of each type of resource Read Only 000 0010 Trigger Event Holds the controlling event Write Only 000 0011 Memory Map Decode Control nube register used to statically configure the memory map Write Only 000 0100 ETM Status Holds the pending overflow status bit Read Only 000 0101 System Configuration Holds the configuration information using the SYSOPT bus Read Only 000 0110 Trace Enable Control 3 Holds the trace on off addresses Write Only wem wees L e L ome EE Goral Fose rert sae were UC wem mem p Wwe mem L AA Name Description Access E
110. atch register set to 6 At the end of the timer cycle where the match occurs the timer count is reset This gives a full length cycle to the match value The interrupt indicating that a match occurred is generated in the next clock after the timer reached the match value Figure 29 shows a timer configured to stop and generate an interrupt on match The prescaler is again set to 2 and the match register set to 6 In the next clock after the timer reaches the match value the timer enable bit in TCR is cleared and the interrupt indicating that a match occurred is generated pclk Prescale Counter Timer Counter Timer Counter Reset Interrupt Figure 28 A timer cycle in which PR 2 MRx 6 and both interrupt and reset on match are enabled pclk Prescale Counter Timer Counter TCR 0 Counter Enable Interrupt Figure 29 A timer cycle in which PR 2 MRx 6 and both interrupt and stop on match are enabled Timer 0 and Timer 1 140 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 ARCHITECTURE The block diagram for Timer O and Timer 1is shown in Figure 30 Match Control Register External Match Register Interrupt Register Control MAT 3 0 Interrupt CAP 3 0 Stop on Match Reset on Match Load 3 0 Capture Control Register
111. atch 0 Match 2 Match 1 Match 2 4 Match 0 Match 4 Match 3 Match 4 Match 0 Match 5 Match 4 2 Match 5 2 6 Match 0 Match 6 Match 5 Match 6 Match 0 Match 3 Match 2 Match 3 Notes 1 Identical to single edge mode in this case since Match 0 is the neighboring match register Essentially PWM1 cannot be a double edged output 2 It is generally not advantageous to use PWM channels 3 and 5 for double edge PWM outputs because it would reduce the number of double edge PWM outputs that are possible Using PWM 2 PWM4 and PWM6 for double edge PWM outputs provides the most pairings Pulse Width Modulator PWM 146 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Rules for Single Edge Controlled PWM Outputs 1 All single edge controlled PWM outputs go high at the beginning of a PWM cycle unless their match value is equal to 0 2 Each PWM output will go low when its match value is reached If no match occurs i e the match value is greater than the PWM rate the PWM output remains continuously high Rules for Double Edge Controlled PWM Outputs Five rules are used to determine the next value of a PWM output when a new cycle is about to begin 1 The match values for the next PWM cycle are used at the end of a PWM cycle a time point which is coincident with the beginning of the next PWM cycle except as noted in rule 3 2 A match value equal to 0 or the current PWM rate
112. ate via one serial bus Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer The 12C bus may be used for test and diagnostic purposes APPLICATIONS Interfaces to external I C standard parts such as serial RAMs LCDs tone generators etc DESCRIPTION A typical 12C bus configuration is shown in Figure 17 Depending on the state of the direction bit R W two types of data transfers are possible on the 12C bus Data transfer from a master transmitter to a slave receiver The first byte transmitted by the master is the slave address Next follows a number of data bytes The slave returns an acknowledge bit after each received byte Data transfer from a slave transmitter to a master receiver The first byte the slave address is transmitted by the master The slave then returns an acknowledge bit Next follows the data bytes transmitted by the slave to the master The master returns an acknowledge bit after all received bytes other than the last byte At the end of the last received byte a not acknowledge is returned The master device generates all of the serial clock pulses and the START and STOP conditions A transfer is ended with a STOP condition or with a repeated START condition Since a repeated START condition is also the beginning of the next serial transfer the 12C bus will not be released This device provides a byte oriented C interface It has four operating modes
113. ay minus the stop bit wnenever THRE 1 and there have not been at least two characters in the U1THR at one time since the last THRE 1 event This delay is provided to give the CPU time to write data to U1 THR without a THRE interrupt to decode and service A THRE interrupt is set immediately if the UART1 THR FIFO has held two or more characters at one time and currently the U1THR is empty The THRE interrupt is reset when a U1THR write occurs or a read of the U1IIR occurs and the THRE is the highest interrupt U11IR3 12001 The modem interrupt U11IR3 12000 is the lowest priority interrupt and is activated whenever there is any state change on modem inputs pins DCD DSR or CTS In addition a low to high transition on modem input RI will generate a modem interrupt The source of the modem interrupt can be determined by examining U1MSR3 0 A U1MSR read will clear the modem interrupt UART 1 102 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 UART1 FIFO Control Register U1FCR 0xE0010008 The U1FCR controls the operation of the UART1 Rx and Tx FIFOs Table 79 UART1 FCR Bit Descriptions U1FCR 0xE0010008 Function Description Active high enable for both UART1 Rx and Tx FIFOs and U1FCR7 1 access This bit FIFO Enable must be set for proper UART1 operation Any transition on this bit will automatically clear the UART1 FIFOs Rx FIFO Reset Writing a logic 1 to U1 FCR1
114. ber 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 VIC REGISTERS This section describes the VIC registers in the order in which they are used in the VIC logic from those closest to the interrupt request inputs to those most abstracted for use by software For most people this is also the best order to read about the registers when learning the VIC Software Interrupt Register VICSoftint OXFFFFF018 Read Write The contents of this register are ORed with the 32 interrupt requests from the various peripherals before any other logic is applied Table 31 Software Interrupt Register VICSoftlnt OXFFFFF018 Read Write VICSoftInt Function Reset Value 1 force the interrupt request with this bit number 31 0 0 do not force the interrupt request with this bit number Writing zeroes to bits in VICSoftInt has no effect see VICSoftIntClear Software Interrupt Clear Register VICSoftintClear OXFFFFF01C Write Only This register allows software to clear one or more bits in the Software Interrupt register without having to first read it Table 32 Software Interrupt Clear Register VICSoftIntClear OXFFFFF01C Write Only VICSoftlntClear Function Reset Value 1 writing a 1 clears the corresponding bit in the Software Interrupt register thus releasing 31 0 the forcing of this request 0 writing a O leaves the corresponding bit in VICSoftlnt unchanged
115. bit The time of break detection is dependent on U1FCRO The break interrupt is associated with the character being read from the UART1 RBR FIFO 0 U1THR contains valid data 1 U1THR is empty THRE is set immediately upon detection of an empty U1THR and is cleared on a U1THR write 0 UTTHR and or the U1TSR contains valid data Transmitter 1 U1THR and the U1TSR are empty Empty TEMT TEMT is set when both THR and TSR are empty TEMT is cleared when either the U1TSR or the U1THR contain valid data 0 U1RBR contains no UART1 Rx errors or U1FCRO 0 1 U1RBR contains at least one UART1 Rx error U1LSR7 is set when a character with a Rx error such as framing error parity error or break interrupt is loaded into the U1RBR This bit is cleared when the U1LSR register is read and there are no subsequent errors in the UART1 FIFO Transmitter Holding Register Empty THRE Error in Rx FIFO RXFE UART 1 106 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 UART1 Modem Status Register U1MSR 0x0xE0010018 The U1MSR is a read only register that provides status information on the modem input signals UT MSR3 0 is cleared on U1MSR read Note that modem signals have no direct affect on UART1 operation they facilitate software implementation of modem signal operations Table 83 UART1 Modem Status Register Bit Descriptions U1MSR 0x0xE0010018 Function Descrip
116. cation Register U1IIR OXE0010008 Read Only The U1IIR provides a status code that denotes the priority and source of a pending interrupt The interrupts are frozen during an U1IIR access If an interrupt occurs during an U1IIR access the interrupt is recorded for the next U1IIR access Table 77 UART1 Interrupt Identification Register Bit Descriptions IIR OXE0010008 Read Only Function Description 0 At least one interrupt is pending Interrupt 1 No pending interrupts Pending Note that U1IIRO is active low The pending interrupt can be determined by evaluating U1IIRS 1 U1IER3 identifies an interrupt corresponding to the UART1 Rx FIFO and modem signals All other combinations of U1IER3 1 not listed above are reserved 100 101 111 Reserved user software should not write ones to reserved bits The value read from a 5 Reserved NS NA reserved bit is not defined 4 FIFO Enable These bits are equivalent to U1FCRO 011 1 Receive Line Status RLS 010 2a Receive Data Available RDA Interrupt 110 2b Character Time out Indicator CTI 3 1 Identification 001 3 THRE Interrupt 000 4 Modem Interrupt Interrupts are handled as described in Table 78 Given the status of U1IIR 3 0 an interrupt handler routine can determine the cause of the interrupt and how to clear the active interrupt The U1IIR must be read in order to clear the interrupt prior to exiting the Interrupt Service Routine The UART1 RLS interru
117. ce that would indicate to the host that a read or write of the U1SCR has occurred Table 84 UART1 Scratchpad Register U1SCR 0xE001001C Description A readable writable byte UART 1 108 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 ARCHITECTURE The architecture of the UART1 is shown below in the block diagram The VPB interface provides a communications link between the CPU or host and the UART1 The UART1 receiver block U1Rx monitors the serial input line RxD1 for valid input The UART1 Rx Shift Register U1RSR accepts valid characters via RxD1 After a valid character is assembled in the U1RSR it is passed to the UART1 Rx Buffer Register FIFO to await access by the CPU or host via the generic host interface The UART1 transmitter block U1Tx accepts data written by the CPU or host and buffers the data in the UART1 Tx Holding Register FIFO U1THR The UART1 Tx Shift Register U1TSR reads the data stored in the U1THR and assembles the data to transmit via the serial output pin TxD1 The UART1 Baud Rate Generator block U1BRG generates the timing enables used by the UART1 Tx block The U1BRG clock input source is the VPB clock pclk The main clock is divided down per the divisor specified in the U1DLL and u1DLM registers This divided down clock is a 16x oversample clock NBAUDOUT The modem interface contains registers Uf MCR and U1MSR This inter
118. ch The UART1 Divisor Latch LSB Register along with the U1DLM register determines the LSB Register baud rate of the UART1 UART 1 99 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Table 75 UART1 Divisor Latch MSB Register U1DLM 0xE0010004 when DLAB 1 Function Description Divisor Latch The UART1 Divisor Latch MSB Register along with the U1 DLL register determines the MSB Register baud rate of the UART1 UART1 Interrupt Enable Register U1IER 0xE0010004 when DLAB 0 The U1IER is used to enable the four interrupt sources Table 76 UART1 Interrupt Enable Register Bit Descriptions U1IER 0xE0010004 when DLAB 0 Function Description 0 Disable the RDA interrupt RBR Interrupt 1 Enable the RDA interrupt Enable U1IERO enables the Receive Data Available interrupt for UART1 It also controls the Receive Time out interrupt 0 Disable the THRE interrupt THRE Interrupt 1 Enable the THRE interrupt Enable U1IER1 enables the THRE interrupt for UART1 The status of this interrupt can be read from U1LSR5 0 Disable the Rx line status interrupts Rx Line Status 1 Enable the Rx line status interrupts 0 Disable the modem interrupt 1 Enable the modem interrupt UART 1 100 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 UART1 Interrupt Identifi
119. ch registers when they are used for PWM generation When software writes to the location of a PWM Match register while the Timer is in PWM mode the value is held in a shadow register When a PWM Match 0 event occurs normally also resetting the timer in PWM mode the contents of shadow registers will be transferred to the actual Match registers if the corresponding bit in the Latch Enable Register has been set At that point the new values will take effect and determine the course of the next PWM cycle Once the transfer of new values has taken place all bits of the LER are automatically cleared Until the corresponding bit in the PWMLER is set and a PWM Match 0 event occurs any value written to the PWM Match registers has no effect on PWM operation For example if PWM2 is configured for double edge operation and is currently running a typical sequence of events for changing the timing would be Write a new value to the PWM Match1 register Write a new value to the PWM Match register Write to the PWMLER setting bits 1 and 2 at the same time The altered values will become effective at the next reset of the timer when a PWM Match 0 event occurs The order of writing the two PWM Match registers is not important since neither value will be used until after the write to PWMLER This insures that both values go into effect at the same time if that is required A single value may be altered in the same way if needed The function of
120. cillator Input Input to the oscillator and internal clock generator circuits Output Crystal Oscillator Output Output from the oscillator amplifier External Interrupt Input 0 An active low general purpose interrupt input This pin may be used to wake up the processor from Idle or Power down modes LOW level on this pin immediately after reset is considered as an external hardware request to start the ISP command handler More details on ISP and Flash memory can be found in Flash Memory System and Programming chapter External Interrupt Input 1 See the EINTO description above External Interrupt Input 2 See the EINTO description above Input External Reset input A low on this pin resets the chip causing I O ports and peripherals P to take on their default states and the processor to begin execution at address 0 System Control Block 37 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 REGISTER DESCRIPTION All registers regardless of size are on word address boundaries Details of the registers appear in the description of each function Table 5 Summary of System Control Registers Address Description Access External Interrupts 0xE01FC140 EXTINT External interrupt flag register RW o OxEO1FC144 EXTWAKE External interrupt wakeup register RW 0 Memory Mapping Control 0xE01FC040 MEMMAP Memory mapping control Rwf o
121. ctions for the purpose of saving power A few peripheral functions cannot be turned off i e the Watchdog timer GPIO the Pin Connect block and the System Control block Each bit in PCONP controls one peripheral as shown in Table 22 The bit numbers correspond to the related peripheral number as shown in the VPB peripheral map in the LPC2106 2105 2104 Memory Addressing section Table 22 Power Control for Peripherals Register PCONP 0xE01FC0C4 Function Description Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined 0 Reserved Z gt PCPWMO When 1 PWM 0 is enabled When 0 PWM 0 is disabled to conserve power User software should not write ones to reserved bits The value read from a reserved Reserved in 2 bit is not defined 7 PCI2C When 1 the 12C interface is enabled When 0 the 12C interface is disabled to conserve power PCSPI When 1 the SPI interface is enabled When 0 the SPI interface is disabled to conserve power PCRTC When 1 the RTC is enabled When 0 the RTC is disabled to conserve power Reserved user software should not write ones to reserved bits The value read from a 31 10 Reserved Pu reserved bit is not defined 1 1 1 1 1 NA 1 1 NA Eu System Control Block 50 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 RESET Reset has two sourc
122. d gt ADDR ERROR Address not on word boundary Return Code ADDR NOT MAPPED COUNT ERROR Byte count is not multiple of 4 PARAM ERROR This command is used to read data from RAM or Flash memory Example X R 1073741824 4 lt CR gt lt LF gt reads 4 bytes of data from address 0x4000 0000 Flash Memory System and Programming 187 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Prepare sector s for write operation lt start sector number gt lt end sector number gt This command makes flash write erase operation a two step process Table 149 ISP Prepare sector s for write operation command description Command P Input Start Sector Number End Sector Number Should be greater than or equal to start sector number CMD SUCCESS BUSY Return Code INVALID_SECTOR PARAM_ERROR This command must be executed before executing Copy RAM to Flash or Erase Sector s Deseo command Successful execution of the Copy RAM to Flash or Erase Sector s command causes P relevant sectors to be protected again The boot sector can not be prepared by this command To prepare a single sector use the same Start and End sector numbers Example P 0 0 lt CR gt lt LF gt prepares the flash sector 0 Copy RAM to Flash Flash address RAM address number of bytes gt Table 150 ISP Copy RAM to Flash command description Command C Flash Add
123. d VPB peripheral areas are 2 megabyte spaces which are divided up into 128 peripherals Each peripheral space is 16 kilobytes in size This allows simplifying the address decoding for each peripheral All peripheral register addresses are word aligned to 32 bit boundaries regardless of their size This eliminates the need for byte lane mapping hardware that would be required to allow byte 8 bit or half word 16 bit accesses to occur at smaller boundaries An implication of this is that word and half word registers must be accessed all at once For example it is not possible to read or write the upper byte of a word register separately LPC2106 2105 2104 Memory Addressing 30 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Vectored Interrupt Controller OxFFFF F000 4G 4K OxFFFF C000 AHB peripheral 126 OxFFFF 8000 AHB peripheral 125 OxFFFF 4000 AHB peripheral 124 OxFFFF 0000 OxFFE1 0000 AHB peripheral 3 OxFFEO C000 AHB peripheral 2 OxFFEO 8000 AHB peripheral 1 OxFFEO 4000 AHB peripheral 0 OxFFEO 0000 Figure 4 AHB Peripheral Map LPC2106 2105 2104 Memory Addressing 31 September 17 2003 Philips Semiconductors ARM based Microcontroller System Control Block VPB peripheral 4127 VPB peripheral 126 VPB peripheral 16 VPB peripheral 15 VPB peripher
124. d instruction by using the following code MSR cpsr c 10x52 Disable irq move to IRQ mode RealMonitor 219 Non vectored app irqDispatch mentioned in this example User can setup September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 MSR spsr r12 Restore SPSR from r12 STMFD sp r0 LDR r0 VICBaseAddr STR rl r0 VICVectAddrOffset Acknowledge Non Vectored irq has finished LDMFD sp r12 r14 r0 Restore registers SUBS pc r14 4 Return to the interrupted instruction user interrupt did not happen so call rm irghandler2 This handler is not aware of the VIC interrupt priority hardware so trick rm irghandler2 to return here STMFD sp ip pc LDR pc rm irqghandler2 rm_irghandler2 returns here MSR cpsr c 0x52 Disable irq move to IRQ mode MSR spsr r12 Restore SPSR from r12 STMFD sp r0 LDR r0 VICBaseAddr STR rl r0 VICVectAddrOffset Acknowledge Non Vectored irq has finished LDMFD sp r12 r14 r0 Restore registers SUBS pc r14 4 Return to the interrupted instruction END RealMonitor 220 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 REALMONITOR BUILD OPTIONS RealMonitor was built with the following options RM_OPT_DATALOGGING FALSE This option enables or disables support for any target to host packets sent on a
125. d sequence has taken place FUN values controlling the PLL as well as the status of the PLL This register enables loading of the PLL control and configuration information 0xE01FC08C PLLFEED from the PLLCON and PLLCFG registers into the shadow registers that actually Read back register for PLL control and configuration information If PLLCON or PLLCFG have been written to but a PLL feed sequence has not yet occurred 0 E01FC088 RELSTA they will not reflect the current PLL state Reading this register provides the actual affect PLL operation System Control Block 43 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Clock Synchronization Direct 0 PSEL 1 0 po 0 Phase Frequency Detector msel lt 4 0 gt MSEL 4 0 Figure 9 PLL Block Diagram PLLCON Register PLLCON 0xE01FC080 The PLLCON register contains the bits that enable and connect the PLL Enabling the PLL allows it to attempt to lock to the current settings of the multiplier and divider values Connecting the PLL causes the processor and all chip functions to run from the PLL output clock Changes to the PLL CON register do not take effect until a correct PLL feed sequence has been given see PLLFEED Register PLLFEED 0xE01FCO8C description System Control Block 44 September 17 2003 Philips Semiconductors Prelimi
126. data stored in used bits only It does not include reserved bits content gt o o o L 0 y O E O Z gt Enable Modem Status Interrupt Enable Rx Line Status Interrupt Enable THRE Interrupt Available Interrupt FIFO Enable EJE O JJ 3 m z M M SB SB LS B LS UART1 contains twelve 8 bit registers as shown in Table 71 The Divisor Latch Access Bit DLAB is contained in U1LCR7 and enables access to the Divisor Latches UART 1 98 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 UART1 Receiver Buffer Register U1RBR 0xE0010000 when DLAB 0 Read Only The U1RBR is the top byte of the UART1 Rx FIFO The top byte of the Rx FIFO contains the oldest character received and can be read via the bus interface The LSB bit 0 represents the oldest received data bit If the character received is less than 8 bits the unused MSBs are padded with zeroes The Divisor Latch Access Bit DLAB in U1LCR must be zero in order to access the U1RBR The U1RBR is always Read Only Table 72 UART1 Receiver Buffer Register U1RBR 0xE0010000 when DLAB 0 Read Only Reset Value Function Description Receiver Buffer The UART1 Receiver Buffer Register contains the oldest received byte in the UART1 Rx un Register FIFO defined UART1 Transmitter Holding Register U1THR 0xE0010000 when DLAB 0 Write Only Th
127. de oscillation the fundamental frequency is represented by L C and Rs Capacitance Cp in Figure 7 drawing c represents the parallel package capacitance and should not be larger than 7 pF Parameters Fc CL Rg and Cp are supplied by the crystal manufacturer LPC2106 2105 2104 LPC2106 2105 2104 x1 X2 x1 x2 Figure 7 Oscillator modes and models a slave mode of operation b oscillation mode of operation C external crystal model used for Cxyx2 evaluation Table 6 Recommended values for Cx4 x2 when oscillation mode is used Fundamental Oscillation Crystal Load Max Crystal Series External Load Frequency Fc Capacitance C Resistence Rs Capacitors Cy4 Cxo 10 pF lt 300 18 pF 18 pF System Control Block 39 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 EXTERNAL INTERRUPT INPUTS The LPC2106 2105 2104 includes three External Interrupt Inputs as selectable pin functions The External Interrupt Inputs can optionally be used to wake up the processor from Power Down mode Register Description The external interrupt function has two registers associated with it The EXTINT register contains the interrupt flags and the EXTWAKEUP register contains bits that enable individual external interrupts to wake up the LPC2106 2105 2104 from Power Down mode
128. ded to clarify the function of the PWM rather than to suggest a specific design implementation Figure 31 PWM block diagram Pulse Width Modulator PWM 145 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 A sample of how PWM values relate to waveform outputs is shown in Figure 32 PWM output logic is shown in Figure 31 that allows selection of either single or double edge controlled PWM outputs via the muxes controlled by the PWMSELn bits The match register selections for various PWM outputs is shown in Table 113 This implementation supports up to N 1 single edge PWM outputs or N 1 2 double edge PWM outputs where N is the number of match registers that are implemented PWM types can be mixed if desired The waveforms below show a single PWM cycle and demonstrate PWM outputs under the following conditions The timer is configured for PWM mode The Match register values are as follows Match 0 is configured to reset the timer counter MRO 100 PWM rate when a match event occurs MR1 41 MR2 78 PWM output Control bits PWMSEL2 and PWMSELA are set MR3 53 MR4 27 PWM4 output MR5 65 PWM5 output counter is reset Figure 32 Sample PWM waveforms Table 113 Set and Reset inputs for PWM Flip Flops PWM Single Edge PWM PWMSELn 0 Double Edge PWM PWMSELn 1 Channel Set by Reset by Set by Reset by 1 Match 0 Match 1 Match 0 Match 1 1 M
129. der is to allow power savings when an application does not require any peripherals to run at the full processor rate The connection of the VPB Divider relative to the oscillator and the processor clock is shown in Figure 11 Because the VPB Divider is connected to the PLL output the PLL remains active if it was running during Idle mode VPBDIV Register VPBDIV 0xE01FC100 The VPB Divider register contains two bits allowing three divider values as shown in Table 24 Table 23 VPBDIV Register Map Address Name Description Access 0xE01FC100 VPBDIV Controls the rate of the VPB clock in relation to the processor clock R W Table 24 VPB Divider Register VPBDIV 0xE01FC100 VPBDIV Function Description The rate of the VPB clock is as follows 0 0 VPB bus clock is one fourth of the processor clock 0 1 VPB bus clock is the same as the processor clock VPBDIV 1 0 VPB bus clock is one half of the processor clock 1 1 Reserved If this value is written to the VPBDIV register it has no effect the previous setting is retained Reserved user software should not write ones to reserved bits The value read from a 7 2 Reserved ra NA reserved bit is not defined System Control Block 52 September 17 2003 Philips Semiconductors ARM based Microcontroller Crystal Oscillator or External Clock Source Fosc VPB Divider Figure 11 VPB Divider Connections System Control Block 53 Preliminary
130. details on RMTarget functionality see the RealMonitor Target Integration Guide ARM DUI 0142A Debugger RDI 1 5 1 RealMonitor dll RMHost h RDI 1 5 1rt Y JTAG unit RealMonitor protocol A DCC transmissions Y over the JTAG link Target RMTarget Board and m Processor Application Figure 44 RealMonitor components RealMonitor 212 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 How RealMonitor works In general terms the RealMonitor operates as a state machine as shown in Figure 45 RealMonitor switches between running and stopped states in response to packets received by the host or due to asynchronous events on the target RMTarget supports the triggering of only one breakpoint watchpoint stop or semihosting SWI at a time There is no provision to allow nested events to be saved and restored So for example if user application has stopped at one breakpoint and another breakpoint occurs in an IRQ handler RealMonitor enters a panic state No debugging can be performed after RealMonitor enters this state MN Figure 45 RealMonitor as a state machine A debugger such as the ARM eXtended Debugger AXD or other RealMonitor aware debugger that runs on a host computer can connect to the target to send commands and receive data This communication between host and target
131. e User must therefore allow sufficient stack space for both RealMonitor and application RealMonitor has the following stack requirements Table 173 RealMonitor stack requirement Processor Mode RealMonitor Stack Usage Bytes Undef 48 IRQ mode A stack for this mode is always required RealMonitor uses two words on entry to its interrupt handler These are freed before nested interrupts are enabled Undef mode A stack for this mode is always required RealMonitor uses 12 words while processing an undefined instruction exception SVC mode RealMonitor makes no use of this stack Prefetch Abort mode RealMonitor uses four words on entry to its Prefetch abort interrupt handler Data Abort mode RealMonitor uses four words on entry to its data abort interrupt handler User System mode RealMonitor makes no use of this stack FIQ mode RealMonitor makes no use of this stack RealMonitor 215 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Handling exceptions This section describes the importance of sharing exception handlers between RealMonitor and user application RealMonitor exception handling To function properly RealMonitor must be able to intercept certain interrupts and exceptions Figure 46 illustrates how exceptions can be claimed by RealMonitor itself or shared between RealMonitor and application If user application requires the
132. e IAP routine should be called with a word pointer in register rO pointing to memory RAM containing command code and parameters Result of the IAP command is returned in the result table pointed to by register r1 The user can reuse the command table for result by passing the same pointer in registers rO and r1 The parameter table should be big enough to hold all the results in case if number of results are more than number of parameters Parameter passing is illustrated in the Figure 39 The number of parameters and results vary according to the IAP command The maximum number of parameters is 5 passed to the Copy RAM to FLASH command The maximum number of results is 2 returned by the Blank check sector s command The command handler sends the status code INVALID COMMAND when an undefined command is received The IAP routine resides at OX7FFFFFFO location and it is thumb code The IAP function could be called in the following way using C Define the IAP location entry point Since the Oth bit of the IAP location is set there will be a change to Thumb instruction set when the program counter branches to this address define IAP LOCATION Ox7ffffffl Define data structure or pointers to pass IAP command table and result table to the IAP function unsigned long command 5 unsigned long result 2 or unsigned long command unsigned long result command unsigned long Ox result unsigned long Ox Define pointer to function ty
133. e U1THR is the top byte of the UART1 Tx FIFO The top byte is the newest character in the Tx FIFO and can be written via the bus interface The LSB represents the first bit to transmit The Divisor Latch Access Bit DLAB in U1LCR must be zero in order to access the U1THR The U1THR is always Write Only Table 73 UART1 Transmit Holding Register U1THR 0xE0010000 when DLAB 0 Write Only Function Description Writing to the UART1 Transmit Holding Register causes the data to be stored in the UART1 transmit FIFO The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available Transmit Holding Register UART1 Divisor Latch LSB Register U1DLL 0xE0010000 when DLAB 1 UART1 Divisor Latch MSB Register U1DLM 0xE0010004 when DLAB 1 The UART1 Divisor Latch is part of the UART1 Baud Rate Generator and holds the value used to divide the VPB clock pclk in order to produce the baud rate clock which must be 16x the desired baud rate The U1DLL and U1DLM registers together form a 16 bit divisor where U1DLL contains the lower 8 bits of the divisor and U1DLM contains the higher 8 bits of the divisor A h0000 value is treated like a h0001 value as division by zero is not allowed The Divisor Latch Access Bit DLAB in U1LCR must be one in order to access the UART1 Divisor Latches Table 74 UART1 Divisor Latch LSB Register U1DLL 0xE0010000 when DLAB 1 Function Description Divisor Lat
134. e edge mode Ww 2003 g 2 2 PWM Match Register 1 MR1 can be enabled through MCR to reset the TC stop both the TC and PC and or generate an interrupt when it matches the TC 0xE001401C ENVIMIMES In addition a match between MR1 and the TC clears PWM1 in either single edge mode or double edge mode and sets PWMe if it is in double edge mode PWM Match Register 2 MR2 can be enabled through MCR to reset the TC stop both the TC and PC and or generate an interrupt when it matches the TC 0xE0014020 nude In addition a match between MR2 and the TC clears PWMe in either single edge mode or double edge mode and sets PWM3 if it is in double edge mode PWM Match Register 3 MR3 can be enabled through MCR to reset the TC stop both the TC and PC and or generate an interrupt when it matches the TC SAUDITA PINIM In addition a match between MR3 and the TC clears PWMS in either single edge mode or double edge mode and sets PWMA if it is in double edge mode PWM Match Register 4 MR4 can be enabled through MCR to reset the TC stop both the TC and PC and or generate an interrupt when it matches the TC ad HL In addition a match between MR4 and the TC clears PWMA in either single edge mode or double edge mode and sets PWMB if it is in double edge mode 0 E Pulse Width Modulator PWM 149 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Table 115 Pulse Width Modulator Re
135. e end of a serial transfer The 12C interface will enter master transmitter mode when software sets the STA bit The 12C logic will send the START condition as soon as the bus is free After the START condition is transmitted the SI bit is set and the status code in I2STAT should be 08h This status code must be used to vector to an interrupt service routine which should load the slave address and Write bit to I2DAT Data Register and then clear the SI bit SI is cleared by writing a 1 to the SIC bit in the I2CONCLR register 12C Interface 112 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 When the slave address and R W bit have been transmitted and an acknowledgment bit has been received the SI bit is set again and the possible status codes now are 18h 20h or 38h for the master mode or 68h 78h or OBOh if the slave mode was enabled by setting AA 1 The appropriate actions to be taken for each of these status codes are shown in Table 3 to Table 6 in 80C51 Family Derivatives 8XC552 562 Overview datasheet available on line at http www semiconductors philips com acrobat various 8XC552_5620VERVIEW_2 paf Slave Address R W DATA A e 4 0 Write Data al 1 Read n Bytes Acknowledge A Acknowledge SDA low From Master to Slave A Not Acknowledge SDA high From Slave to Master S START condition P STOP Condition
136. e integer portion of the RTC prescaler value 0 Prescaler Fraction Register PREFRAC 0xE0024084 This is the fractional portion of the prescale value and may be calculated as PREFRAC pclk PREINT 1 x 32768 Table 136 Prescaler Fraction Register PREFRAC 0xE0024084 PREFRAC Function Description Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined Prescaler Fraction Contains the fractional portion of the RTC prescaler value A Reserved Real Time Clock 168 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Example of Prescaler Usage In a simplistic case the pclk frequency is 65 537 kHz So PREINT int pclk 32768 1 1 and PREFRAC pclk PREINT 1 x 32768 1 With this prescaler setting exactly 32 768 clocks per second will be provided to the RTC by counting 2 pclks 32 767 times and 3 pclks once In a more realistic case the pclk frequency is 10 MHz Then PREINT int pclk 32768 1 2 304 and PREFRAC pclk PREINT 1 x 32768 5 760 In this case 5 760 of the prescaler output clocks will be 306 305 1 pclks long the rest will be 305 pclks long In a similar manner any pclk rate greater than 65 536 kHz as long as it is an even number of cycles per second may be turned into a 32 kHz reference clock for the RTC The only caveat is that if PREFRAC do
137. e interface is in master mode and transmits a START condition thereafter If the 12C interface is in slave mode an internal STOP condition is generated but is not transmitted on the bus 12C Interface 117 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 12EN 12C Interface Enable When I2EN is 1 the I C function is enabled I2EN can be cleared by writing 1 to the I2ENC bit in the I2 CONCLR register When I2EN is 0 the I C function is disabled Table 87 12C Control Set Register I2ZCONSET 0xE001C000 I2CONSET Function Description Reserved user software should not write ones to reserved bits The value read from Reserved a reserved bit is not defined Reserved user software should not write ones to reserved bits The value read from Reserved a reserved bit is not defined Assert acknowledge flag 9 s pono So SU o SW SAT o MN In Reserved user software should not write ones to reserved bits The value read from Reserved d a reserved bit is not defined 12C Control Clear Register IZCONCLR 0xE001C018 m m Table 88 12C Control Clear Register I2CONCLR 0xE001C018 I2CONCLR Function Description Reserved user software should not write ones to reserved bits The value read from FERNE a reserved bit is not defined Assert Acknowledge Clear bit Writing a 1 to this bit clears the AA bit in the I2CONSET re
138. e of 0 to 23 Minutes value in the range of 0 to 59 Reserved user software should not write ones to reserved bits The value read from a reserved 7 6 Reserved nh bit is not defined Seconds value in the range of 0 to 59 Consolidated Time Register 1 CTIME1 0xE0024018 Reserved user software should not write ones to reserved bits The value read from a reserved 15 14 Reserved A bit is not defined The Consolidate Time Register 1 contains the Day of Month Month and Year values Table 129 Consolidated Time Register 1 Bits CTIME1 0xE0024018 CTIME1 Function Description Reserved user software should not write ones to reserved bits The value read from a reserved 31 28 Reserved bit is not defined 27 16 Year value in the range of 0 to 4095 Reserved user software should not write ones to reserved bits The value read from a reserved 15 12 Reserved n bit is not defined Month value in the range of 1 to 12 Reserved user software should not write ones to reserved bits The value read from a reserved 7 5 Reserved nh bit is not defined Day of Month Day of month value in the range of 1 to 28 29 30 or 31 depending on the month and whether itis a leap year Real Time Clock 164 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Consolidated Time Register 2 CTIME2 0xE002401C The Consolidate Time Register 2 contains
139. e system Allows user time critical interrupt code to continue executing while other user application code is being debugged APPLICATIONS Real time debugging DESCRIPTION RealMonitor is a lightweight debug monitor that allows interrupts to be serviced while user debug their foreground application It communicates with the host using the DCC Debug Communications Channel which is present in the EmbeddedICE logic RealMonitor provides advantages over the traditional methods for debugging applications in ARM systems The traditional methods include Angel a target based debug monitor e Multi ICE or other JTAG unit and EmbeddedICE logic a hardware based debug solution Although both of these methods provide robust debugging environments neither is suitable as a lightweight real time monitor Angel is designed to load and debug independent applications that can run in a variety of modes and communicate with the debug host using a variety of connections such as a serial port or ethernet Angel is required to save and restore full processor context and the occurrence of interrupts can be delayed as a result Angel as a fully functional target based debugger is therefore too heavyweight to perform as a real time monitor Multi ICE is a hardware debug solution that operates using the EmbeddedICE unit that is built into most ARM processors To perform debug tasks such as accessing memory or the processor registers Multi ICE must plac
140. e the CPU is not running continuously Idle mode Real Time Clock 157 September 17 2003 Philips Semiconductors ARM based Microcontroller ARCHITECTURE Clock Generator Time Counters Counter Enables REGISTER DESCRIPTION clk32k Strobe Preliminary User Manual LPC2106 2105 2104 Reference Clock Divider Prescaler Comparators Counter Increment Interrupt Enable Interrupt Generator Figure 33 RTC block diagram Alarm Registers Alarm Mask Register The RTC includes a number of registers The address space is split into four sections by functionality The first eight addresses are the Miscellaneous Register Group The second set of eight locations are the Time Counter Group The third set of eight locations contain the Alarm Register Group The remaining registers control the Reference Clock Divider The Real Time Clock includes the register shown in Table 121 Detailed descriptions of the registers follow Real Time Clock 158 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Table 121 Real Time Clock Register Map Address Name Size Description 0xE0024000 ILR 2 Interrupt Location Register 0xE0024004 Clock Tick Counter EATA 0xE0024008 CCR 4 Clock Control Register RW 0xE002400C CIIR EN Counter Increment Interrupt Register RW 0xE0024010 EEE Alarm Mask Register RW 0xE0024014 CTIMEO
141. e the core into a debug state While the processor is in this state which can be millions of cycles normal program execution is suspended and interrupts cannot be serviced RealMonitor combines features and mechanisms from both Angel and Multi ICE to provide the services and functions that are required In particular it contains both the Multi ICE communication mechanisms the DCC using JTAG and Angel like support for processor context saving and restoring RealMonitor is pre programmed in the on chip Flash memory boot sector When enabled It allows user to observe and debug while parts of application continue to run Refer to section How to Enable RealMonitor for details RealMonitor 211 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 RealMonitor Components As shown in Figure 44 RealMonitor is split in to two functional components RMHost This is located between a debugger and a JTAG unit The RMHost controller RealMonitor dll converts generic Remote Debug Interface RDI requests from the debugger into DCC only RDI messages for the JTAG unit For complete details on debugging a RealMonitor integrated application from the host see the ARM RMHost User Guide ARM DUI 0137A RMTarget This is pre programmed in the on chip Flash memory boot sector and runs on the target hardware It uses the EmbeddedICE logic and communicates with the host using the DCC For more
142. each of the bits in the PWMLER is shown in Table 120 Table 120 PWM Latch Enable Register PWMLER 0xE0014050 PWMLER Function Description Enable PWM Writing a one to this bit allows the last value written to the PWM Match 0 register to be 0 become effective when the timer is next reset by a PWM Match event See the Match 0 Latch description of the PWM Match Control Register PWMMCR Writing a one to this bit allows the last value written to the PWM Match 1 register to be become effective when the timer is next reset by a PWM Match event See the description of the PWM Match Control Register PIWMMCR Enable PWM Match 1 Latch Writing a one to this bit allows the last value written to the PWM Match 2 register to be become effective when the timer is next reset by a PWM Match event See the description of the PWM Match Control Register PIWMMCR Enable PWM Match 2 Latch Writing a one to this bit allows the last value written to the PWM Match 3 register to be become effective when the timer is next reset by a PWM Match event See the description of the PWM Match Control Register PIWMMCR Enable PWM Match 3 Latch become effective when the timer is next reset by a PWM Match event See the Match 4 Latch description of the PWM Match Control Register PWMMCR Writing a one to this bit allows the last value written to the PWM Match 5 register to be become effective when the timer is next reset by a PWM Match event See
143. ed and TCR O will be set to 0 if MR3 matches P the TC When zero this feature is disabled 2 3 4 5 7 1 Timer 0 and Timer 1 137 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Capture Registers CRO CR3 Each Capture register is associated with a device pin and may be loaded with the Timer Counter value when a specified event occurs on that pin The settings in the Capture Control Register register determine whether the capture function is enabled and whether a capture event happens on the rising edge of the associated pin the falling edge or on both edges Capture Control Register CCR Timer 0 TOCCR 0xE0004028 Timer 1 TI CCR 0xE0008028 The Capture Control Register is used to control whether one of the four Capture Registers is loaded with the value in the Timer Counter when the capture event occurs and whether an interrupt is generated by the capture event Setting both the rising and falling bits at the same time is a valid configuration resulting in a capture event for both edges Table 110 Capture Control Register CCR Timer 0 TOCCR 0xE0004028 Timer 1 T1CCR 0xE0008028 Reset Function D ription unctio escriptio Value Capture on capture 0 When one a sequence of 0 then 1 on capture 0 will cause CRO to be loaded with rising edge the contents of the TC When zero this feature is disabled 1 Capture on capture 0 When one a se
144. eiver should respond with RESEND lt CR gt lt LF gt In response the sender should retransmit the bytes A description of UU encode is available at http www wotsit org ISP Flow control A software XON XOFF flow control scheme is used to prevent data loss due to buffer overrun When the data arrives rapidly the ASCII control character DC3 stop is sent to stop the flow of data Data flow is resumed by sending the ASCII control character DC1 start The host should also support the same flow control scheme ISP Command Abort Commands can be aborted by sending the ASCII control character ESC This feature is not documented as a command under ISP Commands section Once the escape code is received the ISP command handler waits for a new command Interrupts during ISP Boot block Interrupt vectors located in the boot sector of the flash are active after any reset Interrupts during IAP The on chip flash memory is not accessible during erase write operations When the user application code starts executing the interrupt vectors from the user flash area are active The user should either disable interrupts or ensure that user interrupt vectors are active in RAM and that the interrupt handlers reside in RAM before making a flash erase write IAP call The IAP code does not use or disable interrupts RAM used by ISP command handler ISP commands use on chip RAM from 0x4000 0120 to 0x4000 01FF The user could use this area but the content
145. ember 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 SPI Interface 132 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 13 TIMER O AND TIMER 1 Timer O and Timer 1 are functionally identical except for the peripheral base address FEATURES A 32 bit Timer Counter with a programmable 32 bit Prescaler Upto four Timer 1 and three Timer 0 32 bit capture channels that can take a snapshot of the timer value when an input signal transitions A capture event may also optionally generate an interrupt Four 32 bit match registers that allow Continuous operation with optional interrupt generation on match Stop timer on match with optional interrupt generation Reset timer on match with optional interrupt generation Up to four Timer 1 and three Timer 0 external outputs corresponding to match registers with the following capabilities Setlow on match Sethigh on match Toggle on match Do nothing on match APPLICATIONS Interval Timer for counting internal events Pulse Width Demodulator via Capture inputs Free running timer Timer O and Timer 1 133 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 DESCRIPTION The Timer is designed to count cycles of the peripheral clock pclk and optionally generate inte
146. emiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 In order to preclude the possibility of stale data being read from the Flash memory the MAM holding latches are automatically invalidated at the beginning of any Flash programming or erase operation Any subsequent read from a Flash address will cause a new fetch to be initiated after the Flash operation has completed MEMORY ACCELERATOR MODULE OPERATING MODES Three modes of operation are defined for the MAM trading off performance for ease of predictability 0 MAM off All memory requests result in a Flash read operation see note 2 below There are no instruction prefetches 1 MAM partially enabled Sequential instruction accesses are fulfilled from the holding latches if the data is present Instruction prefetch is enabled Non sequential instruction accesses initiate Flash read operations see note 2 below This means that all branches cause memory fetches All data operations cause a Flash read because buffered data access timing is hard to predict and is very situation dependent 2 MAM fully enabled Any memory request code or data for a value that is contained in one of the corresponding holding latches is fulfilled from the latch Instruction prefetch is enabled Flash read operations are initiated for instruction prefetch and code or data values not available in the corresponding holding latches Table 25 MAM Responses to Program Accesses of Various
147. er Timer O and Timer 1 136 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Prescale Counter Register PC Timer 0 TOPC 0xE0004010 Timer 1 T1PC 0xE0008010 The 32 bit Prescale Counter controls division of pclk by some constant value before it is applied to the Timer Counter This allows control of the relationship of the resolution of the timer versus the maximum time before the timer overflows The Prescale Counter is incremented on every pclk When it reaches the value stored in the Prescale Register the Timer Counter is incremented and the Prescale Counter is reset on the next pclk This causes the TC to increment on every pclk when PR 0 every 2 pclks when PR 1 etc Match Registers MRO MR3 The Match register values are continuously compared to the Timer Counter value When the two values are equal actions can be triggered automatically The action possibilities are to generate an interrupt reset the Timer Counter or stop the timer Actions are controlled by the settings in the MCR register Match Control Register MCR Timer 0 TOMCR 0xE0004014 Timer 1 T1MCR 0xE0008014 The Match Control Register is used to control what operations are performed when one of the Match Registers matches the Timer Counter The function of each of the bits is shown in Table 109 Table 109 Match Control Register MCR Timer 0 TOMCR 0xE0004014 Timer 1 TIMCR 0xE0008
148. er then accessing the SPI data register SPI transfer complete flag When 1 this bit indicates when a SPI data transfer is complete When a master this bit is set at the end of the last cycle of the transfer When a slave this bit is set on the last data sampling edge of the SCK This bit is cleared by first reading this register then accessing the SPI data register Note this is not the SPI interrupt flag This flag is found in the SPINT registrer SPI Data Register SPDR 0xE0020008 This bi directional data register provides the transmit and receive data for the SPI Transmit data is provided to the SPI by writing to this register Data received by the SPI can be read from this register When a master a write to this register will start a SPI data transfer Writes to this register will be blocked from when a data transfer starts to when the SPIF status bit is set and the status register has not been read Table 102 SPI Data Register SPDR 0xE0020008 Function Description Data SPI Bi directional data port SPI Clock Counter Register SPCCR 0xE002000C This register controls the frequency of a master s SCK The register indicates the number of pclk cycles that make up an SPI clock The value of this register must always be an even number As a result bit O must always be 0 The value of the register must also always be greater than or equal to 8 Violations of this can result in unpredictable behavior Table 103
149. er mode llli eh 115 Figure 25 2C Archilecture eos os Aa eee ae E 122 Figure 26 SPI Data Transfer Format CPHA 0 and CPHA 2 1 lssseseseleee eese 124 Figure 27 SPI Block Diagram es o RR Slade a A REET ROOM BERE Sent 131 Figure 28 A timer cycle in which PR 2 MRx 6 and both interrupt and reset on match are enabled 140 Figure 29 A timer cycle in which PR 2 MRx 6 and both interrupt and stop on match are enabled 140 Figure 30 Timer block diagrams scine cystes irani ngana ik a RII IIR In 141 Figure 31 PWM block diagram iseleelee RR tte 145 Figure 32 Sample PWM waveforms 0 06 cee mm 146 Figure 33 RTC block diagram 6 eee teeta 158 Figure 34 RTC Prescaler block diagram 1 0 2 cect n 169 Figure 35 Watchdog Block Diagram 0 0 et tte ae 175 Figure 36 Flash Sector Map 0 2 0 0 cee mmm 178 Figure 37 Map of lower memory after any reset 0 0 0 cece tte eae 179 Figure 38 Boot Process flowchart lille tte tenes 182 Figure 39 IAP Parameter passidQ o oooooocrrrrrr nent ae 195 Figure 40 EmbeddedICE Debug Environment Block Diagram 0 00 anaana eee 204 Figure 41 Waveforms for normal operation not in debug mode n essas ananuna anera 205 Figure 42 Waveforms for Debug mode using the primary JTAG pins 000 ce eee eee 206 Figure 43 ETM Debug Environment Block Diagram lise 210 Figure 44 RealMonitor co
150. erals to device pins is controlled by a Pin Connection Block This must be configured by software to fit specific application requirements for the use of peripheral functions and pins ARM7TDMI S PROCESSOR The ARM7TDMI S is a general purpose 32 bit microprocessor which offers high performance and very low power consumption The ARM architecture is based on Reduced Instruction Set Computer RISC principles and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers This simplicity results in a high instruction throughput and impressive real time interrupt response from a small and cost effective processor core Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously Typically while one instruction is being executed its successor is being decoded and a third instruction is being fetched from memory The ARM7TDMI S processor also employs a unique architectural strategy known as THUMB which makes it ideally suited to high volume applications with memory restrictions or applications where code density is an issue The key idea behind THUMB is that of a super reduced instruction set Essentially the ARM7TDMI S processor has two instruction sets The standard 32 bit ARM instruction set A 16 bit THUMB instruction set The THUNB set s 16 bit instruction length allows it to approach twice the density of standard
151. eration command descripti0N o ooo o o 188 Table 150 ISP Copy RAM to Flash command description 2l 188 Table 151 ISP Go command description oooococcccococncro nn 189 Table 152 ISP Erase sector command description oooococcccconcnc eee 189 Table 153 ISP Blank check sector s command description oococoocccocoocroro eee 190 Table 154 ISP Read Part ID command description ooococcccccncncc eee 190 Table 155 ISP Read Boot Code version command description llli iles esses 190 Table 156 ISP Compare command description o oooococococcnocoa ees 191 Table 157 ISP Return Codes Summary 1 0 2 00 c en 192 Table 158 IAP Command Summary liliis hn 194 Table 159 IAP Prepare sector s for write operation command descripti0N o oooooooo 195 Table 160 IAP Copy RAM to Flash command description 20 0c cece eens 196 Table 161 IAP Erase Sector s command description 000 cece eee 196 Table 162 IAP Blank check sector s command description 0 0 00 ee eee 197 Table 163 IAP Read Part ID command description ooooooooccoccro eee 197 Table 164 IAP Read Boot Code version command description 000 c eee ee eee ee 197 11 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Table 165 IAP Compare command description 0oooocococccoocona
152. es not contain a zero then not all of the 32 768 per second clocks are of the same length Some of the clocks are one pclk longer than others While the longer pulses are distributed as evenly as possible among the remaining pulses this jitter could possibly be of concern in an application that wishes to observe the contents of the Clock Tick Counter CTC directly To Clock Tick pclk Counter VPB Clock Clk 13 bit Integer Counter 15 bit Fraction Counter Down Counter Underflow Reload mbinatorial Logi ET Combinatorial Logic Reload 13 bit Reload Integer Register 15 bit Fraction Register PREINT PREFRAC Figure 34 RTC Prescaler block diagram Real Time Clock 169 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Real Time Clock 170 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 16 WATCHDOG FEATURES Internally resets chip if not periodically reloaded Debug mode Enabled by software but requires a hardware reset or a Watchdog reset interrupt to be disabled Incorrect Incomplete feed sequence causes reset interrupt if enabled Flag to indicate Watchdog reset Programmable 32 bit timer with internal pre scaler Selectable time period from tpoik x 256 x 4 to tpoik x 29 x 4 in multiples of tpoik x 4 APPLICATIONS The purpose of the Watchdog is to res
153. es on the LPC2106 2105 2104 the RST pin and Watchdog Reset The RST pin is a Schmitt trigger input pin with an additional glitch filter Assertion of chip Reset by any source starts the Wakeup Timer see Wakeup Timer description later in this chapter causing reset to remain asserted until the external Reset is de asserted the oscillator is running a fixed number of clocks have passed and the Flash controller has completed its initialization The relationship between Reset the oscillator and the Wakeup Timer are shown in Figure 10 The Reset glitch filter allows the processor to ignore external reset pulses that are very short and also determines the minimum duration of RST that must be asserted in order to guarantee a chip reset Details of the reset timing requirements can be found in the LPC2106 2105 2104 data sheet DC Specifications When the internal Reset is removed the processor begins executing at address 0 which is the Reset vector At that point all of the processor and peripheral registers have been initialized to predetermined values External and internal Resets have some small differences An external Reset causes the value of certain pins to be latched to configure the part External circuitry cannot determine when an internal Reset occurs in order to allow setting up those special pins so those latches are not reloaded during an internal Reset Pins that are examined during an external Reset for various purposes are DBGSEL RTCK
154. esents the first bit to transmit The Divisor Latch Access Bit DLAB in UOLCR must be zero in order to access the UOTHR The UOTHR is always Write Only Table 60 UARTO Transmit Holding Register UOTHR OXE000C000 when DLAB 0 Write Only Function Description Writing to the UARTO Transmit Holding Register causes the data to be stored in the UARTO transmit FIFO The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available Transmit Holding Register UARTO Divisor Latch LSB Register UODLL 0xE000C000 when DLAB 1 UARTO Divisor Latch MSB Register UODLM 0xE000C004 when DLAB 1 The UARTO Divisor Latch is part of the UARTO Baud Rate Generator and holds the value used to divide the VPB clock pclk in order to produce the baud rate clock which must be 16x the desired baud rate The UODLL and UODLM registers together form a 16 bit divisor where UODLL contains the lower 8 bits of the divisor and UODLM contains the higher 8 bits of the divisor A h0000 value is treated like a h0001 value as division by zero is not allowed The Divisor Latch Access Bit DLAB in UOLCR must be one in order to access the UARTO Divisor Latches Table 61 UARTO Divisor Latch LSB Register UODLL OXE000C000 when DLAB 1 Function Description Divisor Latch The UARTO Divisor Latch LSB Register along with the UODLM register determines the LSB Register baud rate of the UARTO Function Description
155. et the microcontroller within a reasonable amount of time if it enters an erroneous state When enabled the Watchdog will generate a system reset if the user program fails to feed or reload the Watchdog within a predetermined amount of time DESCRIPTION The Watchdog consists of a divide by 4 fixed pre scaler and a 32 bit counter The clock is fed to the timer via a pre scaler The timer decrements when clocked The minimum value from which the counter decrements is OxFF Setting a value lower than OxFF causes OxFF to be loaded in the counter Hence the minimum Watchdog interval is tpg x 256 x 4 and the maximum Watchdog interval is tocik x 292 x 4 in multiples of tocik X 4 The Watchdog should be used in the following manner Setthe Watchdog timer constant reload value in WDTC register Setup mode in WDMOD register Start the Watchdog by writing OxAA followed by 0x55 to the WDFEED register Watchdog should be fed again before the Watchdog counter underflows to prevent reset interrupt When the Watchdog counter underflows the program counter will start from 0x00000000 as in the case of external reset The Watchdog time out flag WDTOF can be examined to determine if the Watchdog has caused the reset condition The WDTOF flag must be cleared by software Watchdog 171 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 REGISTER DESCRIPTION The Watchdog contains
156. eur sed bic eR A tien pe unin a oe REA 127 Table 99 SPI Register Map 0 cece eee mr 128 Table 100 SPI Control Register SPCR 0xXE0020000 ssssssssseee nes 128 Table 101 SPI Status Register SPSR 0xE0020004 o ooococcocco lees 129 Table 102 SPI Data Register SPDR 0xE0020008 oo oooooocococc eee 129 Table 103 SPI Clock Counter Register SPCCR OxE002000C 0 0 eee eese 129 Table 104 SPI Interrupt Register SPINT OXE002001C oocccoccccccocc eh 130 Tabl 105 Pin s imtnary i ioi ue a ete d Rx R AA YD RU e ae Rode X REM 134 Table 106 Timer 0 and Timer 1 Register Map o oocoooccccoocr III 135 Table 107 Interrupt Register IR Timer O TOIR OxE0004000 Timer 1 T1IR OXE0008000 sseseseeessese 136 Table 108 Timer Control Register TCR Timer 0 TOTCR 0xE0004004 Timer 1 T1 TCR 0xE0008004 o o oo o 136 Table 109 Match Control Register MCR Timer 0 TOMCR 0xE0004014 Timer 1 T1MCR 0xE0008014 137 10 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Table 110 Capture Control Register CCR Timer 0 TOCCR OxE0004028 Timer 1 T1CCR 0xE0008028 138 Table 111 External Match Register EMR Timer 0 TOEMR 0xE000403C Timer 1 TTEMR 0xE000803C 139 Table 112 External Match Control ococcccccccc ren 139 Table 1
157. face is responsible for handshaking between a modem peripheral and the UART1 The interrupt interface contains registers U1IER and U1IIR The interrupt interface receives several one clock wide enables from the U1Tx U1Rx and modem blocks Status information from the U1Tx and U1Rx is stored in the U1LSR Control information for the U1Tx and U1Rx is stored in the U1LCR UART 1 109 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 U1INTR NTXRDY TxD1 NBAUDOUT RCLK INTERRUPT ARXRDY U1IER PA 2 0 U1IIR PSEL PSTB PWRITE PD 7 0 VPB Interface AR MR UART 1 Figure 16 UART1 Block Diagram 110 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 11 12C INTERFACE FEATURES Standard 12C compliant bus interface Easy to configure as Master Slave or Master Slave Programmable clocks allow versatile rate control Bidirectional data transfer between masters and slaves Multi master bus no central master Arbitration between simultaneously transmitting masters without corruption of serial data on the bus Serial clock synchronization allows devices with different bit rates to communic
158. for lock and then connect the PLL can be called at the beginning of any interrupt service routine that might be called due to the wakeup It is important not to attempt to restart the PLL by simply feeding it when execution resumes after a wakeup from Power Down mode This would enable and connect the PLL at the same time before PLL lock is established PLL Frequency Calculation The PLL equations use the following parameters Fosc the frequency from the crystal oscillator Foco the frequency of the PLL current controlled oscillator cclk the PLL output frequency also the processor clock frequency M PLL Multiplier value from the MSEL bits in the PLLCFG register P PLL Divider value from the PSEL bits in the PLLCFG register The PLL output frequency when the PLL is both active and connected is given by Foco cclk M Fog or cclk 2 P The CCO frequency can be computed as Foco CCIK 2 P or Fogg Foge M 2 P The PLL inputs and settings must meet the following e Fogg is in the range of 10 MHz to 25 MHz e celk is in the range of 10 MHz to Fmax the maximum allowed frequency for the LPC2106 2105 2104 Foco is in the range of 156 MHz to 320 MHz System Control Block 47 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Procedure for Determining PLL Settings If a particular application uses the PLL its configuration may be determined as follows 1 Choose
159. ger portion and a fractional portion The result is not a continuous output at a constant frequency some clock periods will be one pclk longer than others However the overall result can always be 32 768 counts per second The reference clock divider consists of a 13 bit integer counter and a 15 bit fractional counter The reasons for these counter sizes are as follows 1 For frequencies that are expected to be supported by the LPC2106 2105 2104 a 13 bit integer counter is required This can be calculated as 160 MHz divided by 32 768 minus 1 4881 with a remainder of 26 624 Thirteen bits are needed to hold the value 4881 but actually supports frequencies up to 268 4 MHz 32 768 x 8192 2 The remainder value could be as large as 32 767 which requires 15 bits Table 134 Reference Clock Divider registers Address Name Size Description Access 0xE0024080 PREINT 13 Prescale Value integer portion RAN 0xE0024084 PREFRAC Prescale Value fractional portion R W Prescaler Integer Register PREINT 0xE0024080 This is the integer portion of the prescale value calculated as PREINT int pclk 32768 1 The value of PREINT must be greater than or equal to 1 Table 135 Prescaler Integer Register PREINT 0xE0024080 PREINT Function Description Reserved user software should not write ones to reserved bits The value 15 13 Reserved ur read from a reserved bit is not defined 12 0 Prescaler Integer Contains th
160. gister Writing 0 has no effect 12C Interrupt Clear Bit Writing a 1 to this bit clears the SI bit in the I2CONSET register Writing O has no effect 4 Reserved Reserved user software should not write ones to reserved bits The value read from NA a reserved bit is not defined Start flag clear bit Writing a 1 to this bit clears the STA bit in the I2CONSET register 5 STAC xs NA Writing O has no effect C interface disable Writing a 1 to this bit clears the I2EN bit in the IICONSET I2ENC y 2 NA register Writing O has no effect Reserved user software should not write ones to reserved bits The value read from Reserved Aun 3 a reserved bit is not defined 12C Interface 118 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 12C Status Register I2STAT 0xE001C004 This is a read only register It contains the status code of the 12C interface The least three bits are always 0 There are 26 possible status codes When the code is F8H there is no relevant information available and the SI bit is not set All other 25 status codes correspond to defined IC states When any of these states entered SI bit will be set Refer to Table 3 to Table 6 in 80C51 Family Derivatives 8XC552 562 Overview datasheet available on line at http www semiconductors philips com acrobat various 8XC552_ 5620VERVIEW 2 pdf for a complete list of status codes Table 89 12C Status Register I2ST
161. gister 0 oeme omer sr oonan O C ELA Interrupt Location ILR 0xE0024000 The Interrupt Location Register is a 2 bit register that specifies which blocks are generating an interrupt see Table 123 Writing a one to the appropriate bit clears the corresponding interrupt Writing a zero has no effect This allows the programmer to read this register and write back the same value to clear only the interrupt that is detected by the read Table 123 Interrupt Location Register Bits ILR 0xE0024000 Function Description When one the Counter Increment Interrupt block generated an interrupt Writing a one to this bit location clears the counter increment interrupt When one the alarm registers generated an interrupt Writing a one to this bit location clears the 1 RTCALF alarm interrupt Clock Tick Counter CTC 0xE0024004 The Clock Tick Counter is read only It can be reset to zero through the Clock Control Register CCR The CTC consists of the bits of the clock divider counter RTCCIF Table 124 Clock Tick Counter Bits CTC 0xE0024004 Function Description Reserved user software should not write ones to reserved bits The value read from a reserved bit Reseed is not defined Prior to the Seconds counter the CTC counts 32 768 clocks per second Due to the RTC Prescaler these 32 768 time increments may not all be of the same duration Refer to the Reference Clock Divider Prescaler description
162. gister Map Address Name Description PWM Match Register 5 MR5 can be enabled through MCR to reset the TC stop both the TC and PC and or generate an interrupt when it matches the TC 0xE0014044 SERM TUS In addition a match between MR5 and the TC clears PWM5 in either single edge mode or double edge mode and sets PWM6 if it is in double edge mode PWM Match Register 6 MR6 can be enabled through MCR to reset the TC stop both the TC and PC and or generate an interrupt when it matches the TC OAEI OASI Mo In addition a match between MR6 and the TC clears PWM6 in either single edge mode or double edge mode OxE001404C PWMPCR PWM Control Register Enables PWM outputs and selects PWM channel types as either single edge or double edge controlled 0xE0014050 PWMLER PWM Latch Enable Register Enables use of new PWM match values Reset Value refers to the data stored in used bits only It does not include reserved bits content Pulse Width Modulator PWM 150 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 PWM Interrupt Register PWMIR 0xE0014000 The PWM Interrupt Register consists of eleven bits Table 116 seven for the match interrupts and four reserved for the future use If an interrupt is generated then the corresponding bit in the PWMIR will be high Otherwise the bit will be low Writing a logic one to the corresponding IR bit will reset the interru
163. hecking 0 0 Disable break transmission Break Control 1 Enable break transmission Output pin UART1 TxD is forced to logic O when U1LCRE is active high 00 Odd parity 01 Even parity Parity Select 10 Forced 1 stick parity 11 Forced 0 stick parity 7 Divisor Latch 0 Disable access to Divisor Latches Access Bit 1 Enable access to Divisor Latches UART 1 104 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 UART1 Modem Control Register U1MCR 0xE0010010 The U1MCR enables the modem loopback mode and controls the modem output signals Table 81 UART1 Modem Control Register Bit Descriptions U1MCR 0xE0010010 Function Description Source for modem output pin DTR This bit reads as 0 when modem loopback mode is active 1 RTS Control Source for modem output pin RTS This bit reads as 0 when modem loopback mode is active Reserved user software should not write ones to reserved bits The value read from a 2 Reserved Lx NA reserved bit is not defined Reserved user software should not write ones to reserved bits The value read from a 3 Reserved ie NA reserved bit is not defined 0 DTR Control 0 Disable modem loopback mode 1 Enable modem loopback mode The modem loopback mode provides a mechanism to perform diagnostic loopback testing Serial data from the transmitter is connected internally to serial input of the receiver
164. ide this if the pin is left unconnected in the application Details of Debug mode may be found in EmbeddedICE Logic chapter m This column shows the default functionality of each pin during debug mode with the primary JTAG port 3 RTCK is an extra signal added to the JTAG port Multi ICE Development system from ARM uses this signal to maintain synchronization with targets having slow or widely varying clock frequency For details refer to Multi ICE System Design considerations Application Note 72 ARM DAI 0072A RTCK is used as an input when enabling debug mode to choose debug port options Details of Debug mode may be found later in EmbeddedICE Logic chapter PIN DESCRIPTION FOR LPC2106 2105 2104 Pin description for LPC2106 2105 2104 and a brief of corresponding functions are shown in the following table Table 46 Pin description and corresponding functions for LPC2106 2105 2104 operation of port O pins depends upon the pin function selected via the Pin Connect Block P0 0 TxDO PWM1 RxDO PWM3 SCL CAPO 0 SDA MATO O SCK CAPO 1 MISO MATO 1 MOSI CAPO0 2 SSEL PWM2 TxD1 PWM4 RxD1 PWM6 Pin Configuration Transmitter output for UART 0 Pulse Width Modulator output 1 Receiver input for UART 0 Pulse Width Modulator output 3 12C clock input output Open drain output for C compliance Capture input for Timer 0 channel 0 12C data input output Open drain output for C compliance
165. ided the system conforms to the 12C specifications defined by Philips This specification can be ordered using the code 9398 393 40011 Definitions Short form specification The data in a short form specification is extracted from a full data sheet with the same type number and title For detailed information see the relevant data sheet or data handbook Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System IEC 60134 Stress above one or more of the limiting values may cause permanent damage to the device These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied Exposure to limiting values for extended periods may affect device reliability Application information Applications that are described herein for any of these products are for illustrative purposes only Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification Disclaimers Life support These products are not designed for use in life support appliances devices or systems where malfunction of these products can reasonably be expected to result in personal injury Philips Semiconductors customers using or selling these products for use in such applications do
166. ider 2 IPSCLL4 Bit Frequency kHz At fcc MHz amp VPB Clock Divider 2 12SCLH I2SCLL I2SCLH ETA e mus ms CA 12C Interface 121 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 ARCHITECTURE A Address Register Comparator Input Filter Output Shift Register Stage 4 Bit Counter Arbitration amp Input Sync Logic Filter Timing amp Control Logic VPB BUS Serial Clock Generator I2CONSET Control Register amp SCL Duty I2CONCLR I2SCLH Cycle Registers I2SCLL Status Bus Status Status Register Decoder I2STAT Figure 25 lC Architecture 12C Interface 122 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 12 SPI INTERFACE FEATURES Compliant with Serial Peripheral Interface SPI specification Synchronous Serial Full Duplex Communication Combined SPI master and slave Maximum data bit rate of one eighth of the input clock rate DESCRIPTION SPI Overview The SPI is a full duplex serial interface It is designed to be able to handle multiple masters and slaves being connected to a given bus Only a single master and a single slave can communicate on the interface during a given data transfer During a data transfer the master always sends a byte of data to the slave
167. ines the number of pclk cycles for SCL high IPSCLL defines the number of pclk cycles for SCL low The frequency is determined by the following formula Bit Frequency fci IPSCLH I2SCLL Where fc is the frequency of pclk The values for I2SCLL and I2SCLH don t have to be the same Software can set different duty cycles on SCL by setting these two registers But the value of the register must ensure that the data rate is in the I C data rate range of 0 through 400KHz So the value of I2SCLL and I2SCLH has some restrictions Each register value should be greater than or equal to 4 Table 92 I C SCL High Duty Cycle Register I2SCLH 0xE001C010 Reset I2SCLH Function Description Value 15 0 Count Count for SCL HIGH time period selection Ox 0004 Table 93 I2C SCL Low Duty Cycle Register I2SCLL 0xE001C014 Reset I2SCLL Function Description Value 15 0 Count Count for SCL LOW time period selection Ox 0004 Table 94 12C Clock Rate Selections for VPB Clock Divider 1 12SCLL Bit Frequency kHz At fcc k MHz amp VPB Clock Divider 1 I2SCLH Se gt E c 32 3RE 3 FEL a s ms me m eme mee 800 31 373 39 216 78 431 117 647 1280 15 625 31 25 46 875 12C Interface 120 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Table 95 I2C Clock Rate Selections for VPB Clock Div
168. interface primary JTAG pin group CAP1 3 Capture input for Timer 1 channel 3 TMS Test Mode Select for JTAG interface primary JTAG pin group MAT1 2 Match output for Timer 1 channel 2 TCK Test Clock for JTAG interface primary JTAG pin group MAT1 3 Match output for Timer 1 channel 3 TDI Test Data In for JTAG interface primary JTAG pin group PWM5 Pulse Width Modulator output 5 TDO Test Data Out for JTAG interface primary JTAG pin group TRACECLK Trace Clock Standard I O port with internal pullup PIPESTATO Pipeline Status bit 0 Standard I O port with internal pullup PIPESTAT1 Pipeline Status bit 1 Standard I O port with internal pullup PIPESTAT2 Pipeline Status bit 2 Standard I O port with internal pullup TRACESYNCTrace Synchronization Standard l O port with internal pullup Pin Configuration 74 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Table 46 Pin description and corresponding functions for LPC2106 2105 2104 LQFP 48 a E P0 27 TRACEPKTOTrace Packet bit 0 Standard I O port with internal pullup TRST Test Reset for JTAG interface secondary JTAG pin group E TRACEPKT1Trace Packet bit 1 Standard I O port with internal pullup TMS Test Mode Select for JTAG interface secondary JTAG pin group k TRACEPKT2Trace Packet bit 2 Standard I O port with internal pullup TCK Test Clock for JTAG interface secondary JTAG pin group E TRA
169. ion being debugged RealMonitor stops the user application until a Go packet is received from the host When one of these exceptions occur that is not handled by user application the following happens RealMonitor 213 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 RealMonitor enters a loop polling the DCC If the DCC read buffer is full control is passed to rm ReceiveData RealMonitor internal function If the DCC write buffer is free control is passed to rm TransmitData RealMonitor internal function If there is nothing else to do the function returns to the caller The ordering of the above comparisons gives reads from the DCC a higher priority than writes to the communications link e RealMonitor stops the foreground application Both IRQs and FIQs continue to be serviced if they were enabled by the application at the time the foreground application was stopped RealMonitor 214 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 HOW TO ENABLE REALMONITOR The following steps must be performed to enable RealMonitor A code example which implements all the steps can be found at the end of this section Adding stacks User must ensure that stacks are set up within application for each of the processor modes used by RealMonitor For each mode RealMonitor requires a fixed number of words of stack spac
170. iority 1 After any of IRQ requests SPI I2C UARTO or UART1 is made microcontroller will redirect code execution to the address specified at location 0x00000018 For vectored and non vectored IRQ s the following instruction could be placed at 0x18 LDR pc pc OxFFO This instruction loads PC with the address that is present in VICVectAddr register In case UARTO request has been made VICVectAddr will be identical to VICVectAddrO while in case SPI request has been made value from VICVectAddr1 will be found here If neither UARTO nor SPI have generated IRQ request but UART1 and or Ic were the reason content of VICVectAddr will be identical to VICDefVectAddr Vectored Interrupt Controller VIC 70 September 17 2003 Philips Semiconductors ARM based Microcontroller 6 PIN CONFIGURATION NETCHIP PINOUT P0 19 MAT1 2 TCK P0 20 MAT1 3 TDI P0 21 PWM5 TDO NC Vdd1 8 core RST Vss1 P0 27 TRACEPKTO TRST P0 28 TRACEPKT1 TMS P0 29 TRACEPKT2 TCK X1 X2 Figure 14 LPC2106 2105 2104 48 pin package LOFP48 Pin Configuration O o JOO JO fou B foo Nm al jaj o m P0 13 DTR1 MAT1 1 48 P0 18 CAP1 3 TMS 47 P0 17 CAP1 2 TRST 46 P0 16 EINTO MATO 2 45 P0 15 RI1 EINT2 44 P0 14 DCD1 EINT1 43 Vss4 13 15 41 40 Vdd3 1 1 0 39 P0 26 TRACESYNC 38 P0 25 PIPESTAT2 22 23 37 P0 12 DSR1 MAT1 0 P0 0 TxDO
171. ip PLL allows CPU operation up to the maximum CPU rate May be used over the entire crystal operating range APPLICATIONS Internet gateway Serial communications protocol converter Access control Industrial Control Medical equipment Introduction 15 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 ARCHITECTURAL OVERVIEW The LPC2106 2105 2104 consists of an ARM7TDMI S CPU with emulation support the ARM7 Local Bus for interface to on chip memory controllers the AMBA Advanced High performance Bus AHB for interface to the interrupt controller and the VLSI Peripheral Bus VPB a compatible superset of ARM s AMBA Advanced Peripheral Bus for connection to on chip peripheral functions The LPC2106 2105 2104 configures the ARM7TDMI S processor in little endian byte order AHB peripherals are allocated a 2 megabyte range of addresses at the very top of the 4 gigabyte ARM memory space Each AHB peripheral is allocated a 16 kilobyte address space within the AHB address space LPC2106 05 04 peripheral functions other than the interrupt controller are connected to the VPB bus The AHB to VPB bridge interfaces the VPB bus to the AHB bus VPB peripherals are also allocated a 2 megabyte range of addresses beginning at the 3 5 gigabyte address point Each VPB peripheral is allocated a 16 kilobyte address space within the VPB address space The connection of on chip periph
172. ips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Table 78 UART1 Interrupt Handling Interrupt Interrupt Interrupt U1IIR 3 0 Priority Type Source Reset 0001 none 0110 Highest P ee OE or PE or FE or BI U1LSR Read U1RBR Read or 0100 Second Rx Data Rx data available or trigger level reached in FIFO mode UART1 FIFO Available FCRO 1 drops below trigger level Minimum of one character in the Rx FIFO and no character input or removed during a time period depending on how many Character Time characters are in FIFO and what the trigger level is set at 3 5 1100 Second Pt to 4 5 character times U1RBR Read out Indication The exact time will be word length X 7 2 X 8 trigger level number of characters X 8 1 RCLKs U1IIR Read if 0010 Third THRE THRE Source of interrupt or THR write 0000 Modem Status CTS or DSR or RI or DCD MSR Read note values 0011 0101 0111 1000 1001 1010 1011 1101 1110 1111 are reserved The UART1 THRE interrupt U1IIR3 1 001 is a third level interrupt and is activated when the UART1 THR FIFO is empty provided certain initialization conditions have been met These initialization conditions are intended to give the UART1 THR FIFO a chance to fill up with data to eliminate many THRE interrupts from occurring at system start up The initialization conditions implement a one character del
173. is effective only when the DBGSEL input is pulled LOW during RESET Table 49 Pin Function Select Register 1 PINSEL1 0xE002C004 PINSEL1 Pin Name Function when 00 Function when 01 Function when 10 Function when 11 1 0 P0 16 GPIO Port 0 16 EINTO Match 0 2 Timer 0 Reserved 3 2 5 4 7 6 Pin Function Select Register Values The PINSEL registers control the functions of device pins as shown below Pairs of bits in these registers correspond to specific device pins Table 50 Pin Function Select Register Bits Pinsel0 and Pinsel1 Values Function Value after Reset Primary default function typically GPIO Port First alternate function Second alternate function Reserved The direction control bit in the IODIR register is effective only when the GPIO function is selected for a pin For other functions direction is controlled automatically Each derivative typically has a different pinout and therefore a different set of functions possible for each pin Details for a specific derivative may be found in the appropriate data sheet Pin Connect Block 79 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Pin Connect Block 80 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 8 GPIO FEATURES Direction control of individual bits Separate control of output set and clear All
174. isters Address Reset Offset Description LSB Access Value TO External 6 reserved bits Eonia 0xE000403C TOEMR Match Register External Match External Match Ext Ext Ext Control 1 Control 0 Mtch2 Mtch 1 Mtch 0 Timer 1 T1 Interrupt CR3 CR2 CR1 CRO MR3 MR2 MR1 MRO T1 Control CTR CTR 0xE0008008 T1TC 32 bit data RWJ o oxE000800c TiPR I Prescale 32 bit data CEN Register T1 Prescale Hcr LN ums lid LES Counter p jes Jon p 4 reserved bits T1 Match ue MES MR3 MEO 0xE0008014 TTMCR Control R W Register REOR d Ben nto pe jo ian MAI MAI mas MRO MRO i oxE0008018 TimRo 1 Match 32 bit data R W Register 0 0xE000801C T1MR1 Match 32 bit data R W Register 1 oxE0008020 T1 MR 1 Match 32 bit data R W Register 2 oxE0008024 rima 1 Match 32 bit data R W Register 3 Int on 4 reserved bits i Cpt 3 T1 Capture gt falling risi 0xE0008028 T1CCR Control R W Register Int on Int on Int on Int on Int on Int on Cpt 2 Cpt 2 Cpt 1 Cpt 1 Cpt 0 Cpt 0 falling rising i falling rising falling rising oxEO00802C TicRo 1 Capture 32 bit data Register O oxE0008030 T1cR1 I Capture 32 bit data Register 1 oxE0008034 TicR2 I Capture 32 bit data Register 2 Introduction 21 September 17 2003 Philips Semiconductors ARM based Microcontroller Table 1 LPC2106 2105 2104 Registers Address Offset
175. ither primary JTAG nor ETM will be enabled and they could not be used for later debugging However in these cases user s application can assign secondary JTAG functions to pins P0 27 to P0 31 While user s code can redirect JTAG communication to the secondary JTAG pins ETM functionality will not be available since ETM and secondary JTAG interface are sharing the same pins and consequently are excluding one another EmbeddedICE Logic 206 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 19 EMBEDDED TRACE MACROCELL FEATURES Closely track the instructions that the ARM core is executing 10 pin interface 1 External trigger input All registers are programmed through JTAG interface Does not consume power when trace is not being used THUMB instruction set support APPLICATIONS As the microcontroller has significant amounts of on chip memories it is not possible to determine how the processor core is operating simply by observing the external pins The ETM provides real time trace capability for deeply embedded processor cores It outputs information about processor execution to a trace port A software debugger allows configuration of the ETM using a JTAG interface and displays the trace information that has been captured in a format that a user can easily understand DESCRIPTION The ETM is connected directly to the ARM core and not to the main AMBA system bus
176. ived synchronization character in terms of its own frequency and programs the baud rate generator of the serial port It also sends an ASCII string Synchronized lt CR gt lt LF gt to the host In response to this the host should send the received string Synchronized lt CR gt lt LF gt The auto baud routine looks at the received characters to verify synchronization If synchronization is verified then OK lt CR gt lt LF gt string is sent to the host The host should respond by sending the crystal frequency in kHz at which the part is running For example if the part is running at 10 MHz a valid response from the host should be 10000 lt CR gt lt LF gt OK lt CR gt lt LF gt string is sent to the host after receiving the crystal frequency If synchronization is not verified then the auto baud routine waits again for a synchronization character For auto baud to work correctly the crystal frequency should be greater than or equal to 10 MHz The on chip PLL is not used by the boot code Once the crystal frequency is received the part is initialized and the ISP command handler is invoked For safety reasons an Unlock command is required before executing commands resulting in flash erase write operations and the Go command The rest of the commands can be executed without the unlock command The Unlock command is required to be executed once per ISP session Unlock command is explained in the ISP Commands section Communication Protoc
177. ize to the data and assume that the bad stop bit is actually an early start bit However it cannot be assumed that the next received byte will be correct even if there is no Framing Error 0 Break interrupt status is inactive 1 Break interrupt status is active When RxDO is held in the spacing state all 0 s for one full character transmission start data parity stop a break interrupt occurs Once the break condition has been detected the receiver goes idle until RxDO goes to marking state all 1 s An UOLSR read clears this status bit The time of break detection is dependent on UOFCRO The break interrupt is associated with the character being read from the UARTO RBR FIFO 0 UOTHR contains valid data 1 UOTHR is empty THRE is set immediately upon detection of an empty UARTO THR and is cleared on a UOTHR write 0 UOTHR and or the UOTSR contains valid data 1 UOTHR and the UOTSR are empty TEMT is set when both UOTHR and UOTSR are empty TEMT is cleared when either the UOTSR or the UOTHR contain valid data 0 UORBR contains no UARTO Rx errors or UOFCRO 0 1 UARTO RBR contains at least one UARTO Rx error UOLSR7 is set when a character with a Rx error such as framing error parity error or break interrupt is loaded into the UORBR This bit is cleared when the UOLSR register is read and there are no subsequent errors in the UARTO FIFO 92 September 17 2003 Philips Semiconductors Preliminary User Manual ARM ba
178. k Ck KKK KARA ck Ck ck ck ck ck ck ck ck Ck Ck ck ck ck ck ck ck ck ck ck ck ck ck ck ck KKK kk ck ko ck ck Sk Sk Mk ko kx ko ko ko ok Set up the stack pointers for various processor modes Stack grows downwards FER KK A RR RR RARA RARA RA RARA RR RARA A A A RARA k ck kc k kc kck ckok ckok kok sk sk ke e e e f LDR r2 ram end Get top of RAM MRS r0 CPSR Save current processor mode Initialize the Undef mode stack for RealMonitor use BIC rl r0 0x1f ORR rl rl 0x1b MSR CPSRc rl Keep top 32 bytes for flash programming routines Refer to Flash Memory System and Programming chapter SUB sp r2 0x1F Initialize the Abort mode stack for RealMonitor BIC rl r0 0x1f ORR rl rl 0x17 MSR CPSR_c rl Keep 64 bytes for Undef mode stack SUB sp r2 0x5F RealMonitor 218 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Initialize the IRQ mode stack for RealMonitor and User BIC rl r0 0x1f ORR rl rl 0x12 MSR CPSR c rl Keep 32 bytes for Abort mode stack SUB sp r2 40x7F Return to the original mode MSR CPSR c EU Initialize the stack for user application Keep 256 bytes for IRQ mode stack SUB sp r2 0x17F BRK IK RR RR RR RARA kk kk kk k k k k k k RARA A A ARA Ck Ck Ck k ck k ck k ck kckokckok kok sk ke kk Setup Vectored Interrupt controller DCC Rx and Tx interrupts generate Non Vectored IRQ request rm init entry is aware
179. k Diagram Watchdog 175 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Watchdog 176 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 17 FLASH MEMORY SYSTEM AND PROGRAMMING This chapter describes the Flash Memory System and the Boot Loader FLASH MEMORY SYSTEM The Flash Memory System contains 16 sectors each of which is 8K bytes in size Flash memory begins at address 0 and continues upward Details may be found in the NetChip Memory Addressing chapter FLASH BOOT LOADER The Boot Loader controls initial operation after reset and also provides the means to accomplish programming of the Flash memory This could be initial programming of a blank device erasure and re programming of a previously programmed device or programming of the Flash memory by the application program in a running system FEATURES In System Programming In System programming ISP is programming as well as reprogramming the on chip flash memory using the boot loader software and a serial port while the part may reside in the end user system In Application Programming In Application IAP programming is performing erase and write operation on the on chip flash memory as directed by the end user application code APPLICATIONS The flash boot loader provides both In System and In Application programming interfaces for progra
180. ked as and these registers must be initialized by software if the RTC is enabled Registers in LPC2106 2105 2104 are 8 16 or 32 bits wide For 8 bit registers shown in Table 1 bit residing in the MSB The Most Significant Bit column corresponds to the bit 7 of that register while bit in the LSB The Least Significant Bit column corresponds to the bit O of the same register If a register is 16 32 bit wide the bit residing in the top left corner of its description is the bit corresponding to the bit 15 31 of the register while the bit in the bottom right corner corresponds to bit 0 of this register Examples bit ENA6 in PWMPCR register address 0xE001404C represents the bit at position 14 in this register bits 15 8 7 and 0 in the same register are reserved Bit Stop on MR6 in PWMMCR register 0xE0014014 corresponds to the bit at position 20 bits 31 to 21 of the same register are reserved Unused reserved bits are marked with and represented as gray fields Access to them is restricted as already described Table 1 LPC2106 2105 2104 Registers Address Offset WD WD Watchdog WD WD WDRE Description Watchdog 0xE0000004 worc er 32 bit data R W OxFF constant register Watchdog WD _ feed 0xE0000008 8 bit data OxAA fallowed by 0x55 WO NA FEED sequence register Introduction 19 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104
181. l modem The complement value of this signal is stored in U1MCRO Ring Indicator Active low signal indicates that a telephone ringing signal has been detected RH liit by the modem In normal operation of the modem interface U1MCR4 0 the complement P value of this signal is stored in UT MSR6 State change information is stored in Uf MSR2 and is a source for a priority level 4 interrupt if enabled U1IER3 1 Request To Send Active low signal indicates that the UART1 would like to transmit data to the external modem The complement value of this signal is stored in U1MCR1 UART 1 97 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 REGISTER DESCRIPTION Table 71 UART 1 Register Map Address Name Description BIT4 BIT3 0xE0010000 Receiver U1RBR Buffer READ DATA DLAB 0 A Register Transmit 0xE0010000 YitHR Holding WRITE DATA DLAB 0 Register Interrupt OxE0010004 U1IER Enable Jn DLAB 0 Register oxEoo10008 uma InierruptID f FIFOs Enabled Register FIFO 0xE0010008 U1FCR Control Rx Trigger Register Line Control Word Length OxE001000C U1LCR Register Select Modem 0xE0010010 U1MCR Control S DTR Register 0xE0010014 UiLSR Line Status TEMT THRE FE PE OE Register Modem ili 0xE0010018 UIMSR Status ate ers Register Scratch Pad 0xE001001C NS LSB 0xE0010000 Divisor Latch 0xE0010004 Divisor Latch Reset Value refers to the
182. lCVectAddr6 Vector address 6 register RW 0 OxFFFF F11C VICVectAddr7 Vector address 7 register RW o OxFFFF F120 VICVectAddr8 Vector address 8 register RW o OxFFFF F124 VICVectAddr9 Vector address 9 register RW o Vectored Interrupt Controller VIC 62 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Table 30 VIC Register Map Reset Value OxFFFF F128 VICVectAddr10 Vector address 10 register R W 0 E O E ELLE 5 ore vowewmnz weramen ree RW 5 orem vow werwmen ree RW 5 ore ne vows weramem rose RW 5 O O ELE EL eer een voco Vector control 0 register Vector Control Registers 0 15 each control one EIE OxFFFF F200 VICVectCntl0 of the 16 vectored IRQ slots Slot 0 has the highest priority and slot 15 R W the lowest Tarr Teno eR ar wer Wowsoms Vedoreonmelsreaser fw ORFF FeiO VOWeOma Wcorcmwdimgse LO Cia vevenne vescoms LO Orea vevenne venres LO a vevenn WcoremwdTmsse LO Derer F veven Vexwcomor wqus WO wer Veven veronese RW LO PEFFE Fees vevenn Weoremwd mds LO A A veeroo RW TO a A Wcoremwkimsr LO ORFF Fase A Vesorconoliereaier RW LO CA voro fwg Perae vovas veron OOOO A Reset Value refers to the data stored in used bits only It does not include reserved bits content Address Description Access Vectored Interrupt Controller VIC 63 Septem
183. le 81 UART1 Modem Control Register Bit Descriptions U1MCR 0xE0010010 105 Table 82 UART1 Line Status Register Bit Descriptions U1LSR 0xE0010014 Read Only 106 Table 83 UART1 Modem Status Register Bit Descriptions U1MSR 0x0xE0010018 107 Table 84 UART1 Scratchpad Register U1SCR OXE001001C 000 108 Table 85 12C Pin Description umi A Aa A 115 Table 86 12C Register Map oococooccccocr mre 116 Table 87 12C Control Set Register I IPCONSET OxE001CO00 0 0 eee 118 Table 88 12C Control Clear Register I2CONCLR 0xE001C018 0 00 eee ees 118 Table 89 12C Status Register IPSTAT OXE001C004 20 lees 119 Table 90 12C Data Register IBDAT 0xE001C008 oocccoccoccocccnc eee eh 119 Table 91 12C Slave Address Register IBADR OXE001C00C oooooccccccccc eene 119 Table 92 12C SCL High Duty Cycle Register IPSCLH OXE001C010 20 0006 120 Table 93 12C SCL Low Duty Cycle Register I2SCLL OXE001C014 02 0 0 120 Table 94 12C Clock Rate Selections for VPB Clock Divider 1 000 c eee eee eee eee 120 Table 95 12C Clock Rate Selections for VPB Clock Divider 2 0 00 e esee 121 Table 96 12C Clock Rate Selections for VPB Clock Divider 4 00 00 c eee eee esse 121 Table 97 SPI Data To Clock Phase Relationship 0 0 cect eh 124 Table 98 SPI PiriDeseription 06 64
184. lue for Minutes R W 0xE0024068 ALHOUR Alarm value for Hours R W m m m m RTC USAGE NOTES Since the RTC operates from the VPB clock pclk any interruption of that clock will cause the time to drift away from the time value it would have provided otherwise The variance could be to actual clock time if the RTC was initialized to that or simply an error in elapsed time since the RTC was activated No provision is made in the LPC2106 2105 2104 to retain RTC status upon power loss or to maintain time incrementation if the clock source is lost interrupted or altered Loss of chip power will result in complete loss of all RTC register contents Entry to Power Down mode will cause a lapse in the time update Altering the RTC timebase during system operation by reconfiguring the PLL the VPB timer or the RTC prescaler will result in some form of accumulated time error Real Time Clock 167 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 REFERENCE CLOCK DIVIDER PRESCALER The reference clock divider hereafter referred to as the Prescaler allows generation of a 32 768 kHz reference clock from any peripheral clock frequency greater than or equal to 65 536 kHz 2 x 32 768 kHz This permits the RTC to always run at the proper rate regardless of the peripheral clock rate Basically the Prescaler divides the peripheral clock pclk by a value which contains both an inte
185. m AMRDOY When one the Day of Year value is not compared for the alarm AMRMON When one the Month value is not compared for the alarm AMRYEAR When one the Year value is not compared for the alarm Real Time Clock 163 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 CONSOLIDATED TIME REGISTERS The values of the Time Counters can optionally be read in a consolidated format which allows the programmer to read all time counters with only three read operations The various registers are packed into 32 bit values as shown in Tables 128 129 and 130 The least significant bit of each register is read back at bit O 8 16 or 24 The Consolidated Time Registers are read only To write new values to the Time Counters the Time Counter addresses should be used Consolidated Time Register 0 CTIMEO 0xE0024014 The Consolidated Time Register 0 contains the low order time values Seconds Minutes Hours and Day of Week Table 128 Consolidated Time Register 0 Bits CTIMEO 0xE0024014 CTIMEO Function Description E Reserved user software should not write ones to reserved bits The value read from a reserved 31 27 Reserved A bit is not defined 26 24 Day of Week Day of week value in the range of 0 to 6 i Reserved user software should not write ones to reserved bits The value read from a reserved 23 21 Reserved bit is not defined 20 16 Hours value in the rang
186. m an error condition in slave mode When STO is 1 in master mode a STOP condition is transmitted on the 12C bus When the bus detects the STOP condition STO is cleared automatically In slave mode setting this bit can recover from an error condition In this case no STOP condition is transmitted to the bus The hardware behaves as if a STOP condition has been received and it switches to not addressed slave receiver mode The STO flag is cleared by hardware automatically STA is the START flag Setting this bit causes the 12C interface to enter master mode and transmit a START condition or transmit a repeated START condition if it is already in master mode When STA is land the IC interface is not already in master mode it enters master mode checks the bus and generates a START condition if the bus is free If the bus is not free it waits for a STOP condition which will free the bus and generates a START condition after a delay of a half clock period of the internal clock generator If the 12C interface is already in master mode and data has been transmitted or received it transmits a repeated START condition STA may be set at any time including when the 12C interface is in an addressed slave mode STA can be cleared by writing 1 to the STAC bit in the IICONCLR register When STA is 0 no START condition or repeated START condition will be generated If STA and STO are both set then a STOP condition is transmitted on the I C bus if it th
187. m into 3 categories FIQ vectored IRQ and non vectored IRQ The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted Fast Interrupt reQuest FIQ requests have the highest priority If more than one request is assigned to FIQ the VIC ORs the requests to produce the FIQ signal to the ARM processor The fastest possible FIQ latency is achieved when only one request is classified as FIQ because then the FIQ service routine can simply start dealing with that device But if more than one request is assigned to the FIQ class the FIQ service routine can read a word from the VIC that identifies which FIQ source s is are requesting an interrupt Vectored IRQs have the middle priority Sixteen of the 32 requests can be assigned to this category Any of the 32 requests can be assigned to any of the 16 vectored IRQ slots among which slot O has the highest priority and slot 15 has the lowest Non vectored IRQs have the lowest priority The VIC ORs the requests from all the vectored and non vectored IRQs to produce the IRQ signal to the ARM processor The IRQ service routine can start by reading a register from the VIC and jumping there If any of the vectored IRQs are requesting the VIC provides the address of the highest priority requesting IRQs service routine otherwise it provides the address of a default routine that is shared by all the non vectored IRQs The default
188. mapped to the bottom mode by User program of the Static RAM User Flash Software activation mode by Boot code LPC2106 2105 2104 Memory Addressing 33 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Memory Re Mapping In order to allow for compatibility with future derivatives the entire Boot Block is mapped to the top of the on chip memory space In this manner the use of larger or smaller flash modules will not require changing the location of the Boot Block which would require changing the Boot Loader code itself or changing the mapping of the Boot Block interrupt vectors Memory spaces other than the interrupt vectors remain in fixed locations Figure 6 shows the on chip memory mapping in the modes defined above The portion of memory that is re mapped to allow interrupt processing in different modes includes the interrupt vector area 32 bytes and an additional 32 bytes for a total of 64 bytes The re mapped code locations overlay addresses 0x0000 0000 through 0x0000 003F A typical user program in the Flash memory can place the entire FIQ handler at address 0x0000 001C without any need to consider memory boundaries The vector contained in the SRAM external memory and Boot Block must contain branches to the actual interrupt handlers or to other instructions that accomplish the branch to the interrupt handlers There are three reasons this configuration was chosen
189. mbedded Trace Macrocell 209 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 BLOCK DIAGRAM The block diagram of the ETM debug environment is shown below in Figure 43 PERIPHERAL TRACE TRACE PORT ETM ANALYZER TRIGGER PERIPHERAL CONNECTOR ARM HOST RUNNING JTAG DEBUGGER E PUE EmbeddedICE CONNECTOR APPLICATION PCB Figure 43 ETM Debug Environment Block Diagram Embedded Trace Macrocell 210 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 20 REALMONITOR RealMonitor is a configurable software module which enables real time debug RealMonitor is developed by ARM Inc Information presented in this chapter is taken from the ARM document HealMonitor Target Integration Guide ARM DUI 0142A It applies to a specific configuration of RealMonitor software programmed in the on chip flash memory of this device Refer to the white paper Real Time Debug for System on Chip available at http www arm com support White Papers OpenDocument for background information FEATURES Allows user to establish a debug session to a currently running system without halting or resetting th
190. minary User Manual ARM based Microcontroller LPC2106 2105 2104 14 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 1 INTRODUCTION FEATURES ARM7TDMI S processor 128 kilobyte on chip Flash Program Memory with In System Programming ISP and In Application Programming IAP capability Flash programming time is 1 ms for up to a 512 byte line Sector erase or chip erase is done in 400 ms 64 32 16 kilobyte Static RAM LPC2106 2105 2104 Vectored Interrupt Controller Emulation Trace Module supports real time trace RealMonitor module enables real time debugging Standard ARM Test Debug interface for compatibility with existing tools e Very small package TQFP48 7x7mm Two UARTS one with full modem interface C serial interface SPI serial interface Two timers each with 4 capture compare channels PWM unit with up to 6 PWM outputs Real Time Clock Watchdog Timer General purpose l O pins CPU operating range up to 60 MHz Dual power supply CPU operating voltage range of 1 65V to 1 95V 1 8V 8 3 O power supply range of 3 0V to 3 6V 3 3V 10 Two low power modes Idle and Power Down Processor wakeup from Power Down mode via external interrupt Individual enable disable of peripheral functions for power optimization On chip crystal oscillator with an operating range of 10 MHz to 25 MHz On ch
191. mming the on chip flash memory DESCRIPTION The flash boot loader code is executed every time the part is powered on or reset The loader can execute the ISP command handler or the user application code A LOW level after reset at the P0 14 pin is considered as the external hardware request to start the ISP command handler This pin is sampled in software Asuming that proper signal is present on X1 pin when the rising edge on RST pin is generated it may take up to 3 ms before P0 14 is sampled and the decision on wether to continue with user code or ISP handler is made If P0 14 is sampled low and the watchdog overflow flag is set the external hardware request to start the ISP command handler is ignored If there is no request for the ISP command handler execution P0 14 is sampled HIGH after reset a search is made for a valid user program If a valid user program is found then the execution control is transferred to it If a valid user program is not found the auto baud routine is invoked Pin P0 14 that is used as hardware request for ISP requires special attention Since P0 14 is in high impedance mode after reset it is important that the user provides external hardware a pull up resistor or other device to put the pin in a defined state Otherwise unintended entry into ISP mode may occur Flash Memory System and Programming 177 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104
192. mponents o occcco m 212 Figure 45 RealMonitor as a state machine lllleeleleel e 213 Figure 46 Exception Handlers encena ey e eee mre 216 7 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 8 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 List of Tables Table 1 LPC2106 2105 2104 Registers 0 0 0 e 19 Table 2 ARM Exception Vector Locati0NS o ooocoooocconooo eee 33 Table 3 LPC2106 2105 2104 Memory Mapping Modes oocococcocccncc ree 33 Table 4 Pin SUMMANY s a RERO a ERR a AA IR 37 Table 5 Summary of System Control Registers oococcccocococc ees 38 Table 6 Recommended values for CX1 X2 when oscillation mode is used o ooooooooooo 39 Table 7 External Interrupt Registers lille I 40 Table 8 External Interrupt Flag Register EXTINT OXEO1FC140 2 0 0 cee eee esee 40 Table 9 External Interrupt Wakeup Register EXTWAKE OXEO1FC144 oooooococcccccocoo oo 41 Table 10 MEMMAP Register llle RR e eee 42 Table 11 Memory Mapping Control Register MEMMAP 0xE01FC040 o ooooooocooocooo 42 Table 12 PEL Heglsters e epe Be EUN ew ence P er E ur eer tios 43 Table 13 PLL Control Register PLLCON OXEO1FC080 ooocooccooccoor ees 45 Table 14 PLL Configuration Register PLLCFG OXEO1FC084
193. nary User Manual ARM based Microcontroller LPC2106 2105 2104 Table 13 PLL Control Register PLLCON 0xE01FC080 PLLCON Function Description 0 PLLE PLL Enable When one and after a valid PLL feed this bit will activate the PLL and allow it to lock to the requested frequency See PLLSTAT register Table 15 PLL Connect When PLLC and PLLE are both set to one and after a valid PLL feed 1 PLLC connects the PLL as the clock source for the LPC2106 2105 2104 Otherwise the oscillator clock is used directly by the LPC2106 2105 2104 See PLLSTAT register Table 15 Reserved user software should not write ones to reserved bits The value read from a 7 2 Reserved ar NA reserved bit is not defined The PLL must be set up enabled and Lock established before it may be used as a clock source When switching from the oscillator clock to the PLL output or vice versa internal circuitry synchronizes the operation in order to ensure that glitches are not generated Hardware does not insure that the PLL is locked before it is connected or automatically disconnect the PLL if lock is lost during operation In the event of loss of PLL lock it is likely that the oscillator clock has become unstable and disconnecting the PLL will not remedy the situation PLLCFG Register PLLCFG 0xE01FC084 The PLLCFG register contains the PLL multiplier and divider values Changes to the PLLCFG register do not take effect until a correct PLL feed sequence h
194. nch occurs there is a distinct possibility that a loop is being executed In this case the Branch Trail Buffers may already contain the target instruction If so execution continues without the need for a Flash read cycle For a forward branch there is also a chance that the new address is already contained in one of the Prefetch Buffers If it is the branch is again taken with no delay When a branch outside the contents of the Branch Trail and Prefetch buffers is taken one Flash Access cycle is needed to load the Branch Trail buffers Subsequently there will typically be no further fetch delays until another such Instruction Miss occurs The Flash memory controller detects data accesses to the Flash memory and uses a separate buffer to store the results in a manner similar to that used during code fetches This allows faster access to data if itis accessed sequentially A single line buffer is provided for data accesses as opposed to the two buffers per Flash bank that are provided for code accesses There is no prefetch function for data accesses Memory Accelerator Module Blocks The Memory Accelerator Module is divided into several functional blocks A Flash Address Latch for each bank An Incrementer function is associated with the Bank O Flash Address latch Two Flash Memory Banks Instruction Latches Data Latches Address Comparison latches Wait logic Figure 12 shows a simplified block diagram of the Memory Accelerator Mod
195. nnect block settings have no affect on P0 17 P0 21 pins if they are initialized as JTAG pins For debugging using the secondary JTAG pins software must configure the related pins to connect the JTAG port This is done via the Pin Connect Block For effect of hardware override related to DBGSEL and RTCK see Table 45 in Pin Configuration chapter Table 169 shows how JTAG port is selected based on DBGSEL RTCLK and user s code executed after the reset EmbeddedICE Logic 205 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 RST pin t Wakeup Timer Count Time Internal Reset DBGSEL SN DBGSEL has to be high _ RTCK must be high as RST is released An internal pullup will cause RTCK to be high if it is not pulled low externally The RTCK output driver will be turned on when the internal chip reset is released by the wakeup timer Figure 42 Waveforms for Debug mode using the primary JTAG pins Table 169 JTAG Pins Selection DBGSEL After Reset Latched RTCK Value JTAG Primary Pins JTAG Secondaty Pins ETM 1 1 Yes No Yes Start up code residing in Flash should configure port pins P0 27 P0 31 for JTAG function by setting appropriate bits in PINSEL1 register Primary JTAG port and ETM can be selected for debugging only when DBGSEL and RTCK pins are high at reset see Figure 42 If atleast one of DBGSEL or RTCK lines is low at reset ne
196. of Month value generates an interrupt IMDOW When one an increment of the Day of Week value generates an interrupt IMDOY When one an increment of the Day of Year value generates an interrupt IMMON When one an increment of the Month value generates an interrupt 7 IMYEAR When one an increment of the Year value generates an interrupt Alarm Mask The Alarm Mask Register AMR allows the user to mask any of the alarm registers Table 127 shows the relationship between the bits in the AMR and the alarms For the alarm function every non masked alarm register must match the corresponding time counter for an interrupt to be generated The interrupt is generated only when the counter comparison first changes from no match to match The interrupt is removed when a one is written to the appropriate bit of the Interrupt Location Register ILR If all mask bits are set then the alarm is disabled Real Time Clock 162 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Table 127 Alarm Mask Register Bits AMR 0xE0024010 Function Description AMRSEC When one the Second value is not compared for the alarm AMRMIN When one the Minutes value is not compared for the alarm AMRHOUR When one the Hour value is not compared for the alarm AMRDOM When one the Day of Month value is not compared for the alarm AMRDOW When one the Day of Week value is not compared for the alar
197. ol All ISP commands should be sent as single ASCII strings Strings should be terminated with Carriage Return CR and or Line Feed LF control characters Extra CR and lt LF gt characters are ignored All ISP responses are sent as lt CR gt lt LF gt terminated ASCII strings Data is sent and received in UU encoded format Flash Memory System and Programming 179 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 ISP Command Format Command Parameter_0 Parameter 1 Parameter_n lt CR gt lt LF gt Data Applicable only in case of Write commands ISP Response Format Return Code CR LF Response O CR LF Response 1 CR LF Response n CR LF Data Applicable in case of Read commands ISP Data Format The data stream is in UU encode format The UU encode algorithm converts 3 bytes of binary data in to 4 bytes of printable ASCII character set It is more efficient than Hex format which converts 1 byte of binary data in to 2 bytes of ASCII hex The sender should send the check sum after transmitting 20 UU encoded lines The length of any UU encoded line should not exceed 61 characters bytes i e it can hold 45 data bytes The receiver should compare it with the check sum of the received bytes If the check sum matches then the receiver should respond with OK lt CR gt lt LF gt to continue further transmission If the check sum does not match the rec
198. om acrobat various 8XC552 5620VERVIEW 2 pdf for the status codes and actions 12C Interface 114 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 ee Slave Address WwW DATA A a NA P RS p rm Data Transferred n Bytes Acknowledge 1 Read Acknowledge SDA low From Master to Slave Not Acknowledge SDA high From Slave to Master START condition STOP Condition S Repeated START Condition Figure 23 Format of slave receiver mode Slave Transmitter Mode The first byte is received and handled as in the slave receiver mode However in this mode the direction bit will indicate that the transfer direction is reversed Serial data is transmitted via SDA while the serial clock is input through SCL START and STOP conditions are recognized as the beginning and end of a serial transfer In a given application lc may operate as a master and as a slave In the slave mode the 12C hardware looks for its own slave address and the general call address If one of these addresses is detected an interrupt is requested When the microcontroller wishes to become the bus master the hardware waits until the bus is free before the master mode is entered so that a possible slave action is not interrupted If bus arbitration is lost in the master mode IC switches to the slave mode immediately and can detect its own sla
199. on if the Status Code is SECTOR NOT BLANK Result1 Contents of non blank word location This command is used to blank check a sector or multiple sectors of on chip Flash memory To blank Description n check a single sector use the same Start and End sector numbers Read Part ID Status Code Table 163 IAP Read Part ID command description Command Read Part ID Command Code 54 Input parameters None Result Result Part Identification Number This command is used to read the part identification number Read Boot code version Table 164 IAP Read Boot Code version command description Command Read boot code version input Command code 55 p Parameters None Status Code CMD_SUCCESS ResultO 2 bytes of boot code version number It is to be interpreted as lt byte1 Major gt lt byte0 Minor gt This command is used to read the boot code version number Flash Memory System and Programming 197 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Compare Table 165 IAP Compare command description Command Compare Command Code 56 ParamO DST Starting Flash or RAM address from where data bytes are to be compared This address should be a word boundary Param1 SRC Starting Flash or RAM address from where data bytes are to be compared This address should be a word boundary Param2 Number of bytes to be compared Co
200. on vectored FIQ Interrupt Logic VICINT SOURCE i s Non vectored IRQ Interrupt Logic 31 0 r IRQ NonVectIRQ Rawlnterrupt IntSelect E gt 31 0 31 0 i Priority 0 Vector Interrupt 0 Interrupt Priority Logic VectIRQO Hardware Priority Do gt nVICIRQ Logic VectorAddr VectAddr0 31 0 Address Selectfor VectorCntl 5 0 31 0 Highest Priority Interrupt Vector Interrupt 1 Priority 1 VectIRQ1 VectAddr1 31 0 VICVECT VectorAddr j ADDROUT Priority 2 31 0 nd 81 0 Vector Interrupt 15 Priority 14 y _VectiRQIS Default VectAddr15 31 0 iro add w Priority 15 L nVICIRQIN VICVECTADDRIN 31 0 Figure 13 Block Diagram of the Vectored Interrupt Controller Vectored Interrupt Controller VIC 69 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 VIC USAGE NOTES If user s code is runing from the on chip RAM and an aplication uses interrupts interrupt vectors must be re mapped to flash address 0x0 This is necessary because all the exception vectors are located at addresses 0x0 and above This is easily achieved by configuring MEMMAP register located in System Control Block to User RAM mode Application code should be linked such that at 0x4000 0000 the Interrupt Vector Tabe IVT will reside
201. onding bit in PWMLER has been PWM Enable set followed by the occurrence of a PWM Match 0 event Note that the PWM Match register that determines the PWM rate PWM Match 0 must be set up prior to the PWM Timer Counter PWMTC 0xE0014008 The 32 bit PWM Timer Counter is incremented when the Prescale Counter reaches its terminal count Unless it is reset before reaching its upper limit the PWMTC will count up through the value OXFFFFFFFF and then wrap back to the value 0x00000000 This event does not cause an interrupt but a Match register can be used to detect an overflow if needed PWM Prescale Register PWMPR 0xE001400C The 32 bit PWM Prescale Register specifies the maximum value for the PWM Prescale Counter PWM Prescale Counter Register PWMPC 0xE0014010 The 32 bit PWM Prescale Counter controls division of pclk by some constant value before it is applied to the PWM Timer Counter This allows control of the relationship of the resolution of the timer versus the maximum time before the timer overflows The PWM Prescale Counter is incremented on every pclk When it reaches the value stored in the PWM Prescale Register the PWM Timer Counter is incremented and the PWM Prescale Counter is reset on the next pclk This causes the PWM TC to increment on every pclk when PWMPR 0 every 2 pclks when PWMPR 1 etc PWM Match Registers PWMMRO PWMMR6 ThePWM Match register values are continuously compared to the PWM Timer Counter value
202. pe which takes two parameters and returns void Note the IAP returns the result with the base address of the table residing in R1 typedef void IAP unsigned int unsigned int IAP iap entry Setting function pointer iap entry IAP IAP LOCATION Whenever you wish to call IAP you could use the following statement iap entry command result The IAP call could be simplified further by using the symbol definition file feature supported by ARM Linker in ADS ARM Developer Suite You could also call the IAP routine using assembly code The following symbol definitions can be used to link IAP routine and user application lt SYMDEFS gt ARM Linker ADS1 2 Build 826 Last Updated Wed May 08 16 12 23 2002 Ox7fffff90 T rm init entry Ox7fffffa0 A rm undef handler Flash Memory System and Programming 193 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Ox7fffffbO rm prefetchabort handler Ox7fffffcO rm dataabort handler Ox 7fffffd0 rm irghandler pop op P Ox 7fffffeO0 rm irqhandler2 Ox7ffffff0 T iap entry As per the ARM specification The ARM Thumb Procedure Call Standard SWS ESPC 0002 A 05 up to 4 parameters can be passed in the rO r1 r2 and r3 registers respectively Additional parameters are passed on the stack Up to 4 parameters can be returned in the rO r1 r2 and r3 registers respectively Additional parameters are returned indirectly
203. position within a cycle This allows for both positive going and negative going pulses Pulse period and width can be any number of timer counts This allows complete flexibility in the trade off between resolution and repetition rate All PWM outputs will occur at the same repetition rate Double edge controlled PWM outputs can be programmed to be either positive going or negative going pulses Match register updates are synchronized with pulse outputs to prevent generation of erroneous pulses Software must release new match values before they can become effective May be used as a standard timer if the PWM mode is not enabled A 32 bit Timer Counter with a programmable 32 bit Prescaler Four 32 bit capture channels take a snapshot of the timer value when an input signal transitions A capture event may also optionally generate an interrupt DESCRIPTION The PWM is based on the standard Timer block and inherits all of its features although only the PWM function is pinned out on the LPC2106 2105 2104 The Timer is designed to count cycles of the peripheral clock pclk and optionally generate interrupts or perform other actions when specified timer values occur based on seven match registers It also includes four capture inputs to save the timer value when an input signal transitions and optionally generate an interrupt when those events occur The PWM function is in addition to these features and is based on match register events
204. pped to Static RAM 11 Reserved Should not be used Warning Improper setting of this value may result in incorrect operation of the device Reserved user software should not write ones to reserved bits The value read from a 7 2 Reserved Pap A NA reserved bit is not defined The hardware reset value of the MAP bits is 00 for LPC2106 2105 2104 parts The apparent reset value that the user will see will be altered by the Boot Loader code which always runs initially at reset User documentation will reflect this difference System Control Block 42 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 PLL PHASE LOCKED LOOP The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz The input frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current Controlled Oscillator CCO The multiplier can be an integer value from 1 to 32 in practice the multiplier value cannot be higher than 6 on the LPC2106 2105 2104 due to the upper frequency limit of the CPU The CCO operates in the range of 156 MHz to 320 MHz so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency The output divider may be set to divide by 2 4 8 or 16 to produce the output clock Since the minimum output divider value is 2 it is insured that the PLL output has a 5096 duty cycle A block
205. ps Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 REGISTER DESCRIPTION The PWM function adds new registers and registers bits as shown in Table 115 below Table 115 Pulse Width Modulator Register Map Reset Address Value Description Access PWM Interrupt Register The IR can be written to clear interrupts The IR can be read to identify which of the possible interrupt sources are pending PWM Timer Control Register The TCR is used to control the Timer Counter E PWMICR functions The Timer Counter can be disabled or reset through the TCR PWM Timer Counter The 32 bit TC is incremented every PR 1 cycles of pclk 0xE0014008 PWMTC The TC is controlled through the TCR Fr 0xE001400C PWMPR PWM Prescale Register The TC is incremented every PR 1 cycles of pclk RAN 0xE0014000 R W PWM Prescale Counter The 32 bit PC is a counter which is incremented to the 0xE0014010 PWMPC value stored in PR When the value in PR is reached the TC is incremented 0xE0014014 PWMMCR PWM Match Control Register The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs PWM Match Register 0 MRO can be enabled through MCR to reset the TC stop both the TC and PC and or generate an interrupt when it matches the TC OXE 0014018 RY MMRO In addition a match between MRO and the TC sets all PWM outputs that are in single edge mode and sets PWM1 if it is in doubl
206. pt U11IR3 12011 is the highest priority interrupt and is set whenever any one of four error conditions occur on the UART1Rx input overrun error OE parity error PE framing error FE and break interrupt BI The UART1 Rx error condition that set the interrupt can be observed via U1LSR4 1 The interrupt is cleared upon an U1LSR read The UART1 RDA interrupt U11IR3 12010 shares the second level priority with the CTI interrupt U1IIR3 1 110 The RDA is activated when the UART1 Rx FIFO reaches the trigger level defined in U1FCR7 6 and is reset when the UART1 Rx FIFO depth falls below the trigger level When the RDA interrupt goes active the CPU can read a block of data defined by the trigger level The CTI interrupt U11IR3 12110 is a second level interrupt and is set when the UART1 Rx FIFO contains at least one character and no UART1 Rx FIFO activity has occurred in 3 5 to 4 5 character times Any UART1 Rx FIFO activity read or write of UART1 RSR will clear the interrupt This interrupt is intended to flush the UART1 RBR after a message has been received that is not a multiple of the trigger level size For example if a peripheral wished to send a 105 character message and the trigger level was 10 characters the CPU would receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5 CTI interrupts depending on the service routine resulting in the transfer of the remaining 5 characters UART 1 101 September 17 2003 Phil
207. pt Writing a zero has no effect Table 116 PWM Interrupt Register PWMIR 0xE001 4000 Function Description PWMMRO Interrupt Interrupt flag for PWM match channel 0 EUN Bm HESS REO E EC Pulse Width Modulator PWM 151 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 PWM Timer Control Register PWMTCR 0xE001 4004 The PWM Timer Control Register PWMTCR is used to control the operation of the PWM Timer Counter The function of each of the bits is shown in Table 117 Table 117 PWM Timer Control Register PWMTCR 0xE0014004 PWMTCR Function Description When one the PWM Timer Counter and PWM Prescale Counter are enabled for Counter Enable t counting When zero the counters are disabled When one the PWM Timer Counter and the PWM Prescale Counter are Counter Reset synchronously reset on the next positive edge of pclk The counters remain reset until TCR 1 is returned to zero Reserved user software should not write ones to reserved bits The value read from Reserved Ee NA a reserved bit is not defined PWM being enabled Otherwise a Match event will not occur to cause shadow register contents to become effective When one PWM mode is enabled PWM mode causes shadow registers to operate in connection with the Match registers A program write to a Match register will not have an effect on the Match result until the corresp
208. ption 2c nenea p a RR DERE A T O A GR REX RE EUER 203 Block Diagram sore me ad E pe eene 204 D bug Mode lt irren tee a a a UN OUR ANO TURR A 205 Embedded Trace Macrocell oo ooooconnoornn 207 gi cen 207 Applications eg m d uova wen penu uy er rd Ske 207 Description is seser te eroi Rd cho HERE AY MR ENDE E dort odi see 207 Pin Description s odo cee REG up ad eee ee EST Ones eee eate e eek A a 208 Register Description i i kerio Ra RE RR eR d Beebe dos CENE Hae URS 209 Block Diagram iive A Qu A IER RO EP EM 210 RealMonitor 22 it eo ie ive bl x e aei l4 vei xx 211 Features c T x hoses tees UT 211 Applications x eure eh RUP Ve A Eee eee Pace PALA 211 Descriptions anche ERA Rega ether eG Sadie bled BEA Se EAS EUER KE 211 How to Enable RealMonitor 0 0 215 RealMonitor build options 0 tnt III 221 5 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 6 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 List of Figures Figure 1 LPC2106 2105 2104 Block Diagram lesse eh 18 Figure 2 System Memory Map sssseeseeesee hmm mnn 29 Figure 3 Peripheral Memory Map sssee RH HH 30 Figure 4 AHB Peripheral Map si Ree m mH Rape RHODE CH Ro RC ep a 31 Figure 5 VPB Peripheral Map oooooccorrrrorn RR I 3 n 32 Figure 6 Map of lower memory i
209. ptional 7 Go to step 3 if more data is required to transmit Note that a read or write of the SPI data register is required in order to clear the SPIF status bit Therefore if the optional read of the SPI data register does not take place a write to this register is required in order to clear the SPIF status bit Slave Operation SPI Interface 125 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 The following sequence describes how one should process a data transfer with the SPI block when it is set up to be a slave This process assumes that any prior data transfer has already completed It is required that the system clock driving the SPI logic be at least 8X faster than the SPI 1 Set the SPI control register to the desired settings 2 Write the data to transmitted to the SPI data register optional Note that this can only be done when a slave SPI transfer is not in progress 3 Wait for the SPIF bit in the SPI status register to be set to 1 The SPIF bit will be set after the last sampling clock edge of the SPI data transfer 4 Read the SPI status register 5 Read the received data from the SPI data register optional 6 Go to step 2 if more data is required to transmit Note that a read or write of the SPI data register is required in order to clear the SPIF status bit Therefore at least one of the optional reads or writes of the SPI data register must take
210. quence of 1 then 0 on capture 0 will cause CRO to be loaded with falling edge the contents of TC When zero this feature is disabled Interrupt on capture 0 When one a CRO load due to a capture 0 event will generate an interrupt When event zero this feature is disabled Capture on capture 1 When one a sequence of 0 then 1 on capture 1 will cause CR1 to be loaded with rising edge the contents of the TC When zero this feature is disabled Capture on capture 1 When one a sequence of 1 then 0 on capture 1 will cause CR1 to be loaded with falling edge the contents of TC When zero this feature is disabled Interrupt on capture 1 When one a CR1 load due to a capture 1 event will generate an interrupt When event zero this feature is disabled 0 0 2 3 4 5 Capture on capture 2 When one a sequence of 0 then 1 on capture 2 will cause CR2 to be loaded with rising edge the contents of the TC When zero this feature is disabled Capture on capture 2 When one a sequence of 1 then 0 on capture 2 will cause CR2 to be loaded with falling edge the contents of TC When zero this feature is disabled Interrupt on capture 2 When one a CR2 load due to a capture 2 event will generate an interrupt When event zero this feature is disabled Capture on capture 3 Timer 1 only When one a sequence of 0 then 1 on capture 3 will cause CR3 rising edge to be loaded with the contents of TC When zero this feature is disabled Capture on
211. r LPC2106 2105 2104 2e A DATA A DATA A RS 22 A Data Transferred n Bytes Acknowledge A Acknowledge SDA low A Not Acknowledge SDA high S START condition P STOP Condition p a n s SLA Slave Address rom Slave to Master RS Repeat START condition Figure 21 A master receiver switch to master transmitter after sending repeated START Slave Receiver Mode In the slave receiver mode data bytes are received from a master transmitter To initialize the slave receiver mode user should write the Slave Address Register I2ADR and write the 12C Control Set Register IZCONSET as shown in Figure 22 I2CONSET Figure 22 Slave Mode Configuration I2EN must be set to 1 to enable the 12C function AA bit must be set to 1 to acknowledge its own slave address or the general call address The STA STO and SI bits are set to 0 After IZADR and I2CONSET are initialized the 12C interface waits until it is addressed by its own address or general address followed by the data direction bit If the direction bit is 1 R it enters slave transmitter mode After the address and direction bit have been received the SI bit is set and a valid status code can be read from the Status Register I2STAT Refer to Table 5 in 80C51 Family Derivatives 8XC552 562 Overview datasheet available on line at http www semiconductors philips c
212. r eh 198 Table 166 IAP Status Codes Summary 1 0 0 0 0c nn 198 Table 167 EmbeddedICE Pin Description liiilileleeeeeee RII 202 Table 168 EmbeddedICE Logic Registers llle es 203 Table 169 JTAG Pins Selection llis eere 206 Table 170 ETM Gorfiguratlon e RD exe eR ARR OUR UBRO ERE REX RE 207 Table 171 ETM Pin Description o oooooooorrorona eR IRR IIIA HI n 208 Table 172 ETM Registers te PREISE oh ERR vine Rea E Deets REM RR a aaa Sag eke Ei RH RU 209 Table 173 RealMonitor stack requirement 0 0 cee I 215 12 September 17 2003 Philips Semiconductors ARM based Microcontroller DOCUMENT REVISION HISTORY May 2003 Prototype LPC2106 2105 2104 User Manual created from the design specification July 2003 Flash Programming chapter added Memory Accelerator Module chapter added Register names in UARTs and timers updated List of all registers added in the Introduction chapter Pin Configuration chapter added August 2003 MAM VIC GPIO and RTC Usage Notes added EmbeddedICE chapter updated September 2003 e Details on JTAG ports added in the EmbeddedICE chapter Details on crystal oscillator added in the System Control Block chapter Preliminary User Manual LPC2106 2105 2104 List of possible baudrates when ISP is used added in the Flash Memory System and Programming chapter 13 September 17 2003 Philips Semiconductors Preli
213. r provides the transmit and 0xE0020008 SPDR receive data for the SPI Transmit data is provided to the SPI by writing to Read Write this register Data received by the SPI can be read from this register oxE002000c SPCCR SPI Clock Counter Register This register controls the frequency of a Read Write master s SCK 0xE002001C SPINT eee Flag This register contains the interrupt flag for the SPI Read Write Reset Value refers to the data stored in used bits only It does not include reserved bits content SPI Control Register SPCR 0xE0020000 The SPCR register controls the operation of the SPI as per the configuration bits setting Table 100 SPI Control Register SPCR 0xE0020000 SPCR Function Description eset Value Reserved user software should not write ones to reserved bits The value read from 2 0 Reserved NA a reserved bit is not defined Clock phase control determines the relationship between the data and the clock on SPI transfers and controls when a slave transfer is defined as starting and ending When 1 data is sampled on the second clock edge of the SCK A transfer starts with 3 CPHA the first clock edge and ends with the last sampling edge when the SSEL signal is active When 0 data is sampled on the first clock edge of SCK A transfer starts and ends with activation and deactivation of the SSEL signal Master mode select When 1 the SPI operates in Master mode When 0 the SPI 5 MSTR ope
214. ram EmbeddedICE Logic 204 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 DEBUG MODE Debug mode connects JTAG pins to embedded ICE for program debugging through the use of an emulator or other development tool Enabling Debug Mode Debug mode is enabled through the use of the DBGSEL and RTCK pins The two debug variations are selected with the aid of the RTCK pin and software configuration To enable the primary debug mode DBGSEL must be high during and after the CPU is reset For normal non debug operation DBGSEL must be kept low at all times see Figure 41 RST pin DBGSEL RTCK DBGSEL is tied or pulled low at all times An internal pulldown will cause DBGSEL to be low if it is not pulled high externally RTCK is not connected in the application and is pulled up internally Figure 41 Waveforms for normal operation not in debug mode For debugging with the primary JTAG pins RTCK must be high as the RST pin is released see Figure 42 RTCK may be driven high externally or allowed to float high via its on chip pullup The RTCK output driver is disabled until the internal wakeup time has expired allowing an interval between the release of the external reset and the release of the internal reset during which RTCK may be driven by an external signal if necessary This procedure establishes the P0 17 P0 21 pins as the JTAG Test Debug interface Pin co
215. rates in Slave mode LSB First controls which direction each byte is shifted when transferred When LSBF 1 SPI data is transferred LSB bit 0 first When 0 SPI data is transferred MSB bit 7 first 7 SPIE Serial peripheral interrupt enable When 1 a hardware interrupt is generated each time the SPIF or MODF bits are activated When 0 SPI interrupts are inhibited 4 CPOL Clock polarity control When 1 SCK is active low When 0 SCK is active high a m SPI Interface 128 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 SPI Status Register SPSR 0xE0020004 The SPSR register controls the operation of the SPI as per the configuration bits setting Table 101 SPI Status Register SPSR 0xE0020004 Function Description Reserved user software should not write ones to reserved bits The value read from SUED a reserved bit is not defined Slave abort When 1 this bit indicates that a slave abort has occurred This bit is cleared by reading this register Mode fault when 1 this bit indicates that a Mode fault error has occurred This bit is cleared by reading this register then writing the SPI control register Read overrun When 1 this bit indicates that a read overrun has occurred This bit is cleared by reading this register Write collision When 1 this bit indicates that a write collision has occurred This bit is cleared by reading this regist
216. rd Input boundary Number of Bytes Number of bytes to be written Count should be a multiple of 4 CMD_SUCCESS ADDR_ERROR Address not a word boundary Return Code ADDR_NOT_MAPPED COUNT_ERROR Byte count is not multiple of 4 PARAM_ERROR This command is used to download data to RAM The data should be in UU encoded format Example W 1073742336 4 lt CR gt lt LF gt writes 4 bytes of data to address 0x4000 0200 Read Memory lt address gt lt number of bytes gt The data stream is followed by the command success return code The check sum is sent after transmitting 20 UU encoded lines The length of any UU encoded line should not exceed 61 characters bytes i e it can hold 45 data bytes When the data fits in less then 20 UU encoded lines then the check sum is of actual number of bytes sent The host should compare it with the check sum of the received bytes If the check sum matches then the host should respond with OK lt CR gt lt LF gt to continue further transmission If the check sum does not match then the host should respond with RESEND lt CR gt lt LF gt In response the ISP command handler sends the data again Table 148 ISP Read Memory command description Command R Start Address Address from where data bytes are to be read This address should be a word Input boundary Number of Bytes Number of bytes to be read Count should be a multiple of 4 CMD SUCCESS followed by actual data UU encode
217. re command description Command M Input Return Code Address1 DST Starting Flash or RAM address from where data bytes are to be compared This address should be on word boundary Address2 SRO Starting Flash or RAM address from where data bytes are to be compared This address should be on word boundary Number of Bytes Number of bytes to be compared Count should be in multiple of 4 CMD SUCCESS Source and destination data is same COMPARE ERROR Followed by the offset of first mismatch COUNT ERROR Byte count is not multiple of 4 ADDR ERROR ADDR NOT MAPPED PARAM ERROR This command is used to compare the memory contents at two locations Example Flash Memory System and Programming M 8192 1073741824 4 lt CR gt lt LF gt compares 4 bytes from the RAM address 0x4000 0000 to the 4 bytes from the flash address 0x2000 Compare result may not be correct when source or destination address contains any of the first 64 bytes starting from address zero First 64 bytes are re mapped to flash boot sector 191 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Table 157 ISP Return Codes Summary Return P icis Mnemonic Description Command is executed successfully Sent by ISP CMD SUCCESS handler only when command given by the host has been completely and successfully executed 1 INVALID COMMAND Invalid command 2 SRC ADDR ERROR
218. re the ARM7TDMI core is stopped The CHAIN functionality requires two consecutive conditions to be satisfied before the core is halted An example of this would be to set the first breakpoint to trigger on an access to a peripheral and the second to trigger on the code segment that performs the task switching Therefore when the breakpoints trigger the information regarding which task has switched out will be ready for examination The watchpoints can be configured such that a range of addresses are enabled for the watchpoints to be active The RANGE function allows the breakpoints to be combined such that a breakpoint is to occur if an access occurs in the bottom 256 bytes of memory but not in the bottom 32 bytes The ARM7TDMI S core has a Debug Communication Channel function in built The debug communication channel allows a program running on the target to communicate with the host debugger or another separate host without stopping the program flow or even entering the debug state The debug communication channel is accessed as a co processor 14 by the program running on the ARM7TDMI S core The debug communication channel allows the JTAG port to be used for sending and receiving data without affecting the normal program flow The debug communication channel data and control registers are mapped in to addresses in the EmbeddedICE logic For more details refer to IEEE Standard 1149 1 1990 Standard Test Access Port and Boundary Scan Architecture
219. re the new clear operation on the same bit in VICSoftInt using writing into VICSoftIntClear is performed in the future VICSoftIntClear 0x0000 0000 must be assigned Therefore writing 1 to any bit in Clear register will have one time effect in the destination register If the watchdog is enabled for interrupt on underflow or invalid feed sequence only then there is no way of clearing the interrupt The only way you could perform return from interrupt is by disabling the interrupt at the VIC using VICIntEnClr Example Assuming that UART 0 and SPI are generating interrupt requests that are classified as vectored IRQs UARTO being on the higher level than SPI while UART1 and I C are generating non vectored IRQs the following could be one possibility for VIC setup VICIntSelect 0x0000 0000 SPI 12C UART1 and UARTO are IRQ gt bit10 bit9 bit7 and bit6 0 VICIntEnable 0x0000 06C0 SPI 12C UART1 and UARTO are enabled interrupts gt bit10 bit9 bit 7 and bit6 1 VICDefVectAddr 0x holds address at what routine for servicing non vectored IRQs i e UART1 and 12C starts VICVectAddr0 Ox holds address where UARTO IRQ service routine starts VICVectAddrl Ox holds address where SPI IRQ service routine starts VICVectCnt10 0x0000 0026 interrupt source with index 6 UARTO is enabled as the one with priority O the highest VICVectCnt11 0x0000 002A interrupt source with index 10 SPI is enabled as the one with pr
220. ress DST Destination Flash address where data bytes are to be written The destination rout address should be a 512 byte boundary P RAM Address SRO Source RAM address from where data bytes are to be read Number of Bytes Number of bytes to be written Should be 512 1024 4096 8192 CMD SUCCESS SRC ADDR ERROR Address not on word boundary DST ADDR ERROR Address not on correct boundary SRC ADDR NOT MAPPED Return Code DST_ADDR_NOT_MAPPED COUNT_ERROR Byte count is not 512 1024 4096 8192 SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION BUSY CMD_LOCKED PARAM_ERROR This command is used to program the flash memory The affected sectors should be prepared first by calling Prepare Sector for Write Operation command The affected sectors are automatically protected again once the copy command is successfully executed The boot sector can not be written by this command Description Example C 01073774592 512 lt CR gt lt LF gt copies 512 bytes from the RAM address 0x4000 8000 to the flash address 0 Flash Memory System and Programming 188 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Go lt address gt lt Mode gt Table 151 ISP Go command description Command G Address Flash or RAM address from which the code execution is to be started This address should Input be on a word boundary Mode T Execute program in Thumb
221. roller LPC2106 2105 2104 7 PIN CONNECT BLOCK FEATURES Allows individual pin configuration APPLICATIONS The purpose of the Pin Connect Block is to configure the microcontroller pins to the desired functions DESCRIPTION The pin connect block allows selected pins of the microcontroller to have more than one function Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals Peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt s being enabled Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined REGISTER DESCRIPTION The Pin Control Module contains 2 registers as shown in Table 47 below Table 47 Pin Connect Block Register Map Address Name Description Access 0xE002C000 PINSELO Pin function select register 0 Read Write 0xE002C004 PINSEL1 Pin function select register 1 Read Write Pin Connect Block 77 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Pin Function Select Register 0 PINSELO 0xE002C000 The PINSELO register controls the functions of the pins as per the settings listed in Table 50 The direction control bit in the IODIR register is effective only when the GPIO function is selected for a pin For other functions direction is controlled automatically Table 4
222. rotocol commands to the JTAG data needed to access the ARM7TDMI S core present on the target system DESCRIPTION The ARM7TDMI S Debug Architecture uses the existing JTAG port as a method of accessing the core The scan chains that are around the core for production test are reused in the debug state to capture information from the databus and to insert new information into the core or the memory There are two JTAG style scan chains within the ARM7TDMI S A JTAG style Test Access Port Controller controls the scan chains In addition to the scan chains the debug architecture uses EmbeddedICE logic which resides on chip with the ARM7TDMI S core The EmbeddedICE has its own scan chain that is used to insert watchpoints and breakpoints for the ARM7TDMI S core The EmbeddedICE logic consists of two real time watchpoint registers together with a control and status register One or both of the watchpoint registers can be programmed to halt the ARM7TDMI S core Execution is halted when a match occurs between the values programmed into the EmbeddedICE logic and the values currently appearing on the address bus databus and some control signals Any bit can be masked so that its value does not affect the comparison Either watchpoint register can be configured as a watchpoint i e on a data access or a break point i e on an instruction fetch The watchpoints and breakpoints can be combined such that The conditions on both watchpoints must be satisfied befo
223. routine can read another VIC register to see what IRQs are active All registers in the VIC are word registers Byte and halfword reads and write are not supported Additional information on the Vectored Interrupt Controller is available in the ARM PrimeCell Vectored Interrupt Controller PL190 documentation Vectored Interrupt Controller VIC 61 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 REGISTER DESCRIPTION The VIC implements the registers shown in Table 30 More detailed descriptions follow Table 30 VIC Register Map E Reset Address Name Description Access Value OxFFFF F000 VICIRQStatus IRQ Status Register This register reads out the state of those interrupt RO 0 requests that are enabled and classified as IRQ FIQ Status Requests This register reads out the state of those interrupt OXRERE FOUE MEA ls requests that are enabled and classified as FIQ Raw Interrupt Status Register This register reads out the state of the 32 OxFFFF F008 VICRawintr interrupt requests software interrupts regardless of enabling or classification OxFFFF F00C ViCIntSelect Interrupt Select Register This register classifies each of the 32 interrupt R W requests as contributing to FIQ or IRQ Interrupt Enable Register This register controls which of the 32 interrupt OxFFFF F010 VICIntEnable requests and software interrupts are enabled to contribute to FIQ or R W
224. rrupts or perform other actions at specified timer values based on four match registers It also includes four capture inputs to trap the timer value when an input signal transitions optionally generating an interrupt Due to the limited number of pins on the LPC2106 2105 2104 only three of the Capture inputs and Match outputs of Timer 0 are connected to device pins PIN DESCRIPTION Table 105 gives a brief summary of each of the Timer related pins Table 105 Pin summary Pin name Pin direction Pin Description CAPO 2 0 CAP1 3 0 Capture Signals A transition on a capture pin can be configured to load one of the input Capture Registers with the value in the Timer Counter and optionally generate an interrupt External Match Output 0 1 When match register 0 1 MRO 1 equals the timer counter Output TC this output can either toggle go low go high or do nothing The External Match Register EMR controls the functionality of this output Vs Output External Match Output 1 See the MATO MAT1 description above MATO 2 MAT1 2 Output External Match Output 2 See the MATO MAT1 description above MAT1 3 Output External Match Output 3 See the MAT1 description above Timer 0 and Timer 1 134 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 REGISTER DESCRIPTION Each Timer contains the registers shown in Table 106 More detailed descriptions follow Table
225. rs and the THRE is the highest interrupt UOIIR3 1 001 UART 0 89 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 UARTO FIFO Control Register UOFCR 0xE000C008 The UOFCR controls the operation of the UARTO Rx and Tx FIFOs Table 66 UARTO FIFO Control Register Bit Descriptions UOFCR 0xE000C008 clear the UARTO FIFOs Rx FIFO Reset Writing a logic 1 to UOFCR1 will clear all bytes in UARTO Rx FIFO and reset the pointer logic This bit is self clearing Tx FIFO Reset Writing a logic 1 to UOFCR2 will clear all bytes in UARTO Tx FIFO and reset the pointer logic This bit is self clearing Reserved user software should not write ones to reserved bits The value read from a Reserved NE i NA reserved bit is not defined 00 trigger level O default h1 01 trigger level 1 default n4 10 trigger level 2 default h8 p Es 11 trigger level 3 default he These two bits determine how many receiver UARTO FIFO characters must be written UOFCR Function Description Active high enable for both UARTO Rx and Tx FIFOs and UOFCR7 1 access This bit FIFO Enable must be set for proper UARTO opearation Any transition on this bit will automatically 0 1 2 5 8 7 6 before an interrupt is activated The four trigger levels are defined by the user at compilation allowing the user to tune the trigger levels to the FIFO depths chosen UART 0 90 September
226. rt Sector Number p End Sector Number Should be greater than or equal to start sector number CMD_SUCCESS SECTOR_NOT_BLANK followed by lt Offset of the first non blank word location gt lt Contents of non Return Code blank word location gt INVALID_SECTOR PARAM_ERROR es This command is used to blank check a sector or multiple sectors of on chip Flash memory To blank Description n check a single sector use the same Start and End sector numbers 2 3 lt CR gt lt LF gt blank checks the flash sectors 2 and 3 Blank check on sector 0 always fails as first 64 bytes are re mapped to flash boot sector Read Part ID Table 154 ISP Read Part ID command description Command J Input None Return Code CMD SUCCESS followed by part identification number in ASCII format This command is used to read the part identification number Read Boot code version Table 155 ISP Read Boot Code version command description Command K Input None CMD SUCCESS followed by 2 bytes of boot code version number in ASCII format It is to be Return Code d f f interpreted as lt byte1 Major gt lt byte0 Minor gt This command is used to read the boot code version number Flash Memory System and Programming 190 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Compare lt address1 gt lt address2 gt number of bytes gt Table 156 ISP Compa
227. ruction Latches and 12 bit Comparison Address Latches associated with each Flash Bank One of the two sets called the Branch Trail Buffer holds the data and comparison address for that bank from the last Instruction miss The other set called the Prefetch Buffer holds the data and comparison address from prefetches undertaken speculatively by the MAM Each Instruction Latch holds 4 words of code 4 ARM instructions or 8 Thumb instructions Similarly there is a 128 bit Data Latch and 13 bit Data Address latch that are used during Data cycles This single set of latches is shared by both Flash banks Each Data access that is not in the Data latch causes a Flash fetch of 4 words of data which are captured in the Data latch This speeds up sequential Data operations but has little or no effect on random accesses Flash Programming Issues Since the Flash memory does not allow accesses during programming and erase operations it is necessary for the MAM to force the CPU to wait if a memory access to a Flash address is requested while the Flash module is busy This is accomplished by asserting the ARM7TDMI S local bus signal CLKEN Under some conditions this delay could result in a Watchdog time out The user will need to be aware of this possibility and take steps to insure that an unwanted Watchdog reset does not cause a system failure while programming or erasing the Flash memory Memory Accelerator Module MAM 56 September 17 2003 Philips S
228. s 0xE0024014 CTIMEO Time Register O 6 bit Minutes 6 bit 6bitSeconds Gea ee 0xE0024018 CTIME1 Time Consolidated 0xE002401C CTIME2 Time reserved 20 bits 12 bit Day of Year Register 2 Register oxE0024024 6 bit data AN Register ge lod Reais EXER nes LAB Register sad Register NES ipid LEAN Register acids Register Errata ae LER Register 0xE0024034 DOY Dayot vear reserved 7 bits 9 bit data Register Register 0xE002403C YEAR Year Year Register reserved 4 bits 12 t2bitdata data ELI AL ELI value OxE0024064 Alarm value 6 bit data R W i for Minutes AL Alarm value AL Alarm value OxE002406C for Day of 5 bit data R W DOM Month AL Alarm value 0xE0024070 for Day of 3 bit data R W j DOW Week Introduction 26 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Table 1 LPC2106 2105 2104 Registers Address s Reset Offset Name Description LSB Access Value AL Alarm value 0xE0024074 DOY for Day of reserved 7 bits 9 bit data R W A Year Alarm value Alarm value reserved 0xE002407C DES for Veer ED 12 SN data PRE E TeScag reserved 0xE0024080 value integer 13 bit data R W INT 3 bits portion Prescale PRE value 0xE0024084 FRAC fractional 15 bit data R W portion oxE0028000 1oPIN GPIO Pin 32 bit data ro NA value register GPIO 0 0xE0028004 IOSET Output set 32 bi
229. s The value read from Rpacived a reserved bit is not defined Read back for the PLL Enable bit When one the PLL is currently activated When zero the PLL is turned off This bit is automatically cleared when Power Down mode is activated Read back for the PLL Connect bit When PLLC and PLLE are both one the PLL is connected as the clock source for the LPC2106 2105 2104 When zero the PLL is bypassed and the oscillator clock is used directly by the LPC2106 2105 2104 This bit is automatically cleared when Power Down mode is activated Reflects the PLL Lock status When zero the PLL is not locked When one the PLL PLOCK is locked onto the requested frequency Reserved user software should not write ones to reserved bits The value read from PAL a reserved bit is not defined PLL Interrupt The PLOCK bit in the PLLSTAT register is connected to the interrupt controller This allows for software to turn on the PLL and continue with other functions without having to wait for the PLL to achieve lock When the interrupt occurs PLOCK 1 the PLL may be connected and the interrupt disabled PLL Modes The combinations of PLLE and PLLC are shown in Table 16 Table 16 PLL Control Bit Combinations PLLC PLLE PLL Function 0 0 PLL is turned off and disconnected The system runs from the unmodified clock input 1 MEAN The PLL is active but not yet connected The PLL can be connected after PLOCK is asserted NANA Same
230. s UOIIR OXEO00CO008 Read Only 88 Table 65 UARTO Interrupt Handling 0oo ooooooocrcco III II 89 Table 66 UARTO FIFO Control Register Bit Descriptions UOFCR OxE000C008 o 90 Table 67 UARTO Line Control Register Bit Descriptions UOLCR OxXEOOOCOOC 91 Table 68 UARTO Line Status Register Bit Descriptions UOLSR OxE000C014 Read Only 92 Table 69 UARTO Scratchpad Register UOSCR OXE000C01C o oooccoccoco eee 93 Table 70 UART1 Pin Description ssieeseeesese ee IR RR e IIR hh 97 Table 71 UART 1 Register Map sieelseeeee e II Ier 98 Table 72 UART1 Receiver Buffer Register U1RBR OxE0010000 when DLAB 0 Read Only 99 Table 73 UART1 Transmit Holding Register U1THR 0xE0010000 when DLAB 0 Write Only 99 Table 74 UART1 Divisor Latch LSB Register U1DLL 0xE0010000 when DLAB 1 99 Table 75 UART1 Divisor Latch MSB Register U1DLM 0xE0010004 when DLAB 1 100 Table 76 UART1 Interrupt Enable Register Bit Descriptions U1IER 0xE0010004 when DLAB 0 100 Table 77 UART1 Interrupt Identification Register Bit Descriptions IIR OXE0010008 Read Only 101 Table 78 UART1 Interrupt Handling 0 eee III 102 Table 79 UART1 FCR Bit Descriptions U1FCR OxE0010008 0 0 eee eee 103 Table 80 UART1 Line Control Register Bit Descriptions U1LCR OxE001000C 104 Tab
231. s may be lost upon reset Flash programming commands use the top 32 bytes of on chip RAM The stack is located at RAM top 32 The maximum stack usage is 256 bytes and it grows downwards RAM used by IAP command handler Flash programming commands use top 32 bytes of on chip RAM The maximum stack usage in the user allocated stack space is 128 bytes and it grows downwards Flash Memory System and Programming 180 September 17 2003 Preliminary User Manual LPC2106 2105 2104 Philips Semiconductors ARM based Microcontroller RAM used by RealMonitor The RealMonitor uses on chip RAM from 0x4000 0040 to 0x4000 011F The user could use this area if RealMonitor based debug is not required The Flash boot loader does not initialize the stack for the RealMonitor Flash Memory System and Programming 181 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 BOOT PROCESS FLOWCHART Initialize WatchDog Flag Set User Code Valid P0 14 LOW Execute User code Run Auto Baud Auto Baud Successful Receive crystal frequency Run ISP Command Handler Figure 38 Boot Process flowchart Flash Memory System and Programming 182 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 SECTOR NUMBERS Some IAP and ISP commands operate on sectors and specify sector numbers The following table indicates
232. s prior to the falling edge and negative going PWM pulses when the falling edge occurs prior to the rising edge Figure 31 shows the block diagram of the PWM The portions that have been added to the standard timer block are on the right hand side and at the top of the diagram Pulse Width Modulator PWM 144 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Match Register O Shadow Register 0 Load Enable Match Register 1 Shadow Register 1 Load Enable Match Register 2 Shadow Register 2 Load Enable Match Register 3 Shadow Register 3 Load Enable Match Register 4 Shadow Register 4 Load Enable Match Register 5 Shadow Register 5 Load Enable Match Register 6 Shadow Register 6 Load Enable Match O Latch Enable Register Clea Match 0 M S a gt PWM1 Match Control Register Match 1 PWMENA1 E PWMSEL2 a PWM2 Interrupt Register RE PWMENA2 PWMSEL3 Control PWM3 M 6 0 PWMENA3 Interrupt PWMSEL4 Stop on Match S Reset on Match a PWM4 E PWMENA4 gt R PWMSEL5 mux HS Lus QU PWM5 E PWMENAS5 R PWMSEL6 PWM6 Match 6 PWMENAG Prescale Counter PWMENA1 6 PWMSEL2 6 ENABLE MAXVAL Timer Control Register Prescale Register PWM Control Register Note this diagram is inten
233. s register reads out the state of those interrupt requests that are enabled and classified as FIQ If more than one request is classified as FIQ the FIQ service routine can read this register to see which request s is are active Table 38 IRQ Status Register VICFIQStatus OXFFFFF004 Read Only VICFIGStatus Function Reset Value 31 0 1 the interrupt request with this bit number is enabled classified as FIQ and asserted 0 Vector Control Registers 0 15 VICVectCntl0 15 OXFFFFF200 23C Read Write Each of these registers controls one of the 16 vectored IRQ slots Slot O has the highest priority and slot 15 the lowest Note that disabling a vectored IRQ slot in one of the VICVectCntl registers does not disable the interrupt itself the interrupt is simply changed to the non vectored form Table 39 Vector Control Registers VICVectCntl0 15 OXFFFFF200 23C Read Write VICVectCntl0 15 Function Reset Value 1 this vectored IRQ slot is enabled and can produce a unique ISR address when its assigned interrupt request or software interrupt is enabled classified as IRQ and asserted 1 5 The number of the interrupt request or software interrupt assigned to this vectored IRQ slot As a matter of good programming practice software should not assign the same interrupt number to more than one enabled vectored IRQ slot But if this does occur the lower numbered slot will be used when the interrupt request or software interrupt
234. s showing re mapped and re mappable areas 35 Figure 7 Oscillator modes and models a slave mode of operation b oscillation mode of operation C external crystal model used for CX1 X2 evaluation 0 0c eee eens 39 Figure 8 External Interrupt Logic 0 0 cee RR RR m hne 41 Figure 9 PLL Block Diagram ueri m A Re ERES pb e ex 44 Figure 10 Reset Block Diagram including Wakeup Timer 0 0 00 ce eee eee e 51 Figure 11 VPB Divider Connections ssslsleseeseee eR n 53 Figure 12 Simplified Block Diagram of the Memory Accelerator Module oo oocococooo o 56 Figure 13 Block Diagram of the Vectored Interrupt Controller llle 69 Figure 14 LPC2106 2105 2104 48 pin package LQFP48 0 000 000 0020 e eee 71 Figure 15 UARTO Block Diagram s s IRR HI 33 95 Figure 16 VARTI Block DiagraM o0ooooooorernrenr IR I e n 110 Figure 17 12C Bus Configuration lslseleleeee ee mmm 112 Figure 18 Slave Mode Configuration 0 0 cece e 112 Figure 19 Format in the master transmitter mode lie ee 113 Figure 20 Format of master receiver mode 113 Figure 21 A master receiver switch to master transmitter after sending repeated START 114 Figure 22 Slave Mode Configuration ooooooccccccocec teen eens 114 Figure 23 Format of slave receiver MOde o ooocoocooc tae 115 Figure 24 Format of slave transmitt
235. scription Pw o Capture Control Register The CCR controls which edges of the a 0xE0008028 capture inputs are used to load the Capture Registers and whether R W or not an interrupt is generated when a capture takes place CRO 0xE000402C OxE000802C Capture Register 0 CRO is loaded with the value of TC when there TOCRO T1CRO is an event on the capture 0 signal eh 30 ta Sn Capture Register 1 See CRO description ES 21 ORO 24 Capture Register 2 See CRO description EE MAU Gb Capture Register 3 See CRO description Not usable on Timer 0 mo o 0xE000403C 0xE000803C External Match Register The EMR controls the external match R W TOEMR T1EMR pins MATn Reset Value refers to the data stored in used bits only It does not include reserved bits content Timer O and Timer 1 135 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Interrupt Register IR Timer 0 TOIR 0xE0004000 Timer 1 T1IR OxE0008000 The Interrupt Register consists of four bits for the match interrupts and four bits three for Timer 0 for the capture interrupts If an interrupt is generated then the corresponding bit in the IR will be high Otherwise the bit will be low Writing a logic one to the corresponding IR bit will reset the interrupt Writing a zero has no effect Table 107 Interrupt Register IR Timer 0 TOIR 0xE0004000 Timer 1 T1IR 0xE0008000 Reset Function
236. sed Microcontroller LPC2106 2105 2104 UARTO Scratch Pad Register UOSCR 0xE000C01C The UOSCR has no effect on the UARTO operation This register can be written and or read at user s discretion There is no provision in the interrupt interface that would indicate to the host that a read or write of the UOSCR has occurred Table 69 UARTO Scratchpad Register UOSCR 0xE000C01C Function Description A readable writable byte UART 0 93 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 ARCHITECTURE The architecture of the UARTO is shown below in the block diagram The VPB interface provides a communications link between the CPU or host and the UARTO The UARTO receiver block UORx monitors the serial input line RxDO for valid input The UARTO Rx Shift Register UORSR accepts valid characters via RxDO After a valid character is assembled in the UORSR it is passed to the UARTO Rx Buffer Register FIFO to await access by the CPU or host via the generic host interface The UARTO transmitter block UOTx accepts data written by the CPU or host and buffers the data in the UARTO Tx Holding Register FIFO UOTHR The UARTO Tx Shift Register UOTSR reads the data stored in the UOTHR and assembles the data to transmit via the serial output pin TxDO The UARTO Baud Rate Generator block UOBRG generates the timing enables used by the UARTO Tx block The UOBRG clock inp
237. sh memory initialization is complete the processor is released to execute instructions if the external Reset has been de asserted In the case where an external clock source is used in the system as opposed to a crystal connected to the oscillator pins the possibility that there could be little or no delay for oscillator start up must be considered The Wakeup Timer design then ensures that any other required chip functions will be operational prior to the beginning of program execution The LPC2106 2105 2104 does not contain any analog function such as comparators that operate without clocks or any independent clock source such as a dedicated Watchdog oscillator The only remaining functions that can operate in the absence of a clock source are the external interrupts EINTO EINT1 and EINT2 If the external interrupt is enabled to cause wakeup and becomes active is driven low externally an oscillator wakeup must be initiated If the interrupt is also enabled in the Vectored Interrupt Controller the completion of interrupt processing is postponed until the wakeup timer expires To summarize on the LPC2106 2105 2104 the Wakeup Timer enforces a minimum reset duration based on the crystal oscillator and is activated whenever there is a wakeup from Power Down mode or any type of Reset System Control Block 54 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 4 MEMORY ACCELERATOR MO
238. ss OXE000C000 Details of such address aliasing within a peripheral space are not defined in the LPC2106 2105 2104 documentation and are not a supported feature Note that the ARM core stores the Prefetch Abort flag along with the associated instruction which will be meaningless in the pipeline and processes the abort only if an attempt is made to execute the instruction fetched from the illegal address This prevents accidental aborts that could be caused by prefetches that occur when code is executed very near a memory boundary LPC2106 2105 2104 Memory Addressing 36 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 3 SYSTEM CONTROL BLOCK SUMMARY OF SYSTEM CONTROL BLOCK FUNCTIONS The System Control Block includes several system features and control registers for a number of functions that are not related to specific peripheral devices These include Crystal Oscillator External Interrupt Inputs Memory Mapping Control PLL Power Control Reset VPB Divider Wakeup Timer Each type of function has its own register s if any are required and unneeded bits are defined as reserved in order to allow future expansion Unrelated functions never share the same register addresses PIN DESCRIPTION Table 4 shows pins that are associated with System Control block functions Table 4 Pin summary Pin name Pin direction Pin Description X1 Input Crystal Os
239. t data register GPIO 0 0xE0028008 Direction 32 bit data control register GPIO 0 0xE002800C IOCLR Output clear 32 bit data register Pin Connet Block PIN Pin function 0xE002C000 select 32 bit data R W SELO i register O PIN Pin function 0xE002C004 select 32 bit data R W SEL1 a register 1 System Control Block oxE01Fco00 MAM MAM control 2 bit data R W CR register oxEo1FCoo4 MAM MAM timing 3 bit data RW 0x07 TIM control Introduction 27 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Table 1 LPC2106 2105 2104 Registers Address vos Reset Offset Description LSB Access Value Memory 0xE01FC040 mapping 2 bit data control PLL PLL control PLL PLL 0xE01FC084 CFG configuration 2bit data PSEL 5 bit data MSEL R W register PLL status mme eer o register 2bit data PSEL 5 bit data MSEL PLL PLL feed OxEO1FCO8C FEED register 8 bit data register Power control reserved 22 bits ES ES OxEO1FCOCA PCONP for R W Ox3BE peripherals PC PC PC PC PC ec PWMO URT1 URTO TIM1 TIMO oxEo1FC100 VPB VPB divider ES DIV control EXT External OxEOTFC140 yr interrupt flag EINT2 EINT1 EINTO R W register Ei e EXT EXT EXT OxEO1FC144 Lu WAKE WAKE WAKE R W WAKE wakeup 2 4 0 register Introduction 28 September 17 2003 Philips Semiconductors ARM based Microcontroller Preliminary User Manual
240. tem Control Block Functions ooooooooocococco ees 37 Pin Description i5 c ee A A da A Io ERE E 37 Register Description d eod o de E EIER e t E eh m ets A ot 38 Grystal Oscillator i a ai azote trad deed dede pulos 39 External Interrupt Inputs ra o a e RR IR RR t 40 Memory Mapping Control l lilslissseeee ee Rm un 42 PLE Phase Locked Loop iria Ran RE RUE DRE RERO E EIU EE 43 Power Gontlrol 5 zs ep imis eA eee arid imer Ec iere 49 A 51 VPB DiVide soso arar TO Be eee wi ha ree 52 Wakeup Timer 20 iia di eee ii a eed Pg 54 Memory Accelerator Module MAM 00 2c eee eee eee eee eee eee 55 Introduction 4 dtu LII ER be ota we Oe iG garg A TRAE RES 55 Memory Accelerator Module Operating Modes 00 e cece eee teen eee eee 57 MAM Configuration iets geet expe E aial ae a A D GU UE a ee eines 58 Register Description iieiaei p deni ee e ne e me hh 58 MAM Usage Notes ssc edd cia hee UR eel aa Jee aaa O Alanis eee ee RE 59 Vectored Interrupt Controller VIC 200 c eee eee eee 61 Features oi A EDEN ee eo mA em e ety Aa ee 61 Description Pas eu ets Beg E Rua VD Ee EXERCERE A wit at 61 Register Description 0 0 a a a mm rm 62 VIG Registersx S30 osteitis ON 64 Interrupt Sources ss voc Lm NON St Aes NV 68 VIG Usage Notes cues a deed ees bua re eb ee cma e eet 70 Pin Configuration fae eh A ete a a uar xm Rn ers 71 NetGhip PInoUt cct bt nettle Ait a A A D 71 L
241. the description of the PWM Match Control Register PWMMCR Enable PWM Match 5 Latch Writing a one to this bit allows the last value written to the PWM Match 6 register to be become effective when the timer is next reset by a PWM Match event See the description of the PWM Match Control Register PWMMCR Reserved Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined Pulse Width Modulator PWM 155 September 17 2003 Enable PWM Match 6 Latch Enable PWM Writing a one to this bit allows the last value written to the PWM Match 4 register to be E 7 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Pulse Width Modulator PWM 156 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 15 REAL TIME CLOCK FEATURES Measures the passage of time to maintain a calendar and clock Ultra Low Power design to support battery powered systems Provides Seconds Minutes Hours Day of Month Month Year Day of Week and Day of Year Programmable Reference Clock Divider allows adjustment of the RTC to match various crystal frequencies DESCRIPTION The Real Time Clock RTC is designed to provide a set of counters to measure time during system power on and off operation The RTC has been designed to use little power making it suitable for battery powered systems wher
242. the location of the interrupt vectors on the ARM7 processor at addresses 0x0000 0000 through 0x0000 001C as shown in Table 2 below a small portion of the Boot Block and SRAM spaces need to be re mapped in order to allow alternative uses of interrupts in the different operating modes described in Table 3 Re mapping of the interrupts is accomplished via the Memory Mapping Control feature described in the System Control Block section Table 2 ARM Exception Vector Locations Address Exception 0x0000 0000 Reset 0x0000 0004 Undefined Instruction 0x0000 0008 Software Interrupt 0x0000 000C Prefetch Abort instruction fetch memory fault Data Abort data access memory fault wwwws m Identified as reserved in ARM documentation this location is used by the Boot Loader as the Valid User Program key Table 3 LPC2106 2105 2104 Memory Mapping Modes Mode Activation Usage The Boot Loader always executes after any reset The Boot Block interrupt vectors are mapped to the bottom of memory to allow handling exceptions and using interrupts during the Boot Loading process Boot Loader Hardware activation mode by any Reset Activated by Boot Loader when a valid User Program Signature is recognized in memory and Boot Loader operation is not forced Interrupt vectors are not re mapped and are found in the bottom of the Flash memory User RAM Software activation Activated by a User Program as desired Interrupt vectors are re
243. they are configured as GPIO in an OUTPUT mode Writing 1 produces a LOW level at the corresponding port pins and clears the corresponding bits in the IOSET register Writing O has no effect If any pin is configured as an input or a secondary function writing to IOCLR has no effect Table 55 GPIO Output Clear Register IOCLR 0xE002800C Value after Reset Output value CLEAR bits Bit 0 corresponds to P0 0 Bit 31 corresponds to P0 31 0 Description GPIO Direction Register IODIR 0xE0028008 This register is used to control the direction of the pins when they are configured as GPIO port pins Direction bit for any pin must be set according to the pin functionality Table 56 GPIO Direction Register IODIR 0xE0028008 Value after Description Reset Direction control bits 0 INPUT 1 OUTPUT Bit O controls PO 0 Bit 31 controls P0 31 0 GPIO 82 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 GPIO USAGE NOTES If for the specified output pin corresponding bit is set both in GPIO Output Set Register IOSET and in GPIO Output Clear Register IOCLR observed pin will output level determined by the later write access of IOSET nad IOCLR This means that in case of sequence IOSET 0x0000 0080 IOCLR 0x0000 0080 pin PO 7 will have low output since access to Clear register came after access to Set register GPIO 83 September 17
244. tion 0 No change detected on modem input CTS Delta CTS 1 State change detected on modem input CTS Set upon state change of input CTS Cleared on an U1MSR read 0 No change detected on modem input DSR Delta DSR 1 State change detected on modem input DSR Set upon state change of input DSR Cleared on an U1MSR read 0 No change detected on modem input RI Trailing Edge RI 1 Low to high transition detected on RI Set upon low to high transition of input RI Cleared on an U1MSR read Clear To Send State Complement of input signal CTS This bit is connected to U1MCR 1 in modem loopback mode Data Set Ready State Complement of input signal DSR This bit is connected to U1MCR 0 in modem loopback mode Ring Indicator State Complement of input RI This bit is connected to U1 MCR 2 in modem loopback mode Data Carrier Detect State Complement of input DCD This bit is connected to U1MCR S3 in modem loopback mode 0 No change detected on modem input DCD Delta DCD 1 State change detected on modem input DCD Set upon state change of input DCD Cleared on an U1MSR read CTS DSR DCD UART 1 107 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 UART1 Scratch Pad Register U1SCR 0xE001001C The U1SCR has no effect on the UART1 operation This register can be written and or read at user s discretion There is no provision in the interrupt interfa
245. ule data paths In the following descriptions the term fetch applies to an explicit Flash read request from the ARM prefetch is used to denote a Flash read of instructions beyond the current processor fetch address Flash Memory Banks There are two banks of Flash memory in order to allow two parallel accesses and eliminate delays for sequential accesses Memory Accelerator Module MAM 55 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Flash programming operations are not controlled by the Memory Accelerator Module but are handled as a separate function A boot block sector contains Flash programming algorithms that may be called as part of the application program and a loader that may be run to allow serial programming of the Flash memory The Flash memories are wired so that each sector exists in both banks such that a sector erase operation acts on part of both banks simultaneously In effect the existence of two banks is transparent to the programming functions Memory Address Flash Memory Flash Memory Bus Bank 0 Bank 1 Interface ARM Local Bus Bank Selection Memory Data Figure 12 Simplified Block Diagram of the Memory Accelerator Module Instruction Latches and Data Latches Code and Data accesses are treated separately by the Memory Accelerator Module There are two sets of 128 bit Inst
246. unt should be in multiple of 4 CMD SUCCESS COMPARE ERROR Status Code COUNT ERROR Byte count is not multiple of 4 ADDR ERROR ADDR NOT MAPPED Result0 Offset of the first mismatch if the Status Code is COMPARE ERROR This command is used to compare the memory contents at two locations Compare result may not Description be correct when source or destination address contains any of the first 64 bytes starting from address zero First 64 bytes can be re mapped to RAM Table 166 IAP Status Codes Summary Status Code Mnemonic Description CMD SUCCESS Command is executed successfully 1 INVALID COMMAND Invalid command 2 SRC ADDR ERROR Source address is not on a word boundary 3 DST ADDR ERROR Destination address is not on a correct boundary Source address is not mapped in the memory map SRC ADDR NOT MAPPED Count value is taken in to consideration where applicable Destination address is not mapped in the memory DST ADDR NOT MAPPED map Count value is taken in to consideration where applicable COUNT ERROR m is not multiple of 4 or is not a permitted INVALID SECTOR Sector number is invalid SECTOR NOT BLANK Sector is not blank SECTOR NOT PREPARED FOR WRITE OPERATION ee prepareisector for operen COMPARE_ERROR Source and destination data is not same BUSY Flash programming hardware interface is busy 0 S RON Z BE ES A 7 10 11 Flash Memory System and Programming 198 September
247. ut 4 PWMSEL4 When zero selects single edge controlled mode for PWM4 When one selects double edge controlled mode for the PWM4 output 5 PWMSEL5 When zero selects single edge controlled mode for PWM5 When one selects double edge controlled mode for the PWMS output PWMSEL6 When zero selects single edge controlled mode for PWM6 When one selects double edge controlled mode for the PWM6 output 1 0 Reserved N A Reserved user software should not write ones to reserved bits The value read from 8 7 Reserved A a reserved bit is not defined PWMENA1 When one enables the PWM1 output When zero disables the PWM1 output 10 PWMENA2 When one enables the PWM2 output When zero disables the PWM 2 output 11 PWMENA3 When one enables the PWM3 output When zero disables the PWM3 output 12 PWMENA4 When one enables the PWM4 output When zero disables the PWM4 output 13 PWMENA5 When one enables the PWM5 output When zero disables the PWM5 output 14 PWMENA6 When one enables the PWM6 output When zero disables the PWM6 output 15 Reserved Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined N N A Pulse Width Modulator PWM 154 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 PWM Latch Enable Register PWMLER 0xE0014050 ThePWM Latch Enable Register is used to control the update of the PWM Mat
248. ut source is the VPB clock pclk The main clock is divided down per the divisor specified in the UODLL and UODLM registers This divided down clock is a 16x oversample clock NBAUDOUT The interrupt interface contains registers UOIER and UOIIR The interrupt interface receives several one clock wide enables from the UOTx and UORx blocks Status information from the UOTx and UORx is stored in the UOLSR Control information for the UOTx and UORx is stored in the UOLCR UART 0 94 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 NTXRDY NBAUDOUT RCLK INTERRUPT NRXRDY UOIER UOINTR UOIIR PA 2 0 PSEL PSTB PWRITE VPB PD 7 0 Interface AR MR Figure 15 UARTO Block Diagram UART 0 95 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 UART 0 96 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 10 UART 1 FEATURES UART 1 is identical to UART 0 with the addition of a modem interface 16 byte Receive and Transmit FIFOs Register locations conform to 550 industry standard Receiver FIFO trigger points at 1 4 8 and 14 bytes Built in baud rate generator
249. ve and CPHA is set to 0 the transfer starts when the SSEL signal goes active and ends when SSEL goes inactive When a device is a slave and CPHA is set to 1 the transfer starts on the first clock edge when the slave is selected and ends on the last clock edge where data is sampled SPI Peripheral Details General Information There are four registers that control the SPI peripheral They are described in detail in Register Description section The SPI control register contains a number of programmable bits used to control the function of the SPI block The settings for this register must be set up prior to a given data transfer taking place The SPI status register contains read only bits that are used to monitor the status of the SPI interface including normal functions and exception conditions The primary purpose of this register is to detect completion of a data transfer This is indicated by the SPIF bit The remaining bits in the register are exception condition indicators These exceptions will be described later in this section The SPI data register is used to provide the transmit and receive data bytes An internal shift register in the SPI block logic is used for the actual transmission and reception of the serial data Data is written to the SPI data register for the transmit case There is no buffer between the data register and the internal shift register A write to the data register goes directly into the internal shift register
250. ve address in the same serial transfer e Slave Address R DATA A DAIA p m Data Transferred m 1 Read n Bytes Acknowledge A Acknowledge SDA low From Master to Slave A Not Acknowledge SDA high From Slave to Master S START condition P STOP Condition Figure 24 Format of slave transmitter mode PIN DESCRIPTION Table 85 I2C Pin Description Pin Name Description Serial Data 12C data input and output The associated port pin has an open drain output in PA order to conform to 12C specifications Input Serial Clock IC clock input and output The associated port pin has an open drain output in SCL 2 Sepe Output order to conform to I C specifications 12C Interface 115 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 REGISTER DESCRIPTION The 12C interface contains 7 registers as shown in Table 86 below Table 86 IC Register Map i Reset Address Name Description Access Value OxE001C000 I2CONSET 17C Control Set Register Read Set 0 0xE001C004 I2STAT I C Status Register Read Only 0xE001C008 I2DAT IC Data Register Read Write A LI 12C Control Clear Register Reset Value refers to the data stored in used bits only It does not include reserved bits content 12C Interface 116 September 17 2003 Philips Semiconductors Preliminary User Manual
251. vent the slave returns to idle and any data that was received is thrown away There are no other indications of this exception This signal is not directly driven by the master It could be driven by a simple general purpose I O under software control Master In Slave Out The MISO signal is a unidirectional signal used to transfer serial data MISO Input from the slave to the master When a device is a slave serial data is output on this signal When Output a device is a master serial data is input on this signal When a slave device is not selected the slave drives the signal high impedance Input Master Out Slave In The MOSI signal is a unidirectional signal used to transfer serial data MOSI P from the master to the slave When a device is a master serial data is output on this signal Output A Dun si When a device is a slave serial data is input on this signal SPI Interface 127 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 REGISTER DESCRIPTION The SPI contains 5 registers as shown in Table 99 All registers are byte half word and word accessible Table 99 SPI Register Map Reset Address Description Access Value 0xE0020000 SPI Control Register This register controls the operation of the SPI Read Write 0 0xE0020004 SPSR SPI Status Register This register shows the status of the SPI Read Only m SPI Data Register This bi directional registe
252. ver Data Ready RDR Overrun Error OE Parity Error PE Framing Error FE Break Interrupt BI Transmitter Holding Register Empty THRE Transmitter Empty TEMT Error in Rx FIFO RXFE 0 UORBR is empty 1 UORBR contains valid data UOLSRO is set when the UORBR holds an unread character and is cleared when the UARTO RBR FIFO is empty 0 Overrun error status is inactive 1 Overrun error status is active The overrun error condition is set as soon as it occurs An UOLSR read clears UOLSR1 UOLSR1 is set when UARTO RSR has a new character assembled and the UARTO RBR FIFO is full In this case the UARTO RBR FIFO will not be overwritten and the character in the UARTO RSR will be lost 0 Parity error status is inactive 1 Parity error status is active When the parity bit of a received character is in the wrong state a parity error occurs An UOLSR read clears UOLSR2 Time of parity error detection is dependent on UOFCRO A parity error is associated with the character being read from the UARTO RBR FIFO 0 Framing error status is inactive 1 Framing error status is active When the stop bit of a received character is a logic 0 a framing error occurs An UOLSR read clears UOLSR3 The time of the framing error detection is dependent on UOFCRO A framing error is associated with the character being read from the UARTO RBR FIFO Upon detection of a framing error the Rx will attempt to resynchron
253. via memory Some of the IAP calls require more than 4 parameters If the ARM suggested scheme is used for the parameter passing returning then it might create problems due to difference in the C compiler implementation from different vendors The suggested parameter passing scheme reduces such risk The flash memory is not accessible during a write or erase operation IAP commands which results in a flash write erase operation use 32 bytes of space in the top portion of the on chip RAM for execution The user program should not be use this space if IAP flash programming is permitted in the application Table 158 IAP Command Summary IAP Command Command Code Described in Prepare sector s for write operation 50 Table 159 Flash Memory System and Programming 194 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Command Code Command parameter table Parameter 0 Parameter 1 ARM Register rO ARM Register r1 Parameter n Status Code Result 0 Command result table Result 1 Result n Figure 39 IAP Parameter passing Prepare sector s for write operation This command makes flash write erase operation a two step process Table 159 IAP Prepare sector s for write operation command description Command Prepare sector s for write operation Command code 50 Input Paramo Start Sector Number P
254. visor Latch 0xE000C004 Divisor Latch DLAB 1 UODLM MSB MSB LsB mw ES Reset Value refers to the data stored in used bits only It does not include reserved bits content UART 0 contains ten 8 bit registers as shown in Table 58 The Divisor Latch Access Bit DLAB is contained in UOLCR7 and enables access to the Divisor Latches UART 0 Receiver Buffer Register UORBR 0xE000C000 when DLAB 0 Read Only The UORBR is the top byte of the UARTO Rx FIFO The top byte of the Rx FIFO contains the oldest character received and can be read via the bus interface The LSB bit 0 represents the oldest received data bit If the character received is less than 8 bits the unused MSBs are padded with zeroes The Divisor Latch Access Bit DLAB in UOLCR must be zero in order to access the UORBR The UORBR is always Read Only UART 0 86 September 17 2003 Philips Semiconductors Preliminary User Manual ARM based Microcontroller LPC2106 2105 2104 Table 59 UARTO Receiver Buffer Register UORBR 0xE000C000 when DLAB 0 Read Only Reset Value Function Description Receiver Buffer The UARTO Receiver Buffer Register contains the oldest received byte in the UARTO Rx un Register FIFO defined UARTO Transmitter Holding Register UOTHR 0xE000C000 when DLAB 0 Write Only The UOTHR is the top byte of the UARTO Tx FIFO The top byte is the newest character in the Tx FIFO and can be written via the bus interface The LSB repr
255. will be set to p 0 if PWMMR 1 matches the PWMTC When zero this feature is disabled When one an interrupt is generated when PWMMR2 matches the value in the eN PWMTC When zero this interrupt is disabled When one an interrupt is generated when PWMMR4 matches the value in the is ta de PWMTC When zero this interrupt is disabled 13 Reset on PWMMR4 When one the PWMTC will be reset if PWMMR4 matches it When zero this feature is disabled When one the PWMTC and PWMPC will be stopped and PWMTCAR O will be set to H MAIS 0 if PWMMR4 matches the PWMTC When zero this feature is disabled When one an interrupt is generated when PWIMMR5 matches the value in the 5 AMAS PWMTC When zero this interrupt is disabled 16 Reseton PWMMR5 eee the PWMTC will be reset if PWMMR5 matches it When zero this feature 7 Reset on PWMMR2 When one the PWMTC will be reset if PWMMR2 matches it When zero this feature is disabled Stop on PWMMR2 When one the PWMTC and PWMPC will be stopped and PWMTCAR O will be set to p 0 if PWMMR2 matches the PWMTC When zero this feature is disabled When one an interrupt is generated when PWMMRS matches the value in the MURRAY PWMTC When zero this interrupt is disabled 10 Reset on PWMMR3 When one the PWMTC will be reset if PWMMRS3 matches it When zero this feature is disabled When one the PWMTC and PWMPC will be stopped and PWMTCR O will be set to dl Stop on PWMMRS 0 if PWMMR3 matches the PWMTC When zero this feature is disabled
256. x0000 0000 The reset vector contains a jump instruction to the entry point of the flash boot loader software 2 0 GB 8k byte Boot Block Or EE REFER re mapped from top of Flash memory 2 0 GB 8kB Boot Block interrupt vectors 0x7FFF E000 0x0001 FFFF 8k byte Boot Block re Mapped to higher address range 0x0001 E000 0 0 GB Active interrupt vectors from the Boot Block 0x0000 0000 Note memory regions are not drawn to scale Figure 37 Map of lower memory after any reset Criterion for valid user code The reserved ARM interrupt vector location 0x0000 0014 should contain the 2 s complement of the check sum of the remaining interrupt vectors This causes the checksum of all of the vectors together to be 0 The boot loader code disables the overlaying of the interrupt vectors from the boot block then calculates the checksum of the interrupt vectors in sector 0 of the flash If the signatures match then the execution control is transferred to the user code by loading the program counter with Ox 0000 0000 Hence the user flash reset vector should contain a jump instruction to the entry point of the user application code If the signature is not valid the auto baud routine synchronizes with the host via serial port 0 The host should send a synchronization character and wait for a response The host side serial port settings should be 8 data bits 1 stop bit and no parity The auto baud routine measures the bit time of the rece

NXP LPC2104, LPC2105, LPC2106 User Manual

Contents

Download Pdf Manuals

Related Search

Related Contents