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Datasheet - Mouser Electronics

1. 16 4 7 Watchdog timers 16 48 17 4 9 Beeper MeL 17 4 10 16 bit advanced control timer 17 4 11 2 TIMG 16 bit general purpose timers 17 4 12 TIMA 8 bit basic timer css osse o RR RR RR Heed 18 4 13 Analog to digital converter ADC1 18 4 14 Communication interfaces 18 4441 2 RE ad 19 434 2 a dis ee ee Reo e m acute aC aa Ag 20 94 12 n 20 5 Pinouts and pin descriptions 21 5 1 Alternate function remapping 25 6 Memory and register 26 6 1 Memory 26 6 2 27 7 Interrupt vector mapping 37 2 97 DoclD022186 Rev 4 Ly STM8S005C6 STM8S005K6 Contents 8 9 10 11 12 Option T ia ACD 38 Electrical characteristics 42 9 1 Parameter conditions
2. X Port 02 2 Timer 2 ADC ETR 44 28 ETR VO X 3 Port D3 AFRO PD4 TIM2_CH1 Timer 2 BEEP output 45 29 VO X PortD4 AFR7 46 30 PD5 UART2 TX O x X X 1 X X Port 05 data transmit 47 81 O X X X 1 X X Port receive PD7 TLI Top level TIM1 CH4 48 92 Oh runt AFR4 1 A pull up is applied to PF4 during the reset phase This pin is input floating after reset release 2 AIN12 is not selectable in ADC scan mode or with analog watchdog 3 In the open drain output column T defines a true open drain I O P buffer weak pull up and protection diode to Vpp are not implemented 4 The PD1 pin is in input pull up during the reset phase and after the internal reset release 5 1 As shown in the rightmost column of the pin description table some alternate functions can Alternate function remapping be remapped at different I O ports by programming one of eight AFR alternate function remap option bits Refer to Section 8 Option bytes When the remapping option is active the default alternate function is no longer available To use an alternate function the corresponding peripheral must be enabled in the peripheral registers Alternate function remapping do
3. Peripheral clock gating register 1 OxFF 0x00 50C8 CLK CSSR Clock security system register 0x00 0x00 50C9 CLK CCOR Configurable clock control register 0x00 0x00 50CA CLK PCKENR2 Peripheral clock gating register 2 OxFF 0x00 50CB Reserved area 1 byte Ky DoclD022186 Rev 4 29 97 Memory and register map STM8S005C6 STM8S005K6 Table 8 General hardware register map continued 30 97 DoclD022186 Rev 4 Address Block Register label Register name ud 0x00 50CC CLK HSITRIMR HSI clock calibration trimming register 0x00 0x00 50CD OLK SWIMCCR SWIM clock control register xe Reserved area 3 bytes 0x00 50D1 EE WWDG CR WWDG control register Ox7F 0x00 50D2 WWDG WR WWDR window register Ox7F Reserved area 13 bytes 0x00 50E0 IWDG_KR IWDG key register 0x00 50E1 IWDG IWDG PR IWDG prescaler register 0x00 0x00 50E2 IWDG RLR IWDG reload register OxFF Reserved area 13 bytes 0x00 50F0 AWU CSR1 AWU control status register 1 0x00 0x00 50F1 AWU AWU APR AWU asynchronous prescaler buffer register Ox3F 0x00 50F2 AWU_TBR AWU timebase selection register 0x00 0x00 50F3 BEEP BEEP CSR BEEP control status register Ox1F Reserved area 12 bytes 0x00 5200 SPI CR1 SPI control register 1 0x00 0x00 5201 SPI CR2 SPI control register 2 0x00 0x0
4. 42 9 1 1 Minimum and maximum values 42 9 1 2 Typical values edes hd rA eer REA E 42 9 1 3 Typical curves suras cx REOR ee ee Re 42 9 1 4 Typical current consumption 42 9 1 5 Pin loading conditions 43 9 1 6 Loading capacitor ees 43 9 1 7 Pin input voltage 2 eee 43 9 2 Absolute maximum 5 44 9 3 Operating conditions 46 9 3 1 VCAP external capacitor 48 9 3 2 Supply current characteristics 48 9 3 3 External clock sources and timing characteristics 58 9 3 4 Internal clock sources and timing characteristics 60 9 3 5 Memory characteristics 62 9 3 6 port pin characteristics 63 9 3 7 Reset pin characteristics 72 9 3 8 SPI serial peripheral interface 74 9 3 9 2 interface characteristics 77 9 3 10 10 bit ADC characteristics 79 9 311 characteristics 20 0 000 teens 82 Package information
5. 3 3 V standard ports 70 Vpp Vou Vpp 5 high sink ports 70 Typ Vpp Vpp 3 3 V high sink ports 71 Typical NRST Vi and vs temperatures 72 Typical NRST pull up resistance vs Vpp 3temperatures 73 Typical NRST pull up current vs Vpp temperatures 73 Recommended reset pin protection 74 SPI timing diagram slave mode 0 75 SPI timing diagram slave mode and CPHA e 75 SPI timing diagram master mode MP 76 Typical application with 2 bus timing diagram 78 ADC accuracy 6 65 81 Typical application with ADC slsssseeel 81 LQFP48 48 pin 7 x 7 mm low profile quad flat package outline 85 LQFP48 48 7 x 7 mm low profile quad flat recommended footprint 87 LQFP48 marking example package 87 LQFP32 32 pin 7 x 7 mm low profile quad flat package outline 88 LQFP32 32 pin 7 x 7 mm low profile quad flat recommended footprint 89 D
6. Address Block Register label Register name 0 00 5000 PA ODR Port A data output latch register 0x00 0x00 5001 PA IDR Port A input pin value register 0 00 5002 Port A PA DDR Port A data direction register 0x00 0x00 5003 PA CR1 Port A control register 1 0x00 0x00 5004 PA CR2 Port A control register 2 0x00 0x00 5005 PB ODR Port B data output latch register 0x00 0x00 5006 PB IDR Port B input pin value register OxXx 0x00 5007 Port B PB_DDR Port B data direction register 0x00 0x00 5008 PB CR1 Port B control register 1 0x00 0x00 5009 PB CR2 Port B control register 2 0x00 0x00 500A PC ODR Port C data output latch register 0x00 0x00 500B PB IDR Port C input pin value register 0x00 500C Port C PC DDR Port C data direction register 0x00 0x00 500D PC CR1 Port C control register 1 0x00 0x00 500E PC CR2 Port C control register 2 0x00 0x00 500F PD ODR Port D data output latch register 0x00 0x00 5010 PD IDR Port D input pin value register OxXx 0x00 5011 Port D PD_DDR Port D data direction register 0x00 0x00 5012 PD CR1 Port D control register 1 0x02 0x00 5013 PD CR2 Port D control register 2 0x00 DoclD022186 Rev 4 27 97 Memory and register map STM8S005C6 STM8S005K6 Table 7 port hardware register map continued Address Block Register label Register name 0 00 501
7. 65 Output driving current high sink ports llle 66 NRST pin characteristics 2 0 72 SPI characteristics esee esa ad Reb epe d geb data 74 IC characteristics 22628 Seeds hand o decore iq metuis paci a ques acta v d dtr 77 ADC characteristics ee e aa ea ee aes 79 ADC accuracy with RA lt 10 5 80 ADC accuracy with Rain lt 10 RAIN VDDA SION Acc 80 EMO ONG 82 EMI aa eed OA 83 ESD absolute maximum 5 83 DoclD022186 Rev 4 5 97 List of tables STM8S005C6 STM8S005K6 Table 49 Table 50 Table 51 Table 52 Table 53 6 97 Electrical sensitivities 84 LQFP48 48 pin 7 x 7 mm low profile quad flat package mechanical data 86 LQFP32 32 pin 7 x 7 mm low profile quad flat package mechanical data 89 Thermal characteristics cee n 91 Document revision history eee 96 DoclD022186 Rev 4 Ly STM8S005C6 STM8S005K6 List of figures List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figur
8. interrupt enable register 0x00 0x00 5342 SR TIM4 status register 0x00 0x00 5343 TIM4 TIM4_EGR TIM4 event generation register 0x00 0x00 5344 TIM4_CNTR TIM4 counter 0x00 0x00 5345 TIM4_PSCR prescaler register 0x00 0x00 5346 TIM4_ARR TIM4 auto reload register OxFF Reserved area 185 bytes 0x00 5400 ADC CSR ADC control status register 0x00 0x00 5401 ADC CR1 ADC configuration register 1 0x00 0x00 5402 ADC CR2 ADC configuration register 2 0x00 0x00 5403 ADC configuration register 3 0x00 0x00 5404 ADC DRH ADC data register high OxXX 0x00 5405 ADC DRL ADC data register low OxXX 0x00 5406 ADC TDRH ADC Schmitt trigger disable register high 0x00 0x00 5407 iDo ADC_TDRL ADC Schmitt trigger disable register low 0x00 0x00 5408 ADC_HTRH ADC high threshold register high 0x03 0x00 5409 ADC_HTRL ADC high threshold register low OxFF 0x00 540A ADC LTRH ADC low threshold register high 0x00 0x00 540B ADC LTRL ADC low threshold register low 0x00 0x00 540C ADC_AWSRH ADC analog watchdog status register high 0x00 0x00 540D ADC_AWSRL ADC analog watchdog status register low 0x00 0x00 540E ADC_AWCRH ADC analog watchdog control register high 0x00 0x00 540F ADC_AWCRL ADC analog watchdog control register low 0x00 Reserved area 1008 bytes 34 97 DoclD022186 Rev 4 STM8S005C6 STM8S005K6 Memory and register map 1 Depends on the previous reset source 2 Write only register Table 9 CPU SWIM debug m
9. life augmented STM8S005C6 STM8S005K6 Value line 16 MHz STM8S 8 bit MCU 32 Kbytes Flash data EEPROM 10 bit ADC timers UART SPI Features Core e Max fopy 16 MHz e Advanced 5 8 core with Harvard architecture and 3 stage pipeline e Extended instruction set Memories e Medium density Flash EEPROM Program memory 32 Kbytes of Flash memory data retention 20 years at 55 C after 100 cycles Data memory 128 bytes true data EEPROM endurance up to 100 k write erase cycles e RAM 2 Kbytes Clock reset and supply management e 2 95Vt05 5 operating voltage e Flexible clock control 4 master clock sources Low power crystal resonator oscillator External clock input Internal user trimmable 16 MHz RC Internal low power 128 kHz RC e Clock security system with clock monitor e Power management Low power modes wait active halt halt Switch off peripheral clocks individually Permanently active low consumption power on and power down reset Interrupt management e Nested interrupt controller with 32 interrupts e Up to 37 external interrupts on 6 vectors March 2015 Datasheet production data 2 LQFP48 LQFP32 7 x 7mm 7 x 7mm Timers e 2x 16 bit general purpose timers with 2 3 CAPCOM channels IC OC or PWM e Advanced control timer 16 bit 4 CAPCOM channels 3 complementary outputs dead time insertion and flexible synchronizatio
10. 6 MHz 12 2 5 2 MHz 0 2 2 Gain error fApc 4 MHz 0 6 2 5 LSB 6 MHz 0 8 2 5 fapc 2 MHz 0 7 1 5 Ep Differential linearity error 2 fApc 4 MHz 0 7 1 5 fapc 6 MHz 0 8 1 5 2 MHz 0 6 1 5 ELI Integral linearity error 2 fapc 4 MHz 0 6 1 5 fapc 6 MHz 0 6 1 5 Data based on characterization results not tested in production 2 ADC accuracy vs negative injection current Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input It is recommended to add a Schottky diode pin to ground to standard analog pins which may potentially inject negative current Any positive injection current within the limits specified for and in Section 9 3 6 does not affect the ADC accuracy Table 45 ADC accuracy with Rain 10 Rains VppA 3 3 V Symbol Parameter Conditions Typ Max Unit 2 MHz 1 1 2 0 Total unadjusted error E fApc 4 MHz 1 6 2 5 f 2 MHz 0 7 1 5 Eo Offset error fapc 4 MHz 1 3 2 0 f 2 MHz 0 2 1 5 Eg Gain error LSB 4 MHz 0 5 2 0 f 2 MHz 0 7 1 0 Ep Differential linearity error fADC 4 MHz 0 7 1 0 f 2 MHz 0 6 1 5 Integral linearity error 4 MHz 0 6 1 5 1 Data based on char
11. no load e All peripherals are disabled clock stopped by Peripheral Clock Gating registers except if explicitly mentioned e When the MCU is clocked at 24 MHz lt 85 C and the WAITSTATE option bit is set Subject to general operating conditions for and DoclD022186 Rev 4 STM8S005C6 STM8S005K6 Electrical characteristics Table 19 Total current consumption with code execution in run mode at Vpp 5 V Symbol IDD RUN Parameter Conditions Typ Max HSE crystal osc 16 MHz 3 2 fuasrER 16 MHz HSE user ext clock 16 MHz 2 6 3 2 Supply HSI RC osc 16 MHz 25 32 current in run mode a Vas HSE user ext clock 16 MHz 1 6 2 2 code CPU MASTER 2 HSI RC 16 MHz 1 3 2 0 from RAM fopy 128 15 625 kHz HSI RC osc 16 MHz 8 0 75 fcPu fMASTER 128 kHz LSI RC osc 128 kHz 0 55 HSE crystal osc 16 MHz 7 7 fuasrER 16 MHz HSE user ext clock 16 MHz 7 0 8 0 Supply HSI RC osc 16 MHz 70 8 0 current in run mode fopy faster 2 MHz HSI osc 16 2 8 0 1 5 code executed CPU MAsrER 128 125 kHz HSI RC osc 16 MHz 1 35 2 0 from Flash 1 5 1 28 15 625 kHz HSI RC osc 16 MHz 8 0 75 fopu fMASTER 128 kHz LSI RC osc 128 kHz 0 6 Unit mA 1 Data based on charact
12. 85 10 1 LQFP48 package 85 10 2 LQFP32 package 88 10 3 Thermal characteristics 91 10 3 1 Reference document 91 10 3 2 Selecting the product temperature range 92 Part numbering 93 STM8 development tools 94 12 1 Emulation and in circuit debugging tools 94 DoclD022186 Rev 4 3 97 Contents STM8S005C6 STM8S005K6 12 2 acd e a Good eol pew awed 95 12 2 1 51 81001561 occu ace xe nn ER RR Re eS RR Re RR d 95 12 2 2 Candassembly toolchains 95 12 3 Programming 00 eoe send doen Cee aed be vea dera de 95 13 Revision history 96 4 97 DoclD022186 Rev 4 STM8S005C6 STM8S005K6 List of tables List of tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35
13. c 46 32 31 30 29 28 27 26 25 5 1 24 5 8 1_ OSCIN PA1 2 23 Pc6 HS SPI MOSI OSCOUT PA2L 3 22 PC5 HS SPI SCK 4 21 HSyTIM1 5 20 HSyTIM1 6 19 2 HSyTIM1 CH2 17 18 HSyTIM1 CH1 UART2 12 4 8 17 PES SPI 58 9 10 11 12 13 14 15 16 amp jajanna 2 22 2 2 2 2 lt lt lt lt lt lt RoE SEZ 258868 S S E C 2 MSv37490V1 Table 4 Legend abbreviations for STM8S005C6 K6 pin descriptions table Type input O output S power supply Input CM CMOS Level Output HS high sink O1 slow up to 2 MHz O2 fast up to 10 MHz Output speed eee OS fast slow programmability with slow as default state after reset fast slow programmability with fast as default state after reset Port and control Input float floating wou weak pull up configuration Output T true open drain OD open drain PP push pull Bold x pin state after internal reset release Reset state Unless otherwise specified the pin state is the same during the reset phase and after the internal reset releas
14. 20 Reserved DoclD022186 Rev 4 15 97 Product overview STM8S005C6 STM8S005K6 4 6 4 7 16 97 Power management For efficent power management the application can be put in one of four different low power modes You can configure each mode to obtain the best compromise between lowest power consumption fastest start up time and available wakeup sources e Wait mode In this mode the CPU is stopped but peripherals are kept running The wakeup is performed by an internal or external interrupt or reset e Active halt mode with regulator In this mode the CPU and peripheral clocks are stopped An internal wakeup is generated at programmable intervals by the auto wake up unit AWU The main voltage regulator is kept powered on so current consumption is higher than in active halt mode with regulator off but the wakeup time is faster Wakeup is triggered by the internal AWU interrupt external interrupt or reset e Active halt mode with regulator off This mode is the same as active halt with regulator on except that the main voltage regulator is powered off so the wake up time is slower e Halt mode In this mode the microcontroller uses the least power The CPU and peripheral clocks are stopped the main voltage regulator is powered off Wakeup is triggered by external event or reset Watchdog timers The watchdog system is based on two independent timers providing maximum security to the applications Activation
15. 32 pin 7 x 7 mm low profile quad flat package outline SEATING PLANE SU ccc 1 11111111 0 25 mm GAUGE PLANE 5V ME V2 1 Drawing is not to scale DoclD022186 Rev 4 STM8S005C6 STM8S005K6 Package information Table 51 LOFP32 32 pin 7 x 7 mm low profile quad flat package mechanical data millimeters inches Symbol Min Typ Max Min Typ Max A 1 600 0 0630 A1 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 300 0 370 0 450 0 0118 0 0146 0 0177 0 090 0 200 0 0035 0 0079 D 8 800 9 000 9 200 0 3465 0 3543 0 3622 D1 6 800 7 000 7 200 0 2677 0 2756 0 2835 D3 5 600 0 2205 E 8 800 9 000 9 200 0 3465 0 3543 0 3622 E1 6 800 7 000 7 200 0 2677 0 2756 0 2835 E3 5 600 0 2205 e 0 800 0 0315 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 1 000 z 0 0394 k 0 3 5 79 0 3 5 7 0 100 0 0039 1 9 70 4 7 30 0 80 Values in inches are converted from mm and rounded to 4 decimal digits 16 Y 4 gt 7 30 9 a 9 70 0 50 Figure 48 LOFP32 32 pin 7 x 7 mm low profile quad flat
16. ADC1 supply current when converting 955 54 97 1 Data based on a differential Ipp measurement between reset configuration and timer counter running at 16 MHz No IC OC programmed no I O pads toggling Not tested in production 2 Data based on a differential Ipp measurement between the on chip peripheral when kept under reset and not clocked and the on chip peripheral when clocked and not kept under reset No I O pads toggling Not tested in production 3 Data based on a differential Ipp measurement between reset configuration and continuous A D conversions Not tested in production DoclD022186 Rev 4 STM8S005C6 STM8S005K6 Electrical characteristics Current consumption curves Figure 15to Figure 16 show typical current consumption measured with code executing in RAM Figure 11 Typ Ipp nuw VS HSE user external clock 16 MHz 40 C 25 C 2 95 2 9 2 85 2 8 Hse mA 2 75 2 7 Ipp RuN 2 65 2 6 2 55 2 5 2 5 3 3 5 4 4 5 5 5 5 6 MS37494V1 Figure 12 Typ IDD RUN vs VDD HSE user external clock Vpp 25V MA fcpu MHz MS37495V1 d DoclD022186 Rev 4 55 97 Electrical characteristics STM8S005C6 STM8S005K6 56 97 Figure 13 Typ Ipp wri VS Vpp HSE user external clock 16 MHz Ippwrpase mA MS37496V1 Figure 14 Typ Ip
17. consumption 4 170 2509 pA 1 See the application note 2 Guaranteed by design not tested in production 3 Data based on characterization results not tested in production Figure 19 Typical HSI frequency variation vs Vpp at 3 temperatures 16 5 16 4 16 3 N HSI frequency MHz o Voo V MS37498V1 60 97 DoclD022186 Rev 4 STM8S005C6 STM8S005K6 Electrical characteristics Low speed internal RC oscillator LSI Subject to general operating conditions for Vpp and Ty Table 33 LSI oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit figi Frequency 5 128 kHz LSI oscillator wakeup time 70 Hs Ipp Lsiy LSI oscillator power consumption 5 5 1 Guaranteed by design tested in production Figure 20 Typical LSI frequency variation vs Vpp 25 C LSI frequency MHz 150 145 140 135 130 125 120 115 110 105 100 MS37499V1 DoclD022186 Rev 4 61 97 Electrical characteristics STM8S005C6 STM8S005K6 9 3 5 62 97 Memory characteristics RAM and hardware registers Table 34 RAM and hardware registers Symbol Parameter Conditions Min Unit Data retention mode Halt mode or reset Vir max V 1 Minimum supply voltage without losing data stored in RAM in halt mode or under reset or in hardwa
18. 15 us 1 Data based on characterization results not tested in production 2 The Rpy pull up equivalent resistor is based on a resistive transistor 3 Data guaranteed by design not tested in production Figure 34 Typical Vi and Vj vs 3 temperatures gt aaa oun gt MS37713V1 72 97 DoclD022186 Rev 4 STM8S005C6 STM8S005K6 Electrical characteristics Figure 35 Typical NRST pull up resistance vs 3 temperatures NRESET pull up resistance kohm 2 5 3 3 5 4 4 5 5 5 5 6 Voo V MS37714V1 Figure 36 Typical NRST pull up current vs Vpp 3 temperatures 140 120 100 80 60 40 NRESET pull up current uA Voo V MS37715V1 The reset network shown in Figure 37 protects the device against parasitic resets The user must ensure that the level on the NRST pin can go below the Vj max level specified in Table 36 Otherwise the reset is not taken into account internally For power consumption sensitive applications the capacity of the external reset capacitor can be reduced to limit charge discharge current If the NRST signal is used to reset the external circuitry care must be taken of the charge discharge time of the external capacitor to fulfill the external device s reset timing conditions The minimum recommended capacity is 10 nF DoclD022186 Rev 4 73
19. 8010 3 EXTIO A external interrupts Yes 0x00 8014 4 EXTI1 Port B external interrupts Yes Yes 0x00 8018 5 EXTI2 Port C external interrupts Yes Yes 0x00 801C 6 EXTIS Port D external interrupts Yes Yes 0x00 8020 7 EXTIA Port E external interrupts Yes Yes 0x00 8024 8 Reserved 0x00 8028 9 Reserved 0x00 802C 10 SPI End of transfer Yes Yes 0x00 8030 11 ee ee _ _ 0x00 8034 12 TIM1 TIM1 capture compare 0 00 8038 13 TIM2 TIM2 update overflow 0x00 803C 14 TIM2 TIM2 capture compare 0x00 8040 15 TIM3 Update overflow 5 0 00 8044 16 TIM3 Capture compare 0x00 8048 17 Reserved 0x00 804C 18 s Reserved x 0x00 8050 19 interrupt Yes Yes 0x00 8054 20 UART2 complete 5 0 00 8058 21 UART2 Receive register DATA FULL 0x00 805C 22 Apc ADU 0x00 8060 23 TIM4 TIM4 update overflow 5 0 00 8064 24 Flash EOP WR PG DIS 0x00 8068 Reseed 0x00 806C to 0x00 807C 1 Except PA1 Ky DoclD022186 Rev 4 37 97 Option bytes STM8S005C6 STM8S005K6 8 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device They are stored in a dedicated block of the memory Except for the ROP read out protection byte each option byte has to be stored twice in a regular form OPTx and a complemented one for redundancy Option bytes can be modified in ICP mode via SWIM by accessing the EEPROM addres
20. 97 Electrical characteristics 5 85005 6 STM8S005K6 Figure 37 Recommended reset pin protection External reset NRST Filter Internal reset circuit optional STM8 9 3 8 SPI serial peripheral interface Unless otherwise specified the parameters given in Table 41 are derived from tests performed under ambient temperature fyaster frequency Vpp supply voltage conditions 1 fMASTER Refer to I O port characteristics for more details on the input output alternate function characteristics NSS SCK MOSI MISO Table 41 SPI characteristics Symbol Parameter Conditions Min Max Unit f Master mode 0 8 SCK SPI clock frequency MHz Slave mode 0 6 SCK SPI clock rise and fall time Capacitive load C 30 pF 25 tsynss NSS setup time Slave mode 4 X tmasTER tnwss NSS hold time Slave mode 70 1 IMGOKH SCK high and low time Master mode 2 15 tgcK 2 15 w SCKL t 1 Master mode 5 SuMD Data input setup time tsu Sl Slave mode 5 1 Master mode 7 ns thm Data input hold time this Slave mode 10 Data output access time Slave mode 3 X MASTER taisoy 9 Data output disable time Slave mode 25 twso Data output valid time Slave mode after enable edge 73 Data output valid time Mast
21. Package type 1 T LQFP Temperature range 6 6 40 C to 85 C Package pitch No character 0 5 mm 20 8 mm Packing TR No character Tray or tube TR Tape and reel For a list of available options e g memory size package and orderable part numbers or for further information on any aspect of this device please go to www st com or contact the ST Sales Office nearest to you DoclD022186 Rev 4 2 Refer to Table 1 STM8S005C6 K6 value line features for detailed description 93 97 5 8 development tools STM8S005C6 STM8S005K6 12 12 1 94 97 STM8 development tools Development tools for the STM8 microcontrollers include the full featured STice emulation system supported by a complete software tool package including C compiler assembler and integrated development environment with high level language debugger In addition the STM8 is to be supported by a complete range of tools including starter kits evaluation boards and a low cost in circuit debugger programmer Emulation and in circuit debugging tools The STice emulation system offers a complete range of emulation and in circuit debugging features on a platform that is designed for versatility and cost effectiveness In addition STM8 application development is supported by a low cost in circuit debugger programmer The STice is the fourth generation of full featured emulators from STMicroelectronics It
22. Table 9 CPU SWIM debug module interrupt controller registers continued Address Block Register Label Register Name Ox007F90 OMbreakpointiregisterextended byte OxFF 0x00 7F91 DM BK1RH DM breakpoint 1 register high byte OxFF 0x00 7F92 DM BK1RL DM breakpoint 1 register low byte OxFF 0x00 7F93 DM 2 DM breakpoint 2 register extended byte OxFF 0x00 7F94 DM BK2RH DM breakpoint 2 register high byte OxFF 0x00 7F95 DM DM BKA2RL DM breakpoint 2 register low byte OxFF 0x00 7F96 DM debug module control register 1 0x00 0x00 7F97 DM CR2 DM debug module control register 2 0x00 0x00 7F98 DM CSR1 DM debug module control status register 1 0x10 0x00 7F99 DM CSR2 DM debug module control status register 2 0x00 0x00 7F9A DM ENFCTR DM enable function register OxFF ed Reserved area 5 bytes 1 Accessible by debug module only 36 97 DoclD022186 Rev 4 STM8S005C6 STM8S005K6 Interrupt vector mapping 7 Interrupt vector mapping Table 10 Interrupt mapping lees Description atau om Wakeup om Vector address RESET Reset Yes Yes 0x00 8000 TRAP Software interrupt 0 00 8004 0 TLI External top level interrupt 5 0 00 8008 1 AWU Auto wake up from halt Yes 0x00 800C 2 CLK Clock controller 0x00
23. nH 48 pin devices with output on eight standard ports two _ 443 mW high sink ports and two 3 Power dissipation at drain ports simultaneously 85 C for suffix 6 or Sumix 32 pin devices with output on eight standard ports and _ 360 mW two high sink ports simultaneously TA Ambient temperature Ira Maximum power dissipation 40 85 suffix version C Ty Junction temperature range 40 105 1 Care should be taken when selecting the capacitor due to its tolerance as well as the parameter dependency on temperature DC bias and frequency in addition to other factors The parameter specifications must be respected for the full application range This frequency of 1 MHz as a condition for VcAp parameters is given by the design of the internal regulator To calculate Pomax Ta use the formula Ppmax Tymax Ta Oya see Section 10 3 Thermal characteristics on page 91 with the value Tor T amas given in Table 17 above and the value for given in Table 52 Thermal characteristics 4 Referto Section 10 3 Thermal characteristics on page 91 for the calculation method 46 97 022186 Rev 4 STM8S005C6 STM8S005K6 Electrical characteristics Figure 9 Versus Vpp fcp u MHz 24 Functionality not guaranteed in 16 this area 12 1 Functionality guaranteed with 0 wait state 8 1 4 0 2 95 4 0 5 0 5 5 Supply voltage V MS19
24. or not For more details refer to the UMO0560 STMB8L S bootloader manual for more details 40 97 DoclD022186 Rev 4 STM8S005C6 STM8S005K6 Option bytes Table 13 Description of alternate function remapping bits 7 0 OPT2 Option byte number OPT2 Description AFR7Alternate function remapping option 7 0 AFR7 remapping option inactive default alternate function 1 Port D4 alternate function BEEP AFR6 Alternate function remapping option 6 0 AFR6 remapping option inactive default alternate function 1 Port B5 alternate function IC port B4 alternate function Fc Sol AFRB5 Alternate function remapping option 5 0 AFR5 remapping option inactive default alternate function 1 Port B3 alternate function TIM1 ETR port B2 alternate function CHSN port B1 alternate function TIM1_CH2N port BO alternate function AFRA Alternate function remapping option 4 0 AFR4 remapping option inactive default alternate function 1 Port D alternate function TIM1_CH4 AFR3 Alternate function remapping option 0 AFR3 remapping option inactive default alternate function 1 Port DO alternate function AFR2 Alternate function remapping option 2 0 AFR2 remapping option inactive default alternate function 1 Port DO alternate function CLK_CCO Note AFR2 option has priority over AFR3 if both are activated AFR1 Alter
25. to the device This is a stress rating only and functional operation of the device under these conditions is not implied Exposure to maximum rating conditions for extended periods may affect device reliability Table 14 Voltage characteristics Symbol Ratings Min Max Unit Vppx Vss Supply voltage including Vppa 0 3 6 5 Input voltage on true open drain pins PE1 2 2 Vss 0 3 6 5 V Input voltage on any other 0 3 Vpp 0 3 Vppx Variations between different power pins 5 50 mi Vssl Variations between all the different ground pins 50 see Absolute maximum VEsp Electrostatic discharge voltage ratings electrical sensitivity on page 83 1 All power Vppa and ground 5 pins must always be connected to the external power supply 2 Must never be exceeded This is implicitly insured if Vjy maximum is respected If maximum cannot be respected the injection current must be limited externally to the value A positive injection is induced gt while a negative injection is induced by Viy Vas For true open drain pads there is no positive injection current and the corresponding maximum must always be respected DoclD022186 Rev 4 STM8S005C6 STM8S005K6 Electrical characteristics Table 15 Current characteristics Symbol Rati
26. 0 5202 SPI ICR SPI interrupt control register 0x00 0x00 5203 SPI SR SPI status register 0x02 0x00 5204 SPI DR SPI data register 0x00 0x00 5205 SPI CRCPR SPI CRC polynomial register 0x07 0x00 5206 SPI RXCRCR SPI Rx CRC register OxFF 0x00 5207 SPI TXCRCR SPI Tx CRC register OxFF Reserved area 8 bytes 0x00 5210 I2C control register 1 0x00 0x00 5211 I2C CR2 control register 2 0x00 0x00 5212 2 FREQR 2 frequency register 0x00 0x00 5213 2 own address register low 0x00 0x00 5214 own address register high 0x00 0x00 5215 Reserved STM8S005C6 STM8S005K6 Memory and register map Table 8 General hardware register map continued Address Block Register label Register name 0x00 5216 122 DR data register 0x00 0x00 5217 2 SR1 status register 1 0x00 0x00 5218 120 582 status register 2 0 00 0 00 5219 122 SR3 status register 3 0x00 0x00 521A 120 22 interrupt control register 0x00 0x00 521B I2C_CCRL clock control register low 0x00 0x00 521C 122 clock control register high 0x00 0x00 521D 122 TRISER 2 TRISE register 0x02 0x00 521E I2C_PECR packet error checking register 0x00 Reserved area 17 bytes Reserved area 6 bytes 0x00 5240 UART2 SR UART2 status register 0xC
27. 005C6 STM8S005K6 STM8 development tools 12 2 12 2 1 12 2 2 12 3 Software tools STMB8 development tools are supported by a complete free software package from STMicroelectronics that includes ST Visual Develop STVD IDE and the ST Visual Programmer STVP software interface STVD provides seamless integration of the Cosmic and Raisonance C compilers for STM8 A free version that outputs up to 32 Kbytes of code is available STM8 toolset 8 toolset with STVD integrated development environment and STVP programming software is available for free download at www st com This package includes ST Visual Develop Full featured integrated development environment from ST featuring e Seamless integration of C and ASM toolsets e Full featured debugger e Project management e Syntax highlighting editor e Integrated programming interface e Support of advanced emulation features for STice such as code profiling and coverage ST Visual Programmer STVP Easy to use unlimited graphical interface allowing read write and verify the user STM8 microcontroller Flash program memory data EEPROM and option bytes STVP also offers project mode for saving programming configurations and automating programming sequences C and assembly toolchains Control of C and assembly toolchains is seamlessly integrated into the STVD integrated development environment making it possible to configure and control the building of user app
28. 1 capture compare mode register 2 0x00 0x00 525A TIM1 CCMR3 TIM1 capture compare mode register 3 0x00 0x00 525B TIM1_CCMR4 TIM1 capture compare mode register 4 0x00 0x00 525C TIM1_CCER1 TIM1 capture compare enable register 1 0x00 0x00 525D TIM1_CCER2 TIM1 capture compare enable register 2 0x00 0x00 525E TIM1_CNTRH TIM1 counter high 0x00 0x00 525F TIM1_CNTRL TIM1 counter low 0x00 0x00 5260 Lu TIM1 PSCRH TIM1 prescaler register high 0x00 0x00 5261 TIM1 PSCRL TIM1 prescaler register low 0x00 0x00 5262 TIM1 ARRH TIM1 auto reload register high OxFF 0x00 5263 TIM1 ARRL TIM1 auto reload register low OxFF 0x00 5264 TIM1 RCR TIM1 repetition counter register 0x00 0x00 5265 TIM1 CCR1H TIM1 capture compare register 1 high 0x00 0x00 5266 TIM1 CCR1L TIM1 capture compare register 1 low 0x00 0x00 5267 TIM1 CCR2H TIM1 capture compare register 2 high 0x00 0x00 5268 TIM1 CCR2L TIM1 capture compare register 2 low 0x00 0x00 5269 TIM1 CCR3H TIM1 capture compare register 3 high 0x00 0x00 526A TIM1 CCRS3L TIM1 capture compare register 3 low 0x00 0x00 526B TIM1_CCR4H TIM1 capture compare register 4 high 0x00 0x00 526C TIM1_CCR4L TIM1 capture compare register 4 low 0x00 0x00 526D TIM1_BKR TIM1 break register 0x00 0x00 526E TIM1_DTR TIM1 dead time register 0x00 0x00 526F TIM1 OISR TIM1 output idle state register 0x00 a E Reserved area 147 bytes 32 97 DoclD022186 Rev 4 STM8S005C6 STM8S005K6 Memory and register map Table 8 General hardware regis
29. 18 12 2 SCIL O1 X X Port input 4 AFR6 PB3 AINS3 Analog TIM1 ETR 19 13 TIM1 ETR O1 X X Port B3 input 3 AFR5 TIM1 PB2 AIN2 Analog m 20 14 VO X O1 X X Port 82 TIM1 CH3N input 2 AFRS PB1 AIN1 Analog 21 15 O1 X X Port B1 CH2N TIM1_CH2N input 1 AFR5 DoclD022186 Rev 4 23 97 Pinouts and pin descriptions STM8S005C6 STM8S005K6 Table 5 STM8S005C6 and 5 85005 6 pin descriptions continued Pin number Input Output c zo Alternate Default x 8 Pin name 9 5 alternate function Fi 222 8 6 5 function 2127 remap 66 8 8 2 0 s5 option bit l I PBO AINO TIM1 Analo TMi 22 16 CH1N O1 X X Port BO in a CH1N AFR5 23 PE7 AIN8 O X X O1 X X Port E7 Analog input 8 24 PE6 AIN9 VO 11 X Port E6 Analog input 9 SPI 25 17 PE5 SPI_NSS O1 X X Port E5 master slave select Timer 1 channel 26 18 oll VOIX X X 5 03 X Port C1 1 UART2 UART2_CK synchronous clock Timer 1 27 19 PC2 TIM1_CH2 X HS O3 X X Port C2 channel 2 28 20 PPC3 TIM X X 5 03 X X Port channel 3 Timer 1 29 21 4 1 VOIX X X 5 03 X Port channel 4 30 22 PC5 SPI_SCK VO
30. 2186 Rev 4 STM8S005C6 STM8S005K6 Electrical characteristics 9 3 6 I O port pin characteristics General characteristics Subject to general operating conditions for Vpp and T4 unless otherwise specified All unused pins must be kept at a fixed voltage using the output mode of the I O for example or an external pull up or pull down resistor Table 36 I O static characteristics Symbol Parameter Conditions Min Typ Max Unit Input low level ViL voltage 0 3 0 3 x V Input high level VDp 5 V Vis DD 0 7 x Vpp Vpop 0 83 V V Vhys Hysteresis 700 mV Rou Pull up resistor Vpp 5 V ViN Vss 30 55 80 Fast I Os 350 ns tet Rise and fall time Load 50 pF Rr iF 10 90 Standard and high sink I Os _ _ 12502 Load 50 pF Input leakage likg current Vss lt VIN lt Vpp 1 3 analog and digital Analog input ana eos LU 5 250 na Leakage current in likg inj ied Injection current 4 mA 109 1 Hysteresis voltage between Schmitt trigger switching levels Based on characterization results not tested in production 2 Data guaranteed by design not tested in production 3 Data based on characterization results not tested in production DoclD022186 Rev 4 63 97 Electrical characteristics 5 85005 6 STM8S005K6 64 97 Figure 21 Typical V
31. 2186 Rev 4 17 97 Product overview STM8S005C6 STM8S005K6 4 12 TIM4 8 bit basic timer e 8 bit autoreload adjustable prescaler ratio to any power of 2 from 1 to 128 e Clock source CPU clock e Interrupt source 1 x overflow update Table 3 TIM timer features Counter size Prescaler Counting CAPCOM Complem 3yneur bits mode channels outputs trigger onization chaining TIM1 16 Any integer from 1 to 65536 Up down 4 3 Yes TIM2 16 Any power of 2 from 1 to 32768 Up 3 0 No TIM3 16 Any power of 2 from 1 to 32768 Up 2 0 No is TIM4 8 Any power of 2 from 1 to 128 Up 0 0 No 4 13 Analog to digital converter ADC1 STM8S005C6 K6 value line products contain a 10 bit successive approximation A D converter ADC1 with up to 10 multiplexed input channels and the following main features e Input voltage range 0 to VppA e Conversion time 14 clock cycles e Single and continuous buffered continuous conversion modes e Buffer size 10 x 10 bits e Scan mode for single and continuous conversion of a sequence of channels e Analog watchdog capability with programmable upper and lower thresholds e Analog watchdog interrupt e External trigger input e Trigger from TIM1 TRGO e End of conversion EOC interrupt Note Additional AIN12 analog input is not selectable in ADC scan mode or with analog watchdog Values converted from AIN12 are stored only into the ADC_DRH ADC_DRL regist
32. 36 I O static characteristics the notes related to in Section 9 3 Operating conditions 13 Jun 2012 Updated the temperature condition for factory calibrated ACCyg in Table 32 HSI oscillator characteristics Changed SCK input to SCK output in Figure 40 SPI timing diagram master mode 1 26 Mar 2015 Updated the buffer size in Section 4 13 Analog to digital converter ADC1 the disclaimer Added the note to Power on reset threshold in Table 18 Operating conditions at power up power down Figure 46 LQFP48 marking example package top view Figure 49 LQFP32 marking example package top view DoclD022186 Rev 4 STM8S005C6 STM8S005K6 IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections enhancements modifications and improvements to ST products and or to this document at any time without notice Purchasers should obtain the latest relevant information on ST products before placing orders ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement Purchasers are solely responsible for the choice selection and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products No license express or implied to any intellectual property right is granted by ST herei
33. 4 PE ODR Port E data output latch register 0x00 0x00 5015 PE IDR Port E input pin value register 0 00 5016 Port E PE DDR Port E data direction register 0x00 0x00 5017 PE CR1 Port E control register 1 0x00 0x00 5018 PE CR2 Port E control register 2 0x00 0x00 5019 PF ODR Port F data output latch register 0x00 0x00 501A PF IDR Port F input pin value register 0x00 501B Port F PF DDR Port F data direction register 0x00 0x00 501C PF CR1 Port F control register 1 0x00 0x00 501D PF CR2 Port F control register 2 0x00 0x00 501E PG ODR Port G data output latch register 0x00 0x00 501F PG IDR Port G input pin value register OxXx 0x00 5020 PortG PG_DDR Port G data direction register 0x00 0x00 5021 PG CR1 Port G control register 1 0x00 0x00 5022 PG CR2 Port G control register 2 0x00 0x00 5023 PH ODR Port H data output latch register 0x00 0x00 5024 PH IDR Port H input pin value register OxxXx 0x00 5025 Port H PH_DDR Port H data direction register 0x00 0x00 5026 PH CR1 Port H control register 1 0x00 0x00 5027 PH CR2 Port H control register 2 0x00 0x00 5028 PI ODR Port data output latch register 0x00 0x00 5029 PI IDR Port input pin value register 0x00 502A Port PI DDR Port data direction register 0x00 0x00 502B PI CR1 Port control register 1 0x00 0x00 502C PI CR2 Port control register 2 0x00 1 Depends on the external circuitry 28 97 DoclD022186 Rev 4 STM8S005C6 STM8S005K6 Memory and regi
34. 413V1 Table 18 Operating conditions at power up power down Symbol Parameter Conditions Min Typ Max Unit rise time rate 20 us V Vpp fall time rate 20 s oo Reset release delay Vpp rising 1 700 ms Power on reset threshold 2 65 2 8 2 95 V Brown out reset Vi threshold 2 58 2 73 2 88 V Brown out reset VHYS BOR hysteresis 1 1 Guaranteed by design not tested in production 2 f Vpp is below 2 95 V the code execution is guaranteed above the and thresholds RAM content is kept The EEPROM programming sequence must not be initiated DoclD022186 Rev 4 47 97 Electrical characteristics STM8S005C6 STM8S005K6 9 3 1 9 3 2 48 97 VCAP external capacitor Stabilization for the main regulator is achieved connecting an external capacitor to the Vcap pin is specified in Table 17 Care should be taken to limit the series inductance to less than 15 nH Figure 10 External capacitor ESR C ESL Sos T Rleak 1 Legend ESR is the equivalent series resistance and ESL is the equivalent inductance Supply current characteristics The current consumption is measured as described in Figure 6 on page 42 Total current consumption in run mode The MCU is placed under the following conditions e pins in input mode with a static value at Vpp or
35. 8 The 8 bit STM8 core is designed for code efficiency and performance It contains six internal registers which are directly addressable in each execution context 20 addressing modes including indexed indirect and relative addressing and 80 instructions Architecture and registers e Harvard architecture e 3 5 pipeline e 32 bit wide program memory bus single cycle fetching for most instructions e XandY 16 bit index registers enabling indexed addressing modes with or without offset and read modify write type data manipulations e 8 bit accumulator e 24 bit program counter 16 Mbyte linear memory space e 16 bit stack pointer access to a 64 K level stack e 8 bit condition code register 7 condition flags for the result of the last instruction Addressing e 20addressing modes e Indexed indirect addressing mode for look up tables located anywhere in the address space e Stack pointer relative addressing mode for local variables and parameter passing Instruction set e 80instructions with 2 byte average instruction size e Standard data movement and logic arithmetic functions e 8 bit by 8 bit multiplication e 16 bit by 8 bit and 16 bit by 16 bit division e manipulation e Data transfer between stack and accumulator push pop with direct stack access e Data transfer using the X Y registers or direct memory to memory transfers 022186 Rev 4 STM8S005C6 STM8S005K6 Product ove
36. 8 FEFEEESZE SYS 20000000 DSSS FSDLELILLIFEE 0 0 2 00 48 47 46 45 44 43 42 41 4039 38 le 360PG1 OSCIN PA1 12 35H PGO OSCOUT PA2 03 340 PC7 HS SPI_MISO 4 33 HS SPI_MOSI 55 320 Vppio 2 6 31H 2 L7 30 PC5 HS SPI SCK 1 08 291 HS TIM1_CH4 TIM3_CH1 TIM2_CH3 PA3 19 2815 HS TIM1 CH3 HS PA4 0110 27 1 PC2 HS TIM1_CH2 HS 011 260 PC1 HS TIM1 CH1 UART2 CK HS PA6 012 25 5 5 55 1314 151617 18 192021 222324 00000000000 lt lt st CO QN Q rn do cmm P 14 QN OOD 2222222222 lt lt lt lt lt lt lt lt lt lt PC eS o oz 999 Sas a F 222 EBE 1 HS high sink capability 2 T True open drain P buffer and protection diode to Vpp not implemented 3 alternate function remapping option If the same alternate function is shown twice it indicates an exclusive choice not a duplication of the function DoclD022186 Rev 4 21 97 Pinouts and pin descriptions STM8S005C6 STM8S005K6 Figure 4 LQFP 32 pin pinout 9 x a z co 2 X zu a t X 5 o x 9 9 9 2 2 2 2 a4zax00000
37. 9 Total current consumption with code execution in run mode at Vpp 3 3 V 50 Total current consumption in wait mode Vpp 5 51 Total current consumption in wait mode at Vpp 3 8 V 51 Total current consumption in active halt mode at 5 V 40 to 85 C 52 Total current consumption in active halt mode at Vpp 3 3 V 52 Total current consumption in halt mode at 5 V Ta 40 to 85 C 53 Total current consumption in halt mode at 3 3 53 Wakeup times nml rsen emo uei onm Re e eee e US 53 Total current consumption and timing in forced reset state 54 Peripheral current consumption 54 HSE user external clock 5 58 HSE oscillator 5 5 59 HSI oscillator characteristics 2 2 60 LSI oscillator characteristics lille eh 61 RAM and hardware registers 62 Flash program memory data EEPROM memory 62 static characteristics 2 rh 63 Output driving current standard ports llle 65 Output driving current true open drain
38. Fh 38 97 DoclD022186 Rev 4 STM8S005C6 STM8S005K6 Option bytes Table 12 Option byte description Option byte no OPTO Description ROP 7 0 Memory readout protection ROP OxAA Enable readout protection write access via SWIM protocol Note Refer to the family reference manual 0016 section on Flash EEPROM memory readout protection for details OPT1 UBC 7 0 User boot code area 0x00 no UBC no write protection 0x01 Pages 0 to 1 defined as UBC memory write protected 0x02 Pages 0 to 3 defined as UBC memory write protected 0x03 Pages O0 to 4 defined as UBC memory write protected OxFE Pages 0 to 255 defined as UBC memory write protected OxFF Reserved Note Refer to the family reference manual RM0016 section on Flash EEPROM write protection for more details OPT2 7 0 Refer to Table 13 Description of alternate function remapping bits 7 0 of OPT2 OPT3 HSITRIM high speed internal clock trimming register size 0 3 bit trimming supported in CLK_HSITRIMR register 1 4 bit trimming supported in CLK_HSITRIMR register LSI EN Low speed internal clock enable 0 LSI clock is not available as CPU clock source 1 LSI clock is available as CPU clock source IWDG HW ndependent watchdog 0 IWDG Independent watchdog activated by software 1 IWDG Independent watchdog activated by hardware WWDG HW Window watchdog activation 0 WWDG window watchdog activat
39. M8S005C6 STM8S005K6 Figure 40 SPI timing diagram master mode High NSS input 14 teschi 8 0 5 CPOL 0 i n I I T CPHA 0 n 1 SCK Output 32 LI LI CPOL 1 1 1 1 ie LO SCK vt ve pe MISO INT O BITS IN tr CY M OUT BITI OUT OUT ai14136V2 1 Measurement points are done at CMOS levels 0 3 Vpp and 0 7 76 97 DoclD022186 Rev 4 STM8S005C6 STM8S005K6 Electrical characteristics 9 3 9 interface characteristics Table 42 I C characteristics faster Must be at least 8 MHz to achieve max fast 2 speed 400 2 Data based on standard 2 protocol requirement not tested in production The maximum hold time of the start condition has only to be met if the interface does not stretch the low time Standard mode Fast mode 12 0 Symbol Parameter Unit Min Max Min Max tw SCLL SCL clock low time 4 7 1 3 s tw SCLH SCL clock high time 4 0 5 0 6 x 80 SDA setup time 250 100 SDA data hold time 0 o9 9000 60 SDA and SCL rise time 1000 300 ns 8 1 SDA and SCL fall time 300 300 START condition ho
40. O 0x00 5241 UART2 DR UART2 data register OxXX 0x00 5242 UART2 UART2 baud rate register 1 0x00 0x00 5243 UART2 BRR2 UART2 baud rate register 2 0x00 0x00 5244 UART2 CR1 UART2 control register 1 0x00 0x00 5245 UART2 CR2 UART2 control register 2 0x00 0x00 5246 iid UART2_CR3 UART2 control register 3 0x00 0x00 5247 UART2_CR4 UART2 control register 4 0x00 0x00 5248 UART2_CR5 UART2 control register 5 0x00 0x00 5249 UART2_CR6 UART2 control register 6 0x00 0x00 524A UART2_GTR UART2 guard time register 0x00 05248 UART2PSCR UART2 prescaler register 00 eus Reserved area 4 bytes Ky DoclD022186 Rev 4 31 97 Memory and register map STM8S005C6 STM8S005K6 Table 8 General hardware register map continued Address Block Register label Register name wd 0x00 5250 TIM1 CR1 TIM1 control register 1 0x00 0x00 5251 TIM1 CR2 TIM1 control register 2 0x00 0x00 5252 TIM1 SMCR TIM1 slave mode control register 0x00 0x00 5253 TIM1 ETR TIM1 external trigger register 0x00 0x00 5254 TIM1 IER TIM1 Interrupt enable register 0x00 0x00 5255 TIM1 SR1 TIM1 status register 1 0x00 0x00 5256 TIM1 SR2 TIM1 status register 2 0x00 0x00 5257 TIM1 EGR TIM1 event generation register 0x00 0x00 5258 TIM1_CCMR1 TIM1 capture compare mode register 1 0x00 0x00 5259 TIM1_CCMR2 TIM
41. TM8S005C6 K6 value line provide the following benefits performance robustness reduced system cost and short development cycles Device performance and robustness are ensured by true data EEPROM supporting up to 100000 write erase cycles advanced core and peripherals made in a state of the art technology at 16 MHz clock frequency robust I Os independent watchdogs with separate clock source and a clock security system The system cost is reduced thanks to a high system integration level with internal clock oscillators watchdog and brown out reset The common family product architecture with compatible pinout memory map and modular peripherals allow application scalability and reduced development cycles All products operate from a 2 95 V to 5 5 V supply voltage Full documentation is offered as well as a wide choice of development tools Table 1 STM8S005C6 K6 value line features Features STM8S005C6 5 85005 6 Pin count 48 32 Max number of GPIOs I O 38 25 External interrupt pins 35 23 Timer CAPCOM channels 9 8 Timer complementary outputs 3 3 A D converter channels 10 7 High sink I Os 16 12 7 32K 32K Data EEPROM bytes 128 128 RAM bytes 2K 2K Advanced control timer TIM1 general purpose timers TIM2 Peripheral set and TIM3 basic timer TIM4 SPI I2C UART Window WDG independent WDG ADC 10 97 022186 Rev 4 STM8S005C6 STM8S005K6 Bloc
42. Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 Ly STM8S005C6 K6 value line 10 Peripheral clock gating bit assignments CLK_PCKENR1 2 registers 15 TIM timer features 0 0 0 0 0 hr 18 Legend abbreviations for STM8S005C6 K6 pin descriptions table 22 STM8S005C6 and STM8S005K6 pin 5 23 Flash Data EEPROM and RAM boundary 27 port hardware register 27 General hardware register map 29 CPU SWIM debug module interrupt controller 5 35 Interrupt MAPPING uae ecrire Rel ee Re a he UE RO RR a A 37 PED 38 Option byte description 0 0 eee nets 39 Description of alternate function remapping bits 7 0 of OPT2 41 Voltage characteristics 2 ee RR Ih 44 Current characteristics 0 45 Thermal characteristics llle n 45 General operating conditions liiis 46 Operating conditions at power up power down 47 Total current consumption with code execution run mode at Vpp 2 5 V 4
43. X X X X Port C5 5 clock 31 Vssio 2 S I O ground 32 Vppio 2 S I O power supply 23 X X X Port ce SP master out slave in 34 24 75 _ HS O3 X X Port SP master in slave out 35 PGO O X O1 X X Port GO 36 O X O1 X X Port G1 37 PES TIM1_BKIN O X X X O1 X X Port er 1 break input 38 PE2 PC O X 01 Port E2 12 data 39 PE1 2C_SCL O X X 01 Port E1 12 clock 40 PPEOUCLK cco X X HS O3 X X Port Eo COMgurable clock output 24 97 DoclD022186 Rev 4 Ly STM8S005C6 STM8S005K6 Pinouts and pin descriptions Table 5 STM8S005C6 and 5 85005 6 pin descriptions continued Pin number Input Output c Alternate Ooo Default x 8 Pin name 9 5 alternate function 2 25 function after remap o 6 52 55 option bit PDO TIM3 CH2 Timer 3 41 25 BKIN x x X Hs o3 X X Port DO CLK channel 2 CLK CCO AFR2 42 26 PDi SWIM X X X Port p1 data interface PD2 TIM3 CH1 Timer 3 TIM2 CH3 43 27 CHS VO
44. a V 0 5 0 25 8 o mA MS37708V1 Figure 30 Typ Vpp 5 V standard ports mA MS37709V1 DoclD022186 Rev 4 69 97 Electrical characteristics STM8S005C6 STM8S005K6 70 97 Figure 31 Vpp 3 3 V standard ports lon mA MS37710V1 Figure 32 Typ Vpp 5 high sink ports x Vou V 0 5 10 15 20 25 mA MS37711V1 DoclD022186 Rev 4 STM8S005C6 STM8S005K6 Electrical characteristics Figure 33 3 3 V high sink ports 8 mA 12 14 MS37712V1 DoclD022186 Rev 4 71 97 Electrical characteristics STM8S005C6 STM8S005K6 9 3 7 Reset pin characteristics Subject to general operating conditions for Vpp and T4 unless otherwise specified Table 40 NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit NRST input low level voltage 0 0 3 V 0 3 x Vpp Vinwwrst NRST input high level voltage 0 0 7 0 3 V NRST output low level voltage 1 loL 2 mA 5 0 5 Reuwrst NRST pull up resistor 0 1 30 55 80 kQ NRST input filtered pulse 9 75 ns Input not filtered pulse 9 500 A ns toewasr NRST output pulse 0
45. acterization results not tested in production 2 ADC accuracy vs negative injection current Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input It is recommended to add a Schottky diode pin to ground to standard analog pins which may potentially inject negative current Any positive injection current within the limits specified for liny pin and Section 9 3 6 does not affect the ADC accuracy 80 97 DoclD022186 Rev 4 Ly STM8S005C6 STM8S005K6 Electrical characteristics Figure 42 ADC accuracy characteristics A i i ri c e 7 1LSB 7 t 1021 _ IDEAL 1024 212 E 22 7 7 pt 4 3 i 71 A 1 1 64 r ES 1 Eo E 44 2 1 1 1 1 4 2 i 1 1 7 1 34 77 Ep 24 4 lt gt 1d 4 1 LSBipgaL 1 1 1 111 0 1 2 4 5 6 7 1021102210231024 Vssa 1 Example of an actual transfer curve 2 The ideal transfer curve 3 End point correlation line Total unadjusted error maximum deviation between the actual and the ideal transfer curves Eo Offset error deviation between the first actual transition and the first ideal one Eg Gain error deviation between the last ideal transition and the last actua
46. ata memory area 128 bytes EEPROM 71 Option bytes Programmable area from 1 Kbyte UBC area 2 first pages up to 32 Kbytes Remains write protected during IAP 1 page steps Medium density Flash program memory 92 Kbyte Program memory area Write access possible for IAP Read out protection ROP The read out protection blocks reading and writing the Flash program memory and data EEPROM memory in ICP mode and debug mode Once the read out protection is activated any attempt to toggle its status triggers a global erase of the program and data memory Even if no protection can be considered as totally unbreakable the feature provides a very high level of protection for a general purpose microcontroller 14 97 DoclD022186 Rev 4 STM8S005C6 STM8S005K6 Product overview 4 5 Clock controller The clock controller distributes the system clock faster coming from different oscillators to the core and the peripherals It also manages clock gating for low power modes and ensures clock robustness Features e Clock prescaler To get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler e Safe clock switching Clock sources can be changed safely on the fly in run mode through a configuration register The clock signal is not switched until the new clock source is ready The design g
47. by the AHALT bit in the register 52 97 DoclD022186 Rev 4 STM8S005C6 STM8S005K6 Electrical characteristics Total current consumption in halt mode Table 25 Total current consumption in halt mode at Vpp 5 V TA 40 to 85 C Symbol Parameter Conditions Typ Max Unit Flash in operating mode HSI 62 90 clock after wakeup Ipb H Supply current in halt mode Flash in power down mode HSI 6 5 25 clock after wakeup Table 26 Total current consumption in halt mode at Vpp 3 3 V Symbol Parameter Conditions Typ Unit Flash in operating mode HSI clock 60 90 after wakeup Ipp H Supply current in halt mode Flash in power down mode HSI 45 20 clock after wakeup 1 Data based on characterization results not tested in production Low power mode wakeup times Table 27 Wakeup times Symbol Parameter Conditions Typ Max Unit 2 t Wakeup time from wait d WU WFI 3 UWF mode to run mode faster 16 MHz 0 56 1 Flash in operating 10 20 mode MVR voltage 4 regulator on Flash in power down 3 6 5 Wakeup time active halt model HSI after m WU AH mode to run 9 Flash in operating Wakeup 486 5 MVR voltage model 4 regulator off Flash in power down 6 mode 80 Wakeup time from halt Flash in operating mode 52 5 mode to
48. cal characteristics Total current consumption in wait mode Table 21 Total current consumption in wait mode at Vpp 5 V Symbol Parameter Conditions Typ Max Unit HSE crystal osc 16 MHz 2 15 fuasrER 16 MHz HSE user ext clock 16 MHz 1 55 2 0 Supply HSI RC osc 16 MHz 1 5 1 9 Ccurrentin 128 125 kHz HSI RC osc 16 MHz 1 3 wait mode fcpu fuAsrER 128 2 1 15 625 kHz HSI RC osc 16 MHz 8 0 7 cPU fMASTER 128 kHz LSI RC osc 128 kHz 0 5 1 Data based on characterization results not tested in production 2 Default clock configuration measured with all peripherals off Table 22 Total current consumption in wait mode at Vpp 3 3 V Symbol Parameter Conditions Typ Max Unit HSE crystal osc 16 MHz 1 75 16 MHz HSE user ext clock 16 MHz 1 55 2 0 HSI RC osc 16 MHz 1 5 1 9 Supply IpD WFi current in fcpu 1 28 125 kHz HSI RC osc 16 MHz 1 3 mA waitmode fopu fmastER 128 HSI RC osc 16 MHz 8 2 0 7 15 625 kHz fopu fuasrER 128 15 625 kHz LSI RC osc 128 kHz 0 5 1 Data based on characterization results not tested in production 2 Default clock configuration measured with all peripherals off Ly DoclD022186 Rev 4 51 97 Electrical characteristics 5 85005 6 STM8S005K6 T
49. ck 16 2 56 Ipp wri VS HSE user external clock 5 56 Typ IDD RUN VS Vpp HSI RC OSC fopu 16 MHZ ve cele ie a ee 57 Typ IDD WFI VS HSI RC OSC 16 MHZ 57 HSE external clock source 58 HSE oscillator circuit diagram 59 Typical HSI frequency variation vs Vpp at 3 60 Typical LSI frequency variation vs 25 61 Typical Vi and Vj vs Vpp temperatures 64 Typical pull up resistance vs Vpp temperatures 64 Typical pull up current vs temperatures 65 5 V standard 66 Typ 3 3 V standard ports 67 Typ Vpp 5 V true open drain ports 67 Typ 3 3 V true open drain ports 68 5 V high sink ports 68 Typ VoL Vpop 3 3 V high Sink ports i usce ea REN y ER 69 Typ Vpp Vpp 5 V standard 69 Typ Vpp
50. clD022186 Rev 4 STM8S005C6 STM8S005K6 Package information 10 Package information To meet environmental requirements ST offers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com is an ST trademark 10 1 LQFP48 package information Figure 44 LQFP48 48 pin 7 x 7 mm low profile quad flat package outline SEATING PLANE GAUGE PLANE K 5B ME V2 1 Drawing is not to scale Ly DoclD022186 Rev 4 85 97 Package information STM8S005C6 STM8S005K6 86 97 Table 50 LQFP48 48 pin 7 x 7 mm low profile quad flat package mechanical data millimeters inches Symbol Min Typ Max Min Typ Max A 1 600 0 0630 1 0 050 0 150 0 0020 0 0059 2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 170 0 220 0 270 0 0067 0 0087 0 0106 0 090 0 200 0 0035 0 0079 D 8 800 9 000 9 200 0 3465 0 3543 0 3622 D1 6 800 7 000 7 200 0 2677 0 2756 0 2835 D3 5 500 0 2165 8 800 9 000 9 200 0 3465 0 3543 0 3622 E1 6 800 7 000 7 200 0 2677 0 2756 0 2835 ES 5 500 0 2165 x e 0 500 0 0197 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 k 0 3 5 7 0 3 5 19 ccc 0 080 0 0031 1 Val
51. d rate synchronization maximum tolerated initial clock deviation 15 e Synch delimiter checking e 11 bit LIN synch break detection break detection always active e Parity check on the LIN identifier field e LIN error management e Hot plugging support DoclD022186 Rev 4 19 97 Product overview STM8S005C6 STM8S005K6 4 14 2 4 14 3 20 97 SPI e Maximum speed 8 Mbit s fuasrEp 2 both for master and slave e Full duplex synchronous transfers e Simplex synchronous transfers on two lines with a possible bidirectional data line e Master or slave operation selectable by hardware software e CRC calculation e 1 byte Tx and Rx buffer e Slave master selection input pin e 2 master features Clock generation A Start and stop generation e 2 slave features Programmable 2 address detection Stop bit detection e Generation and detection of 7 bit 10 bit addressing and general call e Supports different communication speeds A Standard speed up to 100 kHz Fast speed up to 400 kHz DoclD022186 Rev 4 STM8S005C6 STM8S005K6 Pinouts and pin descriptions 5 Pinouts and pin descriptions Figure 3 LQFP 48 pin pinout o i x 9 8 B dw Haz NO T III Ig 002 9
52. e 22 97 DoclD022186 Rev 4 STM8S005C6 STM8S005K6 Pinouts and pin descriptions Table 5 STM8S005C6 and STM8S005K6 pin descriptions Pin number Input Output c zo Alternate ala 9 Sx eo CIN function e Pin name S 3 3 alternate 2 2115 gjaja 2 5 function after remap 516 5 amp 4 9 5 45 option bit a 2 x 1 1 NRST Reset 2 2 PA1 OSCIN O x O1 X Port crystal in PA2OSCOUT Jot Port 2 Resonator crystal out 4 1 S I O ground 5 4 Vss S Digital ground 6 5 VCAP S 1 8 V regulator capacitor 7 6 Vpp S Digital power supply 8 7 1 S I O power supply Timer 2 TIM3 CH1 9 2 O1 X X Port A3 1 10 PA4 X 5 3 X X Port A4 11 PA5 O X X X X Port A5 12 PA6 X HS O3 X X Port 8 2 VO x X O1 X X Port F4 13 9 S Analog power supply 14 10 Vssa S Analog ground 15 PB7 AIN7 x O1 X Port B7 72109 input 7 16 PB6 AING vo x x x O1 X X Port Be alog input 6 PB5 AIN5 Analog 6 17 11 2 SDA X O1 X X Port B5 input 5 AFR6 PB4 AIN4 Analog 601
53. e s the package junction to ambient thermal resistance C W e is the sum of Pintmax and Pintmax e S the product of Ipp and Vpp expressed Watts This is the maximum chip internal power e represents the maximum power dissipation on output pins where Promax gt 2 and taking account of the actual and of the I Os at low high level in the application Table 52 Thermal characteristics Symbol Parameter Value Unit Thermal resistance junction ambient LQFP 48 7 x 7 mm zd OJA OE Thermal resistance junction ambient LQFP 32 7 x 7 mm 89 C W 1 Thermal resistances are based on JEDEC JESD51 2 with 4 layer PCB in a natural convection environment Reference document JESD51 2 integrated circuits thermal test method environment conditions natural convection still air Available from www jedec org DocID022186 Rev 4 91 97 Package information STM8S005C6 STM8S005K6 10 3 2 92 97 Selecting the product temperature range When ordering the microcontroller the temperature range is specified in the order code see Figure 50 STM8S005C6 K6 value line ordering information scheme 1 The following example shows how to calculate the temperature range needed for a given application Assuming the following application conditi
54. e 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 Ly STM8S005C6 K6 value line block diagram 11 Flash memory organisation 14 LQFP 48 pin pinout 2 rh 21 LOFP 2 ed x Rn eh eee bed 22 Memory map eee xe E eae rare ede gga chat 26 Supply current measurement conditions 42 Pin loading conditions 43 Pin input voltage s nes ck ERR eee Ep RR OR RU Rite ox RI et RC 43 fep max Versus V pp eee eee weal ege aa RR RT Ea aad 47 External capacitor CE r seo siuu 48 Ipp RuN VS HSE user external clock 16 2 55 Ipp RuN VS HSE user external clock Vpp 5 V 55 Ipp wri VS HSE user external clo
55. ed by Viy Vpp while a negative injection is induced by Viy Vss For true open drain pads there is no positive injection current and the corresponding Viy maximum must always be respected 5 Negative injection disturbs the analog performance of the device See note in Section 9 3 10 10 bit ADC characteristics on page 79 6 When several inputs are submitted to a current injection the maximum is the absolute sum of the positive and negative injected currents instantaneous values These results ar based on characterization with maximum current injection on four I O port pins of the device Table 16 Thermal characteristics Symbol Ratings Value Unit Storage temperature range 65 to 150 Maximum junction temperature 150 Ly DoclD022186 Rev 4 45 97 Electrical characteristics STM8S005C6 STM8S005K6 9 3 Operating conditions The device must be used in operating conditions that respect the parameters in Table 17 In addition full account must be taken of all physical capacitor characteristics and tolerances Table 17 General operating conditions Symbol Parameter Conditions Min Max Unit fopu Internal CPU clock frequency 0 16 2 Vpp Vpp Standard operating voltage 1 2 95 5 5 V capacitance of external _ A70 3300 nF capacitor 1 ESR of external capacitor 5 0 3 At 1 MHz ESL of external capacitor 15
56. ed by software 1 WWDG window watchdog activated by hardware WWDG HALT Window watchdog reset on halt 0 No reset generated on halt if WWDG active 1 Reset generated on halt if WWDG active OPT4 EXTCLK External clock selection 0 External crystal connected to OSCIN OSCOUT 1 External clock signal on OSCIN CKAWUSEL Auto wakeup unit clock 0 LSI clock source selected for AWU 1 HSE clock with prescaler selected as clock source for for AWU PRSC 1 0 AWU clock prescaler Ox 16 MHz to 128 kHz prescaler 10 8 MHz to 128 kHz prescaler 11 4 MHz to 128 kHz prescaler DoclD022186 Rev 4 39 97 Option bytes STM8S005C6 STM8S005K6 Table 12 Option byte description continued Option byte no Description HSECNT 7 0 HSE crystal oscillator stabilization time This configures the stabilization time 0x00 2048 HSE cycles onl 0 4 128 HSE cycles 0 02 8 HSE cycles OxE1 0 5 HSE cycles OPT6 Reserved OPT7 Reserved BL 7 0 Bootloader option byte For STM8S products this option is checked by the boot ROM code after reset Depending on the content of addresses 0x487E 0x487F and 0x8000 reset vector the CPU jumps to the bootloader or to OPTBL the reset vector Refer to the UM0560 STM8L S bootloader manual for more details For STMB8L products the bootloader option bytes are on addresses OxXXXX and OxXXXX 1 2 bytes These option bytes control whether the bootloader is active
57. ed to avoid unintentional overwriting of memory that could result from a user software malfunction There are two levels of write protection The first level is known as MASS memory access security system MASS is always enabled and protects the main Flash program memory data EEPROM and option bytes To perform in application programming IAP this write protection can be removed by writing a MASS key sequence in a control register This allows the application to write to data EEPROM modify the contents of main program memory or the device option bytes A second level of write protection can be enabled to further protect a specific area of memory known as UBC user boot code Refer to Figure 2 DoclD022186 Rev 4 13 97 Product overview STM8S005C6 STM8S005K6 The size of the UBC is programmable through the UBC option byte Table 12 in increments of 1 page 512 bytes by programming the UBC option byte in ICP mode This divides the program memory into two areas e Main program memory 32 Kbytes minus UBC e User specific boot code UBC Configurable up to 32 Kbytes The UBC area remains write protected during in application programming This means that the MASS keys do not unlock the UBC area It protects the memory used to store the boot program specific code libraries reset and interrupt vectors the reset routine and usually the and communication routines Figure 2 Flash memory organisation Data D
58. er mode after enable edge 36 inso Slave mode after enable edge 28 Data output hold time Master mode after enable edge 12 1 Values based on design simulation and or characterization results and not tested in production 2 Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data 3 Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi Z 74 97 DoclD022186 Rev 4 Ly STM8S005C6 STM8S005K6 Electrical characteristics Figure 38 SPI timing diagram slave mode and CPHA 0 NSS input tc SCK 0 2 CPOL 0 x 0 CPOL 1 ta SO th SO MISO a OUTP UT BIT6 OUT tsu SI MOSI INPUT BIT1 IN LSB IN ai14134c Figure 39 SPI timing diagram slave mode and 10 NSS input ISU NSS i gt i CPOL 0 __ n x 1 9 CPOL 1 n 1 150 pL t SCKy 14 ta SO He dis SO 4 gt i MISO i MSH OUT OUT LSB OUT ths N MSBI BITI IN LSB IN INPUT 14135 1 Measurement points are done at CMOS levels 0 3 and 0 7 DoclD022186 Rev 4 75 97 Electrical characteristics ST
59. erization results not tested in production 2 Default clock configuration measured with all peripherals off DoclD022186 Rev 4 49 97 Electrical characteristics 5 85005 6 STM8S005K6 Table 20 Total current consumption with code execution in run mode at Vpp 3 3 V Symbol IDD RUN Parameter Conditions Typ Max Unit HSE crystal osc 16 MHz 2 8 fopu 16 MHz HSE user ext clock 16 MHz 2 6 3 2 Supply HSI RC osc 16 MHz 25 3 2 current in run mode 1 HSE user ext clock 16 MHz 1 6 2 2 Z code HSI RC osc 16 MHz 13 20 executed from RAM fopy 28 15 625 kHz HSI RC osc 16MHz 8 0 75 fopy 128 kHz LSI RC osc 128 kHz 0 55 HSE crystal 16 MHz 7 3 16 MHz HSE user ext clock 16 MHz 7 0 8 0 Supply HSI RC osc 16 MHz 7 0 8 0 current in run mode fcpy fuAsrER 2 MHz HSI RC osc 16 2 8 0 1 5 code executed CPU MAsrER 128 125 kHz HSI RC osc 16 MHz 135 2 0 from Flash fopy 28 15 625 kHz HSI RC osc 16 MHz 8 0 75 fcpu fMASTER 128 kHz LSI RC osc 128 kHz 0 6 1 Data based on characterization results not tested in production 2 Default clock configuration 50 97 DoclD022186 Rev 4 STM8S005C6 STM8S005K6 Electri
60. ers 4 14 Communication interfaces 18 97 The following communication interfaces are implemented e 2 full feature UART synchronous mode SPI master mode SmartCard mode IrDA mode IIN2 1 master slave capability e SPI full and half duplex 8 Mbit s 2 up to 400 Kbit s DoclD022186 Rev 4 STM8S005C6 STM8S005K6 Product overview 4 14 1 UART2 Main features e 1 Mbit s full duplex SCI e SPI emulation e High precision baud rate generator e Smartcard emulation e IrDA SIR encoder decoder e LIN master mode e Single wire half duplex mode Asynchronous communication UART mode e Full duplex communication NRZ standard format mark space e Programmable transmit and receive baud rates up to 1 Mbit s 16 and capable of following any standard baud rate regardless of the input frequency e Separate enable bits for transmitter and receiver e Two receiver wakeup modes A Address bit MSB Idle line interrupt e Transmission error detection with interrupt generation e control Synchronous communication e Full duplex synchronous transfers e SPI master operation e 8 bit data communication e Maximum speed 1 Mbit s at 16 MHz fcpu 16 LIN master mode e Emission generates 13 bit synch break frame e Reception detects 11 bit break frame LIN slave mode e Autonomous header handling one single interrupt per valid message header e Automatic bau
61. es not effect GPIO capabilities of the I O ports see the GPIO section of the family reference manual 0016 DoclD022186 Rev 4 25 97 Memory and register map STM8S005C6 STM8S005K6 6 6 1 26 97 Memory and register map Memory map Figure 5 Memory map 0x00 0000 RAM 6 Kbytes 0x00 07FF 512 bytes stack Reserved 0x00 4000 128 bytes data EEPROM 0x00 407F 0x00 4080 Reserved 0x00 47FF 0x00 4800 Option bytes 0x00 487F 0x00 4900 Reserved 0x00 4FFF 0x00 5000 GPIO and peripheral registers 0x00 57FF 0x00 5800 Reserved 0x00 5FFF 0x00 6000 2 Kbytes boot ROM 0x00 67FF 0x00 6800 Reserved 0x00 7EFF 0x00 7 CPU SWIM debug ITC 0x00 7FFF registers 0x00 8000 32 interrupt vectors 0x00 807F Flash program memory 32 bytes 0x00 FFFF 0x01 0000 Reserved 0x02 7FFF MS37491V1 DoclD022186 Rev 4 Ly STM8S005C6 STM8S005K6 Memory and register map 6 2 Table 6 lists the boundary addresses for each memory size The top of the stack is at the RAM end address in each case Table 6 Flash Data EEPROM and RAM boundary addresses Memory area Size bytes Start address End address Flash program memory 32K 0x00 8000 0x00 FFFF RAM 2K 0x00 0000 0x00 07FF Data EEPROM 128 0x00 4000 0x00 407F Register map Table 7 I O port hardware register map
62. guidelines and are not tested Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range where 95 of the devices have an error less than or equal to the value indicated mean 2 gt Typical curves Unless otherwise specified all typical curves are given only as design guidelines and are not tested Typical current consumption For typical current consumption measurements Vppio and Vppa are connected together in the configuration shown in Figure 6 Figure 6 Supply current measurement conditions 5Vor3 3V Vppio Vss Vssa Vssio DoclD022186 Rev 4 STM8S005C6 STM8S005K6 Electrical characteristics 9 1 5 Pin loading conditions 9 1 6 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 7 Figure 7 Pin loading conditions 8 pin 9 1 7 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 8 Figure 8 Pin input voltage l 5 8 pin DoclD022186 Rev 4 43 97 Electrical characteristics STM8S005C6 STM8S005K6 9 2 44 97 Absolute maximum ratings Stresses above those listed as absolute maximum ratings may cause permanent damage
63. icantly with the crystal manufacturer Figure 18 HSE oscillator circuit diagram 20 3 3 3 Resonator fuse to core OSCIN Resonator Consumption control g OSCOUT STM8 HSE oscillator critical gm formula 2 Imorit 2 x TI x fuso x 220 Rm Notional resistance see crystal specification Lm Notional inductance see crystal specification Cm Notional capacitance see crystal specification Co Shunt capacitance see crystal specification 42C Grounded external capacitance Om gt gt Omerit Ly DoclD022186 Rev 4 59 97 Electrical characteristics 5 85005 6 STM8S005K6 9 3 4 Subject to general operating conditions for Vpp and fuse High speed internal RC oscillator HSI Internal clock sources and timing characteristics Table 32 HSI oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit fug Frequency 16 MHz Trimmed by the Accuracy of HSI oscillator GLK_HSITRIMR register 1 09 for given and TA ACCus conditions oL Vpp 5 V Ta 25 5 Accuracy of HSI oscillator factory calibrated Vpp 5 V 5 5 40 C x lt 85 HSI oscillator wakeup _ _ 2 su HS time including calibration HSI oscillator power
64. j and Vy vs Vpp 3 temperatures MS37700V1 Figure 22 Typical pull up resistance vs Vpp 3 temperatures Pull up resistance kohm MS37701V1 DoclD022186 Rev 4 STM8S005C6 STM8S005K6 Electrical characteristics Figure 23 Typical pull up current vs Vpp 3 temperatures 140 60 Pull Up current yA 40 20 MS37702V1 1 The pull up is a pure resistor slope goes through 0 Table 37 Output driving current standard ports Symbol Parameter Conditions Min Max Unit VoL Output low level with 8 pins sunk 10 Vpp 5V 2 y Output low level with 4 pins sunk lio 4 mA Vpp 3 3 V Output high level with 8 pins sourced lig 10 Vpp 5 2 4 en Output high level with 4 pins sourced 4 mA Vpp 3 3 V 2 00 d 1 Data based on characterization results not tested in production Table 38 Output driving current E open drain ports 10 mA 5V lo 10 mA Vpp 3 3 V lio 20 mA 5V 1 Data based on characterization results not tested in production DoclD022186 Rev 4 65 97 Electrical characteristics 5 85005 6 STM8S005K6 Table 39 Output driving current high sink ports Unit Symbol Parameter Conditions Min Max Outputlowlevel with 8pinssunk 10 5 09 Output low leve
65. k can be internally connected to TIM3 input capture channel 1 for calibration Beeper The beeper function outputs a signal on the BEEP pin for sound generation The signal is in the range of 1 2 or 4 kHz The beeper output port is only available through the alternate function remap option bit AFR 7 TIM1 16 bit advanced control timer This is a high end timer designed for a wide range of control applications With its complementary outputs dead time control and center aligned PWM capability the field of applications is extended to motor control lighting and half bridge driver e 16 bit up down and up down autoreload counter with 16 bit prescaler e Four independent capture compare channels CAPCOM configurable as input capture output compare PWM generation edge and center aligned mode and single pulse mode output e Synchronization module to control the timer with external signals e Break input to force the timer outputs into a defined state e Three complementary outputs with adjustable dead time e Encoder mode e Interrupt sources x input capture output compare 1 x overflow update 1 x break TIM2 TIM3 16 bit general purpose timers e 16 bit autoreload AR up counter e 15 bit prescaler adjustable to fixed power of 2 ratios 1 32768 e Timers with or 2 individually configurable capture compare channels e PWM mode e Interrupt sources 2 or 3 x input capture output compare 1 x overflow update DoclD02
66. k diagram 3 Block diagram Figure 1 STM8S005C6 K6 value line block diagram 400 Kbit s 48 12C lt gt Reset block 4 XTAL 1 16 MHz Clock controller Reset 2 0 Reset RC int 16 MHz Detector POR BOR RC int 128 kHz Clock to peripherals and core 2 3 Window WDG STM8 core 2 gt lt gt Independent WDG Single wire debug interf Debug SWIM 32 Kbytes high density program Flash Master slave autosynchro 2 gt LIN master UART lt gt 128 bytes SPI emul data EEPROM 2 Kbytes RAM ES 8 Mbit s lt eds Boot ROM Address and data bus Up to E 16 bit advanced control A timer TIM1 3 complementary outputs up to 10 ADC1 lt gt 16 bit general purpose 1 2 Up to channels timers TIM2 TIM3 5 channels 1 2 4 kHz beep lt Beeper ip 8 bit basic timer AWU timer DoclD022186 Rev 4 11 97 Product overview STM8S005C6 STM8S005K6 4 4 1 12 97 Product overview The following section intends to give an overview of the basic features of the STM8S005C6 K6 value line functional modules and peripherals For more detailed information please refer to the corresponding family reference manual RM0016 Central processing unit STM
67. l one Ep Differential linearity error maximum deviation between actual steps and the ideal one E Integral linearity error maximum deviation between any actual transition and the end point correlation line Figure 43 Typical application with ADC STM8 R v qe BIN 10 bit A D AIN conversion Capc DoclD022186 Rev 4 81 97 Electrical characteristics STM8S005C6 STM8S005K6 9 3 11 82 97 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization Functional EMS electromagnetic susceptibility While executing a simple application toggling 2 LEDs through I O ports the product is stressed by two electromagnetic events until a failure occurs indicated by the LEDs e ESD Electrostatic discharge positive and negative is applied on all pins of the device until a functional disturbance occurs This test conforms with the IEC 61000 4 2 standard e FTB A burst of fast transient voltage positive and negative is applied to Vpp and Vss through a 100 pF capacitor until a functional disturbance occurs This test conforms with the IEC 61000 4 4 standard A device reset allows normal operations to be resumed The test results are given in the table below based on the EMS levels and classes defined in application note AN1709 Designing hardened software to avoid noise problems EMC characterization and optimi
68. l with 4 pins sunk lio 10 Vpp 3 3 V 1 10 Output low level with 4 pins sunk lio 20 mA 5 V 1 60 Output high level with 8 pins sourced 10 mA Vpp 5 3 8 Vou Output high level with 4 pins sourced lo 10 Vpp2 33 V 1 90 Output high level with 4 pins sourced 20 mA Vpp 5 V 2 90 1 Data based on characterization results not tested in production 66 97 Typical output level curves Figure 25to Figure 32 show typical output level curves measured with output on a single pin Figure 24 Typ Voi 5 V standard ports mA MS37703V1 DoclD022186 Rev 4 STM8S005C6 STM8S005K6 Electrical characteristics Figure 25 3 3 V standard ports V 4 lo mA MS37704V1 Figure 26 5 V true open drain ports mA MS37705V1 DoclD022186 Rev 4 67 97 Electrical characteristics STM8S005C6 STM8S005K6 Figure 27 Typ 3 3 V true open drain ports Va 0 75 0 5 0 25 0 2 4 6 8 10 12 14 lo mA MS37706V1 Figure 28 Typ 5 V high sink ports MS37707V1 68 97 DoclD022186 Rev 4 STM8S005C6 STM8S005K6 Electrical characteristics Figure 29 VoL Vpp 3 3 high sink ports 1 5 1 25 0 75 V
69. ld time 4 0 0 6 us tsuista Repeated START condition setup time 4 7 0 6 lsusro STOP condition setup time 4 0 0 6 STOP to START condition time 47 13 lw STO STA bus free us Capacitive load for each bus line 5 400 400 pF 4 The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL DoclD022186 Rev 4 77 97 Electrical characteristics 5 85005 6 STM8S005K6 78 97 Figure 41 Typical application with I C bus and timing diagram VDD 1 START __ tsu STa I 1 Nf XK TN 1 1 1 1 4 50 91 14 lsu SDA 1 4 GER 1 STOP1 su Ih STA 9 SCIL gt lt Ih SDA 1 1 1 1 SCL 3 1 1 tw SCLH 14 91 SCL PH 14 gt tsu STO ai17490V2 1 Measurement points are made at CMOS levels 0 3 x Vpp and 0 7 x Vpp DoclD022186 Rev 4 STM8S005C6 STM8S005K6 Electrical characteristics 9 3 10 10 bit ADC characteristics Subject to general operating conditions for and Ta unless otherwise specified Table 43 ADC characteristics Symbol Parameter Conditions Min Typ Max Unit 3 5 5 V 1 4 fapc ADC clock frequency MHz VDDA 4 5to5 5V 1 6 Anal
70. lication directly from an easy to use graphical interface Available toolchains include e Cosmic C compiler STM8 One free version that outputs up to 32 Kbytes of code is available For more information see www cosmic software com e Haisonance C compiler for STM8 One free version that outputs up to 32 Kbytes of code For more information see www raisonance com STM8 assembler linker Free assembly toolchain included in the STVD toolset which allows users to assemble and link the user application source code Programming tools During the development cycle STice provides in circuit programming of the STM8 Flash microcontroller on user application board via the SWIM protocol Additional tools are to include a low cost in circuit programmer as well as ST socket boards which provide dedicated programming platforms with sockets for programming the user 5 8 For production environments programmers will include a complete range of gang and automated programming solutions from third party tool developers already supplying programmers for the STM8 family DoclD022186 Rev 4 95 97 Revision history STM8S005C6 STM8S005K6 13 96 97 Revision history Table 53 Document revision history Date 14 Oct 2011 Revision 1 Changes Initial release 09 Jan 2012 Updated tper in Table 35 Flash program memory data EEPROM memory Rpy in Table 40 NRST pin characteristics and Table
71. n Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product ST and the ST logo are trademarks of ST All other product or service names are the property of their respective owners Information in this document supersedes and replaces information previously supplied in any prior versions of this document 2015 STMicroelectronics All rights reserved DoclD022186 Rev 4 97 97 Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery amp Lifecycle Information STMicroelectronics STM8S005C6T6TR STM8S005C6T6 8 85005 6 6 STM8S005K6T6CTR
72. n e 8 basic timer with 8 bit prescaler e Auto wakeup timer e Window and independent watchdog timers Communications interfaces e UART with clock output for synchronous operation SmartCard IrDA LIN e SPI interface up to 8 Mbit s 2 interface up to 400 Kbit s Analog to digital converter ADC e 10 bit ADC 1 LSB ADC with up to 10 multiplexed channels scan mode and analog watchdog I Os e Upto 38 I Os on a 48 pin package including 16 high sink outputs e Highly robust I O design immune against current injection Development support e Embedded single wire interface module SWIM for fast on chip programming and non intrusive debugging DoclD022186 Rev 4 1 97 This is information on a product in full production www st com Contents STM8S005C6 STM8S005K6 Contents 1 Tcro 9 2 Description aci ick x e ca ada ei ica Re REC a datu Rc ded 10 3 Bl ck diagram xh acu 11 4 Product overview 12 4 1 Central processing unit STM8 12 4 2 Single wire interface module SWIM and debug module DM 13 4 3 Interrupt controller 13 4 4 Flash program and data EEPROM memory 13 4 5 Clock controller ue qaos edax ERR PP DARE ER RE 15 4 6 Power management
73. nate function remapping option 1 0 AFR1 remapping option inactive default alternate function 1 Port alternate function port D2 alternate function TIM2_CH3 AFRO Alternate function remapping option 0 0 AFRO remapping option inactive default alternate function 1 Port D3 alternate function ADC_ETR 2 1 Do not use more than one remapping option in the same port 2 Refer to the pinout description DoclD022186 Rev 4 41 97 Electrical characteristics STM8S005C6 STM8S005K6 9 9 1 42 97 Electrical characteristics Parameter conditions Unless otherwise specified all voltages are referred to Ves Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature supply voltage and frequencies by tests in production on 100 of the devices with an ambient temperature at T4 25 C and given by the selected temperature range Data based on characterization results design simulation and or technology characteristics are indicated in the table footnotes and are not tested in production Based on characterization the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation mean 3 gt Typical values Unless otherwise specified typical data are based on 25 C Vpp 5 V They are given only as design
74. ngs Unit Total current into Vpp power lines source 2 60 lyss Total current out of Vss ground lines sink 60 is Output current sunk by any I O and control pin 20 Output current source by any I Os and control pin 20 Total output current sourced sum of all and control pins for devices with two pins 200 Total output current sourced sum of all and control pins for devices with one Vppio pin 100 Total output current sunk sum of all and control pins for devices with two pins 160 Total output current sunk sum of all I O and control pins for 8 80 devices with one Vsgio pin Injected current on NRST pin 4 Injected current on OSCIN pin 4 Injected current on any other pin 4 Total injected current sum of all I O and control pins 20 1 Data based on characterization results not tested in production 2 All power Vpp Vppio VppA and ground Vas Vssa pins must always be connected to the external supply 3 pins used simultaneously for high current source sink must be uniformly spaced around the package between the Vppjo Vssio pins 4 must never be exceeded This is implicitly insured if maximum is respected If maximum cannot be respected the injection current must be limited externally to the liy value A positive injection is induc
75. o induce functional disturbance conforming to IEC 61000 4 4 1 Data obtained with HSI clock configuration after applying HW recommendations described in AN2860 EMC guidelines for STM8Smicrocontrollers DoclD022186 Rev 4 Ly STM8S005C6 STM8S005K6 Electrical characteristics Electromagnetic interference EMI Emission tests conform to the SAE IEC 61967 2 standard for test software board layout and pin loading Table 47 EMI data Conditions 1 Symbol Parameter Monitored Max fuse fcpu Unit General conditions frequency band 8 MHz 8 MHz 8 MHz 16 MHz 0 1 MHz to 30 MHz 13 14 Vpp 5 V Peak level TA 25 C 30 MHz to 130 MHz 23 19 dBuV Semi LQFP48 package 130 MHz to 1 GHz 4 0 4 0 conforming to SAE SAE EMI 61967 2 20 15 level 1 Data based on characterization results not tested in production Absolute maximum ratings electrical sensitivity Based on two different tests ESD and LU using specific measurement methods the product is stressed in order to determine its performance in terms of electrical sensitivity For more details refer to the application note AN1181 Electrostatic discharge ESD Electrostatic discharges 3 positive then 3 negative pulses separated by 1 second are applied to the pins of each sample according to each pin combination The sample size depends on the number of supply pins in the device 3 parts n 1 supply
76. oclD022186 Rev 4 7 97 List of figures STM8S005C6 STM8S005K6 Figure 49 LQFP32 marking example package top view 90 Figure 50 STM8S005C6 K6 value line ordering information 93 8 97 DoclD022186 Rev 4 STM8S005C6 STM8S005K6 Introduction 1 Introduction This datasheet contains the description of the STM8S005C6 K6 value line features pinout electrical characteristics mechanical data and ordering information e For complete information on the STM8S microcontroller memory registers and peripherals please refer to the STM8S and STM8A microcontroller families reference manual RM0016 e For information on programming erasing and protection of the internal Flash memory please refer to the 0051 How to program STM8S and STM8A Flash program memory and data EEPROM e For information on the debug and SWIM single wire interface module refer to the STM8 SWIM communication protocol and debug module user manual 0 0470 e For information on the STMB core please refer to the STM8 CPU programming manual PM0044 DoclD022186 Rev 4 9 97 Description STM8S005C6 STM8S005K6 2 Description The STM8S005C6 K6 value line 8 bit microcontrollers offer 32 Kbytes Flash program memory plus 128 bytes of data EEPROM They are referred to as medium density devices in the STM8S microcontroller family reference manual RM0016 All devices of S
77. odule interrupt controller registers Address Block Register Label Register Name 0x00 7F00 A Accumulator 0x00 0x00 7F01 PCE Program counter extended 0x00 0x00 7F02 PCH Program counter high 0x00 0x00 7F03 PCL Program counter low 0x00 0x00 7F04 XH X index register high 0x00 0x00 7F05 XL X index register low 0x00 0x00 7F06 YH Y index register high 0x00 0x00 7F07 YL Y index register low 0x00 0x00 7F08 SPH Stack pointer high 0x17 0x00 7F09 SPL Stack pointer low OxFF 0x00 7F0A CCR Condition code register 0x28 gor Reserved area 85 bytes 0x00 7F60 CPU CFG GCR Global configuration register 0x00 0x00 7F70 SPR1 Interrupt software priority register 1 OxFF 0x00 7F71 ITC_SPR2 Interrupt software priority register 2 OxFF 0x00 7F72 SPR3 Interrupt software priority register 3 OxFF 0x00 7F73 ie ITC_SPR4 Interrupt software priority register 4 OxFF 0x00 7F74 ITC_SPR5 Interrupt software priority register 5 OxFF 0x00 7F75 SPR6 Interrupt software priority register 6 OxFF 0x00 7F76 ITC_SPR7 Interrupt software priority register 7 OxFF 0x00 7F77 ITC_SPR8 Interrupt software priority register 8 OxFF Reserved area 2 bytes 0x00 7F80 SWIM SWIM CSR SWIM control status register 0x00 EE Reserved area 15 bytes Ky DoclD022186 Rev 4 35 97 Memory and register map STM8S005C6 STM8S005K6
78. of the watchdog timers is controlled by option bytes or by software Once activated the watchdogs cannot be disabled by the user program without performing a reset Window watchdog timer The window watchdog is used to detect the occurrence of a software fault usually generated by external interferences or by unexpected logical conditions which cause the application program to abandon its normal sequence The window function can be used to trim the watchdog behavior to match the application perfectly The application software must refresh the counter before time out and during a limited time window A reset is generated in two situations 1 Timeout at 16 MHz CPU clock the time out period can be adjusted between 75 us up to 64 ms 2 Refresh out of window The downcounter is refreshed before its value is lower than the one stored in the window register DoclD022186 Rev 4 STM8S005C6 STM8S005K6 Product overview 4 8 4 9 4 10 4 11 Independent watchdog timer The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures It is clocked by the 128 kHz LSI internal RC clock source and thus stays active even in case of a CPU clock failure The IWDG time base spans from 60 us to 1 s Auto wakeup counter e Used for auto wakeup from active halt mode e Clock source Internal 128 kHz internal low frequency RC oscillator or external clock e LSI cloc
79. offers new advanced debugging capabilities including profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application In addition STice offers in circuit debugging and programming of STM8 microcontrollers via the STM8 single wire interface module SWIM which allows non intrusive debugging of an application while it runs on the target microcontroller For improved cost effectiveness STice is based on a modular design that allows users to order exactly what they need to meet their development requirements and to adapt their emulation system to support existing and future ST microcontrollers STice key features e Occurrence and time profiling and code coverage new features e Advanced breakpoints with up to 4 levels of conditions e Data breakpoints e Program and data trace recording up to 128 KB records HRead write on the fly of memory during emulation e In circuit debugging programming via SWIM protocol e 8 bit probe analyzer e 1 input 2 output triggers e Power supply follower managing application voltages between 1 62 to 5 5 V e Modularity that allows users to specify the components users need to meet their development requirements and adapt to future requirements e Supported by free software tools that include integrated development environment IDE programming software interface and assembler for STM8 022186 Rev 4 STM8S
80. og supply 5 3 5 5 V Positive reference voltage 2750 V Negative reference voltage 5 Vssa 0 50 V B Vssa V Vain Conversion voltage range external Vn V Vrer Vrer pins Internal sample and hold Canc capacitor 5 fapc 4 MHz 0 75 ts Sampling time us fapc 6 MHz 0 5 tstag Wakeup time from standby 7 fADC 4 MHz 3 5 uS Total conversion time including E conv sampling time 10 bit resolution lago 6 MHz 283 BT 14 l fApc 1 Data guaranteed by design not tested in production 2 During the sample time the input capacitance pF max can be charged discharged by the external Source The internal resistance of the analog source must allow the capacitance to reach its final voltage level within ts After the end of the sample time ts changes of the analog input voltage have no effect on the conversion result Values for the sample clock tg depend on programming DoclD022186 Rev 4 79 97 Electrical characteristics STM8S005C6 STM8S005K6 Table 44 ADC accuracy with Ramn lt 10 5 V Symbol Parameter Conditions Typ Max Unit fApc 2 MHz 1 0 2 5 Total unadjusted error 2 4 MHz 1 4 3 6 MHz 1 6 3 5 2 MHz 0 6 2 0 Offset error 2 fApc 4 MHz 1 1 2 5
81. ons e Maximum ambient temperature Tamax 82 C measured according to JESD51 2 e IpDmax 15 mA Vpp 5 5V e Maximum eight standard I Os used at the same time in output at low level with Io 10 mA 2 V e Maximum four high sink I Os used at same time in output low level with Io 20 mA 2 1 5 V e Maximum two true open drain I Os used at the same time in output at low level with lot 20 mA VoL 2V Pintmax 15 mA x 5 5 V 82 5 mW Piomax 10 x 2 V x8 20 mA x 2 V x2 20 mA x 1 5 V x 4 360 mW This gives Pintmax 82 5 mW 360 mW Ppmax 82 5 mW 360 mW Thus Ppmax 443 mW Using the values obtained in Table 52 Thermal characteristics on page 91 T is calculated as follows for LQFP64 10 x 10 mm 46 C W TJmax 82 C 46 C W x 443 mW 82 20 102 C This is within the range of the suffix 6 version parts 40 lt Ty lt 105 In this case parts must be ordered at least with the temperature range suffix 6 DoclD022186 Rev 4 STM8S005C6 STM8S005K6 Part numbering 11 Part numbering Figure 50 STM8S005C6 K6 value line ordering information scheme Example Product class STM8 5 8 microcontroller Family type S S standard Sub family type 005 C 005 peripheral set Pin count K 32 pins C 48 pins Program memory size 6 6 32 Kbytes
82. otal current consumption in active halt mode Table 23 Total current consumption in active halt mode at Vpp 5 V TA 40 to 85 C Conditions Symbol Parameter Mainvoltage Typ Max Unit regulator Flash mode Clock source 2 HSE crystal oscillator 16 MHz 1989 Operating mode SIS j oscillator 128 kHz 299 m HSE oscill Supply current in crystal oscillator 4030 IDD H active halt mode 16 MHz HA Power down mode ETE i oscillator 128 kHz 140 218 Operating mode RC oscillator 68 120 on 128 kH Power down mode 128 kHz 12 60 1 Data based on characterization results not tested in production 2 Configured by the REGAH bit in the CLK_ICKR register 3 Configured by the AHALT bit in the FLASH_CR1 register Table 24 Total current consumption in active halt mode at Vpp 3 3 V Conditions Max Symbol Parameter Main voltage Typ 2 C Unit regulator Flash mode Clock source 1 MVR HSE crystal osc 16 MHz 680 Operating mode LSI RC osc 128 kHz 200 320 n Supply current HSE crystal osc 16 MHz 630 in active halt Power down mode mode LSI RC osc 128 kHz 140 270 Operating mode 66 120 Off k LSI osc 128 kHz Power down mode 10 60 1 Data based on characterization results not tested in production 2 Configured by the REGAH bit in the CLK_ICKR register 3 Configured
83. p wri VS Vpp HSE user external clock Vpp 5 V lIppwrouse mA 0 5 10 15 20 25 30 fcpu MHz MS37497V1 DoclD022186 Rev 4 STM8S005C6 STM8S005K6 Electrical characteristics Figure 15 VS HSI RC osc 16 MHz mA MS37492V1 lpotwryasi MA MS37493V1 DoclD022186 Rev 4 57 97 Electrical characteristics STM8S005C6 STM8S005K6 9 3 3 External clock sources and timing characteristics HSE user external clock Subject to general operating conditions for Vpp and T Table 30 HSE user external clock characteristics Symbol Parameter Conditions Min Typ Max Unit ead clock source 0 _ 16 MHz 14542 5 input pin high level 0 7 x Vpp Vpp 0 3 V Vase t ae input pin low level Vss _ 0 3 x Vpp Vss lt Vin 5 1 1 Data based on characterization results not tested in production Figure 17 HSE external clock source 4 2 gt fuse External clock source OSCIN mI STM8 HSE crystal ceramic resonator oscillator The HSE clock can be supplied with a 1 to 24 MHz crystal ceramic resonator oscillator All the information given in this paragraph is based on characterization results with specified typical e
84. pin This test conforms to the JESD22 A114A A115A standard For more details refer to the application note AN1181 Table 48 ESD absolute maximum ratings Symbol Ratings Conditions Class Unit Electrostatic discharge voltage TA 25 conforming to VESD HBM Human body model JESD22 A114 4 2089 4123 Electrostatic discharge voltage Ta 25 C conforming to VESD CDM Charge device model JESD22 C101 1000 1 Data based on characterization results not tested in production DoclD022186 Rev 4 83 97 Electrical characteristics STM8S005C6 STM8S005K6 84 97 Static latch up Two complementary static tests are required on 10 parts to assess the latch up performance e Asupply overvoltage applied to each power supply pin e A current injection applied to each input output and configurable I O pin is performed on each sample This test conforms to the EIA JESD 78 IC latch up standard For more details refer to the application note AN1181 Table 49 Electrical sensitivities Symbol Parameter Conditions Class TA 25 A LU Static latch up class 85 1 Class description A Class is an STMicroelectronics internal specification All its limits are higher than the JEDEC specifications that means when a device belongs to class A it exceeds the JEDEC standard B class strictly covers all the JEDEC criteria international standard Do
85. re registers only in halt mode Guaranteed by design not tested in production 2 Refer to Table 18 on page 47 for the value of Vir may Flash program memory data EEPROM memory General conditions T4 40 to 85 C Table 35 Flash program memory data EEPROM memory Symbol Parameter Conditions Min Typ Max Unit Operating voltage _ all modes execution write erase fopu lt 16 2 295 um i Standard programming time including erase for byte word block 6 0 6 6 ms iiis 1 byte 4 bytes 128 bytes Fast programming time for 1 block _ 128 bytes 89 2888 terase Erase time for 1 block 128 bytes 30 33 ms Erase write cycles 100 program memory Nnw 85 C cycles Erase write cycles took _ Data retention program memory after 100 erase write cycles at 20 Ta 85 55 C Data retention data memory after 20 years 10 k erase write cycles at 85 C Data retention data memory after 100 erase write cycles at TA 85 C Teer 18 Supply current Flash programming or 20 _ mA DD erasing for 1 to 128 bytes 1 Data based on characterization results not tested in production 2 The physical granularity of the memory is 4 bytes so cycling is performed on 4 bytes even when a write erase operation addresses a single byte DoclD02
86. recommended footprint FP V2 1 Dimensions are expressed in millimeters DoclD022186 Rev 4 89 97 Package information STM8S005C6 STM8S005K6 90 97 Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location Figure 49 LQFP32 marking example package top view Product 0 identification 5 M S 0 0 Date code Standard ST logo Y Y Pin 1 identifier Revision code MS37717V1 1 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity DoclD022186 Rev 4 STM8S005C6 STM8S005K6 Package information 10 3 10 3 1 Thermal characteristics The maximum chip junction temperature must never exceed the values given Table 17 General operating conditions The maximum chip junction temperature in degrees Celsius may be calculated using the following equation X Oga is the maximum ambient temperature C
87. run mode Flash in power down mode 9 54 1 Data guaranteed by design not tested in production 2 twuwe 2 X Waster 7 X 3 Measured from interrupt event to interrupt vector fetch 4 Configured by the REGAH bit in the CLK ICKR register 5 Configured by the AHALT bit in the FLASH register 6 Plus 1 LSI clock depending on synchronization Ly 00 10022186 Rev 4 53 97 Electrical characteristics 5 85005 6 STM8S005K6 Total current consumption and timing in forced reset state Table 28 Total current consumption and timing in forced reset state Symbol Parameter Conditions Typ Max Unit Ipp R Supply current in reset state 2 Vpp 3 3 V 400 release to bootloader vector 150 etch 1 Data guaranteed by design not tested in production 2 Characterized with all I Os tied to Vss Current consumption of on chip peripherals Subject to general operating conditions for and T HSI internal RC fcpy fuAsrER 16 MHz Table 29 Peripheral current consumption Symbol Parameter Typ Unit Ibom TIM1 supply current 0 230 TIM2 supply current 0 115 timer supply current 0 90 4 TIM4 timer supply current 0 30 UART2 supply current 2 110 Ippsey SPI supply current 0 45 20 2 supply current 2 65 Ipp apct
88. rved area 11 bytes 0x00 5320 TIMS control register 1 0x00 0x00 5321 IER TIMS interrupt enable register 0x00 0x00 5322 TIM3_SR1 TIMS status register 1 0x00 0x00 5323 TIM3_SR2 TIMS status register 2 0x00 0x00 5324 TIM3_EGR TIM3 event generation register 0x00 0x00 5325 TIM3 TIM3_CCMR1 capture compare mode register 1 0x00 0x00 5326 TIM3_CCMR2 TIMS capture compare mode register 2 0x00 0x00 5327 TIM3_CCER1 capture compare enable register 1 0x00 0x00 5328 TIM3_CNTRH TIMS counter high 0x00 0x00 5329 TIM3_CNTRL TIM3 counter low 0x00 0x00 532A TIM3_PSCR prescaler register 0x00 Ky DoclD022186 Rev 4 33 97 Memory and register map STM8S005C6 STM8S005K6 Table 8 General hardware register map continued Address Block Register label Register name uid 0x00 532B TIM3_ARRH TIMS auto reload register high OxFF 0x00 532C TIM3 ARRL TIMS auto reload register low OxFF 0x00 532D TIG TIM3 CCR1H TIMS capture compare register 1 high 0x00 0x00 532bE CCR1L TIMS capture compare register 1 low 0x00 0x00 532F TIM3 CCR2H TIMS capture compare register 2 high 0x00 0x00 5330 TIM3 CCR2L TIM3 capture compare register 2 low 0x00 E Reserved area 15 bytes 0x00 5340 TIM4_CR1 TIM4 control register 1 0x00 0x00 5341 4
89. rview 4 2 4 3 4 4 Single wire interface module SWIM and debug module DM The single wire interface module and debug module permits non intrusive real time in circuit debugging and fast memory programming SWIM Single wire interface module for direct access to the debug module and memory programming The interface can be activated in all device operation modes The maximum data transmission speed is 145 bytes ms Debug module The non intrusive debugging module features a performance close to a full featured emulator Beside memory and peripherals also CPU operation can be monitored in real time by means of shadow registers e R W to RAM and peripheral registers in real time e R W access to all resources by stalling the CPU e Breakpoints on program memory instructions software breakpoints e Two advanced breakpoints 23 predefined configurations Interrupt controller e Nested interrupts with three software priority levels e 32 interrupt vectors with hardware priority e Up to 33 external interrupts on six vectors including TLI e Trap and reset interrupts Flash program and data EEPROM memory e 32 Kbytes of high density Flash program single voltage Flash memory e 128 bytes true data EEPROM e Read while write Writing in data memory possible while executing code in program memory e User option byte area Write protection WP Write protection of Flash program memory and data EEPROM is provid
90. s shown in Table 11 Option bytes below Option bytes can also be modified on the fly by the application in IAP mode except the ROP option that can only be modified in ICP mode via SWIM Refer to the STM8S Flash programming manual PM0051 and STM8 SWIM communication protocol and debug module user manual UM0470 for information on SWIM programming procedures Table 11 Option bytes Option bits Factory Option Option Addr B E ith default Meu 6 5 4 3 2 1 0 setting Read out 4800h protection OPTO ROP 7 0 00h ROP 4801h User boot code OPT UBC 7 0 00h UBC NUBC 7 0 FFh 4803h OPT2 AFR7 AFR6 5 ic AFR3 AFR2 AFRO 00h remapping 4804h AFR NOPT2 NAFR7 NAFR6 NAFR5 NAFR4 NAFR3 NAFR2 NAFR1 NAFRO FFh 4805h OPT3 Reserved HSITRIM TEN MN na ps 00h Miscellaneous option NHSI NLSI NIWDG NWWDG NWWDG 4806h Reserved TRIM HW HW HALT FFh EXT CKAWU PRS PRS 4807h OPT4 Reserved CLK SEL C1 CO 00h Clock option NEXT NCKAW NPR NPR 4808h NOPT4 Reserved CLK USEL SC1 SCO FFh 4809h HSE clock OPT5 HSECNT 7 0 00h 480An Startup NOPT5 NHSECNT 7 0 FFh 480Bh OPT6 Reserved 00h I Reserved 480Ch NOPT6 Reserved FFh 480Dh Flash wait OPT7 Reserved 00h 480En States NOPT7 Reserved FFh 487Eh OPTBL BL 7 0 00h Bootloader 487Fh NOPTBL NBL 7 0 F
91. ster map Table 8 General hardware register map Address Block Register label Register name E Reserved area 10 bytes 0x00 505A FLASH Flash control register 1 0x00 0x00 505B FLASH CR2 Flash control register 2 0x00 0x00 505C FLASH NCR2 Flash complementary control register 2 OxFF 0x00 505D Flash FLASH FPR Flash protection register 0x00 0x00 505E FLASH NFPR Flash complementary protection register OxFF 0x00 505F FLASH IAPSR Flash status 0x00 Reserved area 2 bytes 0x00 5062 Flash FLASH PUKR Flash 0x00 0x00 5063 Reserved area 1 byte 0x00 5064 Flash FLASH _DUKR Data EEPROM unprotection register 0x00 CE Reserved area 59 bytes 0x00 50A0 External interrupt control register 1 0x00 0x00 50A1 s EXTI CR2 External interrupt control register 2 0x00 SEE Reserved area 17 bytes 0x00 50B3 RST RST SR Reset status register Oxxx EE Reserved area 12 bytes 0x00 50C0 CLK ICKR Internal clock control register 0x01 0x00 50C1 CLK ECKR External clock control register 0x00 0x00 50C2 Reserved area 1 byte 0x00 50C3 CLK CMSR Clock master status register OxE1 0x00 50C4 CLK SWR Clock master switch register OxE1 0x00 50C5 CLK SWCR Clock switch control register OxXX 0x00 50C6 CLK CKDIVR Clock divider register 0x18 0x00 50C7
92. ter map continued Address Block Register label Register name 0x00 5300 TIM2 CR1 TIM2 control register 1 0x00 0x00 5301 TIM2 IER TIM2 interrupt enable register 0x00 0x00 5302 TIM2 SR1 TIMe status register 1 0x00 0x00 5303 TIM2 SR2 TIMe status register 2 0x00 0x00 5304 TIM2 EGR TIM2 event generation register 0x00 0x00 5305 TIM2 CCMR1 TIM2 capture compare mode register 1 0x00 0x00 5306 TIM2 CCMR2 TIM2 capture compare mode register 2 0x00 0x00 5307 TIM2 CCMR3 TIM2 capture compare mode register 3 0x00 0x00 5308 TIM2 CCER1 TIM2 capture compare enable register 1 0x00 0x00 5309 TIM2 CCER2 TIM2 capture compare enable register 2 0x00 0x00 530A TIM2 TIM2 CNTRH TIM2 counter high 0x00 0x00 530B TIM2 CNTRL TIM2 counter low 0x00 00 530 0 TIM2_PSCR TIM2 prescaler register 0x00 0x00 530D TIM2_ARRH TIM2 auto reload register high OxFF 0x00 530E TIM2 ARRL TIM2 auto reload register low OxFF 0x00 530F TIM2 CCR1H TIM2 capture compare register 1 high 0x00 0x00 5310 TIM2 CCR1L TIM2 capture compare register 1 low 0x00 0x00 5311 TIM2 CCR2H TIM2 capture compare reg 2 high 0x00 0x00 5312 TIM2 CCR2L TIM2 capture compare register 2 low 0x00 0x00 5313 TIM2_CCR3H TIM2 capture compare register 3 high 0x00 0x00 5314 TIM2 CCR3L TIM2 capture compare register 3 low 0x00 Rese
93. uarantees glitch free switching e Clock management To reduce power consumption the clock controller can stop the clock to the core individual peripherals or memory e Master clock sources Four different clock sources can be used to drive the master clock 1 16 MHz high speed external crystal HSE Up to 16 MHz high speed user external clock HSE user ext 16 MHz high speed internal RC oscillator HSI 128 kHz low speed internal RC LSI e Startup clock After reset the microcontroller restarts by default with an internal 2 MHz clock HSI 8 The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts e Clock security system CSS This feature can be enabled by software If an HSE clock failure occurs the internal RC 16 MHz 8 is automatically selected by the CSS and an interrupt can optionally be generated e Configurable main clock output CCO This outputs an external clock for use by the application Table 2 Peripheral clock gating bit assignments in CLK PCKENR1 2 registers Bit Peripheral Bit Peripheral Bit Peripheral Bit Peripheral clock clock clock clock PCKEN17 TIM1 PCKEN13 UART2 PCKEN27 Reserved PCKEN23 ADC PCKEN16 TIM3 PCKEN12 Reserved PCKEN26 Reserved PCKEN22 AWU PCKEN15 TIM2 11 SPI PCKEN25 Reserved 21 Reserved PCKEN14 TIM4 PCKEN10 PCKEN24 Reserved
94. ues in inches are converted from mm rounded to 4 decimal digits DoclD022186 Rev 4 Ky STM8S005C6 STM8S005K6 Package information Figure 45 LQFP48 48 pin 7 x 7 mm low profile quad recommended footprint 0 50 1 20 36 25 0 30 p C37 240 7 Y co d 020 2 E 7 7 5 80 4 Yas 1 12 1 20 580 gt 9 70 gt ai14911d 1 Dimensions are expressed in millimeters Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location Figure 46 LQFP48 marking example package top view Product Standard ST logo Pin 1 identifier identification N T M N 0 0 5 Date code Revision code MS37716V1 1 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity 022186 Rev 4 87 97 Package information STM8S005C6 STM8S005K6 10 2 88 97 LQFP32 package information Figure 47 LOFP32
95. xternal components In the application the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start up stabilization time Refer to the crystal resonator manufacturer for more details frequency package accuracy 58 97 DoclD022186 Rev 4 STM8S005C6 STM8S005K6 Electrical characteristics Table 31 HSE oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit in External high speed oscillator _ 1 16 MHz frequency Rr Feedback resistor 5 220 Recommended load capacitance 2 20 C 20 pF 6 startup 16 MHz 1 6 stabilized 9 HSE oscillator power consumption mA C 10 pF 6 fosc 16 MHz 1 2 stabilized 9 Om Oscillator transconductance 5 Startup time Vpp is stabilized ms 1 Cis approximately equivalent to 2 x crystal Cload 2 The oscillator selection can be optimized in terms of supply current using a high quality resonator with small Rm value Refer to crystal manufacturer for more details 3 Data based on characterization results not tested in production tsu usE is the start up time measured from the moment it is enabled by software to a stabilized 24 MHz oscillation is reached This value is measured for a standard crystal resonator and it can vary signif
96. zation are performed at component level with a typical application environment and simplified MCU software It should be noted that good EMC performance is highly dependent on the user application and the software in particular Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application Software recommendations The software flowchart must include the management of runaway conditions such as e Corrupted program counter e Unexpected reset e Critical data corruption control registers Prequalification trials Most of the common failures unexpected reset and program counter corruption can be recovered by applying a low state on the NRST pin or the oscillator pins for 1 second To complete these trials ESD stress can be applied directly on the device over the range of specification values When unexpected behavior is detected the software can be hardened to prevent unrecoverable errors occurring see application note AN1015 Table 46 EMS data Symbol Parameter Conditions Level class Voltage limits to be applied on any I O pin to 5 V 25 VrEsD fuAsrER 16 MHz 280 induce a functional disturbance conforming to IEC 61000 4 2 Fast transient voltage burst limits to be 5 V 25 applied through 100pF Vpp and pins fyaster 16 MHz t

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