FPGADEVS6 FPGA Development Kit User`s Manual
Contents
1. note 6 1 odd even pin numbers swapped 4 Not used 8MHz clock input 4 NET CLOCK LOC P123 LEDs on the FPGA board Active Hi 1 0 NET LED1 LOC P117 NE LED2 LOC P116 NE LED3 LOC P115 NE LED4 LOC P114 LEDs on the I O board Active 1 0 NE LEDX8 LOC P47 NE LEDX7 LOC P48 NE LEDX6 LOC P45 NE LEDX5 LOC P46 NE LEDX4 LOC P43 NE LEDX3 LOC P44 NET LEDX2 LOC P40 NET LEDX1 LOC P41 7 segment display drive Active Low 0 1 OFF NE sega LOC P102 NE segb LOC P105 NE segc LOC P101 NE segd LOC P97 NE sege LOC P98 NE segf LOC P100 NE segg LOC P104 NE segdp LOC P99 7 segment display digit colon drive Active Low 0 1 OFF NET DIG1 LOC P92 NET DIG2 LOC P93 NE i23 LOC P87 COLON NE DIG3 LOC P84 NE DIGA LOC P88 Pushbutton switches 51 4 When Depressed 0 NE PBS4 LOC P80 NE PBS3 LOC P81 NE PBS2 LOC P78 NE PBS1 LOC P79 8 position slide switch S5 ON 0 OFF 1 NE 95 LOC P55 NE LOC P56 NE S5 3 LOC P57 NE S5 4 LOC P58 NE 5345 LOC 61 95 26 LOC P62 LOC P66 NE S5 8 LOC 67 FPGADEVS6 Page 30 User s Manual Appendix A Board Dimensions Connector Locations 3 000 2 800 FPGADEVS62. GPIO connector P6 Banks 1 amp 2 P8 Power and USB to PC Insert USB Thumb drive here P8 provides power to the board using a powered USB port on a PC or a separate USB power supply As soon as powert is applied the FPGA will be loaded with the file that is stored in the non volatile configuration PROM the Done LED lights and the FPGA runs To reprogram the configuration serial PROM using an external USB thumb drive 1 Use ISE to create and place the desired fpga mcs configuration file in the root of a FAT formatted USB flash thumb drive The fpga mcs file must be created for a single Spartan 6 FPGA part number XC6SLX9 2 in the TQG144 package and a 4M bit SPI PROM type M25P40 2 With power to the board disconnected plug the USB flash drive into USB connector P9 and apply power The USB drive acrtivity light flashes as the USB microcontroller reads the fpga mcs file from the thumb drive and programs the SPI configuration PROM This will take less than a minute and when complete the activity LED on the thumb drive will stop flashing then D5 the Done LED will light up and the new FPGA configuration will begin running 3 Once programming is complete remove the USB drive and the FPGA will be configured from the serial PROM will be used on subsequent power cycles This process takes longer than loading the bit file to the FPGA from JTAG For more details and programming using a JTAG cable see the follo
3. Page A a 2 800 3 000 19 S i 3 3UAUX E U2 2 9 S 26 YN2 1 4 User s Manual 0 300 Appendix B Summary of Specifications The development board specs are standard Xilinx Spartan 6 XC6SL X9 FPGA in 144 pin TQFP package 9 152 logic cell equivalents Thirty two 18K bit block RAMSs 576K bits Sixteen DSP48A Slices Two Digital Clock Managers DCMs Up to 102 user defined I O signals 4Mbit Serial SPI EEPROM for in system configuration PROM JTAG port for low cost download cable Dual USB Controller FTDI VNC2 32 USB 2 0 operation defined by VNC2 Specs Type A USB Connector for flash drive Type Mini B USB Connector for power and PC communication 8 MHz Local Oscillator Two 50 Pin Expansion I O Connectors with 84 Pre Assigned I O Pins 4 On board LEDs On Board Power Supply using National LP3906 Quad Regulator 3 3 1 5 Operating Voltage 1 2 Q 1 5 FPGA Core Voltage 3 3 300 mA FPGA Auxillary Voltage 1 8 300 mA Secondary I O Operating Voltage Note Above load peaks apply only for an external 5V power supply USB power is typically limited to 500 5V z 2 5W max specifications are subject to change FPGADEVS6 Page B User s Manual Appendix C Schematic and Bill of Materials See separate schematic and BOM PDF files available at http www hte com dev FPGADEVS6
4. directly or indirectly by this product including but not limited to any interruption of service loss of business or anticipatory profits or consequential damage resulting from the use or operation of this product This device is not intended for use in life support or life critical equipment Essentially if you do something stupid don t blame us you re on your own HTE reserves the right to make changes to any and all part of this product at any time without obligation to notify any person or entity of such changes and does not represent a commitment on the part of HTE So there On the other hand we will consider any reasonable request from any reasonable customer i e not from a lawyer attorney barrister or solicitor associates their employees contractors legal consultants or their ilk and we will often go far out of our way to assist in any way we can Warranty Registration Please take a moment to e mail your contact info to registration hte com This will assure prompt service in the unlikely event a problem occurs If your company insists on ISO900X certification please be aware that this only means that we will follow our documented procedures no matter how foolish they may seem Just so you know our first documented standard procedure following a customer request for ISO 900X certification is to laugh in your face and double the price Trademarks HTE is a trademark of HTE Xilinx Spartan and ISE are trademarks of Xi
5. 3 3V Default 1 0 2 Vin Variable 3 Mode P5 1 to P5 2 Master Closed Default Slave Open Status LED D5 FPGA Configured ON FPGA Not Configured OFF Page 24 User s Manual Board Layout St 3UAUXT w gt D R Component Locations and I O Pins FPGADEVS6 25 User s Manual Using FPGA with the switch LED user Board The FPGA board may be used with the general purpose switch LED user I O board when connected as shown below The two boards are designed to mate horizontally as shown or if ordered with custom connectors they can be stacked so that the user I O board stacks on top of the FPGA board Connector P1 on user Four digit 7 segment board mates to common anode LED P6 on FPGA board display with DP amp colon 83787852 13322233 p gt Ril 5 7 T si 82 3 54 e 1222 1 5321638 940 0 gt gt F gt 4 pushbutton switches 123456 8 discrete LEDs Power applied through USB cable here P10 JTAG Pinout 8 slide switches Color Signal Pin Red Vcc 1 Gnd 2 Grn 3 Orn 4 TDI 5 TMS 6 FPGADEVS6 Page 27 User s Manual Switch LED user Board Connector Pin Assignments Note that these pins are for the connector on the board and if the board 15 connected usin
6. Page C User s Manual Appendix D Development Board Jumpers Jumper Pins Name Shorted Function 12 225 2 Select I O voltage for I O banks 1 amp 2 P6 P2 T2 Select I O voltage for I O banks 0 amp 3 on P7 5 1 2 Master Mode jumper In Master by default 5V 5VDC Power GND Gnd Return for 5V power Note Asterisk means the default jumper is a trace on the the board Normally the jumpers are not installed The traces can be cut by the user or by special order at the factory prior to being shipped so 0 1 jumper pins and plugs can be installed FPGADEVS6 Page D User s Manual Appendix MCS File Format The mcs file is generated using Xilinx ISE in the Implementation pane on the Deisgn Tab process Generate Target PROM to create the file By default the board will load a file named fpga sys from the root directory of a FAT formatted USB flash drive installed at power up The file format is described below The mcs Intel hex data file formats begin with a 9 character prefix and end with a 2 character suffix The byte count must be equal to the number of data bytes in the record Data record and end of file record are the two types of records The number of bytes per record is variable Each record begins with a colon which is followed by a 2 character byte count The 4 characters following the byte count is the address of the first data byte Each byte is represented by 2 hex digits that equals to the number
7. SWITCH LED USER I O BOARD CONNECTOR PIN ASSIGNMENTS 28 APPENDIX A BOARD DIMENSIONS CONNECTOR LOCATIONS 0 A APPENDIX B SUMMARY OF SPECIFICATIONS cerne eee ee eee eee eo oeste toos eet esee ena B APPENDIX C SCHEMATIC AND BILL OF MATERIALS eee ee eee en eee toes C APPENDIX D DEVELOPMENT BOARD JUMPERS eere ee ee tn eee ease teens een D APPENDIX E MCS EILE FORMAT E APPENDIX TROUBLESHOOT ING e eee ee eee enne seta ene seen aee seen eese F APPENDIX OEM BOARD VERSION 8 41 4 400 112221 41 1 4 7 1 4 44424 4 4 4 02 440044 enne seen G APPENDIX USING THE OEM VERSION OF THE SBOC eere eene eee seen ee ee enne sete tnos etta H M H APPENDIX I USEFUL WEB SITES eee eet esee eo Paro eaa ro oe et Fan e ao e pa aae eR 0d I APPENDIX J OPTIONAL USER I O BOARD LAYOUT e eere ee etn sesta J APPENDIX PROBLEM REPORT AND COMMENT 1 1 1 1 1 K FPGADEVS6 Page 5 User s Manual FPGADEVS6 Page 6 User s Manual FPGA Board with optional User 1
8. and the FPGA loads a valid configuration file from the EEPROM the Done LED D5 will light up 3 Connect your JTAG programming cable to connector P10 At this point you can use impact chipscope and other Xilinx ISE tools to program and debug the FPGA or to program the configuration EEPROM 05 In ISE FPGA Properties must be as shown below for the standard version of the board with a Spartan 6 FPGA part number 651 9 2 in the TQG144 package Location The configuration for LX4 OEM version of board is the same as above except for the Device part number FPGADEVS6 Page 16 User s Manual Sample UCF File NET CLOCK LOC P123 NET LED1 LOC P117 NET LED2 LOC P116 NET LED3 LOC P115 NET LED4 LOC P114 Below Signals on the opt f boards are mated to with UCF file for FPGA P6 right angle to DevIO P1 note P6 P1 odd even pin numbers swapped Not used 8MHz clock input LEDs on the FPGA board Active Hi 1 ON 0 ional User I O Board when right angle connectors LEDs on the I O board Active 1 0 NE LEDX8 LOC P47 NE LEDX7 LOC P48 NE LEDX6 LOC P45 NE LEDX5 LOC P46 NE LEDX4 LOC P43 NE LEDX3 LOC P44 NET LEDX2 LOC P
9. grounded conductive workstations and standard ESD precautions should be used whenever possible when handling the board to prevent device damage FPGADEVS6 Page 11 User s Manual e sea 51 E P 3 3URUXfS U2 D D R FPGADEVS6 Page 12 User s Manual Operating Development Board A typical configuration for debugging development purposes would include e USB A to mini B cable or USB Power source Xilinx ISE Web Pack Development System USB Connections There are two USB connectors 1 P8 is the USB miniB connector which supplies power and can also be used to communicate with a host PC subject to appropriate the firmware in the USB microcontroller 2 P9 15 a USB type A connector which will accommodate USB thumb drive The standard firmware shipped with the unit will read the thumb drive on pwer up and if a file named fpga sys is present in the root directory it will be programmed into the SPI configuration PROM on the board JTAG Connection The JTAG connector P10 allows programming the FPGA or SPI configuration PROM using a compatible JT AG cable such as the Xilinx Platform USB cable FTDI USB Microcontroller Programming Connection P11 is the USB microcontroller chip programming and debug connector this connector can be connected to the FTDI VNC2 Debug Module which is a PC board a little larger than a USB type A connector that allows development debug and pro
10. the problem how to reproduce it and your suggested correction decscribe documention problems suggest enhancements that you would like to see added to this product E mail or fax form to HTE Attn Technical Support 800 748 9172 Fax 800 409 9172 http www hte com Or e mail techsupport hte com FPGADEVS6 Page K User s Manual
11. 2 and 3NI2 to indicate that the pins are connected to bank 3 pair 12 where 3P12 is the positive signal pin and 3N12 is the negative pin of the pair This facilitates the use of adjacent differential wire pairs if a ribbon cable is connected to the 50 pin connector for moderately high speed differential signalling Some FPGA and uC I O pins are not connected or used internally on the board so they are not available on the external user I O connectors The I O pin banks of the FPGA are connected to 3 3V by default however the board can be reconfigured to use a different power supply voltage for the 50 pin connections A jumper can be changed to select either the main 3 3V supply or the auxiliary power supply The voltage for the banks on either 50 pin connector can be configured independently The auxiliary supply can be used to operate the FPGA s I O banks at any voltage between 1 2 and 3 3 volts based on the power supply voltage input on the VAR pins of and P7 The may also be supplied by the board s 1 8V supply by connecting the 1 8V pin to the VARO or VARI signal on P2 P6 or P7 This allows for the use of different logic voltage interface levels on connectors P6 and P7 Please Note This board has CMOS devices which can be damaged if exposed to electrostatic fields and discharges The metallized plastic electrostatic shielding bag provided with the board should be used to protect the board during transport and
12. 40 NET LEDX1 LOC P41 7 segment display drive Active Low 0 1 20FF NET sega LOC P102 NE segb LOC P105 NE segc LOC P101 NE segd LOC P97 NE sege LOC P98 NE segf LOC P100 NE segg LOC P104 NET segdp LOC P99 7 segment display digit colon drive Active Low 0 1 OFF DIGI LOC P92 left most digit NE DIG2 LOC P93 NE L123 LOC P87 COLON NE DIG3 LOC P84 NE DIG4 LOC P88 right most digit Pushbutton switches 51 4 When Depressed 0 NE PBS4 LOC P80 PULLUP NE PBS3 LOC 81 PULLUP NE PBS2 LOC P78 PULLUP NE PBS1 LOC P79 PULLUP 8 position slide switch 55 ON 0 OFF 1 So LOC P55 PULLUP NE s5 2 LOC P56 PULLUP NE S5 LOC P57 PULLUP NE 5 24 58 PULLUP NE M OO LOC P61 PULLUP NE 155 6 LOC 62 PULLUP NE So LOC P66 PULLUP NE S5 8 LOC P67 PULLUP FPGADEVS6 Page 17 User s Manual Example The LED version of Hello World The following program is a very simple example intended to show how a VHDL program can be written to run on this board It blinks the four on board LEDs D1 4 and places walking ones on the connector I O pins Create Date 01 13 07 08 06 2009 Design Name Modu
13. 5 15 19 IO Bank3 N5 14 20 IO Bank3 12 21 IO Bank3 11 22 Bank3 10 23 IO Bank3 N3 9 24 GND 25 GND 26 Bank3 P2 8 27 IO Bank3 N2 7 28 IO Bank3 6 29 IO Bank3 N1 5 30 Bank3 2 31 IO Bank3 NO 1 32 P7 142 33 IO N7 141 34 lO 140 35 IO N6 139 36 lO P5 138 37 IO N5 137 38 lO 134 39 IO 4 133 40 132 41 IO N3 131 42 lO P2 127 43 IO N2 126 44 121 45 IO 120 46 119 47 IO NO 118 48 GND 49 GND 50 Page 22 User s Manual P8 USB Type P9 USB Type A USB Signal P8 Pin 5 Input D D GND c 1 02 nm USB Signal P9 Pin 5V Output P10 JTAG Programming Header FPGADEVS6 JTAG Signal P10 Pin 3 3V Output GND TCK TDO TDI TMS 23 User s Manual Bank 1 2 Operating Voltage Configuration P1 Bank 0 and 3 Operating Voltage Configuration P2 FPGA Mode Configuration P5 Configuration LED D5 FPGADEVS6 Voltages P1 Pin 3 3V Default 1 VCCO_1 2 Vin_ Variable 3 Voltages P2 Pin
14. 9 The configuration options and jumpers that can be added include e Jumpers plugs P2 P5 e Customer Specified I O power e USB VNC2 microcontroller programming debug connector P11 FPGADEVS6 Page G User s Manual Appendix Using OEM version of the SBC Essentially the OEM Original Equipment Manufacturer versions of the board is a minimum configuration version of the Development Board The OEM version is typically a lower cost unit as it does not have the components which are only needed for development of programs It does not have the following items that are included on the development board 50 Pin I O Connector P6 50 Pin I O Connector P7 Connector P8 Connector P9 The FTDI USB IC and crystal The OEM jumper connections are supplied with jumper pins in the default settings by default SUN eol c Note that the OEM board may be ordered with some or all of the above and other custom configurations Contact HTE for more information Once development has been completed on the Development Board the FPGA configuration must be programmed into the SPI serial configuration EEPROM typically using the JTAG connector Optionally the USB thumb drive programming can also be specified at time of order Power can be provided by the external connections at the top left corner of the board using the pins labeled 5V and GND The following is the pinout for the power connector at the top left corner of the board Pin De
15. Board Lu LU EE Rii 913 RIS 817 19 1 2 3 4 o jo jo jlo ADEOSS 321638 9294 0 HH 22232832 12322233 60 EEEEEEEEEEEEEEFEHEG Introduction If you re anxious to start using the board you can skip ahead to the Getting Started section right now See pages 13 and 14 For those select few people who actually read the instructions first the rest of this manual provides a detailed description of the board This manual has been written for the reader who is familiar with digital logic systems specific knowledge of the Xilinx FPGA family is not assumed but it would be advisable for anyone not familiar with this family to obtain and read the relevent documents from the IC manufacturers A large number of useful documents and sample programs are available from many different web sites listed on the HTE web site The term Development Board or Board is used throughout this manual for the FPGA development board The term FPGA is used throughout this manual to represent the Spartan 6 family from Xilinx The abbreviation uC refers to the FTDI USB microcontroller on the board The terms EE or SPI PROM are used to refer to the SPI serial interface EEPROM Features Operates as a stand alone FPGA board Incorporate
16. FPGADEVS6 FPGA Development Kit User s Manual g 21 LE 2 Rev 12 03 www hte com dev 800 748 9172 Int l 1 858 679 1569 Fax 800 409 9172 www hte com dev 4info hte com FPGADEVS6 FPGA Development Kit User s Manual Manual Revision 12 03 March 2012 hte com dev 4info hte com Copyright 2012 by HTE All rights reserved No part of this material may be reproduced in any form or by any means physical or electronic without the express prior written consent of HTE Especially our competitiors But university faculty or students who may copy and distribute at will for any non commercial purpose THE FINE PRINT Disclaimer of warranty and limited warranty HTE has attempted to produce a useful high quality product at a reasonable price Every Development Board unit has been fully tested and checked for quality prior to shipment is warranted to be free of defects in material and workmanship for a period of 90 days after date of purchase During that time period HTE will at no charge to the purchaser of record repair or replace any defective unit returned to its Service Department in accordance with the following instructions 1 Phone HTE at the number above between 10 am and 3 pm Pacific Time GMT 0800 or e mail 4info hte com and obtain a Return Material Authorization RMA number Do not attempt to return the product without an R
17. MA number 2 Provide HTE with Model Serial Number Proof of Purchase with date Return Address and preferred return shipping method Enclose a clear description of the problem experienced and any sample printouts showing the problem if possible 3 Take proper precautions to protect the product during shipping Mark the package FRAGILE and ship via UPS Parcel Post or Air Freight insured and prepaid Be sure the RMA number appears clearly on the box as well as any accompanying correspondence Do not send COLLECT collect shipments will be refused and returned to sender This warranty is void in cases of misuse abuse abnormal conditions of operation or attempts to alter or modify the function of the product or for use within 100 miles of detonation of a nuclear device The product and written material are provided AS IS without warranty of any kind even if HTE has been advised of that purpose The entire risk as to the results and performance of the product is assumed by the user In other words if you do something any reasonable person see below would consider stupid it s your own fault Also we do not recommend inserting the board in any body cavities as injury may result HTE makes no representations or warranties with respect to the contents or use of this product HTE shall have no liability or responsibility to purchaser or to any person or entity with respect to any liability loss or damage caused or alleged to be caused
18. g right angle connectors to another board the odd and even pin numbers will be switched If the board uses straight through or stacking ribbon or header connectors then the pin numbering will be identical for boath boards See I O board schematic DevIO Rev Schematicl pdf file for details Pusbutton Inputs Switches 51 4 Signal P1 Pin Number PB 1 29 2 30 PB 3 21 4 28 8 Position Switch 55 Inputs Signal P1 Pin Number 55 1 15 55 2 16 55 3 17 55 4 18 55 5 19 55 6 20 55 7 21 55 8 22 Discrete LEDs D1 8 Signal P1 Pin Number LED 1 11 LED 2 12 LED 3 9 LED 4 10 LED 5 2 LED 6 8 LED 7 5 LED 8 6 FPGADEVS6 Page 28 User s Manual Four Digit 7 Segment LED Display with Colon FPGADEVS6 Board Connector Pin Definitions Signal P1 Pin Number Vin 1 2 GND 3 4 25 26 49 50 Segment 46 Segment b 48 Segment c 45 Segment d 41 Segment 42 Segment f 44 Segment g 47 Segment dp 43 Character Enable 1 37 Character Enable 2 38 Character Enable 3 33 Character Enable 4 36 Colon Enable 35 Page 29 User s Manual Sample UCF File for use with Board UCF file f or FPGA P6 right angle to
19. gramming of the FTDI 16 bit USB microcontroller using the VNC FPGA Configuration Options The three methods to configure the FPGA are 1 Download the configuration file directly to the FPGA using a JTAG programmer 2 Program the SPI serial configuration EEPROM through the JT AG cable 3 Load the program from a USB thumb drive The development cycle for option 1 or 2 is as follows 1 OnaPC compile your project using ISE and generate the programming file 2 Use Impact to program the FPGA or the SPI configuration EEPROM 3 Upon completion and after power up the FPGA will load from the EEPROM Note that programming the FPGA directly through JTAG will result in loss of that FPGA configuration when power is removed but it is the fastest programming method Programming the SPI EEPROM configuration memory using JTAG is done indirectly through the FPGA and takes more than a minute but the result will be a non volatile configuration that loads automatically after every power cycle It is slower because the Impact utility program must first load an SPI programming file into the FPGA then send the file through the FPGA while the FPGA programs the SPI EEPROM configuration memory one bit at a time FPGADEVS6 Page 13 User s Manual Getting Started Using a USB Thumb Drive GPIO 5V Gnd pins LEDs D1 D4 connector P7 Banks 0 amp 3 Y em 94411 prre Lm 41 Done LED ooi dm Pa ape c LE
20. iguration memory using JTAG The first step is to create an SPI file in mcs format to program the configuration EEPROM using the JTAG cable See Xilinx application note 974 in the file xapp974 pdf Indirect Programming of SPI Serial Flash PROMs with Spartan 3A FPGAs The procedure is the same for the Spartan 6 and the serial PROM on the development board Program SPI PROM configuration memory using USB drive To program the configuration PROM using an external USB drive you must first create and place the desired mcs configuration filefor a 4M bit SPI PROM type M25P40 and the file must be named fpga mcs and placed in the root of a FAT formatted USB drive FPGADEVS6 Page 19 User s Manual Board Pinout and Configuration Connector and FPGA I O Pin Configuration The following tables define the mapping between the various resources on the board and the FPGA pins 8 MHz On Board Oscillator Component FPGA Pin Clock Input GCLK12 123 On Board LED s Component FPGA Pin LED 1 117 LED 2 116 LED 3 115 LED 4 114 Output Signal Logic 1 Turns LED ON FPGADEVS6 Page 20 User s Manual Connector FPGADEVS6 Signal Name FPGA Pin P6 Pin Vin Variable 1 3 3V 2 GND 3 GND 4 10_Bank2_P8 41 5 IO Bank2 N8 40 6 IO Ban
21. k2 P7 44 7 IO Bank2 N7 43 8 Bank2 46 9 45 10 IO Bank2 P5 48 11 IO Bank2 5 47 12 IO Bank2 P4 51 13 IO Bank2 4 50 14 lO Bank2 56 15 IO Bank2 N3 55 16 IO Bank2 P2 58 17 IO Bank2 N2 57 18 IO Bank2 P1 62 19 IO Bank2 N1 61 20 lO Bank2 67 21 IO Bank2 NO 66 22 IO P11 75 23 IO Banki N11 74 24 GND 25 GND 26 IO Banki 10 79 27 IO Banki N10 78 28 P9 81 29 IO 1 9 80 30 1 P8 83 31 IO 1 8 82 32 1 7 85 33 7 84 34 1 P6 88 35 IO 87 36 1 P5 93 37 IO 1 5 92 38 10 1 4 95 39 4 94 40 P3 98 41 IO N3 97 42 10 Banki P2 100 43 IO Banki N2 99 44 IO Banki P1 102 45 IO Banki N1 101 46 IO Banki PO 105 47 IO 1 NO 104 48 GND 49 GND 50 Page 21 User s Manual Connector P7 FPGADEVS6 Signal Name FPGA Pin P7 Pin Vin Variable 1 3 3V 2 GND 3 GND 4 10_Bank3_P12 35 5 10_Bank3_N12 34 6 10_Bank3_P11 33 7 IO Bank3 N11 32 8 Bank3 10 30 9 IO Bank3 N10 29 10 Bank3 P9 27 11 IO Bank3 N9 26 12 Bank3 P8 24 13 IO Bank3 N8 23 14 Bank3 P7 22 15 IO Bank3 N7 21 16 Bank3 17 17 IO 16 18 Bank3 P
22. le Name DevFPGA Behavioral Revision Revision 0 01 File Created Additional Comments library IEEE use IEEE STD LOGIC 1164 ALL use IEEE STD LOGIC ARITH ALL use IEEE STD LOGIC UNSIGNED ALL entity DevFPGA is port Input Pins CLOCK in std logic Output Pins LED out std logic vector 4 downto 1 Bidirectional Pins architecture Behavioral DevFPGA is signal LED Counter std logic vector 23 downto 0 begin LED 4 LED Counter 23 LED 3 LED Counter 22 LED 2 lt LED Counter 21 LED 1 lt LED Counter 20 MAIN process CLOCK begin if CLOCK event and CLOCK 1 then LED Counter lt LED Counter 1 end if end process end Behavioral The pin definitions in the corresponding UCF File are NET CLOCK LOC P123 LEDs on the FPGA board Active Hi 1 0 OFF NET LED 1 LOC P117 NET LED 2 LOC P116 NET LED 3 LOC P115 NET LED 4 LOC P114 NOTE The program above was written in VHDL using the Xilinx ISE Web Pack available on the xilinx com web site FPGADEVS6 Page 18 User s Manual Program FPGA Directly using To program the FPGA using a JTAG cable simply attach the programming cable to P10 the JTAG cable and use Impact to initialize the JTAG chain detect configure and program the FPGA with a bit file in as described in the Xilinx documentation Program SPI PROM conf
23. linx Inc Other trademarks are the property of their owners whoever they may be Table of Contents INTRODUCTION po 7 PERATURES E 7 COMPONENTS 8 Spartan 6 FPGA General 9 GENERAT FEATURES 252050 Svp re Te et rro ne evo c o e swa soe vo seo ocv sue eol Ve Puoi Pes eO P guard o 10 DESIGN CONSIDERATIONS SIGNAL NAMES AND LIMITATIONS 4 eere eee en 2 11 GETTING STARTED USING A USB THUMB DRIVE eee ee eese eene seen 14 GETTING STARTED USING A JTAG CABLE 15 SAMPLE UCE BILE Or 17 EXAMPLE THE LED VERSION OF HELLO 18 PROGRAM FPGA DIRECTLY USING JT AG nennen n nennen 19 PROGRAM SPI PROM CONFIGURATION MEMORY USING JTAQG eese eene 19 PROGRAM SPI PROM CONFIGURATION MEMORY USING USB DRIVE 222 19 BOARD LAYOUT i 25 USING THE FPGA WITH THE SWITCH LED USER BOARD 27
24. loading programs to FPGA USB microcontroller or serial EEPROM from a PC addition the Development Board can prove invaluable as an educational tool for learning about FPGAs microcontrollers and USB interfacing Components e Xilinx Spartan 6 XC6SLX9 FPGA in a 144 pin TQFP package 9 152 logic cell equivalents Thirty two 18K bit block RAMSs 576K bits Sixteen DSP48A Slices Two Digital Clock Managers DCMs Up to 102 user defined I O signals 4Mbit Serial SPI serial EEPROM for in system configuration PROM JTAG port for low cost download cable e Dual USB Controller FTDI VNC2 32 Type A USB Connector Type Mini B USB Connector 8 MHz Local Oscillator e Two 50 Pin Expansion I O Connectors with 84 Pre Assigned I O Pins 4 On board LED 5 e On Board Power Supply using National LP3906 Quad Regulator 3 3 1 5 Operating Voltage 1 2V 1 5 A FPGA Core Voltage 3 3V 300 mA FPGA Auxillary Voltage 1 8 300 mA Secondary I O Operating Voltage for an external 5V supply USB power typically limited to 500mA The user can easily Design FPGA based products with Host Device USB Interface Customize the Board for Small Volume Production Quickly Test and Debug new configurations e Field Update configuration using only a USB Thumb Drive Install New Configurations in the Non volatile SPI configuration PROM In conjunction with any PC capable of running the free ISE Webpack development tools fro
25. m Xilinx and VNC2 IDE from FTDI the Development Board becomes a powerful stand alone hardware and firmware development system The board is capable of supporting either the XC6SLX4 or the XC6SL X9 The development board ships with an 1 9 and the OEM version can be ordered with either the LX4 or the LX9 The key FPGADEVS6 Page 8 User s Manual capabilities are shown in table below Note that 1 9 is has more than twice resources of the 35200 Spartan 3 device present on most FPGA development boards Spartan 6 FPGA General Properties Slices Logic Cells CLB Flip Flops Maximum Distributed RAM Kb Block RAM 18 Kb each Total Block RAM Kb Clock Management Tiles CMT Maximum Single Ended Pins Maximum Differential Pairs DSP48A1 Slices Memory Controller Blocks Configuration Memory Mb Notes 1 Each slice contains four LUTs and eight flip flops Each CMT contains two DCMs and one PLL a N 600 3 840 4 800 75 12 216 132 66 21 Each DSP48A1 slice contains 18x18 multiplier adder an accumulator 1 430 9 152 11 440 90 32 576 200 100 16 21 Spartan 6 FPGA logic cell ratings reflect the increased logic capacity offered by the new 6 input LUT architecture Block RAM are fundamentally 18Kb in size Each block can also be used as two independent 9 Kb blocks The Data above is taken directly from the Xilinx Spartan 6 product
26. of bytes in each record It ends with the checksum BCAAAATTHH HHCC Start character colon BC The hexadecimal number of bytes in the record If BC 0 the it is the end of file record Address in hexadecimal of first data byte in the record TT Record type If TT 00 then data record If TT 01 then end of file record HH One data byte in hexadecimal notation CC Checksum is the two s complement of binary summation of preceding bytes in record including the byte count address and record type FPGADEVS6 Page E User s Manual Appendix Troubleshooting No LEDs light up at all Explanation No power to board Action Check and correct power connection LEDs light but are very dim Explanation No valid FPGA configuration loaded in the serial PROM Action Program with a known good FPGA configuration file FPGADEVS6 Page F User s Manual Appendix Board Version Options You can use the development board and later purchase the OEM version populated with those connectors and features that are actually used in your final application to customize or reduce the cost of the board Custom configurations may be subject to a minimum order quantity Contact HTE for more information The board can be ordered with either a Spartan 6 LX9 or a LX4 device The optional parts that can be left off the OEM board include 50 pin GPIO connectors P7 e USB microcontroller U3 e USB connectors P8 P
27. r Platform USB cables JTAG software to be used with the development board includes Xilinx Impact and ChipScope USB Microcontroller Programming port The 6 pin connector P11 can be used for programming and debug of the on board FTDI VNC2 USB microcontroller using the free FTDI C programming IDE development tools Power Requires a single 5 volt supply at 500 mA typical from a standard PC USB port or an external 5V power supply Dimensions 76 2mm by 76 2mm by 6 4mm high or 3 inches by 3 inches by 0 25 inch high Environmental Storage temperature range 25 to 100 C Operating temperature range 0 to 50 C FPGADEVS6 Page 10 User s Manual Design Considerations Signal Names and Limitations A description of the Development Board s characteristics signals and allocation of resources follows The Development Board uses approximately 60mA of the standard 500mA available from a standard USB port leaving approximately 400 mA for external devices If an external 5V power supply is used additional power may be drawn from the on board regulators subject to their limitations An auxiliary 1 8V output is also available on a pin that is adjacent to LED D4 The 1 2V FPGA core voltage supply is dedicated to U1 The Development Board is configured to use either single ended or differential I O standards Because of this the pins are numbered by bank port type and pin For example adjacent pins 5 and 6 on connector P7 are labeled 3P1
28. s standard JTAG to program the FPGA and serial EEPROM Connects to USB port of a PC for power and communication Can load configuration files from a USB thumb drive FAT file format FTDI USB microcontroller Program download debug via USB Rapid product development compatible with most development tools Low cost OEM version available for dedicated applications The Development Board consists of a minimal configuration Spartan 6 FPGA board containing the absolute minimum stand alone design It is suitable for and development applications The Development Board provides the user with the ability to FPGADEVS6 Page 7 User s Manual download test and debug designs for a prototype or production system The version of the board can be the final target for the application or it can be customized The OEM board can be ordered with standard straight through stackable or right angle 50 pin connectors or without any connectors The Development Board can be stacked or connected horizontally to expansion interfaces such as the optional user board peripheral interface boards or customer specific designs for a specific application The FPGA board provides powerful functions to assist the designer in the integration debug and test phase of FPGA project development The Development Board provides GPIO pin interface pins on standard 0 1 grid header for connectors The JTAG and USB processor connectors allow for powering debugging and down
29. scription 1 5vin This pin can be used instead of the USB connector P8 if you have an externally regulated 5v supply This powers the on board regulator to deliver power to all components on the board 2 Ground NOTE The 5V power input is NOT reverse polarity protected Reversing the 5V and Gnd connections will damage the board FPGADEVS6 Page H User s Manual Appendix Useful Web sites Below is a list of useful web sites related to the board accessories and development tools http www hte com dev The HTE web site has other resources http www xilinx com Xilinx is the manufacturer of the Spartan 6 ICs related FPGA architectures and has documentation app notes and free software utilities that will work with the FPGA board FPGADEVS6 Page User s Manual Appendix J Optional User I O Board Layout FPGADEVS6 Page J User s Manual Appendix Problem Report Comment Form Please complete this form if you discover any software or hardware problems documentation problems or would like to suggest product enhancements Duplicate this form if you need additional copies and or attach extra pages if necessary Hardware Problem Documentation Problem Programming Problem Product Enhancement Date Serial d Product Version 4 Name Title Company City State Zip Country Phone Ext Please describe
30. selection guide FPGADEVS6 Page 9 User s Manual General Features FPGA Xilinx Spartan 6 LX4 or LX9 FPGA the 144 pin TQFP package clocked by an 8 MHz crystal oscillator This frequency makes it easy to generate standard clock rates using the FPGA s internal clock resources USB Microcontroller The FTDI VNC2 32 pin USB Microcontroller supports two USB interfaces USB peripheral device interface with a mini B connector to connect to a PC or power supply and a USB host type A connector that accommodates a flash USB thumb drive containing a configuration file to be programmed into the Serial EEPROM Serial EEPROM Configuration Memory An M25P40 non volatile SPI serial EEPROM configuration memory Upon power application the FPGA automatically loads its configuration data from this SPI serial EEPROM Depending upon what code is present in the USB processor and whether an external USB drive with a valid configuration fpga sys file is present in the root directory the serial EEPROM or the FPGA may also be loaded with different configuration file sources When the file is not present or there is no USB drive at power up or if the USB processor is unprogrammed the FPGA will load the previously programmed configuration file from the serial EEPROM JTAG Port The 0 1 single row 6 pin JTAG connector P10 allows the FPGA or the serial EEPROM to be programmed using any Xilinx compatible JTAG programming cable Xilinx parallel o
31. wing pages FPGADEVS6 Page 14 User s Manual Getting Started Using JTAG Cable 5V Gnd pins LEDs D1 D4 GPIO na Done LED connector P7 Banks 0 amp 3 od NL UN ON4 Banks 1 amp 2 Se 88 22 az amp m P10 6 pin 0 1 JTAG Connnector P8 Power and USB to PC Thumb drive USB connector For JTAG Programming Connector P10 JTAG Connector Pinout Pin Signal Wire Color 1 Red 2 Blk 3 TCK Grn 4 TDO Orn 5 TDI Blu 6 TMS Brn 2 6 2 cae 2N6 P1i QS9905 GNO 3U3 TMS og MIU SEE T mu 8 123456 P10 pinout Connector P8 provides power to the board Before configuring the FPGA or configuration PROM a powered USB port or separate USB power supply must be connected to P8 or 5V must be supplied by the 5V Gnd pins to supply power to the FPGADEVS6 Page 15 User s Manual board 5V is regulated to 3 3V and other voltages required by the FPGA The pins on the P6 and P7 GPIO connectors are defined in Appendix and can be configured for 3 3V or VAR 1 Attach the small end of the A to mini B USB cable to connector P8 on the board 2 Attach the large end of the cable to a PC USB port or a USB power supply When power is connected properly
Download Pdf Manuals
Related Search