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uPD780948 Subseries 8-bit Single

1. TA 25 C Parameter Conditions Vpp 0 3 to 4 6 0 AV pp Supply voltage AVpp AVger 0 3 to Vpp 0 3 AVREF AVss 0 3 to 0 3 P07 P10 P17 P20 P26 P30 P34 P40 P47 P50 P57 P64 P65 P67 P70 P77 j Input voltage P420 P127 P130 P137 P140 P147 X1 X2 RESET Output voltage Vo 0 3 to Vpp 0 3 Analog input voltage Van P10 to P17 Analog input pin AV gg 0 3 to AVpp 0 3 1 pin except P34 10 High level output P34 EH current OH P07 P20 P26 P30 P33 P40 P47 P50 P57 P64 P65 P67 P70 P77 P120 P127 30 P130 137 P140 147 CTXD total Peak 20 1 t P34 ae In exce P i Effective a value mA Peak 20 value Low level output Note P34 current lo Effective 15 value P00 P07 P20 P26 P30 P33 P40 Peak 30 P47 P64 P65 P67 CTXD total Effective 15 P50 P57 P70 P77 P120 P127 Peak 30 P130 P137 P140 P147 total Effective 15 272 Topt 40 to 110 emperature C Storage 40 to 150 temperature Note Effective value should be calculated as follows Effective value Peak value x Vduty Caution Product quality may suffer if the absolute maximum ratings are exceeded for even a single parameter or even momentarily That is the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage T
2. 404 Standby TIMING Ee m 404 HALT Mode Clear upon Interrupt Generation 22 406 HALT Mode Release by 407 STOP Mode Release by Interrupt Generation 409 Release by STOP Mode RESET 44 404 00 00 0 410 Block Diagram of Reset Function essen eene enne 411 Timing of Reset Input by RESET 4 44000 412 Timing of Reset due to Watchdog Timer 412 Timing of Reset Input in STOP Mode by RESET 412 Memory Size Switching Register 416 User s Manual U12670EE3VOUDOO 21 Figure 23 2 Figure 23 3 Figure 23 4 Figure 23 5 Figure 23 6 Figure A 1 22 Internal Expansion RAM Size Switching Register 417 Transmission Method Selection 418 Connection of the Flash Programmer using 3 Wire Serial I O Method 420 Connection of the Flash Programmer using UART 420 Connection of the Flash Programmer using Pseudo 3 wire Serial I O Method 421 Development Tool 492 User s Manual U12670EE3VOUD00
3. 64 General Register Configuration eene 65 Relative 70 Immediate 71 Table Indirect 72 Register 73 Register Addressing eie esed ida a stie D RR 75 Direct addressing eee i aei Casi To et 76 Short direct addressihig ec quete te du eeu 77 Special Function Register SFR Addressing 78 Register indirect 79 Based addressing description example eee 80 Based indexed addressing description 81 Stack addressing description 82 Pon Type RM c didn A ME SA tie ee ae 83 POO to PO7 Configurations ssssssssssssesesee eene nnne nennen enr sitne en 87 P110 to P17 Configurations 88 P20 to P26 Configurations ssssssssssssseeseeee eene nennen nnne sitne 89 P30 to P34 Configurations sssssssssssssseses eee enne enne nnne enne trnnnen 90 P40 to P47 Configurations sss eene nnne nennen nnne sitne en 91 P50 to P57 Configurations ci ty eode e en ae ed i de re ve 92 P64 P65 and P67
4. 303 16 13 5 Message Count Register 304 16 14 Baudrate 306 16 15 Function 312 16 15 1 Transmit 2 312 16 15 2 Receive 2 314 16 15 3 Mask 315 16 15 4 Special 1 317 16 16 Interrupt 319 16 16 1 Interrupt 319 16 16 2 Transmit 319 16 16 3 Receive 319 16 16 4 320 16 17 Influence of the standby Function of the CAN 321 16 17 1 CPU Halt 321 16 17 2 CPU Stop 321 16 17 3 DCAN Sleep 321 16 17 4 DCAN Stop
5. 67 Stack pointer Serg Lu tee te ee ee hae thc Ded ata Be ee 64 Successive approximation register SAR 204 Synchronization Control Registers 0 and 1 308 T Timer clock select register 50 TCL50 1 166 Timer clock select register 51 TCL51 1 167 Transmit control register 2 1 312 Transmit shift register 1 7 60 5 234 Watch Timer Mode Register WTM 187 Watchdog timer clock select register 5 194 Watchdog timer mode register WDTM 195 Z 2 GG aT ete ee pe bea an 63 User s Manual U12670EE3VOUDOO 501 502 User s Manual U12670EE3VOUDOO Appendix Revision History The following shows the revision history up to present Application portions signifies the chapter of each edition Edition No Major items revised Table 2 3 Types of Pin Input Output Circuits revised 1 2 Revised Sections Chapter 2 Pin Function uPD780948 Subseries Note added in Figur
6. lt Av A laddr 6 A lt Av addr16 A HL A Av HL A HL byte lt Av HL byte A HL B A lt Av HL A HL C A amp Av HL A byte A byte saddr byte saddr byte Ar Note 3 AA r nA r A A saddr A laddr16 A saddr A addr16 A HL A HL A HL byte A HL byte A HL B A HL A HL C A HL AX word AX CY lt AX word AX word AX CY AX word AX word CO A CO A A A CO CO CO Co A HR MD A CO CO A AJ BR o AX word XIXI XIXI X X X X X X XIXI XI XIXI XIXI XI X X XI X X XIXI XIXI XI X X X XIX XIXI XI X XI X X X X X X X X XIXI XIX X X X X X X X X X X AxX C MINN U MN NI NI OI NIN NI NINI NI N Ol NINI NINI NINI ONIN AX Quotient C Remainder C When the internal high speed RAM area is accessed or instruction with no data access When an area except the internal high speed RAM area is accessed Except Only when rp BC DE or HL instruction clock cycle is one cycle of the CPU clock fcpy selected by the PCC register This clock cycle
7. 93 P70 to P77 Configurations eire ena dte Deere cetacean 94 P120 to P127 GonfIgurations 3 cete die pce pacco Eat eoa 95 P130 to P 197 Gonfigurations etel etc ete n doce Dr e xL ovt eed 96 P140 to P147 Configurations ssesssssssssseeeseeeeneneneee ennt 97 Port Mode Register 99 Pull Up Resistor Option Register PUO PU4 PU7 and PU13 Format 100 Port Function Register PF2 PF5 PF7 PF12 to PF14 101 Memory Expansion Mode Register 102 Block Diagram of Clock Generator 106 Processor Clock Control Register Format 1 2 107 External Circuit of Main System Clock 2 2 109 External Circuit of Subsystem Clock 2 20000 110 Examples of Oscillator with Bad Connection 1 3 111 Main System Clock Stop Function 0 0 0 116 System Clock and CPU Clock Switching sess 118 Block Diagram of 16 Bit Timer Event Counter 0 120 Format of 16 Bit Timer Mode Control Register 125 Format of Capture Compare Control Register 0 126 Format of 16
8. CROO as compare register 01 as capture register 0 1 When these bits are reset to 0 or set to 1 the other functions can be used along with the pulse width measurement function For details refer to Figures 6 2 and 6 3 User s Manual U15251EE3VOUDOO 133 Chapter6 16 Timer Event Counter 0 Figure 6 12 Configuration for Pulse Width Measurement with Free Running Counter fx 2 4 fx 2 16 bit timer register TMO Selector fx 2 16 bit capture compare register 01 TI00 P05 D 00 Internal bus Figure 6 13 Timing of Pulse Width Measurement with Free Running Counter and One Capture Register with both edges specified 1 TMO count value YooooH a i 1 TIOO pin input 4 m Value loaded V V V to CRO X wi X 9 DOTA D3 1 00 7 134 User s Manual U15251EE3VOUDOO Chapter 6 16 Bit Timer Event Counter 0 2 Measurement of two pulse widths with free running counter The pulse widths of the two signals respectively input to the TIOO and TIO1 pins can be measured when the 16 bit timer register TMO is used as a free running counter refer to Figure 6 14 When the edge specified by bits 4 and 5 500 and 501 of the prescaler mode register 0 is input to the TIOO pin the value of the
9. ID amp Compare ID Compare ID Compare ID One mask Compare ID Compare ID Mask1 Compare ID amp mask1 Compare ID One mask ID amp Mask1 Compare ID amp mask1 Compare ID Two masks ID amp ID amp Compare ID amp maskO Global mask Compare ID Compare ID Compare ID amp maskO Mask1 Compare ID Compare ID amp mask1 amp mask1 Two normal rest global mask One mask rest global mask Priority of receive buffers during compare It is possible that more than one receive buffer is configured to receive a particular message For this case an arbitrary rule for the storage of the message into one of several matching receive buffers becomes effective The priority of a receive buffers depends on its type defined by the setup of the mask register in first place and its number in second place The rules for priority are All non masked receive buffers have a higher priority than the masked receive buffer Lower numbered receive buffers have higher priority Examples 1 All RX buffers are enabled to receive the same standard identifier Ox7FFH Result the message with identifier OX7FFH is stored in RXO 2 n difference to the previous set up the mask option is set fo
10. 375 Program Status Word Format ccccccceecececeeeeeeeeeeeseeeeeeaeeeseeeeeesaeeseeeeeeseaeeeeeaeeeeeas 376 Flowchart from Non Maskable Interrupt Generation to Acknowledge 377 Non Maskable Interrupt Request Acknowledge Timing 378 Non Maskable Interrupt Request Acknowledge Operation 378 Interrupt Request Acknowledge Processing Algorithm 380 Interrupt Request Acknowledge Timing Minimum 381 Interrupt Request Acknowledge Timing Maximum 381 Multiple Interrupt Example 1 2 384 Interrupt Request 4 387 Memory Map when Using External Device Expansion Function 1 3 390 Memory Expansion Mode Register Format sse 393 Memory Expansion Wait Register 394 Memory Size Switching Register Format 395 Instruction Fetch from External 397 External Memory Read 398 External Memory Write 0 399 External Memory Read Modify Write Timing 400 Connection Example of uPD780948 and 401 Oscillation Stabilization Time Select Register
11. 00 16 bit capture compare Noise 01 rejection register 00 00 INTP4 circuit P04 Coincidence ae 16 bit timer register Output 5 control 5 100 fx 2 ircui B Coincidence Noise fx 2 rejection circuit 16 bit capture compare register 01 CRO1 00 TOO P05 circuit INTTMO1 eee Timer output control register TOCO 1 Timermode control register TMCO Prescaler mode register 0 PRMO Internal bus User s Manual U15251EE3VOUDOO 120 1 Chapter 6 16 Bit Timer Event Counter 0 16 bit timer register TMO TMO is a 16 bit read only register that counts pulses The counter is incremented in synchronization with the rising edge of an input clock If the count value is read during operation input of the count clock is temporarily stopped and the count value at that point is read The count value is reset to 0000H in the following cases 1 2 3 4 RESET is input TMCO03 and 02 are cleared Valid edge of TIOO is input in the clear amp start mode by inputting valid edge of TIOO TMO and CROO coincide with each other in the clear amp start mode on coincidence between TMO and CROO User s Manual U15251EE3VOUDOO 121 2 Table 6 2 Chapter6 16 Bit T
12. 109 5 4 1 Main system clock 109 5 4 2 Subsystem clock 110 5 4 3 When no subsystem clock is 114 5 5 Clock Generator 115 5 5 1 Main system clock 116 5 5 2 Subsystem clock 116 5 6 Changing System Clock and CPU Clock Settings 117 5 6 1 Time required for switchover between system clock and CPU clock 117 5 6 2 System clock and CPU clock switching 118 Chapter6 16 Bit Timer Event Counter 0 119 6 1 16 bit Timer Event Counter 0 Function 119 6 2 16 bit Timer Event Counter 0 120 6 3 16 Bit Timer Event Counter 0 Control 124 6 4 16 Bit Timer Event Counter 0 Operations 130 6 4 1 Operation as interval timer 16 5 130 6 4 2 PPG output operation Lek RR RET RE E REPE ax 132 10 User s Manual U12670EE3VOUD00 6 4 3 Pulse width measurement 133 6 4 4 Ope
13. 220 Composition of 51031 226 List of SFRs Special Function 226 Configuration of UART 234 List of SFRs Special Function 235 Relation between 5 bit Counter s Source Clock and n 247 Relation between Main System Clock and Baud 248 User s Manual U12670EE3VOUDOO 23 Table 15 5 Table 16 1 Table 16 2 Table 16 3 Table 16 4 Table 16 5 Table 16 6 Table 16 7 Table 16 8 Table 16 9 Table 16 10 Table 16 11 Table 16 12 Table 16 13 Table 16 14 Table 16 15 Table 16 16 Table 16 17 Table 16 18 Table 16 19 Table 16 20 Table 16 21 Table 16 22 Table 16 23 Table 16 24 Table 16 25 Table 16 26 Table 16 27 Table 17 1 Table 17 2 Table 17 3 Table 17 4 Table 17 5 Table 17 6 Table 17 7 Table 17 8 Table 17 9 Table 18 1 Table 18 2 Table 19 1 Table 19 2 Table 19 3 Table 19 4 Table 20 1 Table 20 2 Table 20 3 Table 21 1 Table 21 2 Table 21 3 Table 21 4 Table 22 1 Table 23 1 Table 23 2 Table 23 3 Table 23 4 Table 23 5 Table 24 1 Table 24 2 24 Causes of Receive Errors c cccccccccccccccceeeececesceeeeuecceeesceauauaceseeseaueueeeeseaueuseeeeeueanans
14. 442 25 4 Subsystem Clock Oscillation Circuit Characteristics 448 25 5 DC 451 25 6 AC Characteristics ee Sad ee eee 460 25 6 1 Basic Operation 1 460 25 6 2 Read Write 7 466 25 6 29 SerialInterface keels ale bac Dh ata ead PME EE 472 25 6 4 A D Converter Characteristics 479 25 6 5 Data Memory Stop Mode Low Supply Voltage Data Retention Characteristics 481 25 6 6 Flash Memory Programming Characteristics 484 Chapter 26 Package 0 487 Chapter 27 Recommended Soldering Conditions 489 Appendix A Development Tools 491 14 User s Manual U12670EE3VOUDOO Appendix Embedded Appendix Index 2 455 vie so nates ro ea whee Appendix D Revision User s Manual U12670EE3VOUDOO 15 16 User s Manual U12670EE3VOUD00 Figure 1 1 Figure 1 2 Figure 1 3 Figure 2 1 Figure 2 2 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4
15. Conditions 510 setup time to SCKO tsik1 510 hold time from SCKO tks 500 output delay time from SCKO 4 tkso1 C 100 pF Nete Note Cis the load capacitance of SOO SCKO output line 472 User s Manual U12670EE3VOUD00 Chapter 25 Electrical Specifications 2 wire serial I O mode SCK1 Internal clock output Parameter Conditions SCK1 cycle time 2000 SCK1 high level width 5 2 160 SCK1 low level width R 1KO 5 2 160 SI1 setup time to SCK1 C 100 pF Note 300 SI1 hold time from SCK1 600 501 output delay time from SCK1 4 Note R and are the load resistance and the load capacitance of the 511 501 and SCK1 output line 3 wire serial I O mode SCK1 External clock output Parameter Conditions SCK1 cycle time SCK1 high level width SCK1 low level width R 1KQ 511 SO1 setup time to SCK1 7 C 100 pF Note 511 501 hold time from SCK1 T 511 501 output delay time from SCK1 4 Note Rand C are the load resistance and the load capacitance of the 511 501 SCK1 output line UART mode Dedicated baud rate generator output C CELL De User s Manual U12670EE3VOUDOO 473 2 pPD780948 A1 Chapter 25 Electrical Specifications TA 40 C to 110 C Vpp 4 0 to 5 5 V 3 wire serial I O mode SCKO
16. de 93 POMS hu me mnc M ALL 94 96 opp LU 95 97 Port function register 4 PF8 and PF9 101 Port mode register 2 PM2 Rime el weed nie el xw e el Wis 170 Port mode register 6 PM6 1 202 Port mode register 7 BM7 234 seed edd Peewee Ra ete REN e pe 129 Port mode registers PMO PM2 PM6 PM8 PM9 98 Power fail compare mode register 208 Power fail compare threshold value register PFT 208 Prescaler mode register PRM2 154 Prescaler mode register O 128 Priority specify flag registers PROL PROH 374 Processor clock control register PCC 107 Program couriter PO sorde Saee Red DERNIER ERU PR RI EURO RR S wield aaa 62 Program status word PSW 62 376 Pull up resistor option register PUO PU4 PU6 PU8 PU9 100 Pulse width measurement with free running counter and one capture register 120 155 R Receive
17. 373 Interrupt request flag ADIF 217 Interrupt request flag registers IFOL IF1L IFTH 372 L LCD display control register LCDC 335 LCD display mode register 334 LCD timer control register LCDTM 357 M Mask controlTegister bea eg ee eee dE 315 Mask Identifier Control Register MCON 1 294 Memory Size Switching Register IMS 416 Message Count Register bude ad Aue Et Rae a bue 304 Oscillation Stabilization Time Select Register 404 Port Oros i tannins 87 october aha heer rari cet ede e 88 eoe eit tede C mm veste i iau oni aita A erae dee 89 REEL 90 POMA 2 Medias dk dn Ns 91 Port bsc sooo ies apre tetas 92 nd
18. 128 128 CO O Cautions 1 When rewriting the contents of SGAM the timer operation does not need to be stopped However note that a high level may be output for one period due to rewrite timing 2 Bit 7 must be set to 0 364 User s Manual U12670EE3VOUDOO Chapter 18 Sound Generator 18 4 Sound Generator Operations 18 4 1 To output basic cycle signal SGOF without amplitude Select SGOF output by setting bit 3 SGOB of the sound generator control register SGCR to 0 The basic cycle signal with a frequency specified by the SGCLO to SGCL2 and SGBRO to SGBR3 is output At the same time the amplitude signal with an amplitude specified by the SGAMO to SGAM6G is output from the SGOA pin Figure 18 6 Sound Generator Output Operation Timing n n n n n n Timer 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Comparator 1 coincidence SGOF User s Manual U12670EE3VOUDOO 365 Chapter 18 Sound Generator 18 4 2 To output basic cycle signal SGO with amplitude Select SGO output by setting bit 3 SGOB of the sound generator control register SGCR to 1 The basic cycle signal with a frequency specified by the SGCLO to SGCL2 and SGBRO to SGBR3 is output When SGO output is selected the SGOA pin can be used as a PCL output clock output or I O port
19. 30 Setting prohibited NI oO BR Caution Writing to BRGCO during a communication operation may cause abnormal output from the baud rate generator and disable further communication operations There fore do not write to BRGCO during a communication operation Remarks 1 Source clock for 5 bit counter 2 n Value set via TPS00 to 502 1 lt lt 8 3 k Value set via MDLOO to MDLO3 0 lt k x 14 240 User s Manual U12670EE3VOUD00 Chapter 15 Serial Interface UART 15 5 Serial Interface Operations This section explains the different modes of the UART 15 5 1 Operation stop mode This mode is used when serial transfer is performed to reduce power consumption In the operation stop mode pins can be used as ordinary ports Register settings Operation stop mode settings are made via the asynchronous serial interface mode register ASIMO and RXEO must be set to 0 Figure 15 5 Register Settings T 5 4 3 2 1 0 R W Address 5 TXEO RXEO PSo1 500 ISRMO RW FFAOH OOH Operation mode Operation stop RXD pin function Port function TXD pin function Port function UARTO mode receive only Serial operation Port function UARTO mode transmit only Port function Serial operation UARTO mode transmit and receive Serial operation User s Ma
20. Port 2 read signal 3 WR Port2 write signal User s Manual U12670EE3VOUDOO 89 Chapter 4 Port Functions 4 2 4 Port 3 Port 3 is a 5 bit input output port with output latch P30 to P34 pins can specify the input mode output mode in 1 bit units with the port mode register Dual function include timer input clock output and sound generator output RESET input sets port 3 to input mode Figure 4 5 shows a block diagram of port 3 Figure 4 5 P30 to P34 Configurations TEE WRport Output Latch P30 to P34 Internal bus P30 T120 P31 T121 P32 TI22 to PM34 Dual Function Remarks 1 Port mode register 2 RD Port3 read signal 3 WR Port 3 write signal 90 User s Manual U12670EE3VOUDOO P33 PCL SGOA P34 SGO SGOF Chapter 4 Port Functions 4 2 5 Port4 This is an 8 bit input output port with output latches P40 to p47 pins can specify the input mode output mode in 8 bit units with the memory expansion mode register MM When P40 to P47 are used as input ports on chip pull up resistor can be connected bit wise with the pull up resistor option register PU4 Dual functions include address data bus function in external memory expansion mode RESET input sets the input mode The port 4 block diagram is shown in Figure 4 6 Figure 4 6 P40 to P47 Configurations Voo o 8 WRreort w P
21. 206 Analog input channel specification register 51 207 Asynchronous serial interface mode register 5 0 236 242 Asynchronous serial interface status register 5150 238 244 Auxiliary cairy tlag 2 ue Ae te has Gale dee Gide ie eae hd eed S 63 B Baud rate generator control register BRGCO 239 245 Bit Rate Prescaler Register 306 CAN control register 1 1 296 CAN Receive Error 303 CAN Transmit Error Counter 303 eroi MP O EEE E a a EIEE DEAS 123 Capture pulse control register 2 1 153 Capture register 20 CR20 1 150 Capture register 21 CR21 1 2 151 Capture register 22 CR22 2 0 151 Capture compare control register 0 126 Capture compare register 00 00 122
22. and 00 is selected by the 16 bit timer mode control register TMCO do not specify CRCOO as a capture register 3 If valid edge of TIOO is both falling and rising the capture operation is not avail able when CRCO1 1 4 To surely perform the capture operation the capture trigger requires a pulse two times longer than the count clock selected by prescaler mode register 0 PRMO 126 User s Manual U15251EE3VOUDOO Chapter 6 16 Bit Timer Event Counter 0 3 16 bit timer output control register TOCO This register controls the operation of the 16 bit timer event counter 0 output control circuit by set ting or resetting the R S flip flop enabling or disabling reverse output enabling or disabling output of 16 bit timer counter TMO enabling or disabling one shot pulse output operation and selecting an output trigger for a one shot pulse by software TOCO is set by an 1 bit or an 8 bit memory manipulation instruction RESET input sets TOCO to 00H Figure 6 4 shows the format of TOCO Figure 6 4 Format of 16 Bit Timer Output Control Register TOCO 7 6 5 4 lt 3 gt lt 2 gt 1 lt 0 gt R W Address PE Reset Timer output F F control on coincidence between CR01 and TMO Disables inversion timer output 1 Enables inversion timer output Set status of timer output F F of 16 bit timer counter TMO Not affected Resets timer output F F 0 Sets timer output F F 1 O O
23. ol ol o ol o 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 01 gt O O OF oO Ol o o oj oj oj OF 308 User s Manual U12670EE3VOUD00 Chapter 16 CAN Controller Figure 16 44 Synchronization Control Registers 0 and 1 2 2 The position of the sample point within the bit timing is defined by SPTOn through SPT4n Sample Point Position ther than under Setting prohibited 2x TQ 3x TQ 4x TQ 5x TQ 6x TQ 7x TQ 8x TQ 9x TQ 10x TQ 11x TQ 12x TQ 13x TQ 14x TQ 15x TQ 16 x TQ 0 17 x TQ Other than above Setting prohibited Ol ol ol ol ol 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 SJWO0 and SJW1 define the synchronization jump width as specified ISO 11898 SJW1 SJWO Synchronisation Jump Width User s Manual U12670EE3VOUDOO 309 Chapter 16 CAN Coniroller Limits on defining the bit timing The sample point position needs to be programmed between 3TQN and 17TQ which equals register value of 2 lt SPTxn lt 16 n 0 1 x 4 to 0 The number of TQ per bit is restricted to the range from 8TQ to 25TQ which equals a register value of 7 x DBTxn x 24 n 0 1 x 4 to 0 The length of phase segment 2 TSEG2 in TQ is given by the difference of TQ per
24. to FFH 2 n2 50 51 176 User s Manual U12670EE3VOUDOO Chapter 8 8 Bit Timer Event Counters 50 and 51 8 4 3 Square wave output A square wave with any selected frequency is output at intervals of the value preset to 8 bit compare registers CR50 CR51 The TO50 P06 TI50 or TO51 P07 TI51 pin output status is reversed at intervals of the count value pre set to CR50 or 51 by setting bit 1 TMC501 and bit 0 50 of the 8 bit timer output control regis ter 5 50 or bit 1 TMC511 and bit 0 TOE51 of the 8 bit timer mode control register 6 TMC51 to 1 This enables a square wave of a selected frequency to be output Figure 8 13 8 Bit Timer Mode Control Register Settings for Square Wave Output Operation TMCn6 TMOCn4 LVSn LVRn TMCn1 TOEn TMCn TOn output enable Inversion of output on match of TMn and CRn Specifies TO1 output F F1 initial value TMn operation enable Clear and start mode on match of TMn and CRn TMn operation enable Setting Method 1 Set the registers Set the port latch and port mode register to 0 TCL5n Selects the count clock CR5n Compare value TMC5n Selects the clear and start mode when TM5n and CR5n match LVS5n LVR5n Setting State of Timer Output flip flop 1 0 High level output 0 1 Low level output Inversion of timer output flip flop enabled Timer output enabled gt TOE5n 1 When TCE5n 1 is set the counter start
25. Error frame Interframe space or overload frame Error delimiter Error flag Error flag Error bit Table 16 7 Definition of each Field Bit Number Definition Error active node sends 6 bits dominant level continuously Error passive node sends 6 bits recessive level continuously Error flag Error flag Nodes receiving an error flag detect bit stuff errors and issue error superpositioning flags themselves Sends 8 bits recessive level continuously Error delimiter In case of monitoring dominant level at 8th bit an overload frame is transmitted after the next bit An error frame is transmitted continuously after the bit where the error Erroneous bit has occurred in case of a CRC error transmission continues after the ACK delimiter Interframe space Interframe space or overload frame continues overload frame 264 User s Manual U12670EE3VOUDOO 16 1 6 Overload Frame Chapter 16 CAN Controller This frame is started at the first bit of the intermission when the reception node is busy with exploiting the receive operation and is not ready for further reception When a bit error is detected in the intermission also an overload frame is sent following the next bit after the bit error detection Detecting a dominant bit during the 3 bit of intermission will be interpreted as START OF FRAME At most two OVERLOAD FRAMEs may be generat
26. No Any simultaneously generated high priority interrupts Yes Interrupt request reserve Interrupt request Vectored interrupt No reserve servicing Yes Interrupt request reserve uo Yes Interrupt request reserve Vectored interrupt servicing Remark Interrupt request flag Interrupt mask flag xxPR Priority specify flag IE Flag to control maskable interrupt request acknowledge ISP Flag to indicate the priority of interrupt being serviced 0 an interrupt with higher priority is being serviced 1 interrupt request is not acknowledged or an interrupt with lower priority is being serviced 380 User s Manual U12670EESVOUDOO Chapter 19 Interrupt Functions Figure 19 11 Interrupt Request Acknowledge Timing Minimum Time 6 Clocks i PSW and PC Save Interrupt Servicing Program fTITIIINII ks xxPR 1 8 Clocks i re A xxPR 0 7 Clocks Remark 1 clock 1 fcpy fepu CPU clock Figure 19 12 Interrupt Request Acknowledge Timing Maximum Time 25 Clocks 6 Clocks 5 PSW PC Save Interrupt CPU Processing Divide Instruction Jump to Interrupt Servicing Servicing Program xxPR 1 33 Clocks Big a x xxPR 0 32 Clocks Remark 1 clock 1 fopy fepu CPU clock User s Manual U12670EE3VOUDOO 381 Chapter 19 Interrupt Functions 19 4 3 Software inte
27. 2 INTP3 INTP4 INTCE INTCR INTCTO INTCT1 INTCSIO INTCSI1 INTSER INTSR INTST 00 INTTMO1 INTTM50 51 INTWTI INTWT BRK 58 User s Manual U12670EE3VOUDOO Chapter 3 CPU Architecture 2 CALLT instruction table area The 64 byte area 0040H to 007FH can store the subroutine entry address of a 1 byte call instruc tion CALLT 3 CALLF instruction entry area The area 0800 to OFFFH can perform a direct subroutine call with a 2 byte call instruction CALLF 3 1 2 Internal data memory space The uPD780948 Subseries units incorporate the following RAMs 1 Internal high speed RAM This is a 1024 x 8 bit configuration in the area FBOOH to FEFFH 4 banks of general registers each bank consisting of eight 8 bit registers are allocated in the 32 byte area to FEFFH The internal high speed RAM has to be used as a stack memory 2 LCD Display RAM The LCD Display RAM is allocated to the 40 x 4 bits area from FA58H to FA7FH LCD Display RAM can also be used as normal RAM 3 Internal expansion RAM Internal expansion RAM is allocated to the 992 byte area from F400H to F7DFH 3 1 3 Special function register SFR area An on chip peripheral hardware special function register SFR is allocated in the area FFOOH to FFFFH Refer to Table 3 8 Special Function Register List on page 67 Caution Do not access
28. P77 P70 P57 P50 A15 A8 Output Common signal output of LCD controller driver LCD drive voltage Output Sound generator output P34 SGOF Output Sound generator amplitude output P33 PCL Output Sound generator frequency output P34 SGO Input A D converter analog input P10 P17 AD converter reference voltage input and analog power supply AD converter ground potential Connect to Vss System reset input Crystal connection for main system clock RC connection for subsystem clock Positive power supply Ground potential High voltage supply for flash programming only flash version 40 Internal connection Connect directly to Vss only Mask ROM version User s Manual U12670EE3VOUD00 Chapter 2 Pin Function uPD780948 Subseries 2 3 Description of Pin Functions 2 3 1 POO to Port 0 This is an 8 bit input output port Besides serving as input output port the external interrupt input an external count clock input to the timer a capture trigger signal input and a timer signal output are imple mented 1 2 Port mode POO to P07 function as input output ports POO to P07 can be specified for input or output bit wise with a port mode register When they are used as input ports pull up resistors can be connected to them by defining the pull up resistors bit wise in the pull up resistor option
29. TXD Output Asynchronous serial interface data output Input P26 CRXD Input CAN serial data input Input CTXD Output CAN serial data output Output CCLK Input CAN serial clock input CL1 TIOO PO5 TOO External count clock input to 16 bit timer TMO TIO1 4 20 P30 21 Input Capture trigger input Input P31 T122 P32 TI50 External count clock input to 8 bit timer TM50 P06 TO50 TI51 External count clock input to 8 bit timer TM51 P07 TO51 TOO 16 bit timer output P05 TIOO T2P0 16 bit timer output Output Input TO50 8 bit timer output also used for PWM output P06 TI50 TO51 8 bit timer output also used for PWM output P07 TI51 PCL Output Clock output Input P33 SGOA ADO AD7 Input Output Low order address data bus at external memory Input P40 P47 expansion High order address data bus at external memory P50 P57 A8 A15 Output expansion Input S39 32 BD Strobe signal output for read operation from external P64 memory Output Input WR Strobe signal output for write operation from external P65 memory ASTB Output Strobe output to access external memory Input P67 User s Manual U12670EE3VOUDOO 39 Pin Name Input Output Output Chapter 2 Pin Function uPD780948 Subseries Table 2 2 Non Port Pins 2 2 Function Segment signal output of LCD controller driver Alternate Function Pin P147 P140 P137 P130 P127 P120
30. Table 8 9 8 Bit Timer Event Counters 51 Square Wave Output Ranges 8 Bit Timer Event Counter Mode TCL501 TCL500 Minimum Pulse Time 1 fx 125 ns Maximum Pulse Time 28 x 1 fy 32 us Resolution 1 fx 125 ns 2 x 1 fx 250 ns 2 x 1 fy 64 ms 2 x 1 fx 250 ns 23 x 1 fx 1 us 11 x 4 fy 256 ms 23 x 1 fx 1 us 25 x 1 fx 4 us 213 x 1 fx 1 ms 2 x 1 fx 4 us 2 x 1 fx 16 us 215 x 1 4 ms 2 x 1 fx 16 us 21 x 1 fx 512 us 220 x 1 fy 131 ms Remarks 1 fy Main system clock oscillation frequency 178 2 Values in parentheses when operated at fy 8 0 MHz 3 n2 50 51 User s Manual U12670EE3VOUD00 21 x 1 fx 512 us Chapter 8 8 Bit Timer Event Counters 50 and 51 8 4 4 PWM output operations Setting the 8 bit timer mode control registers TMC50 and TMC51 as shown in Figure 8 15 allows operation as PWM output Pulses with the duty rate determined by the values preset in 8 bit compare registers CR50 and CR51 output from the TO50 PO6 TI50 or TO51 P07 T151 pin Select the active level of PWM pulse with bit 1 of the 8 bit timer mode control register 50 TMC50 or bit 1 of the 8 bit timer mode control register 51 TMC51 This PWM pulse has an 8 bit resolution The pulse can be converted into an analog voltage by integrat ing it with an external low pass filter LPF Count clock of the 8 bit timer register 50 TM5
31. interrupt request is not accepted or an interrupt with lower priority is being serviced 0 Interrupt request acknowledge is disabled IE 1 Interrupt request acknowledge is enabled 4 xxPR is a flag contained in PROL PROH and PRIL xxPR 0 Higher priority level xxPR 1 Lower priority level User s Manual U12670EE3VOUDOO 383 Chapter 19 Interrupt Functions Figure 19 13 Multiple Interrupt Example 1 2 a Example 1 Two multiple interrupts generated Main Processing INTxx INTyy INTzz Servicing Servicing Servicing IE 0 IE 0 INTyy INTzz INTxx PR 0 PR 0 PR 1 RETI Y Y RETI RETI Y During interrupt INTxx servicing two interrupt requests INTyy and INTzz are acknowledged and a mul tiple interrupt is generated An El instruction is issued before each interrupt request acknowledge and the interrupt request acknowledge enable state is set b Example 2 Multiple interrupt is not generated by priority control Main Processing INTxx INTyy Servicing Servicing Y Y eS To entm eee 21 Y 1 Instruction The interrupt request INTyy generated during interrupt INTxx servicing is acknowledged because the interrupt priority is lower than that of INTxx and a multiple interrupt is not generated INTyy request is retained and acknowledged after execution of 1 instruction execution of the main processing Remark
32. 298 Possible Reactions of the 303 Mask Operation 316 Interrupt SoOUrCes 2 1 onn pe ein eA He Ha eer edt dee Hard odere oa 319 Maximum Number of Display 331 LCD Controller Driver Configuration sees 332 Me ERE c 337 ECD Drive Voltage ric detecte nei spen Pose baee dne e s vae du dias 338 LCD Drive Voltages with On Chip Split Resistor connected externally 340 Selection and Non Selection Voltages COMO 344 Selection and Non Selection Voltages COMO COM 347 Selection and Non Selection Voltages COMO to 2 350 Selection and Non Selection Voltages COMO to 354 Sound Generator eee 360 Maximum and Minimum Values of the Buzzer Output Frequency 362 Interrupt Source List iiid eere ee ee HA ae tt de desire e ia ee eds 368 Various Flags Corresponding to Interrupt Request 371 Times from Maskable Interrupt Request Generation to Interrupt Service 379 Interrupt Request Enabled for Multiple Interrupt during Interrupt Servicing 383 Pin
33. 5 CRC field This field consists of a 15 bit CRC sequence to check the transmission error and a CRC delimiter Figure 16 9 CRC Field Data field and control field T CRC field NE d ACK field R D CRC sequence CRC delimiter 15 bits 1 bit 15 bits CRC generation polynomial is expressed by PEK OXI XP EX T Transmission node Transmits the CRC sequence calculated from the start of frame arbitration field control field and data field eliminating stuff bits Reception node The CRC received will be compared with the CRC calculated in the receiving node For this calculation the stuff bits of the received CRC are eliminated In case these do not match the node issues an error frame User s Manual U12670EE3VOUDOO 261 Chapter 16 CAN Coniroller 6 ACK field For check of normal reception Figure 16 10 ACK Field CRC field M ACK field C End of frame D ACK slot ACK delimiter 1 bit 1 bit Receive node sets the ACK slot to dominant level if no error was detected 7 End of frame Indicates the end of the transmission reception Figure 16 11 End of Frame ACK field End of frame Interframe space of overload frame R D 7 bits 262 User s Manual U12670EE3VOUDOO Chapter 16 CAN Controller 8 Interframe space This sequence is inserted after data frames remote frames error frames and overload frames in the serial bitstream on the bus to indicate start or end of
34. 70 3 3 1 Relative addressing 2 70 3 3 2 Immediate addressing 71 3 3 3 Table indirect 0 72 3 3 4 Register addressing 4 73 3 4 Address Addressing 74 3 4 1 Implied 0 4 454 74 3 4 2 Register addressing 75 3 4 3 Direct addressing 76 3 4 4 Short direct 51 0 77 3 4 5 Special function register SFR addressing 78 3 4 6 Register indirect 0 79 3 4 7 Based 0 80 3 4 8 Based indexed 0 81 3 4 9 Stack addressing 2 4 82 Chapter 4 Port Functions seen uo uh RI 83 441 amp rcl Saree edhe augus 83 42 Port 86 4 2 1 2 hoa ee ee M ee
35. Vpp supply current Vpp supply current Vpp 10 0 V Write time per byte twRT Number of rewrites Erase time TERASE Programming temperature Data Retention 2 Serial write operation characteristics Parameter Conditions Vpp set time tPSRON Vpp high voltage Vpp f set time from Vpp 7 ipRPSR Vpp high voltage RESET set time from Vpp T 1 Vpp high voltage Vpp count start time from t RESET 7 REGE Count execution time COUNT Vpp counter high level width tcu Vpp counter low level width Vpp counter noise elimination width iNEW 484 User s Manual U12670EE3VOUDOO Chapter 25 Electrical Specifications Flash Memory Write Mode Set Timing VoD tDRPSR gt tCOUNT RESET input 0v User s Manual U12670EE3VOUDOO 485 MEMO 486 User s Manual U12670EE3VOUDOO Chapter 26 Package Drawing 100 Pin Plastic QFP 14 x 20 mm Note Each lead centerline is located within 0 15 mm 0 006 inch of its true position T P at maximum material condition Remark The shape and material of the ES product is the same as the mass produced product Detail of lead end P100GF 65 3BA1 2 Item Millimet
36. b Capture compare control register 0 CRCO CRC02 CRCO1 2 00 as compare register 16 bit timer output control register 04 1 50 LVRO 01 TOEO TOCO Enables TOO output Reverses output on coincidence between TMO CROO Specifies initial value of TOO output F F Does not reverse output on coincidence between TMO and CRO1 Remark 0 1 When these bits are reset to 0 or set to 1 the other functions can be used along with the square wave output function For details refer to Figures 6 2 6 3 and 6 4 User s Manual U15251EE3VOUDOO 143 144 Count clock TMO count value CROO 00 TOO output Chapter6 16 Bit Timer Event Counter 0 Figure 6 25 Timing of Square Wave Output Operation aleli 1 ooo0HX0001HX0002HX 1 1 002 KN 1X E User s Manual U15251EE3VOUDOO ILI E 5 E Chapter 6 16 Bit Timer Event Counter 0 6 5 16 Bit Timer Event Counter 0 Operating Precautions 1 2 3 Error on starting timer An error of up to 1 clock occurs before the coincidence signal is generated after the timer has been started This is because the 16 bit timer register TMO is started asynchronously in respect to the count pulse Figure 6 26 Start Timing of 16 Bit Timer Register Count pulses
37. pPD780948 78K 0 series Subseries User s Manual This Manual Instruction Pin functions CPU functions Internal block functions Instruction set Interrupt Explanation of each instruction Other on chip peripheral functions How to Read This Manual Before reading this manual you should have general knowledge of electric and logic circuits and microcontrollers When you want to use this manual as the manual for A products and A1 products Only the quality grade differs between A and A1 products Read the part number as follows uPD780948 uPD780948 A uPD780948 A1 When you want to understand the function in general Read this manual in the order of the contents How to interpret the register format For the bit number enclosed in square the bit name is defined as a reserved word in RA78K 0 and in CC78K 0 and defined the header file of hte IAR compiler To make sure the details of the registers when you know the register name Refer to Appendix C Related Documents The related documents indicated in this publication may include preliminary versions However preliminary versions are not marked as such User s Manual U12670EE3VOUDOO 5 Preface Related documents for PD780948 Subseries Document name pgPD780948 Subseries Users Manual Document No Japanese Planned English This manual 78K 0 Series Users Manual Instruction IEU 849 U12326E 78K 0 Series
38. Appendix A Development Tools Figure A 1 Development Tool Configuration a When using the in circuit emulator IE 78K0 NS A Language Processing Software NH Assembler package C compiler package C library source file Device file Debugging Tool System simulator Integrated debugger Device file Embedded Software Real time OS OS Host Machine PC Interface adapter PC card interface etc Flash Memory Write Environment In circuit Emulator Emulation board Flash programmer Flash memory write adapter On chip flash Emulation probe memory version Conversion socket or conversion adapter Target system Power supply unit Remark Items in broken line boxes differ according to the development environment See A 3 1 Hardware 492 User s Manual U12670EE3VOUDOO Appendix A Development Tools A 1 Language Processing Software NEC Software RA78K 0 Assembler Package This assembler converts programs written in mnemonics into an object codes executa ble with a microcontroller Further this assembler is provided with functions capable of automatically creating symbol tables and branch instruction optimization This assembler should be used in combination with an optional device file lt Precaution when using RA78K 0 PC environment gt This assembler package is a DOS based application It can also be used in Windows however b
39. FF34H Pull up resistor option register 4 PU4 RW x x 00H FF37H resistor option register 7 PU7 RW x x 00H FF3DH resistor option register 13 PU13 RN x x 00H FF40H Clock output select register CKS x 00H FF41H Watch timer mode register WTM RW x x 00H FF42H X Watchdog timer clock selection register WDCS x 00H FF47H Memory expansion mode register MEM RW x x 00H User s Manual U12670EE3VOUDOO 67 Chapter 3 CPU Architecture Table 3 3 Special Function Register List 2 3 Manipulation Bit Address SFR Name Unit 1 bit 8 bit 16 bit Ext INT rising edge enable register Ext INT falling edge enable register Note 1 LCD timer mode control register Port function register 2 Port function register 5 Port function register 7 Port function register 12 Port function register 13 Port function register 14 16 bit timer mode control register 0 Prescaler mode register 0 Capture Compare control register 0 16 bit timer output control register 0 16 bit timer mode control register 2 Prescaler mode register 2 XI X X X X X X X X X X X X Capture Compare control register 2 16 bit timer counter register 2 16 bit capture register 20 16 bit capture register 21 16 bit capture register 22 D D D D D D D D XI X X XI X x X x 8 bit timer mode c
40. FOOOH EFFFH CALLT Table Area Internal Flash EEPROM 144 i 61440 x 8 bits Vector Table Area 0000H Note Inthe expansion RAM between F400H and F7DFH it is not possible to do code execution 56 User s Manual U12670EE3VOUDOO Chapter 3 CPU Architecture 3 1 1 Internal program memory space The internal program memory space stores programs and table data This is generally accessed by the program counter PC The uPD780948 Subseries have various size of internal ROMs or Flash EPROM as shown below Table 3 1 Internal ROM Capacities Internal ROM Part Number Type Capacity 780948 Mask ROM 61440 x 8 bits uPD78F0948 Flash EEPROM 61440 x 8 bits The internal program memory is divided into three areas vector table area CALLT instruction table area and CALLF instruction table area These areas are described on the next page User s Manual U12670EE3VOUDOO 57 Chapter 3 CPU Architecture 1 Vector table area The 64 byte area 0000H to 00 is reserved as a vector table area The RESET input and pro gram start addresses for branch upon generation of each interrupt request are stored in the vector table area Of the 16 bit address low order 8 bits are stored at even addresses and high order 8 bits are stored at odd addresses Table 3 2 Vectored Interrupts Vector Table Address Interrupt Request INWDT INTAD INTOVF INTTM20 2 22 INTPO
41. If an interrupt request with the same or higher priority than that of the interrupt being serviced is gener ated it is acknowledged as a multiple interrupt In the case of an interrupt with a priority lower than that of the interrupt being processed it is not acknowledged as a multiple interrupt An interrupt request not acknowledged as a multiple interrupt due to interrupt disable or a low priority is reserved and acknowledged following one instruction execution of the main processing after the com pletion of the interrupt being serviced During non maskable interrupt servicing multiple interrupts are not enabled Table 19 4 on page 383 shows an interrupt request enabled for multiple interrupt during interrupt servic ing and Figure 19 13 on page 384 shows multiple interrupt examples 382 User s Manual U12670EESVOUDOO Chapter 19 Interrupt Functions Table 19 4 Interrupt Request Enabled for Multiple Interrupt during Interrupt Servicing Maskable Interrupt Request Maskable Interrupt Non maskable Request Interrupt xxPR 0 xxPR 1 Request Interrupt being serviced IE 1 IE 1 Non maskable interrupt D D D D D ISP 0 E E D D D Maskable Interrupt ISP 1 E E D E D Software interrupt E E D E D Remarks 1 E Multiple interrupt enable 2 D Multiple interrupt disable 3 ISP and IE are the flags contained in PSW ISP 0 An interrupt with higher priority is being serviced ISP 1
42. NOP Note NOP NOP enable interrupts bears xis resume with application code Note The interrupt acknowledge needs some clock cycles depends on host core In order to prevent that the variable wakeup interrupt occurred is already read before DI becomes effective some NOP instruction have to be inserted As well the number of NOP instructions after the CPU Stop instruction is dependent on the host core The given example is tailored for 78KO 322 User s Manual U12670EE3VOUDOO Chapter 16 CAN Controller 16 17 4 DCAN Stop Mode The CPU requests this mode from DCAN The procedure equals the request for DCAN Sleep mode The DCAN will signal with the WAKE bit if the request was granted or if it is not possible to enter the DCAN Stop mode due to ongoing bus activities After a successful switch to the DCAN Stop mode the CPU can safely go into halt watch or stop mode without any precautions The DCAN can only be woken up by the CPU Therefore the CPU needs to clear the SLEEP bit in the CANC register This mode reduces the power consumption of the DCAN to a minimum Code example DCAN_Stop_Mode void CANES 0x02 clear Wake bit CANC 0x06 request DCAN Stop mode while CANES amp 0x02 check if DCAN Stop mode was accepted CANES 0x02 try again to get DCAN into stop mode CANC 0x06 User s Manual U12670EE3VOUDOO 323 Chapter 16 CAN Coniroller 16 18 Functional Descript
43. R W R W R W R W R W R W R W R W R W The DCAN stores received data bytes in this memory area Only those data bytes which are actually received and match with the identifier are stored in the receive buffer memory area If the DLC is less than eight the DCAN will not write additional bytes exceeding the DLC value up to eight The DCAN stores a maximum of 8 bytes according to the CAN protocol rules even when the received DLC is greater than eight User s Manual U12670EE3VOUDOO 291 Chapter 16 CAN Coniroller 16 12 Mask Function Table 16 22 Mask Function Name dies Bi ors ors ore ori Unused ID standard part ID standard part 0 0 ID extended part ID extended part ID extended part 0 0 0 Unused Unused Unused Unused Unused Unused Unused Unused Unused Receive message buffer 0 and buffer 2 can be switched for masked operation with the mask control register MASKC In this case the message does not hold message identifier and data of the frame Instead it holds identifier and RTR mask information for masked compare operations for the next higher message buffer number In case the global mask is selected it keeps mask information for all higher message buffer numbers A mask does not store any information about identifier length Therefore the same mask can be used for
44. built in capacitor CSAC4 00MGCA CSTCC4 00MGA built in capacitor CSA8 00MGA CST8 00MGWA built in capacitor CSAC8 00MGCA CSTCC8 00MGA PBRC4 00BRVA built in capacitor PBRC8 00BRVA Main System Clock Crystal Resonator Product Name CX 5FW 4 MHz Frequency MHz Recommended Oscillator Constant C1 pF C2 pF R1 KQ Remarks HC 49 U S 8 MHz CX 11F 8 MHz NDK AT 51 KDS Daishinku AT 49 SaRonix Caution HC49 U13 HC49 L HC49 S The oscillator constants and oscillator voltage range indicate conditions for stable oscillation but do not guarantee oscillation frequency accuracy If oscillation fre quency accuracy is required for actual circuits it is necessary to adjust the oscilla tion frequency of the oscillator in the actual circuit Please contact the manufacturer of the resonator to be used User s Manual U12670EE3VOUDOO 443 Chapter 25 Electrical Specifications 2 pPD780948 A1 40 C to 110 C 4 0 to 5 5 V Resonator Recommended Circuit Parameter Conditions Oscillator frequency Vpp 4 0 to 5 5 V fy Note 1 Ceramic resonator Oscillation stabiliza peo aa i i Note 2 oscillator voltage ERMIS range MIN 4 0 V Oscillator frequency Vpp 4 0 to 5 5 V f Note 1 Crystal x resonator Oscillation stabiliza ane 2 i i No
45. uPD780065 40K to 48K 3 ch time divi sion UART 1 ch uPD780078 48K to 60K 4 ch UART 1 ch uPD780034A uPD780024A 8K to 32K 3 ch UART 2 ch uPD78083 8K to 16K 3 ch UART 1 ch 1 ch UART 1 ch PD780988 16K to 60K 2 ch UART 2 ch uPD780208 32K to 60K uPD780232 16K to 24K uPD78044H 32K to 48K 2 ch uPD78044F 16K to 40K 1 ch 2 ch PD780338 uPD780328 uPD780318 48K to 60K PD780308 48K to 60K 2 ch UART 1 ch uPD78064B 32K 3 ch time divi sion UART 1 ch uPD78064 16K to 32K 2 ch UART 1 ch uPD780948 60 K uPD78098B 40K to 60K uPD780816 32K to 60K 3 ch UART 1 ch 2 ch UART 1 ch uPD780958 48K to 60K 2 ch UART 1 ch uPD780852 32K to 40K uPD780828B 32K to 60K 3 ch UART 1 ch Note 16 bit timer 2 channels 10 bit timer 1 channel 32 User s Manual U12670EE3VOUDOO Chapter 1 1 7 Block Diagram TIOO TOO TIO1 16 bit Timer 0 20 21 l T122 16 bit Timer 2 T2PO TI50 TO50 8 bit Timer 50 TIB1 TO51 8 bit Timer 51 Watch Timer 1 Watchdog Timer 510 500 Serial Interface SCKO Channel 0 911 801 Serial Interface SCK1 Channel 1 RxD TxD ANIO ANI7 AVss AVDD AVREF ADO
46. undefined undefined undefined undefined The identifier of the receive message has to be defined during the initialization of the DCAN The DCAN uses this data for the comparison with the identifiers received on the CAN bus For normal message buffers without mask function this data is only read by the DCAN for comparison In combina tion with a mask function this data is overwritten by the received ID that has passed the mask Address After Reset R W R W R W R W R W R W The identifier of the receive messages should not be changed without being in the initialization phase or setting the receive buffer to redefinition in the RDEF register because the change of the contents can happen at the same time when the DCAN uses the data for comparison This can cause inconsistent data stored in this buffer and also the ID part can be falsified in case of using mask function Remarks 1 The unused parts of the identifier IDREC1 bit 4 0 always and IDREC4 bit 5 0 in case of extended frame reception may be written by the DCAN to 0 They not released 290 for other use by the CPU RTRggc is the received value of the RTR message bit when this buffer is used together with a mask function By using the mask function a successfully received identifier overwrites the IDRECO and IDREC1 registers for standard frame format and the IDRECO to IDREC4 registers for extended frame format For the RTRggc bit exists two m
47. 2nd Operand laddr16 1st Operand rp MOvwWNete sfrp MOVW saddrp MOVW laddr16 MOVW sp MOVW Note Only when rp BC DE HL 3 Bit manipulation instructions 1 AND1 OR1 XOR1 SET1 CLR1 NOT1 BT BF BTCLR Table 24 5 Bit manipulation instructions 2nd Operand 1st Operand sfr bit saddr bit PSW bit HL bit addr16 sfr bit saddr bit PSW bit HL bit 434 User s Manual U12670EE3VOUDOO Chapter 24 Instruction Set 4 Call instructions branch instructions CALL CALLF CALLT BR BC BNC BZ BNZ BT BF BTCLR DBNZ Table 24 6 Call instructions branch instructions 2nd Operand 1st Operand laddr16 addr11 addr5 addr16 Basic instruction BR ian CALLT BNC Compound instruction Other instructions ADJBA ADJBS BRK RET RETI RETB SEL NOP El DI HALT STOP User s Manual U12670EE3VOUDOO 435 MEMO 436 User s Manual U12670EE3VOUDOO Chapter 25 Electrical Specifications 25 1 Absolute Maximum Ratings 1 pPD780948 A 25 C Parameter Symbol Conditions Rating Unit 0 3 to 6 0 Supply voltage AVpp AVngr Vpp 0 3 to Vpp 0 3 0 3 to 0 3 P07 P10 P17 P20 P26 P30 P34 P40 P47 P50 P57 P64 P65 P67 P70 P77 P120 P127 P130 P137 P140 P147 X1 X2 CL1 RESET Output voltage 0 3 to Vpp 0 3 I
48. Asian Nations except Philippines NEC Electronics Singapore Pte Ltd Fax 65 6250 3583 Japan NEC Semiconductor Technical Hotline Fax 81 44 435 9608 would like to report the following error make the following suggestion Document title Document number Page number If possible please fax the referenced page or drawing Document Rating Excellent Clarity o Technical Accuracy Organization m
49. Figure 19 1 Figure 19 2 Figure 19 3 Figure 19 4 Figure 19 5 Figure 19 6 Figure 19 7 Figure 19 8 Figure 19 9 Figure 19 10 Figure 19 11 Figure 19 12 Figure 19 13 Figure 19 14 Figure 20 1 Figure 20 2 Figure 20 3 Figure 20 4 Figure 20 5 Figure 20 6 Figure 20 7 Figure 20 8 Figure 20 9 Figure 21 1 Figure 21 2 Figure 21 3 Figure 21 4 Figure 21 5 Figure 21 6 Figure 22 1 Figure 22 2 Figure 22 3 Figure 22 4 Figure 23 1 Example of LCD Drive Voltage Supply from 342 Example of LCD Drive Power Supply external 343 Static LCD Display Pattern and Electrode 344 Static LCD Panel Connection Example sss 345 Static LCD Drive Waveform 2 242424 346 2 Time Division LCD Display Pattern and Electrode Connections 347 2 Time Division LCD Panel Connection 348 2 Time Division LCD Drive Waveform Examples 1 2 Bias Method 349 3 Time Division LCD Display Pattern and Electrode Connections 350 3 Time Division LCD Panel Connection Example 351 3 Time Division LCD Drive Waveform Examples
50. IN OUT 53 MEMO 54 User s Manual U12670EE3VOUD00 Chapter 3 CPU Architecture 3 1 Memory Space The memory map of the PD780948 is shown in Figure 3 1 Figure 3 1 Memory Map of the 780948 FFFFH Special Function Registers FF20H SFRs 256 x 8 bits FF1FH FFOOH FEEEH General Registers FEEOH 32 x 8 bits FEDFH Internal High speed RAM 1024 x 8 bits FE20H FBOOH FAFFH Not usable FA80H FA7FH LCD Display RAM FA58H 40 x 4 bits FA57H Not usable Program Area 7 F7DFH CALLF Entry Area Internal Expansion RAM 992 x 8 bits Program Area F400H F3FFH External Memory FOOOH EFFFH CALLT Table Area Internal ROM Vector Table Area 0000H Note Inthe expansion RAM between F400H and F7DFH it is not possible to do code execution User s Manual U12670EE3VOUDOO 55 Chapter 3 CPU Architecture The memory map of the uPD78F0948 is shown in Figure 3 2 Figure 3 2 Memory Map of the uPD78F0948 FFFFH Special Function Registers FF20H SFRs 256 x 8 bits FF1FH FFOOH General Registers FEEOH 32 x 8 bits FEDFH Internal High speed RAM 1024 x 8 bits FE20H FBOOH Not usable FA80H FA7FH LCD Display RAM FA58H 40 x 4 bits FA57H Not usable Program Area 7 F7DFH CALLF Entry Area Internal Expansion RAM 992 x 8 bits Program Area F400H F3FFH External Memory
51. In accordance with the dis play pattern in Figure 17 20 selection and non selection voltages must be output to pins S28 and S29 as shown in Table 17 9 at the COMO to COM3 common signal timings Table 17 9 Selection and Non Selection Voltages COMO to COM3 Segment 28 29 Common COMO 5 Remark S Selection NS Non selection From this it can be seen that 1101 must be prepared in the display data memory address FAOBH cor responding to S28 Examples of the LCD drive waveforms between S28 and the COMO and COM1 signals are shown in Figure 17 22 for the sake of simplicity waveforms for COM2 and COMG have been omitted When S28 is at the selection voltage at the COMO selection timing it can be seen that the Vi cp V cp AC square wave which is the LCD illumination ON level is generated Figure 17 20 4 Time Division LCD Display Pattern and Electrode Connections Sen 1 2 CW O coms Sen 1 Remark n 0to18 354 User s Manual U12670EE3VOUDOO Chapter 17 LCD Controller Driver 4 Time Division LCD Panel Connection Example Figure 17 21 COM3 COM2 1 COMO seqouis 50 51 52 53 54 55 56 57 58 59 510 511 Aiowaw geq joued 101 m Lo N 0 D e e ej e 225 9 0 520 521 522 523 524 525
52. NEC User s Manual PD780948 Subseries 8 bit Single Chip Microcontroller uPD780948 uPD78F0948 Documen t No U12670EE3VOUDOO Date Published April 2003 NEC Corporation 2003 Printed in Germany NOTES FOR CMOS DEVICES PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note Strong electric field wnen exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it once when it has occurred Environmental control must be adequate When it is dry humidifier should be used It is recommended to avoid using insulators that easily build static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work bench and floor should be grounded The operator should be grounded using wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with semiconductor devices on it HANDLING OF UNUSED INPUT PINS FOR CMOS Note No connection for CMOS device inputs can be cause of malfunction If no connection is provided to the input pins itis possible that an internal input level may be generated due to noise etc hence causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input lev
53. Receive Transmit control 2 control parity parity INTST check addition generator User s Manual U12670EE3VOUDOO 233 Chapter 15 Serial Interface UART 15 2 Serial Interface UART Configuration The UART includes the following hardware Table 15 1 Configuration of UART Item Configuration Transmit shift register 1 50 Registers Receive shift register 1 RXSO Receive buffer register RXBO Asynchronous serial interface mode register ASIMO Control registers Asynchronous serial interface status register ASISO Baud rate generator control register BRGCO 1 Transmit shift register 1 TXSO This register is for setting the transmit data The data is written to TXSO for transmission as serial data When the data length is set as 7 bits bits 0 to 6 of the data written to TXSO are transmitted as serial data Writing data to TXSO starts the transmit operation TXSO can be written via an 8 bit memory manipulation instructions It cannot be read When RESET is input its value is FFH Cautions 1 Do not write to TXSO during a transmit operation 2 The same address is assigned to TXSO and the receive buffer register RXBO A read operation reads values from RXBO 2 Receive shift register 1 RXSO This register converts serial data input via the RXD pin to parallel data When one byte of the data is received at this register the receive data is transferred to the receive buff
54. Sampling time EP A D converter operation Sampling A D conversion SAR Conversion Undefined result Conversion result INTAD A D conversion operations are performed continuously until bit 7 ADCS1 of the A D converter mode register ADM1 is reset to 0 by software If a write operation to the ADM1 and analog input channel specification register ADS1 is performed during A D conversion operation the conversion operation is initialized and if the ADCS1 bit is set to 1 conversion starts again from the beginning ADCR1 RESET input sets the A D conversion result register ADCR1 to 00H 210 User s Manual U12670EE3VOUDOO Chapter 12 A D Converter 12 4 2 Input voltage and conversion results The relation between the analog input voltage input to the analog input pins ANIO to ANI7 and the A D conversion result stored in the A D conversion result register ADCR1 is given by the following expression VIN ADCR1 INT Wop X 256 0 5 or AVpp AV ADCR1 0 5 X Viy lt ADCR1 0 5 X gt 256 256 where INT Function which returns integer part of value in parentheses VIN Analog input voltage AVpp AVngr 4 AVpp pin voltage ADCR 1 A D conversion result register ADCR1 value Figure 12 8 Relation between Analog Input Voltage and A D Conversion Result on page 212 shows the relation between the analog input voltage and the A D conversion result
55. Status before HALT mode is held PSTB Low level WR RD User s Manual U12670EE3VOUDOO High level 405 Chapter 21 Standby Function 2 HALT mode clear The HALT mode can be cleared with the following four types of sources a Clear upon unmasked interrupt request An unmasked interrupt request is used to clear the HALT mode If interrupt acknowledge is ena bled vectored interrupt service is carried out If disabled the next address instruction is executed Figure 21 3 HALT Mode Clear upon Interrupt Generation Wait Standby Release Signal lap en rte it cial sati Se Operating Mode HALT Mode Wait Operating Mode Clock Oscillation Remarks 1 The broken line indicates the case when the interrupt request which has cleared the standby status is acknowledged 2 Wait time will be as follows When vectored interrupt service is carried out 8 to 9 clocks When vectored interrupt service is not carried out 2to 3 clocks b Clear upon non maskable interrupt request The HALT mode is cleared and vectored interrupt service is carried out whether interrupt acknowl edge is enabled or disabled 406 User s Manual U12670EE3VOUDOO Chapter 21 Standby Function c Clear upon RESET input As is the case with normal reset operation a program is executed after branch to the reset vector address Figure 21 4 HALT Mode Release
56. These pins are dual function pins and serve as segment signal output of LCD controller driver RESET input sets the input mode The port 12 block diagram is shown in Figure 4 10 Caution When used as segment lines set the port function PF12 according to its functions Figure 4 10 P120 to P127 Configurations RD WRpeort A P120 S23 2 127 516 Output Latch P120 to P127 Internal bus PM120 to PM127 Dual Function Remarks 1 Port mode register 2 RD Port 12 read signal 3 WR Port 12 write signal User s Manual U12670EE3VOUDOO 95 4 2 10 Port 13 Chapter 4 Port Functions This is an 8 bit input output port with output latches Input mode output mode can be specified in 1 bit units with a port mode register 13 When P130 to P137 are used as input pins an on chip pull up resis tor can be connected bit wise with the pull up resistor option register PU13 Dual functions include segment signal output of LCD controller driver RESET input sets the input mode Port 13 block diagram is shown in Figure 4 11 Caution When used as segment lines set the port function PF13 according to its functions Figure 4 11 P130 to P137 Configurations Internal bus Remarks 1 2 3 4 96 PU PM RD WR Output Latch P130 to P137 PM130 to PM137 Dual Function Pull up resistor option register Por
57. pin Figure 18 7 Sound Generator Output Operation Timing n n n n n n Timer 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Comparator 1 _ m coincidence SGOF 366 User s Manual U12670EE3VOUD00 19 1 Chapter 19 Interrupt Functions Interrupt Function Types The following three types of interrupt functions are used 1 2 3 Non maskable interrupt This interrupt is acknowledged unconditionally even in a disabled state It does not undergo inter rupt priority control and is given top priority over all other interrupt requests It generates a standby release signal The non maskable interrupt has one source of interrupt request from the watchdog timer Maskable interrupts These interrupts undergo mask control Maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specify flag register PROL PROH PR1L and PR1H Multiple high priority interrupts can be applied to low priority interrupts If two or more interrupts with the same priority are simultaneously generated each interrupts has a predetermined priority see Table 19 1 Interrupt Source List on page 368 A standby release signal is generated The maskable interrupt has seven sources of external interrupt requests and fifteen sources of internal interrupt requests Software interrupt This is a vectored interrupt to be generated by e
58. ra tasTRD gt a RDL1 User s Manual U12670EE3VOUD00 RDH 8 A15 ADO AD7 ASTB A8 A15 ADO AD7 ASTB Lower 8 bit address Chapter 25 Electrical Specifications External data access no wait Upper lower 8 bit address taps tASTH gt lt lt tasTWR tasTRD twos lt gt m a tRDL2 4 iwRwD External data access wait insertion Upper lower 8 bit address Lower 8 bit t ADD2 address 7 Hi Z taps 4 2 tASTH tasTRD 4 iRDWD gt a twos a twRwD t tasTWR gt a twRADH gt User s Manual U12670EE3VOUDOO C 471 25 6 3 Serial Interface 1 pPD780948 A Chapter 25 Electrical Specifications 40 C to 85 C Vpp 4 0 to 5 5 V 3 wire serial I O mode SCKO Internal clock output Parameter SCKO cycle time tkcy1 Conditions 1000 5 high low level width Iia tkcy1 2 50 510 setup time to SCKO tsik1 100 510 hold time from SCKO 7 tksi1 400 500 output delay time from SCKO 4 tkso1 C 100 pF Note Note C is the load capacitance of 500 SCKO output line 3 wire serial I O mode SCKO External clock output Parameter SCKO cycle time SCKO high low level width
59. wj A BR A A sfr bit addr16 A bit addr16 PSW bit addr16 HL bit addr16 B addr16 C addr16 saddr addr16 IE lt 1 Enable Interrupt IE O Disable Interrupt Set HALT Mode Set STOP Mode When the internal high speed RAM area is accessed or instruction with no data access When an area except the internal high speed RAM area is accessed Except r A Only when rp BC DE or HL 1 One instruction clock cycle is one cycle of the CPU clock fcpu selected by the PCC register 2 This clock cycle applies to internal ROM program nis the number of waits when external memory expansion area is read from mis the number of waits when external memory expansion area is written to 432 User s Manual U12670EE3VOUDOO Chapter 24 Instruction Set 24 3 Instructions Listed by Addressing Type 1 8 bit instructions MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MULU DIVUW INC DEC ROR ROL RORC ROLC ROR4 ROL4 PUSH DBNZ Table 24 3 8 bit instructions 2nd Operand HL byte saddr addr16 HL addr16 HL C Note Exceptr A User s Manual U12670EE3VOUDOO 433 Chapter 24 Instruction Set 2 16 bit instructions MOVW XCHW ADDW SUBW CMPW PUSH POP INCW DECW Table 24 4 16 bit instructions
60. xr instruction instructions fy 8fyz instruction 20 instructions fy 16fyz instruction 10 instructions fy 32fyz instruction 5 instructions fy 4fyz instruction 39 instruct ions fy 8fy instruction 20 instructions fy 16fyz instruction 10 instructions fy 32fyz instruction 5 instructions fy 64fy7 instruction 3 instructions Selection of the CPU clock cycle scaling factor PCCO to PCC2 and switchover from the main system clock to the subsystem clock changing CSS from 0 to 1 should not be performed simultaneously Simultaneous setting is possible however for selec tion of the CPU clock cycle scaling factor PCCO to PCC2 and switchover from the subsystem clock to the main system clock changing CSS from 1 to 0 User s Manual U12670EE3VOUDOO 117 Chapter 5 Clock Generator 5 6 2 System clock and CPU clock switching procedure This section describes switching procedure between system clock and CPU clock Figure 5 7 System Clock and CPU Clock Switching RESET Interrupt Request Signal SystemClock fx fx fxr fx CPUClock Minimum Maximum Speed Subsystem Clock High Speed Speed Operation Operation Operation Operation Wait 16 3 ms 8 0 MHz Internal Reset Operation The CPU is reset by setting the RESET signal to low level after power on After that when reset is released by setting the RESET signal to high level main syst
61. 1 One instruction clock cycle is one cycle of the CPU clock selected by the PCC register 2 This clock cycle applies to internal ROM program 3 nis the number of waits when external memory expansion area is read from 4 mis the number of waits when external memory expansion area is written to User s Manual U12670EE3VOUDO00 425 Instruction Mnemonic Group Operands rp word Chapter 24 Co Instruction Set Table 24 2 Operation List 2 8 Operation lt word saddrp word saddrp lt word sfrp word sfrp lt word AX saddrp AX lt saddrp saddrp AX saddrp lt AX AX sfrp AX lt sfrp sfrp AX sfrp lt AX AX rp Note 4 pol po po po aA AX rp rp AX Note 4 A A lt AX AX laddr16 lt addr16 laddr16 4 oj addr16 lt AX rp Note 4 A byte AX x rp A CY A byte saddr byte saddr lt saddr byte A r Note 3 A CY A r r r A A CY lt A saddr A laddr 6 A lt addr16 A HL A HL byte A CY lt HL byte A HL B A CY A HL A CY lt HL A HL A CY A HL C A byte A CY lt A byte CY saddr byte saddr
62. 17 8 8 3 time division display example 350 17 4 4 time division display example 354 17 9 Cautions on Emulation 357 17 9 1 LCD timer control register 357 Chapter 18 Sound Generator 359 18 1 Sound Generator 359 18 2 Sound Generator 360 18 3 Sound Generator Control Registers 360 18 4 Sound Generator 365 18 4 1 To output basic cycle signal SGOF without amplitude 365 18 4 2 To output basic cycle signal SGO with amplitude 366 Chapter 19 Interrupt 367 19 1 Interrupt Function 367 19 2 Interrupt Sources and 368 19 3 Interrupt Function Control 371 19 4 Interrupt Servicing 377 19 4 1 Non maskable interrupt request acknowledge 377 19 4 2 interrupt re
63. 526 527 528 529 530 geq 531 532 533 534 535 536 537 538 539 355 User s Manual U12670EE3VOUDOO Chapter 17 LCD Controller Driver Figure 17 22 4 Time Division LCD Drive Waveform Examples 1 3 Bias Method TF Vico Vici COMO Vice Vss1 Vico Vict COM1 Vice Vss1 Vico Vici COM2 Vice Vss1 Vico Vici COMS Vice Vssi Vico Vici S28 Vice Vss1 Vicp 1 3Vicp 528 0 1 Vicp 1 3Vicp COM1 S28 0 1 3Vicp Vicp 356 User s Manual U12670EE3VOUD00 Chapter 17 LCD Controller Driver 17 9 Cautions on Emulation To perform debugging with an in circuit emulator the LCD timer control register LCDTM must be set LCDTM is a register used to set on the emulation board 17 9 1 LCD timer control register _ LCDTM is a write only register that controls supply of the LCD clock Unless LCDTM is set the LCD controller driver does not operate Therefore set bit 1 TMC21 of LCDTM to 1 when using the LCD controller driver Figure 17 23 LCD Timer Control Register LCDTM Format Symbol 7 6 0 Address After Reset R W 5 4 3 2 1 LCD Clock Supply Control LC
64. AX BC DE and HL They can be described in terms of function names X A C B E D L H AX BC DE and HL and absolute names RO to R7 and RPO to RP3 Register banks to be used for instruction execution are set with the CPU control instruction SEL RBn Because of the 4 register bank configuration an efficient program can be created by switching between a register for normal processing and a register for interruption for each bank Figure 3 10 General Register Configuration a Absolute Name 16 Bit Processing 8 Bit Processing RP3 RP2 RP1 RPO 15 0 b Function Name FEFFH FEF8H FEEOH FEE8H FEEOH 16 Bit Processing 8 Bit Processing _ DE BC AX 15 0 User s Manual U12670EE3VOUDO00 65 FEFFH FEF8H FEFOH FEE8H FEEOH Chapter 3 CPU Architecture 3 2 3 Special function register SFR Unlike a general register each special function register has special functions It is allocated in the FFOOH to FFFFH area The special function registers can be manipulated in a similar way as the general registers by using operation transfer or bit manipulate instructions The special function registers are read from and writ ten to in specified manipulation bit units 1 8 and or 16 depending on the register type Each manipulation bit unit can be specified as follows 66 1 bit manipulation Describe t
65. Capture read signal n CROn interrupt value X X N i N Capture operation Remark nz0to2 User s Manual U12670EE3VOUDOO 159 3 Chapter 7 16 Bit Timer 2 Valid edge setting Set the valid edge of the Tl2m P3m pin after setting bit 2 TMC22 of the 16 bit timer mode control register to 0 and then stopping timer operation Valid edge setting is carried out with bits 2 to 7 ESm0 and ESm1 of the prescaler mode register PRM2 Remark mz0to2 4 5 160 Occurrence of INTTM2n INTTM2n occurs even if no capture pulse exists immediately after the timer operation has been started 02 of TMC2 has been set to 1 with a high level applied to the input pins 20 to 22 of 16 bit timer 2 This occurs if the rising edge with ESn1 and ESn0 of PRMO set to 0 1 or both the rising and falling edges with ESn1 and ESnO of PRM2 set to 1 1 are selected INTTM2n does not occur if a low level is applied to TI20 to TI22 Timer stop When the timer TM2 is disabled the value of the timer register will be undefined User s Manual U12670EE3VOUD00 Chapter 8 8 Bit Timer Event Counters 50 and 51 8 1 8 Bit Timer Event Counters 50 and 51 Functions The timer 50 and 51 have the following functions Interval timer External event counter e Square wave output PWM output 1 8 bit interval timer Interrupts are generated at the present time intervals Table 8 1 8 Bit Timer Event Counter 50 Interval Times M
66. Chapter 9 Watch Timer 1 Watch timer When the main system clock or subsystem clock is used interrupt requests INTWT are generated at 0 5 second intervals 2 Interval timer Interrupt requests INTWTI are generated at the preset time interval Table 9 1 Interval Timer Interval Time When operated at When operated at Interval Time fy 8 00 MHz 32 768 KHz 24 512 us 488 us 1ms 2 ms 4 ms 8 19 ms 16 38 ms Remarks 1 fy Main system clock oscillation frequency 2 fw Watch timer clock frequency 9 2 Watch Timer Configuration The watch timer consists of the following hardware Table 9 2 Watch Timer Configuration Item Configuration Counter 5 bits x 1 Prescaler 9 bits x 1 Control register Watch timer mode control register WTM 186 User s Manual U12670EESVOUDOO Chapter 9 Watch Timer 9 3 Watch Timer Mode Register WTM This register sets the watch timer count clock the watch timer operating mode and prescaler interval time and enables disables prescaler and 5 bit counter operations WTM is set with an 1 bit or an 8 bit memory manipulation instruction RESET input sets WTM to OOH Figure 9 2 Watch Timer Mode Control Register WTM Format 1 2 7 6 5 4 3 2 1 0 Address Alter Reset WTM WTM7 6 WTM5 WTM4 WTM3 0 WTM1 RW FF41H 00H WTM7 Watch Timer Count Clock Selection Input clock set to fy 28 Inp
67. Effective value should be calculated as follows Effective value Peak value x Vduty Caution Product quality may suffer if the absolute maximum ratings are exceeded for even a single parameter or even momentarily That is the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage Therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded Remark The characteristics of the dual function pins are the same as those of the port pins unless otherwise specified User s Manual U12670EE3VOUDOO 439 Chapter 25 Electrical Specifications 25 2 Capacitance 1 pPD780948 A TA 25 C Vpp Vss 0 V Parameter Function Input f 1 MHz capacitance Other than measured pins 0 V P00 P07 P10 P17 P20 P26 P30 P33 P40 P47 P50 P57 Input output f 1 MHz P64 P65 P67 P70 P77 P100 capacitance Other than measured p103 P120 P127 P130 P137 P140 P147 P34 Remark The characteristics of the dual function pins are the same as those of the port pins unless otherwise specified 2 uPD780948 A1 TA 25 C Vpp Vss 0 V Parameter Function Input f21MHz capacitance Other than measured pins 0 V PO7 P10 P17 P20 P26 P30 P33 P40 P47 P50 P57 Input output Hc P64 P65 P67 P70 P77 P100 capacitance Other than measured p1
68. Internal Bus User s Manual U12670EE3VOUD00 106 Chapter 5 Clock Generator 5 3 Clock Generator Control Register The clock generator is controlled by the processor clock control register PCC 1 Processor clock control register PCC The PCC selects a CPU clock and the division ratio determines whether to make the main system clock oscillator operate or stop The PCC is set with an 1 bit or an 8 bit memory manipulation instruction RESET input sets the PCC to 04H Figure 5 2 Processor Clock Control Register Format 1 2 27s 6 lt 5 gt ds 3 2 1 0 Address Alter Reset R W CPU Clock Selection fx 0 25 us fx 2 0 5 us 0 0 fy 2 1 us 0 fx 2 2 us 1 f 2 4 us 2 122 us 0 0 0 0 1 Other than above Setting prohibited R CLS CPU Clock Status 0 Main system clock 1 Subsystem clock User s Manual U12670EE3VOUDOO 107 Cautions 1 2 3 Remarks 108 Chapter 5 Clock Generator Figure 5 2 Processor Clock Control Register Format 2 2 R W Main System Clock Oscillation Control 0 Oscillation possible 1 Oscillation stopped Bit 5 is a read only bit Bit 3 and bit 5 must be set to 0 When the CPU is operating on the subsystem clock MCC should be used to stop the main system clock oscillation A STOP instruction should not be used When external clock input is used MCC should not be set because the X2 p
69. Mask control register MASKC Sound generator control register SGCR Sound generator amplitude control register SGAM Sound generator buzzer control register SGBR Interrupt request flag register OL IFO Interrupt request flag register OH Interrupt request flag register 1L IFA Interrupt request flag register 1H Interrupt mask flag register OL p g reg MKO Interrupt mask flag register OH Interrupt mask flag register 1L E vee MK1 Interrupt mask flag register 1H Priority order specified flag OL Y P B PRO Priority order specified flag OH Priority order specified flag 1L y P d PR1 XI X X X X X X X X X X x Priority order specified flag 1H Memory size switching register IMS Internal expansion RAM size switching register IXS Memory expansion wait register MM Watchdog timer mode register WDTM Oscillation stabilisation time register OSTS XI X X X X X X X X X X X X X X X X X XI X XI X X X X X X X XIXI X XI X Processor clock control register PCC User s Manual U12670EE3VOUDOO 69 Chapter 3 CPU Architecture 3 3 Instruction Address Addressing An instruction address is determined by program counter PC contents The PC contents are normally incremented 1 for each byte automatically according to the number of bytes of an instruction to be fetched each time a
70. P25 RXD Input P26 TXD Input P30 20 Input P31 Port 3 21 Input Input Output P32 5 bit input output port 22 Input P33 input output mode can be specified bit wise PCL SGOA Input P34 SGO SGOF Input Port 4 8 bit input output port Input Output P40 P47 input output mode can be specified bit wise ADO AD7 Input If used as an input port a pull up resistor can be connected by software Port 5 8 bit input output port input output mode can be specified bit wise Input Output P50 P57 This port can be used in External Memory Expan 8 539 A15 S32 Input sion mode Register Not for external memory expan sion used ports can be used either for LCD or port function User s Manual U12670EE3VOUDOO 37 Input Output Input Output Pin Name Chapter 2 Pin Function uPD780948 Subseries Table 2 1 Pin Input Output Types 2 2 Function Port 6 3 bit output port input output mode can be specified bit wise Alternate Function Input Output P70 P77 Port 7 8 bit input output port input output mode can be specified bit wise If used as an input port a pull up resistor can be connected by software This port can be used as a segment signal output port or an I O port in 1 bit units by setting the port function register 31 S24 Input Output P120 P127 Port 12 8 bit input output port input output mode can be specified bit wise This por
71. P52 A10 S37 P53 A11 S36 P54 A12 S35 P55 A13 S34 P56 A14 S33 P57 A15 S32 CRxD 00 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 CTxD P70 S31 POO INTPO 79 71 530 PO1 INTP1 78 72 529 PO2 INTP2 77 P73 S28 2 76 74 527 PO4 INTPA TIO1 75 P75 S26 PO5 TIO0 TOO 74 P76 S25 06 50 050 73 77 524 P07 TI51 TO51 72 P120 S23 20 510 71 121 622 21 500 70 122 521 P22 SCKO 69 P123 S20 23 511 501 68 124 519 P24 SCK1 67 P125 S18 P25 RxD 66 P126 S17 P26 TxD 65 P127 S16 RESET 64 P130 S15 63 P131 S14 2 62 P132 S13 VPP IC P133 S12 CL1 CCLK P134 S11 CL2 P135 S10 Vss2 P136 S9 P137 S8 AVDD AVREF P140 S7 P10 ANIO P141 S6 P11 ANH P142 S5 P12 ANI2 P143 S4 P13 ANI3 P144 S3 P14 ANI4 P145 S2 51 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 484950 295 2888 52 858222280 222 gt 9 8 E amp EXzx xtttoo02 2 diisoooorseo DOR 0 Luc Lee ee a a aoa ag ag Cautions 1 Connect IC internally connected pin directly to Vss 2 AVpp AVrer pin should be connected Vpp 3 AVss pin should be connected User s Manual U12670EE3VOUDOO Remark Chapter 1 Outline uPD780948 Subseries When these devices are used in applications that require reduction of the noise generated from inside the microcontroller the implementation of noise reduction measures such as connecting th
72. PFEN 0 INTAD PFEN 1 First conversion Condition satisfied Remarks 1 n 0 1 4 2 m 0 1 4 214 User s Manual U12670EE3VOUD00 Chapter 12 A D Converter 12 5 A D Converter Precautions 1 Current consumption in standby mode A D converter stops operating in the standby mode At this time current consumption can be reduced by setting bit 7 ADCS1 of the A D converter mode register ADM1 to 0 in order to stop conversion Figure 12 10 shows how to reduce the current consumption in the standby mode Figure 12 10 Example Method of Reducing Current Consumption in Standby Mode App AD converter power supply AVREF P ch lt ADCS1 Series resistor string 21 KQ AVss 2 Input range of ANIO to ANI7 The input voltages of ANIO to ANI7 should be within the specification range In particular if a voltage higher than AVpp or lower than AVss is input even if within the absolute maximum rating range the conversion value of that channel will be undefined and the conversion values of other channels may also be affected 3 Contending operations a Contention between A D conversion result register ADCR1 write and ADCR1 read by instruction upon the end of conversion ADCR1 read is given priority After the read operation the new conversion result is written to ADCR1 b Contention between ADCR1 write and A D converter mode register ADM1 writ
73. PR 0 Higher priority level PR 1 Lower priority level IE 20 Interrupt request acknowledge disable 384 User s Manual U12670EE3VOUDOO Chapter 19 Interrupt Functions Figure 19 13 Multiple Interrupt Example 2 2 c Example 3 A multiple interrupt is not generated because interrupts are not enabled Main Processing INTxx INTyy Servicing Servicing PR 0 1 Instruction IE 0 Execution Because interrupts are not enabled in interrupt INTxx servicing an El instruction is not issued inter rupt request INTyy is not acknowledged and a multiple interrupt is not generated The INTyy request is reserved and acknowledged after 1 instruction execution of the main processing Remark PR 0 Higher priority level IE 0 Interrupt request acknowledge disable User s Manual U12670EE3VOUDOO 385 Chapter 19 Interrupt Functions 19 4 5 Interrupt request reserve Some instructions may reserve the acknowledge of an instruction request until the completion of the execution of the next instruction even if the interrupt request is generated during the execution The following list shows such instructions interrupt request reserve instruction MOV PSW byte MOV A PSW MOV PSW A MOV1 PSW bit CY MOV1 CY PSW bit ANDI CY PSW bit OR1 CY PSW bit CY PSW bit SET1 CLR1 PSW bit RETB PUSH PSW POP PSW PSW bit addr16 BF PSW bit
74. Product Name CSA4 00MGA Frequency MHz Recommended Oscillator Constant C1 pF C2 pF R1 KQ Remarks CST4 00MGWA built in capacitor CSAC4 00MGCA CSTCC4 00MGA built in capacitor CSA8 00MGA CST8 00MGWA built in capacitor CSAC8 00MGCA CSTCC8 00MGA PBRC4 00BRVA built in capacitor PBRC8 00BRVA Main System Clock Crystal Resonator Product Name CX 5FW 4 MHz Frequency MHz Recommended Oscillator Constant C1 pF C2 pF R1 KQ Remarks HC 49 U S 8 MHz CX 11F 8 MHz NDK AT 51 KDS Daishinku AT 49 SaRonix Caution HC49 U13 HC49 L HC49 S The oscillator constants and oscillator voltage range indicate conditions for stable oscillation but do not guarantee oscillation frequency accuracy If oscillation fre quency accuracy is required for actual circuits it is necessary to adjust the oscilla tion frequency of the oscillator in the actual circuit Please contact the manufacturer of the resonator to be used User s Manual U12670EE3VOUDOO 445 Chapter 25 Electrical Specifications 3 pPD78F0948 40 C to 85 C Vpp 4 0 to 5 5 V Resonator Recommended Circuit Parameter Conditions Oscillator frequency Vpp 4 0 to 5 5 V fy Note 1 Ceramic resonator Oscillation stabiliza peo aa i i Note 2 oscillator voltage ERMIS ra
75. Release by interrupt Note In combination with bits 0 to 2 OSTSO to OSTS2 of oscillation stabilization time select register selection 02124 and 2 4 fy to 2174 is possible Remark fx Main system clock oscillation frequency 482 User s Manual U12670EE3VOUDOO Chapter 25 Electrical Specifications Data Retention Timing STOP mode release by RESET Internal reset operation HALT mode m 0 STOP mode wlas aa Operating mode retension mode 4 lsREL STOP instruction execution RESET N 4 lwAT gt Data Retention Timing Standby release signal STOP mode release by Interrupt signal HALT mode 1 STOP mode wa a Operating mode Data retension mode Voo A STOP instruction execution Standby release signal interrupt request 4 gt Interrupt Input Timing INTPO INTP4 RESET Input Timing tRSL RESET User s Manual U12670EE3VOUDOO 483 Chapter 25 Electrical Specifications 25 6 6 Flash Memory Programming Characteristics uPD78F0948 TA 40 C to 85 C Vpp 4 5 to 5 5 V Vss 0 V Vpp 10 2 to 10 4 V 1 Basic characteristics Parameter Conditions Operating frequency 4 0 lt Vpp lt 5 5 V Operation voltage when writing Upon Vpp low level detection Supply voltage PPX Upon Vpp high level detection Upon Vpp high voltage detection
76. S31 as shown in Table 17 7 at the COMO and COM1 common signal timings Table 17 7 Selection and Non Selection Voltages COMO 1 Remark S Selection NS Non selection From this it can be seen that for example xx10 must be prepared in the display data memory corre sponding to S31 Examples of the LCD drive waveforms between S31 and the common signals are shown in Figure 17 15 When S31 is at the selection voltage at the COM1 selection timing it can be seen that the Vi cp Vi cp AC square wave which is the LCD illumination ON level is generated Figure 17 13 2 Time Division LCD Display Pattern and Electrode Connections pum RAN 1 COMO San 3 E San Remark nz0to9 1 User s Manual U12670EE3VOUDOO 347 Chapter 17 LCD Controller Driver Figure 17 14 2 Time Division LCD Panel Connection Example COM3 Open Open COM2 COM1 COMO o o reo zr A DD DH DD HB io D 50 51 52 53 Jeued 21 f o SseJppe Aiowew geq 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 In bits marked X any data be stored because this is 2 time division display Remark User s Manual U12670EE3VOUD00 3
77. SCK1 cycle time 2000 SCK1 high level width 5 2 160 SCK1 low level width R 1KO 5 2 160 SI1 setup time to SCK1 C 100 pF Note 300 SI1 hold time from SCK1 600 501 output delay time from SCK1 4 Note R and are the load resistance and the load capacitance of the 511 501 and SCK1 output line 3 wire serial I O mode SCK1 External clock output Parameter Conditions SCK1 cycle time SCK1 high level width SCK1 low level width R 1KQ 511 SO1 setup time to SCK1 7 C 100 pF Note 511 501 hold time from SCK1 T 511 501 output delay time from SCK1 4 Note Rand C are the load resistance and the load capacitance of the 511 501 SCK1 output line UART mode Dedicated baud rate generator output C CELL De User s Manual U12670EE3VOUDOO 477 Chapter 25 Electrical Specifications Serial Transfer Timing 3 wire serial mode tkcym tkHm SCKO 510 Remark 1 2 wire serial I O mode SCK1 SH SO1 478 User s Manual U12670EE3VOUDOO Chapter 25 Electrical Specifications 25 6 4 A D Converter Characteristics 1 pPD780948 A TA 40 C 85 Vpp 4 0 to 5 5 V AVss Vss oV fx 8 MHz Parameter Test Conditions Resolution Overall error Note Conversion time tconv Analog input voltage VI
78. Set bit 7 of the successive approximation register SAR is set automatically so that the tap selec tor sets the series resistor string voltage tap to 1 2 AVpp The voltage difference between the series resistor string voltage tap and analog input is compared with the voltage comparator If the analog input is greater than 1 2 AVpp the MSB of SAR remains set If the analog input is smaller than 1 2 AVpp the MSB is reset Next bit 6 of SAR is automatically set and the operation proceeds to the next comparison The series resistor string voltage tap is selected according to the preset value of bit 7 as described below Bit 7 1 3 4 AVpp e Bit7 20 1 4 AVpp The voltage tap and analog input voltage are compared and bit 6 of SAR is manipulated as fol lows Analog input voltage gt Voltage tap Bit 6 1 Analog input voltage lt Voltage tap Bit 6 0 Comparison is continued in this way up to bit 0 of SAR Upon completion of the comparison of 8 bits an effective digital result value remains in SAR and the result value is transferred to and latched in the A D conversion result register ADCR1 At the same time the A D conversion end interrupt request INTAD can also be generated Caution The first A D conversion value just after A D conversion start is undefined User s Manual U12670EE3VOUDOO 209 Chapter 12 A D Converter Figure 12 7 Basic Operation of 8 Bit A D Converter m Conversion time
79. Setting prohibited Timer output F F control on coincidence between CROO and TMO Disables inversion timer output F F 1 Enables inversion timer output F F Output control of 16 bit timer counter TMO Disables output port mode 1 Enables output Cautions 1 Before setting TOCO be sure to stop the timer operation 2 LVSO and LVRO are 0 when read after data have been set to them 3 Be sure to set bit 5 to bit 7 to 0 User s Manual U15251EE3VOUDOO 127 Chapter6 16 Bit Timer Event Counter 0 4 Prescaler mode register 0 This register selects a count clock of the 16 bit timer event counter 0 and the valid edge of TIOO 01 input PRMO is set by an 1 bit or an 8 bit memory manipulation instruction RESET input sets PRMO to 00H Figure 6 5 Format of Prescaler Mode Register 0 PRMO 7 6 5 4 3 2 1 0 RW Address ter Reset ES11 ES10 Selection of valid edge of TIO1 0 0 Falling edge Rising edge Setting prohibited Both falling and rising edges Selection of valid edge of TIOO Falling edge Rising edge Setting prohibited Both falling and rising edges Selection of count clock fx 2 4 MHz fy 24 500 KHz f 2 62 5 KHz Valid edge of TIOO Caution When selecting the valid edge of TIOO as the count clock do not specify the valid edge of TIOO to clear and start the timer and as a capture trigger Remark Figures in pare
80. Table 1 1 Table 1 2 Table 1 3 Table 1 4 Table 2 1 Table 2 2 Table 2 3 Table 3 1 Table 3 2 Table 3 3 Table 3 4 Table 3 5 Table 3 6 Table 3 7 Table 3 8 Table 3 9 Table 3 10 Table 3 11 Table 4 1 Table 4 2 Table 5 1 Table 5 2 Table 6 1 Table 6 2 Table 6 3 Table 7 1 Table 8 1 Table 8 2 Table 8 3 Table 8 4 Table 8 5 Table 8 6 Table 8 7 Table 8 8 Table 8 9 Table 9 1 Table 9 2 Table 9 3 Table 10 1 Table 10 2 Table 10 3 Table 10 4 Table 10 5 Table 11 1 Table 12 1 Table 13 1 Table 13 2 Table 14 1 Table 14 2 Table 15 1 Table 15 2 Table 15 3 Table 15 4 List of Tables The major functional differences between the subseries 32 Overview Of FUNGON S cete oce en ee a cur ane cv ddp weed ees 34 Differences between Flash and Mask ROM 35 Differences between Flash and Mask ROM version 35 Pirelnp t Output Types reote er stc 37 INonsPort Pins uoo ee De eere pe ete ene ee Cpu 39 Types of Pin Input Output Circuits ssesssesseseneeeeneeenenen nennen 48 Internal ROM Capacities 57 nno E 58 Special Function Register List nennen nennen enne 67 Addressing 3 etti rrr Did itg ipte Perte bete eee 74 Regis
81. The SIOS1 includes the following hardware Table 14 1 Composition of SIO31 Registers Serial I O shift register 31 S1031 Control registers Serial operation mode register 31 CSIM31 1 Serial shift register 51031 This is an 8 bit register that performs parallel serial conversion and serial transmit receive shift operations synchronized with the serial clock 51031 is set by an 8 bit memory manipulation instruction When 1 is set to bit 7 CSIE31 of the serial operation mode register CSIM31 a serial operation can be started by writing data to or reading data from SIO31 When transmitting data written to SIO31 is output via the serial output SO1 When receiving data is read from the serial input S11 and written to 51031 The RESET signal resets the register value to OOH Caution Do not access SIO31 during a transmit operation unless the access is triggered by a transfer start 14 3 List of SFRs Special Function Registers Table 14 2 List of SFRs Special Function Registers Units available for bit manipulation SFR name Symbol p Value after 1 bit 8 bit 16 bit reset Serial operation mode register 31 CSIM31 x x 00H Serial I O shift register SIO31 R W x 00H 226 User s Manual U12670EE3VOUDOO Chapter 14 Serial Interface Channel 31 14 4 Serial Interface Control Registers The SIO31 uses the following type of register for control functions Serial operation mo
82. circuit DCAN gt INTTM20 1 Pulse width measurement TM2 can measure the pulse width of an external input signal 2 Divided output of input pulse The frequency of an input signal can be divided and the divided signal can be output 3 Timer stamp function for the DCAN An internal signal output of the DCAN module can be used to build a time stamp function of the system please refer to the chapter of the DCAN module User s Manual U12670EE3VOUDOO 149 Chapter 7 16 Bit Timer 2 7 2 16 Bit Timer 2 Configuration Timer 2 consists of the following hardware Table 7 1 Timer 2 Configuration Item Configuration Timer register 16 bits x 1 TM2 Register Capture register 16 bits x 3 CR20 to CR22 16 bit timer mode control register TMC2 Control register Capture pulse control register CRC2 Prescaler mode register PRM2 1 16 bit timer register TM2 TM2 is a 16 bit read only register that counts count pulses The counter is incremented in synchronization with the rising edge of an input clock The count value is reset to 0000H in the following case At RESET input The count value is undefined in the following case TMC22 is disabled Caution When the timer TM2 is disabled the value of the timer register TM2 will be undefined 2 Capture register 20 CR20 The valid edge of the TI20 pin can be selected as the capture trigger Setting of the TI20 valid ed
83. instruction Cautions 1 Once bit 4 WDTM4 of WDTM is set to 1 with the watchdog timer mode selected the interval timer mode is not set unless RESET input is applied 2 The interval time just after setting with WDTM may be shorter than the set time by a maximum of 0 596 3 When the subsystem clock is selected for CPU clock watchdog timer count operation is stopped Table 10 5 Interval Timer Interval Time WDCS2 WDCS1 WDCSO Interval Time 5 21 512 us f 2 1 ms fx 214 2 ms fx 215 4 ms fx 216 8 19 ms 5 21 16 38 ms fy 2 8 32 76 ms Remarks 1 fx Main system clock oscillation frequency fy 2 131 ms 2 Figures in parentheses apply to operation with fy 8 0 MHz User s Manual U12670EE3VOUDOO 197 MEMO 198 User s Manual U12670EESVOUDOO Chapter 11 Clock Output Control Circuit 11 1 Clock Output Control Circuit Functions The clock output control circuit is intended for carrier output during remote controlled transmission and clock output for supply to peripheral LSI Clocks selected with the clock output selection register CKS are output from the PCL P33 SGOA pin Follow the procedure below to route clock pulses to the SGOA pin 1 Select the clock pulse output frequency with clock pulse output disabled with bits O to 3 CCSO to CCS2 of CKS Set the P61 output latch to 0 Set bit 1 PM33 of port mode register 6 to 0 set to
84. x 1 fy 250 ns 29 1 fy 64 us 23 x 1 fx 1 us 25 x 1 fx 4 us 211 x 1 fx 256 us 23 x 1 fx 1 us 21 x 1 fx 1 ms 25 x 1 fx 4 us 27 x 1 fx 16 us 215 x 1 fx 4 ms 2 x 1 fx 16 us 2 x 1 fx 64 us 217 x 1 fy 16 ms 29 x 1 fx 64 us Table 8 4 8 Bit Timer Event Counter 51 Square Wave Output Ranges Minimum Interval Width Maximum Interval Width 1 fx 125 ns 1 125 ns 28 x 1 fy 32 us 2 x 1 fx 250 ns 2 x 1 fx 64 us 2 x 1 fy 250 ns 23 x 1 fx 1 us 211 x 1 fx 256 us 23 x 1 fx 1 us 2 x 1 fx 4 us 2 x 1 fx 4 us 213 x 1 fy 1 ms 2 x 1 fx 16 us 215 x 1 fx 4 ms 2 x 1 fx 16 us 212 x 1 fy 512 us 220 x 1 fy 131 ms 21 x 1 fx 512 us Remarks 1 fy Main system clock oscillation frequency 2 Values in parentheses when operated at fy 8 0 MHz 4 PWM output TM50 and 51 can generate 8 bit resolution PWM output 162 User s Manual U12670EE3VOUD00 Chapter 8 8 Bit Timer Event Counters 50 and 51 8 2 8 Bit Timer Event Counters 50 and 51 Configurations The 8 bit timer event counters 50 and 51 consist of the following hardware Table 8 5 8 Bit Timer Event Counters 50 51 Configurations Item Configuration Timer register 8 bits x 2 TM50 TM51 Register Compare register 8 bits x 2 CR50 CR51 Timer output 2 TO50 TO51 Timer clock select register 50 and 51 T
85. 0 78 87AD Series Fuzzy Inference Development Support Sys tem Translator EEU 862 EEU 1444 78K 0 Series Fuzzy Inference Development Support System Fuzzy Inference Module EEU 858 EEU 1441 78K 0 Series Fuzzy Inference Development Support System Fuzzy Inference Debugger Other Documents Document name EEU 921 EEU 1458 Document No IC Package Manual Japanese C10943X English Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grade on NEC Semiconductor Devices C11531J C11531E Reliability Quality Control on NEC Semiconductor Devices C10983J C10983E Electric Static Discharge ESD Test MEM 539 Semiconductor Devices Quality Assurance Guide MEI 603 MEI 1202 Microcontroller Related Product Guide Third Party Manufacturers Caution latest version document when starting design User s Manual U12670EE3VOUDOO U11416J The above documents are subject to change without prior notice Be sure to use the Legend Preface Symbols and notation are used as follows Weight in data notation Left is high order column right is low order column Active low notation pin or signal name is over scored or xxx slash before signal name Memory map address High order at high stage and low order at low stage Note Explanation of Note in the text Caution Item deserving extra attention Remark
86. 1 PC 1 y SP 2 lt PC 1 PC lt 00000000 addr5 1 PC lt 00000000 addr5 SP lt SP 2 addr5 SP 1 lt PSW SP 2 lt PC 1 y SP 3 lt PC 1 003FH PCL lt 003EH SP SP 8 IE 0 PCy lt SP 1 PCL lt SP SP lt SP 2 PCy lt SP 1 PCL lt SP PSW lt SP 2 SP SP 3 NMIS 0 lt SP 1 PCL lt SP PSW lt SP 2 SP lt SP 3 SP 1 lt PSW SP SP 1 SP 1 lt rpp SP 2 rp SP lt SP 2 PSW lt SP SP lt SP 1 lt SP 1 rp lt SP SP SP 2 rp SP word SP lt word SP AX SP lt AX AX SP AX SP laddr16 PC lt addr16 addr16 PC lt PC 2 jdisp8 AX PCy A PCL X addr16 PC lt PC 2 jdisp8 if CY 1 addr16 PC lt PC 2 jdisp8 if CY 0 addr16 PC lt PC 2 jdisp8 if Z 1 PO PO POT PO PO PO PO N A addr16 PC PC 2 jdisp8 if Z 0 When the internal high speed RAM area is accessed or instruction with no data access When an area except the internal high speed RAM area is accessed Except r A Only when rp BC DE or HL One instruction clock cycle is one cycle of the CPU clock selected by the PCC register This clock cycle applies to internal ROM program ni
87. 1 2 Bias Method 352 3 Time Division LCD Drive Waveform Examples 1 3 Bias Method 353 4 Time Division LCD Display Pattern and Electrode Connections 354 4 Time Division LCD Panel Connection Example 355 4 Time Division LCD Drive Waveform Examples 1 3 Bias Method 356 LCD Timer Control Register LCDTM 357 Sound Generator Block Diagram 359 Concept of Each Sigrial ie et perci eee e eee dee E it dae dE eis 360 Sound Generator Control Register SGCR Format 1 2 361 Sound Generator Buzzer Control Register SGBR 363 Sound Generator Amplitude Register SGAM 364 Sound Generator Output Operation Timing sse 365 Sound Generator Output Operation Timing sse 366 Basic Configuration of Interrupt Function 1 2 369 Interrupt Request Flag Register 372 Interrupt Mask Flag Register 373 Priority Specify Flag Register 2 0 100 374 Formats of External Interrupt Rising Edge Enable Register and External Interrupt Falling Edge Enable Register
88. 18 Bit Synchronization Phase Sync Prop segment segment segment Phase Sync Prop segment 2 segment segment User s Manual U12670EE3VOUDOO 273 Chapter 16 CAN Coniroller 16 2 8 State Shift Chart Figure 16 19 Transmission State Shift Chart Reception Start of frame End Bit error Reception Error passive Start of frame reception n Arbitration field 1 Bit error Control field RTR 0 Bit error Data field End Bit error ACK error Bit error Error active 8 bits of 1 Reception 274 Start of frame transmission Initialization setting User s Manual U12670EE3VOUD00 Chapter 16 CAN Controller Figure 16 20 Reception State Shift Chart Transmission Start of frame Transmission End n Arbitration field Stuff error Control field Stuff error RTR 0 Data field Stuff error CRC error stuff error Initialization setting Start of frame transmission Start of frame reception Transmission User s Manual U12670EE3VOUDOO 275 276 Chapter 16 CAN Coniroller Figure 16 21 Error State Shift Chart a Transmission TEC gt 128 lt 127 gt 256 Transmission error counter b Reception REC gt 128 Error passive REC lt 127 REC Reception error
89. 2 1 0 Address After Reset R W 6 5 4 3 The receive status reflects the current status of a message It signals whether new data is stored or if the DCAN currently transfers data into this buffer In addition the data length of the last transferred data and the reserved bits of the protocol are shown DN Data New 0 No change in data 1 Data changed The DCAN module sets DN twice At first when it starts storing a message from the shadow buffer into the receive buffer and secondly when it finished the operation The CPU needs to clear this bit to signal by itself that it has read the data During initialization of the receive buffers the DN bit should also be cleared Otherwise the CPU gets no information on an update of the buffer after a successful reception MUC Memory Update 0 1 CAN does not access data part CAN is transferring new data to message buffer The DCAN module sets MUC when it starts transferring a message into the buffer and clears the MUC bit when the transfer is finished Reserved Bit 1 Reserved bit 1 of received message was 0 Reserved bit 1 of received message was 1 Reserved Bit 0 Reserved bit 0 of received message was 0 Reserved bit 0 of received message was 1 288 User s Manual U12670EE3VOUD00 Chapter 16 CAN Controller Figure 16 28 Receive Status Bits 2 2 Data Length Code Selection of Receive Message 0 data bytes 1 data bytes 2 dat
90. 21 x 1 fx 512 us Other than above Setting prohibited Remarks 1 fy Main system clock oscillation frequency 2 Values in parentheses apply to operation with fy 8 0 MHz 3 n2 50 51 User s Manual U12670EE3VOUDOO 175 Chapter 8 8 Bit Timer Event Counters 50 and 51 8 4 2 External event counter operation The external event counter counts the number of external clock pulses to be input to the TI50 P06 TO50 and TI51 PO7 TO51 pins with 8 bit timer registers 50 and 51 TM50 and TM51 TM50 and 51 are incremented each time the valid edge specified with timer clock select registers 50 and 51 TCL50 and TCL51 is input Either rising or falling edge can be selected When the TM50 and TM51 counted values match the values of 8 bit compare registers CR50 and CR51 TM50 and 51 are cleared to 0 and the interrupt request signals INTTM50 and INTTM51 are generated Figure 8 11 8 Bit Timer Mode Control Register Setting for External Event Counter Operation TMCn6 TMCn4 LVSn LVRn TMCn1 TOEn TMCn TOn output disable 8 bit timer event counter mode Clear and start mode on match of TMn and CRn TMn operation enable Remarks 1 50 51 2 x don t care Figure 8 12 External Event Counter Operation Timings with Rising Edge Specified LI LT LILI LILLE LT LT LE LIE LIT LT 1 oo Yoyo 00 0 0 00050055 CRn N TCEn rs INTTMn 4 1 Remarks 1 N
91. 2318 RESET x4 cre ek Lu EIE MR x MR E bo nee ts 46 2 9 19 whoa ena vege ies 46 2 9 20 GE WANG GE2 sum re pete iet bx e UPPES 46 2 3 21 RTT 46 2331220 gt NGS iste ie DUE PERRO a aste deca Gs tad e ea kee 47 2 3 23 UPD78F0948 1 47 2 3 24 Mask ROM version 47 2 4 Pin I O Circuits and Recommended Connection of Unused Pins 48 Chapter 3 CPU 55 3 1 Memory Space iia ois eee e at a CERT Rea 55 3 1 1 Internal program memory 57 3 1 2 Internal data memory 59 3 1 3 Special function register SFR 59 3 1 4 External memory space 59 3 1 5 Data memory addressing 60 3 2 Processor Registers 62 3 2 1 Control registers i yeaa sene Tere oon PED E Eee Er DE Rb en pea 62 3 2 2 General registers z RH e aD EE FR Fe NR RO Matters 65 3 2 3 Special function register 66 User s Manual U12670EE3VOUDOO 9 3 3 Instruction Address Addressing
92. 323 16 18 Functional Description 324 16 1831 Mialan oor uere teret tee Sete petu eerte er A S 324 16 18 2 Transmit Preparation 1 325 16 18 3 Abort Transmit 326 16 18 4 Handling by the 327 16 18 5 Receive Event Oriented 328 16 18 6 Receive Task 329 Chapter 17 LCD Controller 331 17 1 LCD Controller Driver Functions 331 17 2 LCD Controller Driver 332 17 3 LCD Controller Driver Control 334 17 4 LCD Controller Driver 05 335 17 5 LCD Display Data Memory 336 17 6 Common Signals and Segment Signals 337 17 7 Supplying of LCD Drive Voltages Vico Vici 2 340 17 8 Display Modes 2 2 IR RR steer te eee eee dee ees 344 17 8 1 Static display example 344 17 8 2 2 time division display example 347
93. 4 DATA5 Message data byte 5 DATA6 Message data byte 6 DATA7 Message data byte 7 Notes 1 This address is a relative offset to the start address of the receive buffer 2 RTRggc is the received value of the RTR message bit when this buffer is used together with a mask function By using the mask function a successfully received identifier overwrites the bytes IDRECO and IDREC1 for standard frame format and IDRECO to IDRECA for extended frame format For the RTRggc bit exist two modes RTR bit in the MCON byte of the dedicated mask is set to 0 In this case RTRggc will always be written to 0 together with the update of the IDn bits in IDREC1 The received frame type data or remote is defined by the RTR bit in IDCON of the buffer RTR bit in the MCON byte of the dedicated mask is set to 1 data and remote frames are accepted In this case the RTR bit in IDCON has no meaning The received mes sage type passed the mask is shown in RTRggc If a buffer is not assigned to a mask function mask 1 mask 2 or global mask the bytes IDRECO to IDRECA are only read for comparing During initialization the RTRggc should be defined to 0 286 User s Manual U12670EE3VOUD00 Chapter 16 CAN Controller 1 Receive control bits definition The memory location labelled IDCON defines the kind of frame data or remote frame with stand ard or extended format that is mo
94. 4 Flash programmer connection Connection of flash programmer and the uPD78F0948 differs depending on communication method 3 wire serial I O UART Each case of connection shows in Figures 23 4 23 5 and 23 6 Figure 23 4 Connection of the Flash Programmer using 3 Wire Serial Method Flash programmer uPD78F0948 Figure 23 5 Connection of the Flash Programmer using UART Method Flash programmer uPD78F0948 420 User s Manual U12670EE3VOUDOO Figure 23 6 RESET System clock CLK X1 Vpp SO RXD TXD Chapter 23 uPD78F0948 Connection of the Flash Programmer using Pseudo 3 wire Serial V O Method Flash programmer 78 0948 RESET Serial clock input Serial data input Serial data output Vss X1 Programming voltage applied from the on board programming tool A RESET is generated and the device is set to the on board programming mode The CPU clock for the device may be supplied by the on board program tool Alternatively the crystal or ceramic oscillator on the target H W can be used in the on board programming mode The external system clock has to be connected with the X1 pin on the device The power supply for the device may be supplied by the on board program tool Alternatively the power supply on the target H W can be used in the on board programming mode Ground level Serial clock generated by the on board progra
95. 500 and serial input line SIO 1 Register settings The 3 wire serial I O mode is set via serial operation mode register 30 CSIM30 CSIM30 can be set via an 1 bit or an 8 bit memory manipulation instructions The RESET input set the value to OOH Figure 13 4 Format of Serial Operation Mode Register CSIM30 lt gt 6 5 4 3 2 1 0 After R W_ Address Reset CSIM30 CSIE30 0 0 MODEO SCL301 SCL300 R W FFA8H 00H CSIE30 Enable disable specification for SIO30 Shift register operation Operation stop Serial counter Clear Port function Note 1 Operation enable Count operation enable Serial operation port function Transfer operation modes and flags Note 2 Operation mode Transmit receive mode Write to SIO30 Transfer start trigger 500 21 500 output Receive only mode SCL300 Note 2 Read from SIO30 Clock selection fy 8 00 MHz External clock input Port function 8 bit timer 50 TM50 output 5 23 14 27 Notes 1 When CSIE30 0 SIO30 operation stop status the pins SIO and SOO can be used for port functions 2 When MODEO 1 Receive mode pin P21 can be used for port function User s Manual U12670EE3VOUDOO 223 Chapter 13 Serial Interface Channel 30 2 Communication Operations In the three wire serial I O mode data is transmitted and received in 8 bit units Each bit of data is sent or re
96. 504 28 60 Succursale Frangaise V lizy Villacoublay France 01 30 67 58 00 01 30 67 58 99 Filiale Italiana Milano Italy Tel 02 66 75 41 Fax 02 66 75 42 99 Branch Netherlands Eindhoven The Netherlands Tel 040 244 58 45 Fax 040 244 45 80 Branch Sweden Taeby Sweden Tel 08 63 80 820 Fax 08 63 80 388 United Kingdom Branch Milton Keynes UK Tel 01908 691 133 Fax 01908 670 290 NEC Electronics Hong Kong Ltd Hong Kong Tel 2886 9318 Fax 2886 9022 9044 NEC Electronics Hong Kong Ltd Seoul Branch Seoul Korea 02 528 0303 02 528 4411 Electronics Singapore Pte Ltd Singapore Tel 65 6253 8311 65 6250 3583 Electronics Taiwan Ltd Taipei Taiwan 02 2719 2377 02 2719 5951 NEC do Brasil S A Electron Devices Division Guarulhos Brasil 55 11 6465 6810 Fax 55 11 6465 6829 User s Manual U12670EE3VOUD00 Preface Readers This manual has been prepared for engineers who want to understand the functions of the PD780948 Subseries and design and develop its application systems and programs pPD780948 Subseries uPD780948 A uPD780948 A1 uPD78F0948 Purpose This manual is intended for users to understand the functions of the uPD780948 Subseries Organization The uPD780948 subseries manual is separated into two parts this manual and the instruction edition common to the 78K 0 series
97. A1 40 C to 110 C Vpp 4 0 to 5 5 V Parameter Symbol Conditions POO P07 P10 P17 P20 P26 P30 P34 P40 P47 P50 P57 P64 P65 P67 P70 P77 P120 P127 High level P130 P137 P140 P147 input voltage RESET CRXD X1 X2 CL1 POO P07 P10 P17 P20 P26 P30 P34 P40 P47 P50 P57 P64 P65 P67 P70 P77 P120 P127 Low level P130 P137 P140 P147 input voltage RESET CRXD X1 X2 CL1 P07 P10 P17 P20 P26 P30 P34 P40 P47 P50 P57 y p 4 0 5 5V P64 P65 P67 P70 P77 P120 P127 P130 P137 P140 P147 CTXD loH 1mA Vpp 4 5 5 5V SGO lou 15 P00 P07 P10 P17 P20 P26 P30 P34 P40 P47 P50 P57 4 0 5 5V P64 P65 P67 P70 P77 P120 Low level P127 P130 P137 P140 P147 lot 1 6mA output voltage CTXD Vpp 4 5 5 5 V 230 lot 15 mA P07 P10 P17 P20 P26 P30 P34 P40 P47 P50 P57 High level P64 P65 P67 P70 P77 P120 input leakage P127 P130 P137 P140 P147 current CRXD ANIO ANI7 X1 X2 CL1 P00 P07 P10 P17 P20 P26 P30 P34 P40 P47 P50 P57 Low level P64 P65 P67 P70 P77 P120 input leakage P127 P130 P137 P140 P147 current CRXD ANIO ANI7 X1 X2 CL1 High level out 4 5 V Vpp lt 5 5 V up resistor Remark characteristics of the dual
98. AD7 A8 A15 RD ASTB INTPO Interrupt INTP4 Control A D Converter External Access Block Diagram Figure 1 3 a 5854s a n gt gt gt gt 78 0 Remark User s Manual U12670EE3VOUDOO 60 K ROM CCLK CRxD DCAN Interface System Control 8MHz SV RC Oscillator Outline uPD780948 Subseries Port 0 5 Port 1 8 Port 2 i Port 3 Port 4 Port 5 en es ey mus K gt ez Sm Port 7 Port 12 Port 13 Port 14 516 523 524 531 Controller driver 532 539 COM0 COM3 VLCO VLC2 SGO SGOF Clock Output Standby Control The internal ROM and RAM capacity depends on the product 33 Chapter 1 Outline uPD780948 Subseries 1 8 Overview of Functions Table 1 2 Overview of Functions Part Number 0780948 78 0948 ROM 60 Kbytes Internal Internal high speed RAM 1024 bytes memory CD Display RAM 40 bytes Internal Expansion RAM 992 bytes Memory space 64 Kbytes General registers 8 bits x 32 registers 8 bits x 8 registers x 4 banks Instruction cycle On chip instruction execution time selective function When main system clock selected 0 25 us 0 5 us 1 us 2 us 4 us at 8 MHz When subsystem clock selected 122 us at 32 768 KHz 16 bit operation
99. ASTB T delay time from RD T at external fetch Address hold time from RD T at external fetch tRDAST 0 8 tcy 15 1 2 tcv tRDADH 0 8 tcy 15 1 2 30 Write data output time from RD 7 tRDWD 40 Write data output time from WR tWRDWD 10 60 Address hold time from WR lWRADH 0 8 toy 15 1 2 toy 30 Remarks 1 4 2 C 100 pF C are capacitances of ADO to 07 8 to A15 RD WR ASTB 3 nindicates the number of waits Caution The external access interface cannot be used on the tPD780948GF A1 at high temperature T4 110 C The maximum temperature is T 85 C User s Manual U12670EE3VOUDOO 467 3 pPD78F0948 40 C to 85 C Vpp 4 0 to 5 5 V Parameter ASTB high level width Conditions Chapter 25 Electrical Specifications Address setup time Address hold time Data input time from address 2 2n tcv 54 Data input time from RD 4 2 2 tcv 87 3 3n 60 343n 93 Address output time from RD J 100 Read data hold time 0 0 RD low level width 1 542n tcy 33 2 5 2n tcv 33 Write data setup time 60 Write data hold time WR low level width twRL 6 1 542n tcy 15 RD J delay time from ASTB J tasTRD 6 WR J delay time from ASTB 1 tASTWR 2 15 ASTB delay time from RD T a
100. Bit Timer Output Control Register 127 Format of Prescaler Mode Register 0 128 User s Manual U12670EE3VOUDOO 17 Figure 6 6 Figure 6 7 Figure 6 8 Figure 6 9 Figure 6 10 Figure 6 11 Figure 6 12 Figure 6 13 Figure 6 14 Figure 6 15 Figure 6 16 Figure 6 17 Figure 6 18 Figure 6 19 Figure 6 20 Figure 6 21 Figure 6 22 Figure 6 23 Figure 6 24 Figure 6 25 Figure 6 26 Figure 6 27 Figure 6 28 Figure 6 29 Figure 7 1 Figure 7 2 Figure 7 3 Figure 7 4 Figure 7 5 Figure 7 6 Figure 7 7 Figure 7 8 Figure 7 9 Figure 7 10 Figure 8 1 Figure 8 2 Figure 8 3 Figure 8 4 Figure 8 5 Figure 8 6 Figure 8 7 Figure 8 8 Figure 8 9 Figure 8 10 Figure 8 11 Figure 8 12 Figure 8 13 Figure 8 14 Figure 8 15 18 Port Mode Register 7 PM7 129 Control Register Settings When Timer 0 Operates as Interval Timer 130 Configuration of Interval 131 Timing of Interval Timer 131 Control Register Settings in PPG Output 132 Control Register Settings for Pulse Width Measurement with Free Running Counter One Capture 133
101. CROO cannot perform its capture operation Figure 6 19 Control Register Settings for Pulse Width Measurement by Restarting a 16 bit timer mode control register TMCO 02 01 OVFO LOESEEUENENESE TET Clears and starts at valid edge of TI00 P70 pin b Capture compare control register 0 CRCO CRC02 CRCO1 NCROO as capture register Captures to CROO at edge reverse to valid edge of 00 70 01 as capture register Remark 0 1 When these bits are reset to 0 or set to 1 the other functions can be used along with the pulse width measurement function For details refer to Figures 6 2 and 6 3 User s Manual U15251EE3VOUDOO 139 Chapter 6 16 Timer Event Counter 0 Figure 6 20 Timing of Pulse Width Measurement by Restarting with rising edge specified t pe is cock IFLFLIFLIFLFLFELELFLFLFLFLFLEI Two count value X bo X X X Xoz TIOO pin input CROO capture value Nu X 1 INTTMO1 Di x1 D2x1 4 EROS Herc NET IEEE 140 User s Manual U15251EE3VOUDOO Chapter 6 16 Bit Timer Event Counter 0 6 4 4 Operation as external event counter 16 bit timer event counter can be used as an external event counter which counts the number of clock pulses input to the TIOO pin from an external source by using the 16 bit timer register TMO Each time the valid edge sp
102. Capture compare register 01 01 1 123 Garry flag OY 3 2 oue Gastar ur cei ad ate S ENT DIR E ENS Beg AUI A M Ree boite 63 Clock output selection register CKS 201 Compare register 50 and 51 CR50 CR51 165 D D A converter mode register 0 218 Error Status Register 300 E External Interrupt Falling Edge Enable Register 375 External interrupt rising edge enable register EGP 375 G General register Sae vp wha wide Chad led 65 IDREGCO to IBREGA ere saure ER p ec 290 IDTXO to IDTX4 1 1 283 In service priority flag ISP 1 63 Internal Expansion RAM Size Switching Register 417 Interrupt enable flag IE 4 63 User s Manual U12670EE3VOUD00 499 Appendix Index Interrupt mask flag registers MKOL MKOH MK1L
103. Channel 1 UART reception error generation INTSR End of channel 1 UART reception INTST End of channel 1 UART transfer INTTMOO Generation of 16 bit timer event counter 50 match signal INTTMO 1 Generation of 16 bit timer 0 capture compare reg ister CROO match signal 50 Generation of 8 bit timer 1 capture compare regis ter 01 match signal 51 Generation of 8 bit timer event counter 51 match signal INTWTI Reference time interval signal from watch timer INTWT Reference time interval signal from watch timer Internal Notes 1 BRK BRK instruction execution Internal Default priorities are intended for two or more simultaneously generated maskable interrupt requests 0 is the highest priority and 22 is the lowest priority 2 Basic configuration types A to D correspond to A to D of Figure 19 10n page 369 368 User s Manual U12670EE3VOUD00 Chapter 19 Interrupt Functions Figure 19 1 Basic Configuration of Interrupt Function 1 2 a Internal non maskable interrupt Internal Bus Vector Table Interrupt Priority Control Address Request Circuit Generator Standby Release Signal b Internal maskable interrupt Internal Bus Vector Table Address Interrupt Generator Request Standby Release Signal Remark IF Interr
104. Configuration for Pulse Width Measurement with Free Running Counter 134 Timing of Pulse Width Measurement with Free Running Counter and One Capture Register with both edges 134 Control Register Settings for Measurement of Two Pulse Widths with Free Running nennen nennen nene nnne nes 135 01 Capture Operation with Rising Edge Specified 136 Timing of Pulse Width Measurement Operation with Free Running Counter with both edges specified enn 136 Control Register Settings for Pulse Width Measurement with Free Running Counter Two Capture 137 Timing of Pulse Width Measurement with Free Running Counter and Two Capture Registers with rising edge specified 138 Control Register Settings for Pulse Width Measurement by Restarting 139 Timing of Pulse Width Measurement by Restarting with rising edge specified 140 Control Register Settings in External Event Counter 141 Configuration of External Event Counter 142 Timing of External Event Counter Operation with rising edge specified 142 Set Contents of Control Registers in Square Wave Output 143 Timing of Square W
105. ControliFunction unie x Rm FOG Sead 268 16 27 Baud Rate Control 271 16 2 8 Stale ShifE Chara uli ei conc Mia a ea A Pee ie Be 274 16 3 Outline Description 277 16 4 Connection with Target 278 16 5 CAN Controller 278 16 6 Special Function Register for CAN module 279 16 7 Message and Buffer Configuration 280 16 8 Transmit Buffer Structure 281 16 9 Transmit Message 281 16 10 Receive Buffer 285 16 11 Receive Message 286 16 12 Mask Funclioh eere eae ean ae RAAE BER Rd EUER 292 16 13 Operation of the CAN Controller 296 16 13 1 control register 296 16 13 2 DCAN Error Status 300 12 User s Manual U12670EE3VOUD00 16 13 3 Transmit Error Counter 303 16 13 4 CAN Receive Error
106. D converter 1 Enables power fail comparison used to detect power failure PFCM Power Fail Compare Mode Selection ADCR 1 gt PFT Generates interrupt request signal INTAD ADCR1 lt PFT Does not generate interrupt request signal INTAD ADCR 1 gt Does not generate interrupt request signal INTAD ADCR1 lt PFT Generates interrupt request signal INTAD Caution Bits 0 to 5 must be set to 0 4 Power fail compare threshold value register PFT The power fail compare threshold value register PFT sets a threshold value against which the result of A D conversion is to be compared PFT is set with an 8 bit memory manipulation instruction RESET input clears PFT to 00H Figure 12 6 Power fail compare threshold value register PFT 7 6 5 4 3 2 1 0 Address Alter Reset 208 User s Manual U12670EE3VOUD00 Chapter 12 A D Converter 12 4 A D Converter Operations 12 4 4 Basic Operations of A D Converter lt gt lt 2 gt lt 3 gt lt 4 gt lt 5 gt lt 6 gt lt 7 gt lt 8 gt Select one channel for A D conversion with the analog input channel specification register ADS1 The voltage input to the selected analog input channel is sampled by the sample amp hold circuit When sampling has been done for a certain time the sample amp hold circuit is placed in the hold state and the input analog voltage is held until the A D conversion operation is ended
107. ES01 of prescaler mode register PRM2 is input to the TI20 P30 pin the value of TM2 is taken into 16 bit capture register 20 CR20 and an external interrupt request signal INTTM20 is set Also when the edge specified by bits 4 and 5 ES10 and ES11 of PRMO is input to the TI21 P31 pin the value of TM2 is taken into 16 bit capture register 21 CR21 and an external interrupt request signal 21 is set When the edge specified by bits 6 and 7 ES20 and ES21 of PRM2 is input to the TI22 P32 pin the value of TM2 is taken into 16 bit capture register 22 CR22 and external interrupt request sig nal 22 is set Any of three edge specifications can be selected rising falling or both edges as the valid edges for the TI20 P30 to TI22 P32 pins by means of bits 2 and 3 ES00 and 501 bits 4 and 5 ES10 ES11 and bits 6 and 7 506 and 507 of PRM2 respectively For TI20 P30 pin valid edge detection sampling is performed at the interval selected by the pres caler mode register PRM2 and a capture operation is only performed when a valid level is detected twice thus eliminates the noise of a short pulse width e Capture operation Capture register operation in capture trigger input is shown Figure 7 7 CR2m Capture Operation with Rising Edge Specified Count clock TM2 Tl2m Rising edge detection CR2m n INTTM2m Remark m 0to2 User s Manual U12670EE3VOUDOO 157 Chapter 7 1
108. Example with 5 V Vicp 5 V Vop1 c 1 3 bias method Example with 5 V Vicp 5 V Vop1 Cautions 1 The Flash version pPD78F0948 has no internal split resistor 2 The Mask version PD780948 has the possibility to implement interval split resis tors via mask option User s Manual U12670EE3VOUDOO 341 Chapter 17 LCD Controller Driver Figure 17 8 Example of LCD Drive Voltage Supply from Off Chip Vppt Vicp Cautions 1 The Flash version pPD78F09468 has no internal split resistor 2 Mask version PD780948 has the possibility to implement interval split resis tors via mask option 342 User s Manual U12670EE3VOUDOO Chapter 17 LCD Controller Driver Figure 17 9 Example of LCD Drive Power Supply external resistors a To supply LCD drive voltage from Vpp 2 6 D Vici Vic2 e 1 Vss b To supply LCD drive voltage from external source Vpp2 Voo LIPS 0 D Ee ps Vico 7 6 E 7 T Vss 5 Vici Vice Vss Cautions 1 Flash version pPD78F0948 has no internal split resistor Tx Vss 2 The Mask version PD780948 has the possibility to implement interval split resis tors via mask option User s Manual U12670EE3VOUDOO 343 Chapter 17 LCD Controller Driver 17 8 Display Modes 17 8 1 Static display example Figure 17 11 shows the connection of a s
109. Figure 3 7 Stack Pointer Configuration 15 0 The SP is decremented ahead of write Save to the stack memory and is incremented after read reset from the stack memory Each stack operation saves resets data as shown in Figures 3 8 and 3 9 Caution Since RESET input makes SP contents indeterminate be sure to initialize the SP before instruction execution Figure 3 8 Data to be Saved to Stack Memory Interrupt and PUSH rp Instruction CALL CALLF and BRK Instruction CALLT Instruction SP SP 3 4 SP SP 2 SP 2 SP 3 PC7 to PCO A SP 2 Register Pair Lower SP 2 PC7 to PCO SP N 2 PC15 to PC8 SP 1 Register Pair Upper SP 1 PC15 to PC8 SP 1 PSW SP gt SP gt SP gt Figure 3 9 Data to be Reset to Stack Memory RETI and RETB POP rp Instruction RET Instruction Instruction SP gt Register Pair Lower SP gt PC7 to PCO SP gt PC7 to PCO SP 1 Register Pair Upper SP 1 PC15 to PC8 SP 1 PC15 to PC8 SP 9 2 SP 9 2 SP 2 PSW SP SP 3 64 User s Manual U12670EE3VOUDOO Chapter 3 CPU Architecture 3 2 2 General registers A general register is mapped at particular addresses to FEFFH of the data memory It consists of 4 banks each bank consisting of eight 8 bit registers X A C B E D L and H Each register can also be used as an 8 bit register Two 8 bit registers can be used in pairs as a 16 bit register
110. For details refer to Figures 6 2 and 6 3 User s Manual U15251EE3VOUDOO 137 6 16 Bit Timer Event Counter 0 Figure 6 18 Timing of Pulse Width Measurement with Free Running Counter and Two Capture Registers with rising edge specified t 1 1 1 1 TMO count value poss X oo Y 1 Xe X Xo X 1 TIOO pin input cH 1 1 t OVFO ee E E 01 DO xt 10000H D1 D2 xt D3 D2 xt 138 User s Manual U15251EE3VOUD00 Chapter 6 16 Bit Timer Event Counter 0 4 Pulse width measurement by restarting When the valid edge of the TIOO pin is detected the pulse width of the signal input to the TIOO pin can be measured by clearing the 16 bit timer register TMO once and then resuming counting after loading the count value of to the 16 bit capture compare register 01 01 The edge of the TIOO pin is specified by bits 4 and 5 500 and 501 of PRMO The rising or fall ing edge can be specified The valid edge is detected through sampling at a count clock cycle selected by the prescaler mode register 0 PRMO and the capture operation is not performed until the valid level is detected two times Therefore noise with a short pulse width can be rejected Caution If the valid edge of the TIOO pin is specified to be both the rising and falling edges the capture compare register 00
111. Functions in External Memory Expansion 389 State of Port 4 to Port 6 Pins in External Memory Expansion Mode 389 Values when the Memory Size Switching Register is 395 HALT Mode Operating Status 405 Operation after HALT Mode 407 STOP Mode Operating Status ssssssssssssssssesse eene eene 408 Operation after STOP Mode Release sse 410 Hardware Status after 413 Differences among UPD78F0948 and Mask ROM Versions 415 Values when the Memory Size Switching Register is 416 Examples of internal Expansion RAM Size Switching Register Settings 417 Transmission Method 418 Main Functions of Flash Memory 419 Operand Identifiers and Description 423 ern REEL 425 User s Manual U12670EE3VOUD00 Table 24 37 Eee eet i sateen ed pee edet aeta 433 Table 24 4 16 bit 434 Table 24 5 Bit manipulation nennen
112. Ics XD xe ne oo 5 7 INTTMn OVFn Active Level Inactive Level Active Level Inactive Level Remark 50 51 Caution If CRn is changed during TMn operation the value changed is not reflected until TMn overflows User s Manual U12670EE3VOUDOO 181 182 Chapter 8 8 Bit Timer Event Counters 50 and 51 8 5 Cautions on 8 Bit Timer Event Counters 50 and 51 1 Timer start errors An error with a maximum of one clock might occur concerning the time required for a match signal to be generated after the timer starts This is because 8 bit timer registers 50 and 51 are started asynchronously with the count pulse Figure 8 20 8 bit Timer Registers 50 and 51 Start Timings TMn Count Value 00H 01H 02H 03H 04H Timer Start Remark 50 51 2 Compare registers 50 51 sets The 8 bit compare registers CR50 and CR51 can be set to OOH Thus when an 8 bit compare register is used as an event counter one pulse count operation can be carried out Figure 8 21 External Event Counter Operation Timings CRn 00H TMn Count Value 00H 00H 00H 00H TOn 45 5 er O T Interrupt Request Flag 50 51 User s Manual U12670EE3VOUD00 Chapter 8 8 Bit Timer Event Counters 50 and 51 3 Operation after compare register change during timer count operation If the values after the 8 bit compare registers CR50
113. Input Connect to Vpp or via a resistor individually Output Leave open P70 S31 P71 S30 P72 S29 P73 S28 P74 S27 P75 S26 P76 S25 P77 S24 Input Connect to Vpp or Vss via a resistor individually Output Leave open P120 S23 121 522 122 521 123 520 124 519 125 518 126 517 127 516 Input Connect Vpp or Vss via a resistor individually Output Leave open User s Manual U12670EE3VOUDOO 49 Pin Name P130 S15 P131 S14 P132 S13 P133 S12 P134 S11 P135 S10 P136 S9 P137 S8 Chapter 2 Pin Function uPD780948 Subseries Table 2 3 Types of Pin Input Output Circuits 3 3 Input Output Circuit Type Recommended Connection for Unused Pins Input Connect to Vpp or Vas via a resistor individually Output Leave open P140 S7 P141 S6 P142 S5 P143 S4 P144 S3 P145 S2 P146 S1 147 50 Input Connect to Vpp or via a resistor individually Output Leave open COMO COM3 Vico Vice Leave open Connect to Vpp via a resistor individually Leave open CL1 CCLK Connect Vpp or via a resistor individually CL2 Leave open RESET AVpp AVREF Connect to Vpp AVss Connect to Vss 50 Connect directly to Vss User s Manual U12670EE3VOUD00 Outp
114. Instruction Table U10903J 78K 0 Series Instruction Set U10904J Related documents for development tools User s Manuals Document name RA78K Series Assembler Package Operation Document No Japanese EEU 809 English EEU 1399 Language EEU 815 EEU 1404 RA78K Series Structured Assembler Preprocessor CC78K Series C Compiler Operation EEU 817 EEU 656 EEU 1402 EEU 1280 Language EEU 655 EEU 1284 CC78K 0 C Compiler Operation U11517J Language U11518J CC78K 0 C Compiler Application Note Programming Note EEA 618 EEA 1208 CC78K Series Library Source File EEU 777 IE 78K0 NS A U14889J U14889E IE 78K0 NS P04 Planned IE 780948 NS EM4 U14514J U14515E NP 100GF TQ SM78KO System Simulator Windows Base Reference 015373 U15373E 5 78 0 Series System Simulator External part user open Interface U15802J U15802E ID78KO NS Integrated Debugger Windows Base Guide U15185J User s Manual U12670EE3VOUD00 U15185E Preface Related documents for embedded software User s Manual Document name Basics Document No Japanese U11537J English 78K 0 Series Real Time OS Installation U11536J Technical U11538J 78K 0 Series OS 78 0 Basics EEU 5010 Fuzzy Knowledge Data Creation Tool EEU 829 EEU1438 78K
115. Internal clock output Parameter SCKO cycle time tkcy1 Conditions 1200 SCKO high low level width te tkcy1 2 100 510 setup time to SCKO tsik1 150 510 hold time from SCKO tksi1 500 500 output delay time from 4 tkso1 C 100 pF Nete Note Cis the load capacitance of 500 SCKO output line 3 wire serial I O mode SCKO External clock output Parameter SCKO cycle time tkcvi Conditions SCKO high low level width 1 510 setup time to SCKO tsik1 510 hold time from SCKO SOO output delay time from 4 tkso1 C 100 pF Note Note C is the load capacitance of 500 SCKO output line 474 User s Manual U12670EE3VOUD00 Chapter 25 Electrical Specifications 2 wire serial I O mode SCK1 Internal clock output Parameter Conditions SCK1 cycle time 2000 SCK1 high level width 5 2 160 SCK1 low level width R 1KO 5 2 160 SI1 setup time to SCK1 C 100 pF Note 300 SI1 hold time from SCK1 600 501 output delay time from SCK1 4 Note R and are the load resistance and the load capacitance of the 511 501 and SCK1 output line 3 wire serial I O mode SCK1 External clock output Parameter Conditions SCK1 cycle time SCK1 high level width SCK1 lo
116. Output Control Circuit Functions 199 11 2 Clock Output Control Circuit Configuration 200 11 3 Clock Output Function Control 201 Chapter 12 A D 203 12 1 A D Converter 203 12 2 A D Converter Configuration 204 12 3 A D Converter Control Registers 206 12 4 A D Converter 209 12 4 1 Basic Operations of A D 1 209 12 4 2 Input voltage and conversion results 211 124 3 A D converter operation 213 12 5 A D Converter 215 12 6 Cautions on Emulation 218 12 6 1 D A converter mode register 218 User s Manual U12670EE3VOUDO00 11 Chapter 13 Serial Interface Channel 30 219 13 1 Serial Interface Channel 30 219 13 2 Serial Interface Channel 30 22
117. P21 can be used for port function User s Manual U12670EE3VOUDO00 221 Chapter 13 Serial Interface Channel 30 13 5 Serial Interface Operations This section explains two modes of SIO30 13 5 1 Operation stop mode This mode is used if the serial transfers are not performed to reduce power consumption During the operation stop mode the pins be used as normal I O ports as well Register settings The operation stop mode can be set via the serial operation mode register 30 CSIM30 CSIM30 be set via an 1 bit or an 8 bit memory manipulation instructions The RESET input sets the value to 00H Figure 13 3 Format of Serial Operation Mode Register 30 CSIM30 After Reset lt gt 6 5 4 3 2 1 0 R W Address 51030 Operation Enable Disable Specification Shift register operation Serial counter Port Operation stop Clear Port functionNete 1 Operation enable Count operation enable Serial operation port function Note When CSIE30 0 SIO30 operation stop status the pins connected to SIO and SOO can be used for port functions 222 User s Manual U12670EE3VOUDOO Chapter 13 Serial Interface Channel 30 13 5 2 Three wire serial mode The three wire serial I O mode is useful when connecting a peripheral I O device that includes a clock synchronous serial interface a display controller etc This mode executes the data transfer via three lines a serial clock line SCKO serial output line
118. PM2 to PM7 12 PM13 and 14 are independently set with a 1 bit or 8 bit memory manipulation instruction RESET input sets registers to FFH When port pins are used as alternate function pins set the port mode register and output latch according to the function Cautions 1 Pins P10 to P17 are input only pins 2 As port 0 has an alternate function as external interrupt request input when the port function output mode is specified and the output level is changed the inter rupt request flag is set When the output mode is used therefore the interrupt mask flag should be set to 1 beforehand 98 User s Manual U12670EE3VOUDOO Chapter 4 Port Functions Figure 4 13 Port Mode Register Format 7 6 5 4 3 2 1 0 R W 7 6 5 4 3 2 1 0 R W 7 6 5 4 3 2 1 0 R W Pus 7 6 5 4 3 2 1 0 R W Pu 7 6 5 4 3 2 1 0 R W 7 6 5 4 3 2 1 0 R W 5 0 R W 7 6 4 3 2 1 aw 7 6 4 3 2 1 R W 6 4 3 2 1 we Pus uu 7 6 4 3 2 1 R W un Rw 5 0 7 5 0 R W 5 0 PMmn Pin Input Output Mode Selection 0 2 7 12 13 14 0 7 Output mode output buffer ON Input mode output buffer OFF User s Manual U12670EE3VOUDOO Address FF20H Address FF22H Address FF23H Address FF24H Address FF25H Address FF26H Address FF27H Address FF2CH Address FF2DH Address FF2EH After Reset FFH After Reset FFH After Reset FFH After Reset FFH Afte
119. Parity bit specification No parity Zero parity always added during transmission No parity detection during reception parity errors do not occur Odd parity Even parity CLO Character length specification 7 bits 1 8 bits 236 User s Manual U12670EESVOUDOO Chapter 15 Serial Interface UART Figure 15 2 Format of Asynchronous Serial Interface Mode Register ASIMO 2 2 Stop bit length specification for transmit data BENE bit 2 bits ISRMO Receive completion interrupt control when error occurs 0 Receive completion interrupt is issued when an error occurs 1 Receive completion interrupt is not issued when an error occurs Caution Do not switch the operation mode until the current serial transmit receive operation has stopped User s Manual U12670EE3VOUDOO 237 Chapter 15 Serial Interface UART 2 Asynchronous serial interface status register ASISO When a receive error occurs during UART mode this register indicates the type of error ASISO can be read using an 8 bit memory manipulation instruction When RESET is input its value is OOH Figure 15 3 Format of Asynchronous Serial Interface Status Register ASISO 7 6 5 4 3 2 1 0 Address Alter Reset PEO Parity error flag No parity error Parity error Incorrect parity bit detected No framing error Framing errorNete 1 Stop bit not detected No overrun error Overrun errorNote 2 Next receive op
120. Port Configuration Item Configuration Port mode register PMm m 0 2 to 7 12 13 14 Pull up resistor option register PUm m 0 4 7 13 Port function register PFm m 2 5 7 12 13 14 Memory expansion mode register MEM Control register Port Total 79 ports Pull up resistor Software specifically for 32 pins 86 User s Manual U12670EE3VOUDOO Chapter 4 Port Functions 4 2 4 Port Port 0 is an 8 bit input output port with output latch POO to PO7 pins can specify the input mode output mode in 1 bit units with the port mode register 0 When POO to PO7 pins are used as input pins a pull up resistor can be connected to them bit wise with the pull up resistor option register PUO Dual function include external interrupt request input external count clock input to the timer and timer output RESET input sets port 0 to input mode Figure 4 2 shows block diagram of port 0 Caution Because port 0 also serves for external interrupt request input when the port func tion output mode is specified and the output level is changed the interrupt request flag is set Thus when the output mode is used set the interrupt mask flag to 1 Figure 4 2 P00 to P07 Configurations Voo e Ode WRPuo o 2 n Lo c POO INTPO 5 Output Latch PO1 INTP1 to to P07 P07 TI51 TO51 PMOO to 07 e Remarks 1 PU Pull up resistor
121. Ran 87 4 2 2 POA eos LM Lo b ed Patt ls 88 4 2 3 POM cide Dats ag ah Oats dd heads Hawtin ende phage eae 89 4 2 4 ate sitesi ce iS erat ye Mae tae GUB aw 90 4 2 5 POM Ar cv godt teo er evecare endeared th ae een 91 4 2 6 POMS ha Se te Bair pmo Lol e Mos es 92 4 2 7 Port 6c RE D Sead Peete ed ante er Ga ste sonda 93 4 2 8 Rein A 94 4 2 9 95 42 10 Port 19 4 i sore rer DESERT ER ben eos 96 4 2 11 Port 14 Datta EUREN ACER E Ge ERE e ice ds 97 43 Port Function Control 98 4 4 Port Function Operations 103 4 4 1 Writing to input output port 2 RII 103 4 4 2 Reading from input output 4 103 4 4 3 Operations on input output 104 Chapter5 Clock 105 5 1 Clock Generator 105 5 2 Clock Generator 106 5 3 Clock Generator Control Register 107 5 4 System Clock
122. Receive interrupt User s Manual U12670EE3VOUD00 Chapter 16 CAN Controller 16 18 6 Receive Task Oriented Figure 16 54 Receive Software Polling Receive Polled Uses CLR1 command No Read or process data Data was changed by CAN during the processing End Receive Polled User s Manual U12670EE3VOUDOO 329 MEMO 330 User s Manual U12670EESVOUDOO Chapter 17 LCD Controller Driver 17 1 LCD Controller Driver Functions The functions of the LCD controller driver incorporated in the uPD780948 Subseries are listed below 1 Automatic output of segment signals and common signals is possible by automatic reading of the display data memory 2 Display mode 9 Static 1 2 duty 1 2 bias 1 3 duty 1 2 bias 1 3 duty 1 3 bias 1 4 duty 1 3 bias wa Any of four frame frequencies be selected each display mode 4 Maximum of 40 segment signal outputs SO to S39 4 common signal outputs COMO to COMS All segment outputs can be switched to input output ports 147 50 to P140 S7 P137 S8 to P130 S15 and 127 516 to P120 S23 are byte wise switchable P77 S24 to P70 S31and P57 S32 to P50 S39 are bitwise switchable The maximum number of displayable pixels is shown in Table 17 1 Table 17 1 Bias Method Time Division Static Maximum Number of Display Pixels Common Signals Used COMO COMI 2 3 Maximum Number of Display Pixels 40 40 segments x 1 co
123. Sce We MSS X cl TMO count value Timer starts 16 bit compare register setting Set another value than 0000H to the 16 bit captured compare register CROO CRO1 This means that a 1 pulse count operation cannot be performed when it is used as event counter Setting compare register during timer count operation If the value to which the current value of the 16 bit capture compare register 00 00 has been changed is less than the value of the 16 bit timer register TMO TMO continues counting over flows and starts counting again from 0 If the new value of CROO is less than the old value the timer must be restarted after the value of CROO has been changed Figure 6 27 Timing after Changing Compare Register during Timer Count Operation CROO N X TMocount X X 1 X X X 1 FFFFH 0000H 0001H 0002H Remark gt gt User s Manual U15251EE3VOUDOO 145 Chapter6 16 Bit Timer Event Counter 0 4 Data hold timing of capture register If the valid edge is input to the TIOO pin while the 16 bit capture compare register 01 CRO1 is read 01 performs the capture operation but this capture value is not guaranteed However the interrupt request flag INTTMO1 is set as a result of detection of the valid edge Figure 6 28 Data Hold Timing of Capture Register TMO count N 1 2 X X X MH 2 Edge input Interrupt request flag Capture read signal
124. Start of frame Remark This frame is transmitted when the reception node requests transmission Data field is not transmitted even if the data length code z 0 in the control field User s Manual U12670EE3VOUDOO 257 Chapter 16 CAN Coniroller 16 1 4 Description of each field 1 R indicates recessive level D indicates dominant level Start of frame The start of data frame and remote frame are indicated Figure 16 3 Data Frame Interframe space Start of frame Arbitration field on bus idle T R D 1 bit The start of frame SOF is denoted by the falling edge of the bus signal Reception continues when Dominant level is detected at the sample point The bus becomes idle state when Recessive level is detected at a sample point 2 Arbitration field Sets priority specifies data frame or remote frame and defines the protocol mode Figure 16 4 Arbitration Field Standard Format Mode a Arbitration field T Control field R Identifier 1028 1018 11 bits 1 bit 1 bit 258 User s Manual U12670EE3VOUD00 Chapter 16 CAN Controller Figure 16 5 Arbitration Field Extended Format Mode Arbitration field T Control field Identifier 1017 1 18bits Identifier 1028 1018 11 bits 1 bit 1 bit 28 IDO is the identifier The identifier is transmitted with MSB at first position Substitute Remote Request SRR is only
125. Supplementary explanation to the text Numeric notation Binary XXXX or Decimal Hexadecimal XXXXH or Ox Prefixes representing powers of 2 address space memory capacity kilo 21 1024 M mega 229 10242 1 048 576 G giga 230 10243 1 073 741 824 User s Manual U12670EE3VOUD00 Table of Contents Preface ios E ER ERVARAKREAEGRWA eae E ks 5 Chapter 1 Outline qPD780948 Subseries 27 121 beatles onere eee etu eue tea aeneum ag 27 1 2 ek at Ae cit LM aL S EL d 27 1 3 Ordering 28 1 4 Quality Grade or lu LIVE v xxu eee ers e euis 28 1 5 Pin Configuration Top 29 1 6 78 0 Series Expansion 31 1 7 BlockDiagram secs o See cae a a as De ae gre IRA 33 1 8 Overview of Functions 34 1 9 Mask Optiony aie le ETHER EE ee eee 35 1 10 Differences between Flash and Mask ROM 35 Chapter 2 Pin Function uPD780948 37 2 Lists acers etn neha ni 37 2 22 Non POr PING lt x oe eee Sa
126. This is an 8 bit input output port Besides serving as input output port they function as segment signal output pins of LCD controller driver The following operating modes can be specified bit wise or byte wise 1 Port mode These ports function as 8 bit input output ports They can be specified bit wise as input or output ports with port mode register 12 2 Control mode These ports function as segment output signal pins S16 to S23 of LCD controller driver 2 3 10 P130 to P137 Port 13 This is an 8 bit input output port Besides serving as input output port they function as segment signal output pins of LCD controller driver The following operating modes can be specified bit wise or byte wise 1 Port mode These ports function as 8 bit input output ports They can be specified bit wise as input or output ports with port mode register 13 When used as input ports pull up resistors can be connected by defining the pull up resistor option register 13 2 Control mode These ports function as segment output signal pins S8 to 515 of LCD controller driver 2 3 11 P140 to P147 Port 14 This is an 8 bit input output port Besides serving as input output port they function as segment signal output pins of LCD controller driver The following operating modes can be specified bit wise or byte wise 1 Port mode These ports function as 8 bit input output ports They can be specified bit wise as input or output ports with p
127. User s Manual U12670EE3VOUDOO 211 Chapter 12 A D Converter Figure 12 8 Relation between Analog Input Voltage and A D Conversion Result 55 ao go ca ot 2 o gt lt 512 256 512 256 512 512 256 512 256 512 256 Input voltage AVop User s Manual U12670EE3VOUD00 212 Chapter 12 A D Converter 12 4 3 A D converter operation mode The operation mode of the A D converter is the select mode One analog input channel is selected from among ANIO to ANI7 with the analog input channel specification register ADS1 and A D conversion is performed when bit ADCS1 in ADM1 is set to 1 The following two types of functions can be selected by setting the PFEN flag of the PFM register 1 2 Normal 8 bit A D converter PFEN 0 Power fail detection function PFEN 1 A D conversion when PFEN 0 When bit 7 ADCS1 of the A D converter mode register ADM1 is set to 1 and bit 7 of the power fail compare mode register PFM is set to 0 A D conversion of the voltage applied to the analog input pin specified with the analog input channel specification register ADS1 starts Upon the end of the A D conversion the conversion result is stored in the A D conversion result register ADCR1 and the interrupt request signal INTAD is generated After one A D conversion operation has ended the next conversion operation is immediately started A D
128. X X 1 Na Capture 5 Setting valid edge Before setting the valid edge of the 00 70 pin stop the timer operation by resetting bits 2 and 02 and TMCO3 of the 16 bit timer mode control register to 0 0 Set the valid edge by using bits 4 and 5 500 and 501 of the prescaler mode register 0 146 User s Manual U15251EE3VOUD00 Chapter 6 16 Bit Timer Event Counter 0 6 Operation of OVFO flag 7 The OVFO flag is set to 1 in the following case Select mode in which 16 bit timer counter is cleared and started on coincidence between TMO and CROO l Set 00 to FFFFH l When TMO counts up from FFFFH to 0000H Figure 6 29 Operation Timing of OVFO Flag Count pulse CROO FFFFH OVFO INTTMOO Contending operations a The contending operation between the read time of 16 bit capture compare register 00 01 and capture trigger input CROO CRO1 used as capture register Capture trigger input is prior to the other The data read from CROO CRO 1 is not defined b The coincidence timing of contending operation between the write period of 16 bit cap ture compare register CROO CRO1 and 16 bit timer register 00 01 used as a compare register The coincidence discriminant is not performed normally Do not write any data to CROO CRO1 near the coincidence timing User s Manual U15251EE3VOUDOO 147 6 16 Bit Timer Event Counter 0 8 Timer op
129. addr16 e BTCLR PSW bit addr16 El DI e Manipulate instructions for IFOL IFOH IF1L IF1H MKOL MKOH MK1L PROL PROH PR1L PR1H EGP EGN registers Caution BRK instruction is not an interrupt request reserve instruction described above However in a software interrupt started by the execution of BRK instruction the IE flag is cleared to 0 Therefore interrupt requests are not acknowledged even when a maskable interrupt request is issued during the execution of the BRK instruction However non maskable interrupt requests are acknowledged 386 User s Manual U12670EESVOUDOO Chapter 19 Interrupt Functions Figure 19 14 shows the interrupt request hold timing Figure 19 14 Interrupt Request Hold CPU processing Save PSW Interrupt service Instruction N Instruction M Jump to interrupt service program xxIF Remarks 1 Instruction N Instruction that holds interrupts requests 2 Instruction M Instructions other than interrupt request pending instruction 3 The xxPR priority level values do not affect the operation of xxIF interrupt request User s Manual U12670EE3VOUDOO 387 MEMO 388 User s Manual U12670EESVOUDOO Chapter 20 External Device Expansion 20 1 External Device Expansion Functions The external device expansion functions connect external devices to areas other than the internal ROM RAM and SFR Connection of external devices uses ports 4 to 6 Po
130. addresses where the SFR is not assigned 3 1 4 External memory space The external memory space is accessible by setting the memory expansion mode register External memory space can store program table data etc and allocate peripheral devices User s Manual U12670EE3VOUDOO 59 Chapter 3 CPU Architecture 3 1 5 Data memory addressing The uPD780948 Subseries is provided with a verity of addressing modes which take account of mem ory manipulability etc Special addressing methods are possible to meet the functions of the special function registers SFRs and general registers The data memory space is the entire 64K byte space 0000 to FFFFH Figures 3 3 and 3 4 show the data memory addressing modes For details of addressing refer to 3 4 Operand Address Addressing on page 74 Figure 3 3 Data Memory Addressing of uPD780948 FFFFH Special Function Registers i FF20H SFRs 256 x 8 bits SFR Addressing CNW eius cue CARE Se FFOOH FEFFH i tu Short Direct General Registers Register Addressing Addressing 32 x 8 bits FEDFH Internal High speed RAM 1024 x 8 bits FE20H FBOOH Not usable FA80H FA7FH LCD Display RAM Direct FASSA 40 x 4 bits Addressing FA57H Register Indirect Addressing Not usable Based Addressing 7 Based Indexed REDEH Addressing Internal Expansion RAM 992 x 8 bits F400H F3FFH External Memory FOOOH EFFFH Internal
131. an LCD panel deteriorates if a DC voltage is applied in the common signals and segment signals it is driven by AC voltage 1 Common signals For common signals the selection timing order is as shown in Table 17 3 according to the number of time divisions set and operations are repeated with these as the cycle In the static display mode the same signal is output to COMO through With 2 time division operation pins COM2 and are left open and with 3 time division oper ation the COMG pin is left open Table 17 3 COM Signals COM signal Time division Static 2 time division 3 time division 4 time division 2 Segment signals Segment signals correspond to a 40 byte LCD display data memory Each display data memory bit 0 bit 1 bit 2 and bit 3 is read in synchronization with the COMO COM1 2 and COMS tim ings respectively and if the value of the bit is 1 it is converted to the selection voltage If the value of the bit is 0 it is converted to the non selection voltage and send to a segment pin SO to S39 Consequently it is necessary to check what combination of front surface electrodes correspond ing to the segment signals and rear surface electrodes corresponding to the common signals of the LCD panel to be used to form the display pattern and then write a bit data corresponding on a one to one basis with the pattern to be displayed In addition because LCD displa
132. and CR51 are changed are smaller than those of 8 bit timer registers TM50 and TM51 TM50 51 continue counting overflow and then restarts counting from 0 Thus if the value after CR50 and CR51 change is smaller than that before change it is necessary to restart the timer after changing CR50 and CR51 Figure 8 22 Timings after Compare Register Change during Timer Count Operation CRn N X M TMn Count Value X4 Um y gt FFFFH 0000H 0001H 0002H Remark 50 51 4 50 51 read during timer operation When 50 and 51 read during operation choose a select clock which has a longer high low level wave because the select clock is stopped temporarily User s Manual U12670EE3VOUDOO 183 MEMO 184 User s Manual U12670EE3VOUDOO Chapter 9 Watch Timer 9 1 Watch Timer Functions The watch timer has the following functions Watch timer e Interval timer The watch timer and the interval timer can be used simultaneously The Figure 9 1 shows Watch Timer Block Diagram Figure 9 1 Block Diagram of Watch Timer Clear 9 bit prescaler Selector 5 bit counter INTWT A Selector Hus fw fw fw Clear 5 8 INTWTI N o wrmt wTMo Watch timer mode control register WTM Internal bus User s Manual U12670EE3VOUDOO 185
133. conversion opera tions are repeated until new data is written to ADS1 If ADS1 is rewritten during A D conversion operation the A D conversion operation under execu tion is stopped and A D conversion of a newly selected analog input channel is started If data with ADCS1 set to 0 is written to ADM1 during A D conversion operation the A D conver sion operation stops immediately Power fail detection function when PFEN 1 When bit 7 ADCS1 of the A D converter mode register ADM1 and bit 7 PFEN of the power fail compare mode register PFM are set to 1 A D conversion of the voltage applied to the analog input pin specified with the analog input channel specification register ADS1 starts Upon the end of the A D conversion the conversion result is stored in the A D conversion result register ADCR1 compared with the value of the power fail compare threshold value register PFT and INTAD is generated under the condition specified by the PFCM flag of the PFM regis ter Caution When executing power fail comparison the interrupt request signal INTAD is not generated on completion of the first conversion after ADCS1 has been set to 1 INTAD is valid from completion of the second conversion User s Manual U12670EE3VOUDOO 213 Chapter 12 A D Converter Figure 12 9 A D Conversion ADM rewrite ADCS1 1 ADS1 rewrite ADCS1 0 A D conversion Conversion suspended p Stop Conversion results are not stored INTAD
134. key words and must be described as they are Each symbol has the following meaning Immediate data specification Absolute address specification Relative address specification Indirect address specification In the case of immediate data describe an appropriate numeric value or a label When using a label be sure to describe the and symbols For operand register identifiers r and rp either function names X A C etc or absolute names names in parentheses in the table below RO R1 R2 etc can be used for description Table 24 1 Operand Identifiers and Description Methods X RO A R1 C R2 B R3 E R4 D R5 L R6 H R7 AX RPO BC RP1 DE RP2 HL RP3 Special function register symbolNote sfrp Special function register symbol 16 bit manipulatable register even addresses only Note saddr FE20H FF1FH Immediate data or labels saddrp FE20H FF1FH Immediate data or labels even address only 0000H FFFFH Immediate data or labels Only even addresses for 16 bit data transfer instructions addr1 1 0800H 0FFFH Immediate data or labels addr5 0040H 007FH Immediate data or labels even address only word 16 bit immediate data or label addr16 byte 8 bit immediate data or label bit 3 bit immediate data or label RBn RBO to RB3 Note Addresses from FFDOH to FFDFH cannot be accessed with these operands Remark For special function register symbols refer
135. lt byte CY Ar Note 3 A CY lt CY A CY lt A CY A laddr 6 A CY lt A addr16 CY A HL A HL byte A CY lt A HL byte CY A HL B MD A A CO A BR A A CY lt HL CY A CY lt HL CY A HL C 1 3 3 1 2 3 2 2 2 3 1 2 2 2 2 3 2 2 2 3 1 2 2 2 A CY A HL C When the internal high speed RAM area is accessed or instruction with no data access When an area except the internal high speed RAM area is accessed Except r A Only when rp BC DE or HL XIX XIX XXI X X XIXI X X X X X XIX x XIX XIXI KIVIAIA AI AX TAEK KK XX XI X X XI X X XIXI X X X X X XIX X XIX 1 One instruction clock cycle is one cycle of the CPU clock selected by the PCC register 2 This clock cycle applies to internal ROM program nis the number of waits when external memory expansion area is read from mis the number of waits when external memory expansion area is written to 426 User s Manual U12670EE3VOUD00 Instruction Group Mnemonic Operands A byte Chapter 24 N Instruction Set Table 24 2 Operation List 3 8 A CY lt
136. manipulation instruction RESET input sets CKS to 00H Caution When enabling PCL output set CCSO to CCS2 then set 1 CLOE with an 1 bit memory manipulation instruction Figure 11 3 Timer Clock Select Register 0 Format After 7 6 5 lt 4 gt 3 2 1 0 R W Address Reset PCL Output Clock Selection fx 8 MHz fx 2 4 MHz fx 2 2 MHz fy 23 1 MHz 6 2 500 KHz 25 250 KHz 1 26 125 KHz 1 1 27 62 5 KHz Other than above Setting prohibited CLOE PCL Output Control Output disable Output enable Remarks 1 fy Main system clock oscillation frequency 2 Figures in parentheses apply to operation with fy 8 0 MHz User s Manual U12670EE3VOUDOO 201 Chapter 11 Clock Output Control Circuit 2 Port mode register 3 PM3 With this register the port mode can be set bit wise When using the P33 PCL SGOA pin for clock output function set PM33 and output latch of P33 to 0 is set with an 1 bit or an 8 bit memory manipulation instruction RESET input sets PM3 to FFH Figure 11 4 Port Mode Register 6 Format After 7 6 5 4 3 2 1 0 R W Address Reset EC TEN E EN 244 PM3n PM3n Pin Input Output Mode Selection n 0 to 4 0 Output mode output buffer ON 1 Input mode output buffer OFF 202 User s Manual U12670EE3VOUDOO Chapter 12 A D Converter 12 1 A D Converter Functions The A D converter is an 8 bit reso
137. mode can be specified bit wise GU P70 P77 If used an input port a pull up resistor can be connected by S31 S24 Input software This port can be used as a segment signal output port or an I O port in 1 bit units by setting the port function register 84 User s Manual U12670EE3VOUD00 Pin Name P120 P127 Chapter 4 Port Functions Table 4 1 Pin Input Output Types 2 2 Function Port 12 8 bit input output port Input output mode can be specified bit wise If used an input port a pull up resistor can be connected by software This port can be used as a segment signal output port or an I O port in 8 bit units by setting the port function register Alternate Function 523 516 130 137 Port 13 8 bit input output port Input output mode can be specified bit wise If used an input port a pull up resistor can be connected by software This port can be used as a segment signal output port or an I O port in 8 bit units by setting the port function register P140 P147 Port 14 8 bit input output port Input output mode can be specified bit wise If used an input port a pull up resistor can be connected by software This port can be used as a segment signal output port or an I O port in 8 bit units by setting the port function register User s Manual U12670EE3VOUDOO 85 Chapter 4 Port Functions 4 2 Port Configuration A port consists of the following hardware Table 4 2
138. occupied by a former transmit request Setting the transmission request bit requests the DCAN to sent the buffer contents onto the bus The DCAN clears the bit after completion of the transmission Completion is either a normal transfer without error or an abort request User s Manual U12670EE3VOUDOO 313 Chapter 16 CAN Coniroller An error during the transmission does not influence the transmit request status The DCAN will auto matically retry the transfer Cautions 1 The bits are cleared when the INIT bit in CANC is set A transmission already started will be finished but not retransmitted in case of an error Writing a 0 to TXRQO bit has no influence Do not use bit operations on this register Do not change data in transmit buffer when the corresponding TXRQ bit is set 16 15 2 Receive Control The receive message register mirrors the current status of the first 8 receive buffers Each buffer has one status bit in this register This bit is always set when a new message is completely stored out of the shadow buffer into the associated buffer The CPU can easily find the last received message during receive interrupt handling The bits in this register always correspond to the DN bit in the data buffers They are cleared when the CPU clears the DN bit in the data buffer The register itself is read only 1 Receive message register This register shows receptions of messages of the DCAN module More than one bit set is possi b
139. operation of the target system on a host machine This simulator runs on Windows Use of the 5 78 0 allows the execution of application logical testing and per formance testing on an independent basis from hardware development without having to use an in circuit emulator thereby providing higher development effi ciency and software quality The SM78KO should be used in combination with the optional device file ID78K0 NS Integrated Debugger supporting In Circuit Emulator IE 78K0 NS A This debugger is a control program to debug 78K 0 Series microcontrollers It adopts a graphical user interface which is equivalent visually and operationally to Windows or OSF Motif It also has an enhanced debugging function for C language programs and thus trace results can be displayed on screen in C lan guage level by using the windows integration function which links a trace result with its source program disassembled display and memory display In addition by incorporating function modules such as task debugger and system perform ance analyzer the efficiency of debugging programs which run on real time OSs can be improved It should be used in combination with the optional device file User s Manual U12670EE3VOUDOO 495 MEMO 496 User s Manual U12670EE3VOUDOO Appendix B Embedded Software For efficient development and maintenance of the uPD780948 Subseries the following embedded soft ware products are available B
140. or FFH User s Manual U12670EE3VOUDOO 101 Chapter 4 Port Functions 4 Memory expansion mode register MEM This register is used to set input output of port 4 5 and 6 MM is set with an 1 bit or an 8 bit memory manipulation instruction RESET input sets this register to OOH Figure 4 16 Memory Expansion Mode Register Format 7 6 5 4 3 2 1 0 RW Address ter Reset Single chip Memory Expansion P40 P47 P50 P57 P64 P65 P67 Pin State Mode Selection 40 47 P50 P53 P54 P55 P56 P57 P64 P67 Single chip mode Port mode Port mode 256 byte mode Port mode Memory 4 Kbyte mode Port mode P64 RD as sion 16 Kbyte mode A8 A11 Port mode A12 A13 1 Full address modeNote 14 15 Other than above Setting prohibited Note The full address mode allows external expansion for all areas of the 64 Kbyte address space except the internal ROM RAM SFR and use prohibited areas 102 User s Manual U12670EE3VOUDOO Chapter 4 Port Functions 4 4 Port Function Operations Port operations differ depending on whether the input or output mode is set as shown below 4 4 4 Writing to input output port 1 Output mode A value is written to the output latch by a transfer instruction and the output latch contents are output from the pin Once data is written to the output latch it is retained until data is written to the output latch again 2 Input mo
141. parity errors do not occur Odd parity Even parity Character length specification 0 7 bits 1 8 bits 242 User s Manual U12670EE3VOUDOO Chapter 15 Serial Interface UART Figure 15 6 Format of Asynchronous Serial Interface Mode Register ASIMO 2 2 Stop bit length specification for transmit data BENE bit 2 bits ISRMO Receive completion interrupt control when error occurs 0 Receive completion interrupt is issued when an error occurs 1 Receive completion interrupt is not issued when an error occurs Caution Do not switch the operation mode until the current serial transmit receive operation has stopped User s Manual U12670EE3VOUDOO 243 Chapter 15 Serial Interface UART b Asynchronous serial interface status register ASISO ASISO can be read using an 8 bit memory manipulation instruction When RESET is input its value is OOH Figure 15 7 Format of Asynchronous Serial Interface Status Register 5150 7 6 5 4 3 2 1 0 RM Address ter Reset PEO Parity error flag No parity error Parity error Incorrect parity bit detected No framing error Framing errorNote 1 Stop bit not detected No overrun error Overrun errorNote 2 Next receive operation was completed before data was read from receive buffer register Notes 1 Even if a stop bit length of two bits has been set to bit 2 SLO in the asynchronous serial interface mode register ASIMO the st
142. prohibited Remark fy Main system clock oscillation frequency at 8 00 MHz Note Bit 3 has to be set to O 334 User s Manual U12670EE3VOUDOO Chapter 17 LCD Controller Driver 2 LCD display control register LCDC This register sets cutoff of the current flowing to split resistors for LCD drive voltage generation and switchover between segment output and input output port functions LCDC is set with an 1 bit or 8 bit memory manipulation instruction RESET input clears LCDC to 00H Figure 17 4 LCD Display Control Register LCDC Format Symbol 7 6 0 Address After Reset R W 5 4 3 2 1 LIPS LCD Driving Power Supply Selection 0 Does not supply power to LCD 1 Supplies power to LCD from Vpp pin Caution Set bit 7 to 1 and bit 1 to bit 6 to 0 17 4 LCD Controller Driver Settings LCD controller driver settings should be performed as shown below 1 Setthe initial value in the display data memory FA58H to FA7FH 2 Set the pins to be used as segment outputs in port function registers PF5 PF7 PF12 PF13 and PF14 3 Set the LCD power supply in the LCD display control register 4 Set the LCD clock in the LCD display mode register LCDM Next set data in the display data memory according to the display contents User s Manual U12670EE3VOUDOO 335 Chapter 17 LCD Controller Driver 17 5 LCD Display Data Memory The LCD display data memory is mapped onto addre
143. reaches up to 10 V with RESET terminal activated on board programming mode becomes available After release of RESET the programming mode is selected by the number of Vpp pulses 23 3 3 Flash memory programming function Flash memory writing is performed through command and data transmit receive operations using the selected transmission method The main functions are listed in Table 23 5 Table 23 5 Main Functions of Flash Memory Programming Function Description Reset Detects write stop and transmission synchronization Batch verify Compares the entire memory contents and input data Batch delete Deletes the entire memory contents Batch blank check High speed write Checks the deletion status of the entire flash memory Performs writing to the flash memory according to the write start address and the number of write data bytes Continuous write Status Performs successive write operations using the data input with high speed write operation Checks the current operation mode and operation end Oscillation frequency setting Inputs the resonator oscillation frequency information Delete time setting Baudrate setting Inputs the flash memory delete time Sets the transmission rate when the UART method is used Silicon signature read User s Manual U12670EE3VOUDOO Outputs the device name memory capacity and device block information 419 Chapter 23 PD78F0948 23 3
144. register Control mode In this mode these ports function as an external interrupt input an external count clock input to the timer and a timer signal output a INTPO to INTP4 INTPO to INTP4 are external interrupt input pins which can specify valid edges rising edge falling edge and both rising and falling edges INTP4 becomes a 16 bit timer event counter capture trig ger signal input pin with a valid edge input b 00 Pin for external count clock input to 16 bit timer event counter and pin for capture trigger signal input to the 16 bit timer event counter capture register 01 Pin for capture trigger signal input to capture register of 16 bit timer event counter CROO d 50 Pin for external count clock input to 8 bit timer event counter TI51 Pin for external count clock input to 8 bit timer event counter f TOO Pin for output of the 16 bit timer event counter g TO50 Pin for output of the 8 bit timer event counter h TO51 Pin for output of the 8 bit timer event counter i T2PO Pin for output of the 16 bit timer 2 User s Manual U12670EE3VOUDOO 41 Chapter 2 Pin Function uPD780948 Subseries 2 3 2 P10 to P17 Port 1 This is an 8 bit input output port Besides serving as input output port they function as an A D con verter analog input The following operating modes can be specified bit wise 1 2 Port mode These ports function as 8 bit inp
145. register ASISO Baudrate generator control register BRGCO Transmit shift register 50 Receive buffer register RXBO Mode register ADM1 Conversion result register ADCR1 A D converter Input select register ADS1 Power Fail Comparator Mode Register PFM Power Fail Threshold Register PFT Mode register LCDM Control register LCDC Request flag register IFOL IFOH IF1L IF 1H Mask flag register MKOL MKOH MK1L Priority specify flag register PROL PROH PR1L PR1H External interrupt rising edge register EGP LCD controller driver External interrupt falling edge register EGN Control register CANC Transmit control register TCR Receive message register RMES Redefinition register REDEF Error status register CANES Transmit error counter register TEC Receive error counter register REC Message count register MCNT Bit rate prescaler register BRPRS Synchronous control register SYNCO Synchronous control register SYNC1 Mark control register MASKC 414 User s Manual U12670EE3VOUDOO Chapter 23 pPD78F0948 The flash memory versions of the uPD780948 Subseries includes the uPD78F0948 The uPD78F0948 replaces the internal mask ROM of the uPD780948 with flash memory to which program can be written deleted and overwritten while mounted on the PCB Table 23 1 lists th
146. s Manual U12670EE3VOUDOO Chapter 25 Electrical Specifications 2 pPD780948 A1 40 C to 110 C Vpp 4 0 to 5 5 V Resonator Recommended circuit Parameter Test Conditions 4 0 V lt Vpp lt 5 5 V R 510 Ko Note 33 pFNote 2 Oscillator Note 1 frequency fxr Note 1 CL1 Input oy lt Vpp lt 5 5V frequency fxr CL1 Input high low level 4 0 V lt Vpp lt 5 5 V width txth Notes 1 Only oscillator circuit characteristics are shown Regarding instruction execute time please refer to AC characteristics Reference data CAN operation with external clock Cautions 1 When using the subsystem clock oscillation circuit wiring in the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance Wiring should be as short as possible Wiring should not cross other signal lines Wiring should not be placed close to a varying high current The potential of the oscillation circuit capacitor ground should always be the same as that of Vss Do not ground wiring to a ground pattern in which a high current flows Do not fetch a signal from the oscillation circuit The subsystem clock oscillation circuit is designed to be a circuit with a low amplification level for low power consumption more prone to mis operation due to noise than that of the main system clock Therefore when
147. s Manual U12670EE3VOUDOO 279 Chapter 16 CAN Coniroller 16 7 Message and Buffer Configuration Table 16 19 Message and Buffer Configuration Address Note 2 Register Name After Reset Transmit buffer 0 Transmit buffer 1 Receive message 0 Mask 0 Receive message 1 Receive message 2 Mask 1 Receive message 3 Receive message 4 Receive message 5 Receive message 6 Receive message 7 Receive message 8 Receive message 9 Receive message 10 Receive message 11 Receive message 12 Receive message 13 Receive message 14 Receive message 15 Notes 1 Contents is undefined because data resides in normal RAM area 2 This address is an offset to the RAM area starting address defined with CADDO 1 in the message count register MONT 280 User s Manual U12670EE3VOUD00 Chapter 16 CAN Controller 16 8 Transmit Buffer Structure The DCAN has two independent transmit buffers The two buffers have a 16 byte data structure for standard and extended frames with the ability to send up to 8 data bytes per message The structure of the transmit buffer is similar to the structure of the receive buffers The CPU can use addresses that are specified as unused in the transmit buffer layout As well the CPU may use unused ID addresses unused data addressesN t and an unused transmit buffer of the for its own purposes con trol bits the ide
148. the port while Vppo corporates the power supply of the oscillator the CPU and the peripherals 46 User s Manual U12670EE3VOUDOO Chapter 2 Pin Function uPD780948 Subseries 2 3 22 Vss Ground potential pin The ground pin Vas corporates the ground of the port while corporates the ground of the oscillator the CPU and the peripherals 2 3 23 Vpp UPD78F0948 only High voltage apply pin for FLASH programming mode setting Connect directly to Vss in normal operat ing mode 2 3 24 IC Mask ROM version only The IC Internally Connected pin is provided to set the test mode to check the uPD78F0948 at delivery Connect it directly to the Vas with the shortest possible wire in the normal operating mode When a voltage difference is produced between the IC pin and Vss pin because the wiring between those two pins is too long or an external noise is input to the IC pin the user s program may not run normally Figure 2 1 Connection of IC Pins Vss IC TIT As short as possible Caution Connect pins to Vss pins directly User s Manual U12670EE3VOUDOO 47 Chapter 2 Pin Function uPD780948 Subseries 2 4 Pin 1 0 Circuits and Recommended Connection of Unused Pins The input output circuit type of each pin and recommended connection of unused pins are shown in the following table For the input output circuit configuration of each type see Table 2 3 Types of Pin Input Output Cir cuits o
149. the same manner The only difference is that the DCAN Stop mode prevents the wake up by CAN bus activity Caution DCAN Sleep or DCAN Stop mode can not be requested as long as the WAKE bit in CANES is set The DCAN Sleep mode is cancelled under following conditions a CPU clears the SLEEP bit b Any transition while idle state on CAN bus STOP 0 c CPU sets SLEEP but CAN protocol is active due to bus activity The WAKE bit in CANES is set under condition b and c SOFSEL Start of Frame Output Function Select Last bit of EOF is used to generate the time stamp SOF is used to generate the time stamp SOFE Start of Frame Enable 0 SOFOUT does not change 1 SOFOUT toggles depending on the selected mode Figure 16 35 DCAN Support Last bit lof EOF Data CRC 2 n MUX T D SOFOUT E Capture Register Recone SOFSEL SOFE EH Clear SOFC DCAN 16 Bit Timer The generation of an SOFOUT signal can be used for time measurements and for global time base syn chronization of different CAN nodes as a prerequisite for time triggered communication User s Manual U12670EE3VOUDOO 297 Chapter 16 CAN Coniroller Table 16 23 Possible Setup of the SOFOUT Function SOFSEL SOFOUT Function Time stamp function disabled Toggles with each E
150. to Table 3 3 Special Function Register List on page 67 User s Manual U12670EE3VOUDOO 423 Chapter 24 Instruction Set 24 1 2 Description of operation column gt gt mox PSW jdisp8 A register 8 bit accumulator X register B register C register D register E register register Lregister AX register pair 16 bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer Program status word Carry flag Auxiliary carry flag Zero flag Register bank select flag Interrupt request enable flag Non maskable interrupt servicing flag Memory contents indicated by address or register contents in parentheses Higher 8 bits and lower 8 bits of 16 bit register Logical product AND Logical sum OR Exclusive logical sum exclusive OR Inverted data addr16 16 bit immediate data or label Signed 8 bit data displacement value 25 1 3 Description of flag operation column I xX gt 424 Blank Not affected Cleared to 0 Setto 1 Set cleared according to the result Previously saved value is restored User s Manual U12670EE3VOUD00 24 2 Operation List Instruction Group Mnemonic Operands byte Chapter 24 Instruction Set Table 24 2 Operation List 1 8 Operation lt byte saddr byte sad
151. with 8 bit immediate data in an instruction word This addressing is applied to the 240 byte spaces FFOOH to FFCFH and FFEOH to FFFFH However the SFR mapped at FFOOH to FF1FH can be accessed with short direct addressing Operand format Table 3 8 Special Function Register SFR Addressing sfr Special function register name sfrp 16 bit manipulatable special function register name even address only Figure 3 18 Special Function Register SFR Addressing a Description example MOV PMO A when selecting PMO FE20H as sfr Operation code 11110110 00100000 20H sfr offset b Illustration OP code sfr offset SFR 15 8 7 0 78 User s Manual U12670EE3VOUDOO Chapter 3 CPU Architecture 3 4 6 Register indirect addressing The memory is addressed with the contents of the register pair specified as an operand The register pair to be accessed is specified with the register bank select flag RBSO and RBS1 and the register pair specify code in the instruction code This addressing can be carried out for all the memory spaces Operand format Table 3 9 Register indirect addressing DE HL Figure 3 19 Register indirect addressing a Description example MOV A DE when selecting DE as register pair Operation code 10000101 b Illustration Memory address specified by register pair DE The contents of addressed memory are transferred User s Manual
152. 0 13 3 List of SFRs Special Function 220 13 4 Serial Interface Control Register 221 13 5 Serial Interface 222 13 5 1 Operation stop mode 222 13 5 2 Three wire serial O 223 Chapter 14 Serial Interface 1 31 225 14 1 Serial Interface Channel 31 225 14 2 Serial Interface Channel 31 226 14 3 List of SFRs Special Function 226 14 4 Serial Interface Control Registers 227 14 5 Serial Interface Channel 31 228 14 5 1 Operation stop mode 228 14 5 2 serial 229 Chapter 15 Serial Interface 233 15 1 Serial Interface UART Functions 233 15 2 Serial Interface UART Configuration 234 15 3 List of SFRS Special Function Registers 235 15 4 Serial Inter
153. 0 can be selected with the timer clock select register 50 TCL50 and count clock of the 8 bit timer register 51 TM51 can be selected with the timer clock select register 51 TCL51 PWM output enable disable can be selected with bit 0 TOE50 of TMC50 or bit 0 TOE51 of TMC51 Figure 8 15 8 Bit Timer Control Register Settings for PWM Output Operation TCEn TMCn6 TMOCn4 LVSn LVRn TMCn1 TOEn TMCn TOn output enable Sets active level 8 bit timer event counter mode PWM mode TMn operation enable Setting Method Set the port latch and port mode register to 1 2 Set the active level width in the 8 bit compare register n CR5n 3 Select the count clock in the timer clock selection register n TCL5n 4 Setthe active level in bit 1 TMCn1 of TMCn 5 Count operation starts when bit 7 TCEn of TMCn is set to 1 Set TCEn to 0 to stop count operation PWM Output Operation 1 When counting starts the PWM output output from TO5n outputs the inactive level until an overflow occurs 2 When the overflow occurs the active level specified in step 1 in the setting method is output The active level is output until CRn and the count of the 8 bit counter n TMn match 3 The PWM output after CR5n and the count match is the inactive level until an overflow occurs again 4 Steps 2 and 3 repeat until counting stops 5 If counting is stopped by TCEn 0 the PWM output goes to the
154. 03 P120 P127 P130 P137 puso P140 P147 P34 Remark The characteristics of the dual function pins are the same as those of the port pins unless otherwise specified 440 User s Manual U12670EE3VOUDOO Chapter 25 Electrical Specifications 3 pPD78F0948 TA 25 C Vss 0 V Parameter Function f 1 MHz Other than measured pins 0 V P00 P07 P10 P17 P20 P26 P30 P33 P40 P47 P50 P57 Input output fy P64 P65 P67 P70 P77 P100 capacitance Other than measured 103 P120 P127 P130 P137 puse P140 P147 P34 Remark The characteristics of the dual function pins are the same as those of the port pins unless otherwise specified User s Manual U12670EE3VOUDOO 441 Chapter 25 Electrical Specifications 25 3 Main System Clock Oscillation Circuit Characteristics 1 pPD780948 A 40 C to 85 C Vpp 4 0 to 5 5 V Resonator Recommended Circuit Parameter Conditions MIN TYP MAX Unit Oscillator frequency Vpp 4 0 to 5 5 V fy Note 1 Ceramic resonator Oscillation stabiliza n iei ion time Note 2 oscillator voltage is range MIN 4 0 V Oscillator frequency Vpp 4 0 to 5 5 V f Note 1 Crystal X resonator Oscillation stabiliza pubs 2 i i Note 2 oscillator voltage range MIN 4 0 V X1 input frequency Vpp 4 0 to 5 5 V fy Note 1 open X1 input high low level
155. 1 setting ASTB E ecc MEN LLL 22 c ADO AD Xio Read Data 5 WieDaa XS A8 A15 Higher Address Internal Wait Signal 5 pom oe eee 1 clock wait 5 Vou 400 User s Manual U12670EE3VOUDOO Chapter 20 External Device Expansion 20 4 Example of Connection with Memory This section provides UPD780948 and external memory connection examples in Figure 20 9 SRAMs are used as the external memory in these diagrams In addition the external device expansion function is used in the full address mode and the address from 0000H to 7FFFH 32 Kbytes are allocated for internal ROM and the addresses after 8000H for SRAM Figure 20 9 Connection Example of uPD780948 and Memory uPD780948 Voo Vop uPD43256B xu H E Data Bus Address pyPD74HC573 Bus um User s Manual U12670EE3VOUDOO 401 MEMO 402 User s Manual U12670EE3VOUDOO Chapter 21 Standby Function 21 1 Standby Function and Configuration 21 1 1 Standby function The standby function is designed to decrease the power consumption of the system The following two modes are available 1 2 HALT mode HALT instruction execution sets the HALT mode The HALT mode is intended to stop the CPU operation clock System clock oscillator continues oscillation In this mode current consumption cannot be decreased as much as in the STOP mode The HALT mode
156. 1 Real Time OS RX78K O is a real time OS conforming with the ITRON specifications Tool configura tor for generating nucleus of RX78K 0 and plural information tables is supplied Used in combination with an optional assembler package RA78K 0 and device file RX78K 0 Real time OS specification subset OS Nucleus of MX78KO0 is supplied This OS performs task management event management and time management It controls the task exe cution sequence for task management and selects the task to be executed next 78 0 OS Caution When purchasing the RX78K O0 fill in the purchase application form in advance and sign the User Agreement B 2 Fuzzy Inference Development Support System Program that supports input edit and evaluation simulation of fuzzy knowledge FE9000 FE9200 data fuzzy rule and membership function FE9200 works on Windows Fuzzy knowledge data creation tool Part number uSxxxxFE9000 PC 9800 Series USxxxxFE9200 PC AT and compatible machines Program that translates fuzzy knowledge data obtained by using fuzzy knowledge Translator data creation tool into assembler source program for RA78KO FT9080 FT9085 Part number uSxxxxF T9080 PC 9800 Series USxxxxFT9085 IBM PC AT and compatible machines Program that executes fuzzy inference Executes fuzzy inference when linked with Era Fuzzy inference module fuzzy knowledge data translated by translator Part num
157. 16 CAN Configuration Item Configuration Message definition In RAM area 1 CTXD 1 CRXD CAN control register CANC Transmit control register TCR Receive message register RMES Redefinition control register REDEF CAN error status register CANES Transmit error counter TEC Receive error counter REC Message count register MCNT Bit rate prescaler BRPRS Synchronous control register 0 SNYCO Synchronous control register 1 SYNC1 Mask control register MASKC CAN input output Control registers 278 User s Manual U12670EE3VOUDOO Chapter 16 CAN Controller 16 6 Special Function Register for CAN module Table 16 17 SFR Definitions Bit Manipulation Units Register Name After Reset 1 bit 8 bit 16 bit CAN control register Transmit control register Receive message register Redefinition control register CAN error status register Transmit error counter Receive error counter Message count register Bit rate prescaler Synchronous control register 0 Synchronous control register 1 Mask control register The following SFR bits can be accessed with 1 bit instructions The other SFR registers have to be accessed with 8 bit instructions Table 16 18 SFR Bit Definitions Description Start of frame enable CANC 4 Sleep mode 2 Initialize 0 Redefinition enable REDEF 7 User
158. 16 bit capture compare register 01 CRO1 and an external interrupt request signal 01 is set The value of is also loaded to the 16 bit capture compare register 00 CROO when an edge reverse to the one that triggers capturing to is input The edge of the TIOO pin is specified by bits 4 and 5 500 and 501 of the prescaler mode reg ister 0 PRMO The rising or falling edge can be specified The valid edge of TIOO pin and TIO1 pin is detected through sampling at a count clock cycle selected by the prescaler mode register 0 PRMO and the capture operation is not performed until the valid level is detected two times Therefore noise with a short pulse width can be rejected Caution If the valid edge of the TIOO pin is specified to be both the rising and falling edges the capture compare register 00 CROO cannot perform its capture operation Figure 6 17 Control Register Settings for Pulse Width Measurement with Free Running Counter and Two Capture Registers a 16 bit timer mode control register TMCO TMCO3 02 01 OVFO meo o e e e Free running mode b Capture compare control register 0 CRCO CRC02 CRCO1 00 as capture register Captures to CROO at edge reverse to valid edge o f TI00 pin 01 as capture register Remark 0 1 When these bits are reset to 0 or set to 1 the other functions can be used along with the pulse width measurement function
159. 16 bit timer event counter 0 can be selected by bits 0 and 1 PRMOO and PRMO1 of the prescaler mode register 0 Figure 6 7 Control Register Settings When Timer 0 Operates as Interval Timer a 16 bit timer mode control register TMCO TMCO3 TMCO2 01 OVFO wo Tote Tele IeI Clears and starts on coincidence between 0 and 00 b Capture compare control register 0 CRCO CRC02 01 CRCOO CROO as compare register Remark 0 1 When these bits are reset to 0 or set to 1 the other functions can be used along with the interval timer function For details refer to Figures 6 2 and 6 3 130 User s Manual U15251EE3VOUD00 Chapter 6 16 Bit Timer Event Counter 0 Figure 6 8 Configuration of Interval Timer 16 bit capture compare register 00 CROO gt INTTMOO fx 2 5 7 fx 2 D 16 bit timer register TMO 01 04 Clear circuit Figure 6 9 Timing of Interval Timer Operation ke SE s TMO count vale oops OA A A Count starts Clear Clear 00 us f a a TOO Interval time Interval time Interval time Remark Interval time N 1 x t N OOOOH to FFFFH User s Manual U15251EE3VOUDOO 131 6 16 Bit Timer Event Counter 0 6 4 2 PPG output operation The 16 bit timer counter can be used for PPG Programmable Pulse Generator
160. 2 pins External clocks can be input to the subsystem clock oscillator In this case input a clock signal to the CL1 pin and open the CL2 pin Figure 5 4 shows an external circuit of the subsystem clock oscillator Figure 5 4 External Circuit of Subsystem Clock Oscillator a RC oscillation b External clock CL2 External Clock Cautions 1 When external clock is used for CAN the CPU operation and the watch timer operation with subsystem clock are prohibited The setting of the CSS bit PCC register and the WTM 7 bit WTM register to 1 is prohibited 2 When using a main system clock oscillator and a subsystem clock oscillator carry out wiring in the broken line area in Figures 5 3 and 5 4 as follows to pre vent any effects from wiring capacities Minimize the wiring length Donotallow wiring to intersect with other signal conductors Do not allow wiring to come near abruptly changing high current Set the potential of the grounding position of the oscillator capacitor to that of Vss Do not ground to any ground pattern where high current is present Do not fetch signals from the oscillator 3 Take special note of the fact that the subsystem clock oscillator is a circuit with low level amplification so that current consumption is maintained at low levels Figure 5 5 shows examples of oscillator having bad connection 110 User s Manual U12670EE3VOUDOO Chapter 5 Clock Generator F
161. 3 PM24 the output latch P23 and P24 should be 0 When used as a slave PM23 and PM24 should be 1 A static output by software is always possi ble by manipulating the output latches If itis necessary to turn off the N ch transistor for data reception FFH must be written to SIO1 reg ister in advance Figure 14 6 2 Wire Mode Connection SCK1 SCK1 Slave 511 801 Master SI1 SO1 User s Manual U12670EE3VOUDOO 231 MEMO 232 User s Manual U12670EESVOUDOO Chapter 15 Serial Interface UART 15 1 Serial Interface UART Functions The serial interface UART has the following modes 1 Operation stop mode This mode is used if the serial transfer is performed to reduce power consumption For details see 15 5 1 Operation stop mode on page 241 2 Asynchronous serial interface UART mode This mode enables the full duplex operation where one byte of data is transmitted and received after the start bit The on chip dedicated UART baud rate generator enables communications using a wide range of selectable baud rates For details see 15 5 2 Asynchronous serial interface UART mode on page 242 Figure 15 1 shows a block diagram of the UART macro Figure 15 1 Block Diagram of UART Internal bus ASIMO RXBO Pardi TXEO RXEO PS01 00 ISRMO Receive shift RxD P25 O 1 register TxD P26 O Transmit register
162. 40 AD 5 Output Latch 4 9 P40 to P47 P47 AD7 PM40 to PM47 e Remarks 1 PU Pull up resistor option register 2 PM Port mode register 3 RD Port4 read signal 4 WR Port 4 write signal User s Manual U12670EE3VOUDOO 91 Chapter 4 Port Functions 4 2 6 Port5 Port 5 is an 8 bit output port with output latch P50 to P57 pins can specify the input mode output mode in 1 bit units with the port mode register 5 PM5 Dual functions include address bus function in external memory expansion mode and segment signal outputs of LCD controller driver RESET input sets port 5 to input mode Figure 4 7 shows a block diagram of port 5 Caution When used as segment lines set the port function PF5 according to its functions Figure 4 7 P50 to P57 Configurations 07 65 WRpeort P50 to P57 to P57 A15 S32 Output Latch P50 A8 S39 Internal bus 50 to 57 Alternate Function Remarks 1 Port mode register 2 RD Port5read signal 3 WR Port 5 write signal 92 User s Manual U12670EE3VOUDOO Chapter 4 Port Functions 4 2 7 Port 6 Port 6 is a 3 bit input output port with output latch P64 P65 and P67 pins can specify the input mode output mode in 1 bit units with the port mode register 6 PM6 Dual function include the control signal output function in external memory expansion mode RESET input sets port 6 to input mode Figure 4 8
163. 404 User s Manual U12670EE3VOUDOO Chapter 21 21 2 Standby Function Operations 21 2 1 HALT mode 1 HALT mode set and operating status The HALT mode is set by executing the HALT instruction It can be set with the main system clock or the subsystem clock The operating status in the HALT mode is described below Table 21 1 HALT mode setting Clock generator HALT execution during main system clock operation Standby Function HALT Mode Operating Status HALT execution during subsystem clock operation Main system clock stops Both main and subsystem clocks can be oscillating Clock supply to the CPU stops CPU Operation stops Port output latch Status before HALT mode setting is held 16 bit timer event counter 0 Operable Operation stops 16 bit timer TM2 Operable Operation stops 8 bit timer event counter TM50 TM51 Operable Operable when is selected as count clock Watch timer Operable Operable when is selected as count clock Watchdog timer Operable Operation stops A D converter Operation stops Serial I F Operable Operable at external SCK CAN Operation stops Sound generator Operable Operation stops External interrupt to INTP4 Operable LCD C D Operable Operation stops Bus lines in external expansion ADO to AD7 High impedance A8 to A15
164. 48 Chapter 17 LCD Controller Driver Figure 17 15 2 Time Division LCD Drive Waveform Examples 1 2 Bias Method Vico COMO Vic1 Vice Vss1 Vico COM1 Vic1 Vice Vss1 Vico S31 Vic1 Vice Vss1 Vicp 1 2Vicp COMO S31 0 1 2Vicp Vicp Vicp 1 2Vicp 1 631 0 1 2Vicp Se oat Vicp User s Manual U12670EE3VOUDOO 349 Chapter 17 LCD Controller Driver 17 8 3 3 time division display example Figure 17 17 shows the connection of a 3 time division type 13 digit LCD panel with the display pattern shown in Figure 17 16 with segment signals SO to S38 and common signals COMO to COM2 The display example is 123456 7890123 and the display data memory contents correspond to this An explanation is given here taking the example of the eighth digit 6 n accordance with the dis play pattern in Figure 17 16 selection and non selection voltages must be output to pins S21 through S23 as shown in Table 17 8 at the COMO to COM2 common signal timings Table 17 8 Selection and Non Selection Voltages COMO to COM2 Segment COMO 1 2 Remark S Selection NS Non selection From this it can be seen that x110 must be prepared in the display data memory address FA12H cor responding to S21 Examples of the LCD drive waveforms between S21 and the common signals are shown in Figure 17 18 1 2
165. 5 V lt Vpp 5 5 V Remark The characteristics of the dual function pins are the same as those of the port pins unless otherwise specified User s Manual U12670EE3VOUDOO 457 Chapter 25 Electrical Specifications uPD78F0948 Parameter Conditions 8 0 MHz crystal oscillation operating mode PCC 00H Note 2 8 0 MHz crystal oscillation operating mode PCC 00H Note 3 8 0 MHz crystal oscillation current RC oscillation operating mode 40 KHz RC oscillation HALT mode 40 KHz CL1 Vpp STOP mode Notes 1 Current through Vppo Vpp1 respectively through Vsso Vss1 Excluded is the current through the inside pull up resistors through AVpp AVnggg the port current 2 CPU is operable The other peripherals like CAN controller Timer 0 Timer 2 serial interfaces A D converter etc are stopped 3 CPU and all peripherals except for the A D converter are in operating mode and PCL out put is fy 4 CPU is in HALT mode and all other peripherals except Watch timer are stopped Remarks 1 fx Main system clock oscillation frequency 2 fxr Subsystem clock oscillation frequency 3 The typical values are with respect to T4 25 C 78 0948 LCD C D Static Method Parameter Conditions LCD drive voltage LCD split resistor LCD output voltage deviation Note common lo 5pA g Vicpo Vicp LCD output voltage devi
166. 6 Bit Timer 2 Figure 7 8 Timing of Pulse Width Measurement Operation by Free Running Counter with Both Edges Specified eee fin Dee count pel Tl2m pin input ir ad Value loaded UM uL 0 218072 Ws _ pin input PA edu LM INTOVE 0 2d 01 00 xt 10000H DO D2 xt D3 D2 xt 10000H D1 D2 1 xt Remark m 0to2 n 1 2 158 User s Manual U12670EE3VOUD00 Chapter 7 16 Bit Timer 2 7 5 16 Bit Timer 2 Precautions 1 Timer start errors An error with a maximum of one clock may occur until counting is started after timer start because the 16 bit timer register TM2 can be started asynchronously with the count pulse Figure 7 9 16 Bit Timer Register Start Timing TM2 count value 0000H Timer start 2 Capture register data retention timings If the valid edge of the TI2n pin is input during the 16 bit capture register Om CR2n is read CR2m performs capture operation but the capture value is not guaranteed However the interrupt request flag INTTM2n is set upon detection of the valid edge Figure 7 10 Capture Register Data Retention Timing opa E eas ES E TM2 count value 8 XN 2X N1 X N XNAX M 2X wn 1 20 Edge input Interrupt request flag
167. 70 P77 P120 P127 P130 P137 P140 P147 CRXD ANIO ANI7 X1 X2 CL1 4 5 V Vpp lt 5 5 V Remark The characteristics of the dual function pins are the same as those of the port pins unless otherwise specified User s Manual U12670EE3VOUDOO 451 Chapter 25 Electrical Specifications pPD780948 A Parameter Conditions 8 0 MHz crystal oscillation operating mode PCC 00H Note 2 8 0 MHz crystal oscillation operating mode PCC 00H Note 3 8 0 MHz crystal oscillation current RC oscillation operating mode 40 KHz RC oscillation HALT mode 40 KHz CL1 Vpp STOP mode Notes 1 Current through Vppo Vpp1 respectively through Vsso Vss1 Excluded is the current through the inside pull up resistors through AVpp AVnggg the port current 2 CPU is operable The other peripherals like CAN controller Timer 0 Timer 2 serial interfaces A D converter etc are stopped 3 CPU and all peripherals except for the A D converter are in operating mode and PCL out put is fy 4 CPU is in HALT mode and all other peripherals except Watch timer are stopped Remarks 1 fx Main system clock oscillation frequency 2 fxr Subsystem clock oscillation frequency 3 The typical values are with respect to T4 25 C pPD780948 A LCD C D Static Method Parameter Conditions LCD drive voltage LCD split resist
168. 8 22 22 ERR RIPE 415 23 4 Memory Size Switching Register 5 416 23 2 Internal Expansion RAM Size Switching Register 417 23 3 Flash memory 418 23 3 1 Selection of transmission 418 23 3 2 Initialization of the programming 419 23 3 3 Flash memory programming 419 23 3 4 Flash programmer connection 420 23 3 5 Flash programming 422 Chapter 24 Instruction Set 2 2522 IRE REIR IRI REED ERE 423 24 4 Legends Used in Operation 423 24 1 1 Operand identifiers and description 423 24 1 2 Description of operation 424 24 2 Operation LL ERN ee ee eee 425 24 3 Instructions Listed by Addressing 433 Chapter 25 Electrical Specifications 437 25 1 Absolute Maximum Ratings 437 25 2 ee wir Ur Pr Tes TE 440 25 3 Main System Clock Oscillation Circuit Characteristics
169. A HL A A HL 4 B A HL C PO PO POT CY PO PO PO CY NINI NI PO CF NI PY PO PY P NIN CL N A A HL C XIXI XI XIX X X When the internal high speed RAM area is accessed or instruction with no data access When an area except the internal high speed RAM area is accessed Except r A Only when rp BC DE or HL 1 One instruction clock cycle is one cycle of the CPU clock fcpu selected by the PCC register 2 This clock cycle applies to internal ROM program 3 nis the number of waits when external memory expansion area is read from 4 mis the number of waits when external memory expansion area is written to User s Manual U12670EE3VOUDOO 427 Instruction Mnemonic Group Operands A byte Chapter 24 Instruction Set Table 24 2 Operation List 4 8 Operation A v byte N saddr byte saddr lt saddr v byte Note 3 A c Avr r lt saddr lt v saddr A laddr 6 A lt v addr16 A HL A HL byte A v HL byte A HL B lt A v HL A A v HL A HL C A A v HL C A byte lt byte saddr byte saddr saddr v byte Ar Note 3 lt lt
170. A D Converter Figure 12 2 Power Fail Detection Function Block Diagram PFCM ANIO P10 ANI1 P11 8 ANI2 P12 9 8 INTAD ANI3 P13 A D converter d ANI4 P14 5 ANI5 P15 ANI6 P16 ANI7 P17 Power fail compare threshold value register PFT Power fail compare mode register PFM Internal bus 12 2 A D Converter Configuration A D converter consists of the following hardware Table 12 1 A D Converter Configuration Item Configuration Analog input 8 channels ANIO to ANI Successive approximation register SAR Registers A D conversion result register ADCR1 A D converter mode register ADM1 Analog input channel specification register ADS1 Control registers Power fail compare mode register PFM Power fail compare threshold value register PFT 1 Successive approximation register SAR This register compares the analog input voltage value to the voltage tap compare voltage value applied from the series resistor string and holds the result from the most significant bit MSB When up to the least significant bit LSB is set end of A D conversion the SAR contents are transferred to the A D conversion result register 204 User s Manual U12670EE3VOUDOO 2 Chapter 12 A D Converter A D conversion result register ADCR1 This register holds the A D conversion result Each time when t
171. AN Reference voltage AVpp AVngr ADCS bit 1 AVpp AV ger current IREF ADCS bit 0 Note Overall error excluding quantization 1 2 LSB It is indicated as a ratio to the full scale value Remark Main system clock oscillation frequency 2 pPD780948 A1 TA 40 C to 110 C Vpp z 4 0 to 5 5 V AVss Vss OV fy 8 MHz Parameter Test Conditions Resolution Overall error Note Conversion time tconv Analog input voltage VIAN Reference voltage AVpp AVngr ADCS bit 1 AVpp AVggr current IREF ADCS bit 0 Note Overall error excluding quantization 1 2 LSB It is indicated as a ratio to the full scale value Remark Main system clock oscillation frequency User s Manual U12670EE3VOUDOO 479 Chapter 25 Electrical Specifications 3 pPD78F0948 40 C to 85 C Vpp 4 0 to 5 5 V AVss Vss OV fy 8 MHz Parameter Test Conditions Resolution Overall error Note Conversion time tconv Analog input voltage VIAN Reference voltage AVpp AVrer ADCS bit 1 ADCS bit 0 AVpp AVper current IREF Note Overall error excluding quantization 1 2 LSB It is indicated as a ratio to the full scale value Remark Main system clock oscillation frequency 480 User s Manual U12670EE3VOUDOO Chapter 25 Electrical Specifications 25 6 5
172. CL50 TCL51 Control register 8 bit timer mode control registers 50 and 51 TMC50 51 Port mode register 0 Figure 8 1 8 Bit Timer Event Counter 50 Block Diagram Internal Bus 8 Bit Compare Register CR50 Match 50 fx 23 za fx 25 2 Output fx 27 9 8 Bit Timer OVF Control fx 29 9 Register 50 TI50 P06 TO50 Clear Selector TCL TCL TCL 502 501 500 Timer Clock Select Register 50 TCE TMC LVS LVR TMC TOE 50 506 50 50 501 50 8 Bit Timer Mode Control Register 50 Internal Bus Note Refer to Figure 8 3 for details of configurations of 8 bit timer event counters 50 and 51 output control circuits User s Manual U12670EE3VOUDO00 163 Chapter 8 8 Bit Timer Event Counters 50 and 51 Figure 8 2 8 Bit Timer Event Counter 51 Block Diagram Internal Bus 8 Bit Compare Register CR51 fx fx 2 fx 23 fx 25 fx 27 fx 21 Selector TI51 P07 TO51 TCL TCL TCL 512 511 510 Timer Clock Select Register 51 X Match 2 8 Bit Timer Register n TM51 4 Clear Selector Output Control 51 Note TO51 P07 TI51 8 Bit Timer Mode Control Register 51 Internal Bus TMC LVS LVR TMC TOE 51 516 51 51 511 51 N
173. CSIE31 6 5 4 3 2 1 CSIM31 CSIE31 0 MODE SCL311 SCL310 RW FFAAH Enable disable specification for SIO31 After 0 R W Address Shift register operation Operation stop Serial counter Clear Port function Port Note Operation enable Count operation enable Serial operation port function Transfer operation modes and flags Operation mode Transfer start trigger Transmit transmit and receive mode Write to 51031 P23 SO1 SI1 501 51 SCL310 Receive only mode Read from 51031 Clock selection External clock input 511 8 bit timer 50 50 output 5 26 5 2 Reset 00H Note When CSIE31 0 51031 operation stop status the pin connected to SI1 SO1 can be used for port functions User s Manual U12670EE3VOUDOO 229 Chapter 14 Serial Interface Channel 31 2 Communication Operations In the two wire serial I O mode the data is transmitted and received in 8 bit units Each bit of data is sent or received synchronized with the serial clock The serial I O shift register 31 S1031 is shifted synchronized with the falling edge of the serial clock Transmission data is held in the SO31 latch and is output from the SO31 pin The data that is received via the SI31 pin synchronized with the rising edge of the serial clock is latched to SIO31 The completion of an 8 bit transfer automatically stops operation of SIO31 and sets a serial tra
174. Converter Characteristics Chapter 25 Electrical Specifications Addition of Chapter 26 Package Drawing Chapter 26 Package Drawing Addition of Chapter 27 Recommended Soldering Conditions Chapter 27 Recommended Soldering Conditions User s Manual U12670EE3VOUD00 503 Appendix D Revision History 2 2 Edition No Major items revised Revised Sections 504 User s Manual U12670EE3VOUDOO NEC Message From Name Company Tel FAX Although NEC has taken all possible steps to ensure thatthe documentation supplied to our customers is complete bug free and up to date we readily accept that errors may occur Despite all the care and precautions we ve taken you may encounter problems in the documentation Please complete this form whenever you d like to report errors or suggest improvements to us Address North America Hong Kong Philippines Oceania NEC Electronics Inc NEC Electronics Hong Kong Ltd Corporate Communications Dept Fax 852 2886 9022 9044 Fax 1 800 729 9288 1 408 588 6130 Korea Europe NEC Electronics Europe GmbH bn aos Hong Kong Ltd Market Communication Dept apes 4411 49 211 6503 274 PE SADED South America Taiwan NEC do Brasil S A NEC Electronics Taiwan Ltd Fax 55 11 6465 6829 Fax 02 2719 5951 Thank you for your kind support
175. D controller driver stop mode supply of LCD clock is stopped LCD controller driver operating mode supply of LCD clock is enabled Cautions 1 LCDTM is a special register that must be set when debugging is performed with an in circuit emulator Even if this register is used the operation of the 0780948 Subseries is not affected However delete the instruction that manip ulates this register from the program at the final stage of debugging 2 Bits 7 to 2 and bit 0 must be set to 0 User s Manual U12670EE3VOUDOO 357 MEMO 358 User s Manual U12670EESVOUDOO Chapter 18 Sound Generator 18 1 Sound Generator Function The sound generator has the function to operate an external speaker The following two signals are supplied by the sound generator 1 Basic cycle output signal with without amplitude A buzzer signal with a variable frequency in a range of 0 5 to 3 8 KHz at fy 8 38 MHz can be output The amplitude of the basic cycle output signal can be varied by ANDing the basic cycle output signal with the 7 bit resolution PWM signal to achieve control of the volume 2 Amplitude output signal A PWM signal with a 7 bit resolution for variable amplitude can be generated independently Figure 18 1 shows the sound generator block diagram and Figure 18 2 shows the concept of each sig nal Figure 18 1 Sound Generator Block Diagram Internal bus Sound generator control register SGCR SGOBSGCL2S
176. D00 Chapter 17 LCD Controller Driver Figure 17 2 LCD Clock Select Circuit Block Diagram Prescaler fx 2 ficp 2 f co 2 LCDCL Selector ficp 2 Al ficp wie cone coms LCDM4 LCD display mode register Internal bus Remarks 1 LCDCL LCD clock 2 ficp LCD clock frequency User s Manual U12670EE3VOUDOO 333 Chapter 17 LCD Controller Driver 17 3 LCD Controller Driver Control Registers The LCD controller driver is controlled by the following two registers LCD display mode register LCDM LCD display control register 1 LCD display mode register LCDM This register sets display operation enabling disabling the LCD clock frame frequency LCDM is set with an 1 bit or 8 bit memory manipulation instruction RESET input clears LCDM to 00H Figure 17 3 LCD Display Mode Register LCDM Format Symbol 7 6 5 4 3 2 1 0 Address After Reset R W LCDM LCDON LCDM6 LCDM5 LCDM4 LCDM2 LCDM1 LCDMO FF90H 00H RW LCD Display Enable Disable 0 Display off all segment outputs are non select signal outputs 1 Display on LCDM6 LCDM5 LCDM4 LCD Clock Selection fy 8 00 MHz 0 0 0 fx 217 61 Hz 0 1 fy 2 6 122 Hz 1 0 fy 2 244 Hz 1 1 fy 2 4 488 Hz Other than above Setting prohibited Selects Display mode of LCD Controller Driver Time Division Bias Mode 0 Static Other than above Setting
177. Data Memory Stop Mode Low Supply Voltage Data Retention Characteristics 1 pPD780948 A 40 C to 85 C Parameter Test Conditions Data retention power supply voltage Data retention power supply current Vpppn 4 0 V Release signal set time Sing m e Release by RESET Oscillation stabilization wait time Release by interrupt Note combination with bits 0 to 2 OSTSO to OSTS2 of oscillation stabilization time select register selection 042124 and 2 fy to 2174 is possible Remark Main system clock oscillation frequency 2 pPD780948 A1 TA 40 C to 110 C Parameter Test Conditions Data retention power supply voltage Data retention power supply current Vpppn 4 0 V Release signal set time Release by RESET Oscillation stabilization wait time Release by interrupt Note combination with bits 0 to 2 OSTSO to OSTS2 of oscillation stabilization time select register selection 02124 and 2 4 fy to 2 fy is possible Remark fy Main system clock oscillation frequency User s Manual U12670EE3VOUDOO 481 Chapter 25 Electrical Specifications 3 pPD78F0948 TA 40 C to 85 C Parameter Test Conditions Data retention power supply voltage Data retention power supply current Vpppn 4 0 V Release signal set time Release by RESET Oscillation stabilization wait time
178. E3VOUDOO 165 Chapter 8 8 Bit Timer Event Counters 50 and 51 8 3 8 Bit Timer Event Counters 50 and 51 Control Registers The following three types of registers are used to control the 8 bit timer event counters 50 and 51 e Timer clock select register 50 and 51 TCL50 TCL51 8 bit timer mode control registers 50 and 51 TMC50 51 Port mode register 0 PMO 1 Timer clock select register 50 TCL50 This register sets count clocks of 8 bit timer register 50 0 is set with an 8 bit memory manipulation instruction RESET input sets TCL50 to OOH Figure 8 4 Timer Clock Select Register 50 Format 7 6 5 4 After 2 1 0 R W Address Reset TCL502 TCL501 TCL500 8 bit Timer Register 50 Count Clock Selection TI50 falling edge Note TI50 rising edge Note fy 8 0 MHz fx 2 4 0 MHz fx 23 1 0 MHz fy 2 250 KHz fx 2 62 5 KHz 1 29 15 6 KHz Other than above Setting prohibited Note When clock is input from the external timer output PWM output cannot be used Cautions 1 When rewriting TCL50 to other data stop the timer operation beforehand 2 Set always bits 3 to 7 to 0 Remarks 1 fy Main system clock oscillation frequency 2 1150 8 bit timer register 50 input pin 3 Values in parentheses apply to operation with fy 8 0 MHz 166 User s Manual U12670EE3VOUD00 Chapter 8 8 Bit Timer Event Counters 50 and 51 2 Timer
179. EE3VOUDOO 115 Chapter 5 Clock Generator 5 5 1 Main system clock operations When operated with the main system clock with bit 5 CLS of the processor clock control register PCC set to 0 the following operations are carried out by PCC setting a Because the operation guarantee instruction execution speed depends on the power supply voltage the instruction execution time can be changed by bits 0 to 2 PCCO to PCC2 of the PCC b If bit 7 MCC of the PCC is set to 1 when operated with the main system clock the main sys tem clock oscillation does not stop When bit 4 CSS of the PCC is set to 1 and the operation is switched to subsystem clock operation CLS 1 after that the main system clock oscilla tion stops see Figure 5 6 Figure 5 6 Main System Clock Stop Function a Operation when MCC is set after setting CSS with main system clock operation MCC CSS y CLS 7 Y Main System Clock Oscillation Subsystem Clock Oscillation pa CPU Clock 5 5 2 Subsystem clock operations When operated with the subsystem clock with bit 5 CLS of the processor clock control register PCC set to 1 the following operations are carried out a The instruction execution time remains constant 122 us when operated at 32 768 KHz irre spective of bits 0 to 2 PCCO to PCC2 of the PCC b Watchdog timer counting stops Caution Do not execute the STOP instruction while the subsystem clock is in operation 116
180. EE3VOUDOO 305 Chapter 16 CAN Coniroller 16 14 Baudrate Generation 1 Bit Rate Prescaler Register This register sets the clock for the DCAN internal DCAN clock and the number of clocks per time quantum TQ BRPRS can be set with an 8 bit memory manipulation instruction RESET input sets BRPRS to 3FH Figure 16 43 Bit Rate Prescaler 1 2 Symbol 7 6 5 4 3 2 1 0 Address After Reset R W R W R W R W R W R W R W R W The PRMn 0 1 bits define the clock source for the operation The PRM selector defines the input clock to the DCAN Macro and influences therefore all DCAN activities Writing to the BRPRS register is only allowed during initialization mode Any write to this register when INIT bit is set in CANC register and the initialization mode is not confirmed by the INITSTATE bit of CANES register can cause unexpected behaviour to the CAN bus Input Clock Selector for DCAN Clock fy is input for DCAN fx 2 is input for DCAN fx 4 is input for DCAN CCLK is input for DCAN The BRPRSn bits n 0 to 5 define the number of clocks applied for one TQ 306 User s Manual U12670EE3VOUD00 Chapter 16 CAN Controller Figure 16 43 Bit Rate Prescaler 2 2 Setting of BRPRSn 5 to 0 BRPRS5 BRPRS4 BRPRS3 BRPRS2 BRPRS1 BRPRSO Bit Rate PrescalerNote 2 x BRPRSn 5 0 2 118 120 122 124 126 Note
181. Figure 3 5 Figure 3 6 Figure 3 7 Figure 3 8 Figure 3 9 Figure 3 10 Figure 3 11 Figure 3 12 Figure 3 13 Figure 3 14 Figure 3 15 Figure 3 16 Figure 3 17 Figure 3 18 Figure 3 19 Figure 3 20 Figure 3 21 Figure 3 22 Figure 4 1 Figure 4 2 Figure 4 3 Figure 4 4 Figure 4 5 Figure 4 6 Figure 4 7 Figure 4 8 Figure 4 9 Figure 4 10 Figure 4 11 Figure 4 12 Figure 4 13 Figure 4 14 Figure 4 15 Figure 4 16 Figure 5 1 Figure 5 2 Figure 5 3 Figure 5 4 Figure 5 5 Figure 5 6 Figure 5 7 Figure 6 1 Figure 6 2 Figure 6 3 Figure 6 4 Figure 6 5 List of Figures Pin COMPQUPAN OM e 29 ABK O Series EXpanslOn oue vetet ri sen ae eee 31 Block DIagtam a terne e UR Ante tet 33 Connection Of IG PINS EE EE 47 Pin Input Output Circuits 1 3 oo cece cece eeeeeeeeeeeeeeeeee 51 Memory of the 0780948 nennen nennen 55 Memory of the PD78F0948 2 56 Data Memory Addressing 0780948 60 Data Memory Addressing 78 0948 61 Program Counter Configuration essssssssssssseeeee eene nnn 62 Program Status Word Configuration eesssssseeeeeeeene nnne 62 Stack Pointer 64 Data to be Saved to Stack 0 21000000 enne 64 Data to be Reset to Stack
182. GCLISGCLO Selector Prescaler Selector 5 bit counter Clear SGO SGOF P34 Selector PWM amplitude PCL SGOA P33 Clock output control circuit PCL 4 ISGBR3SGBR2 SGBR1SGBRO Sound generator buzzer control register SGBR Port mode register 3 PM3 generator amplitude SGAM Internal bus User s Manual U12670EE3VOUDOO 359 Chapter 18 Sound Generator Figure 18 2 Concept of Each Signal Basic cycle output SGOF without amplitude Amplitude output SGOA Basic cycle output SGO with amplitude 18 2 Sound Generator Configuration The sound generator consists of the following hardware Table 18 1 Sound Generator Configuration Item Configuration Counter 8 bits x 1 5 bits x 1 SGO SGOF with without append bit of basic cycle output SGOA amplitude output SG output Sound generator control register SGCR Control register Sound generator buzzer control register SGBR Sound generator amplitude register SGAM 18 3 Sound Generator Control Registers The following three types of registers are used to control the sound generator Sound generator control register SGCR Sound generator buzzer control register SGBR Sound generator amplitude control register SGAM 360 User s Manual U12670EE3VOUD00 Chapter 18 Sound Gener
183. High Impedance Port Pin SSS SSeS Se a es Se Figure 22 4 Timing of Reset Input in STOP Mode by RESET Input x1 STOP Instruction Execution l Oscillation i Stop Status Reset Period Normal Operation Normal Operation e Oscillation Stop Oscillation Stop wr Reset Processing ime Wait RESET Internal Reset Signal l Delay Delay High Impedance Port Pin a en ete ee 412 User s Manual U12670EE3VOUDOO Program counter PC Nete 1 Chapter 22 Reset Function Table 22 1 Hardware Status after Reset 1 2 Hardware Status after Reset The contents of reset vector tables 0000H and 0001H are set Stack pointer SP Undefined Program status word PSW 02H RAM Data memory UndefinedNote 2 General register UndefinedNote 2 Port Output latch Ports 0 to 7 Port 12 13 14 PO to P7 P12 P13 P14 Port mode register PMO to PM7 PM12 PM13 PM14 Pull up resistor option register PUO PU4 PU7 PU13 Port function selection PF2 PF5 PF12 PF14 Processor clock control register PCC Memory size switching register IMS Internal expansion RAM size switching register IXS Oscillation stabilization time select register OSTS 16 bit timer event counter 0 Timer register TMO Capture
184. INTP1 Input P02 Port 0 INTP2 Input 0 8 bit input output port 2 0 Input Output Input output mode can be specified bit wise 04 If used an input port a pull up resistor can be connected by NTP4 T101 Input 5 software bit wise 00 00 Input P06 0 050 Input P07 TI51 TO51 Input Port 1 Input P10 P17 8 input output port ANIO ANI7 Input Input output mode can be specified bit wise P20 SIO Input P21 500 Input Port 2 Dee 7 bit output only port SCKO Input 23 Input output mode can be specified bit wise 511 801 Input Output If used as an output port the port buffer can be set a CMOS aaa P24 SCK1 Input or N ch open drain buffer P25 RXD Input P26 TXD Input P30 20 Input P31 Port 3 TI21 Input p P32 5 bit input output port 22 Input Output Input output mode can be specified bit wise P33 Poe PCL SGOA Input P34 SGO SGOF Input Port 5 8 bit input output port Input Input output mode can be specified bit wise aa ut P50 P57 This port can be used in External Memory Expansion mode A8 S39 A15 S32 with the 4 6 or 8 bit address by setting the Memory sion mode register not for external memory used ports can be used either for LCD or port function oh P64 Port 6 pee Input 65 3 bit input output port WR Input Output Input output mode can be specified bit wise P67 p p ASTB Input Port 7 8 bit input output port Input Input output
185. Multiplication division 8 bits x 8 bits 16 bits 8 bits Bit manipulation set reset test boolean operation BCD adjustment etc Total 79 I O ports CMOS input 8 CMOS I O 71 A D converter 8 bit resolution x 8 channels Instruction set 3 wire mode 1 channel Serial Interface 2 wire mode 1 channel UART mode 1 channel 16 bit timer event counter 2 channels 8 bit timer event counter 2 channels Watch timer 1 channel Watchdog timer 1 channel Timer output 3 16 bit PWM output x 1 8 bit PWM output x 2 62 5 KHz 125 KHz 250 KHz 500 KHz 1 MHz 2 MHz 4 MHz 8 MHz at main system clock of 8 0 MHz Sound Generator 1 channel Timer Clock output LCD controller Driver max 40 seg x 4 CAN 1 channel Internal 22 External 5 Maskable interrupts Vectored interrupts Non maskable interrupts Internal 1 Software interrupts Internal 1 Supply voltage Vpp 4 0 V to 5 5 V Package 100 pin plastic QFP 14 mm x 20 mm 34 User s Manual U12670EE3VOUDOO Chapter 1 Outline uPD780948 Subseries 1 9 Mask Option The mask ROM version provides LCD split resistor which allows user to specify whether to connect LCD split resistor externally The mask options provided in the uPD780948 Subseries are shown in Table 1 3 Table 1 3 Differences between Flash and Mask ROM version LCD split resistor can be specified internally 1 10 Differences between Flash and M
186. OF Toggles with each start of frame on the CAN Bus Toggles with each start of frame on the CAN bus Clears SOFE bit when DCAN starts to store a message in receive buffer 4 SOFC is located in the synchronization register SYNC1 RESET and setting of the INIT bit of CANC register clears the SOFOUT to 0 Table 16 24 Transmission Reception Flag Transmission Flag 0 No transmission 1 Transmission active on CAN bus Note Reception Flag 0 No data on the CAN bus 1 Reception active on the CAN bus The TXF and RXF bits of CANC register show the present status of the DCAN to the bus If both bits are cleared the bus is in idle state RXF and TXF bits are read only bits During initialization mode both bits do not reflect the bus status Note Transmission is active until intermission is completed 298 User s Manual U12670EE3VOUD00 Chapter 16 CAN Controller Figure 16 36 Time Stamp Function INT INT Object n Object n A 4 _Other valid or 4 Valid message invalid message Valid message de SOF SOF SOF A A B Enable SOF Edge for capture Edge for capture Figure 16 37 SOFOUT Toggle Function Any valid or Any valid or Any valid or A invalid message invalid message invalid message SOF SOF SOF A gt Edge for Edge for Edge for capture capture capture Enabl
187. OFF bit changes its value RECS Reception error counter status 0 Reception error counter 96 1 Reception error counter gt 96 Warning level for error passive reached RECS is updated after each reception An interrupt is generated when RECS changes its value Note Issuing TLRES bit may violate the minimum recovery time as defined in ISO 11898 300 User s Manual U12670EE3VOUD00 Chapter 16 CAN Controller Figure 16 39 CAN Error Status Register 2 3 TECS Transmission error counter status Transmission error counter lt 96 Transmission error counter gt 96 Warning level for error passive reached TECS is updated after each reception An interrupt is generated when TECS changes its value INITSTATE Operational status of the DCAN 0 CAN is in normal operation 1 CAN is stopped and ready to accept new configuration data INITSTATE changes with a delay to the INIT bit in CANC register The delay depends on the current bus activity and the time to set all internal activities to inactive state This time can be several bit times long While BOFF bit is set a request to go into the initialization mode by setting the INIT bit is ignored In this case the INITSTATE bit will not be set until the Bus off state is left VALID Valid protocol activity detected 0 No valid message detected by the CAN protocol 1 Error free message reception from CAN bus This bit shows valid protocol activities independe
188. Operation byte N saddr byte saddr CY lt saddr byte Ar Note 3 A CY lt A r lt saddr A CY lt saddr A 16 A CY lt addr16 A HL A CY A A HL byte A CY lt HL byte A HL B HL A CY lt HL A HL C A CY A HL C A byte A CY amp A byte CY saddr byte saddr CY lt saddr byte CY Ar Note 3 A CY A r CY CY r A CY A saddr A CY lt saddr A laddri6 A CY A A HL A CY lt HL A HL byte A HL A CY lt HL B CY A HL C A CY lt HL S CY A CY lt HL C CY XX XIXI X x x X XIXI X X X XIX x xd X XIX XIX XIXI X XIX X XIXI X X X XIX x x A byte A amp A byte saddr byte saddr saddr byte Ar Note 3 lt saddr A laddr16 lt A saddr A lt A addr16 A HL A HL byte A lt A HL byte A HL B A Co A A CO A CO A MD A CO CO A Co A lt
189. Part Number Reset Value uPD780948 uPD78F0948 User s Manual U12670EE3VOUDOO 395 Chapter 20 External Device Expansion 20 3 External Device Expansion Function Timing Timing control signal output pins in the external memory expansion mode are as follows 1 2 3 4 RD pin Alternate function P64 Read strobe signal output pin The read strobe signal is output in data accesses and instruction fetches from external memory During internal memory access the read strobe signal is not output maintains high level WR pin Alternate function P65 Write strobe signal output pin The write strobe signal is output in data access to external memory During internal memory access the write strobe signal is not output maintains high level ASTB pin Alternate function P67 Address strobe signal output pin Timing signal is output without regard to the data accesses and instruction fetches from external memory The ASTB signal is also output when the internal mem ory is accessed ADO to AD7 A8 to A15 pins Alternate function P40 to P47 P50 to P57 Address data signal output pin Valid signal is output or input during data accesses and instruction fetches from external memory These signals change when the internal memory is accessed output values are undefined Timing charts are shown in Figures 20 5 to 20 8 396 User s Manual U12670EE3VOUD00 Chapter 20 External Device Expansion Figure 20 5 Inst
190. ROM 61440 x 8 bits 0000H Note In the expansion RAM between F400H and F7DFH it is not possible to do code execution 60 User s Manual U12670EE3VOUDOO FFFFH FF20H FF1FH FFOOH FEFFH FEEOH FEDFH FE20H FBOOH FAFFH FA80H FA7FH FA58H FA57H F7EOH F7DFH F400H F3FFH FOOOH EFFFH 0000H Note Inthe expansion RAM between F400H and F7DFH it is not possible to do code execution Chapter 3 CPU Architecture Figure 3 4 Data Memory Addressing of uPD78F0948 Special Function Registers SFRs 256 x 8 bits SFR Addressing General Registers 32 x 8 bits Short Direct Register Addressing Addressing y Internal High speed RAM 1024 x 8 bits Not usable LCD Display RAM 40 x 4 bits Not usable Internal Expansion RAM 992 x 8 bits External Memory Internal Flash EEPROM 61440 x 8 bits Direct Addressing Register Indirect Addressing Based Addressing Based Indexed Addressing User s Manual U12670EE3VOUDOO 61 Chapter 3 CPU Architecture 3 2 Processor Registers The PD780948 Subseries units incorporate the following processor registers 3 2 1 Control registers The control registers control the program sequence statuses and stack memory The control registers consist of a program counter a program status word and a stack pointer 1 2 62 Program counter PC The program counter is a 16 bit register which ho
191. Reset RAW Interrupt Servicing Control 0 Interrupt servicing enabled 1 Interrupt servicing disabled Cautions 1 If TMMKA flag is read when the watchdog timer is used as a non maskable interrupt MKO value becomes undefined 2 Set always 1 in MK1H bit 0 and bit 3 to bit 7 User s Manual U12670EE3VOUDOO 373 Chapter 19 Interrupt Functions 3 Priority specify flag registers PROL PROH PR1L PR1H The priority specify flag is used to set the corresponding maskable interrupt priority orders PROL PROH PR1L and PR1H are set with an 1 bit or an 8 bit memory manipulation instruction If PROL and PROH are used as a 16 bit register PRO use a 16 bit memory manipulation instruction for the setting RESET input sets these registers to FFH Figure 19 4 Priority Specify Flag Register Format Symbol lt 7 gt lt 6 gt lt 5 gt lt 4 gt lt 3 gt lt 2 gt lt gt lt 0 gt Address After Reset R W PROL PPR1 PPRO TMPR22 TMPR21 TMPR20 OVFPR ADPR TMPR4 FFE8H FFH R W PROH 1 CTPRO CEPR PPR4 PPR3 PPR2 FFE9H RW PRIL TMPR51 TMPR50 TMPRO1 TMPROO TMPR5S2 STPR SRPR CSIPR1 FFEAH FFH RW PRIH 1 1 1 1 1 wPRF wrIPPR 1 FFEBH FFH RW Priority Level Selection 0 High priority level 1 Low priority level Cautions 1 When watchdog timer is used as a non maskable interrupt set 1 TMPR4 flag 2 Set always 1 in PR1H b
192. TM51 clear to 0 1 Operation Enable Cautions 1 Timer operation must be stopped before setting TMC51 2 If LVS51 and LVR51 are read after data set they will be 0 3 Be sure to set bit 5 to 0 5 Port mode register 0 PMO This register sets port 0 input output in 1 bit units When using the P06 TI50 TO50 and P07 TI51 TO51 pins for timer output set PM06 07 and the output latches of PO6 and 07 to 0 is set with an 1 bit or an 8 bit memory manipulation instruction RESET input sets PMO to FFH Figure 8 8 Port Mode Register 0 Format 7 6 5 4 3 2 1 0 RW Address iter Reset RW FF20H Input Output mode Selection 0 to 7 Output mode output buffer ON Input mode output buffer OFF 170 User s Manual U12670EE3VOUDOO Chapter 8 8 Bit Timer Event Counters 50 and 51 8 4 8 Bit Timer Event Counters 50 and 51 Operations 8 4 1 Interval timer operations 8 bit timer event counter mode Setting the 8 bit timer mode control registers TMC50 and TMC51 as shown in Figure 8 9 allows oper ation as an interval timer Interrupts are generated repeatedly using the count value preset in 8 bit com pare registers CR50 and CR51 as the interval When the count value of the 8 bit timer register 50 or 51 TM50 TM51 matches the value set to CR50 or CR51 counting continues with the TM50 or TM51 value cleared to 0 and the interrupt request signal INTTM50 INTTM51 is generated Count
193. TMO is loaded to the 16 bit capture compare reg ister 01 01 and an external interrupt request signal 01 is set When the edge specified by bits 6 and 7 ES10 and ES11 of the prescaler mode register 0 PRMO is input to the TIO1 pin the value of TMO is loaded to the 16 bit capture compare register 00 CROO and an external interrupt request signal INTTMOO is set The edges of the TIOO and TIO1 pins are specified by bits 4 and 5 500 and 501 and bits 6 and 7 ES10 and ES11 of PRMO respectively The rising falling or both rising and falling edges can be specified The valid edge of TIOO pin and TIO1 pin is detected through sampling at a count clock cycle selected by the prescaler mode register 0 PRMO and the capture operation is not performed until the valid level is detected two times Therefore noise with a short pulse width can be rejected Figure 6 14 Control Register Settings for Measurement of Two Pulse Widths with Free Running Counter a 16 bit timer mode control register TMCO 02 01 OVFO o ___________________ Free running mode b Capture compare control register 0 CRCO CRC02 CRCO1 00 as capture register Captures valid edge of TIO1 P71 pin to CROO 01 as capture register Remark 0 1 When these bits are reset to 0 or set to 1 the other functions can be used along with the pulse width measurement funct
194. The bit rate prescaler value represents the DCAN clocks per TQ User s Manual U12670EE3VOUDOO 128 307 Chapter 16 CAN Coniroller 2 Synchronization Control Registers 0 and 1 These registers define the CAN bit timing They define the length of one data bit on the CAN bus the position of the sample point during the bit timing and the synchronization jump width The range of resynchronization can be adapted to different CAN bus speeds or network characteris tics Additionally some modes related to the baud rate can be selected in SYNC1 register SYNCO and SYNC1 can be read or written with an 8 bit memory manipulation instruction RESET input sets SYNCO to 18H RESET input sets SYNC1 to OEH Figure 16 44 Synchronization Control Registers 0 and 1 1 2 Symbol 7 3 2 1 0 Address After Reset R W SYNCO SPT2 SPT1 SPTO DBT4 DBT3 DBT2 DBT1 DBTO FFB9H 18H R W Symbol 7 3 2 1 0 Address After Reset R W SYNC1 OFC SAMP RXONLY SJW1 JWO SPT4 SPT3 FFBAH OEH R W oT BOS San RORY Swe ET SPY The length of a data bit time is programmable via DBT 4 0 DBT4 DBT3 DBT2 DBT1 DBTO DataBitTime Other than under Setting prohibited 1 8x TQ 9x TQ 10x TQ 11x TQ 12x TQ 13x TQ 14x TQ 15x TQ 16x TQ 17x TQ 18x TQ 19x TQ 20 x TQ 21x TQ 22x TQ 23 x TQ 24 x TQ 0 25 x TQ Other than above Setting prohibited
195. U12670EE3VOUDOO 79 Chapter 3 CPU Architecture 3 4 7 Based addressing 8 bit immediate data is added to the contents of the base register that is the HL register pair and the sum is used to address the memory The HL register pair to be accessed is in the register bank speci fied with the register bank select flags RBSO and RBS1 Addition is performed by expanding the offset data as a positive number to 16 bits A carry from the 16th bit is ignored This addressing can be carried out for all the memory spaces Operand format Table 3 10 Based addressing HL byte Figure 3 20 Based addressing description example MOV A HL 10H when setting byte to 10H Operation code 10101110 00010000 80 User s Manual U12670EE3VOUDOO Chapter 3 CPU Architecture 3 4 8 Based indexed addressing The B or C register contents specified in an instruction are added to the contents of the base register that is the HL register pair and the sum is used to address the memory The HL B and C registers to be accessed are registers in the register bank specified with the register bank select flag RBSO and RBS1 Addition is performed by expanding the contents of the B or C register as a positive number to 16 bits A carry from the 16th bit is ignored This addressing can be carried out for all the memory spaces Operand format Table 3 11 Based indexed addressing HL B HL C Figure 3 21 Based indexed addressing description ex
196. UN to 1 before the STOP mode is set clear the watchdog timer and then execute the STOP instruc tion Cautions 1 The actual overrun detection time may be shorter than the set time by a maximum of 0 596 2 When the subsystem clock is selected for CPU clock watchdog timer count oper ation is stopped Table 10 4 Watchdog Timer Overrun Detection Time Runaway Detection Time 1 212 512 us f 21 1 ms f 2 4 2 ms 215 4 ms 218 8 19 ms f 2 16 38 ms fx 218 32 76 ms 220 131 ms Remarks 1 fy Main system clock oscillation frequency 2 Figures in parentheses apply to operation with fy 8 0 MHz 196 User s Manual U12670EE3VOUD00 Chapter 10 Watchdog Timer 10 4 2 Interval timer operation The watchdog timer operates as an interval timer which generates interrupts repeatedly at an interval of the preset count value when bit 3 WDTMS of the watchdog timer mode register WDTM is set to 0 respectively When the watchdog timer operates as interval timer the interrupt mask flag TMMKA and priority specify flag TMPR4 are validated and the maskable interrupt request INTWDT can be generated Among maskable interrupts the INTWDT default has the highest priority The interval timer continues operating in the HALT mode but it stops in STOP mode Thus set bit 7 RUN of WDTM to 1 before the STOP mode is set clear the interval timer and then execute the STOP
197. User s Manual U12670EE3VOUDOO Chapter 5 Clock Generator 5 6 Changing System Clock and CPU Clock Settings 5 6 1 Time required for switchover between system clock and CPU clock The system clock and CPU clock can be switched over by means of bit 0 to bit 2 PCCO to PCC2 and bit 4 CSS of the processor clock control register PCC The actual switchover operation is not performed directly after writing to the PCC but operation contin ues on the pre switchover clock for several instructions see Table 5 2 Determination as to whether the system is operating on the main system clock or the subsystem clock is performed by bit 5 CLS of the PCC register Set Values after Switchover Table 5 2 Maximum Time Required for CPU Clock Switchover Set Values before Switchover CSS PCC2 PCC1 PCC2 PCC1 PCCO PCC2 PCC1PCCO PCC2 PCCO PCC2 PCCO PCC2 PCCO PCC2 PCC1 0 0 0 01011 instructi 01110 instructi 1 1 instructi 1 0 0 1 instruction X 16 instructi instructi instructi 1 instruction instructi instructi ons instructi 8 instructions instructions instructi 1 instruction 1 instruction instructi ons 8 instructions instructions instructions Caution fy 2fyz instruction 77 instruct ions 39
198. _ rL Vici Vice Vss1 1 Vico Vic1 Vice Vss S21 1 2Vicp 0 1 2Vicp COMO S21 Vicp Vicp 1 2 1 521 0 1 2Vicp Vicp 1 2Vicp COM2 S21 0 1 2Vicp Vicp 352 User s Manual U12670EE3VOUD00 Figure 17 19 3 Time Division LCD Drive Waveform Examples 1 3 Bias Method COMO 1 2 21 COMO S21 COM1 S21 2 521 Chapter 17 LCD Controller Driver fe cien Vico Vict Vice Vssi Vico Vici Vice Vss1 Vico Vict Vice Vss1 Vico Vict Vice Vss1 Vicp 1 3Vicp 0 1 3Vicp Vicb Vicp 1 3Vicp 0 1 3Vicp Vicp User s Manual U12670EE3VOUD00 Vicp 1 3Vicp 0 1 3Vicp Vicp 353 Chapter 17 LCD Controller Driver 17 8 4 4 time division display example Figure 17 21 shows the connection of a 4 time division type 20 digit LCD panel with the display pattern shown in Figure 17 20 with segment signals SO to 539 and common signals COMO to The display example is 123456 78901234567890 and the display data memory contents correspond to this An explanation is given here taking the example of the 15th digit 6
199. a bytes 3 data bytes 4 data bytes 5 data bytes 6 data bytes 7 data bytes 0 8 data bytes Others than above 0 0 0 0 0 0 0 0 1 DSTAT is written by the DCAN two times during message storage At the first access to this buffer DN 1 MUC 1 reserved bits and DLC are written At the last access to this buffer DN 1 MUC 0 reserved bits and DLC are written Note Valid entries for the data length code are 0 to 8 If a value higher than 8 is received 8 bytes are stored in the message buffer frame together with the data length code received in the DLC of the message User s Manual U12670EE3VOUDOO 289 3 Receive Identifier Definition Chapter 16 CAN Coniroller These memory locations define the receive identifier of the arbitration field of the CAN protocol IDRECO to IDREC4 can be set with a 1 bit or an 8 bit memory manipulation instruction RESET input sets IDRECO to IDREC4 to an undefined value Symbol IDRECO IDREC1 IDREC2 IDREC3 IDREC4 7 ID28 ID20 ID17 ID9 ID1 6 ID ID ID27 ID19 ID16 5 ID26 ID18 ID15 ID 4 ID25 ID14 ID 3 ID24 ID13 ID 2 ID23 ID12 ID Figure 16 29 Receive Identifier 1 ID22 ID11 ID 4 N 2 xxx3H 5 6 undefined
200. a format As shown in Figure 15 10 the format of the transmit receive data consists of a start bit character bits a parity bit and one or more stop bits The asynchronous serial interface mode register ASIMO is used to set the character bit length parity selection and stop bit length within each data frame Figure 15 10 Format of Transmit Receive Data in Asynchronous Serial Interface 1 data frame Start bit 1 bit Character bits 7 bits or 8 bits Parity bit Even parity odd parity zero parity or no parity Stop bit s 1 bit or 2 bits When 7 bits is selected as the number of character bits only the low order 7 bits bits 0 to 6 are valid In this case during a transmission the highest bit bit 7 is ignored and during reception the highest bit bit 7 must be set to 0 The asynchronous serial interface mode register ASIMO and the baud rate generator control register BRGCO are used to set the serial transfer rate If a receive error occurs information about the receive error can be recognized by reading the asynchronous serial interface status register ASISO User s Manual U12670EE3VOUDOO 249 Chapter 15 Serial Interface UART b Parity types and operations The parity bit is used to detect bit errors in transfer data Usually the same type of parity bit is used by the transmitting and receiving sides When odd parity or even parity is set er
201. a frame The length of the interframe space depends on the error state active or passive of the node a Error active Consists of 3 bits intermission and bus idle Figure 16 12 Interframe Space Error Active Any frame E m Interframe space B s frame R D Intermission Bus idle 3 bits 0 to bits b Error passive Consists of 3 bits intermission suspend transmission and bus idle Figure 16 13 Interframe Space Error Passive Each frame di Interframe space i Each frame R D Intermission Suspend Bus idle 3 bits transmission 0 to oo bits 8 bits Remark The nominal value of the intermission field is 3 bits However transmission nodes may start immediately a transmission already in the 3 bit of this field when a dominant level is detected Table 16 6 Operation in the Error State Error active Any node in this state is able to start a transmission whenever the bus is idle Any node in this state has to wait for 11 consecutive recessive bits before initiating a transmission Error passive User s Manual U12670EE3VOUDOO 263 Chapter 16 CAN Coniroller 16 1 5 Error Frame The type of an Error Frame is defined by its error flag This frame is sent from a node if an error is detected ACTIVE ERROR FLAG or PASSIVE ERROR FLAG Which kind of flag a node transmits after detecting an error condition depends on the internal count of the error counters of each node Figure 16 14 Error Frame
202. agreement of CRC Reception node Start of frame to data field Field frame check of the fixed format Detection of the fixed for mat error Reception node CRC delimiter ACK field End of frame Error frame Overload frame Check of the ACK slot by ACK error the transmission node Detection of recessive level in ACK slot 2 Output timing of the error frame Transmission node ACK slot Table 16 12 Output Timing of the Error Frame Bit error stuff error form error ACK error Error frame is started at the next bit timing following the detected error Error passive 3 Measures when error occurs CRC error frame is started at the next bit timing following the ACK delimiter Transmission node re transmits the data frame or the remote frame after the error frame The new CAN standard ISO 11898 allows a programmable suppression of this re transmission It is called single shot mode 268 User s Manual U12670EE3VOUD00 4 Error state Chapter 16 CAN Controller a Types of error state Error a Three types of error state These are error active error passive and bus off The transmission error counter TEC and the reception error counter REC control the error state The error counters are incremented on each error occurrence refer to Table 16 13 If the value of error counter exceeds 96 warning level for error passive state is reached When only o
203. ample In the case of MOV A HL B Operation code 10101041 1 User s Manual U12670EE3VOUDOO 81 Chapter 3 CPU Architecture 3 4 9 Stack addressing The stack area is indirectly addressed with the stack pointer SP contents This addressing method is automatically employed when the PUSH POP subroutine call and RETURN instructions are executed or the register is saved reset upon generation of an interrupt request Stack addressing enables to address the internal high speed RAM area only Figure 3 22 Stack addressing description example In the case of PUSH DE Operation code 10110101 82 User s Manual U12670EE3VOUDOO 4 1 Port Functions The uPD780948 Subseries units incorporate five input ports and eighty six input output ports Chapter 4 Port Functions Figure 4 1 shows the port configuration Every port is capable of 1 bit and 8 bit manipulations and can carry out considerably varied control operations Besides port functions the ports can also serve as on chip hardware input output pins Port6 Port7 Port12 Port13 Port14 Figure 4 1 Port Types User s Manual U12670EE3VOUDOO PortO Port1 Port2 Port3 Port4 Port5 83 Chapter 4 Port Functions Table 4 1 Pin Input Output Types 1 2 Pin Name Function Alternate Function POO INTPO Input
204. ansmission Abort Flag Write normal operation Read no abort pending Write aborts current transmission request for this buffer n Read abort is pending Transmission Complete Flag 0 Transmit was aborted no data sent 1 Transmit was complete abort had no effect The TXAn bits n 0 1 allow to free a transmit buffer with a pending transmit request Setting the TXAn bit n 0 1 by the CPU requests the DCAN to empty its buffer by clearing the respective TXRQn bit n 0 1 312 User s Manual U12670EE3VOUDOO Chapter 16 CAN Controller Figure 16 45 Transmit Control Register 2 2 The TXAn bits n 0 1 have a dual function 1 The CPU can request an abort by writing a 1 into the bit 2 The DCAN signals whether such an request is still pending The bit is cleared at the same time when the TXRQn bit n 0 1 is cleared The abort process does not affect any rules of the CAN protocol A frame already started will continue to its end An abort operation can cause different results dependent on the time it is issued d When an abort request is recognized by the DCAN before the start of the arbitration for transmit the TXCn bit n 0 1 is reset showing that the buffer was not send to other nodes e When the abort request is recognized during the arbitration and the arbitration is lost afterwards the TXCn bit n 0 1 is reset showing that the buffer was not send to other nodes f Wh
205. applies to internal ROM program nis the number of waits when external memory expansion area is read from mis the number of waits when external memory expansion area is written to 428 User s Manual U12670EE3VOUD00 Chapter 24 Instruction Set Table 24 2 Operation List 5 8 Instruction Group Increment decrement Mnemonic INC Operands r Operation rer i1 saddr saddr saddr 1 DEC r rer 1 saddr saddr 1 INCW rp rp rp 1 DECW rp rp lt rp 1 ROR A 1 CY Ao Am 1 lt Am x 1 time ROL RORC A 1 A 1 a po pl a CY Ag lt Az Am 1 lt Am x 1 time 0 7 m CY lt Ag A7 CY 1 lt Am x 1 time ROLC A 1 CY lt Az Ag lt CY Am 1 lt Am x 1 time ROR4 12 _ lt _ 9 HL 7_ 4 lt o lt HL _4 ROL4 0 lt HL 7 _ HL 3 o lt A3 o HL 4 HL 3_9 BCD adjust ADJBA Decimal Adjust Accumulator after Addition ADJBS Decimal Adjust Accumulator after Sub tract Bit manipulate CY saddr bit CY lt saddr bit CY sfr bit CY A bit CY lt sfr bit CY lt Abit CY PSW bit CY lt PSW bit CY HL bit saddr bit CY CY lt HL bit saddr bit CY sfr bit CY sfr bit CY A b
206. are 0 0 and 0 Cautions 1 When rewriting SGBR to other data stop the timer operation TCE 0 beforehand 2 Bits 4 to 7 must be set to 0 3 Sound generator amplitude register SGAM SGAM is a register that sets the amplitude of the sound generator output signal SGAM is set with an 1 bit or an 8 bit memory manipulation instruction RESET input clears SGAM to 00H Figure 18 5 shows the SGAM format User s Manual U12670EE3VOUDOO 363 Chapter 18 Sound Generator Figure 18 5 Sound Generator Amplitude Register SGAM Format Symbol 7 6 5 4 3 2 1 0 Address After Reset R W Amplitude 0 128 2 128 3 128 4 128 5 128 6 128 7 128 8 128 9 128 10 128 11 128 12 128 13 128 14 128 15 128 16 128 17 128 18 128 19 128 20 128 21 128 22 128 23 128 24 128 25 128 26 128 27 128 28 128 29 128 30 128 31 128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 O O O O O O O O O O O O O O O O O O O O O O GO 0 O oj O O O O O O O O O O O O O O O O O O O O O O O O O ojojo ol o o o ol Of ol ol ol ol ol ol Of ol o o o o of ol ol ol ol ol ol ol ol ol ol O OF AY OF AY OF
207. are not used by the definition in the DLC bits in the TCON byte are free for use by the CPU for application needs 284 User s Manual U12670EE3VOUDOO Chapter 16 CAN Controller 16 10 Receive Buffer Structure The DCAN has up to 16 receive buffers The number of used buffers is defined by the MCNT register Unused receive buffers can be used as application RAM for the CPU The received data is stored directly in this RAM area The 16 buffers have a 16 byte data structure for standard and extended frames with a capacity of up to 8 data bytes per message The structure of the receive buffer is similar to the structure of the transmit buffers The semaphore bits DN and MUC enable a secure reception detection and data handling For the first 8 receive message buffers the successful reception is mirrored by the DN flags in the RMES register The receive interrupt request can be enabled or disabled for each used buffer separately User s Manual U12670EE3VOUDOO 285 Chapter 16 CAN Coniroller 16 11 Receive Message Format Table 16 21 Receive Message Format Name AddressNote Bit7 Bite Bit5 it 0 IDCON IDE DSTAT RO IDRECO ID standard part IDREC1 ID standard part 0 0 0 RTRpec Note 2 IDREC2 ID extended part IDREC3 ID extended part IDREC4 ID extended part 0 0 0 unused DATAO Message data byte 0 DATA1 Message data byte 1 DATA2 Message data byte 2 DATA3 Message data byte 3 DATA4 Message data byte
208. ask ROM version The differences between the two versions are shown in Table 1 4 below Differences of the electrical specification are given in Chapter 24 Electrical specifications on page 411 Table 1 4 Differences between Flash and Mask ROM version ROM Flash EEPROM Mask ROM LCD Split Resistor None Mask Option Vpp pin Yes None IC pin User s Manual U12670EE3VOUDOO 35 MEMO 36 User s Manual U12670EE3VOUD00 2 1 Pin Function List Chapter 2 Pin Function uPD780948 Subseries Normal Operating Mode Pins Pin Input Output Types Table 2 1 Pin Input Output Types 1 2 Input Output Pin Name Function Alternate Function POO INTPO Input P01 INTP1 Input P02 Port 0 INTP2 Input P03 8 bit input output port INTP3 T2PO Input Input Output input output mode can be specified bit wise P04 If used as an input port a pull up resistor can be INTPA TIO1 Input P05 connected by software bit wise TIOO TOO Input P06 TI50 TO50 Input P07 TI51 TO51 Input Port 1 Input P10 P17 8 bit input port ANIO ANI7 Input Input mode can be specified bit wise P20 SIO Input P21 500 Input Port 2 pee 7 bit output port SONO Input Input Output P23 input output mode can be specified bit wise SI1 SO1 Input If used as an output port the port buffer can be set fea CMOS or N ch open drain buffer Sei input
209. ate for a particular buffer A DN flag set indicates a new message that arrived or a new message that is in progress of being stored to that buffer The application should be prepared to receive a message immediately after redefinition state was set The user can identify this situation because the data new bit DN in the receive buffer will be set This is of special importance if it is used together with a mask function because in this case the DCAN also writes the identifier part of the message to the receive buffer Then the application needs to re write the configuration of the message buffer 318 User s Manual U12670EE3VOUD00 Chapter 16 CAN Controller 16 16 Interrupt Information 16 16 1 Interrupt Vectors The DCAN peripheral supports four interrupt sources as shown in the following table Table 16 27 Interrupt Sources Function Interrupt Flag Error counter Error Overrun error Wake up Receive Received frame is valid Transmit buffer 0 TXRQO is cleared Transmit buffer 1 TXRQ1 is cleared 16 16 2 Transmit Interrupt The transmit interrupt is generated when all following conditions are fulfilled The transmit interrupt 0 is generated when TXRQO bit is cleared The transmit interrupt 1 is generated when TXRQ1 bit is cleared Clearing of these bits releases the buffer for writing a new message into it This event can occur due to a successful transmission or due to an abort of a transmission Only the DCAN
210. ation Note segment lo 1 pA Note The voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs Vi cpw 0 1 2 458 User s Manual U12670EE3VOUDOO pPD78F0948 Chapter 25 Electrical Specifications LCD C D 1 2 Bias Method Parameter LCD drive voltage Conditions LCD split resistor LCD output voltage deviation Note common Vicbo Vicp Vicpi Vicp x 1 2 Vicpe Vicp X 1 2 LCD output voltage deviation Note segment lo 1 pA Note The voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs Vi cpw 0 1 2 pPD78F0948 LCD C D 1 3 Bias Method Parameter LCD drive voltage Symbol Conditions MIN TYP Unit LCD split resistor LCD output voltage deviation Note common Vicpo Vicp Vicpi Vicp x 2 8 Vicpe 1 8 LCD output voltage deviation Note segment lg 2 1 pA Note The voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs Vi cpw 0 1 2 User s Manual U12670EE3VOUDOO 459 Chapter 25 Electrical Specifications 25 6 AC Characteristics 25 6 1 Basic Operation 1 pPD780948 A 40 C to 85 C Vpp 4 0 to 5 5 V Parameter T
211. ator 1 Sound generator control register SGCR SGCR is a register which sets up the following four types Controls sound generator output Selects output of sound generator e Selects sound generator input frequency e Selects 5 bit counter input frequency fggo SGCR is set with an 1 bit or an 8 bit memory manipulation instruction RESET input clears SGCR to 04H Figure 18 3 shows the SGCR format Figure 18 3 Sound Generator Control Register SGCR Format 1 2 Symbol 7 6 2 1 0 Address After Reset R W 5 4 3 TCE Sound Generator Output Selection Timer operation stopped SGOF SGO and SGOA for low level output Sound generator operation SGOF SGO and SGOA for output Caution Before setting the TCE bit set all the other bits Remark SGOF Basic cycle signal without amplitude SGO Basic cycle signal with amplitude SGOA Amplitude signal SGOB Sound Generator Output Selection 0 Selects SGOF and SGOA outputs 1 Selects SGO and PCL outputs 5 Bit Counter Input Frequency fea Selection fgqe 01 22 fsq2 fsq1 29 1501 27 fgq1 2 User s Manual U12670EE3VOUDOO 361 Chapter 18 Sound Generator Figure 18 3 Sound Generator Control Register SGCR Format 2 2 SGCLO Sound Generator Input Frequency Selection 0 fy 2 1 fsc1 fx Cautions 1 When rewriting SGCR to other data stop the timer operation TCE 0 beforehand 2 Bits 4
212. ave Output 144 Start Timing of 16 Bit Timer 145 Timing after Changing Compare Register during Timer Count Operation 145 Data Hold Timing of Capture 146 Operation Timing of OVFO 22 4022440 0000 nennen nnne ns 147 Timer 2 TM2 Block nennen nennen 149 16 Bit Timer Mode Control Register TMC2 152 Capture Pulse Control Register CRC2 153 Prescaler Mode Register PRM2 Format seen 154 Configuration Diagram for Pulse Width Measurement by Using the Free Running Counter sss 155 Timing of Pulse Width Measurement Operation by Using the Free Running Counter and One Capture Register with Both Edges Specified 156 CR2m Capture Operation with Rising Edge Specified 157 Timing of Pulse Width Measurement Operation by Free Running Counter with Both Edges 158 16 Bit Timer Register Start Timing 159 Capture Register Data Retention Timing sse 159 8 Bit Timer Event Counter 50 Block 163 8 Bit Timer Event Counter 51 Block 164 Blo
213. ber uSxxxxFI78K0 PC 9800 Series PC AT and compatible machines Support software for evaluation and adjustment of fuzzy knowledge data by using in FD78K0 circuit emulator and at hardware level Fuzzy inference debugger Part number uSxxxxFD78K0 PC 9800 Series PC AT and compatible machines User s Manual U12670EE3VOUDOO 497 MEMO 498 User s Manual U12670EE3VOUDOO Appendix Index Numerics baie ase 124 16 bit timer mode control register 124 16 bit timer mode control register 2 152 16 bit timer output control register 4 127 16 bit timer register 121 16 bit timer register TM2 150 8 bit timer mode control register 50 TMC50 168 8 bit timer mode control register 51 TMC51 169 8 bit timer registers 50 and 51 TM50 TM51 165 A A D conversion result register ADCR1 205 217 A D converter mode register 1
214. bias method and Figure 17 19 1 3 bias method When 521 is at the selection volt age at the COM 1 selection timing and S21 is at the selection voltage at the COM2 selection timing it can be seen that the cp V cp AC square wave which is the LCD illumination ON level is gener ated Figure 17 16 3 Time Division LCD Display Pattern and Electrode Connections San 1 COMO Vo COM2 Remark nz0to 12 350 User s Manual U12670EE3VOUD00 Chapter 17 LCD Controller Driver Figure 17 17 3 Time Division LCD Panel Connection Example COM3 Open COMO 1 2 Lig 1 LLI8 OLId seqouis 50 51 52 53 54 55 56 57 58 59 510 511 512 513 514 jeued q21 515 516 517 518 sseJppe Aiowew ejeq 19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 531 532 533 534 535 536 537 538 ul o FA98H Irrelevant bits because they have no corresponding segment in the LCD panel x Remarks 1 Irrelevant bits because this is a 3 time division display X 351 User s Manual U12670EE3VOUD00 Chapter 17 LCD Controller Driver Figure 17 18 3 Time Division LCD Drive Waveform Examples 1 2 Bias Method Vico Vic1 Vice Vss COMO Vico Vic1 Vice Vss1 Tr Vico COM2
215. bit DBTxn and the sample point position SPTxn Converted to register values the following condition applies 2 lt DBTxn SPTxn lt 8 n 0 1 x 4 to 0 The number of TQ allocated for soft synchronization must not exceed the number of TQ for phase segment 2 but SJWyn may have as many TQ as phase segment 2 SJWyn x DBTxn SPTxn 1 n 0 1 x 4 to 0 y 0 1 Note Sample point positions of 3 TQ or 4 TQ are for test purposes only For the minimum number of TQ per bit time 8TQ the minimum sample point position is 5 TQ Example System clock fx 8 MHz CAN parameter Baud rate 500 kBaud Sample Point 75 SJW 25 At first calculate the overall prescaler value fx 8 MHz Baudrate 500 16 be split as 1 x 16 2 x 8 Other factors not be mapped to the registers Only 8 and 16 are valid values for TQ per bit Therefore the overall prescaler value realized by BRPRSn is 2 or 1 respectively The following register settings apply Bit fields Register value Description 310 BRPRSn 00h Clock selector fx PRMn 00b BRPRSx 000000b SYNCOn A7h CAN Bit in TQ 8 DBTx 00111b 7 lt fx Baudrate bit rate prescaler lt 25 sample point 75 6 TQ SJW 25 2 TQ 1 TQ equals 2 clocks SPTx 001016 SJWy 016 1 022201006 2 depends on the setting of Number of sampling points Receive only function Use of time stamp or global time system User s Man
216. both types of frames standard and extended during global mask operation All unused bytes can be used by the CPU for application needs 1 Identifier Compare with Mask The identifier compare with mask provides the possibility to exclude some bits from the compari son process That means each bit is ignored when the corresponding bit in the mask definition is set to one The setup of the mask control register MASKC defines which receive buffer is used as a mask and which receive buffer uses which mask for comparison The mask does not include any information about the identifier type to be masked This has to be defined within the dedicated receive buffer Therefore a global mask can serve for standard receive buffers at the same time as for extended receive buffer 292 User s Manual U12670EE3VOUDOO Chapter 16 CAN Controller Figure 16 31 Identifier Compare with Mask Received Identifier Compare Bit by Bit Store on 2 Mask stored in Receive Buffer 0 or 2 Disable Compare for masked Bits Identifier stored in Receive Buffer This function implements the so called basic CAN behaviour In this case the type of identifier is fixed to standard or extended by the setup of the IDE bit in the receive buffer The comparison of the RTR bit can also be masked It is possible to receive data and remote frames on the same masked receive buffer The following information is stored in the receive
217. buffer Identifier 11 or 29 bit as defined by IDE bit Remote bit RTRpec if both frames types data or remote can be received by this buffer Reserved bits Data length code DLC Data bytes as defined by DLC Caution All writes into the DCAN memory are byte accesses Unused bits in the same byte will be written zero Unused bytes will not be written and are free for application use by the CPU User s Manual U12670EE3VOUDOO 293 Chapter 16 CAN Coniroller 2 Mask Identifier Control Register MCON The memory location labelled MCON sets the mask identifier control bit of the CAN protocol MCON can be set with a 1 bit or an 8 bit memory manipulation instruction RESET input sets MCON to an undefined value Figure 16 32 Control Bits for Mask Identifier Symbol 7 6 0 Address After Reset R W 5 4 3 2 1 0 Check RTR bit of received message Note 1 1 Receive message independent from RTR bit Note 2 Notes 1 For RTR 0 the received frame type data or remote is defined by the RTR bit in IDCON of the dedicated buffer In this case RTRggc will always be written to 0 together with the update of the IDn bits n 18 to 20 in IDREC1 2 In case RTR in MCON is set to 1 RTR bit in IDCON of the dedicated receive buffer has no meaning The received message type passed the mask is shown in the RTRpgc bit 294 User s Manual U12670EE3VOUDOO Chapter 16 CAN Controller 3 Mask Identifier Definition Thes
218. buffer register RXBO 234 Receive message register 1 1 314 Receive shift register 1 RXSO 4 234 Redefinition control register 317 Register bank select flags RBSO RBS1 63 5 Serial I O shift register 51030 220 Serial I O shift register SIO31 226 Serial Operation Mode Register CSIM30 222 223 Serial operation mode register CSIM30 221 Serial Operation Mode Register CSIM31 228 229 Serial operation mode register CSIM31 1 227 Sound generator amplitude register 363 500 User s Manual U12670EE3VOUD00 Appendix Index Sound generator buzzer control register SGBR 363 Sound generator control register SGCR 361 Special function register SFR 66 78 Special Function Register List
219. by RESET Input Wait HALT 2 f 16 3 ms Instruction RESET Signal Oscillation Operating Reset Stabilization Operating Mode HALT Mode Period Wait Status Mode Oscillation Oscillation stop Oscillation Clock a Remarks 1 fy Main system clock oscillation frequency 2 Values in parentheses apply to operation at fy 8 0 MHz Table 21 2 Operation after HALT Mode Release Release Source Operation Next address instruction execution 0 Interrupt service execution 0 Maskable interrupt request 1 5 Next address instruction execution 0 1 1 1 Interrupt service execution 1 X X X HALT mode hold Non maskable interrupt request X X Interrupt service execution RESET input x x Reset processing Remark x Don t care User s Manual U12670EE3VOUDOO 407 Chapter 21 Standby Function 21 2 2 STOP mode 1 STOP mode set and operating status The STOP mode is set by executing the STOP instruction It can be set only with the main system clock Cautions 1 When the STOP mode is set the X2 pin is internally connected to Vpp via a pull up resistor to minimize leakage current at the crystal oscillator Thus do not use the STOP mode in a system where an external clock is used for the main system clock 2 Because the interrupt request signal is used to clear the standby mode if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset the
220. can clear this bit The CPU can only request to clear the TXRQn bit by setting the ABORTn bit n 0 1 16 16 3 Receive Interrupt The receive interrupt is generated when all of the following conditions are fulfilled CAN protocol part marks received frame valid The received frame passes the acceptance filter In other words a message buffer with an identifier mask combination fits to the received frame The memory access engine successfully stored data in the message buffer The message buffer is marked for interrupt generation with ENI bit set The memory access engine can delay the interrupt up to the 7th bit of the next frame because of its compare and store operations User s Manual U12670EE3VOUDOO 319 Chapter 16 CAN Coniroller 16 16 4 Error Interrupt The error interrupt is generated when any of the following conditions are fulfilled Transmission error counter BOFF changes its state Transmission error counter status TECS changes its state Reception error counter status RECS changes its state Overrun during RAM access OVER becomes active The wake up condition WAKE becomes active The wake up condition activates an internal signal to the interrupt controller In order to receive further error interrupts generated by other conditions the CPU needs to clear the WAKE bit in CANES register every time a wake up condition was recognized No further interrupt can be detected by the CPU as l
221. cannot be used at high temperature T4 110 C The maximum temperature is T4 85 456 User s Manual U12670EE3VOUDOO 3 pPD78F0948 Chapter 25 Electrical Specifications 40 C to 85 Vpp 4 0 to 5 5 V Parameter Symbol Conditions POO P07 P10 P17 P20 P26 P30 P34 P40 P47 P50 P57 P64 P65 P67 P70 P77 P120 P127 P130 P137 P140 P147 RESET CRXD X1 X2 CL1 Low level P00 P07 P10 P17 P20 P26 P30 P34 P40 P47 P50 P57 P64 P65 P67 P70 P77 P120 P127 P130 P137 P140 P147 input voltage RESET CRXD X1 X2 CL1 P00 07 P10 P17 P20 P26 P30 P34 P40 P47 P50 P57 y 40 55V P64 P65 P67 P70 P77 P120 P127 P130 P137 P140 P147 CTXD lou 1mA Low level output voltage Vpp 4 5 5 5 V loH 20 mA SGO P07 P10 P17 P20 P26 P30 P34 P40 P47 P50 P57 Y p 4 0 5 5V P64 P65 P67 P70 P77 P120 127 130 137 140 147 CTXD Vpp 4 5 5 5V SGO lot 20 P00 07 10 P17 P20 P26 P30 P34 P40 P47 P50 P57 P64 P65 P67 P70 P77 P120 Vin P127 P130 P137 P140 P147 CRXD ANIO ANI7 X1 X2 CL1 P07 P10 P17 P20 P26 P30 P34 P40 P47 P50 P57 P64 P65 P67 P70 P77 P120 P127 P130 P137 P140 P147 CRXD ANIO ANI7 X1 X2 CL1 4
222. ce Expansion 2 Memory expansion wait register MM MM sets the wait count MM is set with an 1 bit memory or an 8 bit memory manipulation instruction RESET input sets this register to 10H Figure 20 3 Memory Expansion Wait Register Format Symbol 7 6 0 Address After Reset R W 5 4 3 2 1 PWO Wait Control 0 No wait 1 Wait one wait state insertion 394 User s Manual U12670EE3VOUDOO Chapter 20 External Device Expansion 3 Memory size switching register IMS This register specifies the internal memory size In principle use IMS in a default status However when using the external device expansion function with the u PD780948 set IMS so that the inter nal ROM capacity is 56 Kbytes or lower IMS is set with an 8 bit memory manipulation instruction RESET input sets this register to the value indicated in Table 20 3 Figure 20 4 Memory Size Switching Register Format Symbol lt 7 gt lt 6 gt lt 2 gt lt 1 gt lt 0 gt Address After Reset R W lt 5 gt 4 lt 3 gt Raw Raw RAW 0 Rone ROM FFFOH Note RM Internal ROM size selection 32 Kbytes 56 Kbytes 60 Kbytes Other than above Setting prohibited RAM2 RAM1 RAMO Internal high speed RAM size selection 1 1 0 1024 bytes Other than above Setting prohibited Note The values after reset depend on the product See Table 20 3 Table 20 3 Values when the Memory Size Switching Register is Reset
223. ceived synchronized with the serial clock The serial I O shift register 30 51030 is shifted synchronized with the falling edge of the serial clock The transmission data is held in the SOO latch and is transmitted from the SOO pin The data is received via the SIO pin synchronized with the rising edge of the serial clock is latched to 51030 The completion of an 8 bit transfer automatically stops operation of 51030 and sets a serial trans fer completion flag Figure 13 5 Timing of Three wire Serial I O Mode Serial clock 1 2 3 4 5 6 7 8 ov os pos 5 58505 oos oos 5 DOO Serial transfer completion flag 3 Transfer completion Transfer starts in synchronized with the serial clock s falling edge 3 Transfer start A serial transfer starts when the following conditions have been satisfied and transfer data has been set to serial I O shift register 30 5 0 The 51030 operation control bit must be set CSIE30 1 In Transmit receive mode When CSIE30 1 and MODEO 0 transfer starts when writing to 51030 n Receive only mode When CSIE30 1 and MODEO 1 transfer starts when reading from 51030 Caution After the data has been written to SIO30 the transfer will not start even if the CSIE30 bit value is set to 1 The completion of an 8 bit transfer automatically stops the serial transfer operation and sets a serial transfer completion flag 224 U
224. ck Diagram of 8 Bit Timer Event Counters 50 and 51 Output Control Circuit 165 Timer Clock Select Register 50 166 Timer Clock Select Register 51 167 8 Bit Timer Mode Control Register 50 168 8 Bit Timer Mode Control Register 51 Format 1 2 169 Port Mode Register 0 170 8 Bit Timer Mode Control Register Settings for Interval Timer Operation 171 Interval Timer Operation Timings 1 3 sess 172 8 Bit Timer Mode Control Register Setting for External Event Counter Operation 176 External Event Counter Operation Timings with Rising Edge Specified 176 8 Bit Timer Mode Control Register Settings for Square Wave Output Operation 177 Square wave Output Operation Timing 178 8 Bit Timer Control Register Settings for PWM Output Operation 179 User s Manual U12670EE3VOUD00 Figure 8 16 Figure 8 17 Figure 8 18 Figure 8 19 Figure 8 20 Figure 8 21 Figure 8 22 Figure 9 1 Figure 9 2 Figure 9 3 Figure 10 1 Figure 10 2 Figure 10 3 Figure 11 1 Figure 11 2 Figure 11 3 Figure 11 4 Figure 12 1 Figure 12 2 Figure 12 3 Figure 12 4 Figure 12 5 Figure 12 6 Figure 12 7 Figure 12 8 Figure 12 9 Figure 12 10 Figure 12 11 Figure 12 12 Figure 12 13 Figure 13 1 Figure 13 2 Figure 13 3 Figu
225. clock of the 8 bit timer register 50 TM50 can be selected with the timer clock select register 50 TCL50 and count clock of the 8 bit timer register 51 TM51 can be selected with the timer clock select register 51 TCL51 Figure 8 9 8 Bit Timer Mode Control Register Settings for Interval Timer Operation TCEn TMCn6 TMCn4 LVSn LVRn TMCn1 TOEn on on on ont 8 bit timer event counter mode Clear and start on match of TMn and CRn TMn operation enable Setting Method 1 Set each register TCL5n Selects the count clock CR5n Compare value TMC5n Selects the clear and start mode when TM5n and CR5n match TMC5n 0000xxxx0B x is not done care 2 When TCE5n 1 is set counting starts 3 When the values of TM5n and CR5n match INTTM5n is generated TM5n is cleared to 00H 4 Then INTTM5n is repeatedly generated during the same interval When counting stops set TCE5n 0 Remarks 1 0 1 Setting 0 or 1 allows another function to be used simultaneously with the interval timer See 8 3 3 8 bit timer mode control register 50 TMC50 on page 168 and 4 8 bit timer mode control register 51 TMC51 on page 169 for details 2 n2 50 51 User s Manual U12670EE3VOUDOO 171 Chapter 8 8 Bit Timer Event Counters 50 and 51 Figure 8 10 Interval Timer Operation Timings 1 3 a When N z 00H to FFH t i Ml mn count vane YoY JE C X4 JO G8 X C4 C83 A A TCEn o
226. clock select register 51 TCL51 This register sets count clocks of 8 bit timer register 51 TCL51 is set with an 8 bit memory manipulation instruction RESET input sets TCL51 to OOH Figure 8 5 Timer Clock Select Register 51 Format 7 6 5 4 3 2 1 0 Address Alter Reset TCL512 TCL511 TCL510 8 bit Timer Register 51 Count Clock Selection TI51 falling edge Note TI51 rising edge Note fx 8 0 MHz fy 2 4 0 MHz 5 23 1 0 MHz fy 2 250 KHz fy 2 62 5 KHz fy 2 1 9 KHz Other than above Setting prohibited Note When clock is input from the external timer output PWM output cannot be used Cautions 1 When rewriting TCL51 to other data stop the timer operation beforehand 2 Set always bits to 7 to 0 Remarks 1 fy Main system clock oscillation frequency 2 T151 8 bit timer register 51 input pin 3 Values in parentheses apply to operation with fy 8 0 MHz User s Manual U12670EE3VOUDOO 167 Chapter 8 8 Bit Timer Event Counters 50 and 51 3 8 bit timer mode control register 50 TMC50 This register enables stops operation of 8 bit timer register 50 sets the operating mode of 8 bit timer register 50 and controls operation of 8 bit timer event counter 50 output control circuit It selects the R S flip flop timer output F F 1 2 setting resetting the active level in PWM mode inversion enabling disabling in modes other than PWM mode and 8 bit timer
227. comparing and storing received data or fetching transmitted data Typically the overrun condition is encountered when the frequency for the macro is too low compared to the programmed baud rate An error interrupt is generated at the same time The DCAN interface will work properly i no overrun condition will occur with the following settings The DCAN clock as defined with the PRM bits in the BRPRS register is set to a minimum of 16 times of the CAN baudrate and the selected CPU clock defined in the PCC register is set to a minimum of 16 times of the baudrate Possible reasons for an overrun condition are Too many messages are defined DMA access to RAM area is too slow compared to the CAN Baudrate The possible reactions of the DCAN differ depending on the situation when the overrun occurs 302 User s Manual U12670EE3VOUD00 Chapter 16 CAN Controller Table 16 25 Possible Reactions of the DCAN Overrun Situation When detected DCAN Behavior The frame itself conforms to the CAN specification but its content is faulty Next data byte request from protocol Corrupted data or ID in the frame Immediate during the frame TXRQX bit x 0 1 is not cleared DCAN will retransmit the correct frame after synchronization to the bus Cannot get transmit data Data in RAM is inconsistent No receive flags DN and MUC bit may be set in message Data storage is ongoing during the Cannot store receive data six bit of th
228. connecting a dedicated flash writer to the host machine and the target system Moreover writing to flash memory can also be performed using a flash memory writing adapter con nected to flash programmer 23 3 1 Selection of transmission method Writing to flash memory is performed using a flash programmer and serial a communication Select the transmission method for writing from Table 23 4 For the selection of the transmission method a format like the one shown in Figure 23 3 is used The transmission methods are selected with the Vpp pulse numbers shown in Table 23 4 Table 23 4 Transmission Method List 25 Number of Number Transmission Method Channels Pin Used Vpp Pulses SIO P20 3 wire serial I O SO0 P21 5 22 P30 Serial data input Pseudo 3 wire serial I O P31 Serial data output P32 Serial clock input RXDO P25 TXDO P26 Cautions 1 Be sure to select the number of Vpp pulses shown in Table 23 4 for the transmis sion method 2 If performing write operations to flash memory with the UART transmission method set the main system clock oscillation frequency to 4 MHz or higher Figure 23 3 Transmission Method Selection Format Vpp pulses RESET Flash write mode Vss 418 User s Manual U12670EE3VOUDOO Chapter 23 078 0948 23 3 2 Initialization of the programming mode When Vpp
229. control register CR00 CRO1 Prescaler selection register PRMO Mode control register TMCO Capture compare control register 0 CRCO Output control register TOCO 16 bit timer event counter 2 Timer register TM2 Capture control register CR20 CR21 CR22 Prescaler mode register PRM2 Mode control register TMC2 8 bit timer event counters 50 and 51 Timer register TM50 TM51 Compare register CR50 CR51 Clock select register TCL50 TCL51 Mode control register TMC50 TMC51 Watch timer Mode register WTM Watchdog timer Clock selection register WDCS Mode register WDTM PCL clock output Clock output selection register CKS Sound generator Control register SGCR Amplitude control SGAM Buzzer control SGBC Notes 1 During reset input or oscillation stabilization time wait only the PC contents among the hardware sta tuses become undefined All other hardware statuses remains unchanged after reset 2 The post reset status is held in the standby mode User s Manual U12670EE3VOUDOO 413 Chapter 22 Reset Function Table 22 1 Hardware Status after Reset 2 2 Hardware Status after Reset Operating mode register 0 CSIM30 Shift register 0 SIO30 Operating mode register 1 CSIM31 Shift register 1 S1031 Serial interface Asynchronous mode register ASIMO Asynchronous status
230. counter User s Manual U12670EE3VOUD00 Chapter 16 CAN Controller 16 3 Outline Description Figure 16 22 Structural Block Diagram CANL CANH CPU Actess Receive Bus Arbitration Logic eiue F Receive Messages CPU Memory Buffer SFR Memory RAM Access Engine Interface Transmit Management Buffers High Spoed includes global registers CAN Protocol External Transceiver Time Stamp Signal DCAN Interface Timer This interface part handles all protocol activities by hardware in the CAN protocol part The memory access engine fetches information for the CAN protocol transmission from the dedicated RAM area to the CAN protocol part or compares and sorts incoming information and stores it into predefined RAM areas The DCAN interfaces directly to the RAM area that is accessible by the DCAN and by the CPU The DCAN part works with an external bus transceiver which converts the transmit data and receive data lines to the electrical characteristics of the CAN bus itself User s Manual U12670EE3VOUDOO 277 Chapter 16 CAN Coniroller 16 4 Connection with Target System The DCAN Macro has to be connected to the CAN bus with an external transceiver Figure 16 23 Connection to the CAN Bus DCAN Macro CRXD CANL CANH 16 5 CAN Controller Configuration The CAN module consists of the following hardware Table 16
231. ct See Table 23 2 Table 23 2 Values when the Memory Size Switching Register is Reset uPD780948 CFH pPD78F0948 CFH 416 User s Manual U12670EE3VOUDOO Chapter 23 PD78F0948 23 2 Internal Expansion RAM Size Switching Register The uPD78F0948 allows users to define its internal extension RAM size by using the internal expansion RAM size switching register IXS so that the same memory mapping as that of a mask ROM version with a different internal expansion RAM is possible The IXS is set by an 8 bit memory manipulation instruction RESET signal input sets IXS to OCH Caution When the pPD780948 and pPD78F0948 are used be sure to set the value specified in Table 23 3 to IXS Other settings are prohibited Figure 23 2 Internal Expansion RAM Size Switching Register Format Symbol 7 2 1 0 Address After Reset R W IXRAM3 IXRAM IXRAM1 IXRAMO Internal Expansion RAM capacity selection 1 0 1 1024 bytes Other than above Setting prohibited The value which is set in the IXS that has the identical memory map to the mask ROM versions is given in Table 23 3 Table 23 3 Examples of internal Expansion RAM Size Switching Register Settings Relevant Mask ROM Version IXS Setting 780948 uPD78F0948 User s Manual U12670EE3VOUDOO 417 Chapter 23 pPD78F0948 23 3 Flash memory programming On board writing of flash memory with device mounted on target system is supported On board writing is done after
232. d TCON includes the information of the RTR bit and the bits of the control field of a data or remote frame TCON is set with a 1 bit or an 8 bit memory manipulation instruction RESET input sets TCON to an undefined value Figure 16 24 Transmit Message Definition Bits Symbol 7 6 2 1 0 Address After Reset R W 5 4 3 Identifier Extension Select Transmit standard frame message 11 bit identifier Transmit extended frame message 29 bit identifier RTR Remote Transmission Select Transmit data frames Transmit remote frames Data Length Code Selection of Transmit Message 0 data bytes 1 data bytes 2 data bytes 3 data bytes 4 data bytes 5 data bytes 6 data bytes 7 data bytes 0 8 data bytes DLC3 DLC2 DLC1 DLCO Others than above Note Remark The control field describes the format of frame that is generated and its length The reserved bits of the CAN protocol are always sent in dominant state 0 Note The data length code selects the number of bytes which have to be transmitted Valid entries for the data length code DLC are 0 to 8 If a value greater than 8 is selected 8 bytes are transmitted in the data frame The Data Length Code is specified in DLC3 through DLCO 282 User s Manual U12670EE3VOUDOO Chapter 16 CAN Controller 2 Transmit Identifier Definition These memory locations set the message identifier in the arbitration field of the CAN prot
233. d and counting starts Notes 1 Once set to 1 WOTM3 WDTM4 cannot be cleared to 0 by software 2 Once set to 1 RUN cannot be cleared to 0 by software Thus once counting starts it can only be stopped by RESET input Caution When 1 is set in RUN so that the watchdog timer is cleared the actual overflow time is up to 0 5 shorter than the time set by watchdog timer clock select register Remark don t User s Manual U12670EE3VOUDOO 195 Chapter 10 Watchdog Timer 10 4 Watchdog Timer Operations 10 4 1 Watchdog timer operation When bit 4 WDTM4 of the watchdog timer mode register WDTM is set to 1 the watchdog timer is operated to detect any inadvertent program loop The watchdog timer count clock inadvertent program loop detection time interval can be selected with bits to 2 WDCSO to WDCS2 of the timer clock select register WDCS Watchdog timer starts by setting bit 7 RUN of WDTM to 1 After the watchdog timer is started set RUN to 1 within the set overrun detection time interval The watchdog timer can be cleared and count ing is started by setting RUN to 1 If RUN is not set to 1 and the inadvertent program loop detection time is past system reset or a non maskable interrupt request is generated according to the WDTM bit 3 WDTM3 value The watchdog timer can be cleared when RUN is set to 1 The watchdog timer continues operating in the HALT mode but it stops in the STOP mode Thus set R
234. de A value is written to the output latch by a transfer instruction but since the output buffer is OFF the pin status does not change Once data is written to the output latch it is retained until data is written to the output latch again Caution In the case of 1 bit memory manipulation instruction although a single bit is manipu lated the port is accessed as an 8 bit unit Therefore on a port with a mixture of input and output pins the output latch contents for pins specified as input are undefined except for the manipulated bit 4 4 2 Reading from input output port 1 Output mode The output latch contents are read by a transfer instruction The output latch contents do not change 2 Input mode The pin status is read by a transfer instruction The output latch contents do not change User s Manual U12670EE3VOUDOO 103 Chapter 4 Port Functions 4 4 3 Operations on input output port 1 Output mode An operation is performed on the output latch contents and the result is written to the output latch The output latch contents are output from the pins Once data is written to the output latch it is retained until data is written to the output latch again 2 Input mode The output latch contents are undefined but since the output buffer is OFF the pin status does not change Caution In the case of 1 bit memory manipulation instruction although a single bit is manipu lated the port is accessed as an 8 bit unit T
235. de register CSIM31 1 Serial operation mode register CSIM31 This register is used to enable or disable the serial clock selects operation modes and defines specific operations CSIM31 can be set via an 1 bit or an 8 bit memory manipulation instruction The RESET input sets the value to OOH Figure 14 2 Format of Serial Operation Mode Register CSIM31 lt 7 gt 6 5 4 3 2 1 0 Address Alter Reset CSIE31 0 5 1311 5 1310 FFAAH 00H Enable disable specification for SIO31 CSIE31 Shift register operation Serial counter Port Note Operation stop Clear Port function Operation enable Count operation enable Serial operation port function Transfer operation modes and flags Operation mode Transfer start trigger SO1 SH P23 Transmit receive mode Write to 51031 501 511 Receive only mode Read from SIO31 Port function SCL311 SCL310 Clock selection fx 8 00 MHz External clock input 8 bit timer 50 TM50 output 1 28 14 27 Note When CSIE31 0 SIO31 operation stop status the pins connected to 511 501 and 5 can be used for port functions User s Manual U12670EE3VOUDOO 227 Chapter 14 Serial Interface Channel 31 14 5 Serial Interface Channel 31 Operations This section explains two modes of 51031 14 5 1 Operation stop mode This mode is used if the serial transfers are not performed to reduce power c
236. djacent to the pin undergoing A D conversion AVrer pin input impedance A series resistor string of approximately 21 is connected between the AVpp AVggr and the AVss pin Therefore if the output impedance of the reference voltage is high this will result in parallel con nection to the series resistor string between the AVpp AVggr pin and the AVss pin and there will be a large reference voltage error User s Manual U12670EE3VOUD00 7 A D conversion Chapter 12 A D Converter Interrupt request flag ADIF The interrupt request flag ADIF is not cleared even if the analog input channel specification reg ister ADS1 is changed Caution is therefore required if a change of analog input pin is performed during A D conversion The A D conversion result and conversion end interrupt request flag for the pre change analog input may be set just before the ADS1 rewrite If the ADIF is read immediately after the ADS1 rewrite the ADIF may be set despite the fact that the A D conversion for the post change analog input has not ended When the A D conversion is stopped and then resumed clear ADIF before the A D conversion operation is resumed Figure 12 12 A D Conversion End Interrupt Request Generation Timing ADS1 rewrite ADS1 rewrite ADIF is set but ANIm conversion start of ANIn conversion start of ANIm wa has not ended ADCR1 Remarks 1 n 0 1 4 2 0 1 4 8 Read of A D conversion r
237. dr byte sfr byte str lt byte Ar Note 3 Aer Note 3 lt saddr lt saddr saddr A saddr lt A A sfr lt sfr sfr sfr A A laddri6 lt addr16 laddr16 addri6 A PSW byte PSW c byte A PSW lt PSW PSW PSW A A DE lt DE DE DE lt A HL lt HL HL A HL A A HL byte lt HL byte HL byte A HL byte A A HL A lt HL HL B A A A HL C A HL HL C A HL C lt Ar Note 3 Aer A saddr A MD MD oj A A AJA 6 saddr A sfr 6 sfr A laddr16 10 n m addr16 A DE 6 n m A HL 6 n m HL A HL byte 10 n m HL byte A HL 10 n m gt DE HL B A HL C PO PO POP H CY NI N a aS NI N NI N NINI N 10 n m o HL When the internal high speed RAM area is accessed or instruction with no data access When an area except the internal high speed RAM area is accessed Except r A Only when rp BC DE or HL
238. dress After Reset MONT GADD CADDO TURES MONTZ WONTS WONTZMONTTIMONT R W R W R W R W R W R W R W R W This register is readable at any time Write is only permitted when the CAN is in initialization mode Receive Message Count Setting prohibited 1 receive buffer 2 receive buffer 3 receive buffer 4 receive buffer 5 receive buffer 6 receive buffer 7 receive buffer oo o o oo co 8 receive buffer 9 receive buffer 10 receive buffer 11 receive buffer 12 receive buffer 13 receive buffer 14 receive buffer 15 receive buffer 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 16 receive buffer Setting prohibited will be automatically changed to 16 304 User s Manual U12670EE3VOUDOO Chapter 16 CAN Controller Figure 16 42 Message Count Register MCNT 2 2 TLRES Reset function for CAN Protocol Machine No Reset is issued Reset of CAN protocol machine is issued if DCAN is in bus off state will enter INIT state CANC 0 1 amp amp CANES 3 1 Cautions 1 Issuing TLRES bit may violate the minimum recovery time as defined in ISO 11898 2 If no receive buffer is desired define one receive buffer and disable this buffer with the REDEF function DCAN Address definition Setting prohibited F600H to F7DFH reset value User s Manual U12670
239. e and Vggp to different ground lines is recommended Pin Identifications POO to P07 P10 to P17 P20 to P26 P30 to P34 P40 to P47 P50 to P57 P64 P65 P67 P70 to P77 P120 to P127 P130 to P137 P140 to P147 INTPO to INTP4 00 01 0 1 20 to 22 TOO 51 TO52 T2PO CRXD CTXD CCLK 510 500 SCKO SCK1 511 801 30 Port 0 1 2 Port 4 5 6 Port 7 12 13 14 Interrupt from Peripherals Timer Input Timer Input Timer Input Timer Output Timer Output CAN Receive Data CAN Transmit Data CAN Clock Serial Input Serial Output Serial Clock Serial Input Output User s Manual U12670EE3VOUD00 RXD TXD SGO SGOA SGOF PCL ADO to AD7 A8 to A15 RD WR ASTB S0 to S39 COMO to COMS X1 X2 CL1 CL2 RESET ANIO to ANI7 AVss AVpp AVReEF Receive Data Transmit Data Sound Generator Output Sound Generator Amplitude Sound Generator Frequency Programmable Clock Output Address Data Bus Address Bus Read Strobe Write Strobe Address Strobe Segment Output Common Output Crystal Main System Clock RC Subsystem clock Reset Analog Input Analog Ground Analog Reference Voltage and ADC Power Supply Power Supply Programming Power Supply Ground Internally Connected Chapter 1 Outline uPD780948 Subseries 1 6 78K 0 Series Expansion The following shows the products or
240. e CALLFladdr11 instruction branches to the area from 0800H to OFFFH Figure 3 12 Immediate Addressing a In the case of CALL addr16 and BR addr16 instructions 7 0 CALL or BR Low Addr High Adar 15 87 0 PC b In the case of CALLF addr11 instruction User s Manual U12670EE3VOUDOO 71 Chapter 3 CPU Architecture 3 3 3 Table indirect addressing Table contents branch destination address of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter PC and branched Table indirect addressing is carried out when the CALLT addr5 instruction is executed This instruction can refer to the address stored in the memory table 40H to 7FH and branch to all the memory space 72 Figure 3 13 Table Indirect Addressing 7 6 5 1 0 15 8 7 6 5 10 Effective Address 0 0 010 010 7 Memory Table 0 Low Addr Effective Address 1 High Addr PC User s Manual U12670EE3VOUD00 Chapter 3 CPU Architecture 3 3 4 Register addressing Register pair AX contents to be specified with an instruction word are transferred to the program coun ter PC and branched This function is carried out when the BR instruction is executed Figure 3 14 Register Addressing User s Manual U12670EE3VOUDOO 73 Chapter 3 CPU Architecture 3 4 Operand Address Addressing The followi
241. e SOF Figure 16 38 Global Time System Function INT Object n Other valid or Valid sync 4 Other valid or A invalid message message buffer 4 invalid message SOF SOF SOF A gt Edge for Edge for capture capture Enable Disable SOF SOF User s Manual U12670EE3VOUDOO 299 Chapter 16 CAN Coniroller 16 13 2 DCAN Error Status Register This register shows the status of the DCAN CANES has to be set with an 8 bit memory manipulation instruction RESET input sets CANES to 00H The RESET sets the INIT bit in CANC register therefore CANES will be read as 08H after RESET release Figure 16 39 CAN Error Status Register 1 3 Symbol 7 6 5 4 3 2 1 0 Address Reset R R R R R R W R W R W Remark BOFF RECS and INITSTATE are read only bits Caution Don t use bit operations on this SFR The VALID WAKE and OVER bits have a special behavior during CPU write operations Writing a 0 to them do not change them Writing an 1 clears the associated bit This avoids any timing conflicts between CPU access and internal activities An internal set condition of a bit overrides a CPU clear request at the same time BOFF Bus Off Flag 0 Transmission error counter x 255 1 Transmission error counter 255 BOFF is cleared after receiving 128 x 11 bits recessive state Bus idle or by issuing a hard DCAN reset with the TLRES bit in the MCNTn register Note An interrupt is generated when the B
242. e 3 1 Memory Map of the uPD780948 and Figure 3 2 Memory Map of the uPD78F0948 Note added in Figure 3 3 Data Memory Addressing of the PD780948 and Figure 3 4 Data Memory Addressing of the uPD78F0948 Chapter 3 CPU Architecture Modification of Figure 7 3 Capture Pulse Control Register CRC2 Format Modification of 7 5 16 bit Timer 2 Precautions Chapter 7 16 bit Timer 2 Modification of 8 5 Cautions on 8 bit Timer Event Counters 50 and 51 Chapter 8 8 bit Timer Event Counters 50 and 51 Modification of Figure 10 1 Watchdog Timer Block Diagram Chapter 10 Watchdog Timer Deletion of Chapter 13 Serial Interface Outline Revision of Chapter 16 CAN Controller Chapter 16 CAN Controller Figure 17 3 LCD Display Mode Register LCDM Format revised Chapter 17 LCD Controller Driver Table 23 4 Transmission Method List revised Modification of Figure 23 4 Connection of the Flash Programmer Using 3 Wire SIO30 Method Modification of Figure 23 5 Connection of the Flash Programmer Using UART Method Modification of Figure 23 6 Connection of the Flash Programmer Using Pseudo 3 Wire Serial I O Chapter 23 uPD78F0948 and Memory Definition Addition of Chapter 25 Electrical Specifications Modification of 25 4 Subsystem Clock Oscillator Circuit Characteristics Modification of 25 5 DC Characteristics Modification of 25 6 1 Basic Operation Modification of 25 6 4 A D
243. e Wave Output 162 8 Bit Timer Event Counters 50 51 163 8 Bit Timer Event Counters 50 Interval 175 8 Bit Timer Event Counters 51 Interval Times seen 175 8 Bit Timer Event Counters 50 Square Wave Output Ranges 8 Bit Timer Event Counter 222 40 1 00 0 eene nennen 178 8 Bit Timer Event Counters 51 Square Wave Output Ranges 8 Bit Timer Event Counter Mode ssssssssssseseeeeee eene nennen 178 Interval Timer Interval Time esses ener 9999 186 Watch Timer 186 Interval Timer nnne 189 Watchdog Timer Inadvertent Program Overrun Detection Times 191 Interval TIM OS c 192 Watchdog Timer 193 Watchdog Timer Overrun Detection 196 Interval Timer Interval 197 Clock Output Control Circuit Configuration 200 A D Converter Configuration enne nnne 204 Composition of SIOSO T aaa aa paa eaaa aa 220 List of SFRs Special Function
244. e differences among the uPD78F0948 and the mask ROM versions Table 23 1 Differences among uPD78F0948 and Mask ROM Versions 78 0948 Mask ROM Versions Available Vpp pin Available None Electrical characteristics Please refer to Chapter 25 Electrical Specifica tions on page 437 of this document Caution Flash memory versions and mask ROM versions differ in their noise tolerance and noise emission If replacing flash memory versions with mask ROM versions when changing from test production to mass production be sure to perform sufficient eval uation with CS versions not ES versions of mask ROM versions User s Manual U12670EE3VOUDOO 415 Chapter 23 078 0948 23 1 Memory Size Switching Register IMS This register specifies the internal memory size by using the memory size switching register IMS so that the same memory map as on the mask ROM version can be achieved IMS is set with an 8 bit memory manipulation instruction RESET input sets this register to the value indicated in Table 23 2 Figure 23 1 Memory Size Switching Register Format Symbol 7 2 1 0 Address After Reset R W Internal ROM size selection 32 K bytes 56 K bytes 60 K bytes Other than above Setting prohibited RAM2 RAM1 RAMO Internal high speed RAM size selection 1 1024 bytes Other than above Setting prohibited Note The values after reset depend on the produ
245. e e deae ee heme 284 Control bits for Receive Identifier 287 Receive Status Bits 1 2 esent enne 288 Receive Idertlfler inicie deem de aie 290 Receive Data cedo eet deed quid aec ede Dv 291 Identifier Compare with 2 4401 0 nennen nennen 293 Control Bits for Mask 2 294 MaSK fer ip 295 GAN Control Register 1 2 a ean ee eda dede ie 296 50 eeen asane etri teen ete Ud dads eta eode Ene pha fure eds 297 Time Stamp FUNGON i cu eder de lle eines 299 SOFOUT Toggle FUnctlon urere err hae 299 Global Time System Function 299 CAN Error Status Register 1 3 300 Transmit Error Gounter s nidis tede se eed Ine 303 Receive Error 303 Message Count Register MCNT 1 2 222004 0 0 0 000000 304 Bit Rate Prescaler 1 2 4 2 44424 1 nnne 306 Synchronization Control Registers 0 and 1 1 2 308 Transmit Control Register 12 312 Receive Message Register 314 Mask Control Register ssssssssssssseseseeenee enne eren neret nnn
246. e memory locations set the mask identifier definition of the DCAN MRECO to MREC4 can be set with a 1 bit or an 8 bit memory manipulation instruction RESET input sets MRECO to MREC4 to an undefined value Symbol MREC2 MREC3 MREC4 7 6 Figure 16 33 Mask Identifier 5 4 3 2 1 0 Address After Reset R W MRECO MID28 MID27 MID26 MID25 MID24 MID23 MID22 MID21 xxxeH MREC1 MID20 MID19 MID18 0 0 0 0 0 xxx3H MID17 MID9 MID1 MID16 MID8 MIDO MID15 MID14 MID13 MID12 MID11 MID10 MID6 MIDS MID4 MID3 MID2 xxx5H 0 0 0 0 0 0 Xxxx6H Mask Identifier Bit n 0 28 Check IDn bit in IDRECO through IDREC4 of received message 0 1 Receive message independent from IDn bit User s Manual U12670EE3VOUDOO undefined R W undefined R W undefined R W undefined R W undefined R W 295 Chapter 16 CAN Coniroller 16 13 Operation of the CAN Controller 16 13 1 CAN control register CANC The operational modes are controlled via the CAN control register CANC CANC can be set with a 1 bit or an 8 bit memory manipulation instruction RESET input sets CANC to 01H Figure 16 34 CAN Control Register 1 2 Symbol 7 6 5 lt 4 gt 3 lt 2 gt 1 lt 0 gt Address After Reset R W R W R W R W R W CANC 5 has always to be written as 0 INIT Request status for operational modes 0 Normal operation Initializa
247. e next frame ID compare is ongoing during six bits Message is not received and its data of next frame is lost Cannot get data for ID comparison 16 13 3 CAN Transmit Error Counter This register shows the transmit error counter TEC register can be read with an 8 bit memory manipulation instruction RESET input sets TEC to 00H Figure 16 40 Transmit Error Counter Symbol 7 6 5 4 3 2 1 0 Address iter Reset R R R R R R R R The transmit error counter reflects the status of the error counter for transmission errors as it is defined in the CAN protocol according ISO 11898 16 13 4 CAN Receive Error Counter This register shows the receive error counter REC can be read with an 8 bit memory manipulation instruction RESET input sets REC to 00H Figure 16 41 Receive Error Counter Symbol 7 6 5 4 3 2 1 0 Address iter Reset R R R R R R R R The receive error counter reflects the status of the error counter for reception errors as it is defined in the CAN protocol according ISO 11898 User s Manual U12670EE3VOUDOO 303 Chapter 16 CAN Coniroller 16 13 5 Message Count Register This register sets the number of receive message buffers and allocates the RAM area of the receive message buffers which are handled by the DCAN module MCNT can be read with an 8 bit memory manipulation instruction RESET input sets MCNT to COH Figure 16 42 Message Count Register MCNT 1 2 Symbol 7 6 5 4 3 2 1 0 Ad
248. e or analog input channel specification register ADS1 write upon the end of conversion ADM1 or ADS1 write is given priority ADCR1 write is not performed nor is the conversion end interrupt request signal INTAD generated User s Manual U12670EE3VOUDOO 215 Chapter 12 A D Converter 4 Noise counter measures To maintain 8 bit resolution attention must be paid to noise input to pin AVpp and pins ANIO to ANI7 Because the effect increases in proportion to the output impedance of the analog input source it is recommended that a capacitor be connected externally as shown in Figure 12 11 to reduce noise Figure 12 11 Analog Input Pin Handling If there is a possibility that noise equal to or higher than AVDD AVREF or equal to or lower than AVss may enter clamp with a diode with a small Vr value 0 3 V or lower Reference voltage O AVDD AVREF input A ANIO to ANI7 C 100 to 1000 pF A 7T AVss Vss 5 ANIO to ANI7 6 216 The analog input pins ANIO to ANI7 also function as input port pins P10 to P17 When A D conversion is performed with any of pins ANIO to ANI7 selected do not execute a port input instruction while conversion is in progress as this may reduce the conversion resolution Also if digital pulses are applied to a pin adjacent to the pin in the process of A D conversion the expected A D conversion value may not be obtainable due to coupling noise Therefore avoid applying pulses to pins a
249. e to stop the timer operation reset 02 and TMCO3 to 0 0 The valid edge of the 00 is selected by using the prescaler mode register 0 PRMO When a mode in which the timer is cleared and started on coincidence between TMO and 00 the OVFO flag is set to 1 when the count value of 0 changes from FFFFH to 0000H with CROO set to FFFFH output pin of 16 bit timer counter 0 input pin of 16 bit timer counter TMO 16 bit timer register compare register 00 compare register 01 User s Manual U15251EE3VOUDOO 125 Chapter6 16 Bit Timer Event Counter 0 2 Capture compare control register 0 CRCO This register controls the operation of the capture compare registers CROO and CRO1 is set by an 1 bit or an 8 bit memory manipulation instruction RESET input sets CRCO to 00H Figure 6 3 Format of Capture Compare Control Register 0 CRCO 7 6 5 4 3 2 1 0 RW Address ter Reset Selection of operation mode of CRO1 Operates as compare register 1 Operates as capture register Selection of capture trigger of CROO Captured at valid edge of TIO1 1 Captured in reverse phase of valid edge of 00 Selection of operation mode of 00 Operates as compare register 1 Operates as capture register Cautions 1 Before setting CRCO be sure to stop the timer operation 2 When the mode in which the timer is cleared and started on coincidence between
250. easures in their design such as redundancy fire containment and anti failure features NEC Electronics products are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to NEC Electronics products developed based on a customer designated quality assurance program for a specific application The recommended applications of NEC Electronics product depend on its quality grade as indicated below Customers must check the quality grade of each NEC Electronics product before using it in a particular application Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots Special Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems life support systems and medical equipment for life support etc The quality grade of NEC Electronics products is Standard unless otherwise expressly specified in NEC Electronics data sheets or data books etc If customers wish to use NEC Electronics products in applications not intended by NEC Electronics they mu
251. ecified by the prescaler mode register 0 PRMO has been input to the TIOO pin TMO is incremented When the count value of TMO coincides with the value of the 16 bit capture compare register 00 CROO TMO is cleared to 0 and an interrupt request signal INTTMOO is generated The edge of the TIOO pin is specified by bits 4 and 5 500 and ES01 of the prescaler mode register 0 PRMO The rising falling or both the rising and falling edges can be specified The valid edge is detected through sampling at a count clock cycle selected by the prescaler mode reg ister 0 PRMO and performed until the valid level is detected two times Therefore noise with a short pulse width can be rejected Figure 6 21 Control Register Settings in External Event Counter Mode a 16 bit timer mode control register TMCO TMCO3 02 01 OVFO Clears and starts on coincidence between TMO and CROO b Capture compare control register 0 CRCO CRC02 CRCO1 CRCOO ao e e Remark 0 1 When these bits are reset to 0 or set to 1 the other functions can be used along with the external event counter function For details refer to Figures 6 2 and 6 3 CROO as compare register User s Manual U15251EE3VOUDOO 141 6 16 Timer Event Counter 0 Figure 6 22 Configuration of External Event Counter 16 bit capture compare register 00 gt 00 Clea
252. ed to delay the next DATA FRAME or REMOTE FRAME OD Figure 16 15 Overload Frame 4 Overload frame EN Interframe space or overload frame Overload delimiter Overload flag superpositioning Node n Overload flag Node m Each frame Table 16 8 Definition of each Frame Bit Number Definition 1 Overload flag 6 Sent 6 bits dominant level continuously 2 Overload flag 0106 A node that receives an overload flag in the interframe space from any node Issues an overload flag Sends 8 bits recessive level continuously Overload ads 4 3 n 8 In case of monitoring dominant level at 8th bit an overload frame is delimiter transmitted after the next bit Output following the end of frame error delimiter and overload 4 Any frame bg delimiter 5 spacer 2 Interframe space or overload frame continues overload frame 20 MAX gt User s Manual U12670EE3VOUDOO 265 Chapter 16 CAN Coniroller 16 2 Function 16 2 1 Arbitration If two or more nodes happen to start transmission in coincidence the access conflict is solved by a bit wise arbitration mechanism during transmission of the ARBITRATION FIELD 1 3 When a node starts transmission During bus idle the node having the output data can transmit When more than one node starts transmission The node with the lower identifier wins the arbitration Any trans
253. ees 253 Outline of the Function A tin ae Bees 255 Bit Number of the nnnm 259 RTR SENG eieh icu e Eee dederit e a eee ee 259 aen 259 Data Length Code Setting 260 Operation in the Error State 0242 4 263 Definition of each Field nennen enne 264 Definition of each Frame 2244 nennen nnns 265 cL 266 Bite Stuttg efe tilt adeo iue 266 cuj H 268 Output Timing of the Error Frame 224 0 eene nnne ns 268 Types Ol DC 269 EE 270 Segment Name and Segment Length sse 271 retener 278 SER Definitions x uen te 279 SER Bit Befinitl ns on teer Pep re rte tr o pecu e an dee 279 Message and Buffer Configuration 280 Transmit Message 281 Receive Message 2 20222 286 Mask EUnctior aiite eiut een perti ete 292 Possible Setup of the SOFOUT 22 298 Transmission Reception
254. ehavior to the CAN bus User s Manual U12670EE3VOUDOO 311 Chapter 16 CAN Coniroller 16 15 Function Control 16 15 1 Transmit Control 1 Transmit control register This register controls the transmission of the DCAN module The transmit control register TCR provides complete control over the two transmit buffers and their status It is possible to request and abort transmission of both buffers independently TCR can be set with a an 8 bit memory manipulation instruction RESET input sets TCR to 00H Figure 16 45 Transmit Control Register 1 2 Symbol 7 6 5 4 3 2 1 0 Address After Reset TCR 0 TXC1 TXCO TXA1 TXAO TXRQ1 FFB1H 00H R W R R R R W R W R W R W Caution Don t use bit operations on this register Also logical operations read modify write via software may lead to unexpected transmissions Initiating a transmit request for buffer 1 while TXRQO is already set is simply achieved by writing 02H or 82H The status of the bits for buffer 0 is not affected by this write operation TXP Transmission Priority 0 Buffer 0 has priority over buffer 1 1 Buffer 1 has priority over buffer 0 The user defines which buffer has to be send first in the case of both request bits are set If only one buffer is requested by the TXRQn bits n 0 1 bits TXP bit has no influence TXCn n 0 1 shows the status of the first transmission It is updated when TXRQn n 0 1 is cleared TXAn Tr
255. elect register WDCS This register sets the watchdog timer count clock WDCS is set with 8 bit memory manipulation instruction RESET input sets WDCS to 00H Figure 10 2 Timer Clock Select Register 2 Format After 7 6 5 4 3 2 1 0 R W Address Reset Overflow Time of Watchdog Timer fx 21 512 us f 21 1 ms 1 214 2 ms f 21 4 ms 1 216 8 19 ms fx 217 16 38 ms fx 218 32 76 ms 220 131 ms Caution When rewriting WDCS to other data stop the timer operation beforehand Remarks 1 fy Main system clock oscillation frequency 2 Figures in parentheses apply to operation with fy 8 0 MHz 194 User s Manual U12670EE3VOUDOO Chapter 10 Watchdog Timer 2 Watchdog timer mode register WDTM This register sets the watchdog timer operating mode and enables disables counting WDTM is set with an 1 bit or an 8 bit memory manipulation instruction RESET input sets WDTM to 00H Figure 10 3 Watchdog Timer Mode Register Format 6 4 3 2 1 0 Address After Reset Watchdog Timer Operation Mode Selection Note 1 Interval timer mode Maskable interrupt occurs upon generation of an overflow Watchdog timer mode 1 Non maskable interrupt occurs upon generation of an overflow Watchdog timer mode 2 Reset operation is activated upon generation of an overflow Watchdog Timer Operation Mode Selection Note 2 Count stop Counter is cleare
256. els of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected to Voo or GND with a resistor if it is considered to have a possibility of being an output pin All handling related to the unused pins must be judged device by device and related specifications governing the devices STATUS BEFORE INITIALIZATION OF MOS DEVICES Note Power on does not necessarily define initial status of MOS device Production process of MOS does not define the initial operation status of the device Immediately after the power source is turned ON the devices with reset function have not yet been initialized Hence power on does not guarantee out pin levels I O settings or contents of registers Device is not initialized until the reset signal is received Reset operation must be executed immediately after power on for devices having reset function 2 User s Manual U12670EE3VOUDOO The information in this document is current as of 24 04 2003 The information is subject to change without notice For actual design in refer to the latest publications of NEC Electronics data sheets or data books etc for the most up to date specifications of NEC Electronics products Not all products and or types are available in every country Please check with an NEC sales representative for availability and additional information No part of this document may be copied or reproduced in any form or by any means
257. ely after system reset and rising edge or both the rising and falling edges are specified as the valid edge for the TIOO pin or TIO1 pin to enable the 16 bit timer counter 0 TMO operation a rising edge is detected immediately after Be careful when pulling up the TIOO pin of the TIO1 pin However the rising edge is not detected at restart after the operation has been stopped once User s Manual U15251EE3VOUDOO Chapter 7 16 Bit Timer 2 7 1 16 Bit Timer 2 Functions The 16 bit timer 2 TM2 has the following functions Pulse width measurement Divided output of input pulse Time stamp function for the Figure 7 1 shows 16 Bit Timer 2 Block Diagram Figure 7 1 Timer 2 TM2 Block Diagram 5 Internal bus Prescaler mode Capture pulse control register PRM2 register CRC2 521 520 ES11 ES10 501 16 bit timer mode control register TMC2 4 fx 8 fx 32 fx 128 INTOVF 16 bit timer register TM2 Selector BE ES20 Prescaler Edge detection 1 12 14 1 8 circuit Noise rejection TI22 P32 circuit 16 bit capture register CR22 ES11 ES10 INTTM22 Noise rejection Edge detection hi i TI21 P31 16 bit capture register CR21 501 500 INTTM21 ister CR20 16 bit capture reg y circuit TPO PO3 INTP3 e TPOE Internal bus 5 Edge detection
258. em clock starts oscillation At this time oscillation stabilization time 2 7 fy is secured automatically After that the CPU starts executing the instruction at the minimum speed of the main system clock 4 us when operated at 8 0 MHz After the lapse of a sufficient time for the Vpp voltage to increase to enable operation at maximum speeds the processor clock control register PCC is rewritten and the maximum speed operation is carried out Upon detection of a decrease of the Vpp voltage due to an interrupt request signal the main sys tem clock is switched to the subsystem clock which must be in an oscillation stable state Upon detection of Vpp voltage reset due to an interrupt request signal 0 is set to bit 7 MCC of PCC and oscillation of the main system clock is started After the lapse of time required for stabili zation of oscillation the PCC is rewritten and the maximum speed operation is resumed Caution When subsystem clock is being operated while main system clock was stopped if 118 switching to the main system clock is made again be sure to switch after securing oscillation stable time by software User s Manual U12670EE3VOUD00 Chapter 6 16 Bit Timer Event Counter 0 6 1 16 bit Timer Event Counter 0 Function 16 bit timer event counter 0 0 has the following functions 1 2 3 4 5 Interval timer PPG output Pulse width measurement External event counter S
259. en the abort request is recognized during frame transmission and the transmission ends with an error afterwards the TXCn bit n 0 1 is reset showing that the buffer was not send to other nodes g When the abort request is recognized during the frame transmission and transmission ends with out error The TXCn bit n 0 1 is set showing a successful transfer of the data l e the abort request was not issued In all cases the TXRQn bit and the TXAn bit n 0 1 bit will be cleared at the end of the abort tion when the transmit buffer is available again Cautions 1 The bits are cleared when the INIT bit in CANC register is set 2 Writing a 0 to TXAn n 0 1 bit has no influence 3 Do not perform read modify write operations on TCR The bit n 0 1 are updated at the end of every frame transmission or abort TXRQn Transmission Request Flag Write no influence Read transmit buffer is free Write request transmission for buffer n Read transmit buffer is occupied by former transmit request The transmit request bits are checked by the DCAN immediately before the frame is started The order in which the TXRQn bit n 0 1 will be set does not matter as long as the first requested frame is not started on the bus The TXRQn bit n 0 1 have dual function 1 Request the transmission of a transmit buffer 2 Inform the CPU whether a buffer is available or if it is still
260. er register RXBO RXSO cannot be manipulated directly by a program 3 Receive buffer register RXBO This register is used to hold receive data When one byte of data is received one byte of new receive data is transferred from the receive shift register RXSO When the data length is set as 7 bits receive data is sent to bits 0 to 6 of RXBO The MSB must be set to 0 in RXBO RXBO can be read to via 8 bit memory manipulation instructions It cannot be written to When RESET is input its value is FFH Caution The same address is assigned to RXBO and the transmit shift register TXSO During a write operation values are written to TXSO 234 User s Manual U12670EE3VOUDOO Chapter 15 Serial Interface UART 4 Transmission control circuit The transmission control circuit controls transmit operations such as adding a start bit parity bit and stop bit to data that is written to the transmit shift register 50 based on the values set to the asynchronous serial interface mode register ASIMO 5 Reception control circuit The reception control circuit controls the receive operations based on the values set to the asyn chronous serial interface mode register ASIMO During a receive operation it performs error checking such as parity errors and sets various values to the asynchronous serial interface sta tus register ASISO according to the type of error that is detected 15 3 List of SFRS Special Function Regi
261. eration 9 a Even if the 16 bit timer counter 0 is read the value is not captured by 16 bit timer cap ture compare register 01 CRO1 b Regardless of the CPU s operation mode when the timer stops the input signals to pins TIOO TIO1 are not acknowledged Capture operation a If TIOO is specified as the valid edge of the count clock capture operation by the capture regis ter specified as the trigger for TIOO is not possible b If both the rising and falling edges are selected as the valid edges of 00 capture is not per formed c To ensure the reliability of the capture operation the capture trigger requires a pulse two times longer than the count clock selected by prescaler mode register 0 d The capture operation is performed at the fall of the count clock An interrupt request input INTTMOn however is generated at the rise of the next count clock 10 Compare operation a The INTTMOn may not be generated if the set value of 16 bit timer capture registers 00 01 CROO CRO1 and the count value of 16 bit timer counter match CROO and CRO1 are overwritten at the timing of INTTMOn generation Therefore do not overwrite CROO and 01 frequently even if overwriting the same value b Capture operation may not be performed for CROO CRO1 set in compare mode even if a cap ture trigger has been input 11 Edge detection 148 If the TIO1 pin is high level immediat
262. eration was completed before data was read from receive buffer register Notes 1 Even if a stop bit length of two bits has been set to bit 2 SLO in the asynchronous serial interface mode register ASIMO the stop bit detection during a receive operation only applies to a stop bit length of 1 bit 2 Be sure to read the contents of the receive buffer register RXBO when an overrun error has occurred Until the contents of RXBO are read further overrun errors will occur when receiving data 238 User s Manual U12670EE3VOUD00 Chapter 15 Serial Interface UART 3 Baud rate generator control register BRGCO This register sets the serial clock for UART BRGCO can be set via an 8 bit memory manipulation instruction When RESET is input its value is OOH Figure 15 4 shows the format of BRGCO Figure 15 4 Format of Baud Rate Generator Control Register BRGCO 1 2 After Reset sRaco 9 TPS02 TPSOO MDL MD FFAZH fx 8 00 MHz 7 6 5 4 3 2 1 0 R W_ Address Source clock selection for 5 bit counter User s Manual U12670EE3VOUDOO 239 Chapter 15 Serial Interface UART Figure 15 4 Format of Baud Rate Generator Control Register BRGCO 2 2 MDLO3 MDLO2 MDLO1 MDLOO Input clock selection for baud rate generator fecil 22 fgcK 23 fscK 24 fgcK 25 26 27 28 29
263. errupt Request Sources Interrupt Request Interrupt Request Interrupt Mask Priority Specify Signal Name Flag Flag Flag INTPO PIFO PMKO PPRO INTP1 PIF1 PMK1 PPR1 INTP2 PIF2 PMK2 PPR2 INTP3 PIF3 PMK3 PPR3 INTP4 PIF4 PMK4 PPR3 00 TMIFOO TMMKOO TMPROO INTTMO1 TMIFO1 TMMKO01 TMPRO1 INTOVF OVFIF OVFMK OVFPR INTTM20 TMIF20 TMMK20 TMPR20 INTTM21 TMIF21 21 TMPR21 INTTM22 TMIF22 TMMK22 TMPR22 50 TMIF50 TMMK50 TMPR50 INTM51 TMIF51 TMMK51 TMPR51 INTWTI WTIIF WTIMK WTIPR INTWT WTIF WTMK WTPR INTWDT WDTIF WDTMK WDTPR INTAD ADIF ADMK ADPR INTCSIO CSIIFO CSIMKO CSIPRO INTCSI1 CSIIF1 CSIMK1 CSIPR1 INTSER SERIF SERMK SERPR INTSR SRIF SRMK SRPR INTST STIF STMK STPR INTCE CEIF CEMK CEPR INTCR RRF CRMK CRPR INTCTO CTIFO CTMKO CTPRO INTCT1 CTIF1 CTMK1 CTPR1 User s Manual U12670EE3VOUDOO 371 Chapter 19 Interrupt Functions 1 Interrupt request flag registers IFOL IFOH IF1L IF1H The interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction is executed It is cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of RESET input IFOL IFOH IF1L and IF1H are set with an 1 bit or 8 bit memory manipulation instruction If IFOL and IFOH are used as a 16 bit register IFO use a 16 bit memory manipulation instruction for the setting RESET in
264. ers Inches A 23 6 0 4 0 929 0 016 B 20 0 0 2 0 79510 009 14 0 0 2 0 551 2 009 D 17 6 0 4 0 693 0 016 0 8 0 031 G 0 6 0 024 H 0 30 0 10 0 01270004 0 15 0 006 0 65 0 026 K 1 8 0 2 0 071 0 008 L 0 8 0 2 0 031 2 009 M 0 1519 0 0069 0 10 0 004 2 7 0 106 Q 0 10 1 0 004 0 004 5 3 0 0 119 User s Manual U12670EE3VOUDOO 487 MEMO 488 User s Manual U12670EE3VOUDOO Chapter 27 Recommended Soldering Conditions The puPD78F0948 should be soldered and mounted under the conditions in the table below For detail of recommended soldering conditions refer to the information document Semiconductor Device Mounting Technology Manual 1207 For soldering methods and conditions other than those recommended below consult our sales personnel uPD780948GF A XXX 3BA 100 pin plastic 14 x 20 mm pPD780948GF A1 XXX 3BA 100 pin plastic QFP 14 x 20 mm pPD78F0948GF 3BA 100 pin plastic QFP 14 x 20 mm Table 27 1 Surface Mounting Type Soldering Conditions Recommended Soldering Method Soldering conditions Condition Symbol Package peak temperature 235 C Duration 30 sec max at 210 C or above Number of times twice max lt Precautions gt reflow 1 The second reflow should be started after the first reflow device R390973 temperature has returned to the ordinary state 2 Flux washing must not be performed by the use of water af
265. ersion operation Enable conversion operation FR12 11 FR10 Conversion Time Selection Note 144 fy 120 fy 96 fy 72 60 fy 1 48 fx Other than above Setting prohibited Note Set so that the A D conversion time is 15 us or more Caution Bits 0 to 2 and bit 6 must be set to 0 Remark Main system clock oscillation frequency 206 User s Manual U12670EESVOUDOO Chapter 12 A D Converter 2 Analog input channel specification register ADS1 This register specifies the analog voltage input port for A D conversion ADS1 is set with an 8 bit memory manipulation instruction RESET input clears ADS1 to 00H Figure 12 4 Analog Input Channel Specification Register ADS1 Format 7 6 5 4 3 2 1 0 Address Alter Reset Analog Input Channel Specification ANIO ANH ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 Other than above Setting prohibited Caution Bits 3 to 7 must be set to 0 User s Manual U12670EE3VOUDOO 207 Chapter 12 A D Converter 3 Power fail compare mode register PFM The power fail compare mode register PFM controls a comparison operation PFM is set with an 1 bit or an 8 bit memory manipulation instruction RESET input clears PFM to OOH Figure 12 5 Power Fail Compare Mode Register PFM Format 7 6 5 4 3 2 1 0 RW Address ter Reset PFEN Enables Power Fail Comparison 0 Disables power fail comparison used as normal A
266. est Conditions Cycle time Note 1 4 0 V lt Vpp 5 5 V 0 TI51 input frequency 0 TI51 input high low level width TI20 TI21 TI22 input high low level width TIOO TIO1 input high low level width Interrupt input high low level width INTPO INTP4 RESET low level width Notes 1 The cycle time equals to the minimum instruction execution time For example 1 NOP instruction corresponds to 2 CPU clock cycles selected by the processor clock control register PCC 2 fsmp2 sampling clock fy 4 1 8 1 32 fy 128 3 sampling clock fy 2 fy 16 1 128 Selection of fy 2 5 16 fy 128 is possible using bits 0 and 1 PRMOO 01 of prescaler mode register PRMO However if the TIOO valid edge is selected as the count clock the value becomes fgypo fy 2 460 User s Manual U12670EE3VOUDOO Cycle time Tcv us Chapter 25 Electrical Specifications Toy vs Vpp Operation guaranteed range i AZ A 1 2 3 4 5 6 Supply voltage Voo V User s Manual U12670EE3VOUDOO 461 Chapter 25 Electrical Specifications 2 pPD780948 A1 40 C to 110 C 4 0 to 5 5 V Parameter Test Conditions Cycle time Note 1 4 0 V lt Vpp lt 5 5V 0 TI51 input frequency 0 1 input high low leve
267. esult register ADCR1 When a write operation is executed to A D converter mode register ADM1 and analog input channel specification register ADS1 the contents of ADCR1 are undefined Read the conversion result before write operation is executed to ADM1 ADS1 If a timing other than the above is used the correct conversion result may not be read User s Manual U12670EE3VOUDOO 217 Chapter 12 A D Converter 12 6 Cautions on Emulation To perform debugging with an in circuit emulator the D A converter mode register DAMO must be set DAMO is a register used to set the emulation board 12 6 1 D A converter mode register DAMO DAMO is necessary if the power fail detection function is used Unless DAMO is set the power fail detection function cannot be used DAMO is a write only register Because the IE 78K0 NS P04 uses an external analog comparator and a D A converter to implement part of the power fail detection function the reference voltage must be controlled Therefore set bit 0 DACE of DAMO to 1 when using the power fail detection function Figure 12 13 D A Converter Mode Register DAMO Format 7 6 5 4 3 2 1 0 RW Address After Reset DACE Reference Voltage Control 0 Disabled 1 Enabled when power fail detection function is used Cautions 1 DAMO is a special register that must be set when debugging is performed with an In Circuit Emulator Even if this register is used the operation of the PD780948 Subserie
268. etection Sleep mode Wake up from CAN bus POWER GOWN Moges Stop mode No wake up from CAN bus User s Manual U12670EE3VOUDOO 255 Chapter 16 CAN Coniroller 16 1 CAN Protocol CAN is an abbreviation of Controller Area Network and is a class C high speed multiplexed communi cation protocol CAN is specified by Bosch in the CAN specification 2 0 from September 1991 and is standardized in ISO 11898 International Organization for Standardization and SAE Society of Auto motive Engineers 16 1 1 Protocol Mode Function 1 Standard format mode This mode supports an 11 bit message identifier thus making it possible to differentiate between 2048 types of messages 2 Extended format mode Inthe extended format mode the identifier has 29 bits It is built by the standard identifier 11 bits and an extended identifier 18 bits When the IDE bits of the arbitration field is recessive the frame is sent in the extended format mode When a message in extended format mode and a remote frame in standard format mode are simultaneously transmitted the node transmitting the message with the standard mode wins the arbitration 3 Bus values The bus can have one of two complementary logical values dominant or recessive During simultaneous transmission of dominant and recessive bits the resulting bus value will be dominant non destructive arbitration For example in case of a wired AND i
269. event counter 5 timer output enabling disabling TMC50 is set with an 1 bit or an 8 bit memory manipulation instruction RESET input sets TMC50 to OOH Figure 8 6 8 Bit Timer Mode Control Register 50 Format lt 7 gt 6 5 4 lt 3 gt lt 2 gt 1 0s Address Reset TOE50 8 Bit Timer Event Counter 50 Output Control Output disabled Port mode Output enabled In PWM Mode In Other Mode Active level selection Timer output F F1 control 501 Active high Inversion operation disabled Active low Inversion operation enabled 8 Bit Timer Event Counter 50 Timer Output F F1 Status Setting No change Timer output F F1 reset 0 Timer output F F1 set 1 Setting prohibited TMC506 8 Bit Timer Event Counter 50 Operating Mode Selection Clear amp start mode on match of TM50 and CR50 PWM mode free running TCE50 8 Bit Timer Register 50 Operation Control Operation Stop TM50 clear to 0 Operation Enable Cautions 1 Timer operation must be stopped before setting TMC50 2 If LVS50 and 50 are read after data set they will be 0 3 Be sure to set bit 4 and bit 5 to 0 168 User s Manual U12670EE3VOUD00 Chapter 8 8 Bit Timer Event Counters 50 and 51 4 8 bit timer mode control register 51 TMC51 This register enables stops operation of 8 bit timer register 51 sets the operating mode of 8 bit timer register 51 and controls operation of 8 bit timer even
270. f Serial Operation Mode Register 30 5 0 222 Format of Serial Operation Mode Register 51 0 223 Timing of Three wire Serial l O 224 Block Diagram of 51031 Macro ssssssssssssseeeeeeeeeeen enne 225 Format of Serial Operation Mode Register 51 31 227 Format of Serial Operation Mode Register 31 51 31 228 Format of Serial Operation Mode Register 31 51 31 229 Timing of Three wire Serial l O 230 2 Wire Mode 231 Block Diagram of tee eene ln needa e eee d 233 Format of Asynchronous Serial Interface Mode Register ASIMO 1 2 236 Format of Asynchronous Serial Interface Status Register ASISO 238 Format of Baud Rate Generator Control Register BRGCO 1 2 239 Register Settings caede Deere tio er de Ede d Eg le eda 241 Format of Asynchronous Serial Interface Mode Register ASIMO 1 2 242 Format of Asynchronous Serial Interface Status Register ASISO 244 Format of Baud Rate Generator Control Register BRGCO 1 2 245 Error Tolerance when k 0 includin
271. f the asynchronous serial interface mode register ASIMO is set 1 and input data via pin is sampled The serial clock specified by ASIMO is used when sampling the RXD pin When the RXD pin goes low the 5 bit counter begins counting the start timing signal for data sampling is output if half of the specified baud rate time has elapsed If the sampling of the RXDO pin input of this start timing signal yields a low level result a start bit is recognized after which the 5 bit counter is initialized and starts counting and data sampling begins After the start bit is recog nized the character data parity bit and one bit stop bit are detected at which point reception of one data frame is completed Once the reception of one data frame is completed the receive data in the shift register is trans ferred to the receive buffer register RXBO and a receive completion interrupt INTSRO occurs Even if an error has occurred the receive data in which the error occurred is still transferred to RXBO and INTSRO occurs see Figure Figure 15 9 Error Tolerance when k 0 including Sam pling Errors on page 248 If the RXEO bit is reset to O during a receive operation the receive operation is stopped imme diately At this time neither the contents of RXBO and ASISO will change nor does INTSR or INTSER occur Figure 15 12 shows the timing of the asynchronous serial interface receive completion interrupt Figure 15 12 Timin
272. face Control Registers 236 15 5 Serial Interface 241 15 5 1 Operation stop mode 241 15 5 2 Asynchronous serial interface UART 242 15 6 Standby 254 Chapter 16 CAN Controller 2 3 0 2 2 oes ec RR 255 16 1 CAN Protocol uei nel LI 4m V es ELI 256 16 1 1 Protocol Mode Function 256 16 1 2 Message 256 16 1 3 Data Frame Remote 257 16 1 4 Description of each 0 258 16 1 5 Error Frame oe RE XD T oy op Seon doe Ue Sos 264 16 1 6 Overload Frame esee x ette RR tC De xe EC CTS 265 16 2 FUl Con seh TAP PNIS DLE IU a E ERE 266 16 2 1 AIDItE allons dete rer eh des Deu es Auten Toni 266 16 22 Bit Stuffinig oat yon e ERR SA ePi EI 266 16 2 3 Multis Mast tee ttre Ge Sach rete tate RD Ute eae Sae 267 16 2 4 Multi Cast zu a tenes Reed wa eles weet ale 267 16 2 5 Sleep Mode Stop 267 16 2 6 Error
273. fore data was read from the receive buffer Overrun error register Figure 15 13 Receive Error Timing Rx00 START oe X or STOP INTSRO INTSERO INTSERO When parity error occurs Cautions 1 The contents of ASISO are reset to 0 when the receive buffer register RXBO is read or when the next data is received To obtain information about the error be sure to read the contents of ASISO before reading RXBO 2 Be sure to read the contents of the receive buffer register RXBO even when a receive error has occurred Overrun errors will occur during the next data receive operations and the receive error status will remain until the contents of RXBO are read User s Manual U12670EE3VOUDOO 253 Chapter 15 Serial Interface UART 15 6 Standby Function Serial transfer operations can be performed during HALT mode During STOP mode serial transfer operations are stopped and the values in the asynchronous serial interface mode register ASIMO the transmit shift register 50 the receive shift register RXSO and the receive buffer register RXBO remain as they were just before the clock was stopped Output from the TXD pin retains the immediately previous data if the clock is stopped if the system enters STOP mode during a transmit operation If the clock is stopped during a receive operation the data received before the clock was stopped is retained a
274. function pins are the same as those of the port pins unless otherwise specified 454 User s Manual U12670EE3VOUDOO Chapter 25 Electrical Specifications 780948 1 Parameter Conditions 8 0 MHz crystal oscillation operating mode PCC 2 8 0 MHz crystal oscillation operating mode PCC 00H Note 3 8 0 MHz crystal oscillation Power supply Note 1 HALT mode PCC 04H Nete 4 current RC oscillation operating mode fr 40 KHz RC oscillation HALT mode fr 40 KHz CL1 Vpp STOP mode Notes 1 Current through Vppo respectively through Vsso Vss1 Excluded is the current through the inside pull up resistors through AVpp AVggg the port current 2 CPU is operable The other peripherals like CAN controller Timer 0 Timer 2 serial interfaces A D converter etc are stopped 3 CPU and all peripherals except for the A D converter are in operating mode and PCL out put is fy 4 CPU is in HALT mode and all other peripherals except Watch timer are stopped Remarks 1 fy Main system clock oscillation frequency 2 fxr Subsystem clock oscillation frequency 3 The typical values are with respect to Ta 25 C 780948 1 LCD C D Static Method Parameter Conditions LCD drive voltage LCD split resistor LCD output voltage 3 0 V Vicp Vpp deviation Note common Vicbo Vicp LCD output voltage deviation Note se
275. g Sampling 248 Format of Transmit Receive Data in Asynchronous Serial Interface 249 Timing of Asynchronous Serial Interface Transmit Completion Interrupt 251 Timing of Asynchronous Serial Interface Receive Completion Interrupt 252 Receive Error Timing iare iratra caedere tte tle cH quede erede 253 HAAF ANE a entier euch tur diede od eee dts 257 Remote Frame cedere Ret need Je oe en Dee ene 257 6 tt 258 Arbitration Field Standard Format 258 User s Manual U12670EE3VOUDOO 19 Figure 16 5 Figure 16 6 Figure 16 7 Figure 16 8 Figure 16 9 Figure 16 10 Figure 16 11 Figure 16 12 Figure 16 13 Figure 16 14 Figure 16 15 Figure 16 16 Figure 16 17 Figure 16 18 Figure 16 19 Figure 16 20 Figure 16 21 Figure 16 22 Figure 16 23 Figure 16 24 Figure 16 25 Figure 16 26 Figure 16 27 Figure 16 28 Figure 16 29 Figure 16 30 Figure 16 31 Figure 16 32 Figure 16 33 Figure 16 34 Figure 16 35 Figure 16 36 Figure 16 37 Figure 16 38 Figure 16 39 Figure 16 40 Figure 16 41 Figure 16 42 Figure 16 43 Figure 16 44 Figure 16 45 Figure 16 46 Figure 16 47 Figure 16 48 Figure 16 49 Figure 16 50 Figure 16 51 Figure 16 52 Figure 16 53 Figure 16 54 Figu
276. g of Asynchronous Serial Interface Receive Completion Interrupt INTSR Caution Be sure to read the contents of the receive buffer register RXBO even when a 252 receive error has occurred Overrun errors will occur during the next data receive operations and the receive error status will remain until the contents of RXBO are read User s Manual U12670EE3VOUD00 Chapter 15 Serial Interface UART e Receive errors Three types of errors can occur during a receive operation parity error framing error or overrun error If as the result of the data reception an error flag is set to the asynchronous serial interface status register ASISO a receive error interrupt INTSERO will occur Receive error interrupts are generated before receive interrupts INTSRO Table 15 5 lists the causes of receive errors As part of the receive error interrupt INTSERO servicing the contents of ASISO can be read to determine which type of error occurred during the receive operation see Table 15 5 and Figure 15 13 The content of ASISO is reset to 0 if the receive buffer register RXBO is read or when the next data is received if the next data contains an error another error flag will be set Table 15 5 Causes of Receive Errors Receive error Parity error Parity specified during transmission does not match parity of receive data Framing error Stop bit was not detected Reception of the next data was completed be
277. ganized according to usage The names in the parallelograms are subseries Figure 1 2 78K 0 Series Expansion ae Products in mass production Products under development Y subseries products are compatible with bus Control uPD78075B EMI noise reduced version of the uPD78078 100 pin uPD78078 uPD78078Y A PD78054 with timer and enhanced external interface 100 pin LPD78070A 78070 ROMless version of the uPD78078 100 pin uPD780018AY 4 PD78078Y with enhanced serial I O and limited function uPD780058 100 pin 80 pin uPD780058Y uPD78054 with enhanced serial I O 80 pin HPD780024A with expanded RAM 64 pin uPD780034A with timer and enhanced serial I O 64 pin 780024 with enhanced A D converter 64 pin u PD78018F with enhanced serial I O 42 44 pin On chip UART capable of operating at low voltage 1 8 V Inverter control 64 pin uPD780988 On chip inverter control circuit and UART EMI noise reduced VFD drive 100 78044 with enhanced I O and VFD C D Display output total 53 faite 80 pin For panel control On chip VFD C D Display output total 53 80 pin 78044 with N ch open drain I O Display output total 34 80 pin Basic subseries for driving VFD Display output total 34 LCD drive B 120 pin PD780308 with enhanced display function and timer Segment signal output 40 pins max 120 pin PD780308 with enhanced display functio
278. ge is performed by setting of the prescaler mode register PRM2 When the valid edge of the TI20 is detected an interrupt request INTTM20 is generated CR20 is read by a 16 bit memory manipulation instruction After RESET input the value of CR20 is undefined 150 User s Manual U12670EE3VOUD00 Chapter 7 16 Bit Timer 2 3 Capture register 21 CR21 The valid edge of the 21 can be selected as the capture trigger Setting of the 21 valid edge is performed by setting of the prescaler mode register PRM2 When the valid edge of the 21 is detected an interrupt request INTTM21 is generated CR21 is read by a 16 bit memory manipulation instruction After RESET input the value of CR21 is undefined 4 Capture register 22 CR22 The valid edge of the 22 pin can be selected as the capture trigger Setting of the 22 valid edge is performed by setting of the prescaler mode register PRM2 When the valid edge of the TI22 is detected an interrupt request 22 is generated CR22 is read by a 16 bit memory manipulation instruction After RESET input the value of CR22 is undefined User s Manual U12670EE3VOUDOO 151 Chapter 7 16 Bit Timer 2 7 3 16 Bit Timer 2 Control Registers The following three types of registers are used to control timer 0 e 16 bit timer mode control register TMC2 Capture pulse control register CRC2 Prescaler mode register PRM2 1 16 bit timer mode control reg
279. generated during execution of a non maskable interrupt servic ing program is acknowledged after the current execution of the non maskable interrupt servicing pro gram is terminated following RETI instruction execution and one main routine instruction is executed If a new non maskable interrupt request is generated twice or more during a non maskable interrupt service program execution only one non maskable interrupt request is acknowledged after termination of the non maskable interrupt service program execution Figure 19 7 Flowchart from Non Maskable Interrupt Generation to Acknowledge WDTM4 1 with watchdog timer mode selected Interval timer Yes Overflow in WDT No WDTM3 0 with non maskable interrupt selected Reset processing Interrupt request generation WDT interrupt servicing Interrupt request held pending Interrupt control register unaccessed Yes Interrupt service start Remark WDTM Watchdog timer mode register WDT Watchdog timer User s Manual U12670EE3VOUDOO 377 Chapter 19 Interrupt Functions Figure 19 8 Non Maskable Interrupt Request Acknowledge Timing 7 PSW and PC Save Jump Interrupt Sevicing to Servicihg Program Remark WDTIF Watchdog timer interrupt request flag Figure 19 9 Non Maskable Interrupt Request Acknowledge Operation a If a new non maskable interrupt request is generated during
280. gment lo 1 pA Note The voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment common outputs Vi cpw 0 1 2 Caution The LCD C D cannot be used at high temperature 110 C The maximum temperature is T4 85 C User s Manual U12670EE3VOUDOO 455 Chapter 25 Electrical Specifications 0780948 1 LCD C D 1 2 Bias Method Parameter Conditions LCD drive voltage LCD split resistor LCD output voltage Vicpo Vicp deviation Nee common Vicp1 1 2 Vicp2 Vicp x 1 2 LCD output voltage lo t1 pA deviation Note segment 9 Note The voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs Vi cpw 0 1 2 Caution The LCD C D cannot be used at high temperature T4 110 C The maximum temperature is T4 85 C pPD780948 A1 LCD C D 1 3 Bias Method Parameter Conditions LCD drive voltage LCD split resistor LCD output voltage Vicpo Vicp deviation Nee common Vicp1 2 8 Vicpe Vicp X 1 3 LCD output voltage lo t1 pA deviation Note segment 9 D Note The voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs Vi cpw 0 1 2 Caution The LCD C D
281. he A D conversion ends the con version result is loaded from the successive approximation register ADCR1 is read with 8 bit memory manipulation instruction RESET input clears ADCR1 to 00H Caution If a write operation is executed to the A D converter mode register ADM1 and the 3 4 5 6 analog input channel specification register ADS1 the contents of ADCR1 are unde fined Read the conversion result before a write operation is executed to ADM1 and ADS1 If a timing other than the above is used the correct conversion result may not be read Sample amp hold circuit The sample amp hold circuit samples each analog input sequential applied from the input circuit and sends it to the voltage comparator This circuit holds the sampled analog input voltage value dur ing A D conversion Voltage comparator The voltage comparator compares the analog input to the series resistor string output voltage Series resistor string The series resistor string is in AVpp AVngr to AVss and generates a voltage to be compared to the analog input ANIO to ANI7 pins These are eight analog input pins to feed analog signals to the A D converter ANIO to ANI7 are alternate function pins that can also be used for digital input Caution Use ANIO to ANI7 input voltages within the specified range If a voltage higher than 7 8 AVpp or lower than is applied even if within the absolute maximum rating range
282. he symbol reserved with assembler for the 1 bit manipulation instruction operand sfr bit This manipulation can also be specified with an address 8 bit manipulation Describe the symbol reserved with assembler for the 8 bit manipulation instruction operand sfr This manipulation can also be specified with an address 16 bit manipulation Describe the symbol reserved with assembler for the 16 bit manipulation instruction operand sfrp When addressing an address describe an even address Table 3 8 Special Function Register List on page 67 gives a list of special function registers The meaning of items in the table is as follows Symbol The assembler software RA78KO translates these symbols into corresponding addresses where the special function registers are allocated These symbols should be used as instruction operands in the case of programming R W This column shows whether the corresponding special function register can be read or written R W Both reading and writing are enabled R The value in the register can read out A write to this register is ignored W A value can be written to the register Reading values from the register is impossible Manipulation The register can be manipulated in bit units After reset The register is set to the value immediately after the RESET signal is input User s Manual U12670EE3VOUD00 Address Chapter 3 CPU Architecture Table 3 3 Special Function Register Lis
283. herefore on a port with a mixture of input and output pins the output latch contents for pins specified as input are undefined even for bits other than the manipulated bit 104 User s Manual U12670EE3VOUDOO Chapter 5 Clock Generator 5 1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware The following type of system clock oscillators is available 1 Main system clock oscillator This circuit oscillates at frequencies of 4 to 8 38 MHz Oscillation can be stopped by executing the STOP instruction or setting the processor clock control register 2 Subsystem clock oscillator The circuit oscillates at typical frequency of 40 KHz Oscillation cannot be stopped User s Manual U12670EE3VOUDOO 105 Chapter 5 Clock Generator 5 2 Clock Generator Configuration The clock generator consists of the following hardware Table 5 1 Clock Generator Configuration Configuration Control register Processor clock control register PCC Main system clock oscillator Oscillator Subsystem clock oscillator Figure 5 1 Block Diagram of Clock Generator Subsystem fxr Clock T Watch Timer Cl2 Oscillator ree Xio 2 Clock to fx ES Peripheral X2 Prescaler fxr Hardware 2 Standby CPU Clock Control Circuit Selector fceu STOP emm ProcessorClock ControlRegister
284. herefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded Remark characteristics of the dual function pins are the same as those of the port pins unless otherwise specified 438 User s Manual U12670EE3VOUDOO Chapter 25 Electrical Specifications 3 pPD78F0948 25 C Parameter Conditions 0 3 to 6 0 0 3 to 11 0 Supply voltage PRY 4 AVpp AVngr Vpp 0 3 to 4 0 3 0 3 to 0 3 P07 P10 P17 P20 P26 P30 P34 P40 P47 P50 P57 P64 P65 P67 P70 P77 P120 P127 P130 P137 P140 P147 X1 X2 CL1 RESET Output voltage 0 3 to Vpp 0 3 Input voltage 0 3 to Vpp 0 3 Analog input voltage P10 to P17 Analog input pin 0 3 to AVpp 0 3 1 pin except P34 10 P34 30 High level output current POO P07 P20 P26 P30 P33 P40 P47 P50 P57 P64 P65 P67 P70 P77 P120 P127 30 P130 P137 P140 P147 CTXD total Peak 20 value 1 pin except P34 Effective value Peak value 10 30 Low level output Effective value P00 P07 P20 P26 P30 P33 P40 Peak 50 P47 P64 P65 P67 CTXD total Effective 20 20 P50 P57 P70 P77 P120 P127 P130 P137 P140 P147 total Effective 20 Operating 40 to 85 temperature Storage 40 to 125 temperature Note
285. igure 5 5 Examples of Oscillator with Bad Connection 1 3 a Wiring of connection circuits is too long b A signal line crosses over oscillation circuit lines PORTn n 010 10 12 13 User s Manual U12670EE3VOUDOO 111 Chapter 5 Clock Generator Figure 5 5 Examples of Oscillator with Bad Connection 2 3 c Changing high current is too near a signal conductor High Jt I Current d Current flows through the grounding line of the oscillator potential at points A B and C fluctuate lo JA High Current 112 User s Manual U12670EE3VOUDOO Chapter 5 Clock Generator Figure 5 5 Examples of Oscillator with Bad Connection 3 3 e Signals are fetched f Signal conductors of the main and subsystem clock are parallel and near each other um 1 CL1 and CL2 are wiring in parallel Remark When using a subsystem clock replace X1 and X2 with CL1 and CL2 respectively Caution In Figure 5 5 f CL1 and X1 are wired in parallel Thus the cross talk noise of X1 may increase with CL1 resulting in malfunctioning To prevent that from occurring it is recommended to wire CL1 and X1 so that they are not in parallel and to connect the IC pin between CL1 and X1 directly to Vss User s Manual U12670EE3VOUDOO 113 Chapter 5 Clock Generator 5 4 3 When no subsystem clock is used If it is not necessary to use sub
286. illator Data Manufacturer Murata Mfg Co Ltd AVX Kyocera Grp Manufacturer Kinseki Main System clock Ceramic Resonator Product Name CSA4 00MGA Frequency MHz Recommended Oscillator Constant C1 pF C2 pF R1 KQ Remarks CST4 00MGWA built in capacitor CSAC4 00MGCA CSTCC4 00MGA built in capacitor CSA8 00MGA CST8 00MGWA built in capacitor CSAC8 00MGCA CSTCC8 00MGA PBRC4 00BRVA built in capacitor PBRC8 00BRVA Main System Clock Crystal Resonator Product Name CX 5FW 4 MHz Frequency MHz Recommended Oscillator Constant C1 pF C2 pF R1 KQ Remarks HC 49 U S 8 MHz CX 11F 8 MHz NDK AT 51 KDS Daishinku AT 49 SaRonix Caution HC49 U13 HC49 L HC49 S The oscillator constants and oscillator voltage range indicate conditions for stable oscillation but do not guarantee oscillation frequency accuracy If oscillation fre quency accuracy is required for actual circuits it is necessary to adjust the oscilla tion frequency of the oscillator in the actual circuit Please contact the manufacturer of the resonator to be used User s Manual U12670EE3VOUDOO 447 Chapter 25 Electrical Specifications 25 4 Subsystem Clock Oscillation Circuit Characteristics 1 pPD780948 A 40 C to 85 C Vpp 4 0 to 5 5 V Re
287. imer Event Counter 0 Capture compare register 00 CROO CROO0 is a 16 bit register that functions as a capture register and as a compare register Whether this register functions as a capture or compare register is specified by using bit 0 00 of the capture compare control register 0 a When using CROO as compare register The value set to CROO is always compared with the count value of the 16 bit timer register TMO When the values of the two coincide an interrupt request INTTMOO is generated When TMOO is used as an interval timer CROO can also be used as a register that includes the interval time b When using CROO as capture register The valid edge of the TIOO or TIO1 pin can be selected as a capture trigger The valid edge of TIOO and TIO1 is performed via the prescaler mode register 0 PRMO Tables 6 2 and 6 3 show the conditions that apply when the capture trigger is specified as the valid edge of the TIOO pin and the valid edge of the TIO1 pin respectively Valid edge of TIOO Pin and valid edge of capture trigger of capture compare register Valid Edge of TIOO Pin Falling edge Capture Trigger of CROO Rising edge Capture Trigger of CRO1 Falling edge Rising edge Falling edge Rising edge Setting prohibited Setting prohibited Setting prohibited Both rising and falling edges No capture operation Both rising and falling edges Table 6 3 Valid edge of TIO1 Pin a
288. in is connected to Vpp via a resistor fx Main system clock oscillation frequency fxr Subsystem clock oscillation frequency Figures in parentheses indicate minimum instruction execution time 2fcp when oper ating at fy 8 0 MHz or fxr 32 768 KHz User s Manual U12670EE3VOUD00 Chapter 5 Clock Generator 5 4 System Clock Oscillator 5 4 1 Main system clock oscillator The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator standard 8 0 MHz connected to the X1 and X2 pins External clocks can be input to the main system clock oscillator In this case the clock signal to the X1 pin and the X2 pin has to be left open Figure 5 3 shows an external circuit of the main system clock oscillator Figure 5 3 External Circuit of Main System Clock Oscillator a Crystal and ceramic oscillation Crystal or Ceramic Resonator b External clock External Clock yPD74HCU04 Caution Do not execute the STOP instruction and do not set MCC bit 7 of processor clock control register PCC to 1 if an external clock is input This is because when the STOP instruction or MCC is set to 1 the main system clock operation stops and the X2 is connected to Vpp via a pull up resistor User s Manual U12670EE3VOUDOO 109 Chapter 5 Clock Generator 5 4 2 Subsystem clock oscillator The subsystem clock oscillator oscillates with a RC resonator standard 40 KHz connected to the CL 1 and CL
289. inactive level Remark 50 51 User s Manual U12670EE3VOUDOO 179 Chapter 8 8 Bit Timer Event Counters 50 and 51 Figure 8 16 PWM Output Operation Timing Active high setting CRn Changing cw Count Value 00 Ce ce OC JC Jc ce XC TCEn i i INTTMn OVFn 7 5 Inactive Level Inactive Level Active Level Inactive Level Remark 50 51 Figure 8 17 PWM Output Operation Timings CRn0 OOH active high setting CRn Changing 00 i rin Coun 5 Jc cs XY Jo Jos Yom DC TCEn EE ME EE MN INTTMn x eu sep y OVFn Inactive Level Inactive Level Remark 50 51 180 User s Manual U12670EE3VOUD00 Chapter 8 8 Bit Timer Event Counters 50 and 51 Figure 8 18 PWM Output Operation Timings CRn active high setting conteoek O LI LIS LU UU UY LULU Uo LU i X o X oe XX FF or XC JC Co INTTMn OVFn TOn Inactive Level Inactive Level Active Level Inactive Level Active Level Remark 50 51 Figure 8 19 Output Operation Timings CRn changing active high setting CRn Changing N M Clock PLE ee TE Clock 1 1 1 1 1 1 1 1 1 1 1 vm YEE Js Yo
290. inal bit time 8 to 25 time quanta Definition of 1 data bit time is as follows Figure 16 16 Nominal Bit Time 8 to 25 Time Quanta Nominal bit time Sync Prop Phase Phase segment segment segment 1 segment 2 a En Sample point 1 Minimum time for one time quantum TQ 1 fx Sync segment In this segment the bit synchronization is performed Prop segment This segment absorbs delays of the output buffer the CAN bus and the input buffer Prop segment time output buffer delay CAN bus delay input buffer delay Phase segment 1 2 These segments compensate the data bit time error The larger the size measured in TQ is the larger is the tolerable error The synchronization jump width SUW specifies the synchronization range The SJW is programmable SJW can have less or equal number of TQ as phase segment 2 Table 16 15 Segment Name and Segment Length Segment Length Segment allowed Number of TQs Sync segment Synchronization segment Prop segment Propagation segment Programmable 1 to 8 Phase segment 1 Phase buffer segment 1 programmable Ted Phase segment 2 Maximum of phase segment 1 Phase buffer segment 2 and the IPT Note SJW Programmable 1 to 4 Note IPT Information Processing Time It needs to be less than or equal to 2 TQ User s Manual U12670EE3VOUDOO 271 Chapter 16 CAN Coniroller 2 Adjusting synchronization of
291. inimum Interval Width Maximum Interval Width 1 fx 125 ns 28 x 1 fy 32 us 1 fx 125 ns 2 x 1 fy 250 ns 29 x 1 fx 64 us 2 x 1 fy 250 ns 23 x 1 fy 1 us 23 x 1 fy 1 us 211 x 1 fy 256 us 25 x 1 f 4 us 213 x 1 fx 1 ms 2 x 1 fx 4 us 2 x 1 f 16 us 215 x 1 fy 4 ms 2 x 1 fy 16 us 29 x 1 fx 64 us 217 x 1 fx 16 ms 29 x 1 fx 64 us Table 8 2 8 Bit Timer Event Counter 51 Interval Times Minimum Interval Width Maximum Interval Width 1 fx 125 ns 28 x 1 fy 32 us 1 fx 125 ns 2 x 1 fy 250 ns 29 x 1 fy 64 us 2 x 1 fy 250 ns 23 x 1 fx 1 us 211 x 1 fx 256 us 23 x 1 fx 1 us 2 x 1 fy 4 us 213 x 1 fy 1 ms 2 x 1 fy 4 us 2 x 1 fx 16 us 215 x 1 fx 4 ms 2 x 1 fy 16 us 212 x 1 fy 512 us 220 x 1 fy 131 ms Remarks 1 fx Main system clock oscillation frequency 21 x 1 fy 512 us 2 Values in parentheses when operated at fy 8 0 MHz User s Manual U12670EE3VOUDOO 161 Chapter 8 8 Bit Timer Event Counters 50 and 51 2 External event counter The number of pulses of an externally input signal can be measured 3 Square wave output A square wave with any selected frequency can be output Table 8 3 8 Bit Timer Event Counter 50 Square Wave Output Ranges Minimum Interval Width Maximum Interval Width 1 fy 125 ns 1 fx 125 ns 28 x 1 fy 32 us 2 x 1 fy 250 ns 2
292. ion Buffer 8 is selected for redefinition Buffer 9 is selected for redefinition Buffer 10 is selected for redefinition Buffer 11 is selected for redefinition Buffer 12 is selected for redefinition Buffer 13 is selected for redefinition ol ol ol ol oO ol Buffer 14 is selected for redefinition 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ek O o o of OF OF 1 Other than above Setting prohibited Buffer 15 is selected for redefinition Cautions 1 Keep special programming sequence Failing to do so can cause inconsistent data or loss of receive data 2 Do not change DEF bit and SEL bit at the same time Change SEL bit only when DEF bit is cleared 3 Write first SEL with DEF cleared Write than SEL with DEF or use bit manipulation instruction Only clear DEF bit by keeping SEL or use bit manipulation instruc tion Setting the redefinition bit removes the selected receive buffer from the list of possible ID hits during identifier comparisons Setting the DEF bit will not have immediate effect if DCAN is preparing to store or is already in progress of storing a received message into the particular buffer In this case the redefinition request is ignored for the currently processed message The application should monitor the DN flag before requesting the redefinition st
293. ion Interrupt service execution Maskable interrupt request Next address instruction execution Interrupt service execution STOP mode hold Non maskable interrupt request Interrupt service execution RESET input Remark Don t care Reset processing 410 User s Manual U12670EE3VOUDOO Chapter 22 Reset Function 22 1 Reset Function The following two operations are available to generate the reset signal External reset input with RESET pin Internal reset by watchdog timer overrun time detection External reset and internal reset have no functional differences In both cases program execution starts at the address at 0000H and 0001H by RESET input When a low level is input to the RESET pin or the watchdog timer overflows a reset is applied and each hardware is set to the status as shown in Table 22 1 Hardware Status after Reset on page 413 Each pin has high impedance during reset input or during oscillation stabilization time just after reset clear When a high level is input to the RESET input the reset is cleared and program execution starts after the lapse of oscillation stabilization time 2 7 fy The reset applied by watchdog timer overflow is auto matically cleared after a reset and program execution starts after the lapse of oscillation stabilization time 2 7 fy see Figure 22 2 Timing of Reset Input by RESET Input on page 412 Figure 22 3 Tim ing
294. ion For details refer to Figures 6 2 and 6 3 User s Manual U15251EE3VOUDOO 135 Chapter6 16 Timer Event Counter 0 a Capture operation free running mode The following figure illustrates the operation of the capture register when the capture trigger is input Figure 6 15 01 Capture Operation with Rising Edge Specified Count clock 1 Tmo 1 3 Pd n2 fo m d n Jf m CRO01 n 01 Figure 6 16 Timing of Pulse Width Measurement Operation with Free Running Counter with both edges specified Geet Pn TMO count value AE ARE DEN GDILE ARS D2 1X02 X Y D3 TIOO pin input E po V V V INTTMO1 lha 7 4 01 c ___ i l E 1 1 00 T I ss aS OVFO f 1 1 E D1 D0 xt px 10000H D1 D2 rd D3 D2 xt 2 10000H D1 02 1 xt 136 User s Manual U15251EE3VOUD00 Chapter 6 16 Bit Timer Event Counter 0 3 Pulse width measurement with free running counter and two capture registers When the 16 bit timer register TMO is used as a free running counter refer to Figure 6 17 the pulse width of the signal input to the TIOO pin can be measured When the edge specified by bits 4 and 5 500 and 501 of the prescaler mode register 0 PRMO is input to the TIOO pin the value of TMO is loaded to the
295. ion by Flowcharts 16 18 1 Initialization Figure 16 49 Initialization Flow Chart RESET Software Init set INIT 1 in CANC set BRPRS SYNCO 1 Initilialize message and mask data Write for Clear INIT 0 in CANG SYNCO 1 MASKC is now disabled End Initialization 324 User s Manual U12670EE3VOUDOO Chapter 16 CAN Controller 16 18 2 Transmit Preparation Figure 16 50 Transmit Preparation Wait or Abort or Try other Buffer Select Priority TXP End Transmit User s Manual U12670EE3VOUDOO 325 Chapter 16 CAN Coniroller 16 18 3 Abort Transmit Figure 16 51 Transmit Abort Transmission Abort Transmit Transmit was successful was aborted before ABORT End Transmission Abort 326 User s Manual U12670EESVOUDOO Chapter 16 CAN Controller 16 18 4 Handling by the DCAN Figure 16 52 Handling of Semaphore Bits by DCAN Module Data Storage Warns that data will be changed Only for buffers that are declared for mask operation Identifier bytes Data is changed MUC 0 signals stable data End Data Storage User s Manual U12670EE3VOUDOO 327 Chapter 16 CAN Coniroller 16 18 5 Receive Event Oriented 328 Figure 16 53 Receive with Interrupt Software Flow Receive Interrupt scans RMES or DN bits to find message Uses CLR1 Command No Data was changed by CAN during the processing Clear Interrupt End
296. ion mode register 30 CSIM30 x x 00H Serial I O shift register 30 51030 00H 220 User s Manual U12670EE3VOUDOO Chapter 13 Serial Interface Channel 30 13 4 Serial Interface Control Register The SIO30 uses the following type of register for control functions Serial operation mode register 30 CSIM30 Serial operation mode register 30 CSIM30 This register is used to enable or disable the serial clock selects operation modes and defines specific operations CSIM30 can be set via an 1 bit or an 8 bit memory manipulation instruction The RESET input sets the value to OOH Figure 13 2 Format of Serial Operation Mode Register 30 CSIM30 lt 7 gt 6 5 4 3 2 1 0 RW Address ter Reset Enable disable specification for SIO30 Shift register operation Serial counter Port Note 1 Operation stop Clear Port function Operation enable Count operation enable Serial operation port function Transfer operation modes and flags Operation mode Transfer start trigger 500 21 Transmit receive mode Write to SIO30 500 output Receive only mode Note 2 Read from 51030 Port function SCL301 SCL300 Clock selection fy 8 00 MHz External clock input 8 bit timer 50 TM50 output 23 2 Notes 1 When CSIE30 0 51030 operation stop status the pins connected to SIO 500 be used for port functions 2 When MODEO 1 Receive mode pin
297. ipulation instruction RESET input sets TMCO to 00H Caution The 16 bit timer register starts operating when a value other than 0 0 operation stop 124 mode is set to 02 and TMCO3 To stop the operation set 0 0 to 02 and TMCO3 User s Manual U15251EE3VOUDOO 7 02 Chapter 6 16 Bit Timer Event Counter 0 Figure 6 2 Format of 16 Bit Timer Mode Control Register TMCO 6 01 5 4 3 Operating mode clear mode Operation stop TMO is cleared to 0 2 1 Selection of TOO output timing Not affected 0 After Reset 00H R W Address Generation of interrupt Does not generate Free running mode Coincidence between TMO and CROO or coincidence between TMO and CRO1 Coincidence between TMO and CROO coincidence between TMO and or valid edge of TIOO Clears and starts at valid edge of TIOO Clears and starts on coinci dence between TMO and CROO Coincidence between TMO and CROO or coincidence between TMO and CRO1 Coincidence between TMO and CROO coincidence between TMO and or valid edge of TIOO Generates on coincidence between TMO and CROO or coincidence between TMO and CRO1 OVFO Detection of overflow of 16 bit timer register 0 Overflows 1 Does not overflow Cautions 1 Remark TOO TIOO TMO CROO 01 Before changing the clear mode and TOO output timing be sur
298. is capable of restart imme diately upon interrupt request and to carry out intermittent operations such as watch applications STOP mode STOP instruction execution sets the STOP mode In the STOP mode the main system clock oscil lator stops and the whole system stops CPU current consumption can be considerably decreased Data memory low voltage hold down to Vpp 2 0 V Note is possible Thus the STOP mode is effective to hold data memory contents with ultra low current consumption Because this mode can be cleared upon interrupt request it enables intermittent operations to be carried out However because a wait time is necessary to secure an oscillation stabilization time after the STOP mode is cleared select the HALT mode if it is necessary to start processing immediately upon interrupt request In any mode all the contents of the register flag and data memory just before entering the standby mode are held The input output port output latch and output buffer status are also held Cautions 1 The STOP mode can be used only when the system operates with the main sys tem clock subsystem clock oscillation cannot be stopped The HALT mode can be used with either the main system clock or the subsystem clock 2 When proceeding to the STOP mode be sure to stop the peripheral hardware operation and execute the STOP instruction 3 The following sequence is recommended for power consumption reduction of the A D converter when the
299. ister TMC2 This register sets the 16 bit timer operating mode and controls the prescaler output signals TMCO is set with an 1 bit or an 8 bit memory manipulation instruction RESET input clears TMC2 value to 00H Figure 7 2 16 Bit Timer Mode Control Register TMC2 Format 7 6 5 4 3 lt 2 gt 1 lt 0 gt RW Address Reset 22 Timer 2 Operating Mode Selection 0 Operation stop 1 Operation enabled TPOE Timer 2 Prescaler Output Control 0 Prescaler signal output disabled 1 Prescaler signal output enabled Cautions 1 Before changing the operation mode stop the timer operation by setting 0 to TMC22 2 Bit 1 and bits to 7 must be set to 0 152 User s Manual U12670EE3VOUDOO Chapter 7 16 Bit Timer 2 2 Capture pulse control register CRC2 This register specifies the division ratio of the capture pulse input to the 16 bit capture register CR22 from an external source 2 is set with an 8 bit memory manipulation instruction RESET input sets CRC2 value to 00H Figure 7 3 Capture Pulse Control Register CRC2 Format 7 6 5 4 3 2 lt 1 gt lt 0 gt R W Address et Reset 22 Capture Pulse Selection Does not divide capture pulse TI22 Divides capture pulse by 2 TI22 2 Divides capture pulse by 4 TI22 4 Divides capture pulse by 8 22 8 Cautions 1 Timer operation must be stopped before setting CRC2 2 Bits 2 to 7 must be set to 0 User s Ma
300. it CY A bit CY PSW bit CY PSW bit CY HL bit CY HL bit CY CY saddr bit CY lt CY saddr bit CY sfr bit CY CY sfr bit CY A bit CY lt CY AA bit CY PSW bit CY lt CY PSW bit CY HL bit PO PO CO CO PO PO GC PO CY lt CY HL bit When the internal high speed RAM area is accessed or instruction with no data access When an area except the internal high speed RAM area is accessed Except r Only when DE or HL One instruction clock cycle is one cycle of the CPU clock fcpu selected by the PCC register This clock cycle applies to internal ROM program nis the number of waits when external memory expansion area is read from mis the number of waits when external memory expansion area is written to User s Manual U12670EE3VOUDOO 429 Instruction Group Mnemonic Operands CY saddr bit Chapter 24 Co Instruction Set Table 24 2 Operation List 6 8 Operation CY lt CY v sadar bit CY sfr bit CY lt CY v sfr bit CY A bit CY CY v A bit CY PSW bit CY CY v PSW bit CY HL bit CY lt CY v HL bit CY saddr bit lt saddr bit CY sfr bit CY lt C v sfr bit CY A bit CY C v A bit CY PSW bit CY C v PSW bit CY HL bi
301. it 0 and bit 3 to bit 7 374 User s Manual U12670EE3VOUDOO Chapter 19 Interrupt Functions 4 External interrupt rising edge enable register EGP external interrupt falling edge enable register EGN EGP and EGN specify the valid edge to be detected on pins to P02 EGP and EGN can be read or written to with an 1 bit or an 8 bit memory manipulation instruction These registers are set to 00H when the RESET signal is output Figure 19 5 Formats of External Interrupt Rising Edge Enable Register and External Interrupt Falling Edge Enable Register Symbol 7 6 5 4 3 2 1 0 Address After Reset R W EGP 0 0 o EGP4 EGP3 EGP2 EGP1 EGPO FF48H 00H RW Symbol 7 6 3 2 1 0 Address After Reset R W 5 4 EGPn EGNn Valid edge of INTPn pin n 0 4 0 Interrupt disable 0 Falling edge 0 1 1 0 Rising edge User s Manual U12670EE3VOUDOO 375 5 376 Chapter 19 Interrupt Functions Program status word PSW The program status word is a register to hold the instruction execution result and the current status for interrupt request The IE flag to set maskable interrupts enable disable and the ISP flag to control multiple interrupt servicing are mapped Besides 8 bit unit read write this register can carry out operations with a bit manipulation instruc tion and dedicated instructions El and DI When a vectored interrupt request is acknowledged and when the BRK instruction is executed the conte
302. it is a O or a 1 No parity No parity bit is added to the transmit data During reception receive data is regarded as having no parity bit Since there is no parity bit no parity errors will occur 250 User s Manual U12670EE3VOUD00 Chapter 15 Serial Interface UART c Transmission The transmit operation is started when transmit data is written to the transmit shift register 50 A start bit parity bit and stop bit s are automatically added to the data Starting the transmit operation shifts out the data TXSO thereby emptying TXSO after which transmit completion interrupt INTSTO is issued The timing of the transmit completion interrupt is shown in Figure 15 11 Figure 15 11 Timing of Asynchronous Serial Interface Transmit Completion Interrupt i Stop bit length 1 bit ii Stop bit length 2 bits INTST Caution Do not write to the asynchronous serial interface mode register ASIMO during a transmit operation Writing to ASIMO during a transmit operation may disable further transmit operations in such cases enter a RESET to restore normal operation Whether or not a transmit operation is in progress can be determined via software using the transmit completion interrupt INTST or the interrupt request flag STIF that is set by INTST User s Manual U12670EE3VOUDOO 251 Chapter 15 Serial Interface UART d Reception The receive operation is enabled when bit 6 RXEO o
303. l width 20 21 22 input high low level width 00 01 input high low level width Interrupt input high low level width INTPO INTP4 RESET low level width Notes 1 The cycle time equals to the minimum instruction execution time For example 1 NOP instruction corresponds to 2 CPU clock cycles fepy selected by the processor clock control register PCC 2 sampling clock fy 4 fy 8 fy 32 1 128 3 fsmpo sampling clock fy 2 fy 16 1 128 Selection of fy 2 1 16 fy 128 is possible using bits 0 and 1 00 PRMO1 of prescaler mode register PRMO However if the TIOO valid edge is selected as the count clock the value becomes 2 462 User s Manual U12670EE3VOUDOO Cycle time Tcv us Chapter 25 Electrical Specifications Toy vs Vpp Operation guaranteed range i AZ A 1 2 3 4 5 6 Supply voltage Voo V User s Manual U12670EE3VOUDOO 463 Chapter 25 Electrical Specifications 3 pPD78F0948 40 C to 85 C Vpp 4 0 to 5 5 V Parameter Test Conditions Cycle time Note 1 4 0 V lt Vpp lt 5 5V 0 TI51 input frequency 0 1 input high low level width 20 21 22 input high low level width 00 01 input high low level width I
304. lds the address information of the next program to be executed In normal operation the PC is automatically incremented according to the number of bytes of the instruction to be fetched When a branch instruction is executed immediate data and register con tents are set RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter Figure 3 5 Program Counter Configuration 15 0 Program status word PSW The program status word is an 8 bit register consisting of various flags to be set reset by instruc tion execution Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW instruction execution and are automatically reset upon execution of the RETB RETI and POP PSW instructions RESET input sets the PSW to 02H Figure 3 6 Program Status Word Configuration 7 0 User s Manual U12670EE3VOUD00 Chapter 3 CPU Architecture a Interrupt enable flag IE This flag controls the interrupt request acknowledge operations of the CPU When 0 the IE is set to interrupt disabled DI status All interrupts except non maskable interrupt are disabled When 1 the IE is set to interrupt enabled El status and interrupt request acknowledge is control led with an in service priority flag ISP an interrupt mask flag for various interrupt sources and a priority specification flag The IE is reset to 0 upon DI instruction execution or interrupt re
305. le RMES can be read with a 1 bit or an 8 bit memory manipulation instruction RESET input sets RMES to 00H Figure 16 46 Receive Message Register Symbol 7 6 0 Address After Reset 5 4 3 2 1 R R R R R R R R This register is read only and it is cleared when the INIT bit in CANC register is set Data New Bit for Message n n 0 7 No message received on message n or CPU has cleared DN bit in message n Data received in message n that was not acknowledged by the CPU DNO bit has no meaning when receive buffer 0 is configured for mask operation in the mask control register DN2 bit has no meaning when receive buffer 2 is configured for mask operation in the mask control register 314 User s Manual U12670EE3VOUDOO Chapter 16 CAN Controller 16 15 3 Mask Control The mask control register defines whether the DCAN compares all identifier bits or if some bits are not used for comparison This functionality is provided by the use of the mask information The mask infor mation defines for each bit of the identifier whether it is used for comparison or not The DCAN uses a receive buffer for this information when it is enabled by the mask control register In this case this buffer is not used for normal message storage Unused bytes can be used for application needs Mask control register This register controls the mask function applied to any received message MASKC can be written with an 8 bit memory manipulation instr
306. lution converter that converts analog input voltages into digital values It can control up to 8 analog input channels ANIO to ANI This A D converter has the following functions 1 A D conversion with 8 bit resolution One channel of analog input is selected from ANIO to ANI7 and A D conversion is repeatedly exe cuted with a resolution of 8 bits Each time the conversion has been completed an interrupt request INTAD is generated 2 Power fail detection function This function is to detect a voltage group in the battery of an automobile The result of an A D con version value of the ADCR1 register and the value of PFT register PFT power fail compare threshold value register are compared If the condition for comparison is satisfied the INTAD is generated Figure 12 1 A D Converter Block Diagram ANIO P10 Sample amp hold circuit ANI1 P11 a a 1 Voltage comparator ANI2 P12 rO gi ANI3 P13 8 aR FT ANI4 P14 9 5 15 9 Successive Bx 35 approximation Lu AVss ANIG P16 register SAR i opm d ANI7 P17 O circuit A D conversion result register ADCR1 ADS12 ADS11 ADS10 Analog input channel specification register Internal bus ADCS1 FR12 FR11 FR10 A D converter mode register User s Manual U12670EE3VOUDOO 203 Chapter 12
307. mitting node compares its output arbitration field and the data level on the bus tlooses arbitration when it sends recessive level and reads dominant from bus Table 16 9 Arbitration Level Detection Status of Arbitrating Node Conformity of Level Continuous Transmission Non conformity of eval The data output is stopped from the next bit and reception operation starts Priority of data frame and remote frame When a data frame and remote frame with the same message identifier are on the bus the data frame has priority because its RTR bit carries Dominant level The data frame wins the arbitration 16 2 2 Bit Stuffing When the same level continues for more than 5 bits bit stuffing insert 1 bit with inverse level takes place Transmission Due to this a resynchronization of the bit timing can be done at least every 10 bits Nodes detecting an error condition send an error frame violating the bit stuff rule and indicating this message to be erroneous for all nodes Table 16 10 Bit Stuffing of data is inserted before the following bit Reception 266 deleting the next bit User s Manual U12670EE3VOUD00 During the transmission of a data frame and a remote frame when the same level continues for 5 bits in the data between the start of frame and the ACK field 1 bit level with reverse level During the reception of a data frame and a remote frame when the same level contin
308. mming tool Serial data sent by the on board programming tool Serial data sent by the device Serial data sent by the on board programming tool Serial data sent by the device User s Manual U12670EE3VOUDOO 421 Chapter 23 PD78F0948 23 3 5 Flash programming precautions Please make sure that the signals used by the on board programming tool do not conflict with other devices on the target H W A read functionality is not supported because of software protection Only a verify operation of the whole Flash EPROM is supported In verify mode data from start address to final address EFFFH has to be supplied by the programming tool The device compares each data with on chip flash content and replies with a signal for O K or not O K 422 User s Manual U12670EE3VOUDOO Chapter 24 Instruction Set This chapter describes each instruction set of the PD780948 Subseries as list table For details of its operation and operation code refer to the separate document 78K 0 series USER S MANUAL Instruction U12326E 24 1 Legends Used in Operation List 24 1 1 Operand identifiers and description methods Operands are described in Operand column of each instruction in accordance with the description method of the instruction operand identifier refer to the assembler specifications for detail When there are two or more description methods select one of them Alphabetic letters in capitals and symbols l and
309. mmon 2 COMO COM1 80 40 segments x 2 commons COMO COM2 120 40 segments x 3 commons 3 3 4 COMO to COMS 160 40 segments x 4 commons User s Manual U12670EE3VOUDOO 331 Chapter 17 LCD Controller Driver 17 2 LCD Controller Driver Configuration The LCD controller driver consists of the following hardware FA7FH FA68H FA67H FA58H 76543210 765483210 76543210 76543210 LCDON LCDM LCDMs LCDM4 LCDM2 LCDM LODMO LIPS Eu Display data memory 3210 selector 77 3210 selector Table 17 2 LCD Controller Driver Configuration Item Configuration Segment signals 40 Display outputs Segment signals with alternate function 40 Common signals 4 COMO to COM3 LCD display mode register LCD display control register LCDC Control registers Figure 17 1 LCD Controller Driver Block Diagram Internal bus LCD display mode register LCDM LCD display control 11 register LCDC 3 LCD clock selector fico 3210 3210 n Timing controller selector selector y ote Port function register PFn n 5 7 12 13 14 Segment selector lt P77 output P50 output buffer buffer S0 P147 S23 P120 524 77 539 50 COMO 1 2 Vico Vici Vice Remark Segment driver 332 User s Manual U12670EE3VOU
310. mmunication operation Remarks 1 Source clock for 5 bit counter 2 n Value set via TPS00 to 502 1 lt lt 8 3 k Value set via MDLOO to MDLO3 0 lt k x 14 246 User s Manual U12670EE3VOUD00 Chapter 15 Serial Interface UART The transmit receive clock that is used to generate the baud rate is obtained by dividing the main system clock Baud rate setting The main system clock is divided to generate the transmit receive clock The baud rate generated by the main system clock is determined according to the following formula f Baud rate kbps 21k 16 fx Oscillation frequency of main system clock in MHz n Value set via TPS00 to 502 1 lt n lt 8 For details see Table 15 3 k Value set via MDLOO to MDLO2 0 lt lt 14 in register BRGCO The relation between the 5 bit counter s source clock assigned to bits 4 to 6 500 to TPS02 of BRGOO and the n value in the above formula is shown in Figure 15 4 Format of Baud Rate Generator Control Register BRGCO 1 2 on page 239 Table 15 3 Relation between 5 bit Counter s Source Clock and n Value Source clock selection for 5 bit counter Remark fy Oscillation frequency of main system clock User s Manual U12670EE3VOUDOO 247 Baud rate Chapter 15 Serial Interface UART Error tolerance range for baud rates The tolerance range for baud rates depends on the number of bits per f
311. mplementation of the bus the dominant level would be represented by a logical 0 and the recessive level by a logical 1 This specific representation is used in this manual Physical states e g electrical voltage light that represent the logical levels are not given in this document 16 1 2 Message Format The CAN protocol message supports different types of frames The types of frames are listed below Data frame Carries the data from a transmitter to the receiver Remote frame Transmission demand frame from the requesting node Error frame Frame sent on error detection Overload frame Frame sent when a data or remote frame would be overwritten by the next one before the receiving node could process it The reception side did not finish its operations on the reception of the previously received frame yet 256 User s Manual U12670EE3VOUD00 Chapter 16 CAN Controller 16 1 3 Data Frame Remote Frame Figure 16 1 Data Frame Data frame 11 1 R 29 3 6 0 64 16 2 7 3 D 9 QD A A A A A Bus idle Interframe space End of frame ACK field CRC field Data field Control field Arbitration field Start of frame Figure 16 2 Remote Frame Remote frame R D A A A A Bus idle Interframe space End of frame ACK field CRC field Control field Arbitration field
312. n 2 0 100 256 byte Expansion Mode when MM2 MM0 01 1 Single chip Mode User s Manual U12670EE3VOUD00 Chapter 20 External Device Expansion Figure 20 1 Memory Map when Using External Device Expansion Function 2 3 b uPD780948 uPD78F0948 Memory map when internal ROM size is 56 Kbytes FFFFH FFOOH FEFFH FBOOH FAFFH FB80H FA7FH FA58H FA57H F7E0H F7DFH F400H F3FFH FOOOH EFFFH E100H FOFFH E000H DFFFH 0000H Special Function Registers Internal High Speed RAM Not usable LCD Display RAM Not usable Internal Expansion RAM Full Address Mode when MM2 MMO 1 11 or 16 Kbyte Expansion Mode when 2 0 101 4 Kbyte Expansion Mode when 2 0 100 256 byte Expansion Mode when 2 0 011 Single chip Mode User s Manual U12670EE3VOUDOO 391 Chapter 20 External Device Expansion Figure 20 1 Memory Map when Using External Device Expansion Function 3 3 UPD780948 uPD78F0948 Memory map when internal ROM size is 60 Kbytes FFFFH Special Function Registers FFOOH FEFFH Internal High Speed RAM FBOOH FAFFH Not usable FB80H FA7FH LCD Display RAM FA58H FA57H Not usable F7EOH F7DFH Internal Expansion RAM F400H F3FFH Not usable FOOOH EFFFH Single chip Mode 0000H Caution When the internal ROM size is 60 Kbytes the area from F000H to F3FFH cannot be used F000H to F3FFH can be used as exter
313. n and timer Segment signal output 32 pins max 120 pin PD780308 with enhanced display function and timer Segment signal output 24 pins max 100 pin LL PD78064 with enhanced SIO and expanded ROM and RAM 100 pin EMI noise reduced version of the PD78064 100 pin Basic subseries for driving LCDs on chip UART Bus interface supported 100 pin Lu PD780948 On chip CAN controller 80 pin uPD78098B uPD78054 with IEBus controller 80 pin uPD780702Y On chip IEBus controller 80 pin uPD780703Y 2 On chip CAN controller 80 pin On chip controller compliant with J1850 Class 2 uPD780833Y 64 uPD780816 Specialized for CAN controller function Meter control 100 pin uPD780958 For industrial meter control 80 pin uPD780852 On chip automobile meter controller driver 80 pin uPD780828B For automobile meter driver On chip CAN controller Remark VFD Vacuum Fluorescent Display is referred to as Fluorescent Indicator Panel in some documents but the functions of the two are the same User s Manual U12670EE3VOUDOO 31 Chapter 1 Outline uPD780948 Subseries The major functional differences between the subseries are shown below Table 1 1 Function Subseries Name uPD78075B ROM Capacity Bytes 32K to 40K uPD78078 48K to 60K uPD78070A PD780058 24K to 60K The major functional differences between the subseries Serial Interface 3 ch UART 1 ch
314. n page 48 Pin Name POO INTPO P01 INTP1 PO2 INTP2 POS INTPS T2PO PO4 INTP4 T1014 P05 T100 TOO P06 TI50 TO50 P07 TI51 TO51 Table 2 3 Input Output Circuit Type Types of Pin Input Output Circuits 1 3 Recommended Connection for Unused Pins Input Connect to Vpp or Vas via a resistor individually Output Leave open P10 ANIO P11 ANI1 P12 ANI2 P13 ANI3 P14 ANI4 P15 ANI5 P16 ANI6 P17 ANI7 Connect to Vpp or Vgs directly 20 510 21 500 P22 SCKO P23 SH SOA P24 SCK1 Input Connect to Vpp or Vss via a resistor individually Output Leave open P25 RXD P26 TXD 20 P31 TI21 32 22 Input Connect to Vpp or Vss via a resistor individually Output Leave open P33 PCL SGOA P34 SGO SGOF 48 User s Manual U12670EE3VOUD00 Pin Name P50 A8 S39 P51 A9 S38 P52 A10 S37 53 11 636 P54 A12 S35 P55 A13 S34 56 14 633 P57 A15 S32 Chapter 2 Pin Function uPD780948 Subseries Table 2 3 Types of Pin Input Output Circuits 2 3 Input Output Circuit Type Recommended Connection for Unused Pins Input Connect to Vpp or Vss via a resistor individually Output Leave open Input Connect to Vpp or Vas via a resistor individually Output Leave open P64 RD P65 WR P67 ASTB
315. nal memory by setting the internal ROM size to less than 56 Kbytes by the memory size switching register IMS 392 User s Manual U12670EESVOUDOO Chapter 20 External Device Expansion 20 2 External Device Expansion Function Control Register The external device expansion function is controlled by the memory expansion mode register MEM the memory expansion wait register MM and memory size switching register IMS 1 Memory expansion mode register MEM MM sets the wait count and external expansion area and also sets the input output of port 4 MM is set with an 8 bit memory manipulation instruction RESET input sets this register to 10H Figure 20 2 Memory Expansion Mode Register Format Symbol 7 6 5 0 Address After Reset R W 4 3 2 1 Single chip Memory P40 P47 P50 P57 P64 P65 P67 Pin state Expansion Mode Selection 40 47 P50 P53 P54 P55 P56 P57 64 P65 P67 Port mode Single chip mode 0 1 Port mode 1 256 byte mode Port mode 0 1 P64 RD 4 KB mode Port mode Memory ADO AD7 P65 WR expansion 16 KB mode P67 ASTB mode A12 A13 Full address A14 A15 1 1 mode Note Other than above Setting prohibited Note The full address mode allows external expansion to the entire 64 Kbyte address space except for the internal ROM RAM and SFR areas and the reserved areas User s Manual U12670EE3VOUDOO 393 Chapter 20 External Devi
316. nction register PF2 PF5 PF7 PF12 to PF14 This register is used to set the output buffer of port 2 P20 to P24 and the LCD segment function of ports 5 7 12 13 and 14 PF2 PF5 and PF7 are set with an 1 bit or 8 bit manipulation instruction PF12 to PF14 are set with an 8 bit manipulation instruction RESET input sets this register to OOH Figure 4 15 Port Function Register PF2 PF5 PF7 PF12 to PF14 Format 7 6 5 4 3 2 1 0 Address Alter Reset PF2 PF24 PF23 PF22 PF 1 PF20 R W FF52H 00H 7 6 5 4 3 2 1 0 Address Alter Reset 5 PF57 PF56 PF55 PF54 PF53 PF52 51 PF50 R W FF55H 00H 7 6 5 4 3 2 1 O Address hd eset 7 PFz7 PF76 PF75 PF74 PF78 PF72 71 PF70 R W FF57H 7 6 5 4 3 2 1 0 Address eset 12 PF127 126 PF125 PF124 PF123 PF122 PF121 PF120 R W FFBCH 0H 7 6 5 4 3 2 1 0 Address iis eset PF13 PF137 PF136 PF135 PF134 PF133 PF132 PF131 130 RW FFBDH 7 6 5 4 3 2 1 0 R W Address bud eset 14 PF147 PF146 PF145 PF144 PF143 PF142 141 140 R W FFBEH 00H P2n Port Function Selection n20 4 0 Push pull output buffer 1 N channel open drain output buffer PFmn PFmn Port Function Selection m 5 7 12 13 14 n 0 7 0 Port function 1 LCD segment function Caution For PF12 to PF14 it is only allowed to set 00H
317. nd all subsequent operations are stopped The receive operation can be restarted once the clock is restarted 254 User s Manual U12670EE3VOUDOO Chapter 16 CAN Controller Table 16 1 Outline of the Function Feature Details CAN2 0 with active extended frame capability Protocol Bosch specification 2 0 part B Baudrate Max 500 Kbps at 8 MHz clock supply Bus line control CMOS in out for external transceiver Clock Selected by register CPU RAM area with shared access Data storage DCAN uses up to 288 byte of RAM Unused bytes can be used by CPU for other tasks Received messages will be stored in RAM area Message organisation depending on message identifier Transmit messages have two dedicated buffers in RAM area One input receive shadow buffer not readable by user Message number Up to 16 receive message objects including 2 masks Two transmit channels Unique identifier on all 16 receive message objects Message sorting Up to 2 message objects with mask Global mask for all messages DCAN protocol SFR access for general control Transmit interrupt for each channel Interrupt One receive interrupt with enable control for each message One error interrupt Support of time stamp and global time system Programmable single shot mode Readable error counters Diagnostic Valid protocol activity flag for verification of bus connection Receive only mode for automatic baudrate d
318. nd valid edge of capture trigger of capture compare register Valid Edge of TIO1 Pin Falling edge Capture Trigger of CROO Rising edge Rising edge Setting prohibited Falling edge Setting prohibited Both rising and falling edges Both rising and falling edges 0 is set by a 16 bit memory manipulation instruction After RESET input the value of CROO is undefined Cautions 1 Set another value than 0000H to CROO This means that an 1 pulse count opera 122 tion cannot be performed when 00 is used as an event counter However in the three running mode and in the clear mode using the valid edge of TIOO if 0000H is set to CROO an interrupt request INTTMOO is generated following overflow FFFFH 2 If the new value of CROO is less than the value of 16 bit counter 0 TMO con tinues counting overflows and than starts counting from 0 again If the new value of CROO is less than the old value therefore the timer must be restarted after the value of CROO is changed User s Manual U15251EE3VOUDOO Chapter 6 16 Bit Timer Event Counter 0 3 Capture compare register 01 CRO1 This is a 16 bit register that can be used as a capture register and a compare register Whether it is used as a capture register or compare register is specified by bit 2 CRCO02 of the capture com pare control register O a When using 01 as compare register The value set to CRO1 is always compa
319. ne node is active at start up it may not receive an acknowledgment on a transmitted message This will increment TEC until error passive state is reached The bus off state will not be reached because for this specific condition TEC will not increment any more if values greater than 127 are reached A node in bus off state will not issue any dominant level on the CAN transmit pin The reception of messages is not affected by the bus off state Operation Transmission ctive reception Table 16 13 Types of Error Value of Error Counter 0 to 127 Output Error Flag Type Active error flag 6 bits of dominant level continue Error p Transmission assive 128 to 255 Reception 128 or more Passive error flag 6 bits of recessive level con tinue Bus off Transmission more than 255 Communication cannot be made Reception Does not exist User s Manual U12670EE3VOUDOO 269 Chapter 16 CAN Coniroller b Error counter Error counter counts up when an error has occurred and counts down upon successful transmission and reception The error counters are updated during the first bit of an error flag Table 16 14 Error Counter Reception node detects an error except bit error in the active error flag or overload flag Transmission Error Counter TEC No change Reception Error Counter REC Reception node detects dominant level following the error flag of the o
320. ng methods are available to specify the register and memory addressing which undergo manipulation during instruction execution 3 4 1 Implied addressing The register which functions as an accumulator A and AX in the general register is automatically implicitly addressed Of the PD780948 Subseries instruction words the following instructions employ implied addressing Table 3 4 Implied Addressing Instruction Register to be Specified by Implied Addressing MULU A register for multiplicant and AX register for product storage DIVUW AX register for dividend and quotient storage ADJBA ADJBS A register for storage of numeric values which become decimal correction targets ROR4 ROL4 A register for storage of digit data which undergoes digit rotation Operand format Because implied addressing can be automatically employed with an instruction no particular operand format is necessary Description example In the case of MULU X With an 8 bit x 8 bit multiply instruction the product of A register and X register is stored in AX In this example the A and AX registers are specified by implied addressing 74 User s Manual U12670EE3VOUD00 Chapter 3 CPU Architecture 3 4 2 Register addressing The general register is accessed as an operand The general register to be accessed is specified with register bank select flags RBSO and RBS1 and register specify code Rn RPn in the instruction code Register addressing i
321. nge MIN 4 0 V Oscillator frequency Vpp 4 0 to 5 5 V f Note 1 Crystal x resonator Oscillation stabiliza ane 2 i i Note 2 oscillator voltage PRENS range MIN 4 0 V X1 input frequency Vpp 4 0 to 5 5 V fy Note 1 open X1 input high low level PD74HCU04 y width typ txL Vpp 4 0 to 5 5 V Notes 1 Indicates only oscillation circuit characteristics Refer to AC Characteristics for instruction execution time 2 Time required to stabilize oscillation after reset or STOP mode release Cautions 1 When using the main system clock oscillation circuit wiring in the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance Wiring should be as short as possible Wiring should not cross other signal lines Wiring should not be placed close to a varying high current The potential of the oscillation circuit capacitor ground should always be the same as that of Vss Do not ground wiring to a ground pattern in which a high current flows Do not fetch a signal from the oscillation circuit 2 When the main system clock is stopped and the system is operated by the sub System clock the subsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured by the program 446 User s Manual U12670EE3VOUDOO Chapter 25 Electrical Specifications Recommended Osc
322. nitored for the associated buffer Notification by the receive inter rupt upon successful reception can be selected for each receive buffer separately IDCON can be set with a 1 bit or an 8 bit memory manipulation instruction RESET input sets IDCON to an undefined value Figure 16 27 Control bits for Receive Identifier Symbol 7 6 0 Address After Reset R W 5 4 3 2 1 IDE Identifier Extension Select Receive standard frame message 11 bit identifier Receive extended frame message 29 bit identifier Remote Transmission Select Receive data frames Receive remote frames Enable Interrupt on ReceiveNete No interrupt generated Generate receive interrupt after reception of valid message The control bits define the type of message that is transferred in the associated buffer if this type of message appears on the bus This byte will never be written by the DCAN Only the host CPU can change this byte Note The user has to define with the ENI bit if he wants to set a receive interrupt request when new data is received in this buffer User s Manual U12670EE3VOUDOO 287 Chapter 16 CAN Coniroller 2 Receive status bits definition The memory location labelled DSTAT sets the receive status bits of the arbitration field of the CAN protocol DSTAT can be set with a 1 bit or an 8 bit memory manipulation instruction RESET input sets DSTAT to an undefined value Figure 16 28 Receive Status Bits 1 2 Symbol 7
323. nnns 434 Table 24 6 Call instructions branch instructions sessseeseeeeeeeennenen ens 435 Table 27 1 Surface Mounting Type Soldering 489 User s Manual U12670EE3VOUDOO 25 26 User s Manual U12670EE3VOUD00 Chapter 1 Outline uPD780948 Subseries 1 1 Features Internal memory Program Memory Part Number ROM uPD780948 60 Kbytes Data Memory Internal high speed RAM 1024 bytes LCD Display RAM 40 bytes Internal Expansion RAM 992 bytes Package 100 pin plastic QFP fine pitch uPD78F0948 60 Kbytes External memory expansion 1024 bytes Minimum instruction execution time can be changed from high speed 0 25 us to ultra low speed O ports 79 N ch open drain 5 8 bit resolution A D converter 8 channels Sound generator e LCD controller driver CAN Interface 40 bytes 992 bytes Serial interface 2 wire mode 3 wire mode UART mode Timer Supply voltage 100 pin plastic QFP fine pitch 3 channels 1 channel 1 channel 1 channel 6 channels 4 0 to 5 5 V The CAN macro is qualified according the requirements of ISO 11898 using the test procedures defined by ISO 16845 and passed successfully the test procedures as recommended by C amp S FH Wolfenbuettel 1 2 Application Dashboard climate contr
324. non maskable interrupt servicing program execution Main Routine NMI Request 1 Instruction NMI Request gt NMI Request Reserve Execution Reserved NMI Request Processing i b If two non maskable interrupt requests are generated during non maskable interrupt servicing program execution Main Routine NMI Request NMI EN Reserved Request 1 Instruction Execution NMI Request Reserved Although two or more NMI requests have been generated only one request has been acknowledged Lk 378 User s Manual U12670EE3VOUD00 Chapter 19 Interrupt Functions 19 4 2 Maskable interrupt request acknowledge operation A maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and the interrupt mask MK flag is cleared to 0 A vectored interrupt request is acknowledged in an interrupt enable state with IE flag set to 1 However a low priority interrupt request is not acknowledged during high priority interrupt service with ISP flag reset to 0 Wait times from maskable interrupt request generation to interrupt servicing are as follows Table 19 3 Times from Maskable Interrupt Request Generation to Interrupt Service When xxPRx 7 clocks 32 clocks When xxPRx 1 8 clocks 33 clocks Note lfan interrupt request is generated just before a divide instruction the wait time is maximized Remark 1 clock 1 fopy fepu CPU clock If two or more maskable i
325. nother instruction is executed However when a branch instruction is executed the branch destination information is set to the PC and branched by the following addressing For details of instructions refer to 78 0 User s Manual Instructions U12326E 3 3 1 Relative addressing The value obtained by adding 8 bit immediate data displacement value jdisp8 of an instruction code to the start address of the following instruction is transferred to the program counter PC and branched The displacement value is treated as signed two s complement data 128 to 127 and bit 7 becomes a sign bit In other words the range of branch in relative addressing is between 128 and 127 of the start address of the following instruction This function is carried out when the BR addr16 instruction or a conditional branch instruction is executed Figure 3 11 Relative Addressing a m PC indicates the start address after the BR instruction jdisp8 S When S 0 all bits of a are 0 When S 1 all bits of a are 1 70 User s Manual U12670EE3VOUDOO Chapter 3 CPU Architecture 3 3 2 Immediate addressing Immediate data in the instruction word is transferred to the program counter PC and branched This function is carried out when the CALL addr16 or BR addr16 or CALLF laddr11 instruction is exe cuted CALL addr16 and BR addr16 instructions can branch to all the memory spac
326. nput voltage 0 3 to Vpp 0 3 Analog input voltage P10 to P17 Analog input pin 0 3 to AVpp 0 3 1 pin except P34 10 P34 30 High level output current POO P07 P20 P26 P30 P33 P40 P47 P50 P57 P64 P65 P67 P70 P77 P120 P127 30 P130 P137 P140 P147 CTXD total Peak 20 value 1 pin except P34 Effective value Peak value 10 30 Low level output current Effective value P00 P07 P20 P26 P30 P33 P40 Peak 50 P47 P64 P65 P67 CTXD total Effective 20 20 P50 P57 P70 P77 P120 P127 29 P130 137 140 P147 total Effective 20 Operating 40 to 85 temperature Storage 40 to 125 temperature Note Effective value should be calculated as follows Effective value Peak value x Vduty Caution Product quality may suffer if the absolute maximum ratings are exceeded for even a single parameter or even momentarily That is the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage Therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded Remark The characteristics of the dual function pins are the same as those of the port pins unless otherwise specified User s Manual U12670EE3VOUDOO 437 Chapter 25 Electrical Specifications 2 pPD780948 A1
327. ns fer completion flag Figure 14 5 Timing of Three wire Serial I O Mode Serial clock 1 2 3 4 5 6 7 8 1 511 801 07 D6 A 05 D4 f X D2 f D1 f DO Serial transfer completion flag l Transfer completion Transfer starts in synchronized with the serial clock s falling edge 3 Operation start A serial operation starts when the following two conditions have been satisfied and transfer data has been set to serial I O shift register 31 51031 The SIO31 operation control bit CSIE31 1 After an 8 bit serial transfer the internal serial clock is either stopped or is set to high level Transmit receive mode When CSIE31 1 and MODE1 0 transfer starts when writing to 51031 Receive only mode When CSIE31 1 MODE1 0 transfer starts when reading from 51031 Caution After data has been written to 51031 transfer will not start even if the CSIE31 bit value is set to 1 Completion of an 8 bit transfer automatically stops the serial transfer operation and sets a serial transfer completion flag 230 User s Manual U12670EE3VOUD00 Chapter 14 Serial Interface Channel 31 4 2 wire serial communication The SCK1 and 611 500 pins can be used with N ch open drain output buffer Therefore the exter nal pull up resistors have to be used as in Figure 14 6 In order to set these pins to N ch open drain type write 1 to PF24 and PF23 registers When this product is used as a master PM2
328. nt from the message definitions and the RXONLY bit setting in SYNC1n register VALID is updated after each reception The VALID bit will be set at the end of the frame when a complete protocol without errors has been detected Cautions 1 The VALID bit is cleared if CPU writes an 1 to it or when the INIT bit in CANC register is set 2 Writing a 0 to the valid bit has no influence User s Manual U12670EE3VOUDOO 301 Chapter 16 CAN Coniroller Figure 16 39 CAN Error Status Register 3 3 WAKE Wake up Condition Normal operation Sleep mode has been cancelled or sleep stop mode request was not granted This bit is set and an error interrupt is generated under the following circumstances a A CAN bus activity occurs during DCAN Sleep mode b Any attempt to set the SLEEP bit in the CAN control register during receive or transmit opera tion will immediately set the WAKE bit The CPU must clear this bit after recognition in order to receive further error interrupts because the error interrupt line is kept active as long as this bit is set Cautions 1 The WAKE bit is cleared to 0 if CPU writes an 1 to it or when the INIT bit in CANC register is set 2 Writing 0 to the WAKE bit has no influence OVER Overrun Condition 0 Normal operation 1 Overrun occurred during access to RAM The overrun condition is set whenever the CAN can not perform all RAM accesses that are necessary for
329. nterrupt input high low level width INTPO INTP4 RESET low level width Notes 1 The cycle time equals to the minimum instruction execution time For example 1 NOP instruction corresponds to 2 CPU clock cycles fepy selected by the processor clock control register PCC 2 sampling clock fy 4 fy 8 fy 32 1 128 3 fsmpo sampling clock fy 2 fy 16 1 128 Selection of fy 2 1 16 fy 128 is possible using bits 0 and 1 00 PRMO1 of prescaler mode register PRMO However if the TIOO valid edge is selected as the count clock the value becomes 2 464 User s Manual U12670EE3VOUDOO Cycle time Tcv us Chapter 25 Electrical Specifications Toy vs Vpp Operation guaranteed range i AZ A 1 2 3 4 5 6 Supply voltage Voo V User s Manual U12670EE3VOUDOO 465 Chapter 25 Electrical Specifications 25 6 2 Read Write Operation 1 pPD780948 A TA 40 C to 85 C Vpp 4 0 to 5 5 V Parameter Conditions ASTB high level width tasTH Address setup time taps Address hold time tADH tapp1 Data input time from address tADD2 m Data input time from RD 4 inpp2 Address output time from RD 4 tRDAD 0 0 Read data hold time 2 2 tBDL1 1 5 2n tcy 38 D low level wid
330. nterrupt requests are generated simultaneously the request specified for higher priority with the priority specify flag is acknowledged first If two or more requests are specified for the same priority with the priority specify flag the interrupt request with the higher default priority is acknowledged first Any reserved interrupt requests are acknowledged when they become acknowledgeable Figure 19 10 on page 380 shows interrupt request acknowledge algorithms When a maskable interrupt request is acknowledged the contents of program status word PSW and program counter PC are saved in this order onto the stack Then the IE flag is reset to 0 and the value of the acknowledged interrupt priority specify flag is transferred to the ISP flag Further the vector table data determined for each interrupt request is loaded into PC and the program will branch accordingly Return from the interrupt is possible with the RETI instruction User s Manual U12670EE3VOUDOO 379 Chapter 19 Interrupt Functions Figure 19 10 Interrupt Request Acknowledge Processing Algorithm Start Yes Interrupt Request Generation lt gt Yes Interrupt request reserve Yes High priority eom a No Low Priority priority interrupt among simultaneously generated xxPR 0 interrupts Any simultaneously generated xxPR 0 interrupts Yes Interrupt request Interrupt request reserve reserve
331. nterval When bit 0 WTMO and bit 1 WTM1 of the watch timer mode control register WTM are set to 1 the count operation starts When set to 0 the 5 bit counter is cleared and the count operation stops For simultaneous operation of the interval timer zero second start can be only the watch timer by setting WTM1 to 0 However since the 9 bit prescaler is not cleared the first overflow of the watch timer INTWT after zero second start may include an error of up to 29 x 1 fw 9 4 2 Interval timer operation The watch timer operates as interval timer which generates interrupt request repeatedly at an interval of the preset count value The interval time can be selected with bits 4 to 6 WTM4 to WTM6O of the watch timer mode control register WTM Table 9 3 Interval Timer Operation Interval Time fy 8 00 MHz Operation fxr 32 768 KHz Operation 512 us 1ms 2 ms 4 ms 8 19 ms 0 16 38 ms Other than above Setting prohibited Remarks 1 fy Main system clock oscillation frequency 2 fxr Subsystem clock oscillation frequency 3 fw Watch timer clock frequency User s Manual U12670EE3VOUDOO 189 Chapter 9 Watch Timer Figure 9 3 Operation Timing of Watch Timer Interval Timer 5 bit counter Overflow Overflow Start E ses Te po ERES E E e Watch timer interrupt INTWT Interrupt time of watch timer Interrup
332. ntheses apply to operation with fy 8 00 MHz 128 User s Manual U15251EE3VOUDOO Chapter 6 16 Bit Timer Event Counter 0 5 Port mode register 0 PMO This register sets port O input output in 1 bit units When using the PO5 TOO TIOO pin for timer output set 5 and the output latch of PO5 to 0 PMO is set with an 1 bit or an 8 bit memory manipulation instruction RESET input sets PMO value to FFH Figure 6 6 Port Mode Register 7 PM7 Format 7 6 b 4 3 2 1 0 Address Alter Reset i RW 20 POn pin input output mode selection 0 to 7 0 Output mode output buffer ON 1 Input mode output buffer OFF User s Manual U15251EE3VOUDOO 129 Chapter6 16 Timer Event Counter 0 6 4 16 Bit Timer Event Counter 0 Operations 6 4 1 Operation as interval timer 16 bits The 16 bit timer event counter operates as an interval timer when the 16 bit timer mode control register TMCO and capture compare control register 0 CRCO are set as shown in Figure 6 7 In this case 16 bit timer event counter repeatedly generates an interrupt at the time interval specified by the count value set in advance to the 16 bit capture compare register 00 CROO When the count value of the 16 bit timer register 0 TMO coincides with the set value of CROO the value of TMO is cleared to 0 and the timer continues counting At the same time an interrupt request signal INTTMOO is generated The count clock of the
333. ntification and the message data have to be stored in the message RAM area The transmission control is done by the TCR register A transmission priority selection allows the cus tomer to realize an application specific priority selection After the priority selection the transmission can be started by setting the TXRQn bit n 0 1 In the case that both transmit buffers are used the transmit priorities can be set For this purpose the DCAN has the TXP bit in the TCR register The application software has to set this priority before the transmission is started The two transmit buffers supply two independent interrupt lines for an interrupt controller Note Message objects that need less than 8 data byte DLC 8 may use the remaining bytes 8 DLC for application purposes 16 9 Transmit Message Format Table 16 20 Transmit Message Format Unused ID standard part ID standard part 0 0 ID extended part ID extended part ID extended part 0 0 Unused Message data byte 0 Message data byte 1 Message data byte 2 Message data byte 3 Message data byte 4 Message data byte 5 Message data byte 6 Message data byte 7 Note This address is a relative offset to the starting address of the transmit buffer User s Manual U12670EE3VOUDOO 281 Chapter 16 CAN Coniroller 1 Transmit Message Definition The memory location labelle
334. nts of PSW automatically is saved onto the stack and the IE flag is reset to 0 If a maskable interrupt request is acknowledged contents of the priority specify flag of the acknowledged interrupt are transferred to the ISP flag The acknowl edged contents of PSW is also saved onto the stack with the PUSH PSW instruction It is retrieved from the stack with the RETI RETB and POP PSW instructions RESET input sets PSW to 02H Figure 19 6 Program Status Word Format Symbol 7 6 After Reset R W 5 4 3 2 1 0 pew z Resi meo o 5 OY Aw Priority of Interrupt Currently Being Received High priority interrupt servicing low priority interrupt disable Interrupt request not acknowledged or low priority interrupt servicing all maskable interrupts enable Interrupt Request Acknowledge Enable Disable 0 Disable 1 Enable User s Manual U12670EE3VOUD00 Chapter 19 Interrupt Functions 19 4 Interrupt Servicing Operations 19 4 1 Non maskable interrupt request acknowledge operation A non maskable interrupt request is unconditionally acknowledged even if in an interrupt request acknowledge disable state It does not undergo interrupt priority control and has highest priority over all other interrupts If a non maskable interrupt request is acknowledged PSW and PC are pushed on the stack The IE and ISP flags are reset to 0 and the vector table contents are loaded into PC A new non maskable interrupt request
335. nual U12670EE3VOUDOO Serial operation Do not switch the operation mode until the current serial transmit receive operation has stopped 241 Chapter 15 Serial Interface UART 15 5 2 Asynchronous serial interface UART mode This mode enables full duplex operation where one byte of the data is transmitted or received after the start bit The on chip dedicated UART baud rate generator enables communications by using a wide range of selectable baud rates 1 Register settings The UART mode settings are made via the asynchronous serial interface mode register ASIMO asynchronous serial interface status register ASISO and the baud rate generator control register BRGCO a Asynchronous serial interface mode register ASIMO ASIMO can be set by an 1 bit or an 8 bit memory manipulation instructions When RESET is input its value is 00H Figure 15 6 Format of Asynchronous Serial Interface Mode Register ASIMO 1 2 lt 7 gt nds 5 4 1 0 Address Alter Reset 3 2 TXEO RXEO Operation mode RXD pin function TXD pin function 0 0 Operation stop Port function Port function UARTO mode receive only UARTO mode transmit only UARTO mode transmit and receive Serial operation Port function Port function Serial operation Serial operation Serial operation Parity bit specification No parity Zero parity always added during transmission No parity detection during reception
336. nual U12670EE3VOUDOO 153 Chapter 7 16 Bit Timer 2 3 Prescaler mode register PRM2 This register is used to set 16 bit timer TM2 count clock and valid edge of n 0 to 2 input 2 is set with an 8 bit memory manipulation instruction RESET input sets PRM2 value to 00H Figure 7 4 Prescaler Mode Register PRM2 Format 7 6 4 3 2 1 0 RW Address Reset 22 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges TI21 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges 501 500 20 Valid Edge Selection 0 0 Falling edge Rising edge Setting prohibited Both falling and rising edges Count Clock Selection Caution Timer operation must be stopped before setting PRM2 154 User s Manual U12670EE3VOUDOO Chapter 7 16 Bit Timer 2 7 4 16 Bit Timer 2 Operations 7 4 1 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the TI20 P30 to TI22 P32 pins by using the 16 bit timer register TM2 TM2 is used in free running mode 1 Pulse width measurement with free running counter and one capture register TI20 When the edge specified by the prescaler mode register PRM2 is input to the TI20 P30 pin the value of TM2 is taken into 16 bit capture register 20 CR20 and an external inte
337. nyo uu rers 39 2 3 Description of Pin Functions 41 2 3 1 0040 07 0 25 YER EY e bea Sel 41 2 3 2 ROMA oo etr oue ite E eu Eq ets 42 2 3 3 20 0 26 2 52 vie ed uno 42 2 3 4 3040 34 3 5 5 exeo donee ace as Sama qiiem 43 2 3 5 PA0 to P47 POM A ouis vun or PET n gods hag ded sles 43 2 3 6 P50 to P57 Ete Mans Me ete tes 44 2 3 7 P64 P65 and P67 Pott 6 2k aue fee e EO e Re E LE EO art 44 2 3 8 BOE joi iier mA eb ue 44 2 3 9 P120 to P T27 Port 12 ore Perera a peat a eae ee 45 22320 13 ke teres coe mE ele Papae ues 45 2 3 11 P140 to PT47 45 2942 OIXD Acadia ange Gram iene eee 46 2 949 CRAD wits e eei RUD eae DEN bed ween 46 2 944 COMO O COMBS ek 46 2 3 15 Vico to Vice OO ee A eee ee Ne ce ee 46 23 16 GANG D AV Beri DEI oe a pus 46 2 aie Ex Seo ee EEA Ad Poa eds 46
338. o operation with fy 8 0 MHz User s Manual U12670EE3VOUDOO 191 Chapter 10 Watchdog Timer 2 Interval timer mode Interrupts are generated at the preset time intervals Table 10 2 Interval Times Interval Time 21 x 1 fy 512 us 213 x 1 fy 1 ms 214 x 1 fx 2 ms 215 x 1 fx 4 ms 216 x 1 8 19 ms 217 x 1 fx 16 38 ms 218 x 1 fx 32 76 ms 220 x 1 fy 131 ms Remark Figures in parentheses apply to operation with fy 8 0 MHz 192 User s Manual U12670EE3VOUDOO Chapter 10 Watchdog Timer 10 2 Watchdog Timer Configuration The watchdog timer consists of the following hardware Table 10 3 Watchdog Timer Configuration Timer clock select register WDCS Control register Watchdog timer mode register WDTM Figure 10 1 Watchdog Timer Block Diagram Internal Bus INTWDT Maskable Interrupt Request 8 Bit Control Counter Circuit gt RESET INTWDT Non Maskable Interrupt Request RUN Selector WDTM4 WDTM3 Watchdog Timer Mode Register Watchdog Timer Clock Selection Register Internal Bus 193 User s Manual U12670EE3VOUDOO Chapter 10 Watchdog Timer 10 3 Watchdog Timer Control Registers The following two types of registers are used to control the watchdog timer Watchdog timer clock select register WDCS Watchdog timer mode register WDTM 1 Watchdog timer clock s
339. ocol IDTXO to IDTX4 register can be set with a 1 bit or an 8 bit memory manipulation instruction RESET input sets IDTXO to IDTX4 to an undefined value Symbol IDTXO IDTX1 IDTX2 IDTX3 IDTX4 Remark 7 6 ID28 ID27 ID20 ID19 ID17 ID16 ID9 ID8 ID1 IDO 5 ID26 ID18 ID15 ID7 Figure 16 25 Transmit Identifier 4 ID25 ID14 ID6 3 ID24 ID13 ID5 2 ID23 ID12 104 1 22 ID11 ID3 0 ID21 ID10 ID2 Address xxx2H xxx3H 5 6 After Reset R W undefined R W undefined R W undefined R W undefined R W undefined R W If a standard frame is defined by the IDE bit in the TCON byte then IDTXO and IDTX1 are used only IDTX2 to IDTX4 are free for use by the CPU for application needs User s Manual U12670EE3VOUDOO 283 Chapter 16 CAN Coniroller 3 Transmit Data Definition These memory locations set the transmit message data of the data field in the CAN frame DATAO to can be set with a 1 bit or an 8 bit memory manipulation instruction RESET input sets DATAO to DATA7 to an undefined value Figure 16 26 Transmit Data Symbol 7 6 5 4 3 2 1 0 Address After Reset DATA5 xxxDH undefined DATA7 ee XxxFH undefined R R lt W W R W R W R W R W R W R W R W Remark Unused data bytes that
340. ode even when there is ongoing bus activity The wake up is independent from the clock The release time for the CPU Stop mode of the device is of no concern because the DCAN synchronizes again to the CAN bus after clock supply has started User s Manual U12670EE3VOUDOO 321 Chapter 16 CAN Coniroller The following example sketches the general approach on how to enter the DCAN Sleep mode Note that the function may not return for infinite time when the CAN bus is busy The user may apply time out controls to avoid excessive run times Code example DCAN_Sleep_Mode void CANES 0x02 clear Wake bit CANC 0x04 request DCAN Sleep mode while CANES amp 0x02 check if DCAN Sleep mode was accepted CANES 0x02 try again to get DCAN asleep CANC 0x04 The following code example assures a safe transition into CPU Stop mode for all timing scenarios of a suddenly occurring bus activity The code prevents that the CPU gets stuck with its oscillator stopped despite CAN bus activity Code example any application code DCAN_Sleep_Mode request and enter DCAN sleep mode uds any application code DI disable interrupts NOP Nete NOP if wakeup interrupt occurred FALSE the variable wakeup interrupt occurred needs to be initialized at system reset and it needs to be set TRUE when servicing the wake up interrupt CPU_STOP enter CPU Stop mode
341. odes bit in the MCON register of the dedicated mask is set to 0 In this case RTRnggc bit will always be written to 0 together with the update of the IDn bits n 18 to 20 in IDREC1 The received frame type data or remote is defined by the RTR bit in IDCON of the buffer bit in the MCON register of the dedicated mask is set to 1 data and remote frames are accepted In this case the RTR bit in IDCON register has no meaning The received message type passed the mask is shown in RTRpgc bit If a buffer is not dedicated to a mask function mask 1 mask 2 or global mask the IDRECO to IDREC4 registers are only read for comparing All receive identifiers should be defined to 0 before the application sets up its specific values User s Manual U12670EE3VOUD00 Chapter 16 CAN Controller 4 Receive Message Data Part These memory locations set the receive message data part of the CAN protocol DATAO to DATA7 can be set with a 1 bit or an 8 bit memory manipulation instruction RESET input sets DATAO to DATA7 to an undefined value Symbol DATAO DATA1 DATA2 DATA3 DATA4 DATAS DATA6 DATA7 Figure 16 30 Receive Data 7 6 5 4 3 2 1 0 EE pq Address After Reset xxx8H Xxx9H XxxAH xxxBH XxxCH undefined undefined undefined undefined undefined undefined undefined undefined
342. of Reset due to Watchdog Timer Overflow on page 412 and Figure 22 4 Timing of Reset Input in STOP Mode by RESET Input on page 412 Cautions 1 For an external reset apply a low level for 10 us or more to the RESET pin 2 During reset the main system clock oscillation remains stopped but the sub system clock oscillation continues 3 When the STOP mode is cleared by reset the STOP mode contents are held dur ing reset However the port pin becomes high impedance Figure 22 1 Block Diagram of Reset Function e Reset Reset Control Circuit e Signal Watchdog Ti Interrupt Count Clock atchdog Timer Fun tion Stop User s Manual U12670EE3VOUDOO 411 Chapter 22 Reset Function Figure 22 2 Timing of Reset Input by RESET Input oe Ae Be e ViVi 0 Reset Period Oscillation Normal Operation HM lt gt Normal Operation l Oscillation Stop Reset Processing RESET Internal Reset Signal High Impedance Port Pin peperere e E EVE Em E Figure 22 3 Timing of Reset due to Watchdog Timer Overflow DDD Dae PDP Normal Operation e4 Reset Period lt Oscillation Normal Operation Oscillation Stop Stabilization Reset Processing 1 n Watchdog Time Wait Timer Overflow Internal Reset Signal
343. oller security unit etc User s Manual U12670EE3VOUDOO 27 Chapter 1 Outline uPD780948 Subseries 1 3 Ordering Information Part Number Package Internal ROM UPD780948GF A xxx 3BA 100 pin plastic QFP 14 x 20 mm resin thickness 2 7 mm Mask ROM UPD780948GF A1 xxx 3BA 100 pin plastic QFP 14 x 20 mm resin thickness 2 7 mm Mask ROM UPD78F0948GF 3BA 100 pin plastic QFP 14 x 20 mm resin thickness 2 7 mm Flash Memory Remark indicates ROM code suffix 1 4 Quality Grade Part Number Package Quality Grade UPD780948GF A xxx 3BA 100 pin plastic QFP 14 x 20 mm resin thickness 2 7 mm Special UPD780948GF A1 xxx 3BA 100 pin plastic QFP 14 x 20 mm resin thickness 2 7 mm Special UPD78F0948GF 3BA 100 pin plastic QFP 14 x 20 resin thickness 2 7 mm Standard Remark indicates ROM code suffix Please refer to Quality Grades on NEC Semiconductor Device Document No C11531E published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications 28 User s Manual U12670EE3VOUDOO Chapter 1 Outline uPD780948 Subseries 1 5 Pin Configuration Top View e 100 pin plastic QFP 14 x 20 uPD780948GF A xxx 3BA uPD780948GF A1 xxx 3BA uPD78F0948GF 3BA Figure 1 1 Pin Configuration P64 RD P65 WR P67 ASTB P40 ADO P41 AD1 P42 AD2 P43 AD3 P44 AD4 P45 AD5 P46 AD6 P47 AD7 P50 A8 S39 P51 A9 S38
344. ollowing three types of sources a Release by unmasked interrupt request An unmasked interrupt request is used to release the STOP mode If interrupt acknowledge is enabled after the lapse of oscillation stabilization time vectored interrupt service is carried out If interrupt acknowledge is disabled the next address instruction is executed Figure 21 5 STOP Mode Release by Interrupt Generation Wait Time set by OSTS Instruction Standby r Release Signal Operationg Oscillation Stabilization Operating Mode STOP Mode Wait Status spies Oscillation Oscillation Stop Oscillation Clock gt t a Remark The broken line indicates the case when the interrupt request which has cleared the standby status is acknowledged User s Manual U12670EE3VOUDOO 409 Chapter 21 Standby Function b Release by RESET input The STOP mode is cleared and after the lapse of oscillation stabilization time reset operation is carried out Figure 21 6 Release by STOP Mode RESET Input Wait STOP 2 16 3 ms Instruction RESET Se Signal Oscillation Operating Reset Stabilization Operating Mode STOP Mode Period Wait Status Mode Oscillation Oscillation Stop Oscillation Clock a Remarks 1 fx Main system clock oscillation frequency 2 Values in parentheses apply to operation at fx 8 0 MHz Table 21 4 Operation after STOP Mode Release Release Source Operation Next address instruction execut
345. ong as the WAKE bit is set 320 User s Manual U12670EESVOUDOO Chapter 16 CAN Controller 16 17 Influence of the standby Function of the CAN Controller 16 17 1 CPU Halt Mode The CPU halt mode is possible in conjunction with DCAN Sleep mode 16 17 2 CPU Stop Mode The DCAN stops any activity when its clock supply stops due to a CPU Stop mode issued This may cause an erroneous behaviour on the CAN bus Entering the CPU Stop Mode is not allowed when the DCAN is in normal mode i e online to the CAN bus The DCAN will reach an overrun condition when it receives clock supply again CPU Stop mode is possible when the DCAN was set to initialization state sleep mode or stop mode beforehand Note that the CPU will not be started again if the DCAN Stop mode was entered previously 16 17 3 DCAN Sleep Mode The DCAN Sleep mode is intended to lower the power consumption during phases where no communi cation is required The CPU requests the DCAN Sleep mode The DCAN will signal with the WAKE bit if the request was granted or if it is not possible to enter the sleep mode due to ongoing bus activities After a successful switch to the DCAN Sleep mode the CPU can safely go into halt watch or stop mode However the application needs to be prepared that the DCAN cancels the sleep mode any time due to bus activities If the wake up interrupt is serviced the CPU Stop mode has not to be issued Otherwise the CPU will not be released from CPU Stop m
346. onsumption During the operation stop mode the pins be used as normal I O ports as well Register settings The operation stop mode can be set via the serial operation mode register 31 CSIM31 CSIM31 can be set via an 1 bit or an 8 bit memory manipulation instructions The RESET input sets the value to 00H Figure 14 3 Format of Serial Operation Mode Register 31 CSIM31 After Reset lt gt 6 5 4 3 2 1 0 R W Address 51031 Operation Enable Disable Specification Shift register operation Serial counter Port Operation stop Clear Port functionNete Operation enable Count operation enable Serial operation port function Note When CSIE31 0 51031 operation stop status the pins 511 501 can be used for port func tions 228 User s Manual U12670EE3VOUDOO Chapter 14 Serial Interface Channel 31 14 5 2 Two wire serial I O mode The 2 wire serial I O mode is useful when connecting a peripheral I O device that includes a clock syn chronous serial interface a display controller etc This mode executes the data transfer via two lines a serial clock line SCK1 and serial input output line SI1 SO1 1 Register settings The 2 wire serial mode is set via serial operation mode register 31 CSIM31 CSIM31 can be set by an 1 bit or 8 bit memory manipulation instructions The RESET input sets CSIM31 to OOH Figure 14 4 Format of Serial Operation Mode Register 31 CSIM31 lt 7
347. ontrol register 50 Timer clock selection register 50 8 bit timer mode control register 51 Timer clock selection register 51 LCD display mode register LCD display control register A D converter mode register 1 Analog channel select register 1 Power fail comparator mode register X X X X X X X X X x Power fail comparator threshold register Note 2 x D A converter channel 0 mode register UART operation mode register UART receive status register Baud rate generator control register Transmit shift register XI X X X X Receive buffer register Notes 1 Only emulator has this register D78P0308 2 This register is needed for the emulation of power fail detect PFD Function 68 User s Manual U12670EE3VOUDOO Chapter 3 CPU Architecture Table 3 3 Special Function Register List 3 3 Manipulation Bit Address SFR Name Unit 1 bit 8 bit 16 bit Serial mode register 0 CSIM30 Serial mode register 1 CSIM31 Serial I O shift register 31 51031 CAN control register CANC Transmit control register TCR x Received message register RMES Redefinition control register REDEF CAN error status register CANES Transmit error counter TEC Receive error counter REC Message count register MCNT Bit rate prescaler BRPRS Synchronous control register 0 SYNCO Synchronous control register 1 SYNC1
348. ontrollers with on chip flash memory FA 100GF Flash Memory Writing Adapter Flash memory writing adapter used connected to the Flashpro Il and Flashpro Ill FA 100GF 100 pin plastic QFP GF 3BA type User s Manual U12670EE3VOUD00 493 A 3 Debugging Tools A 3 1 Hardware Appendix A Development Tools 1 When using the In Circuit Emulator 78 0 5 IE 78K0 NS A In circuit Emulator The in circuit emulator serves to debug hardware and software when developing application systems using a 78K 0 Series product It corresponds to integrated debugger ID78KO NS This emulator should be used in combination with power supply unit emulation probe and interface adapter which is required to connect this emulator to the host machine IE 70000 MC PS B Power Supply Unit This adapter is used for supplying power from a receptacle of 100 V to 240 V AC EB Power FW 7301 05 Power Supply Unit This adapter is used for supplying power from a receptable of 100 V to 240 V AC IE 70000 98 IF C Interface Adapter This adapter is required when using the PC 9800 series computer except note book type as the IE 78K0 NS A host machine C bus compatible IE 70000 CD IF A PC Card Interface This is PC card and interface cable required when using notebook type computer as the IE 78K0 NS A host machine PCMCIA socket compatible IE 70000 PC IF C Interface Adapter This adapter is required when using
349. op bit detection during a receive operation only applies to a stop bit length of 1 bit 2 Be sure to read the contents of the receive buffer register RXBO when an overrun error has occurred Until the contents of RXBO are read further overrun errors will occur when receiving data 244 User s Manual U12670EE3VOUDOO Chapter 15 Serial Interface UART c Baud rate generator conirol register BRGCO BRGCO can be set via an 8 bit memory manipulation instruction When RESET is input its value is OOH Figure 15 8 Format of Baud Rate Generator Control Register BRGCO 1 2 7 6 5 4 3 2 1 0 RW Address Alter Reset praco _0 TPS02 TPSOT 9690 MOLS MDL MD FFAZH fx 8 00 MHz Source clock selection for 5 bit counter User s Manual U12670EE3VOUDOO 245 Chapter 15 Serial Interface UART Figure 15 8 Format of Baud Rate Generator Control Register BRGCO 2 2 MDLO3 MDLO2 MDLO1 MDLOO Input clock selection for baud rate generator fecil 22 fgcK 23 fscK 24 fgcK 25 26 27 28 29 30 Setting prohibited NI oO BR Caution Writing to BRGCO during a communication operation may cause abnormal output from the baud rate generator and disable further communication operations There fore do not write to BRGCO during a co
350. option register 2 Port mode register 3 RD PortO read signal 4 WR Port 0 write signal User s Manual U12670EE3VOUDOO 87 Chapter 4 Port Functions 4 2 2 Port1 Port 1 is an 8 bit input only port Dual functions include an A D converter analog input Figure 4 3 shows a block diagram of port 1 Figure 4 3 P10 to P17 Configurations 10 0 r to P17 ANI7 Internal bus Remark RD Port 1 read signal 88 User s Manual U12670EE3VOUDOO Chapter 4 Port Functions 4 2 3 Port2 Port 2 is a 7 bit output port with output latch P20 to P26 pins can specify the input mode output mode in 1 bit units with the port mode register 2 PM2 Dual functions include serial interface data input output clock input output When P20 to P24 pins are used as output ports the output buffer is selectable between CMOS type or N channel open drain RESET input sets port 2 to input mode Figure 4 4 shows a block diagram of port 2 Caution When used as a serial interface set the input output and output latch according to its functions For the setting method refer to the Serial Operating Mode Register format Figure 4 4 P20 to P26 Configurations tg WRpeort Selector 20 510 21 800 P22 SCKO P23 SI1 01 P24 SCK1 P25 RxD P26 TxD Internal bus Output Latch P20 to P26 20 to PM26 Dual Function Remarks 1 Port mode register 2
351. or LCD output voltage deviation Note common lo 5pA g Vicpo Vicp LCD output voltage deviation Note segment lo 1 pA Note The voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs Vi cpw 0 1 2 452 User s Manual U12670EE3VOUDOO yPD780948 A Chapter 25 Electrical Specifications LCD C D 1 2 Bias Method Parameter LCD drive voltage Conditions LCD split resistor LCD output voltage deviation Note common Vicbo Vicp Vicpi Vicp x 1 2 Vicpe Vicp X 1 2 LCD output voltage deviation Note segment lo 1 pA Note The voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs Vi cpw 0 1 2 pPD780948 A LCD C D 1 3 Bias Method Parameter LCD drive voltage Symbol Conditions MIN TYP Unit LCD split resistor LCD output voltage deviation Note common Vicpo Vicp Vicpi Vicp x 2 8 Vicpe 1 8 LCD output voltage deviation Note segment lg 2 1 pA Note The voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs Vi cpw 0 1 2 User s Manual U12670EE3VOUDOO 453 Chapter 25 Electrical Specifications 2 pPD780948
352. ort mode register 14 2 Control mode These ports function as segment output signal pins SO to S7 of LCD controller driver User s Manual U12670EE3VOUDOO 45 Chapter 2 Pin Function uPD780948 Subseries 2 3 12 CTXD This pin functions as CAN controller transmit output 2 3 13 CRXD This pin functions as CAN controller receive input 2 3 14 COMO to COM3 These are LCD controller driver common signal output pins 2 3 15 Vico to These are LCD drive voltage pins In the Mask ROM product a split resistor for LCD drive voltage gen eration can be incorporated by a mask option without connecting external split resistors 2 3 16 AVpp AVpreF A D converter reference voltage input pin and the power supply for the A D converter When A D converter is not used connect this pin to Vpp 2 3 17 AVss This is a ground voltage pin of A D converter Always use the same voltage as that of the Vgs pin even when A D converter is not used 2 3 18 RESET This is a low level active system reset input pin 2 3 19 X1 and X2 Crystal resonator connect pins for main system clock oscillation For external clock supply input it to 1 2 3 20 1 2 connection pins for subsystem clock oscillation For external clock supply input it to CL1 and leave CL2 open For CAN clock input it to CL1 and leave CL2 open 2 3 21 Positive power supply pin The power supply Vpp corporates the power supply of
353. ote Refer to Figure 8 3 for details of configurations of 8 bit timer event counters 50 and 51 output control circuits 164 User s Manual U12670EE3VOUD00 Chapter 8 8 Bit Timer Event Counters 50 and 51 Figure 8 3 Block Diagram of 8 Bit Timer Event Counters 50 and 51 Output Control Circuit TMCn1 TMCn6 RESET LVRn LVSn TMCn1 Selector 50 6 50 2 gt TO51 P07 T151 P06 7 Output Latch TMCn6 INTTMn PWM Output Circuit Timer Output F F2 TCEn INTTMn OVFn TOEn Remarks 1 The section in the broken line is an output control circuit 2 n 50 51 1 Compare register 50 and 51 CR50 CR51 These 8 bit registers compare the value set to CR50 to 8 bit timer register 5 TM50 count value and the value set to CR51 to the 8 bit timer register 51 TM51 count value and if they match generate interrupts request INTTM50 and INTTM51 respectively CR50 and 51 are set with an 8 bit memory manipulation instruction They cannot be set with a 16 bit memory manipulation instruction The OOH to FFH values can be set RESET input sets CR50 and CR51 values to 00H Caution To use PWM mode set CRn value before setting TMCn n 50 51 to PWM mode 2 8 bit timer registers 50 and 51 TM50 TM51 These 8 bit registers count pulses 50 and 51 are read with an 8 bit memory manipulation instruction RESET input sets TM50 and 51 to OOH User s Manual U12670E
354. ount Start INTTMn e 5 5 3 g gt A 2 o 3 5 3 S gt 3 A 2 o ron pcs ma m Interval Time Interval Time Interval Time Remarks 1 Interval time N 1 x t N to FFH 2 n 50 51 b When CRn 00H Interval time Remark 50 51 172 User s Manual U12670EE3VOUDOO Chapter 8 8 Bit Timer Event Counters 50 and 51 Figure 8 10 Interval Timer Operation Timings 2 3 c When CRn FFH Count clock SEE G a IL U O s sss H S S E wn Jo I IF 9 TI re rr 00 CRn FF FF FF Tn Interrupt received Interrupt received 1 2 Interval time Remark 50 51 d Operated by CH5n transition lt countelock LJ LJ LJ LILI LILI LI LU Lu TM N FFH TCEn INTTMn i i CRn transition TMn overflows since M N Remark 50 51 User s Manual U12670EE3VOUDOO 173 Chapter 8 8 Bit Timer Event Counters 50 and 51 Figure 8 10 Interval Timer Operation Timings 3 3 e Operated by CR5n transition M N countelock T U LJ LI LI LILI LI LJ n 1 m ot TMn TCEn INTTMn CRn transition Remark 50 51 174 User s Man
355. output by setting the 16 bit timer mode control register TMCO and capture compare control register 0 as shown in Figure 6 10 The PPG output function outputs a rectangular wave with a cycle specified by the count value set in advance to the 16 bit capture compare register 00 CROO and a pulse width specified by the count value set in advance to the 16 bit capture compare register 01 CRO1 Figure 6 10 Control Register Settings in PPG Output Operation a 16 bit timer mode control register TMCO TMCO3 02 01 OVFO SES Clears and starts coincidence between 0 and CROO b Capture compare control register 0 CRCO CRC02 CRCO1 CROO as compare register 01 as compare register 16 bit timer output control register 04 LVSO LVRO 01 TOEO Enables TOO output Reverses output on coincidence between TMO and 00 Specifies initial value of TOO output F F Reverses output on coincidence between TMO and CRO1 Remark x don care Cautions 1 Make sure that 0000H lt 01 lt CROO lt FFFFH is set to CROO and 01 2 The cycle of the pulse generator through PPG output CROO setting value 1 has a duty of 01 setting value 1 CROO setting value 1 132 User s Manual U15251EE3VOUDOO Chapter 6 16 Bit Timer Event Counter 0 6 4 3 Pulse width measurement The 16 bit timer regi
356. output mode Set bit 4 CLOE of clock output selection register to 1 SEL Caution Clock output cannot be used when setting P33 output latch to 1 Remark When clock output enable disable is switched the clock output control circuit does not generate pulses with smaller widths than the original signal carries See the portions marked with in Figure 11 1 Figure 11 1 Remote Controlled Output Application Example PCL P33 SGOA Pin Output 11 User s Manual U12670EE3VOUDOO 199 Chapter 11 Clock Output Control Circuit 11 2 Clock Output Control Circuit Configuration The clock output control circuit consists of the following hardware Table 11 1 Clock Output Control Circuit Configuration Clock output selection register CKS Port mode register 3 PM3 Control register Figure 11 2 Clock Output Control Circuit Block Diagram Selector Synchronizing Circuit gt PCL P33 SGOA L1 Clock Output Selection Register Port Mode Register 3 P33 Output Latch Y Internal Bus 200 User s Manual U12670EE3VOUD00 Chapter 11 Clock Output Control Circuit 11 3 Clock Output Function Control Registers The following two types of registers are used to control the clock output function Clock output selection register CKS Port mode register 3 PM3 1 Clock output selection register CKS This register sets PCL output clock CKS is set with an 1 bit or an 8 bit memory
357. put sets these registers to 00H Figure 19 2 Interrupt Request Flag Register Format Symbol lt gt lt 6 gt lt 5 gt lt 4 gt lt 3 gt lt 2 gt lt gt lt 0 gt Address After Reset R W IFOL PIF1 PIFO 22 TMIF21 TMIF20 OVFIF ADIF TMIF4 FFEOH 00H R W IFOH CSIIFO CTIF1 CTIFO CRIF CEIF PIF4 PIF3 PIF2 FFE1H 00H R W IFiL TMIF51 TMIF50 TMIFO1 TMIFOO STIF SRIF SERIF CSIIF1 FFE2H 00H R W IF1H 0 0 0 0 0 WTIF WTIIF 0 FFESH 00H R W Interrupt request flag 0 No interrupt request signal 1 Interrupt request signal is generated interrupt request state TMIF4 flag is R W enabled only when the watchdog timer is used as an interval timer If used in the watchdog timer mode 1 set TMIF4 flag to 0 2 Set always 0 in IF1H bit 0 and bit 3 to bit 7 Cautions 1 372 User s Manual U12670EE3VOUDOO Chapter 19 Interrupt Functions 2 Interrupt mask flag registers MKOL MK1L The interrupt mask flag is used to enable disable the corresponding maskable interrupt service and to set standby clear enable disable MKOL MK1L and are set with an 1 bit or an 8 bit memory manipulation instruction If MKOL and MKOH are used as a 16 bit register MKO use a 16 bit memory manipulation instruc tion for the setting RESET input sets these registers to FFH Figure 19 3 Interrupt Mask Flag Register Format Symbol 7 2 1 0 Address After
358. quare wave output Interval timer When 16 bit timer event counter is used as an interval timer it generates an interrupt request at predetermined time intervals PPG output 16 bit timer event counter can output a square wave whose frequency and output pulse width can be freely set Pulse width measurement 16 bit timer event counter can be used to measure the pulse width of a signal input from an exter nal source External event counter 16 bit timer event counter can be used to measure the number of pulses of a signal input from an external source Square wave output 16 bit timer event counter can output a square wave any frequency User s Manual U15251EE3VOUDOO 119 Chapter6 16 Timer Event Counter 0 6 2 16 bit Timer Event Counter 0 Configuration 16 bit timer event counter 0 TMO consists of the following hardware Table 6 1 Configuration of 16 bit Timer Event Counter TMO Item Configuration Timer register 16 bits x 1 TMO Register Capture compare register 16 bits x 2 00 01 Timer output 1 TOO 16 bit timer mode control register TMCO Capture compare register 0 CRCO Control register 16 bit timer output control register TOCO Prescaler mode register 0 PRMO Port mode register 7 PM7 Figure 6 1 Block Diagram of 16 Bit Timer Event Counter 0 TMO Internal bus Capture compare control register 0 CRCO CRCO1 CRCOO CRC02
359. quest acknowledge 379 User s Manual U12670EE3VOUDOO 13 19 4 8 Software interrupt request acknowledge operation 382 19 4 4 Multiple interrupt servicing 382 19 4 5 Interrupt request reserve 386 Chapter 20 External Device 389 20 1 External Device Expansion 389 20 2 External Device Expansion Function Control Register 393 20 3 External Device Expansion Function Timing 396 20 4 Example of Connection with 401 Chapter 21 Standby 403 21 4 Standby Function and 403 21 1 1 Standby 41 403 21 1 2 Standby function control register 404 21 2 Standby Function 405 21 2 1 HALET mode x2 ire ey D eR s exe ee oes 405 21225 STOR mode ape ete avo eR Feu eph eu ELE 408 Chapter 22 Reset Function occi iu rrr RERRAER ET TE 411 22 1 Reset Function ccc de culpe Ge eee eee IM ERE 411 Chapter 23 78 094
360. quest acknowledgement and is set to 1 upon El instruction execution b Zero flag 2 When the operation result is zero this flag is set 1 It is reset 0 in all other cases c Register bank select flags RBSO and RBS1 These are 2 bit flags to select one of the four register banks In these flags the 2 bit information which indicates the register bank selected by SEL RBn instruc tion execution is stored d Auxiliary carry flag AC If the operation result has carry from bit 3 or a borrow at bit 3 this flag is set 1 It is reset 0 in all other cases e In service priority flag ISP This flag manages the priority of acknowledge able maskable vectored interrupts When 0 acknowledgment of the vectored interrupt request specified to low order priority with the priority specify flag registers PROL PROH and PR1L is disabled Whether an actual interrupt request is acknowledged or not is controlled with the interrupt enable flag IE f Carry flag CY This flag stores overflow and underflow upon add subtract instruction execution It stores the shift out value upon rotate instruction execution and functions as a bit accumulator during bit manipula tion instruction execution User s Manual U12670EE3VOUDOO 63 Chapter 3 CPU Architecture 3 Stack pointer SP This is a 16 bit register to hold the start address of the memory stack area Only the internal high speed RAM area can be set as the stack area
361. r Noise elimination circuit 16 bit timer register TMO Valid edge of TIOO Noise elimination fx circuit 16 bit capture compare register 01 01 fx 2 fx 2 fx 2 Selector Internal bus Figure 6 23 Timing of External Event Counter Operation with rising edge specified Taeao p e TMO count value _ 0000HX0001HX0002HKOOOSHKO004HYOOOSHX KN 1K X0000HX0001HX0002HX0003HX CROO __ 00 Caution Read 0 when reading the count value of the external event counter 142 User s Manual U15251EE3VOUD00 Chapter 6 16 Bit Timer Event Counter 0 6 4 5 Operation to output square wave The 16 bit timer event counter 0 can be used to output a square wave with any frequency at an interval specified by the count value set in advance to the 16 bit capture compare register 00 CROO By setting bits 0 TOEO and 1 01 of the 16 bit timer output control register to 1 the output status of the TOO pin is reversed at an interval specified by the count value set in advance to CROO In this way a square wave of any frequency can be output Figure 6 24 Set Contents of Control Registers in Square Wave Output Mode a 16 bit timer mode control register 02 TMCO1 OVFO d Clears and starts on coincidence between TMO and CROO
362. r Driver Static LCD Panel Connection Example Figure 17 11 lt o 5 7 2 a gt gt gt gt ol o oO 53 54 58 510 511 512 513 514 aN aJa n njan 0 54 lt LL sseJppe ejeq S23 S24 S25 S32 S36 S37 S38 S39 345 User s Manual U12670EE3VOUDOO Chapter 17 LCD Controller Driver Figure 17 12 Static LCD Drive Waveform Examples 2 Vico COMO Vss1 Vico Vss1 Vico Vss1 COMO S19 0 Vicp Vicp 0 520 0 Vicp 346 User s Manual U12670EE3VOUDOO Chapter 17 LCD Controller Driver 17 8 2 2 time division display example Figure 17 14 shows the connection of a 2 time division type 10 digit LCD panel with the display pattern shown in Figure 17 13 with segment signals SO to S39 and common signals COMO COM1 The dis play example is 123456 7890 and the display data memory contents correspond to this An explanation is given here taking the example of the eighth digit 3 In accordance with the dis play pattern in Figure 17 13 selection and non selection voltages must be output to pins S28 through
363. r Reset FFH After Reset FFH After Reset FFH After Reset FFH After Reset FFH After Reset FFH 99 Chapter 4 Port Functions 2 Pull up resistor option register PUO PU4 and PU13 This register is used to set whether to use an internal pull up resistor at each port or not No on chip pull up resistors can be used to the bits set to the output mode irrespective of PUO PU4 PU7 and PU13 setting PUO PU4 PU7 and PU13 are set with an 1 bit or an 8 bit memory manipulation instruction RESET input sets this register to OOH Caution When PUm is set to 1 the on chip pull up resistors are connected irrespective of the input output mode When using in output mode set the bits of PUm to 0 Figure 4 14 Pull Up Resistor Option Register PUO PU4 and PU13 Format 7 6 5 4 3 2 1 0 RW Address Reset Puo PUo7 Puos Puos PUo4 Puos PUO PUO 00 FF30H OOH 7 6 5 4 3 2 1 0 Address iter Reset pus PU47 PU46 PU45 PU44 PU43 PU42 PU41 PU40 R W FF34H 00H 7 6 5 4 3 2 1 0 RW Address After Reset pu7 77 PU76 PU75 PU74 PU73 PU72 PU71 PU70 R W FF37H 00H 7 6 5 4 3 2 1 0 Address Alter Reset PUmn Pin Internal Pull up Resistor Selection 0 4 7 13 0 7 0 On chip pull up resistor not used 1 On chip pull up resistor used 100 User s Manual U12670EE3VOUD00 Chapter 4 Port Functions 3 Port fu
364. r RX2 Again the message Ox7FFH is stored in buffer in RXO 3 If additionally RXO is configured as a mask the message will be stored 316 User s Manual U12670EESVOUDOO Chapter 16 CAN Controller 16 15 4 Special Functions 1 Redefinition control register This register controls the redefinition of an identifier of a received buffer REDEF can be written with an 1 bit or an 8 bit memory manipulation instruction RESET input sets REDEF to 00H Figure 16 48 Redefinition Control Register 1 2 Symbol lt 7 gt 0 Address After Reset R W R W R W R W R W The redefinition register provides a way to change identifiers and other control information for one receive buffer without disturbing the operation of the other buffers Redefine Permission Bit 0 Normal operation 1 Receive operation for selected message is disabled CPU can change definition data for this message This bit is cleared when INIT bit in CANC is set User s Manual U12670EE3VOUDOO 317 Chapter 16 CAN Coniroller Figure 16 48 Redefinition Control Register 2 2 Buffer selection n 0 15 Buffer 0 is selected for redefinition Buffer 1 is selected for redefinition Buffer 2 is selected for redefinition Buffer 3 is selected for redefinition Buffer 4 is selected for redefinition Buffer 5 is selected for redefinition Buffer 6 is selected for redefinition Buffer 7 is selected for redefinit
365. rame and the counter s division rate 1 16 k Table 15 4 describes the relation between the main system clock and the baud rate and Figure 15 9 shows an example of a baud rate error tolerance range Table 15 4 Relation between Main System Clock and Baud Rate fy 8 386 MHz fy 8 000 MHz fy 5 000 MHz fy 4 1943 MHz 0 5 BRGCO BRGCO ERR BRGCO ERR BRGCO ERR 600 1200 2400 4800 9600 19200 31250 38400 76800 115200 Remarks 1 fy Oscillation frequency of main system clock 2 n Value set via TPSOO to TPS02 1 lt lt 8 3 Value set via MDLOO to MDLO3 0 lt k x 14 Figure 15 9 Error Tolerance when k 0 including Sampling Errors Ideal sampling point 32T 64T 256 288T 320T 352T 304T 336T Basic timing clock cycle stant ro A 597 P High speed clock 15 5 clock cycle T i START D7 P iY stop normal j 0 Sampling error 30 45 60 9 304 5 0 5T Low speed clock 15 5T clock cycle T enabling normal STANT DO 10 UU jg P reception 33 55T 67 1T 301 95T 3355 Remark 5 bit counters source clock cycle 248 15 5 x 100 Baud rate error tolerance when k 0 4 8438 96 320 User s Manual U12670EE3VOUD00 Chapter 15 Serial Interface UART 2 Communication operations a Dat
366. ration as external event 141 6 4 5 Operation to output square 143 6 5 16 Bit Timer Event Counter 0 Operating Precautions 145 Ghapter7 16 2 149 7 1 16 Bit Timer 2 149 7 2 16 Bit Timer 2 150 7 3 16 Bit Timer 2 Control Registers 152 7 44 16 Bit Timer 2 155 7 4 1 Pulse width measurement 155 7 5 16 Bit Timer 2 Precautions 159 Chapter8 8 Bit Timer Event Counters 50 and 51 161 81 8 Timer Event Counters 50 and 51 161 8 2 8 Timer Event Counters 50 and 51 163 8 3 8 Timer Event Counters 50 and 51 Control Registers 166 8 4 8 Timer Event Counters 50 and 51 171 8 4 1 Interval timer operations 8 bit timer event counter 171 8 4 2 External event counter operation 1 176 8 4 3 Sq
367. rcuit TM50 CSIE30 MODEO SCL301 SCL300 User s Manual U12670EE3VOUDOO 219 Chapter 13 Serial Interface Channel 30 13 2 Serial Interface Channel 30 Configuration The 5 0 includes the following hardware Table 13 1 Composition of 51030 Registers Serial I O shift register 30 51030 Control registers Serial operation mode register 30 CSIM30 1 Serial shift register 30 SIO30 This is an 8 bit register that performs parallel serial conversion and serial transmit receive shift operations synchronized with the serial clock SIOSO is set by an 8 bit memory manipulation instruction When 1 is set to bit 7 CSIE30 of the serial operation mode register CSIM30 a serial operation can be started by writing data to or reading data from SIO30 When transmitting data written to SIO30 is output via the serial output SOO When receiving data is read from the serial input SIO and written to 51030 The RESET signal resets the register value to OOH Caution Do not access SIO30 during a transmit operation unless the access is triggered by a transfer start Read is disabled when MODE 0 and write is disabled when MODE 1 13 3 List of SFRs Special Function Registers Table 13 2 List of SFRs Special Function Registers Units available for bit manipulation SFR name Symbol p Value after 1 bit 8 bit 16 bit reset Serial operat
368. re 13 4 Figure 13 5 Figure 14 1 Figure 14 2 Figure 14 3 Figure 14 4 Figure 14 5 Figure 14 6 Figure 15 1 Figure 15 2 Figure 15 3 Figure 15 4 Figure 15 5 Figure 15 6 Figure 15 7 Figure 15 8 Figure 15 9 Figure 15 10 Figure 15 11 Figure 15 12 Figure 15 13 Figure 16 1 Figure 16 2 Figure 16 3 Figure 16 4 PWM Output Operation Timing Active high setting 180 PWM Output Operation Timings CRnO OOH active high setting 180 PWM Output Operation Timings CRn active high setting 181 PWM Output Operation Timings CRn changing active high 181 8 bit Timer Registers 50 and 51 Start 0 182 External Event Counter Operation 182 Timings after Compare Register Change during Timer Count Operation 183 Block Diagram of Watch eene ener nnns 185 Watch Timer Mode Control Register WTM Format 1 2 187 Operation Timing of Watch Timer Interval 190 Watchdog Timer Block 193 Timer Clock Select Register 2 Format sss 194 Watchdog Timer Mode Register 195 Remote Controlled Output Application Example 199 Clock Outpu
369. re 17 1 Figure 17 2 Figure 17 3 Figure 17 4 Figure 17 5 Figure 17 6 Figure 17 7 20 Arbitration Field Extended Format 259 Control Field Standard Format 260 Control Field Extended Format 260 Data Field e decine idee e a da pe gd Mandi lane dd ee 261 GRG uio repr 261 ACK Field iion eerte ce ede Vade erae ge d ac e ae ee ee 262 End of Frarrie i na tisha nie dme ete e een eee 262 Interframe Space Error Active ssssssssssssssseeeeenenn nennen 263 Interframe Space Error Passive ssssssssssseeeeeneneeen enne 263 Error Frame iere nuncu duet 264 Overload Frame itd tet e ce ERR be EH etg tede debuts 265 Nominal Bit Time 8 to 25 Time Quanta sss 271 Adjusting Synchronization of the Data 272 Bit Synchronization pce ehe tee e Tae eg ee eod de d rues 273 Transmission State Shift Chart sese 274 Reception State Shift Chart ennt nnns 275 Error State Shift Chat aie das 276 Structural Block 277 Connection to the CAN Bus ssssssssssssssseeneene nennen nennen nennen 278 Transmit Message Definition 282 Tranismit dentifler er cepe eet perpe 283 Transmit Data pene a cae dee pl
370. red with the count value of the 16 bit timer register When the values of the two coincide an interrupt request 01 is generated b When using 01 as capture register The valid edge of the TIOO pin can be selected as a capture trigger The valid edge of TIOO is spec ified by using the prescaler mode register 0 PRMO R01 is set by a 16 bit memory manipulation instruction After RESET input the value of CROO is undefined Caution Set another value than 0000H to 01 This means that an 1 pulse count operation cannot be performed when 01 is used as an event counter However in the three running mode and in the clear mode using the valid edge of TIOO if 0000H is set to 00 an interrupt request INTTMOO is generated following overflow FFFFH User s Manual U15251EE3VOUDOO 123 6 3 Chapter6 16 Bit Timer Event Counter 0 16 Bit Timer Event Counter 0 Control Register The following four types of registers control 16 bit timer event counter 0 1 16 bit timer mode control register TMCO Capture compare control register e 16 bit timer output control register Prescaler mode register 0 PRMO Port mode register 0 PMO 16 bit timer mode control register TMCO This register specifies the operation mode of the 16 bit timer and the clear mode output timing and overflow detection of the 16 bit timer register TMCO is set by an 1 bit or an 8 bit memory man
371. rone to mis operation due to noise than that of the main system clock Therefore when using the sub System clock take special cautions for wiring methods 450 User s Manual U12670EE3VOUDOO Chapter 25 Electrical Specifications 25 5 DC Characteristics 1 pPD780948 A TA 40 C to 85 C Vpp 4 0 to 5 5 V Parameter Symbol Conditions MIN TYP MAX Unit POO P07 P10 P17 P20 P26 P30 P34 P40 P47 P50 P57 P64 P65 P67 P70 P77 P120 P127 P130 P137 P140 P147 RESET CRXD X1 X2 CL1 POO P07 P10 P17 P20 P26 P30 P34 P40 P47 P50 P57 P64 P65 P67 P70 P77 P120 P127 Low level P130 P137 P140 P147 input voltage RESET CRXD X1 X2 CL1 P07 P10 P17 P20 P26 P30 P34 P40 P47 P50 P57 vy 240 55V P64 P65 P67 P70 P77 P120 P127 P130 P137 P140 P147 CTXD lou 1mA Vpp 4 5 5 5 V SGO lou 20 mA POO P07 P10 P17 P20 P26 P30 P34 P40 P47 50 P57 4 0 5 5 P64 P65 P67 P70 P77 P120 Low level P127 P130 P137 P140 P147 output voltage CTXD lo 1 6 Vpp 4 5 5 5 V SGO lot 20 P00 P07 P10 P17 P20 P26 P30 P34 P40 P47 P50 P57 P64 P65 P67 P70 P77 P120 Vin P127 P130 P137 P140 P147 CRXD ANIO ANI7 X1 X2 CL1 POO P07 P10 P17 P20 P26 P30 P34 P40 P47 P50 P57 P64 P65 P67 P
372. rors in the parity bit the odd number bit can be detected When zero parity or no parity is set errors are not detected Even parity During transmission The number of bits in transmit data that includes a parity bit is controlled so that there are an even number of 1 bits The value of the parity bit is as follows If the transmit data contains an odd number of 1 bits the parity bit value is 1 If the transmit data contains an even number of 1 bits the parity bit value is 0 During reception The number of 1 bits is counted among the transfer data that include a parity bit and a parity error occurs when the result is an odd number Odd parity During transmission The number of bits in transmit data that includes a parity bit is controlled so that there is an odd number of 1 bits The value of the parity bit is as follows If the transmit data contains an odd number of 1 bits the parity bit value is 0 If the transmit data contains an even number of 1 bits the parity bit value is 1 During reception The number of 1 bits is counted among the transfer data that include a parity bit and a parity error occurs when the result is an even number Zero parity During transmission the parity bit is set to 0 regardless of the transmit data During reception the parity bit is not checked Therefore no parity errors will occur regardless of whether the parity b
373. rrupt request acknowledge operation A software interrupt request is acknowledged by BRK instruction execution Software interrupt cannot be disabled If a software interrupt is acknowledged the contents of program status word PSW and program coun ter PC are saved to stacks in this order Then the IE flag is reset to 0 and the contents of the vector tables 003EH and 003FH are loaded into PC and the program branches accordingly Return from the software interrupt is possible with the RETB instruction Caution Do not use the RETI instruction for returning from the software interrupt 19 4 4 Multiple interrupt servicing A multiple interrupt service consists in acknowledging another interrupt during the execution of another interrupt routine A multiple interrupt service is generated only in the interrupt request acknowledge enable state IE 1 except non maskable interrupt As soon as an interrupt request is acknowledged it enters the acknowledge disable state IE 0 Therefore in order to enable multiple interrupts it is necessary to set the interrupt enable state by setting the IE flag 1 with the El instruction during interrupt servicing Even in an interrupt enabled state a multiple interrupt may not be enabled However it is controlled according to the interrupt priority There are two priorities the default priority and the programmable pri ority The multiple interrupt is controlled by the programmable priority control
374. rrupt request sig nal 20 is set Any of three edge specifications can be selected rising falling or both edges by means of bits 2 and 500 and ES01 of PRM2 For valid edge detection sampling is performed at the count clock selected by PRM2 and a capture operation is only performed when a valid level is detected twice thus eliminating noise with a short pulse width Figure 7 5 Configuration Diagram for Pulse Width Measurement by Using the Free Running Counter 16 bit timer register TM2 fx 2 TI20 16 bit capture register 20 CR20 gt INTTM20 2 fx 2 fx 2 x N User s Manual U12670EE3VOUDOO 155 Chapter 7 16 Bit Timer 2 Figure 7 6 Timing of Pulse Width Measurement Operation by Using the Free Running Counter and One Capture Register with Both Edges Specified value Kookoo Koo Kok Yos value PHP 1 TD Tl2m pin L __ 77 777 i RUE Value loaded dec oean dome corp xc 7 0 PL Ll LL IL IL INTOVF Remark mz0to2 156 User s Manual U12670EE3VOUD00 Chapter 7 16 Bit Timer 2 2 Measurement of three pulse widths with the free running counter The 16 bit timer register TM2 allows simultaneous measurement of the pulse widths of the three signals input to the TI20 P30 to TI22 P32 pins When the edge specified by bits 2 and 3 500 and
375. rts 4 to 6 control address data read write strobe wait address strobe etc Table 20 1 Pin Functions in External Memory Expansion Mode Pin function at external device connection Alternate function Name Function ADO to AD7 Multiplexed address data bus P40 to P47 A8 to A15 Address bus P50 to P57 Read strobe signal P64 Write strobe signal P65 Address strobe signal P67 Table 20 2 State of Port 4 to Port 6 Pins in External Memory Expansion Mode Ports and bits Port 5 01234567 Single chip mode Port Port 256 byte expansion mode Address data Port 4 Kbyte expansion mode Address data Address Port 16 Kbyte expansion mode Address data Address Port Full address mode Address data Address User s Manual U12670EE3VOUDOO 389 Chapter 20 External Device Expansion Figure 20 1 Memory Map when Using External Device Expansion Function 1 3 UPD780948 uPD78F0948 Memory map when internal ROM size is 32 Kbytes FFFFH FFOOH FEFFH FBOOH FAFFH FB80H FA7FH 58 57 7 F7DFH F400H FA7FH BFFFH 9000H 8FFFH 8100H 80FFH 8000H 7FFFH 0000H 390 Special Function Registers Internal High Speed RAM Not usable LCD Display RAM Not usable Internal Expansion RAM Full Address Mode when MM2 MM0 111 16 Kbyte Expansion Mode when 2 0 101 4 Kbyte Expansion Mode whe
376. ruction Fetch from External Memory ASTB RD ADO AD7 8 15 ASTB RD ADO AD7 No wait 0 setting Lower Address Operation Code Higher Address b Wait PWO 1 setting Lower Address Operation Code EE NE D 5 8 15 Higher Address Internal Wait Signal 1 clock wait User s Manual U12670EE3VOUDOO 397 398 Chapter 20 External Device Expansion Figure 20 6 External Memory Read Timing a No wait 0 setting ASTB RD ADO AD7 Lower Address Read Data 8 15 X Higher Address ASTB RD ADO AD7 8 15 Internal Wait Signal 1 clock wait b Wait PWO 1 setting Lower Address Read Data X Higher Address User s Manual U12670EE3VOUD00 Chapter 20 External Device Expansion Figure 20 7 External Memory Write Timing a No wait 0 setting ASTB WR ADO AD7 7 JLowerAddress ny A8 A15 Higher Address b Wait PWO 1 setting ASTB WR Hi Z ADO AD7 E See Write Data A8 A15 Higher Address Internal Wait Signal fue g CENT a 1 clock wait ES User s Manual U12670EE3VOUDOO 399 Chapter 20 External Device Expansion Figure 20 8 External Memory Read Modify Write Timing a No wait 0 setting ASTB ___ CIEN RD 5 ReniDsa Wea X A8 A15 b Wait PWO
377. s 315 Redefinition Control Register 1 2 nes 317 initialization FloWw Ghart cue eret e ree 324 Transmit 25 2 eere eret a nene eue eee ene o dede 325 TransrmitzADOIE eer 326 Handling of Semaphore Bits by 327 Receive with Interrupt Software 328 Receive Software Polling diea dde 329 LCD Controller Driver Block 332 LCD Clock Select Circuit Block 333 LCD Display Mode Register LCDM 334 LCD Display Control Register LCDC 335 Relationship between LCD Display Data Memory Contents Segment Common Outputs sess nens 336 Common Signal and Static Signal Voltages and 339 LCD Drive Power Supply Connection Examples with External Split Resistor 1 2 340 User s Manual U12670EE3VOUD00 Figure 17 8 Figure 17 9 Figure 17 10 Figure 17 11 Figure 17 12 Figure 17 13 Figure 17 14 Figure 17 15 Figure 17 16 Figure 17 17 Figure 17 18 Figure 17 19 Figure 17 20 Figure 17 21 Figure 17 22 Figure 17 23 Figure 18 1 Figure 18 2 Figure 18 3 Figure 18 4 Figure 18 5 Figure 18 6 Figure 18 7
378. s carried out when an instruction with the following operand format is executed When an 8 bit register is specified one of the eight registers is specified with 3 bits in the operation code Operand format Table 3 5 Register Addressing r X A C B E D L H rp AX BC DE HL and rp can be described with function names X A B E D L H BC DE and HL as well as absolute names RO to R7 and RPO to RP3 Description example Figure 3 15 Register Addressing a MOV A C when selecting C register as r Operation code 01100010 Register specify code b INCW DE when selecting DE register pair as rp Operation code 10000100 Register specify code User s Manual U12670EE3VOUDOO 75 Chapter 3 CPU Architecture 3 4 3 Direct addressing The memory indicated by immediate data in an instruction word is directly addressed Operand format Table 3 6 Direct addressing addr16 Label or 16 bit immediate data Description example MOV A OFEOOH when setting addr16 to Figure 3 16 Direct addressing Operation code 10001110 OP code 00000000 OOH 11111110 FEH 76 User s Manual U12670EE3VOUDOO Chapter 3 CPU Architecture 3 4 4 Short direct addressing The memory to be manipulated in the fixed space is directly addressed with 8 bit data in an instruction word The fixed space to which this addressing is applied to is the 256 b
379. s is not affected However delete the instruction that manipulates this register from the program at the final stage of debugging 2 Bits 7 to 1 must be set to 0 218 User s Manual U12670EE3VOUDOO Chapter 13 Serial Interface Channel 30 13 1 Serial Interface Channel 30 Functions The SIO30 has the following two modes Operation stop mode e 3 wire serial I O mode 1 Operation stop mode This mode is used if serial transfer is not performed For details see 13 5 1 Operation stop mode on page 222 2 3 wire serial mode fixed as MSB first This is an 8 bit data transfer mode using three lines a serial clock line SCKO serial output line SOO and serial input line SIO Since simultaneous transmit and receive operations are enabled in 3 wire serial I O mode the processing time for data transfers is reduced The first bit in the 8 bit data in serial transfers is fixed as the MSB 3 wire serial I O mode is useful for connection to a peripheral I O device that includes a clock syn chronous serial interface like a display controller etc For details see 13 5 2 Three wire serial I O mode on page 223 Figure 13 1 shows a block diagram of the SIO30 Figure 13 1 Block Diagram of SIO30 Internal bus 30 51030 SIO P20 D Y Serial I O shift register 500 21 O SCKO P22 gt Serial clock INTCSIO counter signal generator Serial clock Select s PME elector X control ci
380. s operating When the values of TM5n and CR5n match the timer output flip flop inverts Also INTTM5n is generated and TM5n is cleared to 00H 4 Then the timer output flip flop is inverted for the same interval to output a square wave from TO5n 915 Caution When TI50 P06 TO50 51 07 51 is used as the timer output set port mode register 00 or 07 and output latch to 0 Remark 50 51 User s Manual U12670EE3VOUDO00 177 Chapter 8 8 Bit Timer Event Counters 50 and 51 Figure 8 14 Square wave Output Operation Timing gamd LT LI LIL SU UU UU LeU UU TMn count value KotH XoaHX N ___ N Xo A Count start TOn CRn Note N Note TOn output initial value can be set by bits 2 and LVRn LVSn of the 8 bit timer mode control register TCMn Remark TCL502 50 51 Table 8 8 8 Bit Timer Event Counters 50 Square Wave Output Ranges 8 Bit Timer Event Counter Mode TCL501 TCL500 Minimum Pulse Time 1 fx 125 ns Maximum Pulse Time 28 x 1 fy 32 us Resolution 1 fx 125 ns 2 x 1 fy 250 ns 29 x 1 fx 64 ms 2 x 1 fy 250 ns 23 x 1 fy 1 us 21 x 1 fy 256 ms 23 x 1 fy 1 us 2 x 1 4 us 213 x 1 fy 1 ms 2 x t fy 4 us 27 x 1 fx 16 us 215 x 1 fx 4 ms 2 x 1 fx 16 us TCL502 29 x 1 fx 64 us 217 x 1 fx 16 ms 29 x 1 fy 64 us
381. s the number of waits when external memory expansion area is read from mis the number of waits when external memory expansion area is written to User s Manual U12670EE3VOUDOO 431 Chapter 24 Instruction Set Table 24 2 Operation List 8 8 Instruction Group Mnemonic Operands Operation saddr bit addr16 sfr bit addr16 A bit addr16 PSW bit addr16 HL bit addr16 saddr bit addr16 sfr bit addr16 A bit addr16 PSW bit addr16 HL bit addr16 Co PC amp PC jdisp8 if saddr bit 1 PC amp PC 4 jdisp8 if sfr bit 1 PC amp PC 3 jdisp8 if A bit 1 PC amp PC 3 jdisp8 if PSW bit 1 PC amp PC 3 jdisp8 if HL bit 1 PC amp PC 4 jdisp8 if saddr bit 0 PC amp PC 4 jdisp8 if sfr bit 0 PC lt PC 3 jdisp8 if A bit 0 PC amp PC 4 jdisp8 if PSW bit 0 PC amp PC 3 jdisp8 if HL bit 0 PC amp PC 4 jdisp8 saddr bit addr16 if saddr bit 1 then reset saddr bit PC amp PC 4 jdisp8 if sfr bit 1 then reset sfr bit PC amp PC 3 jdisp8 if A bit 1 then reset A bit PC amp PC 4 jdisp8 if PSW bit 1 then reset PSW bit PC amp PC 3 jdisp8 if HL bit 1 then reset HL bit B B 1 then PC amp PC 2 jdisp8 if B 0 C C 1 then PC 2 jdisp8 if C 0 saddr lt saddr 1 then PC c PC 3 jdisp8 if saddr 0 RBn RBS1 0 lt n No Operation
382. se ports function as high order address bus pins A8 to A15 in external memory expansion mode or as segment signal output pins S32 to S39 of LCD controller driver output 2 3 7 P64 P65 and P67 Port 6 This is a 3 bit input output port Besides serving as input output port they are used for control in exter nal memory expansion mode The following operating modes can be specified bit wise 1 Port mode These ports function as 3 bit input output ports They can be specified bit wise as input or output ports with port mode register 6 2 Control mode These ports function as control signal output pins RD WR ASTB in external memory expansion mode therefore a pin has to be used as a control signal output 2 3 8 P70 to P77 Port 7 This is an 8 bit input output port In addition to its use as an input output port it is also used as segment signal output of the LCD controller driver The following operating modes can be specified bit wise 1 Port mode Port 7 functions as a 8 bit input output port Bit wise specification as an input port or output port is possible by means of port mode register 7 When used as input ports pull up resistors can be connected by defining the pull up resistor option register 7 2 Control mode Port 7 functions as segment signal output pins S24 to S31 of LCD controller driver 44 User s Manual U12670EE3VOUD00 Chapter 2 Pin Function uPD780948 Subseries 2 3 9 P120 to P127 Port 12
383. ser s Manual U12670EE3VOUD00 Chapter 14 Serial Interface Channel 31 14 1 Serial Interface Channel 31 Functions SIO31 has the following two modes 1 2 SM SO1 P23 O 2 D Serial I O shift register Operation stop mode 2 wire serial mode Operation stop mode This mode is used if serial transfer is not performed For details see 14 5 1 Operation stop mode on page 228 2 wire serial mode fixed as MSB first This is an 8 bit data transfer mode using two lines a serial clock line SCK1 and a serial input output line SIO1 Since simultaneous transmit and receive operations are enabled in 2 wire serial I O mode the processing time for data transfers is reduced The first bit in the 8 bit data in serial transfers is fixed as the MSB 2 wire serial I O mode is useful for connection to a peripheral I O device that includes a clock syn chronous serial interface like a display controller etc Figure 14 1 shows a block diagram of the SIO31 macro Figure 14 1 Block Diagram of SIO31 Macro Internal bus 31 SIO31 1 24 gt 4 Serial clock Interruption request INTCSH counter signal generator I fx 28 Selector x27 lt TM50 CSIE31 MODE1 SCL311 SCL310 User s Manual U12670EE3VOUDOO 225 Chapter 14 Serial Interface Channel 31 14 2 Serial Interface Channel 31 Configuration
384. shows block diagrams of port 6 Figure 4 8 P64 P65 and P67 Configurations Selector eo 22 g Output Latch PENR 2 P64 P65 P67 P67 ASTB PM64 PM65 PM67 Remarks 1 Port mode register 2 RD Port6 read signal 3 WR Port 6 write signal User s Manual U12670EE3VOUDOO 93 Chapter 4 Port Functions 4 2 8 Port 7 This is an 8 bit input output port with output latches Input mode output mode can be specified in 1 bit units with a port mode register 7 When P70 to P77 are used as input pins an on chip pull up resistor can be connected bit wise with the pull up resistor option register PU7 Dual functions include segment signal output of LCD controller driver RESET input sets the input mode Port 7 block diagram is shown in Figure 4 9 Caution When used as segment lines set the port function PF7 according to its functions Figure 4 9 P70 to P77 Configurations WRpeuo o 2 a g 9 Output Latch P70 S21 P70 to P77 40 4 to P77 S28 PM70 to PM77 Dual Function Remarks 1 PU Pull up resistor option register 2 PM Port mode register 3 RD Port7 read signal 4 WR Port 7 write signal 94 User s Manual U12670EE3VOUDOO Chapter 4 Port Functions 4 2 9 Port 12 This is an 8 bit input output port with output latches Input mode output mode can be specified in 1 bit units with the port mode register 12
385. sonator Recommended circuit Parameter Test Conditions MIN TYP MAX Unit 4 0 V lt Vpp lt 5 5V R 510 KQ Note 2 33 pFNote 2 Note 1 Oscillator frequency fxr Note 1 CL1 Input 4 0 V lt Vpp lt 5 5 V frequency fxr External clock Note 3 CL1 Input high low level 4 0 V lt Vpp lt 5 5 V width berg Notes 1 Only oscillator circuit characteristics are shown Regarding instruction execute time please refer to AC characteristics Reference data CAN operation with external clock Cautions 1 When using the subsystem clock oscillation circuit wiring in the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance Wiring should be as short as possible Wiring should not cross other signal lines Wiring should not be placed close to a varying high current The potential of the oscillation circuit capacitor ground should always be the same as that of Vss Do not ground wiring to a ground pattern in which a high current flows Donotfetch a signal from the oscillation circuit 2 The subsystem clock oscillation circuit is designed to be a circuit with a low amplification level for low power consumption more prone to mis operation due to noise than that of the main system clock Therefore when using the sub System clock take special cautions for wiring methods 448 User
386. sses FA58H to FA7FH The data stored in the LCD display data memory can be displayed on an LCD panel by the LCD controller driver Figure 17 5 shows the relationship between the LCD display data memory contents and the segment outputs common outputs Any area not used for display can be used as normal RAM Caution Remark 336 Address FA7FH FA7CH FA7DH FA7CH FASAH FA59H FA58H Figure 17 5 Relationship between LCD Display Data Memory Contents and Segment Common Outputs b7 be bs ba bs be bi bo feces M i 50 147 ide GE 1 146 Lect 1 2 145 MD i 53 144 EM EFE ipsun ee 1 1 1 1 1 cu 1 1 MORET S37 P52 ML ELLE S38 P51 D EE i S39 P50 1 1 ff COM3 COM2 COM1 COMO The higher 4 bits of the LCD display data memory do not incorporate memory Be sure to set them to 0 The data of SO is stored at the highest address in the LCD display data memory User s Manual U12670EE3VOUD00 Chapter 17 LCD Controller Driver 17 6 Common Signals and Segment Signals An individual pixel on an LCD panel lights when the potential difference of the corresponding common signal and segment signal reaches or exceeds a given voltage the LCD drive voltage cp As
387. st contact NEC Electronics sales representative in advance to determine NEC Electronics s willingness to support a given application Notes 1 NEC Electronics as used in this statement means NEC Electronics Corporation and also includes its majority owned subsidiaries 2 NEC Electronics products means any product developed or manufactured by or for NEC Electronics as defined above M8E 02 10 User s Manual U12670EE3VOUDOO 3 Regional Information Some information contained in this document may vary from country to country Before using any NEC product in your application please contact the NEC office in your country to obtain a list of authorized representatives and distributors They will verify e Device availability e Ordering information e Product release schedule e Availability of related technical literature e Development environment specifications for example specifications for third party tools and components host computers power plugs AC supply voltages and so forth e Network requirements In addition trademarks registered trademarks export restrictions and other legal issues may also vary from country to country NEC Electronics Inc U S Santa Clara California Tel 408 588 6000 800 366 9782 Fax 408 588 6130 800 729 9288 NEC Electronics Europe GmbH Duesseldorf Germany Tel 0211 65 03 01 Fax 0211 65 03 327 Sucursal en Espa a Madrid Spain 091 504 27 87 Fax 091
388. standby function is used first clear bit 7 CS to 0 to stop the A D conversion operation and then execute the HALT or STOP Insiruction Note The data memory low voltage depends on the operating temperature of the device User s Manual U12670EE3VOUDOO 403 Chapter 21 Standby Function 21 1 2 Standby function control register A wait time after the STOP mode is cleared upon interrupt request till the oscillation stabilizes is control led with the oscillation stabilization time select register OSTS OSTS is set with an 8 bit memory manipulation instruction RESET input sets OSTS to 04H However it takes 2174 until the STOP mode is cleared by RESET input Figure 21 1 Oscillation Stabilization Time Select Register Format Symbol 7 6 1 0 Address After Reset R W 5 4 3 2 Selection of Oscillation Stabilization Time when STOP Mode is Released 2124 512 us 214 2 ms 2 5 fy 4 1 ms 2164 8 9 ms 0 2174 16 38 ms Other than above Setting prohibited Caution The wait time after STOP mode clear does not include the time see a in the Figure 21 2 below from STOP mode clear to clock oscillation start regardless of clearance by RESET input or by interrupt generation Figure 21 2 Standby Timing STOP Mode Clear X1 Pin Voltage Waveform Vss Remarks 1 fy Main system clock oscillation frequency 2 Values in parentheses apply to operating at fy 8 00 MHz
389. standby mode is immediately cleared if set Thus the STOP mode is reset to the HALT mode immediately after execution of the STOP instruction After the wait time set using the oscillation stabilization time select register OSTS the operating mode is set The operating status in the STOP mode is described below Table 21 3 STOP Mode Operating Status STOP mode setting With subsystem clock Without subsystem clock Clock generator CPU Only main system clock stops oscillation Operation stops Port output latch Operation stops 16 bit timer event counter 0 Operable when is selected as count clock 16 bit timer TM2 Operation stops 8 bit timer event counter TM50 TM51 Operable when TI50 or 51 are selected as count clock Watch timer Operable when fxr is selected as Operation stops count clock p p Watchdog timer Operation stops A D converter Operation stops Serial I F Operable at external SCK CAN Operation stops Sound generator Operation stops External interrupt INTPO to INTP4 Operable LCD C D Operation stops Bus lines in external expansion ADO to AD7 High impedance 8 to A15 Status before STOP mode is held PSTB Low level WR RD 408 High level User s Manual U12670EE3VOUD00 Chapter 21 Standby Function 2 STOP mode release The STOP mode can be cleared with the f
390. ster TMO can be used to measure the pulse widths of the signals input to the TIOO and TIO1 pins Measurement can be carried out with TMO used as a free running counter or by restarting the timer in synchronization with the edge of the signal input to the TIOO pin 1 Pulse width measurement with free running counter and one capture register If the edge specified by the prescaler mode register 0 PRMO is input to the TIOO pin when the 16 bit timer register TMO is used as a free running counter refer to Figure 6 11 the value of TMO is loaded to the 16 bit capture compare register 01 01 and an external interrupt request signal 01 is set The edge is specified by using bits 6 and 7 ES10 and ES11 of the prescaler mode register 0 PRMO The rising edge falling edge or both the rising and falling edges can be selected The valid edge is detected through sampling at a count clock cycle selected by the prescaler mode register On PRMO and the capture operation is not performed until the valid level is detected two times Therefore noise with a short pulse width can be rejected Remark Figure 6 11 Control Register Settings for Pulse Width Measurement with Free Running Counter and One Capture Register a 16 bit timer mode control register TMCO 02 01 OVFO EROR ERES Free running mode b Capture compare control register 0 CRCO CRC02 CRCO1
391. sters Table 15 2 List of SFRs Special Function Registers Units available for bit manipulation SFR name 1 bit 8 bit 16 bit Transmit shift register Receive buffer register Asynchronous serial interface mode register Asynchronous serial interface status register Baud rate generator control register User s Manual U12670EE3VOUDOO 235 Chapter 15 Serial Interface UART 15 4 Serial Interface Control Registers The UART uses the following three types of registers for control functions Asynchronous serial interface mode register ASIMO Asynchronous serial interface status register 5150 Baud rate generator control register BRGCO 1 Asynchronous serial interface mode register ASIMO This is an 8 bit register that controls the UART serial transfer operation ASIMO can be set by an 1 bit or an 8 bit memory manipulation instructions RESET input sets the value to OOH Figure 15 2 shows the format of ASIMO Figure 15 2 Format of Asynchronous Serial Interface Mode Register ASIMO 1 2 T dgs 5 4 3 2 1 0 RM Address iter Reset Operation mode Operation stop RXD P25 pin function Port function TXD P26 pin function Port function UARTO mode receive only Serial operation Port function UARTO mode transmit only UARTO mode transmit and receive Port function Serial operation Serial operation Serial operation
392. system clocks for low power consumption operations and clock opera tions connect the CL1 and CL2 pins as follows CL1 Connect to Vpp or GND CL2 Open 114 User s Manual U12670EE3VOUD00 Chapter 5 Clock Generator 5 5 Clock Generator Operations The clock generator generates the following various types of clocks and controls the CPU operating mode including the standby mode Main system clock fy e Subsystem clock fxr CPU clock Clock to peripheral hardware The following clock generator functions and operations are determined with the processor clock control register PCC a Upon generation of RESET signal the lowest speed mode of the main system clock 4 us when operated at 8 0 MHz is selected PCC 04H Main system clock oscillation stops while low level is applied to RESET pin b With the main system clock selected one of the five CPU clock stages fx fy 2 fx 2 f 28 or fx 2 be selected by setting the PCC c With the main system clock selected two standby modes the STOP and HALT modes are available d The PCC can be used to select the subsystem clock and to operate the system with low cur rent consumption 122 us when operated at 32 768 KHz e With the subsystem clock selected main system clock oscillation can be stopped with the PCC The HALT mode can be used However the STOP mode cannot be used Subsystem clock oscillation cannot be stopped User s Manual U12670
393. t CY lt HL bit saddr bit saddr bit lt 1 sfr bit sfr bit 1 A bit A bit lt 1 PSW bit PSW bit 1 HL bit HL bit 1 saddr bit saddr bit lt 0 sfr bit sfr bit 0 A bit A bit lt 0 PSW bit HL bit PSW it 0 HL bit 0 CY CY lt 1 lt 0 PT PY PY P PO PO O N CY lt When the internal high speed RAM area is accessed or instruction with no data access When an area except the internal high speed RAM area is accessed Except A Only when rp BC DE or HL 430 instruction clock cycle is one cycle of the CPU clock fcpy selected by the PCC register This clock cycle applies to internal ROM program nis the number of waits when external memory expansion area is read from mis the number of waits when external memory expansion area is written to User s Manual U12670EE3VOUD00 Instruction Group Chapter 24 Instruction Set Table 24 2 Operation List 7 8 Mnemonic Operands Operation SP 1 SP 2 PC 584419 PC lt 00 16 SP SP 2 SP 1 2 y SP 2 PC laddr1 1 t 2 PCi5 11 00001 0 0 lt addr11 SP lt SP 2 SP
394. t 1 3 SFR Name Port 0 Manipulation Bit Unit 1 bit x 8 bit x 16 bit Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 12 Port 13 Port 14 x x X X X X X X X X X X 16 bit timer counter register 0 8 bit timer register 50 R 8 bit timer register 51 R FF14H CROOL R x 00H 16 bit capture compare register 00 CROO FF15H CROOH R x 00H FF16H CRO1L R x 00H 16 bit capture compare register 01 CRO01 FF17H CRO1H R x 00H FF18H register 50 CR50 00H FF19H register 51 CR51 RW x 00H FF1BH conversion result register ADCR1 R x 00 FF1FH Serial I O shift register 30 SIO30 R W x 00H FF20H Port mode register 0 PMO RW x x FFH FF22H Port mode register 2 PM2 RW x x FFH FF23H Port mode register 3 RW x x FFH FF24H Port mode register 4 PM4 RW x x FFH FF25H Port mode register 5 PM5 RW x x FFH FF26H Port mode register 6 PM6 RW x x FFH FF27H Port mode register 7 PM7 RW x x FFH FF2CH mode register 12 PM12 x x FFH FF2DH Port mode register 13 PM13 RW x x FFH FF2EH mode register 14 PM14 RW x x FFH FF30H Pull up resistor option register 0 PUO RW x x 00
395. t Control Circuit Block Diagram sese 200 Timer Clock Select Register 0 Format sse 201 Port Mode Register 6 202 A D Converter Block 203 Power Fail Detection Function Block 204 A D Converter Mode Register ADM1 206 Analog Input Channel Specification Register ADS1 207 Power Fail Compare Mode Register 208 Power fail compare threshold value register 208 Basic Operation of 8 Bit A D Converter 210 Relation between Analog Input Voltage and A D Conversion Result 212 A D CONVEFSION nere rp Le ne dude ege dt de ee ee 214 Example Method of Reducing Current Consumption in Standby Mode 215 Analog Input Pin enne 216 A D Conversion End Interrupt Request Generation 217 D A Converter Mode Register DAMO 218 Block Diagram of SIO3O sssssssssssssseseeeeeen nennen nennen nennen 219 Format of Serial Operation Mode Register 30 51 0 221 Format o
396. t can be used as a segment signal output port or an I O port in 8 bit units by setting the port function register 523 516 Input Output P130 P137 Port 13 8 bit input output port input output mode can be specified bit wise If used as an input port a pull up resistor can be connected by software This port can be used as a segment signal output port or an I O port in 8 bit units by setting the port function register Input Output 38 P140 P147 Port 14 8 bit input output port input output mode can be specified bit wise This port can be used as a segment signal output port or an I O port in 8 bit units by setting the port function register User s Manual U12670EE3VOUD00 2 2 Non Port Pins Pin Name Input Output Table 2 2 Non Port Pins 1 2 Function External interrupts with specifiable valid edges ris ing edge falling edge both rising and falling edges Chapter 2 Pin Function uPD780948 Subseries After Reset Alternate Function Pin 1 2 2 P04 TIO1 Input Serial interface serial data input P20 P23 SO1 Output Serial interface serial data output P21 23 511 Input Output Serial interface serial clock input output P22 P24 Input Asynchronous serial interface data input P25
397. t counter 51 output control circuit It selects the R S flip flop timer output F F 1 2 setting resetting active level in PWM mode inver sion enabling disabling in modes other than PWM mode and 8 bit timer event counter 51 timer output enabling disabling TMC51 is set with an 1 bit or an 8 bit memory manipulation instruction RESET input sets TMC51 to 00H Figure 8 7 8 Bit Timer Mode Control Register 51 Format 1 2 d 6 5 4 lt 3 gt 285 1 0 R W Address Reset TOE51 8 Bit Timer Event Counter 51 Output Control 0 Output disabled Port mode 1 Output enabled In PWM Mode In Other Mode Active level selection Timer output F F1 control TMC511 Active high Inversion operation disabled Active low Inversion operation enabled 8 Bit Timer Event Counter 51 Timer Output F F1 Status Setting No change Timer output F F1 reset 0 Timer output F F1 set 1 Setting prohibited TMC514 Individual of cascade mode connection 0 Individual mode 8 bit timer counter mode 1 Cascade connection mode 16 bit timer counter mode User s Manual U12670EE3VOUDOO 169 Chapter 8 8 Bit Timer Event Counters 50 and 51 Figure 8 7 8 Bit Timer Mode Control Regisiter 51 Format 2 2 TMC516 8 Bit Timer Event Counter 51 Operating Mode Selection 0 Clear amp start mode on match of TM51 and CR51 1 PWM mode free running TCE51 8 Bit Timer Register 51 Operation Control 0 Operation Stop
398. t external fetch tRDAST 0 8 tey 15 1 2 toy Address hold time from RD 7 at external fetch tRDADH 0 8 tey 15 1 2 tcv 30 Write data output time from RD 7 tRDWD 40 Write data output time from WR T tWRDWD 10 60 Address hold time from WR T Remarks 1 4 2 C 100 pF C are capacitances of ADO to 07 A8 to A15 RD WR ASTB twRADH 3 indicates the number of waits 468 0 8 toy 15 User s Manual U12670EE3VOUD00 1 2 toy 4 30 Chapter 25 Electrical Specifications AC Timing Test Points excluding X1 CL1 inputs 0 8 Voo 1 0 8 0 2 Test pints 0 2 Voo Clock Timing E 1 fx gt X1 Input CL1 Input 0 5 V nps 0 4 V TI Timing TIOO 01 TI20 21 22 User s Manual U12670EE3VOUDOO 469 A8 A15 ADO AD7 ASTB A8 A15 ADO AD7 ASTB 470 Chapter 25 Electrical Specifications Lower 8 bit address Read Write Operation External fetch no wait Upper lower 8 bit address taps tasTH tRDD gt 8 tRDADH gt 4 tRDAST Lower 8 bit address gt lt a iRDH External fetch wait insertion Upper lower 8 bit address taps tAsTH e tRDADH gt tRDAST gt
399. t mode register Port 13 read signal Port 13 write signal User s Manual U12670EE3VOUD00 P130 S15 to P137 S8 Chapter 4 Port Functions 4 2 11 Port 14 This is an 8 bit input output port with output latches Input mode output mode can be specified in 1 bit units with the port mode register 14 These pins are dual function pins and serve as segment signal output of LCD controller driver RESET input sets the input mode The port 14 block diagram is shown in Figure 4 12 Caution Figure 4 12 P140 to P147 Configurations RD UTE WRpeort Output Latch A P140 to P147 Internal bus PM140 to PM147 Dual Function Remarks 1 Port mode register 2 RD Port 14 read signal 3 WR Port 14 write signal User s Manual U12670EE3VOUDOO When used as segment lines set the port function PF14 according to its functions P140 S7 to 147 50 97 Chapter 4 Port Functions 4 3 Port Function Control Registers The following four types of registers control the ports Port mode registers PM2 to PM7 PM12 PM13 14 Pull up resistor option register PUO PU4 PU7 PU13 Port function registers PF2 PF5 PF7 PF12 PF13 PF14 Memory expansion mode register 1 Port mode registers PM2 to PM7 PM12 PM13 14 These registers are used to set port input output in 1 bit units PMO
400. t mode register 3 Control mode These ports function as timer input clock output and sound generator output TI20 21 and TI22 Pin for external capture trigger input to the 16 bit timer capture registers of TM2 b PCL Clock output pin c SGO SGOA and SGOF Pins for separate or composed signal output of the sound generator 2 3 5 P40 to P47 Port 4 This is an 8 bit input output port Besides serving as input output port they function as an address data bus The following operating mode can be specified in 8 bit units 1 2 Port mode These ports function as 8 bit input output ports They can be specified in 8 bit units for input or output ports by using the memory expansion mode register When they are used as input ports pull up resistors can be connected bit wise by defining the pull up resistor option register 4 Control mode These ports function as low order address data bus pins ADO to AD7 in external memory expan sion mode User s Manual U12670EE3VOUDOO 43 Chapter 2 Pin Function uPD780948 Subseries 2 3 6 P50 to P57 Port 5 This is an 8 bit input output port Besides serving as input output port they function as an address bus and LCD controller driver The following operating modes can be specified bit wise 1 Port mode These ports function as 8 bit input output ports They can be specified bit wise as input output ports with port mode register 5 2 Control mode The
401. t time of watch timer l Interval timer interrupt INTWTI En JL TL TL Interval timer T MERE T Remark fw Watch timer clock frequency Caution If the watch timer and 5 bit counter are enabled by the watch timer operation mode control register 0 WDTMO the time from this setting to the occurrence of the first interrupt request INTWDT is not exactly the value set by bits 2 and 3 of WTM This is because the 5 bit counter is late by one output cycle of the 11 bit prescaler in starting to count The second INTWT signal and those that follow are generated exactly at the set time 190 User s Manual U12670EESVOUDOO Chapter 10 Watchdog Timer 10 1 Watchdog Timer Functions The watchdog timer has the following functions Watchdog timer Interval timer Caution Select the watchdog timer mode or the interval timer mode with the watchdog timer mode register WDTM 1 Watchdog timer mode Upon detection of an inadvertent program loop a non maskable interrupt request or RESET can be generated Table 10 1 Watchdog Timer Inadvertent Program Overrun Detection Times Runaway Detection Time 212 x 1 512 us 213 x 1 fx 1 ms 21 x 1 fx 2 ms 215 x 1 fx 4 ms 216 x 1 8 19 ms 217 x 1 fy 16 38 ms 218 x 1 fy 32 76 ms 220 x 1 fy 131 ms Remark Figures in parentheses apply t
402. tatic type 5 digit LCD panel with the display pattern shown in Figure 17 10 with segment SO to S39 and common COMO signals The display example is 123 45 and the display data memory contents addresses FA68H to FA27H correspond to this An explanation is given here taking the example of the third digit 3 3 In accordance with the dis play pattern in Figure 17 10 selection and non selection voltages must be output to pins S16 through 523 as shown in Table 17 6 at the COMO common signal timing Table 17 6 Selection and Non Selection Voltages COMO Segment 516 S17 S18 S19 S20 S21 22 23 Common Remark S Selection NS Non selection From this it can be seen that 10101111 must be prepared in the BITO bits of the display data memory corresponding to S16 to S23 The LCD drive waveforms for S19 S20 and COMO are shown in Figure 17 12 When S19 is at the selection voltage at the timing for selection with COMO it can be seen that the V cp Vi cp AC square wave which is the LCD illumination ON level is generated Shorting the COMO through COMS lines increases the current drive capability because the same wave form as COMO is output to COM1 through Figure 17 10 Static LCD Display Pattern and Electrode Connections Sen 4 _ 2 CL L2 _ Sens COMO N O Sm Sen 7 Remark n 0to4 344 User s Manual U12670EE3VOUDOO Chapter 17 LCD Controlle
403. te 2 oscillator voltage PRENS range MIN 4 0 V X1 input frequency Vpp 4 0 to 5 5 V fy Note 1 open X1 input high low level PD74HCU04 y width typ txL Vpp 4 0 to 5 5 V Notes 1 Indicates only oscillation circuit characteristics Refer to AC Characteristics for instruction execution time 2 Time required to stabilize oscillation after reset or STOP mode release Cautions 1 When using the main system clock oscillation circuit wiring in the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance Wiring should be as short as possible Wiring should not cross other signal lines Wiring should not be placed close to a varying high current The potential of the oscillation circuit capacitor ground should always be the same as that of Vss Do not ground wiring to a ground pattern in which a high current flows Do not fetch a signal from the oscillation circuit 2 When the main system clock is stopped and the system is operated by the sub System clock the subsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured by the program 444 User s Manual U12670EE3VOUDOO Chapter 25 Electrical Specifications Recommended Oscillator Data Manufacturer Murata Mfg Co Ltd AVX Kyocera Grp Manufacturer Kinseki Main System clock Ceramic Resonator
404. ter Addressing 1 2 dui acea 75 Direct add SSiN errr rarae ae AR EAER neri trud it epe 76 Short direct addressing sicpi eee erga i helen 77 Special Function Register SFR 78 Register indirect 0 0 17 79 eG iib hee che ctv 80 Based indexed 2240224 1 81 Pin Input Output 7 84 Port Gonfiguration tp eec i dee Us upto el a eee 86 Clock Generator Configuration esses eene nennen 106 Maximum Time Required for CPU Clock 117 Configuration of 16 bit Timer Event Counter 40 120 Valid edge of TIOO Pin and valid edge of capture trigger of capture compare register 122 Valid edge of TIO1 Pin and valid edge of capture trigger of capture compare register 122 Timer 2 Configuration edv en dere enda 150 8 Bit Timer Event Counter 50 Interval 161 8 Bit Timer Event Counter 51 Interval 161 8 Bit Timer Event Counter 50 Square Wave Output 162 8 Bit Timer Event Counter 51 Squar
405. ter the first reflow Package peak temperature 215 C Duration 40 sec max at 210 C or above Number of times twice max lt Precautions gt 1 The second reflow should be started after the first reflow device temperature has returned to the ordinary state 2 Flux washing must not be performed by the use of water after the first reflow VR15 00 3 Soldering bath temperature 260 C max Duration 10 sec max Wave soldering Number of times once Preheating temperature 120 C max package surface temperature Pin temperature 300 C max Pin part heating Duration 3 sec max per device side Caution Use of more than one soldering method should be avoided except in the case of pin part heating User s Manual U12670EE3VOUDOO 489 MEMO 490 User s Manual U12670EE3VOUDOO Appendix A Development Tools The following development tools are available for the development of systems that employ the uPD780948 Subseries Figure A 1 shows the development tool configuration Support for PC98 NX series Unless otherwise specified products compatible with IBM PC ATTM computers are compatible with PC98 NX series computers When using PC98 NX series computers refer to the explanation for IBM PC AT computers Windows Unless otherwise specified Windows means the following OS Windows 95 98 Windows NT Version 4 0 Windows 2000 User s Manual U12670EE3VOUDOO 491
406. th tRDL2 2 5 2 tcy 33 Write data setup time twos 60 Write data hold time tWDH 6 WR low level width twRL 1 5 2n toy 15 RD J delay time from ASTB tasTRD 6 WR 1 delay time from ASTB J tastwr 2 toy 15 ASTB delay time from RD at external fetch Address hold time from RD T at external fetch iRDAST 0 8 tcy 15 tRDADH 0 8 tcy 15 1 2 30 Write data output time from RD T tRDWD 40 Write data output time from WR T twRDWD 10 60 Address hold time from WR T tWRADH 0 8 toy 15 1 2 tcy 30 Remarks 1 tcy 4 2 100 pF C capacitances of ADO to 07 A8 to 15 RD WR ASTB 3 indicates the number of waits 466 User s Manual U12670EE3VOUDOO Chapter 25 Electrical Specifications 2 0780948 1 TA 40 C to 110 C 4 0 to 5 5 V Parameter Conditions ASTB high level width Address setup time Address hold time 242n tcv 54 Data input time from address 343n tcy 60 242n tcv 87 343n toy 93 100 Data input time from RD 4 Address output time from RD 4 0 Read data hold time 0 1 5 2n 33 2 5 2n 33 RD low level width Write data setup time 60 Write data hold time 6 WR low level width twRL 1 542n tey 15 RD J delay time from ASTB 4 tasTRD 6 WR 41 delay time from ASTB J tASTWR 2 toy 15
407. the IBM PC compatible computers as the IE 78K0 NS A host machine ISA bus compatible IE 70000 PCI IF A Interface Adapter This adapter is required when using a computer with PCI bus as the IE 78K0 NS host machine IE 78K0 NS P04 Emulation Board This board emulates the operations of the peripheral hardware peculiar to a device It should be used in combination with an in circuit emulator IE 780948 NS EM4 Probe Board This board provides the connection and buffers between the emulation board and the connector of the emulation probe NP 100GF TQ Emulation Probe This probe is used to connect the in circuit emulator to a target system and is designed for use with 100 pin plastic QFP NQPACK100RB YQPACK100RB YQSOCKET100RBF HQPACK100RB Conversion Adapter 2 Socket Details NQPACK100RB This conversion adapter connects the NP 100GF TQ to a target system board designed for a 100 pin plastic Socket for soldering on the target YQPACK100RB Adapter socket for connecting the probe to the NQPACK100RB HQPACK100RB Lid socket for connecting the device to the NQPACK100RB YQSOCKET100RBF High adapter between the device to the YQPACK100RB and the probe 494 User s Manual U12670EE3VOUD00 A 3 2 Software 5 78 0 System Simulator Appendix A Development Tools This system simulator is used to perform debugging at C source level or assem bler level while simulating the
408. the conversion value of that channel will be undefined and the conversion values of other channels may also be affected AV pp AVngr pin shared with AVREF pin This pin inputs the A D converter reference voltage and is used as the A D converter power supply pin The supply power has to be connected when the A D converter is used It converts signals from ANIO to into digital signals according to the voltage applied between AVpp AVngr and AVgg Even when the A D converter is not used the pin AVpp AVggr has to be connected to Vpp AVss pin This is the GND potential pin of the A D converter Always keep it at the same potential as the Vss pin even when not using the A D converter User s Manual U12670EE3VOUDOO 205 Chapter 12 A D Converter 12 3 A D Converter Control Registers The following 4 types of registers are used to control A D converter A D converter mode register ADM1 Analog input channel specification register ADS1 Power fail compare mode register Power fail compare threshold value register PFT 1 A D converter mode register ADM1 This register sets the conversion time for analog input to be A D converted conversion start stop and external trigger ADM1 is set with an 8 bit memory manipulation instruction RESET input clears ADM1 to 00H Figure 12 3 A D Converter Mode Register ADM1 Format s 6 5 4 3 2 1 0 RW Address fe Reset A D Conversion Operation Control Stop conv
409. the data bit The transmission node transmits data synchronized to the transmission node bit timing The reception node adjusts synchronization at recessive to dominant edges on the bus Depending on the protocol this synchronization can be a hard or soft synchronization a Hard synchronization This type of synchronization is performed when the reception node detects a start of frame in the bus idle state When the node detects a falling edge of a SOF the current time quanta becomes the synchronization segment The length of the following segments are defined by the values programmed into the SYNCO and SYNC1 registers Figure 16 17 Adjusting Synchronization of the Data Bit Bus idle Start of frame CAN bus N 4 Sync Prop Phase Phase 272 User s Manual U12670EE3VOUDOO Chapter 16 CAN Controller b Soft synchronization When a recessive to dominant level change on the bus is detected a soft synchronization is performed Ifthe phase error is larger than the programmed SJW value the node will adjust the timing by applying this SJW value Full synchronization is achieved by subsequent adjustments on the next recessive to dominant edge s These errors that are equal or less of the programmed SJW are corrected instantly and full synchronization is achieved already for the next bit The TQ at which the edge occurs becomes sync segment forcibly if the phase error is less than or equal to SJW Figure 16
410. thod Selected Not selected Vreo Z Common signal Segment signal Remark OneLCDCL cycle c 1 3 bias method Selected Not selected Common signal _ Segment signal Remark OneLCDCL cycle User s Manual U12670EE3VOUDOO 339 Chapter 17 LCD Controller Driver 17 7 Supplying of LCD Drive Voltages Vi Vici Vi c2 The split resistors makes it possible to produce LCD drive voltages appropriate to the various bias methods shown in Table 17 5 without using external split resistors Table 17 5 LCD Drive Voltages with On Chip Split Resistor connected externally 1 2 Bias Method 1 3 Bias Method LCD Drive Voltage static mode Vicp 1 2 Vi cp An example of supply of the LCD drive voltage from off chip is shown in Figure 17 9 Stepless LCD drive voltages can be supplied by means of variable resistor r Cautions 1 The Flash version pPD78F09468 has no internal split resistor 2 Mask version PD780948 has the possibility to implement interval split resis tors via mask option Figure 17 7 LCD Drive Power Supply Connection Examples with External Split Resistor 1 2 a Static display modeN Vppt Vicp Note LIPS should always be set to 1 including in standby mode 340 User s Manual U12670EE3VOUDOO Chapter 17 LCD Controller Driver Figure 17 7 LCD Drive Power Supply Connection Examples with External Split Resistor 2 2 b 1 2 bias method
411. tion mode The INIT is the request bit to control the DCAN INIT starts and stops the CAN protocol activities Due to bus activities disabling the DCAN is not allowed any time Therefore changing the INIT bit must not have an immediate effect to the CAN protocol activities Setting the INIT bit is a request only The INITSTAT bit in the CANES register reflects if the request has been granted The registers MCNT SYNCO SYNC1 and MASKC are write protected while INIT is cleared independently of INITSTAT Any write to these registers when INIT is set and the initialisation mode is not confirmed by the INITSTAT bit can have unexpected behaviour to the CAN bus STOP Stop Mode Selection Normal sleep operation Sleep mode is released when a transition on the CAN bus is detected Stop operation Sleep mode is cancelled only by CPU access No wake up from CAN bus Sleep Stop Request for CAN protocol Normal operation CAN protocol goes to sleep or stop mode depending on STOP bit 296 User s Manual U12670EE3VOUD00 Chapter 16 CAN Controller Figure 16 34 CAN Control Register 2 2 The clock supply to the DCAN is switched off during initialization DCAN Sleep and DCAN Stop mode All modes are only accepted while CAN protocol is in idle state whereby the CRXD pin must be reces sive high level A sleep or stop request out of idle state is rejected and the WAKE bit in CANES is set DCAN Sleep and DCAN Stop mode can be requested in
412. to 6 must be set to 0 Table 18 2 Maximum and Minimum Values of the Buzzer Output Frequency Maximum and Minimum Values of Buzzer Output fy 8 MHz fy 8 38 MHz Max KHz Min KHz Max KHz Min KHz fgq1 2 1 838 0 976 1 926 1 024 fgq1 29 0 460 0 244 0 481 0 256 fgg1 28 0 919 0 488 0 963 0 512 The sound generator output frequency fgg can be calculated by the following expression fsg 2 SGCLO SGCL1 2 x SGCL2 7 x fy SGBR 17 Substitute 0 or 1 for SGCLO to SGCL2 in the above expression Substitute a decimal value to SGBR For fy 8 MHz SGCLO to SGCL2 is 1 0 0 SGBRO to SGBR3 is 1 1 1 1 SGBR 15 then fgg is retrieved as 2 1 0 2 0 7 fy 15 17 3 906 KHz fsa 362 User s Manual U12670EE3VOUD00 Chapter 18 Sound Generator 2 Sound generator buzzer control register SGBR SGBR is a register that sets the basic frequency of the sound generator output signal SGBR is set with an 8 bit memory manipulation instruction RESET input clears SGBR to 00H Figure 18 4 shows the SGBR format Figure 18 4 Sound Generator Buzzer Control Register SGBR Format Symbol 7 6 2 1 0 Address After Reset R W 5 4 3 Buzzer Output Frequency KHz Nete fy 8 MHz fy 8 38 MHz 0 0 0 0 0 0 0 0 Note Output frequency where SGCLO SGCL1 and SGCL2
413. uPD74HCUO4 width ty tx Vpp 4 010 5 5 Notes 1 Indicates only oscillation circuit characteristics Refer to AC Characteristics for instruction execution time 2 Time required to stabilize oscillation after reset or STOP mode release Cautions 1 When using the main system clock oscillation circuit wiring in the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance Wiring should be as short as possible Wiring should not cross other signal lines Wiring should not be placed close to a varying high current The potential of the oscillation circuit capacitor ground should always be the same as that of Vss Do not ground wiring to a ground pattern in which a high current flows Do not fetch a signal from the oscillation circuit 2 When the main system clock is stopped and the system is operated by the sub system clock the subsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured by the program 442 User s Manual U12670EE3VOUDOO Chapter 25 Electrical Specifications Recommended Oscillator Data Manufacturer Murata Mfg Co Ltd AVX Kyocera Grp Manufacturer Kinseki Main System clock Ceramic Resonator Product Name CSA4 00MGA Frequency MHz Recommended Oscillator Constant C1 pF C2 pF R1 KQ Remarks CST4 00MGWA
414. ual U12670EE3VOUD00 Chapter 16 CAN Controller The receive only mode can be used for baudrate detection Different baudrate configurations can be tested without disturbing other CAN nodes on the bus RXONLY Receive Only Operation 0 Normal operation 1 Only receive operation CAN does not activate transmit line Differences to CAN protocol in the receive only mode The mode never sends an acknowledge error frames or transmit messages The error counters do not count The VALID bit in CANES reports if the DCAN interface receives any valid message SAMP defines the number of sample points per bit as specified in the ISO 11898 SAMP Bit Sampling Sample receive data one time at receive point Sample receive data three times and take majority decision at sample point SOFC works in conjunction with the SOFE and SOFSEL bits in the CAN Control Register CANC For detailed information please refer to the bit description of that SFR register and the time function mode SOFC Start of Frame Control SOFE bit is independent from CAN bus activities SOFE bit will be cleared when a message for receive message 4 is received and SOF mode is selected Caution can read SYNCO SYNC1 register at any time Writing to the SYNCO SYNC1 registers is only allowed during initialization mode Any write to this register when INIT is set and the initialization mode is not confirmed by the INITSTATE bit can have unexpected b
415. ual U12670EE3VOUD00 Chapter 8 8 Bit Timer Event Counters 50 and 51 Table 8 6 8 Bit Timer Event Counters 50 Interval Times TCLn2 TCLn1 TCLnO Minimum Interval Time T n input cycle Maximum Interval Time 28 x T n input cycle Resolution T n input edge input cycle T n input cycle 28 x T n input cycle T n input edge input cycle 1 fx 125 ns 28 x 1 fx 32 us 1 fx 125 ns 2 x 1 fy 250 ns 2 x 1 fx 64 ms 2 x 1 fy 250 ns 23 x 1 fx 1 us 211 x 1 fx 256 ms 23 x 1 fx 1 us 2 x 1 fy 4 us 213 x 1 fy 1 ms 2 x 1 fy 4 us 2 x 1 fy 16 us 215 x 1 fy 4 ms 2 x 1 fy 16 us 1 29 x 1 fy 64 us 217 x 4 fy 16 ms 29 x 1 fy 64 us Other than above Setting prohibited Table 8 7 8 Bit Timer Event Counters 51 Interval Times Minimum Interval Time T n input cycle 28 x T n input cycle Maximum Interval Time Resolution T n input edge input cycle T n input cycle 28 x T n input cycle T n input edge input cycle 1 fx 125 ns 28 x 1 fx 32 us 1 fx 125 ns 21 x 1 fy 250 ns 2 x 1 fy 64 ms 21 x 1 fy 250 ns 23 x 1 fy 1 us 21 x 1 fy 256 ms 23 x 1 fy 1 us 2 x 1 4 us 213 x 1 fx 1 ms 2 x 1 fx 4 us 2 x 1 fy 16 us 215 x 1 fy 4 ms 2 x 1 fx 16 us 1 21 x 1 fx 512 us 220 x 1 fy 131 ms
416. uare wave Output 1 2 2 n 177 8 4 4 PWM output operations 179 8 5 Cautions on 8 Bit Timer Event Counters 50 51 182 Chapter 9 5 55 5 need 185 9 1 Watch Timer 185 9 2 Watch Timer 186 9 3 Watch Timer Mode Register 187 94 Watch Timer 189 9 4 1 Watch timer 189 9 4 2 Interval timer IIIA 189 Chapter 10 Watchdog 191 10 1 Watchdog Timer 191 10 2 Watchdog Timer Configuration 193 10 3 Watchdog Timer Control Registers 194 10 4 Watchdog Timer 196 10 4 1 Watchdog timer 1 196 10 4 2 Interval timer 197 Chapter 11 Clock Output Control 199 11 1 Clock
417. uction RESET input sets MASKC to 00H Figure 16 47 Mask Control Register Symbol 7 6 5 4 3 2 1 0 Address After Reset R W R W R W R W R R W R W R W MSKO Mask 0 Enable 0 Receive buffer 0 and 1 in normal operation 1 Receive buffer 0 is mask for buffer 1 MSK1 Mask 1 Enable 0 Receive buffer 2 and 3 in normal operation 1 Receive buffer 2 is mask for buffer 3 GLOBAL Enable Global Mask 0 Normal operation 1 Highest defined mask is active for all following buffers Caution This register is readable at any time Writing to the MASKC register is only allowed during initialization mode Any write to this register when INIT bit is set and the initialization mode is not confirmed by the INITSTATE bit can have unexpected behavior to the CAN bus User s Manual U12670EE3VOUDOO 315 Chapter 16 CAN Coniroller The following table shows which compare takes place for the different receive buffers The ID in this table always represents the ID stored in the mentioned receive buffer The table also shows which buffers are used to provide the mask information and therefore do not receive messages A global mask can be used for standard and extended frames at the same time The frame type is only controlled by the IDE bit of the receiving buffer Table 16 26 Mask Operation Buffers GLOBAL Receive Buffer Compare ID Compare ID 2 Compare ID Compare ID Compare ID Operation Normal
418. ues for 5 bits in the data between the start of frame and the ACK field the reception is continued by Chapter 16 CAN Controller 16 2 3 Multi Master As the bus priority is determined by the identifier any node can be the bus master 16 2 4 Multi Cast Any message can be received by any node broadcast 16 2 5 Sleep Mode Stop Function This is a function to put the CAN controller in waiting mode to achieve low power consumption The SLEEP mode of the DCAN complies to the method described in ISO 11898 Additional to this SLEEP mode which can be woken up by bus activities the STOP mode is fully con trolled by the CPU device User s Manual U12670EE3VOUDOO 267 16 2 6 Error Control Function 1 Error types Table 16 11 Description of Error Chapter 16 CAN Coniroller Error Types Detection State Detection Method Comparison of output Bit error except stuff bit level and level on the bus Detection Condition Disagreement of both levels Transmission Reception Transmission reception node Field Frame Bit that output data on the bus at the start of frame to the end of frame error frame and overload frame Check of the reception Stuff error data at the stuff bit 6 consecutive bits of the same output level Transmission reception node Start of frame to CRC sequence Comparison of the CRC generated from the reception data and the received CRC sequence CRC error Dis
419. upt request flag IE Interrupt enable flag ISP In service priority flag MK Interrupt mask flag PR Priority specify flag User s Manual U12670EE3VOUDOO 369 Interrupt Request Remark 370 Internal Bus Chapter 19 Interrupt Functions Figure 19 1 Basic Configuration of Interrupt Function 2 2 c External maskable interrupt except INTPO External Interrupt Mode Register EGN EGP Vector Table Creat tS Mies Detector enerator Standby Release Signal d Software interrupt Internal Bus Vector Table Address Generator Interrupt Priority Control Request Circuit IF Interrupt request flag IE Interrupt enable flag ISP In service priority flag MK Interrupt mask flag PR Priority specify flag User s Manual U12670EE3VOUD00 Chapter 19 Interrupt Functions 19 3 Interrupt Function Control Registers The following six types of registers are used to control the interrupt functions Interrupt request flag register IFOL IF1L IF1H Interrupt mask flag register MKOL MKOH MK1L Priority specify flag register PROL PROH PR1L PR1H External interrupt mode register EGP EGN Program status word PSW Table 19 2 gives a listing of interrupt request flags interrupt mask flags and priority specify flags corre sponding to interrupt request sources Table 19 2 Various Flags Corresponding to Int
420. used in extended format mode and is always recessive Table 16 2 Bit Number of the Identifier Protocol Mode Identifier Standard format mode 11 bits Extended format mode 29 bits Table 16 3 RTR Setting Frame Type RTR Bit Data frame 0 Remote frame 1 Table 16 4 Mode Setting Protocol Mode IDE Bit Standard format mode 0 Extended format mode 1 User s Manual U12670EE3VOUDOO 259 Chapter 16 CAN Coniroller 3 Control field The data byte number DLC in the data field specifies the number of data bytes in the current frame DLC 0 to 8 Figure 16 6 Control Field Standard Format Mode Arbitration field T Control field 1 field OD Figure 16 7 Control Field Extended Format Mode Arbitration field T Control field field R D The bits rO and r1 are reserved bits for future use and are recommended to be recessive Table 16 5 Data Length Code Setting Data Length Code DLC2 DLC1 Number of Data Bytes 0 0 0 1 1 0 1 1 1 7 1 X X X 8 Remark n case of a remote frame the data field is not generated even if data length code O 260 User s Manual U12670EE3VOUD00 Chapter 16 CAN Controller 4 Data field This field carries the data bytes to be sent The number of data bytes is defined by the DLC value Figure 16 8 Data Field Control field Data field m nd field R D Data 8 bits Data 8 bits
421. using the sub system clock take special cautions for wiring methods User s Manual U12670EE3VOUDOO 449 Chapter 25 Electrical Specifications 3 pPD78F0948 40 C to 85 Vpp 4 0 to 5 5 V Resonator Recommended circuit Parameter Test Conditions 4 0 V lt Vpp lt 5 5V R 510 KQ Note 2 C 33 pFNote 2 Note 1 Oscillator frequency fxr Note 1 CL1 Input 14 0 V lt Vpp lt 5 5 V frequency fxr CL1 Input high low level 4 0 V lt Vpp lt 5 5 V width txTL Notes 1 Only oscillator circuit characteristics are shown Regarding instruction execute time please refer to AC characteristics Reference data CAN operation with external clock Cautions 1 When using the subsystem clock oscillation circuit wiring in the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance Wiring should be as short as possible Wiring should not cross other signal lines Wiring should not be placed close to a varying high current The potential of the oscillation circuit capacitor ground should always be the same as that of Vss Do not ground wiring to a ground pattern in which a high current flows Do not fetch a signal from the oscillation circuit 2 The subsystem clock oscillation circuit is designed to be a circuit with a low amplification level for low power consumption more p
422. ut disable Input disable Output Chapter 2 Pin Function uPD780948 Subseries Figure 2 2 Pin Input Output Circuits 1 3 V un ve IN OUT Data gt P ch Ge ai i disable 77 Output 2 5 N ch disable F 77 Voo P 8 Input enable Type 8 A oe IN OUT n on Output 4 disable User s Manual U12670EE3VOUDOO IN OUT IN OUT 51 52 Chapter 2 Pin Function uPD780948 Subseries Figure 2 2 Pin Input Output Circuits 2 3 Voo Type 11 B ch Comparator IN OUT Open drain m 2 N ch output disable Vre Threshold Voltage 4 disable Output N ch TU Input enable Vico Vict Type 17 A 1 enable IN OUT Data Output disable Input enable Vico Vict User s Manual U12670EE3VOUD00 IN OUT Chapter 2 Pin Function uPD780948 Subseries Figure 2 2 Pin Input Output Circuits 3 3 Type 17 B 17 enable Voo Data p H Pe Data _ t TH P ch 5 Output 15 feN ch IN OUT disable Output 30 N ch disable Ee TT User s Manual U12670EE3VOUDOO
423. ut clock set to fx Prescaler Interval Time Selection fx 8 00 MHz Operation fxr 32 768 KHz Operation 2 fw 512 us 2 f 488 us 25 fw 1 ms 25 fw 977 us 25 fy 2 ms 26 fw 1 95 ms 2 fy 4 ms 2 fy 3 91 ms 28 fy 8 19 ms 28 fy 7 81 ms 0 2 fy 16 38 ms 2 fy 15 6 ms Other than above Setting prohibited Watch Operating Mode Selections Normal operating mode interrupt generation at 2 4 fy Fast feed operating mode interrupt generation at 2 fw User s Manual U12670EE3VOUDOO 187 Chapter 9 Watch Timer Figure 9 2 Watch Timer Mode Control Register WTM Format 2 2 WTM1 5 Bit Counter Operation Control UM after operation stop Operation enable WTMO Prescaler Operation Control Clear after operation stop Operation enable Caution When the watch timer is used the prescaler should not be cleared frequently When rewriting WTM4 to WTM6 to other data stop the timer operation beforehand Remarks 1 fy Watch timer clock frequency fx 28 or 2 fx Main system clock oscillation frequency 3 fxr Subsystem clock oscillation frequency 188 User s Manual U12670EE3VOUD00 Chapter 9 Watch Timer 9 4 Watch Timer Operations 9 4 1 Watch timer operation When the subsystem clock is used the timer operates as a watch timer with a 0 5 second interval The watch timer is generated interrupt request at the constant time i
424. ut ports Control mode These ports function as A D converter analog input pins ANIO to ANI7 2 3 3 P20 to P26 Port 2 This is a 7 bit input output port Besides serving as input output port they function as data input output to from the serial interface clock input output The following operating modes can be specified bit wise 1 2 Port mode These ports function as 7 bit input output ports They can be specified bit wise as input or output ports with port mode register 2 P20 to P24 are selectable as N ch open drain or as CMOS output Control mode These ports function as serial interface data input output clock input output 510 511 500 SO1 Serial interface serial data input output pins b SCKO and SCK1 Serial interface serial clock input output pins c RXD TXD Asynchronous serial interface data input output pins Caution When this port is used as a serial interface the I O and output latches must be set 42 according to the function the user requires User s Manual U12670EE3VOUD00 Chapter 2 Pin Function uPD780948 Subseries 2 3 4 P30 to P34 Port 3 This is a 5 bit input output port Beside serving as input output ports they function as timer input clock output and sound generator output The following operating modes can be specified bit wise 1 2 Port mode These ports function as 5 bit input output ports They can be specified bit wise as input or output ports with por
425. w level width R 1KQ 511 SO1 setup time to SCK1 7 C 100 pF Note 511 501 hold time from SCK1 T 511 501 output delay time from SCK1 4 Note Rand C are the load resistance and the load capacitance of the 511 501 SCK1 output line UART mode Dedicated baud rate generator output mme C CELL De User s Manual U12670EE3VOUDOO 475 3 pPD78F0948 Chapter 25 Electrical Specifications 40 C to 85 C Vpp 4 0 to 5 5 V 3 wire serial I O mode SCKO Internal clock output Parameter SCKO cycle time tkcy1 Conditions 1000 SCKO high low level width te tkcy1 2 50 SIO setup time to SCKO T tsik1 100 510 hold time from SCKO tksi1 400 500 output delay time from 4 tkso1 C 100 pF Nete Note Cis the load capacitance of 500 SCKO output line 3 wire serial I O mode SCKO External clock output Parameter SCKO cycle time tkcvi Conditions SCKO high low level width 1 510 setup time to SCKO tsik1 510 hold time from SCKO SOO output delay time from 4 tkso1 C 100 pF Note Note C is the load capacitance of 500 SCKO output line 476 User s Manual U12670EE3VOUD00 Chapter 25 Electrical Specifications 2 wire serial I O mode SCK1 Internal clock output Parameter Conditions
426. without prior written consent of NEC Electronics NEC Electronics assumes no responsibility for any errors that may appear in this document NEC Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such NEC Electronics products No license express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC Electronics or others Descriptions of circuits software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples The incorporation of these circuits software and information in the design of customer s equipment shall be done under the full responsibility of customer NEC Electronics no responsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information e While NEC Electronics endeavors to enhance the quality reliability and safety of NEC Electronics products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC Electronics products customers must incorporate sufficient safety m
427. wn error frame No change Transmission node transmits an error flag Exception 1 ACK error is detected in the error passive state and domi nant level is not detected in the passive error flag sent 2 Stuff error generation in arbitration field No change Bit error detection during active error flag and overload flag when transmitting node is in error active state 8 No change Bit error detection during active error flag and overload flag when receiving node is in error active state No change 8 When the node detects fourteen continuous dominant bits counted from the beginning of the active error flag or the over load flag and every time eight subsequent dominant bits after that are detected Every time when the node detects eight continuous dominant bits after the passive error flag When the transmitting node has completed to sent without error 1 0 when error counter 0 No change When the reception node has completed to receive without error c Overload frame No change 1 1 lt REC lt 127 0 REC 0 119 127 REC 127 n case the recessive level of first intermission bit is driven to dominant level an overload frame occurs on the bus Upon detection of an overload frame any transmit request will be postponed until the bus becomes idle 270 User s Manual U12670EE3VOUDOO Chapter 16 CAN Controller 16 2 7 Baud Rate Control Function 1 Nom
428. xecuting the BRK instruction It is acknowledged even in a disabled state The software interrupt does not undergo interrupt priority control User s Manual U12670EE3VOUDOO 367 Chapter 19 Interrupt Functions 19 2 Interrupt Sources and Configuration There are total of 26 interrupt sources non maskable maskable and software interrupts Mask ability Non maskable Interrupt Priority Note 1 Table 19 1 Interrupt Source List Interrupt Source INTWDT Trigger Overflow of watchdog timer When the Watchdog timer NMI is selected Maskable INTWDT Overflow of watchdog timer When the interval timer mode is selected INTAD End of A D converter conversion INTOVF Overflow of 16 bit timer 2 INTTM20 Generation of 16 bit timer capture register CR20 match signal 2 Generation of 16 bit timer capture register CR21 match signal INTTM22 Generation of 16 bit timer capture register CR22 match signal Internal External Internal Vector Address Basic Structure Type Note 2 INTPO INTP2 INTP3 INTP4 Pin input edge detection External INTCE CAN Error INTCR CAN Receive INTCTO CAN Transmit buffer 0 INTCT1 CAN Transmit buffer 1 INTCSIO End of serial interface channel 0 transfer INTCSI1 End of serial interface channel 1 transfer INTSER
429. y data memory bits 1 and 2 are not used with the static display mode bits 2 and 3 are not used with the 2 time division method and bit 3 is not used with the 3 time division method these can be used for other than display purposes Bits 4 to 7 are fixed at 0 User s Manual U12670EE3VOUDOO 337 3 338 Chapter 17 LCD Controller Driver Common signal and segment signal output waveforms The voltages shown in Table 17 4 are output in the common signals and segment signals The V cp ON voltage is only produced when the common signal and segment signal are both at the selection voltage other combinations produce the OFF voltage Table 17 4 LCD Drive Voltage a Static display mode Segment Select Non select Vsst Vico Vico Vss1 b 1 2 bias method Segment Select Non select Vss1 Vico Vico Vss1 Select level Vico Vsst Vicp VLCD 0V 0V Non select level Vici Vice 1 2 Vi 1 2 Vicp 1 2 1 2 1 3 bias method Segment Select Non select Vss1 Vico VLC1 VLC2 Select level Vi Vss1 Vicp Vi cp 1 3 Vi cp 1 3 Vi ep Non select level Vico Vict 1 3 Vicp 1 3 Vicp 1 8 Vi 1 3 Vicp User s Manual U12670EE3VOUD00 Chapter 17 LCD Controller Driver Figure 17 6 Common Signal and Static Signal Voltages and Phases a Static display mode Vicp Common signal Segment signal Vico Remark OneLCDCL cycle b 1 2 bias me
430. y using the Project Manager included in assembler package on Windows CC78K 0 C Compiler Package This compiler converts programs written in C language into object codes executable with a microcontroller This compiler should be used in combination with an optical assembler package and device file lt Precaution when using CC78K 0 PC environment gt This C compiler package is a DOS based application It can also be used in Windows however by using the Project Manager included in assembler package on Windows Device File This file contains information peculiar to the device This device file should be used in combination with an optical tool RA78K 0 CC78K 0 5 78 0 ID78KO NS and ID78K0 Corresponding OS and host machine differ depending on the tool to be used with CC78K 0 L C Library Source File IAR Software A78000 This is a source file of functions configuring the object library included in the C compiler package 78 0 This file is required to match the object library included in C compiler package to the customer s specifications Assembler package used for the 78KO series 78000 C compiler package used for the 78KO series XLINK Linker package used for the 78KO series A 2 Flash Memory Writing Tools FlashMASTER Flashpro Ill part number FL PR3 PG FP3 Flashpro IV part number PG FP4 Flash Programmer Flash programmer dedicated to microc
431. yte space from FE20H to FF1FH An internal high speed RAM and a special function register SFR are mapped at FE20H to FEFFH and FFOOH to FF1FH respectively The SFR area where short direct addressing is applied FFOOH to FF1FH is a part of the SFR area In this area ports which are frequently accessed in a program a compare register of the timer event counter and a capture register of the timer event counter are mapped and these SFRs can be manipu lated with a small number of bytes and clocks When 8 bit immediate data is at 20H to FFH bit 8 of an effective address is set to 0 When it is at OOH to 1FH bit 8 is set to 1 Refer to Figure 3 17 below Operand format Table 3 7 Short direct addressing saddr Label of FE20H to FF1FH immediate data saddrp Label of FE20H to FF1FH immediate data even address only Figure 3 17 Short direct addressing a Description example MOV OFE30H 50H when setting saddr to FE30H and immediate data to 50H Operation code 00010001 OP code 00110000 saddr offset 01010000 50H immediate data 1 b Illustration OP code saddr offset Short Direct Memory Effective Address When 8 bit immediate data is 20H to FFH a 0 When 8 bit immediate data is to 1FH a 1 User s Manual U12670EE3VOUDOO 77 Chapter 3 CPU Architecture 3 4 5 Special function register SFR addressing The memory mapped special function register SFR is addressed

uPD780948 Subseries 8-bit Single

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