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ADSP-BF533 EZ-KIT Lite Evaluation System Manual

1. 3 3V 3 3V R5 O O 33 805 gt 1ADV7183 27MHZ CLK 1 U4 R6 8 33 01 805 R225 Ri 02 gt 1ADV7 71 27MEZ CLK l 10K 10K 7 3 3V 805 805 03 R7 O o4 33 805 1 d R179 IN o U3 33 12 DNP 805 06 R8 3 14 33 R180 E OUT 07 805 U46 22 og 6 ANA PO BEER GLK 777777 pu KN em A 4 er i aa Cem e VVV HAMMER 33 8 19 805 CLKI 10 r 1 b R181 VV V 1 gt DSP CLK __ CLK2 22 R20 IDT74FCT3807AQ 6 5 805 10M QSOP20 R19 VDD CLK3 805 DNP 4 7 NN NS gt 1CLK_OUT_EXP2 1 805 CND GU m0 Se gege A AAA o Not populated in standard EZ KIT Configuration KEE a R109 Can be used to provide DSP clock frequency L EXT_DSP_CLKI V V V IDTZ3U5 TDC 22 other than that of the Video Interface SOIC8 805 U2 R224 A ITALJA Sos DNP TERMI TERM2 e ToE out nci Noo DNP 3 C1 32 768KHZ C3 OSC003 18PF OSCO08 18PF DNP 805 T 805 U1 Eo AiO Baar 77777 penes a L1 PED LLL 1 L RSCLKOI 2 RscLko L oeen ran U BAOPAN 2 propa R T 1 J2 L DROSE I f gt DROSEC 77 TSGIR O r
2. 3 3V 5V 3 3V 5V ees CUN CS O 1 1 e d 4 All USB interface circuitry is considered proprietary and has been omitted from this schematic 3 3V When designing your JTAG interface please refer to the I Led N PFIOASI __ I J3 Engineer to Engineer Note EE 68 which can be found at J2 2 1 2 1 http www analog com 4 8 4 3 r 6 5 6 5 LIX gt AX 8 7 8 7 TER 10 9 R173 poate 10 9 EEN EAT BI 10K L MOSI SCK _ 12 11 805 L MISO 2 14 13 DSP JTAG HEADER Al 14 8 d E 16 15 18 17 L gt INMI l 20 ig gt EMULATOR SELECT 20 19 mu 22 ei 22 ki T T e 2 23 P4 L TMR2 24 E 26 25 1 EMULATOR EMU nn r TMRO 26 E ITMR m 28 b7 3 f paa 28 b7 Kee o RESET 5 5 L DTISECI gt JDRISEG pazar 30 ba e EMULATOR TMS ee Ge RESETI L DTIPRI 30 X a eke a En 32 bi 7 b gt EMULATOR TCK rt ts 32 bi 2007 ADV7183 HSI 9 ho AAA TFSi 53 34 53 e EMULATOR TRST e 34 53 2 ADV7183 FIELD 11 12 L TSCLKII PSC a 36 B5 e gt EMULATOR TDI EEN 36 35 4 ADV7183 HREF 13 44 L DTOSECI LL DRoECC p7777777777 38 87 EMULATOR_TDO L DTOPRIi gt 40 L me r z 40 39 r 3 IRFSO wa 42 41 177 TSCLKO iz IRSCLKO 44 7 Ba ax m qx ee az n o s pn mda Vi Gi e e 77 P 44
3. Power J9 The power connector provides all of the power necessary to operate the EZ KIT Lite board The power connector supplies DC power to the board The following table shows the power connector pinout ADSP BF533 EZ KIT Lite Evaluation System Manual 3 17 Connectors 7 5V Power Supply GlobTek Part Description Manufacturer Part Number 2 5 mm Power Jack J9 SWITCHCRAFT RAPC712 Digi Key SC1152 ND Mating Power Supply shipped with EZ KTT Lite TRICC2000LCP Y The power connector supplies DC power to the EZ KIT Lite board Table 3 10 shows the power supply specifications Table 3 10 Power Supply Specification Terminal Connection Center pin 7 5 VDC 2amps Outer Ring GND FlashLINK P1 The FlashLINK connector allows you to configure and program the STMicroelectronics DSM2150 flash PLD chip See Configuring Flash Memory on page 2 9 for more information about the FlashLINK connector Part Description Manufacturer Part Number Right angle 7X2 Shrouded 0 1 TYCO 2 767004 2 spacing J10 Mating Assembly FlashLINK JTAG Programmer ST Micro FL 101B 3 18 ADSP BF533 EZ KIT Lite Evaluation System Manual EZ KIT Lite Hardware Reference RS232 P2 The RS232 compatible connector is described in Table 3 11 Table 3 11 RS232 Connector Part Description Manufacturer Part Number DB9 Male Right Angl
4. XVili Online Documentation d ak l l le lak XX Pr alli ikuy uuu b lll xx VisualDSP Documentation Set bea asa aadaki xx Hardware EE xxi i ETES xxi Contacting DE EE xxi Notation Convention uuu asaaqasaasqasasqasyassaqaqaqawsqassaqsasqsskas XXII ADSP BF533 EZ KIT Lite Evaluation System Manual CONTENTS GETTING STARTED Connor EZ BIT Lire Para ela 1 1 PL Lo EE 1 3 kul ra ab a 1 3 Installing VisualDSP and EZ KIT Lite Software 1 4 Installing and Registering VisualDSP License 1 5 Setting Up EZ KIT Lite Hardware 1 5 Installing EZ KIT Lite USB Driver rima 1 7 Una 90 USB SEL babi 1 8 Windows 2000 USB Driver inal 1 12 Windows XP USB E 1 13 Vesitving Driver E 1 15 Starine Viraal DSP ria 1 16 USING EZ KIT LITE EZ KIT Lite License Restricti ns 2 2 luani go t 2 2 Usia SORAM Int 2 4 saa NEE 2 5 Plash e Ni ala 2 6 Flash General Porpose a mcm 2 7 Contiguriog Flash Memory eksilme ilana 2 9 Using LEDs and Push Buttons 2 10 DIE Sr E 2 11 vi ADSP BF533 EZ KIT Lite Evaluation System Manual CONTENTS T Vi 2 12 ar i 2 13 Using Background Telemetry Channel Lies R ii 2 13 Using EZ KIT Lite Visuel DISP Interface cias 2 13 Trace 2 14 Enabling Trace b H a aad 2 14 Reading
5. PEDE L5 wi 1 XK HN2L2 1 AA isa Sasi area wan iue el 1 wai paq waq pan SS SS ay 3 AD1836 VREFI AD1836 VREFIBE EES Vemm ees a a ali D8606AR 0 001UF SOIC8 T 805 R102 R101 R85 R84 5 76K 5 76K 5 76K 5 76K 1206 1206 Cot 1206 1206 TS ADC1 LEFT ADC2 LEFT XK C50 0 001UF T 805 R97 237 1206 Q rnI n l C LLla llelL L lllllglglll Ca LLL O tu IXMIAIALLLLLLLLLLLLLLLLLL LLLLL I O E ta e gt HN2L1 i CO UN __1 E m ademi nn D8606AR SOIC8 J5 J5 enis 2X2 FER2 ME R89 R88 2X2 FER4 DUF R100 R92 CON013 600 Er 5 76K 5 76K CON013 600 CAP002 5 76K 5 76K EE 1206 1206 1206 SH 2222 1200 hs 1206 1206 V 4 DEE RIGHT 5 amp I O EEE SEH AAA s s s 21 AC AC 44 C59 6 C47 120PF 3 C56 120PF 100PF 1206 100PF 1206 T 1206 4 4 1206 4 d R95 gt U17 237 A ND AGND GES X 1 e ES deyir e mp M levee AR GE AD1836 VREF H a pias DESOSAR IC8 C52 0 001UF T 805 R82 R83 5 76K 5 76K E 1206 1206 48 100PF ADC2 RIGHT n ADC1 RIGHT X C49 0 001UF T 805 R93 237 RENE DER e e gt HNIR 1 5 E EDS AD1836 VREF M L AD8606AR SOIC8 x DNP Do Not Populate ANALO I 20 Cotton Road Nashua NH 03063 DEVICES PH 1 800 anatoap Approvals Date Title ADSP BF533 EZ KIT LITE AUDIO IN Drawn Engineerin 8 8 Date 3 24 2003 13 34 Sheet 6 of
6. T 805 1206 e e e R182 0 00 DNP Do Not Populate 1206 AGND2 AAAA AGND2 ANAI Ol I 20 Cotton Road nor Nashua NH 03063 o Se 5 DE V ICES PH 1 800 ANALOGD b PFT V NK gt IPFLSDATA 1 R227 N S Fe 0 00 AGND2 itle 805 Approvals Date Gees pory ADSP BF533 EZ KIT LITE VIDEO OUT _PF0 gt IPFO SCLOCK____1 Drawn Engineerin 8 8 Date 2 3 2004 11 53 Sheet 7 of 13 A B C D 3 3V x E a e O O O lt lt lt Q Q a WHITE OUT CN EON EN CC OCA R142 R143 R139 R138 XA NOM RA V NANA id 10K DK er CO CO l ld 805 805 805 805 RED IN O 51 VIDEO DECODER U28 O Y Z Z Z gt gt gt 777777 UADVABR ENBZ CLK 2 XTAL P15 L a 28 XTAL1 P14 P13 66 ALSB P12 r PFT SDATA E 67 SDA P11 AVIN1 AVINA AVIN5 5555 68 i PFO SCLOCK e SCLK P10 Composite Video CVBS CVBS COVBS op SES 77 m mi R183 Differential Component Video Y U ve eese 64 BUE E ADV7183 RESET RESET P8
7. on page 3 5 For the video interface to be operational the following basic steps must be performed 1 Configure the SW3 DIP switch as required by the application Refer to Video Configuration Switch SW3 on page 3 11 for details Remove reset to the video device Refer to Flash General Purpose IO on page 2 7 for details If using the decoder v Enable device by driving programmable flag output PF2 to GA 0 v Select PPI clock see Table 2 8 on page 2 8 Program internal registers of the video device in use Both video encoder and decoder use a 2 wire serial interface to access internal registers A programmable flag PFO functions as a serial clock SCL and PF1 functions as a serial data SDAT Program the ADSP BF533 processor s PPI interface configuration registers DMA etc Example programs are included in the EZ KIT installation directory to demonstrate the capabilities of the video interface ADSP BF533 EZ KIT Lite Evaluation System Manual Using EZ KIT Lite Example Programs Example programs are provided with the ADSP BF533 EZ KIT Lite to demonstrate various capabilities of the evaluation board These programs are installed with the EZ KIT Lite software and can be found in Visu alDSP 16 bit Processors Blackfin EZ KITs ADSP BF533 Examples Please refer to the readme file provided with each example for more information Using Background Telemetry Channel The ADSP BF533 US
8. C126 128 C136 C146 147 C149 155 C159 161 53 B 0 22uF 25V 10 805 C129 130 AVX 08053C224FAT CERM C137 142 54 73 0 1uF 50V 10 805 C6 C8 C71 72 AVX 08055C104KAT CERM C75 81 C84 C86 C88 95 C98 101 C105 C109 111 C114 122 C125 C131 55 s 0 001uF 50V 5 805 C7 C9 11 AVX 08055A102JAT2A NPO C49 50 C52 53 56 8 10uF 16V 10 C CT13 CT21 27 SPRAGUE 2930106 9016 2 TANT 57 45 10K 100MW 5 805 RI R4 R10 AVX CR21 103J T R12 13 R15 16 58 9 133 100MVV 5 805 R5 6 R8 9 R31 AVX CR21 330 TR R144 R179 R183 59 2 4 7K 100MW 5 805 R17 R220 AVX CR21 4701F T 60 1 IM 100MW 5 805 R202 AVX CR21 1004F T 61 1 1 5K 100MW 5 805 R203 AVX CR21 1501F T ADSP BF533 EZ KIT Lite Evaluation System Manual A 5 5 3 E se Bz S 3 9 25 b amp m 2 158 52 3 ES z lola ZA E 62 1 2K 1 8W 5 1206 R129 DALE CRCW1206 122JRT1 63 16 49 9K 1 8W 1 1206 R38 R45 R54 AVX CR32 4992F T R62 R70 R78 64 12 12 21K 1 8W 1 1206 R212 213 AVX CR32 2211F T 65 l 2000pF 50V 5 1206 C83 AVX 12065A202JAT2A CERM 66 12 100pF 100V 5 1206 C15 C20 C25 AVX 12061A101JAT2A NPO 30 35 40 67 55 l0uF 16V 10 B CT1 2 CT14 16 AVX TA B106K016R TANT 68 14 100 100MW 5 805 R149 R152 AVX CR21 101J T R154 155 69 6 220pf 50V 10 1206 C16 C21 C26 AVX 12061A221JAT2A NPO C31 C36 C41 70 l4 600 100MHZ 200MA 603 FER14 17 MURATA BLM11A601SPT 0
9. S Video Y EEN E 36 gt IADV7183 CLKOUT 1 PWRDN P7 SS G A m 4LVC1G32 P6 SOT23 5 J8 65 21 3X2 R141 C90 NC ISO P CON024 0 00 0 1UF p4 22 f EN 805 805 AVIN1 WIDEO AY N NA e ang pa 28 41 24 AIN7 pa mupp ADVABS 9 py 32 m Ke 44 33 C AIN2 Po l i J8 43 e 3X2 R136 C88 ANS CON024 0 00 0 1UF AGND2 27 W WIDEO_AVINS x T p 26 O 01UF SNF 4 VIDEO AVINA 46 L AVIN4 C DIDEOAMM L AWNA O AIN3 LLC2 TT 805 R140 T 805 Ans NCILLCREF L I Bon Eipr 58 MINA 3X2 R135 C89 anio Hs gt tADV7183_HS 1 CON024 0 00 0 1UF 1 LA x2z f ON D 805 805 vs gt 140 7183 1 AVIN5 2000007 e 0 FIELD 882 gt ADV7183 FIELD 33V 7 e am NCIVREF l E gt JADV7183 VREF A A TINA I ki NC HREF l gt IADV7183 HREF O 62 AING 61 16 org AIN12 NC CLKIN SW3 10UF 11 1 i 122 1 gir MB C75 NC AFF R145 L ADV7lI71 HSYNC M W 1 IMRI sos 51 REFOUT SFLHFF FZ 805 7 2077755 HS me 75 75 75 52 NOJAEFI l 2 0 183 VSI D Cae ITMA2 1 Se d ena 2 wi enen Nono 77 e 7 B s SR 49 CAPY2 og 9 1 me iPEA mE fil E 10UF e e e e e A ir gt 32 1 NCIGPO3 809 55 CAPC2 Nc GPo2 19 R232 4 1 8V 3V 10K NC GPO 34 3 3 10K C77 35 AGND2 0 1UF NC GPO0 FERS 805 600 H E
10. T 805 6 l 23 330PF DAC2 LEFT 5 CS e G er DAC3 LEFT R80 T 805 R77 3 5 49K 1 65K 604 C24 1206 1206 1206 ce J4 680PF M s 3X2 R56 T 805 R53 L QUT2LH CAPO CONO24 5 49K 1 65K 604 5 050 o 1206 1206 1206 CTs J4 E 555 177 OUT 10UF N 2 Loan CAP002 gt R81 C41 Ti DAC3 LEFT 27 a7 2 74K 220PF 6 8 mem enm 1206 T 1206 lea R78 s2 401836 VREF lil 1208 1208 2 74K oer 3 1206 T 1206 22 R54 251836 VREF il 1206 1208 e e e e AGND AGND DNP Do Not Populate ANALOG tnos Nashua NH 03063 DEVICES ph 1 800 ANALOGD Title Approvals Date ADSP BF533 EZ KIT L TE AUDIO OUT Drawn Size Board No Rev Checked C A0167 2001 e Engineerin 8 8 Date 3 24 2003 13 34 Sheet 5 of 13 A B C D A J5 J5 2X2 FER3 27 R91 R98 2X2 FER1 mar R105 R87 CONO13 600 DAP 5 76K 5 76K CON013 600 BAB 5 76K 5 76K 70 20 1206 1206 1206 FI OE 1206 1206 1206 y 2 TASTE y t y 5 AET be y t 77755 e gt e AAN 7755 ANN C57 C45 3 C54 120PF 6 C46 120PF 100PF 1206 100PF 1206 1206 4 i 1206 4 4 R99 237 U18 AGND SNE 1206 AG D I
11. The ADSP BF533 EZ KIT Lite Evaluation System Manual provides instructions for using the hardware and installing the software on your PC This manual provides guidelines for running your own code on the ADSP BF533 EZ KIT Lite The manual also describes the operation and configuration of the evaluation board s components Finally a schematic and a bill of materials are provided as a reference for future ADSP BF533 board designs Intended Audience This manual is a user s guide and reference to the ADSP BF533 EZ KIT Lite evaluation system Programmers who are familiar with the Analog Devices Blackfin processor architecture operation and programming are the primary audience for this manual xiv ADSP BF533 EZ KIT Lite Evaluation System Manual Preface Programmers who are unfamiliar with Analog Devices Blackfin processors can use this manual in conjunction with the ADSP BF533 Processor Hard ware Reference and the Blackfin Processor Instruction Set Reference which describe the processor architecture and instruction set Programmers who are unfamiliar with VisualDSP should refer to the VisualDSP online Help and the VisualDSP user s or getting started guides For the loca tions of these documents refer to Related Documents Manual Contents The manual consists of Chapter 1 Getting Started on page 1 1 Provides software and hardware installation procedures PC system requirements and basic board information
12. 166 168 167 201 208 151 130 138 777 Q 01UF 0O 01UF 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF 0 01UF OO1UF 0 01UF 0 01UF 0 01UF 0 22UF 0 22UF 805 805 805 805 805 805 805 805 805 805 805 805 805 805 805 805 805 805 805 805 805 805 e e e e e e e e e X X IDT74FCT3807 PSD4265 A PSD4265 B SN74LVC1G125 SDRAM 74LVC00AD 74LVC14A U4 U5 U6 U7 U8 U9 U10 AD8606 AD8606 U12 U13 3 3V DV A5V A5V A5V A5V A5V A5V A5V 3 3V A3V A3V A3V 3 3V 3 3V w KA db d CN Le Lee EA A US Lee A N x x is Ne C165 C177 C99 C176 C178 C129 C137 C139 C141 C140 C142 C210 C110 C108 C111 C112 C109 C113 C172 C171 0 01UF 0 1UF 0 1UF 0 1UF 0 1UF 0 22UF 0 22UF 0 22UF 0 22UF 0 22UF 0 22UF 0 1UF Q 1UF 0 01UF Q 1UF 0 01UF Q 1UF 0 01UF 0 01UF 0 01UF 805 805 805 805 805 805 805 805 805 805 805 805 805 805 805 805 805 805 805 805 D XK X X X XK X AGND2 AGND2 AGND2 ADG752 ADG752 AG AD1836 U14 AD8606 AD8606 AD8606 AD8606 AD8606 AD8606 SN74AHC1 G08 AD8061 AD8061 AD8061 U25 U26 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 1 3V B 1 3 3V 3 3V 3 3V 3 3V 3 3V A CX TA CX C1
13. 2 14 PF3 3 6 RFSO signal 3 12 PPI CLK 3 6 RSCLKO I 4 ADSP BF533 EZ KIT Lite Evaluation System Manual register 2 11 signals 3 12 S SCLK 2 4 2 5 SDRAM iii 2 2 2 3 2 4 2 5 3 3 secondary flash memory 2 6 serial clock SCL 2 4 2 12 data SDAT 2 12 Serial Peripheral Interconnect SPI 3 4 setting EZ KIT Lite hardware 1 5 target options 2 17 software breakpoints 2 19 SPI port 2 11 SPORTO xiv 2 11 3 4 3 12 3 19 SRAM 2 3 2 6 3 3 starting VisualDSP 1 16 SW 1 2 test DIP switches 3 11 SW3 DIP switch 2 12 3 7 3 9 3 11 system architecture EZ KIT Lite board 3 2 clock 2 4 requirements PC 1 3 T target options dialog box 2 17 miscellaneous 2 18 on emulator exit 2 17 reset 2 17 test DIP switches SV71 2 3 11 TFSO signal 3 12 INDEX TMR1 2 primary processor pins 3 6 trace buffer 2 14 destination 2 15 instruction addresses 2 15 number 2 15 source 2 15 trace window 2 14 2 15 TSCLKO register 2 11 signal 3 12 U UART port 3 8 Universal Asynchronous Receiver Transmitter UART xili xiv USB cable 1 2 connector P7 3 18 3 19 driver installation Windows 2000 1 12 driver installation Windows 98 1 8 driver installation Windows XP 1 13 interface 3 9 interface chip U34 3 14 monitor LED CEDI 8 48 user LEDs LED9 4 3 15 see also LEDs V verifying USB driver installation 1 15 video 2 12 configuration switch SW3 3 11 connector J8 3
14. 4 pes y Aid pas 1418 20 a145 EES Tr z IB T BAO DQ14 5 apis Bee do Pag ee IS i 53 BECH ba DE bg 1515 PBA1 DQ15 mE PG7 PG7 2 7416 41 A16 41 KS 51 i az Fu 51 L SWE we cs ISMS 1 gt IAD1836 RESET PC1 PA0 17 b7 17 Op m vri SCASI CAS CKE SCKE A18 poco PAIRS gt m EEN PA1P 5 ee ke LA 17 491 mE I SRASI RAS CLK ICLK OUT AI pos PA223 gt lA L A9 cs p Gre een UC 9 a f j 9 A N L PCA rou PA3P gt d m roi PAS 13 7 46 55 46 55 DQML PCS AR PC5 PA4 gt I PC5 BIM PC5 PAG 39 2 47 56 47 56 DQMH 1 AMSOL Pce PA gt IPPICLK ONBOARD SELECT Misi O Pce PAS asa 5 Pe 5 i Iren PAG MT4BLCTEMTOAZIG 75 pa7ps TSOP54 L AWE O SSeNTto VVR gt SSeNTto VVR U ACE Cent PB 1 por ABE1 SDQM1 ill 0 NTL2 PB1 onTLe 19 2 pp2e3 i gt PEorTMS PB3 1 pEorrMs page 72 72 65 507 PE1 TCK PB4 57 PEVCK PB4 DNP Do Not Populate E E PB5 im pase FLASH TDO Al TAbEsrrDO PB 74 Pee AN ALOG 20 Cotton Road EE A fel a rama pp768 Nashua NH 03063 1777 FLASH TERRI gt Pesi TERR DO Is TERR DEV ICES PH 1 800 ANALOGD i PEGA kee PD kee poo M PDOB 78 78 80 i PEDAN PE Pbi PE PDI NB Approvals Date Tit
15. C PA7 BiM R13 Reo WiPA2 B 71 ns RB Coen Ra ng BEACH e R17 L PAS BII Tous Ria BGA36 hi6 179 e BGA36 512K x 16 512K x 16 e S6Mb KI 32MB 16M x 16 DAS 2677575 E Alto U5 U6 U8 r 1 r 1 4 ABEO SDQMO B SADO pro 150 3 ABEO SDOMOL B SADO pp a00 171 b EE DN 4 Di d TA 4 Di A0 DQO m ADI PF1 ADI PF1 UL TART 24 4 for r2 ra ro ra 06 4 Al 001 Ki oe SAD2 pepe D2 LD Sans per3 WE K3 25 5 mm E miis 1 9 002 ES A Sang pa KZ Zeg pa TAA 26 w ur vi a Fool SEH 12 az DQ3 LS LM an pa D4 1 441 Tapa ep 108 j Jug Em b DCH TASI 571 We ell LZ VI DQ4 ans PESCHE LAS 1045 pr gt TAS 30 10 EI r r ru 119 L A5 DQ5 LAG Dune pro DS 1 Mang pe DA ESCH 31 wu o ATI T Hae Mer 1 A6 DQG LA ey pepe ABLA LAG ae pee r AB 1 32 18 D r A8 13 r A8 13 A7 DQ7 pee ABB A9 33 42 D8 rag 14 ki D y A9 14 ki D8 A8 Dog AD9 PG0 KZ AD9 PG0 12107 ad WI DS oni Fe k r1 PA9 DQ9 A10 D10 parts D9 y L AU Tp pai P9 aire 22 oro DI GTI more ET I5 L SA10 A10 DQ10 EE page 010 CC EI e it LS SR Kee s mr i SESSI IRA PAT DQ11 jie DIS Map z pages DIL A12 ns paz z EIS 6 o DET neler s z We A12 DQ12 MMA AB Sapi BESSE M T cr Di 01950 Dis 1 IF nai mia A14 IBA DQ13 AK 19
16. Chapter 2 Getting Started on page 1 1 Provides information on the EZ KIT Lite from a programmer s perspective and provides an easy to access memory map Chapter 3 EZ KIT Lite Hardware Reference on page 3 1 Provides information on the hardware aspects of the evaluation system Appendix A Bill Of Materials on page A 1 Provides a list of components used to manufacture the EZ KIT Lite board ADSP BF533 EZ KIT Lite Evaluation System Manual xv What s New in This Manual Appendix B Schematics on page B 1 Provides the resources to allow EZ KIT Lite board level debug ging or to use as a reference design This appendix is not part of the online Help The online Help viewers should go the PDF version of the ADSP BF533 EZ KIT Lite Evaluation System Manual located in the Docs EZ KIT Lite Manuals folder on the installation CD to see the schematics What s New in This Manual This revision of the ADSP BF533 EZ KIT Lite Evaluation System Manual provides the updated schematics and information on the boot mode and core voltage source selection jumpers Technical or Customer Support You can reach DSP Tools Support in the following ways Visit the DSP Development Tools website at www analog com technology dsp developmentTools index html Email questions to dsptools support analog com Phone questions to 1 800 ANALOGD Contact your ADI local sales office or authorized distributor xvi AD
17. R60 R68 R76 88 16 1 65 1 8W 1 1206 R37 R44 R53 PANASONIC JERJ 8ENF1651V R61 R69 R77 89 10 10UF 16V 20 CAP002 CT3 12 DIGO1 PCE3062TR ND ELEC 90 1 153 6K 1 10W 1 805 R184 PHILIPS 9C08052A5362FKRT R ADSP BF533 EZ KIT Lite Evaluation System Manual A 7 5 3 E 2 EE 2 5 9112 9 amp m 2 8 2 E 5 jol c z E 91 1 JIOUH 47 20 IND001 L12 DIGOI 445 1202 2 ND 92 2 10K SOMW 5 BGA36 RN1 2 CTS RT130B7 93 115 10 00 100MW 5 805 R3 R22 R24 25 VISHAY CRCW0805 0 0 RT1 R111 R132 R135 136 R141 R186 189 R210 R222 94 190 100MHZ SA FER002 FER23 DLW5BSN191SQ2 95 1 13 32K 100MW 1 805 C188 DIG01 P3 32KCCTR ND 96 3 22 1 10W 5 805 R14 R180 181 VISHAY DAL CRCVV0805220 RT1 E 97 6 0 68UH 0 72 10 805 14 9 MURATA LQG2INR68K10T1 98 IA ZHCS1000SOT23D D5 ZETEX ZHCS1000 SCHOTTKY 99 11 5 6K 1 10W 5 805 R140 VISHAY CRCW0805562JRT1 100 15 2 2UH 0 63 10 805 L1 3 MURATA LQG21N2R2K10 10113 TUF 10V 10 805 C60 61 C104 AVX 0805ZC105KAT2A 1022 18 50VDC 5 805 CI C3 PANASONIC ECJ 2VC1H180 CERM 10311 10M 1 8W 5 805 R20 AVX CR21 106J T 10411 DB9 9PIN DB9M 2 3M 787203 2 RIGHTANGLEMALE 1057 IK 1 8W 5 1206 R115 R118 119 AVX CR32 102 T R125 126 R131 106 13 100 1 8W 5 1206 R112 R130 R176 CR1206 1003 FRTI 1072 22 1 8W 5 1206 R200 R207 DALE CRCW1206220JRT1 A 8 ADSP BF533 EZ KIT Lite
18. the installer To install the USB driver 1 If VisualDSP 3 5 is already installed on your system go to step 2 Otherwise run VisualDSP 3 5 installation Refer to the VisualDSP 3 5 Installation Quick Reference Card for a detailed installation description When installing VisualDSP 3 5 on Windows XP make sure the appropriate EZ KIT Lite component is selected for the installation ADSP BF533 EZ KIT Lite Evaluation System Manual 1 13 Installation Tasks 2 Connect the EZ KIT Lite device to your PC s USB port By connecting the device to the USB port you activate the Win dows XP Found New Hardware Wizard shown in Figure 1 10 Found New Hardware Wizard Welcome to the Found New Hardware Wizard This wizard helps you install software for ADSP BF533 EZ KIT Lite e If your hardware came with an installation CD os or floppy disk insert it now What do you want the wizard to do Install the software automatically Recommended Install from a list or specific location Advanced Click Next to continue Figure 1 10 Windows XP Found New Hardware Wizard 1 14 ADSP BF533 EZ KIT Lite Evaluation System Manual Getting Started 3 Select Install the software automatically Recommended and click Next When Windows XP completes the driver installation for the selected device see step 1 a window shown in Figure 1 11 appears on the screen Found New Hardware Wizard Completing the Found Ne
19. 17 ADSP BF533 EZ KIT Lite Evaluation System Manual I 5 INDEX decoder xiv installation 1 4 encoder xiv license 1 5 input mode 3 7 online Help xx interface 2 12 requirements 1 3 output mode 3 7 starting 1 16 VisualDSP voltage regulators 3 2 documentation xx VSYNC signal 3 6 3 7 3 11 l 6 ADSP BF533 EZ KIT Lite Evaluation System Manual
20. 22 TG ATTI JI L AD1836_CLK 25 MCLK 6 ra T 618 DAC2 LEFT L ouraL C pura 1 z n u SOK Ee GET MOSII CDATA OUT2R gt IOUT2R Q9 2 RIGHT L MISO COUT oun IGORR HA 4 LAIR INTL 1 1 5 N L OUT3L gt OUT3L I DAC3 LEFT IL ML OUTAL QUTaL 1 549K W 1206 T 1206 L NIRI pe OUT3R gt oun 1 DAC3 RIGHT R34 R36 INR D 81 JINIR oursr gt 0UT3R 1 1206 1206 L OUTIL IN2L CL2 CL2 DSDATA18 1 IN2L CL1 CL1 DSDATA2 IDTOSEC SE NC IN2L1 IN2L DSDATA3 2 36 r C IN2L2 IN2L DLRCLK 1TFSo__ DAC LEFT pack EES gt c14 0 00 680PF ADC RIGHE LE 1206 R40 805 R37 L IN2RTI C IN2R1 IN2R FILTR S eun inc rs MA 12 ji s 1 IN2R CR1 CR1 FILTD U OUTILH M CON024 7 IN2R CR2 CR2 r IDAG LEFT Tale r tus 1 Kb 10UF 0 TS USAR AD1836_RESETI PD RST i 274K 220PF 1206 1206 C12 R38 ee 2200PF 49 9K MQFP52 AD1836 VRET Bl T 1206 1206 e C9 C10 e 3 uie 0 001UF 0 001UF 0 001UF A i 805 805 805 805 m 589 777 2 AD8606AR SOIC8 R28 R27 0 00 1206 XK DNP Do Not Populate For test only R193 0 00 ANAI Ol I 20 Cotton Road SW1 1206 Title 5 Approvals Mate A
21. 3 3V OCTAL BUFFER 3 11 IDT74FCT3807AQ U4 IDT IDT74FCT3807AQ QSOP20 3 3V 1 10 CLOCK DRIVER 4 11 7 64603 128 PQFP128 U34 CYPRESS CY7C64603 128NC USB TX RX MICROCON TROLLER 5 MMBT4401 SOT 23 QI FAIRCHILD MMBT4401 NPNTRANSISTOR200MA 6 74LVCOOAD SOIC14 U9 PHILIPS 74LVC00AD 7 J CY7C1019BV33 15VC U39 CYPRESS CY7C1019BV33 12VC SOJ32 128K X 8 SRAM 8 SN74AHC1G02 SOT23 5 1044 TI SN74AHC1G02DBVR SINGLE 2 INPUT NOR 9 H1 SN74LV164A SOIC14 U35 TI SN74LV164AD 8 BIT PARALLEL SERIAL ADSP BF533 EZ KIT Lite Evaluation System Manual A 1 5 Y 1S 9 m 2 ERE ee E 5 2 lele sb 3 2 8 8 E 55 1018 2 A gt Z 10 1 CY7C4201V 15AC U43 CYPRESS CY7C4201V 15AC TQFP3264 BYTE FIFO 11 112 0MHZ THR OSC006 Y1 DIG01 300 6027 ND CRYSTAL 12 11 ISNZ4AHC1G00 SOT23 5 U42 TI SN74AHC1G00DBVR SINGLE 2 INPUT NAND 13 1 112 283MHZ SMT OSC003 U11 DIGO1 SG 8002CA PCC ND 14 SN74LVC1G125 SOT23 5 JU7 TI SN74LVC1G125DBVR SINGLE 3STATE BUFFER 15 JNDS8434A SO 8 U32 FAIRCHILD NDS8434A P MOSFET SEMI 16 11 MTA48LCIGMIGA2TG 75 U8 MICRON MT48LC16M16A2TG 75 TSOP54 256MB SDRAM 17 1 27MHZ SMT OSC003 U3 EPSON SG 8002CA MP 18 1 132 768KHZ SMT OSC008 U2 EPSON MC 156 32 768KA A2 19 12 PSD4256G6V 10U1 TSOP54 U5 6 ST MICRO PSD4256G6V 10UI 1MB FLASH GPIO 20 1 2305 1 SOIC8 U46 INTE ICS9112AM 16 1 TO 5 ZER
22. 43 IPFIB 71 KA Sa 46 45 Piel 46 45 IPF13 1 A jiem 48 47 TET 48 47 PPT 1 Se ees 50 49 i PF8 50 49 IPF9 52 51 R bi n 54 53 PF4 54 53 1 1 ilmini 56 55 I PF2 56 55 IPF3 58 57 58 57 PEO 58 57 IPF1 1 60 59 i kaskas 60 59 62 61 AMS3 62 61 SPORTO 62 61 64 53 a 64 63 R174 P3 66 65 L ABEHSDOMT 14 AMSL om 65 1206 L DTOPRI lt F 68 67 L ABEO SDQMO x Pe AMSO _ 68 67 L _DTOSE lt J 70 69 i AOE 8 a gt TARDY 70 69 L TESA 5 p 72 d daimi n L AWEL a ARE 1 72 7 1 E 3 Pro gt TEXPANSION_PPI_CLK 72 d SS 5 5 9 10 74 73 UOS E AA 74 73 L TSCLKO1 bd PPL i 74 GN E T 11 12 po hb 76 75 mese U SMS 76 75 IRSCLKO 1 IPP3 C D 7 ER o Se AR di O 0007 77 ti i 76 75 13 7 78 77 M 78 77 R175 78 77 15 16 m ram 0 00 80 79 80 79 DES 1206 es 1 80 79 ET 3 17 18 I lt h 82 81 us 511 eium 82 81 LE DROSEC asl e O 222 BA S e l 84 ka SRASI B ISCKE 7 adl e J 7 IDROPRI 1 gimme 84 83 imm IBG I GONUMM 86 B5 L 5 10 ISCAS 86 85 10 2 86 BST a i gt Bon 88 B7 i SWE ICLK OUT EXP2 88 87 zm e e e Sea 88 87 SA CE e e 90 89 90 89 90 89 45X2 45X2 CON019 45X2 CON019 NZ CON019 e O Z KA Z DNP Do Not Populate ANALOG 20 Cotton Road
23. KIT installation directory to demon strate how to program the Flash memory as well as to demonstrate the functionality of the general purpose IO pins Flash Memory Map Each device includes the following memory segments 1M byte of primary Flash memory 64K bytes of secondary Flash memory 32 Kbytes of internal SRAM 256 Bytes of configuration registers IO control Access to each segment can be 8 bit or 16 bit The processor s AMS0 AMS1 and AMS2 memory select pin are used for that purpose Asynchro nous memory Bank 0 is always enabled after a hard reset while Banks 1 and 2 need to be enabled by software Table 2 4 provides an example on asynchronous memory configuration registers Table 2 4 Asynchronous Memory Control Registers Settings Example Register Value Function EBIU_AMBCTLO 0x7BB07BBO Timing control for Banks 1 and 0 EBIU AMBCTLI bits 15 0 0x7BBO Timing control for Bank 2 Bank 3 is not used EBIU_AMGCTL bits 3 0 OxF Enable all banks Each Flash chip is initially configured with the memory sectors mapped into the processor s address space as shown in Table 2 5 2 6 ADSP BF533 EZ KIT Lite Evaluation System Manual Using EZ KIT Lite Table 2 5 Flash Memory Map Start Address End Address Content 0x2000 0000 0x200F FFFF Flash A Primary 1MB 0x2010 0000 0x201F FFFF Flash B Primary 1MB 0x2020 0000 0x2020 FFFF Flash A Secondary 6
24. Lite Evaluation System Manual 1 9 Installation Tasks 6 Click Next Windows 98 locates the WmUSBEz inf file on the installation CD as shown in Figure 1 5 Add New Hardware Wizard Figure 1 5 Windows 98 Locating Driver 7 Click Next The Coping Files dialog box appears Figure 1 6 Copying Files La Figure 1 6 Windows 98 Searching for SYS File 1 10 ADSP BF533 EZ KIT Lite Evaluation System Manual Getting Started 8 Click Browse The Open dialog box shown in Figure 1 7 appears on the screen Open WmUSBEz sys WmUSBEz sys Figure 1 7 Windows 98 Opening SYS File 9 In Drives select your CD ROM drive 10 Click OK The Copying Files dialog box Figure 1 8 appears Copying Files m Figure 1 8 Windows 98 Copying SYS File 11 Click OK ADSP BF533 EZ KIT Lite Evaluation System Manual 1 11 Installation Tasks The driver installation is now complete as shown in Figure 1 9 Add New Hardware Wizard Hui ADSP BF533 EZ K T Lite Windows has finished installing the software that your new hardware device requires Figure 1 9 Windows 98 Completing Software Installation 12 Click Finish to exit the wizard Verify the installation by following the instructions in Verifying Driver Installation on page 1 15 Windows 2000 USB Driver VisualDSP 3 5 installation software pre installs the necessary drivers for the selected EZ KIT Lit
25. Nashua NH 03063 DEVICES PH 1 800 ANALOGD Title Approvals Date 775 ADSP BF533 EZ KIT LITE CONNECTOR Drawn C 1 6 Engineering Date 2 12 2004 15 37 Sheet 10 of 13 A B C D A B C D 5V A5V s r x F1 FER23 D2 R177 FER18 2 5A CHOKE_COIL 2A VR5 0 00 600 FUS001 DO 214AA 8 l 1206 1206 P s Pret SINPUT OUTPUT d l _UNREG IN i bassai TE eo G ADP3330AKC R178 FER19 J9 SOT 223 VR1 0 00 600 1206 1206 C97 p R176 cT22 C98 cr23 C175 3 2 PR 1000PF DO 214AA 100K 10UF 0 1UF 10UF 0 1UF e INPUT OUTPUT 9 2 1206 1206 Mc T 805 Mc T 805 GND 11 ADP3338AKC 33 3 SOT 223 BVI R C104 era C143 CON005 UF 10UF 04UF 2 5MM JACK T 805 Mc T 805 e e e e e e e C96 1000PF T 1206 R186 0 00 805 XO B VDDRTC R187 OOO i s A 805 4 DSP VDD EXT 57 DSP VDD P R223 04 3 32K 2A 805 DO 214AA IDSP VDD INT 7
26. P P15 m O N TUNRE IN m R188 U32 L12 R222 VR3 0 00 10UH 0 00 m 805 q NDO01 805 IDSP VDD INT 3 e NPUT OUTPUT e 1 b OY YS e 11 GND 2 EN 6 T ADP3339AKC 33 SHORTING SOT 223 3 7 JUMPER e S ka ToT DEFAULT 2 amp 3 cT25 C100 era ET 4 8 8 68UF 10UF 0 1UF 10UF L ROUT ZHCS1000 T D Mc 7T 805 Mc SOT23D SW10 Core Voltage Source Select 4 1A DEFAULT 2 amp 3 NDS8434A JP3 E SO 8 1 osition unction C105 0 1UF 1 and 2 DSP_VDD_INT DSP Internal Voltage Regulation A H 805 jp 3 2and3 DSP VDD INT 1 4V Fixed IDC3XI 3X1 Note For boards without a 750MHz processor this jumper will not be populated and the DSP_VDD_INT will be hard wired with R222 to use the processor internal regulator ER 3 3V R211 L NREG N O 0 00 203 VR6 T 805 VR4 0 00 R214 INI oun i L 805 10K Bs G r DNP e INPUT OUTPUT b R184 GND OUT 64 9K 11 ADP3339AKC 33 6 5 R210 805 3 3V 3 3V 1 8V A1 8V SOT 223 SD GND FB 0 00 O O O O 4 ADP3336ARM 805 C61 eng eren C101 CT26 MSOP8 UF 10UF 10UF 0 1UF 10UF T 805 INC Mc T 805 Mc R FER20 60 VR2 1206 1 R185 7 1 805 340K R192 N DUT EE S Soe Du OUT2 3 R190 OUT3 76 8K C103 5 1206 1UF SD GND FB 805 ARM v MSOP8 C102 1UF R191 T 805 147K 1206 FER21 600 1206 Disk DNP Do Not Populate MH2 M
27. Select Jumper JP3 Table 3 5 Core Voltage Source Settings Position Core Voltage Source l and 2 Processor Internal Voltage Regulator 2 and 3 1 4V External Regulator 3 10 ADSP BF533 EZ KIT Lite Evaluation System Manual EZ KIT Lite Hardware Reference Test DIP Switches SW2 1 Two DIP switches SW1 and SW2 are located on the bottom of the board The switches are used only for testing and should always be in the OFF position Video Configuration Switch SW3 The video configuration switch SW3 controls how some video signals from the ADV7183 video decoder and ADV7171 video encoder are routed to the processor s PPI The switch also determines if the PF2 pin controls the OE of the ADV7183 video decoder outputs Table 3 6 shows which processor s signals are connected to the encoder and decoder when in the ON position Table 3 6 Video Configuration Switch SW3 Switch Position Default Processor Signal Video Signal 1 OFF TMR1 HSYNC HSYNC ADV7171 2 OFF TMR1 HSYNC HS ADV7183 3 OFF TMR2 VSYNC VS ADV7183 4 OFF TMR2 VSYNC VSYNC ADV7171 5 OFF PF3 FIELD FIELD ADV7183 6 ON PF2 0E ADV7183 Positions 1 thorough 5 of SW3 determine how and if the VSYNC HSVNC and FIELD control signals are routed to the processors PPI In standard config uration of the encoder and decoder this is not necessarv because the p
28. Trace Butter Da sea elele elsi elsi 2 15 puc ers Doo E 2 15 Eed 2 16 A 2 17 E 217 aT malaio FE Ula 2 17 Oiber OPANG Eege 2 18 Restricted Software Breakpoints pi ayl 2 19 EZ KIT LITE HARDWARE REFERENCE oxunu MEC adad 3 2 Kuti Dus r LE ae aaa bankla 3 3 SPORTO VUR E 3 4 SPI DONE A AM A R KE RM ON 3 4 Programmable Flags ia e ii allel bi 3 4 PIE rs 3 5 Vid o Output Mode ge ak aa a b 3 7 balal 3 7 VART A A 3 8 ADSP BF533 EZ KIT Lite Evaluation System Manual vii CONTENTS Esparti n T R 3 8 TEM PUN EE 3 9 Jumper and DIP Seat Seting Mm 3 9 Boot Made Select Jumpers PDT sna re 3 10 Core Voltage Source Select Jamper UPS ali daa 3 10 Test DIP Switches ii 3 11 Video Configuration Swatch SW ii 3 11 Push Button Enable Switch 5879 ese rara 3 12 LEDs and Pol Burtons uuu aba e o l 3 13 Programmable Flag Push Buttons SW7 4 3 13 Reset Push Bottom 3 14 Eu r e EE 3 14 Rest LEDE LED ii id 3 14 User LEDs LEDO a i R da 3 15 USB Monit r LED LED coi 3 15 OPE DOE aa o bab 3 16 Expansion merinoz 2 1 3 16 PAO a aa yaa 3 17 55 11 0 usis 3 17 A 3 17 PIN NEEN 3 18 575 aaa 3 19 OPO IP 5 kesik eli degen 3 19 NK E 3 20 viii ADSP BF533 EZ KIT Lite Evaluation System Manual BILL OF MATERIALS INDEX CONTE
29. for information about changing the default boot mode External Bus Interface Unit The External Bus Interface Unit EBIU connects an external memory to the ADSP BF533 device It includes a 16 bit wide data bus an address bus and a control bus Both 16 bit and 8 bit access are supported On the EZ KIT Lite the EBI unit connects to SDRAM and Flash memory 32 Mbytes 16M x 16 bits of SDRAM connect to the synchronous mem ory select 0 pin 5 50 Refer to Using SDRAM Interface on page 2 4 for information about configuring the SDRAM Note that SDRAM clock is the processor s Clock Out CLK 0UT which frequency should not exceed 133 MHz Two Flash memory devices are connected to the asynchronous memory select signals AMS2 through AMSO The devices provide total of 2 Mbytes of primary Flash memory 128 Kbytes of secondary Flash memory and 64 Kbytes of SRAM The processor can use this memory for both booting and storing information during normal operation Refer to Using Flash Memory on page 2 5 for details All of the address data and control signals are available externally via the extender connectors P3 1 The pinout of these connectors can be found in Appendix B Schematics on page B 1 ADSP BF533 EZ KIT Lite Evaluation System Manual 3 3 System Architecture SPORTO Audio Interface The SPORTO interface is connected to the AD1836 audio codec the SPORT connector P3 and the expansion interface The AD183
30. in Session Name or accept the default name Click OK to return to the Session List Highlight the new session and click Activate ADSP BF533 EZ KIT Lite Evaluation System Manual 1 17 Installation Tasks 1 18 ADSP BF533 EZ KIT Lite Evaluation System Manual 2 USING EZ KIT LITE This chapter provides specific information to assist you with developing programs for the ADSP BF533 EZ KIT Lite evaluation system The Information appears in the following sections EZ KIT Lite License Restrictions on page 2 2 Describes the restrictions of the VisualDSP license shipped with the EZ KIT Lite Memory Map on page 2 2 Defines the ADSP BF533 EZ KIT Lite board s memory map Using SDRAM Interface on page 2 4 Defines the register values to configure the on board SDRAM Using Flash Memory on page 2 5 Describes the on board Flash memory Example Programs on page 2 13 Provides information about the example programs included in the ADSP BF533 EZ KIT Lite evaluation system Using Background Telemetry Channel on page 2 13 Highlights the advantages of the Background Telemetry Channel feature of VisualDSP Using EZ KIT Lite VisualDSP Interface on page 2 13 ADSP BF533 EZ KIT Lite Evaluation System Manual 2 1 EZ KIT Lite License Restrictions Describes the trace performance monitoring boot loading con text switching and target options facilities of the EZ KIT Lite system Fo
31. sample rate but allows for simultaneous use of all input and output channels When using I S mode the TSCLKO and RSCLKO pins as well as the TFS0 and RFSO pins of the processor must be tied together external to the processor This is accomplished with the SW9 DIP switch see Push Button Enable Switch SW9 on page 3 12 for more information The AD 1836 audio codec s internal configuration registers are configured using the processor s SPI port The processor s PF4 programmable flag pin is used as the select for this device For information on how to configure the multichannel codec go to www analog com UploadedFiles Datasheets 344740003AD1836_prc pdf The reset for the AD1836 codec comes from the general purpose IO pin PAO of Flash A For information on how to use the pin see Flash Gen eral Purpose IO on page 2 7 Example programs are included in the EZ KIT installation directory to demonstrate the AD 1836 codec operation ADSP BF533 EZ KIT Lite Evaluation System Manual 2 11 Using Video Using Video The board supports video input and output applications The ADV7171 video encoder provides up to three output channels of analog video while the ADV7183 video decoder provides up to three input channels of analog video Both the encoder and the decoder connect to the Parallel Peripheral Interface PPI of the ADSP BF533 processor For additional information on the video interface hardware refer to PPI Interface
32. the ADSP BF533 Blackfin Processor Hardware Refer ence Table 3 2 describes the PPI pins and their use on the EZ KIT Lite board Table 3 2 PPI Connections DSP PPI Pin Other DSP Function EZ KIT Function PPI7 PF12 ADV7171 and ADV7183 Data MSB PPI6 PF13 ADV7171 and ADV7183 Data 15 PF14 ADV7171 and ADV7183 Data PP14 PF15 ADV7171 and ADV7183 Data PPI3 ADV7171 and ADV7183 Data PPI2 ADV7171 and ADV7183 Data PPII ADV7171 and ADV7183 Data PPIO ADV7171 and ADV7183 Data PF3 FS3 ADV7183 Field Pin For more information see Video Configuration Switch SW3 on page 3 11 TMR1 PPI HSYNC ADV7171 and ADV7183 HSYNC For more information see Video Configuration Switch SW3 on page 3 11 TMR2 PPI FSYNC ADV7171 and ADV7183 VSYNC For more information see Video Configuration Switch SW3 on page 3 11 PPI CLK Input from either the ADV7183 output clock or the same 27 MHz oscillator driving the pro cessor For more information see Using Video on page 2 12 The ADSP BF533 EZ KIT Lite board employs 8 bit PPI interface for video output and video input 3 6 ADSP BF533 EZ KIT Lite Evaluation System Manual EZ KIT Lite Hardware Reference Video Output Mode In the video output mode the PPI interface is configured as output and connects to the on board video encoder device ADV7171 The ADV7171 encoder device generates three analog video channels on DAC 8 D
33. verify all writes to target memory Reset cycle counters on run On Emulator E xit Run from current PC y V Auto configure SDRAM Flash tel Figure 2 3 Target Options Dialog Box Reset Options Reset options control how the processor behaves when a reset occurs The reset options are described in Table 2 11 Table 2 11 Reset Options Option Description Core reset Resets the core when the debugger executes a reset Svstem reset Resets the peripherals when the debugger executes a reset On Emulator Exit This target option controls processor behavior when VisualDSP relin quishes DSP control for example when exiting VisualDSP The option is described in Table 2 12 ADSP BF533 EZ KIT Lite Evaluation System Manual 2 17 Using EZ KIT Lite VisualDSP Interface Table 2 12 On Emulator Exit Target Options Option Description location Stall the DSP resets the DSP and then writes a JUMP 0 to the first location in internal memory so the DSP is stuck in a tight loop after exiting On Emulator Exit Determines the state the DSP is left in when the emulator relinquishes con trol of the DSP Reset DSP and Run causes the DSP to reset and begin execution from its reset vector location Run from current PC causes the DSP to begin running from its current Other Options Table 2 13 describes other available target options Table 2 13 Miscellaneous Target Option
34. 0003a JUMP S LOOP2 00000005 Cycle 00000000 PM f0000040 NOP Figure 2 1 Trace Window The trace buffer stores a history of the last 16 changes in program flow taken by the program sequencer View the history to recreate the program sequencer s most recent path The trace buffer does not track changes in flow caused by zero overhead loops or while in the reset service routine To use the trace buffer ensure your program leaves the reset service routine Enabling Trace Buffer To view trace history in the Trace window first enable the trace buffer choose Enable Trace from the Tools Trace menu On each halt the Trace window is updated with the changes that occurred since the last halt Reading the trace buffer destroys the trace buffer s contents and dis cards the information previously stored before the last run 2 14 ADSP BF533 EZ KIT Lite Evaluation System Manual Using EZ KIT Lite Reading Trace Buffer Data The first column between the square brackets in blue indicates the line number in the Trace window The second column between square brackets which comes in vertical pairs shows the trace number For each discontinuity the first top posi tion is the source trace and the second bottom position is the destination trace The third column in between square brackets shows the addresses of the instructions Each address is followed by the assembly instruction The trace grows upwar
35. 13 B C D PPICLK ONBOARD SELECT PPICLK AD7183 SELECT PPCLK 0 0 PPI 27MHZ CLK DEFAULT 0 1 ADV7183 CLKOUT DAC C DAC 1 X EXPANSION CLK Composite Video CVSB CVSB Component Video B R G Differential Component Video U V y 1 i 3 5 C Y MEER PPI 27MHZ CLK U26 R132 Enc 1 3 0 00 805 T 6 paq 1 1 AE ADV7183 CLKOUT gt IPPILCLK 1 R125 6 A 1K PPICLK AD7183 SELECT 3 1206 EE A RARA ADG752BRT SOT23 6 A3V Q SOT23 6 L EXPANSION PPI CLKI EE a PPICLK ONBOARD SELECT U24 J8 R127 3X2 4 5 75 CON024 L5 L3 L4 1206 BES DRE WE 2 0 68 2 2UH 0 68UH 1 VIDEO DAC B 5 1 805 805 805 GEES SR J DAC B aa 3 AD8061ART 3V B 1 YYY ZE NH NAVY b SOT23 5 NL 6 m R126 ii R123 C69 C70 R124 1K 75 330PF 330PF 75 1206 1206 805 T 805 1206 VIDEO ENCODER R128 C71 C72 R129 10K 0 1UF 0 1UF 1 2K TP4 805 805 805 1206 O U27 SVV2 AGKD2 A TOA M P pis DAC APP V
36. 46 C147 C145 C148 C144 C95 C119 C132 C128 C204 C156 C157 C158 C152 C163 C161 C209 0 01UF 0 01UF 0 1UF 0 1UF 0 1UF 0 1UF 0 01UF 0 01UF 0 1UF 0 1UF 0 1UF 0 01UF 0 01UF 0 01UF OUR 805 805 805 805 805 805 T 805 T 805 T 805 805 805 805 805 J 805 T 805 J 805 IT 805 e e e e e e e e e ADV7171 ADV7183 ADM708SAR ADMS202 IDT74FCT3244APY IDT2305 U27 U28 U29 U30 U31 U46 DNP Do Not Populate ANALOG 20 Cotton Road Nashua NH 03063 DEVICES PH 1 800 ANALOGD Title 5 e i ADSP BF533 EZ KIT LITE BYPASS CAPS Checke d ra Board No A0167 2001 ic Engineering Date 2 2 2004 19 17 Sheet 12 of 13 A B D INDEX Symbols AMS0 memory select pin 2 3 2 6 3 3 AMS1 memory select pin 2 3 2 6 2 3 AMS2 memory select pin 2 3 2 6 3 3 SMS0 memory select pin 2 2 3 3 A AD1836 2 11 3 4 3 12 Add New Hardware Wizard Windows 98 1 8 ADSP BF533 processor address space 2 6 audio interface see SPORTO Clock In CLK IN 3 7 Clock Out CLK OUT 3 3 core voltage 3 2 External Bus Interface Unit EBIU 3 3 Input clock 3 3 Internal memory restrictions 2 2 internal SRAM 2 2 IO voltage 3 2 memory map 2 2 parallel peripheral interface PPI 3 5 peripheral ports xiv real time clock RTC 3 3 ADV7171 video encoder 2 12 3 6 3 7 3 11 ADV7183 video decoder 2 12 3 6 3 7 3 11 ASYNC memory banks 0 3 2 3 audio applica
37. 4KB 0x2024 0000 0x2024 7FFF Flash A SRAM 32KB 0x2027 0000 0x2027 00FF Flash A Registers 256 Bytes 0x2028 0000 0x2028 FFFF Flash B Secondary 64KB 0x202C 0000 0x202C 7FFF Flash B SRAM 32KB 0x202E 0000 0x202E 00FF Flash B Registers 256 Bytes All other locations Reserved Flash General Purpose IO This section describes general purpose IO signals that are controlled by means of setting appropriate registers of the Flash A or Flash B These reg isters are mapped into the processor s address space as shown in Table 2 5 on page 2 7 Flash device IO pins are arranged as 8 bit ports labeled A through G There is a set of 8 bit registers associated with each port These registers are Direction Data In and Data Out Note that the Direction and Data Out registers are cleared to all zeros at power up or hardware reset The Direction register controls IO pins direction When a bit is 0 a cor responding pin functions as an input When a bit is 1 a corresponding pin is an output This is a 8 bit read write register The Data In register allows reading the status of port s pins This is a 8 bit read only register ADSP BF533 EZ KIT Lite Evaluation System Manual 2 7 Using Flash Memory The Data Out register allows clearing an output pin to 0 or setting it to 1 This is a 8 bit read write register The ADSP BF533 EZ KIT Lite board employs only Flash A and Flash B ports A and B Table 2 6 and Table 2 7 provide configu
38. 50 BEAD 71 13 2A S2A RECT DO 214AA D2 4 GENER S2A SILICON RECTIFIER ALSEMI 72 112 1600 100MHZ 500MA 1206 FER1 5 DIGI KEY 1240 1019 1 ND 0 70 BEAD FER9 11 FER18 19 FER18 19 FER21 22 73 14 237 1 8W 1 1206 R93 R95 R97 AVX CR32 2370F T R99 74 4 750K 1 8W 1 1206 R86 R90 R94 DALE VISH CRCV 12067503FRT1 R96 AY 75 116 15 76K 1 8W 1 1206 R82 85 R87 89 PHYCOMP 19C12063A5761FKHFT R91 92 R98 ADSP BF533 EZ KTT Lite Evaluation System Manual Bill Of Materials 9 o 3 o 3 85 F E es bb 3 2 3 5 HE e A ez A gt EZ 76 16 11 0K 1 8W 1 1206 R34 R48 R50 DALE CRCW12061102FRT1 R58 R66 R74 77 8 120PF 50V 5 1206 C42 45 C55 PHILLIPS 1206CG121J9B200 NPO C57 59 78 1 168PF 50V 5 1206 C82 PHILLIPS 1206CG680J9B200 79 1 TUF 16V 10 805 C5 MURATA GRM40X7R105K016AL X7R 80 112 75 1 8W 5 1206 R113 114 PHILIPS 9C12063A75ROJLHFT R116 117 R120 121 81 12 130PF 100V 5 1206 206 207 12061 2 82 1 68UF 6 3V 20 D CT28 PANASONIC ECS TOJD686R TANT 83 16 1680PF 50V 1 805 C14 C19 C24 AVX 08055A681FAT2A NPO C29 C34 C39 84 13 JIOUF 25V 80 2096 1210 C198 200 MURATA GRM235Y 5V106Z025 Y5V 85 16 12 74K 1 8W 1 1206 R41 R47 R57 PANASONIC JERJ 8ENF2741V R65 R73 R81 86 12 5 49K 1 8W 196 1206 R35 R40 R42 PANASONIC ERJ 8ENF5491V RA9 R5L R56 R59 87 16 13 32K 1 8W 1 1206 R36 R43 R52 DALE CRCW12063321FRT1
39. 6 codec uses both the primary and secondary data transmit and receive pins to input and output data from the audio input and outputs The pinout of the SPORT connector and the expansion interface connec tors can be found in Appendix B Schematics on page B 1 SPI Interface The processor s Serial Peripheral Interconnect SPI interface is connected to the AD1836 audio codec and the expansion interface The SPI connec tion to the AD1836 is used to access the control registers of the device The PF4 flag of the processor is used as the devices select for the SPI port Programmable Flags The processor has 15 programmable flag pins PFs The pins have multi ple functions depending on the setup of the processor Table 3 1 shows how the programmable flag pins are used on the EZ KIT Lite Table 3 1 Programmable Flag Connections DSP PF Pin Other DSP Function EZ KIT Function PFO Serial clock for programming ADV7171 and ADV7183 PF1 Serial data for programming ADV7171 and ADV7183 PF2 ADV7183 0E PF3 FS3 ADV7183 Field Pin See Video Configuration Switch SW3 on page 3 11 PF4 AD1836 SPI Select 3 4 ADSP BF533 EZ KTT Lite Evaluation System Manual EZ KIT Lite Hardware Reference Table 3 1 Programmable Flag Connections Contd DSP PF Pin Other DSP Function EZ KIT Function PF5 PF6 PF7 PF8 Push button SW4 See Using L
40. AC C and DAC D outputs The PPI data connects to P7 0 of the encoder s pixel inputs The encoder s PPI input clock runs at 27 MHz and it is in phase with CLK IN of the ADSP BF533 processor The encoder s synchronization signals HSYNC and VSYNC can be config ured as inputs or outputs Video Blanking control signal is at level 1 The HSYNC and VSYNC signals can be connected to the ADSP BF533 pro cessor s multiplexed sync pins and to the on board video decoder ADV7183 via the SW3 switch as described in Video Configuration Switch SW3 on page 3 11 Video Input Mode In the video input mode the PPI interface is configured as input and con nects to the on board video decoder device ADV7183 The ADV7183 decoder receives three analog video channels on AIN1 AIN4 and AIN5 input The decoder s pixel data outputs P15 8 drive the PPI data PP13 0 and PF15 12 The decoder s 27 MHz pixel clock output can be selected to drive PPI clock as shown in Table 2 8 on page 2 8 Synchronization outputs of the decoder HS HACTIVE VS VACTIVE and FIELD can connected to the ADSP BF533 processor s multiplexed sync pins and to the on board video encoder ADV7171 via the SW3 DIP switch as described in Video Configuration Switch SW3 on page 3 11 ADSP BF533 EZ KIT Lite Evaluation System Manual 3 7 System Architecture UART Port The processor Universal Asynchronous Receiver Transmitter UART port is connected to the ADM3202
41. ADSP BF533 EZ KIT Lite Evaluation System Manual Revision 1 3 April 2004 Part Number 82 000730 01 Analog Devices Inc One Technology Way ANALOG Norwood Mass 02062 9106 O DEVICES Copyright Information 2004 Analog Devices Inc ALL RIGHTS RESERVED This docu ment may not be reproduced in any form without prior express written consent from Analog Devices Inc Printed in the USA Limited Warranty The EZ KIT Lite evaluation system is warranted against defects in materi als and workmanship for a period of one year from the date of purchase from Analog Devices or from an authorized dealer Disclaimer Analog Devices Inc reserves the right to change this product without prior notice Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by impli cation or otherwise under the patent rights of Analog Devices Inc Trademark and Service Mark Notice The Analog Devices logo VisualDSP VisualDSP logo Blackfin CROSSCORE logo and EZ KIT Lite are registered trademarks of Analog Devices Inc All other brand and product names are trademarks or service marks of their respective owners Regulatory Compliance The ADSP BF533 EZ KIT Lite evaluation system has been certified to comply with the essent
42. ADSP BF533SKBC Ul ANALOG MINIBGA160 DEVICES ADSP BF533 EZ KTT Lite Evaluation System Manual A 3 gt 9 9 8 2 ERE 2 E 5 8218 bb 5 2 4152 E EE e OA SE gt AZ 38 1 AD1836AAS MQFP52 U14 ANALOG AD1836AAS MULTI CHAN DEVICES NEL 96KHZ CODEC 39 5 RUBBER FEET BLACK MH1 5 MOUSER 517 SJ 5018BK 40 PWR2 5MM JACK J9 SWITCH SC1152 ND12 CON005 CRAFT RA 41 11 USB 4PIN CON009 J10 MILL MAX 897 30 004 90 000000 USB 42 1 RCA2X2 CON013 JS SWITCH PJRAS2X2S01 CRAFT 43 1 1 05 10X2 CONO14 P3 AMP 104069 1 RA 44 15 SPST MOMENTARY SW4 8 PANASONIC EVQ PAD04M SWT013 6MM 45 1 IDC 7X2 IDC7X2SRDRA TI MOLEX 70247 1401 RIGHT ANGLE SHROUDED 46 13 10 05 45X2 CON019 J1 3 SAMTEC SFC 145 12 F D A SMT SOCKET 47 4 DIP6 SWTO017 SW1 3 SW9 DIGO1 CKN1364 ND 48 12 RCA 3X2 CON024 J4 8 SWITCH PJRAS3X2S01 RA CRAFT 49 114 10 00 1 8W 5 1206 R27 30 R148 YAGEO 0 0ECT ND R157 158 R167 R174 175 R177 178 R182 R193 A 4 ADSP BF533 EZ KIT Lite Evaluation System Manual Bill Of Materials y o 2 o S 2 ERE E 2 2 B E 9 b amp b 3 2 EE 59 E 55 jol ZA gt E 50 7 AMBER SMT LED001 LED4 9 LED11 PANASONIC ILN1461C TR GULL WING 51 112 330pF 50V 5 805 C13 C18 C23 AVX 08055A331JAT NPO C28 C33 C38 52 142 0 01uF 100V 10 805 C4 C85 C87 AVX 08051C103KAT2A CERM C108 C112 113 C123 124
43. AT lt Mtr TDIMS l TDI E12 222 K2 N2 SAT gt Sa L w TMR2 TMS TMS R2 R10 BRI E D BR smse gt ISMS TRST e TRST Kos Se L BG lt PG L RIXI Par EMUM2 EMU aen ou DSP OLK Ao eno XTALOA BMODEO Z BMODEO C Hu B10 MI BMODE1 3 BMODE wou e MAD L RESET RESET VROUT2 l mE Sur R17 R3 i R11 i T 805 ADSP BF533 750 4 7K 0 00 0 00 DNP MINIBGA160 805 805 2 805 2 DNP DNP IDC2X1 IDC2X1 R13 E E 2X1 2X1 10K MINIBGA160 805 e Z DNP Do Not Populate ANALOG 20 Cotton Road Nashua NH 03063 DEVICES PH 1 800 ANALOGD Titl ar A eg ADSP BF533 EZ KIT LITE DSP Drawn Checke d ra Board No A0167 2001 E Engineering Date 3 2 2004_15 06 Sheet 2 of 12 A B C A C D 3 3V Fl
44. B debug agent supports the Background Telemetry Channel BTC which facilitates data exchange between VisualDSP and the processor without interrupting DSP execution The BTC allows the user to view a variable as it is updated or changed all while the processor continues to execute For increased performance of the BTC including faster reading and writing please check out our latest line of DSP emulators at www analog com Analog Root productPage productHome 0 2121 EMULA TORS 00 html For more information about the Background Telemetry Channel see the VisualDSP 3 5 Users Guide for 16 Bit Processors or online Help Using EZ KIT Lite VisualDSP Interface This section provides information on the following parts of the Visu alDSP graphical user interface Trace Window on page 2 14 Performance Monitor on page 2 15 Boot Load on page 2 16 ADSP BF533 EZ KIT Lite Evaluation System Manual 2 13 Using EZ KIT Lite VisualDSP Interface Target Options on page 2 17 Restricted Software Breakpoints on page 2 19 Trace Window Choosing the Trace command from the View gt Debug Windows menu opens the Trace window Figure 2 1 gt Trace L JDIXI 00000000 Cycle 00000002 PM f000005c JUMP S LOOP4 00000001 Cycle 00000002 PM f0000064 NOP 00000002 Cycle 00000001 PM f000004a JUMP S LOOP3 00000003 Cycle 00000001 PM f0000052 NOP 00000004 Cycle 00000000 PM f00
45. DSP BF533 EZ KIT LITE AUDIO CODEC Board No A01 67 2 0 01 ic Engineering Date 2 11 2004 14 35 Sheet 4 of 13 C A B C D R67 C35 5 49K 100PF 1206 1206 R59 C30 R66 R68 5 49K 100PF 11 0K 3 32K 1206 1206 1206 1206 L OUT2R1 R58 R60 11 0K 3 32K 1206 1206 Sir L OUTSR I T 805 2 C28 DAC2 RIGHT 330PF 3 T 805 6 SPF R72 T 805 R69 DAC3 RIGHT r 5 49K 1 65K 604 5 1206 1206 1206 7 29 1 SON 3X2 680PF L__OUT2R CAP005 CON024 R64 T 805 R61 5 49K 1 65K 604 4 Tp iDA 2 RIGHT 4 1 1206 1206 1206 pg JA L__OUTSR 10UF CONO24 R73 C36 CAP002 ae 2 74K 220PF 6 asf IDACS RIGHT 1 ZTN 1206 T 1206 C32 R70 A NNWf 8 S 2200PF 49 9K AE AD1836_VREF 1206 1206 R65 C31 2 74K 220PF 3 1206 T 1206 C27 R62 E 2200PF 49 9K AD1836 VREFI T 1206 1206 e e e e AGND AGND R75 C40 5 49K 100PF 1206 T 1206 R51 C25 5 49K 100PF R74 R76 1206 T 1206 11 0K 3 32K 1206 1206 amm a R50 R52 L OUT2L1 11 0K 3 32K 1206 1206 C38 L OUT3LA 830PF
46. E 1206 50 AVDD pvppi 22 IDD AS masa A3V AV 10 DNP O O CT14 C79 DVDD2 FER9 10UF 0 1UF 72 600 DNP C76 T B 805 DVDD3 1206 600 2 805 38 PVDD DVDDIO1 4 CY e 1206 e DVDDIO2 H3 e YY YN 39 AGND1 40 3 FER12 e AGND2 DGND1 e 600 47 9 1206 DGND2 e MAN e e e 53 AGND4 DGND3 JI e AGND5 DGND4 T 63 NC AGNDS DGND5 A e i H P PUDO ADVASS 77777 ADV7183AKST LQFP80 FER13 C84 C85 C86 C87 N Z 600 0 1UF 0 01UF 0 1UF 0 01UF 1206 805 805 805 805 DNP Do Not Populate YY YN e ANALOG 9t Rose Nashua NH 03063 DEVICES eu 1 800 ANALOGD Title ve un E ADSP BF533 EZ KIT LITE VIDEO IN Drawn Size BoardNo Rev Checked C A0167 2001 16 Engineerin 8 8 Date 2 13 2004 12 39 Sheet 8 of 13 A B C D B C D 3 3V CN 3 3V CS R150 10K 805 PF8 R149 R157 100 U10 0 00 3 3V 805 1206 O O O e 3 A m amp USB RESET SW4 LED3 SWTO13 Da RED SMT
47. EDs and Push But tons on page 2 10 and Push Button Enable Switch SW9 on page 3 12 for information on how to dis able the push button PF9 Push button SW5 See Using LEDs and Push But tons on page 2 10 and Push Button Enable Switch SW9 on page 3 12 for information on how to dis able the push button PF10 Push button SW6 See Using LEDs and Push But tons on page 2 10 and Push Button Enable Switch SW9 on page 3 12 for information on how to dis able the push button PF11 Push button SW7 See Using LEDs and Push But tons on page 2 10 and Push Button Enable Switch SW9 on page 3 12 for information on how to dis able the push button PF12 17 ADV7171 and ADV7183 Data MSB PF13 PPI6 ADV7171 and ADV7183 Data PF14 PPI5 ADV7171 and ADV7183 Data PF15 PPI4 ADV7171 and ADV7183 Data PPI Interface The Parallel Peripheral Interface PPI of the ADSP BF533 processor is a half duplex bi directional port that can accommodate up to 16 bits of data The interface has a dedicated input clock 27 MHz three multi plexed frame sync signals and four bits of dedicated data The remaining data bits come from re configured programmable flag pins For informa ADSP BF533 EZ KIT Lite Evaluation System Manual 3 5 System Architecture tion about the pins which multiplexed with the PPI see Programmable Flags on page 3 4 For information about the ADSP BF533 processor PPI interface refer to
48. Evaluation System Manual Bill Of Materials w u E E 2 ERE E 2 2 B E 9 bb 3 2 8g E 4 5 z lola ZA gt E 108 9 1270 1 8W 5 1206 R146 147 AVX CR32 271J T R160 162 R164 165 R168 R195 109 1 1680 1 8W 5 1206 R163 AVX CR32 681J T 11011 150 1 8W 1 1206 R122 PANASONIC ER 8ENF1500V 111 2 RED SMT LED001 LED2 3 PANASONIC LN1261C GULL WING 1121 GREEN SMT LED001 LED1 PANASONIC LN1361C GULL WING 11316 604 1 8W 1 1206 R39 R46 R55 PANASONIC ERJ 8ENF6040V R63 R71 R79 1144 luF 25V 20 A CT17 20 PANASONIC ECS T1EY105R TANT 55 125 11512 ADG774A QSOP16 U37 38 ANALOG 774 QUICKSWITCH 257 DEVICES 1161 IDC 7X2 IDC7X2 P4 BERG 54102 T08 07 HEADER 1171 12 5 RESETABLE FUS001 1 RAYCHEM SMD250 2 CORP ADSP BF533 EZ KIT Lite Evaluation System Manual A 9 ADSP BF533 EZ KIT Lite Evaluation System Manual ADSP BF533 EZ KIT Lite DNP Do Not Populate ANALOG 20 Cotton Road Nashua NH 03063 DEVICES PH 1 800 ANALOGD Titl 577 pale ADSP BF533 EZ KIT LITE TITLE Drawn Checked Size Board No A0 1 67 2 0 0 1 e ee Date 3 24 2003_13 34 Sheet ET RE B C D
49. H MH3 MH4 MH Ch Ch CN Y CY 20 Cotton Road estt S S y yY TP12 TP14 TP13 TP11 TP8 TP9 TP10 ANA OG O O O O O O O Nashua NH 03063 FER22 ae DE V IQ ES PH 1 800 ANALOGD 600 1206 0000 Approvals Date Title ADSP BF533 EZ KIT LITE POWER Drawn Fi Size Board No Rev SHON N A A Checked C A0167 2001 1 6 Engineerin 8 8 Date 2 19 2004 13 19 Sheet 11 of 13 A B C D A 177 DSP VDD EXT e A m BBBYP T RES IN PLACE OF C188 181 183 184 182 185 180 199 200 198 190 188 187 189 186 191 196 194 193 195 192 197 179 R194 0 01UF 0 01UF 0 1UF 0 1UF 0 1UF 0 1UF 10UF 10UF 10UF 0 01UF 0 01UF 0 1UF 0 1UF 0 1UF 0 1UF 0 01UF 0 01UF 0 1UF 0 1UF 0 1UF 0 1UF 0 1UF 0 00 805 805 805 805 805 805 1210 1210 1210 805 805 805 805 805 805 805 805 805 805 805 805 805 805 e e e e e e e e e e e e e e e e e ADSP 21533 U1 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V A5V A5V O ee CY CY Lee 159 153 155 154 150 149 136 126 127 124 169 123 174 173
50. IDEO AVINA m pia DAC BE 5 V DEO AVIN5 I 8 Pis DAC CH 9 27 5 8 o P12 DAC_D Hi e pi gm Pio COMP2 DIP6 VREFP e e Ps RSET J8 IPE127 4 p RESET De GN CON024 IPFI3 T 3 ET EE 1 16 12 17 12065 eee jn P6 HSYNC ADV7171HSYNC il 0 68UH 2 2UH 0 68UH VIDEO DA C 2 N DAC C IPRATI 2 1 A me em 805 805 0565 P5 FIELD VSYNC IADV7171 VSYNC 3 AD8061ART S SET a2 M ee o e umm CY Y Y 288s SY Y YN SOT23 5 P4 BLANK 3 Dan b R118 b EHS R122 AD1580 R121 C67 C68 R120 1K i 150 00 75 330PF 330PF 75 1206 m 1206 5 1206 TT 805 T 805 1206 e A et 1 44 d 1 ADV7171_27MAZ_CLK CLOCK VAAT 4 n n mx gt CECR AN RESET RESET vaa a Ris K 30 AGND2 VAA4E e 18 28 ALSB VAASE R131 1 PFI_SDATA 24 SDATA gt a an PF0_SCLOCKI 2355CLOCK GNDI L o NU YY 100K 29 1206 A3V 35 43 O e SCRESET RTC GND3 o rx GN o S rrynEQ GND5 a M U22 J8 R116 3X2 ADV7171KSU 4 5 75 CON024 R112 TQFP44 L8 L1 L9 ke 1206 sss L 100K 0 68UH 2 2UH 0 68UH 1 VIDEO DAC D 8 Y 1206 805 805 805 e kees DAC D NO Og 3 6 20 NL 9 R115 a R113 C73 C74 R114 1K 75 830PF 330PF 75 1206 1206 T 805
51. NTS ADSP BF533 EZ KIT Lite Evaluation System Manual CONTENTS x ADSP BF533 EZ KIT Lite Evaluation System Manual PREFACE Thank you for purchasing the ADSP BF533 EZ KIT Lite Analog Devices ADI evaluation system for Blackfin embedded media processors The Blackfin processors are embedded processors that support a Media Instruction Set Computing MISC architecture This architecture is the natural merging of RISC media functions and digital signal processing DSP characteristics towards delivering signal processing performance in a microprocessor like environment The evaluation board is designed to be used in conjunction with the Visu alDSP development environment to test the capabilities of the ADSP BF533 Blackfin processors The VisualDSP development envi ronment gives you the ability to perform advanced application code development and debug such as Create compile assemble and link application programs written in C C and ADSP BF533 assembly Load run step halt and set breakpoints in application program Read and write data and program memory Read and write core and peripheral registers Plot memory Access to the ADSP BF533 processor from a personal computer PC is achieved through a USB port or an optional JTAG emulator The USB interface gives unrestricted access to the ADSP BF533 processor and the ADSP BF533 EZ KIT Lite Evaluation System Manual xi evaluation board peripher
52. O DELAY CLK GRATED SYS BUF 21 1 ISN74LVC1G32 SOT23 5 U21 TI SN74LVC1G32DBVR SINGLE 2 INPUT OR GATE 22 11 BF533 24LC00 SN U33 U33 ANALOG SEE 1000127 DEVICES 23 2 1000 50V 5 1206 C96 97 AVX 12065A102JAT2A CERM A 2 ADSP BF533 EZ KTT Lite Evaluation System Manual Bill Of Materials w 9 A o m 2 ERE E E z 2 B E 9 bb 3 2 3 2 55 E 58 jol ZA gt E 24 6 2200pF 50V 5 1206 C12 C17 C22 AVX 12065A222JAT050 NPO C27 C32 C37 25 ADM708SAR SOIC8 U29 ANALOG ADM708SAR VOLTAGE SUPERVISOR DEVICES 26 ADP3338AKC 33 SOT 223 VR1 ANALOG ADP3338AKC 3 3 3 3V 1 0AMPREGULATOR DEVICES 27 l ADP3339AKC 5 SOT 223 VR5 ANALOG ADP3339AKC 5 REEL 5V 1 5A REGULATOR DEVICES 28 2 ADP3339AKC 33 SOT 223 VR3 4 ANALOG ADP3339AKC 3 3 RL 3 3V 1 5A REGULATOR DEVICES 29 1 ADP3336ARM MSOP8 VR6 ANALOG ADP3336ARM REEL AD 500MAREGULATOR DEVICES 30 1 ADV7171KSU TQFP44 U27 ANALOG ADV7171KSU VID ENCODER DEVICES 31 l TOMA AD1580BRT DI ANALOG AD1580BRT SOT23D DEVICES 1 2V SHUNT REF 32 2 ADG752BRT SOT23 6 U25 26 ANALOG ADG752BRT CMOS SPDT SWITCH DEVICES 33 3 AD8061ART SOT23 5 U22 24 ANALOG AD8061ART REEL 300MHZ AMP DEVICES 34 1 ADM3202ARN SOICI6 U30 ANALOG ADM3202ARN RS232 TXRX DEVICES 35 l ADV7183KST LQFP80 U28 ANALOG ADV7183KST VID DECODER DEVICES 36 8 AD8606AR SOIC8 U12 13 U15 20 ANALOG AD8606AR OPAMP DEVICES 37 1
53. OGD 1 800 262 5643 or downloaded from the website Data sheets without the suffix can be downloaded from the website only no hard copies are available You can ask for the data sheet by part name or by product number If you want to have a data sheet faxed to you the phone number for that service is 1 800 446 6212 Follow the prompts and a list of data sheet code numbers will be faxed to you Call the Literature Center first to find out if requested data sheets are available Contacting DSP Publications Please send your comments and recommendations on how to improve our manuals and online Help You can contact us at dsp techpubs analog com ADSP BF533 EZ KIT Lite Evaluation System Manual xxi Notation Conventions Notation Conventions The following table identifies and describes text conventions used in this manual Additional conventions which apply only to specific chapters may appear throughout this document Example Description Close command File menu or OK Text in bold style indicates the location of an item within the VisualDSP environment s and boards menu system and user interface items this that Alternative required items in syntax descriptions appear within curly brackets separated by vertical bars read the example as this or that this that Optional items in syntax descriptions appear within brackets and sepa rated by vertical bars read the example as an
54. RAM memory When you are in a VisualDSP EZ KIT Lite session that is using the USB debug interface and not using an emulator the SDRAM registers are con figured automatically through the debugger The values in Table 2 2 are used whenever Bank 0 is accessed through the debugger for example when viewing memory windows or loading a program The numbers were derived for maximum flexibility and work for a system clock frequency between 54 MHz and 133 MHz Table 2 2 EZ KIT Lite Session SDRAM Default Settings Register Value Function EBTU SDGCTL 0x0091998D Calculated with SCLK 133 MHz 16 bit data path External buffering timing disabled rop 2 SCLK cycles tRcp 3 SCLK cycles tgp 3 SCLK cycles tras 6 SCLK cycles pre fetch disabled CAS latency 3 SCLK cycles SCLK1 disabled EBIU_SDBCTL 0x00000013 Bank 0 enabled Bank 0 size 32 MB Bank 0 column address width 9 bits EBIU_SDRRC 0x000001A0 Calculated with SCLK 54 MHz RDIV 416 clock cycles 1 54 MHz lt SCLK lt 133 MHz The EBIU_SDGCTL register can only be re written within the user code by first placing the chip in self refresh see the ADSP BF533 Blackfin Proces sor Hardware Reference Clearing the appropriate checkbox on the Target 2 4 ADSP BF533 EZ KIT Lite Evaluation System Manual Using EZ KIT Lite Options dialog box which is accessible through the Settings pull down menu disables automatic and allows manual conf
55. RS232 line driver as well as to the expansion interface The RS232 line driver is connected to the DB9 male connector allowing you to interface with a PC or other serial device Expansion Interface The expansion interface consists of the three 90 pin connectors Table 3 3 on page 3 8 shows the interfaces each connector provides For the exact pinout of these connectors refer to Appendix B Schematics on page B 1 The mechanical dimensions of the connectors can be obtained from Technical or Customer Support Table 3 3 Connector Interfaces Connector Interfaces J1 5V G ND Address Data PPI J2 3 3V GND SPI NMI TMR2 0 SPORTO SPORT1 PF15 0 EBUI control signals J3 5V 3 3V GND UART Flash IO Reset Video control signals Limits to the current and to the interface speed must be taken into consid eration when you use the expansion interface The maximum current limit is dependent on the capabilities of the regulator used Additional circuitry can also add extra loading to signals decreasing their maximum effective speed Analog Devices does not support and is not responsible for the effects of additional circuitry 3 8 ADSP BF533 EZ KIT Lite Evaluation System Manual EZ KIT Lite Hardware Reference JTAG Emulation Port The JT AG emulation port allows an emulator to access the processor s internal and external memory through a 6 pin interface The JTAG emu lation port of the processo
56. SP BF533 EZ KIT Lite Evaluation System Manual Preface Send questions by mail to Analog Devices Inc One Technology Way P 0 Box 9106 Norwood MA 02062 9106 USA Supported Processors The ADSP BF533 EZ KIT Lite evaluation system supports ADSP BF533 Blackfin Analog Devices embedded processors Product Information You can obtain product information from the Analog Devices website from the product CD ROM or from the printed publications manuals Analog Devices is online at www analog com Our website provides infor mation about a broad range of products analog integrated circuits amplifiers converters and digital signal processors MyAnalog com MyAnalog com is a free feature of the Analog Devices website that allows customization of a webpage to display only the latest information on products you are interested in You can also choose to receive weekly email notification containing updates to the webpages that meet your interests MyAnalog com provides access to books application notes data sheets code examples and more ADSP BF533 EZ KIT Lite Evaluation System Manual xvii Product Information Registration Visit www myanalog com to sign up Click Register to use MyAnalog com Registration takes about five minutes and serves as means for you to select the information you want to receive If you are already a registered user just log on Your user name is your email address DSP Product Inf
57. SPST MOMENTARY 1 0001 3 3V Ten 4 1UF 3 3V DA O R159 RESET 10K LED2 805 RED SMT R165 1 1 0001 270 3 1206 R172 10K 805 N A 4 U9 USB_CONFIGURED he ey 10K 1206 11 13 12 RESET 805 25 2 b SEN 7 OAD O0AD 74 VC14A d b Li SOIC14 SOIC14 SOIC14 O MR X RESET Spa RESET Za A1 vil SPST MOMENTARY NE M v a Ot Ag TO RESET 1 OK SOICB A Dea a S Aq 11412 O 805 N RONS LED3I 11 9 PF9 R155 R167 erige PAT zi 100 0 00 LEDA 13 7 u10 2A2 2Y2 d 1206 SOFT_RESET gt 55 e uL 305 7 sa 19543 ova 00 ZELNCISA 17777 L ps c 17214 SPST MOMENTARY 4 18 1 1UF OH POWER DA 19 LED9 LED8 LED7 LED6 LED5 LED4 LED1 2 AMBER SMT AMBER SMT AMBER SMT AMBER SMT AMBER SMT AMBER SMT GREEN SMT 1 0001 1 0001 1 0001 1 0001 1 1 0001 1 1 0001 1 0001 4 3 3 3 3 3 3 SSOP20 3 3V I R160 R161 R168 R162 R147 R146 R163 O 270 270 270 270 270 270 680 1206 1206 1206 1206 1206 1206 1206 e e e e R156 10K 805 PF10 R154 R148 100 ia 0 00 e 805 1206 O O e 9 8 SW6 SWT013 unii 3 3V SPST MOMENTARY O cT20 Wr TINA C92 UART P5 0106 U30 C91 1 T 805 01UF SU M 805 2 3 IDC2X1 C94 C1 2X1 0 1UF V FER15 TT 805 4 6 600 3 3V 24 V 603 O Seo YA Po FER17 R110 600 a 0 00 r 11 14 603 he 7 I TIXI UN Ber I H 17 rei T2IN T2OUT FER14 60 12 13 600 2 R153 Sw9 RIOUT 603 405
58. Serial Bus controllers Figure 1 12 Device Manager Window If using an EZ KIT Lite on Windows 98 disconnect the USB cable from the board before booting the PC When Windows 98 is booted and you are logged on re connect the USB cable to the board The operation should continue normally from this point Starting VisualDSP To set up a session in VisualDSP 1 Verify that the yellow USB monitor LED LED11 located near the USB connector is lit This signifies that the board is communicat ing properly with the host PC and is ready to run VisualDSP 2 Hold down the Control CTRL key 1 16 ADSP BF533 EZ KIT Lite Evaluation System Manual 3 Getting Started Select the Start button on the Windows taskbar then choose Pro grams Analog Devices VisualDSP 3 5 for 16 bit Processors VisualDSP Environment If you are running VisualDSP for the first time go to step 4 If you already have existing sessions the Session List dialog box appears on the screen 4 Click New Session 5 The New Session dialog box shown in Figure 1 13 appears on the screen New Session ki IX Debug target Processor JEZ KIT Lite ADSP BFeex y Platform ADSP B Fark EZ KIT Lite y Session name aDSP BF533 ADSP BFxxx EZ KIT Lite e Figure 1 13 New Session Dialog Box 6 ds 8 In Debug Target choose EZ KIT Lite ADSP BFxxx In Processor choose the appropriate processor ADSP BF533 Type a new target name
59. Uu E Ii f LED1 en a g al a WUSP 9r533 EZ K ONE RE LU DESIGNED BY ANALOG DE saka DART NUM SW5 SW6 Figure 3 3 LED and Push Button Locations Programmable Flag Push Buttons SW7 4 Four push buttons SW7 4 are provided for general purpose user input The buttons connect to the processor s programmable flag pins PF11 8 The push buttons are active HIGH and when pressed send a High 1 to the processor Refer to Using LEDs and Push Buttons on page 2 10 for more information on how to use the PFs when programming the proces sor The push button enable switch SW9 is capable of disconnecting the ADSP BF533 EZ KIT Lite Evaluation System Manual LEDs and Push Buttons push buttons from the PF refer to Push Button Enable Switch SW9 on page 3 12 for more information The programmable flag signals and their corresponding switches are shown in Table 3 8 Table 3 8 Programmable Flag Switches DSP Programmable Flag Pin Push Button Reference Designator PF8 SW4 PF9 SW5 PF10 SW6 PF11 SW7 Reset Push Button SW8 The RESET push button resets all of the ICs on the board One exception is the USB interface chip U34 The chip is not being reset when the push button is pressed after the USB cable has been plugged in and communi cation has been correctly initialized with the PC After USB communication has been initialized the only way to reset the USB is by powering do
60. als Analog Devices YTAG emulators offer faster communication between the host PC and target hardware Analog Devices carries a wide range of in circuit emulation products To learn more about Analog Devices emulators and DSP development tools go to http www analog com dsp tools ADSP BF533 EZ KIT Lite provides example programs to demonstrate the capabilities of the evaluation board The VisualDSP license provided with this EZ KIT Lite evalua tion system limits the size of a user program to 20 KB of internal memory The board features Analog Devices ADSP BF533 processor v Performance to 756 MHz v 160 pin Mini BGA package v 27 MHz CLKIN oscillator Synchronous Dynamic Read Access Memory SDRAM v MT48LC16M16 32 MB 16M x 16 bits Flash Memory v 2 MB 512K x 16 x 2chips Analog Audio Interface v AD1836 Analog Devices 96 kHz audio codec v 4 input RCA phono jacks 2 channels v 6 output RCA phono jacks 3 channels xii ADSP BF533 EZ KIT Lite Evaluation System Manual Preface Analog Video Interface v ADV7183 video decoder w 3 input RCA phono jacks v ADV7171 video encoder w 3 output RCA phono jacks Universal Asynchronous Receiver Transmitter UART v ADM3202 RS 232 line driver receiver v DB9 male connector e LEDs v 10 LEDs 1 power green 1 board reset red 1 USB red 6 general purpose amber and 1 USB monitor amber Push Buttons v 5 push buttons with debounce logic 1 re
61. ashLINK JTAG HEADER 3 3V i R26 3 3V 10K O 805 P1 R22 1 2 0 00 805 3 4 RN1 i 5 6 EE L FLASH IDI lt FLASH TSTAT U L2 RN2 EE ES i 7 8 FLASH RES d OM 4 E FLASH TMS C e ki B2 lo U7 9 10 SE D R1 R32 1 COM4 RESEHEH le eee E SEAS ID a 1 aa K2 A1 K 60 C EE OW WO 33771 74LVC14A R2 pa PB4 Bi R1 R32 PC5B 17777ELASH TOK lt L2 Pann ATI e 4 SOIC14 SOIC14 bs m A2 ko o si SN74LVC 13 14 s SY R3 R30 1 5 B R2 R31 BP o B 1 SOT23 5 IFLASH TERR 1 L A3 k3 7 75 LASH R4 R29 PBS Billi R3 R3 Mipp2 Bt L FLASH 100 7 po WA 1 pang a Rg micas 805 L FLASH TSTATI ai RET MIPCS A i PB7 G Rs Res HEFLASH TDO _ 7 _ FLASH_TDO lt FLASH TDOA m PESA n es MC 1 i PBT B B re sec 150071 FLASH TD Ai m re nol WEIS TERR 1 i PB2 Billi SCH Rao IMIFLASH RESET R24 L 588HTDLAME ho MIIFLASH TERR PB2 B M 2 6 M FLASH RESET C um Lg oy oe cone x 12 885 805 Ding H PASA 2 comgi I D2 G2 EE f DEER D1 morz R10 R23 IMI PPICLK ONBOARD SELECT 000 l PD BIS Re i EA D R nacht WPa A i L Pop R10 R2362 BEA B 1 e EENG y ML on E R12 Rott 5 B Dou nach E3R13 R20 i PD BiR Rott pa Rig
62. d In Figure 2 1 on page 2 14 trace 0 occurred before trace 1 which occurred before trace 2 and so on Performance Monitor Choosing Performance Monitor from the Settings menu opens the Per formance Monitor Control dialog box shown in Figure 2 2 A description of the dialog box appears in Table 2 10 on page 2 16 Performance Monitor 0 Mode Type Event Count user 7 Exception y Loopo iterations y Performance Monitor 1 Mode Type Event Count Both y Emulation y CSYNC SSYNC instructions 7 0x0 Global Options Cewe Figure 2 2 Performance Monitor Dialog Box ADSP BF533 EZ KIT Lite Evaluation System Manual 2 15 Using EZ KIT Lite VisualDSP Interface The performance monitor is a 32 bit counter that allows you to track occurrences of events within the core and use these to analyze system behavior When the counter reaches zero it causes an exception or emula tion event as specified by the Type option Table 2 10 Performance Monitor Options Option Description Enable Enables performance monitoring Mode Determines the mode of operation for tracking events Disabled disables the monitor User tracks while in user mode Supervisor tracks while in supervisor mode Both tracks while in both user mode and supervisor mode Type Determines the type of event occurring on a match Exception causes an exception to occur You can install a handler to
63. detect and handle this exception Emulation halts the DSP Event Specifies the tracked event Refer to your processor s Hardware Reference for details Events include stalls cache hits or misses loop iterations branches interrupts loads stores DMA accesses and more Count Specifies the count When the 32 bit counter reaches zero an exception or emulation event occurs For example to halt on the third occurrence of an event load the count with OxFFFFFFFE and set Type to Emulation The counter counts up and wraps around causing the processor to halt as desired Boot Load Choosing Boot Load from the Settings menu runs the processor and per forms a hard reset on the board This command saves you from having to shut down VisualDSP reset the EZ KIT Lite board and bring up Visu alDSP again when you want to perform a hard reset Use this feature when loading debug boot code from an external part or when you want to put the device into a known state 2 16 ADSP BF533 EZ KIT Lite Evaluation System Manual Using EZ KIT Lite Target Options Choosing Target Options from the Settings menu opens the Target Options dialog box Figure 2 3 Use target options to control certain aspects of the processor on the ADSP BF533 EZ KIT Lite evaluation system Target Options BF533 EZ KIT Reset Options Other Options Iv Core reset V Reset before loading executable Iv System reset
64. e P2 Digi Key A2096 ND Mating Assembly 2m Female to female cable Digi Key AE1016 ND SPORTO P3 The SPORTO connector is linked to a 20 pin connector The connector s pinout can be found in Schematics on page B 1 For pricing and avail ability on these connectors contact AMP Part Description Manufacturer Part Number 20 position AMPMODU system AMP 104069 1 50 receptacle P3 Mating Connectors 20 position ribbon cable connec AMP 111196 4 tor 20 position AMPMODU system 1 AMP 2 487937 0 20 connector 20 position AMPMODU system AMP 2 487938 0 20 connector w o lock Flexible film contacts 20 per AMP 487547 1 connector ADSP BF533 EZ KIT Lite Evaluation System Manual 3 19 Connectors JTAG P4 The JTAG header is the connecting point for a JTAG in circuit emulator pod When an emulator is connected to the JTAG header the USB debug interface is disabled Pin 3 is missing to provide keying Pin 3 in the mating connector should have a plug When using an emulator with the EZ KIT Lite board follow the connection instructions provided with the emulator 3 20 ADSP BF533 EZ KIT Lite Evaluation System Manual A BILL OF MATERIALS Reference Quantity Description Reference Design Manufacturer Number Part N 74LVC14A SOIC14 U10 U41 TI 74LVC14AD HEX INVER SCHMITT TR IGGER 2 1 IDT74FCT3244APY U31 IDT IDT74FCT3244APY SSOP20
65. e The install also upgrades an older driver if such is detected in the system Q Prior to running the VisualDSP 3 5 installer ensure there are no other Hardware Wizard windows running in the background If there are any wizard windows running close them before starting the installer 1 12 ADSP BF533 EZ KIT Lite Evaluation System Manual Getting Started To install the USB driver 1 If VisualDSP 3 5 is already installed on your system go to step 2 Otherwise run VisualDSP 3 5 installation Refer to the VisualDSP 3 5 Installation Quick Reference Card for a detailed installation description When installing VisualDSP 3 5 on Windows 2000 make sure the appropriate EZ KIT Lite component is selected for the installation 2 Connect the EZ KIT Lite device to your PC s USB port Windows 2000 automatically detects an EZ KIT device and auto matically installs the appropriate driver for the selected device see step 1 3 Verify the installation by following the instructions in Verifying Driver Installation on page 1 15 Windows XP USB Driver VisualDSP 3 5 installation software pre installs the necessary drivers for the selected EZ KIT Lite The install also upgrades an older driver if such is detected in the system O Prior to running the VisualDSP 3 5 installer ensure there are no other Hardware Wizard windows running in the background If there are any wizard windows running close them before starting
66. e Contents tab of the Help window and select Manuals gt Hardware Tools gt EZ KIT Lite Evaluation Systems For more documentation please go to http www analog com technology dsp library html Printed Manuals For general questions regarding literature ordering call the Literature Center at 1 800 ANALOGD 1 800 262 5643 and follow the prompts VisualDSP Documentation Set Printed copies of VisualDSP manuals may be purchased through Ana log Devices Customer Service at 1 781 329 4700 ask for a Customer Service representative The manuals can be purchased only as a kit For additional information call 1 603 883 2430 If you do not have an account with Analog Devices you will be referred to Analog Devices distributors To get information on our distributors log onto www analog com salesdir continent asp xx ADSP BF533 EZ KIT Lite Evaluation System Manual Preface Hardware Manuals Printed copies of hardware reference and instruction set reference manuals can be ordered through the Literature Center or downloaded from the Analog Devices website The phone number is 1 800 ANALOGD 1 800 262 5643 The manuals can be ordered by a title or by product number located on the back cover of each manual Data Sheets All data sheets can be downloaded from the Analog Devices website As a general rule printed copies of data sheets with a letter suffix L M N S can be obtained from the Literature Center at 1 800 ANAL
67. e USB Driver The EZ KIT Lite evaluation system installed on the following platforms requires one full speed USB port Windows 98 USB Driver on page 1 8 describes the installation on Windows 98 Windows 2000 USB Driver on page 1 12 describes the installa tion on Windows 2000 Windows XP USB Driver on page 1 13 describes the installation on Windows XP The USB driver used by the debug agent is not Microsoft certified because it is intended for a development or laboratory environment not a com mercial environment ADSP BF533 EZ KIT Lite Evaluation System Manual 1 7 Installation Tasks Windows 98 USB Driver Before using the ADSP BF533 EZ KIT Lite for the first time the Win dows 98 USB driver must first be installed To install the USB driver 1 Insert the CD into the CD ROM drive The connection of the device to the USB port activates the Win dows 98 Add New Hardware Wizard as shown in Figure 1 2 Add New Hardware Wizard Figure 1 2 Windows 98 Add New Hardware Wizard 2 Click Next 1 8 ADSP BF533 EZ KIT Lite Evaluation System Manual Getting Started 3 Select Search for the best driver for your device as shown in Figure 1 3 Add New Hardware Wizard Figure 1 3 Windows 98 Searching for Driver 4 Click Next 5 Select CD ROM drive as shown in Figure 1 4 Add New Hardware Wizard Figure 1 4 Windows 98 Searching for CD ROM ADSP BF533 EZ KIT
68. er D 1ADI_Setup exe in the Open field where D is the name of your local CD ROM drive Follow the on screen instructions to continue installing the software At the Custom Setup screen select your EZ KIT Lite from the list of available systems and choose the installation directory Click an icon in the Feature Description field to see the selected system s description When you have finished click Next At the Ready to Install screen click Back to change your install options click Install to install the software or click Cancel to exit the install When the EZ KIT Lite installs the Wizard Completed screen appears Click Finish 1 4 ADSP BF533 EZ KIT Lite Evaluation System Manual Getting Started Installing and Registering VisualDSP License VisualDSP and EZ KIT Lites are licensed products You may run only one copy of the software for each license purchased Once a new copy of the VisualDSP or EZ KIT Lite software is installed on your PC you must install register and validate your licence The VisualDSP 3 5 Installation Quick Reference Card included in your package will guide you through the licence installation and registration process refer to Tasks 1 2 and 3 Setting Up EZ KIT Lite Hardware The EZ KIT Lite evaluation system contains ESD electrostatic discharge sensitive devices Electrostatic charges readily accumulate on the human body and equipment and can discharge without detection Pe
69. ial requirements of the European EMC directive 89 336 EEC inclusive 93 68 EEC and therefore carries the CE mark The ADSP BF533 EZ KIT Lite evaluation system had been appended to the Technical Construction File referenced DSPTOOLS1 dated December 21 1997 and was awarded CE Certification by an appointed European Competent Body as listed below Technical Certificate No Z600ANA1 011 Issued by Technology International Europe Limited 41 Shrivenham Hundred Business Park Shrivenham Swindon SN6 8TZ UK The EZ KIT Lite evaluation system contains ESD electrostatic discharge sensitive devices Electro static charges readily accumulate on the human WARNING sc body and equipment and can discharge without _ amp detection Permanent damage may occur on devices subjected to high energy discharges Proper ESD FAD SFEBSITEE DEVICE precautions are recommended to avoid performance degradation or loss of functionality Store unused EZ KIT Lite boards in the protective shipping package CONTENTS iv ADSP BF533 EZ KIT Lite Evaluation System Manual CONTENTS PREFACE Purpose ot This Manual E xiv landed Fh TEE xiv LK AAA xv Whats New m Dae ET NEE xvi Technical or Cusromer DONE LA si ll el xvi Supported c rcr Mm xvii Peta rh xvii Lupi mel e xvii DSP Product aii iat uuu aan a vind aaa ki xviii Related Documents
70. ides four push buttons and six LEDs for gen eral purpose IO The six LEDs labeled LED4 through LED9 are accessed via some of the general purpose IO pins of Flash memory interface For information on how to program the pins see Flash General Purpose IO on page 2 7 The four general purpose push button are labeled SW4 through SW7 A sta tus of each individual button can be read through programmable flag PF inputs PF8 through PF11 A PF reads 1 when a corresponding switch is being pressed on When the switch is released the PF reads 0 A connec tion between the push button and PF input is established through the SW9 DIP switch See Push Button Enable Switch SW9 on page 3 12 for details An example program is included in the EZ KIT installation directory to demonstrate the functionality of the LEDs and push buttons 2 10 ADSP BF533 EZ KIT Lite Evaluation System Manual Using EZ KIT Lite Using Audio The AD 1836 audio codec provides three channels of stereo audio output and two channels of multichannel 96 kHz input The SPORTO interface of the processor is linked with the stereo audio data input and output pins of the AD 1836 codec The processor is capable of transferring data to the audio codec in time division multiplexed TDM or 125 mode The 129 mode allows the codec to operate with a 96 kHz sample rate but only allows you to use two channels of output TDM mode can operate at a maximum of 48 kHz
71. iguration For correct operation of the VisualDSP software and the EZ KIT Lite your computer must have the minimum configuration Windows 98 Windows 2000 Windows XP Intel or comparable 333 MHz processor VGA Monitor and color video card 2 button mouse 200 MB free on hard drive 128 MB RAM Full speed USB port CD ROM Drive Q EZ KIT Lite does not run under Windows 95 or Windows NT Installation Tasks The following task list is provided for the safe and effective use of the ADSP BF533 EZ KIT Lite Follow these instructions in the presented order to ensure correct operation of your software and hardware 1 VisualDSP and EZ KIT Lite software installation VisualDSP license installation and registration EZ KIT Lite hardware setup USB driver installation verification 2 3 4 EZ KIT Lite USB driver installation 5 6 VisualDSP startup ADSP BF533 EZ KIT Lite Evaluation System Manual 1 3 Installation Tasks Installing VisualDSP and EZ KIT Lite Software This EZ KIT Lite comes with the latest version of VisualDSP 3 5 for 16 bit processors VisualDSP installation includes EZ KIT Lite installations To install VisualDSP and EZ KIT Lite software 1 2 Insert the VisualDSP installation CD into the CD ROM drive If Autoplay is enabled on your PC you see the Install Shield Wiz ard Welcome screen Otherwise choose Run from the Start menu and ent
72. iguration For more information see Target Options on page 2 17 Automatic configuration of SDRAM is not optimized for any SCLK fre quency Table 2 3 shows the optimized configuration for the SDRAM registers using a 118 8 MHz 126 MHz and 133 MHz SCLK The fre quency of 118 8 MHz is the maximum SCLK frequency when using a 594 MHz core frequency the maximum frequency for the EZ KIT Lite when using the internal voltage regulator Only the EBIU_SDRRC register needs to be modified in the user code to achieve maximum performance Table 2 3 SDRAM Optimum Settings Register SCLK 133 MHz SCLK 126 MHz SCLK 118 8 MHz Processor MAX CCLK 756 MHz CCLK 594 MHz EBTU SDGCTL 0x0091 9980 0x0091 9980 0x0091 9980 EBIU SDBCTL 0x0000 0013 0x0000 0013 0x0000 0013 EBTU SDRRC 0x0000 0406 0x0000 03CF 0x0000 0397 An example program is included in the EZ KIT installation directory to demonstrate how to set up the SDRAM interface Using Flash Memory The following sections describe how to use the memory and general pur pose IO pins as well as how to configure the Flash memory device The ADSP BF533 EZ KIT Lite board employs two PSD4256G6V Flash General Purpose IO devices from STMicroelectronics These devices not only have Flash memory but also extra IO pins which are memory mapped ADSP BF533 EZ KIT Lite Evaluation System Manual 2 5 Using Flash Memory Example code is provided in the EZ
73. ing cable 2 10 jumpers 1 5 3 9 JP1 2 boot mode select 3 10 JP3 core voltage source select 3 10 L LEDs 1 5 2 10 3 13 LEDI 1 6 3 14 ADSP BF533 EZ KIT Lite Evaluation System Manual I 3 INDEX LED11 1 15 1 16 3 15 LED2 3 1 6 3 14 LED4 9 2 9 3 15 license restrictions 2 2 M memory 2 4 flash configuration 2 6 SDRAM configuration 2 4 select pins see AMSO AMSI AMS2 SMS0 memory map see ADSP BF533 processor P P3 SPORT connector 3 4 package contents 1 1 Parallel Peripheral Interface PPD xiv 2 12 3 5 PC configuration 1 3 parallel port 2 10 Performance Monitor Control dialog box 2 15 PFs see programmable flags power connector J9 3 17 specifications 3 18 supply 3 18 PPI interface 2 12 3 7 primary flash memory 2 6 primary processor pins PPIO 7 3 6 TMRI 2 3 6 processor memory map see ADSP BF533 processor programmable flags PFs 3 4 3 5 PF0 2 12 3 4 PF1 2 12 PF10 11 3 5 3 12 3 14 PF12 15 3 5 3 6 PF2 2 12 3 4 3 11 PF3 3 4 PF4 2 11 3 4 PF5 7 3 5 PF8 11 2 10 3 5 3 12 3 14 PF9 3 5 3 12 3 14 push buttons see also push buttons push buttons 2 10 3 13 connecting to PF pins 3 13 SW4 7 general input 3 5 3 12 3 14 SW8 reset 3 14 SW9 enable 2 11 3 12 3 13 R registering this product 1 2 1 5 regulators 3 2 3 10 reset board 2 16 options 2 17 processor 3 14 push button SW8 3 14 service routines
74. le D pal ADSP BF533 EZ KIT LITE MEMORY FLASH RESETI RESET PD3 RESET PD32 HAVE Drawn TQFP80 TQFP80 G 1 6 Engineerin 8 8 Date 2 13 2004 9 47 Sheet 3 of 13 A C D DIP6 B EE ja x WiDAC3 RIGHT 1 DEVICES Nashua NH 03063 PH 1 800 ANALOGD A B C D 3 3V S Nos O DN e AN 0 O O Qo Qood lt lt R31 U11 33 0 a ESA pw 85 _ ITIN OOO OO LEFT WHITE 1 d u UV IO 1 mam O OOO RIGHT RED KN NA Nou NO SK Z ANS OSC003 Se 20 OUT 424 N J5 5 49K 100PF 1206 T 1206 R48 R43 11 0K 3 32K 1206 1206 Key L__OUTIRA C18 330PF 805 R33 DAC1 RIGHT ie 10K 680PF 805 R49 805 R44 R46 5 49K 1 65K 604 AUDIO CODEC 1206 1206 1206 Kee DADOS CONO24 A NR NEE OK e 0 00 14 TE DACT RIGHT 7 R230 805 ki B05 ASDATA1 om OUTIL 3 DAC1 LEFT R47 cz D DROSECI lt ASDATA2 ouriL our 1 1208 1206 ci7 R45 r RESO ALRCLK L hbis36 VREFINI t 1206 o Se 1 B1 Se 1 L _ _RSCLK0I ABCLK OUT1 R gt yOUTIR DAC1 RIGHT oun
75. on system Installation Tasks on page 1 3 Describes the step by step procedures for setting up the hardware and software Contents of EZ KIT Lite Package Your ADSP BF533 EZ KIT Lite evaluation system package contains the following items ADSP BF533 EZ KIT Lite board EZ KIT Lite Quick Start Guide ADSP BF533 EZ KIT Lite Evaluation System Manual 1 1 Contents of EZ KIT Lite Package VisualDSP 3 5 Installation Quick Reference Card CD containing v VisualDSP for 16 Bit Processors with a limited license v ADSP BF533 EZ KIT Lite debug software v USB driver files v Example programs v ADSP BF533 EZ KIT Lite Evaluation System Manual Universal 7 5V DC power supply USB 2 0 type cable Registration card please fill out and return If any item is missing contact the vendor where you purchased your EZ KIT Lite or contact Analog Devices Inc The EZ KIT Lite evaluation system contains ESD electrostatic discharge sensitive devices Electro static charges readily accumulate on the human body and equipment and can discharge without detection Permanent damage may occur on devices subjected to high energy discharges Proper ESD Fal amp EMAITEE DEVICE precautions are recommended to avoid performance degradation or loss of functionality Store unused EZ KIT Lite boards in the protective shipping package 1 2 ADSP BF533 EZ KIT Lite Evaluation System Manual Getting Started PC Conf
76. on the EZ KIT Lite board LEDs 6 Wl Expansion Connectors 3 JTAG Header JTAG Port 3 32 768 KHz Oscillator 27 MHz Oscillator UART SPORT1 SPORTO PPUPES PBs 4 SPORTO ASV 3 3V Power Regulation 75V Connector RS 232 Phono SE Male Jacks 4 Phono Phono Jacks 3 Jacks 3 Stereo In E Video In Video Out 6 Figure 3 1 System Architecture The EZ KIT Lite has been designed to demonstrate the capabilities of the ADSP BF533 Blackfin processor The processor has IO voltage of 3 3V The c ore voltage of the processor can be supplied from either the internal voltage regulator or a fixed 1 4V external regulator If the processor is operating at speeds greater than 600 MHz it is necessary to use the LAN regulator For more information about setting the source of the core volt age see Core Voltage Source Select Jumper JP3 on page 3 10 3 2 ADSP BF533 EZ KIT Lite Evaluation System Manual EZ KIT Lite Hardware Reference The core voltage and the core clock rate can be set on the fly by the pro cessor The input clock is 27 MHz A 32 768 kHz crystal supplies the Real Time Clock RTC inputs of the processor The default mode for the pro cessor is Flash boot See Boot Mode Select Jumpers JP2 1 on page 3 10
77. optional this or that this Optional item lists in syntax descriptions appear within brackets delim ited by commas and terminated with an ellipsis read the example as an optional comma separated list of this PF9 0 Registers connectors pins commands directives keywords code exam ples and feature names are in text with letter gothic font filename Non keyword placeholders appear in text with italic style format Note A note providing information of special interest or identifying a related topic In the online version of this book the word Note appears instead of this symbol O Caution A caution providing information about critical design or programming issues that influence operation of a product In the online version of this book the word Caution appears instead of this symbol xxii ADSP BF533 EZ KIT Lite Evaluation System Manual 1 GETTING STARTED This chapter provides the information you need to begin using ADSP BF533 EZ KIT Lite evaluation system For correct operation Install the software and hardware in the order presented in Installation Tasks on page 1 3 The chapter includes the following sections Contents of EZ KIT Lite Package on page 1 1 Provides a list of the components shipped with this EZ KIT Lite evaluation system PC Configuration on page 1 3 Describes the minimum requirements for the PC to work with the EZ KIT Lite evaluati
78. or Blackfin Processors VisualDSP 3 5 C C Complier and Library Manual for Blackfin Processors Description of the assembler function and commands for Blackfin processors Description of the complier function and com mands for Blackfin processors VisualDSP 3 5 Linker amp Utilities Manual for 16 Bit Processors Description of the linker function and com mands for 16 bit processors VisualDSP 3 5 Loader Manual for 16 Bit Processors Description of the loader splitter function and commands for 16 bit processors The listed documents can be found through online Help or in the Docs folder of your VisualDSP installation Most documents are available in printed form If you plan to use the EZ KIT Lite board in conjunction with a JTAG emulator refer to the documentation that accompanies the emulator ADSP BF533 EZ KIT Lite Evaluation System Manual xix Product Information Online Documentation Your software installation kit includes online Help as part of the Win dows interface These help files provide information about VisualDSP and the ADSP BF533 EZ KIT Lite evaluation system To view VisualDSP Help click on the Help menu item or go to the Windows task bar and select Start gt Programs gt Analog Devices gt Visu alDSP for 16 bit Processors gt VisualDSP Documentation To view ADSP BF533 EZ KIT Lite Help which now is a part of the VisualDSP Help system go th
79. ormation For information on digital signal processors visit our website at www analog com dsp which provides access to technical publications data sheets application notes product overviews and product announcements You may also obtain additional information about Analog Devices and its products in any of the following ways Email questions or requests for information to dsp support analog com Fax questions or requests for information to 1 781 461 3010 North America or 49 0 89 76903 157 Europe Related Documents For information on product related development software see the follow ing publications Table 1 Related DSP Publications Title Description ADSP BF533 Embedded Processor Datasheet General functional description pinout and timing xviii ADSP BF533 EZ KIT Lite Evaluation System Manual Preface Table 1 Related DSP Publications Cont d Title Description ADSP BF533 Blackfin Processor Hardware Ref erence Description of internal processor architecture and all register functions Blackfin Processor Instruction Set Reference Description of all allowed processor assembly instructions Table 2 Related VisualDSP Publications Title Description VisualDSP 3 5 Users Guide for 16 Bit Proces 5075 Detailed description of VisualDSP 3 5 fea tures and usage VisualDSP 3 5 Assembler and Preprocessor Manual f
80. ou want to manually configure memory Restricted Software Breakpoints The EZ KIT Lite development system restricts breakpoint placement when certain conditions are met That is under some conditions breakpoints can not be placed effectively Such conditions depend on bus architecture pipeline depth and ordering of the EZ KIT Lite and its target processor ADSP BF533 EZ KIT Lite Evaluation System Manual 2 19 Using EZ KIT Lite VisualDSP Interface 2 20 ADSP BF533 EZ KIT Lite Evaluation System Manual 3 EZ KIT LITE HARDWARE REFERENCE This chapter describes the hardware design of the ADSP BF533 EZ KIT Lite board The following topics are covered System Architecture on page 3 2 Describes the configuration of the ADSP BF533 EZ KIT Lite board and explains how the board components interface with the processor Jumper and DIP Switch Settings on page 3 9 Shows the location and describes the function of the configuration jumpers and DIP switches LEDs and Push Buttons on page 3 13 Shows the location and describes the function of the LEDs and push buttons Connectors on page 3 16 Shows the location and gives the part number for all of the con nectors on the board Also the manufacturer and part number information is given for the mating parts ADSP BF533 EZ KIT Lite Evaluation System Manual 3 1 System Architecture System Architecture This section describes the processor s configuration
81. r manent damage may occur on devices subjected to high energy discharges Proper ESD precautions are Fab FRATRE DEVICE recommended to avoid performance degradation or loss of functionality Store unused EZ KIT Lite boards in the protective shipping package The ADSP BF533 EZ KIT Lite board is designed to run outside your per sonal computer as a stand alone unit You do not have to open your computer case To connect the EZ KIT Lite board 1 Remove the EZ KIT Lite board from the package Be careful when handling the board to avoid the discharge of static electricity which may damage some components 2 Figure 1 1 shows the default jumper settings DIP switch connec tor locations and LEDs used in installation Confirm that your board is set up in the default configuration before continuing ADSP BF533 EZ KIT Lite Evaluation System Manual 1 5 Installation Tasks Power i L E Eta L a El we j LE 1 2 d Figure 1 1 EZ KIT Lite Hardware Setup 3 Plug the provided power supply into J9 on the EZ KIT Lite board Visually verify that the green power LED LED1 is on Also verify that the two red reset LEDs LED2 and LED3 go on for a moment and then go off 4 Connect one end of the USB cable to an available full speed USB port on your PC and the other end to J10 on the ADSP BF533 EZ KIT Lite board 1 6 ADSP BF533 EZ KIT Lite Evaluation System Manual Getting Started Installing EZ KIT Lit
82. r is also connected to the USB debugging interface When an emulator is connected to the board at P4 the USB debugging interface is disabled See TTAG P4 on page 3 20 for more information about the JTAG connector To learn more about available emulators contact Analog Devices see Product Information Jumper and DIP Switch Settings This section describes the operation of the jumpers and DIP switches The jumpers and DIP switch locations are shown in Figure 3 2 Figure 3 2 Jumper and DIP Switch Locations ADSP BF533 EZ KIT Lite Evaluation System Manual 3 9 Jumper and DIP Switch Settings Boot Mode Select Jumpers JP2 1 The JP1 and JP2 jumpers determine the boot mode of the processor Table 3 4 shows the available boot mode settings By default the proces sor boots from the on board Flash memory Table 3 4 Boot Mode Settings JP1 BMODEI JP2 BMODEO Boot Mode Installed Installed 16 Bit External Memory Installed Not installed Flash Memory Not installed Installed Reserved Not installed Not installed SPI EEPROM 1 Default settings Core Voltage Source Select Jumper JP3 The core voltage of the processor can be derived from either the proces sor s internal voltage regulator or from a fixed 1 4V external regulator It is necessary to use the 1 4V external regulator when the processor runs at speeds greater than 600 MHz Table 3 5 summarizes the functionality of the Core Voltage Source
83. r more detailed information about programming the ADSP BF533 Blackfin processor see the documents referred to as Related Documents EZ KIT Lite License Restrictions The license shipped with the EZ KIT Lite imposes the following restrictions The size of a user program is limited to 20 KB of the ADSP BF533 processor s internal memory space e No connections to simulator or emulator sessions are allowed The EZ KIT Lite hardware must be connected and powered up in order to use VisualDSP with a kit license Memory Map The ADSP BF533 processor has internal SRAM that can be used for instruction or data storage The configuration of internal SRAM is detailed in the ADSP BF533 Processor Hardware Reference The ADSP BF533 EZ KIT Lite board includes two types of external memory SDRAM and Flash memory The size of the SDRAM is 32 Mbytes 16M x 16 bit The processor s memory select pin SMSO is configured for the SDRAM 2 2 ADSP BF533 EZ KIT Lite Evaluation System Manual Using EZ KIT Lite The Flash memory is implemented with two Dual Bank Flash Memory devices These devices include primary and secondary Flash memory as well as internal SRAM and registers Primary Flash memory totals 2 Mbytes mapped into two separate asynchronous memory banks 1 Mbyte each Secondary Flash memory along with SRAM and registers occupies the third bank of asynchronous memory space The processor s AMSO AMS1 and AMS2 memo
84. ration register addresses for Flash A and Flash B respectively only ports A and B are listed The following bits connect to the Expansion Board connector Flash A port B bits 7 and 6 Flash B port A bits 7 0 and port B bits 7 0 Table 2 6 Flash A Configuration Registers for port A B Register Name Port A Address Port B Address Data In Read only 0x2027 0000 0x2027 0001 Data Out Read Write 0x2027 0004 0x2027 0005 Direction Read Write 0x2027 0006 0x2027 0007 Table 2 7 Flash B Configuration Registers for port A B Register Name Port A Address Port B Address Data In Read only Ox202E 0000 0x202E 0004 Ox202E 0001 Data Out Read Write Ox202E 0005 Direction Read Write 0x202E 0006 Ox202E 0007 Table 2 8 and Table 2 9 depict the IO assignments Table 2 8 Flash A Port A Controls Bit User IO Bit Value 7 Not defined Any 6 Not defined Any 5 PPI Clock Select bit 1 00 Local OSC 27 MHz 2 8 ADSP BF533 EZ KIT Lite Evaluation System Manual Using EZ KIT Lite Table 2 8 Flash A Port A Controls Contd Bit User IO Bit Value 4 PPI Clock Select bit 0 01 Video Decoder Pixel Clock 1X Expansion Board PPI Clock 3 Video Decoder Reset 0 Reset ON 1 Reset OFF 2 Video Encoder Reset 0 Reset ON 1 Reset OFF 1 Reserved Any 0 Codec Reset 0 Rese
85. rocessor is capable of reading the embedded control information which is in the data stream ADSP BE533 EZ KIT Lite Evaluation Svstem Manual 3 11 Jumper and DIP Switch Settings Position 6 of SW3 determines whether PF2 is connected to the 0E signal of the ADV7183 When the switch OFF PF2 can be used for other opera tions and the decoder output enable is held HIGH with a pull up resistor Push Button Enable Switch SW9 The push button enable switch SW9 positions 1 through 4 allow the user to disconnect the drivers associated with the push buttons from the PF pins of the processor Positions 5 and 6 are used to connect the transmit and receive the frame syncs and clocks of SPORTO This is important when the AD 1836 video decoder and the processor are communicating in PS mode Table 3 7 shows which PF is driven when the switch is in the ON position Table 3 7 Push Button Enable Switch SW9 Switch Position Default Setting Pin Signal Side 1 Pin Signal Side 2 1 0 1 SW4 12 PF8 2 0 2 SW5 11 PF9 3 0 3 SW6 10 PF10 4 0 4 SW7 9 PF11 5 OFF 5 TFSO 8 RFSO 6 OFF 6 RSCLKO 7 TSCLKO 3 12 ADSP BF533 EZ KIT Lite Evaluation System Manual EZ KIT Lite Hardware Reference LEDs and Push Buttons This section describes the functionality of the LEDs and push buttons Figure 3 3 shows the locations of the LEDs and push buttons NEM MIT D Li 1 L
86. ry select pins are used for that purpose Table 2 1 EZ KIT Lite Evaluation Board Memory Map Start Address End Address Content External 0x0000 0000 0x07FF FFFF SDRAM Bank 0 SDRAM See Using SDRAM Memory Interface on page 2 4 0x2000 0000 0x2000 FFFF ASYNC Memory Bank 0 Primary Flash A See Using Flash Memory on page 2 5 0x2010 0000 0x201F FFFF ASYNC Memory Bank 1 Primary Flash B See Using Flash Memory on page 2 5 0x2020 0000 0x202F FFFF ASYNC Memory Bank 2 Flash A and B Secondary Memory SRAM and Internal Registers See Using Flash Memory on page 2 5 All other locations Not used Internal OxFF80 0000 OxFF80 3FFF Data Bank A SRAM 16 KB Memory Vo reg 4000 OxFF80 7FFF Data Bank A SRAM CACHE 16 KB BE 0000 osea 3FEF Data Bank B SRAM 16 K OxFF90 4000 OxFF90 ZFFF Data Bank B SRAM CACHE 16 KB OxFFAO 0000 OxFFAQ FFFF Instruction SRAM 64 KB OxFFA1 0000 OxFFA1 3FFF Instruction SRAM CACHE 16 KB OxFFBO 0000 OxFFBO OFFF Scratch Pad SRAM 4 KB OxFFCO 0000 FFFF System MMRs 2 MB OxFFEO 0000 OxFFFF FFFF Core MMRs 2 MB All other locations Reserved ADSP BF533 EZ KIT Lite Evaluation System Manual 2 3 Using SDRAM Interface Using SDRAM Interface The three SDRAM control registers must be initialized in order to use the MT48LC4MIGATG 75 16M x 16 bits 32 MB SD
87. s Option Description Reset before loading exe cutable Resets registers before loading a DSP executable Clear this option when DSP registers must not change to their reset values when a file load occurs Verify all writes to target memory Validates all memory writes to the DSP After each write a read is performed and the values are checked for a matching condition Enable this option during initial program development to locate and fix initial build problems such as attempting to load data into non existent memory Clear this option to increase performance while loading executable files since VisualDSP does not perform the extra reads that are required to verify each write 2 18 ADSP BF533 EZ KIT Lite Evaluation System Manual Using EZ KIT Lite Table 2 13 Miscellaneous Target Options Contd Option Description Reset cycle counters on run Resets the cycle count registers to zero before a Run command is issued Select this option to count the number of cycles executed between breakpoints in a program Auto configure SDRAM bank 0 VisualDSP will auto configure the necessary registers to commu nicate with the SDRAM Bank 0 memory included on the EZ KIT Lite evaluation board Select this option to cause VisualDSP to configure Bank 0 when it is accessed through VisualDSP for example when viewing memory windows or loading a program Clear this option if y
88. set 4 programmable flags Expansion Interface v PPI SPI EBIU Timers2 0 UART programmable flags SPORTO SPORT1 Other Features v JTAG ICE 14 pin header The EZ KIT Lite board has two Flash memories with a total of 2 MB of memory The Flash memories can be used to store user specific boot code allowing the board to run as a stand alone unit For more information see Using Flash Memory on page 2 5 The board also has 32 MB of SDRAM which can be used by the user at runtime ADSP BF533 EZ KIT Lite Evaluation System Manual xiii Purpose of This Manual SPORTO is interfaced with the AD 1836 audio codec allowing you to create audio signal processing applications SPORTO is also attached to an off board connector to allow communication with other serial devices For information about SPORTO see SPORT0 Audio Interface on page 3 4 The Parallel Peripheral Interface PPI of the DSP is connected to both a video encoder and video decoder allowing you to create video signal pro cessing applications The UART of the DSP is connected to an RS232 Line Driver and a DB9 male connector allowing you to interface with a PC or other serial device Additionally the EZ KIT Lite board provides access to most of the pro cessor s peripheral ports Access is provided in the form of a three connector expansion interface For information about the expansion interface see Expansion Interface on page 3 8 Purpose of This Manual
89. souo I7 TFS0 CO ei Ht SHORTING L DTOPRI JUMPER EE H2 DEFAULT JP1 INSTALLED L DTOSECI lt DTOSEC SJ3 U DSCLKT eset SHORTING m JUMPER 3 3V LE G2 ES L RES1 RES DEFAULT JP2 NOT INSTALLED C M D n O SSpniPRI 1 a F3 L DRISECI 2 DR SEC Boot Mode Select Jumpers JP1 JP2 Cer Fi seik DEFAULT Flash Boot 25 E1 3 3V JP1 BMODE1 JP2 BMODEO Boot Mode TFS 5 TFS1 TN F2 L INSTALLED INSTALLED 16 BIT External Memory lt _ pT1 PRI R4 E3 INSTALLED NOT INSTALLED Flash 10K L DTISECI lt DTISEC 805 E14 wes RR a PP 0 3 NOT INSTALLED INSTALLED Reserved AMS gt JAMSO PP0 F14 L3 NOT INSTALLED NOT INSTALLED SPI EEPROM AMSI gt AMSI 1 O RX PP1 AMS2 2 gt AMS2 TX lt 2 EE E13 G12 R15 R18 L _ARDYI ARDY AMS3 gt AMS3 1 PP3 10K 10K 813 EE i D3 805 805 L AGE lt ACE L Mos MOs 33V DB e O iii m Le L ARE lt G RE SRASDIS gt JSRAS L MISOI iso PPI CLK IPPLCIK N LAMEL lt ame SCASP gt ISCAS Lag scx swe gt ISWE R14 TCK TCK L 0 ABEO SDQMOI ABEO SDQMO sckEP 3 SCKE E U TMRO lt gt mol TDO I ABEI SDQMtI C 12 ABE1 SDQM1 cLkourP 4 2 ICGLK OUT 1 U TM
90. t ON 1 Reset OFF Table 2 9 Flash A Port B Controls Bit User IO Bit Value 7 Not used Any 6 Not used Any 5 LED9 0 LED OFF 1 LED ON 4 LED8 0 LED OFF 1 LED ON 3 LED7 0 LED OFF 1 LED ON 2 LED6 0 LED OFF 1 LED ON 1 LED5 0 LED OFF 1 LED ON 0 LED4 0 LED OFF 1 LED ON Configuring Flash Memory The Flash memory is completely configurable To modify the default setup of each flash you must use PSDsoft Express software After the project has been modified the Flash memory must be re programmed using FlashLINKTM The default project file is provided in VisualDSP 32 Bit Processors Blackfin EZ KITS ADSP BF533 PSDConfigFiles directory Analog Devices does not provide any support for setting up the ADSP BF533 EZ KIT Lite Evaluation System Manual 2 9 Using LEDs and Push Buttons PSD4256G6V with PSDsoft Express or programming it using FlashLINK Email STMicroelectronics at apps psd st com for technical assistance The PSD4256G6Vcan be re programmed using the FlashLINK JTAG programming cable available from STMicoreclectronics www st com psd for approximately 59 FlashLINK plugs into any PC parallel port The PSDsoft Express development software is required to modify the DSM2150 configuration and to operate the FlashLINK cable PSDsoft Express can be downloaded at no charge from www st com psd Using LEDs and Push Buttons The EZ KIT Lite prov
91. te board xii flag pins see programmable flags PFs flash A 2 7 configuration registers 2 8 port A controls 2 8 port B controls 2 9 primary 2 7 registers 2 7 secondary 2 7 SRAM 2 7 flash B 2 7 configuration registers 2 8 primary 2 7 registers 2 7 secondary 2 7 l 2 ADSP BE533 EZ KIT Lite Evaluation Svstem Manual SRAM 2 7 flash memory xiii 2 5 3 3 3 10 configuring 2 9 general purpose IO pins U5 3 15 map 2 6 modifying PSDsoft Express 2 9 primary 2 3 3 3 programming FlashLINK 2 9 reserved 2 7 secondary 3 3 flash ports PBO 5 3 15 Found New Hardware Wizard Windows 2000 1 14 frequency 2 4 2 5 G general purpose IO 2 10 2 11 graphical user interface GUI 2 13 H hard reset 2 16 Help online xx HSYNC signal 3 6 3 7 3 11 I 125 mode 2 11 installation summary 1 3 installing EZ KIT Lite USB driver 1 7 VisualDSP and EZ KIT Lite license 1 5 VisualDSP and EZ KIT Lite software 1 4 interfaces INDEX SDRAM 2 4 see graphical user interface GUI internal regulator 3 2 internal memory 2 3 3 9 core MMRs 2 3 data bank A SRAM 2 3 data bank B SRAM 2 3 instruction SRAM 2 3 instruction SRAM CACHE 2 3 reserved 2 3 scratch pad SRAM 2 3 system MMRs 2 3 IO configuration registers 2 6 signals 2 7 voltage 3 2 IO port registers 2 7 Data In 2 7 Data Out 2 8 Direction 2 7 J JTAG connector P4 3 20 emulation port 3 9 programm
92. tions xiv codec 2 11 connectors J4 J5 3 17 interface see SPORTO see also AD1836 B background telemetry channel BTC 2 13 bill of materials A 1 boot load 2 16 mode select JP1 2 3 10 breakpoints restrictions 2 19 C clock frequency 2 4 2 5 codecs 3 configuration registers IO 2 6 ADSP BF533 EZ KIT Lite Evaluation System Manual I 1 INDEX connecting EZ KIT Lite board 1 5 connectors 1 5 3 16 extender connectors P3 1 3 3 FlashLINK P1 3 18 JI expansion interface 3 8 J10 USB 1 6 J2 expansion interface 3 8 J3 expansion interface 3 8 J audio 3 17 J5 audio 3 17 J8 video 3 17 J9 power 3 17 P4 JTAG 3 9 3 20 P9 SPORTO 3 19 RS232 P2 3 19 see also expansion interface contents EZ KIT Lite package 1 1 conventions manual xxii core frequency 2 5 voltage 3 10 customer support xvi D Device Manager window 1 16 DIP switches 3 9 see SW dual bank Flash memory 2 3 E EBIU_SDBCTL 2 4 EBIU_SDGCTL 2 4 EBIU SDRRC 2 4 electrostatic discharge 1 2 emulation events 2 16 example programs 2 13 exceptions 2 16 expansion board 2 8 interface 3 4 3 8 3 16 extender connectors P3 1 3 3 external bus interface unit EBIU 3 3 flash memory see flash memory regulator 3 2 3 10 external memory 3 9 bank 0 primary A 2 3 bank 0 SDRAM 2 3 EZ KIT Lite board architecture 3 2 features xii F features EZ KIT Li
93. tors This section describes the connector functionality and provides informa tion about mating connectors The locations of the connectors are shown in Figure 3 4 on page 3 16 n E 3 REV 15 2002 A DEVICES INC F533 E2UTE Figure 3 4 Connector Locations Expansion Interface J3 1 Three board to board connector footprints provide signals for most of the processor s peripheral interfaces The connectors are located at the bottom of the board For more information about the expansion interface see on page 3 8 For the availability and pricing of the J1 J2 and J3 connec tors contact Samtec 3 16 ADSP BF533 EZ KIT Lite Evaluation System Manual EZ KIT Lite Hardware Reference Part Description Manufacturer Part Number 90 Position 0 05 Spacing SMT 91 J2 J3 Samtec Mating Connector SFC 145 T2 F D A 90 Position 0 05 Spacing Samtec TFM 145 x1 Series Through Hole 90 Position 0 05 Spacing Samtec TFM 145 x2 Series Surface Mount 90 Position 0 05 Spacing Samtec TFC 145 Series Low Cost Audio J5 4 Part Description Manufacturer Part Number 2x2 RCA Jacks J5 SWITCHCRAFT PJRAS2X2S01 3x2 RCA Jacks J4 SWITCHCRAFT PJRAS3X2S01 Mating Connector Two channel RCA interconnect Monster Cable BI100 1M cable Video J8 Part Description Manufacturer Part Number 3x2 RCA Jacks J4 SWITCHCRAFT PJRAS3X2S01
94. w Hardware Wizard The wizard has finished installing the software for Ha ADSP BF533 EZ KIT Lite Click Finish to close the wizard Figure l 11 Windows XP Completing Driver Installation 4 Verifv the installation bv following the instructions in Verifving Driver Installation Verifving Driver Installation Before using the EZ KIT Lite evaluation svstem verifv that the USB driver software is installed properlv 1 Ensure that the USB cable is connected to the evaluation board and the PC 2 Verifv that the vellow USB monitor LED LED11 is lit This signi fies that the board is communicating properlv with the host PC and is ready to run VisualDSP ADSP BE533 EZ KIT Lite Evaluation Svstem Manual l 15 Installation Tasks 3 Verify that the USB driver software is installed properly Open Windows Device Manager and verify that ADSP BF533 EZ KIT Lite shows under ADI Development Tools with no excla mation point as in Figure 1 12 Device Manager File Action View Help BB ADI Development Tools B ADSP BFS33 EZ KIT Lite d Computer lt a Disk drives Display adapters 4 DVD CD ROM drives amp Floppy disk controllers 3 Floppy disk drives amp IDE ATA ATAPI controllers Vx Keyboards A Mice and other pointing devices Monitors BE Network adapters jJ Ports COM amp LPT 8f Processors Sound video and game controllers System devices Universal
95. wn the board Power LED LED1 When LED is lit green it indicates that power is being properly supplied to the board Reset LEDs LED3 2 When LED2 is lit it indicates that the master reset of all the major ICs is active When LED3 is lit the USB interface chip U34 is being reset The USB chips only reset on power up or if USB communication has not been initialized 3 14 ADSP BF533 EZ KIT Lite Evaluation System Manual EZ KIT Lite Hardware Reference User LEDs LED 4 Six LEDs are connected to six of the Flash memory U5 general purpose IO pins The LEDs are active HIGH and are lit by writing a 1 to the correct memory address in the Flash memory Refer to Using LEDs and Push Buttons on page 2 10 for more information about how to use the flash when programming the LEDs Table 3 9 User LEDs LED Reference Designator Flash Port Name LED4 PBO LED5 D I LED6 PB2 LED7 PB3 LED8 PB4 09 5 USB Monitor LED LED11 The USB Monitor LED LED11 indicates that USB communication has been initialized successfully and you may connect to the processor using a VisualDSP EZ KIT Lite session This should take approximately 15 seconds If the LED does not light try cycling power on the board and or reinstalling the USB driver see Installing EZ KIT Lite USB Driver on page 1 7 ADSP BF533 EZ KIT Lite Evaluation System Manual 3 15 Connectors Connec
96. yy 2 gt IPF8 1 20UT R N SARA ti 2 11 FER16 VEN PF11 R152 R158 m QS 1 SOIC16 Con 600 O 100 0 00 3 10 r mm o 603 8 805 i 1206 L Em 1 805 KI ES 5 5 6 4 9 47 l w O Pe pes SW7 or 5 B ASS kasai N SWT013 pO I TES ii ORR A O SEET erts Taser O W 2 DER 11 1UF SWTOI7 SA TNA DIP6 DB9M 9PIN DNP Do Not Populate SW8 PB Enable Switch N Z ANAI Ol I 20 Cotton Road Position Function je Connects the push buttons to the Programmable Flags of the DSP Nashua NH 03063 Useful if using the PFs for another purpose DE V ICES PH 1 800 ANALOGD 56 Connects SPORTO frame sync and clock together external to the DSP Required when AD1838 is n 128 mode Approvals Date ADSP BF533 EZ KIT JO RESET UART Drawn Engineerin 8 8 Date 2 3 2004 11 18 Sheet 9 of 13 B C D EXPANSION INTERFACE TYPE B

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