RCA Microprocessor Hardware Support Kit
Contents
1. must be less than equal to Vpp Power supplies should be sequenced to insure compliance Input Signals To prevent damage to the input protec tion circuit input signals should never be greater than Vpp nor less than Vgc Input currents must not exceed 10 mA even when the power supply is off Unused Inputs A connection must be provided at every input terminal All unused input ter minals must be connected to either Vpp or Vgs whichever is appropriate Output Short Circuits Shorting of outputs to Vpp or Ves may damage COS MOS devices by exceeding the maximum device dissipation OPERATING AND HANDLING CONSIDERATIONS FOR CDP1801UH AND CDP1801RH CHIPS Mounting Considerations COS MOS chips non gold backed and require the use of epoxy mounting DuPont No 5504A conductive silver paste or equiva lent recommended any case the manu facturer s recommendations for storage and use should be followed If DuPont No 5504A paste is used the bond should be cured at temperatures between 1859C and 200 for 75 minutes COS MOS circuits P channel substrates are connected to Vpp therefore when chips are mounted and a conductive paste is used care must be taken to keep the active substrate isolated from ground or other circuit elements Packing Shipping and Storage Criteria Solid state chips unlike packaged devices are non hermetic devices normally fragile and small in physical size and therefore re2. DATA TO COSMAC ES SEDE Re tpmwoH gt gt het PMWHL MWR 92CM 27016 Notes 1 This timing diagram is used to show signal relationships only and does not represent any specific machine cycle N All measurements are referenced to 50 point of the waveforms Fig 2 Timing waveforms 4 CDP1801 CDP1801C File No 900 INTERNAL TIMING INTERVALS 5 6 7 213 4 5 6 7 ol 2 4 5 6 7 1 2 4 5 2 5 tdi ius STATE E so p sion sR SS 50 DMA IR DMA OUT EAM UE DMA IN BUS OFF OFF DMA OUT enn 25442245544 LLL LLL LLL LLL LLLA 2 52 INTER TIMING INTERVALS INTERRUPT TIMING TPA TPB STATE SO OR S2 INTERRUPT NS NS RS 5555 INTERRUPT ENABLE INHIBIT INTERRUPT FLAG INPUT TIMING STATE Po re St el FLAG 92CL 26422 GENERAL TIMING ae ee CLOCK TERN Tie Wrervacs TSISI7 oT 2 3 5 7 D T2 5 IS 7 Te HE TT ES TS T tor TT 8 MACHINE CYCLE EXECUTION EXEC INSTR CH CYCLE INSTRUCTION TIME tz 2CYCLES TIMING PULSES 9 43 spe t Io 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Ln TPB MEMORY TIMING ADDRESS MAO TO MA7 READ MWR NOTE 2 MEMORY OUTPUT 2 2 2 LL A Ne L E No BYTE NOTE 3 VALID BYTE ALLOWABLE MEMOR
3. 265 C OPERATING CONDITIONS AT Ta 25 C Unless Otherwise Specified For maximum reliability nominal operating conditions should be selected so that operation is always within the following ranges CONDITIONS LIMITS CHARACTERISTIC Supply Voltage Range At TA Full Package Temperature Range Recommended Input Voltage Clock Input Rise or Fall Time t t Instruction Time See Fig 4 Notes 1 lt Vpp For CD1801C Vec 5 volts 2 Because large number of nodes may be switching simultaneously 0 1 uF by pass capacitor is recommended in the power supply 3 In order to maintain proper circuit operation the CDP 1801 intra unit wiring capacitance should be less than 25 pF CDP1801 CDP1801C _ File No 900 ELECTRICAL CHARACTERISTICS at 25 C 5 CDP1801U CDP1801CU CDP1801R CDP1801CR LIMITS LIMITS Q o 2 g 3 2 Min Min Max Quiescent Device Current 5 0 01 01 001 05 See Figs 11 12 3 ma 15 e Os 0 05 Low Level V V 2 a0 ops oos 1 5 49 5 495 5 y per OH mhs o Noise Immunity a os s us 225 us 226 V e E ET TII m y 9 101 30 1 1 m D Output Drive Current N Channel Si
4. 92CS 27022 Fig 9 Typical high to low level transition time vs load capacitance CDP1801 CDP1801C File No 900 AMBIENT TEMPERATURE TA 25 C VoD Vcc HIGH LEVEL TRANSITION TIME 1 yj ns 20 40 60 100 LOAD CAPACITANCE C pF 92 5 27023 Fig 10 Typical low to high level transition time vs load Capacitance TEST CIRCUITS Hitt 92 5 27025 Vss Fig 12 CDP1801R CDP1801CR quiescent device current 92CS 27024 Vss Fig 11 CDP1801U CDP1801CU quiescent device current VoD 90 400 AWN NOTE MEASURE INPUTS SEQUENTIALLY TO BOTH AND Vss CONNECT ALL UNUSED INPUTS TO EITHER Vpp OR Vss Vss Vsg NOTES MEASURE INPUTS SEQUENTIALLY TO BOTH Vpp AND Vss CONNECT ALL UNUSED INPUTS TO EITHER Vpp OR Vss t WHEN MEASURING INPUT LEAKAGE ON PINS 2 3 4 5 24 25 26 827 23 MUST BE CONNECTED TO Vpp 92 5 27027 Vss VR 92CS 27026 Fig 13 CDP1801U CDP1801CU input Fig 14 CDP1801R CDP1801CR input leakage current leakage current File No 900 The following is a brief description of the COSMAC microprocessor For more detailed information see the following publication User Manual for the COSMAC Micropro cessor MPM 101 A Hardware Kit CDP 185001 including the CDP1801 Micropro cessor and support logic is also available The RCA Microprocessor COSMAC is im plemented by two CO
5. ADDRESS L OUT M JL ADDRESS 8 CLOCK CLEAR LOAD 3 CLOCK amp CONTROL TIMING amp MSC DEPENDING ON SYSTEM RAM ROM 65536 BYTES COSMAC CONTROL MAX MWRITE CKTS 1 0 DEVICES BUS I Fig 2 System Block Diagram Vss RG Solid State Division Microprocessor Products CDP1801 CDP1801C CDP1801U CU 40 Lead Dual in Line Ceramic D Features CDP1801R CR 28 Lead Dual In Line Ceramic D The RCA CDP1801 and CDP1801C Micropro cessors COSMAC are LSI COS MOS 8 bit register oriented central processing units CPU designed for use as general purpose computing or control elements in a wide range of stored program systems or products The CDP1801 and CDP1801C each comprise two units the control unit designated CDP 1801U CDP1801CU and the register unit designated CDP1801R CDP1801CR The CDP1801 is functionally identical to the CDP1801C The CDP1801 has an operating voltage range of 3 to 12 volts the CDP1801C an operating voltage range of 4 to 6 volts These microprocessors include all of the cir cuits required for fetching interpreting and executing instructions which have been stored in standard types of memories Extensive input output I O control features are also provided to facilitate system design The COSMAC architecture was designed with emphasis on the total microcomputer system as an integra
6. At all other times the register designated as program counter is at the discretion of the user File No 900 Data Pointers The registers in R may be used as data pointers to indicate where the data operand is located in the memory The register de signated by X i e R X points to the operand for the following instructions see Table 1 1 ALU operations FO through F7 2 output instructions 61 through 67 3 input instructions 69 through 6F The register designated by i e R N points to the operand for the load D from memory instruction 4N and the store D instruction 5N The register designated by P i e the program counter is used as the data pointer for ALU instructions F8 through FF During these instruction executions the oper ation is referred to as data immediate Another important use of R as a data pointer supports the built in Direct Memory Access DMA function When a DMA in or DMA out request is received one machine cycle is stolen This operation occurs at the end of the execute machine cycle in the current instruction Register R O is always used as the data pointer during the DMA operation The data is read from or written into the memory location pointed to by the R O register whether the request is for or out At the end of the transfer R O is incremented by one so that the processor is ready to act upon the next DMA byte trans fer request This feature i
7. CR 1 27 26 25 24 17 18 19 20 23 22 These pins are for interchip connections only Notes 1 Any unused input pins should be connected to Vpp or 2 The DATA BUS lines are bi directional and have three state outputs They may be individually connected to Vcc through external pull up resistors 22 recommended to prevent floating inputs 3 All inputs have the same noise immunity and level shifing capability All outputs have the same drive capability shether they have three state outputs or not 4 For the CDP1801C Vcc must be connected to Vpp Fig 17 Terminal assignment diagrams DIMENSIONAL OUTLINES CDP1801R CDP1801CR CDP1801U CDP1801CU 28 Lead Ceramic 40 Lead Ceramic ow T STE wees MIN MAX MIN IU em ORDERING INFORMATION The CDP1801 and CDP1801C are 2 package microprocessors consisting of a control unit CDP1801U or CDP1801CU and a register unit CDP1801R or CDP1801CR When ordering both the control unit and the register unit request the CDP1801 or the CDP1801C When ordering either the control unit or the register unit add the appropriate RCA Solid State Division Somerville NJ 08876 92CM 26419 92CM 27029 NOTES Leads within 0 13 mm 0 005 radius of true position at maximum material condition Dimension L to center of leads when formed parallel When this device is supplied solder dipped the max
8. N 2 OUT 3 OUTPUT 3 M R X gt BUS R X 1 N 3 OUT 4 OUTPUT 4 M R X gt BUS R X 1 N 4 OUT 5 OUTPUT 5 M R X gt BUS R X 1 N 5 OUTPUT 6 MIR X BUS OUT 6 1 6 7 OUT 7 OUTPUT 7 06 R X 1 N 7 Mec isi INP3 INPUT3 BUSMIR X N B INPUT 4 05 gt N C INPUT5 BUS M R X N D BO LE INPUT6 BUS M R X N E INPUT 7 BUS gt M R X N F BUS M R X N 9 BUS M R X N A CDP 1801 CDP1801C Note 2 This type of abbreviated nomen clature is used when programs are de signed with the aid of the COSMAC Assembler Simulator Debugger Sys tem which is available on com mercial timesharing systems Refer to Program Development Guide for the COSMAC Microprocessor MPM 102 for details Note 3 When executing any of the 69 to 6F instructions the contents of the D register may be altered Test and Branch The Test and Branch instructions can branch unconditionally test for 0 0 or D 1 test for DF 0 or DF 1 or can test the status of the four I O flags A successful branch loads the byte following the instruction into the lower order byte position of the current program counter effecting a branch within the current 256 byte page of memory If the test to branch is not successful the next instruction in sequence is executed SIGNAL DESCRIPTION Function A single negative pulse is required A momenta
9. The X designator selects one of the 16 reg isters R X to point to the memory for an operand or data in certain ALU or 1 0 operations The N designator can perform the following five functions depending on the type of in struction fetched 1 designate one of the 16 registers in R to be acted upon during register opera tions indicate to the I O devices a command code or device selection code for peri pherals indicate the specific operation to be executed during the ALU instructions types of tests to be performed during the Branch instructions or operating modes of interrupt handling instruc tions indicate the value to be loaded into P to designate a new register to be used as the program counter R P indicate the value to be loaded into X to designate a new register to be used as data pointer R X The registers in R can be assigned by a pro grammer in three different ways as program counters as data pointers or as scratchpad locations data registers to hold two bytes of data Program Counters Any register can be the main program counter the address of the selected register is held in the P designator The other reg isters in R can be used as subroutine program counters By a single instruction the contents of the P register can be changed to effect a call to a subroutine When interrupts are being serviced register R 1 is used as the program counter for the interrupt servicing routine
10. The three paths depending on the nature of the instruction may operate independently or in various combinations in the same machine cycle CLOCK EFI EF2 EF3 EF4 IN INT REG OUT LOAD STATE 62 ed sci Bo tN ast G CODES MAOMAI MAS MA4 MAB MAG Ssa Qood ele LI TPS MUX e CONTROL LOGIC TIMING d CAMREAD f 1 0 COMMANDS hie TPB 8 DO OO 9 0 9 9 9 BUSO 8 CDP I80ICR SP ASTD STAG AF SPARSE EIA SEAN PSA AT AE TT A AT ASAP 74 AT SL 180 0 CDP I80ICU 92CL 27028 Fig 15 CDP1801 CDP1801C Microprocessor block diagram CDP1801 CDP1801C Every COSMAC instruction consists of two 8 clock pulse machine cycles The first cycle is the fetch cycle and the second is the execute cycle During the fetch cycle the four bits in the P designator select one of the 16 registers R P as the current program counter This selected R P contains the address of the memory location from which the instruction is to be fetched When the instruction is read out from the memory the higher order 4 bits of the instruction byte are loaded into the register and the lower order 4 bits are fed to the N register The content of the program counter is auto matically incremented by one so that R P is now pointing to the next byte in the memory
11. possible The instruction set facilitates the use of interpretive macro instructions The on chip scratch pad of sixteen general purpose 16 bit registers may be used to provide multiple program counters data pointers and data storage Three specific registers are treated by the hardware as implicit built in DMA address pointer program counter for interrupt servicing and interrupt subroutine stack pointer respectively A simple one step program loading facility is provided on the chip Fig 1 shows the internal structure of COSMAC The COSMAC 1 0 interface was designed to provide direct control of 1 0 devices so that over all system complexity and cost can be reduced Flexible open ended 1 0 instructions allow unlimited device attachment The hardware 1 0 interface is capable of supporting devices operating in polled interrupt driven and Direct Memory Access modes Fig 2 illustrates the general form of a system incorpo rating the COSMAC Microprocessor Design aids such as a Microprocessor hardware support kit COSMAC Microkit and a program development system with manuals and software are provided to help system designers in the development of Microprocessor based products The following list summarizes the advanced fea tures and operating characteristics of the COSMAC Microprocessor 8 bit parallel organization 8 bit bidirectional common bus for input output and memory static COS MOS circuitry low power cons
12. the Input Output voltage supply so that the processor may oper ate at maximum speed while interfacing with various external circuit technologies including T2L at 5 volts must be less than or equal to Vpp 13 File No 900 COSMAC Microprocessor State Transitions Fig 16 shows the CDP1801 and CDP1801C Microprocessor state transitions Each ma chine cycle requires the same period of time 8 clock cycles The execution of each COS MAC instruction requires two machine cycles SO followed by 51 52 is the response to a DMA request and S3 is the interrupt response discussed in the preceding text CDP1801 CDP1801C 9265 26557 Fig 16 CDP1801 1801 M croprocessor state transitions OPERATING AND HANDLING CONSIDERATIONS FOR CDP1801 MICROPROCESSOR 1 Handling All inputs and outputs of this device have a network for electrostatic protection during handling Recommended hand ling practices for COS MOS devices are described ICAN 6000 Handling Operating Considerations for MOS In tegrated Circuits available on request from RCA Solid State Division Box 3200 Somerville N J 08876 2 Operating Operating Voltage During operation near the maximum supply voltage limit care should be taken to avoid or suppress power supply turn on and turn off transients power supply ripple or ground noise any of these con ditions must not cause Vpp Vss to exceed the absolute maximum rating
13. 00 Thus program execution begins at location 0001 with R O as the program counter It is recommended that MEM LOC 0000 not be used by the program 12 CDP1801 CDP1801C BUS 0 to BUS 7 Data Bus NO to N3 I O Command EF1 to EF4 4 Flags INTERRUPT DMA IN DMA OUT 3 I O requests SCO SC1 SC2 3 State Code Lines TPB 2 Timing Pulses LOAD VDD Vss Power Levels File No 900 The low M READ line enables the memory output bus gates during the read cycle see Fig 1 Timing Diagram 8 bit bidirectional DATA BUS lines These lines are used for trans ferring data between the memory the microprocessor and I O devices Issued by an I O instruction They are interpreted by I O con trol logic to move data between the memory and the I O inter face discussed in the Architecture section These lines can be used to issue command codes or device selection codes to the I O devices independently or combined with the memory byte on the data bus when an I O instruction is executed N bits are set at the end of every SO cycle These levels enable the I O controllers to transfer status infor mation to the processor These levels can be tested by the con ditional branch instructions They can be used in conjunction with the INTERRUPT request line to establish interrupt prior ities These flags can also be used by I O devices to call the attention of the processor in which case the pro
14. 28 lead hermetic ceramic dual in line package D suffix and in chip form H suffix For ordering information see dimensional out line page AS DATA BUS 92CS 26536R Fig 1 CDP1801 CDP1801C Microprocessor data flow chart Trademark s Registered amp Information furnished by RCA is believed to be accurate and reliable However no responsibility is assumed by RCA for its use nor for any infringements of patents or other rights of Marca s Registrada s Printed in USA 9 75 third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of RCA IVWSOJD 1055920100121 21091402 711091402 File No 900 CDP1801 CDP1801C MAXIMUM RATINGS Absolute Maximum Values Storage Temperature Range T sig EO ee DIS 65 to 150 C Operating Temperature Range 55 to 125 C DC Supply Voltage Range All voltage values referenced to Vss terminal lt Vpp 0 5 to 15 V CDP1801C 0 5 to 7 V Power Dissipation Per Package Pp For 55 to 100 C For 100 to 125 C ee Derate Linearly to 200 mW Device Dissipation Per Output Transistor For TA 559C to 125 C 100 mw Input Voltage Range All Inputs 0 5 to Vpp 0 5 V Lead Temperature During Soldering At distance 1 16 1 32 inch 1 59 0 79 mm from case for 106 max
15. 78 92 27059 Dimensions and Pad Layout for CDP180TUH Chip 24 D 69 9 246 D 20 40 60 80 120 140 160 180 200 220 24050 236 zem A MI zz I4 m c ow te rrr 24 2 TOUTS ee M V 38 2 2242 i PI oe ha m ES LEP ENT 2 Q S i 3 3 43 0 084 0 109 2 0 254 0 102 0 zx 5 919 6 121 92CS 27060 Dimensions and Pad Layout for CDP1801RH Chip Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated Grid graduations are in mils 1073 inch 15 File No 900 VoD DAT BUS 3 BUS 4 AUS 805 5 805 5 BUS BUST BUS 6 gt BUSO BUS 7 NO Vss 0 Ni FFI COMMANDS E 1 0 ome a FLAGS N3 4 x DMA OUT I O x INTERRUPT REQUEST DMA IN Y x CLEAR SON TROL LOAD TIMING TPB Sc PULSES TES 255 pad TPA SCi CODE Sco MWR MREAD Vss x TOP VIEW COPIBOICU 92CS 2641 Package Interconnections Pin Terminals To CDP1801 CDP1801C VoD BUS 3 205 DATA rus BUS 2 Bus Busi gt 8050 TPB MEMORY ADDRESS LINES x t CLEAR 4 PIBOICR 92CS 26418RI ESSBRRRRREREREERE CoP18OTR
16. CA within 90 days of the date of the shipment by RCA After shipment from RCA RCA assumes no responsibility for chips that have been subjected to further 14 CDP1801 CDP1801C File No 900 OPERATING AND HANDLING CONSIDERATIONS FOR CDP1801UH CDP1801RH CHIPS CONT D processing such as but not limited to lead For additional recommended handling prac bonding or chip mounting operations RCA tices for COS MOS chips refer to 6000 reserves the right to change the chip design Handling and Operating Considerations for and processing without notification MOS Integrated Circuits BC 09 69 29 G7 1207 160 180 VO VA Sey Be I 2 5 8 p pue 2 ds SN y vv het dab die xe T i PT 1 re gg RF ae RS at 252 260 6 401 6 604 vx gt EUS de ud ae hi f paan f gl ums EN k 652 Ad fg gt 2 Ae u 17 ail 5 te lt Au Wer i f A aT ih er ur ys gt lt Mx ar AS e C 9 x y 5 lel i Me WI p Zouk gni Addend je NC EY AE 4 8 8 900 0303 9 5 0 102 0 254 3 3 4 3 0 084 0 109 251 259 6 376 6 5
17. COSMAC instruction summary is given in Table I Hexadecimal notation is used to refer to the 4 bit binary codes Many of the instructions have been discussed in the Archi tecture section Symbols used are R W Register designated by W where W or X or P R W 0 Lower order byte of R W R W 1 Higher order byte of R W Register Operations Code Note 1 4d Assembler Mnemonic Note 2 I Name 2 e n cuofcerio Roo o n PLO rmo en N 0 1 2 poe 9 A B E F Hexadecima Notation Memory Reference M R N gt D R N 1 5 STR STORE D M RIN GE ao jF 1t oR JOR MRX vD gt D F a ADDIADD __M R X D gt D C gt DF MN C RIGHT LSB DF O MSB F s cor LOAD ww MRP PDRP Flo minena F JEXCL OR M R P G D gt D IMM R P 1 FiC ADD IMM M R P D gt D C gt DF R P 1 F SDI SUBT D IMM M R P D gt D C gt DF R P 1 FIF SUBT M IMM ID M R P D C gt DF R P 1 These are the only operations that modify DF DF is set or reset by an ALU carry during add or subtract Subtraction is by 2 s complement 1 1 aoe Operation Notation M R N gt DsR N 1 This notation means The memory byte pointed to by R N is loaded into D and R N is incremented by 1 Sl
18. RCA Microprocessor Products RCA LSI Microprocessor The RCA Microprocessor COSMAC is a COS MOS 8 bit register oriented central processing unit designed for use as a general purpose com puting element COSMAC is implemented as two LSI devices one in a 40 pin package and the other in a 28 pin package COSMAC is ideally suited for a wide variety of commercial industrial and government appli cations The architecture has been designed with a total microcomputer system in mind so that systems with maximum flexibility and minimum cost can be realized The CMOS technology used in COSMAC provides a high noise immunity so that the processor can operate in electrically hostile environments The processor can be powered by unregulated power supplies over a wide operating voltage range It has a separate internal voltage supply so that it can operate at maximum speed while interfacing to various external circuit technologies including TTL Only a single phase system clock is required and the processor power consumption is very low Furthermore COSMAC is completely static so that its system clock can be controlled to inter face with very slow memories or 1 0 devices It is capable of operating over the full 55 C to 125 C temperature range COSMAC provides a set of simple easy to use general purpose instructions One can learn to design programs for COSMAC based products with minimum effort Unlimited subroutine nesting is
19. S MOS chips The RCA CDP1801U and CDP1801CU in a 40 lead dual in line ceramic package each contain the arithmetic logic unit ALU control logic and various working registers The RCA CDP 1801R and CDP1801CR in a 28 lead dual in line ceramic package each contain the multi purpose 16 x 16 register array a buffer register associated controls and an incre ment decrement circuit associated with the register array COSMAC is a static system therefore the clock input frequency can be chosen to interface with memories or 1 0 devices having speeds that vary over a wide range Also the input clock may be stopped indef initely without loss of information MEMORY ADDRESS LINES I O FLAGS I O REQUESTS m 235 0 CDP1801 CDP1801C Architecture The COSMAC block diagram is shown in Fig 15 The principal feature of this system is a register array R consisting of sixteen 16 bit scratchpad registers Individual regis ters in the array R are designated selected by a 4 bit binary code from one of the 4 bit registers labeled N P and X The contents of any register can be directed to any one of the following three paths 1 the external memory multiplexed higher order byte first on to 8 mem ory address lines 2 the D register either of the two bytes can be gated to D 3 the increment decrement circuit where it is increased or decreased by one and stored back in the selected 16 bit reg ister
20. The designer thus has complete control over the object program generated but with maximum convenience and readability Using the RCA assembler offers the following advantages 1 Fewer mistakes because mnemonics are provided for each instruction and because writing within a simple syntax reduces errors 2 Easy program revision because memory locations and register names are designer assigned mnemonics which do not change when new instructions are inserted or old ones deleted 3 Easy understandability both by the designer and later by others because of the mne monics used and because of the opportunity to add documentation comments at will The assembler will ignore these comments in the process of assembling the source program The RCA assembly program provides two levels of sophistication At the first level each instruction is referred to by name and each statement defines a single instruction The mnemonics of this level are similar to other conventional assemblers and are the easiest for programming novices to learn The second level of the language provides a variety of shorthand symbolics some Fortran like features and greater flexibility The assembler is written in standard Fortran IV to make it easy to install on a variety of computers THE SIMULATOR DEBUGGER The COSMAC simulator debugger enables the designer to check out his program on timesharing systems using a variety of powerful debugg
21. URRENT 92 5 27019 Fig 6 Minimum output P channel drain characteristics lt 2 Z C MAXIMUM DISSIPATI PER OUTPUT DEVICE 100 mw n CHANNEL DRAIN CU 5 0 15 DRAIN TO SOURCE VOLTAGE Vps V 92 5 27021 Fig 8 Minimum output N channel drain characteristics CDP1801 CDP1801C DRAIN TO SOURCE VOLTAGE Vps V 5 15 10 44l 1 n TAGE CET uy Eum Joes EUS p CHANNEL DRAIN CURRENT 92 5 27018 Fig 5 Typical output P channel drain characteristics MH H m B ied i ATTAN n CHANNEL DRAIN CURRENT IpN mA J MAXIMUM DISSIPATION PER OUTPUT DEVICE 00 mW DRAIN TO 10 15 SOURCE VOLTAGE Vpg V 92CS 27020 Fig 7 Typical output N channel drain characteristics f E z r o z gt a LOW 0 2 nu dun HHH E ui ebbe a ip MM ai H 41 t they LM Zu Me peu H ry M pona H i _ um nr CS LOAD CL pF
22. Y ACCESS qINTERNAL vars 18161710 23 4 567 lol 2 5 4 T5Te ly Toi e s T4 T5Te 7 To fais INPUT INSTRUCTION TIMING STATE N lt 50 gt sis I 6 1XXX 50 OR 52 OR 53 n Bus H4 0FF BYTE MESE eee MWR QUTPUT INSTRUCTION TIMING STATE N 5 50 seise oxxx 0 oR 52 06 53 NO N3 NND 11 22 BUS 2 31 6 BYTE OUT 92CL 2642IRI NOTES I MINIMUM DETERMINED BY Vpp NO MAXIMUM SIGNAL GENERATED BY USER 2 MEMORY WRITE PULSE WIDTH MWR amp 1 5 T INTERNAL TO COSMAC 3 MEMORY OUTPUT OFF INDICATES HIGH IMPEDANCE CONDITION 4 SHADING INDICATES DON T CARE OR INTERNAL DELAYS DEPENDING ON Vpp AND THE CLOCK SPEED Fig 3 CDP1801 and CDP1801C Microprocessor timing diagram File No 900 EMORY SYSTEM ACCESS TIME taccess 745 _ o 4 12 INSTRUCTION 4 2 1 33 0 8 CLOCK INPUT FREQUENCY fer MHz HINSTRUCTION TIME 16 teycLe 13 5 teycLE pMo t su tacces 0 67 92CS 27017 Fig 4 Typical instruction time vs memory system access time DRAIN TO SOURCE VOLTAGE Vps V 5 10 AMBIENT TEMPERATURE 25 C GATE TO SOURCE VOLTAGE 65 5 in 1 H LI N CHANNEL DRAIN C
23. ash mark in Operations Column indicates else or otherwise Table I Instruction Summary Branching 310 UNCOND BR WRPPAPLO 312187 BR IF 0 00 M R P gt R P 0 IF D 00 R P 1 3 3 DF 1 M R P gt R P 0 IF DF 1 R P 1 3 1 1 1 0 IF EF1 1 R P 1 315 2 BR IF EF2 1 M R P gt R P 0 IF EF2 1 R P 1 3 BR IF EF3 1 M R P R P O IF EF3 1 R P 1 3 7 BR IF EF4 1 M R P gt R P 0 IF EF4 1 R P 1 G s se sue Reet 1 2 BR IF 0500 LT M IF D4 00 R P 1 BNF BR IF 0 M R P R P 0 IF DF 0 R P 1 3 C BN1 BR IF EF1 0 gt 0 IF EF 1 0 R P 1 BN2 BR IF EF2 0 M R P gt R P 0 IF amp 2 0 1 BR IF EF3 0 gt 0 IF EF3 0 R P 1 3 BR IF EF4 0 M R P gt R P 0 IF EF4 0 R P 1 Control IDL IDLE DMA IN DMA OUT ser seTP nee PEIN SEX SETX Nx WAIT FOR INTERRUPT 7 RET RETURN M R X X P R X 41 1 IE 7 DIS DISABLE M R X X P 1 0 1 r s ssv save The use of non specified machine codes is not recommended NEUE File No 900 Input Output Byte Transfer M R X gt BUS R X 21 N 1 Note 3 Signal CLEAR CLOCK MAO to MA7 8 Memory Address Lines MWR Write Pulse M READ Read Level gy OUT 1 OUTPUT 1 OUT 2 OUTPUT 2 M R X gt BUS R X 1
24. atically deactivated to inhibit further interruptions The interrupt routine is now in control the contents of T CDP1801 CDP1801C are saved by means of a single instruction 78 in the memory location pointed to by R X where X 2 At the conclusion of the inter rupt the routine restores the pre inter rupted values of X and P with a single in struction The interrupt enable flip flop can be activated to permit further interrupts or can be disabled to prevent them COSMAC Register Summary N 4 Bits Holds Low order Instr Digit I 4 Bits Holds High order Instr Digit D Data Register Accumulator IDF 1Bit Data Flag ALU Carry R 16 Bits 1 of 16 Scratchpad Registers 4 Bits Designates which register is Program Counter 1Bit T 8 Bits Holds old X P after Inter rupt X is high byte Interrupt Enable X 4 Bits Designates which register is Data Pointer Interrupt Action X and P are stored in T after executing current instruction des ignator X is set to 2 designator P is set to 1 interrupt enable is reset to O inhibit and instruction execution is resumed DMA Action Finish executing current in struction R O points to memory area for data transfer data is loaded into or read out of memory and increment R O Note In the event of concurrent DMA and INTERRUPT requests DMA has priority 10 CDP1801 CDP1801C File No 900 Instruction Set The
25. e 1 0 interface lines The latter include Direct Memory Access and inter rupt inputs external flag inputs command lines processor state indicators external timing pulses etc This manual also gives a description of machine code programming methods Detailed examples are provided Potential programming errors are dis cussed Programming techniques regarding inter rupt response long branch subroutine linkage and nesting and various programming techniques are also described This basic manual is intended to help the design engineer understand the COSMAC Microprocessor and aid him in developing simpler and more powerful products based on Microprocessors Microprocessor Products User Manual for the COSMAC Microprocessor 2M1122D Printed in U S A 3 75 RCA Microprocessor Products Program Development Guide For The COSMAC Microprocessor MPM 102 The Program Development Guide is a comprehen sive manual to be used with the COSMAC Software Development Package for designing application programs First it reviews the architecture of the COSMAC Microprocessor so that program designers can become familiar with its register set and instruction repertoire and with other functions such as reset load start DMA and interrupt The manual then describes the COSMAC Software Development Package CSDP CSDP is an inter active program which is available via nationwide timesharing services or can be installed on a custome
26. e Microkit is shown in Fig 2 Each block represents one card A photograph of the Microkit is shown in Fig 1 Registered trademark of Teletype Corporation Registered trademark of Computer Transceiver Systems Inc Fig 1 COSMAC Microkit 2M1122C Printed in U S A 3 75 CONTROL SWITCHES RAM ROM SELECT 3 CLOCK 8 CONTROL j fL 1 0 COMMAND ADDRS MEM ADDRS STATE CODE LATCH EN NERES p mae HEN OMA REQ INTR REQ m USER ADDED MEMORY 8 BU USER VICES FROM MEM fo Sr LH 5 J LATCH 8 BIT 8 BITS Fig 2 Microkit Block Diagram RCA Microprocessor Products User Manual For The COSMAC Microprocessor MPM 101 The RCA Microprocessor Manual provides a de tailed guide to the COSMAC Microprocessor It is written for the electrical engineer with no as sumptions of familiarity with computers It de scribes the microprocessor architecture and its set of simple easy to use instructions Examples are given to illustrate the operation of each instruction For system designers this manual illustrates practi cal methods of adding external memory and con trol circuits Since the processor is capable of supporting Input Output 1 0 devices in polled interrupt driven and Direct Memory Access modes detailed examples are provided for the 1 0 in structions and the use of th
27. gram must routinely test the status of these flag s The flag s are set at the end of every SO cycle These requests were discussed in the Architecture section They are sampled by COSMAC in the interval between the leading edge of TPB and the leading edge of TPA The DMA request has a higher priority than the INTERRUPT request These three lines indicate to the I O controllers that the CPU is 1 processing a DMA request 2 acknowledging an interrupt request 3 fetching an instruction 4 executing an I O instruction or 5 all other instruction executions The levels of state code are tabulated below State Code Lines State Type SC1 SCC S2 DMA S3 Interrupt H 1 SO Fetch 61 1 6 I O Instruction Execute S1 I2 6 All other instructions H H All these states last one machine cycle They may be assumed valid at L Vss Negative pulses that occur once in each machine cycle TPB follows TPA They are used by I O controllers to interpret codes and to time interaction with the data bus The trailing edge of TPA is used by the memory system to latch the higher order byte of the 16 bit memory address A low level that holds the CPU in IDLE mode and allows an I O device to load the memory without the need for a bootstrap loader It modifies the IDLE condition so that DMA operation does not force execution of the next in struction The internal voltage supply Vpp is isolated from
28. imum lead thickness narrow portion will not exceed 0 013 in 0 33 mm suffix letter to the type number follows Control Unit CDP1801U CDP1801CU Register Unit CDP1801R CDP1801CR When ordering a chip add the suffix letter H to the specific type number as follows Control Unit Chip CDP1801UH Register Unit Chip CDP1801RH When incorporating RCA Solid State Devices in equipment it is recommended that the designer refer to Operating Considerations for RCA Solid State Devices Form No 1CE 402 available on request from RCA Solid State Division Box 3200 Somerville N J 08876 RCA Microprocessor Products COSMAC Software Development Package THE ASSEMBLER The RCA symbolic assembly program assembler is a computer program that assists the designer in preparation of machine code programs for the RCA COSMAC microprocessor The assembler allows the system designer to write his program source program in easy to remember symbolics The assembler converts these English like mne monics into machine langauge binary words object program It also does the tedious book keeping keeping track of cross references within the pro gram and facilitates the combining of subprograms to form larger programs The assembler operates one for one basis in that each phrase of a statement in the source program translates directly into a specific machine language byte in the object program
29. ing tools Fig 1 shows the inter relationship of the assembler and simulator debugger in the RCA software support system SIMULATED COSMAC SYSTEM Fig 1 RCA Software Support System To use the support system the program designer works at a terminal to prepare his source program using the editor and then calls on the assembler to assemble the program After assembly the pre pared code is entered into the memory of the simulated COSMAC system During simulation the user Can stop the program at specified points or by specified events He can ask for the contents of registers and memory locations using his original assembly mnemonics and change the values at will He can ask for traces blow by blow descriptions of program execution He can ask the simulator to monitor specified locations and stop when they are read written to or executed from At any time he can store away the entire state of the simulated machine for later retrieval a par ticularly useful tool during debugging sessions or to avoid the cost of reassembly When satisfied the user loads the program directly into his micro processor hardware through his terminal which acts as an input device to the microprocessor Final verification of the program can now be done in real time on the Microprocessor Hardware Support Kit COSMAC Microkit Over 2M1122B Printed in U S A 3 75 SOFTWARE SUPPORT SYSTEM AVAILABILITY The software support
30. l entity so that systems having maximum flexibility and minimum cost can RCA CDP1801 CDP1801C Microprocessor COSMAC CDP1801U CDP1801CU Microprocessor Control CDP1801R CDP1801CR Microprocessor Register IC M Static COS MOS circuitry no minimum clock frequency Full military temperature range High noise immunity wide operating voltage range TTL compatibility 8 bit parallel organization with bidirectional data bus Built in program load facility Any combination of standard RAM ROM via common interface Memory addressing up to 65 536 bytes Flexible programmed I O mode Program interrupt mode On chip DMA facility Four flag inputs directly testable by Branch instructions One byte instruction format with two machine cycles for each instruction 57 easy to use instructions 16 x 16 matrix of registers for use as multiple File Number 900 program counters data pointers or data registers be realized The COSMAC CPU also provides a synchronous interface to memories and ex ternal controllers for 1 devices and mini mizes the cost of interface controllers Fur thermore the I O interface is capable of sup porting devices operating in polled interrupt driven or direct memory access modes CDP1801U CDP1801CU control units are supplied in a 40 lead hermetic ce ramic dual in line package D suffix and in chip form H suffix The CDP1801R and CDP1801CR register units are supplied in a
31. monly required functions program loading memory dump modification of memory locations paper tape punch saving of registers and start of program execution at a given location The Microkit has been designed to allow the user to add memory cards and device electronics for configuring the system to his particular require ments A total of nine spare memory PC card positions are prebussed for memory expansion and a total of fourteen spare 1 0 PC card positions one prewired are made available for user device control electronics Small 44 pin PC cards 4 5 x 3 are used in the basic Microkit card set for modularity and flexibility in building new systems Larger cards up to 4 5 x 6 5 can be used in the enclosure if desired The power supply is capable of providing up to 2 amperes at 5 volts for additional cards Users may write and debug programs with the aid of software packages available on timesharing systems The object code for a program may be automatically loaded into the Microkit RAM for further debugging The Microkit is designed for easy reconfigurability and hardware extension as well as for easy inter action with a timesharing system in software development The Microkit is provided with a detailed manual which carefully describes the hardware and the Utility Program and discusses generally the pro blems of designing a Microprocessor based system Numerous examples are provided A block diagram of th
32. n the COSMAC architecture saves a substantial amount of logic when fast exchanges of blocks of data are required such as with magnetic discs or during CRT display refresh cycles A program load facility using this DMA channel is provided to enable users to load programs into the memory This facility pro vides a simple one step means for initially entering programs into the microprocessor system and eliminates the requirement for specialized bootstrap ROM s Data Registers When registers in R are used to store bytes of data four instructions are provided which allow D to receive from or write into either the higher order or lower order byte por tions of the register designated by N By this mechanism together with loading by data immediate program pointer and data pointer designations are initiated Also this technique allows scratchpad registers in R to be used to hold general data Interrupt Servicing Register R 1 is always used as the program counter whenever interrupt servicing is ini tiated When an interrupt request comes in and the interrupt is allowed by the designer File No 900 Interrupt Servicing Cont d again nothing takes place until the end of the current execute machine cycle of the instruction is completed the contents of the X and P registers are stored in the temporary register and X and P are set to new values hex digit 2 in X and hex digit 1 in P Inter rupt enable is autom
33. nk IpN 0 4 5 1 6 3 2 1 6 32 See Figs 7 8 3 99 Channel Source 25 5 0 8 cubo 0 8 16 1 See Figs 5 6 95 10 9495 509 e Any Input HL See Figs 13 14 ee ee ee Dynamic at 25 C Input t t 20 ns C 50 pF Propagation Delay Times TL RO Clock to TPA tPAHL 5 685 685 ns ee 8 p 5 720 720 ee ee Clock to TPB Ded apo 490 LEE X eee VO se 5 650 650 fs elm MAS to MA15 5 n UNE EO SEO NN SN MAO to MA7 SS Values are for signal lines going to external connections File No 900 CDP1801 CDP1801C ELECTRICAL CHARACTERISTICS at TA 25 C CONT D CONDITIONS CDP1801U CDP1801CU CDP1801R CDP1801CR CHARACTERISTIC Vo Vpp LIMITS LIMITS V V Min Typ Dynamic at TA 25 C Input t t 20 ns 50 pF Data Setup Time See Fig 2 Clock to Memory Write Time See Fig 2 Device Dissipation Total Both Units Pp OP CODE 00 Transition Time See Figs 9 10 Input Capacitance Values for signal lines going to external connections SUHL I SULH t
34. quire special handling considerations as follows 1 Chips must be stored under proper con ditions to insure that they are not sub jected to a moist and or contaminated atmosphere that could alter their elec trical physical or mechanical charac teristics After the shipping container is opened the chip must be stored under the following conditions A Storage temperature 40 C max B Relative humidity 50 max C Clean dust free environment 2 The user must exercise proper care when handling chips to prevent even the slightest physical damage to the chip 3 During mounting and lead bonding of chips the user must use proper assembly techniques to obtain proper electrical thermal and mechanical performance 4 After the chip has been mounted and bonded any necessary procedure must be followed by the user to insure that these non hermetic chips are not subjected to moist or contaminated atmosphere which might cause the development of electrical conductive paths across the relatively small insulating surfaces In addition proper consideration must be given to the protection of these devices from other harmful environments which could conceivably adversely affect their proper performance These unmounted and unencapsulated chips are tested electrically and visually inspected to meet RCA s specifications when they shipped by RCA Written notification of non conformance to such specifications must be made to R
35. r s own interactive computer system The COSMAC assembly language provides the programmer with a means of writing and modifying programs using convenient mnemonics It has been designed to provide the designer with com plete control over the object program generated but with maximum convenience and readability The format is free form no column lineup is needed Blanks can be used at will to improve readability Comments can be inserted on any line The program is self documenting and multiple instructions per line are permitted At the first level Level each instruction is referred to by name and each statement defines a single instruction The mnemonics of this level are similar to those of other conventional assem blers and are the easiest for programming novices to learn The second level Level 11 provides a variety of shorthand symbolics some Fortran like features and greater flexibility It allows additional mnemonics for some instructions a wider use of symbolic names than Level the use of expressions to specify locations and values etc Level 11 is thus a higher level assembly language Several useful programming techniques common programming bugs and sample programs are discussed Program Development Guide for the COSMAC Microprocessor 2M1122E Printed in U S A 3 75
36. ry low on this line places COSMAC in a repeating IDLE cycle with P 0 R O 0000 and IE 1 interrupt request allowed Single phase clock A typical clock frequency is 2 MHz at Vpp 10 V The clock is counted down internally to 8 clock pulses per machine cycle The most significant 8 bits of the memory address is multiplexed out first on these lines and held in a latch in the memory system that is set by TPA The 8 least significant bits are then multi plexed out on the same lines The memory system always sees a 16 bit address within one memory addressing cycle A positive pulse appearing in a memory write cycle after the address lines have settled down low level READ indicates a memory read cycle It can be used to control three state outputs from the addressed memory which may have a common data input and output bus If amemory does not have a three state high impedance output READ is useful for driving memory bus separator gates A repeating IDLE cycle represents an instruction halt The processor will remain in this halt state until an I O Request INTERRUPT DMA IN or DMA OUT is activated When this request occurs the IDLE cycle is terminated and the I O request is serviced and then the nor mal program is resumed DMA request is used to bring the processor out of IDLE it will increment the contents of R O by 1 The first instruction will therefore be fetched from memory location 0001 and not 00
37. system is available in two forms It has been installed on the General Electric Information Services International Network for use by timesharing customers is also available from RCA as a Fortran IV tape for installation any appropriate interactive computer In this case it is supplied as a 9 track 800 bpi IBM compatible tape with a detailed installation manual RCA Microprocessor Products RCA Microprocessor Hardware Support Kit The RCA Microprocessor Hardware Support Kit COSMAC Microkit is a prototyping system for the development of systems based on the RCA COSMAC Microprocessor A Teletype or a termi nal with a TTL bit serial interface can be attached to this system With such a terminal it is an elementary but complete computer system The user is expected to provide something additional to achieve his goals software 1 0 device troller and perhaps additional memory In the basic configuration the Microkit provides the following 1 19 rack mountable card nest with printed circuit backplane 2 Self contained power supply Front panel with basic controls 4 Eleven 4 5 x 3 0 44 pin PC cards CPU card Clock and Control Bus Separato 2 Address Latch Card 512 byte RAM Cards 2 512 byte PROM Card 1 0 Decoder Card Terminal Card for Teletype or Execuport etc Byte 1 0 Card The 512 byte PROM card contains the Utility Pro gram which performs com
38. umption single voltage option 4 12 Vdc operating range TTL compatibility high noise immunity single phase clock single pulse clear built in program load mode standard RAM ROM compatibility separate memory address lines OCT 30 1975 m direct memory addressing up to 65 536 bytes program interrupt mode 8 program controlled interrupt mask enable disable self contained DMA channel cycle stealing mode a flexible programmed 1 0 mode four 1 0 flag inputs directly testable by branch instructions separate 4 bit 1 0 control code m two 1 0 sync pulses one byte instruction format with two machine cycles for each instruction 59 easy to use instructions multiple program counters multiple data registers multiple address registers add subtract shift and logical operations immediate address mode indirect pointer address mode flexible subroutine nesting procedures branch and link capability same fetch and execute cycles for all instructions 2M1122A Printed in U S A 3 75 COSMAC ARCHITECTURE TIMING DMA CLOCK STATE MREAD M ADDRESS IN OUT CLEAR N BUS CODE MWRITE 0 7 INTERRUPT FLAGS LOAD 0 3 0 7 NNNNNNNNN hy me 2277 R SELECT 4 T 8 NNNNNNNNNS SCRATCH PAD REGISTERS SSS lt lt 22 72222222227222222222222222222 2 Fig 1 COSMAC Architecture SYSTEM BLOCK DIAGRAM TPA
Download Pdf Manuals
Related Search