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LPC1759/58/56/54/52/51

1. VDD Y R2 R2 T LPC17xx R1 USB_UP_LED 1 5 KQ R3 TI USB_VBUS USB D Rs 330 gt USB B gt gt connector USB D hsc990 gt Vss aaa 008962 Fig 29 USB interface on a bus powered device where Vgus 5 V Vpp not present Vpp 3v3 USB_UP_LED USB_CONNECT LPC17xx H SoftConnect switch 77 R1 1 5 KQ Vaus UsB p Ps 339 gt USB B connector UsB p Ps 339 Vss 002aad939 Fig 30 LPC1759 58 56 54 52 51 USB interface with soft connect LPC1759 58 56 54 52 51 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 65 of 80 NXP Semiconductors LPC1759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller RSTOUT RESET_N LPC1759 58 56 54 SCL1 2 ADR PSW ID OE_N INT_N 330 VDD SMALE LL Mini AB SPEED DM 330 connector SUSPEND ISP1302 t E Vss SDA1 2 EINTO USB_D USB D USB UP LED Fig 31 LPC1759 58 56 54 USB OTG port configuration 002aae155 TA USB UP LED _ 330 LPC1759 58 56 54 USB PWRD
2. Fem LPC1759 58 56 54 52 51 BUS 32 bit ARM Cortex M3 MCU up to 512 kB flash and 64 kB SRAM with Ethernet USB 2 0 Host Device OTG CAN Rev 8 6 18 August 2015 Product data sheet 1 General description The LPC1759 58 56 54 52 51 are ARM Cortex M3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption The ARM Cortex M3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration The LPC1758 56 57 54 52 51 operate at CPU frequencies of up to 100 MHz The LPC1759 operates at CPU frequencies of up to 120 MHz The ARM Cortex M3 CPU incorporates a 3 stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals The ARM Cortex M3 CPU also includes an internal prefetch unit that supports speculative branching The peripheral complement of the LPC1759 58 56 54 52 51 includes up to 512 kB of flash memory up to 64 kB of data memory Ethernet MAC USB Device Host OTG interface 8 channel general purpose DMA controller 4 UARTs 2 CAN channels 2 SSP controllers SPI interface 2 I C bus interfaces 2 input plus 2 output I2S bus interface 6 channel 12 bit ADC 10 bit DAC motor control PWM Quadrature Encoder interface 4 general purpose timers 6 output general purpose PWM ultra low power Real Time Clock RTC
3. iis source EOP width tFEOPT receiver EOP width teopri tEoPR2 002aab561 LPC1759 58 56 54 52 51 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 57 of 80 NXP Semiconductors LPC1759 58 56 54 52 51 12 9 SPI LPC1759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller Table 17 Dynamic characteristics of SPI pins Tamb 40 C to 85 C Symbol Parameter Min Typ Max Unit Tey PCLK PCLK cycle time 10 E B ns TsPicvc SPI cycle time I 79 6 T ns tspiciky SPICLK HIGH time 0 485xTspicvo ns tsPICLKL SPICLK LOW time 5 0 515 x Tspicye ns SPI master tsPIDSU SPI data set up time 2 o0 D S ns SPIDH SPI data hold time 2 2 x Tey PcLk 5 2 ns tspiav SPI data output valid time 2 2 x Teye 30 ns tsPIOH SPI output data hold time 2 2 x Tey PeLK 5 i p ns SPI slave tspipsu SPI data set up time Bl o F Hs tsPIDH SPI data hold time 2 2x Tey PCLK 5 2 2 ns tspiav SPI data output valid time 2 2 x Toypgi 35 ns tePIoH SPI output data hold time 2 2 x Teye 15 ns 1 Tspicyc ToyPcLi x n 0 5 n is the SPI clock divider value n gt 8 PCLK is derived from the processor clock CCLK 2 Timing parameters are measured with respect to the
4. standard warranty and NXP Semiconductors product specifications 21 4 Trademarks Notice All referenced brands product names service names and trademarks are the property of their respective owners I C bus logo is a trademark of NXP Semiconductors N V For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com LPC1759 58 56 54 52 51 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 78 of 80 NXP Semiconductors LPC1759 58 56 54 52 51 23 Contents 32 bit ARM Cortex M3 microcontroller oc BOND BE iL 8 12 3 1 8 13 1 8 14 8 14 1 8 15 8 15 1 8 16 8 16 1 8 17 8 17 1 8 18 LPC1759 58 56 54 52 51 General description ssess 1 Features and benefits 1 Applications eee 3 Ordering information esse 4 Ordering options lille esses 4 Marking cece eee eee RB 5 Block diagram 0 cs eee eee eee 6 Pinning information lesse 7 PINNING asset iP ene xu brise 7 Pin description 0 0 e ee eee 7 Functional description 14 Architectural overview luus 14 ARM Cortex MG processor 14 On chip flash program memory
5. General purpose digital input output pin 1 0 USB_D USB bidirectional D line PO 3O USB D 23 41 yo PO 30 General purpose digital input output pin 1 0 USB D USB bidirectional D line P1 0 to P1 31 y o Port 1 Port 1 is a 32 bit I O port with individual direction controls for each bit The operation of port 1 pins depends upon the pin function selected via the pin connect block Some port pins are not available on the LQFP80 package P1 0 76 VO P1 0 General purpose digital input output pin ENET TXDO O ENET TXD0 Ethernet transmit data 0 LPC1758 only P1 1 75H VO P1 1 General purpose digital input output pin ENET_TXD1 O ENET_TXD1 Ethernet transmit data 1 LPC1758 only P1 4 740 VO P1 4 General purpose digital input output pin ENET_TX_EN O ENET_TX_EN Ethernet transmit data enable LPC1758 only P1 8 73 VO P1 8 General purpose digital input output pin ENET_CRS ENET_CRS Ethernet carrier sense LPC1758 only P1 9 720 VO P1 9 General purpose digital input output pin ENET_RXDO l ENET RXDO Ethernet receive data LPC1758 only P1 10 710 VO P1 10 General purpose digital input output pin ENET_RXD1 l ENET_RXD1 Ethernet receive data LPC1758 only P1 14 7001 VO P1 14 General purpose digital input output pin ENET_RX_ER ENET_RX_ER Ethernet receive error LPC1758 only P1 15 69L VO P1 15 General purpose digital input outp
6. 2000 200eee 32 Sleep mode 00 cee eee eee 32 Deep sleep mode 2200 32 Power down mode 22 5 33 Deep power down mode 33 Wakeup interrupt controller 33 Peripheral power control 33 Power domains 200 055 33 System control 00020e eee 35 BL DE PEORES TUERI eee 35 Brownout detection 36 Code security Code Read Protection CRP 36 APB interface 20000055 36 AHB multilayer matrix lusu 37 External interrupt inputs 37 Memory mapping control 37 Emulation and debugging 37 Limiting values eee eee 38 Thermal characteristics 39 continued gt gt NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 79 of 80 NXP Semiconductors LPC1759 58 56 54 52 51 10 1 11 11 1 11 2 11 3 12 12 1 12 2 12 3 12 4 12 5 12 6 12 7 12 8 12 9 13 14 15 15 1 15 2 15 3 15 4 15 5 15 6 16 17 18 19 20 21 21 1 21 2 21 3 21 4 22 23 Thermal characteristics 39 Static characteristics 40 Power consumption 43 Peripheral power consumption 46 Electrical pin characteristics 47 Dynamic characteristics 49 Flash memory 0
7. Acronym Description ADC Analog to Digital Converter AHB Advanced High performance Bus AMBA Advanced Microcontroller Bus Architecture APB Advanced Peripheral Bus BOD BrownOut Detection CAN Controller Area Network DAC Digital to Analog Converter DMA Direct Memory Access EOP End Of Packet GPIO General Purpose Input Output IRC Internal RC IrDA Infrared Data Association JTAG Joint Test Action Group MAC Media Access Control MIIM Media Independent Interface Management OTG On The Go PHY Physical Layer PLL Phase Locked Loop PWM Pulse Width Modulator RMII Reduced Media Independent Interface SEO Single Ended Zero SPI Serial Peripheral Interface SSI Serial Synchronous Interface SSP Synchronous Serial Port TTL Transistor Transistor Logic UART Universal Asynchronous Receiver Transmitter USB Universal Serial Bus 19 References LPC1759 58 56 54 52 51 1 LPC176x 5x User manual UM10360 http www nxp com documents user manual UM10360 pdf 2 LPC175x Errata sheet http www nxp com documents errata sheet ES LPC175X pdf 3 Technical note ADC design guidelines http www nxp com documents technical note TN00009 pdf All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 74 of 80 NXP Semiconductors LPC1759 58 56 54 52 51 20 Revision histo
8. Data Carrier Detect input for UART1 I O MOSIO Master Out Slave In for SSPO 1 0 MOSI Master Out Slave In for SPI LPC1759_58_56_54_52_51 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 8 of 80 NXP Semiconductors LPC1 759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller Table 4 Pin description continued Symbol Pin Type Description PO 22 RTS1 TD1 4401 yo P0 22 General purpose digital input output pin O RTS1 Request to Send output for UART1 Can also be configured to be an RS 485 EIA 485 output enable signal O TD1 CAN 1 transmitter output PO 25 ADO 2 7A y o P0 25 General purpose digital input output pin pde SDA l ADO 2 A D converter 0 input 2 VO I2SRX_SDA Receive data It is driven by the transmitter and read by the receiver Corresponds to the signal SD in the S bus specification LPC1759 58 56 only O TXD3 Transmitter output for UART3 PO 26 ADO 3 ei3l yo PO 26 General purpose digital input output pin AOUT RXD3 ADO 3 A D converter 0 input 3 O AOUT DAC output LPC1759 58 56 54 only l RXD3 Receiver input for UART3 PO 29 USB D 2214 y o P0 29
9. This corresponds to a square wave signal with a signal swing of between 280 mV and 1 4 V The XTALOUT pin in this configuration can be left unconnected External components and models used in oscillation mode are shown in Figure 35 and in Table 22 and Table 23 Since the feedback resistance is integrated on chip only a crystal and the capacitances Cy and Cx need to be connected externally in case of fundamental mode oscillation the fundamental frequency is represented by L C and Rs Capacitance Cp in Figure 35 represents the parallel package capacitance and should not be larger than 7 pF Parameters Fosc Ci Rs and Cp are supplied by the crystal manufacturer All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 67 of 80 NXP Semiconductors LPC1 759 58 56 54 52 51 15 3 LPC1759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller LPC1xxx T XTALIN XTALOUT CL CP XTAL ii Rs cx Cx2 ES C NK 002aa 424 Fig 35 Oscillator modes and models oscillation mode of operation and external crystal model used for Cy1 Cy evaluation Table 22 Recommended values for Cy4 Cyz in oscillation mode crystal and external components parameters low frequency mode Fundamental oscillation Crystal load Maximum c
10. with separate battery supply and up to 52 general purpose I O pins For additional documentation see Section 19 References 2 Features and benefits B ARM Cortex M3 processor running at frequencies of up to 100 MHz LPC1758 56 57 54 52 51 or of up to 120 MHz LPC1759 A Memory Protection Unit MPU supporting eight regions is included B ARM Cortex M3 built in Nested Vectored Interrupt Controller NVIC W Upto 512 kB on chip flash programming memory Enhanced flash memory accelerator enables high speed 120 MHz operation with zero wait states E In System Programming ISP and In Application Programming IAP via on chip bootloader software E On chip SRAM includes Up to 32 kB of SRAM on the CPU with local code data bus for high performance CPU access Two one 16 kB SRAM blocks with separate access paths for higher throughput These SRAM blocks may be used for Ethernet LPC1758 only USB and DMA memory as well as for general purpose CPU instruction and data storage NXP Semiconductors LPC1 759 58 56 54 52 51 LPC1759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller Eight channel General Purpose DMA controller GPDMA on the AHB multilayer matrix that can be used with the SSP I S bus UART the Analog to Digital and Digital to Analog converter peripherals timer match signals and for memory to memory transfers Multilayer AHB matrix interconnect provides a separate bus for each AHB master A
11. 3 Vppa and VREFP should be tied to Vpp ava if the ADC and DAC are not used 4 Vppa for DAC specs are from 2 7 V to 3 6 V 5 The RTC typically fails when Vitygar drops below 1 6 V 6 Vpp REGy 3va 9 3 V Tamb 25 C for all power consumption measurements 7 Applies to LPC1758 LPC1756 LPC1754 LPC1752 LPC1751 8 Applies to LPC1759 only 9 IRC running at 4 MHz main oscillator and PLL disabled PCLK CCK 10 BOD disabled 11 On pin Vpp nEG av3 lar 530 nA Vpp ReG ava 3 0 V Vear 3 0 V Tam 25 C 12 On pin VBAT Ipp aeG va 630 nA Vpptmayava 3 0 V Vear 3 0 V Tamb 25 C 13 On pin VBAT Vat 3 0 V Tamb 25 C 14 All internal pull ups disabled All pins configured as output and driven LOW Vpp ava 3 3 V Tamb 25 C LPC1759 58 56 54 52 51 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 42 of 80 NXP Semiconductors LPC1 759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller 15 TCK SWDCLK pin needs to be externally pulled LOW 16 Vppa 3 3 V Tamb 25 C 17 The ADC is powered if the PDN bit in the ADOCR register is set to 1 See LPC 17xx user manual UM10360 18 The ADC is in Power down mode if the PDN bit in the ADOCR register is set to 0 See LPC 17xx user manual UM10360 19 Vivngrp 3 3 V Tamb 25 C 20 Includin
12. All rights reserved Product data sheet Rev 8 6 18 August 2015 61 of 80 NXP Semiconductors LPC1759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller 4095 offset error Eo gain error Eg 4094 4093 4092 4091 4090 Af code out 1LSB ideal Lu l l A 1 2 3 4 5 6 7 Via LSBideal offset error Eo Example of an actual transfer curve 1 2 The ideal transfer curve 3 Differential linearity error Ep 4 Integral non linearity Ei agj 5 Center of a step of the actual transfer curve Fig 26 12 bit ADC characteristics 4090 4091 4092 4093 4094 4095 4096 VREFP VREFN 1 LSB _____ 4096 002aad948 LPC1759 58 56 54 52 51 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 62 of 80 NXP Semiconductors LPC1759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller Fig 27 ADC interface to pins ADO n LPC17xx C3 Ri2 1000 6000 2 2 pF P ADO n COMPARATOR AI cz Le I C2 Cia Rvsi Vss VEXT H7 002aaf197 The values of resistor components Rj and Ri vary with temperature and input voltage and are process dependent see Table 20 Parasitic resistance and capacitance from the pad a
13. Type number Package Name Description Version LPC1759FBD80 LQFP80 plastic low profile quad package 80 leads body 12 x 12 x 1 4 mm SOT315 1 LPC1758FBD80 LQFP80 plastic low profile quad package 80 leads body 12 x 12 x 1 4 mm SOT315 1 LPC1756FBD80 LQFP80 plastic low profile quad package 80 leads body 12 x 12 x 1 4mm SOT315 1 LPC1754FBD80 LQFP80 plastic low profile quad package 80 leads body 12 x 12 x 1 4mm SOT315 1 LPC1752FBD80 LQFP80 plastic low profile quad package 80 leads body 12 x 12 x 1 4mm SOT315 1 LPC1751FBD80 LQFP80 plastic low profile quad package 80 leads body 12 x 12 x 1 4mm SOT315 1 4 1 Ordering options Table2 Ordering options SRAM in kB e 3 55 NEE 5E SE 2 8 3 4 se g BE gt alala Sla z2 o o EEF 2 ag E jaz ej s of 8565 2882 LPC1759FBD80 LPC1759FBD80 551 512 32 16 16 64 no Device Host OTG 2 yes yes 52 120 LPC1758FBD80 LPC1758FBD80Y 512 32 16 16 64 yes Device Host OTG 2 yes yes 52 100 LPC1756FBD80 LPC1756FBD80 CP327 256 16 16 32 no Device Host OTG 2 yes yes 52 100 LPC1754FBD80 LPC1754FBD80 551 128 16 16 32 no Device Host OTG 1 no yes 52 100 LPC1752FBD80 LPC1752FBD80 551 64 16 16 no Device only 1 no no 52 100 LPC1751FBD80 LPC1751FBD80 551 32 8 8 no Device only 1 ino no 52 100 LPC1759_58_56_54_52_51 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Rev 8 6 18 August 2015 4 of 80 Product data shee
14. 14 On chip SRAM 0 0 00 eee eee 14 Memory Protection Unit MPU 15 Memory Map 00 eee eee eee 15 Nested Vectored Interrupt Controller NVIC 17 Features 00000 17 Interrupt SourceS 200 0055 17 Pin connect block 5 17 General purpose DMA controller 17 Features c ce Era eec en 18 Fast general purpose parallel O 18 Features sse eek Rea REL rhe 19 Ethernet LPC1758 only 19 Feat les eee een aia cee 19 USB interface 200000 eee 20 USB device controller 20 Eeat res coo hae ke See bee 20 USB host controller LPC 1759 58 56 54 only 21 Eeat res 222 hee ERR RR eL 21 USB OTG controller LPC1759 58 56 54 only 21 Features ananunua eee eee 21 CAN controller and acceptance filters 21 F atureS silla gal UR es 22 Te3bIt ADG sse nenne oen ENR p ens 22 Feat les es ioi bu Rer ERR DG P 22 10 bit DAC LPC1759 58 56 54 only 22 Features issscuncu e y ess dau v 22 VARTS 5 tonc REESE dle ane etn 23 Feat l6S 52 2 vae ib ob donee 4 bed 23 SPI serial I O controller 23 Feat l6s 52 s Bo ao te dew y dave 23 SSP serial I O controller 23 8 18 1 8 19 8 19 1 8 20 8 20 1 8 21 8 21 1 8 22 8 22 1 8 23 8 24 8 24 1 8 25 8 25 1 8 26 8 27 8 27 1 8 28 8 28 1 8 29 8 29 1 8 29 1 1 8 29 1 2 8 29 1 3 8 29 2 8 29 3 8
15. 54 52 51 v 8 3 20140108 Product data sheet LPC1759 58 56 54 52 51 v 82 Modifications Table 6 Thermal resistance 15 96 Added 15 96 to table title LPC1759 58 56 54 52 51v 82 20131018 Product data sheet LPC1759 58 56 54 52 51 v 8 1 Modifications Table 5 Limiting values Removed condition 5 V tolerant open drain pins from Vi Table 7 Static characteristics Added Table note 3 VDDA and VREFP should be tied to VDD 3V3 if the ADC and DAC are not used Added Table note 4 VDDA for DAC specs are from 2 7 V to 3 6 V Vppa VREFP spec changed from 2 7 V to 2 5 V Table 18 ADC characteristics full resolution Added Table note 1 VDDA and VREFP should be tied to VDD 3V3 if the ADC and DAC are not used Vppa changed from 2 7 V to 2 5 V Table 19 ADC characteristics lower resolution Added Table note 1 VDDA and VREFP should be tied to VDD 3V3 if the ADC and DAC are not used LPC1759 58 56 54 52 51 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 75 of 80 NXP Semiconductors LPC1759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller Table 26 Revision history continued Document ID Release date Data sheet status Change Supersedes notice LPC1759 58 56 54 52 51 v 8 1
16. D code bus see Figure 1 The l code and D code core buses are faster than the system bus and are used similarly to Tightly Coupled Memory TCM interfaces one bus dedicated for instruction fetch I code and one bus for data access D code The use of two core buses allows for simultaneous operations if concurrent operations target different devices The LPC1759 58 56 54 52 51 use a multi layer AHB matrix to connect the ARM Cortex M3 buses and other bus masters to peripherals in a flexible manner that optimizes performance by allowing peripherals that are on different slaves ports of the matrix to be accessed simultaneously by different bus masters ARM Cortex M3 processor The ARM Cortex MG is a general purpose 32 bit microprocessor which offers high performance and very low power consumption The ARM Cortex M3 offers many new features including a Thumb 2 instruction set low interrupt latency hardware division hardware single cycle multiply interruptable continuable multiple load and store instructions automatic state save and restore for interrupts tightly integrated interrupt controller with wakeup interrupt controller and multiple core buses capable of simultaneous accesses Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously Typically while one instruction is being executed its successor is being decoded and a third instruction is being fetched from memory The AR
17. Product data sheet Rev 8 6 18 August 2015 77 of 80 NXP Semiconductors LPC1759 58 56 54 52 51 Export control This document as well as the item s described herein may be subject to export control regulations Export might require a prior authorization from competent authorities Non automotive qualified products Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified the product is not suitable for automotive use It is neither qualified nor tested in accordance with automotive testing or application requirements NXP Semiconductors accepts no liability for inclusion and or use of non automotive qualified products in automotive equipment or applications In the event that customer uses the product for design in and use in automotive applications to automotive specifications and standards customer a shall use the product without NXP Semiconductors warranty of the product for such automotive applications use and specifications and b 22 Contact information 32 bit ARM Cortex M3 microcontroller whenever customer uses the product for automotive applications beyond NXP Semiconductors specifications such use shall be solely at customer s own risk and c customer fully indemnifies NXP Semiconductors for any liability damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors
18. clock to the ARM core In Sleep mode execution of instructions is suspended until either a Reset or interrupt occurs Peripheral functions continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution Sleep mode eliminates dynamic power used by the processor itself memory systems and related controllers and internal buses Deep sleep mode In Deep sleep mode the oscillator is shut down and the chip receives no internal clocks The processor state and registers peripheral registers and internal SRAM values are preserved throughout Deep sleep mode and the logic levels of chip pins remain static The output of the IRC is disabled but the IRC is not powered down for a fast wake up later The RTC oscillator is not stopped because the RTC interrupts may be used as the wake up source The PLL is automatically turned off and disconnected The CCLK and USB clock dividers automatically get reset to zero The Deep sleep mode can be terminated and normal operation resumed by either a Reset or certain specific interrupts that are able to function without clocks Since all dynamic operation of the chip is suspended Deep sleep mode reduces chip power consumption to a very low value Power to the flash memory is left on in Deep sleep mode allowing a very quick wake up All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product
19. data sheet Rev 8 6 18 August 2015 32 of 80 NXP Semiconductors LPC1 759 58 56 54 52 51 8 29 5 3 8 29 5 4 8 29 5 5 8 29 6 8 29 7 LPC1759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller On wake up from Deep sleep mode the code execution and peripherals activities will resume after 4 cycles expire if the IRC was used before entering Deep sleep mode If the main external oscillator was used the code execution will resume when 4096 cycles expire PLL and clock dividers need to be reconfigured accordingly Power down mode Power down mode does everything that Deep sleep mode does but also turns off the power to the IRC oscillator and the flash memory This saves more power but requires waiting for resumption of flash operation before execution of code or data access in the flash memory can be accomplished On the wake up of Power down mode if the IRC was used before entering Power down mode it will take IRC 60 us to start up After this 4 IRC cycles will expire before the code execution can then be resumed if the code was running from SRAM In the meantime the flash wake up timer then counts 4 MHz IRC clock cycles to make the 100 us flash start up time When it times out access to the flash will be allowed Users need to reconfigure the PLL and clock dividers accordingly Deep power down mode The Deep power down mode can only be entered from the RTC block In Deep power down mode power is shut off to the en
20. data sheet LPC1759 58 56 54 52 51 v 6 Modifications Pin description of pins PO 29 and PO 30 updated in Table note 4 of Table 3 Pins are not 5 V tolerant e Typical value for Parameter Nena added in Table 8 e Condition 3 0 V lt Vpp ava 3 6 V added in Table 15 e Typical values for parameters Ipp REG sva and Igar with condition Deep power down mode corrected in Table 6 and Table note 9 Table note 10 and Table note 11 updated For Deep power down mode Figure 8 updated and Figure 9 added LPC1759 58 56 54 52 51 v 6 20100825 Product data sheet LPC1759 58 56 54 52 51v 5 Modifications Section 7 30 2 BOD level corrected Added Section 10 2 LPC1759 58 56 54 52 51v 5 20100716 Product data sheet LPC1759 58 56 54 52 51 v 4 LPC1759 58 56 54 52 51v 4 20100126 Product data sheet LPC1758 56 54 52 51 v 3 LPC1758 56 54 52 51 v 3 20091119 Product data sheet LPC1758 56 54 52 51 v2 LPC1758 56 54 52 51 v2 20090211 Objective data sheet LPC1758 56 54 52 51 v 1 LPC1758 56 54 52 51 v 1 20090115 Objective data sheet LPC1759 58 56 54 52 51 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 76 of 80 NXP Semiconductors LPC1759 58 56 54 52 51 21 Legal information 32 bit ARM Cortex M3 microcontroller
21. in this respect Limiting values Stress above one or more limiting values as defined in the Absolute Maximum Ratings System of IEC 60134 will cause permanent damage to the device Limiting values are stress ratings only and proper operation of the device at these or any other conditions above those given in the Recommended operating conditions section if present or the Characteristics sections of this document is not warranted Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device Terms and conditions of commercial sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale as published at http www nxp com profile terms unless otherwise agreed in a valid written individual agreement In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply NXP Semiconductors hereby expressly objects to applying the customer s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant conveyance or implication of any license under any copyrights patents or other industrial or intellectual property rights NXP Semiconductors N V 2015 All rights reserved
22. input current on pin VREFP Deep sleep mode 19 100 nA Power down mode 19 100 nA Deep power down 19 100 nA mode Standard port pins RESET li LOW level input current Vj 0 V on chip pull up 0 5 10 nA resistor disabled li HIGH level input Vi Vpp ava on chip 0 5 10 nA current pull down resistor disabled loz OFF state output Vo 0 V Vo Vpp av3 0 5 10 nA current on chip pull up down resistors disabled Vi input voltage pin configured to provide 20121 0 5 0 V a digital function 22 Vo output voltage output active 0 Vpp ava V Vin HIGH level input 0 7Vpp av3 V voltage Vi LOW level input voltage 0 3Vpp ava V Vhys hysteresis voltage 0 4 V Vou HIGH level output lou 4 mA Vpp ava V voltage 0 4 VoL LOW level output lo 4 mA 0 4 V voltage loH HIGH level output Vou Vpp ava 0 4 V 4 mA current lot LOW level output VoL 0 4 V 4 mA current lous HIGH level short circuit Vou 0 V 23 45 mA output current lots LOW level short circuit Voi Vpp ava 23 50 mA output current lod pull down current Vi 5V 10 50 150 uA lou pull up current Vi20V 15 50 85 uA Vpp av3 lt Vi lt 5V 0 0 0 uA LPC1759_58_56_54_52_51 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 41 of 80 NXP Sem
23. is de asserted or in case of a BOD triggered reset once the voltage rises above the BOD threshold the RSTOUT pin goes HIGH When the internal Reset is removed the processor begins executing at address 0 which is initially the Reset vector mapped from the boot block At that point all of the processor and peripheral registers have been initialized to predetermined values All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 35 of 80 NXP Semiconductors LPC1 759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller 8 30 2 Brownout detection The LPC1759 58 56 54 52 51 include 2 stage monitoring of the voltage on the Vpp REG 3v3 Pins If this voltage falls below 2 2 V the BOD asserts an interrupt signal to the Vectored Interrupt Controller This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt if not software can monitor the signal by reading a dedicated status register The second stage of low voltage detection asserts reset to inactivate the LPC1759 58 56 54 52 51 when the voltage on the Vpp ngg ava pins falls below 1 85 V This reset prevents alteration of the flash as operation of the various elements of the chip would otherwise become unreliable due to low voltage The BOD circuit maintains this reset down below 1 V at which point
24. power down mode Typical battery supply current Igat versus temperature All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 NXP Semiconductors LPC1 759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller 2aag 12 20 002aag120 a IDD REG 3V3 1 6 1 2 0 8 0 4 40 15 10 35 60 85 temperature C Conditions Vgar 3 0 V Vpp REG 3V3 23 0 V RTC running Fig 9 Deep power down mode Typical regulator supply current Ipp REGyava and battery supply current Igar versus temperature LPC1759 58 56 54 52 51 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 45 of 80 NXP Semiconductors LPC1 759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller 11 2 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the PCONP register All other blocks are disabled and no code is executed Measured on a typical sample at Tamb 25 C The peripheral clock PCLK CCLK 4 Table 8 Power consumption for individual analog and digital blocks Peripheral Con
25. rail 2 0 5 4 6 V Vpp REG 3v3 regulator supply voltage 3 3 V 21 0 5 4 6 V VppA analog 3 3 V pad supply 2 0 5 44 6 V voltage Vi VBAT input voltage on pin VBAT for the RTC 2 0 5 44 6 V Vi VREFP input voltage on pin VREFP 2 0 5 4 6 V ViA analog input voltage on ADC related pins 2II3 0 5 45 1 V Vi input voltage 5 V tolerant digital I O pins 214 0 5 5 5 V Vpp2 2 4 V Vpp 0 V 0 5 3 6 Ipp supply current per supply pin 100 mA Iss ground current per ground pin 100 mA llatch I O latch up current 0 5Vpp ava lt Vi lt 100 mA 1 5Vpp ava Tj lt 125 C Tstg storage temperature 5I 65 150 C Tj max maximum junction temperature 150 C Ptot pack total power dissipation per based on package heat 1 5 W package transfer not device power consumption Vesp electrostatic discharge voltage human body model all pins 6 4000 4000 V 1 The following applies to the limiting values a This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge Nonetheless it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum b Parameters are valid over operating temperature range unless otherwise specified All voltages are with respect to Vss unless otherwise noted c The limiting values are stress ratings only Operating the part at these value
26. referred to as CCLK elsewhere in this document The frequencies of PLLCLKIN and CCLK are the same value unless the PLL is active and connected The clock frequency for each peripheral can be selected individually and is referred to as PCLK Refer to Section 8 29 2 for additional information RTC oscillator The RTC oscillator can be used as the clock source for the RTC block the main PLL and or the CPU All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 30 of 80 NXP Semiconductors LPC1 759 58 56 54 52 51 8 29 2 8 29 3 8 29 4 LPC1759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller Main PLL PLLO The PLLO accepts an input clock frequency in the range of 32 kHz to 25 MHz The input frequency is multiplied up to a high frequency then divided down to provide the actual clock used by the CPU and or the USB block The PLLO input in the range of 32 kHz to 25 MHz may initially be divided down by a value N which may be in the range of 1 to 256 This input division provides a wide range of output frequencies from the same input frequency Following the PLLO input divider is the PLLO multiplier This can multiply the input divider output through the use of a Current Controlled Oscillator CCO by a value M in the range of 1 through 32768 The resulting frequency must be in the range o
27. sheet Rev 8 6 18 August 2015 28 of 80 NXP Semiconductors LPC1 759 58 56 54 52 51 8 28 8 28 1 8 29 8 29 1 LPC1759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller RTC and backup registers The RTC is a set of counters for measuring time when system power is on and optionally when it is off The RTC on the LPC1759 58 56 54 52 51 is designed to have extremely low power consumption i e less than 1 uA The RTC will typically run from the main chip power supply conserving battery power while the rest of the device is powered up When operating from a battery the RTC will continue working down to 2 1 V Battery power can be provided from a standard 3 V Lithium button cell An ultra low power 32 kHz oscillator will provide a 1 Hz clock to the time counting portion of the RTC moving most of the power consumption out of the time counting function The RTC includes a calibration mechanism to allow fine tuning the count rate in a way that will provide less than 1 second per day error when operated at a constant voltage and temperature The RTC contains a small set of backup registers 20 bytes for holding data while the main part of the LPC1759 58 56 54 52 51 is powered off The RTC includes an alarm function that can wake up the LPC1759 58 56 54 52 51 from all reduced power modes with a time resolution of 1 s Features Measures the passage of time to maintain a calendar and clock Ultra low power design to su
28. upon to contain detailed and full information For detailed and full information see the relevant full data sheet which is available on request via the local NXP Semiconductors sales office In case of any inconsistency or conflict with the short data sheet the full data sheet shall prevail Product specification The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer unless NXP Semiconductors and customer have explicitly agreed otherwise in writing In no event however shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet 21 3 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors In no event shall NXP Semiconductors be liable for any indirect incidental punitive special or consequential damages including without limitation lost profits lost savings business interruption costs related to the
29. y o I2STX SDA Transmit data It is driven by the transmitter and read by the receiver Corresponds to the signal SD in the S bus specification LPC1759 58 56 only y o MOSI1 Master Out Slave In for SSP1 O MAT2 3 Match output for Timer 2 channel 3 PO 10 TXD2 3901 y o PO 10 General purpose digital input output pin SDA2 MATS O O TXD2 Transmitter output for UART2 1 0 SDA2 I C2 data input output this is not an open drain pin O MAT3 0 Match output for Timer 3 channel 0 PO 11 RXD2 40l1 VO PO 11 General purpose digital input output pin SCL2 MAT3 1 l RXD2 Receiver input for UART2 y o SCL2 I C2 clock input output this is not an open drain pin O MAT3 1 Match output for Timer 3 channel 1 PO 15 TXD1 4711 VO PO 15 General purpose digital input output pin SCKO SCK O TXD1 Transmitter output for UART1 I O SCKO Serial clock for SSPO VO SCK Serial clock for SPI PO 16 RXD1 4801 VO PO 16 General purpose digital input output pin SSELO SSEL l RXD1 Receiver input for UART1 1 0 SSELO Slave Select for SSPO 1 0 SSEL Slave Select for SPI PO 17 CTS1 46lil VO P0 17 General purpose digital input output pin MISOO MISO l CTS1 Clear to Send input for UART1 1 0 MISOO Master In Slave Out for SSPO y o MISO Master In Slave Out for SPI PO 18 DCD1 4501 VO PO 18 General purpose digital input output pin MOSIO MOSI l DCD1
30. 0 cee eee eee 49 External clock nunana anaana annn 49 Internal oscillators n n nna aaan anana 50 VO PINS pi 3 hia siit oad iee ane 50 RC DUS ere dae ipo ton E e Ete e 51 1 S bus interface LPC1759 58 56 only 53 SSP interface 0 000000 55 USB interface 2 2 0 0 ee eee 57 lupe re Rc 58 ADC electrical characteristics 60 DAC electrical characteristics LPC1759 58 56 54 only 63 Application information 64 Suggested USB interface solutions 64 Crystal oscillator XTAL input and component SelectloDi i roa ces Ce e era RR e 67 XTAL Printed Circuit Board PCB layout guidelines llli 68 Standard I O pin configuration 69 Reset pin configuration 70 ElectroMagnetic Compatibility EMC 71 Package outline lsuueue 72 Soldering 1E RR 73 Abbreviations srl 74 References coo e IIR 74 Revision history leseeseee 75 Legal information Less 77 Data sheet status 00 77 Definitions llle 77 Disclaltflers eoo odes Ro Eo RA 77 Trademarks 0 002 eee eee eee 78 Contact information 78 CONnTENIS secs he ees oe de ee ewes 79 32 bit ARM Cortex M3 microcontroller Please be aware that important notices concerning this document and the product s described herein have been included in section Legal i
31. 18 l External reset input A LOW going pulse as short as 50 ns on this pin resets the device causing I O ports and peripherals to take on their default states and processor execution to begin at address 0 TTL with hysteresis 5 V tolerant LPC1759 58 56 54 52 51 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 12 of 80 NXP Semiconductors LPC1 759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller Table 4 Pin description continued Symbol Pin Type Description XTAL1 191910 Input to the oscillator circuit and internal clock generator circuits XTAL2 20810 O Output from the oscillator amplifier RTCX1 1319111 Input to the RTC oscillator circuit RTCX2 1519 O Output from the RTC oscillator circuit Vss 24 33 l ground 0 V reference 43 57 66 78 Vssa 9 l analog ground 0 V reference This should nominally be the same voltage as Vss but should be isolated to minimize noise and error Vpp 3v3 21 42 l 3 3 V supply voltage This is the power supply voltage for the I O ports 56 77 Vpp REG 3V3 34 67 3 3 V voltage regulator supply voltage This is the supply voltage for the on chip voltage regulator only VppA 8 analog 3 3 V pad supply voltage This should be nominally the same voltage as Vpp sva but should be isolated to m
32. 2 3 6 24 lou mA Conditions Vpp REGy 3V3 Vpp ava 3 3 V standard port pins Fig 10 Typical HIGH level output voltage Voy versus HIGH level output source current loH m 002aaf111 loL T 85 C mA 25 C 40 K 10 5 0 0 0 2 0 4 0 6 VoL V Conditions Vpp REG 3V3 Vpp ava 3 3 V standard port pins Fig 11 Typical LOW level output current loj versus LOW level output voltage VoL All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 47 of 80 NXP Semiconductors LPC1759 58 56 54 52 51 LPC1759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller 002aaf108 Conditions Vpp REG av3 Vpp ava 3 3 V standard port pins Fig 12 Typical pull up current ly versus input voltage Vj 90 002aaf109 Conditions Vpp REGy 3v3 Vpp ava 3 3 V standard port pins Fig 13 Typical pull down current lg versus input voltage Vi All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 48 of 80 NXP
33. 20130912 Product data sheet LPC1759 58 56 54 52 51 v8 Modifications Added Table 6 Thermal resistance Table 5 Limiting values Updated min max values for Vpp 3v3 and VpD REG 3V3 Updated conditions for Vj Updated table notes Table 7 Static characteristics Added Table note 14 TCK SWDCLK pin needs to be externally pulled LOW Updated Section 15 1 Suggested USB interface solutions Added Section 5 Marking Changed title of Figure 29 from USB interface on a self powered device to USB interface with soft connect LPC1759 58 56 54 52 51 v8 20120809 Product data sheet LPC1759_58_56_54_52_51 v 7 Modifications Remove table note The peak current is limited to 25 times the corresponding maximum current from Table 4 Limiting values e Change Vpp ava to Vpp nEG ava in Section 11 3 Internal oscillators Glitch filter constant changed to 10 ns in Table note 5 in Table 3 Description of RESET function updated in Table 3 Pull up value added for GPIO pins in Table 3 Pin configuration diagram for LQFP80 package corrected Figure 2 Pin description of USB UP LED pin updated in Table 3 e Riz and Riz labels in Figure 26 updated Table note 9 updated in Table 3 Table note 1 updated in Table 12 Electromagnetic compatibility data added in Section 14 6 Section 16 added LPC1759 58 56 54 52 51v7 20110329 Product
34. 21 1 Data sheet status Document status 1l2 Product status Definition Objective short data sheet Development This document contains data from the objective specification for product development Preliminary short data sheet Qualification This document contains data from the preliminary specification Product short data sheet Production This document contains the product specification 1 Please consult the most recently issued document before initiating or completing a design 2 The term short data sheet is explained in section Definitions 3 The product status of device s described in this document may have changed since this document was published and may differ in case of multiple devices The latest product status information is available on the Internet at URL http www nxp com 21 2 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information Short data sheet A short data sheet is an extract from a full data sheet with the same product type number s and title A short data sheet is intended for quick reference only and should not be relied
35. 29 4 8 29 5 8 29 5 1 8 29 5 2 8 29 5 3 8 29 5 4 8 29 5 5 8 29 6 8 29 7 8 30 8 30 1 8 30 2 8 30 3 8 30 4 8 30 5 8 30 6 8 30 7 8 31 9 10 All information provided in this document is subject to legal disclaimers FeatureS 000 00 e eee eee eee 24 I2C bus serial I O controllers 24 FeatureS 00 0c eee eee eee 24 I2S bus serial I O controllers LPC1759 58 56 Only ma dax pre DO dedo perd 24 Features ico sus eee REEL REI 25 General purpose 32 bit timers external event COUMES ony i sb eub E Sene Ee 25 Feat tes 4 2288 ue bet Rer dd 25 Pulse width modulator 26 gp ce icc ec innen a ennnen Enna 26 Motor control PWM 27 Quadrature Encoder Interface QEI 27 Features ceea e a 00 e eee 27 Repetitive Interrupt RI timer 28 FeatureSin i biwtiaw aided edt theta 28 ARM Cortex M3 system tick timer 28 Watchdog timer 0 00 5 28 F atUreS s s miel ua y n ER x 28 RTC and backup registers 29 Features ccc oe ile ta kn kd ps 8 29 Clocking and power control 29 Crystal oscillators 00 29 Internal RC oscillator 30 Main oscillator 2 22200 5 30 RTC oscillator 20 00000 eee 30 Main PLL PLLO 0 31 USB PLL PLL1 0 0005 31 Wake up timer 200 0055 31 Power control
36. 330 USB A connector USB PPWR Fig 32 LPC1759 58 56 54 USB host port configuration 5V LM3526 L 002aae 156 LPC1759 58 56 54 52 51 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 66 of 80 NXP Semiconductors LPC1 759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller Fig 33 LPC1759 58 56 54 52 51 USB device port configuration LPC17xx USB UP LED _ VDD A USB_CONNECT USB_D USB B connector 002aad943 15 2 Crystal oscillator XTAL input and component selection LPC1759_58_56_54_52_51 The input voltage to the on chip oscillators is limited to 1 8 V If the oscillator is driven by a clock in slave mode it is recommended that the input be coupled through a capacitor with Ci 100 pF To limit the input voltage to the specified range choose an additional capacitor to ground Cg which attenuates the input voltage by a factor C C Cg In slave mode a minimum of 200 mV RMS is needed LPC1xxx S 100 pF Fig 34 Slave mode operation of the on chip oscillator 002aae835 In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF Figure 34 with an amplitude between 200 mV RMS and 1000 mV RMS
37. 50 edge of the clock PCLK and the 10 96 90 96 edge of the data signal MOSI or MISO SCK CPOL 0 SCK CPOL 1 MOSI MISO TSPICYC tSPICLKH tSPICLKL isPIlQV DATA VALID tsPIDSU gt DATA VALID tSPIDH gt tsPIOH DATA VALID DATA VALID Fig 22 SPI master timing CPHA 1 002aad986 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 58 of 80 NXP Semiconductors LPC1759 58 56 54 52 51 LPC1759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller SCK CPOL 0 TsPICYC tsPICLKH n gt c gt lt tSPICLKL L3 SCK CPOL 1 MOSI DATA VALID DATA VALID tsPIDSU tsPIDH MISO DATA VALID DATA VALID Fig 23 SPI master timing CPHA 0 tsPIOH 002aad987 SCK CPOL 0 SCK CPOL 1 MOSI MISO TsPicvc tsPICLKH tSPICLKL tsPIDSU gt DATA VALID DATA VALID tspliayv 4 tsPIDH gt tsPIOH DATA VALID DATA VALID Fig 24 SPI slave timing CPHA 1 002aad988 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 59 of 80 NXP Se
38. 54 52 51 8 16 8 16 1 8 17 8 17 1 8 18 LPC1759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller UARTs The LPC1759 58 56 54 52 51 each contain four UARTs In addition to standard transmit and receive data lines UART1 also provides a full modem control handshake interface and support for RS 485 9 bit mode allowing both software address detection and automatic address detection using 9 bit mode The UARTS include a fractional baud rate generator Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz Features Maximum UART data bit rate of 6 25 Mbit s 16 B Receive and Transmit FIFOs Register locations conform to 16C550 industry standard Receiver FIFO trigger points at 1 B 4 B 8 B and 14 B Built in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values Fractional divider for baud rate control auto baud capabilities and FIFO control mechanism that enables software flow control implementation e UART1 equipped with standard modem interface signals This module also provides full support for hardware flow control auto CTS RTS Support for RS 485 9 bit EIA 485 mode UART1 UARTS includes an IrDA mode to support infrared communication All UARTs have DMA support SPI serial I O controller The LPC1759 58 56 54 52 51 contain one SPI controller SPI is a full duplex serial interfa
39. 54 52 51 this timer can be clocked from the internal AHB clock or from a device pin Watchdog timer The purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state When enabled the watchdog will generate a system reset if the user program fails to feed or reload the watchdog within a predetermined amount of time Features Internally resets chip if not periodically reloaded Debug mode Enabled by software but requires a hardware reset or a watchdog reset interrupt to be disabled Incorrect Incomplete feed sequence causes reset interrupt if enabled Flag to indicate watchdog reset Programmable 32 bit timer with internal prescaler Selectable time period from Tcy WwDCLK x 256 x 4 to Tcy wDCLk x 232 x 4 in multiples of Tcy WDCLK x 4 The Watchdog Clock WDCLK source can be selected from the Internal RC IRC oscillator the RTC oscillator or the APB peripheral clock This gives a wide range of potential timing choices of Watchdog operation under different power reduction conditions It also provides the ability to run the WDT from an entirely internal source that is not dependent on an external crystal and its associated components and wiring for increased reliability Includes lock safe feature All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data
40. 759 58 56 54 52 51 use accelerated GPIO functions GPIO registers are accessed through the AHB multilayer bus so that the fastest possible I O timing can be achieved Mask registers allow treating sets of port bits as a group leaving other bits unchanged All GPIO registers are byte and half word addressable Entire port value can be written in one instruction Support for Cortex M3 bit banding Support for use with the GPDMA controller All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 18 of 80 NXP Semiconductors LPC1 759 58 56 54 52 51 8 10 1 8 11 8 11 1 LPC1759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller Additionally any pin on Port 0 and Port 2 total of 42 pins providing a digital function can be programmed to generate an interrupt on a rising edge a falling edge or both The edge detection is asynchronous so it may operate when clocks are not present such as during Power down mode Each enabled interrupt can be used to wake up the chip from Power down mode Features Bit level set and clear registers allow a single instruction to set or clear any number of bits in one port Direction control of individual bits e All I O default to inputs after reset Pull up pull down resistor configuration and open drain configuration can be programmed through the pin connect
41. All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 33 of 80 NXP Semiconductors LPC1 759 58 56 54 52 51 LPC1759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller On the LPC1759 58 56 54 52 51 I O pads are powered by the 3 3 V Vpp ava pins while the Vpp nEg 3va Pin powers the on chip voltage regulator which in turn provides power to the CPU and most of the peripherals Depending on the LPC1759 58 56 54 52 51 application a design can use two power options to manage power consumption The first option assumes that power consumption is not a concern and the design ties the Vpp ava and Vpp nEg 3va Pins together This approach requires only one 3 3 V power supply for both pads the CPU and peripherals While this solution is simple it does not support powering down the I O pad ring on the fly while keeping the CPU and peripherals alive The second option uses two power supplies a 3 3 V supply for the I O pads Vpp ava and a dedicated 3 3 V supply for the CPU Vpp ngg 3va Having the on chip voltage regulator powered independently from the I O pad ring enables shutting down of the I O pad power supply on the fly while the CPU and peripherals stay active The VBAT pin supplies power only to the RTC domain The RTC requires a minimum of power to operate which can be supplied by an extern
42. ETHERNET CONTROLLER WITH DMA 2 POWER CONTROL SYSTEM FUNCTIONS USB HOST DEVICE OTG CONTROLLER WITH DMA 4 clocks and l code D code system master master master controls bus bus bus slave C Rom MULTILAYER AHB MATRIX HIGH SPEED zl Sue GPIO APB slave group 0 s J 9 EN e wove a a menn E wr J 9 ew JC NNI MN S meer K rane coa l oseiro are JK C esrseasns IK RTC POWER DOMAIN Block diagram ww 1 LPC 1759 58 56 only AHB TO 2 LPC1758 only BRIDGE 1 slave gt U slave slave FLASH ACCELERATOR FLASH 512 256 128 64 32 kB APB slave group 1 99 7 APB C ae C C C gt TIMER2 3 MOTOR CONTROL PWM mm EET C ee C L wwe Maa 3 LPC1759 58 56 54 only 4 LPC1752 51 USB device only 002aae 153 Grey shaded blocks represent peripherals with connection to the GPDMA SCKO SSELO MISOO MOSIO RXD2 3 TXD2 3 I2SRX SDA l2STX_CLK I28TX WS I28TX SDA TX MCLK RX MCLK SCL2 SDA2 4x MAT2 2 x MATS MCOA 2 0 MCOBJI2 0 MCI 2 0 PHA PHB INDEX AOUT EINTO LPC1759 58 56 54 52 51 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 6 of 80 NXP Semiconductors LPC1759 58 56 54 52 51 7 Pinning informat
43. GoodLink features All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 20 of 80 NXP Semiconductors LPC1 759 58 56 54 52 51 8 12 2 8 12 2 1 8 12 3 8 12 3 1 8 13 LPC1759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller While USB is in the Suspend mode the LPC1759 58 56 54 52 51 can enter one of the reduced power modes and wake up on USB activity Supports DMA transfers with all on chip SRAM blocks on all non control endpoints Allows dynamic switching between CPU controlled slave and DMA modes Double buffer implementation for Bulk and Isochronous endpoints USB host controller LPC1759 58 56 54 only The host controller enables full and low speed data exchange with USB devices attached to the bus It consists of a register interface a serial interface engine and a DMA controller The register interface complies with the Open Host Controller Interface OHCI specification Features e OHCI compliant One downstream port Supports port power switching USB OTG controller LPC1759 58 56 54 only USB OTG is a supplement to the USB 2 0 specification that augments the capability of existing mobile devices and USB peripherals by adding host functionality for connection to USB peripherals The OTG Controller integrates the host controller device controller and a mas
44. HB masters include the CPU General Purpose DMA controller Ethernet MAC LPC1758 only and the USB interface This interconnect provides communication with no arbitration delays Split APB bus allows high throughput with few stalls between the CPU and DMA Serial interfaces On the LPC 1758 only Ethernet MAC with RMII interface and dedicated DMA controller USB 2 0 full speed device Host OTG controller with dedicated DMA controller and on chip PHY for device Host and OTG functions The LPC 1752 51 include a USB device controller only Four UARTs with fractional baud rate generation internal FIFO and DMA support One UART has modem control I O and RS 485 EIA 485 support and one UART has IrDA support CAN 2 0B controller with two LPC 1759 58 56 or one LPC1754 52 51 channels SPI controller with synchronous serial full duplex communication and programmable data length Two SSP controllers with FIFO and multi protocol capabilities The SSP interfaces can be used with the GPDMA controller Two I C bus interfaces supporting fast mode with a data rate of 400 kbit s with multiple address recognition and monitor mode On the LPC1759 58 56 only I S Inter IC Sound interface for digital audio input or output with fractional rate control The 1 S bus interface can be used with the GPDMA The I S bus interface supports 3 wire and 4 wire data transmit and receive as well as master clock input output E O
45. M Cortex M3 processor is described in detail in the Cortex M3 Technical Reference Manual that can be found on official ARM website On chip flash program memory The LPC1759 58 56 54 52 51 contain up to 512 kB of on chip flash memory A new two port flash accelerator maximizes performance for use with the two fast AHB Lite buses On chip SRAM The LPC1759 58 56 54 52 51 contain a total of up to 64 kB on chip static RAM memory This includes the main 32 16 8 kB SRAM accessible by the CPU and DMA controller on a higher speed bus and up to two additional 16 kB each SRAM blocks situated on a separate slave port on the AHB multilayer matrix This architecture allows CPU and DMA accesses to be spread over three separate RAMs that can be accessed simultaneously All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 14 of 80 NXP Semiconductors LPC1 759 58 56 54 52 51 LPC1759 58 56 54 52 51 8 5 8 6 32 bit ARM Cortex M3 microcontroller Memory Protection Unit MPU The LPC1759 58 56 54 52 51 have a Memory Protection Unit MPU which can be used to improve the reliability of an embedded system by protecting critical data within the user application The MPU allows separating processing tasks by disallowing access to each other s data disabling access to memory regions allowing memory regions to be defi
46. OCK USB BLOCK OSCILLATOR DIVIDER INTERNAL RC DMA WATCHDOG OSCILLATOR TIMER GPIO Fig 4 LPC1759 58 56 54 52 51 clocking generation block diagram MAIN PLL USB clock config USB PLL enable USBCLKCFG system ee ARM CLOCK 2 main PLL enable DIVIDER CORTEX M3 CLKSRCSEL CPU clock config ETHERNET CCLKCFG BLOCK NVIC CCLK 8 CCLK 6 pclkwpT PERIPHERAL CLOCK CCLK 4 APB peripherals GENERATOR CCLK 2 RTC Ly OSCILLATOR rick 1Hz_ REAL TIME CCLK CLOCK 002aad947 8 29 1 1 8 29 1 2 8 29 1 3 LPC1759 58 56 54 52 51 Internal RC oscillator The IRC may be used as the clock source for the WDT and or as the clock that drives the PLL and subsequently the CPU The nominal IRC frequency is 4 MHz The IRC is trimmed to 1 96 accuracy over the entire voltage and temperature range Upon power up or any chip reset the LPC1759 58 56 54 52 51 use the IRC as the clock source Software may later switch to one of the other available clock sources Main oscillator The main oscillator can be used as the clock source for the CPU with or without using the PLL The main oscillator also provides the clock source for the dedicated USB PLL The main oscillator operates at frequencies of 1 MHz to 25 MHz This frequency can be boosted to a higher frequency up to the maximum CPU operating frequency by the main PLL The clock selected as the PLL input is PLLCLKIN The ARM processor clock frequency is
47. One match register PWMMR0 controls the PWM cycle rate by resetting the count upon match The other match register controls the PWM edge position Additional single edge controlled PWM outputs require only one match register each since the repetition rate is the same for all PWM outputs Multiple single edge controlled PWM outputs will all have a rising edge at the beginning of each PWM cycle when an PWMMRO match occurs Three match registers can be used to provide a PWM output with both edges controlled Again the PWMMRO match register controls the PWM cycle rate The other match registers control the two PWM edge positions Additional double edge controlled PWM outputs require only two match registers each since the repetition rate is the same for all PWM outputs With double edge controlled PWM outputs specific match registers control the rising and falling edge of the output This allows both positive going PWM pulses when the rising edge occurs prior to the falling edge and negative going PWM pulses when the falling edge occurs prior to the rising edge 8 22 1 Features LPC1759 58 56 54 52 51 LPC1759 58 56 54 52 51 has one PWM block with Counter or Timer operation may use the peripheral clock or one of the capture inputs as the clock source Seven match registers allow up to 6 single edge controlled or 3 double edge controlled PWM outputs or a mix of both types The match registers also allow Continuous operation
48. PO 0 Capture input for Timer 0 channel 0 LPC1759 58 56 54 52 51 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 10 of 80 NXP Semiconductors LPC1 759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller Table 4 Pin description continued Symbol Pin Type Description P1 28 MCOA2 35 yo P1 28 General purpose digital input output pin a O MCOA2 Motor control PWM channel 2 output A I PCAP1 0 Capture input for PWM1 channel 0 O MATO 0 Match output for Timer 0 channel 0 P1 29 MCOB2 36L VO P1 29 General purpose digital input output pin M y O MCOB2 Motor control PWM channel 2 output B l PCAP1 1 Capture input for PWM1 channel 1 O MATO 1 Match output for Timer 0 channel 1 P1 30 Vgus 18 2 VO P1 30 General purpose digital input output pin ADO 4 Vsus Monitors the presence of USB bus power Note This signal must be HIGH for USB reset to occur l ADO 4 A D converter 0 input 4 P1 31 SCK1 172 y o P1 31 General purpose digital input output pin ADOS O SCK1 Serial Clock for SSP1 l ADO 5 A D converter 0 input 5 P2 0 to P2 31 y o Port 2 Port 2 is a 32 bit I O port with individual direction controls for each bit The operation of port 2 pins depends upon the
49. Semiconductors LPC1 759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller 12 Dynamic characteristics 12 1 Flash memory Table 9 Flash characteristics Tamb 40 C to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Nendu endurance I1 40000 100000 cycles tret retention time powered 10 years unpowered 20 years ter erase time sector or multiple 95 100 105 ms consecutive sectors tprog programming time 2 0 95 1 1 05 ms 1 Number of program erase cycles 2 Programming times are given for writing 256 bytes from RAM to the flash Data must be written to the flash in blocks of 256 bytes 12 2 External clock Table 10 Dynamic characteristic external clock Tamb 40 C to 85 C Vpp aya over specified ranges Symbol Parameter Conditions Min Typ Max Unit fosc oscillator frequency 1 25 MHz Toy clk clock cycle time 40 1000 ns tcHcx clock HIGH time Toy clk x 0 4 ns tcLox clock LOW time Toy ctk x 0 4 ns toLcH clock rise time 5 ns tcHcL clock fall time 5 ns 1 Parameters are valid over operating temperature range unless otherwise specified 2 Typical ratings are not guaranteed The values listed are at room temperature 25 C nominal supply voltages tcLcx Toy cik 002aaa907 Fig 14 External clock timing with an amplitud
50. Z N N SJojonpuooruies dXN APB1 peripherals 0x4010 0000 H System control 5 0x400C 0000 30 16 reserved 0x400B coo0 15 QEI 0x400B 8000 14 1 motor control PWM 0x400B 4000 0x400B 0000 12 repetitive interrupt timer reserved 1 reserved 128 1 reserved 12C2 UART3 UART2 timer 3 0x400A C000 0x400A 8000 0x400A 4000 0x400A 0000 0x4009 C000 0x4009 8000 0x4009 4000 0x4009 0000 0x4008 C000 0x4008 8000 0x4008 0000 o i i 1 l timer 2 DAC 3 SSPO 1 0 reserved i N 1 LPC1759 58 56 only 2 LPC1758 only 3 LPC1759 58 56 54 only l code D code memory space 0x0000 0400 256 words 0x0000 0000 active interrupt vectors LPC1759 58 56 54 52 51 memory space 1 OxFFFF FFFF reserved z 0xE010 0000 4GB rivate peripheral bus 3 as 0xE000 0000 reserved gt 0x5020 0000 s i at eA anae AHB peripherals 0x5000 0000 T reserved ENS 0x4400 0000 peripheral bit band alias addressing 0x4200 0000 gt reserved Ss 0x4010 0000 APB1 peripherals 0x4008 0000 APBO peripherals 0x4000 0000 puer sen gt reserved ENS 0x2400 0000 AHB SRAM bit band alias addressing 0x2200 0000 reserven 0x200A 0000 0x2009 C000 reserved Qx2008 4000 16 kB AHB SRAM1 LPC1759 8 0x2008 0000 16 kB AHB SRAMO LPC1759 8 6 4 aes eee s reserved Qx1FFF 2000 8 kB boot ROM Ox1FFF 0000 B reserved Y 0x1000 8000 32 kB local static RAM LPC1759 8
51. a0 4000 16 kB local static RAM LPC1756 4 2 a0 2000 8 kB local static RAM LPC1751 4 00 0000 reserved 0x0008 0000 512 kB on chip flash LPC1759 8 0x0004 0000 256 kB on chip flash LPC1756 0x0002 0000 128 kB on chip flash LPC1754 0x0001 0000 0x0000 8000 64 kB on chip flash LPC1752 Fig 3 LPC1759 58 56 54 52 51 memory map 0GB 32 kB on chip flash LPC1751 0x0000 0000 AHB peripherals 127 4 reserved CAM USB controller reserved 1 GPDMA controller O Ethernet controller 2 APBO peripherals 174 CAN1 16 CAN common 1 CAN AF RAM ADC 4 13 1 0 2 1 pin connect GPIO interrupts RTC backup registers reserved timer 1 0x5020 0000 0x5001 0000 0x5000 C000 0x5000 8000 0x5000 4000 0x5000 0000 0x4008 0000 0x4006 0000 0x4005 C000 0x4004 C000 0x4004 8000 0x4004 4000 0x4004 0000 0x4003 C000 0x4003 8000 0x4003 4000 0x4003 0000 0x4002 C000 0x4002 8000 0x4002 4000 0x4002 0000 0x4001 C000 0x4001 8000 0x4001 4000 0x4001 0000 0x4000 C000 0x4000 8000 0x4000 4000 0x4000 0000 002aae154 19 041u0590491UI JJ X91102 WHV 1q0 c 40 9npuooliul9S dXN LG cS v6 98 885 687 LOd l NXP Semiconductors LPC1 759 58 56 54 52 51 8 8 LPC1759 58 56 54 52 51 8 7 7 1 7 2 8 8 8 9 32 bit ARM Cortex M3 microcontroller Nested Vectored Interrupt Controller NVIC The NVIC is an integral part of the Cortex M3 The tight coupling t
52. ait for them to stabilize before they are used as a clock source When the main oscillator is initially activated the wake up timer allows software to ensure that the main oscillator is fully functional before the processor uses it as a clock source and starts to execute instructions This is important at power on all types of Reset and whenever any of the aforementioned functions are turned off for any reason Since the oscillator and other functions are turned off during Power down mode any wake up of the processor from Power down mode makes use of the wake up Timer The Wake up Timer monitors the crystal oscillator to check whether it is safe to begin code execution When power is applied to the chip or when some event caused the chip to exit Power down mode some time is required for the oscillator to produce a signal of sufficient amplitude to drive the clock logic The amount of time depends on many factors including the rate of Vpp sva ramp in the case of power on the type of crystal and its All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 31 of 80 NXP Semiconductors LPC1 759 58 56 54 52 51 8 29 5 8 29 5 1 8 29 5 2 LPC1759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller electrical characteristics if a quartz crystal is used as well as any other external circuitry e g capa
53. al battery The device core power Vbpp iREG 3v3 is used to operate the RTC whenever VpD REG 3V3 is present Therefore there is no power drain from the RTC battery when Vpp Reg ava IS available All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 34 of 80 NXP Semiconductors LPC1 759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller LPC17xx to I O pads VDD 3V3 Vss VDD REG 3V3 oscillators l l l l to core i REGULATOR to memories T peripherals l l l l MAIN POWER DOMAIN ULTRA LOW POWER VBAT REGULATOR RTCX1 RTCX2 VDDA VREFP VREFN Vssa 002aad978 Fig 5 Power distribution 8 30 System control 8 30 1 LPC1759 58 56 54 52 51 Reset Reset has four sources on the LPC17xx the RESET pin the Watchdog reset power on reset POR and the BrownOut Detection BOD circuit The RESET pin is a Schmitt trigger input pin Assertion of chip Reset by any source once the operating voltage attains a usable level causes the RSTOUT pin to go LOW and starts the wake up timer see description in Section 8 29 4 The wake up timer ensures that reset remains asserted until the external Reset is de asserted the oscillator is running a fixed number of clocks have passed and the flash controller has completed its initialization Once reset
54. block for each GPIO pin Ethernet LPC1758 only The Ethernet block contains a full featured 10 Mbit s or 100 Mbit s Ethernet MAC designed to provide optimized performance through the use of DMA hardware acceleration Features include a generous suite of control registers half or full duplex operation flow control control frames hardware acceleration for transmit retry receive packet filtering and wake up on LAN activity Automatic frame transmission and reception with scatter gather DMA off loads many operations from the CPU The Ethernet block and the CPU share the ARM Cortex M3 D code and system bus through the AHB multilayer matrix to access the various on chip SRAM blocks for Ethernet data control and status information The Ethernet block interfaces between an off chip Ethernet PHY using the Reduced MII RMII protocol and the on chip Media Independent Interface Management MIIM serial bus The Ethernet block supports bus clock rates of up to 100 MHz Features Ethernet standards support Supports 10 Mbit s or 100 Mbit s PHY devices including 10 Base T 100 Base TX 100 Base FX and 100 Base T4 Fully compliant with EEE standard 802 3 Fully compliant with 802 3x full duplex flow control and half duplex back pressure Flexible transmit and receive frame options Virtual Local Area Network VLAN frame support e Memory management Independent transmit and receive buffers memory mapped to sha
55. bus 32 bit register and RAM access Compatible with CAN specification 2 0B ISO 11898 1 Global Acceptance Filter recognizes standard 11 bit and extended frame 29 bit receive identifiers for all CAN buses Acceptance Filter can provide FullCAN style automatic reception for selected Standard Identifiers FullCAN messages can generate interrupts 12 bit ADC The LPC1759 58 56 54 52 51 contain one ADC It is a single 12 bit successive approximation ADC with six channels and DMA support Features 12 bit successive approximation ADC Input multiplexing among 6 pins Power down mode Measurement range VREFN to VREFP 12 bit conversion rate 200 kHz Individual channels can be selected for conversion Burst conversion mode for single or multiple inputs Optional conversion on transition of input pin or Timer Match signal Individual result registers for each ADC channel to reduce interrupt overhead DMA support 10 bit DAC LPC1759 58 56 54 only The DAC allows to generate a variable analog output The maximum output value of the DAC is VREFP Features 10 bit DAC Resistor string architecture Buffered output Power down mode Selectable output drive Dedicated conversion timer DMA support All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 22 of 80 NXP Semiconductors LPC1 759 58 56
56. by the SSEL1 MAT2 0 receiver Corresponds to the signal SD in the 2S bus specification LPC1759 58 56 only y o SSEL1 Slave Select for SSP1 O MAT2 0 Match output for Timer 2 channel 0 LPC1759_58_56_54_52_51 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 7 of 80 NXP Semiconductors LPC1 759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller Table 4 Pin description continued Symbol Pin Type Description PO 7JI2STX CLK 6301 yo PO 7 General purpose digital input output pin SCK1 MAT2 1 y o I2STX CLK Transmit Clock It is driven by the master and received by the slave Corresponds to the signal SCK in the S bus specification LPC1759 58 56 only y o SCK1 Serial Clock for SSP1 O MAT2 1 Match output for Timer 2 channel 1 PO 8 I2STX_WS 6201 y o PO 8 General purpose digital input output pin MISO1 MAT2 2 y o I2STX WS Transmit Word Select It is driven by the master and received by the slave Corresponds to the signal WS in the S bus specification LPC1759 58 56 only yo MISO1 Master In Slave Out for SSP1 O MAT2 2 Match output for Timer 2 channel 2 PO S lASTX SDA e1l yo PO 9 General purpose digital input output pin MOSI1 MAT2 3
57. ce designed to handle multiple masters and slaves connected to a given bus Only a single master and a single slave can communicate on the interface during a given data transfer During a data transfer the master always sends 8 bits to 16 bits of data to the slave and the slave always sends 8 bits to 16 bits of data to the master Features Maximum SPI data bit rate of 12 5 Mbit s Compliant with SPI specification e Synchronous serial full duplex communication Combined SPI master and slave Maximum data bit rate of one eighth of the input clock rate 8 bits to 16 bits per transfer SSP serial I O controller The LPC1759 58 56 54 52 51 contain two SSP controllers The SSP controller is capable of operation on a SPI 4 wire SSI or Microwire bus It can interact with multiple masters and slaves on the bus Only a single master and a single slave can communicate on the All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 23 of 80 NXP Semiconductors LPC1 759 58 56 54 52 51 8 18 1 8 19 8 19 1 32 bit ARM Cortex M3 microcontroller bus during a given data transfer The SSP supports full duplex transfers with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master In practice often only one of these data flows carries meaningful data Feature
58. citors and the characteristics of the oscillator itself under the existing ambient conditions Power conirol The LPC1759 58 56 54 52 51 support a variety of power control features There are four special modes of processor power reduction Sleep mode Deep sleep mode Power down mode and Deep power down mode The CPU clock rate may also be controlled as needed by changing clock sources reconfiguring PLL values and or altering the CPU clock divider value This allows a trade off of power versus processing speed based on application requirements In addition Peripheral Power Control allows shutting down the clocks to individual on chip peripherals allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application Each of the peripherals has its own clock divider which provides even better power control Integrated PMU Power Management Unit automatically adjust internal regulators to minimize power consumption during Sleep Deep sleep Power down and Deep power down modes The LPC1759 58 56 54 52 51 also implement a separate power domain to allow turning off power to the bulk of the device while maintaining operation of the RTC and a small set of registers for storing data during any of the power down modes Sleep mode When Sleep mode is entered the clock to the core is stopped Resumption from the Sleep mode does not need any special sequence but re enabling the
59. clock Configurable word select period in master mode separately for I S input and output Two 8 word FIFO data buffers are provided one for transmit and one for receive Generates interrupt requests when buffer levels cross a programmable boundary Two DMA requests controlled by programmable buffer levels These are connected to the GPDMA block Controls include reset stop and mute options separately for 12S input and I S output 8 21 General purpose 32 bit timers external event counters The LPC1759 58 56 54 52 51 include four 32 bit timer counters The timer counter is designed to count cycles of the system derived clock or an externally supplied clock It can optionally generate interrupts generate timed DMA requests or perform other actions at specified timer values based on four match registers Each timer counter also includes two capture inputs to trap the timer value when an input signal transitions optionally generating an interrupt 8 21 1 Features LPC1759 58 56 54 52 51 A 32 bit timer counter with a programmable 32 bit prescaler Counter or timer operation One 32 bit capture channel for timer 0 and two capture channels for timer 1 The capture channels can take a snapshot of the timer value when an input signal transitions A capture event may also generate an interrupt Four 32 bit match registers that allow Continuous operation with optional interrupt generation on match Stop timer on match with optio
60. d to be an RS 485 EIA 485 output enable signal O TRACEDATA O0 Trace data bit 0 LPC1759 58 56 54 52 51 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 11 of 80 NXP Semiconductors LPC1 759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller Table 4 Pin description continued Symbol Pin Type Description P2 6 PCAP1 0 5201 y o P2 6 General purpose digital input output pin RH TRACECLK PCAP1 0 Capture input for PWM1 channel 0 l RI1 Ring Indicator input for UART1 O TRACECLK Trace Clock P2 7 RD2 5101 y o P2 7 General purpose digital input output pin RTS1 l RD2 CAN receiver input LPC1759 58 56 only O RTS1 Request to Send output for UART1 Can also be configured to be an RS 485 EIA 485 output enable signal P2 8 TD2 50H VO P2 8 General purpose digital input output pin TXD2 e TD2 CAN transmitter output LPC1759 58 56 only O TXD2 Transmitter output for UART2 P2 9 491 VO P2 9 General purpose digital input output pin lia O USB CONNECT Signal used to switch an external 1 5 kO resistor under software control Used with the SoftConnect USB feature l RXD2 Receiver input for UART2 P2 10 EINTO NMI 4115 yo P2 10 General purpose digital input output pin A LOW level on this pin duri
61. dBuV peak level 30 MHz to 150 MHz 1 45 10 15 7 dBuV 150 MHz to 1 GHz 1 6 11 10 16 dBuV IEC level O O N M M 1 IEC levels refer to Appendix D in the IEC61967 2 Specification All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 71 of 80 NXP Semiconductors LPC1 759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller 16 Package outline LQFP80 plastic low profile quad flat package 80 leads body 12 x 12 x 1 4mm SOT315 1 detail X DIMENSIONS mm are the original dimensions UNIT A A2 As bp C 1 5 0 04 1 3 i 0 13 Note 1 Plastic or metal protrusions of 0 25 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN VERSION IEC JEDEC JEITA PROJECTION SOT315 1 136E15 MS 026 t 03 02 25 Fig 38 Package outline LQFP80 ISSUE DATE LPC1759 58 56 54 52 51 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 72 o
62. ditions Typical supply current in mA Notes CCLK 12 MHz 48 MHz 100 MHz Timer 0 03 0 11 0 23 Average current per timer UART 0 07 0 26 0 53 Average current per UART PWM 0 05 0 20 0 41 Motor control 0 05 0 21 0 42 PWM 12C 0 02 0 08 0 16 Average current per I2C SPI 0 02 0 06 0 13 SSP1 0 04 0 16 0 32 ADC PCLK 12 MHz for CCLK 12 MHz 2 12 2 09 2 07 and 48 MHz PCLK 12 5 MHz for CCLK 100 MHz CAN PCLK CCLK 6 0 13 0 49 1 00 Average current per CAN CANO CAN1 PCLK CCLK 6 0 22 0 85 1 73 Both CAN blocks and acceptance filter acceptance filter DMA PCLK CCLK 1 33 5 10 10 36 QEI 0 05 0 20 0 41 GPIO 0 33 1 27 2 58 12S 0 09 0 34 0 70 USB and PLL1 0 94 1 32 1 94 Ethernet Ethernet block enabled in the PCONP 0 49 1 87 3 79 register Ethernet not connected Ethernet Ethernet initialized connected to 5 19 connected network and running web server example 1 The combined current of several peripherals running at the same time can be less than the sum of each individual peripheral current measured separately LPC1759 58 56 54 52 51 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 46 of 80 NXP Semiconductors LPC1 759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller 11 3 Electrical pin characteristics LPC1759 58 56 54 52 51 002aaf11
63. duce an interrupt for whole and partial revolution displacement Digital filter with programmable delays for encoder input signals Can accept decoded signal inputs clk and direction Connected to APB All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 27 of 80 NXP Semiconductors LPC1 759 58 56 54 52 51 8 25 8 25 1 8 26 8 27 8 27 1 LPC1759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller Repetitive Interrupt RI timer The repetitive interrupt timer provides a free running 32 bit counter which is compared to a selectable value generating an interrupt when a match occurs Any bits of the timer compare can be masked such that they do not contribute to the match detection The repetitive interrupt timer can be used to create an interrupt that repeats at predetermined intervals Features 32 bit counter running from PCLK Counter can be free running or be reset by a generated interrupt 32 bit compare value 32 bit compare mask An interrupt is generated when the counter value equals the compare value after masking This allows for combinations not possible with a simple compare ARM Cortex M3 system tick timer The ARM Cortex M3 includes a system tick timer SYSTICK that is intended to generate a dedicated SYSTICK exception at a 10 ms interval In the LPC1759 58 56
64. e customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products and NXP Semiconductors accepts no liability for any assistance with applications or customer product design It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned as well as for the planned application and use of customer s third party customer s Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products NXP Semiconductors does not accept any liability related to any default damage costs or problem which is based on any weakness or default in the customer s applications or products or the application or use by customer s third party customer s Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer s NXP does not accept any liability
65. e of at least Viigus 200 mV LPC1759 58 56 54 52 51 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 49 of 80 NXP Semiconductors LPC1 759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller 12 3 Internal oscillators Table 11 Dynamic characteristic internal oscillators Tamb 40 C to 85 C 27V lt Vpp REG 3V3 8 6 VLI Symbol Parameter Conditions Min Typ Max Unit fosc RC internal RC oscillator frequency 3 96 4 02 4 04 MHz fiRTO RTC input frequency 32 768 kHz 1 Parameters are valid over operating temperature range unless otherwise specified 2 Typical ratings are not guaranteed The values listed are at room temperature 25 C nominal supply voltages 4 036 002aaf107 fosc RC MHz 4 032 4 028 VpD REG 3V3 3 6 V 3 3V 4 024 4 020 4 016 40 15 10 35 60 85 temperature C Conditions Frequency values are typical values 4 MHz 1 96 accuracy is guaranteed for 2 7 V Vpp REG av3 3 6 V and Tamb 40 C to 85 C Variations between parts may cause the IRC to fall outside the 4 MHz 1 96 accuracy specification for voltages below 2 7 V Fig 15 Internal RC oscillator frequency versus temperature 12 4 l O pins Table 12 Dynamic characterist
66. ect to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 56 of 80 NXP Semiconductors LPC1759 58 56 54 52 51 12 8 USB interface 32 bit ARM Cortex M3 microcontroller Table 16 Dynamic characteristics USB pins full speed C 50 pF Rou 1 5 kQ on D to Vpp 3v3 30 V lt Vpp ava 3 6 V Symbol Parameter Conditions Min Typ Max Unit tr rise time 10 to 90 8 5 13 8 ns tr fall time 10 to 90 96 7 7 13 7 ns tFRFM differential rise and fall time tr t 109 96 matching Vcns output signal crossover voltage 1 3 2 0 V tFEOPT source SEO interval of EOP see Figure 21 160 175 ns tFpEoP source jitter for differential transition see Figure 21 2 5 ns to SEO transition Uni receiver jitter to next transition 18 5 18 5 ns tJR2 receiver jitter for paired transitions 10 to 90 9 9 ns tEoPR1 EOP width at receiver must reject as Ol 40 ns EOP see Figure 21 TEOPR2 EOP width at receiver must accept as 0 182 ns EOP see Figure 21 1 Characterized but not implemented as production test Guaranteed by design differential data lines Fig 21 TPERIOD 2 crossover point A differential data to crossover point extended ae SEO EOP skew n x TPERIOD tFDEOP Differential data to EOP transition skew and EOP width
67. emiconductors LPC1 759 58 56 54 52 51 15 4 LPC1759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller order to keep the noise coupled in via the PCB as small as possible Also parasitics should stay as small as possible Values of C44 and Cys should be chosen smaller accordingly to the increase in parasitics of the PCB layout Standard I O pin configuration Figure 36 shows the possible pin modes for standard I O pins with analog input function Digital output driver Open drain mode enabled disabled Digital input Pull up enabled disabled e Digital input Pull down enabled disabled Digital input Repeater mode enabled disabled Analog input The default configuration for standard I O pins is input with pull up enabled The weak MOS devices provide a drive capability equivalent to pull up and pull down resistors VDD VDD open drain enable T pin configured output enable oE RUE ESD as digital output driver data output E strong pull down ESD Vss VDD IE weak pull up pull up enable repeater mode Bi 1 1 weak pin configured J M enable E pull down as digital input pull down enable data input lt l 4 L o select analog input pin configured loa i as analog input analog input Rg 002aaf272 Fig 36 Standard I O pin configuration with analog input All information p
68. f 275 MHz to 550 MHz The multiplier works by dividing the CCO output by the value of M then using a phase frequency detector to compare the divided CCO output to the multiplier input The error value is used to adjust the CCO frequency The PLLO is turned off and bypassed following a chip Reset and by entering Power down mode PLLO is enabled by software only The program must configure and activate the PLLO wait for the PLLO to lock and then connect to the PLLO as a clock source USB PLL PLL1 The LPC 1759 58 56 54 52 51 contain a second dedicated USB PLL1 to provide clocking for the USB interface The PLL1 receives its clock input from the main oscillator only and provides a fixed 48 MHz clock to the USB block only The PLL1 is disabled and powered off on reset If the PLL1 is left disabled the USB clock will be supplied by the 48 MHz clock from the main PLLO The PLL1 accepts an input clock frequency in the range of 10 MHz to 25 MHz only The input frequency is multiplied up the range of 48 MHz for the USB clock using a Current Controlled Oscillators CCO It is insured that the PLL1 output has a 50 duty cycle Wake up timer The LPC1759 58 56 54 52 51 begin operation at power up and when awakened from Power down mode by using the 4 MHz IRC oscillator as the clock source This allows chip operation to resume quickly If the main oscillator or the PLL is needed by the application software will need to enable these features and w
69. f 80 NXP Semiconductors LPC1759 58 56 54 52 51 17 Soldering 32 bit ARM Cortex M3 microcontroller Footprint information for reflow soldering of LQFP80 package SOT315 1 EI Hx gt E Gx gt gt P2 je gt P1 kK 0 UR p UA BUR md gu 7 NN A A A A A A A A J ET MEN ZZ 272 E EE ZZ ZZ E ZZ ZA 1 ZZ ZZ 2d ees Hy Gy ZZ ZZA By Ay RE ER EA A Ys er ER ica LZ LZ a a tadcaies amm ZA ZZA pee E ro tecc ZZZ ZZ E pem I r 3Beaasguaasgeumas r C A l i H Hi pi Wi i EEEE E ee i D2 8x J I lt D1 E Bx gt lt Ax gt Generic footprint pattern Refer to the package outline drawing for actual layout A solder land Occupied area DIMENSIONS in mm P1 P2 Ax Ay Bx By C D1 D2 Gx Gy Hx Hy 0 500 0 560 15 300 15 300 12 300 12 300 1 500 0 280 0 400 12 500 12 500 15 550 15 550 P Fig 39 Reflow soldering for the LQFP80 package LPC1759 58 56 54 52 51 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 73 of 80 NXP Semiconductors LPC1 759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller 18 Abbreviations Table 25 Abbreviations
70. g voltage on outputs in 3 state mode 21 Vbp sva supply voltage 2 4 V 22 3 state outputs go into 3 state mode in Deep power down mode 23 Allowed as long as the current limit does not exceed the maximum current allowed by the device 24 Includes external resistors of 33 Q 1 96 on D and D 11 1 Power consumption 400 002aaf568 IDD Reg 3V3 uA 350 3 6V 3 3V 24V 300 250 200 40 15 10 35 60 85 temperature C Conditions Vpp Reg 3V3 3 3 V BOD disabled Fig 6 Deep sleep mode Typical regulator supply current Ipp reg 3v3 Versus temperature LPC1759 58 56 54 52 51 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 43 of 80 NXP Semiconductors LPC1759 58 56 54 52 51 LPC1759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller 120 002aaf569 IDD Reg 3V3 uA i 3 6V 3 3V 24V 40 0 40 15 10 35 60 85 temperature C Conditions Vpp Reg 3V3 3 3 V BOD disabled Fig 7 Power down mode Typical regulator supply current Ipp Reg 3v3 Versus temperature 18 002aag119 IBAT Vi VBAT 3 6 V uA 3 3V 3 0V 24V 14 1 0 0 6 40 15 10 35 60 85 temperature C Conditions Vpp aEay sva floating RTC running Fig 8 Deep
71. he USB specification revision 2 0 Full speed and Low speed mode only This pad is not 5 V tolerant 5 5 V tolerant pad with 10 ns glitch filter providing digital I O functions with TTL levels and hysteresis This pin is pulled up to a voltage level of 2 3 V to 2 6 V 6 5 V tolerant pad with TTL levels and hysteresis Internal pull up and pull down resistors disabled 7 5 V tolerant pad with TTL levels and hysteresis and internal pull up resistor 8 5 V tolerant pad with 20 ns glitch filter providing digital I O function with TTL levels and hysteresis 9 Pad provides special analog functionality 32 kHz crystal oscillator must be used with the RTC 10 When the system oscillator is not used connect XTAL1 and XTAL2 as follows XTAL1 can be left floating or can be grounded grounding is preferred to reduce susceptibility to noise XTAL2 should be left floating 11 When the RTC is not used connect VBAT to Vpp nec ava and leave RTCX1 floating LPC1759 58 56 54 52 51 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 13 of 80 NXP Semiconductors LPC1 759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller 8 Functional description LPC1759 58 56 54 52 51 8 1 8 2 8 3 8 4 Architectural overview The ARM Cortex M3 includes three AHB Lite buses the system bus the I code bus and the
72. ic I O pinsl l Tamb 40 C to 85 C Vpp aya over specified ranges Symbol Parameter Conditions Min Typ Max Unit tr rise time pin configured as output 3 0 5 0 ns tr fall time pin configured as output 2 5 5 0 ns 1 Applies to standard port pins LPC1759 58 56 54 52 51 All information provided in this document is subject to legal disclaimers Product data sheet Rev 8 6 18 August 2015 NXP Semiconductors N V 2015 All rights reserved 50 of 80 NXP Semiconductors LPC1 759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller 12 5 I C bus Table 13 Dynamic characteristic I2C bus pinsl l Tamb 40 C to 85 C 2l Symbol Parameter Conditions Min Max Unit fscL SCL clock Standard mode 0 100 kHz frequency Fast mode 0 400 kHz t fall time SIIISIIE of both SDA and 300 ns SCL signals Standard mode Fast mode 20 0 1xCp 1300 ns tlow LOW period of Standard mode 4 7 us the SCL clock Fast mode 1 3 us tHIGH HIGH period of Standard mode 4 0 us the SCL clock Fast mode 0 6 us tHp DAT data hold time 3I78 Standard mode 0 us Fast mode 0 us tsu DAT data set up 9 Standard mode 250 ns time Fast mode 100 ns 9 LPC1759_58_56_54_52_51 See the I2C bus specification UM10204 for details Parameters are valid over operating temperature range unless otherwise specified A device must
73. iconductors LPC1 759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller Table 7 Static characteristics continued Tamb 40 C to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Oscillator pins Vi XTAL1 input voltage on pin 0 5 1 8 1 95 V XTAL1 Vo XTAL2 output voltage on pin 0 5 1 8 1 95 V XTAL2 Vi RTCX1 input voltage on pin 0 5 3 6 V RTOX1 Vo RTCX2 output voltage on pin 0 5 3 6 V RTCX2 USB pins loz OFF state output OV lt V lt 3 3V 2 10 uA current VBus bus supply voltage 2 5 25 V Vpi differential input D D 2 0 2 V sensitivity voltage VcM differential common includes Vp range 21 0 8 2 5 V mode voltage range Vih rs se single ended receiver 1 10 8 2 0 V switching threshold voltage VoL LOW level output Ri of 1 5 KQ to 3 6 V 2 0 18 V voltage for low full speed Vou HIGH level output Ri of 15 kQ to GND 21 2 8 3 5 V voltage driven for low full speed Cirans transceiver capacitance pin to GND 2 20 pF Zprv driver output with 33 Q series resistor 224 36 44 1 Q impedance for driver steady state drive which is not high speed capable 1 Typical ratings are not guaranteed The values listed are at room temperature 25 C nominal supply voltages 2 For USB operation 3 0 V lt Vpp ava lt 3 6 V Guaranteed by design
74. idth to attached devices through a token based protocol The bus supports hot plugging and dynamic configuration of the devices All transactions are initiated by the host controller The LPC1759 58 56 54 USB interface includes a device Host and OTG controller with on chip PHY for device and Host functions The OTG switching protocol is supported through the use of an external controller Details on typical USB interfacing solutions can be found in Section 15 1 The LPC1752 51 include a USB device controller only USB device controller The device controller enables 12 Mbit s data exchange with a USB Host controller It consists of a register interface serial interface engine endpoint buffer memory and a DMA controller The serial interface engine decodes the USB data stream and writes data to the appropriate endpoint buffer The status of a completed USB transfer or error condition is indicated via status registers An interrupt is also generated if enabled When enabled the DMA controller transfers data between the endpoint buffer and the on chip SRAM Features Fully compliant with USB 2 0 specification full speed Supports 32 physical 16 logical endpoints with a 4 kB endpoint buffer RAM Supports Control Bulk Interrupt and Isochronous endpoints Scalable realization of endpoints at run time Endpoint Maximum packet size selection up to USB maximum specification by software at run time e Supports SoftConnect and
75. inimize noise and error This voltage is used to power the ADC and DAC This pin should be tied to 3 3 V if the ADC and DAC are not used VREFP 10 l ADC positive reference voltage This should be nominally the same voltage as Vppa but should be isolated to minimize noise and error Level on this pin is used as a reference for ADC and DAC This pin should be tied to 3 3 V if the ADC and DAC are not used VREFN 12 l ADC negative reference voltage This should be nominally the same voltage as Vss but should be isolated to minimize noise and error Level on this pin is used as a reference for ADC and DAC VBAT 1611 l RTC pin power supply 3 3 V on this pin supplies the power to the RTC peripheral 1 5 V tolerant pad providing digital I O functions with TTL levels and hysteresis This pin is pulled up to a voltage level of 2 3 V to 2 6 V 2 5 V tolerant pad providing digital I O functions with TTL levels and hysteresis and analog input When configured as a ADC input digital section of the pad is disabled and the pin is not 5 V tolerant This pin is pulled up to a voltage level of 2 3 V to 2 6 V 3 5V tolerant pad providing digital I O with TTL levels and hysteresis and analog output function When configured as the DAC output digital section of the pad is disabled This pin is pulled up to a voltage level of 2 3 V to 2 6 V 4 Pad provides digital I O and USB functions It is designed in accordance with t
76. internally provide a hold time of at least 300 ns for the SDA signal with respect to the Vin min of the SCL signal to bridge the undefined region of the falling edge of SCL Cp total capacitance of one bus line in pF The maximum t for the SDA and SCL bus lines is specified at 300 ns The maximum fall time for the SDA output stage t is specified at 250 ns This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA SCL bus lines without exceeding the maximum specified ty In Fast mode Plus fall time is specified the same for both output stage and bus timing If series resistors are used designers should allow for this when considering bus timing tHD DAT is the data hold time that is measured from the falling edge of SCL applies to data in transmission and the acknowledge The maximum typ pat could be 3 45 us and 0 9 us for Standard mode and Fast mode but must be less than the maximum of typ pAr Or typ Ack by a transition time see the I2C bus specification UM10204 This maximum must only be met if the device does not stretch the LOW period ti ow of the SCL signal If the clock stretches the SCL the data must be valid by the set up time before it releases the clock tSU DAT is the data set up time that is measured with respect to the rising edge of SCL applies to data in transmission and the acknowledge All information provided in this document is subject to legal disclaimers NXP Se
77. ion 32 bit ARM Cortex M3 microcontroller 7 1 Pinning Fig 2 Pin configuration LQFP80 package 002aae158 7 2 Pin description Table 4 Pin description Symbol Pin Type Description PO 0 to PO 31 VO Port 0 Port 0 is a 32 bit I O port with individual direction controls for each bit The operation of Port 0 pins depends upon the pin function selected via the pin connect block Some port pins are not available on the LQFP80 package PO OV RD1 TXD3 3701 VO PO 0 General purpose digital input output pin SDA1 l RD1 CAN1 receiver input O TXD3 Transmitter output for UART3 1 0 SDA1 I C1 data input output this is not an 1 C bus compliant open drain pin POMyTD1 RXDS3 38l VO PO 1 General purpose digital input output pin SCL1 O TD1 CAN1 transmitter output l RXD3 Receiver input for UART3 1 0 SCL1 I C1 clock input output this is not an 1 C bus compliant open drain pin Po 2 TXD0 AD0 7 798 VO PO 2 General purpose digital input output pin O TXDO Transmitter output for UARTO l ADO 7 A D converter 0 input 7 PO 3 RXDO ADO 6 80 2 VO PO 3 General purpose digital input output pin l RXDO Receiver input for UARTO l ADO 6 A D converter 0 input 6 PO 6 641 VO PO 6 General purpose digital input output pin I2SRX_SDA yo I2SRX SDA Receive data It is driven by the transmitter and read
78. it Ep differential linearity error l8 1 LSB Eig integral non linearity 4 1 5 LSB Eo offset error 5 2 LSB Eg gain error 6 2 LSB fak Apc ADC clock frequency 3 0 V lt VppA 3 6 V 33 MHz 2 7 V lt Vppa lt 3 0 V z gt 25 MHz fapc ADC conversion frequency 3 V lt VppA lt 3 6 V p 500 kHz 2 7 V lt npa lt 3 0 V 400 kHz 1 Vppa and VREFP should be tied to Vpp ava if the ADC and DAC are not used 2 The ADC is monotonic there are no missing codes 3 The differential linearity error Ep is the difference between the actual step width and the ideal step width See Figure 26 4 The integral non linearity E aq is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors See Figure 26 5 The offset error Eo is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve See Figure 26 6 The gain error Eg is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error and the straight line which fits the ideal transfer curve See Figure 26 7 The conversion frequency corresponds to the number of samples per second LPC1759 58 56 54 52 51 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015
79. me in SPI mode 16 1 ns tpH data hold time in SPI mode 0 ns twa data output valid time in SPI mode 2 5 ns tha data output hold time in SPI mode 0 ns SSP slave tps data set up time in SPI mode 16 1 ns tou data hold time in SPI mode 0 ns twa data output valid time in SPI mode 3 Toy PCLK 2 5 ns tha data output hold time in SPI mode 0 ns Toy clk SCK CPOL 0 SCK CPOL 1 A I tQ lt tha MOSI DATAVALID DATA VALID tps tpH CPHA 1 MISO DATA VALID DATA VALID twa gt tha MOSI DATA VALID DATA VALID tos tpH CPHA 0 MISO DATA VALID DATA VALID 002aae829 Fig 19 SSP master timing in SPI mode All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 55 of 80 NXP Semiconductors LPC1 759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller Toy clk SCK CPOL 0 SCK CPOL 1 tps tbH M e Bn MOSI DATA VALID DATA VALID twa lt tha CPHA 1 MISO DATA VALID DATA VALID tps tDH r r MOSI DATA VALID DATA VALID twa gt tna CPHA 0 MISO DATA VALID DATAVALID 002aae830 Fig 20 SSP slave timing in SPI mode LPC1759 58 56 54 52 51 All information provided in this document is subj
80. miconductors LPC1 759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller TsPICYC tsPICLKH tSPICLKL lt 4 gt a SCK CPOL 0 SCK CPOL 1 y tsPIDSU tsPIDH gt 4 MOSI DATA VALID DATA VALID isPIQV 4 tsPIOH MISO DATA VALID DATA VALID 002aad989 Fig 25 SPI slave timing CPHA 0 13 ADC electrical characteristics Table 18 ADC characteristics full resolution Vppa 2 5 V to 3 6 V Tamb 40 C to 85 C unless otherwise specified ADC frequency 13 MHz 12 bit resolution Symbol Parameter Conditions Min Typ Max Unit ViA analog input voltage 0 VppA V Cia analog input capacitance 15 pF Ep differential linearity error l8 1 LSB EL adj integral non linearity 4 3 LSB Eo offset error 516 2 LSB Eg gain error Ul 0 5 96 Er absolute error 8 4 LSB Rysi voltage source interface 9 7 5 kQ resistance folk ADC ADC clock frequency 13 MHz c ADC ADC conversion frequency 10 200 kHz 1 Vppa and VREFP should be tied to Vpp ava if the ADC and DAC are not used 2 The ADC is monotonic there are no missing codes 3 The differential linearity error Ep is the difference between the actual step width and the ideal step width See Figure 26 4 The integral non linearity E aq is the peak diffe
81. miconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 51 of 80 NXP Semiconductors LPC1 759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller tsu DAT SDA SCL blue ar 1 002aa 425 Fig 16 I C bus pins clock timing LPC1759 58 56 54 52 51 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 52 of 80 NXP Semiconductors LPC1 759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller 12 6 1 S bus interface LPC1759 58 56 only Table 14 Dynamic characteristics I S bus interface pins Tamb 40 C to 85 C Symbol Parameter Conditions Min Typ Max Unit common to input and output tr rise time 0o l 35 ns ti fall time mo l 35 ns twH pulse width HIGH on pins I2STX_CLKand H 0 495 x Tey cik I2SRX_CLK twL pulse width LOW on pins I2STX_CLKand H 0 505 x Tey cik NS I2SRX_CLK output tva data output valid time on pin I2STX_SDA mo l 30 ns on pin I2STX_WS uo l 30 ns input tsu D data input set up time on pin I2SRX_SDA 0 13 5 ns th D data input hold time on pin I2SRX_SDA Ol 40 ns 1 CCLK 20 MHz peripheral clock to the I S bus interface PCLK CCK Toy 1600 ns corresponds to the SCK signal in the S bus s
82. nal and I O power dissipation The internal power dissipation is the product of Ipp and Vpp The I O power dissipation of the I O pins is often small and many times can be negligible However it can be significant in some applications Table 6 Thermal resistance 15 Symbol Parameter Conditions Max Min Unit LQFP80 Raja thermal resistance from JEDEC 4 5 in x 4 in still air 39 46 C W junction to ambient Single layer 4 5 in x 3 in still air 59 39 C W Race thermal resistance from 6 769 C W junction to case LPC1759_58_56_54_52_51 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 39 of 80 NXP Semiconductors LPC1759 58 56 54 52 51 11 Static characteristics 32 bit ARM Cortex M3 microcontroller Table 7 Static characteristics Tamb 40 C to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Supply pins Vpp 3v3 supply voltage 3 3 V external rail 2 2 4 3 3 3 6 V VDD REG 3V3 regulator supply voltage 2 4 3 3 3 6 V 3 3 V VDDA analog 3 3 V pad supply ISI4 2 5 3 3 3 6 V voltage Vi vBAT input voltage on pin DI 12 1 3 3 3 6 V VBAT Vi VREFP input voltage on pin BI 2 5 3 3 VppA V VREFP Ipp REG 3V3 regulator supply current active mode code 3 3 V while 1 e
83. nal interrupt generation Reset timer on match with optional interrupt generation Up to four external outputs corresponding to match registers with the following capabilities Set LOW on match Set HIGH on match Toggle on match All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 25 of 80 NXP Semiconductors LPC1 759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller Do nothing on match Up to two match registers can be used to generate timed DMA requests 8 22 Pulse width modulator The PWM is based on the standard Timer block and inherits all of its features although only the PWM function is pinned out on the LPC1759 58 56 54 52 51 The Timer is designed to count cycles of the system derived clock and optionally switch pins generate interrupts or perform other actions when specified timer values occur based on seven match registers The PWM function is in addition to these features and is based on match register events The ability to separately control rising and falling edge locations allows the PWM to be used for more applications For instance multi phase motor control typically requires three non overlapping PWM outputs with individual control of all three pulse widths and positions Two match registers can be used to provide a single edge controlled PWM output
84. ned as read only and detecting unexpected memory accesses that could potentially break the system The MPU separates the memory into distinct regions and implements protection by preventing disallowed accesses The MPU supports up to 8 regions each of which can be divided into 8 subregions Accesses to memory locations that are not defined in the MPU regions or not permitted by the region setting will cause the Memory Management Fault exception to take place Memory map The LPC1759 58 56 54 52 51 incorporate several distinct memory regions shown in the following figures Figure 3 shows the overall map of the entire address space from the user program viewpoint following reset The interrupt vector area supports address remapping The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals The APB peripheral area is 1 MB in size and is divided to allow for up to 64 peripherals Each peripheral of either type is allocated 16 kB of space This allows simplifying the address decoding for each peripheral All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 15 of 80 v o o o E Qa i e o z o c Glog 1snDny gi 9 8 eH sieuirejosip Jea 0 joefqns s jueuinoop siui ui pepi oid uoneuuojul Iv 08 JO OL LS ZS vS 9S 8S 6S 10d1 pamasa SUU Il S LO
85. neral purpose digital input output pin PWM1 2 SCKO l MCIO Motor control PWM channel 0 input Also Quadrature Encoder Interface PHA input O PWM1 2 Pulse Width Modulator 1 channel 2 output I O SCKO Serial clock for SSPO P1 22 MCOBO 2801 y o P1 22 General purpose digital input output pin an O MCOBO Motor control PWM channel 0 output B I USB_PWRD Power Status for USB port host power switch LPC1759 58 56 54 only O MAT1 0 Match output for Timer 1 channel 0 P1 23 MCI1 2901 y o P1 23 General purpose digital input output pin PWM1 4 MISOO MCI1 Motor control PWM channel 1 input Also Quadrature Encoder Interface PHB input O PWM1 4 Pulse Width Modulator 1 channel 4 output 1 0 MISOO Master In Slave Out for SSPO P1 24 MCI2 301 y o P1 24 General purpose digital input output pin PWM1 5 MOSIO MCI2 Motor control PWM channel 2 input Also Quadrature Encoder Interface INDEX input O PWM1 5 Pulse Width Modulator 1 channel 5 output I O MOSIO Master Out Slave in for SSPO P1 25 MCOA1 314 y o P1 25 General purpose digital input output pin MATI 1 O MCOA1 Motor control PWM channel 1 output A O MAT1 1 Match output for Timer 1 channel 1 P1 26 MCOB1 3a VO P1 26 General purpose digital input output pin PWMTISJ CAPO O O MCOB1 Motor control PWM channel 1 output B O PWM1 6 Pulse Width Modulator 1 channel 6 output CA
86. nformation NXP Semiconductors N V 2015 For more information please visit http Awww nxp com For sales office addresses please send an email to salesaddresses nxp com All rights reserved Date of release 18 August 2015 Document identifier LPC1759 58 56 54 52 51
87. ng reset starts the ISP command handler l EINTO External interrupt 0 input l NMI Non maskable interrupt input P4 0 to P4 31 y o Port 4 Port 4 is a 32 bit I O port with individual direction controls for each bit The operation of port 4 pins depends upon the pin function selected via the pin connect block Some port pins are not available on the LQFP80 package PA P8 RX MCLK 65l l VO P4 28 General purpose digital input output pin MAT2 0 TXD3 O RX_MCLK 2S receive master clock LPC1759 58 56 only O MAT2 0 Match output for Timer 2 channel 0 O TXD3 Transmitter output for UART3 P4 29 TX_MCLK 68 y o P4 29 General purpose digital input output pin MAT2 1yRXD3 O TX MCLK 2S transmit master clock LPC1759 58 56 only O MAT2 1 Match output for Timer 2 channel 1 l RXD3 Receiver input for UART3 TDO SWO 1 6 O TDO Test Data out for JTAG interface O SWO Serial wire trace output TDI 20 TDI Test Data in for JTAG interface TMS SWDIO 3 l TMS Test Mode Select for JTAG interface VO SWDIO Serial wire debug data input output TRST 417 l TRST Test Reset for JTAG interface TCK SWDCLK 516 l TCK Test Clock for JTAG interface l SWDCLK Serial wire clock RSTOUT 11 O RSTOUT This is a 3 3 V pin LOW on this pin indicates LPC1759 58 56 54 52 51 being in Reset state RESET 14
88. o the CPU allows for low interrupt latency and efficient processing of late arriving interrupts Features Controls system exceptions and peripheral interrupts n the LPC1759 58 56 54 52 51 the NVIC supports 33 vectored interrupts 32 programmable interrupt priority levels with hardware priority level masking Relocatable vector table Non Maskable Interrupt NMI Software interrupt generation Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags Individual interrupt flags may also represent more than one interrupt Source Any pin on Port 0 and Port 2 total of 30 pins regardless of the selected function can be programmed to generate an interrupt on a rising edge a falling edge or both Pin connect block The pin connect block allows selected pins of the microcontroller to have more than one function Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals Peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt s being enabled Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined Most pins can also be configured as open drain outputs or to have a pull up pull down or no resistor enabled General purpose DMA controller The GPDMA is an AMBA AHB compliant peripheral allo
89. on CRP3 is selected no future factory testing can be performed on the device 8 30 4 APB interface The APB peripherals are split into two separate APB buses in order to distribute the bus bandwidth and thereby reducing stalls caused by contention between the CPU and the GPDMA controller 1 LPC1751FBD80 with device ID 25001110 does not support CRP feature LPC1751FBD80 with device ID 25001118 does support CRP See errata note in ES LPC1751 LPC1759 58 56 54 52 51 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 36 of 80 NXP Semiconductors LPC1 759 58 56 54 52 51 8 30 5 8 30 6 8 30 7 8 31 LPC1759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller AHB multilayer matrix The LPC1759 58 56 54 52 51 use an AHB multilayer matrix This matrix connects the instruction I code and data D code CPU buses of the ARM Cortex MS to the flash memory the main 32 kB static RAM and the Boot ROM The GPDMA can also access all of these memories The peripheral DMA controllers Ethernet LPC1758 only and USB can access all SRAM blocks Additionally the matrix connects the CPU system bus and all of the DMA controllers to the various peripheral functions External interrupt inputs The LPC1759 58 56 54 52 51 include up to 30 edge sensitive interrupt inputs combined with one level sensi
90. onization allows devices with different bit rates to communicate via one serial bus Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer The l C bus can be used for test and diagnostic purposes Both I C bus controllers support multiple address recognition and a bus monitor mode 8 20 I S bus serial I O controllers LPC1759 58 56 only LPC1759 58 56 54 52 51 The I S bus provides a standard communication interface for digital audio applications All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 24 of 80 NXP Semiconductors LPC1 759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller The S bus specification defines a 3 wire serial bus using one data line one clock line and one word select signal The basic 12S connection has one master which is always the master and one slave The I S bus interface provides a separate transmit and receive channel each of which can operate as either a master or a slave 8 20 1 Features The interface has separate input output channels each of which can operate in master or slave mode Capable of handling 8 bit 16 bit and 32 bit word sizes Mono and stereo audio data supported The sampling frequency can range from 16 kHz to 96 kHz 16 22 05 32 44 1 48 96 kHz Support for an audio master
91. pecification lPSTX CLK I STX SDA iy tv Q Pa I2STX WS 002aad992 Fig 17 I S bus timing output LPC1759 58 56 54 52 51 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 53 of 80 NXP Semiconductors LPC1759 58 56 54 52 51 LPC1759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller I2SRX_CLK I2SRX SDA I2ZSRX WS I tsu D gt lt th D 002aae 159 i tsu D gt Fig 18 I S bus timing input tsu D All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 54 of 80 NXP Semiconductors LPC1 759 58 56 54 52 51 LPC1759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller 12 7 SSP interface The maximum SSP speed is 33 Mbit s in master mode or 8 Mbit s in slave mode In slave mode the maximum SSP clock rate must be 1 12 of the SSP PCLK clock rate Table 15 Dynamic characteristics SSP pins in SPI mode C 30 pF on all SSP pins Tamb 40 C to 85 C Vpp sya 3 3 V to 3 6 V input slew 1 ns sampled at 10 and 90 of the signal level Values guaranteed by design Symbol Parameter Conditions Min Max Unit SSP master tps data set up ti
92. pin function selected via the pin connect block Some port pins are not available on the LQFP80 package P2 O PWM1 1 eoi VO P2 0 General purpose digital input output pin TXD1 O PWM1 1 Pulse Width Modulator 1 channel 1 output O TXD1 Transmitter output for UART1 P2 1 PWM1 2 590 y o P2 1 General purpose digital input output pin RXD1 O PWM1 2 Pulse Width Modulator 1 channel 2 output l RXD1 Receiver input for UART1 P2 2 PWM1 3 58 y o P2 2 General purpose digital input output pin CTS1 O PWM1 3 Pulse Width Modulator 1 channel 3 output TRACEDATA S3 l CTS1 Clear to Send input for UART1 O TRACEDATA 3 Trace data bit 3 P2 S PWMt1 4 5511 VO P2 3 General purpose digital input output pin DCD1 O PWM1 4 Pulse Width Modulator 1 channel 4 output TRACEDATA 2 l DCD1 Data Carrier Detect input for UART1 O TRACEDATA 2 Trace data bit 2 P2 4 PWM1 5 540 y o P2 4 General purpose digital input output pin DSR1 O PWM1 5 Pulse Width Modulator 1 channel 5 output TRACEDATA 1 l DSR1 Data Set Ready input for UART1 O TRACEDATA 1 Trace data bit 1 P2 5 PWM1 6 53l y o P2 5 General purpose digital input output pin DTR1 O PWM1 6 Pulse Width Modulator 1 channel 6 output TRACEDATA 0 O DTR1 Data Terminal Ready output for UART1 Can also be configure
93. pport battery powered systems Provides Seconds Minutes Hours Day of Month Month Year Day of Week and Day of Year Dedicated power supply pin can be connected to a battery or to the main 3 3 V Periodic interrupts can be generated from increments of any field of the time registers Backup registers 20 bytes powered by VBAT RTC power supply is isolated from the rest of the chip Clocking and power control Crystal oscillators The LPC1759 58 56 54 52 51 include three independent oscillators These are the main oscillator the IRC oscillator and the RTC oscillator Each oscillator can be used for more than one purpose as required in a particular application Any of the three clock sources can be chosen by software to drive the main PLL and ultimately the CPU Following reset the LPC1759 58 56 54 52 51 will operate from the Internal RC oscillator until switched by software This allows systems to operate without any external crystal and the bootloader code to operate at a known frequency See Figure 4 for an overview of the LPC1759 58 56 54 52 51 clock generation All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 29 of 80 NXP Semiconductors LPC1 759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller L r1 LPC17xx USB PLL usbelk USB 48 MHz Em MAIN CL
94. r control PWM The motor control PWM is a specialized PWM supporting 3 phase motors and other combinations Feedback inputs are provided to automatically sense rotor position and use that information to ramp speed up or down At the same time the motor control PWM is highly configurable for other generalized timing counting capture and compare applications Quadrature Encoder Interface QEI A quadrature encoder also known as a 2 channel incremental encoder converts angular displacement into two pulse signals By monitoring both the number of pulses and the relative phase of the two signals the user can track the position direction of rotation and velocity In addition a third channel or index signal can be used to reset the position counter The quadrature encoder interface decodes the digital pulses from a quadrature encoder wheel to integrate position over time and determine direction of rotation In addition the QEI can capture the velocity of the encoder wheel Features Tracks encoder position e ncrements decrements depending on direction Programmable for 2x or 4x position counting Velocity capture using built in timer Velocity compare function with less than interrupt Uses 32 bit registers for position and velocity Three position compare registers with interrupts Index counter for revolution counting e Index compare register with interrupts Can combine index and position interrupts to pro
95. re not included in this figure Table 20 ADC interface components Component Range Description Ri 2 kQ to 5 2 kQ Switch on resistance for channel selection switch Varies with temperature input voltage and process Rio 100 Q to 600 Q Switch on resistance for the comparator input switch Varies with temperature input voltage and process C1 750 fF Parasitic capacitance from the ADC block level C2 65 fF Parasitic capacitance from the ADC block level C3 2 2 pF Sampling capacitor 14 DAC electrical characteristics LPC1759 58 56 54 only Table 21 DAC electrical characteristics VppA 2 7 V to 3 6 V Tamb 40 C to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Ep differential linearity error 1 LSB EL agi integral non linearity t1 5 LSB Eo offset error 0 6 96 Ec gain error s 0 6 E 96 CL load capacitance 200 pF RL load resistance 1 kQ LPC1759 58 56 54 52 51 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 63 of 80 NXP Semiconductors LPC1 759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller 15 Application information 15 1 Suggested USB interface solutions If the LPC1759 58 56 54 52 51 Vpp is always greater than 0 V while Vg
96. red SRAM DMA managers with scatter gather DMA and arrays of frame descriptors Memory traffic optimized by buffering and pre fetching Enhanced Ethernet features All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 19 of 80 NXP Semiconductors LPC1 759 58 56 54 52 51 8 12 8 12 1 8 12 1 1 LPC1759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller Receive filtering Multicast and broadcast frame support for both transmit and receive Optional automatic Frame Check Sequence FCS insertion with Cyclic Redundancy Check CRC for transmit Selectable automatic transmit frame padding Over length frame support for both transmit and receive allows any length frames Promiscuous receive mode Automatic collision back off and frame retransmission Includes power management by clock switching Wake on LAN power management support allows system wake up using the receive filters or a magic frame detection filter Physical interface Attachment of external PHY chip through standard RMII interface PHY register access is available via the MIIM interface USB interface The Universal Serial Bus USB is a 4 wire bus that supports communication between a host and one or more up to 127 peripherals The host controller allocates the USB bandw
97. removal or replacement of any products or rework charges whether or not such damages are based on tort including negligence warranty breach of contract or any other legal theory Notwithstanding any damages that customer might incur for any reason whatsoever NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof LPC1759 58 56 54 52 51 All information provided in this document is subject to legal disclaimers Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in life support life critical or safety critical systems or equipment nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury death or severe property or environmental damage NXP Semiconductors and its suppliers accept no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is at th
98. rence between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors See Figure 26 5 The offset error Eo is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve See Figure 26 6 ADCOFFS value bits 7 4 2 in the ADTRM register See LPC17xx user manual UM10360 7 The gain error Eg is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error and the straight line which fits the ideal transfer curve See Figure 26 8 The absolute error Er is the maximum difference between the center of the steps of the actual transfer curve of the non calibrated ADC and the ideal transfer curve See Figure 26 9 See Figure 27 10 The conversion frequency corresponds to the number of samples per second LPC1759 58 56 54 52 51 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 60 of 80 NXP Semiconductors LPC1759 58 56 54 52 51 Table 19 ADC characteristics lower resolution Tamb 40 C to 85 C unless otherwise specified 12 bit ADC used as 10 bit resolution ADC l 1 32 bit ARM Cortex M3 microcontroller Symbol Parameter Conditions Min Typ Max Un
99. rom Power down mode via any interrupt able to operate during Power down mode includes external interrupts RTC interrupt USB activity Ethernet wake up interrupt LPC1758 only CAN bus activity Port 0 2 pin interrupt and NMI Brownout detect with separate threshold for interrupt and forced reset Power On Reset POR Crystal oscillator with an operating range of 1 MHz to 25 MHz 4 MHz internal RC oscillator trimmed to 1 accuracy that can optionally be used as a system clock PLL allows CPU operation up to the maximum CPU rate without the need for a high frequency crystal May be run from the main oscillator the internal RC oscillator or the RTC oscillator USB PLL for added flexibility Code Read Protection CRP with different security levels Unique device serial number for identification purposes Available as 80 pin LQFP package 12 mm x 12 mm x 1 4 mm LPC1759 58 56 54 52 51 eMetering Lighting Industrial networking Alarm systems White goods Motor control All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 3 of 80 NXP Semiconductors LPC1759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller 4 Ordering information Table 1 Ordering information
100. rovided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 69 of 80 LPC1759 58 56 54 52 51 NXP Semiconductors 32 bit ARM Cortex M3 microcontroller 15 5 Reset pin configuration 20 ns RC reset lt i GLITCH FILTER d PIN ESD Vss 002aaf274 Fig 37 Reset pin configuration All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved 70 of 80 LPC1759 58 56 54 52 51 Product data sheet Rev 8 6 18 August 2015 NXP Semiconductors LPC1759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller 15 6 ElectroMagnetic Compatibility EMC Radiated emission measurements according to the IEC61967 2 standard using the TEM cell method are shown for part LPC1768 LPC1759 58 56 54 52 51 Table 24 ElectroMagnetic Compatibility EMC for part LPC1768 TEM cell method Vpp 3 3 V Tamb 25 C Parameter Frequency band System clock Unit 12 MHz 24 MHz 48MHz 72MHz 100 MHz Input clock IRC 4 MHz maximum 150 kHz to 30 MHz 7 6 4 7 7 dBuV peak level 30 MHz to 150 MHz 1 45 11 16 49 dBuV 150 MHz to 1 GHz 2 4 11 12 19 dBuV IEC level O O N M L Input clock crystal oscillator 12 MHz maximum 150 kHz to 30 MHz 5 4 4 7 8
101. ry 32 bit ARM Cortex M3 microcontroller Table 26 Revision history Document ID Release date Data sheet status Change notice Supersedes LPC1759 58 56 54 52 51 v 8 6 20150818 Product data sheet LPC1759 58 56 54 52 51 v 8 5 Modifications Updated max value of tq data output valid time in SPI mode to 3 TeypcLk 2 5 ns See Table 15 Dynamic characteristics SSP pins in SPI mode Updated Section 2 Features and benefits Added Boundary scan Description Language BSDL is not available for this device Updated Figure 3 LPC1759 58 56 54 52 51 memory map APBO slot 7 0x4001C000 was reserved and changed it to I2CO Added a column for GPIO pins and device order part number to the ordering options table See Table 2 Ordering options LPC1759 58 56 54 52 51 v8 5 20140624 Product data sheet LPC1759 58 56 54 52 51v 8 4 Modifications SSP timing diagram updated SSP timing parameters tyq th q tps and tpi added See Section 12 7 SSP interface SSP maximum bit rate in master mode corrected to 33 Mbit s Parameter Tjmax added in Table 5 Limiting values Description of capture channels corrected in Section 8 21 1 LPC1759 58 56 54 52 51v 8 4 20140404 Product data sheet LPC1759 58 56 54 52 51 v 8 3 Modifications Table 4 Pin description Changed RX MCLK and TX MCLK type from INPUT to OUTPUT LPC1759 58 56
102. rystal External load frequency Fosc capacitance C series resistance Rs capacitors Cx1 Cx2 1 MHz to 5 MHz 10 pF lt 300 Q 18 pF 18 pF 20 pF lt 300 Q 39 pF 39 pF 30 pF lt 300 Q 57 pF 57 pF 5 MHz to 10 MHz 10 pF lt 300 Q 18 pF 18 pF 20 pF lt 2000 39 pF 39 pF 30 pF lt 1000 57 pF 57 pF 10 MHz to 15 MHz 10 pF 1600 18 pF 18 pF 20 pF 600 39 pF 39 pF 15 MHz to 20 MHz 10 pF 800 18 pF 18 pF Table 23 Recommended values for Cy1 Cx in oscillation mode crystal and external components parameters high frequency mode Fundamental oscillation Crystal load Maximum crystal External load frequency Fosc capacitance C series resistance Rs capacitors Cxy1 Cx 15 MHz to 20 MHz 10 pF 1800 18 pF 18 pF 20 pF 1000 39 pF 39 pF 20 MHz to 25 MHz 10 pF 160 0 18 pF 18 pF 20 pF 800 39 pF 39 pF XTAL Printed Circuit Board PCB layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip Take care that the load capacitors C44 Cy and C 3 in case of third overtone crystal usage have a common ground plane The external components must also be connected to the ground plain Loops must be made as small as possible in All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 68 of 80 NXP S
103. s Maximum SSP speed of 33 Mbit s master or 8 Mbit s slave Compatible with Motorola SPI 4 wire Texas Instruments SSI and National Semiconductor Microwire buses Synchronous serial communication Master or slave operation 8 frame FIFOs for both transmit and receive 4 bit to 16 bit frame e DMA transfers supported by GPDMA I C bus serial I O controllers The LPC1759 58 56 54 52 51 each contain two I2C bus controllers The I C bus is bidirectional for inter IC control using only two wires a Serial Clock Line SCL and a Serial DAta line SDA Each device is recognized by a unique address and can operate as either a receiver only device e g an LCD driver or a transmitter with the capability to both receive and send information such as memory Transmitters and or receivers can operate in either master or slave mode depending on whether the chip has to initiate a data transfer or is only addressed The I C is a multi master bus and can be controlled by more than one bus master connected to it Features e C1 and I C2 use standard I O pins with bit rates of up to 400 kbit s Fast I C bus Easy to configure as master slave or master slave Programmable clocks allow versatile rate control Bidirectional data transfer between masters and slaves Multi master bus no central master Arbitration between simultaneously transmitting masters without corruption of serial data on the bus Serial clock synchr
104. s is not recommended and proper operation is not guaranteed The conditions for functional operation are specified in Table 7 2 Maximum minimum voltage above the maximum operating voltage see Table 7 and below ground that can be applied for a short time 10 ms to a device without leading to irrecoverable failure Failure includes the loss of reliability and shorter lifetime of the device 3 See Table 18 for maximum operating voltage 4 Including voltage on outputs in 3 state mode 5 The maximum non operating storage temperature is different than the temperature for required shelf life which should be determined based on required shelf lifetime Please refer to the JEDEC spec J STD 033B 1 for further details 6 Human body model equivalent to discharging a 100 pF capacitor through a 1 5 kO series resistor LPC1759 58 56 54 52 51 Product data sheet All information provided in this document is subject to legal disclaimers Rev 8 6 18 August 2015 NXP Semiconductors N V 2015 All rights reserved 38 of 80 NXP Semiconductors LPC1 759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller 10 Thermal characteristics 10 1 Thermal characteristics The average chip junction temperature Ty C can be calculated using the following equation T Tamo Pa Raga 1 Tamb ambient temperature C Rina the package junction to ambient thermal resistance C W e Pp sum of inter
105. t NXP Semiconductors LPC1 759 58 56 54 52 51 5 Marking 32 bit ARM Cortex M3 microcontroller LPC1759 58 56 54 52 51 The LPC175x devices typically have the following top side marking LPC175xxxx XXXXXXX xxYYWWR x The last second to last letter in the third line field R will identify the device revision This data sheet covers the following revisions of the LPC175x Table 3 Device revision table Revision identifier R Revision description Initial device revision YN Second device revision Field YY states the year the device was manufactured Field WW states the week the device was manufactured during that year All information provided in this document is subject to legal disclaimers Product data sheet NXP Semiconductors N V 2015 All rights reserved Rev 8 6 18 August 2015 5 of 80 NXP Semiconductors LPC1759 58 56 54 52 51 6 Block diagram 32 bit ARM Cortex M3 microcontroller PO P1 P2 P4 SCK1 SSEL1 MISO1 MOSI1 RXDO TXDO 8 x UART1 RD1 2 TD1 2 SCL1 SDA1 SCK SSEL MOSI MISO 2 x MATO 1 1x CAPO 2x CAP1 PWM1 6 1 PCAP1 1 0 ADO 7 2 PO P2 RTOX1 RTCX2 VBAT Fig 1 JTAG interface debug port TEST DEBUG INTERFACE ARM CORTEX M3 LLI z5 28 3 Ze ut e DMA CONTROLLER LPC1759 58 56 54 52 51 XTAL1 RMII pins USB pins XTAL2 ___ RESET CLOCK t GENERATION
106. ter only I2C bus interface to implement OTG dual role device functionality The dedicated 2C bus interface controls an external OTG transceiver Features Fully compliant with On The Go supplement to the USB 2 0 Specification Revision 1 0a Hardware support for Host Negotiation Protocol HNP Includes a programmable timer required for HNP and Session Request Protocol SRP Supports any OTG transceiver compliant with the OTG Transceiver Specification CEA 2011 Rev 1 0 CAN controller and acceptance filters The Controller Area Network CAN is a serial communications protocol which efficiently supports distributed real time control with a very high level of security Its domain of application ranges from high speed networks to low cost multiplex wiring The CAN block is intended to support multiple CAN buses simultaneously allowing the device to be used as a gateway switch or router among a number of CAN buses in industrial or automotive applications Remark LPC1754 52 51 have only one CAN bus All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 21 of 80 NXP Semiconductors LPC1 759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller 8 13 1 Features 8 14 8 14 1 8 15 8 15 1 LPC1759 58 56 54 52 51 One or two CAN controllers and buses Data rates to 1 Mbit s on each
107. the power on reset circuitry maintains the overall reset Both the 2 2 V and 1 85 V thresholds include some hysteresis In normal operation this hysteresis allows the 2 2 V detection to reliably interrupt or a regularly executed event loop to sense the condition 8 30 3 Code security Code Read Protection CRP This feature of the LPC1759 58 56 54 52 51 allows user to enable different levels of security in the system so that access to the on chip flash and use of the JTAG and ISP can be restricted When needed CRP is invoked by programming a specific pattern into a dedicated flash location IAP commands are not affected by the CRP There are three levels of the Code Read Protection CRP1 disables access to chip via the JTAG and allows partial flash update excluding flash sector 0 using a limited set of the ISP commands This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased CRP2 disables access to chip via the JTAG and only allows full flash erase and update using a reduced set of the ISP commands Running an application with level CRP3 selected fully disables any access to chip via the JTAG pins and the ISP This mode effectively disables ISP override using P2 10 pin too It is up to the user s application to provide if needed flash update mechanism using IAP calls or call reinvoke ISP command to enable flash update via UARTO CAUTION If level three Code Read Protecti
108. ther peripherals 52 General Purpose lI O GPIO pins with configurable pull up down resistors All GPIOs support a new configurable open drain operating mode The GPIO block is accessed through the AHB multilayer bus for fast access and located in memory such that it supports Cortex M3 bit banding and use by the General Purpose DMA Controller 12 bit Analog to Digital Converter ADC with input multiplexing among six pins conversion rates up to 200 kHz and multiple result registers The 12 bit ADC can be used with the GPDMA controller On the LPC1759 58 56 54 only 10 bit Digital to Analog Converter DAC with dedicated conversion timer and DMA support Four general purpose timers counters with a total of three capture inputs and ten compare outputs Each timer block has an external count input Specific timer events can be selected to generate DMA requests One motor control PWM with support for three phase motor control Quadrature encoder interface that can monitor one external quadrature encoder One standard PWM timer block with external count input Real Time Clock RTC with a separate power domain and dedicated RTC oscillator The RTC block includes 20 bytes of battery powered backup registers All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 2 of 80 NXP Semiconduc
109. tire chip with the exception of the RTC module and the RESET pin The LPC1759 58 56 54 52 51 can wake up from Deep power down mode via the RESET pin or an alarm match event of the RTC Wakeup interrupt controller The Wakeup Interrupt Controller WIC allows the CPU to automatically wake up from any enabled priority interrupt that can occur while the clocks are stopped in Deep sleep Power down and Deep power down modes The Wakeup Interrupt Controller WIC works in connection with the Nested Vectored Interrupt Controller NVIC When the CPU enters Deep sleep Power down or Deep power down mode the NVIC sends a mask of the current interrupt situation to the WIC This mask includes all of the interrupts that are both enabled and of sufficient priority to be serviced immediately With this information the WIC simply notices when one of the interrupts has occurred and then it wakes up the CPU The Wakeup Interrupt Controller WIC eliminates the need to periodically wake up the CPU and poll the interrupts resulting in additional power savings Peripheral power control A power control for peripherals feature allows individual peripherals to be turned off if they are not needed in the application resulting in additional power savings Power domains The LPC1759 58 56 54 52 51 provide two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the RTC and the backup Registers
110. tive external interrupt input as selectable pin function The external interrupt input can optionally be used to wake up the processor from Power down mode Memory mapping control The Cortex M3 incorporates a mechanism that allows remapping the interrupt vector table to alternate locations in the memory map This is controlled via the Vector Table Offset Register contained in the NVIC The vector table may be located anywhere within the bottom 1 GB of Cortex M3 address space The vector table must be located on a 128 word 512 byte boundary because the NVIC on the LPC1759 58 56 54 52 51 is configured for 128 total interrupts Emulation and debugging Debug and trace functions are integrated into the ARM Cortex M3 Serial wire debug and trace functions are supported in addition to a standard JTAG debug and parallel trace functions The ARM Cortex M3 is configured to support up to eight breakpoints and four watch points All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 37 of 80 LPC1759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller NXP Semiconductors 9 Limiting values Table 5 Limiting values In accordance with the Absolute Maximum Rating System IEC 60134 Symbol Parameter Conditions Min Max Unit Vpp 3v3 supply voltage 3 3 V external
111. tors LPC1 759 58 56 54 52 51 3 Applications 32 bit ARM Cortex M3 microcontroller WatchDog Timer WDT The WDT can be clocked from the internal RC oscillator the RTC oscillator or the APB clock ARM Cortex M3 system tick timer including an external clock input option Repetitive Interrupt Timer RIT provides programmable and repeating timed interrupts Each peripheral has its own clock divider for further power savings Standard JTAG debug interface for compatibility with existing tools Serial Wire Debug and Serial Wire Trace Port options Boundary scan Description Language BSDL is not available for this device Emulation trace module enables non intrusive high speed real time tracing of instruction execution Integrated PMU Power Management Unit automatically adjusts internal regulators to minimize power consumption during Sleep Deep sleep Power down and Deep power down modes Four reduced power modes Sleep Deep sleep Power down and Deep power down Single 3 3 V power supply 2 4 V to 3 6 V One external interrupt input configurable as edge level sensitive All pins on Port 0 and Port 2 can be used as edge sensitive interrupt sources Non maskable Interrupt NMI input The Wakeup Interrupt Controller WIC allows the CPU to automatically wake up from any priority interrupt that can occur while the clocks are stopped in Deep sleep Power down and Deep power down modes Processor wake up f
112. upported Scatter or gather DMA is supported through the use of linked lists This means that the source and destination areas do not have to occupy contiguous areas of memory Hardware DMA channel priority AHB slave DMA programming interface The DMA Controller is programmed by writing to the DMA control registers over the AHB slave interface One AHB bus master for transferring data The interface transfers data when a DMA request goes active 32 bit AHB master bus width Incrementing or non incrementing addressing for source and destination Programmable DMA burst size The DMA burst size can be programmed to more efficiently transfer data Internal four word FIFO per channel Supports 8 16 and 32 bit wide transactions Big endian and little endian support The DMA Controller defaults to little endian mode on reset An interrupt to the processor can be generated on a DMA completion or when a DMA error has occurred Raw interrupt status The DMA error and DMA count raw interrupt status can be read prior to masking 8 10 Fast general purpose parallel I O LPC1759 58 56 54 52 51 Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers Pins may be dynamically configured as inputs or outputs Separate registers allow setting or clearing any number of outputs simultaneously The value of the output register may be read back as well as the current state of the port pins LPC1
113. us 5 V the Vgus pin can be connected directly to the Vays pin on the USB connector This applies to bus powered devices where the USB cable supplies the system power For systems where Vpp can be 0 V and Vgus is directly applied to the Vays pin precautions must be taken to reduce the voltage to below 3 6 V VpD 3V3 Y R2 LPC17xx R1 USB_UP_LED 1 5kQ VBus 4 USB D Rs 332 gt USB B p gt connector USB_D Ps 339 Vss 002aad940 Fig 28 LPC1759 58 56 54 52 51 USB interface on a bus powered device The maximum allowable voltage on the Vgus pin is 3 6 V One method is to use a voltage divider to connect the Vgus pin to the Vays on the USB connector The voltage divider ratio should be such that the Vgus pin will be greater than 0 7Vpp to indicate a logic HIGH while below the 3 6 V allowable maximum voltage Use the following operating conditions VBUS max 5 25 V Vpp 3 6 V The voltage divider would need to provide a reduction of 3 6 V 5 25 V or 0 686 V LPC1759_58_56_54_52_51 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 64 of 80 NXP Semiconductors LPC1 759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller
114. ut pin ENET_REF_CLK l ENET_REF_CLK Ethernet reference clock LPC1758 only LPC1759_58_56_54_52_51 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 9 of 80 NXP Semiconductors LPC1759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller Table 4 Pin description continued Symbol Pin Type Description P1 18 2511 VO P1 18 General purpose digital input output pin USB UP PEDE O USB_UP_LED USB GoodLink LED indicator It is LOW when the device is PWM1 1 configured non control endpoints enabled or when the host is enabled and has CAP1 0 detected a device on the bus It is HIGH when the device is not configured or when host is enabled and has not detected a device on the bus or during global suspend It transitions between LOW and HIGH flashes when the host is enabled and detects activity on the bus O PWM1 1 Pulse Width Modulator 1 channel 1 output l CAP1 0 Capture input for Timer 1 channel 0 P1 19 MCOAO 26l1 VO P1 19 General purpose digital input output pin ate O MCOAO Motor control PWM channel 0 output A O USB PPWR Port Power enable signal for USB port LPC1759 58 56 54 only l CAP1 1 Capture input for Timer 1 channel 1 P1 20 MCIO 2711 VO P1 20 Ge
115. wing selected LPC1759 58 56 54 52 51 peripherals to have DMA support The GPDMA enables peripheral to memory memory to peripheral peripheral to peripheral and memory to memory transactions The source and destination areas can each be either a memory region or a peripheral and can be accessed through the AHB master The GPDMA controller allows data transfers between the USB and Ethernet LPC1758 only controllers and the various on chip SRAM areas The supported APB peripherals are SSP0 1 all UARTS the I S bus interface the ADC and the DAC Two match signals for each timer can be used to trigger DMA transfers Remark Note that the DAC is not available on the LPC1752 51 and the I2S bus interface is not available on the LPC1754 52 51 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 17 of 80 NXP Semiconductors LPC1 759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller 8 9 1 Features Eight DMA channels Each channel can support an unidirectional transfer 16 DMA request lines Single DMA and burst DMA request signals Each peripheral connected to the DMA Controller can assert either a burst DMA request or a single DMA request The DMA burst size is set by programming the DMA Controller Memory to memory memory to peripheral peripheral to memory and peripheral to peripheral transfers are s
116. with optional interrupt generation on match Stop timer on match with optional interrupt generation Reset timer on match with optional interrupt generation e Supports single edge controlled and or double edge controlled PWM outputs Single edge controlled PWM outputs all go high at the beginning of each cycle unless the output is a constant low Double edge controlled PWM outputs can have either edge occur at any position within a cycle This allows for both positive going and negative going pulses All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 26 of 80 NXP Semiconductors LPC1 759 58 56 54 52 51 8 23 8 24 8 24 1 LPC1759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller Pulse period and width can be any number of timer counts This allows complete flexibility in the trade off between resolution and repetition rate All PWM outputs will occur at the same repetition rate Double edge controlled PWM outputs can be programmed to be either positive going or negative going pulses Match register updates are synchronized with pulse outputs to prevent generation of erroneous pulses Software must release new match values before they can become effective May be used as a standard 32 bit timer counter with a programmable 32 bit prescaler if the PWM mode is not enabled Moto
117. xecuted from flash all peripherals disabled PCLK CCLKg CCLK 12 MHz PLL lez 7 mA disabled CCLK 100 MHz PLL 617 42 mA enabled CCLK 100 MHz PLL eli 50 enabled LPC1759 CCLK 120 MHz PLL 6 8 67 mA enabled LPC1759 sleep mode fele 2 8 mA deep sleep mode eio 240 uA power down mode 6 10 31 uA deep power down mode m 630 nA RTC running IBAT battery supply current Deep power down mode RTC running VpDb REG 3V3 present 12 530 nA Vpp REGy 3v3 Not 13 present 1 1 uA lDD 10 I O supply current deep sleep mode HAns 40 nA power down mode Hans 40 nA deep power down mode 14 10 nA LPC1759_58_56_54_52_51 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 8 6 18 August 2015 40 of 80 NXP Semiconductors LPC1759 58 56 54 52 51 32 bit ARM Cortex M3 microcontroller Table 7 Static characteristics continued Tamb 40 C to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit IDD ADC ADC supply current active mode nelly 1 95 mA ADC powered ADC in Power down 16 18 lt 0 2 uA mode Deep sleep mode 16 38 nA Power down mode 16 38 nA Deep power down mode 16 24 nA l ADC ADC

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