980 Phy & Protocol Aux Channel Analyzer Sink MOI
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1. 5 6 5 7 5 8 5 9 Apply 5 0V between 5V Power and DDC CEC Ground Power on the Sink DUT Use the EDID Analyzer to read block 0 of the Sink s EDID If the Sink DUT does not appropriately ACK each I2C transaction then FAIL If the bytes read from offsets 0 7 do not constitute a valid EDID header then FAIL If the EDID checksum byte read from the Sink DUT does not match the checksum calculated by the EDID analyzer then FAIL Test the setup time sensitivity of the Sink DUT 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 Configure DDC Master so that when the DDC Master is writing to SDA the setup time of SDA is equal to 250ns Connect EDID Analyzer to DDC Master Connect DDC Master to TPA Apply 5 0V between 5V Power and DDC CEC Ground Power on the Sink DUT Use the EDID Analyzer to read block 0 of the Sink s EDID If the Sink DUT does not appropriately ACK each I2C transaction then FAIL If the bytes read from offsets 0 7 do not constitute a valid EDID header then FAIL If the EDID checksum byte read from the Sink DUT does not match the checksum calculated by the EDID analyzer then FAIL HDMI Forum Confidential Page 13 of 25 Vendor Specific Test Procedure Test Equipment A variety of equipment is needed for testing HDMI products Each piece is authorized and included by name in this Compliance Test Specification This section describes the Quantum Data test equipment2. Informative Reference No additional informative references HDMI Forum Confidential Page 5 of 25 Test Sink I C Bus LOW Level Output Voltage Objective Confirm that the LOW level output voltage of the 1 C Bus formed when connecting the Sink DUT to a compliant Source configured so that a LOW level output current of 3mA results in Vo 0 4V is less than or equal to the required maximum Vo for the DDC SDA signal Reference Requirement DDC Rev 4 Section 6 1 For devices and systems compliant with This Specification the Display Data Channel DDC I Os and wires SDA SCL DDC CEC Ground shall meet the requirements specified in the 12C bus specification and user manual UM10204 Rev 5 I2C Specification Section 6 1 for Standard mode devices 12C bus specification and user manual Maximum LOW level output voltage Vo 0 4V at 3mA UM10204 Rev 5 Section 6 1 sink current Capability s There are no specific product capabilities for this test Test Equipment Generic Equipment Vendor Specific Equipment Quantity 1 DDC Master 980 Advanced Test Platform series 1 EDID Analyzer 980 HDMI Phy amp Protocol Aux Channel Analyzer module Generic Procedure Setup 1 Connect TPA to Sink DUT 2 Configure DDC Master with 1 5K pull up resistance to 4 7V supply on both SCL and SDA wires 3 Connect EDID Analyzer to DDC Master 4 Connect DDC Master to TPA 5 Apply 5 0V between 5V Power and DDC
3. 4Q 01 4 4 Verify the resistance of SDA is in valid Range o VSDA A 0 797340V Calculated resistance of SDA is 48342 3 ohms 4 02 5 4 Verify the resistance of SCL is in valid Range Calculated resistance of SCL is 47778 9 ohms 4 DDC2 3 Bus Timing 4 e Iter 01 o 5V Power 4 98 volts WARNING hot plug LOW above Vol 0 4V WARNING RX_SENSE failed 01 10 Verify the Sink DUT appropriately ACK each I2C transaction 02 11 1 Verify NO t HD DAT is less than Ous 03 11 2 Verify NO t SU DAT is less than 250ns 4 DDC2 4 Bus Timing 4 Iter 01 o 5V Power 4 98 volts WARNING hot plug LOW above Vol 0 4V WARNING RX SENSE failed 5 7 Verify the Sink DUT appropriately ACK each I2C transaction Vefity the bytes read from offsets 0 7 constitute a valid EDID Validate the EDID checksum byte read from the Sink DUT Verify the Sink DUT appropriately ACK each I2C transaction 8 Vefity the bytes read from offsets 0 7 constitute a valid EDID J 6 9 Validate the EDID checksum byte read from the Sink DUT DDC2 1 2C Bu Output Voltage Instrument l My980B 192 168 254 185 You can also obtain an HTML report The report can be a summary or include the details of the test results These are shown below HDMI Forum Confidential Page 23 of 25 HTML Viewer C Users nkendall Desktop 980_R4_14_15 hdmict_sink results My_ACA _Sink_Test_3 Report_Summary htm My_ACA Sink Test 3 ACME October 7 2015 8 38 AM XYZ 1 HD
4. HDMI Phy amp Protocol Aux Channel Analyzer Module The Quantum Data 980 HDMI Phy amp Protocol Aux Channel Analyzer module can be installed in the 980B or 980R series Advanced Test Platforms This 980 HDMI Phy amp Protocol Aux Channel Analyzer module serves the generic test functions called out in the HDMI CTS DDC Clarification Refer to the table below Item Quantum Data Equipment 1 980 Advanced Test Platform series Equipped with 980 HDMI Phy Protocol Aux Channel Analyzer module 980 HDMI Phy amp Protocol Aux Channel Analyzer with 980B Series Platform Configuration The figure below shows a depiction of the 980 Phy amp Protocol Aux Channel Analyzer module equipped in various 980B platform Note Card positioning may vary depending on configuration HDMI Forum Confidential Page 14 of 25 Tests Sink DDC Tests 1 Objectives 12C Bus LOW level Output Voltage Confirm that the LOW level output voltage of the 12C Bus formed when connecting the Sink DUT to a compliant Source configured so that a LOW level output current of 3mA results in VOL 0 4V is less than or equal to the required maximum VOL for the DDC SDA signal Pull Up Resistance Confirm that the Sink pull up resistance meets the minimum requirements for DDC signals SCL and SDA Bus Timing driving SDA Confirm that the Sink meets the setup and hold bus timing parameters specified in the 12C bus specification when driving the SDA signal Bus Timing
5. HDMI Source CTS 1 4b icon in the Compliance Tests page of the Apps panel Apps quantumdata Compliance Tests Y HDMI EDID HDMI Source HDMI Source CTS 1 4b CTS 1 4b CTS 2 0 HDMI Sink HDMI Sink HDMI HDCP Transmitter CTS 1 4b CTS 2 0 CTS 1 2 MHL Source MHL Dongle CTS 1 2 2 1 CTS 1 2 2 1 CBUS Source CBUS Sink CBUS Dongle CTS 1 2 2 1 CTS 1 2 2 1 CTS 1 2 2 1 Page 2 of 4 Card Control Compliance Tests Editors Other HDMI Forum Confidential Page 16 of 25 4 2 Navigate to the CDF tab if not already there There are no CDF requirements to be entered Simply fill in the name and model number of the device and click OK and optionally save the file Be sure to indicate the number of HDMI outputs H 3 HDMI L b Sink amp CDF Entry lt lection gt Test Options Preview L Open Ld New El Save CDF File lt not saved gt Product o Formats o Audio What is the product manufacturer s name CME What is the model name number of the product Manufacturer Model How many HDMI output ports are on the product Sink_HDMI_Output_Count 001 02 03 04 05 06 07 08 09 The number of the HDMI Input Port being tested Sink_P 01 02 03 04 05 06 07 Os 9 1 OU OL OLB OV OD E _ Does the DUT indicate correct size at Image Size area in the EDID Sink_Image_Size O Yes 0 No x cm What is the maximum TMDS clock frequency in MHz supported by the p
6. below Test Results Name Execute HDMI 1 4b Sink 1 4b Compliance Tests on Instrument My980B 192 168 254 185 Enter a name for the Test Results My_ACA Sink_Test_1 0617 2015 10 21 06 Testi Enter a name click OK and the test will begin A Test Window will appear below indicating the progress of the test HDMI Forum Confidential Page 20 of 25 r HDMI 1 4b Sink Compliance Test 1 4b My_ACA_Sink_Test_1 Reset Status Status gt Category Test Name 4 DDC 4 DDC2 1 12C Bus LOW level Output Voltage E Iter 01 j DDC2 2 Pull Up Resistance gt DDC2 3 Bus Timing gt DDC2 4 Bus Timing Not Tested Not Tested Not Tested KISS x Assembling the test list Transferring the CDF to the consi Conpons Te A dialog box will appear below indicating the test setup r Test Setup Test DDC2 1 Iter 01 Confirm that the LOW level output voltage of the I2C Bus formed when connecting the Sink DUT to a compliant Source configured so that a LOW level output current of 3mA results in a V_ol 0 4V is less than or equal to the required maximum V_ol for the DDC SDA signal Connect the DUT input port to be tested to the OUT port of the test instrument Test Instrument Port Quantum Data Inc Precision ACA analyzer Card 3 OUT Port Use the cable with serial number 15090007 i
7. 2C bus specification and user manual 1 Data hold time typ pat gt O us UM10204 Rev 5 Section 6 1 2 Data setup time tsu par gt 250 ns Capability s There are no specific product capabilities for this test Test Equipment Generic Equipment Vendor Specific Equipment Quantity 1 DDC Master 980 Advanced Test Platform series 1 EDID Analyzer 980 HDMI Phy amp Protocol Aux Channel Analyzer module Generic Procedure Setup 1 Connect TPA to Sink DUT 2 Configure DDC Master with 2 0K pull up resistance to 5 5V supply on both SCL and SDA wires 3 Configure DDC Master to achieve 750pF total capacitance on SCL and SDA wires 4 Configure DDC Master so that fsc 100kHz 5 Connect EDID Analyzer to DDC Master 6 Connect DDC Master to TPA 7 Apply 5 0V between 5V Power and DDC CEC Ground 8 Power on the Sink DUT HDMI Forum Confidential Page 10 of 25 10 11 Use the EDID Analyzer to read block O of the Sink s EDID If the Sink DUT does not appropriately ACK each 12C transaction then FAIL Use the DDC Master if capable or the General Oscilloscope to measure the specified timing parameters for each occurrence during the EDID read 11 1 If any occurrence of typ pat lt Ops then FAIL 11 2 If any occurrence of tsy pat lt 250ns then FAIL HDMI Forum Confidential Page 11 of 25 Test Sink Bus Timing reading the SDA signal Objective Confirm that the Sink does not requ
8. CEC Ground 6 Power on the Sink DUT 7 Test LOW level output voltage of SDA HDMI Forum Confidential Page 6 of 25 7 1 Use the DDC Master to read block O of the Sink s EDID 7 2 If the Sink DUT does not respond to the DDC transaction then FAIL 7 3 Use the DDC Master if capable or the General Oscilloscope to measure the LOW level output voltage of SDA VOL SDA during the DDC read transaction 7 4 If VOL SDA gt 0 4V then FAIL HDMI Forum Confidential Page 7 of 25 Test Sink Pull Up Resistance Objective Confirm that the Sink pull up resistance meets the minimum requirements for DDC signals SCL and SDA Reference Requirement DDC Rev 4 Section 6 1 For devices and systems compliant with This Specification the Sink pull up resistance on SDA shall be greater than or equal to 42 3kQ which is 47kQ minus 10 HDMI 1 4b Section 4 2 8 Sink pull up resistors for SCL signal 47kQ 10 Capability s There are no specific product capabilities for this test Test Equipment Generic Equipment Vendor Specific Equipment Quantity 1 980 Advanced Test Platform series 1 980 HDMI Phy amp Protocol Aux Channel Analyzer module Generic Procedure Setup 1 Connect TPA to Sink DUT HDMI input connector 2 Drive 5 0V between 5V Power and DDC CEC Ground on the TPA 3 Power on the Sink DUT 4 Test the resistance of SDA 4 1 Measure then connect a 10K 1 resistor RSDA T between
9. Cancel Compliance Test Note Be sure to use the supplied HDMI cable Part No 30 00218 HDMI Forum Confidential Page 21 of 25 When the tests are complete the results are shown in the test window E HDMI 1 4b Sink Compliance Reset Status gt Category Test Name Y Status 4 DDC 4 DDC2 1 I2C Bus LOW level Output Voltage y Pass Iter 01 Y a DDC2 2 Pull Up Resistance y Pass Iter 01 A 4 DDC2 3 Bus Timing y o Pass Iter 01 Y 4 DDC2 4 Bus Timing y Iter 01 y Pass X Close Window HDMI Forum Confidential Page 22 of 25 The test will run and the test application will assess pass or fail The test results screens appears as shown below If the 980 HDMI Protocol Analyzer s compliance test application reports PASS then PASS If the 980 HDMI Phy amp Protocol Aux Channel Analyzer compliance test application reports FAIL then FAIL H al Compliance Test Results Viewer Sox Results Name My_ACA Sink_Test_2 LJ HTML Report Date Tested October 7 2015 8 31 AM Model Name Overall Status SESE Ee Port Tested 1 Test Name Details 4 DDC2 1 12C Bus LOW level Output Voltage 4 Iter 01 o 5V Power 4 98 volts WARNING hot plug LOW above Vol 0 4V o WARNING RX SENSE failed 01 7 2 Verify the Sink DUT respond to the DDC transaction 02 7 4 Verify VOL SDA lt 0 4v 4 DDC2 2 Pull Up Resistance 4 9 Iter 01 o 5V Power 4 97 volts
10. High Definition Multimedia Interface Version 1 4b Quantum Data MOI v1 0 Test DDC Sink October 7 2015 HDMI Forum Confidential Page 1 of 25 Preface Notice THIS DOCUMENT IS PROVIDED AS IS WITH NO WARRANTIES WHATSOEVER EXPRESS OR IMPLIED INCLUDING WITHOUT LIMITATION NO WARRANTIES OF MERCHANTABILITY NONINFRINGEMENT FITNESS FOR ANY PARTICULAR PURPOSE OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL SPECIFICATION OR SAMPLE HDMI Forum Inc and its members disclaim all liability including liability for infringement of any proprietary rights relating to use of information in This Specification Document Revision History 1 0 October 7 2015 Initial Release Intellectual Property Copyright partly in this document is owned by the HDMI Forum Inc who reserves all rights therein The Forum hereby grants a copyright license to portions of this document that were created by the HDMI Forum for use by Test Equipment Makers HDMI Adopters and HDMI ATCs and others that access this document through the HDMI Adopter Extranet to use this document for the testing of purported HDMI Licensed Products as defined in the HDMI Adopters Agreement and the HDMI Adopters Addendum Copyright partly in this document is owned by Quantum Data Inc who reserves all rights therein By uploading or otherwise delivering this document for publication on the HDMI Extranet Quantum Data Inc hereby grants a copyright license to portions
11. MI Forum Confidential Page 24 of 25 HTML Viewer Users nkendall Desktop 980_R4_14_15 hdmict_sink results My_ACA Sink_Test_2 Report htm Iter 01 5V Power 4 98 volts WARNING hot plug LOW above Vol 0 4V WARNING RX_SENSE failed 01 7 2 Verify the Sink DUT respond to the DDC transaction 02 7 4 Verify VOL_SDA lt 0 4V Iter 01 5V Power 4 97 volts 01 4 4 Verify the resistance of SDA is in valid Range VSDA_A 0 797340V Calculated resistance of SDA is 48342 3 ohms 02 5 4 Verify the resistance of SCL is in valid Range Calculated resistance of SCL is 47778 9 ohms Iter 01 5V Power 4 98 volts WARNING hot plug LOW above Vol 0 4V WARNING RX_SENSE failed 01 10 Verify the Sink DUT appropriately ACK each I2C transaction 02 11 1 Verify NO t_HD DAT is less than 0us 03 11 2 Verify NO t_SU DAT is less than 250ns HDMI Forum Confidential Page 25 of 25
12. a r a a r ea atest 8 TEEEJUIAMA A A dd EENE E aa eai 8 Generic PIOCC CUM css scan A A 8 Test Sink Bus TMi ciicecsssissssesicsccntsaserseavnnecn ad AA A A rd EA 10 Objectives cal tipa 10 HDMI Forum Confidential Page 3 of 25 ASA AR ccs ar AETR EEEE Cas ERER E EA annize Dick EA EEEE EEEE Tene 10 Regq irement anina ar i a ata a a A a iaa a see ii eaa a aa dee 10 CODO Ma A e e ea E aa aa r e as 10 FesCEQUIDMENT starrer aaa ai ta iia tae 10 Generic Procedure il i 10 Test Sink BUS TIMO E id A A A A AA ad 12 0 1A AV TAEAE eee ne Pere ene eee 12 Referente a ds 12 ROQquIFre MEN Ei A A a Bee ante tht ras tai 12 COPAS re AA EA bir 12 Test Equipment aa aaea iia 12 GENETIC Procedure A ON 12 Vendor Specific Test Procedure iii 14 HDMI Forum Confidential Page 4 of 25 Introduction This document provides a set of test methods for tests described in High Definition Multimedia Interface Compliance Test Specification DDC Clarification Scope This document provides testing procedures for HDMI CTS 1 4b Sink DDC tests 1 12C Bus LOW level Output Voltage 2 Pull Up Resistance 3 Bus Timing driving SDA and 4 Bus Timing reading SDA References Normative References High Definition Multimedia Interface Specification Version 1 4b October 11 2011 HDMI Compliance Test Specification Version 1 4b October 11 2011 High Definition Multimedia Interface Compliance Test Specification DDC Clarification Version 1 04 May 1 2014
13. ire more setup or hold time than specified in the 12C bus specification when reading the SDA signal Reference Requirement DDC Rev 4 Section 6 1 For devices and systems compliant with This Specification the Display Data Channel DDC I Os and wires SDA SCL DDC CEC Ground shall meet the requirements specified in the 12C bus specification and user manual UM10204 Rev 5 12C Specification Section 6 1 for Standard mode devices I2C bus specification and user manual 1 Data hold time typ pat gt O us UM10204 Rev 5 Section 6 1 2 Data setup time tsu pat gt 250 ns Capability s There are no specific product capabilities for this test Test Equipment Generic Equipment Vendor Specific Equipment Quantity 1 DDC Master 980 Advanced Test Platform series 1 EDID Analyzer 980 HDMI Phy amp Protocol Aux Channel Analyzer module Generic Procedure Setup 1 Connect TPA to Sink DUT 2 Configure DDC Master with 2 0K pull up resistance to 5 5V supply on both SCL and SDA wires 3 Configure DDC Master to achieve 750pF total capacitance on SCL and SDA wires 4 Configure DDC Master so that fsc 100kHz 5 Test the hold time sensitivity of the Sink DUT 5 1 Configure DDC Master so that when the DDC Master is writing to SDA the hold time of SDA is equal to O us 5 2 Connect EDID Analyzer to DDC Master 5 3 Connect DDC Master to TPA HDMI Forum Confidential Page 12 of 25 5 4 5 5
14. of this document that were created by Quantum Data Inc to HDMI Adopters HDMI ATCs and others that access this document through the HDMI Adopter Extranet to use this document for the testing of purported HDMI Licensed Products Only versions of this document that are approved and considered the current versions may be used by HDMI Adopters for compliance testing No charge or fee is associated with such copyright license grant provided herein Contact Information The URL for the HDMI Forum web site is http www hdmiforum org The URL for the Quantum Data website is http www quantumdata com HDMI Forum Confidential Page 2 of 25 Table of Contents A A E 2 IN OEIC iii A di AEE E E DAA A da A dida 2 Document Revision A O 2 Intellectual Property nicas a AA its 2 CONTACELA FO MATO lt A d 2 OO ii di A A bia A RA AAA A A 5 Oi linia 5 ROTOTENCOS sucia id ie A AS do AAN E A A AA snesiaaveas 5 Normative References iia ic slates Ge a e e a ies 5 Informative Referente a ao 5 Test Sink C Bus LOW Level Output Voltage sesiis eiei acallar einen c 6 0 Y1 A0 AV A TE ceees ees Bete eeu Skee a Sei ROO OA ES O NBR iio 6 Referente altillo shtaced teks 6 Requirement inican A A aE andi AAA sae E KEA aE Aai aa aA 6 CONDONES eeen A EEA CE EEA EE N EEIE bien EE E EAE R 6 Test Eg ipmen teenin ish et niin ad vai 6 Generic Procedure A 6 Test Sink Pull Up Resistance a 8 A RO 8 ROA e A e e ed 8 Requirement ae a aaie araen adds 8 COD GAIT ara
15. reading SDA Confirm that the Sink does not require more setup or hold time than specified in the 12C bus specification when reading the SDA signal 2 Test Overview The Pass Fail criteria is assessed by the application with no human examination required 3 Procedure Use the following procedure to conduct this test 1 Connect Sink DUT to the Quantum Data 980 HDMI Phy amp Protocol Aux Channel Analyzer at the module s port labeled IN Use a High Speed HDMI cable The figure below shows a depiction of connections to the 980 HDMI Phy amp Protocol Aux Channel Analyzer module residing in the 980 series chassis Note Be sure to use the supplied HDMI cable Part No 30 00218 Description CBL HDMI 7ft High Speed Heac Calibrated Sink 980B Platform with Phy amp Protocol Aux Channel Analyzer module HDMI Sink DUT PC with 980 GUI Manager Optional 2 Operate the Sink DUT in a normal mode HDMI Forum Confidential Page 15 of 25 Use Quantum Data 980 Embedded Manager GUI touchscreen or invoke Quantum Data 980 External Manager GUI Windows application Note You will not need to connect the PC shown in the figures above if you are running the compliance test through the 980 s embedded display The PC running the 980 HDMI Phy amp Protocol Aux Channel Analyzer module s compliance test application is connected to the 980 through a standard Ethernet cable Complete the following steps 4 1 Click on the
16. roduct Sink_Max_TMDS_Clock Any value e g 74 25 148 5 222 75 etc 148 5 HDMI Forum Confidential Page 17 of 25 4 3 Click on the Test Selection tab and the DDC sub tab and select the DDC1 1 12C Bus Low Level Output Voltage test the DDC1 2 Pull Up Resistance test DDC1 3 Bus Timing driving the SDA and the DDC1 4 Bus Timing reading the SDA Refer to the sample screen below 4 4 Click on Test Options Preview tab and review the list of tests Refer to the sample screen below HDMI Forum Confidential Page 18 of 25 4 HDMI 1 4b Si LO 9 Options Instrument My980B 192 168 254 185 gt Category Test Name 4 DDC 4 DDC2 1 I2C Bus LOW level Output Voltage e Iter 01 DDC2 2 Pull Up Resistance Iter 01 DDC2 3 Bus Timing o Iter 01 DDC2 4 Bus Timing e Iter 01 y y y y y y y y 4 5 Click on Execute tests activation button to initiate the test Refer to the sample screen below 1 3 HDMI 1 4b Sin r amp CDF Entry KZ Test Selection Test Options Preview Instrument My9808 192 168 254 185 b gt Execute Tests gt Category Test Name Y 4 gt DDC 4 DDC2 1 12C Bus LOW level Output Voltage y Iter 01 Y HDMI Forum Confidential Page 19 of 25 Note You will be prompted with a dialog box to assign a name to the test results Refer to the screen example
17. the SDA pin and DDC CEC Ground on the TPA 4 2 Measure the voltage of the SDA pin on the TPA VSDA A referenced to DDC CEC Ground on the TPA 4 3 If OV lt VSDA A lt 0 1V then skip to step 5 4 4 Leave the 10K 1 resistor RSDA T connected as it was in step 4 1 Measure then connect an additional 51 7K 1 resistor RSDA S to the SDA pin on the TPA Connect the other end the 51 7K 1 resistor RSDA S to the positive terminal of a DC Power Supply set to 3 58V 1 and measured VSDA B Connect the negative HDMI Forum Confidential Page 8 of 25 4 5 4 6 4 7 4 8 terminal of the VSDA B supply to DDC CEC Ground on the TPA The Thevenin equivalent of this test circuit is calculated as VSDA TH VSDA B 1 1 RSDA S RSDA T and RSDA TH RSDA S RSDA T RSDA S RSDA T Measure the voltage of the SDA pin on the TPA VSDA C referenced to DDC CEC Ground on the TPA Remove the 10K 1 resistor leaving the 51 7K 1 resistor and 3 58V DC Power Supply that were added in step 4 4 Measure the voltage of the SDA pin on the TPA VSDA D referenced to DDC CEC Ground on the TPA If 42300 ohms lt VSDA D VSDA C VSDA C VSDA TH 1 RSDA TH VSDA D VSDA B 1 RSDA S then continue otherwise FAIL Test the resistance of SCL 5 1 5 2 5 3 5 4 5 5 Measure then connect a 51 7K 1 resistor RSCL S to the SCL pin on the TPA Connect the other end the 51 7K 1 resistor RSCL S to
18. the positive terminal of a DC Power Supply set to 3 58V 1 and measured VSCL A Connect the negative terminal of the VSCL A supply to DDC CEC Ground on the TPA Measure the voltage of the SCL pin on the TPA VSCL B referenced to DDC CEC Ground on the TPA Measure then connect an additional 10K 1 resistor RSCL T between the SCL pin and DDC CEC Ground on the TPA leaving the 51 7K 1 resistor RSCL S and 3 58V DC Power Supply VSCL A that were added in step 5 1 The Thevenin equivalent of this test circuit is calculated as VSCL TH VSCL A 1 1 RSCL S RSCL T and RSCL TH RSCL S RSCL T RSCL S RSCL T Measure the voltage of the SCL pin on the TPA VSCL C referenced to DDC CEC Ground on the TPA If 42300 ohms lt VSCL B VSCL C VSCL C VSCL TH 1 RSCL TH VSCL B VSCL A 1 RSCL S lt 51700 ohms then PASS otherwise FAIL HDMI Forum Confidential Page 9 of 25 Test Sink Bus Timing driving the SDA signal Objective Confirm that the Sink meets the setup and hold bus timing parameters specified in the 12C bus specification when driving the SDA signal Reference Requirement DDC Rev 4 Section 6 1 For devices and systems compliant with This Specification the Display Data Channel DDC I Os and wires SDA SCL DDC CEC Ground shall meet the requirements specified in the 12C bus specification and user manual UM10204 Rev 5 12C Specification Section 6 1 for Standard mode devices I
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