Home

DSP56371 Data Sheet

1. 56 2 0 56371 19 Package Informallor iu ses se 58 verview 20 Design Considerations 64 e e 21 Electrical Design Considerations 65 22 Power Consumption Benchmark 67 2 1 Introduction This manual describes the DSP56371 24 bit digital signal processor DSP its memory operating modes and peripheral modules The DSP56371 is a member of ey oe Freescale Semiconductor Inc 2004 2005 2006 2007 All rights reserved freescale semiconductor DSP56371 Overview the DSP56300 family of programmable CMOS DSPs The DSP56371 is targeted to applications that require digital audio compression decompression sound field processing acoustic equalization and other digital audio algorithms Changes in core functionality specific to the DSP56371 are also described in this manual See Figure 1 for the block diagram of the DSP56371 Memory Expansion Area SHI E Interface Interface Interface Program X Data Y Data RAM RAM RAM 36K x 24 48K x 24 SAI 4 24 ROM ROM ROM 2 64K x 24 32K x 24 32K x 24 Address Generation pow TPT Core DDB Internal Data Bus Mgmt Clock r Data ALU T 4 Program Program I Program lt gt Interrupt Decode Address 24 x 24 5656 bit MAC erator Controller i Controller 1 Generaton Two 56 bit Accumulators 56 bit Barrel Shifter 1 M
2. 50 Freescale Semiconductor Enhanced Serial Audio Interface Timing SCKT 63 I Input Output FST Bit Out FST Word Out Data Out Last Bit Transmitter 0 Drive Enable FST Bit In FST Word In See Note Flags Out phe F Xo Note In network mode output flag transitions can occur at the start of each time slot within the frame In normal mode the output flag state is asserted for the entire frame period Figure 14 is drawn assuming positive polarity bit clock TCKP 0 and positive frame sync polarity 0 Figure 14 ESAI Transmitter Timing DSP56371 Data Sheet Rev 4 1 Freescale Semiconductor 51 Enhanced Serial Audio Interface Timing SCKR Input Output FSR Bit Out FSR Word Out Data In FSR Bit In FSR Word In Flags In Note Figure 15 is drawn assuming positive polarity bit clock RCKP 0 and positive frame sync polarity RFSP 0 Figure 15 ESAI Receiver Timing HCKT SCKT output Note Figure 16 is drawn assuming positive polarity high frequency clock THCKP 0 and positive bit clock polarity TCKP 0 Figure 16 ESAI HCKT Timing DSP56371 Data Sheet Rev 4 1 52 Freescale Semiconductor Note Figure 17 is drawn assuming positive polarity high frequency clock RHCKP 0 and positive bit clock polarity RCKP HCKR SCKR output 0 Figure 17 ESAI HCKR Timing
3. State Signal Name Type During Signal Description Reset MODA IRQA Input Input Mode Select A External Interrupt Request A MODA IRQA is an active low Schmitt trigger input internally synchronized to the DSP clock MODA IRQA selects the initial chip operating mode during hardware reset and becomes a level sensitive or negative edge triggered maskable interrupt request input during normal instruction processing MODA MODB MODC and MODD select one of 16 initial chip operating modes latched into the OMR when the RESET signal is deasserted If the processor is in the stop standby state and the MODA IRQA pin is pulled to GND the processor will exit the stop state Internal Pull up resistor This input is 5 V tolerant DSP56371 Data Sheet Rev 4 1 Freescale Semiconductor 15 Signal Connection Descriptions Table 6 Interrupt and Mode Control continued State Signal Name Type During Signal Description Reset MODB IRQB Input Input Mode Select B External Interrupt Request B MODB IRQB is an active low Schmitt trigger input internally synchronized to the DSP clock MODB IRQB selects the initial chip operating mode during hardware reset and becomes a level sensitive or negative edge triggered maskable interrupt request input during normal instruction processing MODA MODB MODC and MODD select one of 16 initial chip operating modes latched into OMR when the RESET signal is deasserted Intern
4. i ck s internal clock synchronous mode synchronous implies that SCKT and SCKR are the same clock 5 For the internal clock the external clock cycle is defined by and the ESAI control register 6 The word relative frame sync signal waveform relative to the clock operates in the same manner as the bit length frame sync signal waveform but spreads from one serial clock before first bit clock same as bit length frame sync signal until the one before last bit clock of the first word in frame 7 Periodically sampled and not 100 tested 8 ESAI 1 specs match those of ESAI 0 No Characteristics 2 3 Symbol Expression Min Max Condition Unit 88 SCKT edge to transmitter 40 drive enable 34 0 x ck ns deassertion 20 0 i ck 89 FST input bl wr setup time before SCKT 2 0 x ck ns edge 21 0 i ck 90 FST input wl setup time before SCKT edge 2 0 ck ns 21 0 i ck 91 FST input hold time after SCKT edge m 4 0 x ck ns 0 0 i ck 92 FST input wl to data out enable from high 27 0 ns impedance 93 FST input wl to transmitter 40 drive enable 31 0 ns assertion 94 output valid after SCKT edge 32 0 X ck ns 18 0 i ck 95 HCKR HCKT clock cycle 2x Te 13 4 ns 96 HCKT input edge to SCKT output 18 0 ns 97 HCKR input edge to SCKR output 18 0 ns Note DSP56371 Data Sheet Rev 4 1
5. implement the Motorola SPI serial protocol The ESAI consists of independent transmitter and receiver sections each with its own clock generator It is a superset of the DSP56300 family ESSI peripheral and of the DSP56000 family SAI peripheral For more information on the ESAI refer to DSP56371 User s Manual Enhanced Serial Audio Interface ESAI section 2 5 4 Enhanced Serial Audio Interface 1 ESAI 1 The ESAI 1 is a second ESAI interface The ESAI 1 is functionally identical to ESAI For more information on the ESAI 1 refer to DSP56371 User s Manual Enhanced Serial Audio Interface ESAI_1 section 2 5 5 Serial Host Interface SHI The SHI is a serial input output interface providing a path for communication and program coefficient data transfers between the DSP and an external host processor The SHI can also communicate with other serial peripheral devices The SHI can interface directly to either of two well known and widely used synchronous serial buses the Motorola serial peripheral interface SPI bus and the Philips inter integrated circuit control C bus The SHI supports either the SPI or PC bus protocol as required from a slave or a single master device To minimize DSP overhead the SHI supports single double and triple byte data transfers The SHI has a 10 word receive FIFO that permits receiving up to 30 bytes before generating a receive interrupt reducing the overhead for data reception For more information on the SH
6. 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 441 2447 or 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com DSP56371 Rev 4 1 1 2007 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims a
7. 5 ns DSP56371 Data Sheet Rev 4 1 46 Freescale Semiconductor Serial Host Interface SHI C Protocol Timing Table 21 SHI IC Protocol Timing continued Standard NS FOE Mode Unit Min Max Min Max 52 Data set up time Tsu DAT 250 100 ns 53 Data hold time THD DAT 0 0 m 0 0 0 9 us 54 DSP clock frequency Fosc 10 6 28 5 MHz 55 SCL low to data out valid 3 4 0 9 us 56 condition setup time Tsu sTo 4 0 0 6 us 57 HREQindeassertion to last SCL edge HREQ in 0 0 0 0 ns set up time 58 First SCL sampling edge to HREQ output TNG RQO deassertion 4 X 30 52 E 52 ns 59 Last SCL edge to HREQ output not deasserted Tas RQO 2 30 52 52 ns 60 HREQ in assertion to first SCL edge TaS RQI 0 5 Tccp 4327 927 ns 0 5 X Tc 21 61 First SCL edge to HREQ in not asserted 0 0 0 0 ns HREQ in hold time Note 1 VCORE_VDD 1 2 5 0 05 V Tj 40 to 115 C for 150 MHz Tj 0 C to 100 C for 181 MHz CL 50 pF 2 Pull up resistor R P min 1 5 kOhm 3 Capacitive load C b max 50 pF 4 All times assume noise free inputs 5 All times assume internal clock frequency of 180MHz 13 1 Programming the Serial Clock The programmed serial clock cycle is specified by the value of the HDM 7 0 a
8. disconnected GPIO disconnected Serial Data Output 3 When programmed as a transmitter SDO3_1 is used to transmit data from the serial transmit shift register Serial Data Input 2 When programmed as a receiver SDI2_1 is used to receive serial data into the RX2 serial receive shift register Port E8 When the ESAI_1 is configured as GPIO this signal is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected Internal Pull down resistor This input is 5 V tolerant 002_1 SDI3_1 Output Input Input output or disconnected GPIO disconnected Serial Data Output 2 When programmed as a transmitter SDO2_1 is used to transmit data from the TX2 serial transmit shift register Serial Data Input 3 When programmed as a receiver SDI3_1 is used to receive serial data into the RX3 serial receive shift register Port E9 When the ESAI_1 is configured as GPIO this signal is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected Internal Pull down resistor This input is 5 V tolerant DSP56371 Data Sheet Rev 4 1 Freescale Semiconductor 27 Signal Connection Descriptions Table 9 Enhanced Serial Audio Interface_1 Signals Signal Name Signal Type State during Signal Description Reset SDO1_1 Output
9. dor 6 1 1 move p 0 1 move x0 p r1 move 1 1 1 move 50 move 50 move 50 reset move SFFFFFF m0 move 110 11 move m0 m2 move m0 m3 move m0 m4 move 110 115 move 110 116 move m0 m7 move gt 102 ep move gt 18 527 move gt 110000 omr DSP56371 Data Sheet Rev 4 1 66 Freescale Semiconductor move 300 sr movep gt F02000 X SFFFFFF movep 187 X SFFFFFE then sets up BCR and AAR registers then sets up PORTB and HDIO8 PORT andi SFC mr Start running ROM intialisation stage FF1C7E Set green HLX zone table jsr 5 1064 Run GPIONil function jsr FF2F82 Initialise Green HLX jsr FFIFA1 Disable DAX move gt 15 1 move x1 P SFFOD7F Run Green HLX jmp SFF1FDB nop nop nop nop nop nop dor forever endprog nop nop endprog nop DSP56371 Data Sheet Rev 4 1 Power Consumption Benchmark Freescale Semiconductor 67 How to Reach Us Home Page www freescale com E mail support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 1 800 521 6274 or 1 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English
10. CPOL 1 Input MISO Output MOSI Input HREQ Output TUE lt Day 26 Serial Host Interface SPI Protocol Timing lec 23 28 lt Te GH hne ue quel vats 34 X MSB 30 89 4 ORE TT vaia Figure 11 SPI Slave Timing 0 DSP56371 Data Sheet Rev 4 1 Freescale Semiconductor 45 Serial Host Interface SHI Protocol Timing T X 5 lt SCK CPOL 0 Input SCK CPOL 1 Input MISO Output MOSI Input QUU HREQ Output Figure 12 SPI Slave Timing CPHA 1 13 Serial Host Interface SHI Protocol Timing Table 21 SHI 2 Protocol Timing Standard Ms UN one eae rs Unit Min Max Min Max 44 SCL clock frequency FscL 100 400 kHz 44 SCL clock cycle TscL 10 2 5 us 45 Bus free time Taur 4 7 m 1 3 us 46 condition set up time TsusTA 4 7 0 6 us 47 condition hold time THD STA 4 0 lt S 0 6 us 48 SCL low period TLow 4 7 1 3 us 49 SCL high period 4 0 1 3 2 us 50 SCL and SDA rise time TR 5 5 ns 51 SCL and SDA fall time TF 5
11. Connection Descriptions Table 8 Enhanced Serial Audio Interface Signals continued Signal Name Signal Type State during Reset Signal Description SCKR PCO Input or output Input output or disconnected GPIO disconnected Receiver Serial Clock SCKR provides the receiver serial bit clock for the ESAI The SCKR operates as a clock input or output used by all the enabled receivers in the asynchronous mode SYN 0 or as serial flag 0 pin in the synchronous mode SYN 1 When this pin is configured as serial flag pin its direction is determined by the RCKD bit in the RCCR register When configured as the output flag OFO this pin will reflect the value of the OFO bit in the SAICR register and the data in the OFO bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode When configured as the input flag IFO the data value at the pin will be stored in the IFO bit in the SAISR register synchronized by the frame sync in normal mode or the slot in network mode Port CO When the ESAI is configured as GPIO this signal is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected Internal Pull down resistor This input is 5 V tolerant SCKT Input or output Input output or disconnected GPIO disconnected Transmitter Serial Clock This signal provides the serial bit rate
12. FST out bl low 31 0 ck ns 17 0 i ck 80 SCKT edge to FST out wr high 31 0 x ck ns 17 0 i ck 81 SCKT edge to FST out wr low 33 0 ck ns 19 0 ick 82 SCKT edge to FST out wl high 30 0 x ck ns 16 0 i ck 83 SCKT edge to FST out wl low 31 0 ck ns 17 0 ick 84 SCKT edge to data out enable from high 31 0 ck ns impedance 17 0 i ck 85 SCKT edge to transmitter 40 drive enable 34 0 ck ns assertion 20 0 i ck 86 SCKT edge to data out valid 26 5 ck ns 21 0 ick 87 SCKT edge to data out high impedance 31 0 x ck ns 16 0 ick DSP56371 Data Sheet Rev 4 1 Freescale Semiconductor 49 Enhanced Serial Audio Interface Timing Table 22 Enhanced Serial Audio Interface Timing continued 1 VoorE vpp 1 25 0 05 V Ty 40 to 115 C for 150 MHz Ty 0 C to 100 C for 181 MHz 50 pF 2 SCKT SCKT pin transmit clock SCKR SCKR pin receive clock FST FST pin transmit frame sync FSR FSR pin receive frame sync HCKT HCKT pin transmit high frequency clock HCKR HCKR pin receive high frequency clock 3 bl bit length wl word length wr word length relative 4 i ck internal clock X ck external clock i ck a internal clock asynchronous mode asynchronous implies that SCKT and SCKR are two different clocks
13. GPIO Signals continued Signal State During Reset Signal Description PF7 Input GPIO Port F7 this signal is individually programmable as input output output or disconnected internally disconnected The default state after reset is GPIO disconnected disconnected Internal Pull down resistor This input is 5 V tolerant PF8 Input GPIO Port F8 this signal is individually programmable as input output output or disconnected internally disconnected The default state after reset is GPIO disconnected disconnected Internal Pull down resistor This input is 5 V tolerant PF9 Input GPIO Port F9 this signal is individually programmable as input output output or disconnected internally disconnected The default state after reset is GPIO disconnected disconnected Internal Pull down resistor This input is 5 V tolerant PF10 Input GPIO Port F10 this signal is individually programmable as input output or disconnected output or internally disconnected The default state after reset is disconnected GPIO disconnected Internal Pull down resistor This input is 5 V tolerant DSP56371 Data Sheet Rev 4 1 Freescale Semiconductor 31 Signal Connection Descriptions 3 12 Timer Table 12 Timer Signal State Type during Signal Description Reset Signal Name TIOO Input or GPIO Input Timer 0 Schmitt Trigger Input Output When timer 0
14. PLLA 60 FST 4 80 005_ 010_ DSP56371 Data Sheet Rev 4 1 58 Freescale Semiconductor Package Information Se MECHANICAL OUTLINES DOCUMENT NO 98ASS23237W gt freescale DICTIONARY PAGE 917A semiconductor dah tu re eoe NE d Vip a ELECTRONIC VERSN ARE UNCON WHEN RECTLY FROM THE DOCUMENT CONTROL REPOSITORY TED VERSIONS ARE UNCONTROLLED EXCEPT WHEN STAMPED CONTROLLED COPY RES 00 NOT SCALE THIS DRAWING REV E 80X 0 38 am 0 32 PLANE 80 LD LOFP 14 X 14 PKG 0 65 MM PITCH 1 4 THICK DSP56371 Data Sheet Rev 4 1 Freescale Semiconductor 59 Package Information E Fm MECHANICAL OUTUNES DOCUMENT NO 98ASS23237W DICTIONARY PAGE 917A NI CE a EH TE Coa rosa en esas DO NOT SCALE THIS DRAWING REV E 0 38 A SECTION R R ROTATED 90 CW m 80 LD LQFP 14 X 14 PKG 0 65 MM PITCH 1 4 THICK DSP56371 Data Sheet Rev 4 1 60 Freescale Semiconductor Package Information ee DOCUMENT NO 98ASS23237W gt MECHANICAL OUTLINES 2 freescale DICTIONARY PAGE 917A FREESCALE SEMICONDUCTOR INC RIGHTS RESERVED ELECTRONIC VERSIONS ARE UNCONTROLLED EXCEPT WHEN ACCESSED eae me ern DO NOT SCALE THIS DRAWING REV NOTES DIMENSIONING AND TOLERANCING PER ASME Y14 5M 1994 CONTROLLING DIMENSION MILIMETER DATUM PLANE IS LOCATED AT THE BOTTOM OF
15. a system e ability to oscillate at different frequencies reduces costs by eliminating the need to add additional oscillators to a system NOTE The PLL will momentarily overshoot the target frequency when the PLL is first enabled or when the VCO frequency is modified It is important that when modifying the PLL frequency or enabling the PLL that the two step procedure defined in Section 3 DSP56371 Overview be followed 2 4 7 On Chip Memory The memory space of the DSP56300 core is partitioned into program memory space X data memory space and Y data memory space The data memory space is divided into X and Y data memory in order to work with the two Address ALUs and to feed two operands simultaneously to the Data ALU Memory space includes internal RAM and ROM and can not be expanded off chip There is an instruction patch module The patch module is used to patch program ROM The memory switch mode is used to increase the size of program RAM as needed switch from X data RAM and or Y data RAM There are on chip ROMs for program and bootstrap memory 64K x 24 bit X ROM 32K x 24 bit and Y ROM 32K x 24 bit More information on the internal memory is provided in the DSP56371 User s Manual Memory section 2 4 8 Off Chip Memory Expansion Memory cannot be expanded off chip There is no external memory bus DSP56371 Data Sheet Rev 4 1 8 Freescale Semiconductor DSP56371 Overview 2 5 Peripheral Overview The D
16. clock for the ESAI SCKT is a clock input or output used by all enabled transmitters and receivers in synchronous mode or by all enabled transmitters in asynchronous mode Port C3 When the ESAI is configured as GPIO this signal is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected Internal Pull down resistor This input is 5 V tolerant SDO5 SDIO PC6 Output Input Input output or disconnected GPIO disconnected Serial Data Output 5 When programmed as a transmitter SDO5 is used to transmit data from the TX5 serial transmit shift register Serial Data Input 0 When programmed as a receiver SDIO is used to receive serial data into the RXO serial receive shift register Port C6 When the ESAI is configured as GPIO this signal is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected Internal Pull down resistor This input is 5 V tolerant DSP56371 Data Sheet Rev 4 1 Freescale Semiconductor 21 Signal Connection Descriptions Table 8 Enhanced Serial Audio Interface Signals continued Signal Name Signal Type State during Reset Signal Description 004 5011 PC7 Output Input Input output or disconnected GPIO disconnected Serial Data Output 4 When programmed as a transmitter SDO4 is us
17. contents of either the A or B accumulator 56 bit result can be stored as 24 bit operand The LSP can either be truncated or rounded into the MSP Rounding is performed if specified DSP56371 Data Sheet Rev 4 1 Freescale Semiconductor 5 DSP56371 Overview 2 4 2 Address Generation Unit AGU The AGU performs the effective address calculations using integer arithmetic necessary to address data operands in memory and contains the registers used to generate the addresses It implements four types of arithmetic linear modulo multiple wrap around modulo and reverse carry The AGU operates in parallel with other chip resources to minimize address generation overhead The AGU is divided into two halves each with its own Address ALU Each Address ALU has four sets of register triplets and each register triplet is composed of an address register an offset register and a modifier register The two Address ALUs are identical Each contains a 24 bit full adder called an offset adder A second full adder called a modulo adder adds the summed result of the first full adder to a modulo value that is stored in its respective modifier register A third full adder called a reverse carry adder is also provided The offset adder and the reverse carry adder are in parallel and share common inputs The only difference between them is that the carry propagates in opposite directions Test logic determines which of the three summed results of
18. is GPIO disconnected Internal Pull down resistor This input is 5 V tolerant FST_1 PE4 Input or output Input output or disconnected GPIO disconnected Frame Sync for Transmitter_1 This is the transmitter frame sync input output signal For synchronous mode this signal is the frame sync for both transmitters and receivers For asynchronous mode FST 1 is the frame sync for the transmitters only The direction is determined by the transmitter frame sync direction TFSD bit in the ESAI 1 transmit clock control register 1 Port E4 When the ESAI 1 is configured as GPIO this signal is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected Internal Pull down resistor This input is 5 V tolerant DSP56371 Data Sheet Rev 4 1 Freescale Semiconductor 25 Signal Connection Descriptions Table 9 Enhanced Serial Audio Interface_1 Signals Signal Name Signal Type State during Reset Signal Description SCKR_1 PEO Input or output Input output or disconnected GPIO disconnected Receiver Serial Clock_1 SCKR_1 provides the receiver serial bit clock for the ESAI_1 The SCKR_1 operates as a clock input or output used by all the enabled receivers in the asynchronous mode SYN 0 or as serial pin in the synchronous mode SYN 1 When this pin is configured as serial flag p
19. logic voltage level for example either GND or Vpp The suggested value for a pull up or pull down resistor is 4 7 NOTE In the calculation of timing requirements adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum A maximum specification is calculated using a worst case variation of process parameter values in one direction The minimum specification is calculated using the worst case for the same parameters in the opposite direction Therefore a maximum value for a specification will never occur in the same device that has a minimum value for another specification adding a maximum to a minimum represents a condition that can never exist DSP56371 Data Sheet Rev 4 1 Freescale Semiconductor 33 Power Requirements Table 14 Maximum Ratings Rating Symbol Value 2 Unit Supply Voltage VCORE_VDD 0 3 to 1 6 V VPLLD_VDD VPLLP_VDD Vio 0 3 to 4 0 V VDD All 5 0V tolerant input voltages Vin GND 0 3 to 5 5V V Current drain per pin excluding Vpp and GND 12 Except for pads listed below SCK_SCL Isc 16 mA ACI PDO ADO PD1 24 TDO 24 Operating temperature range Ty 40 to 115 C Storage temperature 55 10 125 c Note 1 GND 0 V Ty 40 C to 115 C for 150 MHz Ty 0 C to 100 C for 181 MHz CL 2 Absolute maxi
20. shifter limiter circuits 2 4 1 1 Data ALU Registers The Data ALU registers can be read or written over the X memory data bus XDB and the Y memory data bus YDB as 24 or 48 bit operands or as 16 or 32 bit operands in 16 bit arithmetic mode The source operands for the Data ALU which can be 24 48 or 56 bits 16 32 or 40 bits in 16 bit arithmetic mode always originate from Data ALU registers The results of all Data ALU operations are stored in an accumulator All the Data ALU operations are performed in two clock cycles in pipeline fashion so that a new instruction can be initiated in every clock yielding an effective execution rate of one instruction per clock cycle The destination of every arithmetic operation can be used as a source operand for the immediately following arithmetic operation without a time penalty for example without a pipeline stall 2 4 1 2 Multiplier Accumulator MAC The MAC unit comprises the main arithmetic processing unit of the DSP56300 core and performs all of the calculations on data operands In the case of arithmetic instructions the unit accepts as many as three input operands and outputs one 56 bit result of the following form Extension Most Significant Product Least Significant Product EXT MSP LSP The multiplier executes 24 bit x 24 bit parallel fractional multiplies between two s complement signed unsigned or mixed operands The 48 bit product is right justified and added to the 56 bit
21. the ESAI 1 signals 3 Port D signals are the GPIO port signals which are multiplexed with the DAX signals 4 Port F signals are the dedicated GPIO port signals DSP56371 Data Sheet Rev 4 1 Freescale Semiconductor 11 Signal Connection Descriptions Pinout 80 pin package GPIO ag p SHI GPIOO lt 55 2 GPIO1 MISO HDA ye SCK SCL GPIO4 lt gt hEO 24 GPIO6 4 5 100 TIMER GPIO7 GPIO8 GPIO9 SCKT ESAI GPIO10 TC e FST lt SPDIF TRANSMITTER DAX lt SCKR ADO PD1 lt lt p FSR ACI PDO lt HCKR 5000 5001 INTERRUPTS lt 5002 5013 IRQA MODA p 5003502 IRGB MODB SDO4 SDI1 IRQC MODC c IRQD MODD 5005500 RESET lt SCKT 1 ESAI 1 gt FST PLL AND CLOCK _1 EXTAL gt SCKR 1 NMI PINIT FSR 1 PLL VDD 3 HCKR 1 PLL GND 3 5000 1 SDO1_1 CORE POWER 002 1 8013 1 CORE_VDD 4 5003 1 SDI2 1 5004 1 SDI1 1 4 5 5005 1 SDIO 1 CORE_GND 4 TDI OnCE JTAG SC PERIPHERAL I O POWER a IO VDD 5 TMS 4 GNDS 5 HWE SCAN SCAN Figure 2 Signals Identified by Functional Group DSP56371 Data Sheet Rev 4 1 12 Freescale Semiconductor 3 2 Signal Connection Descriptions Table 2 Power Inputs Power Name Description PLLA_VDD 1 PLLP_VDD 1 PLL Po
22. the external slave device it will trigger the start of the data word transfer by the master After finishing the data word transfer the master will await the next assertion of HREQ to proceed to the next transfer This signal is tri stated during hardware software personal reset or when the HREQ1 HREQO bits in the HCSR are cleared There is no need for an external pull up in this state Internal Pull up resistor This input is 5 V tolerant DSP56371 Data Sheet Rev 4 1 18 Freescale Semiconductor Signal Connection Descriptions 3 8 Enhanced Serial Audio Interface Table 8 Enhanced Serial Audio Interface Signals Signal Name Signal Type State during Reset Signal Description HCKR PC2 Input or output Input output or disconnected GPIO disconnected High Frequency Clock for Receiver When programmed as an input this signal provides a high frequency clock source for the ESAI receiver as an alternate to the DSP core clock When programmed as an output this signal can serve as a high frequency sample clock for example for external digital to analog converters DACs or as an additional system clock Port C2 When the ESAI is configured as GPIO this signal is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected Internal Pull down resistor This input is 5 V tolerant HCKT PC5
23. the full adders is output Each Address ALU can update one address register from its respective address register file during one instruction cycle The contents of the associated modifier register specifies the type of arithmetic to be used in the address register update calculation The modifier value is decoded in the Address ALU 2 4 3 Program Control Unit PCU The PCU performs instruction prefetch instruction decoding hardware DO loop control and exception processing The PCU implements a seven stage pipeline and controls the different processing states of the DSP56300 core The PCU consists of the following three hardware blocks e Program decode controller PDC e Program address generator PAG e Program interrupt controller The PDC decodes the 24 bit instruction loaded into the instruction latch and generates all signals necessary for pipeline control The PAG contains all the hardware needed for program address generation system stack and loop control The Program interrupt controller arbitrates among all interrupt requests internal interrupts as well as the five external requests IRQA IRQB IRQC IRQD and NMI and generates the appropriate interrupt vector address PCU features include the following Position independent code support e Addressing modes optimized for DSP applications including immediate offsets e On chip instruction cache controller On chip memory expandable hardware stack e Nested hardware
24. tolerant PF2 Input GPIO Port F2 this signal is individually programmable as input output output or disconnected internally disconnected The default state after reset is GPIO disconnected disconnected Internal Pull down resistor This input is 5 V tolerant Input GPIO Port F3 this signal is individually programmable as input output output or disconnected internally disconnected The default state after reset is GPIO disconnected disconnected Internal Pull down resistor This input is 5 V tolerant 4 Input GPIO Port F4 this signal is individually programmable as input output output or disconnected internally disconnected The default state after reset is GPIO disconnected disconnected Internal Pull down resistor This input is 5 V tolerant PF5 Input GPIO Port F5 this signal is individually programmable as input output output or disconnected internally disconnected The default state after reset is GPIO disconnected disconnected Internal Pull down resistor This input is 5 V tolerant PF6 Input GPIO Port F6 this signal is individually programmable as input output output or disconnected internally disconnected The default state after reset is GPIO disconnected disconnected Internal Pull down resistor This input is 5 V tolerant DSP56371 Data Sheet Rev 4 1 30 Freescale Semiconductor Signal Connection Descriptions Table 11 Dedicated
25. 1 Interrupt Requests Rate ESAI ESAI 1 SHI DAX Timer 12x Tc ns DMA 8xTc ns IRQ NMI edge trigger 8xTc ns RQ level trigger 12c Tc ns 22 Requests Rate Data read from ESAI ESAI_1 SHI DAX 6xTc ns Data write to ESAI ESAI 1 SHI DAX 7XTc ns Timer 2xTo m ns IRQ NMI edge trigger ns Note 1 When using fast interrupts and IRQA IRQB IRQC and IRQD are defined as level sensitive timings 19 through 21 apply to prevent multiple interrupt service To avoid these timing restrictions the deasserted Edge triggered mode is recommended when using fast interrupts Long interrupts are recommended when using Level sensitive mode 2 For PLL disable using external clock PCTL Bit 13 0 no stabilization delay is required and recovery time will be defined by the OMR Bit 6 settings For PLL enable if bit 12 of the PCTL register is 0 the PLL is shutdown during Stop Recovering from Stop requires the PLL to get locked The PLL lock procedure duration PLL Lock Cycles PLC may be in the range of 0 5 ms 3 Periodically sampled and not 100 tested 4 RESET duration is measured during the time in which RESET is asserted Vpp is valid and the EXTAL input is active and valid When the Vpp is valid but the other required RESET duration conditions as specified above have not been yet met the device circuitry will be in an uninitialized state that can re
26. 4 1 32 Freescale Semiconductor Maximum Ratings 3 13 JTAG OnCE Interface Table 13 JTAG OnCE Interface Signal Signal Stale MEE 1 during Signal Description Reset TCK Input Input Test Clock TCK is a test clock input signal used to synchronize the JTAG test logic It has an internal pull up resistor Internal Pull up resistor This input is 5 V tolerant TDI Input Input Test Data Input TDI is a test data serial input signal used for test instructions and data TDI is sampled on the rising edge of TCK and has an internal pull up resistor Internal Pull up resistor This input is 5 V tolerant TDO Output Tri state Data Output TDO is a test data serial output signal used for test instructions and data TDO is tri statable and is actively driven in the shift IR and shift DR controller states TDO changes on the falling edge of TCK TMS Input Input Test Mode Select TMS is an input signal used to sequence the test controllers state machine TMS is sampled on the rising edge of TCK and has an internal pull up resistor Internal Pull up resistor This input is 5 V tolerant 4 Maximum Ratings CAUTION This device contains circuitry protecting against damage due to high static voltage or electrical fields However normal precautions should be taken to avoid exceeding maximum voltage ratings Reliability of operation is enhanced if unused inputs are pulled to an appropriate
27. 6 SDO4 PE7 SDO3 SDI2 PE8 8002 SDI3 PE9 SDO1 PE10 SDOO PE11 CORE GND CORE VDD MODB IRQA MODB_IRQB MODC_IRQC MODD_IRQD RESET_B PINIT_NMI EXTAL PLLD_VDD PLLD_GND PLLP_GND PLLP_VDD Int Mod Timer OnCE TIOO PBO PB1 CORE LCORE VDD MOSI 5 SDA SS HA2 TDO TDI TCK TMS Figure 3 VDD Connections DSP56371 Data Sheet Rev 4 1 Freescale Semiconductor 13 Signal Connection Descriptions 3 3 Ground Table 3 Grounds Ground Name Description PLLA_GND 1 PLLP_GND 1 PLL Ground The PLL ground should be provided with an extremely low impedance path to ground The user must provide adequate external decoupling capacitors PLLD_GND 1 PLL Ground The PLL ground should be provided with an extremely low impedance path to ground The user must provide adequate external decoupling capacitors CORE_GND 4 Core Ground The Core ground should be provided with an extremely low impedance path to ground This connection must be tied externally to all other chip ground connections The user must provide adequate external decoupling capacitors IO GND 5 SHI ESAI ESAI 1 DAX and Timer I O Ground lO is an isolated ground for the SHI ESAI ESAI 1 DAX and Timer I O This connection must be tied externally to all other chip ground connections The user must provide adequate external decoupli
28. 65 SCKR edge to FSR out bl high 37 0 x ck ns 22 0 ick a 66 SCKR edge to FSR out bl low 37 0 ck ns 22 0 icka DSP56371 Data Sheet Rev 4 1 48 Freescale Semiconductor Enhanced Serial Audio Interface Timing Table 22 Enhanced Serial Audio Interface Timing continued No Characteristics 2 3 Symbol Expression Min Max Condition Unit 67 SCKR edge to FSR out wr high 39 0 x ck ns 24 0 i cka 68 SCKR edge to FSR out wr low 39 0 x ck ns 24 0 icka 69 SCKR edge to FSR out wl high 36 0 x ck ns 21 0 icka 70 SCKR edge to FSR out wl low m 37 0 x ck ns 22 0 ick a 71 Data in setup time before SCKR SCK in 12 0 X ck ns synchronous mode edge 19 0 i ck 72 Data in hold time after SCKR edge 5 0 x ck ns 3 0 i ck 73 FSR input bl wr high before SCKR edge m 2 0 X ck ns 23 0 icka 74 FSR input wl high before SCKR edge 2 0 ck ns 23 0 ick a 75 FSR input hold time after SCKR edge 3 0 X ck ns 0 0 icka 76 Flags input setup before SCKR edge 0 0 ck ns 19 0 i ck s 77 Flags input hold time after SCKR edge 6 0 x ck ns 0 0 i ck s 78 SCKT edge to FST out bl high 29 0 ck ns x 15 0 i ck 79 SCKT edge to
29. AI is configured as GPIO this signal is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected Internal Pull down resistor This input is 5 V tolerant DSP56371 Data Sheet Rev 4 1 22 Freescale Semiconductor Signal Connection Descriptions Table 8 Enhanced Serial Audio Interface Signals continued Signal State during Name Signal Type Reset Signal Description SDO1 Output GPIO Serial Data Output 1 SDO1 is used to transmit data from the 1 disconnected serial transmit shift register PC10 Input output or Port C10 When the ESAI is configured as GPIO this signal is disconnected individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected Internal Pull down resistor This input is 5 V tolerant SDOO Output GPIO Serial Data Output 0 SDOO is used to transmit data from the TXO disconnected serial transmit shift register PC11 Input output or Port C11 When the ESAI is configured as GPIO this signal is disconnected individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected Internal Pull down resistor This input is 5 V tolerant DSP56371 Data Sheet Rev 4 1 Freescale Semiconductor 23 Signal Connection Descriptions 3 9 Enhanced Serial Audio Interface_1 Table 9
30. DO loops e Fast auto return interrupts DSP56371 Data Sheet Rev 4 1 6 Freescale Semiconductor DSP56371 Overview The PCU implements its functions using the following registers PC program counter register SR Status register LA loop address register LC loop counter register base address register SZ stack size register SP stack pointer OMR operating mode register SC stack counter register The PCU also includes a hardware system stack SS 2 4 4 Internal Buses To provide data exchange between blocks the following buses are implemented Peripheral input output expansion bus PIO EB to peripherals Program memory expansion bus PM EB to program memory X memory expansion bus XM EB to X memory Y memory expansion bus YM EB to Y memory Global data bus GDB between registers in the AGU PLL BIU and PCU as well as the memory mapped registers in the peripherals DMA data bus DDB for carrying DMA data between memories and or peripherals DMA address bus DAB for carrying DMA addresses to memories and peripherals Program Data Bus PDB for carrying program data throughout the core X memory Data Bus XDB for carrying X data throughout the core Y memory Data Bus YDB for carrying Y data throughout the core Program address bus PAB for carrying program memory addresses throughout the core X memory address bus XAB for carrying X memory addresses through
31. Digital Audio Transmitter Timing 15 Digital Audio Transmitter Timing Table 23 Digital Audio Transmitter Timing 181 MHz No Characteristic Expression Unit Min Max 99 frequency see note 1 2 90 MHz 100 ACI period 2 11 1 ns 101 ACI high duration 0 5 x Tc 2 8 ns 102 ACIIow duration 0 5 x Tc 2 8 ns 103 rising edge to ADO valid 1 5x Tc 8 3 ns Note 1 In order to assure proper operation of the DAX the ACI frequency should be less than 1 2 of theDSP56371 internal clock frequency For example if the DSP56371 is running at 181 MHz internally the ACI frequency should be less than 90MHz ACI ADO Figure 18 Digital Audio Transmitter Timing DSP56371 Data Sheet Rev 4 1 Freescale Semi conductor 53 Timer Timing 16 Timer Timing Table 24 Timer Timing 181 MHz No Characteristics Expression Unit Min Max 104 TIO Low 2 2 0 13 ns 105 High 2 2 0 13 ns Note 1 vpp 1 25 V 0 05 v T 40 to 115 C for 150 MHz 0 C to 100 C for 181 MHz C 50 pF TIO puces Figure 19 TIO Timer Event Input Restrictions 17 GPIO Timing Table 25 GPIO Timing No Characteristics Expression Min Max Unit 106 FOSC edge to GPIO out valid GPIO out delay time 7 ns 107 FOSC edge t
32. Enhanced Serial Audio Interface_1 Signals Signal Name Signal Type State during Reset Signal Description HCKR_1 PE2 Input or output Input output or disconnected GPIO disconnected High Frequency Clock for Receiver When programmed as an input this signal provides a high frequency clock source for the ESAI_1 receiver as an alternate to the DSP core clock When programmed as an output this signal can serve as a high frequency sample clock for example for external digital to analog converters DACs or as an additional system clock Port E2 When the ESAI_1 is configured as GPIO this signal is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected Internal Pull down resistor This input is 5 V tolerant HCKT_1 Input or output Input output or disconnected GPIO disconnected High Frequency Clock for Transmitter When programmed as an input this signal provides a high frequency clock source for the ESAI_1 transmitter as an alternate to the DSP core clock When programmed as an output this signal can serve as a high frequency sample clock for example for external DACs or as an additional system clock Port E5 When the ESAI_1 is configured as GPIO this signal is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected In
33. Freescale Semiconductor DSP56371 Data Sheet Technical Data Rev 4 1 1 2007 DSP56371 Data Sheet 1 ntrod u ct i on Table of Contents T IBtreductolica sess erbe ee PR TUM RE RR 1 The DSP56371 is a high density CMOS device with 2 DSP56371 OVEMEW 22222 2 ak E RAE 1 3 Signal Connection Descriptions 10 5 0 compatible inputs and outputs 4 Maximum 33 NOTE 5 Power Mequirenients xad 34 2 i 6 Thermal Characteristics 35 This document contains information on a 7 Electrical Characteristics 36 new product Specifications and 8 AC Electrical Characteristics 37 information herein are subject to change 9 Internal Clocks 37 10 External Clock Operation 38 without notice 11 Reset Stop Mode Select and Interrupt Timing 39 E ERE 12 Serial Host Interface SPI Protocol Timing 42 Sp 13 Serial Host Interface SHI Protocol Timing 47 characterization and device qualifications are completed 44 Enhanced Serial Audio Interface Timing 49 15 Digital Audio Transmitter Timing 54 For software or simulation models for example IBIS 16 Timer eicere ERE 59 files contact sales or go to www freescale com 7 coa iid o dob ood dedo dea OR DER A 55 18
34. GPIO Serial Data Output 1 SDO1_1 is used to transmit data from the disconnected TX1 serial transmit shift register PE10 Input output or Port E10 When the ESAI_1 is configured as GPIO this signal disconnected is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected Internal Pull down resistor This input is 5 V tolerant SDOO 1 Output GPIO Serial Data Output 0 SDO O 116 used to transmit data from the disconnected serial transmit shift register PE11 Input output or Port E11 When the ESAI 1 is configured as GPIO this signal disconnected is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected Internal Pull down resistor This input is 5 V tolerant DSP56371 Data Sheet Rev 4 1 28 Freescale Semiconductor Signal Connection Descriptions 3 10 SPDIF Transmitter Digital Audio Interface Table 10 Digital Audio Interface DAX Signals Signal State During Name Type Reset Signal Description ACI Input GPIO Audio Clock Input This is the DAX clock input When Disconnected programmed to use an external clock this input supplies the DAX clock The external clock frequency must be 256 384 or 512 times the audio sampling frequency 256 x Fs 384 x Fs or 512 x Fs respectively PDO Input Port DO When the DAX is configured a
35. I refer to DSP56371 User s Manual Serial Host Interface section 2 5 6 Digital Audio Transmitter DAX The DAX is a serial audio interface module that outputs digital audio data in the AES EBU CP 340 and 958 formats For more information on DAX refer to DSP56371 User s Manual Digital Audio section 3 Signal Connection Descriptions 3 1 Signal Groupings The input and output signals of the DSP56374 are organized into functional groups which are listed in Table 1 and illustrated in Figure 2 The DSP56374 is operated from a 1 25 V and 3 3 V supply however some of the inputs can tolerate 5 0 V A special notice for this feature is added to the signal descriptions of those inputs DSP56371 Data Sheet Rev 4 1 10 Freescale Semiconductor Signal Connection Descriptions Table 1 DSP56374 Functional Signal Groupings Number of Detailed Functional Group ae Signals Description Power Vpp 12 Table 2 Ground GND 12 Table 3 Scan Pins 1 Table 4 Clock and PLL 2 Table 5 Interrupt and mode control 5 Table 6 SHI 5 Table 7 ESAI Port 12 Table 8 1 12 9 SPDIF Transmitter DAX Port D 2 Table 10 Dedicated GPIO Port F 11 Table 11 Timer 2 Table 12 JTAG OnCE Port 4 Table 13 Note 1 Port C signals are the GPIO port signals which are multiplexed with the ESAI signals 2 Port E signals are the GPIO port signals which are multiplexed with
36. Input or output Input output or disconnected GPIO disconnected High Frequency Clock for Transmitter When programmed as an input this signal provides a high frequency clock source for the ESAI transmitter as an alternate to the DSP core clock When programmed as an output this signal can serve as a high frequency sample clock for example for external DACs or as an additional system clock Port C5 When the ESAI is configured as GPIO this signal is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected Internal Pull down resistor This input is 5 V tolerant DSP56371 Data Sheet Rev 4 1 Freescale Semiconductor 19 Signal Connection Descriptions Table 8 Enhanced Serial Audio Interface Signals continued State during Reset Signal Name Signal Description Signal Type FSR Input or output GPIO Frame Sync for Receiver This is the receiver frame sync disconnected input output signal In the asynchronous mode SYN 0 the FSR pin operates as the frame sync input or output used by all the enabled receivers In the synchronous mode SYN 1 it operates as either the serial flag 1 pin TEBE 0 or as the transmitter external buffer enable control TEBE 1 RFSD 1 When this pin is configured as serial flag pin its direction is determined by the RFSD bit in the RCCR register When configured as the output flag OF 1 t
37. LEAD AND 15 COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE DATUM E F AND D TO BE DETERMINED AT DATUM PLANE H DIMENSIONS TO BE DETERMINED AT SEATING PLANE C DIMENSIONS DO NOT INCLUDE MOLD PROTRUSION ALLOWABLE PROTRUSION IS 0 25 PER SIDE DIMENSIONS DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE H DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0 46 MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0 07 80 LD LQFP 14 X 14 PKG 0 65 MM PITCH 1 4 THICK DSP56371 Data Sheet Rev 4 1 Freescale Semiconductor 61 Package Information t DOCUMENT NO 98ASS23237W gt freescale REVISION HISTORY Pace 917A FREESCALE SEMICONDUCTOR INC ALL RIGHTS RESERVED ELECTRONIC VERSIONS ARE UNCONTROLLED EXCEPT WHEN ACCESSED DIRECTLY FROM THE DOCUMENT CONTROL REPOSITORY PRINTED VERSIONS REV ARE UNCONTROLLED EXCEPT WHEN STAMPED CONTROLLED COPY IN RED E ORIGINATOR REVISIONS DRAFTER DATE o GARY JOHNSON REFORMAT DOCUMENT DELETED DUAL DIMENSIONS INCH AZHAR 11 MAR 2004 CHANGED DOCUMENT TITLE FROM TQFP TO LQFP PATRICE L UPDATED DRAWNGS PER FREESCALE FORMAT KL CHIN 7 OCT 2004 CASE NUMBER 917 03 80 LQFP 14 X 14 PKG STANDARD FREESCALE 0 65 MM PITCH 1 4 THICK 3 DSP56371 Data Sheet Rev 4 1 62 Freescale Sem
38. MHz and rated speed DSP56371 Data Sheet Rev 4 1 36 Freescale Semiconductor 9 Internal Clocks Table 17 INTERNAL CLOCKS Internal Clocks No Characteristics Symbol Min Typ Max UNIT Condition 1 Comparison Frequency Fref 5 20 MHZ Fref FN NR 2 Input Clock Frequency FIN Fref NR NR is input divider value 3 Output clock Frequency with FOUT 75 1000 Etc x MF MHZ FOUT FVCO NO PLL enabled PDF x DF x OD where NO is output Tc 13 3 ns divider value 4 Output clock Frequency with FOUT 1000 Etc MHZ PLL disabled Tc 5 Duty Cycle 40 50 60 FVCO 300MHZ 600MHZ Note See users manual for definition 2 DF Division Factor Ef External frequency MF Multiplication Factor PDF Predivision Factor FM Feedback Multiplier OD Output Divider Tc internal clock period 3 Maximum frequency will vary depending on the ordered part number 10 External Clock Operation The DSP56371 system clock is an externally supplied square wave voltage source connected to EXTAL see Figure 4 Note The midpoint is 0 5 Viz Figure 4 External Clock Timing DSP56371 Data Sheet Rev 4 1 Freescale Semiconductor 37 Reset Stop Mode Select and Interrupt Timing Table 18 Clock Operation 150 and 181 MHz Values 150 MHz 181 MHz No Characteristics Symbol Min Ma
39. Manual Pinout memory and peripheral features are described in this manual e DSP56300 modular chassis 181 Million Instructions Per Second MIPS with a 181 MHz clock at an internal logic supply QVDDL of 1 25 V Object Code Compatible with the 56K core Data ALU with a 24 x 24 bit multiplier accumulator and a 56 bit barrel shifter 16 bit arithmetic support Program Control with position independent code support and instruction patch support EFCOP running concurrently with the core capable of executing 181 million filter taps per second at peak performance Six channel DMA controller Low jitter PLL based clocking with a wide range of frequency multiplications 1 to 255 predivider factors 1 to 31 and power saving clock divider 2 i 0 to 7 Reduces clock noise Internal address tracing support and OnCE for Hardware Software debugging JTAG port Very low power CMOS design fully static design with operating frequencies down to DC STOP and WAIT low power standby modes e On chip Memory Configuration 48 24 Bit Y Data RAM and 32Kx24 Bit Y Data ROM 36 24 Bit X Data RAM and 32Kx24 Bit X Data ROM 64 24 Bit Program and Bootstrap ROM 4 24 Bit Program RAM PROM patching mechanism Up to 32Kx24 Bit from Y Data RAM and 8Kx24 Bit from X Data RAM can be switched to Program RAM resulting in up to 44Kx24 Bit of Program RAM e Peripheral modules Enhanced Se
40. ODA IRQA EXTAL MODB IRQB RESET MODC IRQC PINIT NMI MODD IRQD Figure 1 DSP56371 Block Diagram 2 2 DSP56300 Core Description The DSP56371 uses the DSP56300 core a high performance single clock cycle per instruction engine that provides up to twice the performance of Motorola s popular DSP56000 core family while retaining code compatibility with it DSP56371 Data Sheet Rev 4 1 2 Freescale Semiconductor DSP56371 Overview The DSP56300 core family offers a new level of performance in speed and power provided by its rich instruction set and low power dissipation thus enabling a new generation of wireless telecommunications and multimedia products For a description of the DSP56300 core see Section 2 4 DSP56300 Core Functional Blocks Significant architectural enhancements to the DSP56300 core family include a barrel shifter 24 bit addressing an instruction patch module and direct memory access DMA The DSP56300 core family members contain the DSP56300 core and additional modules The modules are chosen from a library of standard pre designed elements such as memories and peripherals New modules may be added to the library to meet customer specifications A standard interface between the DSP56300 core and the on chip memory and peripherals supports a wide variety of memory and peripheral configurations Refer to DSP56371 User s Manual Memory Configuration section Core features are described fully in the DSP56300 Family
41. P_GND GND PLLP_VDD PF9 SCAN PF10 IO GND IO VDD TIOO_PBO TIO1 PB1 CORE GND CORE VDD TDO TDI TCK TMS MOSI_HAO MISO_SDA SCK_SCL SS_HA2 HREQ PLLA_VDD PLLA_GND Figure 24 DSP56371 Pinout DSP56371 Data Sheet Rev 4 1 Freescale Semiconductor 57 Package Information Table 27 Signal Identification by Pin Number Signal Name Signal Name 3A Signal Name Signal Name 1 5004 011 7 21 PF9 41 PLLP_VDD 61 FSR_PE1 2 22 SCAN 42 PLLP_GND 62 SCKT_PE3 3 IO_VDD 23 PF10 43 PLLD GND 63 SCKR PEO 4 5 SDI2 PC8 24 IO_GND 44 PLLD_VDD 64 IO_VDD 5 SDO2_SDI3_PC9 25 IO_VDD 45 EXTAL 65 IO_GND 6 SDO1_PC10 26 TIO PBO 46 PINIT_NMI 66 _ 7 SDOO 11 27 110 PB1 47 RESET 67 HCKR PE2 8 CORE VDD 28 CORE GND 48 MODD IRQD 68 CORE GND 9 29 49 MODC IRQC 69 ADO_PD1 10 PF6 30 TDO 50 MODB 70 ADI_PDO 11 PF7 31 TDI 51 MODA_IRQA 71 CORE 12 CORE GND 32 52 CORE 72 HCKR PC2 18 PF2 33 5 53 CORE GND 73 HCKT2 PC5 14 34 MOSI HAO 54 SDOO PE11 74 IO_GND 15 PF4 35 MISO_SDA 55 SDO1_PE10 75 IO_VDD 16 PF5 36 SCK SCL 56 SDO2 5013 PE9 76 SCKR PCO 17 VDD 37 SS HA2 57 18003 SDI2 77 SCKT 18 PF1 38 HREQ 58 SDO4_SDI1_PE7 78 FSR_PC1 19 PFO 39 PLLA VDD 59 SDO5_SD10_PE6 79 FST 4 20 GND 40
42. SP56371 is designed to perform a wide variety of fixed point digital signal processing functions In addition to the core features previously discussed the DSP56371 provides the following peripherals e As many as 39 dedicate or user configurable general purpose input output GPIO signals Timer event counter TEC module containing three independent timers Memory switch mode in on chip memory e Four external interrupt mode control lines and one external non maskable interrupt line e Enhanced serial audio interface ESAT with up to four receivers and up to six transmitters master or slave using the PS Sony AC97 network and other programmable protocols e second enhanced serial audio interface ESAI 1 with up to four receivers and up to six transmitters master or slave using the PS Sony AC97 network and other programmable protocols e Serial host interface SHI using SPI and protocols with multi master capability 10 word receive FIFO and support for 8 16 and 24 bit words e A Digital audio transmitter DAX a serial transmitter capable of supporting the SPDIF IEC958 CP 340 and AES EBU digital audio formats 2 5 1 General Purpose Input Output GPIO The DSP56371 provides 11 dedicated GPIO and 28 programmable signals that can operate either as GPIO pins or peripheral pins ESAI ESAI 1 DAX and TEC The signals are configured as GPIO after hardware reset Register programming techniques for all GPIO functional
43. Serial Data Output 5_1 When programmed as a transmitter 5005 1 is used to transmit data from the TX5 serial transmit shift register Serial Data Input 0 1 When programmed as a receiver SDIO 1 is used to receive serial data into the RXO serial receive shift register Port E6 When the ESAI 1 is configured as GPIO this signal is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected Internal Pull down resistor This input is 5 V tolerant DSP56371 Data Sheet Rev 4 1 26 Freescale Semiconductor Signal Connection Descriptions Table 9 Enhanced Serial Audio Interface_1 Signals Signal Name Signal Type State during Reset Signal Description 004_1 SDI1_1 PE7 Output Input Input output or disconnected GPIO disconnected Serial Data Output 4_1 When programmed as a transmitter SDOA 1 is used to transmit data from the TX4 serial transmit shift register Serial Data Input 1_1 When programmed as a receiver 1 is used to receive serial data into the RX1 serial receive shift register Port E7 When the ESAI 1 is configured as GPIO this signal is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected Internal Pull down resistor This input is 5 V tolerant 5003 1 SDI2 1 Output Input Input output or
44. al Pull up resistor This input is 5 V tolerant MODC IRQC Input Input Select C External Interrupt Request C MODC IRQC is an active low Schmitt trigger input internally synchronized to the DSP clock MODC IRQC selects the initial chip operating mode during hardware reset and becomes a level sensitive or negative edge triggered maskable interrupt request input during normal instruction processing MODA MODB MODC and MODD select one of 16 initial chip operating modes latched into OMR when the RESET signal is deasserted Internal Pull up resistor This input is 5 V tolerant MODD IRQD Input Input Select D External Interrupt Request D MODD IRQD is an active low Schmitt trigger input internally synchronized to the DSP clock MODD IRQD selects the initial chip operating mode during hardware reset and becomes a level sensitive or negative edge triggered maskable interrupt request input during normal instruction processing MODA MODB MODC and MODD select one of 16 initial chip operating modes latched into OMR when the RESET signal is deasserted Internal Pull up resistor This input is 5 V tolerant RESET Input Input Reset RESET is an active low Schmitt trigger input When asserted the chip is placed in the Reset state and the internal phase generator is reset The Schmitt trigger input allows a slowly rising input such as a capacitor charging to reset the chip reliably When the RESET sign
45. al is deasserted the initial chip operating mode is latched from the MODA MODB MODC and MODD inputs The RESET signal must be asserted during power up A stable EXTAL signal must be supplied while RESET is being asserted Internal Pull up resistor This input is 5 V tolerant 3 7 Serial Host Interface The SHI has five I O signals that can be configured to allow the SHI to operate in either SPI or mode DSP56371 Data Sheet Rev 4 1 16 Freescale Semiconductor Signal Connection Descriptions Table 7 Serial Host Interface Signals Signal Name Signal Type State during Reset Signal Description SCK SCL Input or output Input or output Tri stated SPI Serial Clock The SCK signal is an output when the SPI is configured as a master and a Schmitt trigger input when the SPI is configured as a slave When the SPI is configured as a master the SCK signal is derived from the internal SHI clock generator When the SPI is configured as a slave the SCK signal is an input and the clock signal from the external master synchronizes the data transfer The SCK signal is ignored by the SPI if it is defined as a slave and the slave select SS signal is not asserted In both the master and slave SPI devices data is shifted on one edge of the SCK signal and is sampled on the opposite edge where data is stable Edge polarity is determined by the SPI transfer protocol Serial Cloc
46. ance may need the additional modeling capability of a system level thermal simulation tool The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the package is mounted Again if the estimations obtained from do not satisfactorily answer whether the thermal performance is adequate a system level model may be appropriate A complicating factor is the existence of three common ways for determining the junction to case thermal resistance in plastic packages minimize temperature variation across the surface the thermal resistance is measured from the junction to the outside surface of the package case closest to the chip mounting area when that surface has a proper heat sink e To define a value approximately equal to a junction to board thermal resistance the thermal resistance is measured from the junction to where the leads are attached to the case Ifthe temperature of the package case TT is determined by a thermocouple the thermal resistance is computed using the value obtained by the equation T Tr Pp DSP56371 Data Sheet Rev 4 1 Freescale Semiconductor 63 Electrical Design Considerations As noted above the junction to case thermal resistances quoted in this data sheet are determined using the first definition From a practical standpoint that value is also suitable for determining the junction temperature from a case thermocouple reading in forced conv
47. board ground to each GND pin e Use at least six 0 01 0 1 bypass capacitors positioned as close as possible to the four sides of the package to connect the power source to GND Ensure that capacitor leads and associated printed circuit traces that connect to the chip and GND pins are less than 1 2 cm 0 5 inch per capacitor lead e Route the DVDD pin carefully to minimize noise Use at least a four layer PCB with two inner layers for and GND Because the DSP output signals have fast rise and fall times PCB trace lengths should be minimal This recommendation particularly applies to the IRQA IRQB IRQC and IRQD pins Maximum PCB trace lengths on the order of 15 cm 6 inches are recommended e Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance This is especially critical in systems with higher capacitive loads that could create higher transient currents in the and GND circuits e special to minimize noise levels on the Vccp GNDp pins If multiple DSP56371 devices are the same board check for cross talk or excessive spikes the supplies due to synchronous operation of the devices RESET must be asserted when the chip is powered up A stable EXTAL signal must be supplied before deassertion of RESET DSP56371 Data Sheet Rev 4 1 64 Freescale Semiconductor Electrical Design Consideratio
48. ection environments In natural convection using the junction to case thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will estimate a junction temperature slightly hotter than actual temperature Hence the new thermal metric thermal characterization parameter or has been defined to be Tj Ty Pp This value gives a better estimate of the junction temperature in natural convection when using the surface temperature of the package Remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor The recommended technique is to attach a 40 gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy 21 Electrical Design Considerations CAUTION This device contains circuitry protecting against damage due to high static voltage or electrical fields However normal precautions should be taken to avoid exceeding maximum voltage ratings Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level for example either GND or The suggested value for a pull up or pull down resistor is 10 k ohm Use the following list of recommendations to assure correct DSP operation Provide a low impedance path from the board power supply to each pin on the DSP and from the
49. ed to transmit data from the TX4 serial transmit shift register Serial Data Input 1 When programmed as a receiver SDI1 is used to receive serial data into the RX1 serial receive shift register Port C7 When the ESAI is configured as GPIO this signal is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected Internal Pull down resistor This input is 5 V tolerant 003 5012 Output Input Input output or disconnected GPIO disconnected Serial Data Output 3 When programmed as a transmitter SDO3 is used to transmit data from the TX3 serial transmit shift register Serial Data Input 2 When programmed as a receiver SDI2 is used to receive serial data into the RX2 serial receive shift register Port C8 When the ESAI is configured as GPIO this signal is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected Internal Pull down resistor This input is 5 V tolerant 002 5083 PC9 Output Input Input output or disconnected GPIO disconnected Serial Data Output 2 When programmed as a transmitter SDO2 is used to transmit data from the TX2 serial transmit shift register Serial Data Input 3 When programmed as a receiver SDI3 is used to receive serial data into the RX3 serial receive shift register Port C9 When the ES
50. ement methodology to minimize specific board effects for example to compensate for measured board current not caused by the DSP Use the test algorithm specific test current measurements and the following equation to derive the current per MIPS value MIPS MHz 1 loei F2 Eqn 8 where lyyp current at F2 I p 7current at F2 high frequency any specified operating frequency Fl low frequency any specified operating frequency lower than F2 NOTE F1 should be significantly less than F2 For example F2 could be 66 MHz and F1 could be 33 MHz The degree of difference between F1 and F2 determines the amount of precision with which the current rating can be determined for an application DSP56371 Data Sheet Rev 4 1 Freescale Semiconductor 65 Power Consumption Benchmark 22 Power Consumption Benchmark The following benchmark program permits evaluation of DSP power usage in a test situation CHECKS Typical Power Consumption ORG P 000800 move 000000 r1 move 000000 r0 do 1024 1dmem move 1 0 move rl y r0 ldmem nop move 0 b1 jmp FF2AEO org 5 2 move b1 y gt 100 move SFF B move gt SAF080 xX0 move gt SFF2AD6 r0 move 50 1
51. functions as an Output external event counter or in measurement mode TIOO is used as input When timer 0 functions in watchdog timer or pulse modulation mode TIOO is used as output The default mode after reset is GPIO input This can be changed to output or configured as a timer input output through the timer 0 control status register TCSRO If TIOO is not being used it is recommended to either define it as GPIO output immediately at the beginning of operation or leave it defined as GPIO input but connected to VDD through a pull up resistor in order to ensure a stable logic level at this input Internal Pull down resistor This input is 5 V tolerant TIO1 Input or GPIO Input Timer 1 Schmitt Trigger Input Output When timer 1 functions as an Output external event counter or in measurement mode TIO1 is used as input When timer 1 functions in watchdog timer or pulse modulation mode TIO1 is used as output The default mode after reset is GPIO input This can be changed to output or configured as a timer input output through the timer 1 control status register TCSR1 If TIO1 is not being used it is recommended to either define it as GPIO output immediately at the beginning of operation or leave it defined as GPIO input but connected to Vdd through a pull up resistor in order to ensure a stable logic level at this input Internal Pull down resistor This input is 5 V tolerant DSP56371 Data Sheet Rev
52. his pin will reflect the value of the OF1 bit in the SAICR register and the data in the OF1 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode When configured as the input flag IF1 the data value at the pin will be stored in the IF1 bit in the SAISR register synchronized by the frame sync in normal mode or the slot in network mode PC1 Input output or Port C1 When the ESAI is configured as GPIO this signal is disconnected individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected Internal Pull down resistor This input is 5 V tolerant FST Input or output GPIO Frame Sync for Transmitter This is the transmitter frame sync disconnected input output signal For synchronous mode this signal is the frame sync for both transmitters and receivers For asynchronous mode FST is the frame sync for the transmitters only The direction is determined by the transmitter frame sync direction TFSD bit in the ESAI transmit clock control register TCCR 4 Input output Port C4 When the ESAI is configured as GPIO this signal is disconnected individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected Internal Pull down resistor This input is 5 V tolerant DSP56371 Data Sheet Rev 4 1 20 Freescale Semiconductor Signal
53. iconductor Design Considerations 20 Design Considerations 20 1 Thermal Design Considerations An estimation of the chip junction temperature in C can be obtained from the following equation T PpX Roza Eqn 4 Where TA ambient temperature C Rgya package junction to ambient thermal resistance C W Pp power dissipation in package W Historically thermal resistance has been expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance Rosa Peca Eqn 5 Where RgjA package junction to ambient thermal resistance C W Rgyc package junction to case thermal resistance C W RocA package case to ambient thermal resistance C W Rgjc is device related and cannot be influenced by the user The user controls the thermal environment to change the case to ambient thermal resistance Roc 4 For example the user can change the air flow around the device add a heat sink change the mounting arrangement on the printed circuit board or otherwise change the thermal dissipation capability of the area surrounding the device on a PCB This model is most useful for ceramic packages with heat sinks some 90 of the heat flow is dissipated through the case to the heat sink and out to the ambient environment For ceramic packages in situations where the heat flow is split between a path to the case and an alternate path through the PCB analysis of the device thermal perform
54. ie and the case top surface as measured by the cold plate method MIL SPEC 883 Method 1012 1 7 DC Electrical Characteristics Table 16 DC ELECTRICAL CHARACTERISTICS Characteristics Symbol Min Typ Max Unit Supply voltages Vpp 1 2 1 25 1 31 V Core core vdd e PLL plld vdd Supply voltages Vppio 3 14 3 3 3 46 V Vio vdd e PLL pllp vdd PLL plla vdd Input high voltage V All pins 2 0 2 Note All 3 3 V supplies must rise prior to the rise of the 1 25 V supplies to avoid a current condition and possible system damage Input low voltage All pins Vit 0 3 0 8 V Input leakage current All pins lin 84 uA Clock pin Input Capacitance EXTAL Cin 3 749 pF High impedance off state input current 84 84 uA 3 46 V Output high voltage Vou 2 4 V 5 Output low voltage VoL 0 4 V lot 5mA Internal supply current at internal clock of 181MHz Normal mode 99 200 mA DSP56371 Data Sheet Rev 4 1 Freescale Semiconductor 35 AC Electrical Characteristics Table 16 DC ELECTRICAL CHARACTERISTICS Characteristics Symbol Min Typ Max Unit In Wait mode lccw 48 150 In Stop mode lccs 2 5 82 mA Input capacitance Cin 10 pF Note 1 Section 3 Power Consumption Considerations provides a formula
55. in its direction is determined by the RCKD bit in the RCCR_1 register When configured as the output flag OFO this pin will reflect the value of the OFO bit in the SAICR_1 register and the data in the OFO bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode When configured as the input flag IFO the data value at the pin will be stored in the IFO bit in the SAISR_1 register synchronized by the frame sync in normal mode or the slot in network mode Port EQ When the ESAI_1 is configured as GPIO this signal is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected Internal Pull down resistor This input is 5 V tolerant SCKT 1 PES Input or output Input output or disconnected GPIO disconnected Transmitter Serial Clock 1 This signal provides the serial bit rate clock for the ESAI 1 SCKT_1 isa clock input or output used by all enabled transmitters and receivers in synchronous mode or by all enabled transmitters in asynchronous mode Port E3 When the ESAI 1 is configured as GPIO this signal is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected Internal Pull down resistor This input is 5 V tolerant 5005 1 SDIO 1 Output Input Input output or disconnected GPIO disconnected
56. ity among these interfaces are very similar and are described in the following sections 2 5 2 Triple Timer TEC This section describes a peripheral module composed of a common 21 bit prescaler and three independent and identical general purpose 24 bit timer event counters each one having its own register set Each timer can use internal or external clocking and can interrupt the DSP after a specified number of events clocks Two of the three timers can signal an external device after counting internal events Each timer can also be used to trigger DMA transfers after a specified number of events clocks occurred Two of the three timers connect to the external world through bidirectional pins TIOO TIO1 When a TIO pin is configured as input the timer functions as an external event counter or can measure external pulse width signal period When a TIO pin is used as output the timer is functioning as either a timer a watchdog or a Pulse Width Modulator When a TIO pin is not used by the timer it can be used as a General Purpose Input Output Pin Refer to DSP56371 User s Manual Triple Timer Module section 2 5 3 Enhanced Serial Audio Interface ESAI The ESAI provides a full duplex serial port for serial communication with a variety of serial devices including one or more industry standard codecs other DSPs microprocessors and peripherals that DSP56371 Data Sheet Rev 4 1 Freescale Semiconductor 9 Signal Connection Descriptions
57. k SCL carries the clock for bus transactions in the mode SCL is a Schmitt trigger input when configured as a slave and an open drain output when configured as a master SCL should be connected to Vpp through a pull up resistor This signal is tri stated during hardware software and individual reset Thus there is no need for an external pull up in this state Internal Pull up resistor This input is 5 V tolerant MISO SDA Input or output Input or open drain output Tri stated SPI Master In Slave Out When the SPI is configured as a master MISO is the master data input line The MISO signal is used in conjunction with the MOSI signal for transmitting and receiving serial data This signal is a Schmitt trigger input when configured for the SPI Master mode an output when configured for the SPI Slave mode and tri stated if configured for the SPI Slave mode when SS is deasserted An external pull up resistor is not required for SPI operation Data and Acknowledge In mode SDA is a Schmitt trigger input when receiving and an open drain output when transmitting SDA should be connected to Vpp through a pull up resistor SDA carries the data for transactions The data in SDA must be stable during the high period of SCL The data in SDA is only allowed to change when SCL is low When the bus is free SDA is high The SDA line is only allowed to change during the time SCL is high in the case of
58. mum ratings are stress ratings only and functional operation at the maximum is not guaranteed Stress beyond the maximum rating may affect device reliability or cause permanent damage to the device 3 Operating temperature qualified for automotive applications 5 Power Requirements To prevent high current conditions due to possible improper sequencing of the power supplies the connection shown below is recommended to be made between the DSP56371 IO VDD and CORE VDD power pins IO VDD External Schottky CORE VDD Diode To prevent a high current condition upon power up the IOVDD must be applied ahead of the CORE VDD as shown below if the external Schottky is not used CORE VDD IO VDD DSP56371 Data Sheet Rev 4 1 34 Freescale Semiconductor Thermal Characteristics 6 Thermal Characteristics Table 15 Thermal Characteristics Characteristic Symbol TQFP Value Unit Natural Convection Junction to ambient thermal Roya Or OJA 39 C W resistance Junction to case thermal resistance Rouc or Oje 18 25 C W Note 1 Junction temperature is a function of die size on chip power dissipation package thermal resistance mounting site board temperature ambient temperature air flow power dissipation of other components on the board and board thermal resistance 2 Per SEMI G38 87 and JEDEC JESD51 2 with the single layer board horizontal 3 Thermal resistance between the d
59. nd HRS bits of the HCKR SHI clock control register The expression for is Teccp Tc x 2 x HDM 7 0 1 x 7 x 1 HRS 1 Eqn 1 where HRS is the pre scaler rate select bit When HRS is cleared the fixed divide by eight pre scaler is operational When HRS is set the pre scaler is bypassed HDM 7 0 are the divider modulus select bits A divide ratio from to 256 HDM 7 0 00 to may be selected DSP56371 Data Sheet Rev 4 1 Freescale Semiconductor 47 Enhanced Serial Audio Interface Timing In mode the user may select a value for the programmed serial clock cycle from 6 x if HDM 7 0 02 and HRS 1 Eqn 2 to 4096 x if HDM 7 0 FF and HRS 0 Eqn 3 The programmed serial clock cycle SCL rise time should be chosen in order to achieve the desired SCL serial clock cycle Tsc as shown in Table 22 SCL SDA Figure 13 Timing 14 Enhanced Serial Audio Interface Timing Table 22 Enhanced Serial Audio Interface Timing No Characteristics 2 3 Symbol Expression Min Max Condition Unit 62 Clock cycle tssicc ART 223 x ck ns 4 223 i ck 63 Clock high period tssiccH For internal clock 2 X Tc 12 0 ns For external clock 2 6 12 0 64 Clock low period tesiccL For internal clock 2x Tg 12 0 ns For external clock 2 X Tc 12 0
60. ng capacitors 3 4 SCAN Table 4 SCAN Signals Signal State g Type During Signal Description Name Reset SCAN Input Input SCAN Manufacturing test pin This pin should be pulled low Internal Pull down resistor 3 5 Clock and PLL Table 5 Clock and PLL Signals Signal state 9 during Signal Description Name Reset EXTAL Input Input External Clock Input An external clock source must be connected to EXTAL in order to supply the clock to the internal clock generator and PLL This input is 5 V tolerant PINIT NMI Input Input PLL Initial Nonmaskable Interrupt During assertion of RESET the value of PINIT NMI is written into the PLL Enable PEN bit of the PLL control register determining whether the PLL is enabled or disabled After RESET de assertion and during normal instruction processing the PINIT NMI Schmitt trigger input is a negative edge triggered nonmaskable interrupt NMI request internally synchronized to internal system clock Internal Pull up resistor This input is 5 V tolerant DSP56371 Data Sheet Rev 4 1 14 Freescale Semiconductor Signal Connection Descriptions 3 6 Interrupt and Mode Control The interrupt and mode control signals select the chip s operating mode as it comes out of hardware reset After RESET is deasserted these inputs are hardware interrupt request lines Table 6 Interrupt and Mode Control
61. ns At power up ensure that the voltage difference between 3 3 V tolerant pins and the chip never exceeds a 3 00 V 21 1 Power Consumption Considerations Power dissipation is a key issue in portable DSP applications Some of the factors which affect current consumption are described in this section Most of the current consumed by CMOS devices is alternating current ac which is charging and discharging the capacitances of the pins and internal nodes Current consumption is described by the following formula I CxVxf 6 where C node pin capacitance V voltage swing f frequency of node pin toggle Power Consumption Example For a GPIO address pin loaded with 50 pF capacitance operating at 3 3 V and with a 150 MHz clock toggling at its maximum possible rate 75 MHz the current consumption is I 50 10 12 3 3 75 106 12 375 Eqn 7 The maximum internal current Iccjmax value reflects the typical possible switching of the internal buses on best case operation conditions which is not necessarily a real application case The typical internal current value reflects the average switching of the internal buses on typical operating conditions For applications that require very low current consumption do the following Minimize the number of pins that are switching Minimize the capacitive load on the pins One way to evaluate power consumption is to use a current per MIPS measur
62. ns 27 55 assertion to first edge 0 Slave 2 0 12 6 34 4 ns CPHA 1 Slave x 10 0 ns 28 Last SCK edge to 58 not asserted Slave 12 0 ns 29 Data input valid SCK edge data input set up time Master Slave 0 ns 30 SCK last sampling edge to data input not valid Master Slave 3 0 x Tc 22 4 ns 31 55 assertion to data out active Slave 5 ns 32 55 deassertion to data high impedance Slave 9 ns 33 SCK edge to data out valid Master Slave 3 0x 26 1 50 0 100 ns data out delay time DSP56371 Data Sheet Rev 4 1 Freescale Semiconductor 41 Serial Host Interface SPI Protocol Timing Table 20 Serial Host Interface SPI Protocol Timing continued No Characteristics 3 4 Mode Expressions Min Max Unit 34 SCK edge to data out not valid Master Slave 2 0 x Tc 12 0 ns data out hold time 35 SS assertion to data out valid Slave 15 0 ns CPHA 0 36 First SCK sampling edge to HREQ output deassertion Slave 3 0 x 30 50 ns 37 Last SCK sampling edge to HREQ output not Slave 4 0 x Tc 52 2 ns deasserted CPHA 1 38 55 deassertion to HREQ output not deasserted Slave 3 0 x 30 46 6 ns CPHA 0 39 SS deassertion pulse width 0 Slave 2 0 x Tc 12 7 ns 40 HREQ in assertion to first SCK edge Master 0 5 3 0 63 0 n
63. ny and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part Freescale and the Free
64. o GPIO out not valid GPIO out hold time 7 ns 108 FOSC In valid to EXTAL edge GPIO in set up time 2 ns 109 FOSC edge to GPIO in not valid GPIO in hold time 0 ns 110 Minimum GPIO pulse high width except Port F Tc 13 19 ns 111 Minimum GPIO pulse low width except Port F 13 19 ns 112 Minimum GPIO pulse low width Port F 33 3 ns 113 GPIO pulse high width Port 33 3 ns 114 GPIO out rise time m 13 ns 115 GPIO out fall time 13 ns Note 1 vpp 1 25 V 0 05 V Ty 40 to 115 C for 150 MHz Ty 0 C to 100 C for 181 MHz 50 pF 2 PLL Disabled EXTAL driven by a square wave Figure 20 GPIO Timing DSP56371 Data Sheet Rev 4 1 54 Freescale Semiconductor 18 JTAG Timing Table 26 JTAG Timing JTAG Timing All frequencies No Characteristics Unit Min Max 116 frequency of operation 1 Tc x 6 maximum 22 MHz 0 0 22 0 MHz 117 TCK cycle time 45 0 ns 118 TCK clock pulse width 20 0 ns 119 TCK rise and fall times 0 0 10 0 ns 120 TCK low to output data valid 0 0 40 0 ns 121 low to output high impedance 0 0 40 0 ns 122 TMS TDI data setup time 5 0 ns 123 5 TDI data hold time 25 0 ns 124 TCK low to TDO data valid 0 0 44 0 ns 125 TCK low to TDO high impedance 0 0 44 0 ns Note Vcore vpp 1 25 V 0 05 V Ty 40 C to 115 C for 150 MH
65. out the core Y memory address bus YAB for carrying Y memory addresses throughout the core internal buses on the DSP56300 family members are 24 bit buses See Figure 1 2 4 5 Direct Memory Access DMA The DMA block has the following features Six DMA channels supporting internal and external accesses One two and three dimensional transfers including circular buffering End of block transfer interrupts DSP56371 Data Sheet Rev 4 1 Freescale Semiconductor 7 DSP56371 Overview e Triggering from interrupt lines and all peripherals 2 4 6 PLL based Clock Oscillator The clock generator in the DSP56300 core is composed of two main blocks the PLL which performs clock input division frequency multiplication skew elimination and the clock generator CLKGEN which performs low power division and clock pulse generation PLL based clocking Allows change of low power divide factor DF without loss of lock e Provides output clock with skew elimination e Provides a wide range of frequency multiplications 1 to 255 predivider factors 1 to 31 PLL feedback multiplier 2 or 4 output divide factor 1 2 or 4 and a power saving clock divider 2 i 0 to 7 to reduce clock noise The PLL allows the processor to operate at a high internal clock frequency using a low frequency clock input This feature offers two immediate benefits A lower frequency clock input reduces the overall electromagnetic interference generated by
66. pheral modules are defined in the following sections Memory sizes in the block diagram are defaults Memory may be differently partitioned according to the memory mode of the chip See Section 2 4 7 On Chip Memory for more details about memory size 2 4 DSP56300 Core Functional Blocks The DSP56300 core provides the following functional blocks Data arithmetic logic unit Data ALU Address generation unit AGU Program control unit PCU controller with six channels Instruction patch controller PLL based clock oscillator OnCE module Memory DSP56371 Data Sheet Rev 4 1 Freescale Semiconductor DSP56371 Overview In addition the DSP56371 provides a set of on chip peripherals described in Section 2 5 Peripheral Overview 2 4 1 Data ALU The Data ALU performs all the arithmetic and logical operations on data operands in the DSP56300 core The components of the Data ALU are as follows Fully pipelined 24 bit x 24 bit parallel multiplier accumulator MAC e field unit comprising a 56 bit parallel barrel shifter fast shift and normalization bit stream generation and parsing e Conditional ALU instructions e 24 bit or 16 bit arithmetic support under software control e Four 24 bit input general purpose registers X1 Y1 and YO e Six Data ALU registers A2 Al AO B2 and BO that are concatenated into two general purpose 56 bit accumulators A and B accumulator shifters Two data bus
67. rial Audio Interface ESAI up to 4 receivers and up to 6 transmitters master or DSP56371 Data Sheet Rev 4 1 Freescale Semiconductor 3 DSP56371 Overview slave Ps left justified right justified Sony AC97 network and other programmable protocols Enhanced Serial Audio Interface I ESAI 1 up to 4 receivers and up to 6 transmitters master or slave 125 left justified right justified Sony AC97 network and other programmable protocols Serial Host Interface SHI SPI and PC protocols multi master capability in mode 10 word receive FIFO support for 8 16 and 24 bit words Triple Timer module TEC 11 dedicated GPIO pins Digital Audio Transmitter DAX serial transmitter capable of supporting the SPDIF IEC958 CP 340 and AES EBU digital audio formats Pins of unused peripherals except SHI may be programmed as GPIO lines 2 3 DSP56371 Audio Processor Architecture This section defines the DSP56371 audio processor architecture The audio processor is composed of the following units The DSP56300 core is composed of the Data ALU Address Generation Unit Program Controller DMA Controller Memory Module Interface Peripheral Module Interface and the On Chip Emulator OnCE The DSP56300 core is described in the document lt st blue gt DSP56300 24 Bit Digital Signal Processor Family Manual Motorola publication DSP56300FM AD Phased Lock Loop and Clock Generator Memory modules Peripheral modules The peri
68. s X Tc 5 41 HREQ deassertion to last sampling edge Master 0 ns HREQ in set up time 1 42 First SCK edge to HREQ in not asserted Master 0 ns HREQ in hold time 43 HREQ assertion width Master 3 0 x Tc 20 0 ns Note 1 vpp 1 2 5 0 05 V Ty 40 C to 115 C for 150 MHz 0 C to 100 C for 181 MHz C 50 pF 2 Periodically sampled not 100 tested 3 All times assume noise free inputs 4 All times assume internal clock frequency of 150 MHz 5 Equation applies when the result is positive Tc Figure 9 SPI Master Timing CPHA 0 DSP56371 Data Sheet Rev 4 1 42 Freescale Semiconductor Serial Host Interface SPI Protocol Timing lt 28 24 26 gt lt gt a SCK CPOL 0 Output CPOL 1 Output b oL De 1 e TEE WEE MOSI MSB Output 3 Bee HREQ Input DSP56371 Data Sheet Rev 4 1 Freescale Semiconductor 43 Serial Host Interface SPI Protocol Timing ee s Input 5 P 2 SCK CPOL 0 Output CPOL 1 Output lt 29 2 E V V V V VM MSB INN NN Figure 10 SPI Master Timing 1 DSP56371 Data Sheet Rev 4 1 44 Freescale Semiconductor SS Input CPOL 0 Input SCK
69. s GPIO this signal is output or individually programmable as input output or internally disconnected disconnected The default state after reset is GPIO disconnected Internal Pull down resistor This input is 5 V tolerant ADO Output GPIO Digital Audio Data Output This signal is audio and Disconnected non audio output in the form of AES SPDIF CP340 and IEC958 data in a biphase mark format PD1 Input Port D1 When the DAX is configured as GPIO this signal is output or individually programmable as input output or internally disconnected disconnected The default state after reset is GPIO disconnected Internal Pull down resistor This input is 5 V tolerant DSP56371 Data Sheet Rev 4 1 Freescale Semiconductor 29 Signal Connection Descriptions 3 11 Dedicated GPIO Interface Table 11 Dedicated GPIO Signals Signal State During A rae Name Type Reset Signal Description PFO Input GPIO Port F0 this signal is individually programmable as input output output or disconnected internally disconnected The default state after reset is GPIO disconnected disconnected Internal Pull down resistor This input is 5 V tolerant PF1 Input GPIO Port F1 this signal is individually programmable as input output output or disconnected internally disconnected The default state after reset is GPIO disconnected disconnected Internal Pull down resistor This input is 5 V
70. scale logo are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners Freescale Semiconductor Inc 2004 2005 2006 2007 All rights reserved lt oF 2 freescale semiconductor
71. setup time from RESET Maximum Tc 5 5 ns 13 Syn reset de assert delay time Minimum 2x Tc 11 1 ns Maximum PLL enabled 2xTc TLock 5 0 ms 14 select setup time 10 0 ns 15 select hold time 10 0 ns 16 edge triggered interrupt request 2 XTc 11 1 ns assertion width 17 Minimum edge triggered interrupt request 2XIc 11 1 ns deassertion width DSP56371 Data Sheet Rev 4 1 38 Freescale Semiconductor Reset Stop Mode Select and Interrupt Timing Table 19 Reset Stop Mode Select and Interrupt Timing continued No Characteristics Expression Min Max Unit 18 Delay from interrupt trigger to interrupt code 10 5 60 0 ns execution 19 Duration of level sensitive IRQA assertion to ensure interrupt service when exiting Stop 3 PLL is active during Stop and Stop delay is enabled 9 128 704 us OMR Bit 6 0 PLL is active during Stop and Stop delay is not 25x Tc 138 ns enabled OMR Bit 6 1 PLL is not active during Stop and Stop delay is 9 128 5 7 ms enabled OMR Bit 6 0 PLL is not active during Stop and Stop delay is 25 x 5 ms not enabled OMR Bit 6 1 20 Delay from IRQA IRQB IRQC IRQD NMI 10 x Tc 3 0 59 0 ns assertion to general purpose transfer output valid caused by first interrupt instruction execution 2
72. start and stop events A high to low transition of the SDA line while SCL is high is a unique situation and it is defined as the start event A low to high transition of SDA while SCL is high is a unique situation defined as the stop event This signal is tri stated during hardware software and individual reset Thus there is no need for an external pull up in this state Internal Pull up resistor This input is 5 V tolerant DSP56371 Data Sheet Rev 4 1 Freescale Semiconductor 17 Signal Connection Descriptions Table 7 Serial Host Interface Signals continued State Signal Type during Signal Description Reset Signal Name MOSI Input or Tri stated SPI Master Out Slave In When the SPI is configured as a master MOSI is the output master data output line The MOSI signal is used in conjunction with the MISO signal for transmitting and receiving serial data MOSI is the slave data input line when the SPI is configured as a slave This signal is a Schmitt trigger input when configured for the SPI Slave mode HAO Input Slave Address 0 This signal uses a Schmitt trigger input when configured for the 2 mode When configured for 2 slave mode the HAO signal is used to form the slave device address HAO is ignored when configured for the master mode This signal is tri stated during hardware software and individual reset Thus there is no need for an external pull up in this state In
73. sult in significant power consumption and heat up Designs should minimize this state to the shortest possible duration DSP56371 Data Sheet Rev 4 1 Freescale Semiconductor 39 Reset Stop Mode Select and Interrupt Timing _ All Pins Figure 5 Reset Timing RESET Vin IRQA IRQB MODA MODB ME IRQD NMI MODC MODD PINIT Figure 6 Recovery from Stop State Using IRQA Interrupt Service IRQA IRQC IRQD NMI IRQA IRQB IRQC IRQD NMI T 7 Figure 7 External Interrupt Timing Negative Edge Triggered DSP56371 Data Sheet Rev 4 1 40 Freescale Semiconductor Serial Host Interface SPI Protocol Timing O IRQD NMI a First Interrupt Instruction Execution General 5 3 IRQA IRQB IRQC IRQD NMI b General Purpose I O Figure 8 External Fast Interrupt Timing 12 Serial Host Interface SPI Protocol Timing Table 20 Serial Host Interface SPI Protocol Timing No Characteristics 3 4 Mode Expressions Min Max Unit 23 Minimum serial clock cycle Master 10 0 x Tc 9 64 0 ns 24 Serial clock high period Master 29 5 ns Slave 2 0 19 6 27 5 ns 25 Serial clock low period Master 29 5 xp ns Slave 2 0 19 6 27 5 ns 26 Serial clock rise fall time Master 10 ns Slave 10
74. ternal Pull down resistor This input is 5 V tolerant DSP56371 Data Sheet Rev 4 1 24 Freescale Semiconductor Signal Connection Descriptions Table 9 Enhanced Serial Audio Interface_1 Signals Signal Name Signal Type State during Reset Signal Description FSR_1 PE1 Input or output Input output or disconnected GPIO disconnected Frame Sync for Receiver_1 This is the receiver frame sync input output signal In the asynchronous mode SYN 0 the FSR_1 pin operates as the frame sync input or output used by all the enabled receivers In the synchronous mode SYN 1 it operates as either the serial flag 1 pin TEBE 0 or as the transmitter external buffer enable control TEBE 1 RFSD 1 When this pin is configured as serial flag pin its direction is determined by the RFSD bit in the RCCR_1 register When configured as the output flag OF 1 this pin will reflect the value of the OF1 bit in the SAICR 1 register and the data in the OF 1 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode When configured as the input flag IF1 the data value at the pin will be stored in the IF 1 bit in the SAISR register synchronized by the frame sync in normal mode or the slot in network mode Port E1 When the ESAI 1 is configured as GPIO this signal is individually programmable as input output or internally disconnected The default state after reset
75. ternal Pull up resistor This input is 5 V tolerant SS Input Tri stated SPI Slave Select This signal is an active low Schmitt trigger input when configured for the SPI mode When configured for the SPI Slave mode this signal is used to enable the SPI slave for transfer When configured for the SPI master mode this signal should be kept deasserted pulled high If it is asserted while configured as SPI master a bus error condition is flagged If SS is deasserted the SHI ignores SCK clocks and keeps the MISO output signal in the high impedance state HA2 Input Slave Address 2 This signal uses a Schmitt trigger input when configured for the mode When configured for the Slave mode the HA2 signal is used to form the slave device address HA2 is ignored in the master mode This signal is tri stated during hardware software and individual reset Thus there is no need for an external pull up in this state Internal Pull up resistor This input is 5 V tolerant HREQ Input or Tri stated Host Request This signal is an active low Schmitt trigger input when Output configured for the master mode but an active low output when configured for the slave mode When configured for the slave mode HREQ is asserted to indicate that the SHI is ready for the next data word transfer and deasserted at the first clock pulse of the new data word transfer When configured for the master mode HREQ is an input When asserted by
76. to compute the estimated current requirements in Normal mode In order to obtain these results all inputs must be terminated for example not allowed to float Measurements are based on synthetic intensive DSP benchmarks The power consumption numbers in this specification are 9096 of the measured results of this benchmark This reflects typical DSP applications Typical internal supply current is measured with Vcore vpp 1 25V Vpp jo 3 3V at Ty 25 C Maximum internal supply current is measured with VcoRE 1 30 V Vio 3 46V at Tj 115 2 In order to obtain these results all inputs which are not disconnected at Stop mode must be terminated for example not allowed to float 3 Periodically sampled and not 100 tested 4 Ty 40 to 115 C for 150 MHz Tj 0 C to 100 C for 181 MHz CL 50pF 8 AC Electrical Characteristics The timing waveforms shown in the AC electrical characteristics section are tested with a maximum of 0 8V and a Vj minimum of 2 0V for all pins AC timing specifications which are referenced to a device input signal are measured in production with respect to the 50 point of the respective input signal s transition DSP56371 output levels are measured with the production test machine Vo and Voy reference levels set at 1 0V and 1 8V respectively NOTE Although the minimum value for the frequency of EXTAL is 0 MHz PLL bypassed the device AC test conditions are 5
77. wer The voltage 3 3 V should be well regulated and the input should be provided with an extremely low impedance path to the 3 3 Vpp power rail The user must provide adequate external decoupling capacitors PLLD_VDD 1 PLL Power The voltage 1 25 V should be well regulated and the input should be provided with an extremely low impedance path to the 1 25 Vpp power rail The user must provide adequate external decoupling capacitors CORE_VDD 4 Core Power The voltage 1 25 V should be well regulated and the input should be provided with an extremely low impedance path to the 1 25 Vpp power rail The user must provide adequate decoupling capacitors IO VDD 5 SHI ESAI ESAI 1 DAX and Timer I O Power The voltage 3 3 V should be well regulated and the input should be provided with an extremely low impedance path to the 3 3 Vpp power rail This is an isolated power for the SHI ESAI ESAI 1 DAX and Timer I O The user must provide adequate external decoupling capacitors 5005 50 IO GND IO VDD SDO3 SDI2 PC8 SDO2_SDI3_PC9 001_ 10 5000 PC11 CORE PF8 PF6 PF7 CORE_GND PF2 PF3 PF4 IO VDD PF1 PFO IO GND c a 4 a N gt az za Q gt gt 898585208552855802555 2000200225 922000020 FST_PE4 8005 SDIO PE
78. x Min Max 6 input high 12 Eth 3 33ns 100ns 2 75ns 100ns 40 to 60 duty cycle 7 EXTAL input low Etl 3 33ns 100ns 2 75ns 100ns 40 to 60 duty cycle 8 EXTAL cycle time Etc With PLL disabled 6 66ns inf 5 52ns inf With PLL enabled 6 66ns 200ns 5 52ns 200ns 9 Instruction cycle time Icyc Tc Icyc With PLL disabled 6 66ns inf 5 52ns inf With PLL enabled 6 66ns 13 0ns 5 52ns 13 0ns Note 1 Measured at 50 of the input transition 2 The maximum value for PLL enabled is given for minimum and maximum MF The maximum value for PLL enabled is given for minimum and maximum DF 4 The indicated duty cycle is for the specified maximum frequency for which a part is rated The minimum clock high or low time required for correct operation however remains the same at lower operating frequencies therefore when a lower clock frequency is used the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low time requirements are met 11 Reset Stop Mode Select and Interrupt Timing Table 19 Reset Stop Mode Select and Interrupt Timing No Characteristics Expression Min Max Unit 10 Delay from RESET assertion to all output pins at 11 ns reset value 11 Required RESET duration Power on external clock generator PLL 2XTc 11 1 ns disabled Power on external clock generator PLL 2XTc 11 1 ns enabled 12 Syn reset
79. z 0 C to 100 C for 181 MHz C 50 pF All timings apply to OnCE module data transfers because it uses the JTAG port as an interface TCK Input Figure 21 Test Clock Input Timing Diagram DSP56371 Data Sheet Rev 4 1 Freescale Semiconductor 55 JTAG Timing TCK Input Data Inputs Data Outputs Data Outputs Data Outputs TCK Input TDI TMS Input TDO Output TDO Output TDO Output d 4 DSP56371 Data Input Data Valid Output Data Valid Output Data Valid Figure 22 Debugger Port Timing Diagram Input Data Valid Output Data Valid Output Data Valid Figure 23 Test Access Port Timing Diagram heet Rev 4 1 56 Freescale Semiconductor Package Information 19 Package Information FST_PC4 FSR_PC1 HCKT_PC5 FSR PE1 5005 SDIO PC6 SCKT SCKR PCO HCKR PC2 CORE VDD ADO 1 CORE GND HCKR PE2 HCKT 5 lO GND lO VDD SCKR PEO 80 1 5004 SDM FST PE4 GND 2 5005 800 PE6 3 SDO4_SDI1_PE7 SDO3_SDI2_PC8 4 SDO3_SDI2_PE8 SDO2_SDI3_PC9 5 SDO2_SDI3_PE9 SDO1_PC10 6 SDO1 PE10 SDOO PC11 7 SDOO PE11 CORE VDD 8 CORE GND PF8 9 CORE_VDD PF6 0 MODA_IRQA PF7 MODB_IRQB CORE_GND MODC_IRQC PF2 Int Mod MODD_IRQD PF3 RESET_B PF4 PINIT_NMI EXTAL PLLD PF1 PLLD GND PFO Timer OnCE SHI PLL

DSP56371 Data Sheet

Contents

Download Pdf Manuals

Related Search

Related Contents