Xilinx XAPP964 Reference System : OPB PCI Using the ML410
Contents
1. v Pattern Source Instance pci32_bridge_wrapper pci32_bridge_wrapper OBUF_PCI33_3 pci32_bridge_wrapper pci32_bridge_wrapper OBUF_PCI33_3 pci32_bridge_wrapper pci32_bridge_wrapper IOBUF_PCI33_3 pci32_bridge_wrapper pci32_bridge_wrapper pci32_bridge_wrapper pci32_bridge_wrapper pci32_bridge_wrapper pci32_bridge_wrapper OBUF_PCI33_3 pci32_bridge_wrapper pci32_bridge_wrapper OBUF_PCI33_3 pci32_bridge_wrapper pci32_bridge_wrapper OBUF_PCI33_3 Ipci32_bridge_wrapper pci32_bridge_wrapper PORT pci32_bridge_wrapper pci32_bridge_wrapper LUT2 pci32_br r ric N 7 PORT ci32_br 2 n PORT pci32_bridge_wrapper FDRE pels TPO br er app PORT OPB _timeout pci32_bridge_ i32 _bridge_wrapper _ PORT Make Connections PCl_monitor 6 gt pci32_bridge_wrapper_ pci32_bridge_wrapp AND2B2 Inci32 bridge wrapper Ipci32 bridge wra ra t Move Nets Up PORT m Remove Connections J Move Nets Down Cancel x964_15_111406 Figure 15 Making net connections in ChipScope Inserter 6 Click Insert Core to insert the core into pci32_bridge_wrapper ngo In the ml1410_pci implementation directory copy pci32_bridge_wrapper ngo to pci32_bridge_wrapper ngc 8 In XPS run Hardware Generate Bitstream and Device Configu2. XILINX XAPP964 v1 1 January 9 2007 Summary Included Systems Required Hardware and Tools Application Note Embedded Processing Reference System OPB PCI Using the ML410 Embedded Development Platform Author John Ayer Jr Kris Chaplin Beth Farwell Ed Meinelt Matt Nielson Lester Sanders This application note describes how to build a reference system for the On Chip Peripheral Bus Peripheral Component Interconnect OPB PCI core using the IBM PowerPC 405 PPC405 Processor based embedded system in the ML410 Embedded Development Platform The reference system is Base System Builder BSB based and uses eight pcores This reference system is similar to the reference system in XAPP911 except with the principal exception that the ML410 and ML455 boards are used A set of files containing Xilinx Microprocessor Debugger XMD commands is provided for writing to the Configuration Space Header and for verifying that the OPB PCI core is operating correctly Several software projects illustrate how to configure the OPB PCI core set up interrupts scan the configuration registers and set up and use DMA operations The procedure for using ChipScope to analyze OPB PCI functionality is provided The steps used to build a Linux kernel using MontaVista are listed Simulation output files for analyzing basic PCI transactions are provided This application note includes one reference system e www xilinx com bvdocs appn
3. Net touse for Capture Unit ppenton obb pei_ Doph pe pci _0 sil bdge Bur Reset PClside eer pei_ EA pci_O TE RAPIRE FIFO Reset PElside nnelianjanh nei Manh nei NA init hridael Riwe2IP Reset Priside in Ren Cancel Help For Help press F1 xc2ypsU bigb b No Logic Changes X964_18_111506 speed info Figure 18 Using FPGA Editor to Revise Nets used in ChipScope Analyzer Linux Kernel New users of Monta Vista Linux should read XAPP 765 The steps to build and boot a Linux kernel are given below Steps 1 3 7 8 are run on a Linux machine with MontaVista Professional Edition installed 1 Add opt montavista pro host bin and opt montavista pro devkit ppc 405 bin to PATH Change to the m1410_pci 1linux directory Run tar cf C opt montavista pro devkit lsp xilinx m1300 ppc_405 linux 2 4 20 mv131 tar xf To generate the Linux LSP in XPS enter Software Software Platform Settings Select Kernel and Operating Systems then select linux_mvI31 v1 00 c Under OS and Libraries set the entries as shown in Figure 19 XAPP964 v1 1 January 9 2007 www xilinx com 22 Linux Kernel XILINX Software Platform Settings Processor Information Processor Instance ppe405_0 Software Platform Configuration for OS linux_mvi31 v1 01 os andres Name Current Value Default Value Type Description Drivers E linux_mvi31 Interrupt Handlers connected _periphs R8232
4. XILINX Click OK 7 Select Software Generate Libraries and BSPs to generate the LSP in ml1410_ppc_opb_pci linux 8 From ml410_ppc_opb_pci linux run patch_nobspgen The m1410_ppc_opb_pci linux config is used to define the contents of the Linux kernel Run make oldconfig An alternative is to enter make menuconfig and generate a new config using the following options Select General Setup Enable PCI Disable PS 2 keyboard Change to dev ram for booting from ramdisk Select ATA IDE MFM RLL support Enable Enhanced IDE MFM RLL disk cdrom tape floppy support Enable CMD640 chipset bugfix support and CMD640 enhanced support Enable Include IDE ATAP CDROM support Enable Generic PCI IDE chipset support Enable Include IDE ATA 2 DISK support Enable ALI M15x3 chipset support Enable PROMISE PDC202 46 62 65 68 69 70 support Enable SCSI support Enable SCSI disk support Enable SCSI CD ROM support Enable SCSI generic support Enable SCSI low level drivers Enable Adaptec AHA152X 2825 Adaptec AHA1542 and Adaptec AHA1740 support Select Network Device Support Ethernet 10 or 100 enable 3Com devices Enable Vortex if using the 3Com PCI card Enable EISA VLB PCI and on board controllers Enable DECchip Tulip dc2Ix4x PCI support EtherExpressPro 100 support National Semiconductor DB8381x and SMC EtherPowerll Select Console Drivers Disable Frame Buffer Support Select Input Core Support Disable a
5. name to the directory in which the design files are installed Three paths need to be changed 3 Run Start Programs ChipScope Pro gt ChipScope Inserter 4 From ChipScope Inserter run File Open Project opb_pci cdc XAPP964 v1 1 January 9 2007 www xilinx com 17 Using ChipScope with OPB PCI Figure 14 shows the ChipScope Inserter setup GUI File Edit Insert Help Ss ChipScope Pro Core Inserter opb_pci cdc Os Wd to k XILINX Select Device Options Hidesignsiml41 0_peitimplementationipei32_bridge_wrappe Browse HAdesignsiml41 0_pcitimplementation pci32_bridge_wrappg Browse HAdesignsiml410_pcitimplementation E DEVICE DEVICE I ICON pers 0 LA esign Files cme Input Design Netlist Output Design Netlist LUT Count 450 Output Directory FF Count 462 BRAM Count 15 Device Settings Rin cnn Fomib hfrtova lt Previous Next gt v Browse lessages Exception thrown while reading HAdesignsiml410_pcitimplementationiopb_pci cde java io FileNotF oundException H designsiml410_pcitimplernentationtopb_pci cde The system cannot find the file specified Successfully read project Hidesignsiml410_pcitchipscopelopb_pci cde Figure 14 ChipScope Inserter Setup X964_14_111406 The PCI_ Monitor signals are the PCI bus signals The PCI_Monitor signals are used in ChipScope to
6. Dma Transfer complete n X964_10_111406 Figure 10 C Code for DMA Operation Running the In XPS select the Applications tab Software Projects and Add SW Applications Projects Applications Name the software project e g hello_pci and add the files from the software project src directory to Sources see the cursor in the Project Information Area pane in Figure 11 XAPP964 v1 1 January 9 2007 www xilinx com 14 Running the Applications XILINX The structure of the hello_pci is shown in Figure 11 Make the hello_pci project active and the remaining software projects inactive Xilinx Platform Studio H designs ml410_pcitsystem xmp System Assembly View1 EISS File Edit View Project Hardware Software Device Configuration Debug Simulation Window Help T Ss nropr DA RS 0AT Say aA DABAR spe T TE E rE E se Project Information 4rea Filters IP Catalog Project Applications oo Bus Interface Ports Addresses MA Generate Addresses Software Projects Instance Rae e access Bric Add Software Application Project opb z P Default ppc405_0_bootloop ppc405_0 MDCR IDCR a fF Default ppc405_1_bootloap ppe405_1 MDCR IDCR a _ PCI32_BRIDGE MSOFB 42600 Processor ppe405_0 PCI32_BRIDGE MSOPB DMA 0242800 Executable H designs ml410_pci hello_pci executable PCI32_BRIDGE MSOPB IPIFBAR 0420000 Compiler Options PCI32_BRIDGE MSOPB IPIFBAR Oxe8000 4 Sources oy Heade 2
7. array Peripherals connected to Linux MEM_SIZE 0x04000000 int Main Memory size in bytes PLB_CLOCK_FREQ_HZ 100000000 int PLB clock frequency TARGET_DIR akd dinan string Destination directory for Linux BSP IIC_PERSISTENT_BASEADDR 1024 int Start of persistent storage block inthe EEF IIC_PERSISTENT_HIGHADDR 2047 int End of persistent storage block in the EEP IIC_PERSISTENT_EEPROMADDR 0x40 int Address of the EEPROM on the IIC bus POWERDOWN_BASEADDR int Start address of the powerdown feature POWERDOWN_HIGHADDR int End address of powerdown feature POWERDOWN_VALUE int Value to power the board down a PCI BOARD Name of PCI confioured board fml310 ws r i Configuration for Libraries X964_19_ 111506 Figure 19 BSP Settings Verify that the target directory is the same as the directory containing the Linux source 6 Click Connect_Periphs and add the OPB_INTC OPB_SYSACE OPB_PCI OPB_SPI OPB_IIC and OPB 16550 peripherals using the instance names shown in Figure 20 w Add Delete List of Parameter Values Parameter Name connected_periphs Parameter Description Peripherals connected to Linux R5232 Wart SPI_EEPROM PCI32_BRIDGE Sys4CE_CompactFl Bus opb_intc_0 To add an element to the parameter list click Add To delete an element sel e row and click Delete X964_20_111506 Figure 20 Connected Peripherals XAPP964 v1 1 January 9 2007 www xilinx com 23 Linux Kernel gt
8. shown in below the Add Bus option is useful for analyzing ChipScope results 1 ChipScope Pro Analyzer new project File View JTAG Chain Device TriggerSetup Waveform Window Help Ol ales r Flere New Project IH MyDevicel XCAVFXBD 4 ff INIT MyILAG ILA Bus Signal xO 2 Waveform DEV 1 MyDevice1 XC4VFX60 UNIT 0 MyILAO ILA ooo amp j 100 140 180 220 260 300 340 380 420 460 500 540 580 Trigger Setup oe ___ hy OPB_ABus lt 20 gt ETP OPB_ABus lt 21 gt Signals DEV 1 UNIT 0 17 OPB_ABus lt 17 gt a OPB_ABus lt 22 gt 18 OPB_ABus 18 19 OPB_ABus 19 gt 20 OPB_ABus lt 20 gt 21 OPB_ABus lt 21 gt 22 OPB_ABus lt 22 gt 23 JOPB_ABus lt 23 gt OPB ABus 24 OPB_ABus lt 24 25 OPB_ABus lt 25 gt OPB_ABus 26 OPB_ABus lt 26 gt JOPB ABus 27 OPB_ABus lt 27 Cut 28 JOPB_ABus lt 28 OPB_ABUS Copy OPB_ABus lt 23 gt Add to Bus 29 OPB_ABus lt 29 30 OPB_ABus lt 30 Co E 31 OPB_ABus lt 31 gt OPB_ABus Remove From Viewer 32 OPB_DBus lt 0 gt Bm Clear All 33 0PB_DBus 1 gt m 34 0PB_DBus lt 2 gt gt e atx o 0 ys ip IB OPB_ABus Paste X964_16_111406 Figure 16 Creating Buses from Discrete Signals 11 Set the trigger in the Trigger Setup window The trigger used depends on the problem being debugged For example if debugging a configuration transaction from the OPB tri
9. written and read Xilinx Microprocessor Debug XMD Engine Xilinx EDK 8 2 02Build EDK_Im_Sp2 3 Copyright c 1995 2005 Xilinx Inc All rights reserved XMD mrd 0x4260010C 1 4260010C 00000000 XMD mwr 0x4260010C 0x04400080 XMD _ mrd0x4260010C 1 4260010C 04400080 XMD mrd0x42600110 1 42600110 46050022 XMD mwr 0x426001 10 0x86002002 XMD mrd0x42600110 1 42600110 46050002 XMD mwr 0x4260010C 0x08400080 XMD mrd0x42600110 1 42600110 1A452301 XMD mwr 0x4260010C 0x0C400080 XMD mwr 0x426001 10 0x00FF0000 XMD mrd0x42600110 1 42600110 00FF0000 XMD mwr 0x4270010C 0x10400080 XMD mwr 0x427001 10 0x00000000 XMD mrd0x42700110 1 42600110 08000000 XMD mwr 0x4260010C 0x14400080 X964_09_111406 Figure 9 XMD Commands for Configuring OPB PCI Software Projects The reference system contain the following software projects In each software project directory there are src sub directories for the source code TestApp_Memory This project tests the memory on the ML410 board TestApp_Peripheral This project verifies that the OPB Sysace is used correctly hello_pci This project enables master transactions sets the latency timer defines the bus number subordinate bus number and scans the ML410 configuration registers xpci_tapp_example This project contains two major functions which use level 0 drivers PcilnitLevel_0 and ShowPCl PcilnitLevel reads and writes the bus and subordinate bus number in
10. 3 3V PCI Slot 5 gt PCL_P_AD21 ine PCI_BUS 3 3V PCI Slot 3 gt gt PCLP_AD22 nga f _ _ _ PCI_BUS ALi South Bridge U15 IDSEL Dev ID Audio 0x5451 S Bridge 0x1533 Modem 0x5457 USB 2 0x5237 IDE Bus 0x5229 USB 1 0x5237 PCI Bus PCI_P_AD17 PCI_P_AD18 PCI_P_AD19 PCI_P_AD26 PCI_P_AD27 PCI_P_AD31 E X964_02_11106 Figure 2 PCI Bus Devices on the ML410 Figure 2 shows PCI Bus Devices on the ML410 The T12250 device is a PCI to PCI bridge to the two 5V PCI slots The ALi M1535D South Bridge interfaces to the legacy devices including the audio modem USB and IDE ports The Xilinx Virtex 4 ML455 PCI PCI X Board is inserted into slot 3 XAPP964 v1 1 January 9 2007 www xilinx com Introduction XILINX FPGA U37 ipseL LPCLP_AD24 ALi South Bridge PCI Bus eee S U15 PCI_P_CLK3 48 MHz IDSEL Device ID_ Vendor ID PCI_P_AD1 7 Audio 0x5451 0x10B9 S Bridge 0x1533 0x10B9 Modem 0x5457 0x10B9 14 3181 MHz USB 2 0x5237 0x10B9 IDE Bus 0x5229 0x10B9 USB 1 0x5237 0x10B9 ll PCI Bus 24 576 MHz Primary IDE Secondary IDE U4 J16 J15 X965_03_111006 J5 Figure 3 ALI Bus PCI to Legacy Devices J3 P1 P2 Figure 3 shows the connections of the South Bridge to the legacy devices The functions devices and buses in the OPB PCI reference design de
11. 512 MB CompactFlash CF card in a CompactFlash reader writer Remove the CF card from the CF reader writer and insert it into the CompactFlash slot J22 on the ML410 board Power up the board The bus transactions done by the OPB PCI Bridge are described the UG241 OPB PCI User Guide The m1410_ppc_opb_pci simulation directory contains waveform log files files with wlf extension for the following types of transactions e Configuration from the OPB side e Configuration from the PCI side e OPB to PCI Write e OPB to PCI Read e PCI to OPB Write e PCI to OPB Read Load the wlf files into the Modeltech simulator by typing the File gt Open command then specifying the wif file type See the UG241 OPB PCI User Guide for a detailed definition of each transaction DS437 OPB IPIF LogiCore v3 0 PCI Core Bridge v1 02a Xilinx LogiCore PCI Interface v3 0 Product Specification Xilinx The Real PCI Design Guide v3 0 DS416 Direct Memory Access and Scatter Gather Virtex 4 ML455 PCI PCI X Development Kit User Guide UG084 v1 0 May 17 2005 XAPP765 Getting Started with EDK and MontaVista Linux ML41x Embedded Development Platform User Guide UG085 v1 2 May 26 2006 ChipScope ILA Tools Tutorial UG241 OPB PCI User Manual The following table shows the revision history for this document Date Version Revision 12 5 06 1 0 Initial Xilinx release 1 9 07 1 1 Corrected spelling of author s name XAPP964 v1 1 Janua
12. JTAG port and use Impact to download the ml1410_pci 455 implementation download bit file After configuring the XC4VLX25 FPGA using the bit file the PCI functionality OPB PCI in the XC4VLX25 is configured using Configuration write transactions from the OPB PCI in the XC4VFX60 of the ML410 XAPP964 v1 1 January 9 2007 www xilinx com 9 Reference System Specifics gt XILINX Executing the Reference System using the Pre Built Bitstream and the Compiled Software Applications To execute the system using files inside the ml410_ppc_opb_pci ready_for_download directory follow these steps 1 Change to the m1410_ppc_opb_pci ready_for_download directory 2 Use iMPACT to download the bitstream by using the following impact batch xapp964 cmd 3 Invoke XMD and connect to the MicroBlaze processor by the following command xmd opt xapp964 opt 4 Download the executable by the following command dow lt path gt executable elf Executing the Reference System from EDK To execute the system using EDK follow these steps 1 Open system xmp inside EDK 2 Use Hardware Generate Bitstream to generate a bitstream 3 Download the bitstream to the board using Device Configuration gt Download Bitstream Invoke XMD with Debug Launch XMD 5 Download the executable by the following command dow lt path gt executable elf Verifying the Reference Design with the Xilinx Microprocessor Debugger After downloading the bitstream fil
13. Latency Timer BARs configure m1455 xmd Configures the ML455 CSR Latency Timer BARs m1410 bram xmd Tests the PLB BRAM connected to the ML410 m1410_plbddr xmd Tests PLB DDR connected to the ML410 m1410 455bram xmd Tests ML410 writing to ML455 Board BRAM ml1410_ 455ddr xmd Tests ML410 writing to ML455 DDR SDRAM m1455 bram xmd Tests the BRAM connected to the ML455 m1455_410ddr xmd Tests the ML455 writing to ML410 PLB DDR dma_410_455ddr xmd Tests DMA from the ML410 to ML455 DDR dma_410ddr_455ddr xmd DMA from ML410 PLB DDR to ML455DDR SDRAM dma_455ddr_410ddr xmd Tests DMA from M455 DDR to ML410 DDR dma_410bram_455bram xmd Tests DMA from PLB BRAM to PCI Bridge The following steps use the XMD commands in the files in the directory ml1410_ppc_opb_pci xmd_command 1 Invoke XMD 2 Open the XMD command file e g configure xmd using a text editor such as WordPad 3 Select and copy the XMD commands in the text editor 4 Right click the mouse in the XMD window to paste the commands XAPP964 v1 1 January 9 2007 www xilinx com 11 Reference System Specifics gt XILINX The XMD commands in the configure_m1410 xmd file listed in Figure 9 write to the Configuration Address Port and to the Configuration Data Port to program the Configuration Space Header The Command Status Register Latency Timer and Base Address Registers are
14. PIF2PCI Endianess FIFO Translation Master Address OARS EN Attach Translation Li Optional IP Target 1 DMA Master SM a SM l Interrupt Module Reset Module OPB PCI Bus X964_05_111006 Figure 6 Block Diagram of OPB PCI Bridge Core Virtex 4 ML455 PCI PCI X Development Board In the reference design the OPB PCI in the XC4VFX60 on the ML410 board interfaces to the OPB PCI in the Virtex 4 ML455 PCI PCI X Development board The ML455 board uses the Xilinx XC4VLX25 device in the 668 pin package The m1410_ppc_opb_pci 455 directory contains the system mhs and other project files for the ML455 Table 4 provides the address map for the XC4VLX25 Table 4 XC4VLX25 Address Map Peripheral Instance Base Address High Address LMB_BRAM_IF_CNT DLMB_CNTLR ILMB_CN 0x0000000 0x70003FFF LR TLR OPB_UART16550 RS232_Uart 0x40400000 Ox4040FFFF OPB PCI PCI_Bridge 0x42600000 0x4260FFFF OPB DDR DDR_SDRAM_64Mx32 0x24000000 0x27FFFFFF OPB GPIO LEDs_4Bit 0x40000000 Ox4000FFFF OPB MDM debug_module 0x41400000 0x4140FFFF OPB INTC opb_intc_0 0x41200000 0x4120FFFF The ML455 includes three clock sources a 64 bit PCI edge connector 128 MB 16M x 64 DDR SDRAM memory RS232C port LED displays XCF32P FSG48C Platform Flash configuration PROM and a JTAG port The MicroBlaze microprocessor is used in this design XAPP964 v1 1 January 9 2007 www xilinx com Reference System Specifi
15. System Monitor Over Temperature Alarm a INFO iMPACT 2219 Status register values INFO iMPACT 0011 1111 1111 1110 0000 0000 0000 0000 INFO iMPACT 579 2 Completed downloading bit file to device INFO iMPACT 560 2 Checking done pin done 2 Programmed successfully Elapsed time 6 sec BATCH CMD quit lt ii fay Output Wamings Errors x964_11_111406 Figure 11 Selecting the hello_pci Software Project Select hello_pci and right click to build the project If more than one software project is used make the unused software projects inactive XAPP964 v1 1 January 9 2007 www xilinx com 15 Running the Applications XILINX Connect a serial cable to the RS232C port on the ML410 board Start up a HyperTerminal Set the baud rate to 9600 number of data bits to 8 no parity and no flow control as shown in Figure 12 COM1 Properties Bits per second Data bits Parity Stop bits Flow control Restore Defaults x964_12_111406 Figure 12 HyperTerminal Parameters XAPP964 v1 1 January 9 2007 www xilinx com 16 Using ChipScope with OPB PCI XILINX From XPS start XMD and enter rst Invoke GDB and select Run to start the application as shown in Figure 13 The hello_pci c code written for the ML310 shown in the figure runs without any modifications on this reference system hello c Source Windo
16. a debug operation To revise nets used by ChipScope Analyzer enter the command fpga_editor lt system gt ncd From the FPGA Editor GUI select Tools gt ILA Select an existing net which is not needed in debugging and click Change Net The pattern filter box shown in Figure 18 facilitates the selection of a new net s Click Write CDC to generate an new opb_pci cdc file Click Bitgen to generate a new bit file The FPGA Editor ILA flow is more efficient than regenerating the Chip Inserter flow listed above because the MAP and PAR implementation phases are not required XAPP964 v1 1 January 9 2007 www xilinx com 21 Linux Kernel XILINX 2 Xilinx FPGA Editor top qoiu5t2ad ncd ILA Capture Units Name DataBits Trigger Bits Close ppe top chipscope_ila_O chi ppc top chipscope_opb_iba Help ppc top chipscope_plb_iba_ Write CDC Data and Trigger Bits Bi Net Component Change Net 0 ppc top opb_pci_0 ppc top chipscope_ TE 1 ppc top opb_pci_O ppe top chipscope_ ViewComponent 2 ppe top opb_pci_O ppe top chipscope_ 3 ppc top opb_pci_O ppc top chipscope_ Bitgen 4 ppe top opb_pci_O ppe top chipscope_ gen 5 ppevtop opb pei O ppe top chipscope gt Download I Hilite net of the selected bit in the array and world windows I Hilite component of the selected bit in the array and world windows Pattern peiside
17. cs lt XILINX Figure 7 shows the ML455 PCI PCI X Development board DB9M P4 RS232 Connector P3 Platform Flash Rev SEL Header Platform Flash XC32FP U1 CPLD XC2C32 U6 P8 PCI X Cap Header FPGA U10 XC4VLX25 P9 M66EN Header 200 MHz Y1 Osc 133 MHz Y2 OSC SODIMM 128MB DDR Figure 7 ML455 PCI PCI X Development Board User Push Buttons and LEDs Parallel Cable IV JTAG Connector P5 33 MHz Y3 OSC 64 bit PCI PCI X Expansion Connector J1 P18 P19 J1 Connector VCCO SEL Header P2 Flash FPGA Clock SEL Header P13 IDSEL Header P16 FPGA Bank VCCO SEL Header P11 General Purpose I O or LCD IF Header MODE SW5 X964_07_111006 Interfacing to the OPB PCI on the ML455 PCI PCI X Board XAPP964 v1 1 January 9 2007 www xilinx com Reference System Specifics gt XILINX Figure 8 shows the principle interface blocks when transferring data between the OPB PCI Bridge in the XC4VFX60 on the ML410 board and the OPB PCI Bridge in the XC4VLX25 on the ML455 board ML410 Virtex 4 ML455 Slot 3 X964_08_101406 Figure 8 Interfacing ML410 Board OPB PCI with the ML455 Board OPB PCI Configuration of OPB PCI on the ML410 Board The OPB PCI bridge uses the 32 bit Xilinx LogiCore Version 3 IP v3 0 core For the OPB PCI bridge to perform transactions on the PCI bus the v3 0 core must be configured using configuration transactions from either the PCl side or from the OPB side T
18. dware Software Device Configuration Debug Simulation Window Help 21H XI SB ODN DAAG oY SRM AHOBOR eRe ae ARH S ChipScope Pro rape new project File View JTAG Chain Device TriggerSetup Waveform Window Help Sir snes rcleew piect H TEE DEV 1 MyDevice1 XC4VFX60 UNIT 0 MyiLAO ILA Eran es oot fd 00 140 180 220 260 300 340 380 420 460 500 540 580 MyDevicel C4VFXBD La INIT O MyILAG ILA H Trigger Setup m 3 Bus Signal xio PCI monitor ad 1FF LFF PCI monitor che oj a X Signals DEV 1 UNIT 0 Data Port JPC _monitor_ad f 0PB_A Bus 308 308 JPCl_monitor_cbe 9 OPB DBus 000 000 PCI_monitor lt 6 gt 1 OPB_DBus amp OPB_ABus PCT_moni ta lt o gt 1 CH 0 OPB_ABu 4 CH 1 OPB_ABU PCI_monitor lt 3 gt o o CH 2 OPB_ABu PCI_monitor lt 0 gt tf a CH 3 OPB_ABu l CH 4 OPB_ABu PCI_monitor lt 1 gt 0 0 CH 5 JOPB_ABU PCI_monitor lt 2 gt HES CH 6 OPB_ABu CH 7 OPB_ABu PCI_monitor lt 4 gt AI Bl CH 8 JOPB_ABu y oa PCL tors gt a al CH 9 OPB_ABu PERT RESEESS CH 10 OPB_AB F a eT CH 11 JOPB_AB 4 bila olla vial Es il CH 12 0PB_ABIJ x 0 EP 0 0 INES A X 0 o E ER m re EE Javr Upload X964_17_111506 Figure 17 ChipScope Analyzer Results After running ChipScope it is sometimes necessary to revise the trigger or data nets or both used in
19. e and writing to the configuration header execute the following steps to verify that the ML410 reference design is set up correctly 1 Configure the v3 0 Command Register Latency Timer and BAR s 2 Read the configuration header 3 Configure the Command Register Latency Timer and BAR s of the other devices in the system 4 Read the configuration headers of the other devices in the system 5 Perform a memory read of one of the IPIF BARs 6 Perform a memory write of one of the IPIF BARs Verification is done using either Xilinx Microprocessor Debugger XMD the software projects or both discussed later in this document Text files of the XMD commands are provided in the xmd_command directory in the design files The configure xmd files contain XMD commands which configure the bridge The test_interrupt_regs xmd file contains commands which set up and verify the interrupt registers The write_read_bram xmd and write_read_ddr xmd files contain XMD commands which test PLB BRAM and PLB DDR respectively Table 5 lists the files containing XMD commands which verify that the initial setup of the reference system is correct In the nomenclature below the board name ML410 ML455 is used rather than the device name 4fx60 4vlx25 XAPP964 v1 1 January 9 2007 www xilinx com 10 Reference System Specifics XILINX Table 5 XMD Configuration Commands XMD command configure_m1410 xmd Function Configures the ML410 CSR
20. e the 1 2 Bridge Remote OPB Master Accessing PCI Targets Include the 1 2 Bridge Remote PCI Initiators Accessing OPB Slave Include the Error Recording Module Include Explicit Instantiation of INTR_A 10 buffer Include Explicit Instantiation of REQ_N 10 buffer Include Registers for Each IPIF BAR High order Bits to be Substituted in Translation Include the Register for setting Local Bridge Device Number Number of IDELAYCTAL Primitives V4 only that are explicitly instantiated LOC Constraints of IDELAYCTRL Primitive lt X964_05_ 111006 Figure 5 Specifying the Values of Generics in EDK The C_INCLUDE_PCI_CONFIG generic configures the bridge as a host bridge When C_INCLUDE_BAR_OFFSET 0 the C_IPIFBAR2PCIBAR_ generic s are used in address translation instead of IPIFBAR2PCIBAR_ registers Setting C_DMA_CHAN_TYPE 0 specifies simple DMA Setting C_IPIFBAR_NUM 2 specifies that there are two address ranges for OPB to PCI transactions Setting C_PCIBAR_NUM 1 specifies that one address range is used for PCI to OPB transactions XAPP964 v1 1 January 9 2007 www xilinx com 6 XILINX Reference System Specifics Figure 6 provides a functional diagram of the OPB PCI Full Bridge core The three functions of the core are the OPB IPIF the v3 0 PCI Core and the IPIF v3 0 Bridge OPB IPIF IPIF V3 Bridge IPIF PCl Slave SM Initiator SM Translation Oppppci_TARG PCI2IPIF Endianess FIFO Translation I
21. fined in Figures 2 and 3 are addressed using the Configuration Address Port format shown in Figure 4 00 Doubleword Function No Bus No Reserved E i Device No X964_03_111006 Figure 4 Configuration Address Port Format The Configuration Address Port and Configuration Data Port registers in the Virtex 4 OPB PCI Bridge are used to configure multiple PCI bridges when host bridge configuration is enabled The bit definitions of the Configuration Address Port in the big endian format used by the PLB is given in Table 1 The formats are different Table 1 Configuration Address Port Register Definitions Bit Definition 0 5 Target word address in configuration space 6 7 Hardwired to 0 8 12 Device 13 15 Function 16 23 Bus Number 24 Enable 25 31 Hardwired to 0 XAPP964 v1 1 January 9 2007 www xilinx com 4 XILINX Reference System Specifics Reference In addition to the PowerPC405 processor and OPB_ PCI this system includes DDR and BRAM System memory on the PLB while on the OPB it includes a UART interrupt controller SYSACE IIC S ifi and SPI The relationship of the modules is shown in Figure 1 The PCI Arbiter core is included pecitics in the FPGA Table 2 provides the addresses of the IDSEL lines on the ML410 Board Table 2 ML410 PCI Devices IDSEL Lines Device DevID VendiD Bus Dev Periana FPGA 0x0410 0x10EE 0 8 A Ali M1535D So
22. gger on an OPB address of C_BASEADDR 0x10C If debugging a problem configuring from the PCI side trigger on the PCI_Monitor 43 47 for a configuration write on CBE Change the Windows to N samples to a setting of 500 Arm the trigger by selecting Trigger Setup Arm or clicking on the Arm icon 12 Run XMD or GDB to activate the trigger patterns which cause ChipScope to display meaningful output For example invoke xmpD enter rst and paste the contents of configure xmd into the XMD window 13 ChipScope results are analyzed in the waveform window as shown in Figure 17 This figure shows the original PCI_monitor lt gt signals and the PCl_monitor_ad signal generated in Step 10 The waveforms may be easier to read if the discrete PCI_monitor lt gt signals are removed after they are renamed To share the results with remote colleagues save the results in the waveform window as a Value Change Dump vcd file The vcd files can be translated and viewed in most simulators The vcd2w1f translator in Modeltech reads a vcd file and generates a wif file for viewing in the Modeltech waveform viewer The vcd file can be opened in the Cadence Design System Inc Simvision design tool by selecting File Open Database XAPP964 v1 1 January 9 2007 www xilinx com 20 Using ChipScope with OPB PCI XILINX w Xilinx Platform Studio H designz ml410_ pci lt aystem xmp System Aasembly Viret 0 File Edit View Project Har
23. his reference design configures the bridge from the OPB side therefore C_INCLUDE_PCI_CONFIG is set to 1 In this case IDSEL input of the v3 0 is connected to the address ports specified in Table 2 while the IDSEL port of the bridge is unused To write to the configuration header execute the following steps 1 Configure the Command and Status Register The minimum that must be set is the Bus Master Enable bit in the command register For memory transactions the memory space bit must be set For I O transactions the I O space bit must be set 2 Configure the Latency Timer to a non zero value 3 Configure at least one BAR Configure subsequent BARs as needed for other memory lO address ranges The v3 0 core configures itself only after the Bus Master Enable bit is set and the latency timer is set to avoid time outs If the v3 0 core latency timer remains at the default 0 value configuration writes to remote PCI devices do not complete and configuration reads of remote PCI devices terminate due to the latency timer expiration Configuration reads of remote PCI devices with the latency timer set to 0 return OXFFFFFFFF Configuration of OPB PCI on the ML455 PCI PCI X Board When the ML455 is inserted into a ML410 PCI slot the OPB PCI Bridge in the Xilinx XC4VFX60 FPGA interfaces to an OPB PCI Bridge in the XC4VLX25 FPGA on the ML455 PCI Board To configure the XC4VLX25 connect the Xilinx Download USB or Parallel IV cable to the ML455
24. itializes the bridge device number if present and performs configuration writes to the PCI header to set up the bridge The latency timer is set to the maximum The BAR registers are set and interrupts are enabled xpci_example_level_0 This project uses level 0 drivers to initialize the PCI bridge It then initializes a remote device on the PCI bus and prints messages describing the bridge and memory mappings XAPP964 v1 1 January 9 2007 www xilinx com 12 Reference System Specifics gt XILINX xpci_example_level_1 This project initializes the OPB PCI bridge and a remote device on the PCI bus It then initializes Direct Memory Access DMA and runs local to DMA and DMA to local transfers The Pcilsr function handles interrupts The OPB PCI Bridge supports simple but not scatter gather DMA Simple DMA is enabled by setting C_DMA_CHAN_TYPE 0 The DS416 Direct Memory Access and Scatter Gather product specification provides information on the use of the DMA function in the IPIF The base address for DMA in the ML410 reference system is C_DMA_BASEADDR 0x42800000 The registers used in DMA setup are given below Table 6 DMA Registers DMA Register Address Control Register C_DMA BASEADDR 0x04 Source Address Register C_DMA_BASEADDR 0x08 Destination Address Register C_DMA_BASEADDR 0x0C Length Address Register C_DMA_BASEADDR 0x10 XAPP964 v1 1 January 9 2007 www xilinx com 13 Running the A
25. ll Select Character Devices Disable Virtual Leave Serial enabled Disable Xilinx GPIO and Touchscreen Enable USB support 10 Run make clean dep zImage initrd Verify that the zImage initrd elf file is in the ml1410_ppc_opb_pci linux arch ppc boot images directory 11 Invoke Impact and download implementation download bit to XC4VFX60 Either select Device Configuration Download Bitstream from XPS or run the following command from the command prompt impact batch etc download cmd 12 Invoke XMD From the m1410_pci linux_pci directory enter the following commands in the XMD window rst XAPP964 v1 1 January 9 2007 www xilinx com 24 Simulation Simulation References Revision History XILINX dow arch ppc boot images zImage initrd elf con 13 View the output in the HyperTerminal window Login as root Entered and 1s 1 to view the contents of the mounted Linux partition 14 Enter lspei vv to view the PCI devices For each line of output the first 2 digits represent the PCI bus number followed by the device number and function number 15 An alternative to downloading the Linux kernel executable is to load it into CompactFlash The file used uses an ace file extension To generate an ace file run the command below from the m1410_ppc_opb_pci directory xmd tcl genace tcl jprog hw implementation system bit ace implementation ace_system_hw ace board ML410 Copy the ace file to a 64
26. m 1 Introduction XILINX Introduction This application note accompanies a reference system built on the ML410 development board Figure 1 is a block diagram of the reference system X964_01_111406 Figure 1 OPB PCI Reference System Block Diagram The system uses the embedded PowerPC as the microprocessor and the OPB PCI core On the ML410 board the Virtex 4 XC4VFX60 accesses two 33 MHz 32 bit PCI buses a primary 3 3V PCI bus and a secondary 5 0V PCI bus The FPGA is directly connected to the primary 3 3V bus The 5 0V PCI bus is connected to the Primary PCI bus with a PCI to PCl bridge the T12250 The PCI devices and four PCI add in card slots on the ML410 are listed in Table 2 All PCI bus signals driven by the XC4VFX60 comply with the I O requirements in the PCI Local Bus Specification Revision 2 2 Many of the ML410 functions are accessed over the 33 MHz 32 bit PCI bus The Virtex 4 Platform FPGA contains PPC405 processors which access the primary PCI bus through the OPB PCI Bridge PCI configuration in this reference design uses the OPB PCI Bridge as a host bridge XAPP964 v1 1 January 9 2007 www xilinx com Introduction FPGA U37 IDSEL PCI Bus XILINX PCl to PCl Bridge U32 3 3V 5 0V 5 0V PCI Slot 6 PCI_S_CLKQ N PCI_S_AD18 iDSEL A PCI_BUS 5 0V PCI Slot 4 PCI_S_CLK1 N PCILS_AD19 inge L Pci BUS 0xAC23 104C PCI_P_AD25 s IDSEL PCI_BUS T12250
27. monitor signals AD CBE and the remaining PCI Bus signals Table 7 defines the functionality of the PCIl_Monitor signals which are generally useful to add to ChipScope The Filter Pattern PCI_Monitor is used to locate the signals Table 7 PCI Monitor Signals Bit Position PCI Signal FRAME_N ad DEVSEL_N TRDY_N IRDY_N STOP_N IDSEL_int INTA PERR_N SERR_N olJi NI OD oO AJOIN Req_N_toArb oO PAR 11 42 AD 43 47 CBE XAPP964 v1 1 January 9 2007 www xilinx com Using ChipScope with OPB PCI XILINX 5 Figure 15 shows the GUI for making net connections Click Next to move to the Modify Connections window If there are any red data or trigger signals correct them The Filter Pattern can be used to find net s As an example of using the Filter Pattern enter AD in the dialog box to locate AD signals In the Net Selections area select either Clock Trigger or Data Signals Select the net and click Make Connections Select Net Structure Nets Net Selections pci32_bridge_wrapper pci32_bridge pci_core l_pcim_lc_32bit_generate PCI_LC PCI_LC_ Trigger Signals Data Signals Clock Signals N Channel CH 0 JOPB_ABus lt 23 gt CH 1 _ OPB_ABus lt 27 gt JOPB_ABus lt 28 gt JOPB_ABus lt 29 gt VOPB_xferAck JOPB_RNW PCI_monitor lt 0 gt PCI_monitor lt 2 gt
28. otes xapp964 zip ml410_ppc_opb_pci is the project name used in xapp964 zip Users must have the following tools cables peripherals and licenses available and installed e Xilinx EDK 8 2 02 e Xilinx ISE 8 2 02 e Xilinx Download Cable Platform Cable USB or Parallel Cable IV e Monta Vista Linux v2 4 Development Kit e Modeltech ModelSim v6 1d e ChipScope v8 2 2006 Xilinx Inc All rights reserved All Xilinx trademarks registered trademarks patents and further disclaimers are as listed at http www xilinx com legal htm PowerPC is a trademark of IBM Inc All other trademarks and registered trademarks are the property of their respective owners All specifications are subject fo change without notice NOTICE OF DISCLAIMER Xilinx is providing this design code or information as is By providing the design code or information as one possible implementation of this feature application or standard Xilinx makes no representation that this implementation is free from any claims of infringement You are responsible for obtaining any rights you may require for your implementation Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose XAPP964 v1 1 January 9 2007 www xilinx co
29. pplications gt XILINX The code which transfers DMA data is given in Figure 10 FERRER RRR RERERERER RRR R RRR He ERE R AREA ARERR ERE E EERE EERE EET E ETE TE HATER EER EERE PciDmatransfer interrupt driven DMA to from a device on the PCI bus Parameters LocalAddress address of a local memory device such as SRAM DDR etc RemoteAddress address local to the processor that maps to the PCI bus Bytes bytes to transfer Direction direction to transfer 0 local to remote 1 remote to local JER III III II I II III I II IDI IA void PciDmatTransfer Xuint32 LocalAddress Xuint32 RemoteAddress Xuint32 Bytes int Direction Xuint32 DmaSrc Xuint32 DmaDest setup transfer direction if Direction 0 local to PCI XDmaChannel_SetControl amp Bridge Dma XDC_DMACR_SOURCE_INCR_MASK XDC_DMACR_DEST_INCR_MASK XDC_DMACR_DEST_LOCAL_MASk DmaSrc LocalAddress DmaDest RemoteAddress else if Direction 1 PCI to local XDmaChannel_SetControl amp Bridge Dma XDC_DMACR_SOURCE_INCR_MASK XDC_DMACR_DEST_INCR_MASK XDC_DMACR_SOURCE_LOCAL_MASk DmaSrc RemoteAddress DmaDest LocalAddress else printf Invalid direction argument Must be 0 or 1 n return begin transfer XDmaChannel_Transfer amp Bridge Dma Xuint32 DmaSrc Xuint32 DmaDest Bytes wait for completion Semaphore Take amp Bridge DmaSemaphore printf
30. ration Download Bitstream Do not rerun Hardware Generate Netlist as this overwrites the implementation pci32_bridge_wrapper ngc produced by the step above Verify that the file size of the pci32_bridge_wrapper ngc with the inserted core is significantly larger than the original version 9 Invoke ChipScope Pro Core Analyzer by selecting Start Programs ChipScope Pro ChipScope Pro Analyzer Click on the Chain icon located at the top left of Analyzer GUI Verify that the message in the transcript window indicates that an ICON is found 10 The ChipScope Analyzer waveform viewer displays signals named DATA To replace the DATA signal names with the signal names specified in ChipScope Inserter select File gt Import and enter opb_pci cdc in the dialog box XAPP964 v1 1 January 9 2007 www xilinx com 19 Using ChipScope with OPB PCI gt XILINX The waveform viewer is more readable when buses rather than discrete signals are displayed As shown in Figure 16 select the 32 OPB_ABus lt gt signals click the right mouse button and select Add to Bus New Bus With OPB_ABus lt 0 31 gt in the waveform viewer select and remove the 32 discrete OPB_ABus lt gt signals Do this for the OPB_DBus Make PCI Bus signals by creating a new bus for PCI_Monitor 43 47 and renaming it PCl_Monitor_CBE and for PCI_Monitor 11 42 and renaming it PCI_Monitor_AD Note In Figure Figure 16 the Reverse Bus Order operation option
31. ry 9 2007 www xilinx com 25
32. uth Bridge 0x1533 0x10B9 0 2 AD18 ALi Pwr Mgt 0x7101 0x10B9 0 12 AD28 ALi IDE 0x5529 0x10B9 0 11 AD27 ALi Audio 0x5451 0x10B9 0 11 AD17 ALi Modem 0x5457 0x10B9 0 3 AD19 ALi USB 1 0x5237 0x10B9 0 15 AD31 ALi USB 2 0x5237 0x10B9 0 10 AD26 TI Bridge T12250 0AC23 0x104C 0 9 AD25 3 3V PCI Slot 3 AD22 3 3V PCI Slot 5 N A N A 0 5 AD21 5 0V PCI Slot 4 N A N A 1 3 AD19 5 0V PCI Slot 6 N A N A 1 2 AD18 ML410 XC4VFX60 Address Map Table 3 ML410 XC4VFX60 System Address Map Peripheral Instance Base Address High Address PLB DDR DDR_SDRAM_32Mx64 0x00000000 Ox03FFFFFF OPB SPI SPI_EEPROM 0x40A00000 Ox40A0FFFF OPB UART16550 RS232_Uart_1 0x40400000 Ox4040FFFF OPB INTC opb_intc_0 0x41200000 0x4120FFFF OPB_PCI PCI32_Bridge 0x42600000 0x4260FFFF OPB PCI DMA PCI32_Bridge 0x42800000 0x4280FFFF PLB BRAM plb_bram_if_cntlr_0 OxFFFFC000 OxFFFFFFFF OPB SYSACE SysACE_CompactFlash 0x41800000 0x4180FFFF OPB IIC IIC_Bus 0x40800000 0x4080FFFF Table 3 provides the address map of the ML410 XC4VFX60 The reference design contains the following settings for OPB PCI generics C_INCLUDE_PCI_CONFIG 1 C_INCLUDE_BAROFFSET 0 C_DMA_CHAN_TYPE 0 C_IPIFBAR_NUM 2 XAPP964 v1 1 January 9 2007 www xilinx com 5 Reference System Specifics XILINX C_PCIBAR_NUM 1 Figure 5 shows how to specify the values of generics in EDK PCI32_BRIDGE opb_pci_vy1_02_a User System Includ
33. w DEOK File Run View Control Preferences Help FOU CDRS SAS Od Find a hello c v main x 42 define PCI_CFG_ADDR XPAR_OPB_PCI_1_BASEADDR 6x16C 43 define PCI_CFG_DATA XPAR_OPB_PCI_1_BASEADDR 0x118 44 define PCI_BUSNUM_SUBBUSNUM ADDR XPAR_OPB_PCI_1_BASEADDR 0x114 45 46 int main int loop unsigned long temp32 XUartNs550 SetBaud UART_BASEADDR UART_CLOCK UART_BAUDRATE XUartNs556 mSetLineControlReg UART_BASEADDR XUN _LCR_8 DATA BITS xil_printf PCI Test r n xil_printf Scan PCI Config Regs of ML310 Xilinx PCI Core AD24 r for loop 6 loop lt 6x46 loop 4 XIo_OutSwap32 PCI_CFG_ADDR 6x86664666 loop ML366 was G temp32 XIo_InSwap32 PCI_CFG_DATA f xil_printf Offset 62x 68x loop XIo_InSwap32 PCI_CFG_D xil_printf Offset 62x 68x loop temp32 if flaon AvA Ave vil nrintf FYE ny Program not running Click on run icon to start OxFFFFSO18 X964_13_111406 Figure 13 Running hello_pci in gdb Using To facilitate the use of ChipScope to analyze OPB PCI hardware the opb_pci cdc file is ChipScope with included in the m1410_ppc_opb_pci chipscope directory The opb_pci cdc is used to OPB PCI insert a ChipScope ILA core into the pci32_bridge_wrapper core To insert a core and analyze OPB PCI problems with ChipScope execute the following steps 1 Invoke XPS Run Hardware Generate Netlist 2 In the opb_pci cdc file change the path lt design_directory gt
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