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7702/7703 Group USER`S MANUAL - Digi-Key

1. o e lt o o O O gt gt 11 12 13 14 15 16 17 18 19 20 21 22 External clock input frequency f XIN Address decode time and address latch delay time are not considered Fig 17 1 4 Relationship between taan and f Xin 25 MHz version 2 2 42 Q gt 9 O 18 19 22 23 24 25 2 External clock input frequency f XIN Fig 17 1 5 Relationship between tsup and f Xin 25 MHz version 7702 7703 Group User s Manual 17 7 APPLICATION 17 1 Memory expansion 17 1 3 Points in memory expansion 1 Reading data Figure 17 1 6 shows the timing at which data is read from an external memory When reading data the external data bus is placed in a floating state and data is read from the external memory This floating state is maintained from 2 after the falling edge of the E signal till tpzx e eiz iezz after the rising edge of the E signal Table 17 1 4 lists the values of tpxz E P1z P22 and the formulas to calculate tpzx E P1z P22 Consider timing during data read to
2. RAM 512 bytes ROM 16 Kbytes Fee Hd dz X Note The 7703 Group does not have the P33 P43 P4e P60 P61 P66 P67 P73 P76e P84 and P85 pins Fig 1 4 1 M37702 block diagram 1 12 7702 7703 Group User s Manual Input Output port P5 Input Output port P8 Input Output port PO Input Output Input Output port P2 port P1 Input Output port P3 Input Output port P4 Input Output port P6 Input Output port P7 CHAPTER 2 CENTRAL PROCESSING UNIT CPU 2 1 Central processing unit 2 2 Bus interface unit 2 3 Access space 2 4 Memory assignment 2 5 Processor modes CENTRAL PROCESSING UNIT CPU 2 1 Central processing unit 2 1 Central processing unit The CPU Central Processing Unit has the ten registers as shown in Figure 2 1 1 b15 b8 b7 bO AH AL Accumulator A A b15 b8 b7 bO BH BL Accumulator B B b15 b8 67 bO XH XL Index register X X b15 b8 b7 bO YH Y Index register Y Y 015 08 67 00 Data bank register DT b23 b16 b15 b8 b7 bO b7 b0 s ee es eno ene Program bank register PG b15 b8 b7 bO D15 b8 b7 bO PSH PSL Processor status register PS b15 b10 b9 b8 b7 b6 b5 b4 b3 b2 bi Carry flag Zero flag Interrupt disable flag Decimal mode flag Index register length flag Data length flag Overflow flag
3. setting port P5 and port P6 direction registers Setting count start bit to 1 UN b7 Port P5 direction register 35 Address D16 Couni start register Address 4016 TAOIN pin Timer AO count start bit TATIN Timer 1 count start bit Uae Timer A2 count start bit TASIN pin b7 Timer count start bit Port P6 direction l register Address 1 016 9 Timer A4 count start bit d TA4IN Clear the corresponding bit to 0 a Setting count start bit to 1 b7 Count start register Address 4016 Timer AO count start bit Timer At count start bit Timer 2 count start bit Timer A3 count start bit w timer 4 count start bit d Trigger input to TAi pin eee eee Trigger generated Count starts Fig 5 6 3 Initial setting example for registers relevant to PWM mode 2 5 42 7702 7703 Group User s Manual TIMER A 5 6 Pulse width modulation PWM mode 5 6 2 Count source In the PWM mode the count source select bits bits 6 and 7 at addresses 5616 to 5A e select the count source Table 5 6 2 lists the count source frequency Table 5 6 2 Count source frequency Count source Count source Count source frequency NE bits b7 f Xin 8 MHz f Xin 16 MHz 25 MHz 12 5 MHz 1 125 kHz 250 kHz 390 625 kHz 15625 Hz 31
4. 14 2 14 1 2 Input example of externally generated clockl 14 2 14 3 4 2 1 Clock generated clock generating circuitl a 14 4 HAPTER 15 ELECTRICAL CHARACTERISTICS 4 7 15 2 5 2 Recommended operating conditionsl 1 15 3 o 15 4 15 5 15 6 NER aaa 15 12 X de Mom 15 15 E 15 17 5 9 Memory expansion mode and microprocessor mode with Watt 15 21 5 10 Testing circuit for ports PO to 8 0 1 and 15 25 16 2 16 2 6 1 2 Icc f Xin standard n 16 3 16 4 Memory OX Dal SIO ee 17 2 H 17 2 nce 17 4 7 1 3 Points in memory
5. 7702 7703 Group User s Manual 21 59 APPENDIX Appendix 8 Machine instructions Function are DIR Y or L IDIR Y rj nij fool oo l f o Compares the contenta of the Index ragisar X with the contents af the menmary CPX Note 2 PY Compares the contents of ihe index register Y with the Note 2 contents of tha memory BEC Note 1 dU 2 10 Bf remainder EOR Logical exclusive sum is oblainer of the contents of the accumulation and the contents c the memory The result is placed inte he accumulator INC Acct Acc Tl or ha contants ci tk contents of the accumulator of memory by 1 M M INX X X i Increments the conients of the index register X Dy Pon JMF ABS Places a new address into the program counter and jumps PEL ADL lo that new address 21 60 7702 7703 Group User s Manual 1 2 ABL AD PCH AD PG ADa ABS PC AD PC AD AD L ABS PC AD PCy ADU T1 Pa ADL 2 ABS X Po AD t PC AD X I Saves the contents of tha program counter Lalso the con tenis of tha program bank register for ABE Into the stack and jumps 15 ihe new address ABS X MS 5 5 MS PC 8 5 1 AD AD X
6. 8 17 s 8 19 wm 8 20 9 ettings for single sweep 1 2 6 8 20 8 7 2 Single sweep mode operation description 8 22 8 24 8 24 MM MEME 8 26 8 9 Precautions when using A D amp 8 28 CHAPTER 9 WATCHDOG TIMER G4 9 2 e 9 3 9 1 2 Watchdog timer frequency select register f 9 4 cpm 9 5 n 9 5 ifi O 9 7 OA HH 9 7 9 3 Precautions when using watchdog timerl 9 8 0 1 Clock qeneratina circuill 10 2 ETE EE E p s a 10 3 10 2 1 Termination by interrupt request 10 4 x 10 5 m H 10 6 11 1 Clock generating circuill 11 2
7. 220 min E OC ALS245A w I I TWN 04 tPLH AC74 AC32 X 2 gt 70 max A D j ALS245A ALS245A gt lt tPHL tPLH P lt tPuz tPLz gt lt Write hold time Unit ns Fig 17 1 14 Timing chart for sample circuit using bus buffers 2 7702 7703 Group User s Manual 17 19 APPLICATION 17 1 Memory expansion 17 1 4 Example of memory expansion 1 Example of SRAM expansion minimum model Figure 17 1 15 shows a memory expansion example minimum model using a 32 Kbyte SRAM in the memory expansion mode Figure 17 1 16 shows the timing chart for this example 37702 2 1 eee 451 2 Use the elements of which propagation delay time is within 18 ns Memory map 000016 SFR area 008016 Internal RAM area 088016 External RAM area 800016 5 5256 R W internal ROM area 25 MHz Circuit condition Wait Fig 17 1 15 Example of SRAM expansion minimum model 17 20 7702 7703 Group User s Manual APPLICATION 17 1 Memory expansion lt When reading gt E OE 130 min 12 min Do D7 621 External RAM data output lt When writing gt E OE Ao A14 Do D7 WE lt gt 5 max AC32 tPHL lt gt la s lt gt
8. 5 24 CEES 5 26 5 30 5 32 En 5 94 5 35 5 36 5 39 5 6 1 Setting for PWM 5 41 EUER 5 43 modes 5 43 5 6 4 Operation in PWM 2 0 2 66 5 44 Y 6 2 6 2 6 2 1 Counter and reload register timer Bi register 6 3 et eee et eee ee 6 4 6 2 3 limer Bi mode EEE EEE REE Ean 6 5 6 2 4 Timer Bi interrupt control 6 6 7702 7703 Group User s Manual Table of Contents 2 6 6 7 uu 6 8 6 3 1 Selling TOF mer ModE uu u u 6 10 om EE CON SO OL uu u una 6 11 Sasu 6 12 I S S u X 6 14
9. 7 40 nr 7 44 1 4 5 Method of reception 7 46 un S S SS s nsn 7 49 7 4 7 Process on detecting errorl a 7 51 7 52 Precautions when operating in clock asynchronous serial 7 53 8 2 8 3 S2 AD Control regisi8 ku uuu uuu u u I S RUNE 8 4 n 8 6 8 2 3 A D register i i 0 TO 7 L xu 8 7 A 8 8 8 2 5 Port P7 direction iara ana NEE 8 9 7702 7703 Group User s Manual iii Table of Contents 8 3 A D conversion methodil U U U U U Q 8 10 Q 8 12 8 12 8 4 2 Differential non linearity 1 1 Hmmm 8 13 T PO H 8 14 8 5 1 Settings for one shot modej eese Immer 8 14 S LL 8 16 a MALE 8 17 8 6 1 Settings for repeat model
10. tsu P1D P2D E gt 30 Unit ns Fig 17 1 18 Timing chart for ROM expansion example maximum model 7702 7703 Group User s Manual 17 23 APPLICATION 17 1 Memory expansion 3 Example of ROM and SRAM expansion maximum model Figure 17 1 19 shows a memory expansion example maximum model using two 32 Kbyte ROM and two 32 Kbyte SRAM in the microprocessor mode Figure 17 1 20 shows the timing diagram for this example C M37702S1B M5M27C256AK 15 M5M5256CP 70LL CNVss Address bus BvVTE Y AC573 2 8 08 A15 D15 ALE Data bus even ACOA R W E Ao BHE XIN XOUT Memory map 000016 SFR area 008016 Internal Circuit condition Wait RAM area 028016 External ROM area M5M27C256AK X2 1 2 Use the elements of which sum of propagation delay time is within 92 ns External 2 Use the elements of which propagation delay time is within 12 ns RAM area 3 Use the elements of which propagation delay time is within 13 ns 5 5256 2 Fig 17 1 19 Example of ROM and SRAM expansion maximum model 1 24 7702 7703 Group User s Manual APPLICATION 17 1 Memory expansion lt When reading gt gt NY A 5 max As Ds A15 D15 a a ee sie ep M 1 0 2 28 min po 04 tPHL mE lt lt CE 5 NEA 5 gt lt 32
11. 18 12 18 46 ETSEDGPMSTBaSS 18 18 18 4 7 Single chip modej eee In nmm mn nnn nennen rens 18 21 18 4 8 Memory expansion mode and microprocessor mode with no Walt 18 23 18 4 9 Memory expansion mode and microprocessor mode with Wait 18 27 umen 18 31 18 5 Standard aun 18 32 18 5 1 Port standard 4 01 47 4 4 44 18 32 18 33 18 5 3 A D converter standard characteristics l 18 34 18 6 FA OIG RERUMS 18 35 18 6 1 Memory 4 18 35 18 6 2 Memory expansion example on minimum 2 22 0 0 2 2 18 37 18 6 3 Memory expansion example on medium model l 18 39 18 6 4 Memory expansion example on maximum modell 18 41 18 6 5 Ready generating circuit 09 18 43
12. 1 4 meme nennen nre enis 17 8 7 1 4 Example of memory RR a 17 20 w 17 26 17 2 Sample program execution rate 17 29 dependino Wailll 17 29 17 31 CHAPTER 18 LOW VOLTAGE VERSION CO 18 3 18 4 19 3 Functional descriptio M 18 6 O 18 7 7702 7703 Group User s Manual V Table of Contents vi 7702 7703 Group User s Manual E 18 8 18 4 1 Absolute maximum 1 1 2 1 4 nennen 18 8 18 4 2 Recommended operating 0 1 10 2 07 01 4 18 9 19 4 3 Electrical characteristics 18 10 18 11 18 4 5 Internal peripheral 1 22 6
13. P 11 3 11 2 1 Termination by interrupt request occurrencel 11 4 11 2 2 Termination DY hardware resell ED 11 4 T eeov 11 5 12 1 Signals required for accessing external 12 2 12 1 1 Descriptions of SION al Si uuu a 12 2 12 1 2 Operation of bus interface unit BIU 12 8 IPEESNUEW AWL S M 12 11 12 13 12 14 HM 12 16 wes sss sss ss nas 12 17 7702 7703 Group User s Manual Table of Contents CHAPTER 13 RESE 13 1 Hardware resell 13 2 i S S SS S D s E 13 3 mM 13 4 asi 13 9 Le REMIS 13 10 13 2 Software FOS CUR Mc 13 12 CHAPTER 14 CLOCK GENERATING CIRCUIT Q 14 2 14 1 1 Connection example using resonator oscillator l
14. WN 1x 1 X 10 1 X 10 if S 6 2 _ 0 2 X XIN 2 X in 2 X f XIN 9 th E P2Q 12 TX 10 B 1 10 1 X 10 tpzx E p2z Note f XIN x xw 22 Note For the M37702E2AXXXFP M37702E2AFS M37702E4AXXXFP M37702E4AFS refer to section 19 5 4 Bus timing and EPROM mode For the M37703E2AXXXSP and M37703E4AXXXSP refer to section 20 6 2 Bus timing and EPROM mode 15 22 7702 7703 Group User s Manual ELECTRICAL CHARACTERISTICS 15 9 Memory expansion mode and microprocessor mode with Wait Memory expansion mode and microprocessor mode With Wait lt Write gt f Xin 0 1 E Address output Ao A7 Address output 15 BYTE Address Data output As Ds A15 D15 BYTE Data input 08 015 BYTE L Address Data output A1e Do Az3 D7 Data input Do D7 ALE output BHE output R W output Port Pi output i 4 8 td POA E lt gt lt th E td P1A EJ 5 lt lh E P1A lt gt ta P1A th ALE P1A tw ALE td ALE E td BHE EJ Test conditions 01 E PO P3 Vcc 5 V 10 Output timing voltage Data input Vor 0 8 V 2 0V ViL 0 8 V VIH 2 5 V 7702 7703 Group User s Manual ta P1A E gt lt gt td E P1Q th E P1
15. lt Read gt tw L tw H tr tr tc lt f Xin 1 ld E 6 1 61 E tw EL lt h E Address output Nae Address Address output td P1A E lt h E P1A 15 Address Address Data output E 9 Tpxz E 12 12 As Ds At15 D15 Address BYTE L ta P1A ALE gt th ALE P1A tsu P1D E 26 ata Datal BYTE L td P2A E 27 tozx E 22 Address Data output V TN tft a PIDE ta P2A ALE th ALE 2 tsu P2D E 20 Data input 2 2 eni Do D7 tw ALE Data lt gt td ALE E ALE output td BHE EJ lt gt th E BHE output CTS ta R W lt gt th E R W R W output tsu PiD gt E lt th E Port Pi input i 4 8 Test conditions 01 PO P3 Test conditions P4 P8 Vcc 5 V 10 Vcc 5 V 10 Output timing voltage Vor 0 8 V Vor 2 0 V Input timing voltage VIL 1 0 V VIH 4 0 V Data input VIL 0 8 V VIH 2 5 V Output timing voltage VoL 0 8 V VOH 2 0 V 15 20 7702 7703 Group User s Manual ELECTRICAL CHARACTERISTICS 15 9 Memory expansion mode and microprocessor mode with Wait 15 9 Memory expansion mode and microprocessor mode with Wait
16. 25 18 ns PortP2floatingreleasedelaytime 1 1 11 11 1 865wes 1 18 ns BHE holdtime o 11 1111 18 118 ns R Wholdtme 118 18 ns For the M37702E2AXXXFP M37702bE2AFS M37702E4AXXXFP and M37702EAAFS refer to section 19 5 4 Bus timing and EPROM mode For the M37703E2AXXXSP and M37703EAAXXXSP refer to section 20 6 2 Bus timing and EPROM mode For test conditions refer to Figure 15 10 1 This is the value depending on f Xin For data formula refer to Table 15 8 1 Table 15 8 1 Bus timing data formula Sign E d tw EL ta P1A E ta P2A E ta P1A ALE ld P2A ALE lw ALE th E P2Q 12 22 lt 8 MHz 8 MHz lt f Xw lt 16 MHz 16 MHz lt f Xin lt 25 MHz 2x 10 xi 1 10 1 2 X 10 1 X 10 1x10 _ WA 75 1x10 _ 100 125 12 40 1 10 _ 1X10 1X10 XN 749 XN 7 395 XIN 39 1X10 1X 10 1 X105 Xi 59 XN 279 xw 18 1X 10 1 2 10 _ 1 10 _ 40 100 125 30 XIN 75 f XIN p __1 10 gt __ 1X 10 _ 129 2x 9 2 X 110 1X 10 1 X 10 Note Xm 7 Xm 26 Foun 22 Note For the M37702bE2AXXXFP M37702E2AFS M37702E4AXXXFP and M37702E4AFS refer to section 19 5 4 Bus timing and EPROM mode For the M37703E2AXXXSP and M37703E4AXXXSP refer to section 20 6 2 Bus timing and EPR
17. 2 18 2 4 1 Memory assignment in internal areaL eee 2 18 AIME 2 21 2 5 1 SING o5 E 2 22 2 5 2 Memory expansion and microprocessor modesl 2 22 2 5 3 Setting Mfocessor 2 25 ANT 2 27 CHAPTER 3 INPUT OUTPUT PINS 3 1 Programmable I O 3 2 E T 3 3 su 3 4 3 8 CHAPTER 4 INTERRUPTS 4 2 H 4 4 7702 7703 Group User s Manual i Table of Contents 4 3 ncidseduislt 4 6 4 3 1 Interrupt disable flag 4 8 4 4 Interrupt priority 4 10 4 5 Interrupt priority level detection circuill 4 11 4 6 Interrupt priority level detection timel 4 13 4 14 4 1 Change in IPL at acceptance of interrupt
18. 22 1 X 10 _ 22 Note Note In the M37702E2AXXXFP the M37702E2AFS the M37702E4AXXXFP the M37702E4AFS the M37703E2AXXXSP and the M37703EAAXXXSP refer to section 19 5 4 Bus timing and EPROM mode 7702 7703 Group User s Manual 17 9 APPLICATION 17 1 Memory expansion 2 Writing data Figure 17 1 7 shows the timing at which data is written to an external memory When writing data the output data starts after tae riap2a passes from falling of the E signal Its validated data is output continuously until passes from rising of the E signal Table 17 1 5 lists the calculation formulas of the P1 P20 Table 17 1 6 lists the constants of tag P o e20 Data output at writing data must satisfy the data set up time and the data hold time tho for write to an external memory E External memory __ write signals W External memory chip select signals CE th E P1Q P2Q Address and data output As Ds Ais5 Dis Address Data d Address 2 A16 Do Az23 D7 thio tsu D Specifications of the M37702 The others are specifications of external memory This applies when the external data bus has a width of 16 bits BYTE L Fig 17 1 7 Timing at which data is written to an external memory Table 17 1 5 Calculation formulas of twe piq p2q unit ns nM Xin lt 8 MHz 8 MHz lt lt 16 MHz 16 MHz lt f Xin
19. 4 16 2 Stong p 4 17 4 18 4 18 4 10 External interrupts INT interrupt L ccccccscccsscccscccssccssccesscessesessecesecesseeeseeesseseees 4 20 n 4 23 4 25 Uu m 4 26 CHAPTER 5 TIMER A AX 5 2 5 3 UM ns 5 4 5 2 2 Count start reglster 5 5 5 2 3 Timer Ai mode reqistelrl Sl 5 6 5 2 4 Timer Ai interrupt control register mmn 5 7 5 2 5 Port P5 and port P6 2 2 22 2 5 8 O avem 5 9 5 3 1 Setting for timer model 5 11 COUN SOUCO ENT 5 13 5 3 3 Operation in timer 4 1 41 nennen na 5 14 5 04 Select TUncios pea er 5 15 uns 5 19 5 22
20. A Ao 15 015 P1 D odd D odd Data at odd address A23 D7 A16e Do P2 Aes Dz Aes D x Mdb D D even Data at even address D Data HLDA P33 HIDA X Note j ALE P32 ALE LDA R W P30 W P47 Functions as programmable I O port 1 P42 1 Note 2 RDY P41 Note 4 HOLD P4 Note 4 Notes 1 The 7703 Group does not have the HLDA pin 2 the memory expansion mode this pin functions as a programmable I O port and can be programmed as the clock 1 output pin by software 3 This table shows the pins functions Refer to the following about the input output timing of each signal 12 1 2 Operation of bus interface unit 12 2 Software Wait 12 3 Ready function 12 4 Hold function Chapter 15 Electrical characteristics 4 Fix bits 0 and 1 of the Port P4 direction register to 0 Perform the setup regardless of whether using the P4 o HOLD and P41 RDY pins as the HOLD or RDY pins or not For the external ROM version perform the same setup 12 4 7702 7703 Group User s Manual CONNECTION WITH EXTERNAL DEVICES 12 1 Signals required for accessing external devices 1 External bus Ao to As Ds to A1s Dis 0 to A23 D7 External areas are specified by the address Ao A23 output Figure 12 1 2 shows the external area Pins to As of the ext
21. 1 3 Io Pi u u uuu 1 4 m s 1 6 HP 1 9 1 12 CHAPTER 2 CENTRAL PROCESSING UNIT CPU 2 1 Central processing 2 2 2l T ACCUMULO ACC 2 3 2 3 2 1 3 Index register Y Y L NyY 2 3 R JZi 2 4 2 1 5 Program counter PCG M 4 2 5 MX ang 2 5 2 1 7 Data bank register DIJ 2 6 ES 2 6 tenes 2 8 2 2 Bus interface 2 10 d 2 10 n 2 12 2 14 2 3 Access SO ril EE n C f T 2 16 Much ou 2 17 nme 7 a Rm 2 17 2 4 Memory _assiqnmenLtll J MEER aaa EE
22. uo spuedep esind ye eui 41 01 9 00 Dunes Jaye 191sIB 1 eui 01195 enjeA Meqe ue ueuM D 8 SJo1si68J 219 JO 99 94 21 BOINOS 1unoo Jo AouenbauJJ J Je1siDeJ V 1 0 19 9 0 0 JejsiDeJ V 1 0 19 9 2000 JejsiDeJ ry 01195 S 9 20 0 3 l inolV 1ndlno WMd i i i Bununoo Bununoo i suelsed 5006 i i a M 1 I I I i I I 9 10 c E I I 4 4 4 0 no I I I I i I I I I 1 o i 2 I I I I I 5 8 2 5 1 4 19140 I i i I i T I I i I D l I I r ni NEM UM WIRE Suus e A O O x H s u uo9 SJ9 eosaJg ala euDis 1ndui s uid NIIV L N NOS JUNOD 1 w 4 4 1 X w x 4 4 n mote M UE ES L X L u x 4 1 Fig 5 6 7 Operation example of 8 bit pulse width modulator when counter value is upda
23. Meme ix 2048 18000 to TFFFFw 0000 s to 7FFF4 Werreteers 208 FEF M37702E8BFS 60 2044 gt 111000 to TFFFFic Notes 1 Refer also to section 19 5 4 Bus timing and EPROW mode 2 A blank product of the one time PROM version does not have the ROM number which is printed on the XXX position For example M37702bE2BFP 7702 7703 Group User s Manual 19 3 PROM VERSION 19 2 EPROM mode 19 2 EPROM mode The built in PROM version has the following two modes Normal operating mode This mode has the same function as the mask ROM version EPROM mode The built in PROM can be programmed and read in this mode The PROM version enters this mode when L level is input to the RESET pin 19 2 1 Write method There are 2 types of the EPROM mode 1M mode and 256K mode 256K mode is recommended to write data deeply for the one time PROM version of which internal PROM size is 32 Kbytes or less 1M mode is recommended for the EPROM version owing to its write velocity faster than 256K mode It is because to write and erase is repeated for the EPROM version However the M37702E2AFS and M37702E4AFS cannot use 1M mode Additionally use 1M mode to write and read in the built in PROM version of which PROM size is 32 Kbytes or more 19 4 7702 7703 Group User s Manual PROM VERSION 19 2 EPROM mode 19 2 2 Pin description Table 19 2 1 lists the pin description in the EPROM mode In the nor
24. P4o P47 P5o P57 0 3 to Vcc 0 3 P6o P6 P7o P7 P80 P87 Xovr E Powerdissipalon MS7ORMELXXXGP Ta 25 0 390 Ta 25 Tx Operating temperature _ T Storage temperature J _ 18 8 7702 7703 Group User s Manual LOW VOLTAGE VERSION 18 4 Electrical characteristics 18 4 2 Recommended operating conditions Recommended operating conditions Vcc 2 7 5 5 V Ta 40 to 85 unless otherwise noted Vcc Power source voltage V AVcc Analog power source voltage Me V Vss Power source voltage U 0 V AVss Analog power source voltage C O fy High level input voltage 0 0 P4o P4 5 57 P60 P67 P70 P 77 s P8o P87 Xin RESET CNVss Y BYTE Vin High level input voltage Plo P17 P2o P27 0 8Vec V in single chip mode High level input voltage P1o P17 20 27 memory expansion mode 0 5Vcc Vcc V microprocessor mode Low level input voltage POo P07 P4o P 47 5 57 P6o P67 P7o P77 P8o P87 Xin RESET CNVss M BYTE Vi Low level input voltage 10 1 P2o P27 02010 02V V in single chip mode High level peak output current 0 07 P1c P17 27 peak 40 45 P5o P57 P60 P67 P7o P77 P80 P87 High level average output current POo P07 P1o P17 20 27 loH
25. gt lt gt gt 80 79 78 77 76 75 74 73 7271 74 69 646766 65 7 lt P67 TB2In lt P66 TB1IN lt gt P65 TBOIN lt P64 INT2 lt gt P63 INT1 lt 6 _ P62 INTo lt gt P61 TA4IN lt 8 P60 TA4ouT 9 P57 TAS3IN lt gt P5e TA3OUT lt gt P55 TA2IN lt gt P54 TA2ouT P53 TA1IN lt P52 TA10UT lt P51 TAOIN lt P50 TAOQOUT lt P47 lt gt 46 lt gt P45 lt gt P44 c P43 P42 01 lt P41 RDY lt gt Q A I T 5l RPP RTP miei e amp joj Ol Oly ol o Or 9 gt IODO NE Coy oo gt gt gt N e N I gt lt gt lt gt lt T1 U A BYTE gt P27 A23 D7 gt 5 26 22 06 lt gt 9 25 21 05 lt gt 8 P24 A20 D4 lt gt 5 P40 HOLD Outline 80P6N A Fig 18 2 2 M37702M4LXXXFP pin configuration top view 7702 7703 Group User s Manual eee P84 CTS1 RTS1 P85 CLK1 P86 RxD1 P87 TxD1 POo Ao PO1 A1 PO2 A2 PO4 A4 5 5 PO7 A7 P10 As Ds P11 A9 Do P12 A10 D10 P13 A11 D11 P14 A12 D12 P15 A13 D13 P16 A14 D14 P17 A15 D15 20 16 0 21 17 01 22 18 02 23 19 03 LOW VOLTAGE VERSION 18 3 Functional description 18 3 Functional description The M37702M2
26. 6 16 6 17 6 5 Pulse period pulse width measurement 6 19 6 21 IP PE EE E I RM EE MM EMEN 6 23 m 6 24 m 7 2 d 7 3 Uu 7 4 7 2 2 transmit receive control register O sues 7 6 7 2 3 transmit receive control register 1 5 5 suem 7 7 7 9 7 11 2 em 7 13 7 14 2 8 Port P8 direction registerf 1 7 16 7 3 Clock synchronous serial model 7 17 Em 7 18 7 3 2 Method of transmission 7 19 7 3 3 Transmit 9 4 7 23 f E E EE EEE E E EE 7 25 7 3 9 Receive operaltioni RM o 7 29 T 7 32 7 33 NGC 7 35 7 36 7 4 2 nnne 7 38 7 4 3 MethoW Of 1
27. LOSSARY 7702 7703 Group User s Manual Vii Table of Contents MEMORANDUM Viii 7702 7703 Group User s Manual CHAPTER 1 DESCRIPTION 1 1 Performance overview 1 2 Pin configuration 1 3 Pin description 1 4 Block diagram DESCRIPTION The 16 bit single chip microcomputers 7702 Group and 7703 Group are suitable for office business and industrial equipment controllers that require high speed processing of large amounts of data These microcomputers develop with the M37702M2BXXXFP as the base chip This manual describes the functions about the M37702M2BXXXFP unless there is a specific difference and refers to the M37702M2BXXXXFP as M37702 Notes 1 About details concerning each microcomputer s development status of the 7702 7703 Group inquire of CONTACT ADDRESSES FOR FURTHER INFORMATION described last Notes 2 How the 7702 7703 Group s type name see is described below 3 77 02 M 2 B XXX FP Mitsubishi integrated prefix Represent an original single chip microcomputer Series designation using 2 digits Circuit function identification code using 2 digits Memory identification code using a digit M Mask ROM E EPROM S External ROM Memory size identification code using a digit Difference of electrical characteristics identification code using a digit Mask ROM number Package style FP Plastic molded QFP Plastic molded QFP HP Plastic molded fine pitch QFP SP Plastic
28. fea RW 11 6512 Fig 20 4 3 Structure of timer 1 and B2 mode registers 7702 7703 Group User s Manual 20 7 7703 GROUP 20 4 Functional description 20 4 4 Serial I O The M37703 s UART1 be used only in the clock asynchronous serial mode UART mode It cannot be used in the clock synchronous serial mode Do not set the serial mode select bits bits 2 to 0 at address 38 to 0012 to select the clock synchronous serial mode Figure 20 4 4 shows the structure of the UART1 transmit receive mode register 1 CLK1 pin The M37703 does not have the pin Set the internal external clock select bit bit at address 3816 to 0 to select the internal clock 67 b6 b5 b4 b3 b2 bi bO b2 b1 bO 0 0 0 Seria O disabled P8 functions as a programmable port Not selected Not selected T Not selected UART mode Transfer data length 7 bits Serial I O mode select bits UART mode Transfer data length 8 bits UART mode Transfer data length 9 bits Not selected Fix these bits to 0 To select internal clock Stop bit length select bit One stop bit Valid in UART mode Note Two stop bits Odd Even parity select bit 0 Odd parity RW Valid in UART mode when 1 Even parity parity enable bit is 1 Note Parity enable bit 0 Parity disabled RW Valid in UART mode Note 1 Parity enabled Sleep select bit 0 Sleep mo
29. 206 8000 Glass seal 8Opin QFN EIAJ Package Code JEDEC Code Weight g Scale 2 1 21 0 10 2 3 32MAX 18 4 0 15 L 78TYP 15 6 0 2 2 0 0 15 21 32 7702 7703 Group User s Manual APPENDIX Appendix 4 Package outlines 8 65 Plastic 8Opin 14 14 body EIAJ Package Code JEDEC Code Weight g QFF80 P 1414 0 65 Recommended Mount Pad zumbol Dimension in Millimeters m PL Min Nom Max 3 05 01 G2 c uis 62 m e 14 Detail F SOP6D A EIAJ Package Code JEDEC Code LQFP80 P 1212 050 04 Aloy42 Scale 2 5 1 Recommended Mount Pad mbol Dimension in Millimeters d oe qoe 0 01 14 0 28 C 0 175 12 1 12 1 05 14 2 3 0 5 1 0 T1 Vemmlatatalatatatlatatatatatatatatatatalatalamy Co A 142 03 05 O Li 10 w si Lu 0 025 b 10 Detail F Mo 124 124 ob D are 424 b2 olo lt N gt 7702 7703 Group User s Manual 21 33 APPENDIX Appendix 4 Package outlines 64P4B Plastic 64 75 SDIP EIAJ Package Code JEDEC Cade SDIP64 P 750 1 78 Scale 83 AAAA AAAA DL EL DL C DO Q UV eve 32 D 562 564 566 17 15 778 AT NG PL
30. D AA gt BC32 tPHL gt _ lt 2 F245 WO WE F245 F245 tPHL tPLH tPHZ tPLZ External memory 3D 4 data output B F245 Unit ns Fig 17 1 12 Timing chart for sample circuit using bus buffers 1 7702 7703 Group User s Manual 17 17 APPLICATION 17 1 Memory expansion M37702 Address bus ALE ALS245A 2 As Ds 15 015 B 4 P Data bus odd DIR OCL ALS245A 2 A16 Do _ A23 D7 A B Data bus even DIR OC This is the circuit that extends the write hold time by making the rising of the write signal 1 26 1 clock earlier Circuit condition Wait 1 Use the elements of which propagation delay time is within 30 ns 2 Use the elements of which output enable time is 5 ns or more and output disable time is within 36 ns Fig 17 1 13 Example for using bus buffer connecting with memory requiring a long hold time for write 17 18 7702 7703 Group User s Manual APPLICATION 17 1 Memory expansion lt When reading gt E OC ALS245A As Ds A15 D15 A16 Do A23 D7 External memory data output A ALS245A lt When writing gt 1 1 1Q 74 2Q AC74 WO WE A8 D8 A15 D15 A16 Do A23 D7 External memory data output B ALS245A 220 min a 2 tPHL 32 ALS245A tPZH tPZL ALS245A tPHZ tPLZ
31. LL Addresses 7 16 to 7C16 Interrupt priority level select bits When using interrupts set these bits to level 1 7 When disabling interrupts set these bits to level 0 d Setting count start bit to 1 b7 Count start register Address 4016 Timer BO count start bit Timer B1 count start bit Timer B2 count start bit Count starts Fig 6 3 2 Initial setting example for registers relevant to timer mode 6 10 7702 7703 Group User s Manual TIMER B 6 3 Timer mode 6 3 2 Count source In the timer mode the count source select bits bits 6 and 7 at addresses 5 16 to 5016 select the count source Table 6 3 2 lists the count source frequency Table 6 3 2 Count source frequency Count source Count source Count source frequency a bits b7 25 MHz 0 12 5 MHz 0 1 Je 5 Mz 1 5625 MHz t 0 Je 125kHz 250kHz 390 625 kHz ise 15625 Hz 31250 Hz 48 8281 kHz 7702 7703 Group User s Manual 6 11 TIMER B 6 3 Timer mode 6 3 3 Operation in timer mode When the count start bit is set to 1 the counter starts counting of the count source When the counter underflows the reload register s contents are reloaded and counting continues 3 The timer Bi interrupt request bit is set to 1 when the counter underflows The interrupt request bit remains set to 1 until the interrupt request is acce
32. lt gt POs As 4 P5e TA3o0uT lt gt 9 N N lt gt P06 Acs P55 TA2 In lt gt TI TI lt gt P07 A7 amp P54 TA20UT lt gt ES lt gt Pio As Ds P5s TA1IN lt gt lt gt P11 A9 Do CGED 5 1 4 e a lt gt P12 A10 D10 P51 TAOIN lt gt gt gt lt lt gt 1 11 011 P5o TA0ouT lt gt lt gt 14 12 012 gt 3 lt gt Pis A13 D13 e Ph lt gt lt gt P16 A14 D14 e P4 lt gt lt gt 17 15 015 e Phu gt lt gt P20 A16 D0 Phe lt gt P2uUAv Di C Di C D22 P22 A18 D2 lt 5 Outline 80P6S A Outline 80P6D A Fig 19 4 2 Pin connections in 256K mode 2 19 14 7702 7703 Group User s Manual Connect an oscillating circuit C gt EPROM pins PROM VERSION 19 4 256K mode 19 4 1 Read Program Erase Table 19 4 2 lists the built in PROM state in 256K mode and each mode is described bellow 1 Read When pins and OE are set to L level and an address is input to address input pins the contents of the built in PROM can be output from data I O pins and read When pins and OE are set to H level data I O pins enter the floating state 2 Program Write When pin OE is set to H level and VPP level is applied to pin VPP programming to the built in PROM becomes
33. pala cold 9 GIG eld HG Od loaxy Q S pepuedxe 0 Z Je1siDeJ yius jo Dumndino 19391891 114 Jo eyep Dumndino jeas ta lt Jeisi09J 1 6 ox jenas 0419 49181691 Jus 0 sod pepuedxe 6umndu SO pepuedxe S Fig 17 1 22 Serial transfer timing between M37702 and M66010FP 7702 7703 Group User s Manual 17 28 APPLICATION 17 2 Sample program execution rate comparison 17 2 Sample program execution rate comparison Sample program execution rates are compared in this paragraph The execution time ratio depends on the program or the usage conditions 17 2 1 Difference depending on data bus width and software Wait Internal areas are always accessed at 16 bit data bus width and without software Wait In the external areas the external data bus width and software Wait are selectable Table 17 2 1 lists the sample program refer to Figure 17 2 1 execution time ratio depending on these selection and used memory areas Table 17 2 1 Sample program execution time ratio external data bus width and software Wait Memory area External data bus Software Wait Sample program execution time ratio RAM ROM width bit Sample A Sample B internal 1 0 100 N 110 1 06 148 1 0 Maui im 1 65 C
34. register low order 8 bits setting value n Timer Ai register high order 8 bits setting value Count start condition When a trigger is generated Note Internal or external trigger can be selected by software Count stop condition When count start bit is cleared to 0 Interrupt request occurrence timing At falling of PWM pulse TAiIN pin function Programmable I O port or trigger input TAIOUT pin function pulse output Head from timer Ai register An undefined value is read out Write to timer Ai register While counting is stopped When a value is written to timer Ai register it is written to both reload register and counter e While counting is in progress When a value is written to timer Ai register it is written to only reload register Transferred to counter at next reload time Note The trigger is generated with the count start bit 1 7702 7703 Group User s Manual 5 39 TIMER A 5 6 Pulse width modulation PWM mode b7 b6 b5 b4 b3 02 bl b0 aaa Timer Ai mode register i 0 to 4 Addresses 5616 to 5A16 ee n 00 Writing 1 to count start bit 01 TAim pin functions as a pro grammable port 0 Falling edge of TAin pin s input signal 1 1 1 Rising of TAi ai input signal b4 b3 b7 b6 00 fe 0 1 116 10 164 11 1512 lt When operat
35. 0 at address 5E e during program execution is there any precaution in software Single chip mode Microprocessor mode Memory expansion mode Microprocessor mode If the processor mode is switched as described above by using the processor mode bits the mode is switched simultaneously when the cycle to write to the processor mode bits is completed Then the program counter indicates the address next to the address address XXXX s that contains the write instruction for the processor mode biis Additionally access to the internal ROM area is disabled However since the instruction queue buffer can prefetch up to three instructions the address in the external ROM area and is accessed first after the mode is switched is one of XXXXie 1 to XXXXie 4 ihe instructions at addresses XXXXie 1 to XXXXie 3 in the internal ROM area can be executed To prevent this problem process the following by software Write the write instruction for the processor mode bits and next instructions at least three bytes at the same addresses both in the internal ROM and external ROM areas See below Interna ROM area External ROM area 1 LDM 4000000108 PHR XXXX1e LDM 00000010B PMR 21 92 NOP NOP NOP At least NOP NOP three NOP bytes Transfer the write instruction for the processor mode bits to an internal RAM area and make a branch to there in order to execute the write instruction Af
36. 16 17 52 x R W WE Unit ns Fig 18 6 6 Memory expansion example on medium model A 18 40 7702 7703 Group User s Manual LOW VOLTAGE VERSION 18 6 Application 18 6 4 Memory expansion example on maximum model Figure 18 6 7 shows a memory expansion example on the maximum model Figure 18 6 8 shows the corresponding timing diagram In this example Atmel company s EPROMs AT27LV256R are used as the external ROMs In Figure 18 6 7 the circuit condition is No Wait M37702S1L AT27LV256R 15DI M5M51008AFP 10VLL Address bus 04 AC32 Yooo e K zE S1 51 S2 S2 A0 A15 A16 Data bus even 04 3 AC32 2 RD Memory map AC32 2 000000 6 SFR area re 00008016 Internal 8 MHz RAM area 00028016 External Vcc 3 0 3 3 V OOFFFF e AT27LV256Rx2 Circuit condition no Wait Not used 02000016 Externa 11 2 Use the elements of which propagation delay time is within 30 ns RAM area 43 Use the elements of which propagation delay time is within 50 ns O3FFFF 5 51008 2 16 Fig 18 6 7 Memory expansion example on maximum model 7702 7703 Group User s Manual 18 41 LOW VOLTAGE VERSION 18 6 Application lt When reading gt As Ds A15 D15 Aie Do 61 External memory data output When writing E As Ds A15 D15 A16 Do Di D
37. 25 MHz rate bps BRGi count BRGi aig Actual time BRGi count m Actual time source value bps source value bps 150 300 600 1200 2400 4800 9600 19200 31250 159 9Fw 150 00 fee 162 er 162 x fs 9 1200 00 fe 80 504 maramma en 09 t 40 159 9F 4800 00 162 T 9600 00 80 50s 39 27 1920000 40 7702 7703 Group User s Manual 149 78 301 41 999 12 1205 63 2381 86 4792 94 9645 06 19054 88 31250 00 7 37 SERIAL I O 7 4 Clock asynchronous serial UART mode 7 4 2 Transfer data format The transfer data format can be selected from formats shown in Figure 7 4 1 Bits 4 to 6 at addresses 30 e 3816 select the transfer data format Refer to Figure 7 2 2 Set the same transfer data format for both transmitter and receiver sides Figure 7 4 2 shows an example of transfer data format Table 7 4 5 lists each bit in transmit data Transfer data length of 7 bits Transfer data length of 8 bits Transfer data length of 9 bits Fig 7 4 1 Transfer data format 7 38 1ST 7DATA 15 1ST 7DATA 25 1ST 7DATA 1PAR 1SP 1ST 7DATA 1PAR 2SP 1ST 8DATA 15 1ST 8DATA 25 1ST 8DATA 1PAR 1SP 1ST 8DATA 1PAR 2SP 1ST 9DATA 15 1ST 9DATA 2SP 1ST 9DATA 1PAR 1SP 1ST 9DATA 1PAR 2SP 7702 7703 Gro
38. l 70 45 ns P1 floating start delay time BYTE L C 5 5 ns teia P1 address output delay time 73 11257 ns l PTA ALE 24 5 ns PortP2daetaoutputdelaytime l 70 45 i c 2 Port P2 floating start delay time 5 5 Port P2 address output delay time 7 3 12 ns 2 24 5 ns tace lALEouputdelaytim 14 4 75 85 22 ns ka BHE E 30 120 ns ta w E 30 90 ss Note For test conditions refer to Figure 15 10 1 Xx This is the value depending on f Xin For data formula refer to Table 15 8 1 7702 7703 Group User s Manual 15 17 ELECTRICAL CHARACTERISTICS 15 8 Memory expansion mode and microprocessor mode with no Wait Switching characteristics Vcc 5 10 Vss 0 V Ta 20 to 85 C unless otherwise noted Symbol th E Poa th ALE P1A th E P1Q 12 th E P1A th ALE P2A th E P2Q 22 th E BHE th E RW Notes 1 2 Parameter Unit PotPOaddresshodtime 25 18 Port P1 address hold time BYTE L 9 9 ns Port P1 data hold time BYTE L 25 18 ns Port P1 floating release delay time BYTE 2 4 3236 1 18 C ns Port P1 address hold time BYTE H 25 18 ns PotP2addresholdtim 41 9 9 ns PotP2datahodtime o
39. lt gt P02 A2 P61 TA4IN lt gt 6 lt gt p03 As P60 TA4out lt gt 7 lt gt P04 A4 57 lt gt 8 N N lt gt 5 5 P56 TASout lt gt 9 ES lt gt P55 TA2IN lt gt lt gt P07 A7 54 200 lt gt No 9 lt gt P10 As Ds P53 TA1IN lt gt ons P11 A9 D9 P52 TA1ouT 4 gt lt gt lt lt gt P12 A10 D10 P51 TAOIN lt gt gt lt gt lt lt gt P1s A11 D11 P5o TAOoUT lt gt gt lt gt lt lt gt 14 12 012 P47 gt 16 EN G lt gt 15 1 1 46 gt 17 U 70 16 14 014 P45 lt gt 18 lt gt 17 15 015 44 lt gt 19 lt gt P20 A16 Do P43 lt gt 20 lt gt p24A17 D E Co P3o R W lt gt P27 A23 D7 gt 8 P26 A22 De lt gt P31 BHE 4 P32 ALE lt gt 8 P33 HLDA P25 A21 Ds X P24 A20 D4 _ P23 A19 D3 4 gt P22 A18 D2 lt gt Outline M37702M2L XXXGP 80P6S A Outline M37702M2LXXXHP e 80P6D A x The M37702M2LXXXGP and the M37702M2LXXXHP have the pin configuration shifted to 2 pins assignment from the M37702M2BXXXFP Fig 18 2 1 M37702M2LXXXGP and M37702M2LXXXHP pin configuration top view 18 4 7702 7703 Group User s Manual LOW VOLTAGE VERSION 18 2 Pin configuration oc PET 22485 Z Z Z Z Z Z Z EIR 4 212095
40. shown below 4 cycles b shown below 2 cycles of shown below Do not select xdi rcd eS SS Fix to 0 a ee ee Clock 1 output select bit 2 Interrupt priority level detection time 9 Op code feich cycle Sampling pulse 7 Note a 7cycles fo remit oe c 2cyces l 2 Note Pulse exists when 2 cycles of is selected Fig 4 6 1 Interrupt priority level detection time 7702 7703 Group User s Manual 4 13 INTERRUPTS 4 7 Sequence from acceptance of interrupt request to execution of interrupt routine 4 7 Sequence from acceptance of interrupt request to execution of interrupt routine The sequence from the acceptance of interrupt request to the execution of the interrupt routine is described below When an interrupt request is accepted the interrupt request bit which corresponds to the accepted interrupt is cleared to 0 and then the interrupt processing starts from the next cycle of completion of the instruction which is being executed at accepting the interrupt request Figure 4 7 1 shows the sequence from acceptance of interrupt request to execution of interrupt routine After execution of an instruction at accepting the interrupt request is completed an INTACK Interrupt Acknowledge sequence is executed and a branch is made to the start address of the interrupt routine allocated in addresses O16 to FFFF te The INTACK sequence
41. 16 4 7702 7703 Group User s Manual CHAP TIER 17 APPLICATION 17 1 Memory expansion 17 2 Sample program execution rate comparison APPLICATION 17 1 Memory expansion This chapter describes application Application shown here is just an example The user shall modify them according to the actual application and test them 17 1 Memory expansion This section shows examples for memory and I O expansion Refer to Chapter 12 CONNECTION WITH EXTERNAL DEVICES for details about the functions and operation of used pins when expanding a memory or I O Refer to Chapter 15 ELECTRICAL CHARACTERISTICS for timing requirements of the microcomputer Refer to Chapter 18 LOW VOLTAGE VERSION for timing requirements and application of the low voltage version 17 1 1 Memory expansion model Memory expansion to the external is possible in the memory expansion mode or the microprocessor mode The level of the external data bus width select signal makes it possible to select the four memory expansion models shown in Table 17 1 1 1 2 3 4 Minimum model This is an expansion model of which external data bus width is 8 biis and accessible area is expanded up to 64 Kbytes It is unnecessary to connect the address latch externally This is an expansion model having the cost priority which is suited for connecting the memory of which external data bus width is 8 bits Medium model A This is an expansion model of whic
42. 7702 7703 Group User s Manual 7 19 SERIAL I O 7 3 Clock synchronous serial I O mode UARTO transmit receive mode register Address 3016 UART1 transmit receive mode register Address 3816 b7 bO Clock synchronous serial I O mode Internal External clock select bit 0 Internal clock 1 External clock X It may be O or 1 UARTO transmit receive control register 0 Address 3416 UART1 transmit receive control register 0 Address 3C16 b7 60 D BRG count source select bits b1 b0 00 f2 0 1 f16 10 164 11 f512 CTS RTS select bit 0 CTS function selected E 1 RTS function selected d p UARTO baud rate register BRGO Address 3116 UART1 baud rate register BRG1 Address 3916 b7 00 J Set to 0016 to FF16 2 selected Necessary only when internal clock is UARTO transmit interrupt control register Address 7116 UART1 transmit interrupt control register Address 7316 b7 bO Interrupt priority level select bits When using interrupts set these bits to level 1 7 When disabling interrupts set these bits to level 0 4 6 UARTO transmit buffer register Address 3216 UART1 transmit buffer register Address 3A16 b7 bO Set transmit data here P UARTO0 transmit receive control register 1 Address 3516 hb UART1 transmit receiv
43. FEFF n t n Reload register s contents Time Fig 6 4 4 Reading timer Bi register 6 18 7702 7703 Group User s Manual TIMER B 6 5 Pulse period pulse width measurement mode 6 5 Pulse period pulse width measurement mode In these mode the timer measures an external signal s pulse period or pulse width Refer to Table 6 5 1 Figure 6 5 1 shows the structures of the timer Bi mode register and timer Bi register in the pulse period pulse width measurement mode Pulse period measurement The timer measures the pulse period of the external signal that is input to the TBi pin Pulse width measurement The timer measures the pulse width L level and H level widths of the external signal that is input to the pin Table 6 5 1 Specifications of pulse period pulse width measurement mode Item Specifications Count source f2 f16 fe4 or f512 Count operation Up count Counter value is transferred to reload register at valid edge of mea surement pulse and counting continues after clearing the counter value to 000016 Count start condition When count start bit is set to 1 Count stop condition When count start bit is cleared to 0 Interrupt request occurrence timing 6 When valid edge of measurement pulse is input Note 1 When counter overfiows overflow is set to 1 simultaneously TBIIN pin function Measurement pulse input Head from timer Bi register The value aot by
44. Fig 14 2 1 Clock generating circuit block diagram 7702 7703 Group User s Manual 14 3 CLOCK GENERATING CIRCUIT 14 2 Clock 14 2 1 Clock generated in clock generating circuit 1 9 It is the operation clock of BIU It is also the clock source of The stops by Ready request or execution of the STP or WIT instruction It is not stopped by acceptance of Hold request 2 It is the operation clock of CPU stops by the following Execution of the STP or WIT instruction Ready request L level input to RDY pin Wait request from Hold request acceptance included 3 Clock 9 It has the same period as and is output to the external from the 6 pin The clock 6 stops by execution of the STP instruction It is not stopped by Ready request or acceptance of Hold request or execution of the WIT instruction 4 f2 to 1512 Each of them is the internal peripheral devices operating clock Note Refer to each functional description for details Execution of STP instruction Chapter 10 STOP MODE Execution of WIT instruction Chapter 11 WAIT MODE Paragraph 12 3 Ready function uno XC Paragraph 12 4 Hold function 14 4 7702 7703 Group User s Manual CHAPTER 15 ELECTRICAL CHARACTERISTICS 15 4 Absolute maximum ratings 15 2 Recommended operating conditions 15 3 Electr
45. Interrupt priority level of interrupt request being retained gt Restored processor interrupt priority level IPL 4 18 7702 7703 Group User s Manual INTERRUPTS 4 9 Multiple interrupts Request Nesting Time Main routine I Interrupt 1 IPL 0 Interrupt priority level 3 Interrupt 1 Interrupt 2 IPL 3 Multiple interrupt Interrupt priority level 5 Interrupt 2 5 Interrupt 3 RTI Interrupt priority level 2 IPL 3 RTI This request cannot be accepted because its priority level is lower than interrupt 1 s meses IPL 0 lt The instruction of main routine is not executed then Interrupt disable flag IPL processor interrupt priority level L They are set automatically Set by software Fig 4 9 1 Multiple interrupt mechanism 7702 7703 Group User s Manual 4 19 INTERRUPTS 4 10 External interrupts INTi interrupt 4 10 External interrupts INTi interrupt An external interrupt request occurs by input signals to the INTi i O to 2 pin The occurrence factor of interrupt request can be selected by the level sense edge sense select bit and the polarity select bit bits 5 and 4 at addresses 7 16 to 7Fis shown in Figure 4 10 1 Table 4 10 1 lists the occurrence factor of INT interrupt request When using P62 INTo to P64 INTe pins as input pins of external interrupts set the corresponding bits at address 10 e port P6 dire
46. One shot start register Up down register Timer AO register Timer A1 register Timer A2 register Timer A3 register Timer A4 register Timer BO register Timer B1 register Timer B2 register Timer AO mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Timer BO mode register Timer B1 mode register Timer B2 mode register Processor mode register Z Z x Z Z N Z Z NZ NZ Access characteristics State immediately after a reset b7 bO b7 00 c _ wo oy wo RW RW SS as W R Taw w x RW RW L RW RW WO RW toten H V OO HW olol I 07701010 0 The access characteristics at addresses 4616 to 4F16 vary according to Timer A s operating mode Refer to Chapter 5 TIMER A The access characteristics at addresses 5016 to 5516 vary according to Timer B s operating mode Refer to Chapter 6 TIMER B The access characteristics for bit 5 at addresses 5 16 to 5016 vary according to Timer B s operating mode Refer to Chapter 6 TIMER B The access characteristics for bit 1 at address 5E16 and its state immediately after a reset vary according to the voltage level supplied to the CNVss pin Refer to section 2 5 Processor modes of SFR and internal RAM areas immediately after reset 3 7702 7703 Group User s Manual 13 7 RESET 13 1 Hardware reset Add
47. Using the PSH instruction can store all CPU registers except the stack pointer S 1 Content of stack pointer S is even Address 5 5 odd S 4 even Storing order Low order byte of processor status register PS S odd High order byte of processor status register Stores 16 bits at a time Low order byte of program counter PCL High order byte of program counter PC Program bank register 2 Stores 16 bits at a time CD Storing is completed with 3 times 2 Content of stack pointer S is odd Address 5 5 even Storing order 81 4 ed 6 8 3 even 5 S 2 odd o Stores by each 8 bits SI t oven o S odd 0 Program bank register PG Storing is completed with 5 times S is initial value that the stack pointer S indicates at accepting an interrupt request S s contents become S 5 after storing the above registers Fig 4 7 3 Register storing operation 7702 7703 Group User s Manual 4 17 INTERRUPTS 4 8 Return from interrupt routine 4 9 Multiple interrupts 4 8 Return from interrupt routine When the RTI instruction is executed at the end of the interrupt routine the contents of the program bank register PG program counter PC and processor status register PS immediately before performing the INTACK sequence which were saved to the stack area are automatically rest
48. VoL 0 8 V 2 0 Input timing voltage 2 5V Output timing voltage 7702 7703 Group User s Manual ELECTRICAL CHARACTERISTICS 15 10 Testing circuit for ports PO to P8 E 15 10 Testing circuit for ports PO to P8 1 and E Fig 15 10 1 Testing circuit for ports PO to P8 0 1 and E 7702 7703 Group User s Manual 15 25 ELECTRICAL CHARACTERISTICS 15 10 Testing circuit for ports PO to P8 1 and E MEMORANDUM 15 26 7702 7703 Group User s Manual CHAPTER 16 STANDARD CHARACTERISTICS 16 1 Standard characteristics STANDARD CHARACTERISTICS 16 1 Standard characteristics 16 1 Standard characteristics The data described below are characteristic examples for M37702M2BXXXFP The data is not guaranteed value Refer to Chapter 15 ELECTRICAL CHARACTERISTICS for rated value 16 1 1 Port standard characteristics 1 Programmable I O port CMOS output P channel lou Vou characteristics Power source voltage Vcc 5 V P channel 50 0 40 0 30 0 mA 20 0 10 0 0 1 0 2 0 3 0 4 0 5 0 N 2 Programmable I O port CMOS output channel lo Vo characteristics Power source voltage Vc c 5 V N channel 50 0 40 0 30 0 IOL mA 20 0 0 1 0 2 0 3 0 4 0 5 0 VoL V 16 2 7702 7703 Gr
49. aD 19 2 19 2 EPROM 2 amh aua 19 4 19 4 yp 19 5 we E 19 6 a A E EE 19 9 EE 19 10 X 19 11 YK W u u u uuu 19 12 19 15 19 16 19 17 19 18 19 18 19 18 19 5 9 Precautions on EPROM VeESIOD ctis 19 18 19 5 4 Bus timing EPROM 19 19 20 2 aI 20 3 20 4 20 4 Functional 20 5 T 20 6 r T 2 lili EE 20 7 20 43 Umer 20 7 20 8 20 4 5 A D CoOnverIer u 20 10 Table of Contents 20 6 1 EPROM APPENDIX Appendix 1 Memory assignment
50. the watchdog timer interrupt request occurs 2 When the program runaway occurs values of the data bank register DT and direct page register DPR may be changed When 1 is written to the software reset bit by the addressing mode using DT and DPR set values to DT and DPR again Fig 9 2 1 Example of program runaway detection by Watchdog timer 9 6 7702 7703 Group User s Manual WATCHDOG TIMER 9 2 Operation description 9 2 2 Operation in Stop mode In Stop mode Watchdog timer stops operating Immediately after Stop mode is terminated Watchdog timer operates as follows 1 2 When Stop mode is terminated by a hardware reset Supply of the and starts immediately after Stop mode is terminated and the microcomputer performs the operation after a reset Refer to Chapter 13 RESET The watchdog timer frequency select bit becomes 0 and Watchdog timer starts counting of fsi2 from FFF46 When Stop mode is terminated by an interrupt request occurrence Immediately after the stop mode is terminated Watchdog timer starts counting of the count source fso from FFF e Supply of the and cru starts when the Watchdog timer s most significant bit becomes 0 At this time the watchdog timer interrupt request does not occur Supply of the ceu starts immediately after Stop mode is terminated and the microcomputer executes the routine of the interrupt which is used to terminate Stop mode Watchdog
51. 1 4 Block diagram 1 4 Block diagram Figure 1 4 1 shows the M37702 block diagram External data bus width selection input BYTE Incrementer 24 OV AVss CNVss OV Vss f Vcc Reset input RESET Accumulator B 16 Enable output E e Clock output XOUT Arithmetic Logic Unit 16 5 O c lt Clock input XIN e Data Buffer DBH 8 in Data Buffer DBL 8 5 E Instruction Queue Buffer Qo 8 Cof gt Tii I LN 28 Instruction Queue Buffer Q1 8 ms m r o Instruction Queue Buffer Q2 8 9 I O mas lt Program Address Register PA 24 Data Address Register DA 24 Incrementer Decrementer 24 Program Counter PC 16 Program Bank Register Data Bank Register DT 8 Input Buffer Register IB 16 Processor Status Register PS 11 Direct Page Register DPR 16 Stack Pointer S 16 Index Register Y 16 Index Register X 16 Accumulator 16 Bus Interface Unit BIU Central Processing Unit CPU 16 lt E Data Bus Even E ta 16 Timer TA3 51 E 16 Timer Data Timer TB1 16 16 Timer TA1
52. 16 00C00016 Internal Internal ROM area ROM area OOFFFF16 01000016 UO an mms gt 52 7 XR W 66 SSS ee p gt XN gt 2 Q QO 52 0000000096 gt X 2 lt 5 900000 gt lt n 22050 220 oe x FFFFFFi6 5 E External area Accessing this area make it possible to access external connected devices Notes 1 Addresses 216 to 91s become a external area in the memory expansion mode and microprocessor mode 2 Refer to Appendix 1 Memory assignment for products other than M37702M2BXXXFP Fig 2 5 1 Memory assignment in each processor mode for M37702M2BXXXFP 7702 7703 Group User s Manual 2 21 CENTRAL PROCESSING UNIT CPU 2 5 Processor modes 2 5 1 Single chip mode Use this mode when not using external devices In this mode ports PO to P8 function as programmable I O ports when using an internal peripheral device they function as its pins In the single chip mode only the internal area SFH internal RAM and internal ROM can be accessed 2 5 2 Memory expansion and microprocessor modes Use these modes when connecting devices externally In these modes an external device can be connected to any required location in the 16 Mbyte access space For access to external devices refer to Chapter 12 CONNECTION WITH EXTERNAL DEVICES The memory expansion and microprocessor modes have the same funct
53. 32 teu lt 7 lt 15 max External memory J f oo data output lt Wd gt gt T isu P1D P2D E gt 30 lt When writing gt 170 min z C Xd 22 min KW gt As Ds A15 D15 DiD XK gt 30 lt 23 min 45 max S lt gt AC573 tPHL AC04 K S lt gt AC3 lt 32 WE WO Nf Unit ns Fig 17 1 20 Timing diagram for ROM and SRAM expansion example maximum model 7702 7703 Group User s Manual 17 25 APPLICATION 17 1 Memory expansion 17 1 5 Example of I O expansion 1 17 26 Example of port expansion circuit using M66010FP Figure 17 1 21 shows an example of a port expansion circuit using the M60010FP Use 1 923 MHz or less frequency for Serial I O transfer clock Serial control in this expansion example is described below In this example 8 bit data transmission reception is performed 3 times by using UARTO and 24 bit port expansion is realized Setting of UARTO is described below Clock synchronous serial I O mode Transmission Reception enable state Selected internal clock Transfer clock frequency of 1 5625 MHz LSB first The control procedure is described below Output L level from port P4s Expansion I O ports of M66010FP become floating state by this signal Outpu
54. Addresses 4716 4616 Addresses 4916 4816 w mum i PWM mode 21 24 lt When operating as an 8 bit pulse width modulator gt 615 08 b7 b0 b7 15 to 0 These bits can be set to 000016 to FFFE16 Assuming that the set value n the H el width of the PWM pulse output from the n is expressed as follows fi Frequency of count source f2 fie fe4 Or f512 Timer AO register Addresses 4716 46 6 Timer A1 register Addresses 4916 48 6 Timer A2 register Addresses 4 16 4A 6 Timer register Addresses 4D e 4C 6 Timer A4 register Addresses 4F e 4E16 7 to 0 These bits can be set to 0016 to FF e Assuming that the set value m PWM pulse s period output from the TAiour pin is m 1 28 1 fi expressed as follows 15 to 8 These bits can be set to 0016 to FE e Assuming that the set value n the level width of the PWM pulse output from the TAiour is expressed as follows n m 1 fi fi Frequency of count source f2 fis or f512 7702 7703 Group User s Manual Undefined Undefined APPENDIX Appendix 3 Control registers Timer Bi register b15 b7 bO b0 Timer BO register Addresses 5116 5016 Timer 81 register Addresses 531e 521e Timer B2 register Addresses 5516 5416 to 01 These bits have different functions a Undefined
55. External trigger input in one shot pulse mode External trigger input in pulse width modulation mode tc TA lt m tw TAH gt TAiiN input Up down input count input in event counter mode tc UP tw UPH gt TAiour input Up down input TAiour input Up down input TAIN input Selecting falling count th Tin UP 2 lsu UP Tw TAIN input Selecting rising count I wo phase pulse input in event counter mode tc TA TAJN input lsu TAjiN TAjour lsu TAjiN TAjour lt gt lt lt gt TAjour TAj TAjour Input tsu TAjout TAjin lt gt tsu TAjout TAjin Test conditions e Vcc 2 7 5 5 e Input timing voltage Vi 0 2 V Viu 0 8 V 18 14 7702 7703 Group User s Manual LOW VOLTAGE VERSION 18 4 Electrical characteristics Timer B input count input in event counter mode tme TBiwinputcycletime edge 8 tre input high level pulse width one edge count 125 ns twee input low level pulse width one edge count 125 X ns tre TBiwinputcycletime both edges count 500 trem input high level pulse width both edges count 7 1 2350 ns twret I TBiw input low level pulse width both edges count 250 ns Timer B input pulse period measurement mode Symbol rEg Note TBis input cycle time must be 4 cycles or more of c
56. Figure 2 1 4 shows a setting example of the direct page area Addressing modes using direct page register eDirect eDirect bit eDirect indexed X eDirect indexed Y eDirect indirect eDirect indexed X indirect eDirect indirect indexed Y eDirect indirect long eDirect indirect long indexed Y eDirect bit relative 2 6 7702 7703 Group User s Manual CENTRAL Bank 016 FFFF16 ll 1000016 Bank 116 PROCESSING UNIT CPU 2 1 Central processing unit Direct page area when DPR 000016 Direct page area when DPR 012316 Note 1 FF1016 Direct page area when DPR FF1016 1000 16 ele 2 Notes 1 The number of cycles required to generate an address is 1 cycle smaller when the low order 8 bits of the DPR are 0016 2 The direct page area spans the space across banks O16 and 116 when the DPR is FF0116 or more Fig 2 1 4 Setting example of direct page area 7702 7703 Group User s Manual 2 7 CENTRAL PROCESSING UNIT CPU 2 1 Central processing unit 2 1 9 Processor status register PS The processor status register is an 11 bit register Figure 2 1 5 shows the structure of the processor status register 015 014 013 612 611 010 b9 b8 b7 06 bd b4 b3 02 bl n staus m e d Note 0 is always read from each of bits 15 11 Fig 2 1 5 Processor status register structure 1 Bit 0 Carry flag C It retains a carry or a borrow generated in the arithmetic an
57. Ll j s 518 e om posce me we 5 F 58 LI RI NEN _ 3E pn Ep ae HH 52 89122 13 bd lx um i PLI i asl 23 4 7702 7703 Group User s Manual 21 63 APPENDIX Appendix 8 Machine instructions Symbol PLE 21 64 S Function 5 5 1 5 5 1 MISIT X4 5 5 MUS XL gge x MS X 5 5 1 x M S Y amp 5 5 1 MS Y 8 5 1 5 5 1 mzx 5 S 1 AL 5 5 S 1 M15 m 1 8 5 1 m 5 5 T1 B MS 541 MER m 554 1 5 S 1 5 55 1 DFR M15 55 1 PS 55 11 PS4 Mi3 MS DPR Addressing mode Details stack Saves the contents ol the program bank register into the Saves na contants of the diract page register into the Stack Saves the contents of the program slaive register into the Stack Saves tha contenia of the daia bank register into the mn stack Savas the contenis d the indax register i SR dns sick ono III ud aia t dii B WI Restores th contents of ihe stack on the diract page reg ister Restores Ehe contents of the stack on the
58. PO0 40 45 5 57 7 ME P8o P87 Xin RESET CNVss Low level input voltage P1o P17 20 27 0 02 in single chip mode Low level input voltage P1o P17 P20 P27 memory expansion mode and 2 V microprocessor mode High level peak output current POo P07 P1o P 17 P2o P27 loH peak 3 4 4 P5o P57 P60 P67 P7o P77 P80 P87 High level average output current POQo P07 P10 P17 20 25 loH avg P4o P47 P5o P57 P60 P67 P7o P77 P80 P87 Low level peak output current P0o P07 1 17 P20 P 27 loL peak 3 P40 P43 P5o P57 P60 P67 P7o P77 P80 P87 Low level average output current POo P07 P1o P17 2 2 loL avg 3 P4o P435 P54 P57 5 mA P60 P67 P7o P77 P80 P87 External clock input frequency M37702M2BXXXFP 25 wi ee Notes 1 Average output current is the average value of a 100 ms interval 2 The sum of lo peak for ports PO P1 P2 and P8 must be 80 mA or less the sum of for ports PO P1 P2 and P8 must be 80 mA or less the sum of lo peak for ports P4 P6 and P7 must be 80 mA or less and the sum of for ports P4 P5 P6 and P7 must be 80 mA or less 7702 7703 Group User s Manual 15 3 ELECTRICAL CHARACTERISTICS 15
59. lt 25 MHz Parameter th E P1Q 1X10 1 X 10 1 X 10 20 2 2 2 Table 17 1 6 Constants of 1 2 unit ns Microcomputer type 16 MHz version 25 MHz version Parameter td E P1Q td E P2Q 17 10 7702 7703 Group User s Manual APPLICATION 17 1 Memory expansion 3 Precautions on memory expansion As described to below if specifications of the external memory do not match those of the M37702 some considerations must be incorporated into circuit design as in the following cases When using an external memory that requires a long access time tap When using an external memory that outputs data within 2 22 after the falling edge of the E signal When using an external memory that outputs data for more than 2 22 after the rising edge of the E signal When using external memory that requires long access time taan If the M37702 s tsuPip P2o e cannot be satisfied because the external memory requires a long access time taan examine the method described below Lower Select software Wait Refer to section 12 2 Software Wait Use Ready function Refer to section 12 3 Ready function Figure 17 1 8 shows an example of a Ready signal generating circuit no Wait Figure 17 1 9 shows an example of a Ready signal generating circuit with Wait Ready function is valid for the internal
60. to this bit The value is at reading 55 04 0 0 7 cycles of 0 1 4 cycles of 2 cycles of Not selected 6 Fix this bit to 0 o RW Clock 1 Output select bit 0 Clock o 1 output disabled RW Note 2 P42 functions as a programmable I O port 1 Clock 1 output enabled P42 functions as a clock out put pin Notes 1 While supplying the Vcc level to the CNVss pin bit 1 becomes 1 after a reset Fixed to 1 2 Bit 7 is ignored in the microprocessor mode It may be either 0 or 1 Interrupt priority detection time select bits Bits 3 to 6 are not used when accessing the external area Fig 12 2 1 Structure of processor mode register 7702 7703 Group User s Manual 12 11 CONNECTION WITH EXTERNAL DEVICES 12 2 Software Wait No Wait 1 bus cycle Clock 1 E ALE Ao Ar N ote As Ds A15 D15 A16 Do A23 D7 areas are always accessed in this waveform Wait 1 bus cycle Clock 6 1 E ALE ote As Ds A15 D15 A16 D0 A23 D7 Note When the external data bus is 8 bits width BYTE As Ds to A15 D15 operate with the same bus timing as Ao to Fig 12 2 2 Example of bus timing when software Wait is used BYTE L 12 12 7702 7703 Group User s Manual CONNECTION WITH EXTERNAL DEVICES 12 3 Ready function 12 3 Ready
61. 11 4 7702 7703 Group User s Manual WAIT MODE 11 3 Precautions for Wait mode 11 3 Precautions for Wait mode When executing the WIT instruction after writing to the internal area or an external area the three NOP instructions must be inserted to complete the write operation before the WIT instruction is executed STA A XXXX Writing instruction NOP gt NOP instruction insertion NOP NOP WIT WIT instruction Fig 11 3 1 NOP instruction insertion example 7702 7703 Group User s Manual 11 5 WAIT MODE 11 3 Precautions for Wait mode MEMORANDUM 11 6 7702 7703 Group User s Manual CHAP TIER 12 CONNECTION WITH EXTERNAL DEVICES 12 1 Signals required for accessing external devices 12 2 Software Wait 12 3 Ready function 12 4 Hold function CONNECTION WITH EXTERNAL DEVICES 12 1 Signals required for accessing external devices This chapter describes functions to connect devices externally 12 1 Signals required for accessing external devices The functions and operation of the signals which are required for accessing external devices are described below When connecting an external device that requires a long access time refer to sections 12 2 Software Wait 12 3 Ready function and 12 4 Hold function as well as this section 12 1 1 Descriptions of signals When an external device is connected operate the microcomputer in the memory expansion or microprocessor mode
62. A ABL X EOR LSR EOR EOR LSR JMP EOR LSR EOR RTI MVP PHA PHG ADIR X A SR ADIR DIR AL DIR A IMM A ABS ABS AABL EOR EOR EOR EOR LSR EOR EOR JMP EOR LSR EOR BVC MVN CLI PHY TAD A DIR YIA DIR A SR Y A DIR X DIR X lAL DIR A ABS Y ABL 5 ABS X lA ABL X ADC ADC LDM ADC ROR ADC ADC JMP ADC ROR ADC RTS PLA RTL A DIR X ASR DIR ADIR DIR AL DIR AIMM A 5 ABS A ABL ADC ADC ADC LOM ADC ROR ADC ADC JMP ADC ROR ADC 7 BVS PLY TDA A DIR YIA DIR IA SR Y DIR X A DIR X DIR X 5 5 5 ABS X A ABL X BRA STA BRA STA STY STA STX STA STY STA STX STA DEY TXA PHT REL A DIRX REL ASR DIR ADIR DIRAJA LIDIR ABS 5 ABS A ABL STA STA STA STY STA STX STA STA LDM STA LOM STA BCC TYA TXS TXY A DIR YIA DIR A SR Y DIR X JA DIR X DIR Y j AL DIR A ABS Y ABS lA ABS X ABS X A ABL X LDY LDA LDX LDA LDY LDA LOX LDA LDA LDY LDA LDX LDA A TAY TAX PLT IMM A DIRX IMM ASR DIR DIR AL OIR AIMM aes A BS ABS A ABL LDA LDA LDA LDY LDX LDA LDA LDX LDA TYX A DIR Y A DIR JA SR Y DIRX A DIR X DIR Y AL DIR 5 ABS X 5 ABS Y A ABL X GPY DEC WIT JA DIR X AM
63. ANe selected AN selected Note 2 A D operation mode select bits 0 0 One shot mode 0 1 Repeat mode 1 0 Single sweep mode 1 Repeat sweep mode Trigger select bit Internal trigger External trigger A D conversion start bit Stop A D conversion Start A D conversion 7 A D conversion frequency f2 divided by 4 AD select bit divided by 2 Notes 1 These bits are ignored in the Gs sweep and repeat sweep mode They may be either 0 or 1 2 When selecting an external trigger the AN7 pin cannot be used as an analog input pin 3 Writing to each bit except bit 6 of the A D control register must be performed while the A D converter halts 7702 7703 Group User s Manual 21 13 APPENDIX Appendix 3 Control registers A D sweep pin select register 67 b6 b5 04 b3 02 bl b0 A D sweep pin select register Address 1F 16 A D sweep pin select bits b1 bO 1 RW E Valid in single sweep and repeat 0 0 ANo AN 2 pins IL sweep mode Note 1 0 1 ANo to ANs 4 pins 1 0 ANo to ANs 6 pins 1 1 ANo to AN 8 pins Note 2 Nothing is assigned Notes 1 These bits are invalid in the one shot and repeat modes They may be either 0 or 2 When selecting an external trigger the AN7 pin cannot used as an analog input 3 Writing to each bit of the A D sweep pin select register must be performed while the A D converter halts A D register i D regi
64. Address External address bus HOLD 0 1 X 1 HLDA b Hold state Term unusing bus Term using bus D This is the term in which the bus is not used so that not a new address but an address output just before is output again Clock 6 1 has the same polarity and the same frequency as 6 Signals timing to be input or output externally is ordained by clock 1 as a basis Fig 12 4 2 Timing of acceptance of Hold request and termination of Hold state 1 12 18 7702 7703 Group User s Manual CONNECTION WITH EXTERNAL DEVICES 12 4 Hold function lt When inputting L level to HOLD pin during term using bus when data access is completed with 1 bus cycle gt State when inputting L level to HOLD pin External data bus Data length External data bus width Using 6 Access from even address Judgment timing of input levelto HOLD pin l l l l l Clock 6 T T T ALE E Floati OGIO wa External address bus BHE HOLD o1X 1 HLDA T D Term using bus Hold state Term using bus lt When accepting a Hold request not a new address but an address output just before is output again Notes 1 This figure shows the case of no Wait 2 Clock 1 has the same polarity and the same frequency
65. Fig 4 4 1 Interrupt priority levels set by hardware 4 10 7702 7703 Group User s Manual INTERRUPTS 4 5 Interrupt priority level detection circuit 4 5 Interrupt priority level detection circuit The interrupt priority level detection circuit selects the interrupt having the highest priority level when more than one interrupt request occurs at the same sampling timing Figure 4 5 1 shows the interrupt priority level detection circuit Level 0 initial value Interrupt priority level Interrupt priority level q UART1 transmit Timer A3 lt lt lt lt lt lt lt lt UART1 receive Timer A2 Timer A1 Timer AO UARTO receive INT2 UARTO transmit INT lt lt lt lt lt IPL The highest priority level interrupt Processor interrupt priority level Interrupt e gt disable flag 1 Watchdog timer interrupt gt Accepting of interrupt request Reset Fig 4 5 1 Interrupt priority level detection circuit 7702 7703 Group User s Manual 4 1 1 INTERRUPTS 4 5 Interrupt priority level detection circuit The following explains the operation of the interrupt priority detection circuit using Figure 4 5 2 The interrupt priority level of a requested interrupt Y in Figure 4 5 2 is compared with the resultant priority level sent from the preceding comparator X in Figure 4 5 2 whichever interrupt of the higher priority level is sent to the next comparator Z in Figure
66. P5 I O pins of Timer P6o P6 P62 to P64 Input pins of external interrupts P65 to P67 Input pins of Timer B P7 Input pins of A D converter P8 I O pins of Serial 3 8 7702 7703 Group User s Manual CHAPTER 4 INTERRUPTS 4 1 Overview 4 2 Interrupt sources 4 3 Interrupt control 4 4 Interrupt priority level 4 5 Interrupt priority level detection circuit 4 6 Interrupt priority level detection time 4 7 Sequence from acceptance of interrupt request to execution of interrupt routine 4 8 Return from interrupt routine 4 9 Multiple interrupts 4 10 External interrupts INT interrupt 4 11 Precautions when using interrupts INTERRUPTS 4 1 Overview The suspension of the current operation in order to perform another operation owing to a certain factor is referred to as Interrupt This chapter describes the interrupts 4 1 Overview The M37702 has 19 interrupt sources to generate interrupt requests Figure 4 1 1 shows the interrupt processing sequence When an interrupt request is accepted a branch is made to the start address of the interrupt routine set in the interrupt vector table addresses FFD6 e to FFFF e Set the start address of each interrupt routine at each interrupt vector address in the interrupt vector table Interrupt routine Process interrupt RTI instruction Fig 4 1 1 Interrupt processing sequence 4 2 7702 7703 Group User s Manual INTERRUPTS 4 1 Overview When
67. Parameter Note For test conditions refer to Figure 15 10 1 7702 7703 Group User s Manual Unit ns ns ns ns ns ns ns ns ns 15 15 ELECTRICAL CHARACTERISTICS 15 7 Single chip mode Single chip mode m Port PO output Port PO input Port P1 output Port P1 input Port P2 output Port P2 input Port P3 output Port P3 input Port P4 output Port P4 input Port P5 output Port P5 input Port P6 output Port P6 input Port P7 output Port P7 input Port P8 output Port P8 input Test conditions 5 V 10 Input timing voltage Output timing voltage 15 16 tr tc tw H tw L tsu POD E 10 lt gt td E P2Q tsu P2D E th E P2D isu P3D E lt gt tsu P4D E 50 tsu P6D E tsu P7D E lt gt tsu P8D E lt gt 1 0 V VH 4 0 V VoL 0 8 V Vor 2 0 V 7702 7703 Group User s Manual ELECTRICAL CHARACTERISTICS 15 8 Memory expansion mode and microprocessor mode with no Wait 15 8 Memory expansion mode and microprocessor mode with no Wait Timing requirements Vcc 5 10 Vss 0 V Ta 20 to 85 C unless otherwise noted Symbol Parameter Unit t 62 4 ns External clock input high level pulse width 22 15 ns T External clock input low level pulsewi
68. Sample program After an instruction which writes 0002 to the interrupt priority level select bits fill the instruc tion queue buffer with the NOP instruction to make the next instruction not be executed before the writing is completed CLB 07H XXXIC Sets the interrupt priority level select bits to 0002 NOP NOP NOP LDA A DATA Instruction at the beginning of the routine that should not accept a certain interrupt request 21 48 7702 7703 Group User s Manual APPENDIX Appendix 6 Q amp A Interrupt 1 Which timing of clock is the external interrupts input signals to the pin detected 2 How can four or more external interrupt input pins INTi be used 1 In both the edge sense and level sense external interrupt requests occur when the input signal to the pin changes its level regardless of clock In the edge sense the interrupt request bit is set to 1 at this time 2 There are two methods one uses external interrupt s level sense and the other uses the timer s event counter mode Using external interrupt s level sense In hardware input a logical sum of multiple interrupt signals e g b and c to the pin and input each signal to each corresponding port In software check the ports input levels in the INTi interrupt routine to determine that which of the signals a b and c is input M37702 Using
69. The M37702M2BXXXFP See Note assigns the 512 byte static RAM at addresses 80 e to 27F e The internal RAM area is used as a stack area as well as an area to siore data Accordingly note that set the nesting depth of a subroutine and multiple interrupts level not to destroy the necessary data Internal ROM area The M37702M2BXXXFP See Note assigns the 16 Kbyte mask RAM at addresses 000 6 to FFFF e Its addresses FFD6 e to FFFF e are the vector addresses which are called the interrupt vector table for reset and interrupts In the microprocessor mode and the external ROM version where use of the internal ROM area is inhibited assign a ROM ai addresses FFD6 e to FFFF e Note Refer to Appendix 1 Memory assignment for other products 7702 7703 Group User s Manual CENTRAL PROCESSING UNIT CPU 2 4 Memory assignment M37702M2BXXXFP 00000016 gt Refer to Figure 2 4 2 00007 16 00008016 Internal RAM area 00027 16 552555 090002020 SOX Interrupt vector table 0066060606606 FFD616 A D conversion I 00 0001 i P FFD8te UART1 transmit FFDAt6 UART recieve FFDCte UARTO transmit FFDE16 UARTO recieve 5 FFEOt6 FFEZi TimerB1 R FE4 Timer BO RB Internal ROM area indi i T Timer A1 L H L 1 16 r FFF016 1 FFF216 FFF416 FFF616 FFF816 Timer AO z N 2 zi SEI mrs 2 r o OOFFED6i6 Watchd
70. This signal becomes L level while reading or writing data to and from the data bus See Table 12 1 2 4 Read Write signal R W This signal indicates the state of the data bus This signal becomes L level while writing to the data bus Table 12 1 2 lists the state of the data bus indicated with the E and R W signals Table 12 1 2 State o data bus indicated with E and R W signals E State of data bus H Not used L Read data Write data 5 Byte high enable signal BHE This signal indicates the access to an odd address This signal becomes L level when accessing an only odd address or when simultaneously accessing odd and even addresses This signal is used to connect memories or devices of which data bus width is 8 bits when the external data bus width is 16 bits Table 12 1 3 lists levels of the external address bus Ao and the BHE signal and access addresses Table 12 1 3 Levels of Ao and BHE signal and access addresses Access address Even and odd addresses Even address Odd address Simultaneous 2 byte access 1 byte access 1 byte access Ac H BHE H L 6 Address latch enable signal ALE This signal is used to obtain the address from the multiplexed signal of address and data that is input and output to and from the As De to 5 0 5 and 0 to Azs D7 pins Make sure that when this signal is H latch the address and simultaneously output the addresses When this signal is L retain the
71. Timer Ai i 0 to 4 has four operating modes listed below Except for the event counter mode Timers AO to A4 all have the same functions Timer mode The timer counts an internally generated count source Following functions can be used in this mode Gate function Pulse output function Event counter mode The timer counts an external signal Following functions can be used in this mode Pulse output function wo phase pulse signal processing function Timers 2 A3 and 4 One shot pulse mode The timer outputs a pulse which has an arbitrary width once Pulse width modulation PWM mode Timer outputs pulses which have an arbitrary width in succession The timer functions as which pulse width modulator as follows 16 bit pulse width modulator 8 bit pulse width modulator 5 2 7702 7703 Group User s Manual TIMER A 5 2 Block description 5 2 Block description Figure 5 2 1 shows the block diagram of Timer A Explanation of relevant registers to Timer A is described below However for the following registers refer to the relevant section Up down register address 4416 5 4 2 Operation in event counter mode One shot start register address 42 6 5 5 3 Trigger Count source Data bus odd select bits 16 5 b Data bus even f 64 Low order 8 bits High order 8 bits Timer mode Timer Ai reload register 16 One shot pu
72. clock output disabled and perform the same processing as ports P4s P 47 P 5 P8 8 When processing unused pins use the possible shortest wiring within 20 mm from the microcomputer G N When setting ports for input mode When setting ports for output mode P42 P47 8 4 gt 4 P5 P8 Left open Left open Left open Left open Left open Voc V e Y Fig 1 3 2 Example for processing unused pins in memory expansion mode 1 10 7702 7703 Group User s Manual DESCRIPTION 1 3 Pin description 3 In microprocessor mode Table 1 3 6 Example for processing unused pins in microprocessor mode Pin name Example of processing Ports P43 to P47 P5 to P8 Set for input mode and connect these pins to Vcc or Vss via a resistor or set for output mode and leave these pins open Notes 1 6 BHE Note 2 Leave it open Note 4 ALE Note 3 Note 6 Xour Note 5 Leave it open HOLD RDY Note 7 Connect these pins to Vcc via a resistor pull up AVcc Connect this pin to Vcc AVss Vrer Connect these pins to Vss Notes 1 N When setting these ports to the output mode and leave them open they remain set to the input mode until they are switched to the output mode by software after reset While ports remain set to the input mode consequently voltage levels of pins are unstable and a power source current can increase The contents
73. gt lt gt lt gt n n n n n n ic 60 P86 RxD1 lt gt P87 TxD1 lt P01 A1 lt gt P02 A2 OD 255 lt 4 lt gt 4 N lt gt P05 A5 M lt gt Z lt lt P07 A7 T gt 10 UJ lt P11 A9 D9 gt lt 12 10 10 gt lt P13 A11 D11 gt 14 12 012 15 1 1 U lt gt P16 A14 D14 gt P17 A15 D15 lt gt P2o A1e Do lt P21 A17 D1 FE P3o R W P27 A23 D7 lt gt amp P31 BHE 4 P32 ALE lt gt R _ lt Q L Co Outline 80P6D A P26 A22 De gt 25 21 05 gt Si he M37702M2BXXXHP have the pin configuration shifted to 2 pins assignment from the M37702M2BXXXFP Fig 1 2 2 M37702M2BXXXHP pin con figuration top view 7702 7703 Group User s Manual DESCRIPTION 1 3 Pin description 1 3 Pin description Tables 1 3 1 to 1 3 3 list the pin description However the pin description in the EPROM mode of the built in PROM version is described to section 19 2 EPROM mode 7703 Group The 7703 Group does not have part of pins Refer to Chapter 20 7703 GROUP Table 1 3 1 Pin description 1 Pin Vcc Vss CNVss RESET XIN Xour E BYTE AVcc AVss VREF Clock pe mE output Output Enable output Output Bus width selection Input input
74. hardware reset Except the case that Stop or Wait mode is Undefined software reset Retaining the state immediately before reset terminating Stop or Wait mode Hardware reset is used to terminate it Retaining the state immediately before the STP or WIT instruction is executed Fig 13 1 6 State of SFR and internal RAM areas immediately after reset 4 13 8 7702 7703 Group User s Manual RESET 13 1 Hardware reset 13 1 3 Internal processing sequence after reset Figure 13 1 7 shows the internal processing sequence after reset 1 Single chip and Memory expansion modes 6 TLE LE LLL LLL Kuma m DN NN AHAL X 000016 X x ADu ADL x DATA P4 x gt used Not used X Not used K AD RECTA IPL reset vector address RW U 2 Microprocessor mode LI LI LI Le peru LI Liaw B pL Ap X 0016 x AHAL X 000016 X FFFEt6 X AD x DATA x y Not used Not used Not used X ADu ADL x IPL reset vector address E x yp R W AHAL Low order 16 bits address bus of CPU DATA CPU data bus ADH ADL Contents of r
75. latched address 7 Ready function related signal RDY This is the signal to use the Ready function Refer to section 12 3 Ready function 8 Hold function related signals HOLD HLDA These are the signals to use the Hold function Refer to section 12 4 Hold function 12 6 7702 7703 Group User s Manual CONNECTION WITH EXTERNAL DEVICES 12 1 Signals required for accessing external devices 9 Clock This signal has the same period as 0 In the memory expansion mode this signal is output externally by setting the clock output select bit bit 7 at address 5E e to 1 Figure 12 1 3 shows the output start timing of clock In the microprocessor mode this signal is always output externally Note Even in the single chip mode the clock can be output externally This signal is output externally by setting the clock output select bit to 1 just as in the memory expansion mode Writing 1 to clock 1 output select bit j4 x Clock 1 42 Notes 1 The 1st cycle of clock 9 1 may be shortened indicated by 2 This applies when writing to clock 1 output select bit while P42 pin is outputting L level Fig 12 1 3 Output start timing of clock b7 06 b5 b4 b3 b2 bl Processor mode register Address 5 16 a Single chip mode Memory expansion mode Microprocessor mode Not selected 0 Software Wai
76. lt gt P31 BHE lt P32 ALE lt gt 26 22 06 lt 3 P25 Az1 Ds lt gt 3 P24 A20 D4 lt 5 PAo HOLD lt Outline 80P6N A Fig 1 2 1 M37702M2BXXXFP pin configuration top view 7702 7703 Group User s Manual O gt 4 Od I I p I Gl Al IO Ory Gay ony G RE OP OL NE Cop coli SI Ny 5 ete eee eee P84 CTS1 RTS1 P85 CLK1 P86 RxD1 P87 TxD1 POo Ao 1 1 2 2 P04 A4 5 5 P0e Ae PO7 A7 P10 As Ds P11 A9 Do P12 A10 D10 P13 A11 D11 P14 A12 D12 P15 A13 D13 P16 A14 D14 P17 A15 D15 P20o A16 Do P21 A17 D1 P22 A18 D2 P23 A19 D3 DESCRIPTION 1 2 Pin configuration gt lt gt P67 TB2IN a lt P7o ANO lt 71 1 u lt P72 AN2 a lt P73 AN3 P6e TB1IN lt gt P65 TBOIN lt gt P64 INT2 lt gt P63 INT1 lt gt P62 INTo lt gt P61 TA4IN 16 P6o TA40UT lt gt 57 lt 8 P56 TA3ouT 19 P55 TA2IN lt gt P54 TA20uT lt gt P53 TA1IN lt gt P52 TAlour lt gt P51 TAOIN lt gt P5o TAOoUT lt gt P47 lt gt 46 lt gt P45 lt gt P44 lt gt P43 lt gt O lt So sess 2 x Q Q x lt lt lt 22 gt o
77. request which should not be accepted are met immediately before executing the instruction which is in that buffer When writing to a memory the CPU passes the address and data to the BIU Then the CPU executes the next instruction in the instruction queue buffer while the BIU is writing data into the actual address Detection of interrupt priority level is performed at the beginning of each instruc tion In the above case in the interrupt priority detection which is performed simultaneously with the execution of the next instruction the interrupt priority level before chanaing it is detected and the interrupt request is accepted It is because the CPU executes the next instruction before the BIU finishes changing the interrupt priority levels Interrupt request generated Sequence of execution Interrupt request accepted Interrupt priority detection time Previous instruction CLB instruction LDA instruction CPU operation executed executed BIU operation Instruction prefetch Interrupt priority level select bits set Change of interrupt priority levels completed 7702 7703 Group User s Manual 21 47 APPENDIX Appendix 6 Q amp A Interrupt To prevent this problem use software to execute the routine that should not accept a certain interrupt request after change of interrupt priority level is completed The following shows a sample program
78. taE Po0 Port PO data output delay ime 1 8900 ns Port P1 data output delay time o Z oO 300 ns 0 PortP2dataoutputdelay ime L O 30 ns twe psq PortP3dataoutputdelaytrme 01 300 ns PortP4dataouputdelay ime j 1300 ns lapso Port P5 data output delay time 300 ns PortP6dataoutpuidelaytime O 90 ns PortP7dataoutputdelaytime 800 ns Port P8 data output delay time 800 ns Note For test conditions refer to Figure 18 4 1 7702 7703 Group User s Manual 18 21 LOW VOLTAGE VERSION 18 4 Electrical characteristics Single chip mode tt tr tw H tw L E Nf td E P0Q Port PO output tsu POD E lt th E POD Port PO input td E P1Q Port P1 output s tsu P1D E lt lt th E P1D Port P1 input ta E P2Q Port P2 output X Isu P2D E th E P2D Port P2 input td E P3Q Port P3 output Isu PSD E lt gt lt th E P3D Port P3 input td E P4Q Port P4 output tsu P4D E lt th E P4D Port P4 input td E P5Q Port P5 output tsu P5D E lt th E P5D Port P5 input td E P6Q Port P6 output tsu P6D E lt lt th E P6D Port P6 input td E P7Q Port P7 output tsu P7D E lt gt lt th E P7D Port P7 input ta E P8Q Port P8 output tsu P8D E
79. trigger occurs Fig 8 6 1 Initial setting example of repeat mode 8 18 7702 7703 Group User s Manual A D CONVERTER 8 6 Repeat mode 8 6 2 Repeat mode operation description 1 When an internal trigger is selected The A D converter starts operation when the A D conversion start bit is set to 1 The first A D conversion is completed after 57 cycles of Then the contents of the successive approximation register conversion result are transferred to the A D register i The A D converter repeats operation until the A D conversion start bit is cleared to 0 by software The conversion result is transferred to the A D register i each time the conversion is completed 2 When an external trigger is selected The A D converter starts operation when the input level to the pin changes from to L while the A D conversion start bit is 1 The first A D conversion is completed after 57 cycles of Then the contents of the successive approximation register conversion result are transferred to the A D register i 3 The converter repeats operation until the conversion start bit is cleared to 0 by software The conversion result is transferred to the A D register i each time the conversion is completed When the level of the pin changes from to L during operation the operation at that point is cancelled and is restarted from s
80. 01 snq eujeiu snq eu4eju 19151 eioedg HJS nig yun S0eL9 UI sng Ndo yun DuisseooJud Sna cOZZEW Fig 2 2 1 Bus and bus interface unit BIU 2 11 7702 7703 Group User s Manual CENTRAL PROCESSING UNIT CPU 2 2 Bus interface unit 2 2 2 Functions of bus interface unit BIU The bus interface unit BIU consists of four registers shown in Figure 2 2 2 Table 2 2 1 lists the functions of each register Program address register Data address register Data buffer Fig 2 2 2 Register structure of bus interface unit BIU Table 2 2 1 Functions of each register Name Functions Program address register Indicates the storage address for the instruction which is next taken into the instruction queue buffer Instruction queue buffer Temporarily stores the instruction which has been taken in Data address register Indicates the address for the data which is next read from or written to Data buffer Temporarily stores the data which is read from the memory l O device by the which is written to the memory l O device by the CPU 2 12 7702 7703 Group User s Manual CENTRAL PROCESSING UNIT CPU 2 2 Bus interface unit The CPU and the bus send or receive data via BIU because each operates based on different clocks Note The BIU allows the CPU to operate at high speed without waiting for access to the memoryel O devices
81. 016 For details refer to section 2 4 Memory assignment 2 3 2 Direct page A 256 byte space specified by the direct page register DPR is called direct page A direct page is specified by setting the base address the lowest address of the area to be specified as a direct page into the direct page register DPR By using a direct page addressing mode a direct page can be accessed with less instruction cycles than otherwise Note Refer also to section 2 1 Central processing unit 7702 7703 Group User s Manual 2 17 CENTRAL PROCESSING UNIT CPU 2 4 Memory assignment 2 4 Memory assignment This section describes the internal area s memory assignment For more information about the external area refer also to section 2 5 Processor modes 2 4 1 Memory assignment in internal area SFR Special Function Register internal RAM and internal ROM are assigned in the internal area Figure 2 4 1 shows the internal area s memory assignment 1 2 3 2 18 SFR area The registers for setting internal peripheral devices are assigned at addresses O e to 7F e This area is called SFR Special Function Register Figure 2 4 2 shows the SFR area s memory assignment For each register in the SFR area refer to each functional description in this manual For the state of the SFR area immediately after a reset refer to section 13 1 2 State of CPU SFR area and internal RAM area Internal RAM area
82. 0816 P Ideal A D conversion 0716 a characteristics 0616 0516 0416 0316 0216 0116 0016 40 60 80 100 120 140 160 180 200 220 Analog input voltage mV Fig 8 4 1 Absolute accuracy of A D converter 8 12 7702 7703 Group User s Manual A D CONVERTER 8 4 Absolute accuracy and differential non linearity error 8 4 2 Differential non linearity error The differential non linearity error indicates the difference between the 1 LSB step width the ideal analog input voltage width while the same output code is expected to output of an A D converter with ideal characteristics and the actual measured step width the actual analog input voltage width while the same output code is output For example when Vrer 5 12 V the 1 LSB width of an A D converter with ideal characteristics is 20 mV however when the differential non linearity error is 1 LSB the actual measured 1 LSB width is 0 to 40 mV Refer to section 16 1 3 A D converter standard characteristics Output code A D conversion result 0916 1 LSB width with ideal 0816 A D conversion characteristics 0716 0616 0516 0416 0316 0216 0116 Differential non linearity error 0016 20 40 60 80 100 120 140 160 180 Analog input voltage mV Fig 8 4 2 Differential non linearity error 7702 7703 Group User s Manual 8 13 A D CONVERTER 8 5 One shot mode 8 5 One shot mode In the one shot mode th
83. 1016 1116 1416 m N Port Pio direction bit 0 Input mode Functions as input port Port Pi direction bit Rw 1 Output mode Port Pie direction bit Functions as an output port o RW Port Pis direction bit Port direction bit RW Port Pis direction bit RW Port Pie direction bit o RW Port direction bit o RW Notes 1 Bits 7 to 4 of the port P3 direction register cannot be written they may be either O or 1 and are fixed to 0 at reading 2 In the memory expansion mode or the microprocessor mode fix bits 0 and 1 of the port P4 direction register to 0 7703 Group Fix the following bits which do not have the corresponding pin to 1 Bit 3 of port P3 direction register Bits 3 to 6 of port P4 direction register Bits 0 1 6 and 7 of port P6 direction register Bits 3 to 6 of port P7 direction register Bits 4 and 5 of port P8 direction register ma Sir ss m m mm m e e 21 12 7702 7703 Group User s Manual APPENDIX Appendix 3 Control registers A D control register 67 06 b5 b4 b3 b2 bi b0 A D control register Address 1 16 Bt __ Biname Functions RW Analog input select bits Valid one shot and repeat selected Undefined RW modes Note 1 0 1 AN selected selected ANs selected AN4 selected Undefined RW ANs selected
84. 18 6 2 Memory expansion example on minimum model Figure 18 6 3 shows a memory expansion example on the minimum model with external RAM and Figure 18 6 4 shows the corresponding timing diagram In this example an Atmel company s EPROM AT27LV256R is used as the external ROM In Figure 18 6 3 the circuit condition is No Wait M37702S1L M5M5256CFP 10VLL Memory map 0000 16 SFR area 008016 Internal RAM area 0280 16 External RAM area M5M5256CFP 8000 16 External ROM area AT27LV256R FFFF e XIN 7 Vcc 2 3 0 3 3 V Circuit condition no Wait 221 k2 Use the elements of which propagation delay time is within 30 ns 3 Use the elements of which propagation delay time i within 50 ns Fig 18 6 3 Memory expansion example on minimum model 7702 7703 Group User s Manual 18 37 LOW VOLTAGE VERSION 18 6 Application lt When reading gt 210 min 7y 10 95 min e a 04 gt s AC32 tPHL lt gt lt gt AC32 L gt HOM 25 max RAM 30 max External memory C 5 nm data output m tsu P2D E gt 80 lt When writing gt 210 min E 50 2 50 nin _ 130 min 2 0 Cx X 5 2 tPHL lt gt tsu D gt 40 lt gt AC32 tPLH
85. 3 Electrical characteristics 15 3 Electrical characteristics Electrical characteristics Vcc 5 V Vss 0 V 20 to 85 C unless otherwise o oo High level output voltage 0 0 P1o P17 20 27 P30 P31 P33 P4o P47 P50 P5r P r P6r 7 7 082 710 MA P80 P87 V Vo High level output voltage 0 0 1 1 P2c P2 400 LA 47 V P30 P31 P3 vo High level output voltage lon 10 mA 31 V 400 uA 48 Jo High level output voltage E 400 WA 4 A48 V Low level output voltage P0o P0 P1o P 17 20 27 P30 P31 P33 P4c P47 a P5o P57 P6r P6r 7 7 9 5 10 8 87 Low level output voltage POc P07 1 1 20 27 _ Vo V _ lo 2mA 08 Vo Low level output voltage lo 10mA A 16 v lo 2mMA 0 4 HOLD RDY 4 amp TBOin TB2in VeVe Hysteresis nite Ans CTS CTS CUG C K EEE V Vn Vr Hystresis RESET 4 1 02 05 V Vn VrjHysereis O3 V High level input current POc PO P1o P17 20 27 P30 P33 4 4 P5o P 57 B A P amp P6 7 7 ApS z Xin RESET CNVss BYTE Low level input current POo PO7 10 P17 20 27 P935 P40 4P 47 50 57 _ 5 A L PGe P67 P70 P77 P8o P8r zd Xin RESET CNVss BYTE 2 Vram RAM hold voltage When clock is stopped V loc Power s
86. 4 16 4 16 Timer A3 register Addresses 4D1e 4C1s Timer A4 register Addresses 4F e 4E16 Can be set to 000016 to FFFF e n d Note Counter divides the count source frequency by n 1 Continue to Figure 5 3 3 on next page Fig 5 3 2 Initial setting example for registers relevant to timer mode 1 7702 7703 Group User s Manual 5 1 1 TIMER A 5 3 Timer mode From preceding Figure 5 3 2 Setting interrupt priority level b7 00 Timer Ai interrupt control register i 0 to 4 Addresses 7516 to 7916 Interrupt priority level select bits When using interrupts set these bits to level 1 7 When disabling interrupts set these bits to level 0 Setting port P5 and port P6 direction registers b7 bO Port P5 direction register Address D16 TAOIN pin TAIN TA2IN TAIN b7 b0 Port P6 direction register Address 1016 TAAIN pin When gate function is selected sei the bit corresponding to the pin to 0 Setting count start bit to 1 b7 b0 Count start register Address 4016 Timer AO count start bit Timer A1 count start bit Timer A2 count start bit Timer A3 count start bit Timer A4 count start bit Count starts Fig 5 3 3 Initial setting example for registers relevant to timer mode 2 5 12 7702 7703 Group User s Manual TIMER A 5 3 Timer mod
87. 4 5 2 Initial comparison value is 0 For interrupts for which no interrupt request occurs the priority level sent from the preceding comparator is forwarded to the next comparator When the two priority levels are found the same by comparison the priority level sent from the preceding comparator is forwarded to the next comparator Accordingly when the same priority level is set by software the interrupt requests are subject to the following relation about priority A D conversion gt UART1 transmit gt UART1 receive gt UARTO transmit gt UARTO receive gt Timer B2 gt Timer B1 gt Timer gt Timer 4 gt Timer gt Timer A2 gt Timer A1 gt Timer AO gt INT gt INT gt Among the multiple interrupt requests sampled at the same time one that has the highest priority level is detectedd by the above comparison Then this highest interrupt priority level is compared with the processor interrupt priority level IPL When this interrupt priority level is higher than the processor interrupt priority level IPL and the interrupt disable flag 1 is O the interrupt request is accepted A interrupt request which is not accepted here is retained until it is accepted or its interrupt request bit is cleared to O by software The interrupt priority is detected when the CPU fetches an op code which is called the CPU s op code fetch cycle However when an op code fetch cycle is generated during det
88. 4 gt 17 gt 48 lt gt Pti AolDo COED P51 TAOIN lt gt 18 gt 47 lt gt P12 A10 D19 C P50 TAOouT lt gt 19 S lt 46 lt gt P13 A11D1 11 P47 gt 20 gt lt 45 gt AID Equivalent to P42 b 1 4 gt 21 OD 44 lt gt P15 A13 D13 AD M5M27C256K m P41 RDY 22 70 43 lt gt P16 A14 D14 A 22 Equivalent to 5 27 101 P4o HOLD gt 23 42 he gt 17 15 015 BYTE 24 i41 lt gt P20 A16 Do Do Equivalent to VPP CNVss 25 40 lt gt P21 A17 D1 c DD MSM27C101K RESET gt 26 39 4 gt 22 18 02 lt D2 O XIN 27 38 lt gt P23 A19 D3 lt D3 2 Xour lt 28 37 P24 Az0 Da DD 29 36 lt gt 25 421 05 lt Ds Vss 80 35 26 22 06 De 2 gt 31 34 lt gt 27 23 07 D7 P31 BHE lt gt 32 33 lt gt P3o R W Vss Connect an oscillating circuit lt gt EPROM pins Outline 64P4B Fig 20 6 1 Pin connections EPROM mode 20 14 7702 7703 Group User s Manual 7703 GROUP 20 6 PROM version 20 6 2 Bus timing and EPROM mode The PROM versions shown in Table 20 6 2 have the different bus timing from other PROM versions mask ROM external ROM versions Additionally they can use only 256K mode as the EPROM mode though its PROM
89. 5 1 0 1 5 2 0 2 5 3 0 VoL V 18 232 7702 7703 Group User s Manual LOW VOLTAGE VERSION 18 5 Standard characteristics 18 5 2 Icc f Xin standard characteristics 1 characteristics on operating and at reset Measurement condition Vcc 3 V Ta 25 f XIN square waveform input microprocessor mode On operating Icc mA At reset a ae 5 10 15 MHZ 2 Icc f Xin characteristics during Wait Measurement condition Vcc 3 V Ta 25 C f XIN square waveform input microprocessor mode mA 1 0 5 10 15 MHz 7702 7703 Group User s Manual 18 33 LOW VOLTAGE VERSION 18 5 Standard characteristics 18 5 3 A D converter standard characteristics The lower lines of the graph indicate the absolute precision errors These are expressed as the deviation from the ideal value when the output code changes For example the change in output code from 0416 to 05 6 should occur at 52 7 mV but the measured value is 2 9 mV Therefore the measured point of change is 52 7 2 9 55 6 mV The upper lines of the graph indicate the input voltage width for which the output code is constant For example the measured input voltage width for which the output code is OF e is 12 4 mV Therefore the differential non linear error is 12 4 11 7 0 7 mV 0 06L SB Measurement condition Vcc 3 V f Xin 8 MHz Temp
90. 5 5 1 MS PS 8 5 1 PC AD PCG AUR P Xhg BYC Branches when the contenta of the V flag is 0 Mate 3 Branches when the contents of the V flag is 77 Note 3 UL B Makes the contants of tha specified bi in the memory 07 Note 5 the contenta of tha D Makes the contents of the flag cou the contents of tha specified tit ig 17 Branches when the conlents of me C flag is D Branches whan the contents of the C flag ia 717 Branches when th contents of ihe Z flag i 217 Tests the spacifiad bit of memory Branches when all um CLM mi Makas tha contents of lhe m Dag C CLP P b TEL TT T NA patem of the second byle in the instruction and sets Y in that bit aw n cantante af ma V fag Acc M LN S Mate 1 2 the memory 7 s LLA T 21 58 7702 7703 Group User s Manual APPENDIX Appendix 8 Machine instructions et motte pacar stalus 5 ABS ABS b T Nl B a xltags RAE STK a ABS b SR sine ele umm ic uU ii tiii n E 4213 77 s T al e a Hn HOUR ELLE B 9 DIESES TELL LE EE inn 1111111 CTT TTT E comes
91. 7t05 Nothingisassigned ea a 4 Set to 0 1 to meet the purpose Set to 0 at writing Set to 1 at writing This bit is not used in the specific mode or state It may be either 0 or 1 Nothing is assigned 0 immediately after a reset 1 immediately after a reset Undefined Undefined immediately after reset It is possible to read the bit state at reading The written value becomes valid data It is possible to read the bit state at reading The written value becomes invalid Accordingly the written value may be either 0 or 1 The written value becomes valid data It is not possible to read the bit state The value is undefined at reading However the bit with the commentaries of The value is 0 at reading in the functions column or the notes is always 0 at reading See to 4 above It is no possible to read the bit state The value is undefined at reading However the bit with the commentaries of The value is 0 at reading in the functions column or the notes is always 0 at reading See to 4 above The written value becomes invalid Accordingly the written value may be 0 or 1 Table of Contents Table of Contents CHAPTER 1 DESCRIPTION
92. 8 6 1 Settings for repeat mode Figure 8 6 1 shows an initial setting example of repeat mode 7702 7703 Group User s Manual 8 17 A D CONVERTER 8 6 Repeat mode A D control register b7 o TEE A D control register address 1 16 Analog input select bits b2 61 60 ANo selected selected AN2 selected ANs selected AN4 selected ANs selected ANe selected AN7 selected OOOO OO O O O O Repeat mode Trigger select bit 0 Internal trigger 1 External triggeer A D conversion start bit 0 Stop A D conversion conversion frequency AD select bit 0 divided by 4 1 divided by 2 f N OG Port P7 direction register b7 bO Port P7 direction register address 1116 ANo AN AN2 Set the bits corresponding AN3 to analog input pins to 0 AN Set bit 7 to 0 when selecting external trigger ANe V AN7 4 N A D conversion start bit to 1 b7 b0 r A D control register address 1 16 A D conversion start bit p 4 electing external trigger falling edge to Selecting internal trigger ADrnc Trigger occur Operation start Note Write the each bit except bit 6 of the A D control regiter when the A D conversion stops before
93. 85 C f Xin 8 MHz unless otherwise noted the pos Port PO address hold time 150 5 hALE P1A ns Port P1 data hold time BYTE L 50 1 lpzxE Piz 95 ns 50 twur ee PortP2addressholdtime 19 13 twee PortP2dataholdtime 5 13 22 95 _ ns te BHEholdtime Bs ixEaw R W hold ime 8s Note For test conditions refer to Figure 18 4 1 This is depending on f Xmw For data formula refer to Table 18 4 2 Table 18 4 2 Bus timing data formula f XIN res Note 1 X 10 tapia Note dip sah tarza Note laPrA ALE 1X10 gs ld P2A ALE ases Note Lx 108 50 125 tarw Note f XIN 1x10 jog 1 2 X f XIN ine e10 1X10 db tn E P20 2XXN 7 tpzx E P12 Note 1X10 _ 49 ipzxe P2z Note Unit ns Note For the M37702E2LXXXGP and the M37702E4LXXXFP refer to section 19 5 4 Bus timing and EPROM mode 18 28 7702 7703 Group User s Manual LOW VOLTAGE_VERSION 18 4 Electrical characteristics Memory expansion mode and microprocessor mode With Wait lt Write gt tw H tr tt tc f Xin PUR FII 1 ld E 61 la E 6 1 tw EL Address output Ac Ar C Addes Adress oupu i 7 15 BYTE H Address Data output th E P1A 2 Address Data BYTE 4 NF Data input td P
94. A1 count start bit Timer A2 count start bit TmerBicoutsanbi Bits 7 to 5 are not used for Timer A Fig 5 2 2 Structure of count start register 7702 7703 Group User s Manual 5 5 TIMER A 5 2 Block description 5 2 3 Timer Ai mode register Figure 5 2 3 shows the structure of the timer Ai mode register Operating mode select bits are used to select the operating mode of timer Ai Bits 2 to 7 have different functions according to the operating mode These bits are described in the paragraph of each operating mode 07 066 b5 b4 b3 b2 bi b0 Timer Ai mode register i 0 to 4 Addresses 5616 to 5A 6 Operating mode select bits b1 b0 0 0 Timer mode 0 1 Event counter mode 1 0 One shot pulse mode 1 Pulse width modulation PWM mode Fig 5 2 3 Structure of timer Ai mode register 5 6 7702 7703 Group User s Manual TIMER A 5 2 Block description 5 2 4 Timer Ai interrupt control register Figure 5 2 4 shows the structure of the timer Ai interrupt control register For details about interrupts refer to Chapter 4 INTERRUPTS 67 06 b5 b4 b3 b2 bl Timer Ai interrupt control registers i 0 to 4 Addresses 7516 to 7916 Interrupt priority level select bits Level 0 Interrupt disabled xd Level 1 Low level Level 2 Level 3 RW Level 4 Level 5 RW Level 6 Level 7 High level 3 Interrupt request bit No interrupt request RW 1 Interrupt request Nothi
95. All bits of port Pi direction register are cleared to O after reset Accordingly follow the procedure shown by Figure 20 4 1 in the initial setting program after reset Do not write O after that to the bits to be fixed to 1 Paragraph 1 3 1 Example for processing unused pins explains the examples when there are pins however those pins are not used The above explanation is independent of that example explanation 2 Memory expansion and Microprocessor modes The M37703 does not have the HLDA pin so that the HLDA signal cannot be used in those modes Be sure to set 1 to the bit indicated by using 1 Though these bits do not have the corresponding pins follow the above procedure The above procedure is necessary whether or not other programmable ports are used 67 06 b5 b3 b2 bi 00 UB Port P3 direction register address 916 Ong NS I Port P4 direction register address C16 1 1 Port P6 direction register address 1016 mM rt 1 a Swit titi Port P7 direction register address 1116 LibL LLL Port P8 direction register address 1416 Notes 1 When executing the instruction to write to bits 4 to 7 of Port P3 direction register the value cannot be written into them When reading to those bits 0 is read 2 he bits which are not indicated by using 1 and bits 4 to 7 of Port P3 direction register function as a programmable port Just as in ports PO P2 and P5 set 0
96. D3 De i Di Do SP Stop bit PAR Parity bit 8 bit UART Parity 9 bit UART ock sync 2SP enabled UART O O 1SP Parity Clock sync 7 bit UART bi disabled 8 bit UART UARTI transmit register Clock sync 0 Fig 7 2 5 Block diagram of transmit section UARTO transmit buffer register Addresses 3316 3216 1 transmit buffer register Addresses 3Bie 16 Transmit data is set 15 to 9 Nothing is assigned Fig 7 2 6 Structure of transmit buffer register 7702 7703 Group User s Manual 7 9 SERIAL I O 7 2 Block description The UARTi transmit buffer register is used to set transmit data Set the transmit data into the low order byte of this register when operating in the clock synchronous serial I O mode or when a 7 bit or 8 bit length of transfer data is selected in the UART mode When a 9 bit length of transfer data is selected in the UART mode set the transmit data into the transmit buffer register as follows Bit 8 of the transmit data into bit O of high order byte of this register Bits 7 to 0 of the transmit data into the low order byte of this register The transmit data which is set in the UARTi transmit buffer register is transferred to the UARTI transmit register when the transmission conditions are satisfied and then it is output from the TxDi pin synchronously with the transfer clock The UARTi transmit buffer register becomes empty when the data whic
97. E Reference voltage input Functions Supply 5 V 10 to Vcc pin and 0 V to Vss pin This pin controls the processor mode Single chip mode Memory expansion mode Connect to Vss pin Microprocessor mode Connect to Vcc pin The microcomputer is reset when supplying L level to this pin These are pins of the internal clock generating 3 Connect a ceramic resonator or quartz crystal oscillator between pins Xin and Xour When using an external clock the clock source should be input to Xin pin and Xour pin should be left open This pin outputs E signal Data instruction code read or data write is performed when output from this pin is L level Single chip mode Connect to Vss Memory expansion mode Microprocessor mode Input level to this pin determines whether the external data bus has a 16 bit width or 8 bit width The width is 16 bits when the level is L and 8 bits when the level is H The power supply pin for the A D converter Externally connect AVcc to Vcc pin The power supply pin for the A D converter Externally connect AVss to Vss pin This is a reference voltage input pin for the A D converter x In the low voltage version supply 2 7 5 5V to Vcc 7702 7703 Group User s Manual DESCRIPTION 1 3 Pin description Table 1 3 2 Pin description 2 Input Output Pin POo PO07 P1o P 17 AsDe Ais Dis P2o P27 Aic Do Aes D7
98. E PO0A 9 th E P1A 2 Cp lt gt td ALE E tsu PiD E lh E BHE th E R W th E PiD Output timing voltage VoL 0 8 V 2 0 V Data input ViL 2 0 16 V 0 5 V Test conditions P4 P8 Vcc 2 7 5 5 Input timing voltage 0 2 V 0 8 V Output timing voltage VoL 0 8 V Vor 2 0 V 7702 7703 Group User s Manual LOW VOLTAGE VERSION 18 4 Electrical characteristics 18 4 9 Memory expansion mode and microprocessor mode with Wait Timing requirements Vcc 2 7 5 5 V Vss 0 V Ta 40 to 85 C 8 MHz unless otherwise noted 7 Exemaldokiputyleume 217110715 ExemaldockinputhigPdevelpule width J rs tu External clock input low level pulse with t Exemaldockrse me lll I o 5 i Exemaldockfalime o J oln PotPiimutseuplims 709 tue PortP2imutseuptime 0 tuos PortP4inutseuptime 300 n tuoo 5 90 rs bum PotP6ipuselp me 1 90 ns PorP7inutsetplime 30 ms bum PotPB8iputseup me 9 1 90 rs beso PotPfimuthod me 0 bes PotP2iputhod me o O rs emo j PotP4iputhod me O ns bes PotP5iuthod m
99. E P2Q or td E P1Q Table 18 6 1 lists the calculation tormulas and constants for each parameter of the low voltage version Figure 18 6 1 shows the relationship between ta AD and f Xin Figure 18 6 2 shows the relationship between tsu D and Table 18 6 1 Calculation formulas and constants for each parameter Unit ns lt 8 MHz Paramete Wai 1 X10 td P1A E 125 tap2a c Note lw EL 2 10 _ 4 10 _ B 49 tsu P1D E tsu P2D E 80 ae 130 d E P2Q 1 0 pxz E P2Z tpzx E P1Z 1X 10 30 tpzx E P2Z Note f XIN Note For M37702E2LXXXGP M37702bEALXXXFP refer to section 19 5 4 Bus timing and EPROM mode 7702 7703 Group User s Manual 18 35 LOW VOLTAGE VERSION 18 6 Application 19 O 66 2 External clock input frequency f XIN Address decode time and address latch delay time are not considered Fig 18 6 1 Relationship between taan and f X ns 20001830 18009 A 1609 1430 1400 1653 1200 UG 972 1000 80 60 40 Q 2 2 E 2 9 C External clock input frequency f XIN Fig 18 6 2 Relationship between tsup and f Xin 18 36 7702 7703 Group Users Manual LOW VOLTAGE VERSION 18 6 Application
100. Head from timer Aj register Write to timer Aj register 5 20 Specifications External signal two phase pulse input to the or TAjOUT 2 to 4 Up count or down count can be switched by external signal two phase pulse When the counter overflows or underflows reload register s contents are reloaded and counting is continued e For down count 1 n 1 For up count n Timer Aj register setting value 1 FFFFis n 1 When count start bit is set to 1 When count start bit is cleared to 0 When the counter overflows or underflows Two phase pulse input Counter value can be read out While counting is stopped When a value is written to timer A2 or A4 register it is written to both reload register and counter e While counting is progress When a value is written to timer A2 A3 or A4 register it is written to only reload register Transferred to counter at next reload time 7702 7703 Group User s Manual TIMER A 5 4 Event counter mode 67 06 b5 b4 b3 02 bi b0 x x o Timer Ai mode register i 0 to 4 Addresses 5616 to 5A16 Operating mode select bits a e Renee eer 01 Event counter mode Pulse output function select bit 0 No pulse output TAiour pin functions as a programmable port Pulse output TAiour M functions as a pulse output pin Zamaa s Count polarity select bit x Counts at fallin
101. O 7 3 Clock synchronous serial I O mode When not using interrupts When using interrupts The receive interrupt request occurs when reception is completed N hecking completion of reception UARTO transmit receive control register 1 Address 3516 UART1 transmit receive control register 1 Address 3D16 b7 bO It Receive complete flag 0 Reception not completed receive interrupt Checking error UARTO transmit receive control register 1 Address 3516 UART1 transmit receive control register 1 Address 3D16 b7 00 Overrun error flag 0 No overrun error 1 Overrun error detected Reading of receive data UARTO receive buffer register Address 3616 UART1 receive buffer register Address 3E16 b7 00 fT TT Et tt E rea out receive data Note This figure shows the bits and registers required for processing Refer to Figure 7 3 11 about the change of flag State and the occurrence timing of an interrupt C Processing after reading out receive data request Fig 7 3 8 Processing after reception s completion 7 28 7702 7703 Group User s Manual SERIAL 1 O 7 3 Clock synchronous serial mode 7 3 5 Receive operation When the receive conditions listed on page 7 25 are satisfied the UARTi enters the receive enable state The receive operations are described below The input signal of the RxDi pin is
102. O mode select bits 0 0 0 Serial I O disabled P8 functions as a programmable I O port Clock synchronous serial I O B mode 1 Not selected Not selected UART mode Transter data length 7 bits UART mode 3 Internal External clock select bit 0 Internal clock 1 External clock 4 Stop bit length select bit 0 One stop bit Valid in UART mode Note 1 Two stop bits Odd Even parity select bit 0 Odd parity Valid in UART mode when 1 Even parity parity enable bit is 1 Note Parity enable bit 0 Parity disabled Valid in UART mode Note 1 Parity enabled 7 oleep select bit 0 Sleep mode cleared ignored R Valid in UART mode Note 1 Sleep mode selected Note Bits 4 to 6 are ignored in the clock synchronous serial I O mode They be either 0 or 1 Additionally fix bit 7 to 0 Transfer data length 8 bits DART mode Transfer data length 9 bits 1 1 1 Not selected RW RW RW RW RW RW RW W Fig 7 2 2 Structure of UARTi transmit receive mode register 7 4 7702 7703 Group User s Manual 1 SERIAL I O 7 2 Block description Internal External clock select bit bit 3 Clock synchronous serial I O mode By clearing this bit to O in order to select an internal clock the clock which is selected with the count source select bits bits 0 and 1 at addresses 3416 3C e becomes the count source of BRGi described later The BRGi out
103. P10 As Ds P11 A9 Dg P12 A10 D10 P13 A11 D11 P14 A12 D12 P15 A13 D13 P16 A14 D14 P17 A15 D15 20 16 00 P21 A17 D1 P22 A18 D2 P23 A19 D3 Outline 80P6N A Fig 19 4 1 Pin connections in 256K mode 1 Connect an oscillating circuit C_D EPROM pins 7702 7703 Group User s Manual 19 13 PROM VERSION 19 4 256K mode 256K mode top view 59e apa 15 A a C D7 gt P27 Az23 D7 8 C De gt P2 Az22 De lt gt 8 C Ds gt P25 A21 D5 lt gt C Da gt P24 A20 D4 gt C Ds gt P23 A19 D3 Neo e T z lt 22782232 lt lt lt lt lt lt L Q loo gE WR OO EnS FDD o C S D N gt C gt Oo 0 0 o 0 e n n_ n n n n n n gt lt gt lt gt n n n n n n 84 e rej rel eer 88 87 eel 65 ea 32 61 P6e TB1IN lt gt 60 lt gt P86 RxD1 P65 TBOIN lt O C 4 P87 TxD1 PINT gt D o Ao P63 INT1 lt gt lt gt POUA Pg INTo lt gt lt lt gt gt gt P61 TA4In lt gt 6 CO lt gt P03 A3 P60 TA4out gt M lt gt PO4 A4 P57 TA3IN gt 8
104. P6 direction register Bits to 6 of port P7 direction register Bits 4 and 5 of port P8 direction register els mmm mmm mm Fig 3 1 2 Structure of port Pi i 0 to 8 direction register 7702 7703 Group User s Manual 3 3 INPUT OUTPUT PINS 3 1 Programmable I O ports 3 1 2 Port register Data is input output to from externals by writing reading data to from the port register The port register consists of a port latch which holds the output data and a circuit which reads the pin state Each bit of the port register corresponds one for one to each pin of the microcomputer Figure 3 1 3 shows the structure of the port Pi i O to 8 register When outputting data from programmable 1 0 ports set to output mode By writing data to the corresponding bit of the port register the data is written into the port latch The data is output from the pin according to the contents of the port latch By reading the port register of a port set to output mode the contents of the port latch is read out instead of the pin state Accordingly the output data is correctly read without being affected by an external load Refer to Figures 3 1 4 and 3 1 5 When inputting data from programmable 1 0 ports set to input mode The pin which is set to input mode enters the floating state By reading the corresponding bit of the port register the data which i input from the pin can be read out By wri
105. P6 direction register 1116 Port P7 direction register 1216 Port P8 register 1316 141e Port P8 direction register Fig 3 1 1 Memory map of direction registers and port registers 2 2 7702 7703 Group User s Manual INPUT OUTPUT PINS 3 1 Programmable I O ports 3 1 1 Direction register This register determines the input output direction of the programmable port Each bit of this register corresponds one for one to each pin of the microcomputer Figure 3 1 2 shows the structure of port Pi i O to 8 direction register b7 b6 b5 b4 b3 b2 bi b0 Port Pi direction register i O to 8 Addresses 416 516 816 916 C16 Die 1016 1116 1416 Port Pio direction bit 0 Input mode Functions as an input port EN Port Pi direction bit 1 Output mode Port Pie direction bit Functions as an Output port Port Pis direction bit Port Pia direction bit Port Pis direction bit em Ew Port Pie direction bit Port direction bit Notes 1 Bits 7 to 4 of the port direction register cannot be written they may be either 0 or 1 and are fixed to 0 at reading 2 In the memory expansion mode or the microprocessor mode fix bits 0 and 1 of the port P4 direction register to 0 7703 Group 7703 Group Fix the following bits which do not have the corresponding pin to 1 Bit 3 of port P3 direction register Bits 3 to 6 of port P4 direction register Bits 0 1 6 and 7 of port
106. RW BHE ALE HLDA I O port PO I O port P1 I O port P2 I O port I O I O Functions Single chip mode Port PO is an 8 bit CMOS port This port has an I O direction register and each pin be programmed for input or output Low order 8 bits of the address are output Single chip mode Port P1 is an 8 bit I O port with the same function as Memory expansion mode Microprocessor mode e External bus width 8 bits When the BYTE pin is H level Middle order 8 bits As Ai5 of the address are output e External bus width 16 bits When the BYTE pin is L level Data De to Dis input output and output of the middle order 8 biis Ae A s of the address are performed with the time sharing system Single chip mode P2 15 an 8 bit I O port with the same function as PO Memory expansion mode Microprocessor mode Data Do to D7 input output and output of the high order 8 bits A e Azs of the address are performed with the time sharing system Single chip mode Port is a 4 bit I O port with the same function as PO Memory expansion mode Microprocessor mode 3 3 respectively output R W ALE and HLDA signals en w The Read Write signal indicates the data bus state The state is read while this signal is H level and write while this signal is L level eBHE L level is output when an odd numbered address is accessed ALE
107. RW to the operating mode Timer Bi mode register b7 b6 b5 b4 b3 b2 bl bO Timer mode Event counter mode Pulse period Pulse width RW measurement mode Not selected o RW Undefined E Undefined RO Note RW Note Bit 5 is ignored in the timer mode and event counter mode its value is undefined at reading 7702 7703 Group User s Manual 21 25 APPENDIX Appendix 3 Control registers Timer mode b7 b6 b5 b4 b3 02 bl T Timer Bi mode register i 0 to 2 Addresses 5 16 501 b1 bO 00 Timer mode Operating mode select bits Cm Cn These bits are ignored in timer mode o w Nothing is assigned uei This bit is ignored in timer mode pert b7 b6 Count source select bits 00 fo 01 16 Lon lege ede fea 1 1512 615 08 b7 bO b7 bO Timer BO register Addresses 5116 5016 PY ino register Addresses 531e 520 Timer B2 register Addresses 5516 5416 15 to 0 These bits can be set to 000016 to FFFF e Undefined RW Assuming that the set value n the counter divides the count source frequency by n 1 When reading the register indicates the counter value 21 26 7702 7703 Group User s Manual APPENDIX Appendix 3 Control registers Event counter mode 67 b6 b5 b4 b3 b2 bi 00 Timer Bi mode register i 0 to 2 A
108. TAiin input cycle time must be 4 cycles or more of count source TAin input high level pulse width must be 2 cycles or more of count source TAiw input low level pulse width must be 2 cycles or more of count source Timer A input external trigger input in one shot pulse mode Limits Symbol Parameter Data formula Unit EL turas TAim input high level pulse width 7150 80 ns twra TAin input low level pulse width i oo ns Timer A input external trigger input in pulse width modulation mode Limits Symbol Parameter Uni tw TAH TAii input high level pulse width 125 go ns tw TAL TAii input low level pulse width 125 go ns Timer A input up down input in event counter mode win T Max Min Max input 25001 2000 ns TAiovrinputhigh level pulsewidth 1120 100 ns wur input low level pulsewidth 1120 1000 ns luu TAiourinputsetuptime 150 400 J ns TAiour input hold time 15 400 ns 15 6 7702 7703 Group User s Manual ELECTRICAL CHARACTERISTICS 15 5 Internal peripheral devices Timer A input Two phase pulse input in event counter mode Parameter Unit TAj input cycle time 1000 800 ns TAji input setup time 250 20 ms TAjour input setup time 250 12001 ns 7702 7703 Group User s Manual 15 7 ELECTRICAL CHARACTERISTICS 15 5 Internal p
109. The timer down counts the falling edges to the TAkin pin when the phase has the relationship that the TAk 5 input signal level goes irom H to L while the TAkour 5 input signal is level Refer to Figure 5 4 7 TAkour 4 Up Up Up Down Down Down count count count count count 1 1 1 E 2j Fig 5 4 7 Normal processing 7702 7703 Group User s Manual 5 27 TIMER A 5 4 Event counter mode eQuadruple processing The timer up counts all rising and falling edges to the TA4our and TA4in pins when the phase has the relationship that the TA4in pin s input signal level goes from L to H while the TA4our pin s input signal is H level The timer down counts all rising and falling edges to the TA4our TA4in pins when the phase has the relationship that the TA4in pin s input signal level goes from H to L while the TA4our pin s input signal is H level Refer to Figure 5 4 8 Table 5 4 3 lists the input signals to the 4 TA4in pins when the quadruple processing is selected Up count all edges 1 1 1 1 sss NET x Up count all edges 1 1 41 1 H Fig 5 4 8 Quadruple processing Table 5 4 3 TA4ov and 4 pins input signals when quadruple operation is selected s Input signal to TA4ouT pin Input signal to TA4IN pin Up count Rising Falling L level H level Down count Falling L level Rising H level Falli
110. This is used to obtain only the address from address and data multiplex signals HLDA This is the signal to externally indicate the state when the microcomputer is in Hold state L level is output during Hold state The 7703 Group does not have the P33 HLDA pin 7702 7703 Group User s Manual 1 7 DESCRIPTION 1 3 Pin description Table 1 3 3 Pin description 3 Pin Input Output Functions P4o P47 I O port P4 Single chip mode HOLD RDY P42 P47 HOLD RDY i 4 47 PO These pins be programmed as pins for Port P4 is an 8 bit I O port with the same function as PO P4 be programmed as the clock output pin P5o P5 I O port P5 I O Timers 0 P6v P67 I O port P6 Fort P6 is 8 bit I O port with the same function as PO These pins can be programmed as pins for Timer A4 input pins for external interrupt and input pins for Timers BO B2 input pin The microcomputer is in Hold state while L level is input to the HOLD pin The microcomputer is in Ready state while L level is input to the RDY pin 42 47 function as I O ports with the same functions as PO P4 be programmed for the clock output _ Microprocessor mode P4o functions as the HOLD input pin P4 as the RDY input pin P42 always functions as the clock 91 output pin P4s P4 function as I O ports with the same functions as PO Port P5 8 bi
111. an interrupt request is accepted the contents of the registers listed below immediately preceding the acceptance of the interrupt request are automatically saved to the stack area in order of registers 0O 9G Program bank register PG Program counter PCL PC Processor status register PSL Figure 4 1 2 shows the state of the stack area just before entering the interrupt routine Execute the RTI instruction at the end of this interrupt routine to return to the routine that the microcomputer was executing before the interrupt request was accepted As the RTI instruction is executed the register contents saved in the stack area are restored in order of registers 9 2 gt 0 and a return is made to the routine executed before the acceptance of interrupt request and processing is resumed from it When an interrupt request is accepted and the RTI instruction is executed the only above registers to are automatically saved and restored When there are any other registers of which contents are necessary to be kept use software to save and restore them Stack area Address S 5 S 4 Processor status register low order byte PSL S 3 Processor status register s high order byte PSH S 2 Program counter s low order byte PCL S 1 Program counter s high order byte PCH S Program bank register PG S is an initial value that the stack pointer S indicates at accepting an interrupt
112. analog input pins 7703 Group The number of the 7703 Group s analog input pins is different from the 7702 Group s Refer to Chapter 20 7703 GROUP for more information 8 1 Overview The A D converter has the performance specifications listed in Table 8 1 1 Table 8 1 1 Performance specifications of A D converter Item Performance specifications A D conversion method Successive approximation conversion method Resolution 8 bits Absolute accuracy 3 LSB Analog input pin 8 pins ANo to Note Conversion rate per analog input pin 57 cycles A D converter s operation clock Note In the 7703 Group the analog input pins are 4 pins to ANz Refer to Chapter 20 7703 GROUP for more information The A D converter has the 4 operation modes listed below One shot mode This mode is used to perform the operation once for a voltage input from one selected analog input pin Hepeat mode This mode is used to perform the operation repeatedly for a voltage input from one selected analog input pin Single sweep mode This mode is used to perform the operation for voltages input from multiple selected analog input pins one at a time Repeat sweep mode This mode is used to perform the operation repeatedly for voltages input from multiple selected analog input pins 8 2 7702 7703 Group User s Manual A D CONVERTER 8 2 Block description 8 2 Block description Figure 8 2 1 show
113. as 6 Signals timing to be input or output externally is ordained by clock 1 as a basis Fig 12 4 3 Timing of acceptance of Hold request and termination of Hold state 2 7702 7703 Group User s Manual 12 19 CONNECTION WITH EXTERNAL DEVICES 12 4 Hold function lt When inputting L level to HOLD pin during term using bus when data access is completed with continuous 2 bus cycle gt State when inputting L level to HOLD pin External data bus Data length External data bus width 16 Access from odd address Judgment timing of input level to HOLD pin Clock 1 1 ALE R W External address bus External data bus Ext add b Floati A T Address B HOLD l o1X1 Not accepted HLDA 1 Hold state mue Term using bus Term using bus When accepting a Hold request not a new address but an address output just before is output again Hold request cannot be accepted before input output of 16 bit data is completed Notes 1 This figure shows the case of no Wait 2 Clock 6 1 has the same polarity and the same frequency as Signals timing to be input or output externally is ordained by clock 6 as a basis Fig 12 4 4 Timing of acceptance of Hold request and termination of Hold state 3 12 20 7702 7703 Group User s Manual CHAPTER 13 RESET 13 1 Hardware reset 13 2 Software reset RESET
114. avoid collision between the data being read in and the preceding or following address output because the external data bus is multiplexed with the external address bus Refer to 3 Precautions on memory expansion External memory output enable signal las External memor i CEs Address output and data input 15 015 451 n Address chip select signal 12 27 12 22 A16 Do Az23 D7 tor tdis OE External memory data output __ Specifications of the M37702 The others are specifications of 1 This applies when th external data bus has a width of 16 bits BYTE L Xternal memory 2 If one of the external memory s specifications is smaller than there is a possibility of the tail of address colliding with the head of data Refer to 3 Precautions on memory expansion 453 If one of the external memory s specifications is greater than tpzx E P1z P2z there is a possibility of the tail of data colliding with the head of address Refer to 3 Precautions on memory expansion Fig 17 1 6 Timing at which data is read from an external memory 17 3 7702 7703 Group User s Manual APPLICATION 17 1 Memory expansion Table 17 1 4 Values of 2 22 and formulas to calculate tpz e Piziezz unit ns eM lt 8 MHz 8 MHz lt f Xin lt 16 MHz 16 MHz lt lt 25 MHz Parameter 22 12
115. bit state at reading The written value becomes valid data It is possible to read the bit state at reading The written value becomes invalid Accordingly the written value may be either O or 1 The written value becomes valid data It is impossible to read the bit state The value is undefined at reading However the bit with the commentaries of The value is O at reading in the functions column or the notes is always 0 at reading See 4 above t is impossible to read the bit state The value is undefined at reading However the bit with the commentaries of The value is 0 at reading in the functions column or the notes is always 0 at reading See 4 above The written value becomes invalid Accordingly the written value may be O or 1 7702 7703 Group User s Manual 21 11 APPENDIX Appendix 3 Control registers Port Pi register 67 b6 b5 b4 b3 b2 bi b0 Port Pi register i 0 8 Addresses 216 316 616 716 Ais Bie E16 F16 1216 Lm PP 00000 Pio Data is input output to from a pin by Undefined reading writing from to the corres 1 PotPh o Note Bits 7 to 4 of the port P3 register cannot be written they may be either 0 or 1 and are fixed to O at reading Port Pi direction register 07 06 bd b4 b3 b2 bl 1111111 Port Pi direction register i 0 to 8 Addresses 416 516 816 916 D16
116. contents conversion result of the successive approximation register is transferred to the A D register i The comparison voltage Vre is generated according to the latest contents of the successive approximation register Table 8 3 1 lists the relationship between the successive approximation register s contents and Vier Table 8 3 2 lists changes of the successive approximation register and Vre during the A D conversion Figure 8 3 1 shows the ideal A D conversion characteristics Table 8 3 1 Relationship between successive approximation register s contents and Veer Successive approximation register s contents n Vret V 0 0 V 14265 X n 0 5 256 Vner Reference voltage 7702 7703 Group User s Manual A D CONVERTER 8 3 A D conversion method Table 8 3 2 Change in successive approximation register and Vre during A D conversion eee Successive approximation register Change of Vref A D converter halt VREF VREF 2 512 V V V V lr a 2nd comparison 0 0 0 is t i B V E i 1st comparison comparison resul _1 VREF VREF VREF VREF VREF en 3rd comparison 610000 t 8 7 512 M ne 0 2nd comparison result 8th comparison z VREF d VREF ps V Conversion complete A D conversion result Ideal A D conversion characteristics tp gt VREF VREF VREF 256 X25
117. expansion model Minimum model Memory expansion model Medium model A M37702 M37702 16 Ao A15 n Ao A15 16 bit width BYTE L Do D15 Do D15 Memory expansion model Medium mode B Memory expansion model Maximum model Notes 1 Refer to Chapter 12 CONNECTION WITH EXTERNAL DEVICES about the functions and operation of used pins when expanding a memory Refer to Chapter 15 ELECTRICAL CHARACTERISTICS for timing requirements 2 Because the address bus width is used as maximum 24 bits when expanding a memory strengthen the M37702 s Vss line Refer to Appendix 5 Countermeasures against noise 7702 7703 Group User s Manual 17 3 APPLICATION 17 1 Memory expansion 17 1 2 How to calculate timing When expanding a memory use a memory of which standard specifications satisfy the address access time and the data setup time for write The following describes how to calculate each timing External memory s address access time tap ta Poa P1A P2A E tw EL 1 address decode address latch delay time ta PoA P1A P2A E td P1A E ta P2A E tsu P2D P1D E fsu P2D E tsu P1D E Address decode time Time required for the chip select signal to be enabled after decoding address Address latch delay time Delay time required when latching address Unnecessary in minimum model External memory s data setu
118. f Xin lt 25 MHz M5M5278CP FP J 25 25L MSMSP7BDP FP J 20 20L O oO Note When the user needs a specification of the memories listed above add the comment tor tas og 15 ns product microcomputer and kit 7702 7703 Group User s Manual 17 15 APPLICATION 17 1 Memory expansion M37702 T Address bus AC573 D Q LE OE D Q licae 7 7 F245 2 As Ds B V Data bus odd A15 D15 DIR OC F245 2 A16 Do A B A23 D7 Data bus even DIR OG Eccc Circuit condition Wait 25 MHz 1 Use the elements of which propagation delay time is within 20 ns 2 3 Use the elements of which sum of output disable time 2 and propagation delay time in 423 is within 18 ns and the sum of output enable time in 2 and propagation delay time in 453 is 5 ns more 4 Use the elements of which propagation delay time is within 12 ns Fig 17 1 11 Example for using bus buffer 1 17 16 7702 7703 Group User s Manual APPLICATION 17 1 Memory expansion lt When reading gt m 3 i r gt As Ds A15 D15 w 16 00 2 07 B lt 2 F245 RD lt _ 2 F245 External memory tPzw tPzL data output 245 F245 tPHZ tPLZ When writing 130 min E Onm gt 45 max As Ds A15 D15 A16 Do A23 D7
119. immediately after reset 1 7702 7703 Group User s Manual 13 5 RESET 13 1 Address Hardware reset Register name Access characteristics 2016 A D register 0 2116 2216 A D register 1 2316 2416 A D register 2 2516 2616 A D register 3 2 16 2816 A D register 4 2916 2A16 A D register 5 2 16 2616 A D register 6 2D16 2E16 A D register 7 2F16 3016 UARTO transmit receive mode register 3116 UARTO baud rate register 3216 3316 3416 UARTO transmit receive control register 0 3516 UARTO transmit receive control register 1 3616 3 16 3816 UART1 transmit receive mode register 3916 UART1 baud rate register 3A16 3B16 3C16 UART1 transmit receive control register 0 3D16 UART1 transmit receive control register 1 3E16 3F16 UARTO transmit buffer register UARTO receive buffer register UART1 transmit buffer register UART1 receive buffer register State immediately after a id 7 Oo 0 gt 50 gt 59 42 9 VY EVE VP VE 729 5 729 9 KAS o O gt Fig 13 1 4 State of SFR and internal RAM areas immediately after reset 2 13 6 7702 7703 Group User s Manual RESET 13 1 Hardware reset Address Register name 4016 4116 4216 4316 4416 4516 4616 4716 4816 4916 4A16 4B16 4C16 4D16 4E16 4F16 5016 5116 5216 5316 5416 5516 5616 5716 5816 5916 16 5B16 5C16 5D16 5E16 5F16 Notes 1 2 3 4 Fig 13 1 5 State Count start register
120. interrupt 4 22 7702 7703 Group User s Manual INTERRUPTS 4 10 External interrupts INTi interrupt 4 10 1 Function of INTi interrupt request bit 1 Selecting edge sense mode The interrupt request bit has the same function as that of internal interrupts That is when an interrupt request occurs the interrupt request bit is set to 1 The bit remains set to 1 until the interrupt request is accepted it is cleared to 0 when the interrupt request is accepted By software this bit also can be set to 0 in order to clear the interrupt request or 1 in order to generate the interrupt request 2 Selecting level sense mode The INT interrupt request bit becomes ignored In this case the interrupt request occurs continuously while the level of the pin is valid level When the pin level changes from the valid level to the invalid level before the interrupt request is accepted this interrupt request is not retained Refer to Figure 4 10 4 Valid level This means the level which is selected by the polarity select bit bit 4 at addresses 7D e to 7Fie Invalid level This means the reversed level of a valid level Level sense Edge sense Ln i 0 _ select bit INT pin Ta E EE Interrupt request bit O S gt Interrupt request O Fig 4 10 3 Circuit of INTi Interrupt 7702 7703 Group User s Manual 4 23 INTERRUPTS 4 10 External interrupts INTi interru
121. is automatically performed in the following order The contents of the program bank register PG just before performing the INTACK sequence are stored to stack The contents of the program counter PC just before performing the INTACK sequence are stored to stack The contents of the processor status register PS just before performing the INTACK sequence is stored to stack The interrupt disable flag 1 is set to 1 The interrupt priority level of the accepted interrupt is set into the processor interrupt priority level IPL The contents of the program bank register PG cleared io 0016 and the contents of the interrupt vector address are set into the program counter PC Performing the INTACK sequence requires at least 13 cycles of internal clock Figure 4 7 2 shows the INTACK sequence timing Execution is started beginning with an instruction at the start address of the interrupt routine after completing the INTACK sequence 4 14 7702 7703 Group User s Manual INTERRUPTS 4 7 Sequence from acceptance of interrupt request to execution of interrupt routine Interrupt request is accepted Interrupt request Interrupt response time P zu Duration for detecting interrupt priority level D Time from the occurrence of an interrupt request until the completion of executing an instruction which is being executed at the occurrence Time from the instruction next to Note
122. lt gt me e tsu P2D E gt 30 130 min 18 2 15 Kit guaranteed 2 tPHL lt gt 2 30 tsu D min lt gt AC32 tPLH temas Tene 2 tPHL lt gt lt gt 32 _ Unit Fig 17 1 16 Timing chart for SRAM expansion example minimum model 7702 7703 Group User s Manual nS 17 21 APPLICATION 17 1 Memory expansion 2 Example of ROM expansion maximum model Figure 17 1 17 shows a memory expansion example maximum model using a 2 Mbits ROM in the microprocessor mode Figure 17 1 18 shows the timing chart for this example 1 Use the elements of which propagation delay time is within 12 ns M37702S1B M5M27C202K 10 2 Use the elements of which propagation delay time is within 20 ns Address bus 14 17 Memory map 000016 008016 internal RAM area Data bus Do D15 028016 External ROM area M5M27C202k Circuit condition Wait Fig 17 1 17 Example of ROM expansion maximum model 17 22 7702 7703 Group User s Manual APPLICATION 17 1 Memory expansion lt When reading gt E OE As Ds A15 D15 Aie Do ta aD AC573 tPHL tPLH gt lt 04 04 gt lt 15 External ROM Kit guaranteed data output
123. lt gt P86 RxD1 lt gt P87 TxD1 lt gt 00 lt gt P01 A1 P02 A2 lt gt lt gt P04 A4 5P05 A5 lt gt 05 gt P07 A7 gt P10 As Ds lt gt 11 lt gt P12 A10 D10 lt gt P13 A11 D11 lt gt P14 A12D12 lt gt P15 A13 D13 4 16 14 014 lt gt P17 A15 D15 lt gt P20 A16 Do lt gt 21 17 01 lt gt P22 A18 D2 lt gt P23 A19 D3 lt gt P24 A20 D4 lt gt 25 21 05 lt gt 26 22 06 lt gt P27 A23 D7 lt gt P30 R W Outline 64P4B Fig 20 3 1 M37703M2BXXXSP pin configuration top view 20 4 7702 7703 Group User s Manual 7703 GROUP 20 4 Functional description 20 4 Functional description The M37703 has the same internal circuit as the M37702 The control registers in the SFR area and the memory assignment are also the same However part of the M37703 functions varies from the M37702 s because the number of M37703 s pins is 64 pins Table 20 4 1 lists the differences between the M37703 and M37702 This paragraph describes the differences from the M37702 Refer to the relevant functional descriptions of the M37702 about others Table 20 4 1 Differences between the M37703 and M37702 Parameters M37703M2BXXXSP M37702M2BXXXFP Programmable 1 0 port 53 In single chip mode 68 In single chip mode Port PO 8 bits 8 bits Port P1 8 bits 8 bits Port P2 8 bits 8 bits Port P3 bits Without P33 HLDA pin 4 bits P
124. microcomputer s Vss pin in the shortest possible distance f the wiring cannot be shortened insert a resistor of about 5 kohms as close to the CNVss pin as possible By way of this resistor connect the CNVss pin to the Vss pin lt In microprocessor mode gt Connect the CNVss Ver and Vcc pins in the shortest possible distance Reasons The CNVss Ver pin serves as a power source input pin for the built in PROM and this pin has a reduced impedance to allow a programming current to flow in when programming to the built in PROM This means that noise gets in easily If noise gets into the CNVss Ver pin abnormal instruction codes or data will be read out from the built in PROM causing a program runaway In single chip and Tu memory expansion modes n microprocessor mode M37702 M37702 Shortest possible distance Approx 5 kohms CNVss VPP AW CNVSS VPP Shortest possible distance ITI Connect the CNVss pin to Connect the CNVss pin to the Vss pin in the shortest the Vcc pin in the shortest possible distance possible distance The above processing is unnecessary for the BYTE VPP pin Fig 13 Wiring of CNVss Ves pin of built in PROM version 7702 7703 Group User s Manual 21 37 APPENDIX Appendix 5 Countermeasures against noise 2 Inserting bypass capacitor between Vss and Vcc lines Insert a bypass capacitor of about 0 1 uF between the Vss and Vcc lines When inserting this b
125. molded SDIP FS Ceramic QFN 1 2 7702 7703 Group User s Manual DESCRIPTION 1 1 Performance overview 1 1 Performance overview Table 1 1 1 shows the performance overview of the M37702 7703 Group Refer to Chapter 20 7703 GROUP Table 1 1 1 M37702 performance overview Parameters Functions Number of basic instructions 103 Instruction execution time 160 ns the minimum instruction at 25 MHz M37702M2AXXXFP 250 ns the minimum instruction at f Xin 16 MHz External clock input frequency M37702M2BXXXFP 25 MHz maximum M37702M2AXXXFP 16 MHz maximum Memory size ROM 16384 bytes RAM bytes Programmable Input Output 2 4 8 18 bits X 8 ports P3 T EE Multifunction timers 0 4 16 bits 5 TB0 TB2 7 6 bits 3 Serial I O UARTO UART1 UART or clock synchronous serial I O X 2 A D converter 8 successive approximation method X 1 8 channels Watchdog timer 12 bits X 1 Interrupts 3 external 16 internal priority levels O to 7 can be set for each interrupt with software Clock generating circuit Built in externally connected to a ceramic resonator or a quartz crystal oscillator Supply voltage 5 V 10 96 Power dissipation 60 mW at f Xin 16 MHz frequency typ Port Input Output Input Output withstand voltage 5 V characteristics Output current 5 mA Memory expansion Maximum 16 Mbytes Operating temperature range 20 C to 85 C Device structure CMOS high performance silicon ga
126. ot the l2 _ _ sem ma usss LLL ELTE BELLE ar byte PS ta 1 Mote 1 MERE T zs 81 3 STe esa E Tranamis tha contents of the accumulator A tc the Index register X Transmitg the contents e the accumulator A io tha ides register Y TED Tranamits the contents of the accumulator B 1o the direct page register TBS 5S B Transmita the contents of the accumulato B to the giack H pantar Transmita contents of the accumulator B io the index register X Tranamit amp Ehe contents of the accumulates B io the Indes H register Y s ii Trangmits the contents of the accumulator A to the direct page register AS AX gt Tranamits the contents of the dlaci page regieter to the 79 2 1 accumulator B DPR Tranamits the contenta of the direct page register tc the 42 4 accumulator B 18 NC _ Tranemite the Contenis of the sisck pointer to the accumulator A Tranamits i contents of the stack pointer to tha accumu lator 5 Transmiie the contenta of the stack pointer the raislar X THA Tranamits 106 contanti of tha index ragl tar X the attu mulator Transmils tha contents of tha Index register X i tha accu 2 mulato B Transmits the contents the Index register X the stack pointer Transmits
127. pin functions as a programmable port Pulse output TAiour functions as a pulse output pin Count polarity select bit E Counts at falling edge of external signal Counts at rising edge of external signal Up down switching factor select Contents of up down register bit Input signal to T Aiour pin MER LL loas iL 5 Fix this bit to 0 in event counter mode mis ee These bits ignored event counter mode b15 b8 b7 b7 po Limer AO register Addresses 4716 4616 Timer A1 register Addresses 4916 4816 Timer register Addresses 4016 4 16 Timer A4 register Addresses 4 16 4E16 15 to 0 These bits can be set to 000016 to FFFF16 Undefined RW Assuming that the set value n the counter divides the count source frequency by n 1 when down counting or by FFFF e n 1 when up counting When reading the register indicates the counter value 21 22 7702 7703 Group User s Manual APPENDIX Appendix 3 Control registers One shot pulse mode 67 b6 05 b4 b3 b2 bi 211091111110 Timer Ai mode register i 0 to 4 Addresses 5616 5A 6 o Rw w RW b1 bO 1 0 One shot pulse mode i b4 b3 i 00 Writing 1 to one shot start register 01 functions as a prog rammable I O port 1 0 Falling edge of pin s input s
128. possible Input an address to address input pins and supply data to be programmed to data pins in 8 bit parallel In this condition when pin CE is set to L level the data is programmed at the specified address input address into the built in PROM 3 Erase Possible only in EPROM version The contents of the built in PROM is erased by exposing the glass wiridow on top of the package to an ultraviolet light which has a wave length of 2537 Angstrom The light must be 15 J cm or more Table 19 4 2 Built in PROM state in 256K mode CE OE VPP Vcc Data I O Mode mL Readout Output Output VIL VIH Floating disable e sw 5v Floating Program j T5V Input Program verify Via b 125V 6v Output Program disable 12 5 V Floating X It may be VIL or ViH 7702 7703 Group User s Manual 19 15 PROM VERSION 19 4 256K mode 19 4 2 Programming algorithm of 256K mode Figure 19 4 3 shows the programming algorithm flow chart of 256K mode D Set Vcc 6 V VPP 12 5 V and address to 400016 After applying a programming pulse of 1 ms check whether data can be read or not If the data cannot be read apply a programming pulse of 1 ms again Repeat the procedure which consists of applying a programming pulse of 1 ms and read check until the data can be read Additionally record the number of pulses applied x before the data has been read Apply t
129. processor stalus register Aestores ihe contents of the stack on the data bank reg INI HE inter Restores ihe contents cl the stack on the Index register X Il 7702 7703 Group User s Manual APPENDIX Appendix 8 Machine instructions Addressing made Processor status register CUENTE CA DOO OG ue LOIR LIDIR Y ABS ABS b ABS X EEE ETE _ Hi m 7702 7703 Group User s Manual 21 65 APPENDIX Appendix 8 Machine instructions Symbol Function PLY M S A B X A X MES PUL Note 7 Nae 13 m n bit rotate latt m 1 n rotate eft bz bx m mat m c bz Ttg 5 54 PS MES 55 1 5 55 1 PC M 5 S 5 1 PC MLS 5 54 8 ROL Note 1 amp 8 51 5 55 1 PCy MiS S 5T PGMS RTS PC SBC Note 1 2 21 66 Restores the contenta of the stack on the index register Y Addressing mode Detail Savas tha registers among accumulato r Index register direct page register data bank register program bank register processor status register specilied by ihe Pattern of the second byte of the inatruction Into ihe slack Restores the contents of tha stack to the registers among accumulato index feglater direct page register
130. receive buffer register 3 16 3816 UART1 transmit receive mode register 3916 UART1 baud rate register 16 UART1 transmit buffer register 3B16 3C16 UART1 transmit receive control register 0 3D16 transmit receive contro register 1 3E16 UART1 receive buffer register 3F16 Fig 7 Memory assignment in SFR area 2 21 8 7702 7703 Group User s Manual APPENDIX Appendix 2 Memory assignment in SFR area Address Register name m Access characteristics tate immediately after a reset 4016 Countstart register 4116 4216 One shot start register l w ojo jojo 4316 ww 4416 Up down register 4516 4666 Timer AO register 4716 a 4816 Timer A1 register 4916 328 3 4A16 Timer A2 register 4B16 4 16 Timer A3 register 4D16 Fie 5016 Timer BO register lt 5116 5216 T B1 t 5316 Ea _ aw 5416 Timer B2 register 5516 r o 5616 mode register 6716 A1 mode register 5816 A2 mode register 5916 Timer mode register 5A16 Timer A4 mode register 5Bie X Timer BO mode register X RW 3 RW 5C16 Timer B1 mode register RW x3 RW 5016 Timer B2 mode register RW 3 RW 5E16 Processor mode register RW RW 5F16 1 The access characteristics at addresses 4616 to 4 16 varies according to Time
131. register Flag x is part of the processor status register which is described later When an 8 bit register is selected only the low order 8 bits of index register X are used and the contents of the high order 8 bits is unchanged In an addressing mode in which index register X is as an index register the address obtained by adding the contents of this register to the operand s contents is accessed In the MVP or MVN instruction a block transfer instruction the contents of index register X indicates the low order 16 bits of the source address The third byte of the instruction is the high order 8 bits of the source address Note Refer to 7700 Family Software Manual for addressing modes 2 1 3 Index register Y Y Index register Y is a 16 bit register with the same function as index register X Just as in index register X the index register length flag x determines whether this register is used as a 16 bit register or as an 8 bit register In the MVP or MVN instruction a block transfer instruction the contents of index register Y indicate the low order 16 bits of the destination address The second byte of the instruction is the high order 8 bits of the destination address 7702 7703 Group User s Manual 2 3 CENTRAL PROCESSING UNIT CPU 2 1 Central processing unit 2 1 4 Stack pointer S The stack pointer S is a 16 bit register It is used for a subroutine call or an interrupt It is also used when addr
132. request bit does not change When reading the UARTi receive buffer register by software the data B is read and the overrun error flag becomes 0 simultaneously Accordinaly the overrun error cannot may be detected and it is possible that the data B is managed as ihe data Fig 7 3 12 Case of overrun error cannot be detect using clock synchronous seriai I O mode 7 34 7702 7703 Group User s Manual SERIAL I O 7 4 Clock asynchronous serial I O UART mode 7 4 Clock asynchronous serial I O UART mode Table 7 4 1 lists the performance overview in the UART mode and Table 7 4 2 lists the functions of I O pins in this mode Table 7 4 1 Performance overview in UART mode Item Transfer data Start bit 1 bit format Character bit Transfer data 7 bits 8 bits or 9 bits Parity bt bit or 1 bit Odd or even can be selected Stop bit bit or 2 bits Transfer rate Clock of BRGi output divided by 16 When selecting external clock Maximum 312 5 kbps f Xin 25 MHz Maximum 250 kbps f Xin 16 MHz Maximum 125 kbps f Xin 2 8 MHz 4 types Overrun Framing Parity and Summing Presence of error can be detected only by checking error sum flag Functions Error detection Table 7 4 2 Functions of I O pins UART mode Pin name Functions Meihod of selection TxDi P83 P87 Serial data output Fixed RxDi P82 P8 Port P8 direction register s corresponding bit 0 CLKi P81 P8s BRGi
133. s count source Internal External clock select 1 input CTS RTS P80 P84 CTS input CTS RTS select bit 0 RTS output lt CTS RTS select bit 1 Port P8 direction register Address 1416 Internal External clock select bit 3 at addresses 3016 38 6 CTS RTS select bit bit 2 at addresses 3416 3C e Notes 1 The TxDi pin outputs H level while not transmitting after selecting UARTi s operating mode 2 The RxDi can be used as a programmable port when performing only transmission 3 The pin can be used as a programmable I O port when selecting internal clock 4 The CTS RTSi pin can be used as a input port when performing only reception and not using RTS function when selecting CTS function 7702 7703 Group User s Manual 7 35 SERIAL I O 7 4 Clock asynchronous serial UART mode 7 4 1 Transfer rate frequency of transfer clock The transfer rate is determined by the BRGi addresses 3116 3916 When setting into BRGi n 00 e to FFie BRGi divides the count source frequency by 1 The divided clock BRGi is further divided by 16 and the resultant clock becomes the transfer clock Accordingly the value is expressed by the following formula F NP n Value set into 16 X B F BRGi s count source frequency B Transfer rate An internal clock or an external clock can be selected as the BRGi s count source with the in
134. se quence for b because the interrupt request is sampled by the next sampling pulse Interrupt request b D 2 Sampling pulse 1l r f _ RTI instruction One instruction executed Interrupt routine a Main routine gt lt sequence for interrupt b 21 46 7702 7703 Group User s Manual APPENDIX Appendix 6 Q amp A Interrupt There is a routine where a certain interrupt request should not be accepted with enabled acceptance of all other interrupt requests Accordingly the program set the interrupt priority level select bits of the interrupt to be not accepted to 0002 in order to disable it before executing the routine However the interrupt request of that interrupt has been accepted immediately after the priority level had been changed Why did this occur and what can do about it Interrupt request iS 07 XXXIC Writes 0002 to interrupt priority level select bits accepted in this Clears interrupt request bit to 0 interval LDA A DATA Instruction at the beginning of the routine that should not accept one certain interrupt When changing the interrupt priority level the microcomputer can behave as if the interrupt request is accepted immediately after it is disabled if the next instruction the LDA instruction in the above case is already stored in the BIU s instruction queue Duffer and conditions to accept the interrupt
135. selected transmit buffer empty flag is set to 1 he transmit register empty flag is cleared to 0 UARTi transmit interrupt request occurs and the interrupt request bit is set to 1 The transmit operations are described below Data in the UARTi transmit register is transmitted from the TxDi pin synchronously with the falling of the transfer clock This data is transmitted bit by bit sequentially beginning with the least significant bit When 1 byte data has been transmitted the transmit register empty flag is set to 1 indicating completion of the transmission Figure 7 3 4 shows the transmit operation In the case of an internal clock is selected when the transmit conditions for the next data are satisfied at completion of the transmission the transfer clock is generated continuously Accordingly when performing transmission continuously set the next transmit data to the transmit buffer register during transmission when the transmit register empty flag 0 When the transmit conditions for the next data are not satisfied the transfer clock stops at H level Figures 7 3 5 shows an example of transmit timing when selecting an internal clock 7702 7703 Group User s Manual 1 23 SERIAL I O 7 3 Clock synchronous serial I O mode b7 00 UARTi transmit buffer register Transmit data 57 MSB LSB Transfer clock UAHTI transmit register D7 Ds 05 Da D3 D
136. size is 32 Kbytes or less Table 20 6 2 PROM versions having peculiar bus timing Bus timing 12 tpzx E 22 Type name 8MHz lt lt 16 MHz M37703E2AXXXSP Limits 50 ns Limits 25 ns M37703EAAXXXSP Formulas Formulas 1 X 109 1 X 10 9 2 X 6 25 2 X f X 1 Bus timing The limits and formulas of the PROM versions having the peculiar bus timing which is different from other PROM versions are shown in Table 20 6 2 When the user is planning to use the product shown in Table 20 6 2 for evaluation or in early production and replace it later with the mask ROM version we recommend to use the substitute shown in Table 20 6 3 for evaluation or in early production However the substitute version has the higher frequency external clock input There are no precaution about its operation Table 20 6 3 Substitutes Type name to be used Substitute Remark M37703E2AXXXSP M37703E2BXXXSP The substitute has the higher frequency of external clock input M37703E4AXXXSP M37703EABXXXSP 2 EPROM mode The products shown in Table 20 6 2 can use only 256K mode as the EPROM mode Do not use 1M mode 7702 7703 Group User s Manual 20 15 7703 GROUP 20 6 PROM version MEMORANDUM 20 16 7702 7703 Group User s Manual Appendix 1 Appendix 2 Appendix 3 Appendix 4 Appendix 5 Appendix 6 Appendix 7 Appendix 8 APPENDIX Memory assignment Memory assignment in
137. supply line Use the broader wiring width than that of the other signal wire for the Vss and Vcc lines When using the multilayer boards make sure that one of the middle layer is Vss side and the other one of middle layer is Vcc side When using the double sided boards one side must be located with looped or mesh form to the Vss line centering the microcomputer The vacant space must be filled with the Vss line The other side must be located with the Vcc line just as in the above mentioned Vss line Connect the power supply line of external devices connected to the microcomputer with the bus and the power supply line of the microcomputer in the shortest possible distance Reasons The level of many wiring among 24 pieces of external address bus will change at the same time when connecting external devices That may causes noise of the power supply line 21 44 7702 7703 Group User s Manual APPENDIX Appendix 6 Q amp A Appendix 6 Q amp A Information which may be helpful in fully utilizing the 7702 Group and the 7703 Group are provided in Q amp A format In Q amp A as a rule one question and its answer are summarized within one page The upper box on each page is a question and a box below the question is its answer If a question or an answer extends to two or more pages there is a page number at the lower right corner At the upper right corner of each page the main function related to the contents of descripti
138. switching Timer up down bit factor Timer A4 up down bit 5 Timer A2 two phase pulse signal 0 Two phase pulse signal processing select bit Note processing function disabled 1 Two phase pulse signal Timer A3 two phase pulse signal processing function enabled processing select bit Note When not using the two phase pulse signal processing function make sure to set the bit to 0 The value is 0 at reading Timer A4 two phase pulse signal processing select bit Note Note Use the LDM or STA instruction when writing to bits 5 to 7 7702 7703 Group User s Manual 21 19 APPENDIX Appendix 3 Control registers Timer Ai register b15 b8 Timer AO register Addresses 4716 4616 b7 bO 57 00 A1 register Addresses 4916 4816 Timer A3 register Addresses 4D16 4C16 Timer A4 register Addresses 4F16 4E16 x 15 to 0 These bits have different functions according Undefined RW to the operating mode Timer Ai mode register 67 b6 b5 b4 b3 b2 bl Timer Ai mode register i to 4 Addresses 5616 10 5 6 C mume Operating mode select bits 01 50 00 mode 0 1 Event counter mode 1 0 One shot pulse mode 1 Pulse width modulation PWM mode 21 20 7702 7703 Group User s Manual APPENDIX Appendix 3 Control registers Timer Mode 67 b6 b5 b4 b3 b2 bi jo 1 0 0 Timer Ai mode regist
139. that require a long access time The BIU s functions are described bellow Note The CPU operates based on cPU The period of CPUis normally the same as that of the internal 1 2 3 4 clock The internal bus operates based on the E signal The period of the E signal is twice that of the internal clock at a minimum Reading out instruction Instruction prefetch When the CPU does not require to read or write data that is when the bus is not in use the BIU reads instructions from the memory and stores them in the instruction queue buffer This is called instruction prefetch The CPU reads instructions from the instruction queue buffer and executes them so that the CPU can operate at high speed without waiting for access to the memory which requires a long access time When the instruction queue buffer becomes empty or contains only 1 byte of an instruction the BIU performs instruction prefetch The instruction queue buffer can store instructions up to 3 bytes The contents of the instruction queue buffer is initialized when a branch or jump instruction is executed and the BIU reads a new instruction from the destination address When instructions in the instruction queue buffer are insutiicient for the CPU s needs the BIU extends the pulse duration of clock cPU in order to keep the CPU waiting until the BIU fetches the required number of instructions or more Reading data from memory l O device The CPU spec
140. the possibility that trouble may occur with them Trouble with semiconductors may lead to personal injury fire or property damage Remember to give due consideration to safety when making your circuit designs with appropriate measures such as i placement of substitutive auxiliary circuits ii use of non flammable material or iii prevention against any malfunction or mishap Notes regarding these materials These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer s application they do not convey any license under any intellectual property rights or any other rights belonging to Mitsubishi Electric Corporation or a third party Mitsubishi Electric Corporation assumes no responsibility for any damage or infringement of any third party s rights originating in the use of any product data diagrams charts or circuit application examples contained in these materials All information contained in these materials including product data diagrams and charts represent information on products at ine time of publication of these materials and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information befor
141. the sleep mode for the other slave microcomputers By performing steps 2 to specification of the microcomputer performing transfer is realized Transmit data which has 0 in bit 7 from the master microcomputer Only the microcomputer specified in steps to can receive this data The other microcomputers do not receive this data By repeating step transfer can be performed between the same microcomputers continuously When communicating with another microcomputer perform steps to in order to specify the new slave microcomputer Transfer data between the master Master microcomputer and one slave microcomputer selected from multiple slave microcomputers Slave A Slave B Slave C Slave D Fig 7 4 12 Sleep mode 7 52 7702 7703 Group User s Manual SERIAL I O 7 4 Clock asynchronous serial I O UART mode Precautions when operating in clock asynchronous serial I O mode When receiving data continuously an overrun error cannot be detected in the following situation when the next data reception is completed between reading the error by software and reading the UARTi receive buffer register 8 bit data length parity disabled 1 stop bit Transfer clock RxD N st Do XD De sp Do D UARTi receive buffer register Undefined Receive complete flag Overrun error flag UARTi receive interruput request bit Software managemen
142. timer restarts counting of the count source Note from FFFie Note Clock 32 or which was counted just before executing the STP instruction 9 2 3 Operation in Hold state Watchdog timer stops operating in Hold state When Hold state is terminated Watchdog timer restarts counting in the same state where it stopped operating Hold state Refer to section 12 4 Hold function 7702 7703 Group User s Manual 9 7 WATCHDOG TIMER 9 3 Precautions when using watchdog timer 9 3 Precautions when using watchdog timer 1 When a dummy data is written to address 60 with the 16 bit data length writing to address 6116 is simultaneously performed Accordingly when the user does not want to change a value of the watchdog timer frequency select bit bit 0 at address 6116 write the previous value to the bit simultaneously with writing to address 6016 2 When the STP instruction refer to Chapter 10 STOP MODE is executed Watchdog timer stops When Watchdog timer is used to detect the program runaway select STP instruction disable with mask option 3 To stop Watchdog timer in Hold state the count source which is actually counted by Watchdog timer is the logical AND product of two signals One is the inverted signal input from the HOLD pin and the other is the count source fs2 or fs12 Note Accordingly when the HOLD pin s input signal level changes in a duration which is shorter than 1 cycle of the count sourc
143. transmission bit 0 at addresses 3516 3D16 1 Set data to the UAATi transmit buffer register addresses 3216 6 Pin s state transfer clock is input from the CLKi pin Serial data is output from the TxDi pin Dummy data is output when performing only reception 7 18 7702 7703 Group User s Manual SERIAL I O 7 3 Clock synchronous serial mode 7 3 2 Method of transmission Figures 7 3 1 shows an initial setting example for relevant registers when transmitting Transmission is started when all of the following conditions to G are satisfied When an external clock is selected satisfy conditions to with the following precondition satisfied lt Precondition gt The CLKi pin s input is H level external clock selected Note When an internal clock is selected above precondition is ignored ransmission conditions 0 Transmission is enabled transmit enable bit 1 Transmit data is present in the UARTi transmit buffer register transmit buffer empty flag 40 CTSi pin s input is L level when CTS function selected Note When the CTS function is not selected this condition is ignored When using interrupts it is necessary to set the relevant register to enable interrupts For details refer to Chapter 4 INTERRUPTS Figure 7 3 2 shows writing data after start of transmission and Figure 7 3 3 shows detection of transmission s completion
144. undefined at reset stack area changes when subroutines are nested or when multiple interrupt requests are accepted Therefore make sure of the subroutine s nesting depth not to destroy the necessary data Note Refer to 7700 Family Software Manual for addressing modes Stack area Address o 9 1 Program counter s high order byte PCH 5 Program bank register PG 5 is the initial address that the stack pointer S indicates at accepting an interrupt request The 55 contents become 5 5 after storing the above registers Fig 2 1 2 Stored registers of the stack area 2 4 7702 7703 Group User s Manual CENTRAL PROCESSING UNIT CPU 2 1 Central processing unit 2 1 5 Program counter PC The program counter is a 16 bit counter that indicates the low order 16 bits of the address 24 bits at which an instruction to be executed next in other words an instruction to be read out from an instruction queue buffer next is stored The contents of the high order program counter become FFie and the low order program counter PCL becomes at reset The contents of the program counter becomes the contents of the reset s vector address addresses FFFE e FFFF e immediately after reset Figure 2 1 3 shows the program counter and the program bank register Fig 2 1 3 Program counter and program bank register 2 1 6 Program bank register PG The program ba
145. when parity disabled selecting 2 stop bits 7702 7703 Group User s Manual 7 45 SERIAL I O 7 4 Clock asynchronous serial UART mode 7 4 5 Method of reception Figure 7 4 8 shows an initial setting example for relevant registers when receiving Reception is started when all of the following conditions and are satisfied Reception is enabled receive enable bit 1 The start bit is detected When using interrupts it is necessary to set the corresponding register to enable interrupts For details refer to Chapter 4 INTERRUPTS Figure 7 4 9 shows processing after reception s completion 7 46 7702 7703 Group User s Manual SERIAL I O 7 4 Clock asynchronous serial UART mode UARTO transmit receive mode register Address 30 16 UART1 transmit receive mode register Address 38 16 b2b1b0 100 UART mode 7 bits 101 UART mode 8 bits 1 1 0 UART mode 9 bits Internal External clock select bit 0 Internal clock 1 External clock Stop bit length select bit 0 1 stop bit 1 2 stop bits Odd Even parity select bit 0 Odd parity 1 Even parity Parity enable bit 0 Parity disabled 1 Parity enabled Sleep select bit 0 Sleep mode cleared ignored N 1 Sleep mode selected Note Set the transfer data format in the same way as set on the transmitter side m UARTO transmit receive control register 0 Address 3
146. which is BRGi output s divided by 2 When selecting external clock Maximum 5 Mbps 25 MHz Maximum 4 Mbps f Xin 16 MHz Maximum 2 Mbps f Xin 8 MHz Transmit Receive control CTS function or RTS function can be selected by software Table 7 3 2 Functions of I O pins in clock synchronous serial I O mode Rumes Method of selection TxDi P83 P87 Serial data output Fixed Dummy data is output when performing only reception RxDi P82 P8e Serial data input Port P8 direction register s corresponding bit 0 P81 P8s Transfer clock output Internal Externalclock select bit 0 Transfer clock input Internal Exiernal clock select bit 1 CTS RTSi CTS input CTS RTS select 0 P80 P84 RTS output 5 815 select bit 1 Port P8 direction register Address 1416 Internal External clock select bit bit 3 at addresses 3016 3816 CTS RTS select bit 2 at addresses 3418 3C e Notes 1 The TxDi pin outputs H leve until transmission starts after operating mode is selected 2 RxDi pin can be used as a programmable I O port when performing only transmission 7702 7703 Group User s Manual 7 17 SERIAL I O 7 3 Clock synchronous serial I O mode 7 3 1 Transfer clock synchronizing clock Data transfer is performed synchronously with the transfer clock For the transfer clock the user can select whether to generate t
147. width is read out Fig 6 5 1 Structures of timer Bi mode register and timer Bi register in pulse period pulse width measurement mode 6 20 7702 7703 Group User s Manual TIMER B 6 5 Pulse period pulse width measurement mode 6 5 1 Setting for pulse period pulse width measurement mode Figure 6 5 2 shows an initial setting example for registers relevant to the pulse period pulse width measurement mode Note that when using interrupts set up to enable the interrupts For details refer to Chapter 4 INTERRUPTS 7702 7703 Group User s Manual 6 21 TIMER B 6 5 Pulse period pulse width measurement mode Selecting pulse period pulse width measurement mode and each function Y b7 00 I 110 Timer Bi mode register i 0 to 2 Addresses 5 to 5016 Selection of pulse period pulse width measurement mode Measurement mode select bits b3 b2 0 0 Pulse period measurement Interval between falling edges of measured pulse 0 1 Pulse period measurement Interval between rising edges of measured pulse 0 Pulse width measurement 1 1 1 1 Not selected Timer Bi overflow flag Note 0 No overflow 1 Overflow Count source select bits b7 b6 0 0 fe2 0 1 f16 164 1 1 512 Ne d Setting interrupt priority level Timer Bi interrupt controi register i 0 to 2 Addresses 7A16 to 7616 Interrupt priority level select bits When using in
148. 008016 e External area Internal RAM 00000916 00027F16 212 bytes i Internal RAM 00007F16 2048 bytes Notes 1 These can be used only in the microprocessor mode 2 Interrupt vector table is assigned to addresses OOFFD616 to OOFFFF 6 00087F 16 Set a HOM to this area Bank O16 External area External area Note 2 Note 2 OOFFFF16 01000016 Bank 116 O1FFFF16 FF000016 Bank FF16 FFFFFF16 Fig 5 Memory assignment during microprocessor mode 21 6 7702 7703 Group User s Manual APPENDIX Appendix 2 Memory assignment in SFR area Appendix 2 Memory assignment in SFR area Figures 6 to 9 show the memory assignment in SFR area The significations which are used in Figures 6 to 9 is described below Access characteristics RW It is possible to read the bit state at reading The written value becomes valid data RO It is possible to read the bit state at reading The written value becomes invalid WO The written value becomes valid data It is impossible to read the bit state Nothing is assigned It is impossible to read the bit state The written value is ignored otate immediately after a reset 0 0 immediately after a reset 1 1 immediately after a reset Undefined immediately after a reset Address Register name 016 116 216 316 416 516 616 716 816 916 A16 B16 C16 D16 E16 F16 1016 1116 1216 1316 1416 1516 1616 1716 1816 191
149. 03 Group User s Manual TIMER B 6 5 Pulse period pulse width measurement mode Precautions when operating in pulse period pulse width measurement mode 1 The timer Bi interrupt request occurs by the following two causes Input of measured pulse s valid edge Counter overflow When the overflow is the cause of the interrupt request occurrence the timer Bi overflow flag is set to 4 5 2 After reset the timer Bi overflow flag is undefined When writing to the timer Bi mode register with the count start bit 1 this flag can be cleared to 0 at the next count timing of the count source 3 An undefined value is transferred to the reload register when the first valid edge is input after the counter starts counting In this case the timer Bi interrupt request does not occur 4 The counter value at start of counting is undefined Accordingly the timer Bi interrupt request may occur by the overflow immediately after the counter starts counting 5 If the contents of the measurement mode select bits are changed after the counter starts counting the timer Bi interrupt request bit is set to 1 When writing the same value which has been set yet to the measurement mode select bits the timer Bi interrupt request bit iS not changed that is the bit retains the state 6 If the input signal to the pin is affected by noise tc the counter may not perform the exact measurement We recommend to verify by softw
150. 10 ns input low level pulse width o 1 10 J mns 8 ns thic a TxDi TxDihold time S time 0 0 ns _ RxDiinputsetuptime 7 30 30 External interrupt INTi input Symbol Parameter Unit tw INH INT input high level pulse width 250 250 ns INT input low level pulse width 250 250 J ns 15 10 7702 7703 Group User s Manual ELECTRICAL CHARACTERISTICS 15 5 Internal peripheral devices Internal peripheral devices tc TB lt gt m tw TBH input tc AD 5 tw ADL lt lt ADrna input N lt tc CK tw CKH lt gt CLKi input lt tw CKL y th C Q TxDi output RxDi input INTi input Test conditions Vcc 5 V 10 Input timing voltage Vi 1 0 V Viu 4 0 V Output timing voltage Vor 0 8 V Vor 2 0 V 7702 7703 Group User s Manual 15 11 ELECTRICAL CHARACTERISTICS 15 6 Ready and Hold 15 6 Ready and Hold Timing requirements Vcc 5 V 1096 Vss 0 V Ta 20 to 85 C unless otherwise noted Du a Me as tsu RDY 1 input setup time RDYinputsetuptime 00 setup time ns ome a a a a a a a a aa a o ns tw Roy RDY inputhold time ns tho HoLD HOLD input hold time ns Switching characteristics Vcc 5 10 Vss 0 V Ta 20 to 85 C unless
151. 101K However there is no device identification code Accordingly programming conditions must be set carefully Table 19 3 1 lists the pin correspondence with M5M27C101K Figures 19 3 1 and 19 3 2 show the pin connections in 1M mode Table 19 3 1 Pin correspondence with M5M27C101K M37702E2BXXXFP M5M27C101K M37702E2BFP M37702E2BFS Vcc VPP input VPP Vss Vss Address input 15 Data Do D7 CE input CE OE input P51 OE PGM input P50 PGM 19 6 7702 7703 Group User s Manual PROM VERSION 19 3 1M mode 1M mode top view VSS AVSS AVCC VCC a 4 VREF gt 4 P80 CTSo RTSo P77 AN7 ADTRG gt P81 CLKo 4 71 1 5 75 5 al P76 AN6 9 P82 RxDo P83 TxDo z NE 2 641 P84 CTS1 RTS1 P85 CLK1 gt P86 RxD1 gt P87 TxD1 PyP0d A0 PO1 A 4 P03 A3 04 4 5 5 As P06 A6 PO7 A7 P10 A8 D8 P11 A9 D9 P12 A10 D10 P13 A11 D11 P44 A12 D12 C A12 P15 A13 D13 16 14 014 P17 A15 D15 4 P20 A16 Do 3 P21 A17 D1 2 P22 A18 D2 P23 A19 D3 P60 TA4ouT Lo P57 TA3IN P5e TA3oUT P55 TA2IN P54 TA20uT 9 P53 TA1IN 9 CCED pso TA1ouT CaED P51 TAOIN P5o TAOoUT P47 P46 P45 20 P44 P43 42 1 41 lt gv N NO T NO UJ TI ddXX
152. 13 1 Hardware reset This chapter describes the method to reset the microcomputer There are two methods to do that Hardware reset and Software reset 13 1 Hardware reset When the power source voltage satisfies the microcomputer s recommended operating conditions the microcomputer is reset by supplying L level to the RESET pin This is called a hardware reset Figure 13 1 1 shows an example of hardware reset timing 2usormore 4to5 cycles of lt Internal processing sequence after a reset Program is executed pa pa A Note When the clock is stably supplied Refer to 13 1 4 Time supplying L level to RESET pin H RESET 4 Fig 13 1 1 Example of hardware reset timing The following explains how the microcomputer operates for terms to above After supplying L level to the RESET pin the microcomputer initializes pins within a term of several ten ns Refer to Table 13 1 1 While the RESET pin is L level and within the term of 4 to 5 cycles of the internal clock after the RESET pin goes from L to H the microcomputer initializes the central processing unit CPU and SFR area At this time the contents of the internal RAM area become undefined except when Stop or Wait mode is terminated Refer to Figures 13 1 2 to 13 1 6 After the microcomputer performs Internal processing sequence after reset Refer to Figur
153. 15 1 Absolute maximum ratings Absolute maximum ratings Symbol Ratings Unit 0 8 to 7 AVec oe 0 3 to 7 V Iputvolage RESET CNVss BYTE 031012 Vi Input voltage Pts P1 20 25 P4o P47 5 5 P6o P6 P7o P 77 P80 P87 Vner 0 3 to Vcc 0 3 XIN Vo Output voltage POo P07 P1o P17 2 2 P4o P 47 5 5 0 3 to VCC40 3 3 B 7 7 P80 P87 Xovr Pa Power 25 300 Note T opr Operating temperature ENS 20 to 85 T stg Storage temperature EEN 40 to 150 Note In the 7703 Group this value is 1000 mW 15 2 7702 7703 Group User s Manual ELECTRICAL CHARACTERISTICS 15 2 Recommended operating conditions 15 2 Recommended operating conditions Recommended operating conditions Vcc 5 V 10 20 to 85 C unless otherwise noted Symbol vax Uni Vcc Power source voltage V AVcc Analog power source voltage V Vss Power source voltage 0 V AVss Analog power source voltage 0 V High level input voltage POo P07 40 45 5 57 P7o0 P77 P80 P87 Xin RESET CNVss Once me y BYTE Vis High level input voltage 10 1 20 27 0 8Vcc Vec V in single chip mode High level input voltage ree Vin in memory expansion mode and 0 5 Vcc V microprocessor mode Low level input voltage POo
154. 16 4E16 Can be set to 0000 16 to FFFF e n P The counter divides the count source frequency by n 1 when down counting or by FFFFis 1 when up counting Continue to Figure 5 4 3 on next page Fig 5 4 2 Initial setting example for registers relevant to event counter mode 1 5 22 7702 7703 Group User s Manual TIMER A 5 4 Event counter mode From preceding Figure 5 4 2 f Setting interrupt priority level Timer Ai interrupt control register i 0 to 4 Addresses 7516 to 7916 Interrupt priority level select bits When using interrupts set these bits to level 1 7 When disabling interrupts set these bits to level 0 Setting port 5 and port P6 direction registers b7 b0 Port P5 direction register Address Die TA0our pin TAOIN pin TA10ur pin TAIN pin 2 pin TA2IN pin pin pin b7 bO Port P6 direction register Address 1016 TA40uT pin TA4IN Clear the bit corresponding to the pin to 0 When selecting the TAiour pin s input signal as up down switching factor set the bit corresponding to the TAiour pin to 0 When Selecting the two phase pulse signal processing function set the bit corresponding to the TAjour j 2 to 4 pin to 0 4 Setting the count start bit to 1 b7 Count start register Address
155. 1A ALE th ALE P1A De D15 7 4 4 BYTE L 2 P td E P2Q th E P2Q Address Data output 00 3 07 Data input Do D7 ALE output su Wen NEBE gt 10 ta R W E th E R W R W output ta E PiQ Port Pi output 1 4 8 Test conditions 1 E Test conditions P4 P8 Vcc 2 7 5 5 V Vcc 2 75 5 V Output timing voltage VoL 0 8 V 2 0 V Input timing voltage 0 2 V 0 8 V Data input 0 16 V 20 5 V Output timing voltage VoL 0 8 V Vor 2 0 V 7702 7703 Group User s Manual 18 29 LOW VOLTAGE VERSION 18 4 Electrical characteristics 18 30 Memory expansion mode microprocessor mode With Wait lt Read gt f Xin 0 E Address output Ao A7 Address output 15 BYTE Address Data output 15 015 BYTE Data input Ds D15 BYTE Address Data output 1 07 Data input Do D7 ALE output BHE output R W output Port Pi input i 4 8 eVcc 2 7 5 5 V Output timing voltage VoL 0 8 V 2 0 V tw L tw H tr te tc PURUS td E 6 1 td POA E gt td P1A E le gt lt td P1A ALE td E 01 tw EL Address Address tpxz E P12Z ta P1A E lt gt lt gt lt gt th ALE P1A ts
156. 1o P17 20 27 P30 P31 P33 P4c P47 VoL P5o P5 P7o P77 P8v P87 va Low level output voltage 0 0 1 1 20 27 P30 P31 P33 Low level output voltage VoL P3 Low level output voltage _ VoL E Hysteresis HOLD TAOm TA4n TBOn TB2n Vr Vr INVE INTo INT2 ADtra CTSo CTS CLKo Hysteresis XN 0o P07 P1o P17 20 27 P30 P33 P4o P47 P5o P57 P60 P67 P7o P 77 P80 P87 Xin RESET CNVss BYTE 0 0 P1o P17 20 27 P30 P33 P4o P47 P5o P57 P60 P67 P7o P 77 P80 P87 Xin RESET CNVss BYTE Vr Vr High level input current Low level input current liL VRAM lcc Power source current 18 10 MEN Hysteresis RESET 40 to 85 C unless otherwise noted Test conditions Voc 5 V 10 mA 31 Voc 5 V 400 uA 48 Vcc 3 V lou 1mA 26 5 V lou 10 mA 34 Vcc 5 V lon 400 uA 48 Vcc 3 V lou 1mA 26 Vcc V 1 mA 0 5 Vcc 5 V lou 2mm A 0 45 5 19 5 2 1043 2 44 1 04 Me lo 10mA 16 5 04 Vce 3V l 1 mA 1 04 1 0 1 0 7 Mcc 5V 02 05 01 04 Veoo 5V 01 O03 Vee 3V 006 02 Vcc 5 V Vi 5 5 0 NE Vcc 0 RAM hold voltage When clock is stoppe
157. 2 Di Do L p7 De Ds D4 0 02 01 Do ESI p pe os bs ps pe gt 01 ESSERE 1271 ds 95 64 93 0 ARRRRRRRI mammzmumum gt Fig 7 3 4 Transmit operation A Transfer clock Transmit enable bit 0 Data is set in transmit buffer register Transmit buffer T empty flag n Y UARTi transmit register UARTI transmit buffer register CTSi Stopped because CTSi H Stopped because transmit enable bit 0 TxDi Transmit register 1 empty flag n UARTi transmit 1 interrupt request bit p Cleared to 0 when interrupt request is accepted or cleared by software The above timing diagram applies to Tenni Next transmit conditions are examined when this signal level is the following conditions TENDi is an internal signal Accordingly it cannot be read from an external Internal clock selected Tc 2 n 1 CTS function selected fi BRGi count source frequency f2 f16 fe4 f512 n Value set to BRGi Fig 7 3 5 Example of transmit timing when selecting internal clock 7 24 7702 7703 Group User s Manual SERIAL I O 7 3 Clock synchronous serial mode 7 3 4 Method of reception Figures 7 3 6 and 7 3 7 show initial setting examples for relevant registers when receiving Reception is started when all of the following conditions to G are satisfied When an external clock is selec
158. 25 fn T jaa di ERROR rw poses mam roi esa ene T NLS CL Y J LO I T j X3 T ERROR mw 18 34 7702 7703 Group User s Manual LOW VOLTAGE VERSION 18 6 Application 18 6 Application Some application examples of connecting external memorys for the low voltage version are described bellow Applications shown here are just examples Modify the desired application to suit the user s need and make sufficient evaluation before actually using it 18 6 1 Memory expansion The following items of the low voltage version are the same as those of section 17 1 Memory expansion However a part of the formulas and constants for parameters is different Memory expansion model Formulas for address access time of external memory timing Memory expansion method Address access time of external memory ta AD ta AD td POA P1A P2A E tw EL tsu P2D P1D E address decode time address latch delay time td POA P1A P2A E td POA E td P1A E Or td P2A E tsu P2D P1D E tsu P2D E Or tsu P1D E address decode time time necessary for validating a chip select signal after an address is decoded address latch delay time delay time necessary for latching an address This is not necessary on the minimum model Data setup time of external memory for writing data tsu D tsu D tw EL td E P2Q P1Q td E P2Q P1Q td
159. 25 MHz T 55 MHz Unit 3 73 a a E T A ns Pont P1 address hold ime BYTE Lj ns Ikei Port P1 data hold time BYTE 257 __ s _ ns tpxe piz _ Port P1 floating release delay time BYTE L 36 18 ns th E P1A Port P1 address hold time BYTE ra 18 ns ns Port ns tpxe paz _ Port P2 floating release delay time 36 18 ns _ ns herw R Wholdtime 1 18 18 ns Notes 1 For the M37702bE2AXXXFP M37702bE2AFS M37702EAAXXXFP and M37702E4AFS refer to section 19 5 4 Bus timing and EPROM mode For the M37703E2AXXXSP and M37703EAAXXXSP refer to section 20 6 2 Bus timing and EPROM mode 2 For test conditions refer to Figure 15 10 1 This is the value depending on f Xin For data formula refer to Table 15 9 1 Table 15 9 1 Bus timing data formula f Xw lt 8 MHz 8 MHz lt 16 MHz 16 MHz lt lt 25 MHz lw EL 4 X 10 50 9 1 10 1 2 X 10 1 X 10 ta P1A E 100 125 30 75 A0 ta P2A i XIN f XIN la P1A ALE 1 1x10 1 10 1 X 10 35 ta P2A ALE tw ALE M 1 X 10 1 X 10 f XIN XN 7275 718 1 1 X 10 1 2 X 10 2 12 10 ta R W E 100 125 30 XN 75 ot f XIN th E PoA
160. 250 Hz 48 8281 kHz 5 6 3 Trigger When a trigger is generated the TAiour pin starts outputting PWM pulses An internal or an external trigger can be selected as that trigger An internal trigger is selected when the trigger select bits bits 4 and 3 ai addresses 5616 5A e are 002 O12 an external trigger is selected when the bits are 102 or 112 A trigger generated during outputting of PWM pulses is ignored and it does not affect the pulse output operation 1 When selecting internal trigger A trigger is generated when writing 1 to the count start bit at address 4016 2 When selecting external trigger A trigger is generated at the falling of the 5 input signal when bit 3 at addresses 56 e to 16 is 0 or at its rising when bit 3 is 1 However the trigger input is accepted only when the count start bit is 1 When using an external trigger set the port P5 and P6 direction registers bits which correspond to the TAiw pins for the input mode 7702 7703 Group User s Manual 5 43 TIMER A 5 6 Pulse width modulation PWM mode 5 6 4 Operation in PWM mode When the PWM mode is selected with the operating mode select bits the TAiour pin outputs L level When a trigger is generated the counter pulse width modulator starts counting and the TAiour pin outputs a PWM pulse Notes 1 and 2 The timer Ai interrupt request bit is set to 1 each time the P
161. 3 gt 56 X254 256 x255 VREF Analog input voltage Fig 8 3 1 Ideal A D conversion characteristics 7702 7703 Group User s Manual 8 1 1 A D CONVERTER 8 4 Absolute accuracy and differential non linearity error 8 4 Absolute accuracy and differential non linearity error The A D converter s accuracy is described below 8 4 1 Absolute accuracy The absolute accuracy is the difference expressed in the LSB between the actual A D conversion result and the output code of an A D converter with ideal characteristics The analog input voltage when measuring the accuracy is assumed to be the mid point of the input voltage width that outputs the same output code from an A D converter with ideal characteristics For example when Vner 5 12 V 1 LSB width is 20 mV and 0 mV 20 mV 40 mV 60 mV 80 mV are selected as the analog input voltages The absolute accuracy 3 LSB indicates that when the analog input voltage is 100 mV the output code expected from an ideal A D conversion characteristics is 00516 however the actual A D conversion result is between 002 e to 00816 The absolute accuracy includes the zero error and the full scale error The absolute accuracy degrades when Vner is lowered The output code for analog input voltages Vner to AVcc is Output code A D conversion result 16 16 0916 4 Fd 4
162. 33222 nak lt lt lt lt lt i co cO cO Z KEE 6k Sk FE S A a A zt 7702 7703 Group User s Manual RDY gt R CNVss 1 26 4 BY TE 2 4 gt 40 1 Connect these pins to Vss pin the single chip mode These pins have different functions between the single chip and the memory expansion micropro cessor modes 40 lt gt 20 04 39 4 21 05 381 gt A22 D6 371 23 07 3 RW 35 34 ALE 33 HLDA Vss gt E 30 29 4 XIN 28 43 RESET CNVss 2 lt BYTE 25 HOLD 2 This pin functions as 1 in the microprocessor mode These pins have different functions between the single chip and the memory expansion micropro cessor modes Fig 2 5 2 Pin configuration in each processor mode top view 2 23 CENTRAL PROCESSING UNIT CPU 2 5 Processor modes Table 2 5 1 Functions of ports PO to P4 in each processor mode Processor E modes Single chip mode Memory expansion Microprocessor mode ins PO XP P Functions as a programmable I O port P1 E pP yo e When external data bus width is 16 bits BYTE L P Functions as a programmable D odd I O port D odd Data at odd address When external data bus width is 8 bits BYTE H As A15 P2 B X When external data bus width is 16 bits BYTE L P Functions as a programmable D even D even
163. 4016 Timer AO count start bit Timer A1 count start bit Timer A2 count start bit Timer A3 count start bit C L Timer A4 count start bit d Count starts Fig 5 4 3 Initial setting example for registers relevant to event counter mode 2 7702 7703 Group User s Manual 5 23 TIMER A 5 4 Event counter mode 5 4 2 Operation in event counter mode When the count start bit is set to 1 the counter starts counting of the count source The counter counts the count source s valid edges When the counter underflows or overflows the reload register s contents are reloaded and counting continues The timer Ai interrupt request bit is set to 1 when the counter underflows or overflows The interrupt request bit remains set to 1 until the interrupt request is accepted or the interrupt request bit is cleared to O by software Figure 5 4 4 shows an example of operation in the event counter mode n Reload register s contents FFFF16 Counter contents Hex 000016 Set to 1 by software Count start bit 1 Up down bit 1 Timer Ai interrupt 1 request bit Cleared to 0 when interrupt request is accepted or cleared by software Note The above applies when the up down bit s contents are selected as the up down switching factor i e up down switching factor select bit O Fig 5 4 4 Example of operation in e
164. 416 UART1 transmit receive control register 0 Address 3 16 b7 bO ee BRG count source select bits b1b0 00 12 1 4116 10 64 11 f512 OTS RTS select bit 0 CTS function selected 1 RTS function selected d UARTO baud rate register BRGO Address 3116 UART1 baud rate register BRG1 Address 3916 bO Set to 001610 FFt16 aT P8 direction register Address 1416 gt b7 00 RxDo pin RxD1 UARTO receive interrupt control register Address 7216 UART1 receive interrupt control register Address 7416 Interrupt priority level select bits When using interrupts set these bits to level 1 7 When disabling interrupts set these bits to level 0 UARTO transmit receive control register 1 Address 3516 UART1 transmit receive control register 1 Address 3D16 b7 00 Receive enable bit 1 Reception enabled Reception starts when the start bit is detected Fig 7 4 8 Initial setting example for relevant registers when receiving 7702 7703 Group User s Manual 7 47 SERIAL I O 7 4 Clock asynchronous serial I O UART mode When not using interrupts UARTO transmit receive control register 1 Address 3516 UART1 transmit receive control register 1 Address 3D16 b7 bO PTET ttt Receive complete flag 0 Reception not completed 1 Reception completed p hecking completi
165. 5 V Input timing voltage Vi 0 2 V 0 8 V Output timing voltage Vo 0 8 V 2 0 V 7702 7703 Group User s Manual 18 17 LOW VOLTAGE VERSION 18 4 Electrical characteristics 18 4 6 Ready and Hold Timing requirements Vcc 2 7 5 5 V Vss 0 V Ta 40 to 85 C unless otherwise noted 90 tsuRov o input setup time 90 ns tsu HoLD HOLD input setup time ns RDY input hold time 0 ns th Howp HOLD input hold time 0 ns Switching characteristics Vcc 2 7 5 5 V Vss 0 V Ta 40 to 85 C unless otherwise noted Limits Symbol Parameter Unit y la o HLDA HLDA output delay time 120 ns Note For test conditions refer to Figure 18 4 1 18 18 7702 7703 Group User s Manual LOW VOLTAGE VERSION 18 4 Electrical characteristics Ready With no Wait 1 E output RDY input tsu RDY 1 lt gt With Wait 1 E output RDY input Test conditions Vcc 2 7 5 5 V eInput timing voltage 0 2 V Viri 0 8 V Output timing voltage VoL 0 8 V Vou 2 0 V 1 RDY isu RDY 61 th 6 1 RDY gt e 7702 7703 Group User s Manual 18 19 LOW VOLTAGE VERSION 18 4 Electrical characteristics Hold 1 tsu HOLD 6 1 th 1 HOLD gt gt HOLD input 1 HLDA td 1 HLDA lt gt HLDA out
166. 6 1A16 1 16 1C16 1D16 1E16 1F16 Port PO register Port P1 register Port PO direction register Port P1 direction register Port P2 register Port P3 register Port P2 direction register Port P4 register Port P5 register Port P4 direction register Port P5 direction register Port P6 register Port P7 register Port P6 direction register Port P7 direction register Port P8 register Port P8 direction register A D control register o Always 0 at reading Always undefined at reading 0 immediately after a reset Fix this bit to 0 Access characteristics State immediately after a reset b7 00 In the 7703 Group set 1 to the bit of which corresponding pin is nothing Refer to section 20 4 1 Input Output pins Fig 6 Memory assignment in SFR area 1 7702 7703 Group User s Manual 21 APPENDIX Appendix 2 Memory assignment in SFR area Address Register name b Access characteristics M State immediately after a 2016 A D register 0 2116 2216 A D register 1 2316 2416 A D register 2 2516 2616 A D register 3 2716 2816 A D register 4 2916 2 16 A D register 5 2B16 2 16 A D register 6 2016 2E16 A D register 7 OF 16 3016 UARTO transmit receive mode register 3116 UARTO baud rate register 3216 UARTO transmit buffer register 3316 2127172 1 3416 UARTO transmit receive control register 0 3516 UARTO transmit receive control register 1 3616 e UARTO
167. 6 INTo interrupt contro register 7E16 INT interrupt contro register 7F16 INT2 interrupt control register Access characteristics N oO O D HW JJ LETTE ET Ey j2_ Ess l EK 3 _ RW E 20 20 JJ HW State immediately after a reset b7 00 Note 5 By writing dummy data to address 6016 a value FFF16 is set to the watchdog timer The dummy data is not retained anywhere Note A value FFF16 is set to the watchdog timer Refer to Chapter 9 WATCHDOG Fig 9 Memory assignment in SFR area 4 21 10 7702 7703 Group User s Manual APPENDIX Appendix 3 Control registers Appendix 3 Control registers The register structure of each control register assignment in the SFR area are shown on the following pages The view of the register structure is described below x 2 553 0 1 Undefined RW RO WO x XXX register Address XX1e6 MR 553 w 4 This bitis ignoredin mode RW 4 Set to 0 or 1 to meet the purpose Set to 0 at writing Set to 1 at writing This bit is not used in the specific mode or state It may be either 0 or 1 Nothing is assigned 0 immediately after a reset 1 immediately after a reset Undefined immediately after a reset It is possible to read the
168. 7 w AC 573 teu lt gt ACOA teu 95 min AC32 1 lt gt talaD 1 AC 32 gt lt lisu P1D P2D E gt 80 210 min 50 min 130 max lt gt 32 tsu D gt 40 9 15 min lt AC32 AC573 tPHL AC04 Fig 18 6 8 Timing diagram on maximum model 18 42 7702 7703 Group User s Manual Unit ns LOW VOLTAGE VERSION 18 6 Application 18 6 5 Ready generating circuit example When validating Wait only for a certain area for example ROM area in Figures 18 6 3 to 18 6 8 use Ready function Figure 18 6 9 shows a Ready generating circuit example M37702 Data bus Address gt CS latch CoU m circuit circuit gt Address bus RDY signal falling timing AC D Q d gt 7o T Wait by ready is inserted in only area accessed by CE Term expanded by RDY input Fig 18 6 9 Ready generating circuit example 7702 7703 Group User s Manual 18 43 LOW VOLTAGE VERSION 18 6 Application MEMORANDUM 18 44 7702 7703 Group User s Manual CHAPTER 19 PROM VERSION 19 1 Overview 19 2 EPROM mode 19 3 1M mode 19 4 256K mode 19 5 Usage precaution PROM VERSION 19 1 Overview This chapter describes the PROM version inc
169. 702 Group except for some functions This chapter mainly describes the differences between the 7703 and 7702 Groups Refer to the relevant descriptions of the 7702 Group about the common functions 20 1 Description The 16 bit single chip microcomputers 7703 Group is suitable for office business and industrial equipment controllers that require high speed processing These microcomputers develop with the M37703M2BXXXSP as the base chip This manual describes the functions about the M37703M2BXXXSP unless there is a specific difference and the M37703M2BXXXXSP is referred to as 37703 20 2 7702 7703 Group User s Manual 7703 GROUP 20 2 Performance overview 20 2 Performance overview Table 20 2 1 lists the performance overview of the M37703 Table 20 2 1 M37703 performance overview Parameters Functions Number of basic instructions 103 Instruction execution time 160 ns the minimum instruction at f Xin 25 MHz M37703M2AXXXSP 250 ns the minimum instruction at f Xw 16 MHz External clock input frequency M37703M2BXXXSP 25 MHz maximum M37703M2AXXXSP 16 MHz maximum Memory size ROM 16384 bytes Programmable Input Output PO P1 P2 P5 8 bits X 4 ports PP bits X 1 P4 P6 P7 4 bits X 3 P3 bits 1 Multifunction timers TAO TA4 16 bits X With I O functionX 4 TBO TB2 16 bits X 3 With Input functionX 1 Serial I O UARTO UART1 UART X 2 UARTO also as clock synchronous serial I O A D converter 8 bit successive
170. AL I O 7 3 Clock synchronous serial I O mode When not using interrupts Checking start of transmission UARTO transmit interrupt control register Address 7116 UART1 transmit interrupt control register Address 7316 b7 60 Interrupt request bit 0 No interrupt request 1 Interrupt request Transmission has 5 Checking completion of transmission UARTO transmit receive control register O Address 3416 UART1 transmit receive control register 0 Address 3C16 bO Transmit register empty flag 0 During transmitting 1 Transmitting completed C Processing at completion of transmission Fig 7 3 3 Detection of transmission s completion When using interrupts The transmit interrupt request occurs when the transmission starts transmit interrupt Note This figure shows the bits and registers required for processing Refer to Figure 7 3 5 about the change of flag state and the occurrence timing of an interrupt request 7 22 7702 7703 Group User s Manual SERIAL I O 7 3 Clock synchronous serial mode 7 3 3 Transmit operation When the transmit conditions described in page 7 19 are satisfied the following operations are automatically performed simultaneously transmit buffer register s contents are transferred to the UARTi transmit register 8 transfer clocks are generated when an internal clock is
171. AN LIBE 19 05 B CE 21 34 7702 7703 Group User s Manual APPENDIX Appendix 5 Countermeasures against noise Appendix 5 Countermeasures against noise The following describes some examples of countermeasures against noise Although the effect depends on the system refer to the following if the problem being relevant to noise occurs 1 Reduction in wiring length Wiring on a circuit board can serve as an antenna that pulls in noise into the microcomputer Shorter the total length of wiring in mm the smaller the possibility of pulling in noise into the microcomputer 1 Wiring of RESET pin Reduce the length of wiring connected to the RESET pin Especially a capacitor that is inserted between the RESET and Vss pins must be connected to these pins in the shortest possible distance within 20 mm Reasons If noise gets into the RESET pin the microcomputer will restart op M37702 erating before its internal state is completely initialized which can cause a program runaway circuit Vss M37702 Reset circuit Fig 10 Wiring of RESET pin 7702 7703 Group User s Manual 21 35 APPENDIX Appendix 5 Countermeasures against noise 2 Wiring of clock input output pins Reduce the length of wiring connected to the clock input output pins Connect the lead wire on the ground side of a capacitor connected to the oscillator and the microcomputer s Vss pin in the shortest possible dista
172. B B 0XH 007XH Write to interrupt priority level select bits Note All instructions other than instructions for writing to address 7X16 which have the same cycles as NOP instruction can also be inserted Confirm the number of instructions to be inserted by Table 4 11 1 Fig 4 11 1 Program example to reserve time required for changing interrupt priority level Table 4 11 1 Relation between number of instructions to be inserted with program example of Figure 4 11 1 and interrupt priority detection time select bits Interrupt priority detection time select bits Note Interrupt priority level Number of inserted 05 detection time instructions 0 7 cycles of NOP instruction 4 or more 0 NI i 4 cycles of NOP instruction 2 or more 1 000200000 2 cycles of NOP instruction 1 or more a ae Do not select Note We recommend 65 1 b4 07 4 26 7702 7703 Group User s Manual CHAPTER 5 TIMER A 5 1 Overview 5 2 Block description 5 3 Timer mode 5 4 Event counter mode 5 5 One shot pulse mode 5 6 Pulse width modulation PWM mode TIMER A 5 1 Overview Timer A is used primarily for output to externals It consists of five counters timers AO to A4 each equipped with a 16 bit reload function Timers AO to A4 operate independently of one another 7703 Group Timer A4 s function of the 7703 Group varies from the 7702 Group s Refer to Chapter 20 7703 GROUP 5 1 Overview
173. D conversion is completed after 57 cycles of Then the contents of the successive approximation register conversion result are transferred to the register i 3 At the same time as step the A D conversion interrupt request bit is set to 1 The A D conversion stops operation The A D conversion start bit remains set to 1 after the operation is completed Accordingly the operation of the A D converter can be performed again from step when the level of the ADrne pin changes from H to L When the level of the ADtra pin changes from to L during operation the operation at that point is cancelled and is restarted from step Figure 8 5 2 shows the conversion operation in the one shot mode Trigger occur Conversion result Convert input voltage from o A D register ANi pin A D conversion interrupt request occurs A D converter stops Fig 8 5 2 Conversion operation in one shot mode 7702 7703 Group User s Manual A D CONVERTER 8 6 Repeat mode 8 6 Repeat mode In the repeat mode the operation for the input voltage from the one selected analog input pin is performed repeatedly In this mode no A D conversion interrupt request occurs Additionally the A D conversion start bit bit 6 at address 1E e remains set to 1 until it is cleared to 0 by software and the operation is performed repeatedly while the A D conversion start bit is 1
174. Data at even address e When externa data bus width is 8 bits BYTE H D Data P3 3 HLDA Note 4 P Functions as a programmable P3 gt ALE I O port P31 BHE P30 R W P4 Pp A X P X P Functions as a programmable P Functions as a programmable port I O port Note 1 P42 1 Note 2 P4 HOLD Notes 1 P42 also functions as the clock 1 output pin Refer to Chapter 12 CONNECTION WITH EXTERNAL DEVICES 2 P4 functions as a programmable port in the memory expansion mode and that functions as the clock 1 output pin by software selection Refer to Chapter 12 CONNECTION WITH EXTERNAL DEVICES 3 This table lists a switch of pins functions by switching the processor mode Refer to the following section about the input output timing of each signal Chapter 12 CONNECTION WITH EXTERNAL DEVICES Chapter 15 ELECTRICAL CHARACTERISTICS 4 The 7703 group does not have P33 HLDA pin P4 2 24 7702 7703 Group User s Manual CENTRAL PROCESSING UNIT CPU 2 5 Processor modes 2 5 3 Setting processor modes The voltage supplied to the CNVss pin and the processor mode bits bits 1 and 0 at address 5E e set the processor mode e When Vss level is supplied to CNVss pin After a reset the microcomputer starts operating in the single chip mode The processor mode is switched by the processor mode bits after the microcomputer starts operating When the
175. EB or CLB instruction when setting the INTi interrupt control register i 0 to 2 2 Perform the above setting separately Do not perform 2 or more setting at the same time with 1 instruction Fig 4 10 5 Switching flow of occurrence factor of INTi interrupt request 7702 7703 Group User s Manual 4 25 INTERRUPTS 4 11 Precautions when using interrupts 4 11 Precautions when using interrupts 1 Use the SEB or CLB instruction when setting the interrupt control registers addresses 7016 to TF 16 2 change the interrupt priority level select bits bits O to 2 at addresses 7016 to 7F e 2 to 7 cycles of are required after executing an write instruction until completion of the interrupt priority level s change Accordingly it is necessary to reserve enough time by software when changing the interrupt priority level of which interrupt source is the same within a very short execution time consisting of a few instructions Figure 4 11 1 shows a program example to reserve time required for changing interrupt priority level The time for change depends on the interrupt priority detection timer select bits bits 4 and 5 at address 5 Table 4 11 1 lists the relation between the number of instructions to be inserted with program example of Figure 4 11 1 and the interrupt priority detection time select bits SEB B 0XH 007XH Write to interrupt priority level select bits NOP Insert NOP instruction Note NOP NOP CL
176. ER INPUT OUTPUT PINS 3 1 Programmable ports 3 2 1 0 pins of internal peripheral devices INPUT OUTPUT PINS 3 1 Programmable I O ports This chapter describes the programmable ports in the single chip mode For PO to P4 which change their functions according to the processor mode refer also to the section 2 5 Processor modes and Chapter 12 CONNECTION WITH EXTERNAL DEVICES P4 and P5 to P8 also function as the I O pins of the internal peripheral devices For the functions refer to the section 3 2 I O pins of internal peripheral devices and relevant sections of each internal peripheral devices 7703 Group The 7703 Group varies with the 7702 Group in the number of pins pins assignment and others Refer to the section Chapter 20 7703 GROUP 3 1 Programmable I O ports The 7702 Group has 68 programmable ports PO to The programmable I O ports have direction registers and port registers in the SFR area Figure 3 1 1 shows the memory map of direction registers and port registers Addresses 246 Port PO register 316 Port P1 register 416 Port PO direction register 516 Port P1 direction register 616 Port P2 register 71e Port P3 register 816 Port P2 direction register 916 direction register Aig Port P4 register Bie Port P5 register C16 Port P4 direction register D16 Port P5 direction register Fig Port P6 register Fig Port P7 register 1016 Port
177. ESSING UNIT CPU 2 5 Processor modes Table 2 5 2 Methods for setting processor modes Processor mode CNVss pin level Processor mode bits A b0 Memory expansion mode Bv o TL S V Note 1 Vss 0 V Note 1 0 1 Microprocessor mode E Miele 0 Vcc s V Note 2 Notes 1 The microcomputer starts operating in the single chip mode after a reset The microcomputer can be switched to the other processor modes by setting the processor mode bits 2 The microcomputer starts operating in the microprocessor mode after a reset The microcomputer cannot operate in the other modes so that fix the processor mode bits as follows b1 1 and bO 0 67 b6 b5 b4 b2 bl Processor mode register Address 5E16 CET mode Memory expansion mode Microprocessor mode Not selected dicen Software Wait is inserted when accessing external area No software wait is inserted when accessing external area The microcomputer is reset by WO writing 1 to this bit The value is 0 at reading b5 b4 0 0 7 cycles of 0 1 4 cycles of 2 cycles of 0 Not selected bz Fix this bit to 0 w Clock 1 output select bit 0 Clock 6 1 output disabled RW Note 2 P42 functions as a programmable I O port 1 Clock 6 output enabled P42 functions as a clock 9 out put pin Notes 1 While supplying the Vcc leve
178. Fie d Necessary only when an internal clock is selected Continued to Figure 7 3 7 on next page Fig 7 3 6 Initial setting example for relevant registers when receiving 1 7 26 7702 7703 Group User s Manual SERIAL 7 3 Clock synchronous serial mode From preceding Figure 7 3 6 Port P8 direction register Address 1416 C RxD1 pin UARTO receive interrupt control register Address 7216 UART1 receive interrupt control register Address 7416 Interrupt priority level select bits When using interrupts set these bits to level 1 7 lt When disabling interrupts set these bits to level O P UARTO transmit buffer register Address 3216 UART1 transmit buffer register Address 3A16 b7 00 Set dummy data here UARTO transmit receive control register 1 Address 3516 UART1 transmit receive control register 1 Address 3D16 b7 bO 1 Transmit enable bit 1 Transmission enabled Receive enable bit 1 Reception enabled Note When selecting the internal clock set this register with either of the following setting Set the receive enable bit and the transmit enable bit to 1 simultaneously Set the receive enable bit to 1 and next the transmit enable bit to 1 Reception starts Fig 7 3 7 Initial setting example for relevant registers when receiving 2 7702 7703 Group User s Manual 7 27 SERIAL I
179. Invalid level Timer Ai interrupt 1 request bit 0 i The counter counts when the count start bit 1 and the TAi pin s input signal is at the count valid ae Cleared to 0 when level wmm Interrupt request Is 2 The counter stops counting while the TAiin pin s input signal is not at the count valid level and the im cleared counter value is retained by software Fig 5 3 5 Example of operation selecting gate function 5 16 7702 7703 Group User s Manual TIMER A 5 3 Timer mode 2 Pulse output function The pulse output function is selected by setting the pulse output function select bit bit 2 at addresses 5616 to 5Aie to 1 When this function is selected the TAiour pin is forcibly set for the pulse output pin regardless of the corresponding bits of the port P5 and port P6 direction registers The TAiour pin outputs pulses of which polarity is inverted each time the counter underflows When the count start bit address 4016 is O count stopped the TAiour pin outputs L level Figure 5 3 6 shows an example of operation selecting the pulse output function n Reload register s contents FFFF16 Starts counting Starts counting Restarts counting counter contents Hex 000016 Set to 1 by software Cleared to 0 by software Set to 1 by software Count start bit 1 Pulse output from TAiout
180. LE aX Xp Address Address y A _ _ Address X Address y A16 0 423 07 X Address X Data X Address X Data A KL _ X 8 bit data access A y 16 bit data access Note When accessing 16 bit data 2 times of access are performed in the sequence of the low order 8 bits and high order 8 bits Fig 12 1 6 Example of operating waveforms of signals input and output to from externals 2 12 10 7702 7703 Group User s Manual CONNECTION WITH EXTERNAL DEVICES 12 2 Software Wait 12 2 Software Wait Software Wait provides a function to facilitate access to external devices that require a long access time To select the software Wait use the wait bit bit 2 at address 5E e Figure 12 2 1 shows the structure of the processor mode register address 5E e Figure 12 2 2 shows an example of bus timing when the software Wait is used Software Wait is valid only for the external area The internal areas is always accessed with no Wait b7 b6 b5 b4 b2 bli To TTT 11 Processor mode register Address 5E 16 I I I i i Processor mode bits i I I I b1 bO 0 0 Single chip mode 0 1 Memory expansion mode 0 Microprocessor mode 0 RW 1 1 Not selected Note1 2 Wait bit Software Wai is inserted when RW accessing external area No software Wait is inserted when accessing external area Software reset bit The microcomputer is reset by WO writing i
181. LXXXGP has the same functions as the M37702M2BXXXFP except for the power on reset conditions Power on reset conditions are described below For the other functions refer to chapters 2 CENTRAL PROCESSING UNIT to 14 CLOCK GENERATING CIRCUIT 18 6 7702 7703 Group User s Manual LOW VOLTAGE VERSION 18 3 Functional description 18 3 1 Power on reset conditions Figure 18 3 1 shows the power on reset conditions and Figure 18 3 2 shows an example of power on reset circuit For details of reset refer to Chapter 13 RESET Fig 18 3 1 Power on reset conditions M37702M2LXXXGP In the case of Ca 0 07 uF delay time td is about 10 ms 0 152 X Ca us Ca Fig 18 3 2 Example of power on reset circuit 7702 7703 Group User s Manual 18 7 LOW VOLTAGE VERSION 18 4 Electrical characteristics 18 4 Electrical characteristics The electrical characteristics of M37702M2LXXXGP and M37702M2LXXXHP is described below For the latest data inquire of addresses described last CONTACT ADDRESSES FOR FURTHER INFORMATION 18 4 1 Absolute maximum ratings Absolute maximum ratings Symbol Ratings Unit Vcc 0 3 to 7 MEE input voltage RESET CNVss BYTE 031012 Vi Input voltage 50 PO P2o P27 P4o P47 5 5 P6o P6 7 7 P80 P87 Vner Vo Output voltage POo P0 P1o P17 2 2
182. M ASA DIR A DIR DIR AIMM ABS ABS A ABL CMP DEC JMP DEC CLM STP DER IA CSR Y A DIR X DIR X 5 ans A ABS X ABS X A ABL X CPX SBC SBC CPX SBC INC SBC SBC INC SBC lA DIR X ASR DIR ADIR DIR JAL DIR A IMM ABS AABS ABS A ABL SBC SBC SBC SBC INC SBC SBC F PLX PUL A DIR YIA DIR IA SR Y A DIR X DIR X A ABS Y 5 ABS X A ABL Note 42 specifies the contents of the INSTRUCTION CODE TABLE 2 About the second word s codes refer to the INSTRUCTION CODE TABLE 2 2 89 specifies the contents of the INSTRUCTION CODE TABLE 3 About the third word s codes refer to the INSTRUCTION CODE TABLE 2 notation gt 7702 7703 Group User s Manual 21 55 APPENDIX Appendix 7 Hexadecimal instruction code table ene CODE TABLE 2 The first word s code of each instruction is 42 4 ORA ORA ORA ORA ORA ASL ORA ORA B DIR X B SR B DIR B L DIR B IMM B ABS B ABL ORA ORA ORA ORA ORA ORA DEC ORA ORA TBS eRe DIR B SR Y B DIR X B L DIR B ABS Y B ABS X B ABL X AND AND AND AND AND AND B DIR X B SR B DIR B L DIR B IMM B M B ABL AND AND AND AND AND AND 3 B DIR Y B CDIR B CSR Y B DIR X e B ABS Y 5 B ABL X o leo B DIR 11 12112 EOR EOR EOR EOR EOR EOR EOR EOR TBD B DIR Y B DI
183. Negative flag Processor interrupt priority level Fig 2 1 1 CPU registers structure 2 2 7702 7703 Group User s Manual CENTRAL PROCESSING UNIT CPU 2 1 Central processing unit 2 1 1 Accumulator Acc Accumulators A and B are available 1 Accumulator A A Accumulator A is the main register of the microcomputer The transaction of data such as calculation data transfer and input output are performed mainly through accumulator It consists of 16 bits and the low order 8 bits can also be used separately The data length flag m determines whether the register is used as a 16 bit register or as an 8 bit register Flag m is a part of the processor status register which is described later When an 8 bit register is selected only the low order 8 bits of accumulator A are used and the contents of the high order 8 bits is unchanged 2 Accumulator B B Accumulator B is a 16 bit register with the same function as accumulator A Accumulator B can be used instead of accumulator A The use of accumulator B however except for some instructions requires more instruction bytes and execution cycles than that of accumulator A Accumulator B is also controlled by the data length flag m just as in accumulator A 2 1 2 Index register X X Index register X consists of 16 bits and the low order 8 bits can also be used separately The index register length flag x determines whether the register is used as a 16 bit register or as an 8 bit
184. OM mode 15 18 7702 7703 Group User s Manual ELECTRICAL CHARACTERISTICS 15 8 Memory expansion mode and microprocessor mode with no Wait Memory expansion mode and microprocessor mode With no Wait lt Write gt f Xin 1 E Address output Ao A7 Address output 15 Address Data output As Ds At15 D15 BYTE L Data input Ds D15 BYTE L Address Data output A16 Do A23 D7 Data input Do D7 ALE output BHE output R W output Port Pi output i 4 8 Test conditions 1 E PO P3 eVcc 5 V 10 Output timing voltage Vol 0 8 V VoH 2 0 V Vi 0 8 V 2 5 V Data input tr t tc gt lt td E ld E 61 tw EL td P0A gt p C Address td P1A E gt th E P1A Aes ld P1A E lt gt lt ta E P10 NN th E P1Q lt Ed td P1A ALE th ALE P1A td P2A E ta E P2Q th E P2Q td P2A ALE th ALE P2A Test conditions P4 P8 Vcc 5 V 10 Input timing voltage Output timing voltage 7702 7703 Group User s Manual 1 0 V VIH 4 0 V VoL 0 8 V Vor 2 0V 15 19 ELECTRICAL CHARACTERISTICS 15 8 Memory expansion mode and microprocessor mode with no Wait Memory epxansion mode and microprocessor mode With no Wait
185. PCy AD H 1 APPENDIX Appendix 8 Machine instructions Addressing moda ae E s ABL ABL X ABS ABS X muc a mala ate TEHE icon TIBERI TET SE hi Diii 11 ii EEEE 17 LLLELLEL pep 1 ili iil Wr 30 il 2d Ue ttt tT 7702 7703 Group User s Manual 21 61 2005088 slaius nmm APPENDIX Appendix 8 Machine instructions Addressing mode DIF b CDIR X 1 DIRI Wi LOM M Ent rg the immediate value into the memory 8 Enters the contents of tha memory the accumulator Note 1 2 LOT DT IMM Enters the immediate value inta the date bank register LDX Enters the contanta of the mamory Into index register X Nate 2 LEY Enters the contends of the mamay into indes register Y Note 2 LSR Shiite the contents of the accumulator or the contents da 7 z Nate 1 TR the memory bit the right The bit 0 of the accumula for or tha memory entered imo the C flag la wnierac into bit 18 7 when the m Hag i 1 MPY Mulliplias he contents of accumsa and the contenis of the mam E a Y d e Note 2 11 ory The higher order of the result of aperalion are entered inta acu 12 mulator and the kwer order inko accumulator MVH Transmis the data block The tranamission is done irom Not
186. PWM mode 5 6 1 Setting for PWM mode Figures 5 6 2 and 5 6 3 show an initial setting example for registers relevant to the PWM mode Note that when using interrupts set up to enable the interrupts For details refer to Chapter 4 INTERRUPTS b7 Li g Selecting PWM mode and each function Timer Ai mode register i 0 to 4 Addresses 5616 to 5A16 Selection of PWM mode Trigger select bits b4 b3 00 01 10 Falling of TAin pin s input signal External trigger 1 1 Rising of TAim pin s input signal External trigger Writing 1 to count start bit Internal trigger 16 8 bit PWM mode select bit 0 Operates as 16 bit pulse width modulator 1 Operates as 8 bit pulse width modulator Count source select bits b7 b6 00 fe 0 1 f16 fe4 11 612 615 68 b7 bO When operating as 16 bit pulse width modulator Setting PWM pulse s period and H level width b7 00 Er em NS Ne 2 b7 bO L Can be set to 0016 to FF16 m Can be set to 0016 to FE16 n Timer AO register Addresses 4716 4616 Timer A1 register Addresses 4916 4816 Timer A2 register Addresses 4 16 4A 16 Timer register Addresses 4016 4C16 Timer 4 register Addresses 4 1 4E16 v Can be set to 000016 to FFFE16 n When operating as 8 bit pulse width modulat
187. Q Ih E 6 Test conditions P4 P8 Vcc 5V 10 1 0 V VIH 4 0 V VoL 0 8 V VoH 2 0 V Input timing voltage Output timing voltage 15 23 ELECTRICAL CHARACTERISTICS 15 9 Memory expansion mode and microprocessor mode with Wait 15 24 Memory expansion mode and microprocessor mode With Wait Head f Xin 1 E Address output Ao A7 Address output 15 BYTE Address Data output 0 15 015 BYTE Data input Ds Di15 BYTE T Address Data output 00 23 07 Data input Do D7 ALE output BHE output R W output Port Pi input i 4 8 tw H tr Test conditions 1 E Vcc 5 10 Output timing voltage Data input VoL 0 8 V 2 0 V ViL 0 8 V VIH tf tc td E 61 td E 1 tw EL RY td POA th E _ C Adres NEP taP1A EE 12 12 4 Address 144 ta P1A ALE T th E P1 num a d ta P2A ead Paz Address T 44 ta P2A ALE um th E P2D saam m V UD tw ALE Y lsuPiD E Test conditions P4 P8 e Vcc 5 V 10 1 0 V VIH 4 0 V
188. R 8 SR Y B DIR X B L DIR B ABS Y B ABS X B ABL X ADC ADC ADC ADC ADC ROR ADC ADC PLB B DIR X B SR B DIR B L DIR BIMM B B ABS B ABL ADC ADC ADC ADC ADC ADC ADC ADC 7 TDB B CDIR YIB CDIR B SR Y B DIR X B L DIR B ABS Y 5 B ABL X STA STA STA STA STA STA TXB B DIRX B SR B DIR B L DIR B ABS B ABL STA STA STA STA TYB B DIR YIB DIR B SR Y B DIR X LIDIR 83957 a LDA LDA LDA TBX B DIR X B SR 8 DIR B L DIR 5 B ABL LDA LDA LDA LDA LDA LDA LDA Y B DIRYR SR Y B DIR X B L DIR 5 5 B ABL X CMP CMP CMP CMP CMP CMP CMP B DIR X B SR B DIR B L DIR B IMM B ABS B ABL CMP CMP CMP CMP CMP CMP CMP CMP IB SR Y B DIR X B LDIR B ABS Y B ABS X B ABL X SBC SBC SBC SBC SBC SBC SBC B DIR X B SR B DIA B IMM B ABS BABL SBC SBC SBC SBC SBC SBC SBC 6 DIR YIB DIR IB SR Y B DIR X B ABS Y 5 B ABL X Hexadecimal notation 21 56 7702 7703 Group User s Manual APPENDIX Appendix 7 Hexadecimal instruction code table Se ea CODE TABLE 3 The first word s code of each instruction is 89 MPY MPY MPY MPY MPY MPY DIR X SR A DIR ABS MPY MPY MPY MPY MPY DIR Yl DIR SR Y DIR X L DIR ABS Y ABS X ABL X DIV DIV DIV DIV DIV DIV DIV DIR X SR DIR Om DIR ABS ABL DIV DIV DIV DIR Yi DIR SR Y DIR X L DIR ABS Y 5 ABL X Hexadecimal
189. R W and the external bus become floating state In Hold state the input level of the HOLD pin is judged at every falling of 0 Then when H level is detected the HLDA pin s level changes L to H next rising of When 1 cycle of has passed after the level of HLDA pin becomes H the microcomputer terminates Hold state Figures 12 4 2 to 12 4 4 show timing of acceptance of Hold request and termination of Hold state Note has a same polarity and a same frequency as the clock However siops by the Ready request or executing the STP or WIT instruction Accordingly judgment of the input level of the HOLD pin is not performed during Ready state Judgment timing of input level to HOLD pin Judge No judge Glock LI LT N ALE Reading Writing Accessing word data with 2 bus cycle Example of no Wait Fig 12 4 1 Judgment when accessing word data beginning from odd address with 2 bus cycle 7702 7703 Group User s Manual 12 17 CONNECTION WITH EXTERNAL DEVICES 12 4 Hold function lt When inputting L level to HOLD pin during term unusing bus gt State when inputting L level to HOLD pin External data bus Data length External data bus width o Unused 8 16 moomoo J 1 J Clock d N s N Floating R W Ext add bus 2 Hj xternal address bus CEN
190. RTS function selected Transmit register empty flag 0 Data present in transmit register During transmitting 1 No data present in transmit register Transmitting completed Nothing is assigned umdimed Fig 7 2 3 Structure of transmit receive contro register 0 1 CTS RTS select bit bit 2 mM By clearing this bit to 0 in order to select the CTS function pins P80 and P84 function as CTS input pins and the input signal of L leve io these pins becomes one of the transmission conditions By setting this bit to 1 in order to select the RTS function pins P80 and P84 become RTS output pins When the receive enable bit bit 2 at addresses 3516 3D e is 0 reception disabled the RTS output pin outputs H level The output level of this pin becomes L when the receive enable bit is set to 1 It becomes H when reception starts and it becomes L when reception is completed 2 Transmit register empty flag bit 3 This flag is cleared to 0 when the UARTi transmit buffer register s contents are transferred to the UARTi transmit register When transmission is completed and the transmit register becomes empty this flag is set to 1 7 6 7702 7703 Group User s Manual SERIAL I O 7 2 Block description 7 2 3 UARTi transmit receive control register 1 Figure 7 2 4 shows the structure of UARTi transmit receive control register 1 For bit
191. Refer to Chapter 7 SERIAL I O Occurs at serial data transmission Refer to Chapter 7 SERIAL l O Occurs when A D conversion is completed Meier to Chapter 8 A D CONVERTER 7702 7703 Group User s Manual INTERRUPTS 4 3 Interrupt control 4 3 Interrupt control The enabling and disabling of maskable interrupts are controlled by the following Interrupt request bit Interrupt priority level select bits Processor interrupt priority level IPL Interrupt disable flag 1 The interrupt disable flag 1 and the processor interrupt priority level IPL are assigned to the processor status register PS The interrupt request bit and the interrupt priority level select bits are assigned to the interrupt control register of each interrupt Figure 4 3 1 shows the memory assignment of the interrupt control registers and Figure 4 3 2 shows their structure eMaskable interrupt An interrupt of which request s acceptance can be disabled by software Non maskable interrupt including Zero division BRK instruction Watchdog timer interrupts An interrupt which is certain to be accepted when its request occurs These interrupts do not have their interrupt control registers and are independent of the interrupt disable fiag 1 Address Fig 4 3 1 Memory assignment of interrupt control registers 4 6 7702 7703 Group User s Manual INTERRUPTS 4 3 Interrupt control 06 05 04 b3 b2 bl 60 A D conve
192. Refer to section 2 5 Processor modes In these modes pins PO to P4 and the E pin function as I O pins for the signals required for accessing external devices Figure 12 1 1 shows the pin configuration in the memory expansion and microprocessor modes Table 12 1 1 lists the functions of pins PO to P4 and the E pin in the memory expansion and the microprocessor modes 12 2 7702 7703 Group User s Manual CONNECTION WITH EXTERNAL DEVICES 12 1 Signals required for accessing external devices External data bus width 16 bits BYTE 4 E r 2 E x DJ gg ur US So 0 we EET 556099998008 ccaucd4cdaadcacacaaaAaAa els 49 e2 41 P83 TxDo 65 A20 D4 P82 RxDo 166 21 05 P81 CLKo 67 22 06 P8o CTSo RTSo 68 23 07 Vcc 69 R W AVcc BHE VREF gt 71 ALE AVss HLDA Vss Vss 77 74 E P76 AN6 175 XOUT P75 AN5 176 XIN P74 AN4 77 RESET P73 AN3 78 CNVss P72 AN2 lt gt 79 BYTE HOLD P71 AN1 lt gt P47 12 46 P45 lt 8 44 lt gt x P43 m 45 P4 1 RDY gt gt P7o ANo 57 P5e TA3oUT 55 21 P54 TA20UT P53 TAIIN P52 TAloutT lt gt a P51 TAOIN lt gt P5o TAOOUT gt 4 lt gt x As 1 microprocessor mode External address bus external da
193. SFR area Control registers Package outlines Countermeasures against noise Q amp A Hexadecimal instruction code table Machine instructions APPENDIX Appendix 1 Memory assignment Appendix 1 Memory assignment Figure 1 to Figure 5 show the memory assignment of the M37702 and the M37703 in each processor mode Refer to the memory assignment whose type name show suitable memory type and memory size M37702M2BXXXFP Memory type and memory size Single chip mode Memory size type M2 E2 Memory size type MD Note 00000016 00007F 16 SFR area SFR area SFR area 00008016 Internal RAM 512 bytes 00027F16 Internal RAM Internal RAM 1024 bytes 1024 bytes 00047F16 Not used Not used Not used 2 00800016 00A00016 Internal ROM 32 Kbytes 00C00016 Internal ROM 24 Kbytes Internal ROM 16 Kbytes OOFFFF16 Note These can be used only in the single chip mode Fig 1 Memory assignment during single chip mode 1 21 2 7702 7703 Group User s Manual APPENDIX Appendix 1 Memory assignment Single chip mode Memory size type M8 E8 00000016 00007F16 00008016 Internal RAM Internal RAM Internal RAM 2048 bytes 2048 bytes 2048 bytes 00087F 16 Notused Not used 00100016 Not used NW 00400016 Internal ROM 60 Kbytes 00800016 Internal ROM 48 Kbytes Internal ROM 32 Kbytes OOFFFF16 Fig 2 Memory assignment during single chip mo
194. TAIN TA2IN b7 TAIN 00 Port 6 direction register Address 1016 TA4IN pin Set the corresponding bit to 0 4 b7 etting count start bit to 1 00 Count start register Address 4016 Timer AO count start bit Timer A1 count start bit Timer A2 count start bit Timer A3 count start bit Trigger input to pin Timer A4 count start bit gt When internal trigger is selected Setting count start bit to 1 b7 00 Count start register Address 4016 Timer AO count start bit Timer A1 count start bit Timer A2 count start bit Timer A3 count start bit Timer A4 count start bit d b7 00 E 2122 7 i N _ X 4 Setting one shot start bit to 1 gt One shot start register Address 4216 Timer AO one shot start bit Timer A1 one shot start bit Timer A2 one shot start bit Timer A3 one shot start bit Timer A4 one shot start bit J Trigger generated Count starts Fig 5 5 3 Initial setting example for registers relevant to one shot pulse mode 2 7702 7703 Group User s Manual 5 33 TIMER A 5 5 One shot pulse mode 5 5 2 Count source In the one shot pulse mode the count source select bits bits 6 and 7 at addresses 5616 to 5A e select th
195. TERRUPTS 4 3 Interrupt control 4 3 1 Interrupt disable flag l All maskable interrupts can be disabled by this flag When this flag is set to 1 all maskable interrupts are disabled when the flag is cleared to 0 those interrupts are enabled Because this flag is set to 1 at reset clear the flag to O when enabling interrupts 4 3 2 Interrupt request bit When an interrupt request occurs this bit is set to 1 The bit remains set to 1 until the interrupt request is accepted and it is cleared to 0 when the interrupt request is accepted This bit also can be set to 0 or 1 by software Use the SEB or CLB instruction to set this bit For the INT interrupt request bit i 0 to 2 when using the interrupt with level sense the bit is ignored 4 3 3 Interrupt priority level select bits and processor interrupt priority level IPL The interrupt priority level select bits are used to determine the priority level of each interrupt Use the SEB or CLB instruction to set these bits When an interrupt request occurs its interrupt priority level is compared with the processor interrupt priority level IPL The requested interrupt is enabled only when the comparison result meets the following condition Accordingly an interrupt can be disabled by setting its interrupt priority 10 0 Each interrupt priority level gt Processor interrupt priority level IPL Table 4 3 1 lists th
196. Timer Ai interrupt 4 request bit n Cleared to 0 when interrupt request is accepted or cleared by software Fig 5 3 6 Example of operation selecting pulse output function 7702 7703 Group User s Manual 5 17 TIMER A 5 3 Timer mode Precautions when operating in timer mode By reading the timer Ai register the counter value can be read out at any timing while counting is in progress However if the timer Ai register is read at the reload timing shown in Figure 5 3 7 the value FFFF e is read out When reading the timer Ai register after setting a value to the register while counting is not in progress and before the counter starts counting the set value is read out correctly Weg om ot Read value ex 2 1 FFFF n 1 Time n Reload register s contents Fig 5 3 7 Reading timer Ai register 5 18 7702 7703 Group User s Manual TIMER A 5 4 Event counter mode 5 4 Event counter mode In this mode the timer counts an external signal Refer to Tables 5 4 1 and 5 4 2 Figure 5 4 1 shows the structures of the timer Ai mode register and timer Ai register in the event counter mode Table 5 4 1 Specifications of event counter mode when not using two phase pulse signal processing function Item Count source Count operation Divide ratio Count start condition Count stop condition Interrupt request occurrence timing pin function TAiour pin
197. Timing requirements Vcc 5 10 Vss 0 V Ta 20 to 85 C unless otherwise noted Symbol tw H tw L tr lt tsu P1D E tsu P2D E tsu P4D E tsu P5D E tsu P6D E tsu P7D E tsu P8D E th E P1D 20 40 5 th E PeD th E P7D Parameter External clock input cycle time 164 40 External clock input high level pulse width 15 External clock input low level pulsewidth 1251 J 15 External clock rise time 10 8 Extemalcockfaltime 1211018 Port P1 input setup time 45 380 Port P2 input setup time 14 30 Port P4 input setup time 110 60 Port P5 input setup time iC 60 Port P6 input setup time 110 6 Y Port P7 input setup time 71 10 60 Port P8 input setup time 11016 Port P1 input hold ime 1 0 O Port P2 input hold time J y J 9 O O PortP4inputholdtime 0 of Port P5 input hold time 1 of of PortP6inputholdtime O 0 PortP7inputholdtime 20 0 of Port P8 input hold time Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Switching characteristics Vcc 5 V 10 Vss 0 V Ta 20 to 85 C unless otherwise noted symbol Parameter PortP4dataoutputdelaytime gt 100 80 PortPSdataoutputdelaytime 12110 80 tu
198. To all our customers Regarding the change of names mentioned in the document such as Mitsubishi Electric and Mitsubishi XX to Renesas Technology Corp The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April Ist 2003 These operations include microcomputer logic analog and discrete devices and memory chips other than DRAMs flash memory SRAMS etc Accordingly although Mitsubishi Electric Mitsubishi Electric Corporation Mitsubishi Semiconductors and other Mitsubishi brand names are mentioned in the document these names have in fact all been changed to Renesas Technology Corp Thank you for your understanding Except for our corporate trademark logo and corporate statement no changes whatsoever have been made to the contents of the document and these changes do not constitute alteration to the contents of the document itself Note Mitsubishi Electric will continue the business operations of high frequency amp optical devices and power devices Renesas Technology Corp Customer Support Dept April 1 2003 24 NE SAS Renesas Technology Corp MITSUBISHI 16 BIT SINGLE CHIP MICROCOMPUTER 7700 FAMILY 7700 SERIES Z NE SAS Renesas Technology Corp Keep safety first in your circuit designs Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable but there is always
199. WM pulse level goes from H to L The interrupt request bit remains set to 1 until the interrupt request is accepted or the interrupt request bit is cleared to 0 by software Each time a PWM pulse has been output for one period the reload register s contents are reloaded and the counter continues counting The following explains operation of the pulse width modulator 16 bit pulse width modulator When the 16 8 bit PWM mode select bit is set to 0 the counter operates as a 16 bit pulse width modulator Figures 5 6 4 and 5 6 5 show operation examples of the 16 bit pulse width modulator 8 bit pulse width modulator When the 16 8 bit PWM mode select bit is set to 1 the counter is divided into 8 bit halves Then the high order 8 bits operate as an 8 bit pulse width modulator and the low order 8 bits operate as an 8 bit prescaler Figures 5 6 6 and 5 6 7 show operation examples of the 8 bit pulse width modulator Notes 1 If a value 000046 is set into the timer Ai register when the counter operates as a 16 bit pulse width modulator the pulse width modulator does not operate and the output from the TAiour pin remains L level The timer Ai interrupt request does not occur Similarly if a value 0016 is set into the high order 8 bits of the timer Ai register when the counter operates as an 8 bit pulse width modulator the same is performed 2 When the counter operates as 8 bit puise width mod
200. X82e36c0ZZ 8lN CD5 gt CD4 gt P24 A20 D4 9 P32 ALE 9 I 27 A23 D7 25 A21 D5 CD6 2 26 22 06 E P CD75 P Outline 80P6N A gt ninm a oscillating circuit Outline 80D0 ibi Fig 19 3 1 Pin connections in 1M mode 1 7702 7703 Group User s Manual 19 7 PROM VERSION 19 3 1M mode 1M mode top view 94 P66 TB1 IN lt gt 4 P6s TBOIN 4 4 P 4 INT2 lt gt P63 INT1 4 T P62 INTo gt 1 4 lt gt 6 P60 TA4ouTt lt gt 57 lt 8 P56 TASouT lt gt 9 1 P55 TA2N lt gt P54 TA20UT lt gt P53 TA1IN lt gt CCE gt P52 TA1ouT lt gt P51 TAOIN 4 CPGND Pb5o TAOoUT lt gt PM 4 1 1 11 11 11 lt gt lt gt am tc z lt c Nesssssee5 85240 lt lt lt lt 4 lt lt 4 lt lt Q O 0 pg qq 5 01 515 9 0 j R n n n n n n gt lt gt lt gt Qn n n n n ied e 8 77 747574 73 es 67 ee 65 64 63 a 161 O 60 lt gt P86 RxD1 lt gt P87 TxD1 _ lt gt lt gt PQ A lt l
201. a WoL VPP VPP Vcc Vcc 1 Vcc Vcc I VIH CE VIL VIH PGM VIL OE VIH VIL Switching characteristics measuring conditions Program Verify tAH Data output valid DFP lt gt Limits Limits OoOO T us us us us us ns us us ms ms us ns tvG lnput voltage Vi 0 45 V 2 4 V lnput signal rise fall time 1096 9096 lt 20 ns Reference voltage in timing measurement Input output L 0 8 V H 7702 7703 Group User s Manual 2 19 11 PROM VERSION 19 4 256K mode 19 4 256K mode 256K mode can perform reading programming from and to the built in PROM with the same manner as M5M27C256K However there is no device identification code Accordingly programming conditions must be set carefully Table 19 4 1 lists the pin correspondence with M5M27C256K Figures 19 4 1 and 19 4 2 show the pin connections in 256K mode Table 19 4 1 Pin correspondence with M5M27C256K M37702E2BXXXFP M5M27C256K M37702E2BFP M37702EHBFS Vcc Vcc Vcc VPP input CNVss BYTE VPP Vss Vss Vss Address input PO P1 A0 A14 Data I O P2 Do D7 52 P51 m 19 12 7702 7703 Group User s Manual PROM VERSION 19 4 256K mode 256K mode top view P70 ANo P67 TB2IN gt P6se TB1IN gt P65 TBOIN g
202. able I O port or gate input Programmable I O port or pulse output Counter value can be read out While counting is stopped When a value is written to timer Ai register it is written to both reload register and counter e While counting is in progress When a value is written to timer Ai register it is written to only reload register Transferred to counter at next reload timing Timer Ai register setting value 7702 7703 Group User s Manual TIMER A 5 3 Timer mode 67 06 b5 b4 b3 b2 bi bO jo fofo Timer Ai mode register i 0 to 4 Addresses 5616 to 5A16 b4 b3 00 01 Gate function select bits 10 1 1 00 01 ae see 10 et ENS Count source select bits 5 Lm mem qe Operating mode select bits 0 0 Timer mode Pulse output function select bit 0 No pulse output RW TAiour pin functions as a programmable I O port 1 Pulse output TAiour pin functions as a pulse output pin RW No gate function TAiiN pin functions as a prog rammable port Gate function Counter counts only while RW pin s input signal is L level Gate function Counter counts only while pin s input signal is H level Ma lnc LI Fix this bit to 0 in the timer mode f2 f16 fe4 RW 1 1 12 615 08 Timer AO register Addresses 4716 4616 b7 00 07 00 Timer 1 register Addresses 4916 4816 T
203. al SERIAL I O 7 4 Clock asynchronous serial I O UART mode 7 4 7 Process on detecting error Errors listed below can be detected in the UART mode Overrun error An overrun error occurs when the next data is prepared in the UARTi receive register with the receive completion flag 1 that is data present the UARTI receive buffer register and that data is transferred to the UARTi receive buffer register In other words when the next data is prepared before the contents of the UARTi receive buffer register is read out an overrun error occurs When an overrun error occurs the next receive data is written into the UARTi receive buffer register and the UARTi receive interrupt request bit is not changed However it is impossible to detect an overrun error as the case may be Refer to 1 in Precautions when operating in clock asynchronous serial l O mode Framing error A framing error occurs when the number of detected stop bits does not match the number of stop bits set The UARTI interrupt request bit becomes 1 Parity error A parity error occurs when the sum of 176 in the parity bit and character bits coes not match the number of 175 set The UARTi interrupt request bit becomes 1 Each error is detected when data is transferred from the UARTI receive register to the receive buffer register and the corresponding error flag is set to 1 Furthermore when any of the above errors occur
204. al peripheral devices Operating Stopped Operating Operating A A 7 STP instruction interrupt request used to eWatchdog timer s MSB 0 is executed terminate Stop mode However watchdog timer interrupt occurs request does not occur Oscillation starts When Supply of BiU starts an externa clock is input einterrupt request which has been used from the pin clock to terminate Stop mode is accepted input starts eWaichdog timer starts counting Fig 10 2 1 Stop mode terminating sequence by interrupt request occurrence 10 2 2 Termination by hardware reset Supply L level to the RESET pin by using the external circuit until the oscillation of the oscillator is Stabilized The CPU and the SFR area are initialized in the same way as a system reset However the internal RAM area retains the same contents as that before executing the STP instruction The termination sequence is the same as the internal processing sequence which is performed after a reset To determine whether a hardware reset was performed to terminate Stop mode or a system reset was performed use software after a reset Refer to Chapter 13 RESET for details about a reset 7702 7703 Group User s Manual 10 5 STOP MODE 10 3 Precautions for Stop mode 10 3 Precautions for Stop mode 1 When using the STP instruction with the mask ROM version select STP instruction enable with the STP instruction opt
205. alculation value 0 90 Calculation value The value is calculated from the shortest execution cycle number of each instruction described in the software manual 7702 7703 Group User s Manual 17 29 APPLICATION 17 2 Sample program execution rate comparison Sample Sample B SEP M X SEP X LDA B A 0 CLM STA A DEST 64 DATA 16 STA A DEST 65 INDEX 8 STA A DEST 66 LDY 69 LDX B 63 LOOPO LDX 69 ITALIC LDA A SOUR X LOOP1 ASL SOUR X TAY SEM AND B 00000011 DATA 8 STA A DEST X ROL SOUR 2 X TYA ROL B AND B A 00001100B CLM ORA A DEST 1 X DATA 16 STA Rm lr L ZX ROR A TYA DEX AND B A 00110000B DEX ORA A DEST 2 X DEX STA BNE LOOP 1 STA A DEST Y AND B A 11000000B SEM ORA A DEST 3 X DATA 8 STA A DEST 3 X STA DEX CLM BPL ITALIC DATA 16 DEY DEY DEY BNE LOOP 0 SOUR DEST Work area Direct page area Access this area at the following mode eDirect addressing mode Direct Indexed X addressing mode Absolute Indexed Y addressing mode Fig 17 2 1 Sample program list 17 30 7702 7703 Group User s Manual APPLICATION 17 2 Sample program execution rate comparison 17 2 2 Comparison software Wait f Xin 20 MHz with software Wait Ready f Xin 25 MHz The following condiitons and are compared Refer to Figure 17 2 1 about executed sample program The execution time ratio depends on the program or the usage conditions Condition When se
206. an tpzxe p1z p2z after the rising edge of the E signal there will be a possibility of the tail of data colliding with the head of address In this case examine the method described below Cut the tail of data output from the external memory by using a bus buffer and others Use the Mitsubishi s memories that can be connected without a bus buffer Figures 17 1 11 to 17 1 14 show examples for how to use a bus buffer and the timing diagrams Table 17 1 7 lists the memories that can be connected without a bus buffer These memories do not require a bus buffer because timing parameters tor and taistos listed below are guaranteed However the read signal must go high within 10 ns after the rising edge of E signal Table 17 1 7 Memories that can be connected without bus buffer Memory Type description tpr taisog Maximum Conditions EPROM M5M27C256AK 85 10 12 15 15 ns lt 20 MHz M5M27C512AK 10 12 15 Guaranteed by kit Note M5M27C100K 12 15 M5M27C101K 12 15 M5M27C102K 12 15 M5M27C201K JK 10 12 15 M5M27C202K JK 10 12 15 One time PROM M5M27C256AP FP VP RV 12 15 M5M27C512AP FP 15 M5M27C100P 15 M5M27C101P FP J VP RV 15 M5M27C102P FP J VP RV 15 M5M27C201P FP J VP RV 12 15 M5M27C202PeFP J VP RV 12 15 Frash memory M5M28F101P FP J VP RV 10 12 15 M5M28F102FRyJ VP RV 10 12 15 SRAM M5M5256CP FP KP VP RV 55LL 55XL 70LL 70XL 85LL 85XL 10LL 10XL 10 ns
207. approximation method X 1 4 channels Watchdog timer 12 bits X 1 Interrupts 3 external 16 internal priority levels O to 7 can be set for each interrupt with software Clock generating circuit Built in externally connected to a ceramic resonator or a quartz crystal oscillator Supply voltage 5 V 10 96 Power dissipation 95 mW at 25 MHz frequency typ Port Input Output Input Output withstand voltage 5 V characteristics Output current 5 mA Memory expansion Maximum 16 Mbytes Operating temperature range 20 to 85 C Device structure CMOS high performance silicon gate process Package 80 pin plastic molded SDIP 7702 7703 Group User s Manual 20 3 7703 GROUP 20 3 Pin configuration 20 3 Pin configuration Figure 20 3 1 shows the M37703M2BXXXSP pin configuration AVCC VREF AVss P77 AN7 ADTRG gt P72 AN2 P71 AN1 6 P70 ANo P65 TBOIN gt 8 P64 INT2 lt gt 9 P63 INT1 lt gt P62 INTo lt gt 57 gt P56 TA30UT gt P55 TA2IN gt 54 200 lt gt P53 TA1IN lt gt P52 TA10UT gt P51 TAOIN gt P5o TAOOUT P47 gt P42 0 1 P41 RDY lt gt P40 HOLD BYTE gt gt CNVss RESET XOUT Vss P32 ALE lt gt P31 BHE lt N C2 lt NO UJ gt gt 2 lt e 64 gt Vcc lt gt 80 5 5 lt gt P81 CLKo lt gt P82 RxDo 60 P83 TxDo
208. apter 12 CONNECTION WITH EXTERNAL DEVICES 2 2 1 Overview Transfer operation between the CPU and memory l O devices is always performed via the BIU Figure 2 2 1 shows the bus and bus interface unit BIU The reads an instruction from the memory before the CPU executes it When the CPU reads data from the memory I O device the CPU first specifies the address from which data is read to the BIU The BIU reads data from the specified address and passes it to the CPU When the CPU writes data to the memory I O device the CPU first specifies the address to which data is written to the BIU and write data The BIU writes the data to the specified address To perform the above operations the inputs and outputs the control signals and control the bus 2 10 7702 7703 Group User s Manual CENTRAL PROCESSING UNIT CPU 2 2 Bus interface unit Sng u JO jnoge S39IA3d T1VNH3 LX3 NOLLO3NNOO 721 J91deu 0 22 Jeujoue auo JO snq eujejxe pue Sng euaegjur snq SUL L SION T EE s euDis 0J1u02 VIJIADP Lq eev 0 oqyerv eup gt s Q S rV 8q 8V V 0 Snq eUJ91X3 UOISJOAUOD sng 935 eJeudued euJ81u 041009 euJelu AJOWOW euJo u oy euJeju pa 0 snq eugelu
209. are that the measurement values are within a constant range 7702 7703 Group User s Manual 6 27 TIMER B 6 5 Pulse period pulse width measurement mode MEMORANDUM 6 28 7702 7703 Group User s Manual CHAP TIER 7 SERIAL 7 1 Overview 7 2 Block description 7 3 Clock synchronous serial I O mode 7 4 Clock asynchronous serial UART mode SERIAL I O 7 1 Overview This chapter describes the Serial The Serial I O consists of 2 channels UARTO and UART1 They each have a transfer clock generating timer for the exclusive use of them and can operate independently UARTO and UART1 have the same functions 7703 Group UART1 s function of the 7703 Group varies from the 7702 Group s Refer to Chapter 20 7703 GROUP 7 1 Overview UARTi i 0 and 1 has the following 2 operating modes Clock synchronous serial mode Transmitter and receiver use the same clock as the transfer clock Transfer data has the length of 8 bits e Clock asynchronous serial I O UART mode Transfer rate and transfer data format can arbitrarily be set The user can select a 7 bit 8 bit or 9 bit length as the transfer data length Figure 7 1 1 shows the transfer data formats in each operating mode e Clock synchronous serial I O Transier data length of 8 bits UART mode Transfer data length of 7 bits Transfer data length of 8 bits Transfer data length of 9 bits Fig 7 1 1 Transfer data formats
210. areas so that the circuits in Figures 17 1 8 and 17 1 9 use the chip select signal CS2 to specify the area where Ready function is valid 7702 7703 Group User s Manual 17 11 APPLICATION 17 1 Memory expansion M37702M2AXXXFP A8 A23 Data bus Do D15 m Address latch ji gt CS at circuit CS Ao A7 Address bus AC32 032 E 120 ACOA Insert Wait by Ready function only for areas accessed by CS2 Circuit condition lt 14 5 MHz no Wait td E 6 1 0 1 CS2 Q x condition satisfying tsu RDY 1 gt 60 ns is tc gt 68 5 ns RDY Accordingly when lt 14 5 MHz this L circuit example satisfies tsu RDY 1 gt 60 ns tsu RDY 6 1 Wait by Ready function AC32 propagation delay time max 8 5 ns This applies when using the 16 MHz version Fig 17 1 8 Example of Ready signal generating circuit no Wait 17 12 7702 7703 Group User s Manual APPLICATION 17 1 Memory expansion M37702M2BXXXFP 1 3 Use the elements of which sum of Data bus propagation delay time is within Do D15 2X10 Address oss gt CS Tx tsu RDY 01 decode Xin gt CS 25 MHz 25 ns A0 A7 Address bus RDY 4 3 E Insert Wait by Ready tunction only for areas accessed by CS2 1 Circuit condition lt 25 MHz Wa
211. at which the PWM pulse goes H depends on the timing at which the new value is set Note The above applies when an external trigger rising of TAi pin s input signal is selected Fig 5 6 5 Operation example of 16 bit pulse width modulator when counter value is updated during pulse output 7702 7703 Group User s Manual 5 45 TIMER A 5 6 Pulse width modulation PWM mode 1 fi 1 X 28 1 Count source pin s H input signal i ee l Y lt 1 fix m 8 bit prescaler s underflow signal PWM pulse output from TAiour Timer Ai interrupt T request bit n fi Frequency of count source 11 5 f fo fre fea or 1512 Cleared to O when interrupt request is accepted or cleared by software D The 8 bit prescaler counts the count source 2 The 8 bit pulse width modulator counts the 8 bit prescaler s underflow signal Note The above applies when the reload register s high order 8 bits n 0216 and low order 8 bits m 0216 and an external trigger falling of TAiin pin input signal is selected Fig 5 6 6 Operation example of amp bit pulse width modulator 5 46 7702 7703 Group User s Manual TIMER A 5 6 Pulse width modulation PWM mode si JeuDis 1ndui s uid L jo Buijej 19661 euje1xe ue u uA y 91ON JOS n 8A MOU y YOIYM ye
212. atings shown in Table 20 5 1 and the parameters of not existing pins of the M37703 Refer to Chapter 15 ELECTRICAL CHARACTERISTICS Additionally the M37703 standard characteristics is the same as the M37702 s and refer to Chapter 16 STANDARD CHARACTERISTICS Table 20 5 1 Absolute maximum ratings Parameter Conditions Rangs Power dissipation Ta 25 G 1000 Note The electrical characteristics except above is the same as the M37702 s 20 12 7702 7703 Group User s Manual 7703 GROUP 20 6 PROM version 20 6 PROM version In the PROM version programming to the built in PROM can be performed by using a general purpose PROM programmer and a programming adapter which is suitable for the used microcomputer The PROM version of M37703 is the one time PROM version Programming to the PROM can be performed once in this version The one time PROM version has the same functions as the mask ROM version except that the former has a built in PROM Table 20 6 1 lists the write address of PROM version The M37703 does not have the EPROM version Use the EPROM version of M37702 with a pitch converter for the M37703 evaluation Table 20 6 1 Write address of PROM version Type name RAM size Write address Byte Byte 256K mode M37703E2BXXXSP 16K 512 400016 to 7FFF46 M37703E2AXXXSP Note 1 a M37703E4BXXXSP 000016 to 7FFF e M37703E4AXXXSP Note 1 i Notes 1 Refer also to section 20 6 2 Bus t
213. avg 40 45 P5o P57 P60 P67 P7o P77 P80 P87 Low level input voltage P1o P17 20 27 Vit in memory expansion mode and 0 16Vcc V microprocessor mode Low level peak output current 0 P1o P17 P20 P 27 loL peak 4 4 P5o P57 P60 P67 7 7 P80 P87 Low level average output current POc PO7 P1o P17 20 27 avg 4 4 P54 P57 P60 P67 P7o P77 P80 P87 f Xin External clock input frequency 8 Notes 1 Average output current is the average value of a 100 ms interval 2 The sum of lo peak for ports PO P1 P2 and P8 must be 80 mA or less the sum of for ports PO P1 P2 and P8 must be 80 mA or less the sum of for ports P4 P5 P6 and P7 must be 80 mA or less and the sum of for ports P4 P5 P6 and P7 must be 80 mA or less 7702 7703 Group User s Manual 18 9 LOW VOLTAGE VERSION 18 4 Electrical characteristics 18 4 3 Electrical characteristics Electrical characteristics Vcc 5 V Vss 0 V Symbol Parameter High level output voltage PQo P07 P1o P 17 20 27 Von P30 P31 P33 P4c P47 P5o P5 P6o P6 P7o P77 P amp P8 Vo High level output voltage POc P07 P1o P 17 20 27 P30 P31 P33 High level output voltage P3 High level output voltage _ VoH E Low level output voltage POc P0 P
214. b7 00 tert rite Timer Ai mode register i 0 to 4 Addresses 5616 to 16 Selection of one shot pulse mode Trigger select bits b4 b3 Writing 1 to one shot start bit Internal trigger 1 0 Falling of pin s input signal External trigger 1 1 Rising of pin s input signal External trigger Count source select bits b7 b6 00 fe 0 1 f16 10 164 11 1 12 d S AETERNE b15 b8 2 Timer AO register Addresses 4716 4616 b7 bO b7 bo Timer A1 register Addresses 4916 4816 Timer register Addresses 4016 4 16 Timer 4 register Addresses 4F e 4 16 w Can be set 000116 to FFFF e n d Note H level width E Setting interrupt priority level b7 00 Timer Ai interrupt control register i 0 to 4 751 Interrupt priority level select bits When using interrupts set these bits to level 1 7 q When disabling interrupts set these bits to level 0 Continue to Figure 5 5 3 Fig 5 5 2 Initial setting example for registers relevant to one shot pulse mode 1 5 32 7702 7703 Group User s Manual TIMER A 5 5 One shot pulse mode When external trigger is selected From preceding Figure 5 5 2 k ls b7 etting port P5 and port P6 direction registers Port P5 direction register Address Die 00 TAOIN pin
215. bit contents of the up down register are selected as the up down switching 3 Timer AS up down bit factor Timer A4 up down bit 5 Timer A2 two phase pulse signal 0 Disabled Two phase pulse signal WO processing select bit Note processing function 1 Enabled Two phase pulse signal Timer A3 two phase pulse signal Processing function processing select bit Note When not using the two phase pulse _ signal processing function make pue Sure to set the bit to 0 The value is 0 at reading Note Use the LDM or STA instruction when writing to bits 5 to 7 Fig 5 4 5 Structure of up down register 7702 7703 Group User s Manual 5 25 TIMER A 5 4 Event counter mode 5 4 3 Select functions The following describes the selective pulse output and two phase pulse signal processing functions 1 Pulse output function 5 26 The pulse output function is selected by setting the pulse output function select bit bit 2 at addresses 5616 to 5Aie to 1 When this function is selected the pin is forcibly set for the pulse output pin regardless of the corresponding bits of the port P5 and port P6 direction registers The TAiour pin outputs pulses of which polarity is inverted each time the counter underflows or overflows Refer to Figure 5 3 6 When the count start bit address 4016 is 0 count stopped the TAiour pin outputs L level 7702 7703 Group Use
216. cates the number of registers among B X Y DT and PS to ba restored while i 2 when DPR is 12 ne restored Note B The number of cycles is the case whan the number of bytes to be transfered is evan When ihe number cf bytes to be transfered is odd the number is calculated 3 7 U2 X 7 4 Note that 1 2 shows the integer part when i is divided by 2 Note 9 The number of cycles is the case when the number of byles to be transfered even When the number of bytes to be transfered is odd the number is calculated as 9 1 2 X745 Note that 1 2 shows the Integer part when is divided by 2 Note 10 The number ol cycles the case in the 16 bit 8 bit operation The number of cycles is incremented by 16 for 32 blt 16 bit oparation Note 11 The number of cycles 5 the case in the 2 bitX B bit operation number of cycles is incremented by B for 16 bit X 16 bit operation Note 12 When setting flag x to handla tha dala as 16 bit data in tha immediate addressing mode the number of bytes increments by 1 Note 13 When flag m is 0 the 6yte in the table is incremented by 1 7702 7703 Group User s Manual 21 71 APPENDIX Appendix 8 Machine instructions MEMORANDUM 21 2 7702 7703 Group User s Manual GLOSSARY GLOSSARY This section briefly explains the terms used in this user s manual The terms defined here apply to this manual only Term Reva Term Access Means performing rea
217. cc VIH CE VIL OE VIH VIL 7702 7703 Group User s Manual 19 17 PROM VERSION 19 5 Usage precaution 19 5 Usage precaution The usage precaution of PROM version is described bellow 19 5 1 Precautions on all PROM versions When programming to the built in PROM high voltage is required Accordingly be careful not to apply excessive voltage to the microcomputer Furthermore be especially careful during power on 19 5 2 Precautions on One time PROM version One time PROM versions shipped in a blank of which built in PROMs are programmed by users are also provided For these microcomputers a programming test and screening are not performed in the assembly process and the following processes To improve their reliability after programming we recommend to program and test as the flow shown in Figure 19 5 1 before use Programming with PROM programmer Screening Note Leave at 150 C for 40 hours Note Never expose to 150 C exceeding 100 hours Fig 19 5 1 Programming and test flow for One Time PROM version 19 5 3 Precautions on EPROM version 1 Cover transparent glass window Cover the transparent glass window with a shield or others during the read mode because exposing to sun light or fluorescent lamp can cause erasing the programmed data A shield to cover the transparent window is available from Mitsubishi Electric Corporation Be careful that the shield does not touch the EPROM lead pins 2 E
218. ccepted This bit can be set to 1 or O by software 7702 7703 Group User s Manual 7 15 SERIAL I O 7 2 Block description 7 2 8 Port P8 direction register I O pins of UARTi are shared with port P8 When using pins P8 and 86 as serial data input pins RxDi set the corresponding bits of the port P8 direction register to 0 to set these pins for the input mode When using pins 8 P8 8 to P8s and P87 as I O pins CTS RTSi TxDi of UARTI these pins are forcibly set as I O pins of UARTi regardless of port P8 direction register s contents Figure 7 2 13 shows the relationship between the port P8 direction register and UARTi s pins b7 06 05 b4 b3 b2 bl 1 Output mode CLKo pin When using pins P82 and P8e as serial data pino Axo xD set the corresponding bits to 0 3 TxDo pin CLK pin 5 TxD Fig 7 2 13 Relationship between port direction register UARTi s I O pins 7 16 7702 7703 Group User s Manual SERIAL I O 7 3 Clock synchronous serial I O mode 7 3 Clock synchronous serial I O mode Table 7 3 1 lists the performance overview in the clock synchronous serial mode and Table 7 3 2 lists the functions of pins in this mode Table 7 3 1 Performance overview in clock synchronous serial mode Item Functions Transfer data format Transfer data has a length of 8 bits LSB first Transfer rate Clock
219. ceive data is read out from here 0 data i Receive data is read out from here 0 read out from here Undefined RO 15 to 9 Nothing is assigned The value is 0 at reading 7702 7703 Group User s Manual 21 17 APPENDIX Appendix 3 Control registers Count start register 67 b6 b5 b4 b3 b2 bi bO Count start register Address 4016 Fm Cn Cree Timer AO count start bit A Stop counting Start counting La Timer A1 count start bit Timer A2 count start bit S Timer Bt count startbt One shot start register 67 06 b5 b4 b3 02 bl One shot start register Address 42 6 rons ee Timer AO one shot start bit Start outputting one shot pulse wo when selecting internal KW Timer Ai one shot start bit trigger Timer A2 one shot start bit The value is Q at reading OPUS FN Timer A3 one shot start bit Timer A4 one shot start bit at 2 1 Nothing is assigned undetined F m w 21 18 7702 7703 Group User s Manual APPENDIX Appendix 3 Control registers Up down register 67 b6 b5 04 b3 b2 bi bO TITTI Up down register Address 4416 Timer AO up down bit 0 Down count 1 Up count Timer A1 up down bit This function is valid when the Timer A2 up down bit contents of the up down register is selected as the up down
220. ck pointer relativa addressing moda DER Direct registers upper 8 bits SR Y Stack pointer relative Indirect Indexed Y addressing DPR Direct page registers lower hits Processor status register BLK Block transter addressing mode Processor status registers upper 8 bits C Carry tlag PS Processor status registers lower B bits z Zero flag PSp Processor status registur s b th bit Interrupt disabie flag MIS Contents of memory at address indicated stack D Decimal operation mode pointer x Index register jength selection tiag Mag b th memory location m Data lengih selaction flag ADs Value of 24 bit address s upper 4 bit Ain Overflow flag AD Value of 24 bit addresa s middle 8 bit N Negative figg AD Value ol 24 bit addrass s lower B bit Ag IPL Processor interrupt priority level op Operation code Addition n Number of cycia Subtraction Number of byte Multiplication Number of transfer byte or rotation JU Divislon ls Number of registers pushed or pulled 2 Logical AND s Logicel APPENDIX Appendix 8 Machine instructions The number of cyclas shown in the table is described in case of the fastest mode for each instruction Tha number ol cycles shown in the table is calculated for 0 The number of cycles in the addressing mode conceming the OPA when DPR 0 must be incramented by 1 The number of cyctas shown In the table diff
221. count source Refer to Table 6 3 1 Figure 6 3 1 shows the structures of the timer Bi mode register and timer Bi register in the timer mode Table 6 3 1 Specifications of timer mode Item Count source Count operation Divide ratio Count start condition Count stop condition Interrupt request occurrence timing TBIIN pin function Read from timer Bi register Write to timer Bi register Specifications f2 f16 164 or 1512 Down count When the counter underflows reload register s contents are reloaded and counting continues 1 n 1 When count start bit is set to 1 When count start bit is cleared to 0 When the counter underflows Programmable port Counter value can be read out e While counting is stopped When a value is written to the timer Bi register it is written to both reload register and counter While counting is in progress When value is written to the timer Bi register it is written to only reload register iransferred to counter at next reload time n Timer Bi register setting value 7702 7703 Group User s Manual TIMER B 6 3 Timer mode 67 06 b5 b4 b3 02 bi b0 x Timer mode register i 0 to 2 Addresses 5 16 5D 6 b1 b0 Operating mode select bits 00 Timer mode These bits are ignored in timer mode Nothing is assigned This bit is ignored in timer mode Count source select bits b7 b6 00 fe 01 fie 10 fea 11 fs12 00 T
222. ction register to 0 Refer to Figure 4 10 2 The signals input to the pin require or L level width of 250 ns or more independent of the f Xn Additionally even when using the pins P62 INTo to P64 INT2 as the input pins of external interrupt the user can obtain the pin s state by reading bits 2 to 4 at address E e port P6 register Note When selecting an input signal s falling or L level as the occurrence factor of an interrupt request make sure that the input signal is held L for 250 ns or more When selecting an input signal s rising or H level as that make sure that the input signal is held H for 250 ns or more Table 4 10 1 Occurrence factor of interrupt request b5 INT interrupt request occurrence actor Interrupt request occurs at falling of the signal input to the INTi pin edge sense Interrupt request occurs at rising of the signal input to the INTi pin edge sense 00 Interrupt request occurs while the INT pin level is H level sense Interrupt request occurs while the INT pin level is L level sense The INT interrupt request occurs by always detecting the INT pin s state Accordingly when the user does not use the interrupt set the INTi interrupt s priority evel to level 0 4 20 7702 7703 Group User s Manual INTERRUPTS 4 10 External interrupts INTi interrupt 67 b6 b5 b4 b3 b2 bl INTo to INT2 interrupt control r
223. cution time ratio 17 32 7702 7703 Group User s Manual CHAPTER 1 LOW VOLTAGE VERSION 19 1 Performance overview 18 2 Pin configuration 18 3 Functional description 18 4 Electrical characteristics 18 5 Standard characteristics 18 6 Application LOW VOLTAGE VERSION The low voltage version has the following characteristics Low power source voltage 2 7 to 5 5 V Wide operating temperature range 40 to 85 C The low voltage version is suitable to control equipment which is required to process a large amount of data with a low power dissipation for example portable equipment which is driven by a battery and OA equipment Differences between the M37702M2LXXXGP and the M37702M2BXXXFP are mainly described below For the EPROM mode of the PROM version refer to Chapter 19 PROM VERSION 18 2 7702 7703 Group User s Manual 18 1 Performance overview Table 18 1 1 shows the performance overview of the M37702M2L XXXGP Table 18 1 1 M37702M2LXXXGP performance overview Parameters Number of basic instructions Instruction execution time External clock input frequency f Xin ROM 16384 bytes RAM 512 bytes Po Pa Paps 5 bits x 8 P 4 biis Xi Memory size Programmable Input Output ports Multifunction timers Serial I O A D converter Watchdog timer Interrupts Clock generating circuit Supply voltage Power dissipation TBO TB2 LOW VOLTAGE VERSION 18 1 Performance ov
224. d 2 6 12 8 25 c when 1 85 c when messe 2 In single chip mode output pins are open and the other pins are connected to Vss 7702 7703 Group User s Manual Unit V V lt uA uA mA uA uA LOW VOLTAGE VERSION 18 4 Electrical characteristics 18 4 4 A D converter characteristics CONVERTER CHARACTERISTICS Vcc AVcc 2 7 5 5 V Vss AVss 0 V 40 to 85 C otherwise noted 8 MHz unless Bits eV Ruwoen Ladder resistance 2 tow Conversion time 285 Ver Reference votagg Z 27 Ve V Va Analog input vollage L 7702 7703 Group User s Manual 18 11 LOW VOLTAGE VERSION 18 4 Electrical characteristics 18 4 5 Internal peripheral devices Timing requirements Vcc 2 7 5 5 V Vss 0 V Ta 40 to 85 C unless otherwise noted Timer A input count input in event counter mode TAi input cycle time 250 ns tw TAH TAiin input high level pulse width 125 ns tw TAL TAiin input low level pulse width 125 ns Timer A input gating input in timer mode Max 9 TAii input cycle time 2 1000 o m 9 tw TAH TAi input high level pulse width E 500 9 tw TAL input low level pulse width i C 500 Note TAlin input cycle time must be 4 cycles or mo
225. d RW 1 Sleep mode selected Note Bits 4 to 6 are ignored in the clock synchronous serial I O mode They may be either 0 or 1 Additionally fix bit 7 to 0 UARTi baud rate recisier BRGI b7 00 fe UARTO baud rate register Address 3116 UART1 baud rate register Address 3916 7 to O Can be set to 0016 to FF e Assuming that the set value n 0016710 u Undefined WO divides the count source frequency by n 1 7702 7703 Group User s Manual 21 15 APPENDIX Appendix 3 Control registers UARTi transmit buffer register b15 b8 b7 bO b7 bO UARTO transmit buffer register Addresses 3316 3216 UART1 transmit buffer register Addresses 3Bt 6 16 Transmit data is set 15 to 9 Nothing is assigned Undefined UARTi transmit receive control register 0 b7 06 b5 b3 b2 bi 00 UARTO transmit receive control register 0 Address 34 6 UART1 transmit receive control register 0 Address BRG count source select bits b1 bO 00 12 O1 f16 ie 1 512 CTS RTS select bit CTS function selected RTS function selected L Transmit register empty flag 0 Data present in transmit register During transmitting 1 No data present in transmit register Transmitting completed 55 n Nothing is assigned 21 16 7702 7703 Group User s Manual APPENDIX Appendix 3 Co
226. d write or read and write Access area An accessible memory space of up to 16 Mbytes Access Access characteristics Means whether accessible or not Access Baud rate Means a transfer rate of Serial I O Branch Means moving the program s execution point address to another location Bus control signal A generic name for ALE E BHE R W RDY HOLD HLDA and BYTE signals Count source A signal that is counted by Timers and B the UARTi baud rate register and Watchdog timer That 15 f2 f16 164 512 selected by the count source select bits and others Counter contents values Means a value read when reading the timer Ai and Bi registers Down count Means decreasing by 1 and counting Up count Event counter mode Means the mode of Timers which can count the number of external pulses exactly without a divider An accessible area for external devices connected in the memory Internal area expansion or microprocessor mode t is up to 16 Mbyte external External area area External bus A generic name for the external address bus and the data bus External device Devices connected externally to the microcomputer A generic name for a memory an 1 device and a peripheral IC Gate function of Timer Means the function that the user can control input of the timer count source Internal area An accessible internal area A generic name for areas of the External area Interrupt routine A routine that is automa
227. d DL IL Transferred Transferred measured value undefined value Measurement pulse Reload register counter Transfer timing Timing at which counter is cleared to 000016 Count start bit a Timer Bi interrupt 1 request bit 0 Cleared to 0 when interrupt request is accepted or i4 cleared by software Timer Bi overflow flag 0 D Counter is initialized by completion of measurement Counter overflow Note The above applies when measurement is performed for an interval from one falling to the next falling of the measurement pulse Fig 6 5 3 Operation during pulse period measurement 7702 7703 Group User s Manual 6 25 TIMER B 6 5 Pulse period pulse width measurement mode Count source H Measurement pulse l Transferred Transferred Y undefined Transferred measured Transferred measured value measured Reload register counter value Transfer timing Timing at which counter is cleared to 000016 Count start bit Timer Bi interrupt 1 request bit n Cleared to 0 when interrupt request is accepted or Timer Bi overflow flag cleared by software D Counter is initialized by completion of measurement Counter overflow Fig 6 5 4 Operation during pulse width measurement 6 26 7702 77
228. d logic unit ALU during an arithmetic operation This flag is also affected by shift and rotate instructions When the BCC or BCS instruction is executed this flag s contents determine whether the program causes a branch or not Use the SEC or SEP instruction to set this flag to 1 and use the CLC or CLP instruction to clear it to 0 2 Bit 1 Zero flag Z It is set to 1 when a result of an arithmetic operation or data transfer is 0 and cleared to 0 when otherwise When the BNE or BEQ instruction is executed this flag s contents determine whether the program causes a branch or not Use the SEP instruction to set this flag to 1 and use the CLP instruction to clear it to 0 Note This flag is invalid in the decimal mode addition the ADC instruction 3 Bit 2 Interrupt disable flag 1 It disables all maskable interrupts interrupts other than watchdog timer the BRK instruction and zero division Interrupts are disabled when this flag is 1 When an interrupt request is accepted this flag is automatically set io 1 to avoid multiple interrupts Use the SEI or SEP instruction to set this flag to 1 ane use ihe CLI or CLP instruction to clear it to 0 This flag is set to 1 at reset 4 Bit 3 Decimal mode D It determines whether addition and subtraction are performed in binary or decimal Binary arithmetic is performed when this flag is 0 When it is 1 d
229. d use the CLM or CLP instruction to clear it to 0 This flag is cleared to 0 at reset Note When transferring data between registers which are different in bit length the data is transferred with the length of the destination register but except for the TXA TYA TXB TYB and TXS instructions Refer to 7700 Family Software Manual for details Bit 6 Overflow flag V It is used when adding or subtracting with word regarded as signed binary When the data length flag m is 0 the overflow flag is set to 1 when the result of addition or subtraction exceeds the range between 32768 and 32767 and cleared to 0 in all other cases When the data length flag m is 1 the overflow flag is set to 1 when the result of addition or subtraction exceeds the range between 128 127 and cleared to 0 in all other cases The overflow flag is also set to 1 when a result of division exceeds the register length to be stored in the DIV instruction a division instruction When the BVC or BVS instruction is executed this flag s contenis determine whether the program causes a branch or not Use the SEP instruction to set this flag to 1 and use the CL V or CLP instruction to clear it to 0 Note This flag is invalid in the decimal mode Bit 7 Negative flag N It is set to 1 when a result of arithmetic operation or data transfer is negative Bit 15 of the result is 1 when t
230. data bank register or processor status register specified by the bit pattern tha second byte of tha Instruction Aotates the contents 3 the accumulates A n bits to the latt mE Raturns irom the Tha contents of the program bank register are restored 42 4211013 F Fl 7702 7703 Group User s Manual Links the accumulator or tha memory to C flag and rotalea result 1o the Jett by 1 BIL Links tha accurnulBior of tha memory 1o Hag and rotates result to tha right by 1 bit Returns from tha aubtowtin Tha contents of tha program bank register pra not resiored Subtracts tha contents of tha memory and the borrow from the contente of the accumulator APPENDIX Appendix 8 Machine instructions pope status ragister D ache b 5 ABS Y Y ABL O STK STK REL SP R a 18 8 5 Ronee n Pelei he E x 2 id Ill i restored the contents of PS Ill i it becomes ite value And the E case le no changea i ege serene 7702 7703 Group User s Manual 21 67 APPENDIX Appendix 8 Machine instructions Addrassing moda sta me om ome nx aay nnnc SEB Mo Makes the contents of ihe specillad bit in the mamory wa PAPEL 6 1 Makestne contents
231. data taken in CC OC OOO UARTi receive register receive buffer register UARTi receive buffer register is read out Receive complete flag UARTi receive 1 interrupt request bit p Cleared to 0 when interrupt request is accepted uu cleared by software The above timing diagram applies to the following input level is H safisfy the setting conditions ellowi acne External clock selected Ollowing cinditions RTS function selected 9 iransmit enable bit 5 1 Receive enable bit 1 Writing of dummy data to transmit fexr Frequency of external clock buffer register Fig 7 3 11 Example of receive timing when selecting external clock 7702 7703 Group User s Manual 7 31 SERIAL I O 7 3 Clock synchronous serial I O mode 7 3 6 Process on detecting overrun error In the clock synchronous serial mode an overrun error can be detected However it is impossible to detect an overrun error as the case may be Refer to 6 in Precautions when operating in clock synchronous serial I O mode An overrun error occurs when the next data is prepared in the receive register with the receive complete flag 1 data is present in the UARTI receive buffer register and that is transferred to the receive buffer register in other words when the next data is prepared before reading out the c
232. ddresses 5616 to 5 16 Selection of event counter mode Pulse output function select bit 0 No pulse output 1 Pulse output Count polarity select bit 0 Counts at falling edge of external signal 1 Counts at rising edge of external signal Up down switching factor select bit 0 Contents of up down register 1 Input signal to TAiour pin X It may be either 0 or 1 b Setting up down register b7 Up down register Address 4416 Timer AO up down bit Set the corresponding up down bit when the contents of Timer A1 up down bit the up down register are selected as the up down Timer A2 up down bit sw itching factor Timer A3 up down bit 0 Down count 1 Up count Timer A4 up down bit Timer 2 two phase pulse signal processing select bit Timer AS two phase pulse signal processing select bit Timer A4 two phase pulse signal processing select bit Set the corresponding bit to 1 when the two phase pulse signal processing function is selected for timers A2 to A4 0 Two phase pulse signal processing function disabled 1 Two phase pulse signal processing function enabled Setting divide ratio Oo b7 bo Timer A1 register Addresses 4916 4816 Timer A2 register Addresses 4B16 4A16 Timer AO register Addresses 4716 4616 Timer register Addresses 4D16 4 16 Timer A4 register Addresses 4F
233. ddresses 5Bie 5016 S Am pss EN Operating mode select bits Event counter mode s s Count polarity select bits RW Count at falling edge of external signal Count at rising edge of external signal Mid Counts at both falling and rising edges of external signal Not selected I Nothing is assigned Undefined NEC This bit is ignored in event counter mode Undefined These bits are ignored in event counter moda gt 11 5 1 08 b7 bO 57 bO 0 register Addresses 5116 5016 Timer 2 register Addresses 5516 5416 15 to 0 These bits can be set to 000016 to FFFF16 Undefined RW Assuming that the set value n the counter divides the count source frequency by n 1 When reading the register indicates the counter value 7702 7703 Group User s Manual 21 27 APPENDIX Appendix 3 Control registers Pulse period pulse width measurement mode b7 56 b5 04 b3 02 bl Timer Bi mode register i 0 to 2 Addresses 5 16 5016 _ Fundions reset RW ER o fw Operating mode select bits 1 0 Pulse period Pulse width measurement mode Measurement mode select bits Pulse period measurement Interval between falling edges of measurement pulse Pulse period measurement Interval between rising edges of measurement pulse Pulse width m
234. de 2 7702 7703 Group Users Manual 21 3 APPENDIX Appendix 1 Memory assignment Memory expansion mode e Memory size type M2 E2 Memory size type SFR area ie External area 00000016 00007F16 00008016 SFR area Internal RAM 00027F e gt 12 bytes Internal RAM 2048 bytes 00087F16 Bank 016 External area External area 008000 16 Internal ROM 00C00016 32 Kbytes Internal ROM 16 Kbytes _Y_OOFFFF16 01000016 Bank 116 y OMFFFF165 000142224 External area External area I FF000016 BE Bank 16 FFFFFF16 Fig 3 Memory assignment during memory expansion mode 1 21 4 7702 7703 Group User s Manual APPENDIX Appendix 1 Memory assignment Memory expansion mode Memory size type M6 E6 0000064 ore S Rama _ p 00008016 External area Internal RAM Internal RAM 2048 bytes 2048 bytes 00087F16 Bank 016 External area Z External area A 00100016 00400016 Internal ROM 60 Kbytes Internal ROM 48 Kbytes OOFFFF16 01000016 Bank 116 O1FFFF16 External area External area FF000016 Bank FF16 FFFFFF16 Fig 4 Memory assignment during memory expansion mode 2 7702 7703 Group User s Manual 21 5 APPENDIX Appendix 1 Memory assignment Microprocessor mode e Memory size type M2 E2 S1 Note 1 Memory size type M4 E4 M6 E6 8 E8 54 Note 1 00000016 7 00000016 00
235. de Refer to Chapter 19 PROM VERSION PROM version Including One time PROM 7702 7703 Group User s Manual 13 3 RESET 13 1 Hardware reset 13 1 2 State of CPU SFR area and internal RAM area Figure 13 1 2 shows the state of the CPU registers immediately after reset Figures 13 1 3 to 13 1 6 show the state of the SFR area and internal RAM area immediately after reset 0 0 immediately after a reset 1 1 immediately after a reset Undefined immediately after a reset Always 0 at reading Register name otate immediately after a reset b15 08 b7 00 Accumulator 015 08 b7 00 Accumulator B B b15 68 b7 00 Index register X X 015 68 b7 00 Index register Y Y 615 68 b7 bO Stack pointer S b7 00 Data bank register DT b7 bO Program bank register b15 08 b7 bO Program counter PC Contents at address FFFF46 Contents at address FFFEt16 b15 68 b7 bO Direct page register DPR b15 b8 b7 bO Processor status register PS IPL N Vm x DI Z C Fig 13 1 2 State of CPU registers immediately after reset 13 4 7702 7703 Group User s Manual RESET 13 1 Hardware reset SFR area 016 to 7F16 RW It is possible to read the bit state at reading The written value becomes valid data RO It is possible to read the bit state at reading The written value becomes invalid WO The written value becomes valid data It is not possible to
236. de cleared ignored RW Valid in UART mode Note 1 Sleep mode selected Note Bits 4 to 6 are ignored in the clock synchronous serial I O mode They may be either 0 or 1 Additionally fix bit 7 to 0 Fig 20 4 4 Structure of UART1 transmit receive mode register 20 8 7702 7703 Group User s Manual 7703 GROUP 20 4 Functional description 2 CTS RTS pin The M37703 does not have the CTS RTS pin Fix the CTS RTS select bit bit 2 at address 3Cie to 1 Figure 20 4 5 shows the structure of the UART1 transmit receive control register 0 and Figure 20 4 6 shows the structure of the port P8 direction register when using UART1 08 05 En 63 02 bl E UART1 transmit receive control register 0 Address 3C 6 Dm mum Im BRG count source select bits b1 50 00 f2 0 1 f16 164 RW 1512 Transmit register empty flag 0 Data present in transmit register During transmitting 1 No data present in transmit register Transmitting completed Nothing is assigned Fig 20 4 5 Structure of UART1 transmit receive contro register 0 67 06 b5 b4 b3 b2 bi b0 Port P8 direction register Address 1416 1 Output mode When using P82 as serial data O RW Fix these bits to 1 RW input pin RxD set bit 6 to 0 o mr Bits 0 to are not used in UART1 Fig 20 4 6 Struct
237. de select bits RW 0 0 One shot mode 0 1 Repeat mode RW 1 1 Repeat sweep mode 5 Trigger select bit Internal trigger RW 1 External trigger A D conversion start bit 0 Stop A D conversion RW 1 Start A D conversion 7 A D conversion frequency 0 f2 divided by 4 RW AD select bit 1 fe divided by 2 Notes 1 These bits are ignored in the single sweep and repeat sweep modes They may be either 0 or 1 2 When selecting an external trigger the AN7 pin cannot be used as an analog input pin 3 Writing to each bit except bit 6 of the A D control register must be performed while the A D converter halts Fig 20 4 7 Structure of A D control register 20 10 7702 7703 Group User s Manual 7703 GROUP 20 4 Functional description 04 b2 bl sy E Port P7 direction register Address 11 16 EN Corresponding bit name Functions KA ANo pin 0 Input mode 1 mode converter s input pins set the Fix these bits to 1 AN7 pin ADTRG pin 0 Input mode 1 Output mode When using this pin as A D converter s input pin or external trigger input pin set this bit to 0 Fig 20 4 8 Structure of the port P7 direction register when using A D converter 7702 7703 Group User s Manual 20 11 7703 GROUP 20 5 Electrical characteristics 20 5 Electrical characteristics The M37703 electrical characteristics is the same as the M37702 s except for the absolute maximum r
238. ding to the operating mode Table 5 2 2 lists reading and writing from and to the timer Ai register Table 5 2 1 Memory assignment of timer Ai register Timer Ai register Low order byte Timer 0 register Address 4616 Timer A1 register Address 4816 Timer A2 register Address 4 16 Timer A3 register Address 4C e Timer A4 register Address 4F46 Address 4 6 Note VWhen reset the contents of the timer Al register are undefined Table 5 2 2 Reading and writing from and to timer Ai register Operating mode Write Timer mode Counter value is read out During counting Event counter mode Note 1 Written to only reload register lt When not counting gt One shot pulse mode Undefined value is read out written to both counter and Pulse width modulation PWM mode reload register Notes 1 Also refer to Precautions when operating in timer mode and Precautions when oper ating in event counter mode 2 When reading anc writing to from the timer Ai register perform them in an unit of 16 bits 5 4 7702 7703 Group User s Manual TIMER A 5 2 Block description 5 2 2 Count start register This register is used to start and stop counting Each bit of this register corresponds to each timer Figure 5 2 2 shows the structure of the count start register 67 b6 b5 04 b3 b2 bl bO Count start register Address 4016 Fm sn Cree eem Timer AO count start bit _ Stop counting Start counting L3 Timer
239. dix 5 Countermeasures against noise 3 Protection with Vss pattern For double sided boards in which the oscillator is mounted on one side mount side make sure that there is a Vss pattern at the same position as the oscillator on the reverse side solder side of the board This Vss pattern must be connected to the microcomputer s Vss pin in the shortest possible distance and must be located away from the other Vss patterns Example of Vss pattern on reverse side of oscillator M37702 Example of mount pattern for oscillator unit Separate the Vss pattern for oscillator from the Vss supply line Fig 19 Vss pattern on reverse side of oscillator 21 42 7702 7703 Group User s Manual APPENDIX Appendix 5 Countermeasures against noise 5 Processing of ports Take protective measures for ports in both hardware and software lt Hardware protection gt Insert a resistor of 100 ohms or more in series Software protection For ports in the input mode try reading in several times to detect whether their levels are matched or not For ports in the output mode since the output data can reverse owing to noise periodically set the port Pi register Set the port Pi direction register again at stated periods Data bus mu Port latch imm 72 Fig 20 Processing of ports 7702 7703 Group User s Manual 21 43 APPENDIX Appendix 5 Countermeasures against noise 6 Reinforcement of the power
240. dth 25 _ 15 X ns t External clock rise time 771014 8 ms t External clock fallime 8 13 hupip Port P1 input setup time 141 8 X ns tsuP20 Port P2 input setup time 45 30 Port P4 input setup time 100 60 13 bue PorP5inputtsetptime 7 10 60 13 bup Port P6 input setup time 7110 60 ns Port P7 input setup time 60 n tsupeo e PortPBinputsetuptime 110202 60 _ emo jPotPfinpthodtim 00 o n ber Port P2 input hold time 3D 00 1 0 OJ PorP4inputhodtim 20 0 715 heso 5 input hold 400 o 75 bere PotP6inputholdtm 10 0f ns be 7 PortP7inputholdtime L 0 of the peo Port P8 input hold time ts Switching characteristics Vcc 5 V 10 Vss 0 V Ta 20 to 85 C unless otherwise noted Symbol Parameter Unit Wero _ PortP4 data 100 80 ns Wero 5 data outputdelaytime 100 80 ns Wero data outputdelaytime 100 80 ns Wero PortP7dalaouputdeaylims o 100 80 ns Wero data outputdelay ime 100 80 ns te outptdelay ime 22L4L0 0 2010 18 ns wep E low level pulsewidth 19 50 ms ta Poa E 30 1124 ns t Po Port P1 data output delay time BYTE L
241. e Tn bes rs beso PotP7imuthod me oO of ns tero Port PB inputholdtime 1291 11 Switching characteristics Vcc 2 7 5 5 V Vss 0 V 40 to 85 C f Xw 8 MHz unless otherwise noted Symbol Parameter Unit lago PortP5dataoutputdelayme 300 ns la output delay time 0 40 ns Elow pulsewidth 2 146 X ms tyrone Port PO address output delay time o Z o Z o Z 1 50 X ns ta E P1Q Port P1 data output delay time BYTE L 1 130 ns Port P1 floating start delay time BYTE L 10 ns taera PortPiaddressoutputdelaytime 509 X ns tap1a aLE Port P1 address output delay time 140 X ns P2 data output delay time 130 ns 20 Port P2 floating start delay time 10 ns P2 address output delay time 509 ns tapza ALE Port P2 address output delay 14 ms ALE output delay time 4 ns twas ALEpulsewidth o 60 X ns taere output delay time 509 X ns tarw R W output delay time 215051 75 Note For test conditions refer to Figure 18 4 1 This is depending For data formula refer to Table 18 4 2 7702 7703 Group User s Manual 18 27 LOW VOLTAGE VERSION 18 4 Electrical characteristics Switching characteristics Vcc 2 7 5 5 V Vss 0 V 40 to
242. e 5 3 2 Count source In the timer mode the count source select bits bits 6 and 7 at addresses 5616 to 5A e select the count source Table 5 3 2 lists the count source frequency Table 5 3 2 Count source frequency Count source Count source Count source frequency a bits b7 f Xw 25 MHz 7702 7703 Group User s Manual 5 13 TIMER A 5 3 Timer mode 5 3 3 Operation in timer mode When the count start bit is set to 1 the counter starts counting of the count source When the counter underflows the reload register s contents are reloaded and counting continues The timer Ai interrupt request bit is set to 1 when the counter underflows in The interrupt request bit remains set to 1 until the interrupt request is accepted or the interrupt request bit is cleared to 0 by software Figure 5 3 4 shows an example of operation in the timer mode Reload register s contents FFFF16 Starts counting Stops counting Restarts counting I I I 1 Counter contents Hex 000016 Set to 1 by software Cleared to 0 by software Setto 1 by software 4 7 Count start bit Timer Ai interrupt 1 request bit 9 fi frequency of count source I f fie fea f512 Cleared to O when interrupt request is accepted or cleared by software Fig 5 3 4 Example of operation in timer mode without pulse output and ga
243. e FFF e is set to Watchdog timer The watchdog timer interrupt is a nonmaskable interrupt When the watchdog timer interrupt request is accepted the processor interrupt priority level IPL is set to 1112 Table 9 2 1 Occurrence interval of watchdog timer interrupt request Watchdog timer 25 MHz frequency select bit Count source Occurrence interval 0 41 94 ms 1 32 2 62 ms 7702 7703 Group User s Manual 9 5 WATCHDOG TIMER 9 2 Operation description 1 Example of program runaway detection Write to the address 6046 watchdog timer register before the most significant bit of Watchdog timer becomes 0 In the case that Watchdog timer is used to detect a program runaway if writing to address 60 e is not performed owing to a program runaway the watchdog timer interrupt request occurs when the most significant bit of Watchdog timer becomes 0 It means that a program runaway has occurred To reset the microcomputer after a program runaway write 1 to the software reset bit bit 3 at address 5E e in the watchdog timer interrupt routine Address 6016 Value o watchdog timer 16 Note 1 Watchdog timer interrupt request occur program runaway Watchdog timer interrupt routine Software reset bit 1 Note 2 Address 5 16 b3 Reset microcomputer Notes 1 Initialize write to address 6016 Watchdog timer before the most significant bit of Watchdog timer becomes 0
244. e Note counting by Watchdog timer can be performed Refer to Figure 9 3 1 Note It is selected with the watchdog timer frequency select bit Clock 2 or 1512 Lb J jo HOLD pin input signal i Count source actually counted by Watchdog timer When HOLD pin s input signal level changes in duration which is shorter than 1 cycle of fs2 or fs12 Fig 9 3 1 Watchdog timer s count source 9 8 7702 7703 Group User s Manual CHAPTER 10 STOP MODE 10 1 Gioek generating circuit 10 2 Operation description 10 3 Precautions for Stop mode STOP MODE 10 1 Clock generating circuit This chapter describes Stop mode Stop mode is used to stop oscillation when there is no need to operate the central processing unit CPU The microcomputer enters Stop mode when the STP instruction is executed Stop mode can be terminated by an interrupt request occurrence or the hardware reset 10 1 Clock generating circuit Figure 10 1 1 shows the clock generating circuit CPU Central Processing Unit BIU Bus Interface Unit Watchdog timer frequency select bit Bit O at address 6116 f2 XIN 01 fte Operation clock for Q 164 Interrupt request 1 8 512 Watchdog timer frequency f512 select bit STP instruction f 32 Watchdog am internal peripheral devices Hold request Reset Watchdog t
245. e purchasing a product listed herein Mitsubishi Electric Corporation Semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes such as apparatus or systems for transportation vehicular medical aerospace nuclear or undersea repeater use he prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials if these products or technologies are subject to the Japanese export control restrictions they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination Any diversion or reexport contrary to the export control laws and regulations of JAPAN and or the country of destination is prohibited Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein Preface This manual describes the hardware of the Mitsubishi CMOS 16 bit microcomputers 7702 Group and 7703 Group After reading this manual the user will be able to understand the functions so that they can utilize their capabil
246. e 13 1 7 The microcomputer executes a program beginning with the address set into the reset vector addresses which are and Frr Fie 13 2 7702 7703 Group User s Manual RESET 13 1 Hardware reset 13 1 1 Pin state Table 13 1 1 lists the microcomputer s pin state while the RESET pin is L level Table 13 1 1 Pin state while RESET pin is L level 00 ldentification CNVss pin level Pin Port name Pin state M6 M8 M3 MD M2 M4 51 54 Mask ROM version Vss or Vcc Floating Outputs H level Vss Floating Vss Floating Outputs H level Outputs H or L level Outputs H level P5 to P8 Vcc P42 Vcc A8 D8 A15 Outputs H or L level 015 Ai6 Do A23 07 BHE R W HLDA E Outputs H level Outputs L level Outputs Vss d E LE HOLD RDY P43 Floating P47 P5 to P8 P2 Outputs P40 P41 P43 P47 Floating External ROM version PO to P8 Floating and EPROM versions Vco Note Floating Floating while supplying H level to two pins of P51 and P52 or one of them Outputs H or L level while sup plying L level to two pins of P51 and P52 Outputs H level Identification This expresses the internal memory type and its size identification Refer to Chapter 1 DESCRIPTION Note Each pin becomes the above state It is because the microcomputer enters the EPROM mo
247. e 81 ihe lower order address of the block MVP Mn I Mm t TransmHs ma data Block Transmission 16 done ihe higher arder address of the data block Advances the program counter but peciarms noting elis Tas Mama NENNEN Logical sum par bit of the contents of the accumulator and Note 1 2 Ihe contenta of he mamory is obtained The result lg on tered into the accumulato 42 09 MIS MZ The 3rd and the 2nd bytes of the instruction savad Into S 8 1 the stack this order MS 5 5 1 MIS MLLDPA FIMM Soacifies 2 sequentis bytes in the direct paga in the 2nd I byte of tha and saves the contents Into the 53 1 atack MES MEEDPRI HIMM S 8 1 FARCPC TIMM IMM Regards tha 2nd and 3rd bytes of the instruction as 16 bit numersis adds them the program counter and saves tha me M S EAR f 5 Saves ie conrenta of accumulator A inta the atack 5 1 Saves the contents of accumulator into the stack 21 62 7702 7703 Group User s Manual APPENDIX Appendix 8 Machine instructions mE FIT Processor status register REL KSR Y eee eee set r Um TEES EZ li B L 1 2 gt Lt er a Er P B m E JP A m H T EH BH 4 ERE a E E 5 8 Ble 5 op S 8
248. e bits corresponding to analog input pins to 0 Set bit 7 to 0 when selecting external trigger 4 8 5 One shot mode G A D conversion start bit to 1 b7 bo A D control register address 1 16 A D conversion start bit d Selecting external trigger Input falling edge to ADrnc pin m SERRE Note Write each bit except bit 6 of the A D control register when the A D conversion stops before trigger occurs Fig 8 5 1 Initial setting example of one shot mode Selecting internal trigger Trigger occur Qperation start 7702 7703 Group User s Manual A D CONVERTER 8 5 One shot mode 8 5 2 One shot mode operation description 1 2 When an internal trigger is selected A D converter starts operation when the A D conversion start bit is set to 1 The A D conversion is completed after 57 cycles of Then the contents of the successive approximation register conversion result are transferred to the A D register i 3 At the same time as step the A D conversion interrupt request bit is set to 1 The A D conversion start bit is cleared to O and the A D converter stops operation When an external trigger is selected A D converter starts operation when the input level to the ADtra pin changes from to L while the A D conversion start bit is 1 The A
249. e control register 1 Address 3D16 b7 b0 ll l NEE Transmit enable bit 1 Transmission enabled d Transmission starts In the case of selecting the CTS function transmission starts when the CTSi pin s input level is L Fig 7 3 1 Initial setting example for relevant registers when transmitting 20 7702 7703 Group User s Manual When not using interrupts SERIAL I O 7 3 Clock synchronous serial mode When using interrupts The UARTi transmit interrupt request occurs when the UARTI transmit buffer register becomes empty UARTO transmit receive control register 1 Address 3516 UART1 transmit receive control register 1 Address 3Dt6 07 00 LIII nb Transmit buffer empty flag hecking state of UARTi transmit buffer register 0 Data present in transmit buffer register 1 No data present in transmit buffer register Writing of next transmit data is possible p UARTI transmit interrupt Writing of next transmit data UARTO transmit buffer register Address 3216 UART1 transmit buffer register Address 3A16 bO 2 Note This figure shows the bits and registers required for processing Refer to Figure 7 3 5 about the change of flag state and the occurrence timing of an interrupt request Set transmit data Fig 7 3 2 Writing data after start of transmission 7702 7703 Group User s Manual 7 21 SERI
250. e count source Table 5 5 2 lists the count source frequency Table 5 5 2 Count source frequency 5 34 Count source Count source Count source frequency select bits b7 b6 25 MHz o 0 fe 2 4MH 8 12 5 MHz o 15 250kHz 390 625 kHz 7702 7703 Group User s Manual TIMER A 5 5 One shot pulse mode 5 5 3 Trigger The counter is enabled for counting when the count start bit address 4016 is set to 1 The counter starts counting when a trigger is generated after it has been enabled An internal or an external trigger can be selected as that trigger An internal trigger is selected when the trigger select bits bits 4 and at addresses 5616 to 5Ais are 002 or O12 an external trigger is selected when the bits are 102 or 112 If a trigger is generated during counting the reload register s contents are reloaded and the counter continues counting If generating a trigger during counting make sure that a certain time which is equivalent to one cycle of the timer s count source or more has passed between the previous generated trigger and a new generated trigger 1 When selecting internal trigger A trigger is generated when writing 1 to the one shot start bit address 4216 Figure 5 5 4 shows the structure of the one shot start register 2 When selecting external trigger A trigger is generated at the falling of the TAiw 6 input signal when bit 3 at addresse
251. e operation for the input voltage from the one selected analog input pin is performed once and the A D conversion interrupt request occurs when the operation is completed 8 5 1 Settings for one shot mode Figure 8 5 1 shows an initial setting example of the one shot mode When using an interrupt it is necessary to set the relevant registers to enable the interrupt Refer to Chapter 4 INTERRUPTS for more descriptions 8 14 7702 7703 Group User s Manual Y A D CONVERTER 4 b A D control register 0 ANo selected 1 selected 0 AN selected 1 ANs selected 0 AN4 selected 1 AN5 selected 0 ANe selected 1 AN7 selected One shot mode Trigger select bit 0 Internal trigger 1 External trigger A D conversion start bit 0 Stop A D conversion select bit 0 f2 divided by 4 1 2 divided by 2 b7 b0 l olol LL A D control register address 1 16 Analog input select bits b2 b1 bO A D conversion frequency 0 AD lnterrupt priority level b7 bo Tm Interrupt priority level select bits Set to a level between 1 to 7 when using this interrupt Set to a level 0 when disabling this interrupt A D conversion interrupt control register address 7016 d Port P7 direction register b7 bO Port P7 direction register address 1116 ANo AN AN2 AN4 ANs ANe AN7 oet th
252. e rea Port P6 data output delay time 12 10 80 Port P7 data output delayatime 100 80 Port P8 data output delay ime 10 f 80 be output delay timet 0120 0 18 wep Elow pulse width 200001204 _ 130 PO address Output delay time 30 12 ta E P1Q Port P1 data output delay time BYTE L 70 j 45 txe Piz Port P1 floating start delay time BYTE 4 1 5 5 kipi Port P1 address output delay time 1309 12 Port P1 address output delay time 124 5 tue req PortP2dataoutputdelaytime 70 45 i t e22 PortP2floatingstartdelaytime C o Z 1 5 J 5 PortP2 address output delay time 01309 12 lyrea ate Port P2 address output delay time 1244 tae ALE output delay time 0 4 _ 4 P e ALEpusewdh 1 O 35 22 X twee BHEoutputdelaytime 130 20 tarw R W output delay time U 30 j 2 Note For test conditions refer to Figure 15 10 1 This is the value depending on For data formula refer to Table 15 9 1 7702 7703 Group User s Manual Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 15 21 ELECTRICAL CHARACTERISTICS 15 9 Memory expansion mode and microprocessor mode with Wait Switching characteristics Vcc 5 10 Vss 0 V Ta 20 to 85 C unless otherwise noted ae MERC Symbol Parameter
253. e setting of interrupt priority level and Table 4 3 2 lists the interrupt enabled level corresponding to IPL contents All the interrupt disable flag 1 interrupt request bit interrupt priority level select bits and processor interrupt priority level IPL are independent of one another they do not affect one another Interrupt requests are accepted only when the following conditions are satisfied Interrupt disable flag 1 0 Interrupt request bit 1 Interrupt priority level Processor interrupt priority level IPL 4 8 7702 7703 Group User s Manual INTERRUPTS 4 3 Interrupt control Table 4 3 1 Setting of interrupt priority level Interrupt priority level select bits Interrupt priority level Priority b2 b 0 o 0 1 let 1 0 Jjlevl2 J 0 O _0 o 0 1 j tee8 1 Of eve 002 _1_ 1 jbevl7 High Table 4 3 2 Interrupt enabled level corresponding to IPL contents IPL2 Enabled interrupt priority level O 9 Enable level 1 and above interrupts Enable level 2 and above interrupts 1 O Enable level 3 and above interrupts 0 0 0 0 a Enable level 4 and above interrupts 1 1 1 1 Enable level 5 and above interrupis Enable level 6 and level 7 interrupts 1 0 Enable only level 7 interrupt Disable all maskable interrupts IPLo Bit 8 in processor status
254. e shifted by 1 bit to the right 3 Steps and are repeated at each rising of the transfer clock When one set of data has been prepared in other words the shift according to the selected data format has been completed the UARTi receive registers contents are transferred to the UARTI receive buffer register Simultaneously with step the receive complete flag is set to 1 and the UARTIi receive interrupt request occurs and its interrupt request bit is set to 1 The receive complete flag is cleared to 0 when the low order byte of the UARTI receive buffer register is read out Figure 7 4 11 shows an example of receive timing when the transfer data length is 8 bits Transmitter side Receiver side Fig 7 4 10 Connection example 7702 7703 Group User s Manual 7 49 SERIAL I O 7 4 Clock asynchronous serial I O UART mode BRGi count LT source 4 s Receive enable bit ed RxDi Stop bit Transfer clock Receive 1 complete flag RTSi 4 UARTi receive interrupt 1 request bit 0 The above timinig diagram applies to Cleared to 0 when interrupt request is accepted the following conditions or cleared by software Parity disabled 1 stop bit RTS function selected Fig 7 4 11 Example of receive timing when transfer data length is 8 bits when parity disabled selecting 1 stop bit 7 50 7702 7703 Group User s Manu
255. easurement Interval from a falling edge to a rising edge and froma rising edge to a falling edge of measurement pulse Not selected 4 Nothing is assigned 5 Timer Bi overflow flag No overflow Undefined Note Overflowed Count source select bits m Note The timer Bi overflow flag is cleared to 0 by writing to the timer Bi mode register with the count start bit 1 b15 68 b7 bO b7 29 Timer BO register Addresses 5116 5016 Timer B2 register Addresses 5516 5416 0 The measurement result of Undefined pulse width is read out 21 28 7702 7703 Group User s Manual APPENDIX Appendix 3 Control registers Processor mode register 67 06 b5 b4 b3 b2 bli Processor mode register Address 5 16 LINE EMEN 207 b1 bO Sales Processor mode bits 0 0 Single chip mode 0 1 Memory expansion mode M 0 Microprocessor mode 1 1 Not selected T 1 2 Wait bit Software Wait is inserted when accessing external area No software Wait is inserted when accessing external area Software reset bit The microcomputer is reset by WO writing 1 to this bit The value is i 0 at reading e pee b5 64 MELLE Interrupt priority detection time 0 0 7 cycle amp of 0 01 4 cycles of 9 1 2 Gycles 1 Not selected Ls Fm bio v idrev eer Clock 6 1 outpu
256. ecimal arithmetic is performed with each word treated as two or four digits decimal determined by the data length flag Decimal adjust is automatically performed Decimal operation is possible only with the ADC and SBC instructions Use the SEP instruction to set this flag to 1 and use the CLP instruction to clear it to 0 This flag is cleared to 0 at reset 5 Bit 4 Index register length flag x It determines whether each of index register X and index register Y is used as a 16 bit register or an 8 bit register That register is used as 16 bit register when this flag is 0 and as an 8 bit register when it is 1 Use the SEP instruction to set this flag to 1 and use the CLP instruction to clear it to 0 This flag is cleared to 0 at reset Note When transferring data between registers which are different in bit length the data is transferred with the length of the destination register but except for the TXA TYA TXB TYB and TXS instructions Refer to 7700 Family Software Manual for details 2 8 7702 7703 Group User s Manual 6 7 8 9 CENTRAL PROCESSING UNIT CPU 2 1 Central processing unit Bit 5 Data length flag m It determines whether to use a data as a 16 bit unit or as an 8 bit unit A data is treated as a 16 bit unit when this flag is 0 as an 8 bit unit when it is 1 Use the SEM or SEP instruction to set this flag to 1 an
257. ected by the other signals 1 Isolation from signal wires where a large current flows The signal wires where a large current exceeding the microcomputer s current limits accepted flows must be located as far away from the microcomputer especially the oscillator as possible example motors LEDs and thermal M37702 heads When a large current flows m in these signal wires noise due to Mutual inductance mutual inductance is generated Large current Fig 17 Connection of signal wires where a large current flows Reasons A system using a microcomputer contains signal wires to control for 2 Isolation from signal wires whose levels change rapidly The signal wires whose levels change rapidly must be located as far away from the oscillator as possible Make sure that signal wires whose levels change rapidly do not cross any other clock related or noise susceptible signal wires Reasons The signal wires whose voltage levels change rapidly tend to affect M37702 other signal wires as the signal level Must not cross changes from high to low or from other signal wires low to high Especially if these signal wires cross clock related signal wire they can disturb the clock wavetorm causing the microcomputer to malfunction or a program runaway pin for a signal whose level changes rapidly Fig 18 Wiring of rapidly level changing signal wire 7702 7703 Group User s Manual 21 41 APPENDIX Appen
258. ection of an interrupt priority new detection of that does not start Refer to Figure 4 6 1 Since the state of the interrupt request bit and interrupt priority levels are latched during detection of interrupt priority even if the bit state and priority levels change the detection is performed on the previous state before it has changed Interrupt source Y Comparator X Resultant priority level sent from the preceding Priority level comparator Highest priority at this point comparison Y Priority level of interrupt source Y Z Highest priority at this point eWhen X gt Y then Z X eWhen X gt Y then Z Y Fig 4 5 2 Interrupt priority level detection model 4 12 7702 7703 Group User s Manual INTERRUPTS 4 6 Interrupt priority level detection time 4 6 Interrupt priority level detection time After sampling had started an interrupt priority level detection time has elapses before an interrupt request is accepted The interrupt priority level detection time can be selected by software Figure 4 6 1 shows the interrupt priority level detection time As the interrupt priority level detection time normally select 2 cycles of internal clock 1 Interrupt priority detection time select bits 67 b6 05 b4 53 02 bl LBLLLLLI Processor mode register Address 5 16 L t Processor mode bits Wait bit Software reset bit Interrupt priority detection time select bits 7 cycles of 9
259. ed because it is sampled immediately before Wait by software Wait indicated lt Wait gt however CPU stops at L level RDY pin input level amp sampling timing L J Q Clock 1 N a D CPU E 72277727 TS AE x 9 7 Bus in use Fig 12 3 1 Timings of acceptance of Ready request and termination of Ready state 7702 7703 Group User s Manual 12 15 CONNECTION WITH EXTERNAL DEVICES 12 4 Hold function 12 4 Hold function When composing the external circuit DMA which accesses the bus without using the central processing unit CPU the Hold function is used to generate a timing for transferring the right to use the bus from the CPU to the external circuit Fix bit 0 of the port P4 direction register to 0 In the memory expansion or microprocessor mode the microcomputer enters Hold state by input of L level to the HOLD pin and retains this state while the level of the HOLD pin is at L Table 12 4 1 lists the microcomputer s state in Hold state In Hold state the oscillation of the oscillator does not stop Accordingly the internal peripheral devices can operate However Watchdog timer stops operating Table 12 4 1 Microcomputer s state in Hold state Item State Oscillation Operating Operating cpu Stopped at L E Stopped at H Pins Ao to As Ds to A1s D15 Floating 0 to A23 D7 R W Pins Note 1 ALE Outputs L l
260. egisters Addresses 7016 to 7F 6 a emn Interrupt priority level select bits Level 0 Interrupt disabled Level 1 Low level Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 High level Interrupt request bit Note 1 0 No interrupt request RW 1 Interrupt request Polarity select bit 0 Set the interrupt reguest bit at RW H level for level Sense and at falling edge for edge sense 1 Set the interrupt request bit at L level for level sense and at rising edge for edge sense Level sense Edge sense select bit Edge sense Level sense 7 EI Nothing is allocated Undefined m Notes 1 The INTo to INT interrupt request bits are invalid when selecting the level sense 2 Use the SEB or CLB instruction to set the INTo INT2 interrupt control registers Fig 4 10 1 Structure of INT i 0 to 2 interrupt control register 7702 7703 Group User s Manual 4 21 INTERRUPTS 4 10 External interrupts INTi interrupt b7 06 b5 b4 b3 b2 bl Port P6 direction register Address 1016 EN TA4out pin 0 Input mode RW 1 Output mode TA n pin aw When using pins as external interrupt INTo pin input pins set the corresponding bits nw sa to 0 Ir ERE 7 mem m Bits 0 1 and bits 5 to 7 are not Used for external interrupts Fig 4 10 2 Relationship between port P6 direction regisier and input pins of external
261. enerated with the count start bit 1 5 30 7702 7703 Group User s Manual TIMER A 5 5 One shot pulse mode b7 06 05 04 b3 015 b7 b2 bi 00 b1 60 1 0 One shot pulse mode b4 b3 0 O Writing 1 to one shot start bit 0 1 pin functions as progra mmable I O port 10 Falling edge of pin s input signal 1 Rising edge of pin s input signal b7 b6 00 fe 0 1 f16 164 1 512 Timer 0 register Addresses 4716 4616 Timer A1 register Addresses 4916 4816 Timer A2 register Addresses 4 16 4 16 Timer register Addresses 4016 4 16 Timer A4 register Addresses 4Fi6 4E16 Bi 15 to 0 These bits can be set to 000116 to Undefined WO Assuming that the set value n the H level width of the one shot pulse output from the TAiour pin is expressed as follows n fi fi Frequency of count source fe fis fea or fs12 Fig 5 5 1 Structures of timer Ai mode register and timer Ai register in one shot pulse mode 7702 7703 Group User s Manual 5 31 TIMER A 5 5 One shot pulse mode 5 5 1 Setting for one shot pulse mode Figures 5 5 2 and 5 5 3 show an initial setting example for registers relevant to the one shot pulse mode Note that when using interrupts set up to enable the interrupts For details refer to Chapter 4 INTERRUPTS f Selecting one shot pulse mode and each function B
262. er above the counter and TAiour pin perform the same operations beginning from again Furthermore if a trigger is generated during counting the counter down counts once after this generated new trigger and it continues counting with the reload register s contents reloaded If generating a trigger during counting make sure that a certain time which is equivalent to one cycle of the timer s count source or more has passed between the previous generated trigger and a new generated trigger The one shot pulse output from the TAiour pin can be disabled by ciearing the timer Ai mode register s bit 2 to 0 Accordingly timer Ai be also used as an internal one shot timer that does not perform the pulse output In this case the TAiour pin functions as a programmable port 5 36 7702 7703 Group User s Manual TIMER A 5 5 One shot pulse mode EEEE n Reload registers contents Stops Starts counting counting Starts counting Stops counting Counter contents Hex 000116 Set to 1 by software Count start bit 1 0 Trigger during counting TAi pin H input signal 1 fix n1 One shot pulse H output from TAiour pin Timer Ai interrupt 1 request bit fi Frequency of count source f2 fie fea or f512 Cleared to 0 when interrupt request is accepted or cleared by software When the count start bit O counti
263. er i to 4 Addresses 5616 to 5 16 Operating mode select bits 0 Timer mode EREI Pulse output function select bit 0 No pulse output TAiour pin functions as a programmable I O port 1 Pulse output TAiour pin functions as a pulse output pin b4 b3 0 0 No gate function Gate function select bits 0 1 J pin functions as a prog I rammabie port Gate function Counter counts only while pin s input signal is L level Gate function I Counter counts only while pin s input signal is H level l b7 b6 00 f2 01 72 10 164 1 1 12 615 08 Timer AO register Addresses 4716 4616 b7 90 b7 bO Timer A1 register Addresses 4916 4816 Timer register Addresses 4016 4 16 Timer A4 register Addresses 4F16 4 16 15 to 0 These bits can be set to 000016 to FFFF e Undefined RW Assuming that the set value n the counter divides the count source frequency by n 1 When reading the register indicates the counter value 7702 7703 Group User s Manual 21 21 APPENDIX Appendix 3 Control registers Event counter mode 67 06 b5 b4 b3 b2 bi b0 x x o Timer Ai mode register i 0 to 4 Addresses 5616 to 5A16 LIN NACL Even counter mode ESL Pulse output function select bit 0 No pulse output TAiour
264. er 4 Addresses 2816 D register 5 Addresses 2A 16 D register 6 Addresses 2C16 D register 7 Addresses 2E16 67 06 05 b4 b3 b2 bl A A A A A A A A 7 to 0 Reads an A D conversion result lundeined RO F Fig 8 2 4 Structure of A D register i Table 8 2 2 Correspondence of analog input pin and A D register i Analog input pin A D register i where conversion result is stored ANo pin A D register 0 AN pin A D register 1 AN pin A D register 2 ANs pin A D register 3 AN pin A D register 4 ANs pin A D register 5 ANe pin A D register 6 AN pin A D register 7 7702 7703 Group User s Manual 8 7 A D CONVERTER 8 2 Block description 8 2 4 A D conversion interrupt control register Figure 8 2 5 shows the structure of the A D conversion interrupt control register For details about interrupts refer to Chapter 4 INTERRUPTS b7 b6 b5 b4 b3 b2 bi A D conversion interrupt control register Address 7016 Level 0 Interrupt disabled ind Level 1 Low level Level 6 Level 2 Level 3 RW Level 4 Level 5 RW Level 7 High level 3 Interrupt request bit 0 No interrupt request RW 1 Interrupt request Nothing is assigned Umeined Note Use the SEB or CLB instruction to set the A D conversion interrupt control register Fig 8 2 5 Structure of A D conversion interrupt contro register 1 Interrupt priority level select bits bits 2 10 0 These bi
265. eripheral devices Internal peripheral devices Count input in event counter mode Gating input in timer mode External trigger input in one shot pulse mode External trigger input in pulse width modulation mode tw TAH TAIN input Up down input count input in event counter mode tc UP lt tw UPH lt gt TAiour input Up down input TAiour input Up down input TAIN input When count by falling k UfeuP tsuUP T TAIN input When count by rising Two phase pulse input in event counter mode c TA lt lt TAjiN input tsu TAjin TAjout tsu TAjin TAjout TAjour input tsu TAjout TAjin gt tsu TAjout TAjin Test conditions Vcc 5 V 10 timing voltage 1 0 V 4 0 V 15 3 7702 7703 Group User s Manual ELECTRICAL CHARACTERISTICS 15 5 Internal peripheral devices Timer B input count input in event counter mode Symbol Parameter Unit input cycle time one edge count 125 80 ns tw TBH input high level pulse width one edge count 62 40 ns tw TBL input low level pulse width one edge count 62 40 ns input cycle time both edges count 250 11601 ns tw TBH TBim input high level pulse width both edges count 125 80 ns tw TBL input low level pulse widt
266. eristics tc 61 E td P1A E td E 6 1 tw EL 9 Address zi td E P1Q th E th E P1A R W ta E Test conditions 1 E P0 P3 Vcc 2 725 5 Output timirig voltage VoL 0 8 V 2 0 V eData input 0 16 V VIH 0 5 V Test conditons P4 P8 Vcc 2 Output timing voltage VoL 0 8 V 2 0 V 7702 7703 Group User s Manual 7 5 5 Input timing voltage VIL 0 2 V 0 8 V 18 25 LOW VOLTAGE VERSION 18 4 Electrical characteristics 18 26 Memory epxansion mode and microprocessor mode With no Wait Head f XiN 1 Address output Ao A7 Address output 15 BYTE z H Address Data output As Ds At15 D15 BYTE L Data input Ds D15 BYTE L Address Data Input 6 00 23 07 Data input Do D7 ALE output BHE output R W output Port Pi input i 4 8 tw L tw H t t tc 1 td POA E 1 td P1A E td P1A ALE Test conditions 41 E eVcc 2 7 5 5 V ta E 6 1 tw EL lt gt lt 9 lt lt 2 17 th ALE P1A tsu P1D E 22 th ALE P2A tsu P2D E C Ades C Ades lh
267. ernal address bus and pins Do to Dis of the external data bus are assigned to the same pins When the BYTE pin level described later is L i e external data bus width is 16 bits the As Ds to A1s D15 and A e Do to Azs D7 pins perform address output and data input output with time sharing When the BYTE pin level is H i e external data bus width is 8 bits the A e Do to Azs Dz pins perform address output and data input output with time sharing and pins As to Ais output addresses Memory expansion mode 016 SFR area Note Internal RAM area 28016 00016 Internal ROM area 1000016 FFFFFFi6 External area Note Addresses 216 to 91e become an external area Fig 12 1 2 External area Microprocessor mode 016 280164 FFFFFF46 7702 7703 Group User s Manual SFR area Note Internal RAM area 12 5 CONNECTION WITH EXTERNAL DEVICES 12 1 Signals required for accessing external devices 2 External data bus width switching signal BYTE pin level This signal is used to select the external data bus width between 8 bits and 16 bits When this signal level is L the external data bus width is 16 bits when the level is H the bus width is 8 bits refer to Table 12 1 1 Fix this signal to either H or L level This signal is valid only for the external areas When accessing the internal areas the data bus width is always 16 bits 3 Enable signal E
268. errupt request occurs supply of clock starts The interrupt request which occurs in is accepted The following interrupts are used to terminate Wait mode The occurrence of the watchdog timer interrupt request also terminates Wait mode INTi interrupt i 0 to 2 Ai interrupt i 0 to 4 Timer Bi interrupt i 0 to 2 UARTI transmit interrupt i 0 1 UARTi receive interrupt i 0 1 A D converter interrupt Note Refer to Chapter 4 INTERRUPTS and each functional description about interrupts Before executing the WIT instruction enable interrupts used to terminate Wait mode In addition the interrupt priority level of the interrupt used to terminate Wait mode must be higher than the processor interrupt priority level IPL of the routine where the WIT instruction is executed When the above multiple interrupts are enabled Wait mode is terminated by the first interrupt request 11 2 2 Termination by hardware reset The CPU and the SFR area are initialized in the same way as a system reset However the internal RAM area retains the same contents as that before executing the WIT instruction The termination sequence is the same as the internal processing sequence which is performed after a reset To determine whether a hardware reset was performed to terminate Wait mode or a system reset was performed use software after a reset Refer to Chapter 13 RESET for details about a reset
269. ers according to the bytes fetched Into the instruction queue buffer or according to whether tha memory read write address is odd or even It also differ amp when the external region memory Is accessed by Note 1 Tha operation code at the upper row 15 used for accumulator and the operation at tha lower row 15 used for accumulator B Note 2 When setting flag m 0 handle the data as 16 bit data in the immediata addressing mode the number of bytes increments by 1 Note 3 The number of cycles increments 2 when branching Hole 4 The operation code on the upper row is used for branching in tha range of 128 1 127 and ihe operation code on the lower row is used for branching in the range of 32768 32767 Note 5 When handling 16 bit data with flag 0 the byte in the table is incremented by 1 Note 6 Type ot register A B X Y DPR DT PG PS Number ofcycles 2 2 2 2 2 1 The number of cycles corresponding to the register ta be pushed are added The number of cycles when no pushing is dona is 12 i indicates the number of registers among A B X Y DPA and PS to be saved while i indicates the number of registers among DT and PG te be saved Nite 7 ol register A B DPR DT PS Numbar of cycies 3 4 3 3 The number of cycles corresponding to the register to be pulled are added The number of cycles when no pulling is 1 14 i indi
270. erview Functions 103 500 ns the minimum instruction at f Xin 8 MHz 8 MHz maximum 16 bits X 3 UARTO UART1 UART or clock synchronous serial I O X 2 8 bit successive approximation method X 1 8 channels 12 bits X 3 3 external 16 internal priority levels O to 7 can be set for each interrupt with software Built in externally connected to a ceramic resonator or a quartz crystal oscillator 2 5 5 V 12 mW at supply voltage 3 V f Xin 8 MHz frequency 30 mW at supply voltage 5 V 8 MHz frequency Input Output withstand voltage 5 V 5 mA Maximum 16 Mbytes Port Input Output characteristics Memory expansion Operating temperature range 40 C to 85 C Device structure CMOS high performance silicon gate process Package 80 pin plastic molded QFP Note Low voltage versions except the M37702M2LXXXGP are the same except for the package type memory type and memory size 7702 7703 Group User s Manual 18 3 LOW VOLTAGE VERSION 18 2 Pin configuration 18 2 Pin configuration Figure 18 2 1 shows the M37702M2LXXXGP and the M37702M2L XXXHP pin configuration Figure 18 2 2 shows the M37702MALXXXFP pin configuration GG Q T 222222222 Bzagpz 2 0 2 P6e TB1IN lt 60 4 P86 RxD1 P65 TBOIN lt gt O 3 P8 TxD1 P64 INT2 lt gt 00 P63 INT1 lt gt lt gt 1 P62 INTo lt gt
271. es Hold request Reset O gt 9 Watchdog timer s eta signal Ready request ote Request of CPU wait from BIU acceptance of Hold request included WIT instruction R Note This is the signal generated when the watchdog timer s most significant bit becomes 0 Fig 11 1 1 Clock generating circuit 1129 7702 7703 Group User s Manual WAIT MODE 11 2 Operation description 11 2 Operation description When the WIT instruction is executed ceu and stop The oscillators oscillation is not stopped This state is called Wait mode In Wait mode the microcomputer s power consumption is reduced though the Vcc is power source voltage is maintained Table 11 2 1 lists the microcomputers state and operation in and after Wait mode Table 11 2 1 Microcomputer state and operation in and after Wait mode Item State in Operating Wait mode Stopped Clock er fa to i12 Operating Timer A Operating State and Operation Watchdog timer Retains the same state in which the WIT instruction was executed Operation By interrupt request Supply of 0CPU and starts just after the termination after termi occurrence C Q c nating Wait By hardware reset Operates in the same way as hardware reset mode 7702 7703 Group User s Manual WAIT MODE 11 2 Operation description 11 2 1 Termination by interrupt request occurrence When an int
272. eset vector address FFFE16 FFFF16 0 cpu CPU standard clock AP High order 8 bits address bus of CPU Fig 13 1 7 Internal processing sequence after reset 7702 7703 Group User s Manual 13 9 RESET 13 1 Hardware reset 13 1 4 Time supplying L level to RESET pin Time supplying L level to the RESET pin varies according to the state of the clock oscillation circuit When the oscillator is stably oscillating or a stable clock is input from the pin supply L level for 2 Ls or more ef the oscillator is not stably oscillating including a power on reset and In Stop mode supply L level until the oscillation is stabilized The time to stabilize oscillation varies according to the oscillator For details contact the oscillator manufacturer Figure 13 1 8 shows the power on reset condition Figure 13 1 9 shows an example of a power on reset circuit For details about Stop mode refer to Chapter 10 STOP MODE For details about clocks refer to Chapter 14 CLOCK GENERATING CIRCUIT Powered on here x 4 5V OV Note Refer to Figure 18 3 1 Power on reset conditions for the low supply voltage version Fig 13 1 8 Power on reset condition 13 10 7702 7703 Group User s Manual RESET 13 1 Hardware reset M37702 The delay time is about 11 ms when Cas 0 033 LF taz 0 34 X Ca us Ca pF Note Refer to Figure 18 3 2 Example of power on reset circuit for the l
273. ess 1F 16 LINE NN CC A D sweep pin select bits Valid in single sweep and repeat 0 0 ANo AN 2 pins sweep mode Note 1 0 1 ANo to ANs 4 pins 1 1 0 ANo to 6 pins 1 RW 1 1 ANo to AN 8 pins Note 2 Nothing is assigned Notes 1 These bits are invalid in the one shot and repeat modes They may be either 0 or 4 2 When selecting an external trigger the AN7 pin cannot be used as an analog input pin 3 Writing to each bit of the A D sweep pin select register must be performed while the A D converter halts Fig 8 2 3 Structure of A D control register 1 1 A D sweep pin select bits bits 1 and 0 These bits are used to select analog input pins in ihe single sweep mode or repeat sweep mode In the single sweep mode and repeat sweep mode pins which are not selected as analog input pins function as programmable I O ports 8 6 7702 7703 Group User s Manual A D CONVERTER 8 2 Block description 8 2 3 A D register i i 0 to 7 Figure 8 2 4 shows the structure of the A D register i When the A D conversion is completed the conversion result contents of the successive approximation register is stored into this register Each A D register corresponds to an analog input pin ANi Table 8 2 2 lists the correspondence of an analog input pin to A D register i D register 0 Addresses 2016 D register 1 Addresses 2216 D register 2 Addresses 2416 D register 3 Addresses 2616 D regist
274. essing modes using the stack are executed The contents of S indicate an address stack area for storing registers during subroutine calls and interrupts Bank 016 is specified for the stack area Refer to 2 1 6 Program bank register PG When an interrupt request is accepted the microcomputer stores the contents of the program bank register PG at the address indicated by the contents of S and decrements the contents of S by 1 Then the contents of the program counter PC and the processor status register PS are stored The contents of S after accepting an interrupt request is equal to the contents of S decremented by 5 before the accepting of the interrupt request Refer to Figure 2 1 2 When completing the process in the interrupt routine and returning to the original routine the contents of registers stored in the stack area are restored into the original registers in the reverse sequence PS gt PC gt PG by executing the RTI instruction The contents of S is returned to the state before accepting an interrupt request The same operation is performed during a subroutine call however the contents of PS is not automatically stored The contents of PG may not be stored This depends on the addressing mode The user should store registers other than those described above with software when the user needs them during interrupts or subroutine calls Additionally initialize S at the beginning of the program because its contents are
275. evel Pin 42 In the memory expansion mode When clock output select bit 1 this pin outputs clock When clock output select bit 0 this pin retains the state when Hold request was accepted In the microprocessor mode his pin outputs Clock gi Pins P4s to P47 P5 to P8 Note 2 Retains the state when Hold request was accepted Watchdog timer Stopped Clock output select bit Bit 7 at address 5E e Notes 1 The 7703 Group does not have the HLDA pin 2 When this functions as a programmable port 12 16 7702 7703 Group User s Manual CONNECTION WITH EXTERNAL DEVICES 12 4 Hold function 12 4 1 Operation description Judgment timing of the input level of the HOLD pin depends on the state using the bus While the bus is not in use the judgment is performed at every falling of While the bus is in use judgment is performed at the falling of the last in each bus cycle Additionally when accessing word data starting from an odd address with 2 bus cycle the judgment is performed only at the second bus cycle See Figure 12 4 1 When L level is detected at judgment of the input level the microcomputer enters Hold state This is called acceptance of Hold request When the Hold request is accepted cru stops next rising of At the same time the HLDA 5 level changes H to L When 1 cycle of has passed after the level of HLDA pin becomes L pins
276. face unit 2 2 3 Operation of bus interface unit BIU Figure 2 2 3 shows the basic operating waveforms of the bus interface unit BIU About signals which are input output externally when accessing external devices refer to Chapter 12 CONNECTION WITH EXTERNAL DEVICES 1 2 2 14 When fetching instructions into the instruction queue buffer When the instruction which is next fetched is located at an even address the BIU fetches 2 bytes at a time with the timing of waveform a However when accessing an external device which is connected with the 8 bit external data bus width BYTE H only 1 byte is fetched When the instruction which is next fetched is located at an odd address the BIU fetches only 1 byte with the timing of waveform a The contents at the even address are not taken When reading or writing data to and from the memory l O device When accessing 16 bit data which begins at an even address waveform is applied The 16 bits of data are accessed at a time When accessing a 16 bit data which begins at an odd address waveform b is applied The 16 bits of data are accessed separately in 2 operations 8 bits at a time Invalid data is not fetched into the data buffer When accessing 8 bit data at an even address waveform a is applied The data at the odd address is not fetched into the data buffer When accessing an 8 bit data at an odd address waveform a is app
277. ffer register 7702 7703 Group User s Manual 7 11 SERIAL I O 7 2 Block description The UARTI receive register is used to convert serial data which is input to the RxDi pin into parallel data This register takes in the input signal to the RxDi pin synchronously with the transfer clock one bit at a time The UARTi receive buffer register is used to read out receive data When reception is completed receive data which is taken in the UARTi receive register is automatically transferred to the UARTi receive buffer register The contents of UARTi receive buffer register is updated when the next data is ready before reading out the data which has been transferred to the UARTi receive buffer register i e an overrun error occurs The UARTi receive buffer register is initialized by setting the receive enable bit bit 2 at addresses 3516 3D e to 1 after clearing it to 0 Figure 7 2 9 shows the contents of UARTi receive buffer register when reception is completed High order byte Low order byte addresses 3716 3F 6 addresses 3616 3E16 b7 b7 b0 b0 se COC Receive data 9 bits In clock synchronous in UART mode ejojojoppoo fy Receive data 8 bits 1 s L Transfer data length 8 bits Same value as bit 7 in low order byte 2220 7 bits Same value as bit EM G in low order byte Receive data 7 bits Fig 7 2 9 Contents of UARTi receive buffer regi
278. ftware The above timing diagram applies to the following conditions Parity enabled 1 stop bit Tc 16 n 1 fi or 16 n 1 fEXT CTS function selected o frequency fe f16 f64 f512 fExT count source frequency external clock n Value set to BRGi TENDi Next transmit conditions are examined when this signal level is TENDi is an internal signal Accordingly it cannot be read from an external Fig 7 4 6 Example of transmit timing when transfer data iength is 8 bits when parity enabled selecting 1 stop bit Transfer clock T it enable bit ON Data is set in UARTi transmit buffer register Transmit buffer empty flag Tu UARTI transmit register transmit buffer register TENDi Staf TxDi Transmit register empty flag transmit interrupt request bit Cleared to 0 when interrupt request is accepted or cleared by software The above timing diagram applies to TENDi Next transmit conditions are examined when this signal level is H the following conditions TENDi is an internal signal Accordingly it cannot be read from an external Parity disabled 2 stop bits Tc 16 n 1 fi or 16 n 1 fEXT CTS function disabled fi count source frequency f2 f16 fe4 1512 fExT BRGi count source frequency external clock n Value set to BRGi Fig 7 4 7 Example of transmit timing when transfer data length is 9 bits
279. function Head from timer Ai register Write to timer Ai register Specifications External signal input to the TAiIN pin The count source s valid edge can be selected between the falling and the rising edges by software Up count or down count can be switched by external signal or software When the counter overflows or underflows reload register s contents are reloaded and counting continues For down count 1 n 1 For up count n Timer Ai register setting value FFFFis n 1 When count start bit is set to 1 When count start bit is cleared to 0 When the counter overflows or underflows Count source input Programmable port pulse output or up count down count switch signal input Counter value can be read out e While counting is stopped When value is written to timer Ai register it is written to both reload register and counter While counting is in progress When a value is written to timer Ai register it is written to only reload register Transferred to counter at next reload time 7702 7703 Group User s Manual 5 19 TIMER A 5 4 Event counter mode Table 5 4 2 Specifications of event counter mode when using two phase pulse signal processing function with timers A2 A3 and A4 ltem Count source Count operation Divide ratio Count start condition Count stop condition Interrupt request occurrence timing TAjin TAjour 2 to 4 pin function
280. function Ready function provides a function to facilitate access to external devices that require a long access time Fix bit 1 of the port P4 direction register to 0 By supplying L level to the RDY pin in the memory expansion or microprocessor mode the microcomputer enters Ready state and retains this state while the RDY pin is at L level Table 12 3 1 lists the microcomputer s state in Ready state In Ready state the oscillator s oscillation does not stop so that the internal peripheral devices can operate Ready function is valid for the internal and external areas Table 12 3 1 Microcomputer s state in Ready state Item otate Oscillation Operating QcPu Stopped at L Pins Ao to As Ds to Retains the state when Ready request was accepted Ais Dis Aie Do to 07 E R W BHE HLDA Note 1 ALE Pins P4s to P47 P5 to P8 Note 2 P42 1 In the memory expansion mode When clock output select bit 1 this pin outputs clock When clock output select bit 0 this pin retains the state when Ready request was accepted In the microprocessor mode This pin outputs Clock Watchdog timer Operating Clock output select bit Bit 7 at address 5E e Notes 1 The 7703 Group does have the pin 2 When this functions aS a programmable port 7702 7703 Group User s Manual 12 13 CONNECTION WITH EXTERNAL DEVICES 12 3 Ready function 12 3 1 Opera
281. g edge of external signal Counts at rising edge of external signal Up down switching factor select gt Contents of up down register EN Input signal to 1 Aiour eee NUN INE 25 Fix this bit to O in event counter mode RRR eR tal These bits are ignored in event counter mode b15 b8 po 0 register Addresses 4716 4616 Timer A1 register Addresses 4916 4816 ll Fines register Addresses 4Bis 4 Timer register Addresses 4016 4 16 Timer A4 register Addresses 4F 16 4 16 15 to 0 These bits can be set to 000016 to FFFF16 Undefined RW Assuming that the set value n the counter divides the count source frequency by n 1 when down counting or by FFFF e n 1 when up counting When reading the register indicates the counter value Fig 5 4 1 Structures of timer Ai mode register and timer Ai register in event counter mode 7702 7703 Group User s Manual 5 21 TIMER A 5 4 Event counter mode 5 4 1 Setting for event counter mode Figures 5 4 2 and 5 4 3 show an initial setting example for registers relevant to the event counter mode Note that when using interrupts set up to enable the interrupts For details refer to Chapter 4 INTERRUPTS amp Selecting event counter mode and each function UN b7 00 ETE Timer Ai mode register i 2 O to 4 A
282. gister In the single chip mode make sure to fix this register to 00146 It is because the access space of the single chip mode is the internal area within the bank Ote This register is cleared to 0016 at reset Addressing modes using data bank register eDirect indirect eDirect indexed X indirect eDirect indirect indexed Y eAbsolute Absolute bit Absolute indexed X Absolute indexed Y eAbsolute bit relative Stack pointer relative indirect indexed Y 2 1 8 Direct page register DPR The direct page register is a 16 bit register The contents of this register indicate the direct page area which is allocated in bank O16 or in the space across banks and 1 e The following addressing modes use the direct page register The contents of the direct page register indicate the base address the lowest address of the direct page area The space which extends to 256 bytes above that address is specified as a direct page The direct page register can contain a value from 40009146 to FFFF e When it contains a value equal to or more than FF0116 the direct page area spans the space across banks 016 and 116 When the contents of low order 8 bits of the direct page register is 001 the number of cycles required to generate an address 1 1 cycle smaller than the number when its contents are not 0016 Accordingly the access efficiency can be enhanced in this case This register is cleared to 000016 at reset
283. h both edges count 125 80 ns Timer B input pulse period measurement mode Symbol Parameter Data formula u d aeu Unit 8 X 10 sic NR do dades dt soa 30 4 X 10 tw TBH input high level pulse width EXN 250 160 ns A 4 X 10 tw TBL input low level pulse width 250 160 ns Note TBin input cycle time must be 4 cycles or more of count source input high level pulse width must be 2 cycles or more of count source TBiin input low level pulse width must be 2 cycles or more of count source Timer B input pulse width measurement mode Symbol Parameter Data formula uu Min 3 8 X 10 cycle time EXN 0 2 9 tw TBH input high level pulse width T 250 4 X 10 Note TBis input cycle time must be 4 cycles or more of count source input high level pulse width must be 2 cycles or more of count source TBiin input low level pulse width must be 2 cycles or more of count source A D trigger input Symbol Parameter Unit ADree input cycle time minimum allowable trigger 1000 1000 X ns wap ADrne input low level pulse width 125 125 n 7702 7703 Group User s Manual 15 9 ELECTRICAL CHARACTERISTICS 15 5 Internal peripheral devices Serial CLK input cycle time 1250112001 ms twckH input high level pulse width 11251
284. h external data bus width is 8 bits and accessible area is expanded up to 16 Mbytes In this expansion model the high order 8 bits of the external address bus A23 to Ais are multiplexed with the external data bus Accordingly an n bit n lt 8 address latch is required for latching addresses n bits of to Ate Medium model B This is an expansion model of which external data bus width is 16 bits and accessible area is expanded up to 64 Kbytes This expansion model is used when having the speed performance priority In this expansion model the middle order 8 bits of the external address bus Ais to As are multiplexed with the external data bus Accordingly an 8 bit address latch is required for latching address Ais to As Maximum modei This is an expansion model of which external data bus width is 16 bits and accessible area is expanded up to 16 Mbytes In this expansion model the high and middle order 16 bits of the external address bus Aes to As are multiplexed with the external data bus Accordingly an 8 bit address latch for latching Ais to As and an n bit n lt 8 address latch for latching n bits of Aes to Ate are required 7702 7703 Group User s Manual APPLICATION 17 1 Memory expansion Table 17 1 1 Memory expansion model Access area External data Maximum 64 Kbytes bus width Maximum 16 Mbytes M37702 M37702 Ao A15 n Ao A15 8 bit width BYTE H Do D7 Memory
285. h is set in the UARTI transmit buffer register is transferred to the UARTi transmit register Accordingly the user can set next transmit data When quitting the transmission which is in progress and setting the UARTI transmit buffer register again follow the procedure described bellow Clear the serial mode select bits bits 2 to 0 at addresses 30 e 3816 10 0002 Serial I O disabled Set the serial I O mode select bits again Set the transmit enable bit bit O at addresses 3516 3D e to 1 transmission enabled and set transmit data in the UARTi transmit buffer register 7 10 7702 7703 Group User s Manual SERIAL I O 7 2 Block description 7 2 5 UARTi receive register and UARTi receive buffer register Figure 7 2 7 shows the block diagram of receive section Figure 7 2 8 shows the structure of UARTi receive buffer register Data bus odd OOOO O Data bus even 0 Dz Bs Ds De Ds De D Do butter register SP Stop bit 8 bit UART PAR Parity bit rd 9 bit UART enabled 9 bit UART Clock sync 7 bit UART 7 bit UART 3 8 bit UART UARTI receive register Clock sync receive buffer register Addresses 3716 3616 UART1 receive buffer register Addresses 3F16e 3E16 Receive data is read out from here Undefined RO 15 to 9 Nothing is assigned The value is 0 at reading Fig 7 2 8 Structure of UAH TI receive bu
286. he data length flag m is 0 or bit 7 of the result is 1 when the data length flag m is 1 It is cleared to O in all other cases the BPL or BMI instruction is executed this flag determines whether the program causes a branch or not Use the SEP instruction to set this flag to 1 and use the CLP instruction to clear it to 0 Note This flag is invalid in the decimal mode Bits 10 to 8 Processcr interrupt priority level IPL These three bits can determine the processor interrupt priority level to one of levels 0 to 7 The interrupt is enabled when the interrupt priority level of a required interrupt which is set in each interrupt control register is higher than IPL When an interrupt request is accepted IPL is stored in the stack area and IPL is replaced by the interrupt priority level of the accepted interrupt request There are no instruction to directly set or clear the bits of IPL IPL can be changed by storing the new IPL into the stack area and updating the processor status register with the PUL or PLP instruction The contents of IPL is cleared to 0002 at reset 7702 7703 Group User s Manual 2 9 CENTRAL PROCESSING UNIT CPU 2 2 Bus interface unit 2 2 Bus interface unit A bus interface unit is built in between the central processing unit CPU and memory l O devices BIU s function and operation are described below When externally connecting devices refer to Ch
287. he direction registers s contents Figure 5 2 5 shows the relationship between the port P5 and port P6 direction registers and the Timer Ais pins 67 b6 b5 b3 b2 bi b0 aee e m ERE EHE Fe maris aQ EHE EHE Ft TA4Gur pin 0 Input mode 1 Output mode TA4 In pin j 2 c When using these pins as IN To pin Timer Ais input pins set the corresponding bits to 0 3 INT pin 4 IN T pin TBO pin TB iN pin TB2IN pin Bits 7 to 2 are not used for Timer A Fig 5 2 5 Relationship between port P5 and port P6 direction registers and Timer Ai s I O pins 5 8 7702 7703 Group User s Manual 5 3 Timer mode TIMER A 5 3 Timer mode In this mode the timer counts an internally generated count source Refer to Table 5 3 1 Figure 5 3 1 shows the structures of the timer Ai mode register and timer Ai register in the timer mode Table 5 3 1 Specifications of timer mode Item Count source Count operation Divide ratio Count start condition Count stop condition Interrupt request occurrence timing TAIIN pin function TAIOUT pin function Head from timer Ai register Write to timer Ai register Specifications f2 f16 fe4 or f512 e Down count When the counter underflows reload register s contents are reloaded and counting continues E n 4 1 When count start bit is set to 1 When count start bit is cleared to 0 When the counter underflows Programm
288. he transfer clock internally or to input it from an external The transfer clock is generated by operation of the transmit control circuit Accordingly even when performing only reception set the transmit enable bit to 1 and set dummy data in the UARTIi transmit buffer register in order to make the transmit control circuit active 1 Generating transfer clock internally The count source selected with the BRG count source select bits is divided by the BRGi and its BRGi output is further divided by 2 This is the transfer clock The transfer clock is output from the CLKi pin Setting relevant registers Select an internal clock bit 3 at addresses 3016 3816 0 Select the BRGi s count source bits 0 and 1 at addresses 3416 3C 6 Set divide value 1 to the BRGi addresses 3116 3916 fi 2 n 1 n Setting value to fi Frequency of BRGis Count source fe fie fe fs12 Transfer clock frequency Enable transmission bit 0 at addresses 3516 3D e 417 Set data to the UARTi transmit buffer register addresses 5216 16 Pin s state transfer clock is output from the CLKi pin Serial data is output from the TxDi pin Dummy data is output when performing only reception 2 Inputting transfer clock from an external A clock input from the CLKi pin is the transfer clock Setting relevant registers Select an external clock bit 3 at addresses 30 e 3816 1 Enable
289. hen the A D conversion start bit is set to 1 The A D conversion of the input voltage from the ANo pin is completed after 57 cycles of dav Then the contents of the successive approximation register conversion result are transferred to the A D register 0 The operation to all selected analog input pins is performed The conversion result is transferred to the A D register i each time each pin is converted When the step G is completed the A D conversion interrupt request bit is set to 1 A D conversion start bit is cleared to 0 and the A D converter stops operation When an external trigger is selected The A D converter starts operation for the input voltage from the ANo pin when the input level to the ADtra pin changes from to L while the A D conversion start bit is 1 The A D conversion of the input voltage from the ANo pinis completed after 57 cycles of dav Then the contents of the successive approximation register Conversion result are transferred to the A D register O The operation to all selected analog input pins is performed The conversion result is transferred to the A D register i each time each pin is converted When the step is completed the A D conversion interrupt request bit is set to 1 The A D conversion stops operation The A D conversion start bit remains set to 1 after the operation is completed Accordingly the operat
290. hen the counter underflows the reload register s contents are reloaded into the counter Values are set to the counter and reload register by writing a value to the timer Bi register Table 6 2 1 lists the memory assignment of the timer Bi register The value written into the timer Bi register when the counting is not in progress is set to the counter and reload register The value written into the timer Bi register when the counting is in progress is set to only the reload register In this case the reload register s updated contents are transferred to the counter when the counter underflows next time The counter value is read out by reading out the timer Bi register Note When reading and writing from to the timer Bi register perform them in an unit of 16 bits For more information about the value got by reading the timer Bi register refer to Precautions when operating in timer mode and Precautions when operating in event counter mode 2 Functions in pulse period pulse width measurement mode The counter up counts each time count source is input The reload register is used to hold the pulse period or pulse width measurement result When a valid edge is input to the TBi pin the counter value is transferred to the reload register In this mode the value got by reading the timer Bi register is the reload register s contents so that the measurement result is obtained Note When reading from the timer Bi reaister perform it in an un
291. hen the instruction which is next fetched is located at an even address in the 16 bit external data bus width the BIU fetches 2 bytes at a time with the waveform a When in the 8 bit external data bus width the BIU fetches only 1 byte with the first half of waveform e When the instruction which is next fetched is located at an odd address in the 16 bit external data bus width the BIU fetches only 1 byte with the waveform d When in the 8 bit external data bus width the BIU fetches only 1 byte with the first half of waveform f When a branch to an odd address is caused by a branch instruction and others in the 16 bit external data bus width the BIU first fetches 1 byte in waveform d and after that fetches each two bytes at a time in waveform a When reading or writing data to and from memory O device When accessing 16 bit data which begins at an even address waveform a or e is applied When accessing 16 bit data which begins at an odd address waveform b or f is applied When accessing 8 bit data at an even address waveform c or the first half of e is applied When accessing 8 bit data at an odd address waveform d or the first half of f is applied For instructions that are affected by the data length flag m and the index register length flag x operation or is applied when flag m or x 0 operation or is applied when flag m or x 1 The setup of flags and x and the selecti
292. hen the transmission starts When not using interrupts P Checking start of transmission UARTO transmit interrupt control register Address 7116 UART1 transmit interrupt control register Address 7316 UARTi transmit interrupt b7 bO 0 No interrupt request 1 Interrupt request w Transmission has lee Interrupt request bit Note This figure shows the bits and registers required hecking completion of transmission for processing UARTO transmit receive control register 0 Address 3416 Reter to Figures 7 4 6 to 7 4 7 about the UART1 transmit receive control register 0 Address 3C16 change of flag state and the occurrence timing bO of an interrupt request Transmit register empty flag 0 During transmitting 1 Transmitting completed d C Processing at completion o transmission gt Fig 7 4 5 Detection of iransmission s completion 7702 7703 Group User s Manual 7 43 SERIAL I O 7 4 Clock asynchronous serial UART mode 7 4 4 Transmit operation Simultaneously when the transmit conditions listed on page 7 40 are satisfied the following operations are automatically performed UARTi transmit buffer register s contents are transferred to the transmit register he transmit buffer empty flag is set to 1 transmit register empty flag is cleared to 0 The UARTi transmit interrupt request occurs and the interr
293. his results in easy control of multiple interrupts Refer to section 4 9 Multiple interrupts When at reset or the watchdog timer or the software interrupt is accepted the value shown in Table 4 7 1 is set in the IPL Table 4 7 1 Change in IPL at interrupt request acceptance Interrupt source Change in IPL Reset Level 0002 is set Watchdog timer Level 7 1112 is set Zero division No change BRK instruction No change Other interrupts Interrupt priority level of the accepted interrupt request is set 4 16 7702 7703 Group User s Manual INTERRUPTS 4 7 Sequence from acceptance of interrupt request to execution of interrupt routine 4 7 2 Storing registers The register storing operation performed during INTACK sequence depends on whether the contents of the stack pointer S at accepting interrupt request are even or odd When the contents of the stack pointer S are even the contents of the program counter PC and the processor status register PS are stored as a 16 bit unit simultaneously at each other When the contents of the stack pointer S are odd they are stored with twice by an 8 bit unit for each Figure 4 7 3 shows the register storing operation In the INTACK sequence only the contents of the program bank register PG program counter PC and processor status register PS are stored to the stack area The other necessary registers must be stored by software at the beginning of the interrupt routine
294. hree times as many numbers as x pulses described in that is 3 X x ms as additional programming pulses When this procedure to is completed increment the address and repeat the above procedure until the last address is reached After programming to the last address read data when Vcc VPP 5 V or Vcc VPP 5 5 V x This applies to the M37702E2BXXXFP Refer to Table 19 1 1 about each write address of other products ADDR FIRST LOCATION Vcc 6 0 V VPP 12 5 V gt C 0 PROGRAM ONE PULSE OF 1 ms p NO FAIL DEVICE FAILED PASS PROGRAM PULSE OF 3 X X ms DURATION INCREMENT ADDR NO LAST ADDR YES Vcc VPP 5 0 VERIFY FAIL DEVICE ALL BYTE FAILED PASS DEVICE PASSED 4 5 V lt Vcc VPP lt 5 5 V Fig 19 4 3 Programming algorithm flow chart of 256K mode 19 16 7702 7703 Group User s Manual PROM VERSION 19 4 256K mode 19 4 3 Electrical characteristics of programming algorithm in 256K mode AC electrical characteristics Ta 25 5 C Vcc 6 V 0 25 V VPP 12 5 0 3 V unless otherwise noted Limits Symbol Parameter Unit Min VPS VPP setup time 012 Hs tOPW Additional CE pulse width 285 7875 ms 3 Programming timing diagram Program Verify VIH VIL ViH VOH tas Data VIUVOL Dese 7 4 Data output valid p tos tDFP VPP 2 VPP Vcc 1 Vcc tvcs V
295. i Clock synchronous serial I O mode fi BRGi O Transfer clock for transmit operation I Transfer clock for receive operation lt UART mode gt Transfer clock for transmit operation Transfer clock for receive operation fi Clock selected by BRG count source select bits f2 He 164 or f512 fext Clock input to pin external clock Fig 7 2 11 Block diagram of transfer clock generating section 7702 7703 Group User s Manual 7 13 SERIAL I O 7 2 Block description 7 2 7 UARTi transmit interrupt control and UARTi receive interrupt control registers When using UARTi 2 types of interrupts which are UARTi transmit and UARTI receive interrupts can be used Each interrupt has its corresponding interrupt control register Figure 7 2 12 shows the structure of transmit interrupt control receive interrupt control registers For details about interrupts refer to Chapter 4 INTERRUPTS 05 b2 bl 00 UARTO transmit interrupt control register Address 7116 UARTO receive interrupt control register Address 7216 UART1 transmit interrupt control register Address 7316 UARTI receive interrupt control register Address 7416 a e eee Interrupt priority level select bits Level 0 Interrupt disabled 0 1 Level 1 Low level Level 2 Level 3 RW Level 4 Level 5 Level 6 Level 7 High level 1 nte
296. ical characteristics 15 4 A D converter characteristics 15 5 Internal peripheral devices 15 6 Ready and Hold 15 7 Single chip mode 15 8 Memory expansion mode and microprocessor mode with no Wait 15 9 Memory expansion mode and microprocessor mode with Wait 15 10 Testing circuit for ports PO to P8 and E ELECTRICAL CHARACTERISTICS 15 1 Absolute maximum ratings This chapter describes electrical characteristics of the M37702M2BXXXFP and M37702M2AXXXFP For the low voltage version refer to section 18 4 Electrical characteristics The 7703 Group s available pins varies from that of the 7702 Group Refer to Chapter 20 7703 GROUP For the latest data inquire of addresses described last rx CONTACT ADDRESSES FOR FURTHER INFORMATION In a part of the standard indicated in this chapter there are the limits depending on each microcomputer product or used external clock input frequency Distinguish it described below Limits depending on each microcomputer Example M37702M2BXXXFP When this sign is A refer to the column of 16 MHz When this sign is B refer to the column of 25 MHz Limits depending on used external clock input frequency The calculation formula is described in the table When the microcomputer is 16 MHz version the limits is the value in the case of f Xin 16 MHz When the microcomputer is 25 MHz version the limits is the value in the case of f Xin 25 MHz
297. ifies the storage address of data to be read to the BIU s data address register and requires data The CPU waits until data is ready in the BIU The outputs the address received from the CPU onto the address bus reads contents at the specified address and takes it into the data buffer The CPU continues processing using data in the data buffer However if the BIU uses the bus for instruction prefetch when the CPU requires to read data the BIU keeps the CPU waiting Writing data to memory el O device The CPU specifies the address of data to be written to the BIU s data address register Then the CPU writes data into the data buffer The outputs the address received from the CPU onto the address bus and writes data in the data buffer into the specified address The CPU advances to the next processing without waiting for completion of BIU s write operation However if the BIU uses the bus for instruction prefetch when the CPU requires to write data the BIU keeps the CPU waiting Bus control To perform the above operations 1 to 3 the BIU inputs and outputs the control signals and controls the address bus and the data bus The cycle in which the BIU controls the bus and accesses the memory l O device is called the bus cycle Refer to Chapter 12 CONNECTION WITH EXTERNAL DEVICES about the bus cycle at accessing the external devices 7702 7703 Group User s Manual 2 13 CENTRAL PROCESSING UNIT CPU 2 2 Bus inter
298. igger RW External trigger A D conversion start bit E Stop A D conversion RW Start A D conversion 7 A D conversion frequency 0 2 divided by 4 RW AD select bit 1 f2 divided by 2 Notes 1 These bits are ignored in the single sweep and repeat sweep mode They may be either 0 or 1 2 When selecting an external trigger the AN7 pin cannot be used as an analog input pin 3 Writing to each bit except bit 6 of the A D control register must be performed while the A D converter halts Fig 8 2 2 Structure of A D control register 1 Analog input select bits bits 2 to 0 These bits are used to select an analog input pin in the one shot mode and repeat mode Pins which are not selected as analog input pins function as programmable I O ports These bits must be set again when the user switches the A D operation mode to the one shot mode or repeat mode after performing the operation in the single sweep mode or repeat sweep mode 8 4 7702 7703 Group User s Manual A D CONVERTER 8 2 Block description 2 Trigger select bit bit 5 This bit is used to select the source of trigger occurrence Refer to 3 A D conversion start bit 3 A D conversion start bit bit 6 When internal trigger is selected Setting this bit to 1 generates a trigger causing the A D converter to start operating Clearing this bit to O causes the A D converter to stop operating In the one shot mode or single swee
299. ignal 1 1 Rising edge of pin s input signal SSP seus impe ees Fix this bit to O in one shot pulse mode o nw pe we 5 b7 b6 s Count source select bits 00 fe 01 f16 1 O 194 q f512 615 08 Timer AO register Addresses 4716 4616 Br b0 Timer A1 register Addresses 4916 4816 Timer register Addresses 4016 4 16 Timer A4 register Addresses 4F 16 4 16 15 to 0 These bits can be set to 000116 to FFFFie Undefined WO Assuming that the set value n the H level width of the one shot pulse output from the TAiour pin is expressed as follows n fi fi Frequency of count source fe fis fea or fs12 7702 7703 Group User s Manual 21 23 APPENDIX Appendix 3 Control registers Pulse width modulation PWM mode b7 b6 b5 b4 b3 b2 bli PTT TL ip Timer Ai mode register i 0 to 4 Addresses 5616 to 16 When operating as a 16 bit pulse width modulator b15 b8 b7 bO b7 b4 b3 00 Writing 1 to count start register 01 N pin functions as a pro grammable port 0 Falling edge of TAin pin s input signal 1 1 1 Rising 2L of input signal b7 b6 00 f2 01 f16 164 11 f512 Timer AO register Timer A1 register Timer A2 register Addresses 4 16 4 16 Timer register Addresses 4016 4 16 Timer A4 register Addresses 4 16 4E16
300. imer register Addresses 4016 4 16 Timer A4 register Addresses 4F 16 4E16 15 to O These bits can be set to 000016 to FFFFi6 Undefined RW Assuming that the set value n the counter divides the count source frequency by n 1 When reading the register indicates the counter value Fig 5 3 1 Structures of timer Ai mode register and timer Ai register in timer mode 5 10 7702 7703 Group User s Manual TIMER A 5 3 Timer mode 5 3 1 Setting for timer mode Figures 5 3 2 and 5 3 3 show an initial setting example for registers relevant to the timer mode Note that when using interrupts set up to enable the interrupts For details refer to section Chapter 4 INTERRUPTS Selecting timer mode and each function b7 bO MEUNNNU Timer Ai mode register i 0 to 4 Addresses 5616 to 16 Selection of timer mode Pulse output function select bit 0 No pulse output 1 Pulses output Gate function select bits b4 b3 x No gate function 1 0 Gate function Counter counts only while TAiiN pin s input signal is L level 1 1 Gate function Counter counts only while TAiiN pin s input signal is level Count source select bits b7 b6 0 0 fe fie 1 O 164 1 1 612 Setting divide ratio Timer AO register Addresses 4716 4616 08 ane Timer A1 register Addresses 4916 4816 Timer A2 register Addresses
301. imer BO register Addresses 5116 5016 Timer B1 register Addresses 5316 5216 Timer 2 register Addresses 5516 5416 15 to 0 These bits can be set 000016 to FFFF16 Undefined RW Assuming that the set value n the counter divides the count source frequency by n 1 When reading the register indicates the counter value Fig 6 3 1 Structures of timer Bi mode register and timer Bi register in timer mode 7702 7703 Group User s Manual 6 9 TIMER B 6 3 Timer mode 6 3 1 Setting for timer mode Figure 6 3 2 shows an initial setting example for registers relevant to the timer mode Note that when using interrupts set up to enable the interrupts For details refer to Chapter 4 INTERRUPTS Selecting timer mode and count source gt 00 Timer Bi mode register i 0 to 2 Addresses 5B 6 to 5016 Selection of timer mode Count source select bits b7 b6 00 f2 0 1 f16 1 0 164 X It may be either 0 1 w 1 1 512 d amp Setting divide ratio 015 68 b7 bO 07 bo Timer BO register Addresses 5116 5016 timer B2 register Addresses 5516 5416 s Can be set to 000016 to FFFF e n d Note The counter divides the count source by n 1 Setting interrupt priority leve 7 Timer Bi interrupt control register i 0 to 2 a imer Bi interrupt control register i O to
302. imer s underflow signal Ready request unde Request of CPU wait m CPU from BIU acceptance of Hold request included WIT instruction R Note This is the signal generated when watchdog timer s most significant bit becomes 0 Fig 10 1 1 Clock generating circuit 10 2 7702 7703 Group User s Manual STOP MODE 10 2 Operation description 10 2 Operation description When the STP instruction is executed the oscillator stops oscillating This state is called Stop mode In Stop mode the contents of the internal RAM can be retained intact when the Vcc power source voltage is 2 V or more Additionally the microcomputer s power consumption is reduced It is because the CPU and all internal peripheral devices using clocks fz to fs12 stop the operation Table 10 2 1 lists the microcomputer state and operation in and after Stop mode Table 10 2 1 Microcomputer state and operation in and after Stop mode Item State and Operation State in Oscillation Stopped TimerA Operating enabled only in event counter mode Serial Operating enabled only when selecting external clock Stopped Pins Retains the same state in which the STP instruction was executed Operation By interrupt request Supply of CPU and starts after a certain time measured by after termi occurrence watchdog timer has passed nating Stop By hardware reset mode C Q p Q G c c Operate
303. iming and EPROM mode 2 A blank product of the one time PROM version does not have the ROM number which is printed on the XXX position For example M37703E2BSP 20 6 1 EPROM mode The EPROM mode of M37703 is the same as the M37702 s Refer to section 19 2 EPROM mode The pin connections vary from the M37702 s Figure 20 6 1 shows the pin connections in EPROM mode 7702 7703 Group User s Manual 20 13 7703 GROUP 20 6 PROM version AVcc 1 64 lt gt Vcc VREF gt 2 63 lt gt P80 CTSo RTSo AVss 3 62 lt gt P81 CLKo P77 AN7 ADTRG 4 61 lt gt P82 RxDo P72 AN2 lt gt 5 60 lt gt P83 TxDo P71 AN1 6 59 lt gt P86 RxD1 P70 ANo 7 58 lt gt P87 TxD1 P65 TBOIN 8 57 lt gt Ao Equivalent to P64 INT2 9 56 lt gt PO1 A1 CAD 5 276256 P63 INT1 lt gt 10 55 lt gt PO2 A2 GAD P62 INTo lt gt 11 Z 54 lt gt P03 A3 AD P57 TA3IN 4 12 53 lt gt P04 A4 AD Equivalent to P56 TA30UT lt gt 13 N 52 P05 A5 MSM27C101K P55 TA2IN lt gt 14 e 51 lt gt 6 C Ae P54 TA20UT lt gt 15 50 lt gt PO7 A7 IKA7 P53 TA1IN gt 16 TI 49 lt gt P10 As De As gt 1 2 CCE gt P52 TAtout
304. in each operating mode 7 9 7702 7703 Group User s Manual SERIAL I O 7 2 Block description 7 2 Block description Figure 7 2 1 shows the block diagram of Serial Registers relevant to Serial I O are described below Data bus odd Data bus even D7 05 Dal Dal 02 D1 UARTIi receive buffer register RxDi C UARTI receive register dne on source 1 Receive Transfer clock Select DILS control circuit o Transmit control Transienclock O wg 64 o 2 circuit synchronous Clock synchronous A internal clock selected UARTIi transmit register transmit UARTIi transmit register Clock synchronous Clock R internal clock selected external clock selected PY 4 CLKi O lt CTSi RTSi O bus odd n Values set in UARTi baud rate register BRGi Fig 7 2 1 Block diagram of Serial I O 7702 7703 Group User s Manual 7 3 SERIAL I O 7 2 Block description 7 2 1 UARTi transmit receive mode register Figure 7 2 2 shows the structure of UARTi transmit receive mode register The serial mode select bits is used to select UARTi s operating mode Bits 4 to 6 are described in the section 7 4 2 Transfer data format and bit 7 is done in the section 7 4 8 Sleep mode b7 b6 b5 04 b3 b2 bl UARTO transmit receive mode register Address 3016 UART1 transmit receive mode register Address 3816 b2 b1 b0 Serial I
305. ing as 16 bit pulse width modulator gt b15 b8 Timer AO register Addresses 4716 4616 2 o 00 1 register Addresses 4916 4816 Timer register Addresses 4016 461 Timer A4 register Addresses 4F 16 4 16 15 to O These bits can be set to 000016710 FFFE16 Undefined WO Assuming that the set value n the level width of the PWM pulse output from the TAiour pin is expressed as follows E l PWM pulse s period is expressed as follows n 6 1 fi fi Frequency of count source f2 He fe4 or 1512 When operating as an 8 bit pulse width modulator b15 b8 p m M Timer AO register Addresses 4716 4616 Timer A1 register Addresses 4916 4816 Timer register Addresses 4016 4C 6 Timer A4 register Addresses 4F 16 4E16 7 to 0 These bits can be set to 0016 to FF e Undefined WO Assuming that the set value m PWM pulse s period output from the TAiour pin is expressed as follows _ nie 1 i 15 to 8 These bits can be set to 0016710 FE e Undefined WO Assuming that the set value n the H level width of the PWM pulse output from the TAiour pin is expressed as follows n m 1 fi fi Frequency of count source fz He fe Or f512 Fig 5 6 1 Structures of timer Ai mode registers and timer Ai registers in PWM mode 5 40 7702 7703 Group User s Manual TIMER A 5 6 Pulse width modulation
306. ion enabled and set the transmit data to the transmit buffer register 7 32 7702 7703 Group User s Manual SERIAL I O 7 3 Clock synchronous serial I O mode Precautions when operating in clock synchronous serial I O mode 1 The transfer clock is generated by operation of the transmit control circuit Accordingly even when performing only reception transmit operation setting for transmission must be performed In this case dummy data is output from the TxDi pin When an internal clock is selected during reception the transfer clock is generated by setting the transmit enable bit to 1 transmission enabled and setting dummy data to the UARTi transmission buffer register When an external clock is selected the transfer clock is generated by setting the transmit enable bit to 1 and inputting a clock to the pin after setting dummy data to the UARTi transmission buffer register When selecting an external clock satisfy the following 3 conditions with the input to CLKi pin H level When transmitting Set the transmit enable bit to 1 Write transmit data to the UARTi transmit buffer register Input L level to the CTSipin when selecting the CTS function When receiving Set the receive enable bit to 1 Set the transmit enable bit to 1 Write dummy data to the transmit buffer register When receiving data write dummy data to the l
307. ion of the A D converter can be performed again from step when the level of the ADrne changes from io L When the level of the ADtra pin changes from H to L during operation the operation at that point is cancelled and is restarted from step Figure 8 7 2 shows the conversion operation in the single sweep mode 7702 7703 Group User s Manual A D CONVERTER 8 7 Single sweep mode Trigger occur Convert input voltage from Conversion result ANo pin A D register 0 Convert input voltage from Conversion result AN pin A D register 1 Convert input voltage from Conversion result A ANi pin _ A D register i A D converter interrupt request occur A D converter halt Fig 8 7 2 Conversion operation in single sweep mode 7702 7703 Group User s Manual 8 23 A D CONVERTER 8 8 Repeat sweep mode 8 8 Repeat sweep mode In the repeat sweep mode the operation for the input voltage from the multiple selected analog input pins is performed repeatedly The A D converter is operated in ascending sequence from the ANo pin In this mode no A D conversion interrupt request occurs Additionally the A D conversion start bit bit 6 at address 1E e remains set to 1 until it is cleared to 0 by software and the operation is performed repeatedly while the A D conversion start bit is 1 8 8 1 Settings for repeat sweep mode Figure 8 8 1 shows an initial setting exa
308. ion on the MASK ROM ORDER CONFIRMATION FORM The STP instruction is always enabled in the built in PROM version and the external ROM version 2 When executing the STP instruction after writing to the internal area or an external area the three NOP instructions must be inserted to complete the write operation before the STP instruction is executed STA A XXXX Writing instruction NOP NOP instruction insertion NOP NOP STP STP instruction Fig 10 3 1 NOP instruction insertion example 10 6 7702 7703 Group User s Manual CHAPTER 11 WAIT MODE 11 1 Gioek generating circuit 11 2 Operation description 11 3 Precautions for Wait mode WAIT MODE 11 1 Clock generating circuit This chapter describes Wait mode Wait mode is used to stop ceu and when there is no need to operate the central processing unit CPU The oscillator continues its oscillation The microcomputer enters Wait mode when the WIT instruction is executed Wait mode can be terminated by an interrupt request occurrence or the hardware reset 11 1 Clock generating circuit Figure 11 1 1 shows the clock generating circuit CPU Central Processing Unit BIU Bus Interface Unit Watchdog timer frequency select bit Bit O at address 6116 fe XIN fte Operation clock for O 164 Interrupt request 1512 Watchdog timer 512 frequency select bit STP instruction f O 32 Watchdog Anm O Q internal peripheral devic
309. ions except for the following the microprocessor mode access to the internal ROM area is disabled by force and the internal ROM area is handled as an external area the microprocessor mode port P42 always functions as the clock 91 output pin In the memory expansion and microprocessor modes PO to P3 P40 and P41 when the external data bus width is 16 bits function as the pins for the signals required for accessing external devices Consequently these pins cannot be used as programmable I O ports If an external device is connected with an area with which the internal area overlaps when this overlapping area is read data in the internal area is taken in the CPU but data in the external area is not taken in If data is written to an overlapping area the data is written to the internal area and a signal is output externally at the same timing as writing to the internal area Figure 2 5 2 shows a pin configuration in each processor mode Table 2 5 1 lists the functions of PO to P4 in each processor mode For the function of each pin refer to section 1 3 Pin aescription Chapter 3 INPUT OUTPUT PINS each descriptions of internal peripheral devices and Chapter 12 CONNECTION WITH EXTERNAL DEVICES 2 22 7702 7703 Group User s Manual CENTRAL PROCESSING UNIT CPU 2 5 Processor modes Single chip mode gt PS4CTSi RTS 8 P85 CLK1 g P8e RxD1 P87 TxD1 P83 TxDo l
310. ister Refer to Figure 9 1 2 e When the most significant bit of Watchdog timer becomes 0 When the STP instruction is executed Refer to Chapter 10 STOP MODE At reset b7 LL Watchdog timer register Address 6016 7100 Initializes the watchdog timer Undefined When a dummy data is written to this register ihe watchdog timer s value is initialized to FFF16 Dummy 0016 to FF 6 Fig 9 1 2 Structure of watchdog timer register 7702 7703 Group User s Manual 9 3 WATCHDOG TIMER 9 1 Block description 9 1 2 Watchdog timer frequency select register This is used to select the watchdog timer s count source Figure 9 1 3 shows the structure of the watchdog timer frequency select register 67 b6 b5 b4 b3 b2 bi bO Watchdog timer frequency select register Address 6116 Bit name Functions At reset reset RW RW 1 82 701 to 1 Nothing is allocated Undefined Fig 9 1 3 Structure of watchdog timer frequency select register 0 4 7702 7703 Group User s Manual WATCHDOG TIMER 9 2 Operation description 9 2 Operation description The operation of Watchdog timer is described below 9 2 1 Basic operation Watchdog timer starts down counting from FFF e When the Watchdog timer s most significant bit becomes 0 counted 2048 times the watchdog timer interrupt request occurs Refer to Table 9 2 1 When the interrupt request occurs at above a valu
311. it 1 47 a II it TY Th gap Software Wait Wait by Ready function m This applies when using the 25 MHz version Fig 17 1 9 Example of Ready signal generating circuit Wait 7702 7703 Group User s Manual 17 13 APPLICATION 17 1 Memory expansion When using external memory that outputs data within tpxze Piziezz after falling edge of E signal Because the external memory outputs data within tpxze Piz ezz after the falling edge of the E signal there will be a possibility of the tail of address colliding with the head of data In this case generate the memory read signal OE by delaying only the leading edge of the fall of the E Refer to Figure 17 1 10 External memory output enable signal Read signal Address output Address External memory data output S Specifications of the M37702 The others are specifications of external memory Note Satisfy lt ten 05 d If ten oE lt lpxz E Piz P22 Sens ensure a certain time i e d in this diagram by delaying the falling edge of OE after the falling edge ofE Fig 17 1 10 Example of causing to delay data output timing 17 14 7702 7703 Group User s Manual APPLICATION 17 1 Memory expansion When using external memory that outputs data for more than 2 22 after rising edge of E signal Because the external memory outputs data for more th
312. it of 16 bits Table 6 2 1 Memory assignment of timer Bi registers Timer Bi register Low order byte Timer BO register Address 5016 Timer B1 register Address 5216 Timer B2 register Address 5416 Note When reset the contents of the timer Bi reg ister are undefined 7702 7703 Group User s Manual 6 3 TIMER B 6 2 Block description 6 2 2 Count start register This register is used to start and stop counting Each bit of this register corresponds each timer Figure 6 2 2 shows the structure of the count start register b7 06 b5 b4 b3 b2 bl b0 Count start register Address 4016 e KW Timer A0 count start bit x Stop counting Start counting EN Timer A1 count start bit Timer A2 count start bit S TmerBicontsanbt Bits 0 to 4 are not used for Timer Fig 6 2 2 Structure of count start register 6 4 7702 7703 Group User s Manual TIMER B 6 2 Block description 6 2 3 Timer Bi mode register Figure 6 2 3 shows the structure of the timer Bi mode register The operating mode select bits are used to select the operating mode of timer Bi Bits 2 and 3 and bits 5 to 7 have different functions according to the operating mode These bits are described in the paragraph of each operating mode b7 b6 b5 b4 b3 b2 bi bO IM Timer Bi mode register i to 2 Addresses 5B e to 5016 Le ee crues Tore Operating mode select bits Timer mode Event counter mode P
313. it to 1 UARTi enters the transmission enable state By clearing this bit to O during transmission UARTi enters the transmission disable state after the transmission which is performed at that time is completed Transmit buffer empty flag bit 1 This flag is set to 1 when data set in the UARTi transmit buffer register is transferred from the UARTi transmit buffer register to the UARTi transmit register This flag is cleared to 0 when data is set in the UARTi transmit buffer register Receive enable bit bit 2 By setting this bit to 1 UARTi enters the reception enable state By clearing this bit to 0 during reception UARTi quits the reception then and enters the reception disable state Receive complete flag bit 3 This flag is set to 1 when data is ready in the UARTi receive register and that is transferred to the UARTi receive buffer register i e when reception is completed This 0 is cleared to 0 when the low order byte of the UARTI receive buffer register is read out or when the receive enable bit bit 2 is cleared to 0 7702 7703 Group User s Manual SERIAL I O 7 2 Block description 7 2 4 UARTi transmit register and UARTi transmit buffer register Figure 7 2 5 shows the block diagram of transmit section Figure 7 2 6 shows the structure of transmit buffer register Data bus odd Data bus even transmit buffer register i De Ds i Da
314. ities fully For details concerning the software refer to the 7700 Family Software Manual BEFORE USING THIS MANUAL 1 Constitution This user s manual consists of the following chapters Refer to the chapters relevant to used products and the processor mode Chapter 1 DESCRIPTION to Chapter 17 APPLICATION Functions which are common to all products and all processor modes are explained using the M37702M2BXXXFP as an example When there are functional differences between the low voltage version PROM version and the 7703 Group the referential section is indicated Refer to that section about differences and to Chapter 1 to Chapter 17 about the common functions Chapter 18 LOW VOLTAGE VERSION Refer to this chapter when using the products of which difference of electrical characteristics identification code see on page 1 2 is L the M37702M2LXXXGP for example This chapter mainly explains the differences from the M37702M2BXXXFP using the M37702M2LXXXGFP as an example OG Chapter 19 PROM VERSION Refer to this chapter when using the products of which memory identification code see on page 1 2 is E the M37702E2BXXXFP for example This chapter mainly explains the differences from the M37702M2BXXXFP using the M37702E2BXXXFP as example OG Chapter 20 7703 GROUP Refer to this chapter when using the 7703 Group This chapter mainly explains the differences from the 7702 Group using the M37703M2BXXXSP as an examp
315. l clock input cycle time 62 40 External clock input high level pulse width 1 2 15 External clock input low level pulse width n 25 J 15 External clock rise ime C 1 j 10 8 External clock fall time j S 10 S 8 Port PO input setup time 100 6 Port P1 input setup time 110 COC Port P2 input setup time 110060400 PotP3inputsetuptime 110016000 Port P4 input setup time 110 160000 Parameter Port P5 input setup time 10 Port P6 input setup time 10 6 PortP7inputsetuptime 104 6 PortP8inputsetuptime 1106140 Port PO input hold ime 100 0 Port P1 input hold time Port P2 input hold time Port input hold time Port P4 input hold time Port P5 input hold time PortP6inputholdtime PortP7inputholdtime 2 a 0 lof PortP8inputholdtime Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Switching characteristics Vcc 5 V 10 Vss 0 V Ta 20 to 85 C unless otherwise noted Limits PotPOdataouputdelaylime 100 80 Port P1 data outp t delay time 100 80 Port P2 data output delay time PorttP3dataouiputdelaytime 1100280 Port P4 data output delay time Port P5 data output delay time Port P6 data output delay time 10 80 Port P7 data output delay time 10 1 80 Port P8 data output delay time 100 80
316. l signal 1 1 Not selected M X It may be either 0 or 1 amp Setting divide ratio N b15 b8 b7 bO b7 00 Timer register Addresses 5116 5016 Timer B1 register Addresses 5316 5216 Timer B2 register Addresses 5516 5416 Can be set to 000014 to FFF e y Note The counter divides the count source by n 1 Setting interrupt priority level b7 bO Timer Bi interrupt control register i O to 2 Addresses 7 16 to 7 16 Interrupt priority level select bits When using interrupts set these bits to level 1 7 When disabling interrupts set these bits to level O Setting port P6 direction register b7 Port P6 direction register Address 1016 TBOm pin TB1wm pin Clear the corresponding bit to 0 q TB2in pin J b Setting count start bit to 1 b7 Count start register Address 4016 Count starts Timer BO count start bit Timer B1 count start bit Timer B2 count start bit b 4 Fig 6 4 2 Initial setting example for registers relevant to event counter mode 6 16 7702 7703 Group User s Manual TIMER B 6 4 Event counter mode 6 4 2 Operation in event counter mode When the count start bit is set to 1 the counter starts counting of the count source The counter counts the count source s valid edges amp When the counte
317. l to the CNVss pin this bit becomes 1 after a reset Fixed to 1 2 This bit is ignored in the microprocessor mode It may be either O or 1 Interrupt priority detection time select bits Bits 7 to 2 are not used for setting of the processor mode Fig 2 5 4 Structure of processor mode register 2 26 7702 7703 Group User s Manual CENTRAL PROCESSING UNIT CPU Precautions when selecting the processor mode Precautions when selecting processor mode 1 For the products operating only in the single chip mode be sure to set the following Connect the CNVss pin with Vss Fix the processor mode bits bits 1 and 0 at address 5E e to 002 2 The external ROM version is only for the microprocessor mode Accordingly be sure to set the following Connect the CNVss pin with Vcc Fix the processor mode bits bits 1 and 0 at address 5E e to 102 3 When using the memory expansion mode or microprocessor mode be sure to set bits 0 and 1 of the port P4 direction register to 0 Set the above setting whether using PA HOLD pin as HOLD pin and P4 RDY pin as RDY pin For also the external ROM version set the above setting Additionally it is not need to set the port PO to P3 direction registers 7702 7703 Group User s Manual 2 27 CENTRAL PROCESSING UNIT CPU Precautions when selecting the processor mode MEMORANDUM 2 28 7702 7703 Group User s Manual CHAP TI
318. lator has stopped oscillating rio interrupts other than those above can be used 3 Refer to Chapter 4 INTERRUPT and the description of each internal peripheral device for details about each interrupt Before executing the STP instruction enable interrupts used to terminate Stop mode In addition the interrupt priority level of the interrupt used to terminate Stop mode must be higher than the processor interrupt priority level IPL of the routine where the STP instruction is executed When multiple interrupts in Table 10 2 2 enabled Stop mode is terminated by the first interrupt request There is possibility that all interrupt requests occur after the oscillation starts in and until supply of ceu and su starts 9 The interrupt requests which occur during this time are accepted in order of priority Note after the watchdog timer s MSB becomes 0 For interrupts not to be accepted set their interrupt priority levels to level O interrupt disabled before executing the STP instruction Note The interrupt request which has the highest priority is accepted first 10 4 7702 7703 Group User s Manual STOP MODE 10 2 Operation description Stop mode om SVU V A o JUO IL CPU BIU Interrupt request used to terminate 4 Stop mode oodd osos o Lo 19 f32 2048 counts Interrupt request bit lt q r T Value of watchdog timer CPU Operating Stopped Stopped Operating Intern
319. le e Appendix Useful information for 7702 and 7703 Groups usage is shown 2 Remark 25 MHz version and 16 2 version The 25 MHz version products are distinguished from the 16 MHz version products in part of Chapters as the case may be Hefer to it as follows Products of which difference of electrical characteristics identification code is M37702M2BXXXFP as an example Column of 25 MHz version Products of which difference of electrical characteristics identification code is A M37702M2AXXXFP as an example Column of 16 MHz version e Product expansion See the latest data book and data sheets Additionally ask the contact addresses on the last page O Electrical characteristics See also the latest data book or data sheet Development support tools See the latest data book and data sheet e Software See 7700 Family Software Manual eMask ROM Confirmation Form PROM Confirmation Form Mark Specification Form Copy the form in the latest data book and use it Or ask the contact addresses on the last page 3 Register structure The view of the register structure is described below 2 553 67 06 b5 04 b3 02 bi bO s di x XXX register Address XX16 422 gt rem Fr s select bit Undefined WO 353 2 flag a
320. le 5 5 1 When a trigger occurs the timer outputs H level from the TAiour pin for an arbitrary time Figure 5 5 1 shows the structures of the timer Ai mode register and timer Ai register in the one shot pulse mode Table 5 5 1 Specifications of one shot pulse mode Item Count source Count operation Output pulse width H Count start condition Count stop condition Interrupt request occurrence timing TAIIN pin function TAIOUT pin function Head from timer Ai register Write to timer Ai register Specifications f2 f16 fe4 or f512 Down count When the counter value becomes 000016 reload register s con tents are reloaded and counting stops a trigger occurs during counting reload register s contents are reloaded then and counting continues n m s n Timer Ai register setting value When trigger occurs Note Internal or external trigger be selected by software When the counter value becomes 000016 When count start bit is cleared to 0 When counting stops Programmable I O port or trigger input One shot pulse output An undefined value is read out e While counting is stopped When a vaiue is written to timer Ai register it is written to both reload register and counter While counting is in progress When a value is written to timer Ai register it is written to only reload register Transferred to counter at next reload time Note The trigger is g
321. lecting software Wait and f Xin 20 MHz Condition When selecting software Wait and f Xin 25 MHz and inserting a Wait which is 1 cycle of inserting total Wait of 2 cycles of 0 Table 17 2 2 Comparison condition Item Processor mode External data bus width Software Wait Ready Program area Work area Software Wait valid area Condition 2 Microprocessor mode 20MHz 25 MH 16 bits Inserted Inserted Invalid only to external EPROM areas External EPROM External EPROM Internal or External SRAM Internal or External SRAM M37702 memory map SFR area Internal SRAM Specify either area as the work area External SRAM E _ Condition Ready valid area Program area t Wait of 9 X 2 cycles at access External EPROM ld including software Wait Fig 17 2 2 Memory allocation at execution rate comparison 7702 7703 Group User s Manual 17 31 APPLICATION 17 2 Sample program execution rate comparison Figure 17 2 3 shows that there is almost no difference between conditions and about the execution time The bus buffers become unnecessary by using the specific memory See Table 17 1 7 Consequently the case selecting f Xin 20 MHz and inserting software Wait is superior in the cost performance Execution time ratio in sample A Execution time ratio in sample B Work area Internal RAM Work area External RAM Condition 9 Condition Fig 17 2 3 Exe
322. les of Interrupt priority detection time select bits 2 cycles of Not selected 6 Fix this bit to 0 RW Clock 6 1 output select bit 0 Clock 1 output disabled RW Note 2 P42 functions as a programmable I O port 1 Clock 1 output enabled P42 functions as a clock 6 out put pin Notes 1 While supplying the Vcc level to the CNVss pin this bit becomes 1 after a reset Fixed to 1 2 This bit is ignored in the microprocessor mode It may be either O or 1 Bits O to 2 and 4 to 7 are not used at software reset Fig 13 2 1 Structure of processor mode register 13 12 7702 7703 Group User s Manual CHAPTER 14 CLOCK GENERATING CIRCUIT 14 1 Oscillation circuit example 14 2 Clock CLOCK GENERATING CIRCUIT 14 1 Oscillation circuit example This chapter describes a clock generating circuit which supplies the operating clock of the central processing unit CPU bus interface unit BIU or internal peripheral devices The clock generating circuit contains the oscillation circuit 14 1 Oscillation circuit example To the oscillation circuit a ceramic resonator or a quartz crystal oscillator can be connected or the clock which is externally generated can be input The example of the oscillation circuit is described below 14 1 1 Connection example using resonator oscillator Figure 14 1 1 shows an example when connecting a ceramic resonator
323. lied The data at the even address is not fetched into the data buffer For instructions that are affected by the data length flag m and the index register length flag x operation or is applied when flag m or x 0 operation or is applied when flag m or x 1 7702 7703 Group User s Manual CENTRAL PROCESSING UNIT CPU 2 2 Bus interface unit E Internal address bus Ao tO A23 Internal data bus Do tO D7 X Data Even address Internal data bus Ds tO D15 Data Odd address z Internal address bus Ao to A23 Address Odd address Address Even address Internal data bus Do to D7 Invalid data Data Even address Internal data bus Ds to D15 Data Odd address Invalid data Fig 2 2 3 Basic operating waveforms of bus interface unit BIU 7702 7703 Group User s Manual 2 15 CENTRAL PROCESSING UNIT CPU 2 3 Access space 2 3 Access space Figure 2 3 1 shows the M37702 s access space By combination of the program counter PC which is 16 bits of structure and the program bank register PG a 16 Mbyte space from addresses 000000 to FFFFFF e can be accessed For details about access of an external area refer to Chapter 12 CONNECTION WITH EXTERNAL DEVICES The memory and I O devices are allocated in the same access space Accordingly it is possible to perform transfer and arithmetic operations using the same instructions without discrimination of the memory f
324. lse mode PWM mode Timer mode Timer Ai i Gate function Timer Ai counter 16 interrupt request bit Polarity Event counter mode itchi switchin Count start bit 9 Always down count except for event counter mode Trigger Down count Up down bit O Pulse output function select bit T TAi our s Fig 5 2 1 Block diagram o Timer A 7702 7703 Group User s Manual 5 3 TIMER A 5 2 Block description 5 2 1 Counter and reload register timer Ai register Each of timer Ai counter and reload register consists of 16 bits The counter down counts each time the count source is input In the event counter mode it can also function as an up counter The reload register is used to store the initial value of the counter When the counter underflows or overflows the reload register s contents are reloaded into the counter Values are set to the counter and reload register by writing a value to the timer Ai register Table 5 2 1 lists the memory assignment of the timer Ai register The value written into the timer Ai register when counting is not in progress is set to the counter and reload register The value written into the timer Ai register when counting is in progress is set to only the reload register In this case the reload register s updated contents are transferred to the counter at the next reload time The value got when reading out the timer Ai register varies accor
325. lt gt lt th E P8D Port P8 input Test conditions e Vcc 2 7 5 5 V e Inputtiming voltage 0 2 V 0 8 V e Output timing voltage Vo 0 8 V Vor 2 0 V 18 22 7702 7703 Group User s Manual LOW VOLTAGE VERSI ON 18 4 Electrical characteristics 18 4 8 Memory expansion mode and microprocessor mode with no Wait Timing requirements Vcc 2 7 5 5 V Vss 0 V 40 to 85 C f Xw 8 MHz unless otherwise noted Symbol tw H tw L tr lt tsu P1D E tsu P2D E tsu P4D E tsu P5D E tsu P6D E tsu P7D E tsu P8D E th E P1D th E P2D th E P4D th E P5D th E PeD th E P7D 80 arameter External clock input cycle time dT External clock input high level pulse width s f 50 External clock input low level pulse width 50 External clock rise time s s 20 External clock fall time 2 Port P1 input setup time 8 Port P2 input setup time Port P4 input setup time 1393000 Port P5 input setup time 800 Port input setup time 1393000 Port P7 input setup time 1300 Port P8 input setup time Port P1 input hold time O Port P2 input hold time O Port P4 input hold time Port P5 input hold time Port P6 input hold time 02002001040 Port P7 input hold time Port P8 input hold time Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Switching characte
326. luding the PROM The PROM version can be used with the program written into the built in PROM 7703 Group Refer to Chapter 20 7703 GROUP about the pin connections and others 19 1 Overview In the PROM version programming to the built in PROM can be performed by using a general purpose PROM programmer and a programming adapter which is suitable for the used microcomputer The PROM version has the following two types One time PROM version Programming to the PROM can be performed once This version is suitable for a small quantity of and various productions EPROM version Programming to the PROM can be performed repeatedly because program can be erased by exposing the erase window on the top of the package to an ultraviolet light source This version can be used only for program development evaluation only The built in PROM version has the same functions as the mask ROM version except that the former has a built in PROM 19 2 7702 7703 Group User s Manual PROM VERSION 19 1 Overview Table 19 1 1 Write address of PROM version PROM size RAM size Write address Byte Byte 256K mode One time PROM version EPROM version M37702E2BXXXFP 1 000 to 1FFFFie 400016 to 7FFFie M37702E2AXXXFP Note 1 M37702E2LXXXHP M RERO Note 1 MSTTDAERDOOMP 1 N 2048 18000 to 1FFFFis 0000 to 7FFF46 2048 14000 to 1FFFF e ae 2048 1100016 to 1FFFF e Mamwemes amen
327. mal operating mode each pin has the same function as the mask ROM version Table 19 2 1 Pin description in EPROM mode Pin Functions Vcc Vss Power source input Apply 5 V 10 to pin Vcc and 0 V to pin Vss CNVss Apply VPP level when programming or verifying BYTE RESET Connect to pin Vss XIN Connect a ceramic resonator or a quartz crystal oscillator between pins XIN and Xour When an XOUT external generated clock is input the clock must be input to pin XIN and pin XOUT must be left open E Open AVcc AVss Analog power source input Connect pin AVcc to Vcc and pin AVss to Vss VREF Connect to pin Vss 00 07 Input pins for Ao A7 of address 10 17 Address input 15 Input pins for 15 of address Connect P17 to Vcc in 256K mode 20 27 pins for data Do D7 Connect to Vss 40 47 Connect to Vss P50 Control input Input 5 functions as PGM input pin in 1M mode Connect to Vcc in 256K mode P51 P52 P51 functions as OE input pin and P52 does as CE input pin 53 55 Input port 5 input Connect to Vcc P56 Connect to Vcc in 1M mode or to 55 256K mode P57 Connect to Vss P60 P67 Connect to Vss P70 P77 Connect to Vss P80 P87 Connect to Vss 7702 7703 Group User s Manual 19 5 PROM VERSION 19 3 1M mode 19 3 1M mode 1M mode can perform reading programming from and to the built in PROM with the same manner as M5M27C
328. ment mode select bits and pulse period pulse width measurements b3 b2 Pulse period pulse width measurement Measurement interval Valid edges 0 0 Pulse period measurement From falling to falling Falling 0 1 From rising to rising Rising 1 O Pulse width measurement From falling to rising and from rising to falling Falling and rising 1 1 Not selected 6 24 7702 7703 Group User s Manual TIMER B 6 5 Pulse period pulse width measurement mode 2 Timer Bi overflow flag The timer Bi interrupt request occurs when the measurement pulse s valid edge is input or the counter overflows The timer Bi overflow flag is used to identify the cause of the interrupt request that is whether it is an overflow occurrence or an effective edge input The timer Bi overflow flag is set to 1 by an overflow Accordingly the cause of the interrupt request occurrence is identified by checking the timer Bi overflow flag in the interrupt routine When a value is written to the timer Bi mode register with the count start bit 1 the timer Bi overflow flag is cleared to 0 at the next count timing of the count source The timer Bi overflow flag is a read only bit Use the timer Bi interrupt request bit to detect the overflow timing Do not use the timer Bi overflow flag to do that Figure 6 5 3 shows the operation during pulse period measurement Figure 6 5 4 shows the operation during pulse width measurement Count source U
329. mple of repeat sweep mode 8 24 7702 7703 Group User s Manual A D CONVERTER 8 8 Repeat sweep mode A D control register and A D sweep pin select register b7 0 A D control register address 1 16 A D sweep pin select register address 1F 6 b7 50 A D sweep pin select bits b1 50 0 ANo AN 2 pins Repeat sweep mode Trigger select bit 1 ANo ANs 4 pins 0 Internal trigger 1 0 ANo ANS 6 pins 1 External trigger 1 1 8 pins A D conversion start bit 0 Stop A D conversion A D conversion frequency o AD select bit 0 f2 divided by 4 1 2 divided by 2 x OF or 1 ePort P7 direction register b7 bO Port P7 direction register address 1116 ANo AN Set the bits corresponding to analog input pins to 0 ANa Set bit 7 to 0 when ANs selecting external trigger ANe AN7 b 4 e b Ge Set A D conversion start bit to 1 b7 bo 11 A D control register address 1E 6 A D conversion start bit d Selecting external trigger wv Input falling edge to ADrnc Selecting internal trigger Trigger occur Operation start Note Write each bit except bit 6 of the A D control register and each bit of the A D sweep pin select register when the A D conversion sto
330. nal clock 1 External clock Stop bit length select bit 0 1 stop bit 1 2 stop bits UARTO transmit interrupt control register Address 7116 UART1 transmit interrupt control register Address 7316 b7 00 hh Interrupt priority level select bits When using interrupts set these bits to level 1 7 When disabling interrupts set these bits to level 0 Odd Even parity select bit 0 Odd parity 1 Even parity Parity enable bit 0 Parity disabled 1 Parity enabled 7 Sleep select bit 0 Sleep mode cleared ignored Io U p WARTO transmit buffer register Addresses 3316 3216 UN UART1 transmit buffer register Addresses 3B16 3A16 b15 b8 b7 bO UARTO transmit receive control register 0 Address 3416 M 2 UART1 transmit receive control register 0 Address 3C16 67 00 oT count source select bits b1 bO 0 0 0 1 H6 1 0 fe4 1 12612 lt Set transmit data here a UARTO transmit receive control register 1 Address 3516 UART1 transmit receive control register 1 Address 3D16 b7 bO Transmit enable bit 1 Transmission enabled CTS RTS select bit 0 075 function selected 1 ATS function selected CTS function disabled Note The CTS RTS select bit is valid when the CTS RTS enable bit is O and the D Ai output enable bit bits 6 and 7 at I I address 1F 16 is 0 Transmission starts In
331. nce within 20 mm Separate the Vss pattern for oscillation purpose from the other Vss patterns Refer to Figure 19 Reasons The microcomputer operates synchronously with the clock generated by the oscillation circuit If noise gets into the clock input output pins the clock waveform is disturbed which can cause the microcomputer to malfunction or a program runaway Furthermore if noise causes a potential difference between the microcomputer s Vss level and the XIN XIN XOUT XOUT Vss Vss IN G O K oscillator s Vss level the oscillator G cannot generate an exact clock Fig 11 Wiring of clock input output pins M37702 M37702 3 Wiring of CNVss pin When connecting the CNVss and Vss pins connect them in the shortest possible distance Reasons The voltage level on the CNVss pin affects the selection of microcomputer s processor modes M37702 Noise M37702 If noise causes a potential difference between the voltage levels of the CNVss and Yss pins CNVss CNVss when these pins are connected X the microcomputer s processor Vss Vss mode will become unstable causing the microcomputer to N G malfunction or program runaway Fig 12 Wiring of CNVss pin 21 36 7702 7703 Group User s Manual APPENDIX Appendix 5 Countermeasures against noise 4 Wiring of CNVss V pin of built in PROM version lt In single chip or memory expansion mode gt Connect the CNVss Vee pin to the
332. ng L level 5 28 7702 7703 Group User s Manual TIMER A 5 4 Event counter mode Precautions when operating in event counter mode 1 By reading the timer Ai register the counter value can be read out at any timing while counting is in progress However when the timer Ai register is read at the reload timing shown in Figure 5 4 9 a value FFFFie at the underflow 000015 at the overflow is read out When reading the timer Ai register after setting a value to the register while counting is not in progress and before the counter starts counting the set value is read out correctly 1 For down count 2 For up count Reload Reload C Count 2 in FFDFFFE FFFF n 1 Read val Read val x wee 2 1 0 1 ad Hex FFFD FFFE FFFF 0000 Time Time n Reload register s contents n Reload register s contents Fig 5 4 9 Reading timer Ai register 2 The TAiour pin is used for all functions listed below Accordingly only of these functions can be selected for each timer Switching between up count and down count by TAicur pin s input signal Pulse output function wo phase pulse signal processing function tor timers A2 to 4 7702 7703 Group User s Manual 5 29 TIMER A 5 5 One shot pulse mode 5 5 One shot pulse mode In this mode the timer outputs a pulse which has an arbitrary width once Refer to Tab
333. ng is assigned Note Use the SEB or CLB instruction to set each interrupt control register Fig 5 2 4 Structure of timer Ai interrupt control register 1 Interrupt priority level select bits bits 2 to 0j These bits select a timer Ai interrupt s priority level When using timer Ai interrupts select priority levels 1 to 7 When a timer Ai interrupt request occurs its priority level is compared with the processor interrupt priority level IPL so that the requested interrupt is enabled only when its priority level is higher than the IPL However this applies when the interrupt disable flag 1 0 To disable timer Ai interrupts set these bits to 0002 level 0 2 Interrupt request bit bit 3 This bit is set to 1 when the timer Ai interrupt request occurs This bit is automatically cleared to 0 when the timer Ai interrupt request is accepted This bit can be set to 1 or 0 by software 7702 7703 Group User s Manual 5 TIMER A 5 2 Block description 5 2 5 Port P5 and port P6 direction registers The I O pins of Timers AO to are shared with port P5 and the I O pins of Timer A4 are shared with port P6 When using these pins as Timer Al s input pins set the corresponding bits of the port P5 and port P6 direction registers to O to set these ports for the input mode When used as Timer Ai s output pins these pins are forcibly set to output pins of Timer Ai regardless of t
334. ng mode Accu Accumulator s upper 8 bits DIR X Direct indexed X addressing mode Accumulator s lower bits GIR Y Direct indexed Y addressing mode A Accumulaior A DIR Direct indirect addressing moda Accumulator A s upper bits DIR X Direct indexed X Indirect addressing mode AL Accumulator A s lower B bits DIR Y Direct indirect indexed Y addressing mods B Accumulator L Diract indirect long addressing mode Bu Accumulator B s upper 8 bits L CDIR Y Direct indirect long indexed Y addressing mode B Accumulator B s lower B bits ABS Absolute addressing mode x Index ragister X ABS b bsoiute addressing mode Index register X s upper 8 bite ABS X Absolute indexed X addressing mode XL Index register X s lower B bits ABS Y Absolute Indexed Y addressing made index register Y ABL Absolute long addressing mode Index register Y s upper 8 bits ABL X Absoluta long indexed X addressing mode Y Index register Y s lower 8 bits ABS Absolute indirect addressing mode 5 Stack pointer L ABS Absolute indirect long addressing mode PC Program counter ABS X Absolute Indexed X indirect addressing moda PCu Program countera upper 8 bits STK Stack addressing moda Program counters lower 8 bits REL Relative addressing mode PG Program bank register DIR b REL Direci bit relativa addressing mode DT Data bank register ABS REL Absolute bit relative addressing mode DPR Direct page register SR Sta
335. ng stopped the TAiour pin outputs L level When a trigger is generated during counting the counter counts the count source n 1 times after a new trigger is generated Note The above applies when an external trigger rising of pin s input signal is selected Fig 5 5 5 Example of operation in one shot pulse mode selecting external trigger 7702 7703 Group User s Manual 5 37 TIMER A 5 5 One shot pulse mode Precautions when operating in one shot pulse mode 1 If the count start bit is cleared to 0 during counting the counter stops counting and the reload register s contents are reloaded into the counter and the TAiour pin s output level becomes L At the same time the timer Ai interrupt request bit is set to 1 2 A one shot pulse is output synchronously with an internally generated count source Accordingly when selecting an external trigger there will be a delay equivalent to one cycle of count source at maximum from when a trigger is input to the pin till when a one shot pulse is output Trigger input TAiin pin s input signal Count source output from TAiour pin Starts outputting of one shot pulse One shot pulse Output delay Note The above applies when an external trigger falling of T Ai pin s input signal is selected Fig 5 5 6 Output delay in one shot pulse output 3 When setting the timer s operating mode in one of
336. nk register is an 8 bit register This register indicates the high order 8 bits of the address 24 bits at which an instruction to be executed next in other words an instruction to be read out from an instruction queue buffer next is stored These 8 bits are called bank When a carry occurs after adding the contents of the program counter or adding the offset value to the contents of the program counter in the branch instruction and others the contents of the program bank register is automatically incremented by 1 When a borrow occurs after subtracting the contents of the program counter the contents of the program bank register is automatically decremented by 1 Accordingly there is no need to consider bank boundaries in programming usually In the single chip mode make sure to prevent the program bank register from being set to the value other than 0016 by executing the branch instructions and others It is because the access space of the single chip mode is the internal area within the bank 016 This register is cleared to 0016 at reset 7702 7703 Group User s Manual 2 5 CENTRAL PROCESSING UNIT CPU 2 1 Central processing unit 2 1 7 Data bank register DT The data bank register is an 8 bit register In the following addressing modes using the data bank register the contents of this register is used as the high order 8 bits bank of a 24 bit address to be accessed Use the LDT instruction to set a value to this re
337. notation 7702 7703 Group User s Manual 21 57 APPENDIX Appendix 8 Machine instructions Appendix 8 Machine instructions MACHINE INSTRUCTIONS fon one modas PR 108 RE 42 7 75 Dalails Apc G Ape tM 6 Adds carry he accumulator and ihe mamory contents The resuit is entared into the accumulator When tha D ling 18707 binary additions Is dong and when tha D lag is 1 dacimai addition 6 dona ADC Note 1 2 AND Acc Acc Obtains the logical product of the contenta of the accumu Mote 1 2 lat and tha contents of tha memory The resuit is en tered into the accumulato m ohifis the accumulator the memory contents ons bit c H pd 5 0 ine left D is entered inta of the accumulator the memory The coments of bit 15 bi 7 when the m flag i5 1 of the accumulato or memory before shill is entered Imo the C flag mel Tests the specified bit of the memory Branchaa when all tha contents of Ihe specified bit is O Branches when the conients of the is 71 AL HEINE Ani I Branchas when tha contents ol the H flag is 05 ni mn PC PC offset Jumps to tha address indicated by ihe program counter Nota PG PG 1 plus the offset valua carry occured PG PG 1 borrow occured Executes software inl rruption MLS PG 85 1 5 5 5 1 M S PC 5 MiS PS
338. nting Down count A state where the oscillation circuit is operating however the Stop mode program execution is stopped By executing the WIT instruction the microcomputer enters Wait mode 7702 7703 Group User s Manual 3 GLOSSARY MEMORANDUM 4 7702 7703 Group User s Manual MITSUBISHI SEMICONDUCTORS USER S MANUAL 7702 7703 Group Mar First Edition 1997 Editioned by Committee of editing of Mitsubishi Semiconductor USER S MANUAL Published by Mitsubishi Electric Corp Semiconductor Marketing Division This book or parts thereof may not be reproduced in any form without permission of Mitsubishi Electric Corporation 1997 MITSUBISHI ELECTRIC CORPORATION User s Manual 7702 7703 Group Renesas Technology Corp Nippon Bldg 6 2 Otemachi 2 chome Chiyoda ku Tokyo 100 0004 Japan H EF493 A KI 9703 Printed in Japan ROD New publication effective Mar 1997 1997 MITSUBISHI ELECTRIC CORPORATION Specifications subject to change without notice
339. ntrol registers UARTi transmit receive control register 1 b7 b6 b5 b4 b3 b2 bl bO UARTO transmit receive control register 1 Address 3516 UART1 transmit receive control register 1 Address 3D16 x Bitname x Biname Functions At reset reset RW LI enable bit gt disabled Transmission enabled Transmit buffer empty flag 0 Data present in transmit buffer register 1 No data present in transmit buffer register Receive enable bit Reception disabled Reception enabled Receive complete flag 0 2 presaj In receive uffer register 1 Data present in receive buffer register 4 Overrun error flag Note 1 0 No overrun error 1 Overrun error detected 5 Framing error flag Notes 1 2 framing error Valid in UART mode Framing error detected Parity error flag Notes 1 2 No parity error Valid in UART mode Parity error detected Error sum flag Notes 1 2 d No error Valid in UART mode Error detected Notes 1 Bits 7 to 4 are cleared to 0 when clearing the receive enable bit to 0 or when reading the low order byte of the receive buffer register addresses 3616 3E16 out 2 Bits 5 to 7 are ignored in the clock synchronous serial I O mode UARTi receive buffer register b15 b8 b7 b0 b7 bO UARTO receive buffer register Addresses 3716 3616 UART1 receive buffer register Addresses 3F16 3E16 8100 to 8100 Re
340. ode This mode is used to transfer data between the specified microcomputers which are connected by using UARTi The sleep mode is selected by setting the sleep select bit bit 7 at addresses 3016 3816 to 1 when receiving In the sleep mode receive operation is performed when the MSB Ds when the transfer data length is 9 bits D when it is 8 bits De when it is 7 bits of the receive data is 1 Receive operation is not performed when the MSB is 0 The UARTI receive register s contents are not transferred to the UARTi receive buffer register Additionally the receive complete flag and error flags do not change and the receive interrupt request does not occur The following shows an usage example of sleep mode when the transfer data length is 8 bits Set the same transfer data format for the master and slave microcomputers Select the sleep mode for the slave microcomputers Transmit data which has 1 in bit 7 and the address of the slave microcomputer with which communicates in bits O to 6 from the master microcomputer to all slave microcomputers All slave microcomputers receive data of step At this time the UARTi receive interrupt request occurs In all slave microcomputers check in the interrupt routine whether bits 0 10 6 in the receive data match their addresses In the slave microcomputer of which address matches bits 0 to 6 in the receive data clear the sleep mode Do not clear
341. of the direction register can be changed by noise or a program runaway generated by noise To improve its reliability we recommend to periodically set the contents of the direction register by software When processing unused pins use the possible shortest wiring within 20 mm from the microcomputer This applies when H level is input to the BYTE pin his applies when H level is input to the BYTE pin and the access space is 64 Kbytes When supplying Vss level to the CNVss pin these pins remain set to the input mode until they are switched to the output mode by software after reset While pins remain set to the input mode consequently voltage levels of pins are unstable and a power source current can increase This applies when a clock externaily generated is input to the Xm pin In the 7703 Group the following ports does not have the corresponding pins and have only the direction registers Fix the bit of these direction registers to 1 output mode Ports 4 46 P60 P61 Pos P67 P73 P 7e P84 P8s There is not the HLDA pin When processing unused pins use the possible shortest wiring within 20 mm from the microcomputer When setting ports for input mode When setting ports for output mode 4 4 P5 P8 4 4 P5 P8 Left open Left open Left open Fig 1 3 3 Example for processing unused pins in microprocessor mode 7702 7703 Group User s Manual 1 11 DESCRIPTION
342. og timer a DBC Note 1 FFFAt6 BRK instruction FFFCi6 zero divide FFFEi6 OOFFFF e RESET 1 The internal memory is not allocated Notes 1 DBC is an interrupt only for debugging do not use this interrupt 2 Access to the internal ROM area is disabled in the microprocessor mode Refer to section 2 5 Processor modes 3 Memory assignment of internal area varies according to the type of microcomputer Refer to Appendix 1 Memory assignment for other products Fig 2 4 1 Internal area s memory assignment 7702 7703 Group User s Manual 2 19 CENTRAL PROCESSING UNIT CPU 2 4 Memory assignment Address 016 F 216 316 416 516 616 716 816 916 A16 B16 C16 D16 E16 F16 1016 1116 1216 1416 1516 1616 1716 1816 1916 1A16 1 16 1 16 1D16 1E16 A D control register 1F16 2016 21642 2216 A D register 1 2316 2416 2616 register 3 2716 _ 2816 A D register 4 2916 00 0 0 0 0000000 2A16 A D register 5 2B16 A D register 2 A D register 6 2C16 SSS 2E16 A D register 7 26 _ OSOS 3016 UARTO transmit receive mode register 3116 UARTO baud rate register BRGO 3216 UARTO transmit buffer register 3316 3416 UARTO transmit receive control register 0 3916 UART1 baud rate register BRG1 16 UART1 transmit buffer register 3C16 UART1 transmit receive control register 0 3D16 UART1 transmit receive control registe
343. on in that page is listed 7702 7703 Group User s Manual 21 45 APPENDIX Appendix 6 Q amp A Interrupt If an interrupt request b occurs while executing an interrupt routine a is the main routine is not executed before the INTACK sequence for the next interrupt b is executed after the interrupt routine a under execution is completed Sequence of execution RTI instruction Interrupt routine lt Main routine lt INTACK sequence for interrupt b Condition is cleared to 0 with theRTI instruction The interrupt priority level of the interrupt b is higher than the main routine IPL The interrupt priority detection time is 2 cycles of sampling for interrupt requests are performed by sampling pulses generated synchronously with the CPU s op code fetch cycles 1 If the next interrupt request b occurs before the sampling pulse for the RTI instruction is generated the microcomputer executes the INTACK sequence for b without executing the main routine not even one instruction because sampling is completed while executing the RTI instruction yulnierrupt request b D Sampling pulse p RTI instruction Interrupt routine a lt INTACK sequence for interrupt b If the next interrupt request b occurs immediately after generating of the sampling pulse the microcomputer executes one instruction of the main routine before executing the INTACK
344. on of reception b Checking error bh UARTO transmit receive control register 1 Address 3516 UART1 transmit receive control register 1 Address 3D16 Overrun error flag Framing error flag Parity error flag Error sum flag 0 No error 1 Error detected b dA When using interrupts The receive interrupt request occurs when reception is completed UARTI receive interrupt 48 eading of receive data UARTO receive buffer register Addresses 3716 3616 UART1 receive buffer register Addresses 3F 16 3E16 b15 b8 b7 bO R ead out receive data 664 C Processing after reading out receive data D Fig 7 4 9 Processing after reception s completion Note his figure shows the bits and registers required for processing Refer to Figure 7 4 11 about the change of flag state and the occurrence timing of an interrupt request 7702 7703 Group User s Manual SERIAL I O 7 4 Clock asynchronous serial I O UART mode 7 4 6 Receive operation When the receive enable bit is set to 1 the UARTi enters the reception enabled state and reception starts at detecting ST The receive operation is described below The input signal of the RxDi pin is taken into the most significant bit of the UARTi receive register synchronously with the transfer clock s rising The contents of UARTi receive register ar
345. on of the external data bus width do not affect each other 7702 7703 Group User s Manual CONNECTION WITH EXTERNAL DEVICES 12 1 Signals required for accessing external devices External data bus width 16 bits BYTE L lt 16 bit data access gt a Access from even address E 4 ALE N Ds 15 015 Data odd A16 Do A23 D7 Data even Ao b Access from odd address E NV QQ Z ALE N K N As De Ars Di A16 Do As D7 y NK X 8 bit data access C Access to even address d Access to odd address E vn Ff E ALE N ALE N AT A15 015 AddressX A15 015 Data odd A16 Do A23 D7 Data even A16 Do A23 07 Address X Ao N Ao y N _ Y M XK Fig 12 1 5 Example of operating waveforms of signals input and output to from externals 1 7702 7703 Group User s Manual 12 9 CONNECTION WITH EXTERNAL DEVICES 12 1 Signals required for accessing external devices External data bus width 8 bits BYTE lt 8 16 bit data access gt e Access from even address ALE Ao Ar l l X Address X Address A16 Do A23 D7 f Access from odd address _ A
346. on result is transferred to the A D register i each time each pin is converted The operation to all selected analog input pins is performed again The operation is performed repeatedly until the A D conversion start bit is cleared to 0 by software When the level of the ADtra pin changes from to L during operation the operation at that point is cancelled and is restarted from step Figure 8 8 2 shows the conversion operation in the repeat sweep mode 8 26 7702 7703 Group User s Manual A D CONVERTER 8 8 Repeat sweep mode Trigger occur Conversion result Convert input voltage from ANo pin A D register 0 Conversion result Convert input voltage from 1 A D register 1 Conversion result Convert input voltage from ANi pin a A D register i Fig 8 8 2 Conversion operation in repeat sweep mode 7702 7703 Group User s Manual 8 27 A D CONVERTER 8 9 Precautions when using A D converter 8 9 Precautions when using A D converter 1 Write to each bit except bit 6 of the A D control regisrer and each bit of the A D sweep pin select register before a trigger occurs while the A D converter stops operation 2 When selecting the AN7 pin as an analog input pin while an external trigger is selected A D conversion is performed for a trigger input which is the input voltage on the pin and the conversion result is stored into the A D registe
347. onnect these pins to Vss Notes 1 When setting these ports to the output mode and leave them open they remain set to the input mode until they are switched to the output mode by software after reset While ports remain set to the input mode consequently voltage levels of pins are unstable and power source current can increase The contents of the direction register can be changed by noise or a program runaway generated by noise To improve its reliability we recommend to periodically set the contents of the direction register by software When processing unused pins use the possible shortest wiring within 20 mm from the microcomputer his applies when H level is input to the BYTE pin his applies when H level is input to the BYTE pin and the access space is 64 Kbytes 4 When supplying Vss level to the CNVss pin these pins remain set to the input mode until they are switched to the output mode by software reset While pins remain set to the input mode consequently voltage levels of pins are unstable and a power source current can increase his applies when a clock externa ly generated is input to the Xm pin 6 In the 7703 Group the following poris does not have the corresponding pins and have only the direction registers Fix the bit of these direction registers to 1 output mode Ports P43 P46 P6o P6 P65 P67 P7s P7e P84 85 There is not the HLDA pin 7 Set the P42 pin to the P42 function
348. ontents of the UARTi receive buffer register When an overrun error occurs the next receive data is written into the UARTI receive buffer register and the UARTi receive interrupt request bit is not changed An overrun error is detected when data is transferred from the receive register to the UARTi receive buffer register and the overrun error flag is set to 1 The overrun error flag is cleared to 0 by reading out the low order byte of the UARTi receive buffer register or clearing the receive enable bit to 0 When an overrun error occurs during reception initialize the overrun error flag and the UARTi receive buffer register before performing reception again When it is necessary to perform retransmission owing to an overrun error which occurs in the receiver side set the transmit buffer register again before starting transmission again The method of initializing the UARTi receive buffer register and that of setting the UARTi transmit buffer register again are described below 1 Method of initializing UARTi receive buffer register Clear the receive enable bit to 0 reception disabled Set the receive enable bit to 1 again reception enabied 2 Method of setting UARTi transmit buffer register again Clear the serial I O mode select bits to 0002 Serial ignored 2 Set the serial mode select bits to 0012 again Set the transmit enable bit to 1 transmiss
349. or Timer AO register Addresses 4716 4616 Timer A1 register Addresses 4916 4816 Timer A2 register Addresses 4 16 4 16 Timer register Addresses 4016 4 16 Timer A4 register Addresses 4F 16 4 16 Note When operating as 8 bit pulse width modulator m 1 28 1 fi n m 1 Period H level width 216 1 fi Period H level width fi Note When operating as 16 bit pulse width modulator fi Frequency of count source However if n 001 the pulse width modulator does not operate and the TAiour pin outputs L level At this time no timer Ai request occurs Continue to 7702 7703 Group User s Manual fi Frequency of count source However if n 000016 the pulse width modulator does not operate and the TAiour pin outputs L level At this time no timer Ai request occurs Figure 5 6 3 Fig 5 6 2 Initial setting example for registers relevant to PWM mode 1 5 41 TIMER A 5 6 Pulse width modulation PWM mode From preceding Figure5 6 2 Setting interrupt priority level bO E b7 Timer Ai interrupt control register i 0 to 4 Addresses 7516 to 7916 Interrupt priority level select bits When using interrupts set these bits to level 1 7 When disabling interrupts set these bits to level 0 When external C 4 trigger is selected z When internal trigger is selected
350. ored and control returns to the routine executed before the acceptance of interrupt request and processing is resumed from it left off For any register that is saved by software in the interrupt routine restore it with the same data length and same register length as it was saved by using the PUL instruction and others before executing the RTI instruction 4 9 Multiple interrupts When a branch is made to the interrupt routine the microcomputer becomes the following situation Interrupt disable flag 1 1 interrupts disabled Interrupt request bit of the accepted interrupt 0 Processor interrupt priority level IPL interrupt priority level of the accepted interrupt Accordingly as long as the IPL remains unchanged the microcomputer can accept the interrupt request that has higher priority than the interrupt request being executed now by clearing the interrupt disable flag 1 to 0 in the interrupt routine This is multiple interrupts Figure 4 9 1 shows the multiple interrupt mechanism The interrupt requests that have not been accepted owing to their low priority levels are retained When the RTI instruction is executed the interrupt priority level of the routine that the microcomputer was executing before accepting the interrupt request is restored to the IPL Therefore one of the interrupt requests being retained is accepted when the following condition is satisfied at next detection of interrupt priority level
351. ort P4 4 bits Without P4s to P4e pins 8 bits Port P5 8 bits 8 bits Port P6 4 bits Without P60 P6 P6e and P67 pins 8 bits Port P7 4 bits Without to P7e pins 8 bits Port P8 6 bits Without P84 and 85 pins 8 bits Timer 16 bits X 8 16 bits X 8 With timer I O pins Input pin TAim Output With timer I O pins Input pin TAjin Output TA1 pin TAiour i 2 O to 3 pin TAjour j O to 4 TA2 With timer input pins Input pin TBkin k Internal timer Without I O pins 0 to 2 Serial I O z UARTO Clock synchronous or Clock asynchronous Clock synchronous or Clock asynchronous UARTI1 Clock asynchronous Clock synchronous or Clock asynchronous A D converter Resolution 8 bits X 1 Resolution 8 bits X 1 Analog input pin 4 channels ANo AN AN Analog input pin 8 channels ANo to AN pins Without ANs to ANe pins pins Package 64 pin plastic molded SDIP 64P4B 80 pin plastic molded QFP 80P6N A 7702 7703 Group User s Manual 20 5 7703 GROUP 20 4 Functional description 20 4 1 pin The M37703 does not have the following pins of the M37702 Port P33 Ports P43 to P4e Ports P60 P61 P66 P67 Ports P73 to 76 P84 85 1 Port direction register Fix the bits of port Pi i 3 4 6 7 8 direction register which do not have the corresponding pins to 1 All products of the M37703 need this procedure Do it regardless of the product type and the used mode
352. otherwise me nama Symbol Parameter eo MHz Unit Mn uin Wax Min td HLDA HLDA output delay time 50 50 ns Note For test conditions refer to Figure 15 10 1 15 12 7702 7703 Group User s Manual ELECTRICAL CHARACTERISTICS 15 6 Ready and Hold Ready function With no Wait 1 E output f RDY input tsu RDY lt lt th 6 1 RDY gt With Wait 1 E output RDY input tsu RDY_ 04 lt lt gt th 0 1 RDY gt Test conditions Vcc 5 Vt10 eInput timing voltage 1 0 V 4 0 V Output timing voltage 0 8 V 2 0 V 7702 7703 Group User s Manual 15 13 ELECTRICAL CHARACTERISTICS 15 6 Ready and Hold e Hold function Q 1 tsu HOLD 6 1 HOLD input td 1 HLDA gt HLDA output Test conditions Vcc 5 10 timing voltage Vi 1 0 V VH 4 0 V Output timing voltage VoL 0 8 V Vor 2 0 V 15 14 7702 7703 Group User s Manual th 0 1 HOLD td 6 1 HLDA ELECTRICAL CHARACTERISTICS 15 7 Single chip mode 15 7 Single chip mode Timing requirements Vcc 5 V 10 Vss 0 V Ta 20 to 85 C unless otherwise noted Symbol tw H tw L tr tr tsu POD E tsu P1D E tsu P2D E tsu P3D E tsu P5D E tsu P6D E tsu P7D E tsu P8D E th E PoD tsu P4D E Limits Externa
353. ount source input high level pulse width must be 2 cycles or more of count source TBiin input low level pulse width must be 2 cycles or more of count source Timer B input pulse width measurement mode w 9 TBi input cycle time E 1000 m ns 9 w TBH TBii input high level pulse width i A so frs 9 tw TBL input low level pulse width AAI Note TBiin input cycle time must be 4 cycles or more of count source input high level pulse width must be 2 cycles or more of count source input low level pulse width must be 2 cycles or more of count source A D trigger input ADrne input cycle time minimum allowable trigger 2000 ns ADrne input low level pulse width 250 ns 7702 7703 Group User s Manual 18 15 LOW VOLTAGE VERSION 18 4 Electrical characteristics Serial I O Symbol unit 500 _ ns tco TxDiholdtime ns External interrupt INTi input tw INH INT input high level pulse width 250 ns tw INL INT input low level pulse width 250 ns 18 16 7702 7703 Group User s Manual LOW VOLTAGE VERSION 18 4 Electrical characteristics Internal peripheral devices Le tc TB a lt TBiin input tc AD M tw ADL lt ADrnc input N tc Ck tw CKH gt CLKi input TxDi input RxDi input INTi input Test conditions 2 7 5
354. oup User s Manual STANDARD CHARACTERISTICS 16 1 Standard characteristics 16 1 2 Icc f Xin standard characteristics 1 characteristics on operating and at reset Measurement condition Vcc 5 V Ta 25 f XIN square waveform input single chip mode 20 On operating 10 Icc mA 5 10 15 20 25 30 MHz 2 Icc f Xin characteristics during wait Measurement condition Vcc 5 V 25 C square waveform input single chip mode 4 0 3 0 2 0 Icc mA 5 10 15 20 25 30 MHz 7702 7703 Group User s Manual 16 3 STANDARD CHARACTERISTICS 16 1 Standard characteristics 16 1 3 A D converter standard characteristics The lower lines of the graph indicate the absolute precision errors These are expressed as the deviation from the ideal value when the output code changes For example the change in output code from 0016 to 0116 should occur at 10 mV but the measured value is 5 mV Therefore the measured point of change is 10 5 15 mV The upper lines of the graph indicate the input voltage width for which the output code is constant For example the measured input voltage width for which the output code is 1 22 mV Therefore the differential non linear error is 22 20 2 mV 0 1L SB Measurement condition Vcc 5 12 V Xin 25 MHz Temp 25 ERROR 3 5
355. ource current In single chip mode E 25 19 38 output pins are mA open and the other ne C when pins are connected ding IS gt 15 4 7702 7703 Group User s Manual ELECTRICAL CHARACTERISTICS 15 4 A D converter characteristics 15 4 A D converter characteristics CONVERTER CHARACTERISTICS Vcc AVcc 5 V 10 Vss AVss 0 V 20 to 85 C unless otherwise noted w Bits Absolute accurac ORE E LSB Ronen Ladder resistance Veevo ko 25 MHz 9121420 tom Vrer Reference voltage 2 J BU V Va Analog input voltage V 7702 7703 Group User s Manual 15 5 ELECTRICAL CHARACTERISTICS 15 5 Internal peripheral devices 15 5 Internal peripheral devices Timing requirements Vcc 5 V 10 Vss 0 V Ta 20 to 85 C unless otherwise noted Timer A input count input in event counter mode Symbol Parameter Unit Min _ te TA input cycle time RUN NS fw TAH TAiin input high level pulse width 62 40 ns lw TAL TAi input low level pulse width 62 40 ns Timer A input gating input in timer mode Symbol Parameter Data formula Unit Min Max Min Max 9 lc TA TAii input cycle time x AE 5 30 ns t E i 2 i tw TAL TAii input low level pulse width EXN Pao ns Note
356. ow oreder byte of the UARTi transmission buffer register for each reception of 1 byte data The output level of the RTSi pin becomes L simultaneously at setting the receive enable bit to 1 The output level of this pin becomes H when receive starts and it becomes L when receive is completed The output level of this pin changes regardiess of the contents of the transmit enable bit the transmission buffer empty flag and the receive complete flag 7702 7703 Group User s Manual 7 33 SERIAL I O 7 3 Clock synchronous serial I O mode 6 When receiving data continuously an overrun error cannot be detected in the following situation when the next data reception is completed between reading the error flag by software and reading the UARTi receive buffer register Transfer clock UARTI receive buffer register Undetined X Data A Receive complete flag Overrun error flag UARTI receive interruput request bit Software management Error flag reading Data reading Data A error flag Data B reading No error When checking this error flag by software the microcomputer judges errors nothing because errors do not have occurred at data A receiving When receiving the data B the data B is written to the receive buffer register and the data A is cleard and the overrun error flag becomes 1 simultaneously The UARTi receive interrupt
357. ow supply voltage version Fig 13 1 9 Example of power on reset circuit 7702 7703 Group User s Manual 13 11 RESET 13 2 Software reset 13 2 Software reset When the power source voltage satisfies the microcomputer s recommended operating conditions the microcomputer is reset by writing 1 to the software reset bit bit at address This is called software reset In this case the microcomputer initializes pins CPU and SFR area just as in the case of a hardware reset However the microcomputer retains the contents of the internal RAM area Refer to Table 13 1 1 and Figures 13 1 2 to 13 1 6 Figure 13 2 1 shows the structure of processor mode register After completing initialization the microcomputer performs the internal processing sequence after a reset Refer to Figure 13 1 7 After that it executes a program beginning from the address set into the reset vector addresses which are FFFE e and FFFFte 67 b6 b5 b4 b3 b2 bl Tol TIIT Processor mode register Address 5E16 b1 bO Processor mode bits 0 0 Single chip mode 0 1 Memory expansion mode 0 Microprocessor mode 11 Nc selected NE 2 Wait bit Software Wait is inserted when accessing external area No software Wait is inserted when accessing external area Software reset bit The microcomputer is reset by WO writing 1 to this bit The value is 0 at reading EE b5 b4 0 0 7 cycles of 0 0 1 4 cyc
358. ower source current can increase The contents of the direction register can be changed by noise or a program runaway generated by noise To improve its reliability we recommend periodically set the contents of the direction register by software When processing unused pins use the possible shortest wiring within 20 mm from the microcomputer This applies when a clock externally generated is input to the Xm pin 3 In the 7703 Group the following ports does not have the corresponding pins and have only the direction registers Fix the bit of these direction registers to 1 output mode N ePorts P33 P4s P4e P60 P61 P6e P67 P7s P7e P84 P85 When setting ports for input mode When setting ports for output mode Left open Left open Left open Vcc Vcc Fig 1 3 1 Example for processing unused pins in single chip mode 7702 7703 Group User s Manual 1 9 DESCRIPTION 1 3 Pin description 2 In memory expansion mode Table 1 3 5 Example for processing unused pins in memory expansion mode Pin name Example of processing Ports P42 to P47 P5 to P8 Set for input mode and connect these pins to Vcc or Vss via a resistor or set for output mode and leave these pins open Notes 1 6 7 BHE Note 2 Leave them open Note 4 ALE Note 3 HLDA Note 6 Xout Note 5 Leave it open HOLD RDY Note 8 Connect these pins to Vcc via a resistor pull up AVcc Connect this pin to Vcc AVss VREF C
359. owever this applies when the interrupt disable bit 1 0 To disable timer Bi interrupts set these bits to 0002 level 0 2 Interrupt request bit bit 3 This bit is set to 1 when the timer Bi interrupt request occurs This bit is automatically cleared to 0 when the timer Bi interrupt request is accepted This bit can be set to 1 or cleared to 0 by software 6 6 7702 7703 Group User s Manual TIMER B 6 2 Block description 6 2 5 Port P6 direction register Timer Bi s input pins are shared with port P6 When using these pins as Timer Bi s input pins set the corresponding bits of the port P6 direction register to O to set these pins for the input mode Figure 6 2 5 shows the relationship between port P6 direction register and Timer Bi s input pins b7 06 b5 b2 bi bO Port P6 direction register Address 10 6 Bit Corresponding pin name Functions i TA4our pin 0 Input mode Rw 1 Output mode When using these pins as o RW IN To pin Timer Bi s input pins set the RW INT ch corresponding bits to 0 o RW IN 2 pin 0 RW pin o RW 1 RW TB2inpin o RW Bits 0 to 4 are not used for Timer Fig 6 2 5 Relationship between port P6 direction register and Timer Bi s input pins 7702 7703 Group User s Manual 6 7 TIMER B 6 3 Timer mode 6 3 Timer mode In this mode the timer counts an internally generated
360. own in Tables 19 5 1 and 19 5 2 When the user is planning to use the product shown in Tables 19 5 1 and 19 5 2 for evaluation or in early production and replace it later with the mask ROM version we recommend to use the substitute shown in Table 19 5 3 for evaluation or in early production However the substitute for the low voltage version has the larger ROM and RAM size Make sure of its memory usage The substitute for the 16 MHz version has the higher frequency of external clock input There are no precaution about its operation Table 19 5 3 Substitutes Type name to be used Substitute Remark M37702E2AXXXFP M37702E2BXXXFP The substitute has the higher frequency of external clock input M37702E2AFS M37702E2BFS M37702E4AXXXFP M37702E4BXXXFP M37702E4AFS M37702E4BFS M37702E2LXXXGP M37702E4LXXXGP The substitute has the larger ROM and RAM size M37702E4LXXXFP M37702E6LXXXFP 2 EPROM mode The products shown in Table 19 5 1 can use only 256K mode as the EPROM mode Do not use 1M mode 7702 7703 Group User s Manual 19 19 PROM VERSION 19 5 Usage precaution MEMORANDUM 19 20 7702 7703 Group User s Manual CHAPTER 20 7703 GROUP 20 1 Description 20 2 Performance overview 20 3 Pin configuration 20 4 Functional description 20 5 Electrical characteristics 20 6 PROM version 7703 GROUP 20 1 Description This chapter describes the 7703 Group The 7703 Group has the same functions as the 7
361. p mode this bit is cleared to O after the operation is completed In the repeat mode or repeat sweep mode the A D converter continues operating until this bit is cleared to 0 by software When external trigger is selected When the ADrnc pin level goes from to L with this bit 1 a trigger occurs causing the A D converter to start operating The A D converter stops when this bit is cleared to 0 In the one shot mode or single sweep mode this bit remains set to 1 even after the operation is completed In the repeat mode or repeat sweep mode the A D converter continues operating until this bit is cleared to O by software 4 A D conversion frequency 6 ab select bit bit 7 As shown in Table 8 2 1 the operating time of the A D converter varies depending on the selected operating clock by this bit Since the A D converter s comparator consists of capacity coupling amplifiers keep that gt 250 kHz during A D conversion Table 8 2 1 Time for performance to one analog input unit ps A D conversion frequency ao select bit O 1 Conversion time 8 MHz 28 5 16 Mi 1425 amp 25 MHz 18 24 9 12 7702 7703 Group User s Manual 8 5 A D CONVERTER 8 2 Block description 8 2 2 A D sweep pin select register Figure 8 2 3 shows the structure of the A D sweep pin select register b7 06 b5 b4 b3 b2 bl A D sweep pin select register Addr
362. p time for write tsup lsup tw EL td E P2Q P1Q la E P2Q P1Q ta g P20 ta E P1Q Table 17 1 2 lists the calculation formulas for each parameter Table 17 1 3 lists the data of each parameter Figure 17 1 1 shows the bus timing diagrams Figures 17 1 2 and 17 1 4 show the relationship between tax and f Xin Figures 17 1 3 and 17 1 5 show the relationship between tsup and Table 17 1 2 Calculation formulas for each parameter unit ns f Xin lt 8 MHz 8 MHz lt Xm 16 MHz 16 MHz lt lt 25 MHz Parameter Wait 9 9 9 latP1A E 172 X 10 1X 10 40 L ta P2A E tw EL Table 17 1 3 Data of each parameter unit ns e 16 MHz version 25 MHz version tsu P1D E 30 tsu P2D E td E P1Q 45 2 17 4 7702 7703 Group User s Manual APPLICATION 17 1 Memory expansion External data bus width 8 bits BYTE H m ALE A0 A7 A8 A15 A16 Do A23 D7 td P1A E Address high order td P2A E ta AD tsu P2D E td E P2Q tsu D R W When reading data When writing data External data bus width 16 bits BYTE L TII ALE A0 A7 A8 D8 A15 D15 A16 Do A23 D7 R W Add
363. processor mode bits are set to 012 the microcomputer enters the memory expansion mode when these bits are set to 102 the microcomputer enters the microprocessor mode The processor mode is switched at the rising edge of signal E after writing to the processor mode bits Figure 2 5 3 shows the timing when pin functions are switched by switching the processor mode from the single chip mode to the memory expansion or microprocessor mode with the processor mode bits When the processor mode is switched during the program execution the contents of the instruction queue buffer is not initialized Refer to Appendix 6 Q amp A e When Vcc level is supplied to CNVss pin After a reset the microcomputer starts operating in the microprocessor mode this case the microcomputer cannot operate in the other modes Fix the processor mode bits to 102 5 Table 2 5 2 lists the methods for setting processor modes Figure 2 5 4 shows the structure of processor mode register address 5E16 Written to processor mode bits KE 1 Programmable port gt External address bus Ao Note Functions of pins POt to P07 P1 to P40 to P42 are switched at the same timing shown above Function of pin P42 is however switched only when the processor mode is switched to the microprocessor mode Fig 2 5 3 Timing when pin functions are switched 7702 7703 Group User s Manual 2 25 CENTRAL PROC
364. ps before trigger occurs Fig 8 8 1 Initial setting example of repeat sweep mode 7702 7703 Group User s Manual 8 25 A D CONVERTER 8 8 Repeat sweep mode 8 8 2 Repeat sweep mode operation description 1 When an internal trigger is selected 2 The operation for the input voltage from the ANo pin starts when the A D conversion start bit is set to 1 The A D conversion of the input voltage from the ANo pin is completed after 57 cycles of dav Then the contents of the successive approximation register conversion result are transferred to the A D register O The operation to all selected analog input pins is performed The conversion result is transferred to the A D register i each time each pin is converted The operation to all selected analog input pins is performed again The operation is performed repeatedly until the A D conversion start bit is cleared to 0 by software When an external trigger is selected The A D converter starts operation for the input voltage from the pin when the input level to the ADtra pin changes from to L while the A D conversion start bit is 1 The A D conversion of the input voltage from the ANo pin is completed after 57 cycles of dav Then the contents of the successive approximation register conversion result are transferred to the A D register O The operation to all selected analog input pins is performed The conversi
365. pt When the INTi pin s level changes to an invalid level before an interrupt request is accepted the interrupt request is not Interrupt request is accepted retained Return to main routine Valid INTi pin level Invalid Main routine Main routine First interrupt routine Second interrupt Third interrupt routine routine Fig 4 10 4 Occurrence of INT interrupt request in level sense mode 4 24 7702 7703 Group User s Manual INTERRUPTS 4 10 External interrupts INTi interrupt 4 10 2 Switch of occurrence factor of INTi interrupt request To switch the occurrence factor of INTi interrupt request from the level sense to the edge sense set the INT interrupt control register in the sequence shown in Figure 4 10 5 1 To change the polarity set the INT interrupt control register in the sequence shown in Figure 4 10 5 2 1 Switching from level sense to edge sense 2 Changing polarity Set the interrupt priority level to level 0 Set the interrupt priority level to level 0 Disable INTi interrupt Disable INTi interrupt Clear level sense edge sense select bit to 0 Set polarity select bit Select edge sense Clear interrupt request bit to 0 oet the interrupt priority level to level 1 7 Enable acceptance of INTi interrupt request Clear interrupt request bit to 0 Set the interrupt priority level to level 1 7 Enable acceptance of INTi interrupt request Notes 1 Use the S
366. pted or the interrupt request bit is cleared to 0 by software Figure 6 3 3 shows an example of operation in the timer mode n Reload register s contents FFFF16 Starts counting Restarts counting E I 1 Counter contents Hex 000016 Set to 1 by software Cleared to 0 by software Set to 1 by software Count start bit Timer Bi interrupt 1 request bit Q fi frequency of count source Cleared to 0 when interrupt request is accepted or cleared by software Fig 6 3 3 Example of operation in timer mode 6 12 7702 7703 Group User s Manual TIMER B 6 3 Timer mode Precautions when operating in timer mode By reading the timer Bi register the counter value can be read out at any timing while counting is in progress However if the timer Bi register is read at the reload timing shown in Figure 6 3 4 the value FFFF16 is read out When reading the timer Bi register after setting a value to the register while counting is not in progress and before the counter starts counting the set value can be read out correctly Reload nter val eg 2 1 1 Read value He 2 1 En n Reload register s contents Time Fig 6 3 4 Reading timer Bi register 7702 7703 Group User s Manual 6 13 TIMER B 6 4 Event counter mode 6 4 Event counter mode In this mode the time
367. put Test conditions Vcc 2 7 5 5 V eInput timing voltage 0 2 V 0 8 V Output timing voltage Vor 0 8 V Vou 2 0 V 18 20 7702 7703 Group User s Manual LOW VOLTAGE VERSION 18 4 Electrical characteristics 18 4 7 Single chip mode Timing requirements Vcc 2 7 5 5 V Vss 0 V Ta 40 to 85 C unless otherwise noted Min tc External clock input cycle time 125 ns te Exemardockinputhighlevelpusewidh 80 lrs tu External clock input low level pulse width 1 50 ns t External clock 20 ns t External clock fal 20 ns teo Port PO input setup time 00 JFotPiiputsetupim 931 tup20 5 PortP2inputsetuptime 30 tsueso5 Port input setup 300 ns tpe Porta inputsetuptime 300 teupso e Port Poinputsetuptime 300 ns twee Port input setup time _ 130 tsuz Port P input setup time ns twee Port P8 input setup time y 7 950 ms ew Port PO input hold time 777 Wy olJ n Port P1 input hold time es ns thye Ps0 PPs ns i e PortP6inputholdtime 0 es PotP7iputhod me 0 ns Switching characteristics Vcc 2 7 5 5 V Vss 0 V Ta 40 to 85 C unless otherwise noted Symbol Parameter Wh Mars Unit in ax
368. put of which frequency is divided by 2 becomes the transfer clock Additionally the transfer clock is output from the CLKi pin By setting this bit to 1 in order to select an external clock the clock input to the CLKi pin becomes the transfer clock UART mode By clearing this bit to O in order to select an internal clock the clock which is selected with the count source select bits bits 0 and 1 at addresses 3416 3C e becomes the count source of the described later Then the pin functions as a programmable I O port By setting this bit to 1 in order to select an external clock the clock input to the CLKi pin becomes the count source of BRGi Always in the UART mode the BRGi output of which frequency is divided by 16 is the transfer clock BRGi UARTi baud rate register Refer to section 7 2 6 UARTi baud rate register BRGi 7702 7703 Group User s Manual 1 5 SERIAL I O 7 2 Block description 7 2 2 transmit receive control register 0 Figure 7 2 3 shows the structure of UARTi transmit receive control register 0 For bits 0 and 1 refer to 7 2 1 1 Internal External clock select bit b7 b6 b5 b4 b3 b2 bi b0 UARTO transmit receive control register 0 Address 3416 UART1 transmit receive control register 0 Address 3C 6 3 T BRG count source select bits b1 50 RW i 00 fe 0 1 f16 RW 164 11 1512 CTS RTS select bit CTS function selected
369. quartz crystal oscillator between pins Xin and Xour The circuit constants such as Rf Rd Cin and Cour shown in Figure 14 1 1 depend on the resonator oscillator These values shall be set to the resonator oscillator manufacturer s recommended values M37702 Fig 14 1 1 Connection example using resonator oscillator 14 1 2 Input example of externally generated clock Figure 14 1 2 shows an input example of the clock which is externally generated The external clock must be input from the Xin pin and the pin M37702 must be left open Externally generated clock vet LI LILI Vss Fig 14 1 2 Externally generated clock input example 14 2 7702 7703 Group User s Manual CLOCK GENERATING CIRCUIT 14 2 Clock 14 2 Clock Figure 14 2 1 shows the clock generating circuit block diagram CPU Central Processing Unit BIU Bus Interface Unit Watchdog timer frequency select bit Bit O at address 6116 fe XIN Xour fte Operation clock for Q Q Q Interrupt request S Q gt STP instruction R Reset o fea internal peripheral devices 1 8 f512 a 0 Watchdog timer 1512 frequency select bit faa Watchdog 4 timer Hold request 9 Ready request Request of CPU wait 122 S Q from BIU acceptance of Hold request included WIT instruction R Note This is the signal generated when the watchdog timers most significant bit becomes 0
370. r 7703 Group Timers B1 and B2s function of the 7703 Group varies from the 7702 Group s Refer to Chapter 20 7703 GROUP 6 1 Overview Timer Bi i O to 2 has three operating modes listed below Timer mode The timer counts an internally generated count source Event counter mode The timer counts an external signal Pulse period pulse width measurement mode The timer measures an external signal s pulse period or pulse width 6 2 Block description Figure 6 2 1 shows the block diagram of Timer B Explanation of registers relevant to timer B is described below Count source select bits Data bus odd f2 f 16 9 N 1 bus even f 64 512 High order 8 bits Timer mode Pulse period Pulse width measurement mode Event counter Q Timer Bi Polarity switchin and 5 pulse Timer Bi counter i 2 generating circuit q Count start bit Timer Bi overflow flag Counter reset circuit Valid in pulse period pulse width measurement mode Fig 6 2 1 Block diagram of Timer B 6 2 7702 7703 Group User s Manual TIMER B 6 2 Block description 6 2 1 Counter and reload register timer Bi register Each of timer Bi counter and reload register consists of 16 bits and has the following functions 1 Functions in timer mode and event counter mode The counter down counts each time count source is input The reload register is used to store the initial value of the counter W
371. r 1 16 UART1 receive buffer register 3F 16 3516 UARTO transmit receive control register 1 ister 3616 UARTO receive buffer register 3716 ister 3816 UART1 transmit receive mode register Fig 2 4 2 SFR area s memory map 2 20 Address Count start register One shot start register Up down register 4616 Timer AO register 4716 4816 Timer A1 register 4916 4A16 Timer A2 register 4B16 4C16 Timer A3 register 4D16 4E16 Timer A4 register 4F16 9016 Timer BO register 5116 9216 Timer B1 register 0316 9416 Timer B2 register 5516 5616 5716 5816 5916 5A16 5B16 5C16 5016 516 6016 6116 A D conversion interrupt control register UARTO transmit interrupt control register 7702 7703 Group User s Manual CENTRAL PROCESSING UNIT CPU 2 5 Processor modes 2 5 Processor modes The M37702 can operate in 3 processor modes single chip mode memory expansion mode and microprocessor mode Some pins functions memory assignment and access space vary according to the processor modes This section describes the differences between the processor modes Figure 2 5 1 shows a memory assignment in each processor mode Single chip mode Memory expansion mode Microprocessor mode Memory expansion mode Microprocessor mode SFR area SFR area SFR area i 00000216 555555505 Note 1 00000916 Internal Internal Internal RAM area RAM area RAM area 00027 16 00028016
372. r 7 Consequently the user cannot use the AN pin as an analog input pin while an external trigger is selected 3 Refer to Appendix 6 Countermeasures against noise when using the A D converter 8 28 7702 7703 Group User s Manual CHAPTER S WATCHDOG TIMER 9 1 Block description 9 2 Operation description 9 3 Precaution when using watchdog timer WATCHDOG TIMER 9 1 Block description This chapter describes Watchdog timer Watchdog timer has the following functions Detection of a program runaway Measurement of a certain time when oscillation starts owing to terminating Stop mode Refer to Chapter 10 STOP MODE 9 1 Block description Figure 9 1 1 shows the block diagram of the watchdog timer 32 e 512 6 Watchdog timer Hold request interrupt request FFE16 iS Set Writing to watchdog timer register address 6016 2 2Vcc RESET detection circuit ur STP instruction Fig 9 1 1 Block diagram of watchdog timer 9 2 7702 7703 Group User s Manual WATCHDOG TIMER 9 1 Block description 9 1 1 Watchdog timer Watchdog timer is a 12 bit counter that down counts the count source which is selected with the watchdog timer frequency select bit bit O at address 6116 A value FFF e is automatically set in Watchdog timer in the cases listed below An arbitrary value cannot be set to Watchdog timer e When dummy data is written to the watchdog timer reg
373. r A s operating mode Refer to Chapter 5 TIMER A 2 The access characteristics at addresses 5016 to 5516 varies according to Timer B s operating mode Refer to Chapter 6 TIMER B 3 The access characteristics of bit 5 at addresses 5 16 to 5016 varies according to Timer B s operating mode Refer to Chapter 6 TIMER B 4 The access characteristics of bit 1 at address 5 16 and its state immediately after a reset vary according to the voltage level supplied to the CNVss pin Refer to section 2 5 Processor modes Fig 8 Memory assignment in SFR area 3 7702 7703 Group User s Manual 21 9 APPENDIX Appendix 2 Memory assignment in SFR area Address Register name 6016 Watchdog timer register 6116 Watchdog timer frequency select register 6216 6316 6416 6516 6616 6716 6816 6916 6A16 6 16 6C16 6D16 6E16 6F 16 7016 0 conversion interrupt control register 7116 UARTO transmit interrupt control register 7216 UARTO receive interrupt control register 7316 UART1 transmit interrupt control register 7416 UARTI receive interrupt control register 7516 Timer AO interrupt control register 7616 Timer A1 interrupt control register 7716 Timer A2 interrupt control register 7816 Timer A3 interrupt control register 7916 Timer 4 interrupt control register 7 16 Timer BO interrupt control register 7 16 Timer 1 interrupt control register 7 16 Timer B2 interrupt control register 7D1
374. r counts an external signal Refer to Table 6 4 1 Figure 6 4 1 shows the structures of the timer Bi mode register and the timer Bi register in the event counter mode Table 6 4 1 Specifications of event counter mode Item Specifications Count source External signal input to the pin count source s effective edge can be selected from the falling edge the rising edge or both of the falling and rising edges by software Count operation Down count When the counter underflows reload register s contents are reloaded and counting continues Divide ratio 1 l l l l n4 1 n Timer Bi register setting value Count start condition When count start bit is set to 1 Count stop condition When count start bit is cleared to 0 Interrupt request occurrence timing When the counter underflows TBiIN pin function Count source input Head from timer Bi register Counter value can be read out Write to timer Bi register e While counting is stopped When a value is written to the timer Bi register it is written to both reload register and counter While counting is in progress When a value is written to the timer Bi register it is written to only reload register Transferred to counter at next reload time 6 14 7702 7703 Group User s Manual TIMER B 6 4 Event counter mode 67 06 b5 b4 b3 02 bl ofa Timer Bi mode register i 0 to 2 Addresses 5Bie to 5016 b1 bO 0 1 Event counte
375. r mode b3 b2 0 0 Count at falling edge of external signal 0 1 Count at rising edge of external signal 1 0 Counts at both falling and rising edges of external signal 1 1 Not selected Nothing is assigned Undefined This bit is ignored event counter mode a 6 These bits are ignored in event counter mode b0 Timer BO register Addresses 5116 5016 Timer B2 register Addresses 5516 5416 15 to 0 These bits can be set to 000016 to FFFF e Undefined RW Assuming that the set value n the counter divides the count source frequency by n 1 When reading the register indicates the counter value Fig 6 4 1 Structures of timer Bi mode register and timer Bi register in event counter mode 7702 7703 Group User s Manual 6 15 TIMER B 6 4 Event counter mode 6 4 1 Setting for event counter mode Figure 6 4 2 shows an initial setting example for registers relevant to the event counter mode Note that when using interrupts set up to enable the interrupts For details refer to section Chapter 4 INTERRUPTS Selecting event counter mode and count polarity 4 bO 0 1 Timer Bi mode register i 0 to 2 Addresses 5B16 to 5Di6 b7 Selection of event counter mode Count polarity select bits b3 b2 0 0 Counts at falling of external signal 0 1 Counts at rising of external signal 1 0 Counts at both of falling and rising of externa
376. r s Manual TIMER A 5 4 Event counter mode 2 Two phase pulse signal processing function Timers A2 to A4 For timers A2 to A4 the two phase pulse signal processing function is selected by setting the two phase pulse signal processing select bits bits 5 to 7 at address 4416 to 1 Refer to Figure 5 4 5 Figure 5 4 6 shows the timer A2 A3 and A4 mode registers when the two phase pulse signal processing function is selected With timers selecting the two phase pulse signal processing function the timer counts two kinds of pulses of which phases differ by 90 degrees There are two types of the two phase pulse signal processing normal processing and quadruple processing In timers A2 and A3 normal processing is performed in timer A4 quadruple processing is performed For some bits of the port P5 and P6 direction registers correspond to pins used for two phase pulse input set these bits for the input mode 67 06 05 04 b3 02 bi 1 timer a3 mode register Address 59 9 Timer A4 mode register Address 5 16 X It may be either O or 1 Fig 5 4 6 Timer A2 A3 and A4 mode registers when two phase pulse signal processing function is selected Normal processing The timer up counts the rising edges to the pin when the phase has the relationship that the TAkin pin s input signal level goes from L to H while the TAkour 2 and 3 input signal is H level
377. r underflows the reload register s contents are reloaded and counting continues The timer Bi interrupt request bit is set to 1 when the counter underflows The interrupt request bit remains set to 1 until the interrupt request is accepted or the interrupt request bit is cleared to 0 by software Figure 6 4 3 shows an example of operation in the event counter mode n Reload register s contents FFFF16 Starts counting Stops counting Counter contents Hex 000016 mu Cited 10707 E Set 1 by software software Set to 1 by software 4 Count start bit 9 Timer Bi interrupt gt 4711 41 request bit 0 Cleared to 0 when interrupt request is accepted or cleared by software Fig 6 4 3 Example of operation in event counter mode 7702 7703 Group User s Manual 6 17 TIMER B 6 4 Event counter mode Precautions when operating in event counter mode By reading the timer Bi register the counter value can be read out at any timing while counting is in progress However if the timer Bi register is read at the reload timing shown in Figure 6 4 4 the value FFFF16 is read out When reading the timer Bi register after setting a value to the register while counting is not in progress and before the counter starts counting the set value can be read out correctly Reload Counter value Hey 2 t 90 n nt Read value Weg 2 1
378. rase Clean the transparent glass before erasing There is a possibility that fingers fat and paste disturb the passage of ultraviolet rays and affect badly the erasure capability 3 Usage The EPROM version is a tool only for program development evaluation only and do not use it for the mass product run 19 18 7702 7703 Group User s Manual PROM VERSION 19 5 Usage precaution 19 5 4 Bus timing and EPROM mode The PROM versions shown in Tables 19 5 1 and 19 5 2 have the different bus timing from other PROM versions mask ROM external ROM versions Additionally they can use 256K mode as EPROM mode though its PROM size is 32 Kbytes or less Table 19 5 1 PROM versions having peculiar bus timing 16MHz version Bus timing lozx E 17 tpzx E Pez Type name lt 8 MHz 8MHz f Xin x 16 MHz M37702E2AXXXFP Limits 50 ns Limits 25 ns M37702bE2AFS Formulas Formulas M37702EAAXXXFP 1 X 10 12 5 1 X 10 6 25 M37702E4AFS 2X 2 7 Table 19 5 2 PROM versions having peculiar bus timing Low voltage version lpzx E P1Z tpzx E 22 Type name M37702b2L XXXGP Limits 50 ns Limits 50 ns M37702bEALXXXFP Formulas Formulas 1 X 10 1 x 10 2xi X 125 20 2 ta PoA td P1A E ta P2A td BHE E ta R w E 1 Bus timing The limits and formulas of the PROM versions having the peculiar bus timing which is different from other PROM versions are sh
379. re of count source TAiw input high level pulse width must be 2 cycles or more of count source TAiw input low level pulse width must be 2 cycles or more of count source Unit Timer A input external trigger input in one shot pulse mode Data formula minimum i E l 250 ns TAim input high level pulse width ns tw TAL TAi input low level pulse width E ns Timer A input external trigger input in pulse width modulation mode Sm in Un tw TAH TAi input high level pulse width 250 ns tw TAL TAii input low leve pulse width 250 ns Timer A input up down input in event counter mode tum TAowinputoydetlime 3 500 ns teu TAiourinput high level pulsewidth _ 2500 ns tum TAiourinput low level pulse width _ 2500 ns TAiorinputsetuptime oO 3 1 1000 ns bmw TAiwrinputhold me IC 71100042175 18 12 7702 7703 Group User s Manual LOW VOLTAGE VERSION 18 4 Electrical characteristics Timer A input Two phase pulse input in event counter mode in Max tc TA TAjin input cycle time 2 Tsu TAjn TAjour TAjin input setup time TAjour input setup time TAjoutT Ajin 5 7702 7703 Group User s Manual 18 13 LOW VOLTAGE VERSION 18 4 Electrical characteristics Internal peripheral devices Count input in event counter mode Gating input in timer mode
380. read the bit state 0 0 immediately after a reset 1 1 immediately after a reset Undefined immediately after a reset Address Register name 016 116 216 Port PO register 316 Port P1 register 416 Port PO direction register 516 Port P1 direction register 616 Port P2 register 716 Port P3 register 816 Port P2 direction register 916 Port direction register RW RW A16 Port P4 register B16 Port P5 register C16 Port P4 direction register D16 Port P5 direction register E16 Port P6 register F16 Port P7 register 1016 Port P6 direction register 1116 Port P7 direction register 1216 Port P8 register 1316 1416 Port P8 direction register 1516 1616 1716 1816 1916 1 16 1 16 1616 1016 1 16 A D control register 1F16 0 sweep pin select register 0 Always 0 at reading Access characteristics Nothing is assigned It is not possible to read the bit state The written value becomes invalid Always undefined at reading NN 0 immediately after a reset Fix to 0 285 immediately after a i Eg ws _ wn 7 F 08 910 0 0 of 0 0 0 Note Note Note Note Note In the 7703 Group after a reset set 1 to the bits which do not have corresponding pins Refer to section 20 4 1 I O pin Fig 13 1 3 State of SFR and internal RAM areas
381. reading timer Bi register is the reload register s contents measurement result Note 2 Write to timer Bi register Impossible Overflow flag The bit used to identify the source of an interrupt request occurrence Notes 1 This interrupt request does not occur when the first valid edge is input after the timer starts counting 2 The value read out from the timer Bi register is undefined until the second valid edge is input after the timer starts counting 7702 7703 Group User s Manual 6 19 TIMER B 6 5 Pulse period pulse width measurement mode b7 b6 b5 b 04 63 b2 bl b0 b1 bO 1 0 Pulse period Pulse width measurement mode Measurement mode select bits Pulse period measurement Interval between falling edges of measurement pulse Pulse period measurement Interval between rising edges of measurement pulse Pulse width measurement Interval from falling edge to rising edge and from rising edge to falling edge of measurement pulse 1 Not selected Nothing is assigned qem p e Note Overflow b7 b6 3h Count source select bits O f gt 0 1 fas Hn 171 512 Note The timer Bi overflow flag is cleared to 0 by writing to the timer Bi mode register with the count start bit 1 b15 b8 b7 bO b7 b0 Timer BO register Addresses 5116 5016 Timer B2 register Addresses 5516 5416 15 to 0 The measurement result of pulse period or Undefined pulse
382. register PS IPL Bit 9 in processor status register PS IPL Bit 10 in processor status register PS 7702 7703 Group User s Manual 4 9 INTERRUPTS 4 4 Interrupt priority level 4 4 Interrupt priority level When two or more interrupt requests are detected at the same sampling timing at which whether an interrupt request exists or not is checked in the case of the interrupt disable flag 1 0 interrupts enabled they are accepted in order of priority levels with the highest priority interrupt request accepted first Among a total of 19 interrupt sources the user can set the desired priority levels for 16 interrupt sources except software interrupts zero division and BRK instruction interrupts and the watchdog timer interrupt Use the interrupt priority level select bits to set their priority levels Additionally the reset which is handled as one that has the highest priority of all interrupts and the watchdog timer interrupt have their priority levels set by hardware Figure 4 4 1 shows the interrupt priority levels set by hardware Note that software interrupts are not affected by interrupt priority levels Whenever the instruction is executed a branch is certain to be made to the interrupt routine 16 interrupt sources except software interrupts Priority levels determined by hardware and watchdog timer interrupt The user can set the desired priority levels inside of the dotted line Priority level High
383. request The S s contents become S 5 after saving the above registers Fig 4 1 2 State of stack area just before entering interrupt routine 7702 7703 Group User s Manual 4 3 INTERRUPTS 4 2 Interrupt sources 4 2 Interrupt sources Table 4 2 1 lists the interrupt sources and the interrupt vector addresses When programming set the start address of each interrupt routine at the vector addresses listed in this table Table 4 2 1 Interrupt sources and interrupt vector addresses Interrupt Source Interrupt vector address Remarks High order Low order address address Reset Zero division BRK instruction DBC Note Watchdog timer INTo INT INT2 Timer AO Timer A1 Timer A2 Timer A3 Timer A4 Timer BO Timer B1 Timer B2 UARTO receive UARTO transmit UART1 receive UART1 transmit A D conversion FFFF e FFFE e Non maskable FFFDi6 FFF Cte Non maskable software interrupt FFFBie FFFAte Non maskable software interrupt Not used usually Non maskable interrupt External interrupt due to INTo pin input signal External interrupt due to IN 1 pin input signal External interrupt due 19 INTe pin input signal Internal interrupt from Timer AO FFEDie FFEBie FFE9 6e FFE5 e FFESie FFECte Internal interrupt from Timer A1 FFEAte Internal interrupt from Timer A2 FFE8 6 Internal interrupt from Timer A3 Internal interrupt from Timer A4 FFE4 6 Interna interrupt from Timer BO FFE2 6 Inte
384. ress Register name Access characteristics T tate immediately after a reset 6016 Watchdog timer register Note 1 2 2 2 6116 Watchdog timer frequency select register 6216 6316 6416 6516 6616 6716 6816 6916 6A16 6 16 6C16 6D16 GE16 6F16 7016 A D conversion interrupt control register 1010 0 7116 UARTO transmit interrupt control register 0 0 7216 UARTO receive interrupt control register 0 0 0 0 7316 transmit interrupt control register 0 7416 UART1 receive interrupt control register BEES NN 7516 Timer AO interrupt control register 7616 Timer A1 interrupt control register 7716 Timer 2 interrupt control register 22 0 Of 0 OF 7816 Timer interrupt control register 7916 Timer 4 interrupt control register 10 0 0 0 7 16 Timer BO interrupt control register 7 16 Timer 1 interrupt control register nny 7C16 Timer B2 interrupt control register 7 010 7D16 INTo interrupt control register 2 10 0 0 7E16 INT interrupt control register 7 16 INT2 interrupt control register 2 0 0 0 0 0 0 Notes 1 By writing dummy data to address 6016 the value 16 is set to the watchdog timer The dummy is not retained anywhere 2 The value FFF16 is set to the watchdog timer Refer to Chapter 9 WATCHDOG TIMER lnternal RAM area addresses 8016 to 27 16 in M37702M2BXXXFP
385. ress hold time BYTE L 1 o 1 1 1 1 9 J ns te a Port P1 data hold time BYTE L 50 ns 12 95 ns hE P14 50 ns tm t PortP2addressholdtime o Jl 9 n iE PortP2dataholdtime o Z 50 X ns 22 95 ts holdtime f 1 1 1 1 1 1 1 1 11 1 18 n thew R W hold time Ins Notes 1 For test conditions refer to Figure 18 4 1 x This is depending on f Xin For data formula refer to Table 18 4 1 Table 18 4 1 Bus timing data formula Note xay tapia Note Note 1X10 45 ta P2A ALE f XIN f XIN mee Note 50 110 12 famine Note EXN 1 1 TE 2 XXN 7 2 tn E P10 ES Mn tn E P2Q 2X f XIN 7 ipzx E P1Z Note 1X10 _ 40 ipzxE P22 Note Unit ns Note For the M37702E2LXXXGP and the M37702E4LXXXFP refer to section 19 5 4 Bus timing EPROM mode 18 24 7702 7703 Group User s Manual Memory expansion mode and microprocessor mode With no Wait lt Write gt f Xin 1 E Address output Ao A7 Address output 15 BYTE H Address Data output As Ds A15 D15 BYTE Data input Ds D15 BYTE L Address Data output 00 23 07 Data input Do D7 ALE output BHE output R W output Port Pi output i 4 8 tw L tw H tr te LOW VOLTAGE VERSION 18 4 Electrical charact
386. ress low order td POA E Address middle order Address high order e td P2A E ta AD Fig 17 1 1 Bus timing diagrams tsu P2D E Address middle order ta E P1Q Address high order Data low order gt lt la E P2O m tsu D When reading data When writing data M37702 s standard characteristics The others are the external memory s 7702 7703 Group User s Manual 17 5 APPLICATION 17 1 Memory expansion e wait Wait lt tv tz o O O 4 gt O E gt 10 11 12 13 16 MHz External clock input frequency f XIN Address decode time and address latch delay time are not considered Fig 17 1 2 Relationship between ta and f Xin 16 MHz version e No wait Wait e 2 42 Q 2 4 YW 10 11 External clock input frequency f XIN Fig 17 1 3 Relationship between and f Xin 16 MHz version 17 6 7702 7703 Group User s Manual APPLICATION 17 1 Memory expansion
387. ristics Vcc 2 7 5 5 V Vss 0 V Ta 40 to 85 C f Xw 8 MHz unless otherwise noted Symbol Parameter ena data outputdelaytime 7 800 laeso PortP5dataoutputdelaytime 22124130 twe pea Port P6 data output delay time 222124130 _ Port P7 data output delay time 8300 t output delay times 40 tyPoa e Port PO addressoutputdelaytime 1 50 X tae Pia Port P1 data output delay time BYTE L 1130 toxz E P1z Port P1 floating start delay time BYTE L 10 tae1a Port P1 address output delay time 1 50 tyPia ale Port P1 address output delay time t t f 1 40 O the pea PortP2dataoutputdelaytime 4190 tpxe p2z _ PortP2floatingstartdelaytime 10 laP e PortP2addressoutputdelaytime 150 thP2a aLE Port P2 address output delay time 21408004 taare ALE output delay time eee 4 twara ALE pulse width BHE output delay time 8 tarw R Woutputdelaytime Note For test conditions refer to Figure 18 4 1 This is the value depending on f Xin For data formula refer to Table 18 4 1 7702 7703 Group User s Manual Unit 18 23 LOW VOLTAGE VERSION 18 4 Electrical characteristics Switching characteristics Vcc 2 7 5 5 V Vss 0 V Ta 40 to 85 C f Xin 8 MHz unless otherwise noted th E PoA 50 ns thate rta Port P1 add
388. rnal interrupt from Timer B1 FFEO e Internal interrupt from Timer B2 FFE1 16 FFDF ie 6 Internal interrupt from UARTO FFDDie FFDCie FFDBie FFDAte Internal interrupt from UART1 FFD9 s FD8 e FFD 16 FFD616 Internal interrupt from A D converter Note The DBC interrupt Source is used exclusively for debugger control 7702 7703 Group User s Manual INTERRUPTS 4 2 Interrupt sources Table 4 2 2 lists occurrence factors of internal interrupt request which occur due to internal operation Table 4 2 2 Occurrence factors of internal interrupt request Interrupt Zero division interrupt BRK instruction interrupt Watchdog timer interrupt Timer Ai interrupt i O to 4 Timer Bi interrupt i 2 O to 2 UARTi receive interrupt i O transmit interrupt i O A D conversion interrupt Interrupt request occurrence factors Occurs when 0 is specified as the divisor for the DIV instruction Division instruction Refer to 7700 Family Software Manual Occurs when the BRK instruction is executed Refer to 7700 Family Software Manual Occurs when the most significant bit of the watchdog timer becomes 0 Refer to Chapter 9 WATCHDOG TIMER Differs according to the timer Ai s operating modes Refer to Chapter 5 TIMER A Differs according to the timer Bi s operating modes Refer to Chapter 6 TIMER B Occurs at serial data reception
389. rom I O devices 00000016 00007 16 00008016 Internal RAM area 00027 16 00 000 6 Internal ROM area OOFFFFie 01000016 Bank O16 Bank 116 02000016 0 0000 6 Indicates the memory allocaton of the internal areas FF000016 2 Indicates that nothing is allocated Note Viemory assignment of internal area varies according to the type of microcomputer This figure shows the case of the M37702M2BXXXFP Refer to Appendix 1 Memory assignment for other products SFR Special Function Register Fig 2 3 1 M37702 s access space 2 16 7702 7703 Group User s Manual CENTRAL PROCESSING UNIT CPU 2 3 Access space 2 3 1 Banks The access space is divided in units of 64 Kbytes This unit is called bank The high order 8 bits of address 24 bits indicate a bank which is specified by the program bank register PG or data bank register DT Each bank can be accessed efficiently by using an addressing mode that uses the data bank register DT If the program counter PC overflows at a bank boundary the contents of the program bank register PG is incremented by 1 If a borrow occurs in the program counter PC as a result of subtraction the contents of the program bank register PG is decremented by 1 Normally accordingly the user can program without concern for bank boundaries SFR Special Function Register internal RAM and internal ROM are assigned in bank
390. rrupt request Nothing is allocated Undefined Note Use the SEB or CLB instruction to set each interrupt control registers Fig 7 2 12 Structure of UARTi transmit interrupt contro and UARTI receive interrupt control registers 7 14 7702 7703 Group User s Manual 1 2 SERIAL I O 7 2 Block description Interrupt priority level select bits bits 0 to 2 These bits select the priority level of the UARTi transmit interrupt or UARTi receive interrupt When using UARTI transmit receive interrupt select priority levels 1 to 7 When the UARTI transmit receive interrupt request occurs its priority level is compared with the processor interrupt priority level IPL so that the requested interrupt is enabled only when its priority level is higher than the IPL However this applies when the interrupt disable flag 1 0 To disable the transmit receive interrupt set these bits to 0002 level 0 Interrupt request bit bit 3 The UARTi transmit interrupt request bit is set to 1 when data is transferred from the transmit buffer register to the UARTi transmit register The UARTI receive interrupt request bit is set to 1 when data is transferred from the receive register to the UARTi receive buffer register However when an overrun error occurs it does not change Each interrupt request bit is automatically cleared to 0 when its corresponding interrupt request is a
391. rsion UARTO and 1 transmit UARTO and 1 receive timers AO to A4 timers BO to B2 interrupt control registers Addresses 7016 to 7C16 Interrupt priority level select bits Level 0 Interrupt disabled Level 1 Low level Level 2 g Level 3 Level 4 Level 5 Level 6 Level 7 High level Interrupt request bit No interrupt request Interrupt request 1704 7 to 4 Nothing i is allocated Note Use the SEB or CLB instruction to set each interrupt control register b7 56 b5 b4 b3 b2 bi b0 INTo to INT2 interrupt control registers Addresses 7016 to 7F 6 Interrupt priority level select bits Level 0 Interrupt disabled Level 1 Low level Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 High level Polarity select bit 0 Set the interrupt request bit at H level for level sense and at falling edge for edge sense Set the interrupt request bit at L level for level sense and at rising edge for edge sense Interrupt request bit Note 1 E No interrupt request Interrupt request Level sense Edge sense select T Edge sense EXTR Level sense 7 7 6 Nothing is allocated Undefined Notes 1 The INTo to INTe interrupt request bits are invalid when selecting the level sense 2 Use the SEB or the CLB instruction to set the INTo to INT2 interrupt control registers Fig 4 3 2 Structure of interrupt control register 7702 7703 Group User s Manual 4 7 IN
392. s the error sum flag is set to 1 Accordingly the error sum flag informs the user whether any error has occurred or not Error flags such as the overrun error flag the framing error flag the parity error flag the error sum flag are cleared to 0 by reading the contents of the UARTi receive buffer register low order byte or clearing the receive enable bit to 0 When errors occur during reception initialize the error flags and the UARTi receive buffer register and then perform reception again When it is necessary to perform retransmission owing to an error which occurs in the receiver side set the UART transmit buffer register again and then starts transmission again The method of initializing the UARTI receive buffer register and that of setting the UARTi transmit buffer register again are described below 1 Method of initializing V ARTi receive buffer register Clear the receive enable bit to 0 reception disabled Set the receive enable bit to 1 again reception enabled 2 Method of setting UARTi transmit buffer register again Clear the serial mode select bits to 0002 serial ignored Set the serial I O mode select bits again Set the transmit enable bit to 1 transmission enabled and set the transmit data to the UARTI transmit buffer register 7702 7703 Group User s Manual 7 51 SERIAL I O 7 4 Clock asynchronous serial UART mode 7 4 8 Sleep m
393. s 4 to 7 refer to each operation mode s description b7 b6 b5 b4 b3 b2 bi 00 UARTO transmit receive control register 1 Address 3516 UART1 transmit receive control register 1 Address 3D16 x Bitnme Bitnme Functions At reset reset RW enable bit mE disabled ransmission enabled Transmit buffer empty flag 0 Data present in transmit buffer register 1 No data present in transmit buffer register Receive enable bit Reception disabled Reception enabled Receive complete flag 0 uffer register 1 Data present in receive buffer register 4 Overrun error flag Note 1 2 No overrun error 1 Overrun error detected 5 Framing error flag Notes 1 2 No framing error Valid in UART mode Framing error detected Parity error flag Notes 1 2 No parity error Valid in UART mode Parity error detected Error sum flag Notes 1 2 D No error Valid in UART mode Error detected Notes 1 Bits 7 to 4 are cleared to 0 when clearing the receive enable bit to O or when reading the low order byte of the UARTi receive buffer register addresses 3616 3E16 out 2 Bits 5 to 7 are ignored in the clock synchronous serial I O mode Fig 7 2 4 Structure of VARTI transmit receive control register 1 7702 7703 Group User s Manual 7 7 SERIAL I O 7 2 Block description 1 2 3 4 Transmit enable bit bit 0 By setting this b
394. s 5616 to is 0 or at its rising when bit 3 is 1 When using an external trigger set the port P5 and P6 direction registers bits which correspond to the TAiw pins for the input mode 67 06 b5 b2 bi 00 One shot start register Address 4216 Timer AO one shot start bit 1 Start outputting one shot pulse o wo valid when selecting internal 72 Ls ve Fig 5 5 4 Structure of one shot start register 7702 7703 Group User s Manual 5 35 TIMER A 5 5 One shot pulse mode 5 5 4 Operation in one shot pulse mode When the one shot pulse mode is selected with the operating mode select bits the TAiour pin outputs L level When the count start bit is set to 1 the counter is enabled for counting After that counting starts when a trigger is generated When the counter starts counting the TAiour pin outputs H level When the counter value becomes 000016 the output from the TAiour pin becomes L level Additionally the reload register s contents are reloaded and the counter stops counting there Simultaneously at the timer Ai interrupt request bit is set to 1 This interrupt request bit remains set to 1 until the interrupt request is accepted or the interrupt request bit is cleared to O by software Figure 5 5 5 shows an example of operation in the one shot pulse mode When a trigger is generated aft
395. s applied to pin VPP programming to the built in PROM becomes possible Input an address to address input pins and supply data to be programmed to data pins in 8 bit parallel In this condition when pin PGM is set to L level the data is programmed at the specified address input address into the built in PROM 3 Erase Possible only in EPROM version The contents of the built in PROM is erased by exposing the glass wiridow on top of the package to an ultraviolet light which has wave length of 2537 Angstrom The light must be 15 J cm or more Table 19 3 2 Built in PROM state in 1M mode Data I O Mode Read out 5 55 Output Output 5 Floating disable vm x xm wsv 5v Floating Program Vi ve 125 ev Input Program verify w 125V _ Output Program disable Floating X It may be VIL or ViH 7702 7703 Group User s Manual 19 9 PROM VERSION 19 3 1M mode 19 3 2 Programming algorithm of 1M mode Figure 19 3 3 shows the programming algorithm flow chart of 1M mode Set Vcc 6 V VPP 12 5 V and address to 1C000 e After applying a programming pulse of 0 2 ms check whether data can be read or not If the data cannot be read apply a programming pulse of 0 2 ms again Repeat the procedure which consists of applying a programming pulse of 0 2 ms and read check until the data can be read Additionally record the number of applied pulses x before
396. s in the same way as hardware reset 7702 7703 Group User s Manual 10 3 STOP MODE 10 2 Operation description 10 2 1 Termination by interrupt request occurrence When terminating Stop mode by interrupt request occurrence instructions are executed after a certain time measured by the watchdog timer has passed When an interrupt request occurs the oscillator starts oscillating Simultaneously supply of clock qu f2 to fs12 starts The watchdog timer starts counting owing to the oscillation start The watchdog timer counts fez When the watchdog timer s MSB becomes 0 supply of u starts At the same time the watchdog timer s count source returns to fa or fsi2 that is selected by the watchdog timer frequency select bit bit 0 at address 6116 The interrupt request which occurs in is accepted Table 10 2 2 lists the interrupts used to terminate Stop mode Table 10 2 2 Interrupts used to terminate Stop mode Interrupt Conditions for using each function to generate interrupt request INTi interrupt i O to 2 Timer Ai interrupt i O to 4 Enabled in event counter mode Timer Bi interrupt i 2 O to 2 UARTi transmit interrupt i 0 1 Enabled when selecting external clock UARTi receive interrupt i 0 1 Notes 1 Since the oscillator has stopped oscillating each function does not work unless they are operated under the above condition Also the A D converter does not work 2 Since the oscil
397. s the block diagram of the A D converter Registers relevant to the A D converter are described below f2 1 2 1 2 VREF e Resistor Vref AVss b ladder network Successive approximation register A D sweep pin select register gt A D control register A D register 0 e A D register 1 e d A _ 058 A D register 4 A D register 5 A D register 6 A D register 7 ANo AN CO AN4 ANs ANe AN7 ADtra C VIN Selector Fig 8 2 1 Block diagram of A D converter 7702 7703 Group User s Manual 8 3 A D CONVERTER 8 2 Block description 8 2 1 A D control register Figure 8 2 2 shows the structure of the A D control register The A D operation mode select bit selects the operation mode of the A D converter The other bits are described below 67 56 05 b4 b3 b2 bl A D control register Address 1 6 LINE 5 Analog input select bits Valid in one shot and repeat ANo selected Undefined RW modes Note 1 0 1 AN selected ANe selected ANs selected AN4 selected Undefined RW ANs selected ANe selected AN selecied Note 2 A D operation mode select bits 9453 RW 0 0 One shot mode 0 1 Repeat mode 10 Single sweep mode 1 1 Repeat sweep mode RW 5 Trigger select bit Internal tr
398. st RW Interrupt request Nothing is assigned Undefined Note Use the SEB or CLB instruction to set each interrupt control register 67 66 b5 04 b3 b2 bl b0 INTo to INT2 interrupt control registers Addresses 701 to 7F 6 WV O m Interrupt priority level select bits Level 0 Interrupt disabled Level 1 Low level Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 High level 3 Interrupt request bit Note 1 0 No interrupt request RW 1 Interrupt request Polarity select bit 0 Set the interrupt request bit at RW H level for level sense and at falling edge for edge sense Set the interrupt request bit at L level for level sense and at rising edge for edge sense v Level sense 7 6 Nothing is assigned Unde ned Notes 1 The INTo to INT interrupt request bits are invalid when selecting the level sense 2 Use the SEB or CLB instruction to set the INTo to INT2interrupt interrupt control registers 7702 7703 Group User s Manual 21 31 APPENDIX Appendix 4 Package outlines Appendix 4 Package outlines 80P6N A Plastic 8Opin 14 x 20mm body EIAJ Package Code JEDEC Code QFP80 P 1420 80 158 Aloy42 Scale 2 1 Dimension in Millimeters Symbol Nom pow 2 S co lt D ex 1 0 2 8 0 45 3 14 2 20 2 08 17 1 3 1 04 06 p cop om N O e Me
399. ster 0 Addresses 2016 D register 1 Addresses 2216 D register 2 Addresses 2416 D register 3 Addresses 2616 D register 4 Addresses 2816 D register 5 Addresses 2A 16 D register 6 Addresses 2C16 A D register 7 Addresses 2E16 A A A A A 67 06 05 b4 b3 b2 bi 00 A A 715 0 Reads A D conversion result Undefined 21 14 7702 7703 Group User s Manual UARTI transmit receive mode register 67 b6 b5 b4 b3 b2 bi b0 APPENDIX Appendix 3 Control registers UARTO transmit receive mode register Address 3016 UART1 transmit receive mode register Address 3816 Bitname Bitname Serial I O mode select bits Odd Even parity select bit Valid in UART mode when Functions 000 Serial I O disabled Clock synchronous serial I O T Not selected Not selected UART mode UART mode Transfer daia length 8 bits UART mode Transfer data length 9 bits Not selected 3 Internal External clock select bit Internal clock External clock Stop bit length select bit A One stop bit Valid in UART mode Note Two stop bits 0 Odd parity 1 Even parity parity enable bit is 1 Note P8 functions as a programmable I O port mode Transfer data length 7 bits Parity enable bit 0 Parity disabled RW Valid in UART mode Note 1 Parity enabled Sleep select bit Valid in UART mode Note 0 Sleep mode cleared ignore
400. ster when reception is completed 7 12 7702 7703 Group User s Manual SERIAL I O 7 2 Block description 7 2 6 UARTi baud rate register The UARTi baud rate register is an 8 bit timer exclusively used for UARTi to generate a transfer clock It has a reload register Assuming that a value set in the is n 001 to FFie the divides the count source frequency by n 1 In the clock synchronous serial I O mode the is valid when an internal clock is selected and a clock of which frequency is the BRGi output s frequency divided by 2 becomes the transfer clock In the UART mode the BRGi is always valid and a clock of which frequency is the BRGi output s frequency divided by 16 becomes the transfer clock The data which is written to the addresses 3116 and 3916 is written to both the timer register and the reload register whether transmission reception is stopped or in progress Accordingly writing to their addresses perform it while that is stopped Figure 7 2 10 shows the structure of the UARTi baud rate register BRGi Figure 7 2 11 shows the block diagram of transfer clock generating section UARTO baud rate register Address 31 16 UART1 baud rate register Address 3916 7 to 0 Can be set to 0016 to FF 6 Undefined WO Assuming that the set value n divides the co nt source frequency by n 1 Fig 7 2 10 Structure of UARTi baud rate register BRG
401. sult in The CPU registers and the SFR are not initialized in the above mentioned way Accordingly it is necessary that you must perform the initial setting for these all by software The processor interrupt priority level IPL retains 7 of the watchdog timer interrupt priority level and that is not initialized Consequently all interrupt requests are not accepted When rewriting the IPL by software store once the 15 bit immediate value to the stack area and next return that 16 bit immediate value to all bits of the processor status register PS We recommend software reset in order to initialize the microcomputer for software runaway 21 54 7702 7703 Group User s Manual APPENDIX Appendix 7 Hexadecimal instruction code table Appendix 7 Hexadecimal instruction code table INSTRUCTION CODE TABLE 1 Hexadecimal ORA SEB ORA ASL ORA ORA ASL SEB ORA ASL ORA ASR DIRb ADIR DIR AL DIR A IMM A ABS b 5 ABS AABL OR ORA ORA CLB ORA ASL ORA ORA DEC CLB ORA ASL ORA CLC TAS D DIR b A DIR X DIR X AL DIR AABSY ABS b A ABS X ABS X A ABL X JSR BBS AND ROL AND AND ROL BBS AND ROL AND PLP PLD ABS j A DIRX ABL DIR b R A DIR DIR A IMM A ABS b R AABS ABS A ABL AND AND AND BBC AND ROL AND AND INC BBC AND ROL AND SEC TSA MORTON Y DIR b RIA DIR X DIR X AABSY ABS b RIA ABS X ABS X
402. sw Nf Unit ns Fig 18 6 4 Timing diagram on minimum model 18 238 7702 7703 Group User s Manual LOW VOLTAGE VERSION 18 6 Application 18 6 3 Memory expansion example on medium model A Figure 18 6 5 shows a memory expansion example on the medium model A of mask ROM version and PROM version Figure 18 6 6 shows the corresponding timing diagram M37702M2L E2LXXXGP M5M51008AFP 10VLL Memory map 00000016 00008016 Internal RAM 00027 F16 area Not used 00 00016 Internal ROM area OOFFFF16 Not used 02000016 External RAM area O3FFFFie M5M51008AFP 7 Circuit condition no Wait Vcc 2 7 3 3 V Use the elements of which propagation delay time is within 50 ns Fig 18 6 5 Memory expansion example on medium model A 7702 7703 Group User s Manual 18 39 LOW VOLTAGE VERSION 18 6 Application lt When reading gt 210 min 1 50 min 10 Dome 74 A lt gt 95 min AC573 tPHL 4 16 A17 S2 N E lt 573 External memory 7 mmm Co lt gt P tsu P1D P2D E gt 80 ta OE ta 51 lt When writing gt 210 min E OE S1 N 50 min gt tsu D gt 40 gt 50 min 130 lt gt lt gt 573 tPHL gt
403. t P64 INT2 lt gt amp lt gt 6 gt P62 INTo lt gt 8 P60 TA4ouT P57 TASIN lt gt P5e TA3oUT P55 TA2IN P54 TA20UT P53 TA1IN OUT lt gt P51 TAOIN lt gt P59 TAQouT P47 lt gt 4 P45 lt gt P44 lt gt Phua 42 1 P41 RDY gt Vss lt gt P73 AN3 lt gt P74 AN4 9 4 P75 AN5 e P76 ANe e 8 lt gt 7 1 lt 4 7 gt 2 lt gt P7z ANzADTRG e 2 4 P8e RxDo e 2 P83 TxDo e N Q IAT IR TIARA you aA jar Jory jan G o POLIO ID INP PO POP IA Joy IN G9 I PTO lt gv N NI NO T N UJ gt lt gt gt lt lt 9 QIK S 78484002 Ot s s lt s lt lt ee CD Do Do Do 84 1 1 P85 CLK1 P86 RxD1 P8z TxD1 POo Ao P0O1 A1 2 2 P03 A3 P04 A4 5 5 PO7 A7
404. t H level from port P4s Output L level from port P44 Transmit Receive 24 bit data by using UARTO Output H level from port P44 Figure 17 1 22 shows serial transfer timing between M37702 and M66010FP 7702 7703 Group User s Manual APPLICATION 17 1 Memory expansion M37702 M66010FP X TxDo ave pam E al gt RxDo gt gt CLKo ow E VN gt P44 yee gt L NVNN e 45 XII TAE di RTSo ev gt Ao A7 wt Expanded port 2 gt As Ds E x gt A15 D15 gt E A16 Do A23 D7 n b 2 ALE lt P B gt Circuit condition used in clock synchronous serial I O mode Internal clock selected Frequency of transfer clock 28 1 1 5625 MHz 25 MHz Fig 17 1 21 Example of port expansion circuit using M60010FP 7702 7703 Group User s Manual 17 27 APPLICATION 17 1 Memory expansion uonejedo pue s 4401099 N ae eu S Z0ZZEN adj 1ndino urejp uedo suod pepuedx3 x X veld p Q lt A uod d d LOQ HO uod pepuedxy
405. t Error flag reading Data A error flag Data B reading No error When checking this error flag by software the microcomputer judges errors nothing because errors do not have occurred at data A receiving When receiving the data B the data B is written to the UARTI receive buffer register and the data A is cleard and the overrun error flag becomes 1 simultaneously The UARTi receive interrupt request bit does not change When reading the receive butter register by software the data is read and the overrun error flag becomes 0 simultaneously Accordingly the overrun error cannot may be detected and it is possible that the data B is managed as the data A Fig 7 4 13 Case of overrun error cannot be detect using clock asynchronous seriai I O mode 7702 7703 Group User s Manual 7 53 SERIAL I O 7 4 Clock asynchronous serial UART mode MEMORANDUM 7 54 7702 7703 Group User s Manual CHAP TIER A D CONVERTER 8 1 Overview 8 2 Block description 8 3 A D conversion method 8 4 Absolute accuracy and differential non linearity error 8 5 One shot mode 8 6 Repeat mode 8 7 Single sweep mode 8 8 Repeat sweep mode 8 9 Precautions when using A D converter A D CONVERTER 8 1 Overview This chapter describes the A D converter The 7702 Group has a built in 8 bit A D converter The A D converter performs successive approximation conversion The 7702 Group has the 8
406. t gt 65 40 gt P24 P82 RxD 04 gt 66 39 lt gt P25 P81 CLKo lt gt 38 lt gt P26 P80 C TSo RTSo lt gt 68 37 P27 Vcc 69 36 P30 AVcc 35 gt VREF 34 4 gt P32 AVss 72 33 4 is M37702M2BXXXFP P77 AN7 ADTRG si E P76 ANe 39 XoUT P75 AN5 gt 29 4 XIN 28 4 P74 AN4 P73 AN3 78 P72 AN2 gt 79 P71 AN1 lt gt go O 70 4 P67 TB2IN 66 11 P65 TBOIN m P43 gt P42 0 1 lt p gt P64 INT2 P63 INT1 P62 INTo P61 TA4IN P60 TA4out lt P57 TASIN 5 P56 TA3 out 4 gt P55 TA2IN 4 5 P54 TA20UT lt gt P53 TA1IN P5 2 TA1out lt P51 TAOIN s P5o TAOour lt gt zi P47 P46 P45 P44 Memory expansion Microprocessor mode P 83 TxDo P82 RxDo 66 P81 C lt L67 8 TSo R TS lt gt 68 Vcc 69 VREF AVss Vss P77 AN7 ADrTRG P 7e A 75 P 75 AN5 lt gt P74 AN4 P 73 ANS 7 4 gt P71 AN1 4 gt P84CTSI RTSI P85 C P8e RxDt1 P87 TxD1 ge E18 2 O P7o ANo lt gt P67 TB2N v P6e TB1IN M3 02M2BXXXFP LIL ele Ll ed bed ell ede a ns Up s SEEES282 222 22
407. t lt gt POA lt gt P03 A3 gt zu PO4 A4 lt gt P05 A5 N N gt P06 Ac TI T lt gt P07 A7 lt gt 10 Ae gt lt gt lt lt gt 11 09 CAsD S lt gt lt lt gt P12 A10 D10 gt gt lt lt gt P13 A11 D11 T lt gt 14 2 012 Y U lt gt Pis Ais Dia C A132 lt gt Pie AuDi4 CAD lt gt Piz Ais Dis C 152 C lt gt p2o A16 Do C Do lt gt P21 A17 D1 CDi gt CDz gt P27 Az23 D7 lt gt 8 C De gt P2 A22 De 8 CDs gt P25 A21 Ds5 lt gt CD4 gt P24 A20 D4 lt gt CDs 2 P23 A19 Ds 8 gt P22 A18 D2 lt 5 516 gle o x Connect an oscillating circuit Outline 80P6S A C D EPROM pins Outline 80P6D A Fig 19 3 2 Pin connections in 1M mode 2 19 8 7702 7703 Group User s Manual PROM VERSION 19 3 1M mode 19 3 1 Read Program Erase Table 19 3 2 lists the built in PROM state in 1M mode and each mode is described bellow 1 Read When pins and OE are set to L level and an address is input to address input pins the contents of the built in PROM can be output from data I O pins and read When pins and OE are set to H level data I O pins enter the floating state 2 Program Write When pin CE is set to L level and pin OE is set to H level and VPP level i
408. t I O port with the same function as Memory expansion mode P7o P77 port P7 Port P7 is an 8 bit I O port with the same function as PO These pins can be programmed as input pins for P80 P87 port P8 Port P8 is an 8 bit I O port with the same function as PO These pins can be programmed as pins for serial P4o functions as the HOLD input pin P4 as the RDY A D converter x The 7703 Group does not have the P4s P4e P60 P61 P6e P67 7 76 P84 and P8s pins 1 8 7702 7703 Group User s Manual DESCRIPTION 1 3 Pin description 1 3 1 Example for processing unused pins Examples for processing unused pins are described below These descriptions are just examples The user shall modify them according to the user s actual application and test them 1 In single chip mode Table 1 3 4 Example for processing unused pins in single chip mode Pin name Example of processing Ports PO to P8 Set for input mode and connect these pins to Vcc or Vss via a resistor or set for output mode and leave these pins open Notes 1 3 E Leave it open Xout Note 2 Connect this pin to Vcc AVss Vrer BYTE Connect these pins to Vss Notes 1 When setting these ports to the output mode and leave them open they remain set to the input mode until they are switched to the output mode by software after reset While ports remain set to the input mode consequently voltage levels of pins are unstable and a p
409. t is inserted when accessing external area 1 No software Wait is inserted when accessing external area The microcomputer is reset by writing 1 to this bit The value is 0 at reading b5 b4 00 7 cycles of 9 01 4 cycles of ne 2 cycles of Not selected Fix this bit to 0 o RW Clock 1 output select bit 0 Clock 6 output disabled RW Note 2 P42 functions as a programmable I O port 1 Clock 1 output enabled P42 functions as a clock 6 out put pin Notes 1 While supplying the Vcc level to the CNVss pin this bit becomes 1 after a reset Fixed to 1 2 This bit is ignored in the microprocessor mode It may be either O or 1 Interrupt priority detection time select bits Bits 0 to 6 are not used for setting of clock 6 1 output Fig 12 1 4 Structure of processor mode register 7702 7703 Group User s Manual 12 7 CONNECTION WITH EXTERNAL DEVICES 12 1 Signals required for accessing external devices 12 1 2 Operation of bus interface unit BIU Figures 12 1 5 and 12 1 6 show the examples of operating waveforms of the signals input and output to from externals when accessing external devices The following explains these waveforms compared with the basic operating waveform refer to section 2 2 3 Operation of bus interface unit BIU 1 When fetching instructions into instruction queue buffer 2 12 8 W
410. t select bit 0 Clock 1 output disabled RW Note 2 P42 functions as a programmable I O port 1 Clock 1 output enabled P42 functions as a clock out put pin Notes 1 While supplying the Vcc level to the CNVss pin this bit becomes 1 after a reset Fixed to 1 2 This bit is ignored in the microprocessor mode It may be either O or 1 select bits 7702 7703 Group User s Manual 21 29 APPENDIX Appendix 3 Control registers Watchdog timer register b7 bO PL EEL EEE Watchdog timer register Address 6016 7 to O Initializes the watchdog timer Undefined When a dummy data is written to this register the watchdog timer s value is initialized to FFF16 Dummy data 0016 to FF 16 Watchdog timer frequency select register 67 b6 b5 b4 b3 b2 bi b0 Watchdog timer frequency select register Address 6116 701 to 1 7 to 1 Nothing i is assigned 21 30 7702 7703 Group User s Manual APPENDIX Appendix 3 Control registers Interrupt control register b7 b6 b5 b4 b3 b2 bi 50 A D conversion UARTO and 1 transmit UARTO and 1 receive timers AO to A4 timers BO to B2 interrupt control registers Addresses 7016 to 7C16 Interrupt priority level select bits Level 0 Interrupt disabled Level 1 Low level Level 2 Level 3 RW Level 4 Level 5 Level 6 Level 7 High level RW Interrupt request bit No interrupt reque
411. ta bus bus control signal External data bus width 8 bits BYTE gt P84 CTS1 RTS1 P86 RxD1 P87 TxD1 gt 85 gt 40 lt gt Q P8o CTSo RTSo lt gt 68 37 lt gt Vcc 69 36 l AVcc 35 gt VREF gt 71 34 AVss 33 Vss P77 AN7 ADTRG 474 P7e AN6 475 P75 AN5 lt gt 7e P74 AN4 7 P73 AN3 178 P72 AN2 lt gt 79 P71 AN1 lt gt 4 lt gt c P42 0 1 8 RDY gt R P63 INT1 o 7 lt gt _ P67 TB2IN lt gt gt P64 INT2 P62 INTo lt gt P61 TA4IN lt gt Peo TA4ouT lt gt 57 lt gt P55 TA2IN P54 TA20UT lt gt P53 TA1IN lt gt P52 TA1ouT lt gt P51 TAOIN la P5o TAOoUT P66 TB1IN o 56 P65 TBOIN gt 20 04 21 05 22 06 23 07 RW BHE ALE HLDA Vss XOUT XIN RESET CNVss BYTE HOLD As 1in microprocessor mode External address bus external data bus bus control signal Fig 12 1 1 Pin configuration in memory expansion and microprocessor modes top view 7702 7703 Group User s Manual 12 3 CONNECTION WITH EXTERNAL DEVICES 12 1 Signals required for accessing external devices Table 12 1 1 Functions of pins PO to P4 and E pin in memory expansion and microprocessor modes 8 bits BYTE
412. taken into the most significant bit of the UARTi receive register synchronously with the rising of the clock The contents of the UARTi receive register are shifted by 1 bit to the right Steps and Q are repeated at each rising of the transfer clock When 1 byte data is prepared in the UARTi receive register the contents of this register are transferred to the UARTi receive buffer register Simultaneously with step the receive complete flag is set to 1 and the UARTi receive interrupt request occurs and its interrupt request bit is set to 1 The receive complete flag is cleared to 0 when the low order byte of the UARTi receive buffer register is read out Figure 7 3 10 shows the receive operation and Figure 7 3 11 shows an example of receive timing when selecting an external clock 7702 7703 Group User s Manual 7 29 SERIAL I O 7 3 Clock synchronous serial mode Transmitter side Receiver side Fig 7 3 9 Connection example receive register o b7 00 receive buffer register Fig 7 3 10 Receive operation 7 30 7702 7703 Group User s Manual SERIAL I O 7 3 Clock synchronous serial I O mode Receive enable bit 4 Transmit enable bit 0 Dummy data is set to UARTi transmit buffer register Transmit buffer T empty flag UARTi transmit register UARTi transmit buffer register RTSi Received
413. te functions 5 14 7702 7703 Group User s Manual TIMER A 5 3 Timer mode 5 3 4 Select function The following describes the selective gate and pulse output functions 1 Gate function The gate function is selected by setting the gate function select bits bits 4 and at addresses 5616 to 5A16 to 102 or 112 The gate function makes it possible to start or stop counting depending on the TAiw pin s input signal Table 5 3 3 lists the count valid levels Figure 5 3 5 shows an example of operation selecting the gate function When selecting the gate function set the port P5 and port P6 direction registers bits which correspond to the pin for the input mode Additionally make sure that the pin s input signal has a pulse width equal to or more than two cycles of the count source Table 5 3 3 Count valid levels Gate function select bits Count valid level Duration when counter counts gt 1 0 While TAIN input signal is L level 1 While TAilN pin s input signal is H level Note The counter does not count while the pin s input signal is not at the count valid level 7702 7703 Group User s Manual 5 15 TIMER A 5 3 Timer mode n Reload register s contents D Starts counting Stops counting Counter contents Hex Set to 1 by software Time Count start bit i Count valid TAiiN pin s level fN input signal
414. te process Package 80 pin plastic molded QFP Notes 1 All of the 7702 Group microcomputers are the same except for the package type memory type memory size and electric characteristics 2 For the low voltage version refer to Chapter 18 LOW VOLTAGE VERSION 7702 7703 Group User s Manual 1 3 DESCRIPTION 1 2 Pin configuration 1 2 Pin configuration Figure 1 2 1 shows the M37702M2BXXXFP pin configuration Figure 1 2 2 shows the M37702M2BXXXHP pin configuration Note For the low voltage version of the 7702 Group refer to Chapter 18 LOW VOLTAGE VERSION 7703 Group Refer to Chapter 20 7703 GROUP 7 P67 TB2IN lt gt P66 TB1IN lt 65 lt gt P64 INT2 lt gt P63 INT1 lt gt 6 P62 INTo lt gt P61 TAIN lt 8 P60 TA4out lt gt 9 P57 TA3IN lt gt P56 TA3ouT lt gt P55 TA2IN lt 54 200 lt gt P53 TA1IN lt gt P52 TA1OUT lt P51 TAOIN lt P5o TAOOUT lt gt P47 lt gt 46 lt gt P45 P44 lt gt po 9 P42 01 lt P41 RDY lt gt pg lt x WO OR 9 24 Z Z xL te ta te S E gt gt S do d gt lt gt lt gt Qn n n n P i O OO N J N N UJ gt lt gt lt gt TI U B BYTE gt E B B EN B P30 R W P27 A23 D7 lt gt 9 Vss P33 HLDA
415. ted satisfy conditions to with the following precondition satisfied lt Precondition gt The CLKi pin s input is H level Note When an internal clock is selected above precondition is ignored lt Reception conditions gt Reception is enabled receive enable bit 1 Transmission is enabled transmit enable bit 1 Dummy data is present in the transmit buffer register transmit buffer empty flag 0 When using interrupts it is necessary to set the relevant register to enable interrupts For details refer to Chapter 4 INTERRUPTS Figure 7 3 8 shows processing after reception s completion 7702 7703 Group User s Manual 7 25 SERIAL I O 7 3 Clock synchronous serial I O mode UARTO transmit receive mode register Address 3046 UART1 transmit receive mode register Address 3846 Clock synchronous serial I O mode Internal External clock select bit 0 Internal clock 1 External clock w x lt may be 0 or 1 UARTO transmit receive control register 0 Address 3416 UN UART1 transmit receive control register 0 Address 3 16 BRG count source select bits b1 bO 00 f2 01 f16 10 164 11 1512 CTS RTS select bit 0 CTS function selected 1 RTS function selected UARTO baud rate register BRGO Address 31 6 UART1 baud rate register BRG1 Address 39 6 b7 bO S 2 DO Set to 0016 to F
416. ted during pulse output 5 47 7702 7703 Group User s Manual TIMER A 5 6 Pulse width modulation PWM mode Precautions when operating in PWM mode 1 If the count start bit is cleared to 0 while outputting PWM pulses the counter stops counting When the TAiour pin was outputting H level at that time the output level becomes L and the timer Ai interrupt request bit is set to 1 When the TAiour pin was outputting L level the output level does not change and the timer Ai interrupt request does not occur 2 When setting the timer s operating mode in one of the followings the timer Ai interrupt request bit is set to 1 e When the PWM mode is selected after a reset e When the operating mode is switched from the timer mode to PWM mode e When the operating mode is switched from the event counter mode to the PWM mode Therefore when using the timer Ai interrupt interrupt request bit be sure to clear the timer Ai interrupt request bit to 0 after the above setting 5 48 7702 7703 Group User s Manual CHAPITER 6 TIMER B 6 1 Overview 6 2 Block description 5 3 Timer mode 6 4 Event counter mode 6 5 Pulse period pulse width mea surement mode TIMER B 6 1 Overview 6 2 Block description Timer B consists of three counters Timers BO to B2 each equipped with a 16 bit reload function Timers BO to B2 have identical functions and operate independently of each othe
417. tep Figure 8 6 2 shows the conversion operation in ihe repeat mode Trigger occur Conversion result Convert input voltage from A D register ANi pin Fig 8 6 2 Conversion operation in repeat mode 7702 7703 Group User s Manual 8 19 A D CONVERTER 8 7 Single sweep mode 8 7 Single sweep mode In the single sweep mode the operation for the input voltage from multiple selected analog input pins is performed one at a time The A D converter is operated in ascending sequence from the ANo pin The A D conversion interrupt request occurs when the operation for all selected input pins are completed 8 7 1 Settings for single sweep mode Figure 8 7 1 shows an initial setting example of single sweep mode When using an interrupt it is necessary to set the relevant registers to enable the interrupt Refer to Chapter 4 INTERRUPTS for more information 8 20 7702 7703 Group User s Manual A D CONVERTER 8 7 Single sweep mode A D control register and A D sweep pin select register b7 bO b7 bo fo 1 0 x x X A D control register address 1E 6 BEEN A D sweep pin select register address 1F 16 E E pin select bits 0 0 ANo AN 2 pins Single sweep mode Trigger select bit 0 1 ANo ANs 4 pins 0 Internal trigger 1 0 ANo ANs 6 pins 1 External trigger 1 1 ANo AN 8 pins A D conversion start bit 0 Stop A D conversion A D conversion frequenc
418. ter that make a branch to the program address in the external ROM area Contents of the instruction queue buffer is initialized by a branch instruction 7702 7703 Group User s Manual APPENDIX Appendix 6 Q amp A SFR Is there any SFR for which instructions that can be used to set registers or bits are limited 1 Use the STA or LDM instruction to set the registers or the bits listed below Do not use read modify write instructions i e CLB SEB INC DEC ASL ASR LSR ROL and ROR UARTO baud rate register address 3116 UART1 baud rate register address 39 6 UARTO transmit buffer register addresses 3316 3216 UART1 transmit buffer register addresses 3B e 3 6 Timer A4 two phase pulse signal processing select bit bit 7 at address 4416 Timer two phase pulse signal processing select bit bit 6 at address 44 6 Timer A2 two phase pulse signal processing select bit bit 5 at address 4416 2 Use the SEB and CLB instructions to set interrupt control registers addresses 7 to 706 7702 7703 Group User s Manual 21 53 APPENDIX Appendix 6 Q amp A Watchdog timer When detecting the software runaway by the watchdog timer if not software reset but setting the same value as the contents of the reset bector address to the watchdog timer interrupt bector address is processed how does it result in When branching the reset branch address within the watchdog timer interrupt routine how does it re
419. ternal external clock select bit bit at addresses 3016 3816 When an internal clock is selected the clock selected with the BRG count source select bits bits 0 and 1 at addresses 34 e 3C e becomes the BRGi s count source When an external clock is selected the clock input to the CLKi pin becomes the BRGi s count source Tables 7 4 3 and 7 4 4 are list the setting examples of transfer rate Set the same transfer rate between the transmitter and the receiver Table 7 4 3 Setting examples of transfer rate 1 Transfer Xin 8 MHz 16 MHz Xn 8MHZ 97 rate bps BRGi count BRGi E p time count BRGi Actual time 75 12069 7512 25099 752 110 maed nof 110 04 1345 fe 57 99 134809 115 73 134 70 150 51839 154 103 67 150 24 300 25 19 30048 f 300 48 600 12 0Cw 5006 25 19 600 96 1200 25 99 120192 51 33 1201 92 2400 12 0 a 2403 85 25 TIT 2403 85 4800 Lp 8 _ 4807 69 9600 95 09 961539 51 33w 9615 39 19200 ios imr 25 1944 19230 77 31250 h M7 er 15 31250 00 N 09 O 7 36 7702 7703 Group User s Manual SERIAL I O 7 4 Clock asynchronous serial I O UART mode Table 7 4 4 Setting examples of transfer rate 2 Transfer f Xin 24 576 MHz
420. terrupts set these bits to level 1 7 When disabling interrupts set these bits to level 0 p Setting port P6 direction register b7 00 Port P6 direction register Address 1016 TBiwpin Clear the corresponding bit to 0 V TB2iN pin J h Setting count start bit to 1 b7 b0 Count start register Address 4016 Timer B0 count start bit Count starts Timer B1 count start bit Timer B2 count start bit 4 Note The timer Bi overflow flag is a read only bit This bit is undefined after reset This bit is cleared to 0 by writing to the timer mode register with the count start bit 1 Fig 6 5 2 Initial setting example for registers relevant to pulse period pulse width measurement mode 6 22 7702 7703 Group User s Manual TIMER B 6 5 Pulse period pulse width measurement mode 6 5 2 Count source In the pulse period pulse width measurement mode the count source select bits bits 6 and 7 at addresses 5Bie to select the count source Table 6 5 2 lists the count source frequency Table 6 5 2 Count source frequency b7 Count source Count source Count source frequency select bits 8 MHz 16 MHz 25 MHz D O 7702 7703 Group User s Manual 6 23 TIMER B 6 5 Pulse period pulse width measurement mode 6 5 3 Operation in pulse period pulse width measurement mode When
421. the case of selecting the CTS function transmission starts when the CTSi pin s input level is L Fig 7 4 3 Initial setting example for relevant registers when transmitting 7702 7703 Group User s Manual 7 41 SERIAL I O 7 4 Clock asynchronous serial UART mode When not using interrupts When using interrupts The UARTi transmit interrupt request occurs when the transmit buffer register becomes empty Checking state of UARTi transmit buffer register B UARTO transmit receive control register 1 Address 3516 UART1 transmit receive control register 1 Address 3D16 UARTI transmit interrupt b7 bO BENE NN E Transmit buffer empty flag 0 Data present in transmit buffer register 1 No data present in transmit buffer register Writing of next transmit data is possible This figure shows the bits and registers Writing of next transmit data required for processing Hefer to Figures 7 4 6 and 7 4 7 about the change of flag state and the occurrence timing of an interrupt request UARTO transmit buffer register Addresses 3316 3216 UART1 transmit buffer register Addresses 3B16 3A16 b15 b8 b7 00 Set transmit data here J Fig 7 4 4 Writing data after start of transmission 7 42 7702 7703 Group User s Manual SERIAL I O 7 4 Clock asynchronous serial I O UART mode When using interrupts The transmit interrupt request occurs w
422. the contents of ihe Index register X to the index 1 r amp glater Y Transmite the contents of the index register Y to the accu 88 mulator Tranamite the contents ol ihe index register Y to the accu mulato B Tranamits ihe contents of the Index regisier Y to index E register X w __ the internal clock Exchanges the contents of the accumulator and the con tents of the accumulator B 21 68 7702 7703 Group User s Manual APPENDIX Appendix 8 Machine instructions T DIA ILIDIR eee ABSX ABSY ABL ABL LLABS ABSX STK REL ed pur RID REI in n o n prn SEE HH ET EEE TH ETT Tt TT ETT TT aT LT TT IMEEM BEEEBH CREEL D BE LETT TTT TTT eff B EH 5059695 Hn LH EHE LOL ees eemper cepe aidan ba ME ete et BD 83 a TUTTE THIS in Hl pua ERE m u 7702 7703 Group User s Manual 21 69 APPENDIX Appendix 8 Machine instructions Symbols in machine instructions table 21 70 7702 7703 Group User s Manual implied addressing mode z Exclusive OR IM M Immediate addressing mode Nagation Accumuiator addressing mode Movement to the arrow direction DIA Direct addrassing mods Acc Accumulator DIA b Direct bit addressi
423. the count start bit is set to 1 the counter starts counting of the count source The counter value is transferred to the reload register when an valid edge of the measurement pulse is detected Refer to section 1 Pulse period pulse width measurement 3 The counter value is cleared to 000015 after the transfer and the counter continues counting The timer Bi interrupt request bit is set to 1 when the counter value is cleared to 000015 in Note The interrupt request bit remains set to 1 until the interrupt request is accepted or the interrupt request bit is cleared to O by software The timer repeats operations to above Note The timer Bi interrupt request does not occur when the first valid edge is input after the timer starts counting 1 Pulse period pulse width measurement The measurement mode select bits bits 2 and 3 at addresses 5Bie to 5D e specify whether the pulse period of an external signal is measured or its pulse width is done Table 6 5 3 lists the relationship between the measurement mode select bits and the pulse period pulse width measurements Make sure that the measurement pulse interval from the falling to the rising and from the rising to the falling are two cycles of the count source or more Additionally use software to identify whether the measurement result indicates the H level or the L level width Table 6 5 3 Relationship between measure
424. the data has been read Apply x pulses 0 2 X x ms described as additional programming pulses When this procedure to is completed increment the address and repeat the above procedure until the last address is reached After programming to the last address read data when Vcc VPP 5 V or Vcc VPP 5 5 V x This applies to the M37702b2BFS Refer to Table 19 1 1 about each write address of other products ADDR FIRST LOCATION Vcc 6 0 V VPP 12 5 V PROGRAM ONE PULSE OF 0 2 ms DEVICE FAILED PROGRAM PULSE OF 0 2 X X ms DURATIO INCREMENT ADDR LAST ADDR YES Vcc VPP 5 0 V VERIFY ALL BYTE PASS DEVICE PASSED 4 5 V lt Vcc VPP lt 5 5 V Fig 19 3 3 Programming algorithm flow chart of 1M mode 19 10 7702 7703 Group User s Manual PROM VERSION 19 3 1M mode 19 3 3 Electrical characteristics of programming algorithm in 1M mode AC electrical characteristics Ta 25 5 C Vcc 6 V 0 25 V VPP 12 5 0 3 V unless otherwise noted foe _ Data mWmssmod ms 3 0 Data hoa 2 dey me atere fo fw tAS tOES tDS tAH tDH tDFP 5 tVPS tPW tOPW tCES tOE Address hold time Vcc Vec setup time o time Westm aoa FH pulse wa arm ceseuptime 0 Data delay time after OE 0 Programming timing diagram VIH Address VIL ViH VOH Dat
425. the followings the timer Ai interrupt request bit is set to 4 When the one shot pulse mode is selected after a reset When the operating mode is switched from the timer mode to the one shot pulse mode When the operating mode is switched from the event counter mode to the one shot pulse mode Therefore when using the timer Ai interrupt interrupt request bit be sure to clear the timer Ai interrupt request bit to O after above setting 4 Do not set 000015 to the timer Ai register 5 38 7702 7703 Group User s Manual TIMER A 5 6 Pulse width modulation PWM mode 5 6 Pulse width modulation PWM mode In this mode the timer continuously outputs pulses which have an arbitrary width Refer to Table 5 6 1 Figure 5 6 1 shows the structures of the timer Ai mode register and timer Ai register in the PWM mode Table 5 6 1 Specifications of PWM mode Item Specifications Count source f2 f16 fe4 or f512 Count operation Down count operating as an 8 bit or 16 bit pulse width modulator Reload register s contents are reloaded at rising of PWM pulse and counting continues A trigger generated during counting does not affect the counting PMW period H level width 16 bit pulse width modulator Period E s H level width s n Timer Ai register setting value lt 8 bit pulse width modulator gt 1 28 1 Period E 5 s H level width 1 fi m Timer
426. tically executed when an interrupt request is accepted Set the start address of this routine into the interrupt vector table LSB first Means a transfer data format of Serial l O LSB is transferred Overflow A state where the up count resultant is greater than the counter Under flow Power saving Means reducing a power dissipation by Stop mode Wait mode or Stop mode Read modify write An instruction that reads the memory contents modifies them instruction and writes back to the same address Relevant instructions are the ASL CLB DEC INC LSR ROL ROR SEB instructions Signal required for access generic name for bus control address bus and data bus signals control to external device signal Stop mode A state where the oscillation circuit halts and the program execution Wait mode is stopped By executing the STP instruction the microcomputer enters Stop mode Synchronizing clock Means a transfer clock of the clock synchronous serial I O 2 7702 7703 Group User s Manual GLOSSARY Term UART Under flow Up count Wait mode Meaning Relevant term Clock asynchronous serial I O When used to designate the name Clock of a functional block this term also means the serial I O which synchronous can be switched to the cock synchronous serial I O serial I O A state where the down count resultant is greater than the counter Overflow resolution Down count Means increasing by 1 and cou
427. timer s event counter mode In hardware input interrupt signals to the TAilN pins or TBIIN pins In software set the timer s operating mode to the event counter mode and a value 000046 into the timer register to the effective edge The timer s interrupt request occurs when an interrupt signal selected effective edge is input 7702 7703 Group User s Manual 21 49 APPENDIX Appendix 6 Q amp A Serial I O UART mode In the case selecting the CTS function in UART clock asynchronous serial I O mode when the transmitting side check the CTS input level It is check near the middle of the stop bit when two stop bits are selected the second stop bit Input level to CTSi pin is checked near here Transmit data Transmit data n 2 n 2 n 1 bit length 21 50 7702 7703 Group User s Manual APPENDIX Appendix 6 Q amp Hold function When L level is input to the HOLD pin how long is the bus actually opened The bus is opened after 50 ns at maximum has passed from the rising edge of next clock when the HLDA pin output becomes L level Clock 0 LJ LJ LI LJ HOLD HLDA Term where bus is open lexz HOLD PZ Maximum 50 ns Note The 7703 Group does fot have the HLDA pin 7702 7703 Group User s Manual 21 51 APPENDIX Appendix 6 Q amp A Processor mode If the processor mode is switched as described below by using the processor mode bits bits 1
428. ting data to the port register of a programmable I O port set to input mode the data is only written into the port latch and is not output to externals The pin retains floating 3 4 7702 7703 Group User s Manual INPUT OUTPUT PINS 3 1 Programmable I O ports b7 b6 b5 b4 b3 b2 bl 50 Port Pi register i 0 8 Addresses 216 316 616 716 A16 Bie E16 F16 1216 Port Pio Data is input output to from a pin by Undefined R W reading writing from to the corres eire 1 level 6 Note Bits 7 to 4 of the port register cannot be written they may be either 0 or 1 and are fixed to 0 at reading Fig 3 1 3 Port Pi i 0 to 8 register structure 7702 7703 Group User s Manual 3 5 INPUT OUTPUT PINS 3 1 Programmable I O ports Figures 3 1 4 and 3 1 5 show the port peripheral circuits Inside dotted line not included Ports POo Ao to PO7 A7 P10 As Ds to P17 A 5 Dis 20 to P27 Az3 D7 P3o R W to P33 HLDA P43 to P4e Inside dotted line included Data bus Ports PA HOLD P4 RDY P47 P5 1 TAO 5 1 55 2 57 in m P61 TA4in P62 INTo to P64 INT2 P65 TBOw to P67 TB2in P82 RxDo P8e RxD There is no hysteresis for P82 RxDo and P8eRxDi f Direction register Port latch A OR GU a s s Inside dotted line not included Ports P42 1 P8s TxDo P8
429. tion description The input level of the RDY pin is judged at the falling of the clock Then when L level is detected the microcomputer enters Ready state This is called acceptance of Ready request In Ready state the input level of the RDY pin is judged at every falling of the clock Then when H level is detected the microcomputer terminates Ready state next rising of the clock Figures 12 3 1 shows timing of acceptance of Ready request and termination of Ready state Refer also to section 17 1 Memory expansion about use of the Ready function 12 14 7702 7703 Group User s Manual CONNECTION WITH EXTERNAL DEVICES 12 3 Ready function lt No Wait gt RDY pin input level sampling timing c6 Clock 1 Q Q NE A A e evel which is input to the in is D The L level which is inp he RDY pin i accepted so that E stops at H level for 1 cycle of clock 1 indicated by and CPU stops j at L level E The L level which is input to the RDY pin is not accepted however CPU stops at L level ALE The L level which is input to the pin is accepted so that E stops at L level for 1 cycle of clock 1 indicated by 62777 and p CPU stops RDY at L level Bus notinuse Businus The ready state is terminated 5 The 1 level which is input to the RDY pin is not accept
430. tionship between port P7 direction register and A D converter s input pins 7702 7703 Group User s Manual 8 9 A D CONVERTER 8 3 A D conversion method 8 3 A D conversion method The A D converter compares the comparison voltage Vre which is internally generated according to the contents of the successive approximation register with the analog input voltage Vin which is input from the analog input pin ANi By reflecting the comparison result on the successive approximation register Vin is converted into a digital value When a trigger is generated the A D converter performs the following processing D Determining bit 7 of the successive approximation register The A D converter compares Vre with Vin At this time the contents of the successive approximation register is 100000002 initial value Bit 7 of the successive approximation register changes according to the comparison result as follows When lt Vin bit 7 1 When Vret gt Vin bit 7 0 Determining bit 6 of the successive approximation register After setting bit 6 of the successive approximation register to 1 the A D converter compares Veret with Vin Bit 6 changes according to the comparison result as follows When Vre lt Vin bit 6 1 When Vret gt Vin bit 6 40 Determining bits 5 to 0 of the successive approximation register Operations in are performed for bits 5 to O When bit 0 is determined the
431. transfer data length 7 bits 8 bits or 9 bits is only that data length When selecting a 7 or 8 bit data length set the transmit data into the low order byte of the UARTi transmit buffer register When selecting a 9 bit data length set the transmit data into that low order byte and bit 0 of that high order byte Transmission is started when all of the following conditions to are satisfied Transmit is enabled transmit enable bit 1 Transmit data is present in the UARTi transmit buffer register transmit buffer empty 07 CTSi pin s input is L level when CTS function selected Note When the CTS function is not selected this condition is ignored When using interrupts it is necessary to set the corresponding register to enable interrupts For details refer to Chapter 4 INTERRUPTS Figure 7 4 4 shows writing data after start of transmission and Figure 7 4 5 shows detection of transmission s completion 7 40 7702 7703 Group User s Manual SERIAL I O 7 4 Clock asynchronous serial I O UART mode UARTO baud rate register BRGO Address 3116 UART1 baud rate register BRG1 Address 3916 UARTO transmit receive mode register Address 3016 UART1 transmit receive mode register Address 3816 b7 bO b2 b1 50 1 0 1 UART mode 8 bits 1 1 0 UART mode 9 bits lt C Set to 0016 to FF4146 Internal External clock select bit 0 Inter
432. ts select the A D conversion interrupt s priority level When using A D conversion interrupts select priority levels 1 to 7 When an A D conversion interrupt request occurs its priority level is compared with the processor interrupt priority level IPL and the requested interrupt is enabled only when its priority level is higher than tne IPL However this applies when the interrupt disable flag 1 0 To disable the A D conversion interrupt set these bits to 0002 level 0 2 Interrupt request bit bit 3j This bit is set to 1 when an A D conversion interrupt request occurs This bit is automatically cleared to 0 when the A D conversion interrupt request is accepted This bit can be set to 1 or cleared to 0 by software 8 8 7702 7703 Group User s Manual A D CONVERTER 8 2 Block description 8 2 5 Port P7 direction register The A D converter and port P7 use the same pins in common When using these pins as the A D converter s input pins set the corresponding bits of the port P7 direction register to O to set these ports for the input mode Figure 8 2 6 shows the relationship between the port P7 direction register and A D converter s input pins b7 b6 b5 b4 b3 b2 bi b0 Port P7 direction register Address 11 6 o wem sona nos ome 1 Output mode o aw vosmet corresponding bits to 0 RW aw aw Fig 8 2 6 Rela
433. u PiD E th E P1A th E P1D th E P2D th E BHE th E R W d Test conditions 1 E PO P3 Data input 0 16 V Viu 0 5 V Test conditons P4 P8 Vcc 2 7 5 5 V Input timing voltage VIL 0 2 V 0 8 V Output timing voltage VoL 0 8 V 2 0 V 7702 7703 Group User s Manual LOW VOLTAGE VERSION 18 4 Electrical characteristics 18 4 10 Testing circuit for ports PO to P8 and Fig 18 4 1 Testing circuit for ports PO to P8 1 and E 7702 7703 Group User s Manual 18 31 LOW VOLTAGE VERSION 18 5 Standard characteristics 18 5 Standard characteristics The data described below are characteristic examples for M37702M2LXXXGP The data is not guaranteed value Refer to section 18 4 Electrical characteristics for rated value 18 5 1 Port standard characteristics 1 Programmable I O port CMOS output P channel lou Vou characteristics Power source voltage Vcc 3 V P channel 25 0 20 0 15 0 mA 10 0 5 0 0 0 5 1 0 20 25 3 0 V 2 Programmable I O port CMOS output channel lo Vo characteristics Power source voltage Vcc 3 V N channel 25 0 Ta 40 C ae 25 T lt 150 85 10 0 5 0 0 0
434. ulator the TAiour pin outputs L level of the PWM pulse which has the same width as set H level of the PWM pulse after a trigger generated After that the pulse output starts from the TAiour pin 5 44 7702 7703 Group User s Manual TIMER A 5 6 Pulse width modulation PWM mode 1 fix 216 1 Count source l L _ _ pin s input signal j mou Trigger is not generated by this signal PWM pulse output HW from TAiour pin T Timer Ai interrupt T request bit i fi Frequency of count source fo f16 164 or f512 Cleared to 0 when interrupt request is accepted or cleared by software Note The above applies when reload register 000316 and an external trigger rising of pin s input signal is selected Fig 5 6 4 Operation example of 16 bit pulse width modulator n Reload register s contents 1 fi 216 1 1 fi x 216 1 4 1 Counter contents Hex 000116 Stops Restarts counting counting pin s H input signal gt PWM pulse output from TAiour pin 4 FFFE e is set to timer Ai 000016 is set to timer Ai 200016 is set to timer Ai fi Frequency of count source register register register f2 fie fe4 Or f512 When an arbitrary value is set to the timer Ai register after setting 000016 to it the timing
435. ulse period Pulse width RW measurement mode Not selected eG EN Undefined RO Note ERE o w Note Bit 5 is ignored in the timer mode and event counter mode its value is undefined at reading Fig 6 2 3 Structure of timer Bi mode register 7702 7703 Group User s Manual 6 5 TIMER B 6 2 Block description 6 2 4 Timer Bi interrupt control register Figure 6 2 4 shows the structure of the timer Bi interrupt control register For details about interrupts refer to Chapter 4 INTERRUPTS 67 06 b5 b4 b3 02 bli Timer Bi interrupt control registers i to 2 Addresses 7 16 to 7C 6 Interrupt priority level select bits j Level 0 Interrupt disabled 0 1 Level 1 Low level Level 6 Level 2 Level 3 Level 4 Level 5 RW Level 7 High level 3 Interrupt request bit 0 No interrupt request RW 1 Interrupt request Nothing is assigned Umeined Note Use the SEB or CLB instruction to set each interrupt control register Fig 6 2 4 Structure of timer Bi interrupt control register 1 Interrupt priority level select bits bits 2 to 0 These bits select a timer Bi interrupt s priority level When using timer Bi interrupts select priority levels 1 to 7 When the timer Bi interrupt request occurs its priority level is compared with the processor interrupt priority level IPL so that the requested interrupt is enabled only when its priority level is higher than the IPL H
436. until the completion of executing instruction which is being done at the end of priority detection Note At this time interrupt priority detection starts Time required to execute the INTACK sequence 13 cycles of at minimum Fig 4 7 1 Sequence from acceptance of interrupt request to execution of interrupt routine e When stack pointer S s contents is even no Wait Internal clock cpu Pa X o Xo Xm o X o X o X o Xo X 9 X PO X 5 10 28 IS S SFOS ISFSWAISESA Fe X o X A Interrupt disable flag 1 INTACK sequence CPU standard clock Not used High order 8 bits of CPU internal address bus S Contents of stack pointer S Middle order 8 bits of CPU internal address bus XX16 Low order 8 bits of vector address Low order 8 bits of CPU internal address bus ADu Contents of vector address High order address CPU internal data bus for odd address AD Contents of vector address Low order address CPU internal data bus for even address Fig 4 7 2 INTACK sequence timing at minimum 7702 7703 Group User s Manual 4 15 INTERRUPTS 4 7 Sequence from acceptance of interrupt request to execution of interrupt routine 4 7 1 Change in IPL at acceptance of interrupt request When an interrupt request is accepted the processor interrupt priority level IPL is replaced with the interrupt priority level of the accepted interrupt T
437. up User s Manual 4 Start bit DATA Character bit transfer data PAR Parity bit SP Stop bit SERIAL I O 7 4 Clock asynchronous serial I O UART mode Example of 1ST 8DATA 1PAR 1SP ime Transmit Receive data gt Next transmit receive data DATA 8 bits When continuously transferring Fig 7 4 2 Example of transfer data format Table 7 4 5 Each bit in transmit data Name Functions ST L signal equivalent to 1 character bit which is added immediately before the Start bit character bits It indicates start of data transmission DATA Transmit data which is set in the UARTi transmit buffer register Character bit PAR A signal that is added immediately after the character bits in order to improve data Parity bit reliability The level of this signal changes according to selection of odd even parity in such a way that the sum of 1 s in this bit and character bits is always an odd or even number ST H level signal equivalent to 1 or 2 character bits which is added immediately after Stop bit the character bits or parity bit when parity is enabled It indicates finish of data transmission 7702 7703 Group User s Manual 7 39 SERIAL I O 7 4 Clock asynchronous serial UART mode 7 4 3 Method of transmission Figure 7 4 3 shows an initial setting example for relevant registers when transmitting The difference due to selection of
438. upt request bit is set to 1 The transmit operations are described below Data in the UARTi transmit register is transmitted from the TxDi pin This data is transmitted bit by bit sequentially in order of STA DATA LSB 5 DATA MSB PAR SP according to the set transfer data format When the stop bit has been transmitted the transmission register empty flag is set to 1 indicating completion of transmission When the transmit conditions for the next data are satisfied at completion o transmission the start bit is generated following the stop bit and the next data is transmitted When performing transmission continuously set the next transmit data in the UARTi transmit buffer register during transmission when the transmit register empty 0 When the transmit conditions for the next data are not satisfied the TxDi pin outputs H level Figures 7 4 6 shows example of transmit timing when the transfer data length is 8 bits and Figure 7 4 7 shows an example of transmit timing when the transfer data length is 9 bits 7 44 7702 7703 Group User s Manual SERIAL I O 7 4 Clock asynchronous serial I O UART mode Transfer clock Transmit enable bit Data is set in UARTi transmit buffer register Transmit buffer empty flag CTSi TENDi TxDi Transmit register empty flag transmit interrupt request bit Cleared to 0 when interrupt request is accepted or cleared by so
439. ure of port P8 direction register when using UART1 7702 7703 Group User s Manual 20 9 7703 GROUP 20 4 Functional description 20 4 5 A D converter 37703 analog inputs are 4 channels ANo to AN and AN 1 One shot and Repeat modes Set the analog input select bits bits 2 to 0 at address 1E e to one of 0002 0012 0102 and 1112 Set the bits of the port P7 direction register which do not have pins corresponding to analog inputs ANs to ANe to 1 to make them output mode Figure 20 4 7 shows the structure of the A D control register and Figure 20 4 8 shows the structure of the port P7 direction register when using A D converter 2 Single sweep and Repeat sweep modes Set the bits of the port P7 direction register corresponding to ANo to AN and AN pins to 0 to make them input mode Set the bits of the port P7 direction register which do not have pins corresponding to analog inputs ANs to ANeto 1 to make them output mode The A D register contents corresponding to analog inputs ANs to ANe which do not have their pins become undefined 67 b6 05 b4 b3 b2 bl A D control register Address 1 6 Analog input select bits Valid in one shot and repeat ANo selected Undefined RW modes Note 1 AN1 selected AN2 selected Not selected f Not selected Undefined RW Not selected Not selected AN selected Note 2 1 0 Single sweep mode A D operation mo
440. vent counter mode without pulse output function and two phase pulse signal processing function 5 24 7702 7703 Group User s Manual TIMER A 5 4 Event counter mode 1 Switching between up count and down count The up down register address 4416 or the input signal from the TAiour pin is used to switch the up count from and to the down count This switching is performed by the up down bit when the up down switching factor select bit bit 4 at addresses 56 to 5A e is 0 and by the input signal from the TAiour pin when the up down switching factor select bit is 1 When switching the up count down count this switching is actually performed when the count source s next valid edge is input Switching by up down bit The counter down counts when the up down bit is 0 up counts when the up down bit is 1 Figure 5 4 5 shows the structure of the up down register Oe Switching by TAiour pin s input signal The counter down counts when the TAiour pin s input signal is at L level and up counts when the TAiour pin s input signal is at H level When using the pin input signal to switch the up count down count set the port P5 and P6 direction registers bits which correspond to the TAiour pin for the input mode 67 b6 b5 b4 b2 bi bO Up down register Address 4416 Timer AO up down bit 0 Down count 1 Up count Timer A1 up down bit This function is valid when the Timer A2 up down
441. when using as an input port and set 1 when using as an output port Fig 20 4 1 Procedure of port Pi i 2 3 4 6 7 8 direction register 20 6 7702 7703 Group User s Manual 7703 GROUP 20 4 Functional description 20 4 2 Timer A The M37703 does not have the I O functions of Timer A4 It can be used only in the timer mode Fix bits 5 to 0 of the timer A4 mode register to 0000002 Figure 20 4 2 shows the structure of the timer A4 mode register 67 06 b5 b4 b3 b2 bi bO 0 0 0 0 0 0 Timer A4 mode register Addresses 5A16 Functions ens re Fix these bits to 0 s pee In timer mode without pulse output and gate functions Count source select bits bad pee 00 fe 0 1 f16 1 11 1512 1 1 1 1 1 1 1 1 L 1 Fig 20 4 2 Structure of timer A4 mode register 20 4 3 Timer B The M37703 does not have the input functions of Timers B1 and B2 They can be used only in the timer mode Fix bits 1 and 0 of the timer B1 and B2 mode registers to 002 Figure 20 4 3 shows the structure of the timer B1 and B2 mode registers 67 06 b5 04 b3 b2 bi Timer B1 mode register Addresses 5Cie Timer B2 mode register Addresses 5Die Fix these bits to O HW In timer mode These bits are ignored in timer mode RW o w Nothing is assigned This bit is ignored timer mode neus Count source select bits Dr 285 RW 00 fe 01
442. y AD select bit 0 f2 divided by 4 1 12 divided by 2 lnterrupt priority level B b7 Sg A D conversion interrupt control register address 7016 Interrupt priority level select bits Set to a level between 1 to 7 when using this interrupt Set to a level 0 when disabling this interrupt d pon P7 direction register N b7 b0 Port P7 direciion register address 1116 ANo AN AN2 Set the bits corresponding to analog input pins to 0 AN4 Set bit 7 to 0 when ANE selecting external trigger ANe AN7 E A D conversion start bit to 1 b7 A D control register address 1 16 A D conversion start bit electing external trigger wv Input falling edge to ADrnc Selecting internal trigger Trigger occur Operation start Note Write each bit except bit 6 of the A D control register and each bit of the A D sweep pin select register when the A D conversion stops before trigger occurs Fig 8 7 1 Initial setting example of single sweep mode 7702 7703 Group User s Manual 8 21 A D CONVERTER 8 7 Single sweep mode 8 7 2 Single sweep mode operation description 1 2 8 22 When an internal trigger is selected The operation for the input voltage from the ANo pin starts w
443. y if the capacitor between the analog input pin and AVss pin is grounded away from the AVss pin noise on that ground can get into the microcomputer via the capacitor Thermistor Heference value Approximately 100 to 10000 CI Approximately 100 to 1000 pF Notes 1 Make sure that the external circuit of the pin is designed so that the pin can be charged discharaed within 1 cycle of AD 2 his resistor is used to divide resistance from the thermistor Fig 15 Example for protecting analog input pin against noise by using thermistor 7702 7703 Group User s Manual 21 39 APPENDIX Appendix 5 Countermeasures against noise 2 Processing of analog power source pins and others For each of the Vcc AVcc and Vrer pins use separated power sources Insert capacitors between the AVcc and AVss pin and between the Vrer and AVss pin respectively Reasons Avoids affecting the A D converter due to noise on Vcc M37702 Reference value C1 gt 0 47 uF C2 gt 0 47 uF Note Connect capacitors with the thickest possible wiring in the shortest possible distance sensor and others P Fig 16 Processing of analog power source pin and others 21 40 7702 7703 Group User s Manual APPENDIX Appendix 5 Countermeasures against noise 4 Consideration to oscillator The oscillator that generates the fundamental clock of the microcomputer s operation requires careful consideration not to be aff
444. ypass capacitor make sure that the following conditions are satisfied Wiring length between the Vss pin and the bypass capacitor equals that between the Vcc pin and the bypass capacitor Wiring between the Vss pin and the bypass capacitor and that between the Vcc pin and the bypass capacitor have the shortest possible length The Vss and Vcc lines both have broader wiring width than the other signal wires Bypass capacitor Wiring pattern Wiring pattern M37702 Fig 14 Bypass capacitor between Vss and Vcc lines 21 38 7702 7703 Group User s Manual APPENDIX Appendix 5 Countermeasures against noise 3 Wiring processing of analog input pin analog power source pin and others 1 Processing of analog input pin Connect a resistor in series to the analog signal wire connecting to an analog input pin at the position closest possible to the microcomputer Insert a capacitor between the analog input pin and AVss pin at a position closest possible to the AVss pin Reasons Normally the signal which is input to the analog input pin is an output signal from a sensor A sensor used to detect changes in event is in many cases located away from the board on which the microcomputer is mounted Accordingly wiring from the sensor to the analog input pin inevitably becomes long This long wiring can serve as an antenna that pulls in noise into the microcomputer letting noise get into the analog input pin easily Additionall
445. z TxD eoo eger lt II _ Inside dotted line included Ports P5o0 TAQout P52 TA1out P54 TA2ovr P5e6 TASout P6o TA4our Data bus wet Ecce Inside dotted line not included Ports P7o ANo to P7e ANe Direction register Port latch m Analog input Inside dotted line included Port P77 AN7 ADtre Data bus qoem URNA Sees eas Sao 7703 Group There are not pins P33 P43 P46 P60 P61 P66 P67 P73 P76 Fig 3 1 4 Port peripheral circuits 1 3 6 7702 7703 Group User s Manual INPUT OUTPUT PINS 3 1 Programmable I O ports Ports P80 CTSo RTSo P81 CLKo P84 CTSi RTS i P8s CLK Q UE E output pin 7703 Group There are not pins P84 and P85 Fig 3 1 5 Port peripheral circuits 2 7702 7703 Group User s Manual 3 7 INPUT OUTPUT PINS 3 2 I O pins of internal peripheral devices 3 2 pins of internal peripheral devices P42 and P5 to P8 also function as the I O pins of the internal peripheral devices Table 3 2 1 lists I O pins for the internal peripheral devices For their functions refer to relevant sections of each internal peripheral devices For the clock output pin refer to Chapter 12 CONNECTION WITH EXTERNAL DEVICES Table 3 2 1 1 0 pins for internal peripheral devices Port I O pins for internal peripheral devices P4 Clock output pin

7702/7703 Group USER`S MANUAL - Digi-Key

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