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IP330A User`s Manual

1. Conversion Timer Register Start Channel Value Register End Channel Value Register IMPORTANT SAFETY CONSIDERATIONS It is very important for the user to consider the possible adverse effects of power wiring component sensor or software failures in designing any type of control or monitoring system This is especially important where economic property loss or human life is involved It is important that the user employ satisfactory overall system design It is agreed between the Buyer and Acromag that this is the Buyer s responsibility 1 0 GENERAL INFORMATION The Industrial I O Pack IP Series IP330A module is a precision 16 bit high density single size IP with the capability to monitor 16 differential or 32 single ended analog input channels The IP330A utilizes state of the art Surface Mounted Technology SMT to achieve its high channel density Four units may be mounted on a carrier board to provide up to 64 differential or 128 single ended analog input channels per 6U VMEbus system slot or XO CO cO CO CO COO OO 1 OO OO O1 O1O1 01010101 3 3 00 OO TO IO New Data Register M 10 ISA bus PC AT system slot The IP330A offers a variety of Missed Data Register e 10 features which make it an ideal choice for many industrial and Start Convert Register 10 scientific applications as described below
2. SIDE VIEW G RAIL DIN MOUNTING SHOWN HERE DIN EN 50035 32mm T RAIL DIN MOUNTING SHOWN HERE DIN EN 50022 35mm d SLOT FOR REMOVAL FROM T RAIL NOTES DIMENSIONS ARE IN INCHES MILLIMETERS TOLERANCE 40 020 0 5 MODEL 5025 552 TERMINATION PANEL ARTI 4501 464A A B C D 125 48 49 50 125 48 49 50 125 48 49 50 125 48 49 50 CONNECTORS ON PC BOARD MODEL TRANS GP MODULE SCHEMATIC BK 1253 48 49 50 123 48 49 50 1253 48 49 50 1253 48 49 50 FRONT PANEL A B C D TOP VIEW lt 9 19 233 4 gt X o 5 5 E X 1 Seg a Th d 3 15 lt o 3 35 80 0 j V lj 9 Uu 85 1 q A ieee co tent ECT O O02 2 5 E a lt M lo E Ti E q y FRONT VIEW 078 Qi M S m 9 98 69 5 SP lx 10 31 261 9 TRANS GP MECHANICAL DIMENSIONS AND SIMPLIFIED SCHEMATIC 4501 465A NOTE DIMENSIONS ARE IN INCHES MILLIMETERS 28
3. ASSEMBLY PROCEDURE 1 THREADED SPACERS ARE PROVIDED IN TWO DIFFERENT LENGTHS THE SHORTER LENGTH IS FOR USE WITH AVME 9630 9660 CARRIER BOARDS SHOWN CHECK YOUR CARRIER BOARD TO DETERMINE ITS REQUIREMENTS MOUNTING HARDWARE PROVIDED MAY NOT BE COMPATIBLE WITH ALL TYPES OF CARRIER BOARDS SERT FLAT HEAD SCREWS ITEM A THROUGH SOLDER SIDE OF P MODULE AND INTO HEX SPACERS ITEM B AND TIGHTEN 4 PLACES UNTIL HEX SPACER IS COMPLETELY SEATED 3 CAREFULLY ALIGN IP MODULE TO CARRIER BOARD AND PRESS TOGETHER UNTIL CONNECTORS AND SPACERS ARE SEATED SERT PAN HEAD SCREWS ITEM C THROUGH SOLDER SIDE OF CARRIER BOARD AND INTO HEX SPACERS ITEM B AND TIGHTEN 4 PLACES P 5 IP MODULE TO CARRIER BOARD MECHANICAL ASSEMBLY 4201 4348 MOVd O I WIYLSNAGNI VOEEd I 9384345 FINGOW LAdNI ALISN3G LIg 9L YO ANALOG INP DESIRED ADC INPUT RANGE VDC 1 800 4 0 020 REQUIRED INPUT SPAN VOLTS LOGIC INTERFACE P1 1 0 INTERFACE P2 J3 IS FOR FACTORY USE ONLY DO NOT CONNECT SWITCH IN OFF POSITION 3 10 SWITCH IN OFF POSITION DIP SWITCH SHOWN WITH DEFAULT SWITCH SETTIN POSITIONS 1 3 4 AND 9 ON J3 2 6S COMPONENT SIDE VIEW REQUIRED INPU
4. 1 0 LOGIC TERFACE CONTROL P2 CALIBRATION RANGE LOGIC P1 VOLTAGES SELECTION DIP SWITCH ID SPACE Identification Bytes DATA BUS SECOND INPUT INST S H amp DATA SERIAL TO PARALLEL cf LEVEL AMP amp 16 BIT CONVERTER MUX rT MUX PGA ADC MAIL BOX BUFFER 52 X 16 BITS NEW DATA ADDRESS BUS REGISTER MISSED DATA REGISTER CONTROL GAIN SELECT L EXTERNAL TRIGGER INPUT OR OUTPUT REGISTERS CONTROL BUS INTERVAL L anatos TIMER COMMON 4 V INTERRUPT 4 LOGIC AND VECTOR 15V SUPPLIES J1 amp J2 12V SUPPLIES SUPPLY SELECTION IP53 A BLOCK DIAGRAM MOVd O I WIYLSNAGNI VOEEd I SAIWAS FINGOW LAdNI ALISN3G LIg 9L PIN 5 OF P1 amp P2 CONNECT TO GROUND SHIELD Jo NU 4 O1 O O0 CO I M Qi 4 O1 O O0 CO MODEL 5025 551 SCHEMATIC MODEL 5025 551 x SIGNAL CABLE SHIELDED TO AVME9630 9660 CARRIER BOARD P3 OR P4 P5 P6 1004 534 50 PIN CONNECTOR 1004 512 NOTE SEVEN DIGIT PART NUMBERS ARE ACROMAG PART NUMBERS XXXX XXX P1 I TO MODEL 5025 552 1 0 TERMINATION STRAIN RELIEF m 5
5. IP330A JUMPER LOCATION X 24 KEY IPSSOAFEATURES droite eden ce ce ANALOG INPUT CONNECTION en 25 INDUSTRIAL I O PACK INTERFACE FEATUREG IP330A BLOCK 26 SIGNAL INTERFACE PRODUCTS sess 4501 463 CABLE 5025 551 SHIELDED 27 INDUSTRIAL I O PACK SOFTWARE LIBRARY 4501 464 TERMINATION PANEL 5025 552 28 2 0 PREPARATION FOR 5 4501 465 TRANSITION MODULE TRANS GP 28 UNPACKING AND INSPECTION CARD CAGE CONSIDERATIONS BOARD CONFIGURATION it Default Hardware Jumper Configuration Analog Input Range Hardware Jumper Configuration Power Supply Hardware Jumper Configuration Software Configuration 5 IP Field I O Connector P2 Analog Inputs Noise and Grounding Considerations External Trigger IP Logic Interface Connector P1 3 0 PROGRAMMING IP IDENTIFICATION PROM as SPACE ADDRESS 5 Control Register esee Analog Ranges amp Corresponding Digital O P Codes Interrupt Vector Register eesssseess Timer Prescaler
6. Temperature Coefficient See spec of calibration voltages Vectored Interrupt on end channel conversion or end of group of channel conversions Note 8 Reference Test Conditions Differential inputs 5V input range PGA Gain 1 Temperature 25 C 12V internal power supplies 67K conversions second using Acromag s APC8621A PCI carrier with a 6 inch shielded cable length connection to the field analog input signals 9 A total of 2048 input samples were taken statistically assuming a normal distribution to determine the RMS value Accuracy may be further improved by increasing the time between conversions e g from 15 usec to 30 psec 10 External Trigger Input Output As An Must be an active low 5 volt logic TTL compatible debounced signal referenced to analog common Conversions are triggered on the falling edge of this trigger signal Minimum pulse width 500n seconds As An Output Active low 5 volt logic TTL compatible output is generated The trigger pulse is low for a maximum of 500n seconds INDUSTRIAL I O PACK COMPLIANCE Specification This module meets or exceeds ANSI VITA 4 1995 specifications Electrical Mechanical Interface Single Size IP Module SERIES IP330A INDUSTRIAL I O PACK 16 BIT HIGH DENSITY ANALOG INPUT MODULE IP Data Transfer Cycle
7. Gain Select Ch 26 3C Gain Select Ch 28 Gain Select Ch 30 2C sed Gain Select Ch 01 Gain Select Ch 03 Gain Select Ch 05 Gain Select Ch 07 Gain Select Ch 09 Gain Select Ch 11 Gain Select Ch 13 Gain Select Ch 15 Gain Select Ch 17 Gain Select Ch 19 Gain Select Ch 21 Gain Select Ch 23 Gain Select Ch 25 Gain Select Ch 27 Gain Select Ch 29 Gain Select Ch 31 27 e Mailbox Ch 00 SE or Diff Mode Mai Mai Mai Mailbox Ch 04 Mailbox Ch 05 Mailbox Ch 06 Mailbox Ch 07 Mailbox Ch 08 Mailbox Ch 09 A box Ch 01 SE or Diff Mode box Ch 02 SE or Diff Mode box Ch 03 SE or Diff Mode SE or Diff Mode SE or Diff Mode SE or Diff Mode SE or Diff Mode SE or Diff Mode SE or Diff Mode Mailbox Ch 10 Mailbox Ch 11 SE or Diff Mode SE or Diff Mode Mailbox Ch 12 Mailbox Ch 13 SE or Diff Mode SE or Diff Mode Mailbox Ch 14 ae Nae Na Nae ee SE or Diff Mode Mailbox Ch 15 SE or Diff Mode Mailbox Ch 16 SE Ch 00 Diff Mode Mailbox Ch 17 SE Ch 01 Diff Mode Mailbox Ch 18 SE Mailbox Ch 19 SE Ch 02 Diff Mode Ch 03 Diff Mode ee ee Mailbox Ch 20 SE Mailbox Ch 21 SE Mailbox Ch 22 SE Mailbox Ch 23 SE ec Ch 04 Diff Mode Ch 05 Diff Mode Ch 06 Diff Mode Ch 07 Diff Mode I a 70 72 74 76 78 7A Mailbox Ch 24 SE Mailbox Ch 25 SE Mailbox Ch 26 SE Mailbox Ch 27 SE Mailb
8. plating in the mating area Threaded metric M2 screws and spacers are supplied with the module to provide additional stability for harsh environments see Mechanical Assembly Drawing 4501 434 The field and logic side connectors are keyed to avoid incorrect assembly P2 pin assignments are unique to each IP model see Table 2 3 and normally correspond to the pin numbers of the field I O interface connector on the carrier board you should verify this for your carrier board When reading Table 2 3 note that channel designators are abbreviated to save space For example single ended channel 0 is abbreviated as S00 the input for differential channel 0 is abbreviated as D00 Both of these labels are attached to pin 1 but only one is active for a particular installation i e if your inputs are applied differentially which is recommended for the lowest noise and best accuracy follow the differential channel labeling for each channel s and input leads IMPORTANT All unused analog input pins should be tied to analog ground Floating unused inputs can drift outside the input range causing temporary saturation of the input analog circuits Recovery from saturation is slow and affects the reading of the desired channels Assuming a gain of 1 These ranges can only be achieved with 15V external power supplies The input ranges will be clipped if 12V supplies are used typically to 9 8 V maximum inputs Table
9. represents the analog signal digitized in the previous convert cycle That is the A D Converter transfers digitized analog input data to the FPGA one convert cycle after it has been digitized Serially shifting of the 16 bits of digitized data to the FPGA and then writing to the Mailbox buffer is completed 8 usec after start of the convert cycle Upon initiation of an A D convert cycle the analog input data is digitized and stored into an internal A D Converter buffer Also during this cycle the last converted data value is moved from the A D Converter buffer to the FPGA s Mailbox Buffer At this time the New Data Available bit corresponding to the previous converted channel is set in the FPGA register Understanding this sequence of events is important when using the External Trigger Only scan mode The first digitized value received from the A D Converter in External Trigger Only mode will not be written to the Mailbox buffer if the Start Convert bit is set prior to issuance of the first external trigger signal This first value received from the A D Converter is digitized data that has remained in the A D Converter s buffer from a previous data acquisition session Likewise to update the Mailbox with the last desired digitized data value one additional convert cycle is required For all other scan modes the FPGA control logic will automatically discard the first digitized data value received from the A D Converter It is not written to t
10. 2 3 IP330A Field I O Pin Connections P2 Pin Description Number Pin Description Number COMMON S18D02 8 COMMON 9 ndicates that the signal is active low Sense is the common ground for all single ended inputs Power Supply Hardware Jumper Configuration The selection of internal or external analog power supplies is accomplished via hardware jumpers J1 and J2 J1 J2 controls the selection of either the internal 12 12 Volt supply sourced from P1 connector or the external 15 15 Volt supply sourced from the P2 connector The configuration of the jumpers for the different supplies is shown in Table 2 2 IN means that the pins are shorted together with a shorting clip OUT means that the clip has been removed The jumper locations are shown in IP330A Jumper Location in the Drawing Section Table 2 2 Power Supply Selections Pins of J1 and J2 Power Supply J1 J1 J2 J2 Selection 1 amp 2 2 amp 3 1 amp 2 2 amp 3 12 Volt Internal P1 15 Volt External P2 nternal and external supplies should not be mixed e g do not use 12 Volts with 15 Volts Software Configuration Software configurable control registers are provided for control of external trigger mode data output format acquisition mode timer control interrupt mode convert channel s selection and channel gain selection No hardware jumpers are required for SERIES IP330A INDUSTRIAL I O PACK 16 BI
11. 8 Repeat the above steps periodically to re measure the calibration parameters CountcA and CountcaA o as required Measure Channels 3 to 13 Single Ended and Correct Using Uniform Single Mode 12 Execute Write of to Control Register at Base Address OOH Select Straight Binary External Trigger Input Select Single Ended Input Uniform Single Scan Mode Timer Enabled f Interrupts Disabled 13 Execute Write of 0DO3H to End Start Channel Value Register at Base Address 06H This will permit conversions of channels 3 to 13 Writing the Gain Selects is not necessary since they do not need to change from that programmed in step 3 above 14 Execute Write of 50H as a byte data transfer to the Timer Prescaler at Base Address 02H This sets the Timer Prescaler to 80 decimal 15 Execute Write 0008H to the Conversion Timer at Base Address 04H This Conversion Timer value in conjunction with the Timer Prescaler sets the interval time between conversions to 80 8 8 80 usec 16 Execute Write 0001H to the Start Convert Bit at Base Address 10H This starts a uniform single mode of conversions Conversions of channels 3 to 13 are implemented and stored in their corresponding Mailbox Buffers 17 Execute Read of the Mailbox Buffers at Base Address 46H to 5AH The data represents the uncorrected Count Actual term in equation 1 Since all parameters on the right hand side of equation 1 are known The calibrated v
12. Electric Fast Transient Immunitys EFT Complies with IEC61000 4 4 Level 2 0 5KV at field input and output terminals and European Norm EN61000 6 1 Radiated Emissions Meets or exceeds European Norm EN61000 6 3 for class B equipment ADC ADS8509 or equivalent 25 C ttt ttem cds rt TI ADS8509 A D Resolution 16 bits Data Format Binary 2 s Complement and Straight Binary No Missing Codes No Missing Codes 15 bits ADC A D Integral Linearity Error 1 LSB Typical 2 LSB Maximum ADC Unipolar Zero Error 5 mV Maximum for 0 10 V Range 3 mV Maximum for 0 5 V Range Bipolar Offset Error 5 mV Maximum for 10 V Range 5 mV Maximum for 5 V Range Full Scale Error 0 5 Maximum PGA AD8251 or equivalent 25 C PG ADI AD8251 PGA Linearity Error 0 005 Maximum 3 27 LSB Offset Error 1 0 mV Typical 2 5 mV Maximum Gain Error all gains DRE 0 01 Typical 0 1 Maximum Note 5 Software calibration eliminates these error components Programmable Calibration Voltages Ideal Maximum Value Tolerance Volts 25 C Volts Maximum Temperature Drift ppm 9C AutoZero 0 0000 30000550 o0 Note 6 Worst case temperature drift is the sum of the 10 ppm 9C drift o
13. Gain Select 10 Mailbox B ffer 1 5 ener teri 11 m MODES OF OPERATION MEET Model Operating Temperature Range Uniform Continuous Mode id 11 Uniform 12 Burst 12 Burst 6 iu 12 Convert On External Trigger OUI MH 12 How abo M 16 bit capacitor based successive PROGRAMMING CONSIDERATIONG 2 13 p IS Use of Calibration Signals 13 approximation Analog to Digital Converter ADC with integral Calibration Programming Example 1 5 14 sample and hold and reference Calibration Programming Example 2 15 e 5 usec Conversion Time A maximum conversion rate of Programming Interrupts 17 200 kHz is supported Maximum recommended conversion 4 0 THEORY OF 17 rate for specified accuracies is 67 kHz FIELD ANALOG INPUTS 17 e High Density Monitors up to 16 differential or 32 single LOGIC POWER INTERFACE 18 ended analog inputs acquisition mode and channels are IP INTERFACE LOGIC 18 selected via programmable control registers IP330A CONTROL LOGIC 18 INTERNAL CHANNEL POINTERS g 18 9 Individual Channel Mailbox Two storage buffer reg
14. Types Supported Input Output IOSel D16 or D08 read write of data ID Read IDSel 32 x 8 ID PROM read on DO D7 as D16 or D08 Interrupt Select INTSel 8 bits D08 Interrupt Vector Register contents Access Times 8 MHz Clock ID PROM Read I O Space Read Mailbox I O Space Read 1 wait state 375 ns cycle 1 wait state 375 ns cycle 1 wait state typical 375 ns cycle 3 wait states maximum if ongoing internal Mailbox write Space Write 1 wait state 375 ns cycle Interrupt Select Read 1 wait state 375 ns cycle Power Up Initialization Time 200mS Max During this time the IP module will ignore all signals APPENDIX CABLE MODEL 5025 550 x Non Shielded MODEL 5025 551 x Shielded Type Flat Ribbon Cable 50 wires female connectors at both ends The cables are available in 4 7 or 10 feet lengths Custom lengths 12 feet maximum are available upon request Choose shielded or unshielded cable according to model number The unshielded cable is recommended for digital I O while the shielded cable is recommended for optimum performance with precision analog I O applications Applications Used to connect Model 5025 552 termination panel to carrier board 50 pin field connectors Length Last field of part number designates length in feet 4 7 or 10 feet standard It is recommended that this length
15. at Base Address OOH a Select Straight Binary External Trigger Input Select 4 9000v Calibration Voltage Burst Single Scan Mode Timer Disabled Interrupts Disabled OT 8 Writing the Start Channel Value End Channel Value and the Gain Selects is not necessary if they have not been changed from that programmed in steps 2 and 3 above 9 Execute Write 0001H to the Start Convert Bit at Base Address 10H This starts the burst single mode of conversions Thirty two conversions of the 4 9 volt calibration voltage are implemented and stored in the 32 Mailbox Buffers Execute Read of the 32 Mailbox Buffers at Base Address 40H to 7EH 11 Take the average of the 32 ADC values and save this number as Countc al 15 Calculate Equation 2 Calculate m actual_slope from equation 2 since all parameters are known It is now possible to correct input channel data from any input channel using the same input range i e 10 to 10 volts with a PGA gain 1 Repeat the above steps periodically to re measure the calibration parameters CountcA and Countc ay o as required Measure Channels 0 to 3 Differentially and Correct 12 Execute Write of 0402H to Control Register at Base Address OOH Select Straight Binary External Trigger Input All Channels Differential Input Burst Single Scan Mode Timer Disabled Interrupts Disabled 2aeo5H 13 Execute Write of 0300H to End Start C
16. be kept to a minimum to reduce noise and power loss Cable 50 wire flat ribbon cable 28 gage Non shielded cable model uses Acromag Part 2002 221 3M Type C3365 50 or equivalent Shielded cable model uses Acromag Part 2002 261 3M Type 3476 50 or equivalent Headers Both Ends 50 pin female header with strain relief Header Acromag Part 1004 512 3M Type 3425 6600 or equivalent Strain Relief Acromag Part 1004 534 3M Type 3448 3050 or equivalent Keying Headers at both ends have polarizing key to prevent improper installation Schematic and Physical Attributes For shielded cable model see Drawing 4501 463 Shipping Weight 1 0 pound 0 5Kg packed TERMINATION PANEL MODEL 5025 552 Type Termination Panel For IP Carrier Boards Application To connect field I O signals to the Industrial I O Pack IP Termination Panel Acromag Part 401 040 Phoenix contact Type FLKM 50 The 5025 552 termination panel facilitates the connection of up to 50 field I O signals and connects to AVME9630 9660 9668 or APC8620 21 non intelligent carrier boards via a flat ribbon cable Model 5025 550 x or 5025 551 x The A E connectors on the carrier board connect the field I O Pack modules Field signals are accessed via screw terminal strips The terminal strip markings on the termination panel 1 50 correspond to P2 pins 1 50 on the IP Each IP has its own unique P2 pin 22 assignments Refer to the IP module manual for correct
17. carrier CPU board to verify that it is correctly configured Replacement of the board with one that is known to work correctly is a good technique to isolate a faulty board Use the unmodified example we provide CAUTION POWER MUST BE TURNED OFF BEFORE REMOVING OR INSERTING BOARDS WHERE TO GET HELP If you continue to have problems your next step should be to visit the Acromag worldwide web site at http Awww acromag com Our web site contains the most up to date product and software information Choose Bus Board Products then go to the Support tab in the Acromag banner to access e Application Notes e Frequently Asked Questions FAQ s e Knowledge Base e Tutorials e Software Updates Drivers An email question can also be submitted from within the Knowledge Base or directly from the Contact Us tab Acromag s application engineers can also be contacted directly for technical assistance via telephone or FAX through the numbers listed below When needed complete repair services are also available Phone 248 624 1541 Fax 248 624 9234 Email solutions acromag com 20 6 0 SPECIFICATIONS GENERAL SPECIFICATIONS Operating Temperature 0 to 70 C eripe iiia bane 40 to 85 C E Version Relative Humidity 5 95 non condensing Storage Temperature 55 C to 150 C Physical Configuration Single Industrial I O Pack Module Len
18. first half of the Mailbox buffer is utilized As seen in Table 3 2 the first half of the Mailbox is defined by word addresses 40H to 5EH Interrupts can be enabled to activate after conversion of each channel or the group of channels as defined by the Start and End Channel Values If interrupts are configured to go active after the conversion of each channel an interrupt will be issued every 15 usec not recommended If interrupt upon completion of a group of channels is selected an interrupt will be issued 20 psec after conversion of the last channel has started Convert On External Trigger Only Mode In convert on External Trigger Only Mode of operation each conversion is initiated by an external trigger falling edge of a logic low pulse input to the IP330A on the EXT TRIGGER signal of the P2 connector Conversions are performed for each channel between and including the Start and End Channel Values in sequential order The interval between conversions is controlled by the period between external triggers The interval timer has no functionality in this mode of operation and must be disabled by setting bit 11 of the control register to logic low SERIES IP330A INDUSTRIAL I O PACK 16 BIT HIGH DENSITY ANALOG INPUT MODULE The external trigger signal must be configured as an input for this mode of operation The external trigger can be configured as an input by setting bit 2 of the Control register low At least 5 usec of data ac
19. in making the VMEbus interrupt request IRQx corresponding to the IP interrupt request 3 The VMEbus host interrupt handler asserts IACK and the level of the interrupt it is seeking on A01 A03 4 When the asserted VMEbus IACKIN signal daisy chained is passed to the AVME9630 60 the carrier board will check if the level requested matches that specified by the host If it matches carrier board will assert the INTSEL line to the appropriate IP together with carrier board generated address bit A1 to select which interrupt request is being processed A1 low corresponds to INTREQO 5 The IP330A puts the interrupt vector on the local data bus D00 DO7 for the D08 O interrupter and asserts ACK to the carrier board The carrier board passes this along to the VMEbus DO8 O and asserts DTACK 6 The host uses the vector to form a pointer to an interrupt service routine for the interrupt handler to begin execution 7 Example of Generic Interrupt Handler Actions p a Disable the interrupting IP by writing O to the appropriate bit in the AVME9630 60 IP Interrupt Enable Register b Service the interrupt by reading converted data resident in the Mailbox Buffer of the IP330A Use the New Data Available register to identify valid Mailbox Buffer data C Clear the interrupting IP by writing a 1 to the appropriate bit in the AVME9630 60 IP Interrupt Clear register d Enable the interrupting IP by writing 1 t
20. the ID space per the IP module specification This area of memory contains 32 bytes of information at most Both fixed and variable information may be present within the ID space Fixed information includes the IPAC identifier model number and manufacturer s identification codes Variable information includes unique information required for the module The IP330A ID information does not contain any variable e g unique calibration information ID space bytes are addressed using only the odd addresses in a 64 byte block on the Big Endian VMEbus Even addresses are used on the Little Endian PC ISA bus The IP330A ID space contents are shown in Table 3 1 Note that the base address for the IP module ID space see your carrier board instructions must be added to the addresses shown to properly access the ID space Execution of an ID space read requires 1 wait state SERIES IP330A INDUSTRIAL I O PACK 16 BIT HIGH DENSITY ANALOG INPUT MODULE Table 3 1 IP330A ID Space Identification ID PROM Hex Offset From ID PROM Base Address ASCII Character Equivalent Numeric Value Acromag ID Code IP Model Code Not Used Revision Not Used Driver ID Low Byte Not Used Driver ID High Byte 3 15 0C Total Number of ID PROM Bytes E O a i9to3F 1 NotUsed Notes Table 3 1 1 The IP model number is represented by a two digit code within the ID space the IP330A model is represented b
21. the register contents are cleared upon reset DataBit 07 06 05 04 03 o2 ot oo SE or Ditt Ch 07 06 05 04 03 02 OO Missed Data Register Read Only 0CH DataBit 15 14 13 12 11 10 09 08 SEorDif Ch 15 14 13 12 11 10 09 O8 10 DataBit 07 06 05 04 03 02 o1 00 Diff Channel 07 06 05 04 03 02 O1 00 DataBit 15 14 13 12 11 10 09 08 Diff Channel 15 14 13 12 11 10 O9 O8 Start Convert Register Write Only 11H The Start Convert register is a write only register and is used to trigger conversions by setting data bit O of this register to a logic one The desired mode of data acquisition must first be configured by setting the following registers to the desired values and modes Control Interrupt Vector Timer Prescaler Conversion Timer Start Channel Value End Channel Value and Gain Select This register can be written with either a 16 bit or 8 bit data value Data bit O must be a logic one to initiate data conversions For the External Trigger Only mode the Software Start Convert bit is not used to start data acquisition However the Start Convert bit should be set prior to the first external trigger In this mode the Start Convert bit serves as a means for the hardware to identify the occurrence of the first External Trigger On the first external trigger give
22. to access the interrupt handling routine This example assumes that the IP330A is installed onto an Acromag AVME9630 60 carrier board consult your carrier board documentation for compatibility details Interrupt Programming Example with AVME9630 60 Carrier 1 Clear the global interrupt enable bit in the carrier board status register by writing a O to bit 3 2 Write the interrupt vector to the IP330A Module base address 03H 3 Write to the carrier board interrupt Level Register to program the desired interrupt level per bits 2 1 amp 0 4 Write 1 to the carrier board IP Interrupt Clear Register corresponding to the desired IP interrupt request being configured 5 Write 1 to the carrier board IP Interrupt Enable Register bit corresponding to the IP interrupt request to be enabled 6 Enable interrupts for the carrier board by writing a 1 to bit 3 the Global Interrupt Enable Bit of the carrier board s Status Register 7 Enable the IP330A for interrupt after each channel or after conversion of a group of channels by setting bits 12 and 13 of the Control register as required 8 Interrupts can now be generated after start of a scan mode of operation burst continuous or external trigger only General Sequence of Events for Processing an Interrupt 1 The IP330A asserts the Interrupt Request 0 Line INTREQO in response to an interrupt condition 2 The AVME9630 60 carrier board acts as an interrupter
23. to be used bit 2 of the Control register must be set low to accept the external trigger as an input signal When configured for differential input the Mailbox functions as a dual level data buffer However for Uniform Single Mode only one pass from the start channel to the end channel is implemented Thus only the first half of the Mailbox buffer is utilized As seen in Table 3 2 the first half of the Mailbox is defined by word addresses 40H to 5EH Interrupts can be enabled to activate after conversion of each channel or the group of channels as defined by the Start and End Channel Values If interrupts are configured to go active after the conversion of each channel the actual interrupt will be issued 8 usec after the programmed interval has lapsed If interrupt upon completion of a group of channels is selected an interrupt will be issued 5 psec after the interval time of the last selected channel has expired Burst Continuous Mode In burst continuous mode of operation conversions are continuously performed in sequential order from the channel defined by the Start Channel Value to the channel defined by the End Channel Value Within a group of channels the interval between conversions is fixed at 15 usec However the interval after conversion of a group of channels can be controlled by the interval timer Timer Prescaler and Conversion Timer Burst modes can be used to provide pseudo simultaneous sampling for many low to mediu
24. 0 PIN CONNECTOR 1004 512 LAM POLARIZING KEY PIN 1 STRAIN RELIEF 1004 534 4501 463A MOVd O I WIYLSNAGNI VOEEd I S3lHdS FINGOW LAdNI ALISN3G LIg 9L SERIES IP330A INDUSTRIAL I O PACK 16 BIT HIGH DENSITY ANALOG INPUT MODULE 1234 56 7 8 9 101112 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 45 44 45 46 47 48 49 50 P1 1254567 B 9 10 111213 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 55 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 MODEL 5025 552 TERMINATION PANEL SCHEMATIC TERMINATION a PANEL ACROMAG PART NUMBER 4201 040 al Ly EETHERERERER aki 3 032 77 0 TB1 le 5 315 135 0 TOP VIEW 2 4 6 B 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 f 3 5 7 9 1113 15 17 19 2123 25 27 29 31 33 35 37 39 41 43 45 47 49 2 203 D 58 5
25. ADC have significant offset and gain errors see specifications in chapter 6 which reveal the need for software calibration Calibrated Performance Very accurate calibration of the IP330A can be accomplished by using calibration voltages present on the board The four voltages and the analog ground reference are used to determine two points of a straight line which defines the analog input characteristic The calibration voltages are precisely adjusted at the factory to provide optimum performance as detailed in chapter 6 The calibration voltages are used with the auto zero signal to find two points that determine the straight line characteristic of the analog front end for a particular range The recommended calibration voltage selection for each range is summarized in Table 3 7 SERIES IP330A INDUSTRIAL I O PACK 16 BIT HIGH DENSITY ANALOG INPUT MODULE Equation 1 following is used to correct the actual ADC data i e the uncorrected bit count read from the ADC making use of the calibration voltages and range constants Corrected_Count Volta ALLO Gain Ideal Zero 65536 m Ideal Volt Span Actual Count 1 ER catol D Where m represents the actual slope of the transfer characteristic as defined in equation 2 m Gain 1 Gain Voltc A VoltcaLLo Hi CountcaLLo Ideal_Volt_Span Count_Actual Ideal_ Zero VoltcAr gr 7 VoltcAT 2 Countc A1 gp 7 Coun
26. Acromag 4 Series IP330A Industrial I O Pack 16 Bit High Density Analog Input Module USER S MANUAL ACROMAG INCORPORATED 30765 South Wixom Road P O BOX 437 Wixom MI 48393 7037 U S A Tel 248 624 1541 Fax 248 624 9234 Copyright 2007 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 804 A07F000 SERIES IP330A INDUSTRIAL I O PACK 16 BIT HIGH DENSITY ANALOG INPUT MODULE The information contained in this manual is subject to change without notice Acromag Inc makes no warranty of any kind with 6 0 5 20 regard to this material including but not limited to the implied e 2 warranties of merchantability and fitness for a particular purpose fs 5 Further Acromag Inc assumes no responsibility for any errors INDUSTRIAL UO PACK GOMPLIAINGE c codes 22 that may appear in this manual and makes no commitment to APPENDIX 2 Ie a a A a e 22 update or keep current the information contained in this manual NE GDL Dane ee F No part of this manual may be copied or reproduced in any form 7 without the prior written consent of Acromag Inc TRANSITION MODULE MODEL TRANS GP 22 DRAWINGS Page Table of Contents Page 4501 434 IP MECHANICAL ASSEMBLY 23 1 0 GENERAL
27. DMA control INTREQ1 ERROR and STROBE signals are not used A Field Programmable Gate Array FPGA installed on the IP Module provides an interface to the carrier board The interface to the carrier board allows complete control of all IP330A functions IP INTERFACE LOGIC IP interface logic of the IP330A is imbedded within the FPGA This logic includes address decoding I O and ID read write control circuitry and ID PROM implementation Address decoding of the six IP address signals A 1 6 is implemented in the FPGA in conjunction with the IP select signals to identify access to the IP modules ID or I O space In addition the byte strobes BS0 and BS1 are decoded to identify low byte high byte or double byte data transfers The carrier to IP module interface implements access to both ID and I O space via 16 or 8 bit data transfers Read only access to ID space provides the identification for the individual module as given in Table 3 1 per the IP specification Read and write accesses to the I O space provide a means to control the IP330A and retrieve newly converted data from the Mailbox buffer 18 Access to both ID and I O spaces are implemented with one wait state read or write data transfers There is one exception on a rare occasions read and write operations to the Mailbox buffer may contend Since the Mailbox buffer is not implemented as a dual port memory simultaneous read and write access to RAM is not possi
28. O DCH00 i ZW EET DCH01 a CQ CH1 1 DCH1 nue l SSS ais E DCH15 A qv CH15 1 DCH15 idt ANALOG COMMON i EARTH CROUND oe Y ES nd SEE NOTE 2 TYPICAL V gw 7 SINGLE ENDED VOLTAGE INPUT CONNECTION DIAGRAM B3 os 5 4 CHO eS SCHOO Eso HE CH1 SCH 1 d eJ A i cH32 SCH32 Da ES32 R A ANALOG COMMON 4 EARTH GROUND CONNECTION AT Vai SEE NOTE 2 Y SHIELD I 4 vA AE alles SEE NOTE 1 1 SHIELDED CABLE IS RECOMMENDED FOR LOWEST NOISE SHIELD IS CONNECTED TO GROUND REFERENCE AT ONE END ONLY TO PROVIDE SHIELDING WITHOUT GROUND LOOPS CONNECTED TO ANALOG COMMON 2 REFERENCE CHANNELS TO ANALOG COMMON IF THEY WOULD OTHERWISE BE FLOATING CHANNELS ALREADY 4 DIFFERENTIAL VOLTAGE INPUT CONNECTIONS ARE RECOMMENDED OVER SINGLE ENDED TO ACHIEVE HAVING A GROUND REFERENCE MUST NOT BE CONNECTED TO ANALOG COMMON TO AVOID GROUND LOOPS THE GREATEST ACCURACY AND LOWEST NOISE 3 EXTERNAL SUPPLIES CAN BE USED BY JUMPERING IT IS RECOMMENDED THAT THE SUPPLY COMMONS BE MOVd O I WIYLSNAGNI VOEEd I SAIWAS FINGOW LAdNI ALISN3G LIg 9L 1 n2 ANALOG INPUT CHANNELS
29. O connections are not isolated from the carrier board and backplane Care should be taken in designing installations without isolation to avoid noise pickup and ground loops caused by multiple ground connections This is particularly important for analog inputs when a high level of accuracy resolution is needed Contact your Acromag representative for information on our many isolated signal conditioning products that could be used to interface to the IP330A input module External Trigger Input Output The external trigger signal on pin 49 of the P2 connector can be programmed to input a TTL compatible external trigger signal or output IP330A hardware generated triggers to allow synchronization of multiple IP330As As an input the external trigger must be a 5 Volt logic TTL compatible debounced signal referenced to analog common The external trigger signal is an active low edge sensitive signal That is the external trigger signal will trigger the IP330A hardware on the falling edge Once the external trigger signal has been driven low it should remain low for a minimum of 500n seconds As an output an active low TTL signal can be driven to additional IP330As thus providing a means to synchronize the conversions of multiple IP330As The additional IP330As must program their external trigger for signal input and convert on external trigger only mode See section 3 0 for programming details to make use of this signal IP Logic Interfac
30. T TYPE SWITCH SETTINGS ON UT RANGE SELECTION DIP Switch Settings SWITCH SETTINGS OFF 5 900 020 POWER SUPPLY SELECTIONS PINS OF J1 AND J2 POWER SUPPLY SELECTION 12 VOLT INTERNAL P1 5 TO 5 10 Bipolar 1 3 4 9 2 5 6 7 8 15 VOLT EXTERNAL P2 10 TO 10 Bipolar 2 5 6 9 1 3 4 7 8 INTERNAL AND EXTERNAL SUPPL 5 Unipo 1 3 5 8 2 4 6 7 9 ES SHOULD NOT BE MIXED E G DO NOT USE 12 VOLTS WITH 15 VOLTS THE BOARD IS SHIPPED WITH TH 9 TO c 10x ASSUMING A GAIN OF 1 THE BOARD IS SHIPPED WITH THE DEFAULT DIP SWITCH SETTING FOR THE 5 TO 5 VOLT RANGE AS SHOWN IN THE ABOVE DIAGRAM xxx THESE RANGES CAN ONLY BE ACHIEVED WI 15 VOLT EXTERNAL POWER SUPPLIES Unipo TH THE 1 5 4 7 ADC INPUT INPUT RANGES WILL CLIPPED IF 14 12 VOLT SUPPLIES ARE USED TYPICALLY TO 8 5 VOLT MAXIMUM INPUTS 2 5 6 8 9 THE DIAGRAM ABOVE IP 5 50A JUMPER LOCATIONS E DEFAULT JUMP 450 ER SETTING FOR 12 VOLT SU 2 045A PPLIES AS SHOWN IN MOVd O I WIYLSNAGNI VOEEd I S3lHdS FINGOW LAdNI ALISN3G LIg 9L Qo A DIFFERENTIAL VOLTAGE INPUT CONNECTION DIAGRAM IP330A CARRIER BOARD SEE NOTE 4 P2 CN ON s ESO DCHOO xa CY CH
31. T HIGH DENSITY ANALOG INPUT MODULE Analog Inputs Noise and Grounding Considerations Differential inputs require two leads and per channel and provide rejection of common mode voltages This allows the desired signal to be accurately measured However the signal being measured cannot be floating It must be referenced to analog common on the IP module and be within the normal input voltage range Differential inputs are the best choice when the input channels are sourced from different locations having slightly different ground references and when minimizing noise and maximizing accuracy are key concerns See Analog Input Connection in the Drawing Section for analog input connections for differential and single ended inputs Shielded cable of the shortest length possible is also strongly recommended Single ended inputs only require a single lead per channel with a shared sense reference lead for all channels and can be used when a large number of input channels come from the same location e g printed circuit board The channel density doubles when using single ended inputs and this a powerful incentive for their use However caution must be exercised since the single sense lead references all channels to the same common which will induce noise and offset to the degree they are different The IP330A is non isolated since there is electrical continuity between the logic and field I O grounds As such the field I
32. Voltage Input 100 2 4500v Calibration Voltage Input 101 1 2250v Calibration Voltage Input 110 0 6125v Calibration Voltage Input 111 Auto Zero Calibration Voltage Input Scan Mode 000 Disable 001 Uniform Continuous 010 Uniform Single 011 Burst Continuous 100 Burst Single 101 Convert on External Trigger Only 110 Not Used 111 Not Used BT L9 0 1 Output It is possible to synchronize the data acquisition of multiple IP330A modules A single master IP330A module must be selected to output the external trigger signal while all other IP330A modules are selected to input the external trigger signal The external trigger signal pin 49 of the field I O connector must also be wired together u Acquisition Input Mode F 35865 10 9 8 See the Modes of Operation section for a description of each of these scan modes 000 All Channels Differential Input 11 Timer Enable FUNCTION 0 Disable 1 Enable Interrupt Control 00 Disable Interrupts 01 Interrupt After Convert of Each Channel 10 Interrupt After Conversion of all selected channels is completed A group of channels includes all channels from the Start Channel up to and including the End Channel value 11 Disable Interrupts 14 15 Notes Table 3 3 1 All bits labeled Not Used will return on a read access the last value written Analog Input Ranges and Corresponding Digital Output Code Selection of an analog
33. X Schematic and Physical Attributes See Drawing 4501 465 Field Wiring 50 pin header male connectors 3M 3433 D303 or equivalent employing long ejector latches and 30 micron gold in the mating area per MIL G 45204 Type II Grade C Connects to Acromag termination panel 5025 552 from the rear of the card cage or to AVME9630 9660 9668 boards within card cage via flat 50 pin ribbon cable cable Model 5025 550 X or 5025 551 X Connections to AVME9630 9660 50 pin header male connectors 3M 3443 1302 or equivalent employing long ejector latches and 30 micron gold in the mating area per MIL G 45204 Type Il Grade C Connects to AVME9630 9660 boards within the card cage via flat 50 pin ribbon cable cable Model 5025 550 X or 5025 551 X Transition module is inserted into a 6U size single width slot at the rear of the VMEbus card cage Mounting Transition module is inserted into a 6U size single width slot at the rear of the VMEbus card cage Printed Circuit Board Military grade FR 4 epoxy glass circuit board 0 063 inches thick Operating Temperature 40 C to 85 C Storage Temperate 55 C to 105 C M2 x 6 A Cy FLAT HEAD SCREW lane SIDE OF IP MODULE I THREADED M2 COMPONENT SIDE SPACER OF CARRIER BOARD Hh 4 j B m E Mus P1 CONNECTOR FRONT PANEL CONNECTOR OB H9 M2 x 6 PAN HEAD SCREW
34. actual data will be converted using uniform single mode From Tables 3 7 and 3 8 several calibration parameters can be determined Preselect 0 to 10v ADC Range via hardware DIP switch Gain 8 From Table 3 7 Volto A 1 2250 volts CAL2 From Table 3 7 VoltcA 0 6125 volts CAL3 From Table 3 7 Ideal Volt Span 10 0000 volts From Table 3 8 Ideal Zero 0 0000 volts From Table 3 8 SERIES IP330A INDUSTRIAL I O PACK 16 BIT HIGH DENSITY ANALOG INPUT MODULE The 0 to 5v ADC range could alternatively be used with a gain of 4 This approach may reduce the affect of noise over the ADC range and gain selected in this example The calibration parameters Countc A jjj and Countc a o remain to be determined before uncorrected input channel data can be taken and corrected Determination of the CountcA Value 1 Execute Write of 0432H to Control Register at Base Address OOH a Select Straight Binary External Trigger Input Select 0 6125v Calibration Voltage Burst Single Scan Mode Timer Disabled Interrupts Disabled 2 Execute Write of 1FOOH to End Start Channel Value Register at Base Address 06H This will permit 32 conversions of the calibration voltage to be stored in the 32 Mailbox Buffers 3 Execute Write of 03H as byte data transfers only to Gain Select Channel Registers Base Address 20H to 3FH This selects a gain of eight for all 32 channels 4 Exe
35. alue Corrected Count can be calculated for each of the channels 18 If channel response time requirements are not high speed it is recommended that a running average i e of the last 8 16 32 etc of readings be maintained for each channel This will minimize noise effects and provide the best accuracy Error checking should be performed on the Corrected Count value to make sure that calculated values below 0 or above 65 535 are restricted to those end points Note that the software calibration cannot recover signals near the end points of each range which are clipped off due to the uncalibrated hardware e g PGA and ADO or power supply limitations See the specification chapter for details regarding the maximum corrected i e calibrated error SERIES IP330A INDUSTRIAL I O PACK 16 BIT HIGH DENSITY ANALOG INPUT MODULE Programming Interrupts Interrupts can be enabled for generation after conversion of individual channels or after a group of channels have been converted Interrupts generated by the IP330A use interrupt request line INTREQO Interrupt Request 0 The interrupt release mechanism is Release On Acknowledge ROAK type That is the IP330A will release the INTREQO signal during an interrupt acknowledge cycle from the carrier The IP330A Interrupt Vector register can be used as a pointer to an interrupt handling routine The vector is an 8 bit value and can be used to point to any one of 256 possible locations
36. ate the last channel in a sequence to be converted When scanning all channels between and including the start and end channels are converted A single channel can be selected by writing the desired channel value in both the Start and End Channel Value registers The End Channel Value register can be read or written with 8 bit data transfers In addition the End Channel Value register can be simultaneously accessed with the Start Channel Value with a 16 bit data transfer The unused data bits are zero when read The register contents are cleared upon reset End Channel Value Register 15 14 13 12 ti 10 09 08 SERIES IP330A INDUSTRIAL I O PACK 16 BIT HIGH DENSITY ANALOG INPUT MODULE New Data Registers Read Only 08H to OBH The New Data registers can be read to determine which channels of the Mailbox buffer contain new converted data A set bit in the New Data register indicates that the Mailbox buffer corresponding to the channel of the set bit contains new converted data A set New Data register bit is cleared upon a read of its corresponding Mailbox buffer The New Data bits are also cleared at the start of all new data acquisition cycles initiated with either the Software Start Convert command or an external trigger This is done to avoid mistaking data from an old scan cycle with that of a new scan cycle The New Data registers can be read via 16 bit or 8 bit data transfers In addition the register cont
37. ble If a read access to the RAM is initiated simultaneously with an internal RAM write for update of the Mailbox buffer with ADC data the read access will be held until after the write operation has completed Thus the read operation from RAM Mailbox may require up to six waits to avoid contention with an internal write cycle IP330A CONTROL LOGIC All logic to control data acquisition is imbedded in the IP s FPGA The control logic of the IP330A is responsible for controlling the operation of a user specified sequence of data acquisitions Once the IP330A has been configured the control logic performs the following Controls the channel multiplexers based upon start and end channel values and single ended or differential analog input mode e Selects channel gain at the programmable gain amplifier corresponding to the current channel e Controls data conversion at the A D Converter based on one of five different scan modes of operation Controls data transfer from the A D Converter to the FPGA s 16 bit serial shift register e Controls and updates the Mailbox buffer New Data register and Missed Data register Stops data acquisition for Single Cycle Scan modes Provides external or internal trigger control Controls the interval between data conversions Issues interrupt requests to the carrier INTERNAL CHANNEL POINTERS Internal counters in the FPGA are used as pointers to control the multiplexers for selection of
38. ch IP module has its own 8 bit ID signature which can be read via access to the ID space e 16 bit and 8 bit I O Port register Read Write is performed through data transfer cycles in the IP module I O space e High Speed Access times for all data transfer cycles are described in terms of wait states 1 wait state is required for reading and writing all control registers and ID values Interrupt select cycles also require 1 wait state for reading the interrupt vector Read of the Mailbox Buffers typically requires 1 wait state but to avoid contention with an ongoing memory write cycle could require from 1 to 6 wait states see Specifications section for detailed information SIGNAL INTERFACE PRODUCTS See Appendix for more information on compatible products This IP module will mate directly to any industry standard IP carrier board including Acromag s AVME9630 60 70 75 VMEbus APC8620A 21A PCI bus and ACPC8625 30 35 Compact PCI bus non intelligent carrier boards A wide range of other Acromag IP modules are also available to serve your signal conditioning and interface needs The cables and termination panels described in the following paragraphs represent some of the accessories available from Acromag Each Acromag carrier has its own unique accessories They are not all listed in this document Consult your carrier board documentation for the correct interface product part numbers to ensure compatibility with your carrier boa
39. channels selected for scanning are digitized once at a 66 7 kHz conversion rate 15 usec Channel The scan is initiated by a software or external trigger e External Trigger Scan Mode A single channel is digitized with each external trigger Successive channels are digitized in sequential order with each new external trigger This mode allows synchronization of conversions with external events that are often asynchronous e External Trigger Output The external trigger is assigned to a field I O line This external trigger may be configured as an output signal to provide a means to synchronize other IP330A s or devices to a single IP330A s on board timer reference e User Programmable Gain Amplifier Provides independently software controlled gains 1 2 4 and 8 V V for each of the 16 differential or 32 single ended channels e Precision On Board Calibration Voltages Calibration autozero and autospan precision voltages are available to permit host computer correction of conversion errors Trimmed calibration voltages include 0 V local analog ground 0 6125 V 1 225 V 2 45 V and 4 9 V e Hardware DIP Switch For Selection of A D Ranges Both bipolar 5 V 10 V and unipolar 0 to 5 V and 0 to 10 V ranges are available Selected range applies to all channels and can not be individually selected on a per channel basis e New Data Register This register can be polled to indicate when new digitized data is available in the Mai
40. cute Write 0001H to the Start Convert Bit at Base Address 10H to start burst single mode conversions Thirty two conversions of the calibration voltage are implemented and stored in the 32 Mailbox Buffers 5 Execute Read of the 32 Mailbox Buffers at Base Address 40H to 7EH 6 Take the average of the 32 ADC values and save this number as CountcA o Determination of the Countc A Value 7 Execute Write of 042AH to Control Register at Base Address OOH a Select Straight Binary External Trigger Input Select 1 2250v Calibration Voltage Burst Single Scan Mode Timer Disabled Interrupts Disabled 8 Writing the Start Channel Value End Channel Value and the Gain Selects is not necessary if they have not been changed from that programmed in steps 2 and 3 above 9 Execute Write 0001H to the Start Convert Bit at Base Address 10H This starts a burst single mode of conversions Thirty two conversions of the 1 2250 calibration voltage are implemented and stored in the 32 Mailbox Buffers Execute Read of the 32 Mailbox Buffers at Base Address 40H to 7EH 11 Take the average of the 32 ADC values and save this number as Countca 16 Calculate Equation 2 Calculate m actual slope from equation 2 since all parameters are known It is now possible to correct input channel data from any input channel using the same input range i e 0 to 1 25 volts with a PGA gain
41. d separately To facilitate the development of Windows 98 Me 2000 XP applications accessing Industry Pack modules installed on Acromag PCI Carrier Cards and CompactPCI Carrier Cards This software Model IPSW API WIN consists of low level drivers and Windows 32 Dynamic Link Libraries DLLS that are compatible with a number of programming environments including Visual C Visual Basic Borland C Builders and others The DLL functions provide a high level interface to the carriers and IP modules eliminating the need to perform low level reads writes of registers and the writing of interrupt handlers IP MODULE VxWorks DRIVER SOFTWARE Acromag provides a software product sold separately consisting of board VxWorks software This software Model IPSW API VXW is composed of VxWorks real time operating system libraries for all Acromag IP modules and carriers including the AVME9670 AVME9600 9630 APC8620A 21A ACPC8630 35 and ACPC8625 The software is implemented as a library of C functions which link with existing user code to make possible simple control of all Acromag PCI boards IP MODULE QNX SOFTWARE Acromag provides a software product sold separately consisting of board QNX software This software Model IPSW API QNX is composed of QNX real time operating system libraries for all Acromag IP modules and carriers including the AVME9670 AVME9660 9630 APC8620A 21A ACPC8630 35 and ACPC 8625 The software support
42. e Connector P1 P1 of the IP module provides the logic interface to the mating connector on the carrier board This connector is a 50 pin female receptacle header AMP 173279 3 or equivalent which mates to the male connector of the carrier board AMP 173280 3 or equivalent This provides excellent connection integrity and utilizes gold plating in the mating area Threaded metric M2 screws and spacers are supplied with the IP module to provide additional stability for harsh environments see Drawing 4501 434 for assembly details Field and logic side connectors are keyed to avoid incorrect assembly The pin assignments of P1 are standard for all IP modules according to the Industrial I O Pack Specification see Table 2 4 Table 2 4 Standard Logic Interface Connections P1 Pin Description Number Pin Description Number 6 4 29 Doe 6 memset 3 D4 8 mse 33 505 9 DMWack 34 pos 10 os 35 o7 it 1 RESERVED 36 on s S ERROR o D2 6e a 53 11 1 Rer 42 o Da Bs m _ s is ie wear a Bso 2 a Bs 21 STROBE 46 aw 2 47 29 acw 48 An Asterisk is used to indicate an active low signal BOLD ITALIC Logic Lines are NOT USED by this IP Model 3 0 PROGRAMMING INFORMATION IP IDENTIFICATION PROM Read Only 32 Odd Byte Addresses Each IP module contains identification ID information that resides in
43. e factory it is configured as follows e Analog input range is configured for a bipolar input with a 10 volt span i e an ADC input range of 5 to 5 Volts e Internal 12 and 12 Volt power supplies are used sourced from P1 connector e The default programmable software control register bits at power up are described in section 3 The control registers must be programmed to the desired gain mode and channel configuration before starting ADC analog input acquisition Analog Input Range Hardware Jumper Configuration Power should be removed from the board when installing IP modules cables termination panels and field wiring Refer to the IP Mechanical Assembly Drawing located in the Drawings Section of this manual and the following discussion for configuration and assembly instructions Table 2 1 Analog Input Range Selections DIP Switch Settings Desired Required Required Switch Switch ADC Input Input Span Input Settings Settings Range Volts Type ON OFF VDC control of these functions These control registers must also be configured as desired before starting ADC analog input acquisition Refer to section 3 for programming details CONNECTORS IP Field I O Connector P2 P2 provides the field I O interface connections for mating IP modules to the carrier board P2 is a 50 pin female receptacle header which mates to the male connector of the carrier board This provides excellent connection integrity and utilizes gold
44. ed to activate after conversion of each channel or the group of channels as defined by the Start and End Channel Values If interrupts are configured to go active after the conversion of each channel the actual interrupt will be issued every 15 usec If interrupt upon completion of a group of channels is selected an interrupt will be issued 20 usec after conversion of the last channel in the group has started At this time 15 usec between interrupts is not sufficient time to perform back to back interrupt acknowledge cycles on the VME and PC platforms Thus interrupting after each channel is converted cannot be recommended Burst Single Mode In burst single mode of operation conversions are performed once for all channels in sequential order starting with Start Channel and ending with the End Channel The interval between conversions of each channel is fixed at 15 usec The interval timer has no functionality in this mode of operation After software selection of the burst single mode of operation conversions are started either by an external trigger or by setting the software start convert bit If the external trigger is to be used bit 2 of the Control register must be set low to accept the external trigger as an input signal When configured for differential input the Mailbox functions as a dual level data buffer However for Burst Single Mode only one pass from the start channel to the end channel is implemented Thus only the
45. elect Binary Codes Gain Data Bits 7 to 2 Data Bit 1 Data Bit 0 1 3 o 1 4 Unsa 1 0o 8 Unsa ue 1 The Gain Select register contents are set to 00 upon power up or system reset The Gain Select registers corresponding to all channels selected for conversion must be written with the desired gain select binary codes prior to initializing data conversions This register can be written with either a 16 bit or 8 bit data value Mailbox Buffer Read Only 40H 7EH The Mailbox Buffer is read only and contains 16 bit digitized input channel values The Mailbox Buffer has 32 storage locations one for each of the 32 channels supported by the IP330A in the single ended mode of operation If the IP330A is used in the differential mode of operation each of the 16 channels supported are allocated two Mailbox Buffer locations See Table 3 2 which gives the Mailbox Buffer address locations corresponding to each of the 32 channels or 16 channels in differential mode In differential mode the first digitized data values will be stored in buffer locations 40H to 5FH while the second digitized values are stored in buffer locations 60H to 7EH The storage of data in the Mailbox in differential mode will continue to alternate between these two Mailbox sections The New Data register can be read to determine which Mailbox Buffers contain updated digitized data A set bit in the N
46. ents are cleared upon reset New Data Register Read Only 09H DataBit 07 o6 o5 o4 o3 o2 ot oo SE or Diff Ch 1 o7 06 05 04 03 o2 o1 00 New Data Register Read Only 08H 15 14 13 12 11 10 09 08 Data Bit SE or Diff Ch 15 14 13 12 11 10 09 08 New Data Register Read Only 0 15 15 Data Bit 07 06 05 04 03 02 ot 00 SE Channel Diff Channel 07 06 05 04 03 02 01 00 New Data Register Read Only 0AH Data Bit 15 14 13 12 11 10 09 08 SE Channel Diff Channel 15 14 13 12 11 10 09 O8 Missed Data Registers Read Only OCH to OFH The Missed Data registers can be read to determine if a channel s Mailbox buffer has been overwritten with new converted data before the last converted value was read A set bit in the Missed Data register indicates a converted value corresponding to the channel of the set bit was overwritten before being read A set Missed Data register bit is cleared upon a read of its corresponding Mailbox buffer The Missed Data bits are also cleared at the start of all new data acquisition cycles initiated with either the Software Start Convert command or an external trigger This is done to avoid mistaking missed data from an old scan cycle with that of a new scan cycle The Missed Data registers can be read via 16 bit or 8 bit data transfers In addition
47. es ADC Ideal Volt Ideal Range Span Zero Volts Volts Volts RUNI on t 10to 10 20 0000 10 0000 aes CENE ONSE NS DNE ee ee or perc ee eee ee a Input Range PGA Volts Gain 5 to 5 1 2 5 to 2 5 1 25 to 1 25 10 to 10 5 to 5 2 5 to 2 5 1 25 to 1 25 0 to 5 0 to 42 5 0 to 1 25 0 to 40 625 0 to 10 0 to 5 0 to 42 5 0 to 1 25 10 0000 The calibration parameters Countc A and Countc a o for each active input range should not be determined immediately after startup but after the module has reached a stable temperature and updated periodically e g once an hour or more often if ambient temperatures change to obtain the best accuracy Note that several readings e g 64 of the calibration parameters should be taken via the ADC and averaged to reduce the measurement uncertainty since these points are critical to the overall system accuracy Calibration Programming Example 1 Assume that the desired input range is 10 to 10 volts select desired input range via hardware DIP switch Channels 0 to 3 are connected differentially and corrected input channel data is desired From Tables 3 7 amp 3 8 several calibration parameters can be determined Gain 1 From Table 3 7 Voltc A 4 9000 volts CALO From Table 3 7 V
48. etween conversions is controlled by the interval timer 11 Timer Prescaler and Conversion Timer as described in the Conversion Timer Register section The interval timer must be used in this mode of operation After software selection of the uniform continuous mode of operation conversions are started either by an external trigger or by setting the software start convert bit If the external trigger is to be used bit 2 of the Control register must be set low to accept the external trigger as an input signal Stopping the execution of uniform continuous conversions is possible by writing 000 to the Scan Mode bits 8 10 of the Control register See the Control register section for additional information on the Scan Mode control bits and the Control register board address location When configured for differential input the Mailbox functions as a dual level data buffer The first half of the Mailbox is used to store all selected channel data for the initial pass through the channels defined by the Start and End Value registers The second half of the Mailbox is then used to store the channel data corresponding to the second pass though all selected channels Storage of channel data continues to alternate between the first and second halves of the Mailbox Buffer As seen in Table 3 2 the first half of the Mailbox is defined by word addresses 40H to 5EH while the second half is defined by word addresses 60H to 7EH Interrupts can be e
49. ew Data register indicates an updated digitized data value resides in its corresponding Mailbox Buffer In addition the Missed Data register can be read to determine if a Mailbox Buffer has been overwritten with a new digitized value before the previous one had been read A set bit in the Missed Data register indicates that a digitized data value has been lost or overwritten All register accesses to the IP330A require one wait state with the exception of a read access to the Mailbox Buffer A read access to the Mailbox Buffer could take up to six wait states if a read is issued while a hardware write of channel data to the same Mailbox is currently underway Most of the time contention with hardware writes is not an issue In which case one wait state is required for a read access to the Mailbox MODES OF OPERATION The IP330A provides five different modes of analog input acquisition to give the user maximum flexibility for each application These modes of operation include uniform continuous uniform single burst continuous burst single and convert on external trigger only In all modes a single channel or a sequence of channels may be converted The following sections describe the features of each and how to best use them Uniform Continuous Mode In uniform continuous mode of operation conversions are performed continuously in sequential order for all channels between and including the Start and End Channel Values The interval b
50. f the cal voltage reference 15 ppm C for E Version plus the 5 ppm 9C drift of the resistors in the voltage divider Calibration Signal 24 Maximum Overall Calibrated Error 2 25 C The maximum corrected i e calibrated error is the worst case accuracy possible It is the sum of error components due to ADC quantization of the low and high calibration signals PGA and ADC linearity error and the absolute errors of the recommended calibration voltages at 25 C Max LSB ADC Range Typ Err LSB Input Range Volts Volts Span Span 5 to 5 5 to 5 8 6 LSB 2 LSB 0 013 0 003 Note 7 A total of 256 input samples autozero values and calibration voltages were averaged with a throughput Rate of 67 kHz conversions second Follow the input connection recommendations of Section 2 because input noise and non ideal grounds can degrade overall system accuracy For critical applications multiple input samples should be averaged to improve performance Accuracy versus temperature depends on the temperature coefficient of the calibration voltage Settling Time 20V step 3 5 uS to 0 01 Typical PGA A D Conversion Time 5 uS Maximum Conversion Rate 200 kHz Maximum Recommended Conversion Rate 67 kHz A D External and Software Input Noise 2 LSB rms Typical
51. gth esses 3 880 inches 98 5 mm 1 780 inches 45 2 mm Board Thickness 0 062 inches 1 59 mm Max Component Height 0 314 inches 7 97 mm Connectors P1 IP Logic Interface 50 pin female receptacle header AMP 173279 3 or equivalent P2 Field l O 50 pin female receptacle header AMP 173279 3 or equivalent Power Requirements 5 Volts 5596 65 mA Typical 200 mA Maximum 12V 4 15V 5 14 mA Typical 20 mA Maximum 12V 15V 4550 11 mA Typical 15 mA Maximum Note 2 The 12 volt power supplies are normally supplied through P1 logic interface connector Optionally jumper selectable on the IP the user may connect external 15 volt supplies through the field I O interface connector P2 Non Isolated Logic and field commons have a direct electrical connection ANALOG INPUTS Input Channels Field Access 32 Single ended or 16 Differential Input Signal Voltage Non isolated Input Ranges DIP switch selectable Bipolar 5 to 5 Volts Bipolar 10 to 10 Volts Unipolar 0 to 5 Volts Unipolar 0 to 10 Volts Notes 3 Range assumes the programmable gain is equal to one Additional ranges are created with other gains Divide the listed range by the programmable gain to de
52. hannel Value Register at Base Address 06H This will permit conversions of channels 0 to 3 Writing the Gain Selects is not necessary since they do not need to change from that programmed in step 3 above 14 Execute Write 0001H to the Start Convert Bit at Base Address 10H This starts the burst single mode of conversions Conversions of channels 0 to 3 are implemented and corresponding results are stored in the first four Mailbox Buffer locations at Base Address 40H to 46H 15 Execute Read of the 4 Mailbox Buffers at Base Address 40H to 46H The data represents the uncorrected Count_Actual term in equation 1 Since all parameters on the right hand side of equation 1 are known calculate the calibrated value Corrected_Count This is the desired corrected value Repeat this procedure for each of the channels 16 If channel response time requirements are not high speed it is recommended that a running average i e of the last 8 16 32 etc of readings be maintained for each channel This will minimize noise effects and provide the best accuracy Calibration Programming Example 2 Assume that the desired input range is 0 to 1 25 volts selection of the desired input range is implemented via hardware DIP switch Channels 3 to 13 are connected single ended and corrected input channel data is desired The calibration voltages are converted using burst single mode for quick conversion of the calibration voltages while the
53. he Mailbox buffer In addition the FPGA logic also automatically generates the required flush convert signals to obtain the last converted data value from the A D Converter EXTERNAL TRIGGER The external trigger connection is made via pin 49 of the P2 Field I O Connector For the Burst and Continuous scan modes the falling edge of the external trigger will start data acquisition which will then be controlled by the FPGA For External Trigger Only mode each falling edge of the external trigger causes a conversion at the A D Converter Once the external trigger signal has been driven low it should remain low for minimum of 500n seconds TIMED PERIODIC TRIGGER CIRCUIT Timed Periodic Triggering is provided by two programmable counters an 8 bit Timer Prescaler and a 16 bit Conversion Timer The Timer Prescaler is clocked by the 8MHz board clock The output of the Timer Prescaler counter is then used to clock the second counter Conversion Timer In this way the two counters are cascaded to provide variable time periods anywhere from 8 usec to 2 0889 seconds The output of the second counter is used to trigger the start of new A D conversions for the Uniform Scan modes of operation For the Burst Continuous mode the interval between conversions of each channel is fixed at 15 usec However the interval between the group burst of channels can be controlled by the Interval Timer 19 INTERRUPT CONTROL LOGIC The IP330A can be co
54. input range is implemented via the DIP switch setting given in Table 2 1 The ideal input voltage corresponding to each of the supported input ranges is given in Table 3 4 Then in Table 3 5 the digital output code corresponding to each of the given ideal analog input values is given in both binary two s complement and straight binary formats Table 3 4 SESCAPTON T Full Scale Ranges and Ideal Analog Input DESCRIPTION ANALOG INPUT LSB Least 305uV 158 153 nV Significant Bit Weight Full Scale 9 999695 9 999847 4 999847 4 999924 Midscale Volts Volts The digital output format is controlled by bit 1 of the Control register The two formats supported are Binary Two s Complement and Straight Binary The hex codes corresponding to these two data formats are depicted in Table 3 5 Table 3 5 Digital Output Codes and Poe IGITAL OUTPUT Voltages DIGITALOUTPUT OUTPUT Binary 2 s Comp Straight Binary DESCRIPTION Hex Code Hex Code Interrupt Vector Register Read Write 03H The Vector Register can be written with an 8 bit interrupt vector This vector is provided to the carrier and system bus upon an active INTSEL cycle Read or writing to this register is possible via 16 bit or 8 bit data transfers 16 bit data transfers will SERIES IP330A INDUSTRIAL I O PACK 16 BIT HIGH DENSITY ANALOG INPUT MODULE implement simultaneous access the Interrupt Vector and Timer Prescaler registers The regi
55. isters EXTERNAL n 2 19 are available for each of the 16 differential channels If TIMED PERIODIC TRIGGER CIRCUIT 19 configured for 32 single ended channels one storage buffer INTERRUPT CONTROL LOGIC 19 register is available for each of the 32 channels 5 0 SERVICE AND e 20 e interrupt Upon Conversion Complete Mode May be SERVICE AND REPAIR ASSISTANCE 20 programmed to interrupt upon completion of conversion for PRELIMINARY SERVICE PROCEDURE 20 each individual channel or upon completion of conversion of WHERE 20 the group of all scanned channels SERIES IP330A INDUSTRIAL I O PACK 16 BIT HIGH DENSITY ANALOG INPUT MODULE 9 Programmable Control of Channel Scanning Scan all channels or a subset of the channels to allow an overall higher sample rate The channels digitized include all sequential channels beginning with a specified start channel value and ending with a specified end channel value e User Programmable Interval Timer Controls the delay between each channel converted when Uniform Continuous or Single Scan modes are selected If Burst Continuous is selected the Interval Timer controls the delay after a group of channels are converted before conversion is initiated on the group again Supports a minimum interval of 5 usec and a maximum inter
56. itch selection should be made prior to powering the unit Thus all channels will use the same A D Converter range However the analog input range can vary on an individual channel basis depending on the programmable gain selection The logic interface provides 12 Volt supplies to the analog circuitry The 10 to 10 and 0 to 10 Volt A D Converter ranges will be clipped if these supplies are used typically to 8 5 Volt maximum inputs The user has the option of providing 15 Volt external supplies to fully utilize input ranges to 10 Volts These supplies are selected via hardware jumpers J1 and J2 as detailed in section 2 Jumper selection should be made prior to powering the unit Internal and external supplies should not be mixed e g do not use 12 Volts with 15 Volts When selecting supplies low noise linear supplies are preferred All supplies should switch ON or OFF at the same time The board contains four precision voltage references and a ground autozero reference for use in calibration These provide considerable flexibility in obtaining accurate calibration for the desired A D Converter range and gain combination when compared to fixed hardware potentiometers for offset and gain calibration of the A D Converter and PGA LOGIC POWER INTERFACE The logic interface to the carrier board is made through connector P1 refer to Table 2 4 The P1 interface also provides 5V and 12V power to the module Note that the
57. l which can be programmed to occur is 40 1 8 8 usec This minimum of 8 usec is defined by the minimum conversion time of the hardware but does sacrifice conversion accuracy To achieve specified conversion accuracy a minimum conversion time of 15 usec is recommended see the specification chapter for details regarding accuracy Start Channel Value Register Read Write 07H The Start Channel Value register can be written with a 5 bit value to select the first channel that is to be converted once conversions have been triggered All channels between the start and end channel values are converted A single channel can be selected by writing the desired channel value in both the Start and End Channel Value registers The Start Channel Value register can be read or written with 8 bit data transfers In addition the Start Channel Value register can be simultaneously accessed with the End Channel Value via a 16 bit data transfer The unused bits are zero when read The register contents are cleared upon reset Start Channel Value Register 7 06 05 04 08 o2 o0 After running data conversions are halted the internal hardware pointers are reinitialized to the start channel value Thus when conversions are started again the first channel converted is defined by the Start Channel Value register End Channel Value Register Read Write 06H The End Channel Value register can be written with a 5 bit value to indic
58. lbox A set bit indicates a new digitized data value is available in the bit s corresponding Mailbox register Register bits are cleared upon read of their corresponding Mailbox register or start of a new scan cycle e Missed Data Register A set bit in the Missed Data Register indicates that the last digitized value was not read by the host computer quickly enough and has been overwritten by a new conversion The Missed Data Register has a bit corresponding to each of the 16 differential or 32 single ended channels Each Missed Data Register bit is cleared by a read of its corresponding Mailbox data value or start of a new scan cycle e User Programmable Data Output Format Software control provides selection of straight binary or binary two s complement data output format e Hardware Jumpers For Selection of Internal or External Supply Hardware jumper provide a means to select internal 12 volts or external 15 volt supplies External supplies are required when using inputs exceeding 8 5 volts e Fault Protected Input Channels Analog input overvoltage protection from 35 V to 55 V is provided in the event of power loss or power off INDUSTRIAL I O PACK INTERFACE FEATURES e High density Single size industry standard IP module footprint Four units mounted on a carrier board provide up to 64 differential or 128 single ended channels in a single system slot Both VMEbus and ISA bus PC AT carriers are supported e LocalID Ea
59. ly mode of operation in which the Start Convert bit does not cause data conversions When configured for differential input the Mailbox functions as a dual level data buffer The first half of the Mailbox is used to store all selected channel data for the initial pass through the channels defined by the Start and End Value registers The second half of the Mailbox is then used to store the channel data corresponding to the second pass though all selected channels Storage of channel data continues to alternate between the first and second halves of the Mailbox Buffer As seen in Table 3 2 the first half of the Mailbox is defined by word addresses 40H to 5EH while the second half is defined by word addresses 60H to 7EH Interrupts can be enabled to activate after conversion of each channel or the group of channels as defined by the Start and End Channel Values If interrupts are configured to go active after the conversion of each channel an interrupt will be issued 8 usec after a valid external trigger pulse is detected The only exception to this is upon the very first external trigger pulse no interrupt will be issued since data is not written to the Mailbox buffer If interrupt upon completion of a group of channels is selected an interrupt will be issued 8 usec after detection of the first external trigger following conversion of all channels in the selected group Again one extra external trigger is needed to complete update of the Mailb
60. m speed applications requiring simultaneous channel acquisition The 15 usec between conversion of each channel can essentially be considered simultaneous sampling for low to medium frequency applications After software selection of the burst continuous mode of operation conversions are started either by an external trigger or by setting the software start convert bit If the external trigger is to be used bit 2 of the Control register must be set low to accept the external trigger as an input signal Stopping the execution of burst continuous conversions is accomplished by writing 000 to the Scan Mode bits 8 10 of the Control register See the Control register section for additional information on the Scan Mode control bits and the Control register board address location 12 When configured for differential input the Mailbox functions as a dual level data buffer The first half of the Mailbox is used to store all selected channel data for the initial pass through the channels defined by the Start and End Value registers The second half of the Mailbox is then used to store the channel data corresponding to the second pass though all selected channels Storage of channel data continues to alternate between the first and second halves of the Mailbox Buffer As seen in Table 3 2 the first half of the Mailbox is defined by word addresses 40H to 5EH while the second half is defined by word addresses 60H to 7EH Interrupts can be enabl
61. n the Software Start Convert bit is set converted data from the A D Converter is not written to the Mailbox buffer since it is old convert data See the Convert On External Trigger Only Mode in the Modes of Operation section for additional details Start Convert Register Not Used Start Convert ee ee 07 06 05 o4 O3 O2 Ot At least 5 usec of data acquire time should be provided after programming of the Control register Start Value register and Gain Selects before a Software Start Convert command is issued These configuration registers control the IP330A on board multiplexers and programmable gain amplifier which respectively control the channel and gain selected for the input provided to the converter Gain Select Registers Read Write 20H 3FH The Gain Select registers are readable writeable and are used to individually select the gain corresponding to each of the 32 channels See Table 3 2 which lists the Gain Select register addresses corresponding to each of the 32 channels In differential mode Gain Select registers corresponding to channels 0 to 15 are utilized The four gain settings supported 1 2 4 and 8 are listed in Table 3 6 with their correspond binary select code A gain can be selected by writing the desired binary code to the least significant two bits of a given Gain Select register SERIES IP330A INDUSTRIAL I O PACK 16 BIT HIGH DENSITY ANALOG INPUT MODULE Table 3 6 Gain S
62. nabled to activate after conversion of each channel or the group of channels defined by the Start and End Channel Values If interrupts are configured to go active after the conversion of each channel the actual interrupt will be issued 8 usec after the programmed interval has lapsed If interrupt upon completion of a group of channels is selected an interrupt will be issued 8 psec after the interval time of the last selected channel has expired If interrupts are selected to go active after conversion of each channel be sure to program a large enough interval between conversions to allow adequate time for execution of an interrupt service routine It may also be necessary to allow time for your computer to perform other housekeeping operations between servicing interrupts SERIES IP330A INDUSTRIAL I O PACK 16 BIT HIGH DENSITY ANALOG INPUT MODULE Uniform Single Mode In uniform single mode of operation conversions are performed once in sequential order for all channels between and including the Start and End Channel Values The interval between conversions is controlled by the interval timer Timer Prescaler and Conversion Timer as described in the Conversion Timer Register section The interval timer must be used in this mode of operation After software selection of the uniform single mode of operation conversions are started either by an external trigger or by setting the software start convert bit If the external trigger is
63. nfigured to generate an interrupt after completion of conversion of a single channel or after conversion of a group of channels is completed IP interrupt signal INTREQO is issued to the carrier to request an interrupt An 8 bit interrupt service routine vector is provided during an interrupt acknowledge cycle on data lines DO to D7 The interrupt release mechanism employed is ROAK Release On AcKnowledge The IP330A will release the INTREQO signal during an interrupt acknowledge cycle from the carrier SERIES IP330A INDUSTRIAL I O PACK 16 BIT HIGH DENSITY ANALOG INPUT MODULE 5 0 SERVICE AND REPAIR SERVICE AND REPAIR ASSISTANCE Surface Mounted Technology SMT boards are generally difficult to repair It is highly recommended that a non functioning board be returned to Acromag for repair The board can be easily damaged unless special SMT repair and service tools are used Further Acromag has automated test equipment that thoroughly checks the performance of each board When a board is first produced and when any repair is made it is tested placed in a burn in room at an elevated temperature and retested before shipment Please refer to Acromag s Service Policy Bulletin or contact Acromag for complete details on how to obtain parts and repair PRELIMINARY SERVICE PROCEDURE Before beginning repair be sure that all of the procedures in Section 2 Preparation For Use have been followed Also refer to the documentation of your
64. o the appropriate bit in the AVME9630 60 IP Interrupt Enable Register 4 0 THEORY OF OPERATION This section contains information regarding the hardware of the IP330A A description of the basic functionality of the circuitry used on the board is also provided Refer to the IP330A Block Diagram drawing at the end of this manual as you review this material FIELD ANALOG INPUTS The field I O interface to the carrier board is provided through connector P2 refer to Table 2 3 Field I O signals are NON ISOLATED This means that the field return and logic common have a direct electrical connection to each other As such care must be taken to avoid ground loops see Section 2 for connection recommendations Ignoring this effect may cause operation errors and with extreme abuse possible circuit damage Refer to the IP Analog Input Connection Drawing located in the Drawings Section for example wiring and grounding connections Analog inputs and calibration voltages are selected via analog multiplexers IP330A control logic automatically programs the multiplexers for selection of the required analog input channel The multiplexer control is based upon selection of single ended or differential analog input and the Start and End channel register values Single ended and differential channels cannot be mixed i e they must all be single ended or differentially wired Up to 32 single ended inputs can be monitored where each channel s inp
65. olte A o7 0 0000 volts Auto Zero From Table 3 7 Ideal Volt Span 20 0000 volts From Table 3 8 Ideal Zero 10 0000 volts From Table 3 8 SERIES IP330A INDUSTRIAL I O PACK 16 BIT HIGH DENSITY ANALOG INPUT MODULE The calibration parameters Countc A and Countc a o remain to be determined before uncorrected input channel data can be taken and corrected Determination of the Countc ALLO Value 1 Execute Write of 043AH to Control Register at Base Address OOH a Select Straight Binary External Trigger Input Auto Zero Calibration Voltage Burst Single Scan Mode Timer Disabled Interrupts Disabled aog 2 Execute Write of 1FOOH to End Start Channel Value Register at Base Address 06H This will permit 32 conversions of the Auto Zero value to be stored in the 32 Mailbox Buffers 3 Execute write of 00H as byte data transfers only to Gain Select Channel Registers Base Address 20H to 3FH This selects a gain of one for all 32 channels 4 Execute Write 0001H to the Start Convert Bit at Base Address 10H This starts the burst single mode of conversions Thirty two conversions of the Auto Zero are implemented and stored in the 32 Mailbox Buffers 5 Execute Read of the 32 Mailbox Buffers at Base Address 40H to 7EH 6 Take the average of the 32 ADC values and save this number as Countca Lo Determination of the CountcA Value 7 Execute Write of 041AH to Control Register
66. ox Ch 28 SE Mailbox Ch 29 SE Mailbox Ch 30 SE Mailbox Ch 31 SE Notes Table 3 2 issued simultaneously with an 0E LiF 201 21 22 23 24 25 326 27 28 29 2 2B 20 2D 2 2F 30 301 32 33 34 35 36 37 38 39 3A 3B 3C 3D SE L3F 0 A 42 43 4 45 46 48 49 4 4B 4C Mailbox Ch 06 SE or Diff Mode 40 4E MailboxCh07 SEorDiff Mode 4F 50 51 52 53 54 55 56 58 59 5 5B 56 95D 5 5F 0 61 62 63 64 65 66 68 69 6A 6B 66 6D 8 6F 70 71 72 73 74 75 76 7 78 7 7B 7E Ch 08 Diff Mode Ch 09 Diff Mode Ch 10 Diff Mode Ch 11 Diff Mode Ch 12 Diff Mode Ch 13 Diff Mode Ch 14 Diff Mode Ch 15 Diff Mode _ ee ee Ne Re Ne Nae a Na All addresses that are Not Used will read as logic low All Reads and writes are 1 wait state except a Mailbox read ongoing hardware write of a new convert value In this case a read cycle will include from 1 to 6 wait states channels it is two levels deep The Mailbox is one level deep when using single ended with differential mode SERIES IP330A INDUSTRIAL I O PACK 16 BIT HIGH DENSITY ANALOG INPUT MODULE Thi
67. ox buffer for the selected group of channels 13 External Trigger Only mode of operation can be used to synchronize multiple IP330A modules to a single IP330A running in uniform continuous uniform single burst continuous or burst single mode The external trigger of the IP330A running uniform or burst mode must be programmed as an output The external trigger signal of that IP330A must then be connected to the external trigger signal of all other IP330As that are to be synchronized These other IP330As must be programmed for External Trigger Only Mode Data conversion can then be started by writing high to the Start Convert bit of the IP330A configured for Uniform or Burst mode PROGRAMMING CONSIDERATIONS FOR ACQUIRING ANALOG INPUTS The IP330A provides different methods of analog input acquisition to give the user maximum flexibility for each application The following sections describe the features of each and how to best use them USE OF CALIBRATION SIGNALS Reference signals for analog input calibration have been provided to improve the accuracy over the uncalibrated state The use of software calibration allows the elimination of hardware calibration potentiometers traditionally used in precision analog front ends Uncalibrated Performance The uncalibrated performance is affected by two primary error Sources These are the Programmable Gain Amplifier PGA and the Analog to Digital Converter ADC The untrimmed PGA and
68. quire time should be provided after programming of the Control register Start Value register and Gain Selects before the first external trigger is issued These configuration registers control the IP330A on board multiplexers and programmable gain amplifier which respectively control the channel and gain selected for the input provided to the converter In the external trigger only mode it is important to understand the sequence in which converted data is transferred from the ADC to the Mailbox Buffer Upon an external trigger the selected analog signal is converted but remains at the ADC while the previous digitized value is output from the ADC to the Mailbox Buffer Thus with this sequence the Mailbox is consistently updated with the previous cycle s converted data In other words new data in the Mailbox is one cycle behind the ADC With this sequence at the end of data conversions one additional external trigger is required to move the data from the ADC to the Mailbox buffer At the start of data conversion with the first external trigger signal given the Start Convert Bit is set data is not input to the Mailbox buffer since the data in the ADC buffer is old convert data The IP330A requires the setting of the Start Convert bit to logic one prior to receiving the first active external trigger pulse This will prevent erroneous data from being written into the Mailbox Buffer corresponding to the first channel converted This is the on
69. rd SERIES IP330A INDUSTRIAL I O PACK 16 BIT HIGH DENSITY ANALOG INPUT MODULE Cables Model 5025 551 X Shielded Cable or Model 5025 550 X Non Shielded Cable A flat 50 pin cable with female connectors at both ends for connecting AVME9630 9660 or other compatible carrier boards to Model 5025 552 termination panels The shielded cable is recommended for optimum performance with precision analog I O applications Termination Panels Model 5025 552 A DIN rail mountable panel that provides 50 screw terminals for universal field I O termination Connects to all Acromag carriers or other compatible carrier boards via flat 50 pin ribbon cable Model 5025 550 X or 5025 551 X Transition Module Model TRANS GP This module repeats field I O connections of IP modules A through D for rear exit from a VMEbus card cage It is available for use in card cages which provide rear exit for I O connections via transition modules transition modules can only be used in card cages specifically designed for them It is a double height 6U single slot module with front panel hardware adhering to the VMEbus mechanical dimensions except for a shorter printed circuit board depth It connects to Acromag Termination Panel 5025 552 from the rear of the card cage and to AVME9630 9660 boards within the card cage via flat 50 pin ribbon cable Model 5025 550 X or 5025 551 X IP MODULE Win32 DRIVER SOFTWARE Acromag provides a software product sol
70. rrupt Vector and Timer Prescaler registers The Timer Prescaler register contents are cleared upon reset Conversion Timer Register Read Write 04H The Conversion Timer Register can be written to control the interval time between conversions Read or writing to this register is possible with either 16 bit or 8 bit data transfers This register s contents are cleared upon reset Conversion Timer Register 15 14 13 12 11 10 0908 07 06 05 04 03 02 01 00 This 16 bit number is the second divisor of an 8 MHz clock signal and is used together with the Timer Prescaler Register to derive the frequency of periodic triggers for precisely timed intervals between conversions The interval time between conversion triggers is generated by cascading two counters The first counter the Timer Prescaler is clocked by an 8 MHz clock signal The output of this clock is input to the second counter the Conversion Timer and the output is used to generate periodic trigger pulses The time period between trigger pulses is described by the following equation Timer Prescaler Conversion Timer 8 Tin psec Where T time period between trigger pulses in microseconds Timer Prescaler can be any value between 40 and 255 decimal Conversion Timer can be any value between 1 and 65 535 decimal The maximum period of time which can be programmed to occur between conversions is 255 65 535 8 2 0889 seconds The minimum time interva
71. s X86 PCI bus only and is implemented as library of C functions These functions link with existing user code to make possible simple control of all Acromag IP modules and carriers 2 0 PREPARATION FOR USE UNPACKING AND INSPECTION Upon receipt of this product inspect the shipping carton for evidence of mishandling during transit If the shipping carton is badly damaged or water stained request that the carrier s agent be present when the carton is opened If the carrier s agent is absent when the carton is opened and the contents of the carton are damaged keep the carton and packing material for the agent s inspection For repairs to a product damaged in shipment refer to the Acromag Service Policy to obtain return instructions It is suggested that salvageable shipping cartons and packing material be saved for future use in the event the product must be shipped This board is physically protected with packing material and electrically protected with an anti static bag during shipment However it is recommended that the board be visually inspected for evidence of mishandling prior to applying power v CAUTION SENSITIVE ELECTRONIC DEVICES DO NOT SHIP OR STORE NEAR STRONG ELECTROSTATIC ELECTROMAGNETIC MAGNETIC OR RADIOACTIVE FIELDS The board utilizes static sensitive components and should only be handled at a static safe workstation CARD CAGE CONSIDERATIONS Refer to the specifications for loading and power req
72. s memory map reflects byte accesses using the Big Endian byte ordering format Big Endian is the convention used in the Motorola 68000 microprocessor family and is the VMEbus convention In Big Endian the lower order byte is stored at odd byte addresses The Intel x86 family of microprocessors uses the opposite convention or Little Endian byte ordering Little Endian uses even byte addresses to store the low order byte As such installation of this module on a PC carrier board will require the use of the even address locations to access the lower 8 bit data while on a VMEbus carrier use of odd address locations are required to access the lower 8 bit data Control Register Read Write Base 00H This read write register is used to select the output data format select the external trigger signal as an input or output select acquisition input mode select scan mode enable disable the timer and select the interrupt mode The function of each of the control register bits are described in Table 3 3 This register can be read or written with either 8 bit or 16 bit data transfers A power up or system reset sets all control register bits to 0 Table 3 3 Control Register FUNCTION Output Data Format 0 Binary Two s Complement 1 Straight Binary See Tables 3 4 and 3 5 for a description of these two data formats External Trigger Input 001 All Channels Single Ended Input 010 Not Used 011 4 9000v Calibration
73. ster contents are cleared upon reset Interrupt Vector Register Interrupts are released on an interrupt acknowledge cycle Read of the interrupt vector during an interrupt acknowledge cycle signals the IP330A to remove its interrupt request Timer Prescaler Register Read Write 02H The Timer Prescaler register can be written with an 8 bit value to control the interval time between conversions Timer Prescaler Register LSB typ 14 i3 12 1 10 o o This 8 bit number divides an 8 MHz clock signal The clock signal is further divided by the number held in the Conversion Timer Register The resulting frequency can be used to generate periodic triggers for precisely timed intervals between conversions The Timer Prescaler has a minimum allowed value restriction of 28 hex or 40 decimal A Timer Prescaler value of less then 40 decimal will result in an empty Mailbox Register buffer This minimum value corresponds to a conversion interval of 5 usec which translates to the maximum conversion rate of 200 KHz Although the board will operate at the 200 KHz conversion rate conversion accuracy will be sacrificed The formula used to calculate and determine the desired Timer Prescaler value is given in the Conversion Timer section which immediately follows this section Read or writing to this register is possible via 16 bit or 8 bit data transfers A 16 bit data transfer will implement simultaneous access to the Inte
74. ter ro The Programmable Gain Amplifier Setting Used See Table 3 7 High Calibration Voltage See Table 3 7 Low Calibration Voltage See Table 3 7 Actual ADC Data Read With High Calibration Voltage Applied Actual ADC Data Read With Low Calibration Voltage Applied deal ADC Voltage Span See Table 3 8 Actual Uncorrected ADC Data For Input Being Measured Ideal ADC Input For Zero See Table 3 8 Table 3 7 Recommended Calib Voltages For Input Ranges Input Range Volts 5 12 5 1 25 10 5 2 5 1 25 5 2 5 0 625 to 5 to 5 0 0000 0 6125 0 625 Auto Zero CAL3 Rec High Calib Voltage Volte at gj Volts 5 to 45 0 0000 4 9000 Auto Zero CALO 5 to 5 0 0000 2 4500 Auto Zero CAL1 5 to 5 0 0000 1 2250 Auto Zero CAL2 ADC Range Volts Auto Zero CALO Auto Zero CALO Auto Zero CAL1 Auto Zero CAL2 CAL3 CALO 0 6125 CAL3 2 4500 CAL1 14 Rec Low Calib Voltage VoltcaLLO Rec High Calib Voltage Volte at gj E ctos 1 Volts 0 6125 CAL3 0 0000 Auto Zero 0 6125 CAL3 0 6125 CAL3 0 6125 CAL3 Volts CAL2 CAL3 4 9000 4 9000 CAL1 0 6125 1 2250 CAL3 CAL2 The hardware offset may prevent you from calibrating this range 0 to 5 0 to 45 0 to 10 0 to 10 0 to 10 0 to 10 Table 3 8 Ideal Voltage Span and Zero For Input Rang
75. termine the actual input range Input signal ranges may actually fall short of reaching the specified endpoints due to hardware limitations For example if an input may reach zero volts or less a bipolar input range should be selected 4 These ranges can only be achieved with 15 Volt external power supplies The input ranges will be clipped if 12 Volt supplies are used typically to 9 8 Volt maximum inputs Programmable Gains X1 X2 x4 and x8 Input Overvoltage Protection VSS 20 V to VDD 40 V with Power ON 35 V to 55 Volts Power OFF Input Resistance 1000 MO Typical SERIES IP330A INDUSTRIAL I O PACK 16 BIT HIGH DENSITY ANALOG INPUT MODULE Input Bias Current 1 nA Typical Common Mode Rejection Ratio 60 Hz 9 96 dB Typical Channel to Channel Rejection Ratio 60 96 dB Typical Radiated Field Immunitys Designed to comply with IEC61000 4 3 Level 3 10V m 80 to 1000MHz AM amp 900MHz keyed and European Norm EN61000 6 1 with error less than 0 5 of FSR Electromagnetic Interference Immunitys EMI Error is less than 0 25 of FSR under the influence of EMI from switching solenoids commutator motors and drill motors Not required for signal per European Norm EN61000 6 1 Surge Immunity
76. the current channel s analog signal select and set the current channel s Gain and control update of the Mailbox RAM buffer The start channel register controls the value at which these counters start and the end value register controls the maximum channel number which is reached In the continuous modes of operation these counters continuously cycle in sequential order from the defined start value to the defined end value When the continuous mode of operation is halted by disabling the scan mode via the control register the internal hardware counter remains at the count value reached when halted Upon start of a new scan mode via the software start convert bit or external trigger the internal pointers are reinitialized Thus the first channel converted upon restart of data conversions will correspond to that set in the start value register A 16 bit serial shift register is implemented in the IP s FPGA This serial shift register interfaces to the A D Converter A clock signal provided by the converter is used to serially shift the new data from the converter to the FPGA s 16 bit serial shift register Use of the converter s clock signal instead of an external clock minimizes the danger of digital noise feeding through and corrupting the results of a conversion in process SERIES IP330A INDUSTRIAL I O PACK 16 BIT HIGH DENSITY ANALOG INPUT MODULE The converted data serially shifted from the A D Converter to the FPGA
77. uirements Be sure that the system power supplies are able to accommodate the power requirements of the carrier board plus the installed IP modules within the voltage tolerances specified IMPORTANT Adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature The dense packing of the IP modules to the carrier board restricts air flow within the card cage and is cause for concern Adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature and to prolong the life of the electronics If the installation is in an industrial environment and the board is exposed to environmental air careful consideration should be given to air filtering BOARD CONFIGURATION The board may be configured differently depending on the application All possible DIP switch and jumper settings will be discussed in the following sections The DIP switch and jumper locations are shown in the IP Mechanical Assembly Drawing located in the Drawings Section Remove power from the board when configuring hardware jumpers installing IP modules cables termination panels and field wiring Refer to IPS30A Jumper Location in the Drawing section and the following paragraphs for configuration and assembly instructions SERIES IP330A INDUSTRIAL I O PACK 16 BIT HIGH DENSITY ANALOG INPUT MODULE Default Hardware Jumper Configuration When the board is shipped from th
78. ut is individually selected along with a single sense lead for all channels Up to 16 differential inputs can be monitored where each channel s and inputs are individually selected A Programmable Gain Instrumentation Amplifier PGA takes as input the selected channel s and inputs or and sense and outputs a single ended voltage proportional to it The gain can be 1 2 4 or 8 and is selected through the Gain Control registers The output of the PGA feeds the A D Analog to Digital Converter The A D Converter is a state of the art 16 bit successive approximation converter with a built in sample and hold circuit The sample and hold circuit goes into the hold mode when a conversion is initiated This maintains the selected channel s voltage constant until the A D has accurately digitized the input Then it returns to sample mode to acquire the next channel Once a conversion has been started control logic on the IP330A automatically updates the multiplexer and PGA for the next channel to be converted as required This allows the input to settle for the next channel while the previous channel is SERIES IP330A INDUSTRIAL I O PACK 16 BIT HIGH DENSITY ANALOG INPUT MODULE converting This pipelined mode of operation facilitates a maximum system throughput A miniature DIP switch on the board controls the range selection for the A D Converter 5 to 5 10 to 10 0 to 5 and 0 to 10 Volts as detailed in section 2 DIP sw
79. val of 2 09 seconds e Uniform Continuous Scanning Mode All channels selected for scanning are continually digitized in a round robin fashion with the interval between conversions controlled by the programmed interval timer The results of each conversion are stored in the channel s corresponding Mailbox buffer Scanning is initiated by a software or external trigger Scanning is stopped by software control e Burst Continuous Scanning Mode All selected input scan channels are sequentially digitized at a 67 kHz conversion rate 15 usec conversion times At the end of a programmed interval time a new conversion of all channels is re initiated The conversion results are stored in each channel s Mailbox buffer This mode can be used as a pseudo simultaneous sampling mode for low to medium speed applications requiring simultaneous channel acquisition For example if four channels are selected then they could be pseudo simultaneously converted every 60 usec each of the channels actually takes 15 psec This is repeated in bursts determined by the programmed interval time The scan is initiated by a software or external trigger Scanning is stopped by software control e Uniform Single Cycle Scan Mode All channels selected for scanning are digitized once with the idle time between each channel conversion controlled by the programmed interval timer The scan is initiated by a software or external trigger e Burst Single Cycle Scan Mode All
80. wiring connections to the termination panel Schematic and Physical Attributes See Drawing 4501 464 Field Wiring 50 position terminal blocks with screw clamps Wire range 12 to 26 AWG Connections to Acromag non intelligent carrier boards P1 50 pin male header with strain relief ejectors Use Acromag 5025 550 x or 5025 551 x cable to connect panel to VME boards Keep cable as short as possible to reduce noise and power loss Mounting Termination panel is snapped on the DIN mounting rail Printed Circuit Board Military grade FR 4 epoxy glass circuit board 0 063 inches think Operating Temperature 40 C to 100 C Storage Temperature 40 C to 100 C Shipping Weight 1 25 pounds 0 6Kg packed TRANSITION MODULE MODEL TRANS GP Type Transition module for AVME9630 9660 boards Application To repeat field signals for IP modules A through D for rear exit from VME card cages This module is available for use in card cages which provide rear exit for I O connections via transition modules transition modules can only be used in card cages specifically designed for them It is a double height 6U single slot modules with front panel hardware adhering to the VMEbus mechanical dimensions except for shorter printed circuit board depth Connects to Acromag termination panel 5025 552 from the rear of the card cage and to AVME9630 9660 boards within card cage via flat 50 pin ribbon cable cable Model 5025 550 X or 5025 551
81. y 11 Hex 1 I O SPACE ADDRESS MAP This board is addressable in the Industrial Pack I O space to control the acquisition of analog inputs from the field As such three types of information are stored in the I O space control status and data The I O space may be as large as 64 16 bit words 128 bytes using address lines A1 to A6 but the IP330A uses only a portion of this space The I O space address map for the IP330A is shown in Table 3 2 Note that the base address for the IP module space see your carrier board instructions must be added to the addresses shown to properly access the I O space Both 16 and 8 bit accesses to the registers in the I O space are permitted Table 3 2 IP330A I O Space Address Hex Memory Map Base MSB LSB Base Addr D15 08 D07 DOO Addr as Control Register P Conversion Timer End Channel Start Channel Value Value 07 New Data Register P Channels 0 to 15 New Data Register Channels 16 to 31 Missed Data Register Channels 0 to 15 Missed Data Register Channels 16 to 31 Not Used Start Convert Bits15 to Bit 01 Bit 0 11 Base MSB LSB Base Addr D15 D08 D07 DOO Addr 12 NotUsed 13 ee Not U Gain Select Ch 00 Gain Select Ch 02 Gain Select Ch 04 Gain Select Ch 06 Gain Select Ch 08 Gain Select Ch 10 Gain Select Ch 12 Gain Select Ch 14 Gain Select Ch 16 Gain Select Ch 18 Gain Select Ch 20 Gain Select Ch 22 Gain Select Ch 24

IP330A User`s Manual

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