Fujitsu PLL Frequency Synthesizer Evaluation Tool (Version 5.0
Contents
1. series MB15Fxx series MB15A01 MB15F02 A02 A03 F02L F02SL SSOP 16 MB1500EB01 SSOP 16 MB1500EB13 Bump Chip MB1516A SSOP 16 MB1500EB01 Carrier 16 MB1500EB13B MB15A16 SSOP 16 MB1500EB01 MB15F03 SSOP 16 MB1500EB13 FO3L FO3SL Bump Chip MB1517A SSOP 16 MB1500EB01 Carrier 16 MB1500EB13B MB15A17 SSOP 16 MB1500EB01 MB15F06 SSOP 16 MB1500EB13 MB15Bxx series MB15FO7SL SSOP 16 MB1500EB13 4 Bump Chip MB15B01 SSOP 20 MB1500EB11 Carrier 16 MB1500EB13B MB15B03 SSOP 16 MB1500EB13 MB15F08SL SSOP 16 MB1500EB13 MB15B11 Bump Chip B13 SSOP 20 MB1500EB11 Carrier 16 MB1500EB13B 15 series MB15Uxx series SSOP 16 MB1500EB01 MB15U10 SSOP 20 MB1500EB12 MB15E03 EO3L EO3SL app MB1500EB01B MB15U32 SSOP 20 MB1500EB14 SSOP 16 MB1500EB01 MB15Cxxx series MB15E05 5 0581 Bump ChIP MB1500EB01B MB15C101 gsop g 1500 02 Bump Chip MB15E06 SSOP 16 MB1500EB01 Carrier 16 MB1500EB02B MB15E07 SSOP 16 MB1500EB01 MB15C103 SSOP 8 MB1500EB02 E07L E07SL Bump Chip MB1500EB01B Bump MB1500EB02B Carrier 16 MB15F7xSP series MB15F72SP TSSOP 20 MB1500EB16 F73SP F78SP Bump Chip MB1500EB16B Carrier 16 There are some components attached on a board They are used for every synthesizers in common and not so much influence to loop characteristics except for low pass filter components Accordingly additio2. from a R8 R10 VCO output connector 0 1uF 0 1uF 1 0nF 1000pF 1 0nF 0 1uF 1 2 3 4 5 6 7 8 0 1uF 0 1uF 0 1uF 1 0nF 1000pF PLL Evaluation tool ver5 0 Fig 3 16 MB1500EB14 board layout Top view Bottom view 900 ee sa 1 EP 80 69 5 1 4 27 PLL Evaluation tool ver5 0 28 3 2 9 MB1500EB16 Fig 3 17 MB1500EB16 circuit image From an oscillator output O ps C9 OSCN Clock od s SNB O from a connector R1 LE e ns Vvco C3 C VCO er Table 9 Components list on the evaluation board 1000pF 1000pF 10uF 10uF 10uF 10 1000 1000 1000 10 10 1 2 3 4 5 6 7 8 9 mk PLL Evaluation tool ver5 0 Fig 3 18 MB1500EB16board layout Top view RF Block LPF Bottom view LPF IF Block Veer LD fout VpRF VccRF ETE RYEN 29 PLL Evaluation tool ver5 0 30 3 2 10 MB1500EB16B output Fig 3 19 MB1500EB16B circuit image From an oscillator from a connector output Wem 2 R12 R10 R11 VCO Table 10 Components list on the eval
3. Mi 3C JELIS PLL Evaluation tool ver5 0 CHAPTER 2 SOFTWARE DESCRIPTION 2 1 Windows95 VERSION 2 1 1 STANDARD SYNTHESIZERS except for MB15E FxxSL series 2 1 1 1 INTRODUCTION This program is designed to demonstrate the operation of the Fujitsu PLL frequency synthesizers It will allow the user to investigate the operation capability of the IC and modify the loop parameters 2 1 1 2 USED ENVERNOMENT OS Windows95 2 1 1 3 CONTENTS FiPLL exe file to evaluate PLL series fjPLL ini Initialization file fjpll vxd Virtual device driver Applied device MB15E03 MB15E03L 15 05 MB15E05L MB15E06 MB15E07 MB15E07L 1516 1517 MB15A01 MB15A02 MB15A16 MB15A17 MB15F02 MB15F02L MB15F03 15 MB15F04 MB15F05 15 MB15B03 MB15U10 1551 15 03 15 03 MB15U32 device file has to housed in the directory LIB that locates under the same directory FjPLL exe does o not change a name of the directory LIB Only the device file for MB15U10 name its suffix as DT2 Name suffix for other device files as DT1 2 1 1 4 SET UP This programming tool consists of an interface board a RF evaluation board and programming software 1 Connect a parallel cable from the interface board to a printer port of a personal computer 2 Connect the data input wire three wire blue yellow and white from the interface boa
4. 1 2 HARDWARE SETUP This programming tool enables you to control FUJITSU PLL frequency synthesizers via a personal computer The personal computer is connected to the interface board via a parallel port The programming software installed generates signals to the interface board Then the signals are converted into control signals and sent to an IC on the evaluation board Fig 1 1 Hardware constructure image Parallel Port Key board Interface Evaluation Programm Device file 1 3 INTERFACE BOARD DESCRIPTION Fig 1 2 The interface board top view P No MB1500EB00 Connector Ground Delay control switch Trigger switch Data output pins BN nn r i C connecto Power source pins PLL Evaluation tool ver5 0 Connectors The personal computer and the interface board is connected with a cable The connector should have 25 pin connector for the personal computer s printer port and 36 pin connector for the interface port Trigger Switch Logical level of the trigger signal can be switched by the trigger switch Q Active high Q Active Low Trigger Trigger BNC Connector This connector should be connected to a time interval analyzer A trigger signal is output through this connector Delay Control Switch The delay time between the trigger signal and the last LE signal outputs can be adjusted by the delay control switch Turning the white
5. MB1500EB11 board layout Top view Connector Top direction Bottom view PLL Evaluation tool ver5 0 3 2 5 MB1500EB12 Fig 3 9 circuit image R1 1 1 2 2 From R3 fin1 Y 5 R4 oscillator 3 OSCin Dol Voo O 221 Pa fr2 OSCout SW4 R10 id ANA ow O R8 L Qy R7 W3 Iser R6 AN VCO outpu PO LD O Vp 9 SW5 Do2 Vvco O AGND 7 a ce fin2 R5 ma E OVoo DD2 LE from a Data connector Clock Table 5 Components list on the evaluation board z Value 0 1uF 0 1uF 0 1uF 1000pF 1000pF 0 1uF 1000pF 0 1uF N O QO GQ NN 0 1uF 2 2 20 PLL Evaluation tool ver5 0 Fig 3 10 MB1500EB12 board layout Top view Bottom view DI Connector direction ee 21 PLL Evaluation tool ver5 0 3 2 6 MB1500EB13 Fig 3 11 MB1500EB13 circuit image O lock From an d O from a oun oscillator Data connector VCO output R1 O R3 LE R4 ne 79 R5 i fine 08 O O VCO C4 Ha VCCRF Hos veo Vvco V 2 Xtinee sen Mi d d sw c Zr PSnr 7 LPF Table 6 Components list on the evaluation board 1000pF 1000pF 0 1uF 0 1uF 1000pF 0 1uF 0 1uF 1000pF 10uF 10
6. button Output current Ch Data then the value of the present channel is automatically calculated and output through the port Click the button Output Next Ch Data then the value of the next channel is automatically calculated and output through the port In the both cases serial data and an trigger is output If the calculation is failed the PLL Frequency Hopping mode can not be selected Set parameters correctly 2 1 1 5 4 OHTERS When any of OSC Frequency Frequency Range and Channel Spacing is changed the PLL Frequency Hopping mode can not be selected In that case click the button Output Current Ch Data There is not a function to save the set data Certainly house the device files in the LIB directory that locates in the same directory as FjPLL exe Do not change the name of LIB directory Only the device file for MB15U10 name its suffix as DT2 Name suffix for other device files as DT1 Apply DOS 8 3 type for the name of the device file PLL Evaluation tool ver5 0 10 2 1 2 STANDARD SYNTHESIZERS MB15E FxxSL F7xSP series 2 1 2 1 INTRODUCTION This program is designed to demonstrate the operation of PLL MB15E FxxSL series It will allow the user to investigate the operation capability of the IC and modify the loop parameters 2 1 2 2 USED ENVERNOMENT OS Windows95 2 1 2 3 CONTENTS FiPLL exe Execution file to evaluate PLL series MB15ExxSL series version 3 4 1 MB15FxxSL F7xSP series vers
7. Edition 5 0 D Jan 2000 F UJITSU Fujitsu PLL Frequency Synthesizer Evaluation Tool Version 5 0 User s Manual FUJITSU LIMITED PLL Evaluation tool ver5 0 CONTENTS CHAPTER 1 HARDWARE DESCRIPTION 1 1 INTRODUCTION 1 2 HARDWARE SETUP 1 3 INTERFACE BOARD DESCRIPTION 1 4 INTERFACE BOARD LAYOUT CHAPTER 2 SOFTWARE DESCRIPTION 2 1 Windows 95 VERSION 2 1 1 STANDARD SYSNTHESIZER except for MB15E FxxSL series 2 1 1 1 INTRODUCTION 2 1 1 2 USED ENVERNOMENT 2 1 1 3 CONTENTS 2 1 1 4 SET UP 2 1 1 5 HOW TO USE THE PROGRAM 2 1 1 5 1 STARTING THE PROGRAM 2 1 1 5 2 SETTING THE TEST CONDITIONS 2 1 2 5 3 MEASUREMENT 2 1 2 5 4 OTHERS 2 1 2 STANDARD SYSNTHESIZER MB15E FxxSL series 2 1 2 1 INTRODUCTION 2 1 2 2 USED ENVERNOMENT 2 1 2 3 CONTENTS 2 1 2 4 SET UP 2 1 2 5 HOW TO USE THE PROGRAM CHAPTER 3 EVALUATION BOARD DESCRIPTION 3 1 OVERVIEW 3 2 EVALUATION BOARD DESCRIPTION 3 2 1 MB1500EB01 3 2 2 MB1500EB01B 3 2 3 1500 02 3 2 4 1500 11 3 2 5 1500 12 3 2 6 1500 13 3 2 7 1500 13 3 2 8 1500 14 3 2 9 1500 16 3 2 10 MB1500EB16B PLL Evaluation tool ver5 0 CHAPTER 1 HARDWARE DESCRIPTION 1 1 INTRODUCTION This evaluation tool is designed to demonstrate the operation of the FUJITSU 15 series PLL frequency synthesizers It will allow the user to investigate the operation capability of the and modify the loop parameters
8. ch parameter FLL GEGE TG Made oppna EI am AA eed EET CH r Maz 22 Only for a programmable parameter becomes valid Click each value futon and input data If any of the parameter is not filled in you can not go to the next step FjPLL dialog Parameter setting OSC Frequency input ALT O Input a positive value Frequency Range input ALT F The value in the column From must be a positive number and less than that in the column To Channel Spacing input ALT 5 Input a positive value Current Channel input ALT C Input an integer 0 or more Hopping Channel input ALT The value in the column From CH must be an integer 0 more and less than the value in the column To CH Number of repeat input ALT E Input an integer 1 or more Note As regards Frequency Range value in the case that the display of data and real data differ please confirm the value The value be inputed in conformity with the calculation MxN A fr channel spacing PLL Evaluation tool ver5 0 2 1 1 5 3 MEASUREMENT After test conditions are entered the measurement can be done by sending the serial data to the testing sample via the interface board Hopping enable progress ALT E Hopping Repeat Hopping is repeated at designated time by Number of repeat em It can be cancelled using a space key iit o Press SPACE key to Cancel Click the
9. ion 3 3 2 fjPLL ini Initialization file fjpll vxd Virtual device driver Applied device Version 3 4 1 MB15E03SL MB15E05SL MB15E07SL Version 3 3 2 MB15F02SL MB15F03SL MB15F07SL MB15F08SL device has to housed in the directory LIB that locates under the same directory as FjPLL exe does o not change a name of the directory LIB 2 1 2 4 SET UP This programming tool consists of an interface board a RF evaluation board and programming software 1 Connect a parallel cable from the interface board to a printer port of a personal computer 2 Connect the data input wire three wire blue yellow and white from the interface board to the Data Clock and LE pins on the evaluation board Refer to CHAPTER 1 3 Insert the floppy disk into the floppy disk drive on the personal computer 4 Change a disk drive from the current drive to the floppy disk drive 2 1 2 4 HOW TO USE THE PROGRAM It conforms to chapter 2 1 1 5 The bit configuration differs from MB15E Fxx and MB15E FxxL series PLL Evaluation tool ver5 0 3 EVALUATION BOARD DESCRIPTION 3 1 OVERVIEW Some synthesizers are pin compatible or similar pin assignment so that an evaluation board is used for several PLLs The below table shows PLL part number and corresponding evaluation board numbers Table 1 P No of synthesizers and corresponding Evaluation board Part No PKG type Eval board No Part No PKG type Eval board No 15
10. list on the evaluation board 1000pF 0 1uF 0 1uF 1000pF 0 1uF 10uF 10uF 10uF 1 2 3 4 5 6 7 8 PLL Evaluation tool ver5 0 Fig 3 4 MB1500EB01B board layout Top view Connector direction Three pins Bottom view 520 018 o o o 15 PLL Evaluation tool ver5 0 16 3 2 3 MB1500EB02 Fig 3 5 MB1500EB02 circuit image C3 VccO Ds from a TCXO OSCin LPF LD Vcc Ri R2 fout Ps VCO Lape sw C2 Div i R3 Table 3 Components list on the evaluation board 0 1uF 1000pF 1000pF 10uF PLL Evaluation tool ver5 0 Fig 3 6 MB1500EB02 board layout Top view Bottom view 0 17 PLL Evaluation tool ver5 0 3 2 4 MB1500EB11 Fig 3 7 MB1500EB11 circuit image C1 ND lock From an si dui from a oscillator OSCin Data connector VCO output O VCO output C2 OSCout LE 7 4 fin1 fin2 VccO ma ma Ovcc SE Vcc1 Vcc2 T C6 fr fp Vvco Vvco LD1 LD2 4 ir T ps BSC1 or Vp1 BSC2 or Vp2 LPF Dol Do2 Gi 51 52 Table 4 Components list the evaluation board 1000pF 1000pF 0 1uF 0 1uF 0 1uF 0 1uF 1000pF 18 PLL Evaluation tool ver5 0 Fig 3 8
11. nal components such as VCO a reference oscillator optimized loop filter etc should be properly arranged by customers according to application PLL Evaluation tool ver5 0 12 3 2 EVALUATION BOARD DESCRIPTION 3 2 1 MB1500EB01 Fig 3 1 MB1500EB01 circuit image C1 From an oscillator OSCin oR C1 C2 OSCout Ter 2 HE Vp fout or LD fout VccO ma Veo C2 C3 T Vcc NC or ZC o SW Do FC or PS XJ O GND LE LPF O from a C4 LD or Xfin Data connector R1 O fin Clock R2 VCO R3 VCO output m Vvco 5 TT Table 2 Components list on the evaluation board 1000pF 0 1uF 0 1uF 1000pF 0 1uF 10uF 10uF 10uF N O A O N gt PLL Evaluation tool ver5 0 Fig 3 2 MB1500EB01 board layout Top view Connector direction gt Three pins Bottom view 13 PLL Evaluation tool ver5 0 14 3 2 2 MB1500EB01B Fig 3 3 MB1500EB01B circuit image C1 OSCin From an oscillator C C2 OSCout Vp O 2 Vp Vcc i C2 C3 Vcc oP fout or LD fout Vcc NC or ZC pou SW O Do FC or PS 1 Ie Fin GND LE LPF 9 from a e SET Ca LD or Xfin Data connector 21 fin Clock L We VCO ne R3 VCO output n Vvco 5 C3 Table 2 Components
12. rd to the Data Clock and LE pins on the evaluation board Refer to CHAPTER 1 3 Insert the floppy disk into the floppy disk drive on the personal computer 4 Change a disk drive from the current drive to the floppy disk drive PLL Evaluation tool ver5 0 2 1 1 5 HOW TO USE THE PROGRAM 2 1 1 5 1 STARTING THE PROGRAM Double clicking the FjPLL exe on the windows explorer and run the program When you run the program using floppy disk please release a protector of the floppy disk If a write protect is valid the following message is appeared and the program does not run Can t write FjPLL ini Device locked or File protected 2 1 1 5 2 SETTING THE TEST CONDITIONS The following window is opened on executing the FjPLL exe 1 Clicking exit program button this program is quit FUJITSU PLL Frequency Synthesizer Evaluation Tool ver 3 2 lam Select Device File Pereli port arallel port mb15a16 dt1 Exit Program 2 Click the parallel port button and select a used port As is indicated below you can select only valid parallel port Paralel port Select parallel port f address Cancel f LPT1 378 37 C LPT3 PLL Evaluation tool ver5 0 3 Select the device file and then click the button OPEN The below shown parameter setting dialog window is opened An usable parameter is different by the device file Set ea
13. screw part the delay time can be adjusted in the range from bus to 600us Data Output Pin Connect one side of the three wire white blue and yellow connector to the data output pins on the interface board The other side is connected to the data input pins on the evaluation board Power Source Pin Connect two wire red and black connector to the power source pins and the other side to ground and Vcc respectively Vcc 3V to 5V needs to be as same as supply voltage for the IC Ground Connect to ground PLL Evaluation tool ver5 0 1 4 INTERFACE BOARD LAYOUT 00000000 00000000 exit goooaooon 000000000 999090000 EED 00000009 00000000 00000000 00000000000000 090990 000000000000000000 Top Layer abs 5 3 21 23 C2 ms Teg iviid vol D ED N mr f va oe 5 h o o dou of Bolo pwan ooo o M 39 11 6006 5 56 oooooooo 00 D 5 921 6 3 MW SU Hi fci2urL 3 n is m o 57 2 m E n OQ N FLSIHEL LIHrL G My C 9 zt GO lt 5 s m a run OES sd ki 5 E iva m m F z N SSS L a a
14. uF 10uF 10uF O QO A nm PLL Evaluation tool ver5 0 Fig 3 12 MB1500EB13 board layout Top view Bottom view e Cik 2 Be WANG J DELAK e Connector direction Three pins 23 PLL Evaluation tool ver5 0 24 3 2 7 MB1500EB13B Fig 3 13 MB1500EB13B circuit image C1 From 20 VCO output oscillator OSCin R1 R3 R4 W R5 Vico d LD fout ye 4 from connector LE Table 7Components list on the evaluation board 1000pF 1000pF 0 1uF 0 1uF 1000pF 0 1uF 0 1uF 1 2 3 4 5 6 7 8 1000pF 10pF 10uF 10uF 10uF LPF PLL Evaluation tool ver5 0 Fig 3 14 MB1500EB13B board layout Top view Connector direction Three pins Bottom view 1502 8 o 25 PLL Evaluation tool ver5 0 26 3 2 8 MB1500EB14 Fig 3 15 MB1500EB14 circuit image C4 finnr w 1 IHs GNDrr From an a oscillator ce OSCin GNDnr VCO output Table 8 Components list the evaluation board 0 1uF LPF 610 Vvco VCO R9
15. uation board 1000pF 1000pF 10uF 10uF 10uF 10uF 1000pF 1000pF 1 2 3 4 5 6 7 8 9 1000pF 10uF O 10uF C11 Vvco PLL Evaluation tool ver5 0 Fig 3 20 MB1500EB16board layout Top view 2 9 m w RF Block LPF Bottom view
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