USER`S MANUAL
Contents
1. UNPACKING AND INSPECTION 2 CARD CAGE CONSIDERATIONS sees BOARD Default Hardware Jumper Configuration Power Supply Hardware Jumper Configuration Programmable Register Configuration be Analog Output Data CONNECTORS YR R a IP Field Connector Analog Output Noise and Grounding Considerations IP Logic Interface Connector P1 PROGRAMMING ADDRESS MAPS eret rere nee Gece IP Identification 2 DAC Channel Transparent Mode ife Simultaneous Simultaneous Output Trigger Channel Offset Gain Error Coefficients 220 PROGRAMMING CONSIDERATIONS Using the Transparent Mode Using the Simultaneous Mode USE OF CALIBRATION DATA Uncalibrated Performance Calibrated THEORY OF OPERATION i ANALOG OUTPUTS SS ite etre erii ini LOGIC POWER 2 202. DO NOT USE 12 VOLTS WITH 15 VOLTS IP22 JUMPER LOCATIONS ag Mion ante 220 JUMPER LOCATION OT ene 2 M2 x 6 Be FLAT HEAD SCREW I eee SIDE 2 OF IP MODULE 2 I THREADED M2 COMPONENT SIDE SPACER OF CARRIER BOARD 5 3 1 FRONT PANEL CONNECTOR OR 19 SCREW 4 ASSEMBLY PROCEDURE 4 1 THREADED SPACERS ARE PROVIDED TWO DIFFERENT LENGTHS THE SHORTER LENGTH IS FOR USE WITH AVME 9630 9660 CARRIER BOARDS SHOWN CHECK YOUR CARRIER BOARD TO DETERMINE ITS REQUIREMENTS MOUNTING HARDWARE PROVIDED MAY NOT BE COMPATIBLE WITH ALL TYPES OF CARRIER BOARDS 2 INSERT FLAT HEAD SCREWS A THROUGH SOLDER SIDE OF MODULE AND INTO HEX SPACERS AND TIGHTEN 4 PLACES UNTIL HEX SPACER 15 COMPLETELY SEATED 5 3 CAREFULLY ALIGN IP MODULE TO CARRIER BOARD AND PRESS 5 TOGETHER UNTIL CONNECTORS AND SPACERS ARE SEATED 4 INSERT PAN HEAD SCREWS ITEM THROUGH SOLDER SIDE OF CARRIER BOARD AND INTO HEX SPACERS TIGHTEN 4 PLACES IP MODULE TO CARRIER BOARD MECHANICAL ASSEMBLY Arenos FEE om E por 8e a ee SEE NOTE 2 R LEAD SEE NOTE 4 LOAD 15 RLEAD EXT SUPPLY EXT SUPPLY DE NOTE 3 1 NOTES 1 SHIELDED CABLE 15 RECOMMENDED FOR LOWEST
3. Monotonicity over 12 bits Linearity Error 1 2 LSB Maximum Differential Linearity Error 1 LSB Maximum System 0 025 of 20V SPAN Maximum corrected error i e calibrated at 25 C See Note 5 with the output unloaded Settling Time 8uS to within 0 012 for 20V step change load of 5KQ in parallel with 470 pf Output at Reset Bipolar Zero Volts See Note 6 Output Noise 2 rms 20MHz bandwidth Typical Output 10 Maximum at 25 C a load of 10 will introduce 0 01 output error Short Circuit Protection Indefinite at 25 C Output Load Stability Maximum recommended capacitive load is 500pf Capacitive loads above 500pf can be tolerated but with additional overshoot Gain Drift aga 30ppm per 9C Maximum Bipolar Zero Drift 15ppm of 20V SPAN per C Resistance to 2 Error is lt 0 25 of a 20V span for RFI field strengths up to 10V m at 27MHz 159 2 and 460MHz Notes Analog Outputs 3 Maximum output current 5 can be achieved at the range endpoints using the internal 12 volt power supplies sourced through P1 The exter
4. including Acromag AVME9630 9660 3U 6U non intelligent carrier boards Additionally PC carrier boards are also supported See Acromag Model APC8610 Consult the documentation of your carrier board to ensure compatibility with the following interface products since all connections to field signals are made through the carrier board which passes them to the individual IP modules Cables Model 5025 551 X Shielded Cable or Model 5025 550 X Non Shielded Cable A Flat 50 pin cable with female connectors at both ends for connecting AVME9630 9660 or other compatible carrier boards to Model 5025 552 termination panels The unshielded cable is recommended for digital while the shielded cable is recommended for optimum performance with this module and for precision analog I O applications Termination Panel Model 5025 552 DIN rail mountable panel provides 50 screw terminals for universal field I O termination Connects to Acromag AVME9630 9660 or other compatible carrier boards via flat 50 pin ribbon cable Model 5025 550 X or 5025 551 X Transition Module Model TRANS GP This module repeats field I O connections of IP modules A through D for rear exit from the card cage It is available for use in card cages which provide rear exit for I O connections via transition modules transition modules can only be used card cages specifically designed for them It is a double height 6U single slot module with front panel hardwa
5. 44 45 46 47 48 49 50 MODEL 5025 552 TERMINATION PANEL SCHEMATIC G RAIL DIN MOUNTING SHOWN HERE TERMINATION 5 DIN EN 50035 32mm PANEL ACROMAG PART NUMBER 4801 4048 T RAIL DIN MOUNTING SHOWN HERE DIN EN 50022 35mm SCREWORIVER SLOT FOR REMOVAL FROM RAIL SIDE VIEW NOTES DIMENSIONS ARE IN INCHES MILLIMETERS TOLERANCE 0 020 3 0 5 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 33 35 37 39 41 43 45 47 49 MODEL 5025 552 TERMINATION PANEL Acromag WIXOM MICH TITLE FRONT VIEW CONNECTORS ON PC BOARD MODEL TRANS GP MODULE SCHEMATIC CONNECTORS ON FRONT PANEL TOP VIEW PEG 9 19 233 4 9 u we 7 MODEL TRANS GP TRANSITION MODULE Awe
6. Analog Output Data Format The bipolar output range 10 to 10 Volts is programmed with Bipolar Offset Binary BOB data to the Digital to Analog Converter DAC The following table indicates the relationship between the data format and the ideal analog output voltage from the module Table 2 2 Bipolar Offset Binary BOB Output Data Format Volts Hex 0 0049 8010 ee a eee The BOB 12 bit data is left justified within the 16 bit word The 4 Least Significant Bits LSB s are shown as zero in the table but actually it does not matter what is written to them CONNECTORS IP Field I O Connector P2 P2 provides the field interface connector for mating IP modules to the carrier board P2 is a 50 pin receptacle female header AMP 173279 3 or equivalent which mates to the male connector of the carrier board AMP 173280 3 or equivalent This provides excellent connection integrity and utilizes gold plating in the mating area Threaded metric M2 screws and spacers are supplied with the module to provide additional stability for harsh environments see Mechanical Assembly Drawing 4501 434 The field and logic side connectors are keyed to avoid incorrect assembly P2 Pin assignments are unique to each IP see Table 2 3 and normally correspond to the pin numbers of the front panel field I O interface connector on the carrier board you should verify this for your carrier board In Table 2 3 channel designations are ab
7. gain error of 13 and an offset error of 25 are read from the PROM on the IP220 for the desired channel substitution into equation 4 yields Corrected Count 1 13 16384 3072 2048 2048 25 4 3066 56 If this value rounded to 3067 is used to program the DAC output following conversion to Hex and left justification the output value will approach 5 Volts to within the calibrated error specified in Table 3 4 1 LSB Note that the quantization error up to 0 5 LSB introduced by rounding to 3067 is not included in the overall accuracy specification Calibration Programming Example The available bipolar range centered around 0 Volts is 10 to 10 Volts Assume it is necessary to program channel 0 with an output of 2 5 Volts 1 Write to the Transparent Mode register BASE 20H with data of FFFFH to select the Transparent Mode In this mode data written to the Channel Register will be automatically transferred from the input latch to the output latch and converted to the desired output SERIES IP220 INDUSTRIAL I O PACK 12 BIT HIGH DENSITY ANALOG OUTPUT MODULE 2 Read the PROM to retrieve the channel s unique offset calibration error data For channel 0 read byte BASE 41H An 8 bit two s compliment number is read assume 20H This corresponds to a PROM_Offset_Error of 32 decimal 3 Read the PROM to retrieve the channel s unique gain calibration error data For channel 0 read byte B
8. the procedures in Section 2 Preparation For Use have been followed Also refer to the documentation of your carrier board to verify that it is correctly SERIES IP220 INDUSTRIAL PACK 12 BIT HIGH DENSITY ANALOG OUTPUT MODULE configured Replacement of the module with one that is known to work correctly is a good technique to isolate a faulty module CAUTION POWER MUST BE TURNED OFF BEFORE REMOVING OR INSERTING BOARDS Acromag s Applications Engineers can provide further technical assistance if required When needed complete repair services are also available from Acromag 6 0 SPECIFICATIONS GENERAL SPECIFICATIONS Operating Temperature 0 to 70 C 40 to 85 C E Versions Relative Humidity 5 9596 Non Condensing Storage Temperature 55 C to 100 C Physical Configuration Single Industrial Pack Module Length teens 3 900 in 99 0 mm Width eet 1 800 in 45 7 mm Board Thickness 0 062 in 1 59 mm Max Component Height 0 314 in 7 97 mm Connectors P1 IP Logic Interface 50 pin female receptacle header AMP 173279 3 or equivalent P2 Field O 50 pin female receptacle header AMP 173279 3 or equivalent Power 5 Volts 5 150mA Typical 200mA Maximum 12 Volts 4596 from P1 or 200mA Typical 300mA Maximum 15 Volt
9. user employ satisfactory overall system design It is agreed between the Buyer and Acromag that this is the Buyer s responsibility 1 0 GENERAL INFORMATION The Industrial I O Pack IP Series 220 module is a 12 bit high density single size IP analog output board with the capability to drive up to 16 analog voltage output channels The IP220 utilizes state of the art Surface Mounted Technology SMT to achieve its high channel density and is an ideal choice for many industrial control and scientific applications that require high density high reliability and high performance at a low cost MODEL OUTPUTS OPERATING TEMPERATURE RANGE 220 16 01070 2208 8 00705 220 16 40 to 85 C IP220 8E 8 40 to 85 C KEY IP220 FEATURES High Channel Count Individual control of up to 16 analog voltage output channels is provided Four units mounted on a carrier board provide up to 64 output channels in a single system slot 12 Accuracy Each channel contains its own 12 bit Digital to Analog Converter DAC with an 8uS output settling time Bipolar Outputs Provides bipolar voltage range outputs 10 to 10 Volts Reliable Software Calibration Calibration coefficients Stored on board provide the means for accurate software calibration of the module Individual Output Control Output channels can be individually selected and updated with a single channel data write command when
10. 34 220 8 6C R CHII Offset Erro GE Gain Erro 70 2 Offset Error DAC Channel Registers Write Base 00H to Base 1EH 72 12 R CH13 Offset Error The IP220 contains sixteen 16 DAC Channel Registers in the 76 Gain Error space Writing to the address of the specific register enables 78 6 Offset Error the 12 bit input buffer of the 12 bit input double buffer to latch the Gain Error data existing on the data bus The 12 bit DAC registers are written 7C R CHI5 Offset Error will not respond to reads with 16 bit words D16 with the four least A3 Acromag ID Code 23 220 8 Code Not Used Revision Not Used Driver ID Low Byte 5 2 2 AYA KY PO O O gt Co Driver ID Total Number of ID PROM 0 Not Used L FE Gain Error significant bits D3 to D0 being non functional during a digital to analog conversion cycle Execution of a DAC Channel Write Notes Table 3 1 command requires 0 wait states 1 The IP will not respond to addresses that are Not Used SERIES IP220 INDUSTRIAL PACK 12 BIT HIGH DENSITY ANALOG OUTPUT MODULE The twelve bits of data are left justified within the 16 bit word D16 The four LSB s are undefined typically passive pull ups on t
11. 50 PIN CONNECTOR 1004 512 NOTE SEVEN DIGIT PART NUMBERS ARE ACROMAG PART NUMBERS X FEET TOP VIEW NON SHIELDED x RIBBON CABLE 2002 211 PIN 1 ON CABLE IS DESIGNATED WITH RED INK FRONT VIEW MODEL 5025 550 SIGNAL CABLE NON SHIELDED MODEL 5025 552 TERMINATION CONNECTOR 1004 512 NS 2 2 7 LA 2 LA 2 2 2 2 2 2 2 2 2 7 7 STRAIN RELIEF 1004 534 A cromag a reo aj A p foe ow ev 1e1 Esser 462 f PIN 50 OF P1 amp P2 CONNECT TO GROUND SHIELD P1 TO AVME9630 9660 CARRIER BOARD GROUND SHIELO ON BACK SIDE OF CABLE MODEL 5025 552 1 0 TERMINATION P3 OR P4 PS P6 X FEET TOP VIEW STRAIN RELIEF RIBBON CABLE BLACK LINE ON CABLE CONNECTOR 1004 534 2002 261 INDICATES PIN 59 1004 512 POLARIZING KEY 59 PIN CONNECTOR 1 CABLE 1004 512 NO MARKINGS STRAIN RELIEF 1004 534 FRONT VIEW NOTE SEVEN DIGIT PART NUMBERS ARE ACROMAG PART NUMBERS XXXX XXX tH lt romag MODEL 5025 551 SIGNAL CABLE SHIELDED tials oP 1e 4501 463 1 2 3 4 5 6 7 84 9 1811 12 13 14 15 16 17 1H 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 48 41 42 43 44 45 46 47 48 49 58 P1 1 2 3 4 5 6 7 8 8 10 111213 14 15 16 1718 19 20 21 22 2324 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 48 41 42 43
12. ASE 43H An 8 bit two s compliment number is read assume F1H This corresponds to a PROM_Gain_Error of 15 decimal 4 Calculate the Ideal Count required to provide an uncorrected output of the desired value 2 5 Volts by using equation 2 Ideal_Count 4096 20 2 5 2048 1536 0 5 Calculate the Corrected_Count required to provide an accurate output of the desired value 2 5 Volts by using equation 4 Corrected Count 1 15 16384 1536 0 2048 2048 32 4 1544 47 6 Write to the DAC Channel 0 Register BASE 00H with the desired data 6080H data is determined by rounding 1544 47 decimal to 1544 then converting to Hex 608 and left justifying as 6080H 7 OPTIONAL Observe or monitor that the specific DAC channel 0 reflects the results of the digital data converted to an analog output voltage at the field connector 8 Repeat steps 2 7 to adjust the unique calibration characteristic and update each channel used or repeat steps 4 7 to update the value of a single channel Error checking should be performed on the calculated count values to insure that calculated values below 0 or above 4095 decimal are restricted to those end points Note that the software calibration cannot generate outputs near the endpoints of the range which are clipped off due to the uncalibrated hardware i e the DAC 4 0 THEORY OF OPERATION This section describes the basic functionality of the 220 circu
13. Acromag 4 Series IP220 Industrial Pack 12 Bit High Density Analog Output Board USER S MANUAL ACROMAG INCORPORATED 30765 South Wixom Road P O BOX 437 Wixom MI 48393 7037 U S A Tel 248 624 1541 Fax 248 624 9234 Copyright 1994 1996 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 486 98 015 SERIES 1 220 INDUSTRIAL PACK 12 BIT HIGH DENSITY ANALOG OUTPUT MODULE The information contained in this manual is subject to change without notice Acromag Inc makes no warranty of any kind with regard to this material including but not limited to the implied warranties of merchantability and fitness for a particular purpose Further Acromag Inc assumes no responsibility for any errors that may appear in this manual and makes no commitment to update or keep current the information contained in this manual No part of this manual may be copied or reproduced in any form without the prior written consent of Acromag Inc Table of Contents 1 0 2 0 3 0 4 0 5 0 6 0 GENERAL KEY 220 6 INDUSTRIAL I O PACK INTERFACE FEATUREG SIGNAL INTERFACE PRODUCTS INDUSTRIAL PACK SOFTWARE LIBRARY INDUSTRIAL I O PACK OLE CONTROL SOFTWARE PREPARATION FOR
14. IAL PACK 12 BIT HIGH DENSITY ANALOG OUTPUT MODULE Uncalibrated Performance The uncalibrated performance is affected by two primary error sources These are the channel s offset and gain errors The use of channel specific calibration coefficients to accurately adjust offset and gain is important because the worst case uncalibrated error can be significant although the typical uncalibrated errors observed may be much less The maximum uncalibrated error is summarized as follows DAC4813AP 25 C Linearity Error is 0 012 maximum i e 1 2 LSB Bipolar Offset Error is 0 4 FSR i e 20V SPAN maximum Gain Error is 0 2 FSR maximum Table 3 3 summarizes the maximum uncalibrated error combining the linearity offset and gain errors Table 3 3 Maximum Overall Uncalibrated Error Max Linearity Max Offset Max Gain Max Total Error Error Error Error This represents the worst case error with all errors summed Typically each error component is much less than its maximum and all error components do not reinforce each other Thus typical errors are much less than that shown in the table above Calibrated Performance Accurate calibration of the 1 220 can be accomplished through software control by using calibration coefficients to adjust the analog output voltage Unique calibration coefficients are stored in the PROM as 1 4 LSB s for each specific channel Once retrieved the ch
15. NOISE SHIELD 15 CONNECTED TO GROUND REFERENCE AT ONLY ONE END TO PROVIDE SHIELDING WITHOUT GROUND LOOPS ALL 16 CHANNELS ARE REFERENCED TO ANALOG COMMON AT THE 220 TO AVOID GROUND LOOPS 00 NOT CONNECT GROUNDED CHANNELS THE NEGATIVE SIDE OF THE OUTPUT EXTERNAL SUPPLIES CAN BE USED BY JUMPERING IT IS RECOMMENDED THAT THE SUPPLY COMMONS CONNECTED TO ANALOG COMMON lt VO DUE TO VOLTAGE DROPS ACROSS THE LEAD RESISTANCE OF THE WIRE IT IS RECOMMENDED THAT A HIGH RESISTANCE LOAD WTH A SHORT WIRE RUN BE CONNECTED AT THE OUTPUT TO REDUCE THE EFFECTS OF LEAD AND SOURCE RESISTANCE VOLTAGE DROPS IN THE WIRE SOURCE d R source ANALOG lt 7 COMMON 220 ANALOG OUTPUT CONNECTION DIAGRAM EARTH GROUND CONNECTION AT POWER SUPPLY TYPICAL wiYOM MICH ANALOG OUTPUT CONNECTION DIAGRAM LD ez 401 440 INO INTERFACE INTERFACE DIGITAL TO ANALOG OUTPUT CONVERTER LATCH CHANNEL DATA BUS CONTROL LOGIC ID PROM DIGITAL TO ANALOG OUTPUT CALIBRATION CONVERTER LATCH PROM CHANNEL 15 7 ANALOG COMMON 15V SUPPLIES 41 amp J2 SUPPLY SELECTION NOTE REFERENCED mod APRS NNECT 3 LOADS TO THE NEGATIVE SIDE OF THE OUTPUT IP22 BLOCK DIAGRAM pope 191 24501 439 af pl Be ee eo Oe AVME9630 9660 CARRIER BOARD P3 OR P4 P5 P6 STRAIN RELIEF 1004 5534
16. Part 2002 261 Type 3476 50 or equivalent Headers Both Ends 50 pin female header with strain relief Header Acromag Part 1004 512 8M Type 3425 6600 or equivalent Strain Relief Acromag Part 1004 534 3M Type 3448 3050 or equivalent Keying Headers at both ends have polarizing key to prevent improper installation Schematic and Physical Attributes For Non Shielded cable model see Drawing 4501 462 For Shielded cable model see Drawing 4501 463 Shipping Weight 1 0 pound 0 5Kg packed TERMINATION PANEL MODEL 5025 552 Type Termination Panel For AVME9630 9660 Boards Application To connect field I O signals to the Industrial I O Pack IP Termination Panel Acromag Part 4001 040 Phoenix Contact Type FLKM 50 The 5025 552 termination panel facilitates the connection of up to 50 field I O signals and connects to the AVME9630 9660 3U 6U non intelligent carrier boards A D connectors only via a flat ribbon cable Model 5025 550 x or 5025 551 x The A D connectors on the carrier board connect the field I O signals to the P2 connector on each of the Industrial Pack modules Field signals are accessed via screw terminal strips The terminal strip markings on the termination panel 1 50 correspond to P2 pins 1 50 on the Industrial I O Pack IP Each Industrial I O Pack IP has its own unique P2 pin assignments Refer to the IP module manual for correct wiring connections to the termination panel Schematic an
17. SERVICE AND SERVICE AND REPAIR ASSISTANCE PRELIMINARY SERVICE PROCEDURE me 5 GENERAL ANALOG OUTPUTS ttes ee INDUSTRIAL I O PACK APPENDIX CABLE MODEL 5025 550 CABLE MODEL 5025 551 TERMINATION PANEL MODEL 5025 552 3 TRANSITION MODULE MODEL TRANS GP DRAWINGS Page 4501 441 IP220 JUMPER LOCATIONS 13 4501 434 IP MECHANICAL ASSEMBLY 13 4501 440 ANALOG OUTPUT CONNECTIONS 14 4501 439 IP220 BLOCK 01 14 4501 462 CABLE 5025 550 NON SHIELDED 15 4501 463 CABLE 5025 551 SHIELDED 15 4501 464 TERMINATION PANEL 5025 552 16 4501 465 TRANSITION MODULE TRANS GP 16 IMPORTANT SAFETY CONSIDERATIONS It is very important for the user to consider the possible adverse effects of power wiring component sensor or software failures in designing any type of control or monitoring system This is especially important where economic property loss or human life is involved It is important that the
18. annel s unique offset and gain coefficients can be used to correct the data value sent to the DAC channel to accurately generate the desired output voltage Table 3 4 summarizes the maximum calibrated error combining the linearity and adjusted offset and gain errors Table 3 4 Maximum Overall Calibrated Error Max Linearity Max Offset Max Gain Max Total Error LSB Error LSB Error LSB Error LSB 0 25 0 25 1 0 0 025 Thus correcting the value programmed to the DAC Channel Register using the stored calibration coefficients provides the means to obtain excellent accuracy Data is corrected using a couple of formulas Equation 1 expresses the ideal relationship between the value ideal_count written to the 12 bit DAC to achieve a specified voltage within the 10 to 10 Volt output range assuming Bipolar Offset Binary BOB data format see Section 2 for details Ideal Count Count_Span Ideal_Volt_Span Desired_Voltage Ideal_Zero_Count 1 where Count Span 4096 a 12 bit converter has 212 possible levels Ideal Volt Span 20 Volts for the bipolar 10 to 10 Volt range Ideal_Zero_Count 2048 count for an ideal output of 0 Volts Equation 1 can be simplified using the above constants since the range and DAC are fixed on the IP220 Equation 2 results Ideal_Count 4096 20 Desired_Voltage 2048 Using equation 2 one can determine the ideal count for any desired voltage within th
19. arent Mode allows channels to be updated quickly on an individual basis since data written to the input latch is immediately transfered to the output latch and converted to an updated analog output voltage Selection of the Simultaneous Mode allows many or all channels to be updated at once In this mode the data for channels is written to their associated input latch but does not get transfered to the output latch until a Simultaneous Trigger command is sent All channels update synchronously and simultaneously upon receipt of the trigger command The logic interface provides 12 Volt supplies to the analog circuitry If desired the user has the option of providing 15 Volt external supplies However supplies cannot be mixed do not use 12V with 15V Rated outputs are achieved using either internal or external supplies and this is selected via hardware jumpers J1 8 J2 prior to powering the unit see Section 2 LOGIC POWER INTERFACE The logic interface to the carrier board is made through connector P1 refer to Table 2 4 Not all of the IP logic P1 pin functions are used P1 also provides 12V and 5V to power the module A programmable logic device installed on the IP Module provides the control signals required to operate the board It decodes the selected addresses in the and ID spaces and produces the chip selects control signals and timing required by the DAC s software registers and ID PROM as well as the acknowledg
20. at a specific time The Simultaneous Mode register must be written to first Then writing to the Simultaneous Output Trigger register creates the trigger for digital data to be converted and transferred to the board s field connector The 12 bit digital data written to the address specific channel s input latch will continue to be held until the Simultaneous Output Trigger register is written This will trigger the transfer of digital data from the D A input latch to the output latch and the digital to analog conversion producing the updated analog output Execution of a Simultaneous Output Trigger Write command requires 0 wait states The data written to this location D16 is immaterial since the write is sufficient to complete the action D15 D00 X means Don t Care the bit value does not matter RESET CONDITION Defaults to Simultaneous Mode All register bits are undefined All analog output channels are set to 0 Volts Note The reset function resets only the D A output latch of the input double buffer Therefore after a reset good data must be written to all the input latches before enabling the Transparent Mode or enabling the Simultaneous Output Trigger for a DAC output update Otherwise old data or unknown data present SERIES 1 220 INDUSTRIAL I O PACK 12 BIT HIGH DENSITY ANALOG OUTPUT MODULE in the input latches will be transferred to the D A output latch producing an undesired analog output The S
21. breviated to save space i e channel 0 is abbreviated as amp for the amp connections respectively Further note the output signals all have the same ground reference and the minus leads of all other channels are connected to analog common on the module Table 2 3 IP220 Field I O Pin Connections P2 Pin Description Number Pin Description Number 6 8 9 SERIES IP220 INDUSTRIAL PACK 12 BIT HIGH DENSITY ANALOG OUTPUT MODULE Note 1 minus leads of all channels are connected to analog common on the module Analog Output Noise and Grounding Considerations All output channels are referenced to analog common on the module See Drawing 4501 440 for analog output connections but each channel has a separate return minus lead to maintain accuracy and reduce noise Still the accuracy of the voltage output depends on the amount of current loading impedance of the load and the length impedance of the cabling High impedance loads e g loads gt 100 provide the best accuracy For low impedance loads the IP220 can source up to 5mA but the effects of source and cabling resistance should be considered Output common is electrically connected to the IP module ground As such the IP220 is non isolated between the logic and field grounds Consequently the field connections not isolated from the carri
22. d Physical Attributes See Drawing 4501 464 Field Wiring 50 position terminal blocks with screw clamps Wire range 12 to 26 AWG 12 Connections to 9630 9660 P1 50 pin male header with strain relief ejectors Use Acromag 5025 550 x or 5025 551 x cable to connect panel to VME board Keep cable as short as possible to reduce noise and power loss Mounting Termination panel is snapped on the DIN mounting rail Printed Circuit Board Military grade FR 4 epoxy glass circuit board 0 063 inches thick Operating Temperature 40 C to 100 C Storage Temperature 40 C to 100 C Shipping Weight 1 25 pounds 0 6kg packed TRANSITION MODULE MODEL TRANS GP Type Transition module for AVME9630 9660 boards Application To repeat field signals of IP modules A through D for rear exit from VME card cages This module is available for use in card cages which provide rear exit for connections via transition modules transition modules can only be used in card cages specifically designed for them It is a double height 6U single slot module with front panel hardware adhering to the VMEbus mechanical dimensions except for shorter printed circuit board depth Connects to Acromag termination panel 5025 552 from the rear of the card cage and to AVME9630 9660 boards within card cage via flat 50 pin ribbon cable cable Model 5025 550 X or 5025 551 X Schematic and Physical Attributes See Drawing 4501 465 Field Wir
23. del are indicated in BOLD ITALICS Table 2 4 Standard Logic Interface Connections P1 Pin Description Number Pin Description Number 5 39 Do 6 memset r 04 8 9 10 1 20 A 45 Bst 21 5 46 2 48 24 RESERVED 49 50 Asterisk is used to indicate active low signal BOLD ITALIC Logic Lines are NOT USED by this IP Model 3 0 PROGRAMMING INFORMATION This board is addressable in the Industrial Pack I O space to control the level of analog outputs in the field and to read offset and gain calibration coefficients The I O space may be as large as 64 16 bit words 128 bytes using address lines A1 A6 The IP220 uses this address space for enabling control signals for DAC functions and addressing offset and gain calibration coefficients used by the software to adjust the accuracy of the output range The calibration coefficients are accessed via reads from PROM in the I O space The I O space address map for the IP220 is shown in Table 3 1 below Note the base addresses for the IP module I O space see your carrier board instructions must be added to the addresses shown to properly access the space All accesses are performed on a 16 bit word basis DO D15 This manual is presented using the Big Endian byte ordering format Big Endian is t
24. e range For example if it is desired to output a voltage of 5 Volts equation 2 returns the result 3072 for Ideal_Count If this value is used to program the DAC output following conversion to Hex and left justification the output value will approach 5 Volts to within the uncalibrated error specified in Table 3 3 This will be acceptable for some applications 2 For applications needing better accuracy the software calibration coefficients should be used to correct the Ideal Count into the Corrected Count required to accurately produce the output voltage This is illustrated in equation 3 Corrected Count Ideal Gain Gain Correction Ideal Count Ideal Zero Count Ideal Zero Count Offset Correction 3 where Ideal Gain 1 Gain Correction PROM Gain Error 4 4096 Gain Error 16384 Offset Correction PROM Offset Error 4 Ideal Count is determined from equation 2 and Ideal Zero Count remains 2048 PROM Gain Error and PROM Offset Error are obtained from the PROM on the IP220 on a per channel basis Equation 3 can be written as 4 by making the listed substitutions Corrected Count 1 PROM Gain Error 16384 Ideal Count 2048 2048 PROM Offset Error 4 4 Using equation 4 you can determine the corrected count from the ideal count For the previous example equation 2 returned a result 3072 for the Ideal Count to produce an output of 5 Volts Assuming that a
25. ement signal required by the carrier board per the IP specification It also controls the mode selection and triggering to start DAC conversions for the Transparent and Simultaneous Modes The ID PROM read only installed on the IP module provides the identification for the individual module per the IP specification The Calibration PROM same physical device as the ID PROM but mapped into the space contains channel specific calibration coefficients to correct both offset and gain errors The coefficients must be used to trim the outputs to within their accuracy specification The PROM software registers and DAC s are all accessed through the 16 bit data bus interface to the carrier board 5 0 SERVICE AND REPAIR SERVICE AND REPAIR ASSISTANCE Surface Mounted Technology SMT boards are generally difficult to repair It is highly recommended that a non functioning board be returned to Acromag for repair The board can be damaged unless special SMT repair and service tools are used Further Acromag has automated test equipment that thoroughly checks the performance of each board When a board is first produced and when any repair is made it is tested placed in a burn in room at elevated temperature and retested before shipment Please refer to 5 Service Policy Bulletin or contact Acromag for complete details on how to obtain parts and repair PRELIMINARY SERVICE PROCEDURE Before beginning repair be sure that all of
26. ent Mode Use of the Transparent Mode provides the quickest method of updating the desired analog output This method is geared for those applications that require maximum speed without the need for updating all channels simultaneously In Transparent Mode each analog output channel is updated as soon as it is written to Multiple channels may be written to separately resulting in the analog outputs being updated one channel at a time Functionally the input latch is written to and the D A latch is automatically updated providing more speed by eliminating a separate write instruction Transparent Mode Programming Example 1 Write to the Transparent Mode register to setup the transparent type of data transfer 2 Read the PROM to acquire the channel s unique offset and gain calibration coefficient data This data is necessary to adjust by software the accuracy of the involved channel s analog output See USE OF CALIBRATION DATA 3 Write the 16 bit corrected 12 bit left justified digital data to the desired DAC Channel Register 4 OPTIONAL Observe or monitor that the specific DAC channel reflects the results of the digital data converted to an analog output voltage at the field connector 5 Repeat steps 1 4 until all the desired channels reflect the updated analog output voltage at the field connector Using the Simultaneous Mode Use of the Simultaneous Mode provides a method of distributing data simultaneously and synchrono
27. er board and backplane Care should be taken in designing installations without isolation to avoid noise pickup and ground loops caused by multiple ground connections This is particularly important for analog outputs when a high level of accuracy resolution is needed e g 12 bits or more Refer to Drawing 4501 440 for example output and grounding connections Contact your Acromag representative for information on our many isolated signal conditioning products that could be used to provide isolated voltage or current outputs when used in conjunction with the 220 output module IP Logic Interface Connector P1 P1 of the IP module provides the logic interface to the mating connector on the carrier board This connector is a 50 pin female receptacle header AMP 173279 3 or equivalent which mates to the male connector of the carrier board AMP 173280 3 or equivalent This provides excellent connection integrity and utilizes gold plating in the mating area Threaded metric M2 screws and spacers are supplied with the IP module to provide additional stability for harsh environments see Drawing 4501 434 for assembly details Field and logic side connectors are keyed to avoid incorrect assembly The pin assignments of P1 are standard for all IP modules according to the Industrial Pack Specification see Table 2 4 Note that the P220 does not utilize all of the logic signals defined for the P1 connector Logic lines NOT USED used by this mo
28. er requirements Be sure that the system power supplies are able to accommodate the power requirements of the carrier board plus the installed IP modules within the voltage tolerances specified IMPORTANT Adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature The dense packing of the IP modules to the carrier board restricts air flow within the card cage and is cause for concern SERIES IP220 INDUSTRIAL I O PACK 12 BIT HIGH DENSITY ANALOG OUTPUT MODULE Adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature and to prolong the life of the electronics If the installation is in an industrial environment and the board is exposed to environmental air careful consideration should be given to air filtering BOARD CONFIGURATION The board may be configured differently depending on the application All possible jumper settings will be discussed in the following sections The jumper locations are shown in Drawing 4501 441 Power should be removed from the board when configuring hardware jumpers installing IP modules cables termination panels and field wiring Refer to Mechanical Assembly Drawing 4501 434 and your IP module documentation for configuration and assembly instructions Default Hardware Jumper Configuration A board is shipped from the factory configured as follows Internal 12 Volt power supplies are u
29. fficient to complete the action D15 D00 X means DON T CARE the bit value does not matter RESET CONDITION Defaults to Simultaneous Mode All register bits are undefined All analog output channels are set to 0 Volts Note The reset function resets only the D A output latch of the input double buffer Therefore after a reset good data must be written to all the input latches before enabling the Transparent Mode or enabling the Simultaneous Output Trigger for a DAC output update Otherwise old or unknown data present in the input latches will be transferred to the D A output latch producing an undesired analog output In the Transparent Mode the Simultaneous Mode can be activated by a write to the Simultaneous Output Trigger register Simultaneous Mode Write Base 22H The Simultaneous Mode is a write only register will not respond to reads in the I O space that is used to select the simultaneous type of data transfer Once the Simultaneous Mode is selected 12 bit digital data written to the address specific channel s input latch will continue to be held until the Simultaneous Output Trigger register is written before digital data is transferred to the output latch and the updated analog output appears at the board s field connector The data of all the channels is simultaneously transferred once per simultaneous trigger from the D A input latch to the output latch and analog output updated on
30. he carrier board will cause undriven bits to be high The data format is Bipolar Offset Binary BOB see Section 2 for details MSB 15 14 13 12 11 10 9 lt X means Don t Care the bit value does not matter RESET CONDITION All output channels are set to 0 Volts Note The reset function resets only the D A output latch of the input double buffer Therefore after a reset good data must be written to all the input latches before a DAC output update by enabling the Transparent Mode or enabling the Simultaneous Output Trigger Otherwise old data or unknown data present in the input latches will be transferred to the D A output latch producing an undesired analog output Transparent Mode Write Base 20H The Transparent Mode is a write only register in the space that is used to select and enable the transparent type of data transfer it will not respond to reads Once the Transparent Mode is selected 12 bit digital data written to the address specific channel s input latch will automatically be converted and transferred to the board s field connector The data is transferred from the input latch through the D A latch transparent in this mode to the analog output field connector until a reset Simultaneous Mode or Simultaneous Output Trigger is enabled Execution of a Transparent Mode write command requires 0 wait states The data written to this location D16 is immaterial since the write is su
31. he convention used in the Motorola 68000 microprocessor family and is the VMEbus convention In Big Endian the lower order byte is stored at odd byte addresses Thus byte accesses are done on odd address locations The Intel x86 family of microprocessors use the opposite convention or Little Endian byte ordering Little Endian uses even byte addresses to store the low order byte As such use of this module on an ISAbus PC AT carrier board will require the use of the even address locations to access the data while a VMEbus carrier will require the use of odd address locations SERIES 1 220 INDUSTRIAL PACK 12 BIT HIGH DENSITY ANALOG OUTPUT MODULE 2 Channels 8 15 are present in the IP220 16 Model only ADDRESS MAPS The following sections give details on the function of each location in the I O space noted above Table 3 1 IP220 I O Space Address Memory Base Even Byte Odd Byte IP Identification PROM Read Only 32 odd byte addresses Address D15 008 007 000 Each IP module contains an identification ID PROM that W DAC Channel 0 resides in the ID space per the IP module specification This area of W DAC Channel 1 memory contains 32 bytes of information at most Both fixed and W DAC Channel 2 variable information may be present within the ID PROM Fixed W DAC Channel 3 information includes the IPAC identifier model number and W DAC Channel 4 manufacturer s identification codes Variable inf
32. imultaneous Mode can also be activated while in Transparent Mode if a write occurs to the Simultaneous Output Trigger register Channel Offset Gain Error Coeff Read Base 41 to 7FH Calibration data is provided in the form of calibration coefficients so the user can adjust and improve the accuracy of the analog output voltage over the uncalibrated state Each channel s unique offset and gain calibration coefficients are stored PROM These coefficients can be retrieved read only by accessing the last 32 odd bytes 41H to 7FH of the I O space 008 or using the lower 8 bits for D16 accesses The offset and gain calibration coefficients read from the PROM are stored with 1 4 LSB resolution Thus it is necessary to divide each coefficient by four to correctly use them when calibrating the bipolar outputs Each is stored as a two s complement i e signed eight bit number This number has a range of 128 to 127 which represents the offset or gain adjustments from 32 to 31 75 LSB s Execution of a Channel Offset or Gain Error Read command requires 0 wait states EVEN BYTE ODD BYTE MSB LSB 7 6 5 4 3 2 1 0 15 14 13 121110 9 8 gt 55 PROGRAMMING CONSIDERATIONS FOR ANALOG OUTPUTS The IP220 provides two methods of analog output programming for maximum flexibility with different applications The following paragraphs describe the features of each and how to best use them Using the Transpar
33. ing 100 pin header male connectors 3433 0303 or equivalent employing long ejector latches and 30 micron gold in the mating area MIL G 45204 Type 1 Grade C Connects to Acromag termination panel 5025 552 from the rear of the card cage via flat 50 pin ribbon cable cable Model 5025 550 X or 5025 551 X Connections to AVME9630 9660 50 pin header male connectors 8M 3433 1302 or equivalent employing long ejector latches and 30 micron gold in the mating area per MIL G 45204 Type Il Grade C Connects to AVME9630 9660 boards within the card cage via flat 50 pin ribbon cable cable Model 5025 550 X or 5025 551 X Transition module is inserted into a 6U size single width slot at the rear of the VMEbus card cage Mounting Transition module is inserted into a 6U size single width slot at the rear of the VMEbus card cage Printed Circuit Board Six layer military grade FR 4 epoxy glass circuit board 0 063 inches thick Operating Temperature 40 C to 85 C Storage Temperature 55 C to 105 C Shipping Weight 1 25 pounds 0 6Kg packed 2 1 800 0 020 i x COMPONENT SIDE VIEW 3 900 0 020 POWER SUPPLY SELECTIONS PINS OF J1 AND J2 POWER SUPPLY J1 m J2 42 SELECTION 1 amp 2 2 amp 3 1 amp 2 2 amp 3 37 12 VOLT INTERNAL P mw 37 15 VOLT EXTERNAL P2 m INTERNAL AND EXTERNAL SUPPLIES SHOULD NOT BE MIXED
34. itry Review the block diagram shown in Drawing 4501 439 as you study the following paragraphs ANALOG OUTPUTS The field interface to the carrier board is provided through connector P2 refer to Table 2 3 Field analog outputs are NON ISOLATED This means that the field return output channel minus and logic common have a direct electrical connection to each other As such care must be taken to avoid ground loops and excessive output loading see Section 2 for connection recommendations Ignoring this effect may cause operation errors and with extreme abuse possible circuit damage Refer to Drawing 4501 440 for example analog output and grounding connections The fully populated board contains sixteen 12 bit DAC s IP220 16 one per channel This allows each channel to be independently programmed for maximum speed and accuracy and avoids the problems associated with designs using sample and hold amplifiers multiplexed to a single DAC Each DAC may source up to 5mA of output current without requiring separate buffer amplifiers DAC calibration is done via software to avoid the mechanical drawbacks of hardware potentiometers for each DAC channel This also conserves board space and helps to achieve high channel density Calibration parameters are stored in PROM on a per channel basis DAC inputs are double buffered This allows channels to be programmed by either of two modes software register selectable 10 The Transp
35. ly when the Simultaneous Output Trigger register is enabled Execution of a Simultaneous Mode Write command requires 0 wait states The data written to this location D16 is immaterial since the write is sufficient to complete the action D15 D00 X means Don t Care the bit value does not matter RESET CONDITION Defaults to Simultaneous Mode All register bits are undefined All analog output channels are set to 0 Volts Note The reset function resets only the D A output latch of the input double buffer Therefore after a reset good data must be written to all the input latches before enabling the Transparent Mode or enabling the Simultaneous Output Trigger for a DAC output update Otherwise old data or unknown data present in the input latches will be transferred to the D A output latch producing an undesired analog output The Simultaneous Mode can also be activated while in Transparent Mode if a write occurs to the Simultaneous Output Trigger register Simultaneous Output Trigger Write Base 24H The Simultaneous Output Trigger is a write only register will not respond to reads in the I O space that produces the pulse needed to trigger the simultaneous type of data transfer The Simultaneous Output Trigger register works in conjunction with the Simultaneous Mode register to simultaneously transfer all the channels digital data from the D A input latch to the output latch and update the analog output
36. nal 15 volt power supplies sourced through P2 are not required to achieve rated output 4 The actual outputs may fall short of the range endpoints due to hardware offset and gain errors The software calibration corrects for these across the output range but cannot extend the output beyond that achievable with the hardware 5 Offset and gain calibration coefficients stored in the ID PROM must be used to perform software calibration in order to achieve the specified accuracy Specified accuracy does not include quantization error Follow the output connection recommendations of Section 2 because non ideal grounds can degrade overall system accuracy 6 The reset function resets only the D A i e output latch of the input double buffer Therefore after a reset good data must be written to all the input latches before a simultaneous DAC output update Otherwise old data or unknown data present in the input latches will be transferred to the D A output latch producing an undesired analog output INDUSTRIAL I O PACK COMPLIANCE Specification This module meets or exceeds all written Industrial Pack specifications for Type modules per ANSI VITA 4 1995 Electrical Mechanical Interface Single Size IP Module IP Data Transfer Cycle Types Supported Input Output IOSel 16 bit word write of 12 bit left justified channel data 16 bit write to control registers 16 bi
37. of interrupt handlers all the complicated details of programming are handled by the OLE controls These functions are intended for use in conjunction with the APC8610 ISAbus PC AT carrier and consist of a Carrier Configuration Program and APC8610 OLE control and an OLE control for each Acromag I O Pack model 2 0 PREPARATION FOR USE UNPACKING AND INSPECTION Upon receipt of this product Inspect the shipping carton for evidence of mishandling during transit If the shipping carton is badly damaged or water stained request that the carrier s agent be present when the carton is opened If the carrier s agent is absent when the carton is opened and the contents of the carton are damaged keep the carton and packing material for the agent s inspection For repairs to a product damaged in shipment refer to the Acromag Service Policy to obtain return instructions W It is suggested that salvageable shipping cartons and packing material be saved for future use in the event the product must be shipped This board is physically protected with packing material and electrically protected with an anti static bag during shipment Itis recommended that the board be visually inspected for evidence of mishandling prior to applying power CAUTION The board utilizes static sensitive components and should only be handled at a static safe workstation CARD CAGE CONSIDERATIONS Refer to the specifications for loading and pow
38. ormation includes DAC Channel 5 unique information required for the module 1 220 ID PROM bytes are addressed using only the odd addresses in a 64 byte block The 220 ID PROM contents are shown in Table 3 2 Note that the base address for the IP module ID space see your carrier board instructions must be added to the addresses shown to properly access the ID PROM Execution of an ID PROM Read requires 0 wait states W DAC Channel 12 W DAC Channel 13 W DAC Channel 14 Table 3 2 IP220 ID Space Identification ID PROM W DAC Channel 15 Hex Offset W Transparent Mode From ID ASCII Numeric PROM Base Character Value Field W Simultaneous Output Trigger Address Equivalent Description All IP s have IPAC 24 0 08 24 26 3E NOT USED 7 R CHO Offset Error Ll 44 Offset Error Ll R CH1 Gain Error 7 Offset Error 7 2 Gain Error Ll Offset Error Ll R CH3 Error 7 R CH4 Offset Error 8 5 Offset Error 5 R CH6 Offset Error SA RCH6 Error 5c RCHZ Offset Error 5E R CH8OfsetEmo 62 84 R CH9GanEmo 6 R CHi0Of setEmor 6A RCHIOGain Error
39. re adhering to the VMEbus mechanical dimensions except for shorter printed circuit board depth Connects to Acromag Termination Panel 5025 552 from the rear of the card cage and to AVME9630 9660 boards within the card cage via flat 50 pin ribbon cable cable Model 5025 550 X or 5025 551 X INDUSTRIAL I O PACK SOFTWARE LIBRARY Acromag provides an Industrial Pack Software Library diskette Model IPSW LIB M03 MSDOS format to simplify SENSITIVE ELECTRONIC DEVICES DO NOT SHIP OR STORE NEAR STRONG ELECTROSTATIC ELECTROMAGNETIC MAGNETIC OR RADIOACTIVE FIELDS communication with the board All functions are written in the programming language and can be linked to your application Refer to the README TXT file in the root directory and the INFO220 TXT file in the IP220 subdirectory on the diskette for more details INDUSTRIAL I O PACK OLE CONTROL SOFTWARE Acromag provides a software diskette of Industrial Pack Object Linking and Embedding OLE drivers for Windows 95 and Windows NT compatible application programs Model IPSW DVR OLE PC MSDOS format This software provides individual drivers that allow Acromag I O Packs and the APC8610 carrier to be easily integrated into Windows application programs such as Visual C Visual Basic etc The OLE controls provide a high level interface to Acromag Packs eliminating the need to perform low level reads writes of registers and the writing
40. s 4596 from 2 See Notes 1 amp 2 Below 12 Volts 590 from P1 or 80mA Typical 180mA Maximum 15 Volts 45 from P2 See Notes 1 amp 2 Below Non Isolated Logic and field commons have a direct electrical connection Notes Power 1 The 12 volt power supplies are normally supplied through P1 logic interface connector Optionally jumper selectable on the IP the user may connect external 15 volt supplies through the field I O interface connector P2 2 The maximum current draw assumes that the rated current of 5mA per channel is drawn Current draw will be reduced proportionately for high impedance output loads ANALOG OUTPUTS Output Channels Field Access P220 16 16 Single Ended IP220 8 8 Single Ended Output Type Voltage Non isolated Output Range Bipolar 10V to 10 See Notes 3 amp 4 Output Current 5mA to 5mA Maximum this corresponds to a minimum load resistance of 2KO with a 10V output See Notes 3 amp 4 Data Format left justified Bipolar Offset Binary BOB DAC Programming Immediate transparently programmed to DAC output Simultaneous input latches of multiple DAC s are loaded with new data before simultaneously updating DAC outputs 12 bits 11
41. sed sourced from P1 Analog output range is 10 to 10 Volts and is not configurable Programmable software register bits are undefined at reset but the board defaults to O Volts on all analog outputs and the Simultaneous Channel Update Mode see Section 3 Power Supply Hardware Jumper Configuration Hardware jumpers J1 amp J2 allow the selection of internal or external analog power supplies J1 J2 controls the selection of either the internal 12 12 Volt supply sourced from the P1 connector or the external 15 15 Volt supply sourced from the P2 connector The IN OUT configuration of the jumpers for the different supplies is shown in the following table IN means that the pins noted are shorted together with a shorting clip OUT means that the clip has been removed Table 2 1 Power Supply Selections Pins of J1 and J2 Power Supply J1 J1 J2 J2 Selection 1 amp 2 2 amp 3 182 2 amp 3 12 Volt Internal P1 15 Volt External P2 Do not mix internal and external supplies e g do not use 12V internal with 15V external Note that the IP220 module can achieve rated output using either internal or external supplies Programmable Register Configuration Programmable registers are software configurable That is there are no hardware jumpers associated with them Registers must be accessed to select the desired mode of operation and to update analog outputs refer to Section 3 for details
42. t read of 8 bit right justified DAC SERIES 1 220 INDUSTRIAL I O PACK 12 BIT HIGH DENSITY ANALOG OUTPUT MODULE offset and gain calibration coefficients ID Read IDSel 32x8 ID PROM read on DO D7 Access Times 8MHz Clock ID PROM Read 0 wait states 250ns cycle DAC Channel Data Write 0 wait states 250ns cycle DAC Offset Gain Coeff Read 0 wait states 250ns cycle Control Register Writes 0 wait states 250ns cycle APPENDIX CABLE MODEL 5025 550 x Non Shielded MODEL 5025 551 x Shielded Type Flat Ribbon Cable 50 wires female connectors at both ends The x suffix designates the length in feet 12 feet maximum Choose shielded or unshielded cable according to model number The unshielded cable is recommended for digital I O while the shielded cable is recommended for optimum performance with precision analog I O applications Application Used to connect Model 5025 552 termination panel to the AVME9630 9660 non intelligent carrier board A D connectors Both have 50 pin connectors Length Last field of part number designates length in feet user specified 12 feet maximum It is recommended that this length be kept to a minimum to reduce noise and power loss Cable 50 wire flat ribbon cable 28 gage Non Shielded cable model uses Acromag Part 2002 211 C3365 50 or equivalent Shielded cable model uses Acromag
43. updated analog output voltages at the field connector 6 OPTIONAL Observe or monitor that DAC channels reflect the results of the digital data converted to an analog output voltage at the field connector 7 Repeat steps 2 6 for continued simultaneous and synchronous triggered updates of all desired channels USE OF CALIBRATION DATA Calibration data is provided in the form of calibration coefficients so the user can adjust and improve the accuracy of the analog output voltage over the uncalibrated state Each channel s unique offset and gain calibration coefficients are stored in the PROM The use of software calibration allows the elimination of hardware calibration potentiometers traditionally used in producing precision analog outputs A comparison of the uncalibrated and software calibrated performance is shown to illustrate the importance of the software calibration Software calibration uses some fairly complex equations Acromag provides you with the Industrial I O Pack Software Library diskette to make communication with the board and calibration easy It relieves you from having to turn the equations of the following sections into debugged software calibration code The functions are written in the C programming language and can be linked to your application Refer to the README TXT file in the root directory and the INFO220 TXT file in the IP220 subdirectory on the diskette for details SERIES IP220 INDUSTR
44. using the transparent output mode e Simultaneous Output Control All output channels can be simultaneously updated with a single software trigger command when using the simultaneous output mode DAC s are double buffered which allows new data to be written to each channel before the simultaneous trigger updates the outputs SERIES 1 220 INDUSTRIAL I O PACK 12 BIT HIGH DENSITY ANALOG OUTPUT MODULE Easy Mode Selection Selection of transparent and simultaneous output modes is easily done via software commands Resetis Failsafe Outputs reset to 0 volts following a power up or reset INDUSTRIAL I O PACK INTERFACE FEATURES High density Single size industry standard IP module footprint Up to four units may be mounted on a carrier board e Local ID Each IP module has its own 8 bit ID PROM which is accessed via data transfers in the ID Read space 16 bit I O Control register writes DAC writes and calibration coefficient reads are performed through 16 bit data transfer cycles in the IP module Input Output space e High Speed This IP model does not generate any wait states Thus all data transfers proceed at maximum speed with O wait states Hold State Support This IP module supports Hold states if generated by the carrier board SIGNAL INTERFACE PRODUCTS See Appendix for more information on compatible products This IP module will mate directly to any industry standard IP carrier board
45. usly to produce desired analog outputs This method is useful for applications that require updating all the channels simultaneously and synchronously Each channel is written to with the required 16 bit 12 bit left justified data When all the required channels contain the desired digital data then a write to the Simultaneous Output Trigger register will produce a pulse to simultaneously trigger each channel s digital to analog converter Thus all the analog outputs are updated simultaneously Functionally each input latch is written to separately When all input latches contain the desired digital data then all channels are pulsed simultaneously and synchronously to convert to the updated analog output voltage Simultaneous Mode Programming Example 1 Write to the Simultaneous Mode register to setup the simultaneous type of data transfer 2 Read the PROM to acquire the channel s unique offset and gain calibration coefficient data This data is necessary to adjust by software the accuracy of the involved channel s analog output See USE OF CALIBRATION DATA 3 Write the 16 bit corrected 12 bit left justified digital data to the desired DAC Channel Register 4 Repeat steps 2 3 to write new digital data to the DAC Channel Registers for all other channels requiring update 5 Write to the Simultaneous Output Trigger register to produce a pulse to simultaneously trigger digital to analog conversions for all channels resulting in
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