EE201L_divider_sp201..
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1. 23 1 means T 0 168 sec MC means MCEN count count of MCEN pulses MCEN Cont MCEN Continuous state Here MCEN behaves like CCEN See the output coding table on page 3 Names of the students submitting EE201L divider sp2011 fm 3 1 11 5 9 C 2011 Gandhi Puvvada 5 ee201_ divider_with_ single step Here in the compute state we single step the division operation using the SCEN produced out of Btn2 ee201 divider with single step Go through the files and download the provided bit file and test x O 2 a A l Z e gt 3 i 4 Qi ANITIAL REMINDER Mo Qc COMPUTE E es Note that unlike in the first design ee201 divider simple we run the core divider in this design at the full speed of 50Mhz Mm Qd DONE Ss w Ss DIVIDEND DIVISOR SINGLE STEP START ACK Notice the following aspects of the design A The divider and the divider instantiation have a new port pin called SCEN for the top level design to generate and pass SCEN pulses Single Clock wide clock enable pulses more accurately data enable pulses as the clock itself is not inhibited f instantiate the core divider design Note the SCEN SCEN divider divider 1 Xin Xin Yin Yin Start Start Ack Ack Clk sys_ clk Reset Reset ee Done Done Quotient Quotient Remainder Remainder Qi Qi Qc Qc Qd Qd B Single Step Control can easily be exercised on selected states such2. behavior change Does your answer to Q 1 above change C Why does the behavior of the next design ee201 divider_with debounce appear to be quite different from this design Is it just appearance only or 1s it really different EE201L divider sp2011 fm 3 1 11 2 9 C 2011 Gandhi Puvvada 4 ee201 divider _ with debounce First a debouncer design ee201_ debounce DPB SCEN CCEN MCEN v is presented to debounce a given push button and produce 4 outputs DPB SCEN CCEN MCEN Output coding for the states in the state machine is used for glitch free outputs state Name DPB SCEN MCEN CCEN TB1 TBO initial TB1 and TBO are the tie breakers to break aliasing in output codes Walt quarter WO SCEN state SCEN st Wait half WH MCEN state MCEN st CCEN state CCEN st MCEN cont MCEN st Counter Clear CCR WECR state WECR o amp o 6 oS oS e ee ee oo coc coc O orcricacF ie So oF FP FP SG eHIO ISE gt Help gt Software Manuals gt Click on Design Verification Design Synthesis in the diagram copy shown on sibel the side gt XST User guide gt Search for FSM Behavioral E di Simulation ncoding Design synthesis As shown here we used verilog attributes to enforce our output coding Through these attributes we are informing the tool vendor Xilinx here that Functional simulation Design we want the tool to honor and retain our user encod Implementation p ysis me Back Timing Annotation Simulation It is
3. possible or it works if we produce a Btn0 SCEN and gt use it as START as well as ACK or f E r v z 6 ee201 divider with VIO multi step and the Epp Interface Here we are interfacing to the virtual I O in Adept 2 0 The file IOExpansion vhd provided by Digilent implements the Epp slave side address and data registers in FPGA We translated the same to Verilog The file is called IOExpansion v Note that now the UCF file needs to have pins associated with Epp to talk to the Cypress USB interface chip Please refer to the Adept User s manual on your PC Start gt All Pro grams gt Digilent gt Adept gt Adept User s manual ee201_divider_with_VIO_multi_step Multiplexing the two displays on the four 7 seg displays using Btn DIVIDEND DIVISOR QUOTIENT REMAINDER o through the files and download I T I iTi Im 1m m mi he provided bit file and test m f Nie l l l l ll il l l A e when btn1 is not pressed when btn1 is pressed DISPLAY SELECT Step ACK 5 O START zil II Itt The switches on the board are not used here 8 bit dividend and 8 bit m m divisor are set using the 16 switches on Adept IOExpansion W Multi WE RESET START ACK EE201L divider sp2011 fm 3 1 11 7 9 C 2011 Gandhi Puvvada Cypress E USB pH NET EppDB lt 0 gt _ LOC R14 Epp USB miniBB Address Write connector l l DB X y Spartan 3E FPGA W
4. EE201L Divider design Objective To introduce to students RTL coding style for state machine and datapath coding Testbench example Simple TOP design making use of I O resources on Nexys 2 board UCF file example Introduce Epp protocol Exploit the I O resources in Adept 2 0 I O Expansion References for the TAs not for students 1 Nexys 2 board reference manual Nexys2_rm pdf and schematic http www digilentinc com Products Detail cfm NavPath 2 400 789 amp Prod NEX Y S2 http www digilentinc com Data Products NEX YS2 Nexys2_rm pdf http www digilentinc com Data Products NEX YS2 Nexys2_sch pdf 2 Epp protocol First 4 pages of the Digilent Parallel Interface Model Reference Manual http www digilentinc com Data Products ADEPT DpimRef 20programmers 20manual pdf Also see http www beyondlogic org epp epp htm Files provided A zip file is provided containing source files for four sample designs in four folders Please read the notes at the top of each file to get to know important aspects of the design to note 1 ee201 divider simple 2 ee201 divider with debounce 3 ee201 divider with single step 4 ee201 divider with VIO multi step A short description of each of the above 4 designs follows 3 ee201 divider_simple Points to note Extract from divider combined cu dpu v The datapath elements shall be inferred by the syn jes ea thesis tool So we do not code OFL explicitly See the begin diagram o
5. RITE Aao A gt JTAG port PROG sB Lf Slave seral DONE WAIT port Data Write Data Read WRITE write si DSTB DSTB if WAIT WAIT The following signals make up the interface Name Source Description DBO DB7 bidir Data bus The host is the source during write cycles and the peripheral is the source during read cycles WRITE host Transfer direction control Hiah read Low write ASTB host Address strobe Causes data to be read or written to the address register DSTB host Data strobe Causes data to be read or written to a data register WAIT peripheral synchronization signal used to indicate when the peripheral is read to accept data or has data available Instead of viewing this as a low active wait 1t may be easier to view it as a high active GOT signal Notice that the Epp protocol implements the full 4 way handshake EPP Address register always posedge EppAstb begin Epp Address Register is written at the end of the Epp Address Strobe because Epp Write control line is Extract of _ gt IOExpansion v if Eppwr ar aa eee TS CCEDPNEI o low indicating intent to write regEppAdr lt EppDB Your PC running Adept 2 0 or higher is the Epp master which drives the three control lines EppAstb Epp Address Strobe active low ending edge is posedge EppDstb Epp Data Strobe active low ending edge is posedge EppWr Epp Write Control active low low means intent to w
6. as the compute state in the divider as shown below The if SCEN clause before begin ensures that 1 all state transformations from the COMPUTE state and 11 all data transformations with in the compute state are under the control of SCEN We do not have to rewrite the state diagram as shown below COMPUTE Original if SCEN Notice SCEN begin RS state transitions in the control unit if X lt Y state lt DONE S RTL operations in the Data Path if X lt COMPUTE Difficult way begin X lt X Y Quotient lt Quotient 1 end if X gt Y SCEN X lt X Y Q lt Q 1 EE201L divider sp2011 fm 3 1 11 6 9 C 2011 Gandhi Puvvada Questions on ee201 divider with single step A Is it possible to use SCEN to control one state or a few states MCEN to control another state or a sep arate bunch of states and further CCEN to control yet another state B If we are simulating an external event such as a sensor embedded under a road for traffic light control we can produce a Btnl_ SCEN pulse SCEN pulse produced by pressing Btn1 can you single step such a system using another button say Btn2 to produce Btn2 SCEN Do you see any problem operational or logical or Can we choose to place all three states of the divider design under single stepping control and simultaneously combine Start and Ack z ie as ee Ne E under one button say Btn0 5 m Is this just not
7. l the four folders have verilog source files ucf source file a bit file of the completed design After reading the code you can download the bit file to the Nexys 2 500K board and operate the divider The bit files provided to you have a TAs prefix so that you do not overwrite when you compile the sam ple designs to get practice in forming a xilinx project and implementing the same When you are done you will submit a report to your TA your answers to questions posted under first three designs No questions are posted for the last design 8 Celebrate your success Don t forget this step EE201L divider sp2011 fm 3 1 11 9 9 C 2011 Gandhi Puvvada
8. n the next page state lt INITIAL 8 P 8 X lt ee ae Tp ee to avoid f Y lt 4 bXXXX recirculating mux The datapath and the control unit can be combined in Quotient lt 4 bXXXX controlled by Reset one case statement under clock as shown in else divider combined_cu_dpu v Notice the lines on the side which avoid unnecessary recirculating muxes OO OO90900090 i l l j We have also provided another file SSDS sgp2 ems divider separate cu dpu v a E E m E E 7 ae BTNO EE201L divider sp2011 fm 3 1 11 1 9 C 2011 Gandhi Puvvada Traditional division Division between DPU and between DPU and CU CU for HDL coding OFL combinational logic OFL combinational logic is in the CU is moved to DPU It is NOT coded explicitly The OFL is implicit in the DPU s RTL in the CASE statement NSL l p Current State CU ee201 divider simple Go through the files and download the provided bit file and test E 3 Qi ANITIAL A gt O S QO Q D W A Qd DONE s DIVIDEND DIVISOR Questions for the ee201_ divider_simple design A What happens if you divide by zero Is the behavior of the quotient digit display on SSD1 different if you attempt to divide 3 by 0 vs if you attempt to divide F by 0 How about 0 divided by 0 B If you improve the divider design to move from compute state to done state if X is equal or less than Y instead of the current X less than Y will the above
9. possible to set FSM Encoding option under ISE gt Synthesis XST gt Properties gt HDL options gt FSM Encoding Algorithm User But this will apply to the entire design iling Device In Circuit Programming Verification fsm encoding user Verilog attributes are placed in parentheses between asterisks Another example reg 5 0 state full case parallel case case state FSM Encoding Algorithm Verilog Syntax Example Place FSM Encoding Algorithm immediately before the module or signal declaration fsm _ encoding auto one hot compact sequential gray johnson speed1l user The default is auto EE201L divider sp2011 fm 3 1 11 3 9 C 2011 Gandhi Puvvada Read the code ee201 debounce DPB SCEN CCEN MCEN v and complete the state diagram on the next page Simulate it using ee201_ debounce DPB SCEN CCEN MCEN tb v for 9 us ee201 debouncer N dc 4 ee201 debouncer 1 CLK Clk tbh RESET Reset th PB PB th Notice that the testbench has instantiated the UUT with N dc of 4 in the generic map DPE DEE th SCEN SCEN tb MCEN MCEN tb CCEN CCEN tb Questions on the debouncer 1 Briefly explain why the N dc parameter was changed to 4 during simulation from the actual value of 24 for synthesis and implementation Use words such as inefficient wasteful readability of waveform etc 2 When you simulate zoom into the area of above wavefo
10. rite high means intent to read The EppDB is the Epp 8 bit data bus During an active address or data strobe Epp master drives data if write 1s true EppWr 0 else slave drives data if read is true EppWr 1 Active low WAIT active high GOT acts like a hand shake signal between the two parties Address Read Cycle is not implemented in Adept Virtual I O protocol EE201L divider sp2011 fm 3 1 11 8 9 C 2011 Gandhi Puvvada ee201 divider with VIO multi step In this example 58H is the dividend and 04H is the divisor The quotient is 16H and the remainder is 00H Dividend Divisor Connect Onboard USB ee GE _ Product Nexys2 500 Dividend Divisor Quotient Remainder Config Test Register I O File 1 0 WOEx Settings From FPGA Light Bar Replica of Nexys 2 LEDs NK Zo oe Format Hexadecimal pet i oooO Buttons ral See EE e e en ee Can be used to set Divisor X Can be used to set Dividend I Sn ecnenenonenens Replica of Nexys 2 Buttons Light Bar Light Bar eee VOO00800 00000000 DUUNIA Light Bar when not lit m Btn 2 Btn 1 Btn 0 Btn 2 Btn 1 Bat 7 Task to be performed Download the zip file provided to you into your C xilinx_projects directory and extract files to form C xilinx projects ee201 divider _verilog directory with 4 sub folders 1 ee201 divider simple 2 ee201 divider with debounce 3 ee201 divider with single step 4 ee201 divider with VIO multi step Al
11. rm extract and arrive at your answer for the above question in the waveform extract why do we see 8 more pulses on MCEN after already seeing two pulses 3 We took time to design output coded state machine with no OFL at all there by avoiding any glitches in the SCEN MCEN etc Are glitches really harmful in our design or we have just shown a way to produce glitch free outputs 4 Did we use the DPB Debounced Push Button pulse or SCEN Single Clock enable pulse to act as the Start signal and the Acknowledge signal Could we have used anyone of them ee201 divider_with debounce QUOTIENT REMINDER Go through the files and download the provided bit file and test DIVDND DIVISOR iI II ii l l 3 Qc COMPUTE 3 Qi CNITIAL 3 Qd DONE S I I I 1 I Note that unlike in the earlier design ee201 divider simple we run the core divider in this design at the m n m full speed of 50Mhz C3 a C3 Pn Fae Fama SEs DIVIDEND DIVISOR RESET START ACK EE201L divider sp2011 fm 3 1 11 4 9 C 2011 Gandhi Puvvada Debouncing State Machine Complete the missing state transition conditions and also any RTL in the state MCEN Cont PB PB T 0 084 OS INI I lt 0 SCEN St I lt 0 PBeT 0 084 MC lt MC 1 PBeT 0 084 CCEN St MCEN St I lt 0 MC lt MC 1 I lt I 1 PBeT 0 168 count 22 1 22 1 means T 0 084 sec count 23 1
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