ISP Synario System Design Tutorial
Contents
1. Figure 1 25 Synario Project Navigator 49 To create the source highlight the abeltop source then select Source gt New In the New Source dialog box choose ABEL HDL Module and click OK A Synario Text Editor appears with the New ABEL HDL Source dialog box Figure 1 26 SynarioTextEditor A File View Templates Tools dad stall ea Module Hame abeltop File Hame abeltop abl Title This is the Top Level ABEL file COo o T T T Pem Ne _ Figure 1 26 New ABEL HDL Source Dialog Box ISP Synario System Design Tutorial 28 In order for the file to be linked to the symbol the Module Name must match the symbol name The File Name does not need to match the symbol name but to make things simple in this tutorial you will make them the same Fill in the text fields as follows Module Name abletop File Name abeltop abl Title This is the Top Level ABEL file Click OK You will now be in the Synario Text Editor and will see the ABEL HDL framework already started for you 50 Enter the code as follows Make sure that you enter it between the TITLE statement and the END statement as shown in Figure 1 27 LA DUS INL INZ INS pio QUEPUES OUTL OUTZ OUTS OUT4 pias Equations OUT1 IN1 amp LING OUT2 IN1 amp IN2 OUT3 IN1 amp IN2 IN OUT4 IN2 amp IN3 o nario Text Editor abeltop abl Options Window Help TITLE This is the Top Level ABEL file Inputs2. Lattice a Semiconductor CETER Corporation ISP Synario System Design Tutorial Technical Support Line 1 800 LATTICE or 408 428 6414 ISPSYN TT Rev 3 00 Copyright This document may not in whole or part be copied photocopied reproduced translated or reduced to any electronic medium or machine readable form without prior written consent from Lattice Semiconductor Corporation LSC The software described in this manual is copyrighted and all rights are reserved by Lattice Semiconductor Corporation Information in this document is subject to change without notice The distribution and sale of this product is intended for the use of the original purchaser only and for use only on the computer system specified Lawful users of this product are hereby licensed only to read the programs on the disks cassettes or tapes from their medium into the memory of a computer solely for the purpose of executing them Unauthorized copying duplicating selling or otherwise distributing this product is a violation of the law Trademarks The following trademarks are recognized by Lattice Semiconductor Corporation Generic Array Logic ISP ispATE isoCODE isoDOWNLOAD ispGDS ispStarter ISOSTREAM Latch Lock pDS RAL RFT and Twin GLB are trademarks of Lattice semiconductor Corporation E CMOS GAL ispGAL ispLSI pDS pLSI Silicon Forest and UltraMOS are registered trademarks of Lattice Semiconductor Corporation Mic
3. Limitations on Warranty Any applicable implied warranties including warranties of merchantability and fitness for a particular purpose are hereby limited to ninety days from the date of purchase and are subject to the conditions set forth herein In no event shall Lattice Semiconductor Corporation be liable for consequential or incidental damages resulting from the breach of any expressed or implied warranties Purchaser s sole remedy for any cause whatsoever regardless of the form of action shall be limited to the price paid to Lattice Semiconductor Corporation for the Lattice Semiconductor software The provisions of this limited warranty are valid in the United States only Some states do not allow limitations on how long an implied warranty lasts or exclusion of consequential or incidental damages so the above limitation or exclusion may not apply to you This warranty provides you with specific legal rights You may have other rights which vary from state to state ISP Synario System Design Tutorial 3 Table of Contents PICIOCO pesca serene router edad aa pra beni 5 A E A 6 Where to Look for Information o ooooooono eee eee ee 6 Documentation Conventions n anaa aaa a eae 7 Related Documentation a na naaa aaa aaa 8 Lattice Semiconductor 0 0 eet eee eee eee 8 O Mal autres eres recrea ritos bea 8 Software Support ee ee eee eee tenes 9 CU lome HOUING 44 044 bade arcano 4 4s aa an e 9 Chap
4. Monospaced Courier font indicates file and directory names and text that the system displays For example INPUT S2 lt 50 7 SDE Clock Bold Courier font indicates text you type in response to system prompts For example dpm if edif of verilog Vertical bars indicate options that are mutually exclusive you can select only one For example S ald Titles of chapters or sections in chapters in this user manual are shown in quotation marks For example Property File Indicates a special note Indicates a situation that could cause loss of data or other problems Indicates a special hint that makes using the software easier Indicates a menu option leading to a submenu option For example File gt New ISP Synario System Design Tutorial 7 Related Documentation Related Documentation In addition to this tutorial the following documents are useful when using the ISP Synario System Lattice Semiconductor m pDS Fitter User Manual m Lattice Semiconductor Data Book Synario ISP Synario System User Manual Project Navigator User Manual Equation 8 JEDEC Simulators User Manual Schematic Entry User Manual Waveform Tools Manual ISP Synario System Design Tutorial 8 Software Support Software Support Customer Hotline lf you have any questions or problems with this software please call Lattice Semiconductor Applications Hotline at 1 800 LATTICE 1 800 528 8423 or 408 428 6414 The Hotli
5. The tutor rpt window appears within the Synario Report Viewer Figure 1 33 You can scroll through the report window for your design data oynario Report Viewer File Edit View Options Window Help tutor rpt l l is pLSI Development System Plus Release 2 2 11 Jun 19 1996 14 49 24 4 Design Parameters IGNORE FIAED PIN OFF HAs GLB IW 16 is pLS11060 is pLSI20060 24 4 MAX GLB OUT STRATEGY AREA Design Specification BE gt Ent Cal 1223 RO RecOff Nowrap DOS INS NUM CAP _ Figure 1 33 Synario Report Viewer and tutor rpt windows CONGRATULATIONS You have completed the design example and are now familiar with the major functions of the ISP Synario System ISP Synario System Design Tutorial 34
6. I O Pad symbols not to the I O Markers Also note that I O Pad symbols are only necessary if you want to add attributes to a pin Otherwise you only need an I O Marker The following procedure can also be used to lock an input pin however it is not shown 21 From the Schematic Editor menu bar select Add Symbol Attribute The symbol Attribute Editor dialog box appears On the schematic click on the I O Pad attached to the OUT net A list of related attributes appears in the dialog box 22 Select the SynarioPin 4 attribute and replace the in the text box with the number 4 as shown in Figure 1 9 Close the dialog box Notice that the number 4 has been added in the I O Pad symbol in the schematic ISP Synario System Design Tutorial 16 List All Attributes Protect H SlowSlew H Pulllp N Figure 1 9 Symbol Attribute Editor 23 The steps are similar for adding a Net or Path attribute From the Schematic Editor menu bar select Add gt Net Attribute The Net Attribute Editor dialog box appears On the schematic click on the net that connects input C to the AND gate The list of related attributes appears in the dialog box 24 Select the CriticalPath attribute and type S path1 in the text box as shown in Figure 1 10 The S signifies that Start of the path and pathi comprise the unique name for the path attribute You will not see anything on your schematic for this attribute Net Attribute Editor Cri
7. _ Figure 1 28 Synario Project Navigator after ABEL HDL Compile Simulate the Design You will now simulate the entire design To do this you need a test vector ABv file For the purpose of this tutorial you will just modify the one you created earlier 53 Double click on the demo abv source The Synario Text Editor appears with the syntax you input in step 29 Modify the text as follows module demo 6 462 eX 7 CLK TOBIN TOPINZ LOPLNS TOPOUL PLN Thor VECTORS Oy Oy 7 7 Aa A A AAAA AQA hhRRRooo E H G o HHG E Z U ISP Synario System Design Tutorial CLK TOPINLT TOPLNZ2 LOPINS gt TOPOUTT J eo XI 30 o nario Text Editor demo abw Edit Options Window Help module demo C 8 C 3 CLE TOPINI TOPIN TOPINS TOPOUT PIN TEST VECTORS CLE TOPINI TOPIN TOPINS gt TOPOUT F 0 gt x 1 1 gt x 8 gt x 1 gt x 8 gt x gt 1 gt x 8 gt x 1 gt x 1019 IWR Rec Off Nowrap DOS INS NUM CAP Figure 1 29 Synario Text Editor with Text Vector Syntax 54 When you are finished select File Save then File gt Exit 55 In the Navigator with Compile Test Vectors still selected double click on the Equation Simulation Waveform process Since you edited the existing test vector file instead of creating a new one you will get an error
8. 0 With the 2032 device selected select Source New from the Synario Project Navigator menu bar In the dialog box select Schematic and click OK Select the path c synplsi examples and enter the file name top sch in the text box Click OK You are now in the Schematic Editor 41 Add the symbol for the schematic you created in Section 1 Select Add gt Symbol The Symbol Libraries dialog box appears with the Local library selected Notice the demo symbol in the lower text box Figure 1 21 Select the demo symbol and place it on your schematic ISP Synario System Design Tutorial 24 El SehematicEditor TOP Sheetiof1 File Edit View Add Object Options Help HAE yi 2 AAA Symbol Libraries LIBRARY A AGENERICAMISCE A AGENERICAARITHS LIB A AGENERICAGATES LIB A GENERICSIOPADS LIB STMBOL E O El E Y Symbol Click to Place Symbol DEMO Figure 1 21 Schematic Editor with Symbol Libraries Dialog box The next step is to create a top level symbol for your ABEL HDL design file A symbol can be created for any lower level design module as long as you know its interface The actual ABEL HDL file for your design will be completed in a later step 42 n the schematic editor select Add New Block Symbol In the dialog box that appears type abeltop in the Block Name text box IN1 IN2 IN3 in the Input Pins text box and OUT1 OUT2 OUT3 OUT4 in the Output Pins text box Figure 1 22 Click
9. A CK A B C D OUT PIN TEST_VECTORS CK A B C D gt OUT ES y Os Uy Oy Miri LE y Up Uy La Vleet LS y Ly Lt Os Ul gt il E y Ue Ey Ty Bee END 30 When finished select File Save from the Synario Text Editor menu bar to save your test vector file Select File Exit Synario returns you to the Project Navigator which appears as in Figure 1 12 ISP Synario System Design Tutorial 18 swnario Project Navigator TUTOR S YN Process Options Window Help ll Strategy Normal 3 2 8 N Sources in Project Processes for Current Source E Demo Project gd ispLsl 2032 150 TOFP44 Compiler Listing Elo O Simulate Equations E demo demo sch Equation simulation Report A Equation Simulation Waveform D ouble click to open the selected test D ouble click the item in the list or select the Start button bo start the wectors process Select the Properties button to start the property editor Figure 1 12 Synario Project Navigator Compile Schematics and Test Vectors Now that you have created sources for your project the next step is to execute the processes associated with each source By selecting each source you can see the different processes that can be executed You will compile the schematic and the test vectors separately 31 In the Synario Project Navigator window highlight the schematic source demo demo sch in the Sources in Project list Double click on Compile Schematic in the P
10. BEL HDL files test vector files or documentation files In the following steps you will add a blank schematic sheet source to your project add several schematic symbols and connect them with nets 7 With the 2032 device selected notice the processes associated with this source 8 From the menu bar select Source gt New In the New Source dialog box select Schematic and click OK or press Enter A dialog box appears asking you to enter the name for a new schematic Select the path c synplsi examples and enter the file name demo sch in the text field Click OK or press Enter NOTE In order to avoid problems it is a good idea to use a different name for your source file than the project name The schematic editor appears with a blank schematic Figure 1 5 From the menu bar select Add gt Symbol ISP Synario System Design Tutorial 13 Schematic Editor DEMO Sheet 1 of 1 File Edit View Add Object Option File Successtully Saved Select A Command E Figure 1 5 Schematic Editor Window 10 In the Symbol Libraries dialog box select C generic gates lib from the library list then highlight the G_2AND symbol Figure 1 6 symbol Libraries LIBRARY CA AGENERICAMUXES LIB CA AGENERICAREGS LIB Figure 1 6 Symbol Libraries Window 11 Move the pointer back over the Schematic Editor notice the AND gate attached to your pointer Place the gate by clicking on the schematic Place anot
11. IH1 IHN2 IN3 pin Outputs OUT1 OUT OUTS OUTS Equations OUTI IN1 amp TINS OUTZ IN1 amp IH2 OUTS tIN1 amp IN 1H3 OUTS IN amp IWS 18 WR Rec Off No wrap DOS INS NUM CAF Figure 1 27 Synario Text Editor with Code Entered 51 Select File Save then File Exit Notice in the Project Navigator that the icon next to the abeltop source has changed This means you have an ABEL HDL file associated with this source and it is linked correctly ISP Synario System Design Tutorial 29 Compile ABEL HDL 52 In the Sources in Project field of the Project Navigator select the abeltop source abeltop ab1 In Processes for Current Source double click on Reduce Logic The Navigator will take care of running the Compile Logic process before it executes the Reduce Logic process When the process Is finished your Navigator should match the one in Figure 1 28 swnario Project Navigator TUTOR S YN E ources in Project El Demo Project S IspLol 032 150 TUFP44 demo aj EA top E demo demo sch Double click to open the selected SOUICEe Process Options Window Help Processes for Current Source af DS Compile Logic O Check Syntax Compiler Listing E l Reduced Equations Double click the item in the list or select the Start button to start the process Select the Properties button to start the property editor Process Reduce Logic is up to date
12. Run New Block Symbol Block Hame abeltop Use Data From This Block Input Pins INT IN2 IN3 Output Pins OUT1 0UT2 0UT3 0UT4 Bidir Pins Figure 1 22 New Block Symbol Dialog Box ISP Synario System Design Tutorial 25 43 A symbol will be added to your local library and the symbol will be attached to your cursor Place the symbol to the left of the demo symbol Click with the right mouse button to display the Symbol Libraries dialog box Figure 1 23 Note the abeltop symbol in the Local library Close the dialog box Sonoma Editor TOP Sheet 1 of 1 cE GENERIC ARITHS LIB Unh AGENERICAGATES LIB o C GENERICMIOPADS LIB STMBOL NN Symbol Click to Place Symbol ABELTOP Figure 1 23 Adding Symbols from the Local Library 44 Complete the top level schematic by adding the necessary wires net names and I O Markers to finish the design Figure 1 24 Refer to the instructions for adding nets and symbols page 1 15 if you need assistance When you are finished save your design and exit the schematic editor ISP Synario System Design Tutorial 26 Schematic Editor TOP Sheet I of 1 View Add Object Options Help JEE w i a N E Figure 1 24 Completed Abeltop Design If you are interested in verifying the correctness and consistency of your top level design you can move through the design levels using the Hierarchy Navigator feature A number o
13. ame will be attached to your cursor 16 Move the cursor to the uppermost input and click and hold on the unconnected end of the net i e the red box at the left end of the net and drag to the left This will place the net name and create an input net simultaneously The net name should now be attached to the end of the net 17 Repeat this procedure to add the net names B C D and CK to the inputs and OUT to the output 18 From the Schematic Editor menu bar select Add I O Marker The I O Markers dialog box appears Choose Input ISP Synario System Design Tutorial 15 19 Move the cursor to the end of an input net between the end of the net and the net name and click An input marker appears with the net name inside of it Move to the next input and click again Repeat until all inputs have I O Markers 20 Choose Output from the I O Markers dialog box and click on the end of the output net The completed schematic should appear as shown in Figure 1 8 Schematic Editor DEMO Sheet 1 of 1 File Edit View Add Object Options Help a ALA m Y l E al Gl ao E2 Me Figure 1 8 Completed Schematic Add Design Attributes Attributes can be added to either symbols or nets For this example you will add a LOCK attribute to the output pad symbol and a SCP ECP Start End Critical Path attribute pair to an input path Note that in Synario pin attributes are actually added to the
14. cs related to the fitting of your design Figure 1 19 oynario Report Viewer File Edit View Options Window Help demo rpt isjpLSI Development System Plus Release 2 2 11 Jun 19 1996 14 Design Parameters IGHORE_FIAED PIH OFF HAN GLB IH 16 15 pL511066 isj pLS176608 4 HAX GLE OUT STRATEGY icon is RO fec Ofi No wian DOS INS NIM Figure 1 19 Design Statistics After Design Fitting ISP Synario System Design Tutorial 23 Combine ABEL HDL and Schematics In this section you will create a small ABEL HDL design then connect it to the schematic from the previous steps on a top level schematic This complete design will be simulated and compiled into an ispLSl device 39 If you quit from ISP Synario after the last section re start by double clicking on the icon in the ISP Synario System Program Group Your Navigator screen should look like the one in Figure 1 20 If not make sure all the previous steps were completed correctly s nario Project Navigator TUTOR S YH E Demo Project d lef GLink Design dema aby Linked Equations E demo demo sch Ca Fit Design Pre Fit Equations signal Cross Reference El JEDEC File ISP Synario Fitter Report Double click to choose a different Double click the item in the list or select the Start button to start the device process Select the Properties button to start the property editor Figure 1 20 Synario Project Navigator 4
15. e Synario Project Navigator select the isoLSI 2032 150 TQFP44 source and observe the related processes that have been created 59 In the Processes for Current Source list double click on Fit Design This will force the Navigator to finish compiling the source and to link the source files together before trying to partition and fit the design into a LSC part The Synario Project Navigator will add check marks to successfully completed processes Figure 1 32 s nario Project Navigator TUTOR S YN 3 Update All Schematic Files dla US Link Design demo aby E top ftop sch fo A abeltop fabeltop abl Pre Fit Equations E demo demo sch Signal Cross Reference e E JEDEC File ISP Synario Fitter Report Double click to choose a different Double click the item in the list or select the Start button to start the device process Select the Properties button to start the property editor Figure 1 32 Synario Project Navigator After Successful Design Fit 60 Note that the pDS Fitter has several user controls that can be accessed from the Navigator highlight Fit Design and click Properties at the bottom of the Navigator window You will see a dialog box with a list of pDS Fitter properties in it See the pDS Fitter User Manual for an explanation of these properties ISP Synario System Design Tutorial 33 61 To see all of the statistics related to the fitting of your design double click on ISP Synario Fitter Report
16. f editing functions are available through the Navigator 45 In the Sources in Project list of the Synario Project Navigator window highlight the top level schematic top sch In the Processes list double click on Navigate Hierarchy A Building Hierarchy message box will appear briefly then the Hierarchy Navigator window appears with your top level design 46 Select View gt Push Pop The cursor becomes a cross hairs Click on the desired symbol The Hierarchy Navigator will open the sheet for that symbol at the next level If you click on a symbol that is a primitive cell a message at the bottom of the Navigator window will prompt you 47 Select File Exit to close the Hierarchy Navigator You will be asked to save changes you made if any ISP Synario System Design Tutorial 27 Create the ABEL HDL Source File Now you need to create the ABEL HDL source file and link it to the symbol on the top level schematic The Project Navigator makes this simple 48 Your Navigator should look like the one in Figure 1 25 The icon for abeltop means that the source is unknown since you have not created it yet Also notice the hierarchy indents the abeltop and demo sources under the top schematic swnario Project Navigator TUTOR S YN File View Source Process ca ae Window Help can in TREE ee for Current Source El Demo Project P S isoLSl 2032 150 TOFP44 LA G Compile schematic demo abw O Reduce Schematic Logic t Reduced Equations
17. her AND gate below the first 12 Move the cursor back to the Symbol Libraries dialog box and select the G_2OR symbol Place that gate to the right of the two AND gates 13 From the Schematic Editor menu bar select Add gt Wire Click on the output pin of the top AND gate to start the wire Each successive click will bend the wire a double click will end the wire if it is not connected Connect the wire to an input of the OR gate with a single click Repeat for the lower AND gate ISP Synario System Design Tutorial 14 14 Repeat the above procedure to add a g_d register from the REGS LIB library and a G_OUTPUT from the IOPADS LIB Connect them so that the schematic follows the example Figure 1 7 ama Ba DEMO Sheet 1 of 1 Figure 1 7 Building the Schematic Complete the Design In this section you will complete the schematic by adding the net names and I O Markers When adding net names you will use a feature of Synario that allows you to add the net name and the net simultaneously I O Markers are the special symbols that indicate what signals enter and leave a schematic Nets cannot be left dangling they must have an I O Marker The markers assume the name of the net they are attached to and are different from the I O Pad symbols 15 On the Schematic Editor menu bar select Add gt Net Name The status bar at the bottom of the screen will prompt you to enter the net name to add Type A and press Enter The Net N
18. iconductor pLSI part Since you selected a part earlier in this example the remaining steps are straightforward 36 Select the ispLSI 2032 150 TQFP44 source and observe the related processes Double click on the process Fit Design A Synario Process dialog box appears momentarily Figure 1 17 The Navigator finishes compiling the source then links the source files together Finally the Navigator partitions and fits the design into the LSC part swnarlo Process Updating Fit Design blifopt demo bl red bypin choose sweep aie Figure 1 17 Synario Process Dialog Box 37 When the process is complete the Synario Project Navigator window returns Figure 1 18 Note that check marks have been added to Fit Design processes that have been successfully completed s nario Project Navigator TUTOR S YN File Yiew Source Process Options Window Help E Normal E 418 GLink Design demo abw Linked Equations E demo demo sch ef Fit Design Pre Fit Equations of signal Cross Reference E JEDEC File ISP Synario Fitter Report Double click to choose a different Double click the item in the list or select the Start button to start the device process Select the Properties button to start the property editor Ready Figure 1 18 Synario Project Navigator After the Fitter Process ISP Synario System Design Tutorial 22 38 Double click on ISP Synario Fitter Report in the Processes list to see the statisti
19. llowing Adding Schematics to Your Design Adding Design Attributes Creation of Simulation Test Vectors schematics and Test Vectors Compilation Execution of Functional Simulation and Waveform Output Symbol Creation ABEL HDL Creation and Compilation Design Simulation Where to Look for Information Chapter 1 Installation Lists what products you must have installed beore you can use this tutorial This chapter also contains operational notes and other information that you might find useful before Installation Requirements Chapter 2 Tutorial Introduces the Synario Schematic tool and the provides procedures to become adept at entering ABEL syntax with a preview of the Waveform viewer ISP Synario System Design Tutorial 6 Documentation Conventions Documentation Conventions The conventions in this tutorial are defined in the following table Convention Italics Bold Courier Font Bold Courier Quotes NOTE A CAUTION TIP Definition and Usage Italicized text represents variable input For example design 1 This means you must replace design with the file name you used for all the files relevant to your design Valuable information may be italicized for emphasis Book titles also appear in italics The beginning of a procedure appears in italics For example To open a design Valuable information may be boldfaced for emphasis Commands are shown in boldface For example edif2laf
20. message Figure 1 30 saying that the signal names you used earlier cannot be found Accept the message and close the Report Viewer ISP Synario System Design Tutorial 31 oynario Report Viewer pla err A Hot Found E Hot Found C Hot Found D Hot Found Hode OUT Hot Found a rcar e TAL eco No wian DOS INS NUM CAP Figure 1 30 Synario Report Viewer and Error Message Window 56 The Waveform Viewer window appears To see the waveforms select Edit gt Show The Show Waveforms dialog box appears with all your signal names as well as the intermediate ones listed for you 57 One at a time select TOPIN1 TOPIN2 TOPIN3 TOPOUT and CLK and click Show Each of these signals will be visible in the Waveform Viewer Figure 1 31 Close the Show Waveforms dialog box Select File Save in the Waveform Viewer window then File gt Exit Waveform Viewer Timewave PLA File Edit View Object Options Jump Help Instances GND TOPOUT Creo Ce ae Time 0 Low Input ABEL Figure 1 31 Show Waveforms dialog box and Waveform Viewer ISP Synario System Design Tutorial 32 Fit the Design into a Lattice Part You have completed the design and the simulation of your mixed schematic and ABEL HDL design The only step remaining is to fit the design into a Lattice Semiconductor ispLSl part Since you selected a part in the beginning steps the remaining steps are straightforward 58 From the Sources in Project portion of th
21. ne is available from 8 00 AM to 5 00 PM Pacific Time Or send e mail to applications latticesemi com Information Need USA amp Canada Other Locations Telephone Hotline 1 800 LATTICE 408 428 6414 1 800 528 8423 408 94445 SPESUpESl Bulletin Board 408 428 6417 Applications Support System applications latticesemi com FTP Site http www latticesemi com ftp index html World Wide Web http www latticesemi com 1 888 477 7537 pogo Ser ISP Synario System Design Tutorial 9 Chapter 1 Tutorial The ISP Synario Tutorial using a simple design example will guide you through the following Requirements Start ISP Synario Add a Schematic to Your Design Complete the Design Add Design Attributes Create Simulation Test Vectors Compile Schematics and Test Vectors Execute Functional Simulation and Waveform Output Create a Symbol Combine ABEL HDL and Schematics Create the ABEL HDL Source File Compile ABEL HDL simulate the Design Fit the Design into a Lattice Semiconductor Part ISP Synario System Design Tutorial 10 Requirements Before you can proceed with this tutorial you must have the following products installed m Synario Design Entry m ISP Synario Fitter m Win32s Refer to the ISP Synario System User Manual for installation instructions The Project Navigator From ISP Synario s Project Navigator you can perform a number of design functions including accessing the components for your design and kee
22. og Box Figure 1 15 appears Show YW aweforms Net Name Show ZZZOOOm Figure 1 15 The Show Waveforms Dialog Box 35 One at a time highlight each signal name that you want to see and press Show The waves you selected will appear in the Waveform Viewer window in the order you chose them Figure 1 16 Select File gt Exit to close the Waveform Viewer A dialog box will appear asking you to confirm changes to PLA wav ISP Synario System Design Tutorial 20 Waveform Viewer Timewave pla Out Figure 1 16 A Completed Waveform Create a Symbol A useful feature of the Synario tool is the ability to quickly create a symbol for a schematic By doing this you create a reusable macro that can be placed on a higher level schematic sheet a Open the schematic file by double clicking on the schematic source demo sch b In the schematic editor menu bar select File Matching Symbol c Select File Exit to close the schematic d The symbol has been created and added to your symbol list You will use this symbol in the next section ISP Synario System Design Tutorial 21 Fit the Design into a Lattice Semiconductor Part You have now completed the design and simulation of your example design If you plan to proceed to the next section Combine ABEL HDL and Schematics you need not complete the steps remaining in this section Otherwise the last process is to fit the design into a Lattice Sem
23. ping track of the necessary processing steps You can open schematic and text editors navigate through your design hierarchy and more This tutorial will familiarize you with the Project Navigator and allow you to become adept at entering ABEL HDL syntax with a preview of the Waveform viewer Start ISP Synario 1 Start the ISP Synario System by double clicking on the ISP Synario icon in the ISP Synario program group The Synario Project Navigator window appears Figure 1 1 E AA 5 E ES 6 104 5 Sources in Project Processes for Current Source No Project Open No Processes Available Select New Project or Open Open 4 project to make processes available Project in the Fille menu to open a project EN Srat Pronerties Figure 1 1 Synario Project Navigator Window ISP Synario System Design Tutorial 11 2 Select File gt New Project The Create New Project dialog box appears Figure 1 2 Project File Name Directories tutor yn cAsynplshexamples gt spnpls braklite 3 micount 3 multiply 27 tach List Files of Type Drives Create Dir Project File _syn E c ms dos_6 Figure 1 2 Create New Project Dialog Box 3 In the C home drive click to open synplsi then highlight the examples directory In the Project File Name text box type tutor syn Figure 1 2 Click OK or press Enter 4 In the Project Navigator there are two sources Untitled and Virtual De
24. rocesses list A status dialog box Figure 1 13 appears briefly When the process is finished the Compile Schematic process will have a green check mark next to it indicating a successful compile gt wnarlo Process Updating Compile Schematic bliflink demo bls o demo bl0 ipo propadd Figure 1 13 Synario Process Status Dialog Box 32 In the Synario Project Navigator window highlight the test vector source demo abv Double click on Compile Test Vectors in the Processes list When finished Compile Test Vectors shows a green check mark next to it ISP Synario System Design Tutorial 19 Functional Simulation and Waveform Output The ISP Synario System includes a functional simulator and waveform viewer The following steps will demonstrate how you can execute the process and have the Navigator complete all the necessary steps to achieve the results In this case you want to see the waveform output of your vector simulation The Navigator will simulate the vectors and open the waveform environment for you 33 With the test vector source demo abv highlighted double click on Equation Simulation Waveform in the Processes list Synario simulates the equations and the Waveform Viewer window appears Figure 1 14 Waveform Viewer Timewave pla File Edit View Object Options Jump Help Figure 1 14 The Waveform Viewer 34 To see the waveforms select Edit Show from the Waveform Viewer menu bar A Show Waveforms Dial
25. rosoft Windows and MS DOS are registered trademarks of Microsoft Corporation IBM is a registered trademark of International Business Machines Corporation DATA 1 0 and Synario are registered trademarks of Data I O Corporation Lattice Semiconductor Corporation 5555 NE Moore Court Hillsboro OR 97124 503 681 0118 August 1996 ISP Synario System Design Tutorial 2 Limited Warranty Lattice Semiconductor Corporation warrants the original purchaser that the Lattice Semiconductor software shall be free from defects in material and workmanship for a period of ninety days from the date of purchase lf a defect covered by this limited warranty occurs during this 90 day warranty period Lattice Semiconductor will repair or replace the component part at its option free of charge This limited warranty does not apply if the defects have been caused by negligence accident unreasonable or unintended use modification or any causes not related to defective materials or workmanship To receive service during the 90 day warranty period contact Lattice Semiconductor Corporation at Phone 1 800 LAT TICE Fax 1 408 944 8450 E mail applications latticesemi com lf the Lattice Semiconductor support personnel are unable to solve your problem over the phone we will provide you with instructions on returning your defective software to us The cost of returning the software to the Lattice Semiconductor Service Center shall be paid by the purchaser
26. ter 1 Tutotlal perceeneceecenne setecuseges oeeeebaseceseusuateracaeses ae 10 KOCU MEN Os ou cue paa Be ds ide dl iones o oo need a a 11 The Project Navigator o o o oooooooor ee eee ee ete 11 Slalt ISF SYN enmascara radianes arar eee coda 11 Add a Schematic to your Design 1 eee ens 13 Complete the Design 1 0c ee ee ee eee teens 15 Add Design AUNDUTOS sasaaa Sesame te wend Be eee open eee tes eee one eee eae 16 Create Simulation Test Vectors 2 0 eee eee eee 18 Compile Schematics and Test Vectors 1 0 0 cc eee eens 19 Functional Simulation and Waveform Output 0 0 0 0 0 eee 20 Aj SVIMNMDOls casa ge Sede dedeeee auc koe nde Gude dee eneu denen chegededads 21 Fit the Design into a Lattice Semiconductor Part o oo ooooooomoooooo 22 Combine ABEL HDL and Schematics 0 0 0 eens 24 Create the ABEL HDL Source File n anaana nanana ee ene 28 Compile ABEL HDL 0 0 0 cc ee eee eee eens 30 simulate the DESIGN 4 2052 rodni enire ke E Grenn meee edeiv Gude eae eens 30 Fit the Design into a Lattice Part 0 0 cee eee 33 ISP Synario System Design Tutorial 4 Preface This preface contains sections about the following information a What is in this Tutorial Documentation Conventions m Related Documentation m Software Support ISP Synario System Design Tutorial What is in this Tutorial What is in this Tutorial This tutorial contains instruciton on the fo
27. ticalPath S path 7 VHDL NetType Preserve Group Figure 1 10 Net Attribute Editor 25 On the schematic click on the net that connects the OR gate with the D flip flop In the Net Attribute Editor dialog box enter E path1 This will signify the end of the critical path named path1 Close the dialog box 26 From the Schematic Editor menu bar select File Save to save your design select File Exit to close the Schematic Editor window ISP Synario System Design Tutorial 17 Create Simulation Test Vectors In ISP Synario you can use one or more sets of test vectors to simulate the function of a device For the purposes of this tutorial you will enter a simple test vector 27 In the Synario Project Navigator highlight the ispLS 2032 150 TQFP44 device From the menu bar select Source gt New A New Source dialog box appears Highlight Abel Test Vectors and click OK or press Enter 28 The New File dialog box and a blank Synario Text Editor window appears Enter the file name demo as shown in Figure 1 11 for your test vector file name Click OK or press Enter Synario Text Editor 2 File View Templates Tools Options Help EME TR demo Default Dot Extension Eso A aera Ree tN _ Figure 1 11 Synario Text Editor with the New File Dialog Box 29 In the Synario Text Editor window type the following keeping aware of case sensitivity Cc versus C module demo Cpe
28. vice To name your project double click on Untitled A Project Title dialog box appears Type Demo Project in the Title field then click OK Figure 1 3 Synario Project Navigator DEMO SYN v File View Source Process Options Window Help BEE Sources in Project Processes for Current Source No Processes Available ES virtual Device ProjectTitle lt Demo Project Cancel Select the New button to add No processe source or Import in the Source the Source li menu to add from a existing design Figure 1 3 Synario Project Navigator and Project Title Box ISP Synario System Design Tutorial 12 5 Double click on Virtual Device You will see the Choose Device pop up window Select ISP Synario Device list in the Device Kit field A device list appears Figure 1 4 Choose Device Device Kit ISP Synario Device list EE mananc Device Device PLSI 2032 180 PLECA pL5I 2032 180 TOFP44 na a LE e BLS 2032 135 PLCCA44 PLS 2032 135 TQFP44 pLS 2032 110 PLCC44 pLS 2032 110 TOFP44 Figure 1 4 Choose Device Window 6 Scroll through the device list until you find ispLSI 2032 150 TQFP44 Highlight this device and click OK You will be asked to confirm your choice since it will result in changes in the Project Navigator design environment Click Yes Add a Schematic to your Design Design projects are made up of one or more sources which can be schematics A
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