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LTspice/SWCAD User`s Manual

1. 110 response with the behavioral source is also potentially a compute bound process C Capacitor Symbol names CAP POLCAP Syntax Cnnn nl n2 capacitance ic lt value gt Rser lt value gt Lser lt value gt Rpar lt value gt Cpar lt value gt m lt value gt RLshunt lt value gt temp lt value gt It is possible to specify an equivalent series resistance series inductance parallel resistance and parallel shut capacitance The equivalent circuit is given below lt Capacitance gt RLshunt Capacitor Instance Parameters Nam Description e Rse Equivalent series resistance 111 Lse Equivalent series inductance E Rpa Equivalent parallel resistance Ir Cpa Equivalent parallel capacitance E RLs Shunt resistance across Lser hun E m Number of parallel units tem Instance temperature for tempcos in a p corresponding model statement iG Initial voltage used only if uic is flagged on the tran card It is computationally better to include the parasitic Rpar Rser RLshunt Cpar and Lser in the capacitor than to explicitly draft them LTspice uses proprietary circuit simulation technology to simulate this model of a physical capacitor without any internal nodes This makes the simulation matrix smaller faster to solve and less likely to be singular at short
2. Vo Carrier mobility knee voltage V Trel Re linear temperature TA coefficient e Tre2 Re quadratic temperature 1 coefficient ze 2 Trbl Rb linear temperature 1 coefficient ue Trb2 Rb quadratic temperature 1 coefficient C 2 Trel Rc linear temperature 1 coefficient Eo Tre2 Rc quadratic temperature 1 coefficient e 2 Trmi Rmb linear temperature 1 coefficient 2e Trm2 Rmb quadratic temperature 1 coefficient ue 2 Iss Substrate junction saturation A current NS Substrate junction emission Coefficient odel parameter level of BJT in LTspice Due e code from Dr Ing Di can be used to specify another to a generous contribution of etmar Warning of DAnalyse GmbH n Germany LTspice inc ludes a version of VBIC Set 9 to use the alternat evel 9 The following documentation has been supplied by Dr Warning Vertical Bipolar Inte 154 device Level 4 is a synonym r Company model VB The VBIC model is a Standard Gummel Poon xtended development of the SGP model with the focus of integrated bipolar transistors in today s modern semiconductor technologies modified Quasi Saturation is also possible to model characteristic of switching With the implemented model from Kull and Nagel it the special output It is a transistors widely used alternative to the SGP model for silic
3. sse 83 OPTIONS Set Simulator Options sssssssssss 83 PARAM User Defined Parameters sse 88 SAVE Limit the Quantity of Saved Data sssssssssessss 92 SAVEBIAS Save Operating Point to Disk esses 93 STEP Parameter SWeEDS cceesceceeeeeeeeeeeeeaeseeeeeseeaeeeeaeeteeeeeeenees 94 SUBCKT Define a Subcircuit sse 95 TEMP Temperature Sweeps ssssssssseeeeennenen 96 TF Find the DC Small Signal Transfer Function 96 TRAN Perform a Nonlinear Transient Analysis ss 97 WAVE Write Selected Nodes to a Wav File ssssssse 98 Transient Analysis Options essssssssseseseeeee eene 99 TRAN Modifiers esses eene enne nnne nnne nns 99 lJIG 2 entente etd ce A A e te Ee 99 jcigiPop TUMULI TT 99 Steady cei tod ER med E EE eid 100 DodiScalds ue hec MedXotbs e A eet nod Nb ixl dee 100 dI 101 Gircuit Elements iet eripi nte oer aate ek aeta ua tee Meuse aa daeka e ade 102 A Special Functions sssssssssssseseseeeeenennen nnne 102 B Arbitrary behavioral voltage or current sources s 104 emper ejngrcc E 111 Di Di0de EE 113 E Voltage Dependent Voltage Source sssssssssss 117 F Current Dependent Curr
4. MOSFET level 1 2 and 3 parameters Nam Description Uni Def e ts aul t Vto Zero bias V 0 threshold voltage Kp Transconductance A V 2e parameter 2 5 Gam Bulk threshold Vis 0 ma parameter Phi Surface inversion V 0 6 potential 140 Exa mpl Lam bda Rd Cbd Cbs Pb Cgs Cgd Cgb Rsh Cj Channel length modulation level 1 and 2 only Drain ohmic resistance Source ohmic resistance Zero bias B D junction capacitance Zero bias B S junction capacitance Bulk junction saturation current Bulk diode emission coefficient Bulk junction potential Gate source overlap capacitance per meter channel width Gate drain overlap capacitance per meter channel width Gate bulk overlap capacitance per meter channel width Drain and source diffusion sheet resistance Zero bias bulk junction bottom 1 V F m F m F m F m C C le 20f 20f le 1 5 4e 11 4e 11 2e 10 T0 2e 141 Mj Cjs Mjs JS Tox IPG Xj Ld 142 capacitance per Square meter of junction area Bulk junction bottom grading coefficient Zero bias bulk junction sidewall capacitance per meter of junction perimeter Bulk junction sidewall grading coefficient Bulk junction saturation current per square meter of junction area Oxide thi
5. Nearest integer to x Alternate syntax for idt Sign of x Sine of x Hyperbolic sine of x Square root of x Interpolate a value for x based on a look up table given as a set of pairs of points Tangent of x Hyperbolic tangent of x Unit step i e lif x gt O else 0 x if x gt 0 else O Random number between 5 and 5 smoothly transitions between values even more smoothly than random Alternative syntax for inv x Alternative syntax for inv x o The following operations grouped in reverse order of precedence of evaluation Ope Description ran d amp Convert the expressions to either side to Boolean then AND Convert the expressions to either side to Boolean then OR 108 Convert the expressions to either side to Boolean then XOR gt True if expression on the left is greater than the expression on the right otherwise false lt True if expression on the left is less than the expression on the right otherwise false gt True if expression on the left is less than or equal the expression on the right otherwise false lt True if expression on the left is greater than or equal the expression on the right otherwise false Floating point addition Floating point subtraction E Floating point multiplication Floating point divisi
6. model MySwitch CSW Ron 1 Roff 1Meg It h 2 5 Ihe current through the named voltage source controls the switch s impedance A model card is required to define the behavior of the current controlled switch Current Controlled Switch Model Parameters Na Description Un Defaul me it t S It Threshold V 0 current Ih Hysteresis V 0 current Ro On resistance Q Ln n Ro Off resistance Q 1 Gmin ff 173 The switch has three distinct modes of current control depending on the value of the hysteresis current Ih f Ih is zero the switch is always completely on or off according to whether the control current is above threshold f Ih is positive the switch shows hysteresis with trip point currents at It Ih and It Ih If Ih is negative the switch will smoothly transition between the on and off impedances The transition occurs between the control currents of It Ih and It Ih The smooth transition follows a low order polynomial fit to the logarithm of the switch s conduction X Subcircuit Syntax Xxxx nl n2 n3 lt subckt name gt lt parameter gt lt expression gt Subcircuits allow circuitry to be defined and stored ina library for later retrieval by name Below is an example of defining and calling a voltage divider and invoking it in a circuit calling a subcircuit
7. Open the file typically installed as C Program Files LTC SwCAD lib cmp standard ind to add or edit inductor models MOSFET Models What is the difference between SwitcherCAD III MOSFET and standard SPICE MOSFET models Besides the standard SPICE MOSFET models SwitcherCAD also includes a proprietary MOSFET model that is not implemented in other SPICE programs It directly encapsulates the charge behavior of the vertical double diffused MOS transistor This allows a power device to be modeled with an intrinsic VDMOS device LTspice instead of a subcircuit as in other SPICE programs See models definition for details Can I add my own MOSFET models Yes you can add your own model in the 195 C Program Files LTC SwCAD lib cmp standard mos file This file is only for devices defined with a model statement not as subcircuits If you want to use a subcircuit follow the following steps Add Change the Prefix attribute of the component instance of the symbol to be an X Don t change the symbol just the instances of the symbol as a component on a schematic You can access this attribute by holding down the control key and right clicking on the body of the component Edit the Value attribute of the component to coincide with the name of the subcircuit you wish to use a SPICE directive on the
8. This is the circuit X1 in out 0 divider top 9K bot 1K Vl in 0 pulse O 1 0 5m 5m O 1m This is the subcircuit Subckt divider A B C R1 A B top R2 B C bot ends divider tran 3m end Z MESFET transistor Symbol Names MESFET Syntax Zxxx D G S model area off IC lt Vds Vgs gt 174 temp lt value gt A MESFET transistor requires a model card to specify its characteristics The model card keywords NMF and PMF specify the polarity of the transistor The MESFET model is derived from the GaAs FET model described in H Statz et al GaAs FET Device and Circuit Simulation in SPICE EEE Transactions on Electron Devices V34 Number 2 February 1987 ppl160 169 Two ohmic resistances Rd and Rs are included Charge storage is modeled by total gate charge as a function of gate drain and gate source voltages and is defined by the parameters Cgs Cgd and Pb Na Description Un Defa me it ult S Vt Pinch off voltage V c2 O Be Transconductance parameter A Ted ta V B Doping tail extending parameter 1 0 3 V Al Saturation voltage parameter 1 2 ph V a La Channel length modulation 1 0 md V a Rd Drain ohmic resistance Q 0 Rs Source ohmic resistance Q Q Cg Zero bias G S junction F 0 S capacitance Cg Zero bias G D junction F 0 d Capacitance 175 Pb Gate junction potential V Kf Flicker noise coefficient
9. ii it CE iii professionals historically experienced with ators are familiar with worki ng directly schematic capture was not CE simulators in older systems There are several resources of example circuits for LTspice SwitcherCAD There is a directory typically installed at C Program Files LTC SwCAD examples Educational that gives numbers non commercial examples of SPICE simulations that illustrate different analysis types methods or program features In the directory C Program Files LTC SwCAD examples jigs there is an example simulation for every Linear Technology device with a macromodel in LTspice SwitcherCAD Note that these jig circuits are often only test jigs for the macromodel not necessarily recommended reference designs Most importantly your Linear Technology office can probably give you design support specific you your application needs F jlinear Technology LTspice SwitcherCAD III 5v 12v 20mA 1316 asc Eq File Edit Hierarchy View Simulate Tools Window Help 8 x Aas A PIF 09 QQQRQ oN Bae sem Os 4p Sw Open an existing file Look in amp boost 8 ex E3 i1 5V 12V 16m4 1073 asc 1 5V S 50m4 1610 asc 3 3V 12V 120rr 1 5V 3 3V 75mA 1307 asc 2 5V 18V 120mA 1302 asc Es 3 3V S 200m X 1 5V3 3V 75m 1307B asc 1 2 5V 3710 3V 5V 250m X 1 5V3V20mA10
10. Control Panel Ls ow e Allow direct component pin shorts Normally you can draw a wire directly through a component and the wire segment shorting pins is deleted If you check it the shorting wire will not be automatically deleted Automatically scroll the view Checking this box makes the view of the schematic scroll as you move the mouse close the edge while editing the schematic Mark text Justification anchor points Draw a small circle to indicate the reference point of text blocks Mark unconnected pins Draw a small square at each unconnected pin to flag it as unconnected Show schematic grid points Start with visible grid enabled 186 Orthogonal snap wires Force wires to be drawn in vertical and horizontal segments while drawing If not checked a wire can drawn at any angle and will snap to any grid Holding down the control key will momentarily toggle the current setting while drawing wires Cut angled wires during drags During the Drag command a non orthogonal wire will be broken into two connected wires if you click along the middle of the wire Undo history size Set the size of the undo redo buffer Draft with thick lines Increases the all line widths Useful for generating images for publication Show Title Block For internal use Internet Options 187 Control Panel http LT spice lineartech com Default Recommended P
11. Prefix X SpiceModel name of file including the spicemodel gt Value What ever you want visible on the schematic Value2 The value as you want in the netlist Value2 would be made to coincide with a subcircuit name defined in the file including the spicemodel and may pass additional parameters to the subcircuit When a symbol is defined in this manner an instance of the symbol as a component on a schematic cannot be edited to have different attributes If you wish the symbol to represent another page of a hierarchical schematic all attributes should be left blank the symbol type should be changed from Cell to Block No attribute values need be set There is a symbol attribute ModelFile that may be Specified This is used for the name of a file to be included in the netlist as a library See the symbol subcircuit pair lib sym Opamps lpole asy and lib sub lpole sub to see an example of the utility of this attribute If the prefix attribute is X and there is a symbol attribute SpiceModel defined that is subcircuit defined in the model file then a drop list of all subcircuits names will be available when an instance of the symbol is edited on a schematic Attribute Visibility You can edit the visibility of attributes using the menu command Edit gt Attributes gt Attribute Window After you select an attribute with this dialog you will then be ab
12. tn ta VC Temperature exponent of VO Activation energy for IS Activation energy for BE Activation energy for BCI IBEIP Activation energy for BCIP Activation energy for BEN Activation energy for BCN IBENP Activation energy for IBCNP Temperature exponent of IS Temperature exponent of BEI IBCI IBEIP IBCIP Temperature exponent of BEN IBCN IBENP IBCNP Temperature exponent of NF Temperature exponent of AVC2 Thermal resistance Thermal capacitance Punch through voltage of internal B C junction Smoothing parameter for reach through Fixed C S capacitance K W Ws C 161 SO qb nk xi kf xr CX xr bx Xr bp is JE S de ea vb be nb be ib be bb el EV bb e2 tn bb 162 Select SGP qb formulation High current beta rolloff Temperature IKF Temperature RCX Temperature RBX Temperature RBP Separate IS rey Temperature ISR for ISRR Excitation en ESP B E breakdown B E breakdown coefficient B E breakdown current Linear temperatu coefficient of VBBE Quadratic temperature coefficient of VBBE expon expon expon expon eni eni en e
13. 5 BSIM2 see Min Chie Jeng Design and Modeling of Deep Submicrometer MOSFETs ERL Memo Nos ERL M90 90 Electronics Research Laboratory University of California Berkeley October 1990 6 MOS6 see T Sakurai and A R Newton A Simple MOSFET Model for Circuit Analysis and its application to CMOS gate delay analysis and series connected MOSFET Structure ERL Memo No ERL M90 19 Electronics Research Laboratory University of California Berkeley March 1990 8 BSIM3v3 3 0 from University of California Berkeley as of July 29 2005 9 BSIMSOI3 2 Silicon on insulator from the BSIM Research Group of the University of California Berkeley February 2004 12 EKV 2 6 based on code from Ecole Polytechnique Federale de Lausanne See http legwww epfl ch ekv and The EPFL EKV MOSFET Model Equations for Simulation Version 2 6 M Bucher C Lallement F Theodoloz C Enz F Krummenacher EPFL DE LEG June 1997 14 BSIM4 6 1 from the University of California Berkeley BSIM Research Group May 18 2007 The DC characteristics of the level 1 through level 3 MOSFETs are defined by the device parameters VTO KP LAMBDA PHI and GAMMA These parameters are computed if the process parameters NSUB TOX are given but user Specified values always override VTO is positive negative for enhancement mode and negative positive for depletion mode N channel P channel devices Charge s
14. Undo Undo Redo Redo Text the electrical schematic with the las the last command Undo command Place text on the schematic information impact SPICE Directive included in the netlist capture with a SPI simulation options define new models commands you the the SPICE Resistor model a SP Analysis on the Place text CE net circuit This This merely annotates ist It Place a new resis Enter edit include files that con or use any ol You can even use i don t have a symbol for by stating an CE command that schematic and including the definition CO ther valid t begins with lets you This text has no on the schematic that will be lets you mix schematic set tain models SPICE run a su bcircuit that instance of and X on the simulation command tor on the schematic Capacitor Place a new capacitor on the schematic Inductor Diode Component Place a new component on the schematic Place a new diode on the schematic Place a new inductor on the schematic The command brings up a dialog that lets you browse and preview the symbol database This is a more general form of the Resistor Capacitor Inductor and Diode commands Rotate Rotate the sprited objects Note this is greyed out when t
15. lt ref gt source TF I voltage source source Examples TF V out Vin TF V 5 3 Vin TF I Vload Vin TRAN Perform a Nonlinear Transient Analysis Perform a transient analysis This is the most direct simulation of a circuit It basically computes what happens when the circuit is powered up Test signals are often applied as independent sources Syntax TRAN Tstep Tstop Tstart dTmax modifiers TRAN Tstop modifiers The first form is the traditional tran SPICE command Tstep is the plotting increment for the waveforms but is also used as an initial step size guess LTspice uses waveform compression so this parameter is of little value and can be omitted or set to zero Tstop is the duration of the simulation Transient analyses always start at time equal to zero However if Tstart is specified the waveform data between zero and Tstart is not saved This is a means of managing the size of waveform files by allowing startup transients to be ignored The final parameter dTmax is the maximum time step to take while integrating the circuit equations If Tstart or dTmax is Specified Tstep must be specified 97 Several modifiers can be placed on the tran line WAVE Write Selected Nodes to a Wav File LTspice can write wav audio files These files can then be listened to or be used as the input of another simulation Syntax
16. 100 Sp lp AF EG Tno Bet aTc Vto T alp ha Vk Xti Flicker noise exponent Coefficient for forward depletion capacitance Parameter measurement temperature Transconductance parameter exponential temperature coefficient Threshold voltage temperature coefficient Gate junction emission coefficient Gate junction recombination current parameter Emission coefficient for Isr Tonization coefficient Ionization knee voltage Saturation current temperature coefficient K Mutual Inductance Oo oe Q oy E 27 129 50 Symbol Names None this is placed as text on the schematic Syntax Kxxx L1 L2 L3 coefficient L1 and L2 are the names of inductors in the circuit The mutual coupling coefficient must be in the range of 1 to T The line Kl L1 L2 L3 L4 1 is synonymous with the six lines K1 L1 L2 K2 L2 L3 K3 L3 L4 K4 L1 L3 K5 L2 L4 K6 L1 L4 It is recommended to start with a mutual coupling coefficient equal to 1 This will eliminate leakage inductance that can ring at extremely high frequencies if damping is not supplied and slow the simulation However a mutual inductance value of 1 or 1 can lead to simulation difficulties if the uic directive is flagged on the tran card L Inductor Symbol Names IND IND2 Syntax Lxxx n
17. gain voltage Current dependent Fxx n n Vnam gain current Voltage dependent Gxx n n net nc lt transcond gt current Current dependent Hxx n n Vnam lt transres gt 64 voltage off Independent current Ixx n n current source JFET transistor Jxx D G S model area IC lt Vds Vgs gt temp lt T gt Mutual inductance Kxx L1 L2 L3 lt coeff gt Inductance Lxx n n inductance ic lt val gt Rser lt val gt Rpar lt val gt Cpar lt val gt m lt val gt MOSFET transistor Mxx DG S B model L lt len gt IC lt Vds temp lt T gt W lt width gt AD lt area gt AS lt area gt PD lt perim gt PS lt perim gt NRD lt value gt NRS lt value gt off Vgs Vbs gt Lossy transmission line Oxx L L R R model Bipolar transistor Qxx C B E S model area off IC Vbe Vce temp lt T gt Resistor Rxx nl n2 value Voltage controlled Sxx nl n2 nc nc model switch on off Lossless transmission Txx L L R R ZO value line TD lt value gt Uniform RC line Uxx nl n2 ncommon lt model gt L lt len gt N lt lumps gt Independent voltage Vxx n n voltage source Current controlled Wxx nl n2 Vnam model switch on off Subcircuit Xxx nl n2 n3 subckt name gt MESFET transistor Zxx D G S
18. or an independent current source lt Iin gt Th node V ou terminated the termin t or a resistor with resistances Rin and Rout tion impedances default to 1 Ohm except si case of the output port the terminat tion resistances default impedanc Terminai statement will override devic for the normal NET statement will not calculation currents but not That is e optional output port is specifi d either with a I Rout Voltage source with an Rser specified The ports will be If unspecified in the Specified with a resistor or an two Cases In those tion values specified on the ts to the device NET the impedances for AC node voltages and the NET impose 81 terminating impedances on the network for the normal voltages and currents computed as part of the AC analysis See the example file typically installed as C Program FilesNLTCNSwCAD examples Educational S param It recommends using a voltage source V4 with Rser set the desired source impedance and a resistor Rout to set the output termination with a NET statement reading simply net I Rout V4 No Rin or Rout values specified on the net statement and the input output devices supply default termination values This arrangement makes the nod voltages and currents of the the AC a
19. Af Flicker noise exponent Fc Forward bias depletion coefficient Control Panel Accessing the Control Panel To get to the Control Panel use the menu command Tools gt Control Panel There you can configure many aspects of LTspice SwitcherCAD III Compression Control Panel 176 LTspice compresses the raw data files as they are generated A compressed fil Window Size No Relative Tolerance pane of the control panel a the compression runs le can be 50 times smaller than the un compressed one This is a lossy compression This llows you to control how lossy of Points Maximum number of points that can be compressed into two end points The relative error allowed between th compressed data and the uncompressed data Absolute Voltage tolerance V the compression algorithm Absolute Current tolerance A the compression algorithm These compression settings are not remembered betw program invocations to encourage use of the defaul Ihe voltage error allowed by The current error allowed be n ts They are available on the control panel for diagnostic purposes The tolerances and window size can be specified wil parameters plo plotwinsize in directives on treltol plotvntol plotabstol and option statements placed as SPICE the schematic File Size Vs Fidelity study th option 177 Linear Technol
20. Note that if specifying a non zero gap the magnetic field H is not under the proportional to the current in the windings LTspice solves for the magnetic fields in the core and gap assumption of uniform cross sectional area and thin or uniformly distributed gap 135 Below is an example that shows inductance vs current for L1 an inductor wound on a gapped core You can read out the inductance as V n001 since current source I1 supplies a unity dI dt The core follows the initial magnetization curve so you can see that the permeability first increases from the initial value as the current is ramped and then drops as it saturates Since the gap makes the inductance insensitive to the exact permeability of the core you have to really zoom in on V n001 to see that it does increase The peak is when H inside the core is equal to its Hc L1 N001 0 Hc 16 Bs 44 Br 10 A 0 0000251 Lm 0 0198 Lg 0 0006858 N 1000 I1 0 NOO1 PWL O O 1 1 eteran so options maxstep 10u end M MOSFET Symbol Names NMOS NMOS3 PMOS PMOS3There are two fundamentally different types of MOSFETS in LTspice monolithic MOSFETs and a new vertical double diffused power MOSFET model Monolithic MOSFET Syntax Mxxx Nd Ng Ns Nb model m lt value gt L lt len gt W lt width gt AD lt area gt AS lt area gt PD lt perim gt PS lt perim gt NRD lt value gt
21. ascii Use ASC raw files Seriously degrades program performance sp Run in batch mode E g scad3 exe b deck cir will leave the data in file deck raw big Start as a maximized window Encrypt a model library For 3 parties encrypt wishing to allow people to use libraries without revealing implementation details Not used by Linear Technology Corporation models Batch conversion of a binary raw file to FastAcc Fast Access format ess 15 max Synonym for big Batch conversion of a schematic to a netlist netlist nowine Prevent use of WINE Linux workarounds 5 Batch conversion of a schematic to a PCB PCBnetl format netlist ist Force LTspice to store user preferences MRU registr etc in the registry instead of the y WINDIR scad3 ini file Run Start simulating the schematic opened on the command line without pressing the Run button SOI Allow MOSFET s to have up to 7 nodes even in subcircuit expansion Executes one step of the uninstallation uninsta process 11 web Equivalent to executing menu command update Tools gt Sync Release wine Force use of WINE Linux workarounds Schematic Capture Basic Schematic Editing The schematic capture program is used to create new schema tics or modify the example circuits provided circuit t size and depth of hierarchy is computer resources The program
22. n Tnom The model name V and P channel device The polarit To specify P channel channel junction potential Body diode grading coefficient Body diode coefficient for forward bias depletion capacitance formula Body diode transit time Body diode activation energy for temperature effect on Is Body diode saturation current temperature exponent Length scaling Width scaling Flicker noise coefficient Flicker noise exponent N channel VDMOS P channel VDMOS Parameter measurement temperature DMOS is used bot Lr ue fa lse 21 th for a N channel ty defaults to N flag the model with 10n 50 147 the keyword pchan e g model xyz VDMOS Kp 3 pchan defines a P channel transistor O Lossy Transmission Line Symbol Name LTLIN Syntax Oxxx L L R R model Example Ol in 0 out 0 MyLossyTline model MyLossyTline LTRA len 1 R 10 L 1u C 10n This is a single conductor lossy transmission line N1 and N2 are the nodes at port 1 N3 and N4 are the nodes at port 2 A model card is required to define th lectrical characteristics of this circuit element Model parameters for Lossy Transmission Lines Name Description Units Typ Defa e ult R O unit 0 len L H unit 0 len G 1 Q unit 0 len C F unit 0 len Len Number of Unit 0 148 Rel Abs NoStepLim it NoControl LinIn
23. then be downloaded automatically if there is a difference in checksum SwCAD program files that were saved under the same name will be overwritten Most of the macromodels are less than 3KB and can be transferred in a few seconds During the update of the SCAD3 EXE the new file is first copied to the Windows temp directory and the old SCAD3 EXE is overwritten after the download is complete The old program is still preserved if the user cancels the file transfer The changelog txt file lists the changes of program revisions 206 Index AC Performan AC analysis sess ies ote pee weston E eden ERE RED Eee erue 66 BACKANNO Annotate the subcircuit pin names on to the port currents sseesee 67 DC Perform a DC source sweep analysis eese eee enne rennen 67 IND aiino beth arca e n rana i p a bb n mE emat ret 68 ENDS irt betae p delta a E bte m Co eed ent 68 Ferret Download a File Given the URL eese eene nennen 70 GLOBAL Declare global nodes trn eee et eater pre 70 IC setamtial conditions Eo Dre a ede m e RO ETE 70 INCLUDE 1nclide another file 5 5 2 3 0p tec epa peto er iie bep e t ees 71 LIB Include library itor ies anata atcp nnt 72 LOADBIAS Load a previously solved DC solution esee 75 MEASURE Evaluate User Defined Electrical Quantities sess 75 MODED or a e st ODE
24. tic capture program wit type has two basic modes of driving the Use the program as a general purpose schematic capture program with an integrated simulator commands Fil Menu asc tlist ora to be used as a general th an integrated SPI CE The idea is you draw a circuit or start with an t that s already drafted lator The design process LTspice SwitcherCAD and observe its involves uit until the desired circuit behavior is in simulation Earlier versions of incl uded a synthesizer that would attempt to divine a SMPS design from a user supplied Specification obsoleted The schemat bu ic is ultima tely converted to a textual SPI netlist tha is usually extrac LTspice Swit directly wit uses i FilterCAD programs SPICE circu t is passed tcherCAD to the sim ted from a graphical schematic drafted in thout having a schematic Linear Technology s fili can synthesize a netlist for LTspice to simulate the time domain or frequency response of a filter simplifies benchmarking LTspice against other SPI ulator While that mode of operation has been CE the netlist an imported netlist can be run it simul wi in th the tex tegrated with SPI Example Circuits 10 tual netlists becaus This has several ter synthesis program
25. Syntax func lt name gt args lt expression gt Example func Pythag x y sqrt x xty y The func directive allows the creation of user defined functions for use with user parameterized circuits and behavioral sources This is useful for associating a name with a function for the sake of clarity and parameterizing subcircuits so that abstract circuits can be saved in libraries The func statement can be included inside a subcircuit definition to limit the scope the function to that subcircuit and the subcircuits invoked by that subcircuit To invoke parameter substitution and expression evaluation with these user defined functions enclose th xpression in curly braces The enclosed expression will be replaced with the floating point value Below is a example using both a func and param statements Example deck using a func statement func myfunc x y sqrt x xty y param u 100 v 600 Vl a 0 pulse 01 0 1n in 5p 1p Rl a b myfunc u v 3 C1 b 0 100p tran 3y end All parameter substitution evaluation is done before th simulation begins 69 FERRET Download a File Given the URL This command allows you to download files in batch mode by specifying the urls This is handy when you don t want to have to point your browser at every file The downloaded file will be in the same directory as the source schematic or netlist This command has
26. The parameter list depends on the type of model Below is a list of model types Type Associated Circuit Element SW Voltage Controlled Switch CSW Current Controlled Switch URC Uniform Distributed RC Line LTRA Lossy Transmission Line 80 PJ NMOS PMOS NMF PMF VDMOS See the descrip of which paramet NPN Bipol Diode ar Transistor PNP Bipol N chan P chan N P N P Vertical are common to a model Double JFET JFET nel nel annel annel annel annel U o eh ch ch ch lar Transistor model model MOSFET MOSFET MESFET MESFET Diffused Power MOSFET tion of the circuit element for a list ters are instance specific and which NET Compute Network Parameters in a AC Analysis This sta compute parameters Syntax net Rin lt val gt V out ref H parame can also be AC statement twork analysis tement is used with a small signal AC the input and output admit Z parameters a 2 port network It input admittance and impedance of a l port network must be used with a frequency sweep of the ne ters Rout Rout lt val gt tance Vin I analysis to impedance Y and S parameters of used to compute the the This which determines th in The network input is specified by either an independent voltage source Vin
27. The response must drop at high frequencies or an error is reported It is recommended that the LTspice first be allowed to make a guess at this and then check the accuracy my reducing reltol or explicitly setting nfft and window The reciprocal of the value of window is the frequency resolution The value of nfft times this resolution is the highest frequency considered The Boolean XOR operator is understood to mean exponentiation xx when used in a Laplace expression 120 Syntax Gxxx n n value lt expression gt This is an alternative syntax of the behavioral source rbitrary behavioral voltage source B Syntax Gxxx n n POLY lt N gt nodel nodel node2 node2 nodeN nodeN gt lt c0 cl c2 c3 c4 This is an archaic means of arbitrary behavioral modeling with a polynomial It is useful for running existing Linear Technology behavioral models H Current Dependent Voltage Source Symbol Name H Syntax Hxxx n n lt Vnam gt transresistance This circuit element applies a voltage between nodes n and n The voltage applied is equal to the value of the gain times the current through the voltage source lt Vnam gt Syntax Hxxx n n value lt expression gt This is an alternative syntax of the behavioral Source arbitrary behavioral voltage source B Syntax Hxxx n n POLY lt N gt V1 V2 V3 cO cl c2 G
28. atanh x buf x ceil x cos x cosh x d exp x floor x hypot x y if x y z int x inv x limit x y z Arc cosine of x Synonym for acos Arc hyperbolic cosine Arc sine Synonym for sin Arc hyperbolic sine Arc tangent of x Synonym for atan Four quadrant arc tangent of y x Arc hyperbolic tangent if x gt 5 else 0 Integer equal or greater than x Cosine of x Hyperbolic cosine of x Finite difference based derivitive e to the x Integer equal to or less than X sqrt x 2 y 2 If x gt 5 then y else z Convert x to integer 0 if x gt 5 else 1 Intermediate value of x y and z Natural logarithm of x Alternate syntax for In 45 For complex data the functions atan2 sgn u buf inv uramp int floor ceil rand min limit if 46 log10 x max x y min x y pow x y pwr x y pwrs x y rand x random x round x sgn x Sin x sinh x sqrt x table x a b c d Base 10 logarithm The greater of x or y The smaller of x or y x y abs x y sgn x abs x y Random number between 0 and 1 depending on the integer value OT X Similar to rand but smoothly transitions between values Nearest integer to x Sign of x Sine of x Hyperbolic sine of x Square root of x Interpolate a value for x based on a
29. inductor damping if no Rpar is given This setting will be remembered between invocations of the program There is also a default series resistance of 1 milliOhm for inductors that aren t mentioned in a mutual inductance statement This Rser allows SwitcherCAD to integrate the inductance as a Norton equivalent circuit instead of Thevenin equivalent in order to reduce the size of the circuit s linearized matrix If you don t want LTspice to introduce this minimum resistance you must explicitly set Rser 0 for that inductor This will require LTspice to use the more cumbersome Thevenin equivalent of the inductor during transient analysis There are two forms of non linear inductors available in LTspice One is a behavioral inductance specified with an expression for the flux The inductor s current is referred to by the keyword x in the expression Below is an example in a netlist 132 L1 NOO1 0 Flux lm tanh 5 x O NOO1 PWL O O 1 1 tran end In the above example Il supplies a unity dI dT so that the inductance can be read off as the voltage on node NO0OI There other non linear inductor available in LTspice is a hysteretic core model based on a model first proposed in by John Chan et la in IEEE Transactions On Computer Aided Design Vol 10 No 4 April 1991 This model defines th hysteresis loop with only three para
30. lt expr gt WHEN lt expr gt AT lt expr gt TD lt vall gt lt RISE FALL CROSS gt lt count1 gt LAST Note one can optionally state the type of analysis to which the MEAS statement applies This allows you to use certain MEAS statements only for certain analysis types The name is required to give the result a parameter name that can be used in other MEAS statements Below are example MEAS statements that refer to a single point along the abscissa MEAS TRAN resl FIND V out AT 5m Print the value of V out at t 5ms labeled as resl MEAS TRAN res2 FIND V out I Vout WHEN V x 3 V y Print the value of the expression V out I Vout the first time the condition V x 3 V y is met This will be labeled res2 MEAS TRAN res3 FIND V out WHEN V x 3 V y cross 3 Print the value of V out the third time the condition V x 3 V y is met This will be labeled res3 MEAS TRAN res4 FIND V out WHEN V x 3 V y rise last 76 Print the value of V ou V x 73 V y is met when wrt 3 V y This will t the last time the condition approached as V x increasing be labeled res4 MEAS TRAN res5 FIND V out WHEN V x 3 V y cross 3 TD 1m Print the value of V ou V x 73 V y is met but time as elapsed to 1ms t the third time the condition don t start counting until t
31. n lt inductance gt ic lt value gt 130 Rser value Rpar lt value gt Cpar value m lt value gt temp lt value gt series inductances capacitance Na me Rs er Rp Cp ar TG It is possible to specify an equivalent series resistance parallel resistance and parallel shut lt Inductance gt The equivalent circuit is given below Inductor Instance Parameters Equ Equ Equ Num Ini Description ivalent seri S resistance ivalent paral lel resistance ivalent paral lel capacitance ber of parall tial current flagged on the lel units used only if uic tran card 131 tc Linear inductance temperature coeff Be Quadratic inductance temperature coeff te Instance temp mp It is better to include the device parasitics Rpar Rser and Cpar in the inductor than to explicitly draft them LTspice uses proprietary circuit simulation technology to simulate this physical inductor without any internal nodes This makes the simulation matrix smaller faster to compute and less likely to be singular over all time step sizes By default LTspice will supply losses to inductors to aid SMPS transient analysis For SMPS these losses are of usually of no consequence but may be turned off if desired On the Tools gt Control Panel gt Hacks page uncheck Supply a min
32. 0 QQQRQ EIS BEY ES ADS Enter an algebraic expression to plot Delete this trace l6us 20s 24us 28us 32us 36s 40us 44s 48s 52us 56s 60ps Right Click to edit expression Control eft Click to integrate ns Z When there are attached cursors active a readout display becomes visible that will tell you the location and difference of the cursors 54 PX Ele View Tools window Hep E AS HP Xo amp Q amp RESBtY E5PRAOS 0 LT1074 app m Cursor 1 out Harz 41 512us Vert 5 11878V Cursor 2 Vout B Horz 45 6867us Vert 5 13251V Diff Horz 4 1747us 13 7339mV Freq 239 538KHz 1 3289 79 lous 20us 24us 28us 32us 36us 40s 44s 48ps 52us 56s x240J208 y 25 12132V Note that there is also mouse cursor readout independent of the above attached cursor readout As you move the mouse over the waveform window the mouse position is readout on the status bar If you drag the mouse as if you were going to zoom the size of box is displayed on the status bar This lets you quickly measure differences with the mouse Cursors If the horizontal axis is time then this time difference is also converted to frequency 55 Fi Linear Technology LTspice SwitcherCAD III preamp asc File Edit Hierarchy View Simulate Tools Window Help Bs OF 40 QQQRQ SG ABs sew OS ECC Ous 20us Click to plot V 1 N003 You can measure differences in this manner witho
33. Each time you execute Simulate gt Efficiency Calculation gt Mark Start you restart the efficiency calculation and clear the waveform history This is a good method of preventing the data file from becoming too large and slowing down plotting so it s recommended that you periodically execute Simulate gt Efficiency Calculation gt Mark Start whenever it is clear that you ve accumulated substantial data that you don t want to be included in the integration of efficiency Use the ic directive to specify node voltages and inductor currents to reduce the length of the transient analysis required to find the steady state nodiscard 100 Don t delete the part of the transient simulation before steady state is reached step Compute the step response of the circuit This function works with a current source used as a load with a list of step currents The procedure is 1 compute to steady state and discard the history unless nodiscard is set 2 ramp the step load to the next value in the list of currents at the rate of 20A us 3 compute to steady state 4 change the step load to the next value in the list or quit if there is none Due to the circuit complexity the automatic STEP transition might not be detectable Under this circumstance it is best to use the TRAN command to run the transient simulation and observe the starting and ending periods of the desired step load response Use PWL command to program
34. Elierarchy 5 eir t ee tite ee ete i tee dem 36 Netlist OptlOnS cress etr reti o e eie RU inei t dee ee te et 183 208 O O Lossy Transmission Line 5 4 5 tee eie re ee teet re Cette Here berita p 148 Operation 2 Sit deed ee ie a i A ak ape ee elaine la 178 OVERVIEW M 34 P PCB Netlist Extraction nicer tse rer tete e reb cvsea cde caueesta deae ea eee dnd ee aes en dea 24 Placimg COtfpOnents e tr ete P spe dente eats PEE E ELE hie E eese epi oen 22 Plot Pan is cece sdentees Boban E EEEE S E ENEE E AES AE VRE EE pivenboucuns EL E aE 51 Prefdceeis ai eR A RR OK EE ERRARE RE EUR A ERREUR EEERR T 4 Programming Keyboard Shortcuts eese nennen inneren 23 Q Q Bipolar tr nsistOr m e A Em E e A EE ena EU bids EPA be Ted 150 R R RESSON EM r 163 Rul s of Hierarchy Jet Re e iiie PR ibecten citi het ttd nt 35 Runnin s Under Ean seg ederet eR pde eeu eiae Pe rut 203 S 8 Voltage Controlled Switcli iniit nine ELO OO Re E EE EE e ue 164 Save Plot ConfiguratiOnDs aei one Oeo CD P TRO Re DOR TR Tee CORTE 57 Schematic Colors nni nto dot CORP ERR ER COR ERRORES 21 S heinatic Editino 3 i neg eme a nU DEP EGO p OU RERO RAT DR 16 Software Installation d ahiecoten nme poro en dm aro m D EO E s 8 Specialized Component Editors 2 2 n es e ep bt tr ere Pe ERI EHE orien 26 SPICE Error Log Command e nni orte e n E ep eire
35. Example S1 out 0 in 0 MySwitch model MySwitch SW Ron 1 Roff 1Meg Vt 0 Vh 5 Lser 10n Vser 6 The voltage between nodes nc and nc controls the switch s impedance between nodes nl and n2 A model card is required to define the behavior of the switch See the schematic file examples Educational Vswitch asc to see an example of a model card placed directly on a schematic as a SPICE directive Voltage Controlled Switch Model Parameters Na Description me Vt Threshold voltage Vh Hysteresis voltage Ro On resistance n 164 Un it Defa ult Ro Off resistance Q 1 Gm ff in Ls Series inductance H 0 er Vs Series voltage V 0 er Il Current limit A Infi im it The switch has three distinct modes of voltage control depending on the value of the hysteresis voltage Vh If Vh is zero the switch is always completely on or off depending upon whether the input voltage is above the threshold If Vh is positive the switch shows hysteresis as if it was controlled by a Schmitt trigger with trip points at Vt Vh and Vt Vh Note that Vh is half the voltage between trip points which is different than the common laboratory nomenclature If Vh is negative the switch will smoothly transition between the on and off impedances The transition occurs between the control voltages of Vt Vh and Vt Vh The smooth transition follows a low order polynomial fit to the logarithm o
36. MODEL statements are for intrinsic SPICE devices like diodes and transistors The MODEL statement gives the parameters for the specific component The behavior of the device it already known by SPICE only the parameters need to be given to finish specifying the component s electrical characteristics On the other hand models given by SUBCKT statements define the modeled component by a collection of circuitry of intrinsic SPICE devices For example the SPICE model of an opamp would be given as a subcircuit 191 The way how to include the model in LTspice depends on whether th SUBCKT Example for an NPN transistor defined with a model is given as a MODEL statement or a MODEL statement 1 Add an instance of the symbol NPN to your schematic 2 Edit the value NPN to be BC547C to coincide with the name used in the target MODEL statement 3 Now either 3a Add the Or 3b 3c 192 MODEL BC547C st atement as a SPICE directive on your schematic MO fale bipol lib pipol lib file extensions and defaults to not showing th you if you have a file cal which you can edit view in orer shows you the file exits as SPICE directive to incl If you used get an error message that Expl The bipol sub txt wil If you have a fi DEL BC547C le bipol li then add the SPICE b containing your other mode
37. Modulation index Fsi Signal frequency Hz g The current is given by off Iamp sin 2 pi Fcar time MDI sin 2 pi Fsig time Syntax Ixxx n n tbl voltage current voltage current Sp o The current can also be specified as a function of the voltage across the output nodes with a look up table This is useful for modeling the characteristics of a load Syntax Ixxx n n value step lt valuel gt lt value2 gt lt value3 gt load 125 This is a special form for the current source The current is specified as a list of currents to use in a step load response transient analysis In this mode the simulation is computed until steady state is reached at the first current in the list lt valuel gt Then the current is stepped to the next value in the list lt value2 gt The simulation proceeds until steady state is achieved at that current Then the current is stepped to the next value and the process repeats until the list is exhausted If the tran command doesn t specify step then the original value is used Syntax Ixxx n n R lt value gt This is not a current source at all but a resistor It is used to model a resistive load when the load is netlisted as a current source LISEZ 12 US I3 Syntax Ixxx n n PWL t1 Arbitrary Pi wise linear current source c For times before tl the c
38. as a general purpose circuit design package with schematic capture and SPICE simulation We do encourage students using the program to become familiar with the analog design process We cannot guarantee support for non Linear Technology related program usage but we ll fix all general program bugs and appreciate such reports We do extensive in house testing and believe the program has superior convergence capability There are no known outstanding bugs Who can I contact at Linear Technology for help For all software issues e mail scad3 linear com For all hardware issues such as additional application information for Linear Technology IC s call Linear Technology application department at 408 954 8400 during normal business hours Circuit Efficiency Calculation What is the difference between APP and ASC files An APP file is a schematic file and has embedded control statements to help calculate efficiency and other product information ASC file is the general schematic file without any hidden SPICE commands ASC file is the more general and powerful file format It is recommended that you save your own designs with a ASC file name extension How can I get an efficiency report for my schematic 198 You need to add a TRAN time steady statement on the schematic state by checking The program wil 1 automatically detect the steady the internal state of
39. curve iteration count limit Transient analysis time point iteration count limit Set to zero to prevent Source stepping for the initial DC solution Alternative name for itle maximum number of clock cycles to save Maximum step size for transient analysis Complex number format of meas statement results One of polar cartesian or bode Number of significant figures used for measure statement output Numerical integration method either trapezoidal or Gear minimum number of clock cycles to save 85 MinDeltaG min nomarch noopiter numdgt pivrel pivtol reltol srcstepme thod sstol startcloc ks temp 86 Nu Nu le fal se fal se le le 13 ay Sets a limit for termination of adaptive gmin stepping Do not plot marching waveforms Go directly to gmin stepping Historically numdgt was used to set the number of significant figures used for output data In LTspice if numdgt is set to be gt 6 double precision is used for dependent variable data Relative ratio between the largest column entry and an acceptable pivot value Absolute minimum value for a matrix entry to be accepted as a pivot Relative error tolerance Which source stepping algorithm to start with Relative error for steady state detection Numbe
40. example the following deck will download this manual as a pdf file Dummy simulation to download the help file The simulation will abort with an error but you ll be left with the file scad3 pdf in the same directory containing the netlist inc http ltspice linear com software scad3 pdf end X X LIB Include a Library Syntax lib filename This directive includes the model and subcircuit definitions of the named file as if that file had been typed into the netlist instead of the lib command Circuit elements at global scope are ignored An absolute path name may be entered for the filename Otherwise LTspice looks first in the directory 72 lt SwCAD gt lib cmp and then lt SwCAD gt lib sub and then in the directory that contains the calling netlist where lt SwCAD gt is the directory containing the scad3 exe executable typically installed as C Program Files LTC SwCAD No file nam xtension is assumed You must use lib myfile lib not lib myfile if the file is called myfile lib It is possible to specify a url of the following form as a file name lib http www company com models library mod The file library mod will be http transferred to the circuit directory and included as a library For subsequence simulations in the interest of avoiding downl
41. internal temp lt value gt time lt value gt repeat step lt value gt DCl lt value gt DC2 lt value gt DC3 lt value gt This command writes a text file to disk that is reloaded with a loadbias command in a subsequent simulation If you have a circuit that has a difficult to solve DC Operating point you can save that solution to disk so that the next analysis can save time finding the DC solution before proceeding to the rest of the simulation The keyword internal can be added to indicate that the internal nodes of some devices should also be kept so that a more complete version of the DC solution is kept If you want to save a particular DC operating point from a tran analysis you can give specify a time The first solved time point after the stipulated time will be written The modifier repeat will cause the DC solution 93 to be written after every period specified by this time The file will contain only the most recently solved DC point DC1 DC2 and DC3 can be given to extract a single Operating point from dc sweep analysis The savebias command writes a text file in the form of a nodeset command Note that nodeset statements are only recommendations of the solution That is the solver will start iterating the solution with the node voltages given in the nodeset statements but will continue iterating until it s sati
42. is the frequency that the magnitude of V out is equal to 0 7071067811865475 Also the result of a MEAS statement can be used in another MEAS statement In this example the 3dB bandwidth is computed MEAS AC tmp max mag V out find the peak response and call it tmp MEAS AC BW trig mag V out tmp sqrt 2 rise 1 targ mag V out tmp sqrt 2 fall last Print the difference in frequency between the two points 3dB down from peak response NOTE The data from a AC analysis is complex and so are the measurement statements results However the equality refers only to the real part of the complex number that is mag V out tmp sqrt 2 is equivalent to Re mag V out Re tmp sqrt 2 The AVG RMS and INTEG operations are different for NOISE analysis than the analysis types since the noise is more meaningfully integrated in quadrature over frequency Hence AVG and RMS both give the RMS noise voltage and INTEG gives the integrated total noise Hence if you add the SPICE directives MEAS NOISE out totn INTEG V onoise MEAS NOISE in totn INTEG V inoise to a noise analysis the total integrated input and output referenced rms noise will be printed in the log file MEAS statements are done in post processing after the simulation is completed This allows you to write a script of MEAS statements and execute them on
43. line switch nowine in case you re interesting in working on WINE issues What about a Paper Manual You can download a pdf of these help pages from http LTspice linear com software scad3 pdf and print it if you wish 204 What about a Users Group There is an independent users http groups yahoo com group LTspice group at The group has a Files section with additional tutorials libraries and examples SPICE Error Log Command Use this command to display the simulation log file A typical log file is shown as follows Circuit D XP lib app LT1300 DC035A app Date tnom 27 temp 27 method modified trap totiter 14872 traniter 14862 points 3865 tran accept 2986 rejected 879 trancuriters matrix size llins 2 fi W N O lver Normal eb Update Tue Oct 05 Total elapsed time 16 57 31 1999 6 64 seconds All windows must be closed first before the Sync_Release command can be activated internet connection first The SwCAD The user needs to establish the program will then download the master index file release log from the LTC web server The master index file contains the checksums for every file in the sub directories checksum is then cal The local file s lculated and checked against the one in the master index file The file on the web server will 205
44. model area off Dot Commands IC lt Vds Vgs gt C Simulator Directives Dot Commands To run a simulation AC small signal not only must the circuit be defined but also the type of analysis to be performed six different types of analyses DC sweep noise DC operating point There are linearized small signal DC 65 transfer function and transient analysis Precisely one of these six analyses must be specified Whereas the circuit topology is typically schematically drafted the commands are usually placed on the schematic as text All such commands start with a period and are therefore called dot commands AC Perform an Small Signal AC Analysis Linearized About the DC Operating Point The small signal linear AC portion of LTspice computes the AC complex node voltages as a function of frequency First the DC operating point of the circuit is found Next linearized small signal models for all of the nonlinear devices in the circuit are found for this operating point Finally using independent voltage and current sources as the driving signal the resultant linearized circuit is solved in the frequency domain over the specified range of frequencies This mode of analysis is useful for filters networks stability analyses and noise considerations Syntax ac oct dec lin lt Nsteps gt StartFreq lt EndFreq gt The frequency is swept between fr
45. model of Gummel and Poon This modified Gummel Poon model extends the original model to include several effects at high bias levels quasi saturation and substrate conductivity The model automatically simplifies to the Ebers Moll model when certain parameters are not specified The DC model is defined by the parameters Is Bf Nf Ise Ikf and Ne which determine the forward current gain characteristics Is Br Nr SC kr and Nc which determine the reverse current gain characteristics and Vaf and Var which determine the output conductance for forward and reverse regions Three ohmic resistances Rb Rc and Re are included where Rb can be high current dependent Base charge storage is modeled by forward and reverse transit times Tf and Tr the forward transit time Tf being bias dependent 150 if desired capacitances Mje for the B E junction B C junction and Cjs Vjs and Mjs for the Collec Substrate junction The temperature dependenc gap Eg exponent XII and nonlinear depletion layer and the saturation current temperature Additionally base current temperature which are determined by Cje Vje and Cjc Vjc and MJC for the tor of the saturation current Is is determined by the energy dependence is modeled by the beta temperature exponent XTB in assumed to hav the new model The values
46. ships with approximately 800 symbols symbols cover most of LTC s power and many general purpose devices for circuit design ICs opamps The limited only by These comparitors You can also draw your own symbols for devices you wish to import into the program 16 i ziBlxll File Edit Hierarchy View Simulate Tools Window Help xi ee ee Si BSW ES CAOS L mi r edo op SPICE Directive SPICE Analysis Resistor Capacitor 3 Inductor SE Diode D Component Em Rotate Ea Timor _ Draw Wire 3 Label Net xr Place GND amp Delete B2 Duplicate Move fri Paste Drag Line Rectangle Circle Unlike many schematic capture programs this one was written explicitly for running SPICE simulations This means that if you click on an object the default behavior is to plot the voltage on that wire or current through that component not select the object for editing or some other editing behavior which would then invalidate the simulation just performed Hence when you wish to move mirror rotate drag or delete objects first select the move drag or delete command Then you can select an object by clicking on it You can select multiple objects by dragging a box about them The program will stay in the move drag or delete mode until the right mouse button is clicked or the Esc key is pressed All schematic edits can be undone or redone 17
47. simulation capability has been added along with extensive enhancements to the analog SPICE simulator to make LTspice the industry superlative board level analog and mixed mode simulator for many classes of circuits such as switching regulators and switched capacitor filters Many Linear Technology products are modeled with proprietary building blocks and or a proprietary hardware disruption language that accurately encapsulate realistic behavior with custom macromodels This allows the power system board to be simulated and prototyped rapidly LTspice can be used as a general purpose SPICE simulator New circuits can be drafted with the built in schematic 59 capture Simulation commands and parameters are placed as text on the schematic using established SPICE syntax Waveforms of circuit nodes and device currents can be plotted by clicking the mouse on the nodes in the schematic during or after simulation An invaluable reference that complements this documentation is the 2nd Edition of Semiconductor Device Modeling with SPICE by Giuseppe Massobrio and Paolo Antognetti McGraw Hill 1993 That book documents the semiconductor device equations and extensions that have been used in various commercial SPICE programs including those used in this one For BSIM 3 and 4 devices see the relevant documentation available from the UC Berkeley CAD group LTspice and SwitcherC
48. specified are been measured at the temperature TNOM line or which can be specified on the OPTIONS control overridden by a specification on the model line The BJT parameters used in the modified Gummel Poon model are listed Name Bf Nf Vaf Ikf Ise below Modified Gummel Poon BJT Parameters Description Transport saturation current Ideal maximum forward beta Forward current emission coefficient Forward Early voltage Corner for forward beta high current roll off B B E leakage saturation current E Ideal akag mission coefficient maximum reverse beta Reverse current emission coefficient Un it Defa ult le 16 100 Infi Infi 151 Var Isc Nc Rb Irb Rbm Vje Mje If yc Vjc Mjc 152 Reverse Early voltage Corner for reverse beta high current roll off B C leakage saturation current B C leakag mission coefficient Zero bias base resistance Current where base resistance falls halfway to its min value Minimum base resistance at high currents Emitter resistance Collector resistance B E zero bias depletion capacitance B E built in potential B E junction exponential factor Ideal forward transit time Coefficient for bias dependence Of TI Voltage describing Vbc dependence of Tf High current parameter for
49. tch mode power ing simplifying assum t have upply tions nulat a S P which don t allow arbitrary control logic and fully sim SPI Swi ulai te the complexity of th CE with integrated logic primi tch mode contro fast simulati allows the f on tin exibil e swil tching waveforms A new L provides a be ives that perform the ter answer It can give nes yield d ity for arbit SwitcherCA D is mode model parasit circuit elementi ling board level a new SPICE Incorporated into the new SP practical board level components inductors can be modeled with series resis tic aspects of their behavior withou ts or internal nodes was developed for power MOSFET s that accurately CE tailed waveforms and still trary circuit modifications that was developed for switching regulator systems are circuit elements to Also Capacitors and tance and other t using sub a simulation circuit exhibi nodes ts their usual gate charge behavior without using sub circuits or internal nodes the simulator needs to solve significantly reduces Reducing the number of the computation required for a given simulation without compromising the accuracy or del tail of the switching waveforms Another benefit of these new simulation devices is that converg
50. the LTC macro models It doesn t work when LTC switching regulator part is absent There must be exactly one Voltage source in the circuit This will be identified as the input There must be exactly one current source in the circuit This will be identified as the load After the simulation is done you can select the Efficiency see the report on the schematic Custom Symbols Report under the View menu to Can I create my own symbols Yes you can create your own symbols How do I create my own symbol Start with the menu command File New Symbol Can I create my own switching regulator models Not very easily with LTspice SwitcherCAD The switching regulator models that ship use a new hardware description language and new intrinsic SPICE devices designed to encapsulate the behavior of LTC s switching regulator Even if you succeed in making a model with products standard SPICE primitives orders of magnitude longer Note that some people hav made such devices switching regula the simulation time will be tor models with standard SPICE LTspice can run these models and will usually outperform the simulator for which they were targeted Memory Problems 199 How much memory do I need to run the program You can basically run the SwitcherCAD if you can operate your Windows system W
51. the file plot defs in the same directory as the SwCADIII executable scad3 exe Then the syntax is the same as the param and func statements used for parameterized circuits E g the line 50 func Pythag x y sqrt x x y y defines the function Pythag to be the square the sum of its two arguments Similarly the line param twopi 2 pi would define twopi to be 6 28318530717959 Note th uses the already internally defined constant pi of waveform viewer Axis Control root of at Xt the When you move the mouse cursor beyond the data plotting region the cursor turns into a ruler This tries indicate that you are pointing at that axis attrib When you left click you can enter a dialog to manua enter that axis range and the nature of the plot example for real data if you move the mouse to th of the screen and left click you can enter a dialog to change the horizontal quantity plotted This lets parametric plots For complex data you can choose to plot eithe group delay or nothing against the right vert axis data from Bode to Nyquist or Car to utes lly For e bottom you make r phase ical You can change the representation of complex tesian by moving the mouse to the left vertical axis of complex data Plot Panes Multiple plot panes can be displayed on one window This allows better separation between traces and allo
52. the more popularly supported wav file formats have 1 or 2 channels 8 or 16 bits channel and a sample rate of 11025 22050 or 44100 Hz 98 Transient Analysis Options TRAN Modifiers UIC Skip the D C operating solution and use user specified initial conditions steady Stop the simulation when steady state has been reached nodiscard Don t delete the part of the transient simulation before steady state is reached startup Solve the initial operating point with independent voltage and current sources turned off Then start the transient analysis and turn these sources on in the first 20 us of the simulation step Compute the step response of the circuit UIC Use Initial Conditions Normally a DC operating point analysis is performed before starting the transient analysis This directive suppresses this initialization The initial conditions of some circuit elements can be can be specified on an instance per instance basis Uic is not a particularly recommended feature of SPICE Skipping the DC Operating point analysis leads to a nonphysical initial condition For example consider a voltage Source connected in parallel to a capacitance The node voltage is taken as zero if not specified Then in the first time step an infinite current is required to charge the capacitor The simulator cannot find a short enough time step to make the current nonsingular and a time step too small c
53. the output load current and switches to different levels at desired time periods For example PWL O 0 5 Im 0 5 1 01m 0 1 3m 0 1 3 01m 0 5 The load current starts with 0 5A at time 0 stays at 0 5A at 1ms switches to 0 1A at time 1 01ms stays at 0 1A until 3ms and switches to 0 5A at 3 01ms and stays at 0 5A The PWL can have almost unlimited pairs of time value Sequence 101 Circuit Elements A Special Functions Symbol names INV BUF AND OR XOR SCHMITT SCHMTBUF SCHMTINV DFLOP VARISTOR and MODULATE Syntax Annn n001 n002 n003 n004 n005 n006 n007 n008 model instance parameters These are Linear Technology Corporation s proprietary Special function mixed mode simulation devices Most of these and their behavior are undocumented as they frequently change with each new set of models available for LTspice However here we document some of them because of their general interest INV BUF AND OR and XOR are generic idealized behavioral gates All gates are netlisted with eight terminals These gates require no external power Current is sourced or sunk from the complementary outputs terminals 6 and 7 and returned through device common terminal 8 Terminals 1 through 5 are inputs Unused inputs and outputs are to be connected to terminal 8 The digital device compiler recognizes that as a flag that that terminal is not used and removes it from the simulation
54. triode asc U180 60 U2G0 0 x1 A G O SU3CX300 dc U1 0 500 1 U2 50 10 10 subckt SU3CX300 A G K Emu mu O0 UVALUE PWRS U G K 0 98 Eshape shape 0 URLUE 280 U G K 280 Eos gs 0 URLUE LIMIT U AO K U G K x7 5 0 1E6 Egs2 gs2 0 VALUE PWRS U gs xU shape 1 5 135E 6 Ecath cc 0 VALUE U gs2 Ga A K VALUE U cc Cok G K 25p Coa A G 10p Cak A K Ip ends Efficiency Report It is possible to obtain an efficiency report from a converter from a time domain the keyword steady DC tran analysis that contains After a steady state simulation DC an efficiency report can be made visible on the schematic as a block of comment text 13 Efficiency Report Efficiency 77 6 Input 16 5W 9 97 Output 12 8W 5 12 Irms Ipeak 339mA 495mA 190mA OmA 2686mA 2681mA 1mA 1mA Dissipation Bmw 1mWwW Om 418mw Bmw 3mW 2mWwW OMA ouw 2040mA 2894mA 3266mW The efficiency of the DC DC converter is derived in the following manner In order to identify the input and output there must be exactly one voltage source and one current source The voltage source is assumed to be the input while the current source is assumed to be the output The circuit is run until steady state is sensed by the simulator This requires the SMPS macromodels to be written with information on how to detect steady state Usually this is detected by noting when the error amp
55. what they re those who are sure switching regulator Th xperienced designer n to quickly alter aspect ds a what if program ts of a circuit to Ihe neophyte needs a cookbook liable design based on the The loose cannon designer needs a allow him to exercise his free will but intelligent enough to alert him to fatal design flaws To that end we made SwitcherCAD an extremely flexible what if electronic design tool that has warning labels when things are getting out of hand We designed th program to have a complete initial on the essential inputs of voltage This allows the terrified designer circuit permits th xperienced d design cycle based only and power requirements to start with a working signer to have unlimited fun changing things and we hope provides enough safeguards to prevent bad designs Please be aware however that SwitcherCAD is not intended as a total solution It is only a tool to ease the design procedure which must also include breadboarding and testing Use common sense with the results obtained from simulation SwitcherCAD Ill Overview SwitcherCAD is the third generation switching regulator design program by Linear Technology The program consists of a high performance SPICE simulator extended with a mixed mode simulation capability that includes
56. 3 O4 uis This is an archaic means of arbitrary behavioral modeling with a polynomial It is useful for running existing Linear Technology behavioral models l Current Source Symbol Name CURRENT Syntax Ixxx n n current AC lt amplitude gt load 121 This circuit element sources a constant current between nodes n and n source is forced to be dissipat goes to zero if the voltage be zero or a negative value current if the ou For AC analysis of the source at Syntax If the source is flagged as a load the tive that is the current tween nodes n and n goes to The purpose of this options is to model a current load on a power supply that doesn t draw tput voltage is zero the value of AC is used as the amplitude the analysis frequency Ixxx n n PULSE off on Tdelay Trise Tfall Ton Tperiod Ncycles Time dependent pulsed current source Nam lon Tde Tr If Ton Tpe rio Ncy 122 Description Un it S Initial value A Pulsed value A Delay se Ge Rise time se o Fall time se o On time se e Period se e Number of cycles Omit cy cle for free running pulse cl function es Syntax Ixxx n n SINE Ioffset Iamp Freq Td Theta Phi Ncycles Time dependent sine wave current source Nam e Iof fse t lam p Fre Td The ta Phi N
57. 73 asc XK 2 5v 5 Type LTspice Schematic ly sy 100mA 1 40 LSV3V30mA1610 asc di 2 5y 226 237 KB V 5V 100m 1 X 15v 5V10mA1110 asc X 3 3V 12V 100mA 1301 asc d 3V 5V 100m 1 gt R3 Filename Files of type Schematics asc sch app oa Cancel Z General Purpose Schematic Driven SPICE You are free to use LTspice SwitcherCAD as a general purpose schematic capture SPICE program This is useful not only for SMPS design but many aspects of analog engineering The example circuits typically installed in the directory C Program 11 FilesNLTCNSwCAD examples Educational illustrate various LTspice capabilities F jLinear Technology LTspice SwitcherCAD III astable asc IE x File Edit Hierarchy View Simulate Tools Window Help ASslibr 0 QCQR BA BSH be Al 8S 5Y 1V Oms 3ms 6ms 9ms 12ms 15ms 18ms 21ms 24ms astable asc Click to plot V NO02 il Ui Externally Generated Netlists You can open netlists generated either by hand or by other schematic capture programs These files usually have a filename extension of cir but net and sp are understood The ASC editor used for netlist files supports unlimited file size and unlimited undo redo The menu command Tools gt Color Preferences can be used to adjust the colors used in the ASC editor 12 Bie Edit view Simulate Tools Window Help ASET x
58. AD are registered trademarks of Linear Technology Corporation Introduction Circuit Description Circuits are defined by a text netlist The netlist consists of a list of circuit elements and their nodes model definitions and other SPICE commands The netlist is usually graphically entered To start a new schematic select the File gt Open menu item A windows file browser will appear Either select an existing schematic and save it under a new name or type in a new name to create a new blank schematic file LTspice uses many different types of files and documents You will want to make a file with a file name extension of asc The schematic capture commands are under the Edit menu Keyboard shortcuts for the commands are listed under Schematic Editor Overview When you simulate a schematic the netlist information is extracted from the schematic graphical information to a file with the same name as the schematic but with a file extension of net LTspice reads in this netlist 60 You can also open simulate and edit a text netlist generated either by hand or externally generated Files with the extensions net cir or sp are recognized by LTspice as netlists This section of the help documents the syntax used in netlists but occasionally gives schematic level advice General Structure and Conventions The circuit to be analyzed is described by a text file called a netlist The fi
59. AD as it extracts SwitcherCAD is updated often After SwitcherCAD is initially installed you can use a built in update menu command that will bring your installation to the current revision level if you have access to the web The update process will first download a master index file from Linear s website that has the size and checksum of each file in the distribution If there is a file missing of a different size or a difference between the local checksum and the one from the index file then that file will be updated automatically Component databases are merged in the update process so if you ve added devices to your installation those additions won t be lost when you run the automatic update utility License Agreement Disclaimer SwitcherCAD License Agreement Disclaimer Copyright 2001 Linear Technology Corporation All rights reserved SwitcherCAD is Linear Technology Corporation s switch mode power supply synthesis and analog circuit simulation software This software is copyrighted You are granted a non exclusive non transferable non sublicenseable royalty free right solely to evaluate LTC products and also to perform general circuit simulation Linear Technology Corporation owns the software You may not modify adapt translate revers ngineer decom
60. Bache le ned eee 183 HACKS ariani een eee pt ee a ea 185 Drafting Options aceti o rei de eet eta eee tia et 185 Internet Optlons 3 ace anna ait a alannah wel 187 FAQs 189 Program Updales es ditte d io te diei 189 Transformer Models sss entente nnne nnns 190 Thirdsparty Models 2 intecis peto errato te ISAE ENEAK 191 Inid ctor Models iae rite eir ema ccrte a ie tar tir er ee Read 194 MOSFET Models eite tetra peperere the AAE ex i e tad 195 License and Distribution eessseeeeennn enne 197 Circuit Efficiency Calculation essent 198 G stom Symbols tereti e tte haic ent to YR Ree d er etin eng 199 Memory Problems ciue o iere tete tates 199 Model Compatibility eessssses eee 201 SPIGE Netlist z t onte attentis menia anu 201 Exporting Merging Waveform Data sssssse een 201 Running Under LIN K areire rekri Aa EAEE nennen ener nnns 203 What about a Paper Manual ssssssssssseeeee enne 204 What about a Users Group cccceceeeeeeeneeceeeeeceaeeeseaeeeeneeeeeeesaeeeneeeeeaees 205 SPICE Error Log Command 205 Web Update 205 Introduction Preface Do we need another SPI CE Analog circuit simula tion has been inseparable from analog IC design SPICE simulators are the only way to test circuitry prior to integration onto a chip Further the SPICE simulation allo
61. CHER EE ee Con 205 Starting the Control Panel oia en ere d iet tr ti hr bei le 176 Steady suos eene Ceo e tenni 100 SwitcherCAD III Overview pecine enceinte erret EEE KE opviesuecoucaveceytesaeasaleesdevecencseaaneve 6 Symbol Editing adeb eene eae ava eran be RU eT ate 24 T T Lossless Transmission Line cesccesessceesseeseeeseeeeceeecesecnscescesseceecaeceaecaeceaecaeecaeeeaeeeseeeneees 166 Trace Selection zn eire ated eh oe o n TR es ne I iactis an OPERE IIS 38 HAD cise vest E 99 100 101 HCM E 100 rni deeds 99 dij 101 U U Untorm RC Ime 52 notte EE ie e HE D UR qe E HET erret dee 166 User Defined Borse ST 50 V Mine Mt 168 Mie wer OVervle Wise ich dieere p reet e dieere pee o Creed a dv iiri ee ater i e ned 38 W W Current Controlled O MVO eese enne ener nennen nnne nennen 173 Wavetorm Arithmetica ete e eie ete dr m Y 43 Mhat about a Users s Group cente em etre ert ER 205 209 X boxed m uM 174 Z Zc NSI E Ti transistoE eon terea n sade sacs Ea NE 174 Vv 43 210
62. Charact er x Comment A Special function device B Arbitrary behavioral source C Capacitor D Diode E Voltage dependent voltage source F Current dependent current source G Voltage dependent current source H Current dependent voltage source I Independent current source J JFET transistor K Mutual inductance L Inductor M MOSFET transistor O Lossy transmission line Q Bipolar transistor 62 n H zx 4 d Resistor Voltage controlled switch Lossless transmission line Uniform RC line Independent voltage source Current controlled switch Subcircuit Invocation MESFET transistor A simulation directive For example options reltol 1e 4 A continuation of the previous line The is removed and the remainder of the line is considered part of the prior line Numbers can be expressed not only in scientific notation e g multipl written as 1K le iers That Be 12 but also using engineering is 1000 0 or 1e3 can also be ow is a table of understood iers multipl Suffix T G Meg K Mil M u or ug Multiplier 1e12 1e9 1e6 1e3 25 4e 6 1e 3 6 9 1e 12 5 The suffixes are not case sensitive Unrecognized immediately following a number or engineering letters multiplier are ignored Hence 10 10V 10Volts and 10Hz all represent the same number and M MA MSec 63 and MMhos all represent the same scale f
63. Export Netlist allows you to generate the ASCII netlist for PCB layout Note that you would have to make a set of symbols that have the same order of pin netlist order For example if you want to import an LTspice schematic s netlist into ExpressPCB you would have to make a set of symbols for either LTspice or ExpressPCB that had the same netlist order for every symbol you use Otherwise diodes could netlist backwards or transistor lead connections could be scrambled The following formats are available Accel Algorex Allegro Applicon Bravo Applicon Leap Cadnetix Calay Calay90 CBDS Computervision EE Designer ExpressPCB Intergraph Mentor Multiwire PADS Scicards Tango Telesis Vectron and Wire List Editing Components Editing Components 24 Components can be edited in two or three different ways depending on the type of component Most visible component attribute fields can be edited by pointing at it with the clicking The mouse caret when it s poin such bipolar Many component types inductors diodes mouse and then right cursor will turn into a text ting at the texi as resistors transistors capacitors MOSFET transistors JFET t Sources independen circuit blocks have can access the appr use these editors ransistors independent voltage t current sources and hierarchical Special editors These editors opriate database of devices To right mouse click on
64. Gs sever Conigureucn WSiElly anno VASUTEGTTT ESL SG y SENEN SEETJNBITIET IZHSSVWITOGE This pane of the Control Panel is used for the incremental updates obtained from the web LTspice is often updated with new features and models Use the menu command Tools 5Sync Release to update to the current version If you don t update for a couple months LTspice will begin to ask if you would like to check for updates LTspice never accesses the web without asking for your permission to do so LTspice contains no spyware or transmits any type of data while obtaining the files it need for update Don t cache files Neither cache nor use files cached on our machine for the update Don t verify checksums For security reasons LTspice uses a proprietary and confidential 128bit checksum algorithm to authenticate the files it receives off the web for updating This authentication can be disabled in case there s a error in that algorithm However no problem with this has ever been reported so it is not recommended that you ever defeat this security feature 188 LTspice uses only high level operating system calls for its Internet access It should not be required to make any adjustments to these settings except in rare cases when you need to specify the Proxy server and password since LTspice is not managing the Internet access but your computer and Operating system Settings on this pane are not remembered between program invoc
65. NRS lt value gt off IC lt Vds Vgs Vbs gt temp lt T gt M1 Nd Ng Ns 0 MyMOSFET model MyMOSFET NMOS KP 001 136 M1 Nd Ng Ns Nb MypMOSFET model MypMOSFET PMOS KP 001 Vertical double diffused power MOSFET Syntax Mxxx Nd Ng Ns model L lt len gt W lt width gt Me area m lt value gt off IC lt Vds Vgs Vbs gt temp lt T gt Example M1 Nd Ng Ns Si4410DY model Si4410DY VDMOS Rd 3m Rs 3m Vto 2 6 Kp 60 Cgdmax 1 9n Cgdmin 50p Cgs 3 1n Cjo 1n Is 5 5p Rb 5 7m The MOSFET s model card specifies which type is intended The model card keywords NMOS and PMOS specify a monolithic N or P channel MOSFET transistor The model card keyword VDMOS specifies a vertical double diffused power MOSFET Monolithic MOSFETS are four terminal devices Nd Ng NS and Nb are the drain gate source and bulk i e substrate nodes L and W are the channel length and width in meters AD and AS are the areas of the drain and source diffusions in square meters Note that the suffix u specifies um and p square pm If any of L W AD or AS are not specified default values are used PD and PS are the perimeters of the drain and source junctions in meters NRD and NRS designate the equivalent number of squares of the drain and source diffusions these values multiply the sheet resistance RSH specified on the MODEL control line PD and PS default t
66. RIG and TARG The TRIG point defaults to the start of the simulation if omitted Similarly the TARG point defaults to the end of simulation data If all three of the TRIG TARG and the previous WHEN points are omitted then the MEAS statement operates over th ntir range of data The types of measurement operations that can be done over an interval are Keyw Operation perform over interval ord AVG Compute the average of lt expr gt MAX Find the maximum value of lt expr gt MIN Find the minimum value of lt expr gt PP Find the peak to peak of lt expr gt RMS Compute the root mean square of lt expr gt NTE Integrate lt expr gt If no measurement operation is specified the result of the MEAS statement is the distance along the abscissa between the TRIG and TARG points Below are example interval MEAS statements MEAS TRAN res7 AVG V NSO1 TRIG V NS05 VAL 1 5 TD 1 1u FALL 1 TARG V NS03 VAL 1 5 TD 1 1u FALL 1 Print the value of average value of V NS01 from the 1 fall of V NS05 to 1 5V after 1 lus and the lst fall of V NS03 to 1 5V after 1l 1us This will be labeled res7 For AC analyses the conditional expressions of complex data are translated to real conditions by converting the expression to its magnitude So in this example MEAS AC rel18 when V out 1 sqrt 2 78 The result rel8
67. SE 9 1 with 20040716 OK I ve never used WINE how do I install this Check with http www winehq com to find the current version of WINE for your system At the time of this writing for RedHat 8 0 this pointed to http mecano gme usherb ca vberon wine Copy the appropriate rpm file to your machine and open it from nautilus 203 Get the file swcadiii exe from http www linear com In an xterm execute wine swcadiii exe to install LTspice There will now be a Linear Technology Logo on your gnome desktop Double click it to start or type wine scad3 exe from an xterm to start the program The schematic fonts don t scale as smoothly under WINE as Windows Why is that WINE is doing the best it can with the fonts it finds It will do better if you tell it how to find the files arial ttf and cour ttf from your Windows system The PWL additional point editor doesn t look right under WINE Try using the native Windows dll from your Windows system The command line to then invoke LTspice from WINE is wine dll commctrl comctl32 2n scad3 exe It seems LTspice is running slightly differently under WINE Linux than windows Why is that LTspice detects whether or not it s running under WINE f So it works around a few WINE issues You can force LTspice to think it s running under WINE with the command line switch wine You can force it to think it s not with the command
68. Table of Contents Introduction 4 Pref Ce aie es eed naa Ps ike i d eR e RE EX Ee RA ERRARE RR EX Ee Rid ds 4 SwitcherCAD IIl Overview ssseesessseeeenen enne nennen 6 Hardware Requirements eese eene enne nnn 7 Software Installation tie etit te ctn en cta bia et tuse tte o aeuo eua vada ces 8 License Agreement Disclaimer esee enn 8 Mode of Operation 10 ad ES 10 Example CirCuits 1 ot rvs CT 10 General Purpose Schematic Driven SPICE ssssssssssss 11 Externally Generated Netlists ssssssseeeenneens 12 Efficiency Report dee Reo perte te Pe or Em EE Ee Rap lets 13 Command Line Switches sesssssssssssssee eee 15 Schematic Capture 16 Basic Schematic Editing ssssssssssseeeenteenes 16 Label a node name sssssssssssssssssssees esee ener tentent 20 ieri mE 21 Placing New Components sse nnns 22 Programming Keyboard Shortcuts ssssssssssseeeeeenes 23 PCB Netlist Extraction esses nnns 24 Editing Components ssssssssssssseseeee enne nnne ennt ens 24 Edit a Visible Attribute ssesssssssseseseeeneneenn 25 Specialized Component Editors sse 26 General Attribute Editor esses 27 Creating New Symbols cccceeececeeeeeeeeeeeeeee
69. This leads to the potentially confusing situation where AND gates act differently when an input is grounded or at zero volts If ground is the gate s common then the grounded input is not at a logic false condition but simply not part of the simulation The reason that these gates are implemented like that is that this allows one device to act as 2 3 4 or 5 input gates with true inverted or complementary output with no simulation speed penalty for unused terminals That is the AND device acts as 12 different types of AND gates The gates default to OV 1V logic with a logic threshold of 5V no propagation delay and a 1Ohm output impedance Output characteristics are set with these instance parameters 102 Name Def Description aul t Vhigh i logic high level Vlow 0 logic low level Trise 0 Rise time Tfall TET Fall time se Tau 0 Output RC time constant Cout 0 Output capacitance Rout 1 Output impedance Rhigh Rou Logic high level impedance Rlow Rou Logic low level impedance Note that not all parameters can be specified on the same instance at the same time g the output characteristics are either a slewing rise time or an RC time constant not both The propagation delay defaults to zero and is set with instance parameter Td Input hold time is equal to the propagation dela
70. a are B ER ES 31 Adding the Pins reiten oie qo quei paved epe 31 Attached GUrsots e etre E ie teet rr e reU M oeees bee ie TUR ieee ete ree E He eU Ete EE 53 54 57 Attribute Visibilty etie teri fete i pete renidet deren p tete ext een 33 AxIS Control eter remo een ee penis e eiie 51 B B Arbitrary behavioral voltage or current sources sese enne 104 B Circuit description uu oer reete o epi e ede d Mies eee E ete cem 60 C C Simulator directives dot commands eese eene ener enne rennen enne 65 Cy Capacitor uico amato teg SEE tet el anto paie eb EUH 111 Color Control 4 5 oerte pb e ee ien Oe re ae te perdio 52 Command Line Switches icin dain feoaiaentba et rentet eot e bet ees 15 207 COIDpressiOHz eoe be teh eb reet et re Mee a E eost ces 177 Creating Symbol OVervIeW s e erue eite ae t Ptole eia be tee te ID pina 29 D D Diode Ente EROR EORR EET UR 113 Drawing the body espoir ep EEE E Aa Aar E R AEE ai EEE ESEA EERE TAN EEES 30 E E Voltage Dependent Voltage Source eee neesii i isee an eTe es 117 Edit visible attribute 5 creen E KEE E EE ee e Poe hee etie EREE EE eeri 25 Efficiency Report e 13 Example Circuits eodein deep e dde tede rtp ep ied et ede e aoe 11 Exporting Waveform Datta 5 essct esten KE ae er era eher ee abdo erede sede eire neuen 201 Externally Generated Netlists nicaieri ari escen
71. a dataset To to this make the waveform window the active window and execute menu command File gt Execute MEAS Script Another 79 consequence of MEAS statements being done in post processing after the simulation is that the accuracy of the MEAS statement output is limited by the accuracy of the waveform data after compression You may want to adjust the compression settings for more precise MEAS statement output Note when testing a condition such as when lt condl gt lt cond2 gt you will want the condition to go through the equality not must meet it This relates to the fact that floating point equality should never be required due to the finite precession used in storing numbers MODEL Define a SPICE Model Defines a model for a diode transistor switch lossy transmission line or uniform RC line Some circuit elements for example transistors have many parameters Instead of defining every transistor parameter for every instance of a transistor transistors are grouped by model name and have parameters in common The transistors of the same model can have different sizes and the electrical behavior is scaled to the size of the instance Syntax model modname lt type gt lt parameter list gt The model name must be unique That is two different types of circuit elements such as a diode and a transistor cannot have the same model name
72. a dene bate ain ub A E S 80 NET Compute Network Parameters in a AC Analysis eese 81 NODESET supply hints for initial DC solution esee eere 82 NOISE Perform a noise analysis eeeeseseeeseeeeeee eene enne enne e e aE nre nennen 82 OP Find the DC operating point rene enne nren nennen enne trennen trenes 83 OPTIONS Set simulator options eeeseeeeseeeeeneeeneenen eene eene rose trennen trennen 83 PARAM User defined parameters esee eene enne ennt nre 88 SAVE Limit the amount of saved data eese eene 92 SAVEBIAS Save operating point to disk eene ener 93 STEP Parameter s weeps aure e e o eec ete petere Ie ren Te RE OE e ERR ceo Sade 94 SUBCKT define a s bcircult ii ee dete drop deci t Hle ede L o edere Da en eden T 95 TEMP Temperature SWeeps ec rre oce er ertet pae ipa eco oy e tete It 96 TF Find the DC small signal transfer function essere eene 96 TRAN Do a non linear transient analysis nennen enne 97 TRAN Modifiers iom Su em e Eb d eroe PREFIERES TR eve N 99 WAVE Write selected nodes to a wav file 0 cc eeeeeecseeescsseeeeesecseesecneesecsaeeecsaecaeesesnereeeaeeees 98 A A General Structure and Conventions eese eren eene nre enne 61 Ar Special functions 2 oet ee teet eo Be RR P HU dete tipo EE ed 102 Adding Attributes ai 3 nro a tet ade tis aee pite
73. a tete cielo rei Let epo de cae eade dade 12 F F Current Dependent Current Source essere enne trennen 119 Fast Access File Format niet P euer d tire e e E Pens 58 G G Voltage Dependent Current Source eee cseeneeeeeeeeceseceeseesecnsecsaecsaecsaecaecsaeenaecsaeeaeeens 119 General Attribute Editor sce eee eicit e tede oe e FU op tc c ERR TER e idt ees 27 General Purpose Schematic Driven SPICE eese eene nennen 11 H H Current Dependent Voltage Source essere ener 121 Hardware Requirements iri crece ete e eden re erdt dre e Lon ene eee Pn e dde Pv ex 7 I IenusliMuTI T 121 III Circuit Element Quick Reference cccccccscccssscsescecssecesscessecesseeceseeeeseecsseeeeseecsseeesseeceseeeenees 64 Is there paper manual epit ee tee gr RECO TR S IEEE UR ERR RRERREDURER 204 J J JEFE LtransistOE uen RP HU Rd DUE 127 K K Mutual Inductance asic tette ette rit epe reete aec epe Io deve exe Heer ERE 129 L E IndU GtOE ue oe e eed eite eer ec a eei Eee obe e bee ec m than 130 Labela node name oe ea tees ue E ER NEEE AE IER e CHER Nee exe ERR EARS 20 License Agreement Disclaimer isis esas a edt eo weenie wlio eee 8 LT Spice Overview cou eret EE EEEE E EEN KERE E aie 59 M M MOSFET es 5a hob eAnna nod betonte aste ATE ate ave te en 136 Modes Of Operation ee dp ee E RE E e entier be ei teet oa NEA 10 N Nayisatine the
74. actor 001 A common error is to draft a resistor with value of 1M thinking of a one MegaOhm resistor however 1M is interpreted as a one milliOhm resistor This is necessary for compatibility with standard SPICE practice LTspice will accept numbers written in the form 6K34 to mean 6 34K This works for any of the multipliers above It can be turned off by going to Tools gt Control Panel gt SPICE and unchecking Accept 3K4 as 3 4K Nodes names may be arbitrary character strings Global circuit common node ground is 0 though GND is special synonym Note that since nodes ar character strings 0 and 00 are distinct nodes Throughout the following sections of the manual angle brackets are placed around data fields that need to be filled with specific information for example lt srcname gt would be the name of some specific source Square brackets indicate that the enclosed data field is optional Circuit Element Quick Reference Component Syntax Special functions Axx nl n2 n3 n4 n5 n6 n7 n8 model extra parameters Arbitrary behavioral Bxx n n V or I gt source Capacitor Cxx n n capacitance ic lt val gt Rser lt val gt Lser lt val gt Rpar lt val gt Cpar lt val gt m lt val gt Diode Dxx A K model area Voltage dependent Exx n n nc nc
75. al B coefficient B C weak ava parameter 1 B C weak ava parameter 2 C Ideal B C emission mission lanche lanche Parasitic transport saturation current Portion of Parasitic fwd emission coefficient ICCP Ideal parasitic B E saturation current Non ideal parasitic B E saturation c saturation c urrent Ideal parasitic B C urrent Ideal parasitic B C emission coefficient Non ideal parasitic B C saturation current Non ideal parasitic B C emission coefficient Forward Earl y vol Reverse Earl y vol tage tage 1 V 1 V C Infin Infin 159 160 Forward knee current Reverse kn current Parasitic knee current Ideal forward transit time Variation of TF with base width modulation Coefficient for bias dependence of TF Voltage giving VBC dependence of TF High current dependenc of TF Ideal reverse transit time Forward excess phas delay time B E Flicker Noise Coefficient B E Flicker Noise Exponent B E Flicker Noise 1 f dependence Temperature exponent of RE Temperature exponent of RBI Temperature exponent of RCI Temperature exponent of RS Sec Sec Infin Infin Infin C Infin Infin C C C XV ea ea ie ea ic ea is
76. and program it to automatically include the necessary model for the simulation See help section Schematic Capture gt Creating New Symbols Example for a 3 pin NPN transistor but defined with a SUBCKT statement 1 Add an instance of symbol NPN to your schematic 2 Move the cursor over the body of the newly placed NPN symbol instance Press lt Ctrl gt RightMouseButton A dialog box will appear Change Prefix QN to Prefix X This causes this instance of the symbol to netlist as a subcircuit instead of an intrinsic bipolar transistor 3 Edit the value NPN to be BFG135 to coincide with the name given on the SUBCKT line 4 Then either 4a Add the SUBCKT BFG135 lines to your schematic 193 Or 4b If you have a file Phil lib containing your SUBCKT BFG135 others may be too in this file then you have to add a SPICE directive INCLUDE Phil lib One aspect of adding a SUBCKT model to LTspice is that you need have the symbol used to call the subcircuit and the model agree on the same pin port netlist order The above examples assume the 3 party model you re adding follows popular pin order conventions Further related information is in the help sections Schematic Capture and LTspice The basic idea is that the schematic capture program generates a netlist that the simulator LTspice reads Any aspect of importing 3 party models can be resolved by und
77. as multiple instances in the same circuit Before the simulation runs the circuit is expanded to a flat netlist by replacing each invocation of a subcircuit with the circuit elements in the subcircuit definition There is no limit on the size or complexity of subcircuits The end of a subcircuit definition must be a ends directive Here is an example using a subcircuit This is the circuit definition ab 0 divider a 0 pulse 0 10 5p 5p 0 1p lt K ox x this is the definition of the subcircuit subckt divider nl n2 n3 95 ri nd n2 1k r2 n2 n3 1k ends tran 3p end Which runs after expanding to Expand X1 into two resistor network reed ca D Lk ridez ws O Tk vl a O0 pulse 01 0 5p 5n O 1p tran s Note that unique names based on the subcircuit name and the subcircuit definition element names are mad for the circuit elements inserted by subcircuit expansion TEMP Temperature Sweeps This is an archaic form for the step command for temperature It performs the simulation for each temperature listed The syntax TEMP T1 T2 is equivalent to STEP TEMP LIST T1 T2 TF Find the DC Small Signal Transfer Function 96 This is an analysis mode that finds the DC small signal transfer function of a node voltage or branch current due to small variations of an independent source Syntax TF V node
78. as the name of a net in the lower level schematic The Netlist Order determines the order this pin is netlisted for SPICE Adding Attributes 31 You can define default attributes for a symbol using the menu command Edit gt Attributes gt Edit Attributes The most important attribute is called the Prefix This determines the basic type of symbol If the symbol is intended to represent a SPICE primitive the symbol should have the appropriate prefix R for resistor C or capacitor M for MOSFET etc See the LTspice reference for a complete set of SPICE primitives available The prefix should be X if you want to use the symbol to represent a subcircuit defined in a library Symbol Attribute Editor Symbol Type Block This determines the type of a circuit element e g R C or L Prefix E MONIINNPQUNMNNNNINM SpiceModel Value Value SpiceLine SpiceLine2 Cancel The symbol s attributes can be overridden in the instance of the symbol as a component in a schematic For example if you have a symbol for a MOSFET with a prefix attribute of M it s possible to override the prefix to an X on an instance by instance basis so that the transistor can be modeled as subcircuit instead 32 There is a special combination of attributes that will cause a required library to be automatically included in every schematic that uses the symbol
79. at pair The output is linearly interpolated when the control voltage is between specified points If the control voltage is beyond the range of the look up table the output voltage is extrapola ted as a constant voltage of the last point of the look up table Syntax Exxx n n nc nc Laplace lt func s gt window lt time gt nfft lt number gt mtol lt number gt The transfer function of this circuit element is specified by its Laplace transform The Laplace transform must be a function of s The frequency response at frequency f is found by substituting s with sqrt 1 2 pi f The time domain behavior is found from the impulse response found from the Fourier transform of the frequency domain response LTspice must guess an appropriate frequency range and resolution The response must drop at high frequencies or an error is reported It is recommended that the LTspice first be allowed to make a guess at this and then check the accuracy my reducing reltol or explicitly setting nfft and the window The reciprocal of the value of the window is the frequency resolution The value of nfft times this resolution is the highest frequency considered The Boolean XOR operator is understood to mean exponentiation when used in a Laplace expression Syntax Exxx n n value lt expression gt This is an alternative syntax of the behavioral source arbitrary behavi
80. ations FAQs Installation Problems How do I install SwitcherCAD III 1 Go to http www linear com and download the file Swcadiii exe into a temporary directory on your PC 2 Run the swcadiii exe to install I m running a Chinese Edition of Windows The Greek Mu character doesn t show up correctly what can I do That problem should be completely fixed in the current version of LTspice SwCAD But you can go to the menu item Tools gt Control Panel Sette Options and check Convert y to u This option now not only applies to netlists but will draw a Greek Mu as u wherever it might appear on the screen Program Updates How do I get the latest version Once installed there are two ways to getting the latest version You can always reinstall the program again as mentioned in Installation Problems You don t have to 189 remove the old version before installing If your PC has an internet connection it is much easier to get the latest release by using the Sync Release feature How do I know what new features are added After you have updated your file to the latest version the changelog txt file in your root directory usually at c Program Files ltc swcadiii Changelog txt has a detailed program revision list Can I go back to the old version after Sync Release It is not reversible All symbols models and programs are updated with the n
81. ay be excited To simulate such a situation two transmission lin lements are required U Uniform RC line Symbol Names URC Syntax Uxxx N1 N2 Ncom model L lt len gt N lt lumps gt 166 N1 and N2 are the two element nodes the RC line connects whereas Ncom is the node to which the capacitances are connected MNAME is the model name and LEN is the length of the RC line in meters Lumps if specified is the number of lumped segments to use in modeling the RC line A guess at an appropriate number of lumps to use will be made if lumps is not specified The URC model is derived from a model proposed by L Gertzberrg in 1974 The model is accomplished by a subcircuit type expansion of the URC line into a network of lumped RC segments with internally generated nodes The RC segments are in a geometric progression increasing toward the middle of the URC line with K as a proportionality constant The URC line is made up strictly of resistor and capacitor segments unless the ISPERL parameter is given a nonzero value in which case the capacitors are replaced with reverse biased diodes with a zero bias junction capacitance equivalent to the capacitance replaced and with a saturation current of ISPERL amps per meter of transmission line and an optional series resistance equivalent to RSPERL ohms per meter Na Description Un Defa me it ult S K Propagation Constant Di
82. ckness Substrate doping Surface state density Fast surface state Type of gate material 1 opp to substrate same as substrate 0 Al gate Metallurgical junction depth Lateral diffusion 0 5 F m 0 50 33 A m 0 m le 7 1 c 0 m3 1 c 0 m2 1 c 0 m2 5 1 m 0 m 0 lp level iu Uo Ucr it Uex Utr Vma Nef Kf Af Del ta The ta Surface mobility Critical field for mobility degradation level 2 only Critical field exponent in mobility degradation level 2 only Transverse field coefficient level 2 only Maximum carrier drift velocity levels 2 amp 3 only Total channel charge exponent level 2 only Flicker noise coefficient Flicker noise exponent Coefficient for forward bias depletion capacitance formula Width effect on threshold voltage levels 2 and 3 Mobility modulation level 3 only cm 600 V S V c 1e4 m 0 Q0 m s 0 Hi 0 dies 0 5 0 7 oF 700 le4 5e4 26 143 Eta Static feedback 2 0 level 3 only Kap Saturation field 0 2 pa level 3 only Tno Parameter 2C 27 m measurement temperature VDMOS Rd Rb voy Body Rg Rs Diode The discrete vertical double diffused MOSFET transistor VDMOS popularly used in board level switch mode power supplies has beha
83. current averaged over a clock cycle diminishes to a small value for several cycles Then at a clock edge the energy stored in each reactance is noted and the simulation is run for another ten clock cycles but now integrating the dissipation in every device At the clock edge of the last cycle the energy stored in every reactance is noted again and the simulation is stopped The efficiency is reported as the ratio of output power delivered to the load by the 14 input power sourced by the input voltage after making an adjustment for the change in energy stored in the reactances Since the dissipation of each device was also noted it is possible to look how close the energy checksum is to zero You can usually compute efficiency of SMPS circuits you draft yourself by using checking the Stop simulating if steady state is detected on the Edit Simulation Command editor After the simulation use the menu command View gt Efficiency Report Automatic detection of steady state doesn t always work Sometimes the criteria for steady state detection is too strict and sometimes too lenient You then either adjust the option parameter sstol or simply interactively set th limits for the efficiency integration Command Line Switches The following table summarizes the command line switches understood by the LTspice executable scad3 exe Flag Description
84. cy cle Description Uni ts DC offset A Amplitude A Frequency Hz Delay sec Damping factor 1 s ec Phase of sine wave deg ree S Number of cycles Omit cyc for free running les pulse function For times less than Td or times after completing Ncycles have run the output current is given byloffset Iamp sin pi phi 180 Otherwise the current is given by Td pi phi 180 Ioffset t Iamp exp time Td Theta sin 2 pi Freq time 123 The damping factor Theta is the reciprocal of the decay time constant Syntax Ixxx n n EXP Il 2 Tdl Taul Td2 Tau2 Time dependent exponential current source Nam Description Un e it S I1 Initial value A I2 Pulsed value A Tdl Rise delay time se o Tau Rise time constant se ill c Td2 Fall delay time se G Tau Fall time constant se 2 Cc For times less than Tdl the output current is Il For times between Tdl and Td2 the current is given by 1 I2 1I1 1 exp time Td1 Tau1 For times after Td2 the current is given by 1 I2 I1 1 exp time Td1 Taul I1 12 1 exp time Td2 Tau2 124 Syntax Ixxx n n SFFM Ioff Iamp Fcar MDI Fsig Time dependent single frequency FM current source Nam Description Un e it S Iof DC offset A f lam Amplitude A p Fca Carrier frequency Hz MDI
85. dent current source circuit elements 119 Syntax Gxxx n n nc nc gain This circuit element asserts an output current between th nodes n and n that depends on the input voltage between nodes nct and nc This is a linearly dependent source specified solely by a constant gain ct cl Syntax Gxxx n n nc nc table value pair lt value pair gt nes Here a lookup table is used to specify the transfer function The table is a list of pairs of numbers The second value of the pair is the output current when the control voltage is equal to the first value of that pair The output is linearly interpolated when the control voltage is between specified points If the control voltage is beyond the range of the look up table the output current is extrapolated as a constant current of the last point of the look up table Syntax Gxxx n n nc nc Laplace lt func s gt window lt time gt nfft lt number gt mtol lt number gt The transfer function of this circuit element is specified by its Laplace transform The Laplace transform must be a function of s The frequency response at frequency f is found by substituting s with sqrt 1 2 pi f The time domain behavior is found from the impulse response which is found from the Fourier transform of the frequency domain response LTspice must guess an appropriate frequency range and resolution
86. e have spent a great deal of effort in minimizing the memory requirement of this program While a typical simulation might generate 8Gigabytes of raw data that data will be compressed on the disk to 400Megabytes To view a single trace would require less than 65Megabytes of RAM Of course the more memory the better the performance will be Also SwitcherCAD benefits from the improved memory performance of Windows NT and later operating systems so you might consider upgrading operating system if you run out of memory Where is the waveform stored during simulation All the waveform data are stored on hard disk Only the plotted traces are loaded into RAM Turning off the marching waveforms can reduce the RAM memory requirement Note that for most analysis types there is no particular file size limit You can generate and view raw files that are very many Gigabytes in size What if I don t have enough disk space for long simulation The waveform data has been compressed but it is still proportional to the run time and the number of traces saved The easiest way to save memory is to select desired traces for storing before the simulation starts OK I ve done everything and I m still running out of memory What can I do During a transient analysis you can interactively throw away the past waveforms by pressing the 0 key That will retrig
87. eal part of the arc cosine of X e g acos 5 returns 3 14159 not 3 14159 2 29243i Synonym for acos Real part of the arc hyperbolic cosine of x e g acosh 5 returns 0 not 1 04721 Real part of the arc sine of x e g asin 5 returns 1 57080 not 1 57080 2 29243i Synonym for asin Arc hyperbolic sine Arc tangent of x Synonym for atan Four quadrant arc tangent of y x Arc hyperbolic tangent 89 buf x cbrt x ceil x COS X cosh x exp x fabs x flat x floor x gauss x hypot x y if x y z int x inv x limit x y z in x log x log10 x max x y mc x y min x y pow x y pwr x y l atx 25 else 0 Cube root of x Integer equal or greater than x Cosine of x Hyperbolic cosine of x e to the x Same as abs x Random number between x and x with uniform distribution Integer equal to or less than x Random number from Gaussian distribution with sigma of x sqrt x 2 4 y 2 If x 5 then y else z Convert x to integer 0 if x gt 5 else 1 Intermediate value of x y and Z Natural logarithm of x Alternate syntax for In Base 10 logarithm The greater of x or y A random number between x 1 y and x 1 y with uniform distribution The smaller of x or y Real part of x y e g pow 5 1 5 returns 0 not 0 353553 abs x
88. eeeeeeceaeeeeaaeeeeeeeeseaeeeeaaeeeeneeeaas 29 Symbol Editing Overview ssssssssseeeeeeeneen nenne 29 Drawing the body croisiere arani aaa a EN S a iaaii 30 Adding the Pins RC e epe dtu te p a Ede 31 Adding Attributes essseseeeeeeeenen nennen nenne 31 Attribute VISibIIItV sce ei Ern eere ete pleated 33 hierarchy a sium dt in tan than et De tee en ee deg 34 Hierarchy Oveni Waran ionta autetn e aeta kaa aaa nnne enne nene 34 Rules of Hierarchy iet e nee tene tee eee ardens 35 Navigating the Hierarchy 36 Waveform Viewer 38 Waveform Viewer Overview sssssssesssseeeeeeenenen enne enne nnne 38 Data Trace Selection docti pa ceteri tr ha citer nti de e ra ed eR nd Dr etr de ends 38 Paolo C LEER 43 Waveltorti Arthrmetlo s renane oaa ter pta PE Fn RI LS RRA PESE NY eH HIE TY SIE ESA 43 User Defined Functions enne enne 50 Vae ET 51 PIOE PAS 5 aer rite ace errores tuber UR BIA e eR ege eee Rs 51 Colon Go nliro REP ETE 52 Attached GUISOIS iiiee iia ete a sinn hath eni a hn eR aH RR AL EN RR RH AREE 53 Save Plot Configurations c cceccceeeeeeeeeeeeeeeeceeeeeceaeeesaaeeeeeeeseaeeeeaeeseeeeseas 57 Fast Access File Format esses 58 LTspice amp 59 Introd ction else need dicen rine re eie cedens 60 Circuit Descrip ON asinsradinieki ade ieee adie needs 60 General Structure and ConventiOns c ccceecceceeeeeeeeeeeeeeeessaeeeeneee
89. eeeees 61 Circuit Element Quick Reference cccccceceeceeeeeeeeeeneeseeeeeseaeeteaeeeenees 64 Dor Commands ioni tuenda cade E E E a NE a la ea anda du do dua 65 C Simulator Directives Dot Commands ssssssssssss 65 AC Perform an Small Signal AC Analysis Linearized About the DC Operating el CL E 66 BACKANNO Annotate the Subcircuit Pin Names to the Port Currents67 DC Perform a DC Source Sweep Analysis sssssssss 67 END End OF NetliSt s cauere eri cereo er tutt ene tage teu rnt 68 ENDS End of Subcircuit Definition sssssssees 68 FOUR Compute a Fourier Component after a TRAN Analysis 68 FUNC User Defined Functions eeeene 69 FERRET Download a File Given the URL sss 70 JC Set Initial Conditions ssssssseseeeeeeennnennnns 70 INCLUDE Include Another File 71 LIB Inelude a Elbraty ir teer tete rites 72 LOADBIAS Load a Previously Solved DC Solution 75 MEASURE Evaluate User Defined Electrical Quantities 75 MODEL Define a SPICE Model 80 NET Compute Network Parameters in a AC Analysis 81 NODESET Supply Hints for Initial DC Solution 82 NOISE Perform a Noise Analysis ssssseeeeene 82 OP Find the DC Operating Point
90. effect on Tf Excess phase at freq 1 Tf 2 PI Hz B C zero bias depletion capacitance B C built in potential B C junction exponential factor Infi Infi Rb 75 233 Infi wid 633 Xcjc Tr Xtb Eg Xti Kf Af Fc Tnom Cn Gamm Qco Quas imod Fraction of B C depletion capacitance connected to internal base node Ideal reverse transit time Zero bias collector substrate capacitance Substrate junction built in potential Substrate junction exponential factor Forward and reverse beta temperature exponent Energy gap for temperature effect on Is Temperature exponent for effect on Is Flicker noise coefficient Flicker nois xponent Coefficient for forward bias depletion capacitance formula Parameter measurement temperature Quasi saturation temperature coefficient for hole mobility Quasi saturation temperature coefficient for scattering limited hole carrier velocity Epitaxial region doping factor Epitaxial region charge factor Quasi saturation flag for temperature dependenc eV ue ul 27 2 42 NPN 2 2 PNP 97 NPN 52 PNP le 11 p not set 153 The m type sourc Berli Level for 1 VBIC Rco Epitaxial region resistance Q Vg Quasi saturation extrapolated V bandgap voltage at O K
91. ence problems are easier to avoid since they like the board level component the model have finite impedance at all frequencies Modern change switch mode power supplies include controller logic with multiple modes of operation from pulse switch modulation to burst For example devices may t mode or to cycle skipping depending on the circuit s operation An original new mixed mode compil ler and simula into SwitcherCAD that allows these prod realistically modeled in a computationally fast manner There are current Technology products modeled in Swi program is freely downloadable from th y approximately seven h tcherCAD tor were written ucts to be undred Linear The Linear Technology website and is a high performance general purpose SPICE simulator Included are demonstration files that allow you to watch step load response start up and transient behavior on a cycle by cycle basis SPICE is a full featured schematic entry program for entering new circuits Included with the SwitcherCAD is designed to be used by three different doing design will b types of design engineers those who think they know and they know absolutely nothing about that allows him find an optimum design approach that yields a rel simplest of inputs program that will those who know
92. engine is a benefit for simulating general analog circuits and should be of interest to all electronic engineers With over 500 000 copies distributed so far many users have reported that LTspice SwitcherCAD is their main simulation schematic capture tool We hope you enjoy the program and find it useful LOTEREES Technology LTspice SwitcherCAD III LT1613 app File Edit View Simulate Tools Window Help Aa PFU RLAR RS BS A BeA BS LLIF YD SC 300mA 240mA 180mA 120mA 60mA 0mA 80us 160us 240s 320us 400s 480us 560us 640s 720s 800ps Hardware Requirements LTspice SwitcherCAD runs on PC s running Windows 98 2000 NT4 0 Me or XP Since a simulation can generate many megabytes of data in a few minutes free hard disk space gt 200MB and large amount of RAM 128MB are highly recommended Basically the program can run on any PC with Windows 98 or above but the simulation may not finish if there is not enough hard disk space LTspice SwitcherCAD will also run on Linux The program has been tested on Linux RedHat 8 0 with WINE version 20030219 Software Installation SwitcherCAD can be downloaded from the LTC website http www linear com A direct link to the distributed file is http ltspice linear com software swcadiii exe The file swcadiii exe is a self extracting gziped file that installs SwitcherC
93. ent Source 119 G Voltage Dependent Current Source esee 119 H Current Dependent Voltage Source sssssssssss 121 I C trrent Source dece idee ces de He e Dv c eid Ha eva ete doa 121 Jy JFET transistor aiii ce dim te Ue i a e Ha Hee es 127 K Mutual Inductance ssssssseseeeeeeeerenee enne 129 Le riluctOt oi mee epp te epe 130 M MOSFET i ete aient orina p Ete teens 136 O Lossy Transmission Line essssssssseeeeeneeeennns 148 Q Bipolar transistor sse 150 Parameters i iet cepa tede e e Ta Rabe creeds 156 References ssssssssssesesesseeeeene enne entren nennen rst 163 Ra BSISIOE nei horrere Ee CORRI GRE RE Avie 163 S Voltage Controlled Switch sees 164 T Lossless Transmission Line eeeene 166 Uo Uniform RG linez iier ee cen me int nens 166 V Voltage Source ennt nnne ens 168 W Current Controlled Switch s sse 173 Xex SUDIC a c LEE 174 Z MESFET transistor sssssssssssssseeeenenneeeen nnne 174 Control Panel 176 Accessing the Control Panel sse enne 176 GomlpressSIOn x 50 0 Ince Cd e d reed dieere o reden eh 176 Operation anti cde ed i Ca e t onte eee Ae 178 Save Defaults x iC e teda e p vete pedcs 180 SPIGE 2 5 ttai taie o RE pred eU co uta dte eq ab ta 182 Netlist ODtions 2 2 2 2 noes capte
94. ent parallel devices of a specified model The JFET model is derived from the FET model of Shichman and Hodges extended to include Gate junction recombination current and impact ionization The DC characteristics are defined by the parameters VTO and BETA which determine the variation of drain current with gate voltage LAMBDA which determines the output conductance and Is the saturation current of the two gate junctions Two ohmic resistances Rd and Rs are included Charge storage is modeled by nonlinear depletion layer capacitances for both gate junctions which vary as the 1 2 power of junction voltage and are defined by the parameters Cgs Cgd and PB A fitting parameter B has been added See A E Parker and 127 D oJ Simulators Skellern An Improved FET Model for Computer IEEE Trans CAD vol 9 1990 Nam Vto Bet Lam bda Rd Rs Cgs Cgd Pb KF 128 Description Threshold voltage Transconductance parameter Channel length modulation parameter Drain ohmic resistance Source ohmic resistance Zero bias G S junction capacitance Zero bias G D junction capacitance Gate junction potential Gate junction saturation current Doping tail parameter Flicker noise coefficient 2 cux lt auteS5G cn S199 Def aul C le 14 May Exam ple le 3 le 4 100
95. equencies StartFreq and EndFreq The number of steps is defined with the keyword oct dec or lin and Nsteps according to the following table Key Nsteps wor d Oct No of steps per octave Dec No of steps per decade Lin Total number of linearly spaced steps between StartFreq and EndFr 66 BACKANNO Annotate the Subcircuit Pin Names to the Port Currents Syntax backanno This directive is automatically included in every netlist SwitcherCAD generates from a schematic It directs LTspice to include information in the raw file that can be used to refer to port currents by the pin name This allows you to plot the current into the pin of a symbol by mouse clicking on the symbol s pin DC Perform a DC Source Sweep Analysis This performs a DC analysis while sweeping the DC value of a source It is useful for computing the DC transfer function of an amplifier or plotting the characteristic curves of a transistor for model verification Syntax dc srcnam lt Vstart gt lt Vstop gt Vincr lt srcnam2 gt lt Vstart2 gt lt Vstop2 gt lt Vincr2 gt The lt srcnam gt is either an independent voltage or current source that is to be swept from lt Vstart gt to lt Vstop gt in lt Vincr gt step sizes In the following example the default BSIM3v3 2 4 characteristic curves are plotted Example dc sweep MI 2 1 0 0 nbsi
96. erstanding SPICE netlist syntax and how the schematic capture program generates that syntax There are also tutorials prepared on this topic archived at the independent users group at http groups yahoo com group LTspice Inductor Models How do I design a coupled inductor You first draw at least two inductors and then define the K coefficient between the two inductors See mutual inductance section How do I control the inductor parasitic resistance By default LTspice will supply losses to inductors to aid SMPS transient analysis For SMPS these losses are of usually of no consequence but may be turned off if desired On the Tools gt Control Panel gt Hacks page uncheck Supply a min inductor damping if no Rpar is 194 given This setting will be remembered between invocations of the program There is also a default series resistance of 1 milliOhm for inductors that aren t mentioned in a mutual inductance statement This Rser allows SwitcherCAD to integrate the inductance as a Norton equivalent circuit instead of Thevenin equivalent in order to reduce the size of the circuit s linearized matrix If you don t want LTspice to introduce this minimum resistance you must explicitly set Rser 0 for that inductor This will require LTspice to use the more cumbersome Thevenin equivalent of the inductor during transient analysis Can I add edit my own inductor model
97. es 2 Compute the average or RMS of a trace 43 3 Display the Fourier Transform of a Trace 1 Plot expressions of traces Both the View gt Visible Traces and View gt Add Trace commands allow one to enter an expression of data Another method to to plot an expression of available simulation data traces is to move the mouse to the trace s label and right click This dialog box also allows you to set the trace s color and allows you to attach a cursor to the waveform LTspice will do a dimensional analysis of the expression and plot it against a vertical axis labeled with those units All waveforms in a plotting pane with the same units are plotted on the same axis Fj Linear Technology LTspice SwitcherCAD Ill warning2 cir uw File View Plot Settings Simulation Tools Window Help As UP 46 QQQRQ EC SEs soem ass one Expression Editor x Trace Color EA Attached Cursor none M Enter an algebraic expression to plot Cancel 1 1 pow V 8 2 abs v 1 1 le 013 T Delete this trace 50ns 100ns 150ns 200ns 250ns Right Click to edit expression Control Left Click to integrate The difference of two voltages e g V a V b can equivalently written as V a b The following functions are available for real data Function Name Description abs x Absolute value of x 44 acos x arccos x acosh x asin x arcsin x asinh x atan x arctan x atan2 y x
98. esigns Don t save Ib Ie Is Ig This saves only the collector drain currents of transistors in the interest of reducing the size of the output data file This is useful for IC design but it using it means that there isn t enough data available to compute transistor dissipation 181 Save Device Currents Check this so that you can plot device and terminal currents You will also need it to be able to plot dissipation SPICE This pane allows you to define the various defaults for LTspice These defaults can be overridden in any simulation by specifying the options in that simulation Usually you can leave these options as they are If you have frequently updated the program over the web you might want to press Reset to Default Values to reset to the current recommended settings Control Panel One default you may want to change is Trtol Most commercial SPICE programs default this to 7 In LTspice this defaults to 1 so that simulations using the SMPS macromodels are less likely to show any simulation artifacts in their waveforms Trtol more affects the timestep strategy than directly affects the accuracy of the 182 simulation For transistor level simulations a value larger than 1 is usually a better overall solution You might find that you get a speed of 2x if you increase trtol with out adversely affecting simulation accuracy Your trtol is remembered between program invocations Howeve
99. esis tance n sic substrate tance itic base tance Transport saturation current Forward emission coefficient Reverse emission coefficient Fwd bias depletion Capacitance limit Extrinsic B E overlap Capacitance Zero b ias B E depletion capacitance B E built in potential B E junction grading coefficient B E capacitance Infin Infin C C 1e 16 C un 157 cb CO qc cj ep pc mc cj cp ms ib ei wb ne ib en ne ib 158 smoothing factor Extrinsic B C overlap capacitance Zero bias B C depletion capacitance Epi charge parameter B C extrinsic zero bias capacitance B C built in potential B C junction grading coefficient B C capacitance smoothing factor Zero bias S C capacitance S C junction built in potential S C junction grading coefficient S C capacitance smoothing factor Ideal B E saturation current Portion of IBEI from Vbei 1 WBE from Vbex Ideal B E emission coefficient Non ideal B E saturation current Non ideal B E emission coefficient Ideal B C saturation current C C 1e 18 1e 16 nc ib cn nc cl av c2 is WS nf ib ei ib en ib Gu nc ip ib cn nc np ve ve coefficient Non ideal B C saturation current Non ide
100. eter N sets the number of s devices A diode requires a model card to specify l devices eries its characteristics There are two types of diodes linear available One is a conduction region wis model that yields a computationally light representation of an idealized diode It linear regions of conduction on off and breakdown Forward conduction and reverse Ilimit revlIlimit tanh is used to fit weight has three reverse breakdown can non linear by specifying a current limit with the slope of the forward conduction to the limit current The parameters epsilon and revepsilon can be s pecified to smoothly switch between the off and conducting states A quadratic function is fit between the off and on state such that the diode s IV curve is co value and slope and the transition occurs voltage specified by the value of epsilon to forward conduction and revepsilon for t transition between off and reverse breakdo ntinuous in over a for the off he wn Below are the model parameters for this type of diode Name Description Ron Resistance in forward conduction Roff Resistance when off Vfwd Forward threshold voltage to enter conduction Vrev Reverse breakdown voltage Rrev Breakdown impedance Ilimit Forward current limit Revili Reverse current limit 114 U Def n aul i t t S Q T Q Ty Gmi n V 0 V Inf i
101. ew ones You need to make a backup copy before the Sync Release starts The component databases standard will be merged with the new ones automatically If you added new inductors or capacitors your devices will be preserved and merged with the new ones from program update Your own local working file won t be affected Transformer Models How do I build a transformer model The best way would be to draft a model with coupled inductors with a mutual inductance statement placed as a SPICE directive on the schematic See the section in mutual Inductance for more information Inductors participating in a mutual inductance will be drawn with a phasing dot The following example demonstrates a transformer with 1 3 turns ratio one to nine inductance ratio with a sine wave input and simulates for 0 1lms The K is set to 1 to model a transformer with no leakage inductance 190 ORTEN Technology SwitcherCAD III xformer asc i ml x File Edit View Simulate Tools Window Help amp xJ Ea m aeae sla Ses seja eel e in K1 L1 L2 1 Ew L2 R4 s 900pH 100K sine 0 1 100K tran 0 1ms Third party Models This section explains the basics to adding a third party model to LTspice SwitcherCAD Basically there are two types of third party SPICE models those described with a MODEL statement and those defined with a SUBCKT Models given as
102. f It is possible to specify voltage dissipation ratings for a model not affect check if 116 the diode t the electrical behavior is being used beyond it S fs 7 8 9 C eC jn 2 0 Sbd 0 1 05 5 Inf 40 Ts le 10 21 50 0 2 Inf in C current and power These model They all parameters do low LTspice to ts rated capability The following parameters apply to either model These parameters do not scale with area Na Description Un me it S Vp Peak voltage rating V k Ip Peak current rating A k Ia Ave current rating A ve Ix RMS current rating A ms di Maximum power dissipation W SS rating E Voltage Dependent Voltage Source Symbol Names E E2 There are thr types of voltage dependent voltage Source circuit elements Syntax Exxx n n n t nc gain This circuit element asserts an output voltage between th nodes n and n that depends on the input voltage between nodes nc and nc This is a linearly dependent source specified solely by a constant gain Gt ct Syntax Exxx n n nc nc table lt value pair lt value pair 117 A look up table is used to specify the transfer function The table is a list of pairs of numbers The second value of the pair is the output voltage when the control voltage is equal to the first value of th
103. f aul Val Description 83 Abstol baudrate chgtol cshunt cshuntint ern defad defas defl defw delay fastacces S flagloads Gmin 84 El ag El ag ue 1pA no ne 10f csh unt 100 100 fal se fal se le 12 Absolute current errortolerance Used for eye diagrams Tells the waveform viewer how to wrap the abscissa time to overlay the bit transitions Absolute charge tolerance Optional capacitance added from every node to ground Optional capacitance added from every device internal node to ground Default MOS drain diffusion area Default MOS source diffusion area Default MOS channel length Default MOS channel width Used for eye diagrams Shifts the bit transitions in the diagram Convert to fastaccess file format at end of simulation Flags external current Sources as loads Conductance added to every PN junction to aid convergence gminsteps gshunt itl6 srcsteps maxclocks maxstep meascplxf mt measdgt method minclocks Nu st ri ng 25 100 25 25 Inf in Inf in bod tra 10 Set to zero to prevent gminstepping for the initial DC solution Optional conductance added from every node to ground DC iteration count limit DC transfer
104. f the switch s conduction There is also a level 2 voltage controlled switch which is an advanced version of the level 1 switch with negative hysteresis The level 2 switch is never completely on or off The conduction as a function of control voltage Vc is g Vc exp A atn Vc Vt Vh B where A pi log 1 Ron log 1 Roff B log 1 Ron log 1 Roff 165 Also the transition of the level 2 switch to current limit is gradual instead of abrupt At a fixed control voltage the I V curve is giving by the equation I V Ilimit tanh g Vc V The level 2 switch supports the option to conduct in only one direction by either specifying the flag oneway or Specifying a voltage drop with parameter Vser The transition between forward conduction and reverse open circuit can be specified to be a smooth transition by Specifying the parameter epsilon to be non zero T Lossless Transmission Line Symbol Name TLINE Syntax Txxx L L R R Zo lt value gt Td lt value gt L and L are the nodes at one port R and R are the nodes for the other port Zo is the characteristic impedance The length of the line is given by the propagation delay Td This element models only one propagation mode If all four nodes are distinct in the actual circuit then two modes m
105. fall Ton Un it se se se se se cy cl es Theta Phi 169 Time dependent sine wave voltage source Nam e Vof fse Vam Fre Td The ta Phi Ncy cle Description Uni ts DC offset V Amplitude V Frequency Hz Delay sec Damping factor 178 ec Phase of sine wave deg ree S Number of cycles Omit cyc for free running les pulse function For times less than Td or times after completing Ncycles have run the output voltage is given by Voffset Vamp sin pi Phi 180 Otherwise the voltage is given by Voffsett Vamp exp tim Td Theta sin 2 pi Freg time Td pi Phi 180 The damping factor Theta is the reciprocal of the decay time constant Syntax VXXX nt 170 n EXP V1 V2 Tdl Taul Td2 Tau2 Time dependent exponential voltage source Nam Description Un e it S V1 Initial value V V2 Pulsed value V Tal Rise delay time se Tau Rise time constant se 1 Cc Td2 Fall delay time se e Tau Fall time constant se 2 Cc For times less than Tdl the output voltage is Vl For times between Tdl and Td2 the voltage is given by V1 V2 V1 1 exp time Td1 Taul For times after Td2 the voltage is given by V1 V2 V1 1 exp time Td1 Taul V1 V2 1 exp time Td2 Tau2 Syntax Vxxx n n SFFM Voff Vamp Fcar MDI Fsig Time dependent single frequency FM voltage sou
106. ge is not driven negative The gate drain capacitance follows the following empirically found form Cgdmax C atan a Ved D A tanh a Ved B uM Cgdmin Vod o For positive Vgd Cgd varies as the hyperbolic tangent of Vgd For negative Vdg Cgd varies as the arc tangent of Vgd The model parameters a Cgdmax and Cgdmax parameterize the gate drain capacitance The source drain capacitance is supplied by the graded capacitance of a body diode connected across the source drain electrodes outside of the source and drain resistances Name Description U Def Exa n aul mpl i t e t S Vto Threshold voltage V 0 1 0 Kp Transconductance A La is 145 Phi Lamb da Rd Rs Rg Rds Rb C jo Cgs Cgam in Cgam Vj 146 parameter Surface inversion potential Channel length modulation Drain ohmic resistance Source ohmic resistance Gate ohmic resistance Drain source shunt resistance Body diode ohmic resistance Zero bias body diode junction capacitance Gate source capacitance Minimum non linear G D capacitance Maximum non linear G D capacitance Non linear Cgd capacitance parameter Body diode saturation current Bulk diode emission coefficient Body diode C Inf in C C le 10M eg in C C le 15 Ec Lt Eg Xti Kf Af ncha n pcha
107. ger the simulation time to t 0 as the present time 200 Model Compatibility Are the switching regulator models compatible with PSpice models and others The LTspice SMPS macromodels are implemented in a combination of new proprietary native LTspice devices and or a proprietary hardware description language While it is possible in principle to develop generic SPICE or PSpice macromodels the resultant simulation speed would not be viable LTspice can however run PSpice semiconductor and behavioral models and is generally a much higher performance simulator so you might move your Pspice simulations to LTspice Many users upgrade from PSpice to LTspice SPICE Netlist How do I create a SPICE netlist A netlist can be created with any text editor capable of generating an ASC file You can view the SPICE netlist of any schematic in SwitcherCAD with the command View gt SPICE netlist From this view you can copy the netlist to the clipboard by selecting all text and typing Ctrl C to bring the netlist to a different editor How do I run a netlist Just open the text file first and then run it LTspice SwitcherCAD will recognize the file as a netlist if it has file extension of cir Exporting Merging Waveform Data Can I export the waveform data to other applications 201 You can copy a plot as bitmap by making a waveform windo
108. he This will be labeled res5 MEAS TRAN res6 PARAM 3 resl res2 Print the value of 3 re printing expressions of It s not intended that simulation data such a expression to be evalua taken from the last sim labeled rese sl res2 This form is useful for other meas statement results expressions based on direct s V 3 are present in the ted but if they are the data is ulated point The result will be Note that the above examples while referring to one point along the abscissa the requested result is based on ordinate data the dependent variables If no ordinate information is requested point on the abscissa that occurs then the MEAS statement prints the measurement condition MEAS TRAN res6 WHEN V x 3 V y Print the first time th This will be labeled r e condition V x 3 V y is met s6 The other type of MEAS statement refers to a range over the abscissa The following syntax is used Syntax MEAS AC DC OP TRAN TF NOISE lt name gt 2n lt AVG MAX MIN PP RMS INTEG gt lt expr gt TRIG lt lhsl gt VAL lt rhsl gt TD 2 vall TARG lt lhs2 gt gt lt RISE FALL CROSS gt lt count1 gt gt gt 2 lt RISE FALL CROSS gt lt count2 VAL lt rhs2 gt TD lt val 77 The range over the abscissa is specified with the points defined by T
109. here are no objected sprited Mirror Mirror the sprited objects Note this is greyed out when there are no objected sprited Draw Wire Click the left mouse button to start a wire Each mouse click will define a new wire segment Click on an exis existing one Right draw wires through con wire t click again to quit this command nponents such as resistors ting wire segment to join the new wire with an Right click once to cancel the current You can The wire will automatically be cut such that the resistor is now in series wi 18 th the wire Label Net Specify the name of a node so an arbitrary one isn t generated by the netlister for this node Place GND Place a GROUND symbol This is node 0 the global circuit common Delete Delete objects by clicking on them or dragging a box around them Duplicate Duplicate objects by clicking on them or dragging a box around them You can copy from one schematic to another if they are both opened in the same invocation of LTspice SwitcherCAD Start the Duplicate command in the window of the first schematic Then make the second schematic the active window and type Ctrl V Move Click on or drag a box around the objects you wish to move Then you can move those objects to a new location Paste It is enabled in a new schematic window when objects were already selected with the Duplica
110. his manner you can cross probe the nodes and current in the block Note that you should have the options Save Subcircuit Node Voltages and Save Subcircuit Device Currents checked on the Save Defaults Pane of the Control Panel Also if you ve highlighted a node on the top level schematic that node will be also highlighted in the lower level block 2 NEN top 100K bot 20K Note that is dialog also allows you to enter parameters to pass to this instance of the circuitry in preamp asc 37 Waveform Viewer Waveform Viewer Overview SwitcherCAD includes an integrated waveform viewer that allows complete control over the manner the simulation data is plotted Data Trace Selection There are thr basic means of selecting plotted traces 1 Probing directly from the schematic 2 Menu command Plot Settings gt Visible Traces 3 Menu command Plot Settings gt Add Trace The undo and redo commands allow you to review the different trace selections plotted no matter which method of selection is used T Probing directly from the schematic Th asiest method is to simply probe the schematic You simply point and click at a wire to plot the voltage on that wire You plot the current through any component with two connections like a resistor capacitor or an inductor by clicking on the body of the component This works at any level of the circ
111. ined for node COM but this node has no special significance That is it s not the SPICE global common and it s not even a global node It s just sometimes convenient to have a graphical symbol associated with a node distinct from ground If you give a node a name starting with the characters SG as in for example G VDD then that node is global no matter where the name occurs in the circuit hierarchy Fi C GND global node 0 E C COM fec fout Port Type None Port type is only visible if drawn at the end of a wire Cancel It is possible to indicate that a node is a port of type input output or bi directional These port types will be drawn differently but have no significance to the 20 netlister Indicating a port type can make circuit more readable Global nodes are also drawn differently in that a box is drawn around the name NONE Cour C BR Schematic Colors The menu command Tools gt Color Preferences colors allows you to set the colors used in displaying the schematics You click on an object in the sample schematic and use the red green and blue sliders to adjust the colors to your preferences 21 Color Palette Editor x l waveFom X Schematic B Netlist Selected ltem Wires Cw m Selected Item Color Mix x ance Re o Geen k Apply Blue J 255 Defaults Note Non elect
112. interes used in the ac directive Output data trace V onoise density referenced to the voltage source then data referred noise voltage den as a current source then Ihe parameters oct t and resolution in the manner is the noise spectral voltage node s specified as the output in the above syntax If the input signal is given as a noise referred to the inpu noise contribution of each component trace V inoise is the input Sity If the input is specified the data trace inoise is the t current source signal The can be plotted These contributions are referenced to the output You can t by dividing by the data trace reference them to the inpu gain n The waveform viewer can in Ctrl Key left mouse bu corresponding data trace 1 OP Find the DC Operating abel Point tegrate noise over a bandwidth by tton clicking on the Perform a DC solution with capacitances open circuited and d Usually a DC solution is performed as part of another analysis in order to find the inductances short circuite Operating point of the cir this operating point to be in a dialog box After a status bar cuit Use op if you wish only found The results will appear OP simulation when you point at a node or current the OP solution will appear on the OPTIONS Set Simulator Options Keyword Da ta Ty pe De
113. is encrypted file has been supplied by a 3rd party vendor that does not wish to publicize the technology used to implement this library Permission is granted to use this file for simulations but not to revers ngineer its contents Copyright O 2005 Acme SPICE Modeling For additional information see www acmespicemodels com Begin 50 3E 46 OF FA 6E 67 FF B8 4D D9 62 14 32 60 24 36 71 35 OB 66 4F AD 52 B8 F5 9E 22 9F CO 18 8B FB FE 1D LOADBIAS Load a Previously Solved DC Solution Syntax loadbias filename The loadbias command is the compliment to the savebias command First run a simulation that executes a savebias command Then change the savebias command to a loadbias command MEASURE Evaluate User Defined Electrical Quantities 75 There are two basic different types of MEASURE statements Those that refer to a point along the abscissa the independent variable plotted along the horizontal axis i e the time axis of a tran analysis and MEASURE statements that refer to a range over the abscissa The first version those that point to one point on the abscissa are used to print a data value or expression thereof at a specific point or when a condition is met The following syntax is used Syntax MEAS SURE AC DC OP TRAN TF NOISE lt name gt lt FIND DERIV PARAM gt
114. le to position it as you wish with respect to the symbol 33 lAttribute Window to Add x InstName Type SpiceModel SpiceLine SpiceLine2 You can modify the text justification and contents of attributes that you ve already made visible by right mouse clicking on the text of the attribute Symbol Attribute Hierarchy Hierarchy Overview 34 Hierarchical schematic drafting has powerful advantages Much larger circuits can be drafted than sheet schematic while retaining the clari schematics Repeated circuitry to be eas abstract manner Blocks of circuitry can latter use in a different project Rules of Hierarchy can fit onto a one ty of the smaller ily handled in an be libraried for The way to refer to another schematic as a block in a higher level schematic is to create a symbol with the same name as the block schematic and then by placing that symbol on the higher level schematic top level schematic called topXY For examp Z asc and le if you have a another schematic file called preamp asc that you wish to place in the schematic of topXYZ then create a symbol called preamp asy and place an instance of that symbol on the schematic of topXYZ The electrical connecti is established by connecting wires of the higher level vity betw schematic to pins on the lo
115. look up table given as a set of pairs of points Tangent of x Hyperbolic tangent of x Unit step i e lif x gt 0 else 0 x if x gt 0 else O Random number between 5 and 5 smoothly transitions between values even more smoothly than random and table are not available The functions Re x and Im x are available for complex data and return a complex number with the real part equal to the real or imaginary part of the argument respectively and the imaginary part equal to zero The functions Ph x and Mag x are also available for complex data and return a complex number with the real part equal to the phase angle or magnitude of the argument respectively and the imaginary part equal to zero The function conj x is also available for complex data and returns the complex conjugate of x The following operations grouped in reverse order of precedence of evaluation are available for real data Ope Description ran d amp Convert the expressions to either side to Boolean then AND Convert the expressions to either side to Boolean then OR Convert the expressions to either side to Boolean then XOR gt TRUE if expression on the left is greater than the expression on the right otherwise FALSE lt TRUE if expression on the left is less than the expression on the right otherwi
116. ls may be too in this directive INCLUDE must be the con on your schematic Note that nplete name with any that Windows Explorer fil xtension So led bipol lib txt found You can alternatively add the statement to the fil C Program notepad and Windows bripol sub lude this file is inc inc bipol sub you that file can t be MODEL BC547C le typically installed as Files LTC SwCAD lib cmp standard bjt If you do that you will automatically s the model as a choice was editing the NPN transistor If you edi you will have to restart tha the file has changed this standard bjt file outside of LTspice LTspice for it to notice Example for a 5 pin opamp This will be defined with a SUBCKT statement 1 Add an instance of symbol opamp2 to your schematic 2 Edit the value opamp2 to TLO72 on the schematic to coincide with the name of the SUBCKT 3 Either 3a Paste the SUBCKT TLO72 ENDS definition as one multi line SPICE directive to your schematic Or 3b If you have a file called TI lib containing the definition of subcircuit TLO72 It will look like a line that starts out as SUBCKT TLO72 add the SPICE directive INCLUDE TI lib to the schematic It is possible to create a new symbol
117. m Vgs 1 0 3 5 Vds 2 0 3 5 sde Vids 3 5 0 0 05 Wgs 0 3 5 0 5 model nbsim NMOS Level 8 save I Vds end 67 END End of Netlist This directive marks the end of the textual netlist All lines after this one are ignored Do not place this as text on the schematic as the netlist extractor supplies it at the end ENDS End of Subcircuit Definition This directive marks the end of a subcircuit definition See SUBCKT for more information FOUR Compute a Fourier Component after a TRAN Analysis Syntax four frequency Nharmonics Nperiods data tracel data trace2 Example four lkHz V out This command is performed after a transient analysis It s supplied in order to be compatible with legacy SPICE simulators The output from this command is printed in the log file Use the menu item View gt Spice Error Log to see the output For most purposes the FFT capability built into the waveform viewer is more useful If the integer Nharmonics is present then the analysis includes that number of harmonics The number of harmonics defaults to 9 if not specified The Fourier analysis is performed over the period from the final time Tend to one period before Tend unless an integer Nperiods is given after Nharmonics If Nperiods is given as 1 the Fourier analysis is performed over the entire simulation data range 68 FUNC User Defined Functions
118. meters N Description Units a m e H Coercive force Amp c turns meter B Remnant flux density Tesla r B Saturation flux density Tesla S The upper and lower branches of the hysteresis major loop are given by H Hc Bup H Bs t ppo H H He He Bs Br 1 and H He Bdn H Bs pO H H Hc He Bs Br 1 133 These functions are plotted in following figure Hc and Br are the intersections of the major hysteresis loop with the H and B axes Bs is the B axis intersection of the asymptotic line Bsat H Bs 0 H approached as H goes to infinity Bs Br 5 The initial magnetization curve is given by Bmag H 5 Bup H Bdn H Minor loops are obtained by various translations of the above equations per the cited reference The core s absolute and differential permeabilities are a function of H and the history of values of H The plot below shows the path taken by an asymmetrical minor loop for a typical power ferrite Hc 16 A turns m Bs 44T Br 10T 134 major asymmetric minor loop loop e initial magnetization In addition to the core property parameters Hc Br and Bs mechanical dimensions of the core are required Na Description Units me Lm Magnetic Length excl meter gap Lg Length of gap meter A Cross sectional area meter 2 N Number of turns
119. n je E of of of of for fwd and exponent of re ergy for voltage Delta activation energy emission Temperature coefficient of NBBE C C 1e 06 eb exp VBBE NBBE Vtv be dt Locale Temperature em difference p ve Revision Version rs VI Reference Version ef References C C McAndrew et al Vertical Bipolar Inter Company 1995 An Improved Vertical IC Bipolar Transistor Model Proceedings of the IEEE Bipolar Circuits and Technology Meeting pp 170 177 1995 C C McAndrew et al VBIC95 The Vertical Bipolar Inter Company Model IEEE Journal of Solid State Circuits vol 31 No 10 October 1996 C C McAndrew VBIC Model Definition Release 1 2 18 Sep 1999 R Resistor Symbol Names Syntax The resistor supplies a simpl between nodes nl and n2 RES RES2 Rxxx nl n2 value tc tcl temp lt value gt EGZAS c n linear resistance A tempera Cur dependence can be defined for each resistor instance with the parameter tc The resistance R R RO Cla RUE Ue gelb Poder gz CN a tc2 t will be JsdE NS 9 ees 163 where RO is the resistance at the nominal temperature and dt is the difference between the resistor s temperature and the nominal temperature S Voltage Controlled Switch Symbol Names SW Syntax Sxxx nl n2 nct nc model on off
120. n Q Ron A nf in A Inf mit Epsilo n Reveps ilon Width of quadratic region Width of reverse quad region This idealized model is used if any of Ron Vrev or Rrev is specified in the model The other model available is the standard Berkeley SPICE semiconductor diode but extended to handl breakdown behavior and recombination current factor determines th of a specified model for this diode Na me Rs TU Eg Description saturation current Ohmic resistance Emission coefficient Transit time Zero bias junction cap Junction potential Grading coefficient Activation energy number of equivalent parallel Below are the diode model par in V 0 V 0 Roff Vfwd more detailed The area devices ameters Un Def Exam it aul ple s t A le le 7 14 Q Oi 104 1 Ts se 0 2n Cc F 0 2p V ltd 6 0 5 045 eV 1 1 1 11 1 Si 0 69 Sbd 0 67 Ge 115 Xt Kf Af Fc BV Tn om Ti kf Tr sl de s2 Sat current temp exp Flicker noise coeff Flicker noise exponent Coeff for forward bias depletion capacitance formula Reverse breakdown voltage Current at breakdown voltage Parameter measurement temp Recombination current parameter Isr emission coeff High injection knee current Linear Ikf temp coeff linear Rs temp coeff Quadratic Rs temp coef
121. n a Laplace expression The frequency response at frequency f is found by substituting S with sqrt 1 2 pi f The time domain behavior is found from the sum of the instantaneous current or voltage with the convolution of the history of this current or voltage with the impulse response Numerical inversion of a Laplace transfer function to the time domain impulse response is a potentially compute bound process and a topic of current numerical research In LTspice the impulse response is found from the FFT of a discreet set points in frequency domain response This process is prone to the usual artifacts of FFT s such as spectral leakage and picket fencing that is common to discreet FFT s LTspice uses a proprietary algorithm that exploits that it has an exact analytical expression for the frequency domain response and chooses points and windows to cause such artifacts to diffract precisely to zero However LTspice must guess an appropriate frequency range and resolution It is recommended that the LTspice first be allowed to make a guess at this The length of the window and number of FFT data points used will be reported in the log file You can then adjust the algorithm s choices by explicitly setting nfft and window length The reciprocal of the value of the window is the frequency resolution The value of nfft times this resolution is the highest frequency considered Note that the convolution of the impulse
122. n use the plot settings file from another simulation of the same analysis type Fast Access File Format During simulation LTspice usually uses a compressed binary file format that allows additional simulation data to be appended without modifying the rest of the file But once the simulation is completed this file format can be slow to access for the purposes of adding a single new plot trace from the file To reduce this time you can convert the file to an alternative Fast Access format This format can only be done after the simulation is completed when no new data will be added to the file But once the file is converted to this format the load time of a new traces will be reduced typically by a factor equal to the number of data traces that have been saved in the file For example if you have a 5GB file with 2000 data traces it might take 4min to add a new trace But after you convert it to Fast Access format this four minute load time would be reduced to a single second This makes cross probing large circuits with huge simulation data files interactive The exact time it takes to load a trace from a Fast Access format file will depend more on the amount of physical memory you have than your hard disk speed To convert a waveform window to Fast Access format make the waveform window the active window and execute menu command gt Files gt Convert to Fast Acce
123. nalysis correspond to the network being terminated in the same manner as in the NET statement NODESET Supply Hints for Initial DC Solution The nodeset directive supplies hints for finding the DC operating point If a circuit has multiple possible DC states as for example a flipflop the iteration process for finding the DC solution may never converge A nodeset directive can be used to lead the circuit to one or another state Basically after a solution pass is done with the voltage Specified on the nodeset directive the constraint is removed for subsequent iterative passes Syntax NODESET V nodel voltage V node2 voltage espe NOISE Perform a Noise Analysis This is a frequency domain analysis that computes the noise due to Johnson shot and flicker noise The output data is noise spectral density per unit square root bandwidth Syntax noise V lt out gt lt ref gt src oct dec lin Nsteps lt StartFreq gt lt EndFreq gt 82 V lt out gt lt ref gt is the node a noise is calculated It can be represent the voltage between t which the total output expressed as V nl n2 to two nodes src is the name of an independent source to which input noise is referred src is the noiseless input signal dec lin lt Nsteps gt lt StartFreq gt and EndFreq define th frequency range of
124. ne of x asin 5 is 1 57080 not 1 57080 42 29243i Synonym for asin Arc hyperbolic sine Arc tangent of x Synonym for atan Four quadrant arc tangent of y x Arc hyperbolic tangent if x gt 5 else 0 Integer equal or greater than x Cosine of x cosh x ddt x delay x t tmax exp x floor x hypot x y idt x ic all idtmod x ic m o qw if x y z int x inv x limit x y z in x log x log10 x max x y min x y pow x y pwr x y pwrs x y rand x random x Hyperbolic cosine of x Time derivative of x Same as absdelay e to the x Integer equal to or less than x sqrt x 2 4 y 2 Integrate x optional initial condition ic reset if a is true Integrate x optional initial condition ic reset on reaching modulus m offset output by o If x 5 then y else z Convert x to integer 0 if x gt 5 else 1 Intermediate value of x y and Natural logarithm of x Alternate syntax for In Base 10 logarithm Ihe greater of x or y Ihe smaller of x or y Real part of x y e g pow l5 5 05 not T abs x y sgn x abs x y Random number between 0 and 1 depending on the integer value Of X Similar to rand but smoothly transitions between values 107 round x sdt x ic assert sgn x Sin x sinh x sqrt x table x a b c d
125. new intrinsic SPICE devices for macromodeling Switch Mode Power Supply SMPS controllers and regulators The program includes an integrated hierarchical schematic capture program that allows users to edit example SMPS circuits or design new circuits An integrated waveform viewer displays the simulated waveforms and allows further analysis of the simulation data There is a built in database for most of Linear Technology s power ICs and many passive components The device database schematic editing simulation control and waveform analysis are integrated into one program Due to the mixed mode simulation capability and many other enhancements over previous SPICE programs the simulation speed is greatly improved while simulation accuracy is retained Detailed cycle by cycle SMPS simulations can be performed and analyzed in minutes A user can get a detailed analysis of power systems with a few mouse clicks without knowing anything about the device SPICE or the schematic capture program Pre drafted demo circuits can be used as a starting point to build the custom circuit to fit different power supply requirements After the new schematic is created the system can be simulated and a report generated The program s integrated hierarchical schematic capture and SPICE simulator are completely available for general use The improved performance of the SPICE simulation
126. ng point e lefi 5 rel ting point ting point ting point hand side only real part turns zero addition subtraction multiplication division to power of right hand is returned e g not 2 828431 SAVE Limit the Quantity of Saved Data Some simul generate restricted by using specific node voltages and device current Syntax 92 lations large amount particularly time domain simulations can of data The amount of output can be save V out the Sav V in directiv I L1 to save only the of interest I1 S2 1 dialogbox The directive save I Q2 will save the base collector and emitter currents of bipolar transistor Q2 To save a single terminal current specify Ic Q2 The wildcard characters and can be used to specify data traces matching a pattern For example save V Id will save every voltage and every drain current If the keyword dialogbox is specified then a dialog box with a list of all available default nodes and currents is displayed allowing the user to select from the list which should be saved If the netlist was generated from a schematic then nodes and devices can be pointed to and clicked on in the schematic to highlight them as selected in the dialog box SAVEBIAS Save Operating Point to Disk Syntax savebias filename
127. ng subcircuits so that abstract circuits can be saved in libraries The param statement can be included inside a subcircuit definition to limit the scope the parameter value to that subcircuit and subcircuits invoked by that subcircuit To invoke parameter substitution and expression evaluation enclose th xpression in curly braces The enclosed expression will be replaced with the floating point value Below is a example using both a param statement and directly passing parameters on the subcircuit invocation line This is the circuit definition params x y y z z lk tan pi 4 1 Xl a b 0 divider top x bot z Vl a O0 pulse 01 0 5n 5n 0 1p this is the definition of the subcircuit Subckt divider nl n2 n3 rI ni n2 top r2 n2 n3 bot 88 ends tran 3y end The parameter substitution scheme is a symbolic declarative language Ihe parameters are not passed to the subcircuit as evaluated values but by the expressions and relations themselves When curly braces are encountered the enclosed expression is evaluated on the basis of all relations available at the scope and reduced to a floating point value The following functions and operantoins are availible Function Name abs x acos x arccos x acosh x asin x arcsin x asinh x atan x arctan x a tan2 y tanh x x Description Absolute value of x R
128. no effect on the simulation example deck ferret http ltspice linear com software scad3 pdf end GLOBAL Declare Global Nodes Syntax global lt nodel gt node2 node3 Example global VDD VCC The global command allows you to declare that certain nodes mentioned in subcircuits are not local to subcircuit but are absolute global nodes Note that global circuit common is node 0 and that a global statement is not required Also node names that of the form SG are also global nodes without being mentioned in a global statement IC Set Initial Conditions The ic directive allows initial conditions for transient analysis to be specified Node voltages and inductor currents may be specified A DC solution is performed using the initial conditions as constraints Note that although inductors are normally treated as short circuits in the DC solution in other SPICE programs if an initial current is specified they are 70 treated as infinite impedance current sources in LTspice Syntax ic V n1 2 voltage I lt inductor gt lt current gt Example ic V in 2 V out 5 V vc 1 8 I L1 2300m INCLUDE Include Another File Syntax include filename This directive includes the named file as if that file had been typed into the netlist instead of the include command This is useful for including libraries of m
129. ny kind and Linear Technology Corporation expressly disclaims al express or implied including but o1 not implied warranties of merchantability particular purpose Under no circumsi her warranties limited to the and fitness for a ances will LTC be liable for damages either direct or consequential aris from the use of this product or from the possibility of such damages the inability to us this product even if we have been informed in advance of Redistribution of this software is permitted as long as is distributed in its entirety with all documentation example files symbols and models without modification additions This program is specifically not licensed for use by semiconductor manufacturers in the promotion demonstrat or sale of their products Specific permission must be obtained from Linear Technology for the use of SwitcherCAD for these applications IS ing e T Ore ion Mode of Operation Overview SwitcherCAD simulator foreign net capture tool Cir LTspice SwitcherCAD purpose schema simulator example circui Operation in the simul iterating the circ achieved le gt New Feed the simulator with a handcrafted ne list generated with a different schematic Menu command File gt Open file type and File gt Open file is intended
130. o zero while NRD and NRS to one OFF indicates an initial condition on the device for DC analysis The initial condition specification using IC VDS VGS VBS is for use with the UIC option 137 on the TRAN control line when a transient analysis is desired starting from other than the quiescent Operating point The optional TEMP value is the temperature at which this device is to operate and overrides the temperature specification on the OPTION control line The temperature specification is ONLY valid for level 1 2 3 and 6 MOSFETs not for level 4 5 or 8 BSIM devices LTspice contains seven different types of monolithic MOSFET s and one type of vertical double diffused Power MOSFET There are seven monolithic MOSFET device models The model parameter LEVEL specifies the model to be used The default level is one level model 1 Shichman Hodges 2 MOS2 see A Vladimirescu and S Liu The Simulation of MOS Integrated Circuits Using SPICE2 ERL Memo No M80 7 Electronics Research Laboratory University of California Berkeley October 1980 3 MOS3 a semi empirical model s reference for level 2 4 BSIM see B J Sheu D L Scharfetter and P K Ko SPICE2 Implementation of BSIM ERL Memo No ERL M85 42 Electronics Research Laboratory University of California Berkeley May 1985 138
131. oading the file each time you run the simulation you can edit the lib statement to lib library mod Note that if the url you specify doesn t exist most web Servers don t return an error but return a html web page to be displayed in your web browser that explains the error LTspice can t always read these pages as error conditions so you may get some cryptic error message when the simulation tries to proceed with the included html language error page included in the simulation as valid SPICE syntax If the http transferred url is a pdf file the simulation will abort after the download For example the following deck will download this manual as a pdf file 73 Dummy simulation to download the help file The simulation will abort with an error but you ll be left with the file scad3 pdf in the same directory containing the netlist lib http ltspice linear com software scad3 pdf end X Encrypted Libraries LTspice can generate and read a special form of encrypted libraries This allows one user to prepare a library that another user can use in a simulation without revealing the implementation of the library A reasonable attempt has been made to make the encrypted library difficult to decode by unauthorized concerns but it cannot be considered perfectly secure if for no other reason than it is implemented in software To
132. odels or subcircuits An absolute path name may be entered for the filename Otherwise LTspice looks first in the directory SwCAD gt lib sub and then in the directory that contains the calling netlist where lt SwCAD gt is the directory containing the scad3 exe executable typically installed as C Program Files LTC SwCAD No file nam xtension is assumed You must use inc myfile lib not inc myfile if the file is called myfile lib It is possible to specify a url of the following form as a file name inc http www company com models library lib The file library lib will be http transferred to the circuit directory and included For subsequence 71 simulations in the interest of avoiding downloading the file each time you run the simulation you can edit the inc statement to inc library lib Note that if the url you specify doesn t exist most web Servers don t return an error but return a html web page to be displayed in your web browser that explains the error LTspice can t always read these pages as error conditions so you may get some cryptic error message when the simulation tries to proceed with the included html language error page included in the simulation as valid SPICE syntax If the http transferred url is a pdf file the simulation will abort after the download For
133. ogy SwitcherCAD III full raw File View Window Help al T 131 1 ajajajaj lic el BT 1613 Step Step Response BCompressed File 10 c T1613 Step Response fal No Compression 2 4MB Eere Operation 178 Control Panel on Z Suspende 3 ee xI E Settings marked with an asterisk are remembered between program invocations Marching Waveforms Check to enable simulation results to be incrementally plotted during the simulation Generate Expanded Listing Dump the flat netlist after expanding subcircuits to the in the SPICE Error Log file Open Demo circuits as regular schematics Use to open demo circuits in SwCADIII lib app SPICE commands will be visible The schematic and saved to a new file The double dots circuit display control use Only one dot is editing File Open app All can be edited is for demo required for 179 Don t warn when using preliminary models Turn off the warning message for all preliminary models Note All SMPS models are flagged as preliminary as a disclaimer Automatically delete raw files This allows waveform data files to be deleted automatically after closing a simulation This dramatically reduces the amount of disk Space used by LTspice but requires the simulation to be rerun when you reopen the simulation Automatically delete net files This allows the schematic s netlist to be automatically deleted
134. on SiGe and V HBT devices o Integrated Substrat transis in integrated processes IC Capabilities compared to Standard Gummel Poon Model tor for parasitic devices mi tter breakdown model Weak avalanche and Bas Physical separation of Improved Dep Improved Self heating modeling O O O O O O not Improved Early Effect modeling Ic and letion capacitance model temperature modeling Ib in this version Model Structure 155 CX lext leer Parameters Because the VBIC model is based on SGP model it is possible to start with SGP parameters carry out some transformations Following parameters are from VBIC version 1 2 which is implemented in LTSpice in the 4 terminal version without excess phase network and self heating effect To switch from SGP to VBIC you should set the extra parameter level to 9 Na Parameter meaning Uni Defau me t lt tn Parameter measurement oc 27 om temperature EC Extrinsic coll Q 0 1 x resistance 156 Ic VO ga mm hr Gf rb rb re rs rb is nf fc cb eo pe me aj Intrinsic coll resistance Epi drift saturation voltage Epi doping parameter High current RC factor Extri resis Intri resis Intri n n n sic base tance sic base tance sic emitter resis Intri resis Paras r
135. on Ek Raise left hand side to power of right hand side Only the real part is returned e g 1 1 5 gives zero not i Convert the following expression to Boolean and invert True is numerically equal to 1 and False is 0 Conversion than 0 5 to Boolean converts a value to 1 if the value is greater otherwise the value is converted to 0 109 Note that LTspice uses the caret character for Boolean XOR and for exponentiation Also LTspice distinguishes between exponentiation x y and the function pwr x y Some 3rd party simulators have an incorrect implementation of behavioral exponentiation evaluating 3 3 incorrectly to 27 instead of 27 presumably in the interest of avoiding the problem of exponentiating a negative number to a non integer power LTspice handles this issue by returning the real part of the result of the exponentiation E g 2 1 5 evaluates to zero which is the real part of the correct answer of 2 828427124746191 This means that when you import a 3rd party model that was targeted at a 3rd party simulator you may need to translate the syntax such as x y to x y or even pwr x y If an optional Laplace transform is defined that transform is applied to the result of the behavioral current or voltage The Laplace transform must be a function solely Of S4 The Boolean XOR operator is understood to mean exponentiation when used i
136. onvergence fail message is issued startup This is similar to SPICE s original uic It means that independent sources should be ramped on during the first 20us of the simulation However a DC operating point 99 analysis is performed using the constraints specified on a ic directive steady Stop the simulation when steady state has been reached This is required for an efficiency calculation report Steady state detection is written into the SMPS macromodels Typically they are written to look for zero error amp output current averaged over a clock cycle The algorithm takes the error amp s output compliance range into consideration The fraction of peak current that is considered zero current is specified with the sstol option The automatic steady state detection can fail either by being too critical or not critical enough You can interactively specify steady state in the following manner As soon as the simulation starts execute menu command Simulate gt Efficiency Calculation gt Mark Start The first time you execute this command you tell LTspice you re going to manually specify the integration limits After the circuit looks like it s reached steady state execute that command again That will clear the history and restart the Efficiency Calculation Then after awhile as in you see well more than 10 clock cycles execute Simulate gt Efficiency Calculation gt Mark End
137. oral voltage source B Syntax Exxx n n POLY lt N gt nodel nodel node2 node2 nodeN nodeN gt lt cO cl c2 c3 c4 This is an archaic means of arbitrary behavioral modeling with a polynomial It is useful for running existing Linear Technology behavioral models 118 Note It is better to use a G source shunted with a resistance to approximate an E source than to use an E Source A voltage controlled current source shunted with a resistance will compute faster and cause fewer convergence problems than a voltage controlled voltage Source Also the resultant nonzero output impedance is more representative of a practical circuit F Current Dependent Current Source Symbol Name F Syntax Fxxx n n Vnam gain This circuit element applies a current between nodes n and n The current applied is equal to the value of the gain times the current through the voltage source specified as lt Vnam gt Syntax Fxxx n n value lt expression gt This is an alternative syntax of the behavioral Source arbitrary behavioral voltage source B Syntax Fxxx n n POLY lt N gt V1 V2 VN cO cl c2 C3 G4 2l This is an archaic means of arbitrary behavioral modeling with a polynomial It is useful for running existing Linear Technology behavioral models G Voltage Dependent Current Source Symbol Names G G2 There are thr types of voltage depen
138. pile or disassemble t software executable s or models of LTC products provide We take no responsibility for the accuracy of third part he d y models used in the simulator whether provided by LTC or the user While we have mad very effort to ensure that SwitcherCAD operates in the manner described Operation to be error free Upgrades we do not guarante modifications or repairs to this program will be strictly at the discreti of LTC If you encounter problems SwitcherCAD for the purpose of sel LTC products you may obtain technical installing or operati calling our Applications Department at between 8 00 am and 5 00 pm Pacific time Monday through Friday We do not provide such technical support for general circuit simulations that are not for the evaluation of LTC products Because of the great variety of PC compatible computer systems operating system versions peripherals currently in use we do not guarantee that you will be able to use SwitcherCAD such systems If you are unable to use SwitcherCAD assistance by 408 432 1900 successfully on all e on ng lecting and evaluating and LTC does provide design support for LTC switching regulator by whatever means necessary ICs The software and related documentation are provided AS and without warranty of a
139. prepare an encrypted library you need to invoke LTspice from the command line with the command line option encrypt You will need to first backup the library because it will be replaced with the encrypted version IHERE EXISTS NO UTILITY TO CONVERT AN ENCRYPTED LIBRARY BACK TO CLEAR TEXT Below summarizes the two steps 1 Make a backup copy of the library The version you encrypt is deleted 2 From a command line type scad3 exe encrypt filename The file filename will be replaced with an encrypted version The encryption process will take a few minutes One this process is finished you have an encrypted ASC file It s possible to add a copyright notice above the Begin line but the first 9 lines of the file must remain unchanged and each line of copyright notice you add must begin with the character That is here an encrypted file written by LTspice LTspice Encrypted File This encrypted file has been supplied by a 3rd party vendor that does not wish to publicize F 74 the technology used to implement this library Permission is granted to use this file for simulations but not to revers ngineer its contents F F Begin 50 3E 46 OF FA 6E 67 FF B8 4D D9 62 14 32 60 24 36 71 35 0B 66 4F AD 52 B8 F5 9E 22 9F CO 18 8B FB FE 1D you can change this to be LTspice Encrypted File Th
140. r most of the traditional SPICE tolerance parameters gmin abstol reltol chgtol vntol are not remembered between program invocations If you want to use something other than the default values you will have to write a option Statement specifying the values you want to use and place it on the schematic or keep the settings in a file and inc that file Also interesting is which solver is used LTspice contains two complete versions of SPICE One is called the normal solver and the other is called the alternate solver The alternate solver uses a different sparse matrix package with reduced roundoff error Typically the alternat solver will simulate at half the speed of the normal solver but with one thousand times more internal accuracy This can be a useful diagnostic to have available There is no option to specify which solver is used the choice must be made before the netlist is parsed because the two solvers use different parsers Check the box next to Accept 3K4 as 3 4K to force LTspice to understand a number written as 4K99 to be equal to 4 99K Normal SPICE practice does not allow this but it is available in LTspice by popular request Netlist Options Convert p to u Replace all instances of p to u Useful if your MS Windows installation can t display a Greek Mu as e g some Chinese editions of Windows don t wi
141. r of clock cycles to wait before looking for steadystate Default temperature tnom topologyc heck trtol trytocomp act vntol plotrelto l plotvntol plotabsto Nu Nu Nu 27 luV 00 25 10g l1nA for circuit element instances that don t Specify temperature Default temperature at which device parameters were measured for models that don t specify this temperature Set to zero to skip check for floating nodes loops of voltage sources and non physical transformerwinding topology Set the transient error tolerance This parameter is an estimate of the factor by which the actual truncation error is overestimated When non zero the simulator tries to condense LTRA transmission lines history of input voltages and currents Sets the absolute voltage error tolerance Sets the relative error tolerance for waveform compression Sets the absolute voltage error tolerance toleranc for waveform compression Sets the absolute 87 l m current error tolerance for waveform compression plotwinsi Nu 300 Number of datapoints ze m to compress in one window Set to zero to disable compression PARAM User Defined Parameters The param directive allows the creation of user defined variables This is useful for associating a name with a value for the sake of clarity and parameterizi
142. rce Nam Description Un e it 171 Vof DC offset V f Vam Amplitude V p Fca Carrier frequency Hz ie MDI Modulation index Fsi Signal frequency Hz g The voltage is given by Voff Vamp sin 2 pi Fcar time MDI sin 2 pi Fsig tim e Syntax Vxxx n n PWL tl1 vl t2 v2 t3 v3 Arbitrary Piece wise linear voltage source For times before tl the voltage is vl For times between tl and t2 the voltage varies linearly between vl and v2 There can be any number of time voltage points given For times after the last time the voltage is the last voltage Syntax Vxxx n n wavefile filename chan lt nnn gt This allows a wav file to be used as an input to LTspice filename is either a full absolute path for the wav file or a relative path computed from the directory containing the simulation schematic or netlist Double quotes may be used to specify a path containing spaces The wav file may contain up to 65536 channels numbered O0 Eo 65535 Chan may be set to specify which channel is used By default the first channel number 0 is used The wav file is interpreted as having a full scale range from 1V to 1V 172 This source only has meaning in a tran analysis W Current Controlled Switch Symbol Names CSW Syntax Wxxx nl n2 Vnam model on off Example W1 out 0 Vsense MySwitch Vsense a b O ll jo
143. rical graphical annotations made to schematics such as lines and circles will be draw in the same color as a component body Placing New Components Certain frequently used components such as resistors capacitors and inductors can be selected for placing on the schematic with a toolbar button For most symbols use the menu command Edit Component to start a dialog to browse for the device you wish 22 Select Component Symbol Top Directory D Axp lib sym yPower Synchronous Buck Boost DC DC Converter D xp lib sym PowerProducts LTC3440 LTC3402 LTC3406B 1 8 LTC3716 LTC3404 LTC3411 LTC371 LTC3405 LTC3412 LTC3718 LTC3405A LTC3413 LTC3718 LTC3405A 1 5 C3440 LTC3720 LTC3405A 1 8 LTC3 01 LTC372 LTC3406 LTC3704 LTC3728 LTC3406 1 5 LTC3 0 LTC3728L LTC3406 1 8 LTC3 11 LTC3729 LTC3406B LTC3713 LTC3732 LTC3406B 1 5 LTC3 14 LTC3778 ial Cancel Programming Keyboard Shortcuts The menu command Tools gt Control Panel gt Drafting Options gt Hot Keys allows you to program the keyboard short cuts for most commands Simply mouse click on a command and then press the key or key combination you would like to code for the command To remove a shortcut click on the command and press the Delete key 23 Schematic Editing Keyboard Shortcut Map at fay sn n fa sa sd OPN Sy ot BY coy ro u SIGE PCB Netlist Extraction The schematic menu command Tools gt
144. ripdt control step rejection If the voltage across a source changes by more than tripdv volts in tripdt seconds that simulation time step is rejected Expressions can contain the following o Node voltages e g V n001 o Node voltage differences e g V n001 n002 o Circuit element currents for example I S1 the current through switch S1 or Ib Q1 the base current of Ql However it is assumed that the circuit element current is varying quasi statically that is there is no instantaneous feedback between the current through the referenced device and the behavioral source output Similarly any ac component of such a device current is assumed to be zero in a small signal linear AC analysis 105 The keyword simulation The keyword The following functions Function Name abs x absdelay x t tmax l acos x arccos x acosh x asin x arcsin x asinh x atan x arctan x atan2 y atanh x buf x ceil x cos x 106 Lime meaning the current time in the pi meaning 3 14159265358979323846 x Description Absolute value of x x delayed by t Optional max delay notification tmax Real part of the arc cosine of X e g acos 5 returns 3 14159 not 3 14159 2 29243i Synonym for acos Real part of the arc hyperbolic cosine of x e g acosh 5 returns 0 not 1 04721 Real part of the arc si
145. rst line in the netlist is ignored that is it is assumed to be a comment The last line of the netlist is usually simply the line END but this can be omitted Any lines after the line END are ignored The order of the lines between the comment and end is irrelevant Lines can be comments circuit element declarations or simulation directives Let s start with an example This first line is ignored The circuit below represents an RC circuit driven with a 1MHz square wave signal Rl nl n2 1K a 1KOhm resistor between nodes nl and n2 C1 n2 0 100p a 100pF capacitor between nodes n2 and ground Vl nil 0 PULSE O 100 O 5p 1p a 1Mhz square wave tran 3p do a 3us long transient analysis end The first two lines are comments Any line starting with a is a comment and is ignored The line starting with R1 declares that there is a 1K resistor connected between nodes nl and n2 Note that the semicolon can be used to start a comment in the middle of a line The line starting with C1 declares that there is a 100pF capacitor between nodes 61 n2 and ground The node O is the global circuit common ground Below is an overview of the lexicon of LTspice o Letter case leading spaces blanks and tabs are ignored o The first non blank character of a line defines the typ of circuit element Leading Type of line
146. s all available symbol attributes Next to each field is a check box to indicate if the field should be visible on the schematic 27 Component Attribute Editor ERIS The attributes SpiceModel Value Value2 SpiceLine and SpiceLine2 are all part of the overall value of the component In terms of the way the component is netlisted for SPICE the component will generate a line of SPICE that looks like this name nodel node2 lt SpiceModel gt lt Value gt lt Value2 gt lt SpiceLine gt lt SpiceLine2 gt The prefix attribute character is prefixed to the reference designator if different than the first character of the reference designator The Prefix character and InstName will be separated with a S character in this case For example if you have a Prefix attribute of M and an InstName attribute of O1 the name in the netlist will be MSQOl This allows you use reference designators with a leading character different than SPICE uses to identify the type of device There are three exceptions to the above rule There is one special symbol jumper that does not translate into a 28 circuit element but is a directive to the netlist generator that there are two different names for the same electrically identical node Another exception is a symbol defined to have a prefix of X and both a Value and Value2 attributes defined Such a component netlists as t
147. schematic such as inc fil name where filename is the name of the file containing the definition of the subcircuit Note that this must be the complete name with any file extension and Windows Explorer defaults to not showing the file extension So you if you have a file called my lib sub txt which you can edit view in notepad and Windows Explorer shows you the file exists as my lib sub The SPICE directive to include this file is linc mylib sub txt If you used inc mylib sub you will get an error message that that file can t be found Is there a tool for generating native LTspice VDMOS MOSFET models instead of subcircuits Yes Hendrik Jan Zwerver developed a free VDMOS tool that is distributed from the Files section of the independent users group http groups yahoo com group LTspice Who is Hendrik Jan Zwerver The guy on the right 196 Paris Nov 20 2006 License and Distribution Can I re distribute the software Yes you can distribute the software freely whether you are a Linear Technology customer or not See the license section for more details Technical support for non Linear Technology customers is purely discretionary Is it a shareware freeware or demo 197 This program is not a shareware or a demo It is fully functional freeware The purpose of this software is to help our customers use our products It can also be used
148. se FALSE gt TRUE if expression on the left is less than or equal the expression on the right otherwise FALSE lt TRUE if expression on the left is greater than or equal the expression on the right otherwise FALSE Addition 47 Subtraction X Multiplication Division KR Raise left hand side to power of right hand side Convert the following expression to Boolean and invert Step selection operator TRUE is numerically equal to 1 and FALSE is 0 Conversion to Boolean converts a value to 1 if the value is greater than 0 5 otherwise the value is converted to 0 The step selection operator is useful when multiple simulation runs are available as in a step temp or dc analysis It selects the data from a Specific run For example V 1 3 would plot the data from the 3 run no matter what Steps where selected for plotting For complex data only and are available Also with regard to complex data the Boolean XOR operator is understood to mean exponentiation The following constants are internally defined Na Value me E 2 7182818284590452354 48 E 3 14159265358979323846 K 1 3806503e 23 Q 1 602176462e 19 The keyword time is understood when plotting transient analysis waveform data Similarly freq and omega are understood when plotting data from an AC anal
149. sfied that the solution is valid If you want to restart a tran solution from the DC operating point you can edit the file from a nodeset to a ic to try to coercive the solver to start from this DC state Since the integration state of all the circuit reactances isn t saved in the savebias file success with this technique varys STEP Parameter Sweeps This command causes an analysis to be repeatedly performed while stepping the temperature a model parameter a global parameter or an independent source Steps may be linear logarithmic or specified as a list of values Example step oct vl 1 20 5 Step independent voltage source V1 from 1 to 20 logarithmically with 5 points per octave Example step I1 10u 100u 10u Step independent current source I1 from 10u to 100u in step increments of 10u ES Os LO Example step param RLOAD I 94 Perform the simulation three times with global parameter Rload being 5 10 and 15 Example step NPN 2N2222 VAF 50 100 25 Step NPN model parameter VAF from 50 to 100 in steps of 25 Example step temp 55 125 10 Step the temperature from 55 C to 125 C in 10 degr step Step sweeps may be nested up to thr levels deep SUBCKT Define a Subcircuit As an aid to defining a circuit repetitive circuitry can be enclosed in a subcircuit definition and used
150. ss The conversion process will require an amount of free disk space equal to the file size to be converted but the converted file will be only 11 bytes larger than the original file The conversion process can take a long time and use up to one quarter of your physical memory In fact it can take more time to convert the file to Fast Access format then was required for the initial simulation The exact time the conversion requires will depend on such factors as the state of the hard disk fragmentation and the amount of 58 physical memory you have During conversion you may find your machine is not very respondent to your mouse and keyboard It is possible to convert files in a batch command with the following command line syntax scad3 exe FastAccess lt file gt Where lt file gt is the name of the raw file you wish to convert to Fast Access format This format is only supported for real data not the complex data that comes from a ac analysis LTspice LTspice Overview LTspice is the circuit simulation engine for the SwitcherCAD LTspice is a schematic driven circuit simulation program The LTspice simulator was originally based years ago on Berkeley SPICE 3F4 5 The simulator has gone through a complete re write in order to improve the performance of the simulator fix bugs and extend the simulator so that it can run industry standard semiconductor and behavioral models A digital
151. t New Symbol NOTE Screen updates during symbol editing can be slow If this is a problem with your video card reduce the area of the symbol editing window to speed up screen redraws and or reduce the screen s color resolution This will give better tactical response to mouse movement Drawing the body You draw the body of the symbol as a series of lines rectangles circles and arcs The objects have no electrical impact on the circuit You can also draw text on the symbol with the Draw Text command that has no impact on the circuit The anchor points of this objects are drawn with small red circles so you know what to grab when dragging them about You can toggle the red markers off and on with the menu command View gt Mark Object Anchors 30 Adding the Pins The pins allow electrical connection to the symbol Use the menu command Edit gt Add Pin Port to add a new pin Pin Port Properties The Pin Label Position determines how the pin label is presented TOP BOTTOM LEFT and RIGHT are text justifications For example if a pin label is TOP justified the pin the label s text justification s anchor point will be above the label If the symbol represents a SPICE primitive element or a subcircuit from a library then the pin label has no direct electrical impact on the circuit However if the symbol represents lower level schematic of a hierarchical schematic then the pin name is Significant
152. te command Drag Click on or drag a box around the objects you wish to drag Then you can move those objects to a new location and the attached the wires are rubber band with the new location Draw gt Line Draw a line on the schematic Such lines have no electrical impact on the circuit but can be useful for annotating the circuit with notes Draw gt Rectangle Draw a rectangle on the schematic This rectangle has no electrical impact on the circuit but can be useful for annotating the circuit with notes Draw gt Circle Draw a circle on the schematic This circle has no electrical impact on the circuit but can be useful for annotating the circuit with notes Draw Arc Draw an arc on the schematic This arc has no electrical impact on the circuit but can be useful for annotating the circuit with notes NOTE The graphical annotations to the schematic lines rectangles circles and arcs snap by default to the 19 same grid as the used for electrical contacts of wires and pins Hold down the control key while positioning these to defeat this snap Label a node name Each node in the circuit requires a unique name You can Specify the name of a node so an arbitrary one isn t generated by the netlister Node 0 is the circuit global ground and is drawn with a special graphical symbol instead of the name 0 There is also a graphical symbol def
153. terp MixedInte rp CompactRe l CompactAb S TruncNr TruncDont Cut Lengths Relative rate of change of derivative CO set a breakpoint Absolute ra change of te of derivative CO set a breakpoint Don t limit time step to less than line delay Don t attempt complex time step control Use linear interpolation Use linear interpolation when quadratic seems to fail Reltol for history compaction Abstol for history compaction Use Newton Raphson method for time step control Don t limit time step to keep impulse response errors low flag flag flag flag flag flag not set not set not set set RELT OL ABST OL not set noi se ct ct 149 Q Bipolar transistor Symbol Names NPN PNP NPN2 PNP2 Syntax Qxxx Collector Base Emitter Substrate Node model area off IC lt Vbe Vce temp lt T gt Example Q1 C B E MyNPNmodel model MyNPNmodel NPN Bf 75 Bipolar transistors require a model card to specify its characteristics The model card keywords NPN and PNP indicate the polarity of the transistor The area factor determines the number of equivalent parallel devices of a Specified model The bipolar junction transistor model is an adaptation of the integral charge control
154. th default fonts and ii generating netlists for SPICE simulators that don t understand the u character as the metric multiplier of le 6 Reverse comp order Circuit elements are normally netlisted in the order in which they were added to the 183 schematic Checking this box causes this order to be reversed Default Devices Whenever a diode is used in an LTspice schematic the default model statement model D D is added to the netlist to suppress messages about using the default model Unchecking this option suppresses inclusion of this line as well as the analogous model statements for bipolar MOSFET and JFET transistors Default Libraries Whenever a diode is used in an LTspice schematic the default library standard dio is included in the simulation by a lib statement Unchecking this option suppresses inclusion of this library as well as the analogous library statements for bipolar MOSFET and JFET transistors Convergence Aids For Internal program development use only Control Panel 184 Hacks This pane was used for internal program development but is currently almost obsolete Usually you can leave these options as they are If you have frequently updated the program over the web you might want to press Reset to Default Values to reset to the current recommended settings Control Panel im it ka I I Drafting Options 185
155. the body of the component 3 Place the mouse over a symbol hold down the control key and click the right mouse button A dialog box will appear that will displays all available symbol attributes Next to each field is a check box to indicate if the field should be visible on the schematic Edit a Visible Attribute Most visible compone nt attribute fields can be edited by pointing at it wi clicking The mouse caret when it s poin convenient way of ch th the mouse and then right cursor will turn into a text ting at the text This is a anging the value of a component 25 Enter new Value for L1 Specialized Component Editors Many component types such are resistors capacitors inductors diodes bipolar transistors MOSFET transistors JFET transistors independent voltage sources independent current sources and hierarchical circuit blocks have special editors These editors can access the appropriate database of related components To use these editors right mouse click on the body of the component 26 General Attribute Editor Sometimes it is desired to get direct access to every available component attribute to edit their contents and visibility An editor that allows you to do this can be reached by placing the mouse over the body of a symbol holding down the control key and clicking the right mouse button A dialog box will appear that will display
156. tic probing technique is to plot the instantaneous power dissipation of a component To do this hold down the Alt key and click on the body of the symbol of the component The instantaneous power dissipation will be plotted as an expression of voltages and currents It will be plotted on it s own scale with the units of Watts The mouse cursor turns into an icon that looks like a thermometer when it s pointing at a dissipation that can be plotted You can find the average power dissipation by control clicking the trace label 40 F Linear Technology LTspice SwitcherCAD III LT1371 Mi E3 File Edit Hierarchy View Simulate Tools Window Help ASHIT ZJ QQQRQ EU BBY d BE 1 340 m m D MBR i fLT1371 asc Sus 12us 16us Left click to plot D1 dissipation V SW OUT I D1 Ax Menu command Plot Settings gt Visible Traces The menu command Plot Settings gt Visible Traces is the dialog seen at the beginning of plotting data from a simulation It lets you select the initial traces to start the plot It also gives you random access to the full list of traces plotted Select Visible Waveforms xi Select Waveforms to Plot Ctrl Click to toggle Cancel AltDouble Click to enter an expression 41 3 Menu command View gt Add Trace The Plot Settings gt Add Trace command is similar to the Plot Settings gt Visible Traces command However you can not delete traces that are already
157. time steps Note that since the capacitor element includes these parasitics it is useful for macromodeling the fundamental of a piezoelectric crystal There is also a general nonlinear capacitor available Instead of specifying the capacitance one writes an expression for the charge LTspice will compile this expression and symbolically differentiate it with respect to all the variables finding the partial derivative s that correspond to capacitances Syntax Cnnn nl n2 Q lt expression gt ic lt value gt m lt value gt 112 There is a special variable x that means the voltage across the device Therefore a 100pF constant capacitance can be written as Cnnn n1 n2 Q 100p x A capacitance with an abrupt change from 100p to 300p at zero volts can be written as Cnnn nl n2 Q x if x lt 0 100p 300p This device is useful for rapidly evaluating the behavior of a new a hypothetical charge model for e g a transistor D Diode Symbol Names DIODE ZENER SCHOTTKY VARACTOR Syntax Dnnn anode cathode model area t off m lt val gt n lt val gt temp lt value gt Examples D1 SW OUT MyIdealDiode model MyIdealDiode D Ron 1 Roff 1Meg Vfwd 4 D2 SW OUT dio2 model dio2 D Is 1e 10 113 Instance parameter M sets the number of paralle while instance param
158. tional PLL asc The instantaneous oscillation frequency is set by the voltage on the FM input The conversion from voltage to frequency is linear and set by the two instance parameters mark and space Mark is the frequency when the FM input is at 1V and space is the frequency when the input is at OV The amplitude is set by the voltage on the AM input and defaults to 1V if that input is unused connected to the MODULATE common The schematic capture aspect of LTspice netlists symbols for these devices in a special manner All unconnected terminals are automatically connected to terminal 8 Also if terminal 8 is unconnected then it is connected to node 0 B Arbitrary behavioral voltage or current sources 104 Symbol names BV BI Syntax Bnnn n001 n002 V lt expression gt ic lt value gt tripdv lt value gt tripdt lt value gt laplace lt expression gt window lt time gt nfft lt number gt mtol lt number gt Bnnn n001 n002 I lt expression gt ic lt value gt tripdv lt value gt tripdt lt value gt Rpar lt value gt laplace lt expression gt window lt time gt nfft lt number gt mtol lt number gt The first syntax specifies a behavioral voltage source and the next is a behavioral current source For the current source a parallel resistance may be specified with the Rpar instance parameter Tripdv and t
159. torage is modeled by three constant capacitors CGSO CGDO and CGBO which represent overlap capacitances by the 139 non linear thin oxide capacitance which is distributed among the gate source drain and bulk regions and by the nonlinear depletion layer capacitances for both substrate junctions divided into bottom and periphery which vary as the MJ and MJSW power of junction voltage respectively and are determined by the parameters CBD CBS CJ CJSW MJ MJSW and PB Charge storage effects are modeled by the piecewise linear voltages dependent capacitance model proposed by Meyer The thin oxide charge storage effects are treated slightly different for the Level 1 model These voltage dependent capacitances are included only if Tox is Specified There is some overlap among the parameters describing the junctions e g the reverse current can be specified either through Is Amp or through Js Amp m m Whereas the first is an absolute value the second is multiplied by Ad and As to give the reverse current of the drain and source junctions respectively The same idea applies also to the zero bias junction capacitances CBD and CBS Farad on one hand and CJ Farad m m on the other The parasitic drain and source series resistance can be expressed as either RD and RS Ohms or RSH Ohms square the latter being multiplied by the number of squares NRD and NRS input on the device lin
160. uit s hierarchy You can also plot current into a particular connection of a component with more than two pins by clicking on that pin of the symbol If you click the same voltage or current twice then all other traces will be erased and the double clicked trace will be plotted by itself You can delete individual traces by clicking on the trace s label after selecting the delete command The following Screen shot shows how to point at a pin current 38 Notice that the mouse cursor turns into an icon that looks like a clamp on ammeter when it s pointing at a current that can be plotted LOTES Technology LTspice SwitcherCAD III LT1371 me File Edit View Simulate Tools Window Help AS EP 4 0 QQQRQ 20 Fey sae INA 1 221 V TES 4us Sus 12us 16us Left button click to plot I U1 SW When plotting a pin current the convention of positive current is in the direction into the pin It is also possible to point at voltage differences with the mouse You can click on one node and drag the mouse to another node You will see the red voltage probe at the first node and a black probe on the second This allows you to differentially plot voltages 39 LOTES Technology LTspice SwitcherCAD III LT1371 l Ei File Edit View Simulate Tools Window Help ASOT 4 9 QQQRQ CC Bae sae L2 MBRS340 SUS 12us 16us Release Left button to plot SWV OUT Yet another schema
161. urrent is il tl and t2 the current varies There can be any number of time current points For times between linearly between il and i2 given For times after the last time the current is the last current Syntax This allows a IXXX nd n wavefile lt filename gt wav file to be used as an filename is either a full file or a relative pa containing the simulat quotes may be used to The wav file may con to 65535 used By default The from 1A to 1A 126 Chan may be set the first wav file is interpreted as having a full scale range th computed from th tion schematic or n absolute path for input chan lt nnn gt to LTspice the Wav e direci etlist Specify a path con tain up to 65536 ch channel n taining annels Lory Double spaces numbered O0 to specify which channel is umber 0 is used This source only has meaning in a tran analysis J JFET transistor Symbol Names NJF PJF Syntax Jxxx D G S model area off IC Vds Vgs temp T Examples J1 0 in out MyJFETmodel model MyJFETmodel NJF Lambda 001 J2 0 in out MyPJFETmodel model MyPJFETmodel PJF Lambda 001 A JFET transistor requires a model card to specify its characteristics Note that the model card keywords NJF and PJF specify the polarity of the transistor The area factor determines the number of equival
162. ut performing the zoom by either pressing the Esc key or right mouse button before releasing the left mouse button 56 i File View Plot Settings Simulation Tools Window Help Aa a PIF 9 QQQR PM EBSS X GBP PMO O amp e I Cursor Step Information iX A Cursor 1 11 60p 2n2222 vafj 100 Temp 25 Run 4 24 OmV 100mV 200mV 300mV 400mV 500mV Left Click amp drag to move Cursor 1 Right Click to see step temp dc values Alternate The attached cursors can also be used to readout which trace belongs to which run of a step dc temp set of Simulation runs You can navigate the cursor from dataset to dataset with the up down keyboard cursor keys and then right click on the cursor to see the step information for that run Save Plot Configurations The menu commands Plot Settings gt Save Plot Settings Open Plot Settings files allow you to read and write plot configurations to disk Plot setting files are ASC files that have a file extension of plt The default filename is computed from the name of the data file by replacing the data file s raw extension with plt If such a file name exists when a data file is first opened that plot settings file is read for initial plot configuration Each analysis type tran ac noise etc has its own entry in the plot settings file It isn t possible to load the settings from one analysis type 57 to another But you ca
163. vior that is qualitatively different than the above monolithic MOSFET models In particular i the body diode of a VDMOS transistor is connected differently to the external terminals than the substrate diode of a monolithic MOSFET and ii the gate drain capacitance Cgd non linearity cannot be modeled with the simple graded capacitances of monolithic MOSFET models In a VDMOS transistor Cgd abruptly changes about zero gate drain voltage Vgd When Vgd is negative Cgd is physically based a capacitor with the gate as one electrode and the drain on the back of the die as the other electrode This capacitance is fairly low due to the thickness of the non conducting die But when Vgd is positive the die is conducting and Cgd is physically based on a capacitor with the thickness of the gate oxide Traditionally elaborate subcircuits have been used to duplicate the behavior of a power MOSFET A new intrinsic spice device was written that encapsulates 144 50 this behavior in the interest of compute speed reliability of convergence and simplicity of writing models The DC model is the same as a level 1 monolithic MOSFET except that the length and width default to one so that transconductance can be directly specified without scaling The AC model is as follows The gate source capacitance is taken as constant This was empirically found to be a good approximation for power MOSFETS if the gate source volta
164. visible with it It has two useful capabilities One is an edit box near the top of the dialog that allows you to enter a pattern of characters Only trace names that match the pattern will be shown in the dialog This is very useful for finding a trace when you can only partially remember the name Also it s a bit easier to compose an expression of trace data because you can click on a name in the dialog instead of typing out its name LA Technology LTspice SwitcherCAD III butter asc of x File View Tools Window Help Asa PFOQQQRQ SG ES X364 ea sso faa butter asc 0 6 V 0 4 O02V O0V A Only list traces containing I C 2 j X Cancel Expression s to add I C24y C32 42 Zooming LTspice SwitcherCAD autozooms whenever there is new data to plot To zoom up on an area simply drag a box about the region you wish to see drawn larger Fe Linear Technology LTspice SwitcherCAD III LT1371 lel Ed ES File View Tools Window Help m x kB Xs QQQR Eig Em t Be LUTES PATES KUTE 400us 500uUs dx 174 938us 5 71631KHz dy 3 24 7 There are toolbar buttons and menu commands for zooming out panning and returning to the autoranged zoom Note the undo and redo commands allow you to review the different zooms used Waveform Arithmetic There are thr types of mathematical operations that can be performed on waveform data 1 Plot expressions of trac
165. vs Fm Maximum Frequency of interest Hz 1G ax Rp Resistance per unit length Q 1K er 1 Cp Capacitance per unit length F le er ih 1 167 Is Saturation Current per unit A pe length rl Rs Diode Resistance per unit Q pe length rl V Voltage Source Symbol Names VOLTAGE BATTERY Syntax Vxxx n n voltage AC lt amplitude gt Rser lt value gt Cpar lt value gt This element sources a constant voltage between nodes nt and n For AC analysis the value of AC is used as the amplitude of the source at the analysis frequency A series resistance and parallel capacitance can be defined The equivalent circuit is lt Voltage gt 168 Voltage sources have historical lly been used as the current meters in SPICE and are used as current sensors for current controlled elements If Rser is specified the voltage source can not be or W elements However element including the voltage source Syntax Vxxx n n PULSE V1 Tperiod Ncycles Time dependent pulsed voltage source Nam Description e Vof Initial value f Von Pulsed value Tde Delay lay Tr Rise time TE Fall time Ton On time Tpe Period rio d Ncy Number of cycles Omit cle for free running pulse S function Syntax Vxxx n n SINE Voffset Vamp Freq Td Ncycles used as a sense element for F H the current of any circuit can be plotted V2 Tdelay Trise T
166. w the active window and typing Ctrl C Then in an application that accepts bitmap pastes from the clipboard like Word or Paint type Ctrl V Note that this also works for bitmaps of schematics These images can also be exported as Windows metafiles Menu command Tools Write to a wmf file which writes the image as vector graphics to a wmf file that can be imported in various desktop publishing tools When exporting a metafile of waveform data you first go to Tools gt Control Panel gt Waveform gt Font and select Arial The default System is highly legible on a CRT but is a fixed font that does not scale correctly in metafiles OK that works for bitmaps but can I get the data itself to an application like Excel There is an export utility Waveform Menu File gt Export that allows data to be exported to an ACS file There is also a 3 party free utility written by Helmut Sennewald It is available from the independent users group http groups yahoo com group LTspice This utility allows various forms of manipulation of the data including the ability to merge waveforms from different simulation runs Who is Helmut Sennewald The guy on the right 202 Running Under Linux Do you have a Linux version of this program Not a separate edition but it does run under WINE The program has been tested on Linux RedHat 8 0 with WINE version 20030219 RedHat 9 0 with WINE 20040716 and Su
167. wave filename wav lt Nbits gt lt SampleRate gt V out V out2 example wave C output wav 16 44 1K V left V right filename wav is either a complete absolute path for the wav file you wish to create or a relative path computed from the directory containing the simulation schematic or netlist Double quotes may be used to specify a path containing spaces Nbits is the number of sampling bits The valid range is from 1 to 32 bits SampleRate is the number of samples to write per simulated second The valid range is 1 to 4294967295 samples be second The remainder of the syntax lists the nodes that you wish to save Each node will be an independent channel in the wav file The number of channels may be as few as one or as many as 65535 It is possible to write a device current e g Ib Ql1 as well as node voltage The wav analog to digital converter has a full scale range of 1 to 1 Volt or Amp Note that it is possible to write wav files that cannot be played on your PC sound system because of the number of channels sample rate or number of bits due to limitations of your PC s codec But these wav files may still be used in LTspice as input for another simulation See the sections LTspice gt Circuit Elements gt V Voltage Source and Current source for information on playing a wav file into an LTspice simulation If you want to play the wav file on your PC sound card keep in mind that
168. wer 1 vel bloc matches the name of a node in th As the names of symbols used as names of the schematics correspo lower l n the schematics k s symbol that vel schematic schematic blocks and the nding to those block must consist of valid characters that can be used as filenames They also cannot contain the space character 35 Fi Linear Technology LTspice SwitcherCAD III preamp asc File Edit Hierarchy View Simulate Tools Window Help BASH v FO QQQR EISE sem SS 249673 Y Ous 20ps Click to plot V 1 N003 LTspice will look in the directory of the top level schematic for symbols and blocks to complete the circuitry of the top level schematic The symbol you create to represent the lower level schematic block should have no attributes defined Navigating the Hierarchy Any file opened with the File gt Open command is considered a top level schematic You can add SPICE directives to that block and run simulations using only it and any lower level schematics to which it refers 36 To open a schematic block as an instance of a block of a higher level schematic first open the higher level schematic and then move the mouse to the body of the instance of the symbol calling the block When you right mouse click on the body of the instance of that symbol a special dialog appears that allows you to open the schematic When you open the schematic in t
169. whenever the schematic is closed These files can be thought of as small temporary files and deleting them makes exploring the directory tidier They define th lectrical connectivity of the schematic to the LTspice simulator Some people prefer not to delete them because they have further use for them Automatically delete log files This allows the simulation log to be automatically deleted whenever the simulation is closed These files contain various simulation statistics such as elapsed time during the simulation warning and error messages and step parameters used for Step temp dc analyses Directory for Temporary Files Directory for temporary storage of waveform and update files Save Defaults These settings are used when you don t explicitly state which nodes should be saved in a simulation Useful setting are Save Device Currents Save Subcircuit Node Voltages and Save Subcircuit Device Currents Device voltages and internal device voltages are only of internal program development use 180 Control Panel Save Device Currents Check this so that you can plot device and terminal currents You will also need it to be able to plot dissipation Save Subcircuit Node Voltages You will need to check this to plot voltages in hierarchical designs Save Subcircuit Device Currents You will need to check this to plot currents in hierarchical d
170. wo lines of SPICE lib lt SpiceModel gt name nodel node2 lt Value2 gt This allows symbols to be defined that automatically include the library that contains the definition of the subcircuit called by the component The netlist compiler removes duplicate lib statements Note that such components are not editable on the schematic The third exception is a symbol that has other exception is a symbol defined to have a prefix of X and a ModelFile attribute defined Such a component also netlists as two lines of SPICE lib lt ModelFile gt lt name gt nodel node2 lt SpiceModel gt lt Value gt lt Value2 gt lt SpiceLine gt lt SpiceLine2 gt Use this method when you want to automatically include a library file yet still want to have an instance of this symbol editable If the symbol attribute SpiceModel exists and is the name of a subcircuit in the file specified as lt ModelFile gt then a drop list of all subcircuits names will be available when an instance of the symbol is edited on a schematic Creating New Symbols Symbol Editing Overview Symbols can represent a primitive device such as a resistor or a capacitor a subcircuit libraried in a separate file or another page of the schematic This section describes 29 how to define your own new symbols To start a new symbol use the menu command File g
171. ws different traces to be independently autoscaled Traces can be dragged between panes by 51 dragging the label A copy of a trace can be made on another pane by holding down the control key when you release the mouse button LOTES Technology LTspice SwitcherCAD III astable asc File View Tools Window Help Bu HB J QQQRQ EISE Color Control The menu command Tools gt Color Preferences colors allows you to set the colors used for plotting data You click on an object in the sample plot and use the red green and blue sliders to adjust the colors to your preferences 52 Color Palette Editor LX iz WaveForm x Schematic E Netlist Click on an item above to change its color X Selected Item Trace va OK Selected Item Color Mix Red 0 Green 255 Apply Suec n 0 Defaults Cancel It Attached Cursors There are up to two attached cursors available You can attach a cursor to a trace by left mouse clicking on the trace label You can attach both cursors to a single trace by right clicking on the trace label and selecting lst amp 2nd You can also attach the 1st or 2nd cursor or both cursors to any trace by right clicking on that trace s label and using the Attached Cursor drop down box The attached cursors can be dragged about with the mouse or moved with the cursor keys 53 FX Ble View Toos window Hep PII IEd ASHP
172. ws measurements of currents and voltages that circuii are viri The success of these anal simulation spread to board breadboard simulat Given wh an commercial su well as s mu in order regulator long for Ther cual lly impossible to do any other way simulators has made It is easier in many cases to simul and the abili tion for performance of well understood robust the number of commercially available SPI y should a new simulator be wri alog functions are extremely difficult to simulate wil og circuit ty to anal and probl circuit level circuit design late rather than lyze the circuit in the lems speeds the design ts CE simula Because certain COTS tten ch CE simulators lly available SPI pplies have fast high frequency switching square waves as low overall loop response Commercial have b simula n analog circui shown some success in speedin lation but at a cost of m Switch mode power This means simulations st run for thousands to hundreds of thousands of cycles to see the overall response of a switching lly available SPI this to be a useful simul times for a switch mode power supply n hours for a simulator to be useful CE s simply take too lation method Simulation nust be in minutes not t ak sin g up swi tion methods th
173. y The input logic threshold defaults to 5 Vhight Vlow but can be set with the instance parameter Ref The hold time is equal to the propagation delay The exclusive XOR device has non standard behavior when more than two inputs are used The output is true only when exactly one of all inputs is true Use the associative property of XOR s with multiple XOR devices to implement an XOR block with more than two inputs 103 The Schmitt trigger devices have similar output characteristics as the gates Their trip points are specified with instance parameters Vt and Vh The low trip point is Vt Vh and the high trip point is Vt Vh The gates and Schmitt trigger devices supply no timestep information to the simulation engine by default That is they don t look when they are about to change state and make sure there s a timestep close to either side of the state change The instance parameter tripdt can be set to stipulate a maximum timestep size the simulator takes across state changes The VARISTOR is a voltage controlled varistor Its breakdown voltage is set by the voltage between terminals 1 and 2 Its breakdown impedance is specified with the instance parameter rclamp See the example schematic examples Educational varistor asc The MODULATE device is a voltage controlled oscillator See the example schematic examples Educa
174. y pwrs x y rand x random x round x sgn x sgn x abs x y Random number between 0 and 1 depending on the integer value of x Similar to rand but smoothly transitions between values Nearest integer to x Sign of x Sine of x Hyperbolic sine of x Real part of the square root of X e g sqrt 1 returns O0 not 0 7071071i Interpolate a value for x based on a look up table given as a set of pairs of points Tangent of x Hyperbolic tangent of x Unit step i e lif x gt O else 0 xo AE XC eLhs 0 4 The following operations are grouped in reverse order of precedence o f evaluation Description the expressions to either side to then AND Ope ran d amp Convert Boolean Convert Boolean the expressions to either side to then OR 91 c Convert the expressions to either side to Boolean then XOR True if expression on the left is greater than the expression on the right otherwise false True if expression on the left is less than the expression on the right otherwise false True if expression on the left is less than or equal the expression on the right otherwise false True if expression on the left is greater than or equal the expression on the right otherwise false Rais side ZNWWI loa loa loa loa ti
175. ysis w can be used as a synonym for omega 2 Compute the average or RMS of a trace The waveform viewer can integrate a trace to obtain the average and RMS value over the displayed region First zoom the waveform to the region of interest then move the mouse to the label of the trace hold down the control key and left mouse click F 4 inear Technology LTspice SwitcherCAD III L11074 app n x File view Tools Window Help S x AS EA PI40 QQQR EISES xta Waveform I D1 x Interval Start igs Interval End 98 2607 is Average 848 59mA RMS 1 4583A AVES 40us 60us 80us Right Click to edit expression Control Left Click to integrate 3 Display the Fourier Transform of a Trace You can use the menu command View gt FFT to perform a Fast Fourier transform on various data traces 49 Select Waveforms to include in FFT V n003 C1 I B u1 2 I C u1 11 I C2 I B u1 4 I C u1 12 I C3 I B u1 I C u1 13 D1 I C u1 14 ul n005 I lloact I C u1 1 I C u1 15 V u1 n010 I L1 I C u1 2 I D u1 1 V ul n011 R1 I C u1 5 I D u1 2 a TO 3 V ul n013 R3 I C u1 8 I D u1 5 ul n01 4 I vin I C u1 9 I D u1 V u1 n015 I B u1 1 I C u1 10 W G ul 1 User Defined Functions The menu command Plot Settings gt Edit Plot Defs File allows you to enter your own function definitions and parameter definitions for use in the waveform viewer These functions are kept in

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