Datasheet - NXP Semiconductors
Contents
1. o a oemoer Fue a Dae a a Lue STALIN Time L5 1L TT Jese Ve See e ka ress roid ater Gusha qe TU Ua oey trom rising edge s 1117 10 GASPuseWidhHgh nis OW Pulse vi Lon 9 id DRAM Cycles RAS precharge time thus minimum RAS high time n tc 168 jo Generic Data Read Only taHDR 7 14 Address hold A19 A1 only not 0 after CS BLE rise at tc 12 ns end of Generic Data Read Cycle not code fetch Data Read and Instruction Fetch Cycles 7 8 10 11 12 14 15 Data In Valid setup to ClkOut rising edge 17 18 19 Ds 78 10 14 5 178 ove 810 1 1418 JE io KA Daa Bus Drive Enable Jem Write Cycles we 5 o o Dos 1920 Data VaidprortoStobstow iss oe Mnimum Adress Hold Time afer srobe goes made 5 ns Data hold after strobes CS and BHE BLE high 056 25 ons Reese um a Cd Wait Input WAIT setup stable high or low to ClkOut rising edge WAIT hold stable high or low after ClkOut rising edge NOTE 1 See notes after the 3 3 V AC Timing Table 1999 Sep 24 29 Philips Semiconductors Preliminary specification Single chip 16 b2. Ad ae Note is inactive during all writes 5001282 Figure 13 DRAM Write on 16 Bit Bus also 8 Bit Write 8 Bit Bus 1999 Sep 24 34 Philips Semiconductors Preliminary specification Single chip 16 bit microcontroller Driven by Driven by XA GU v On all cycles on 8 bit bus BHE remains high inactive Note On the external bus ALL XA H4 reads are 16 bit reads If the CPU instruction only specifies 8 bits then the CPU uses the appropriate byte and discards the extra byte Thus 8 Bit Reads and 16 Bit Reads appear to be identical on the bus On an 8 bit bus this will appear as two consecutive 8 bit reads even though the CPU will only use one of the two bytes WARNING Some 8 bit I O devices especially FIFOS cannot operate correctly with 2 bytes being read for a one byte read The most common and least expensive solution is to operate these 8 bit devices on a 16 bit bus and access them in software on all odd byte or all even byte boundaries An added benefit of this tech nique is that byte reads are faster than on an 8 bit bus because only 1 word is fetched a single read instead of 2 consecutive bytes 5001283 Figure 14 Generic SRAM Flash I O Device etc Read 16 Bit 8 Bit on 8 Bit Bus Clkout toHAV N toHAV pe 1 toHAV Note 3 ipis ipis pat tDIH ipis
3. ClkOut 45 CS3 RAS3 46 CS2 RAS2 47 C81 48 1999 Sep 24 5001269 Philips Semiconductors Preliminary specification Single chip 16 bit microcontroller XA H4 LOGIC SYMBOL XA H4 Int2 CS4 RAS4 CS5 RAS5 ResetOut TimerO CS3 RAS3 CS2 RAS2 CST RAS1 50 A19 DRAM A22 A0 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 Wait Size16 Resetin 5001270 1999 24 5 Philips Semiconductors Preliminary specification Single chip 16 bit microcontroller XA H4 XA H4 BLOCK DIAGRAM XA H4 CPU Core 256 Bytes Data SRAM MMR Bus SFR Bus Match Chars DMA RO USART 0 Autobaud Match Chars 1 e Autobaud Match Chars USART2 e Autobaud Match Chars USART3 lt DMA T3 Timer 1 Autobaud DMA TO DMA R1 DMA T1 DMA R2 DMA T2 Watchdog Timer Memory Bus Controller DRAM 6 Chip Selects Controller Dynamic Bus Sizing Dynamic Bus Timing External System Bus 5001271 1999 24 6 Philips Semiconductors Preliminary specification Single chip 16 bit microcontroller 4 4 MEMORY MAPS FFFFFFh Code and Data Intermixed Throughout 16 MB Space 000000h Unified Memory also known as von Neuman architecture 1999 Sep 24 FFFFFFh FFFFFFh Code in Data in Dedicated Dedicated 16 MB Space 16 MB Space 000000h 000000h Harvard Architecture 50012
4. RO 8 8ECh SDLC byte count low register RO 8 8EEh SDLC byte count high and FIFO status Reserved USART3 Read Register 10 8FOh Receive Buffer 8F2h Reserved 8F4h Loop clock status 8F6 8FEh Rx DMA Registers DMA Control Register Ch 0 Rx FIFO Control amp Status Reg Ch 0 Rx Segment Register Ch 0 Rx Buffer Base Register Ch 0 Rx R W 100h Control Register 00h 101h Control amp Status Register 102h Points to 64 k data segment R W Buffer Bound Register Ch 0 Rx Address Pointer Reg Ch 0 Rx 8 104h Wrap Reload Value for A15 A8 A7 A0 reloaded 00h to zero by hardware R W 106h Upper Bound plus 1 on A15 AO 0000h Byte Count Register Ch 0 Rx Data FIFO Register Ch 0 Lo Rx Data FIFO Register Ch 0 Hi Rx DMA Control Register Ch 1 Rx FIFO Control amp Status Register Ch 1 Rx Segment Register Ch 1 Rx 0000h 8 R W 16 108h Current Address pointer A15 AO 0000h Corresponds to A15 AO Byte Count generates 16 interrupt if enabled and byte count exceeded 8 10Ch Byte 0 older 00h R W 10Ch 10Dh Byte 1 younger 00h 10Eh Byte 2 older 00h R W 10Eh 10Fh Byte 3 younger 00h 110h Control Register 111 Control amp Status Register R W 112h Points to 64 k data segment 00h 1999 Sep 24 15 Philips Semiconductors Preliminary specification Single chip 16 bit microcontroller XA H4 Read Write Address s gi Reset MMR Name or
5. Address Pointer Reg Ch 2 Tx 166h 168h Upper Bound plus 1 on A15 0 Current Address pointer A15 AO 0000h 0000h Byte Count Register Ch 2 Tx Data FIFO Register Ch 2 Lo Tx 6 6 6 6 6 15Ch ByteO amp 1 0000h 6 6 6 6 Corresponds to A15 0 Byte Count generates interrupt if enabled and byte count exceeded 16Ch ByteO amp 1 0000h 16Ah 0000h 6 Data FIFO Register Ch 2 Hi Tx DMA Control Register Ch 3 Tx 6 16Eh Byte2 amp 3 0000h 170h Control Register h FIFO Control amp Status Register Ch 3 Tx Segment Register Ch 3 Tx R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W AN 0 R 171h Control amp Status Register 0 1 1 1 15Eh Byte2 amp 3 0000h 8 160h Control Register 8 8 8 1 1 1 1 1 8 8 Oh 00h Buffer Base Register Ch 3 Tx Buffer Bound Register Ch 3 Tx R W 8 172h Points to 64 k data segment Wrap Reload Value for A15 A8 R W 8 174h A7 0 reloaded to zero by hardware Address Pointer Reg Ch 3 Tx Byte Count Register Ch 3 Tx 00h R W 16 176h Upper Bound plus 1 on A15 AO 0000h R W 16 178h Current Address pointer A15 AO 0000h Data FIFO Register Ch 3 Lo Tx Data FIFO Register Ch 3 Hi Tx Corresponds to A15 AO Byte Count generates 16 LAN interrupt if enabled and byte count exceeded 0000h R W 16 17Ch Byte0 amp 1 0000h R W 16 17Eh Byte2 amp 3 0
6. Applications that are described herein for any of these products are for illustrative purposes only Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification Disclaimers Life support These products are not designed for use in life support appliances devices or systems where malfunction of these products can reasonably be expected to result in personal injury Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application Right to make changes Philips Semiconductors reserves the right to make changes without notice in the products including circuits standard cells and or software described or contained herein in order to improve design and or performance Philips Semiconductors assumes no responsibility or liability for the use of any of these products conveys no license or title under any patent copyright or mask work right to these products and makes no representations or warranties that these products are free from patent copyright or mask work right infringement unless otherwise specified Philips Semiconductors Copyright Philips Electronics North America Corporation 1999 811 East Arques Avenue rights reserved Printed in U S A P O Box 3409 Sunnyvale Californi
7. ClkOut tcHav N icHsL D 15 0 Driven by XA EN Note processor can prefetch from one to eight words 5001131 Figure 8 Generic SRAM ROM Flash etc Burst Code Fetch on 16 Bit Bus ClkOut 5001278 Figure 9 Generic SRAM Devices etc Write 1999 Sep 24 32 Philips Semiconductors Preliminary specification Single chip 16 bit microcontroller XA H4 V V E RAS ADDRESS CAS ADDRESS V 5001279 Figure 10 DRAM Single Read Cycle ClkOut tcHav t RAS ADDRESS CAS ADDRESS CAS ADDRESS 2 M M Jo icHSH W D 15 0 Driven by XA Driven by Slave Device s Word from CAS Addr Word from CAS Add 4 Byte Fetch 1 Word 2 Bytes is shown on 16 bit bus burst can be 2 to 16 bytes 1 to 8 words 5001280 Figure 11 DRAM EDO Burst Code Fetch on 16 Bus 1999 Sep 24 33 Philips Semiconductors Preliminary specification Single chip 16 bit microcontroller XA H4 ClkOut toHAV tcHAV V W VV eel tcHSL tCHAH gt 1 tavsL 4 DIS 4 8 Note processor can fetch from one to eight Words 1 2 bytes 5001281 Figure 12 DRAM Fast Page Mode Burst Code Fetch ClkOut Mj
8. Master External Status Even Channel Abort IE 820 7 Interrupt Enable External Status IP WR15 7 WR1 0 RR3 3 81E 7 802 0 826 3 Tx Underrun EOM Tx Underrun EOM IE RRO 6 WR15 6 820 6 81E 6 RRO 5 820 5 SYNC HUNT SYNC RRO 4 XA H4 Only HUNT IE 82214 WR15 4 81E 4 DCD RROJSI 82013 Zero Count Zero Count IE RRO 1 WR15 1 820 1 81E 1 EXCEPTION TRAPS PRECEDENCE Description Vector Address Arbitration Ranking TRAP 0 15 software 0040 007F 1999 Sep 24 26 Philips Semiconductors Preliminary specification Single chip 16 bit microcontroller XA H4 EVENT INTERRUPTS High Priority HSWR3 00BF 00BC EHSWR3 Description Event i Interrupt Vector Interrupt Source Flag Bit Enable Bit SFR Field SFR Arb Rank 17 16 Software Interrupt 3 High Priority Software Interrupt 2 High Priority Software Interrupt 1 High Priority Software Interrupt 0 USART USART2 3 Interrupt USART USARTO Interrupt DMA DMAH Interrupt DMA DMAL Interrupt External Interrupt 2 INT2 Timer 1 External Interrupt 1 External Interrupt 0 IEO INTO SFR 410 1 MMR 200115 HSVVR2 MMR 2001141 HSWR1 MMR 2001131 HSWRO MMR 200112 00BB 00B8 00 7 00 4 00 3 00 0 multiple OR from 00A7 00A4 USART2 amp USART3 multiple OR from 00 00 0 USARTO amp multiple OR from DMA mul
9. Processor can infer the byte count count register count register by the processor thus an interrupt is from the DMA address pointer generated once every n received bytes Asynchronous Byte Count can be calculated by If no character is received Processor specifies time out period between incoming Character software from the DMA address within a specified time out characters If no character is received within that time Time Out pointer period then interrupt a maskable interrupt is generated Asynchronous Byte Count can be calculated by When matched character There are four match registers each incoming character Character software from the DMA address stored in memory is received within that time a maskable interrupt is Match pointer generated When a matched character is stored in memory by DMA a maskable interrupt is generated Data FIFO 3 Data FIFO 2 Data FIFO 1 Data FIFO 0 DMA Control Segment Buffer Base Buffer Bound Address Pointer Byte Count FIFO Control Rx Channel Rx Time Out Data FIFO 3 Data FIFO 2 Data FIFO 1 Data FIFO 0 DMA Control Segment Tx Channel Buffer Base Buffer Bound Address Pointer Byte Count FIFO Control 5001240 Figure 5 Rx Tx Registers 1999 Sep 24 23 Philips Semiconductors Single chip 16 bit microcontroller DMA Registers In addition to the 16 bit Gl
10. These address lines output A19 0 during SRAM etc bus cycles 18 3 DRAMS 4 only are connected only to pins 22 21 18 10 pins A17 to A7 see user manual MIF Chapter for connecting various DRAM sizes the appropriate address values are multiplexed onto these 11 pins for RAS and CAS during DRAM bus cycles D15 DO 42 30 y o Data 15 0 Bi directional data bus D15 DO 27 25 0 0 0 Port 0 Bit 0 or USARTO Sync input output or USARTO output or 1 USARTO TxCIk output 0 1 RTSO Port 0 Bit 1 or USARTO RTS Request To Send output 1 P0 2 50 Port 0 Bit 2 or USARTO CTS Clear To Send input 0 4 TRCIKO Port 0 Bit 4 or USARTO TR clock input P0 5 RTCIKO Port 0 Bit 5 or USARTO RT clock input ms 1999 Sep 24 8 Philips Semiconductors Preliminary specification Single chip 16 bit microcontroller 4 96 rad Transmit data for USARTO md moo 97 RxDo Receive data for USARTO p GPOut GPOut General Purpose Output Bar Similar to GPIO but Push Pull and inverted output only WARNING This output is inverted The polarity of the pin is the opposite of the bit that drives it GPOut 7 pro 68 VO P1 0_RxD2 Port 1 Bit 0 or USART2 RxD input pir 69 VO TxD2 Port 1 Bit 1 USART2 TxD output pra 70 VO P1 2 2 Port 1 Bit 2 USART2 RT Clock input 2 pis 71 VO 1 3 TRCIKZ P
11. tDIH ipis tDIH ce te Note 2 Note 2 Los md Note 2 m BHE remains high inactive for all accesses on an 8 bit bus A burst code fetch can be from 1 to 8 words 1 word 2 bytes a 2 word fetch is shown here 1999 Sep 24 Figure 15 Burst Code Fetch on 8 Bit Bus Generic Memory 35 mja MS Byte Note 2 y N 5001245 Philips Semiconductors Preliminary specification Single chip 16 bit microcontroller 4 tavsL Note OE is inactive during all writes SU01246 Figure 16 Generic 16 Bit Write on 8 Bit Bus ClkOut icHsL P V EDO e INO Y gt tcHAH t tavsL tCHSH CASL CASH stays high 5001284 Figure 17 16 Bit Read 8 Bit Bus DRAM both and EDO 1999 Sep 24 36 Philips Semiconductors Single chip 16 bit microcontroller ClkOut toHAV RAS CAS ADDR CAS ADDR M ADDR M Even ODD tcHSL tCHSL tavsL icHsH icPwH CAS ADDR CASADDR V Even M ODD N Preliminary specification icHsH T toHDE ClkOut Note 2 8 EE s ARE 5 4 Byte Fetch is shown on 8 bit bus burst can be 2 to 16 bytes Data bus is sampled on the rising edge of clock 6 and every three clocks thereafter clo
12. Handbook for a full explanation of the exception structure including event interrupts of the XA CPU Because the High Priority Software Interrupts are not implemented on all XA derivitives they are explained in the XA H4 User Manual XA Core Interrupt Controller DMA Interrupts USARTO USART1 USART2 Interrupt Master Interrupt USART3 Enable Enable Let Disable Bits EA To XA CPU Autobaud 3 0 Timer 1 High Priority Software Ints HSWR 3 0 SU01276 Figure 6 XA H4 Interrupt Structure Overview 1999 Sep 24 Philips Semiconductors Preliminary specification Single chip 16 bit microcontroller XA H4 Table 7 USARTO Interrupts Interrupt structure is the same except for bit locations for all 4 USARTS et Individual Enable Bit Source Bit Group Enable Bit S Group Flag Bit Master Enable Bit Interrupt MMR Hex Offset MMR Hex Offset MMR Hex Offset MMR Hex Offset MMR Hex Offset Rx Character Available RRO 0 WR1 4 3 Even Channel Rx USARTO 1 Master 820 0 802 4 3 RR3 5 Interrupt Enable 826 5 WR9 3 81213 SDLC EOF RR1 7 XA H4 Only 822 7 CRC Framing Error RR1 6 822161 Rx Overrun RR1 5 822 5 Parity Error WR1 2 RR1 4 802 2 82214 Tx Buffer Empty See WR1 1 RRO 2 Tx Interrupt Enable Even Channel Tx IP 820 2 WR1 1 RR3 4 802 1 826141 Break Abort Break RRO 7
13. INTERFACE MIF In the memory or system bus interface terminology generic bus cycles are synonymous with SRAM bus cycles because these cycles are designed to service SRAMs Flash EEPROM peripheral chips etc Chip select output pins function as either CS or RAS DRAMS and thus RAS on X 4H only depending on whether the memory bank has been programmed as generic or DRAM 1999 Sep 24 The XA H4 has a highly programmable memory bus interface with a complete complete onboard DRAM controller Most DRAMs up to 8 per RAS pin SRAMs Flash ROMs and peripheral chips can be connected to this interface with zero glue chips The bus interface provides 6 mappable chip select outputs five of which can be programmed to function as RAS strobes to DRAM CAS generation proper address multiplexing for a wide range of DRAM sizes and refresh are all generated onboard The bus timing for each individual Philips Semiconductors Preliminary specification Single chip 16 bit microcontroller XA H4 memory bank or peripheral can be programmed to accommodate Each memory bank and associated chip select programmed for slow or fast devices generic SRAM Flash ROM peripheral chips etc is capable of supporting a 1 MB address space Each memory bank and its associated RAS chip select in DRAM ppormng P mode output can be programmed to access up to an 8 MB The Memory Interface can be programmed to support both Intel mappable address space in e
14. USART3 Write Register USART3 Write Register 4 z R W 8 8C4h Extended Features Control Xx R 8 8C6h Receive Parameter and Control 00h z USART3 Write Register 5 USART3 Write Register 6 R 8 8C8h Tx Rx miscellaneous parameters amp mode 00h 8 8CAh Tx parameter and control 00h R z USART3 Write Register 7 USART3 Write Register 8 z R W 8 8CCh HDLC SDLC address field or Match Character 0 00h R 8 8CEh HDLC SDLC flag or Match Character 1 Xx USART3 Write Register 9 R W 8 8DOh Transmit Data Buffer R W 8 8D2h Master Interrupt control Xx USART3 Write Register 10 R W 8 8D4h Miscellaneous Tx Rx control register 00h USART3 Write Register 11 8 8D6h Clock Mode Control USART3 Write Register 12 8 USART3 Write Register 13 USARTS Write Register 14 R W XX R W 8D8h Lower Byte of Baud rate time constant 00h R W 8 8DAh Upper Byte of Baud rate time constant 00h USART3 Write Register 15 USART3 Write Register 16 R W 8 8DCh Miscellaneous Control bits Xx R W 8 8DEh External Status interrupt control f8h USART3 Write Register 17 USART3 Read Register 0 R W 8 8E8h Match Character 2 WR16 00h R W 8 8EAh Match Character 3 WR17 00h USART3 Read Register 1 Reserved RO 8 8E0h Tx Rx buffer and external status RO 8 8E2h Receive condition status residue code USART3 Read Register 3 USART3 Read Register 6 8bE4h 8E6h Interrupt Pending Bits USART3 Read Register 7 USART3 Read Register 8
15. through IMO In power down mode the power supply voltage may be reduced to the RAM keep alive voltage Vram This retains the RAM register and SFR contents at the point where power down mode was entered WARNING must be raised to within the operating range before power down mode is exited Interrupts In the XA architecture all exceptions including Reset are handled in the same general exception structure The highest priority exception is of course Reset and is non maskable All exceptions are vectored through the Exception Vector Table in low memory Coming out of Reset these vectors must be stored in non volatile memory based at location 000000 Later in the boot sequence DRAM or SRAM can be mapped into this address space if desired There is a feature in the Memory Controller called Bank Swap that supports replacing the ROM vector table and other low memory with RAM See the XA H4 User Manual for details Philips Semiconductors Single chip 16 bit microcontroller The XA H4 has a standard XA CPU Interrupt Controller implemented with 15 Maskable Event Interrupts Event Interrupts are defined as maskable interrupts usually generated by hardware events However in the XA H4 4 of the 15 Event Interrupts are generated by software writing directly to the interrupt flag bit These 4 interrupts are referred to as High Priority Software Interrupts Preliminary specification XA H4 See the C25 XA Data
16. 000h R W 180 1FEh RESERVED for future DMA Miscellaneous DMA Registers Rx Character Time Out Register Ch 0 Rx Character Time Out Register Ch 1 200h 0 value disables counter interrupt 0 Rx Character Time Out Register Ch 2 Rx Character Time Out Register Ch 3 R W 8 Oh R W 8 202h Same as above for Rx1 00h R W 8 204h Same as above for Rx2 00h Global DMA Interrupt Register GPOut R W 8 206h Same as above for Rx3 00h R W 16 210h DMA Interrupt Flags 0000h GPOut 7 drives pin 98 GPOut through an inverter R W 8 260h GPOut 6 0 are unused and must be written with 8xh zeroes BDAEE H4 Only Autobaud Registers H4 Only BDCS H4 Only 1999 Sep 24 R W 8 270h Autobaud echo enable H4 Only 00h R W 8 272h Autobaud Control and Status H4 Only 00h 17 Philips Semiconductors Preliminary specification Single chip 16 bit microcontroller XA H4 MMR Name emo Size js Description e Memory Interface MIF Registers BOCFG R W 8 280h MIF Bank 0 Config OFh BOTMG 8 282h MIF Bank 0 Timing Params um LX EE j B1AM 285h MIF Bank 1 Base Address m ar s fr ne B2CFG R W 8 288h MIF Bank 2 Config Fs pce fea ie B2TMG R W 8 28Ah MIF Bank 2 Timing Params a MN RR R W 8 28Dh MIF Bank 3 Base Address a a Desire B4CFG R W 8 290h MIF Bank 4 Config i pom peser B4TMG R W 8 292h MIF Bank 4 Timing Params L
17. 12Fh Byte 3 younger 00h DMA Control Register Ch 3 Rx R W 8 130h Control Register 00h FIFO Control amp Status Register Ch 3 Rx R W 8 131h Control amp Status Register 00h Segment Register Ch 3 Rx RW 8 132h Points to 64 k data segment Wrap Reload Value for A15 A8 A7 0 reloaded to Buffer Base Register Ch 3 Rx R W E 134h zero by hardware Buffer Bound Register Ch 3 Rx R W 16 136h Upper Bound plus 1 on A15 AO 0000h Address Pointer Reg Ch 3 Rx R W 16 138h Current Address pointer A15 AO 0000h Corresponds to A15 Byte Count generates Byte Count Register Ch 3 Rx iis 13Ah interrupt if enabled and byte count exceeded 0000h 13Ch Byte 0 older 00h Data FIFO Register Ch 3 Lo Rx R W 16 13Ch 13Dh Byte 1 younger 00h 13Eh Byte 2 older 00h Data FIFO Register Ch 3 Hi Rx R W 16 13Eh 13Fh Byte 3 younger 00h DMA Control Register Ch 0 Tx Tx DMA Registers 140h Control Register 00h R i e S FIFO Control amp Status Register Ch 0 Tx R W 8 141h Control amp Status Register Segment Register Ch 0 Tx R W 8 142h Points to 64 k data segment 00h i Wrap Reload Value for A15 A8 A7 A0 reloaded Buffer Base Register Ch 0 Tx R W 8 144h to zero by hardware 00h Buffer Bound Register Ch 0 Tx R W 146h Upper Bound plus 1 on A15 AO 0000h Address Pointer Reg Ch 0 Tx 148h Current Address pointer A15 AO 0000h Corresponds to A15 0 Byte Count generates Byte Cou
18. 4 8 trp is specified as the minimum high time thus inactive on each of the 5 individual CS_RAS 5 1 pins when such pin is programmed in the memory controller to service DRAM The number of CClks system clocks in tap is programmable and is represented by in the tap equation in the AC tables Regardless of what value is programmed into the control register n will never be less than 2 clocks Thus at 30 Mhz system clock the minimum value for RAS precharge is tRP 2 tc 16 2 33 33 16 50 6 ns As the system clock frequency Fc is slowed down tc system clock period of course becomes greater and thus tap becomes greater 9 The MIN value for this parameter is guaranteed by design and is not tested in production to the specified limit In those cases where a maximum value is specified in the table for this parameter it is tested TIMING DIAGRAMS references to numbered Notes are to the notes following the AC Electrical Characteristics tables ClkOut tCHSL Does Include 0 cs 4 pe Note 2 Note Generic Data Reads 0 can terminate a full clock period before 19 1 and therefore should not be used on some peripheral devices 5001277 Figure 7 Generic SRAM ROM Flash 1 Devices etc Read 16 Bit Bus 1999 Sep 24 31 Philips Semiconductors Preliminary specification Single chip 16 bit microcontroller XA H4
19. 72 Philips Semiconductors Preliminary specification Single chip 16 bit microcontroller XA H4 PIN DESCRIPTIONS Lqfp R See Vss Ground 0 V reference Power Supply This is the power supply voltage for normal idle and power down operation Reset A low this pin resets the microcontroller causing VO ports and peripherals to take on Resetin 55 their default states and the processor to begin execution at the address contained in the reset vector VVAITI 52 Wait Size16 During Reset this input determines bus size for boot device 1 16 bit boot Size16 device 0 8 bit During normal operation this is the Wait input 1 Wait 0 Proceed XTALIn Crystal 1 Input to the inverting amplifier used in the oscillator circuit and input to the internal clock generator circuits XTALOut Crystal 2 Output from the oscillator amplifier Chip Select 0 This output provides the active low chip select to the boot device usually ROM or Flash It cannot be connected to DRAM From reset it is enabled and mapped to an address range based at 000000h It can be remapped by software to a higher base in the address map see the Memory Interface chapter in the XA H4 User Manual Chip Select 1 or RAS1 Chip Selects and RAS 1 through 5 come out of reset disabled They can be programmed to function as normal chip selects or as RAS strobes to DRAM 51 can be swapped with CSO see the SWAP operation and control bi
20. Bit 1 or CS5 output or USART1 Request To Send output Active low chip selects CS1 through CS5 come out of reset disabled They can be programmed to P3 1 57 VO function as normal chip selects or as RAS strobes to DRAM CS2 through CS5 are not used with the SWAP operation see the Memory Controller chapter in the 4 User Manual They mappable to any region of the 16 MB address space P3 2 TimerO ResetOut Port 3 Bit 2 TimerO input or output ResetOut output ResetOut If the ResetOut function is selected this pin outputs a low whenever the XA H4 processor is reset by an internal source Watchdog Reset or the RESET instruction P3 2 58 WARNING Unlike the other 31 GPIO pins during power up reset this pin can output a strongly driven low pulse The duration of this low pulse ranges from 0 ns to 258 system clocks starting at the time that Vcc is valid The state of the Resetin pin does not affect this pulse When used as GPIO this pin can be driven low by software without resetting the 63 P3 3_Timer1_BRG1_Synct Port 3 Bit or Timer1 input or output or USART1 BRG output or USART1 Sync rm or output P3 4 CTS1 Port 3 Bit 4 or USART1 Clear To Send input pas 65 VO 5 RxDt Port Bit 5 or Receive Data input pnm pse 6 VO P3 6 TxD1 Port 3 Bit 6 or USART1 Transmit Data output ERE par 67 VO Inti Port
21. Bit 7 or External Interrupt input or USART1 TR Clock input m2 78 10 CD1 Int2 USART1 Carrier Detect or External Interrupt 2 External Interrupt 0 NOTES 1 See XA H4 User Guide Pins Chapter for how to program selection of pin functions 2 RTClk input is usually used for Rx Clock if an external clock is needed but can be used for either Rx or Tx or both TRCIk is usually used for Tx Clock but can be used for Rx or Tx or both 1999 Sep 24 9 Philips Semiconductors Single chip 16 bit microcontroller CONTROL REGISTER OVERVIEW There are two types of control registers in the XA H4 these are SFRs Special Function Registers and MMRs Memory Mapped Registers The SFR registers with the exception of MRBL MRBH MICFG BCR BRTH BRTL and RSTSRC are the standard XA core registers See WARNINGS about BCR BRTH and BRTL in Table 2 SFRs are accessed by direct addressing only see C25 XA User Manual for direct addressing The MMRs are specific to the XA H4 Table 2 Special Function Registers SFR Preliminary specification on chip peripherals can be accessed by any addressing mode that can be used for off chip data accesses The MMRs are implemented in a relocatable block See the Memory Controller chapter in the XA H4 User Manual for details on how to relocate the MMRs by writing a new base address into the MRBL and MRBH MMR Base Low and High registers SFR B
22. CFGA 2 P3CFGA POCFGB P1CFGB P2CFGB P3CFGB PSWH PSWL PSW51 RSTSRC RTHO RTH1 RTLO RTL1 SCR 1999 Sep 24 Port 0 Configuration A Port 1 Configuration A Port 2 Configuration A Port 3 Configuration A Port 0 Configuration B Port 1 Configuration B Port 2 Configuration B Port 3 Configuration B Power Control Reg Program Status Word High Program Status Word Low 80C51 Compatible PSW Reset Source Reg Timer 0 Reload High Timer 1 Reload High Timer 0 Reload Low Timer 1 Reload Low System Configuration Reg Segment Selection Reg Software Interrupt Enable Timer 0 1 Control Timer 0 High Timer 1 High Timer 0 Low Timer 1 Low Timer 0 1 Mode Preliminary specification 227 226 225 224 223 222 221 220 Js pape i 2 229 2 28 29 28 Co ERR UN 217 216 215 214 213 212 211 210 c s T ro v mom Row 21F 21E 21D 21C 21B 21A 219 218 sues wes swes sues ower Sve sw sw sues sui ooh 11 XA H4 Philips Semiconductors Preliminary specification Single chip 16 bit microcontroller XA H4 Bit Functions and Addresses Description SFR Reset Address MSB LSB Value TSTAT Timer 0 1 Extended Status 00h W NO BON 00h X X DL Watchdog Time
23. IFO buffer internal to the DMA channel 9 Rx Char Time Out Register RXCTOR Rx DMA channels only Holds the initial value for an 8 bit character timeout countdown timer which can generate an interrupt Four USARTS 9 Asynchronous features Asynchronous transfers up to 921 6 kbps Can monitor input stream for up to four match characters per receiver H4 only 5 6 7 or 8 data bits per character 1 1 5 or 2 Stop bits per character Even or Odd parity generate and check Parity Rx Overrun and Framing Error detection Break detection Supports hardware Autobaud detection and response up to 921 6 kbps SDLC HDLC features Automatic Flag and Abort Character generation and recognition Automatic CRC generation and checking can be disabled for pass thru Automatic zero bit insertion and stripping Automatic partial byte residue code generation 14 bit Packet byte count stored in memory with received packet by DMA 1999 Sep 24 24 Preliminary specification Synchronous character oriented protocol features only Automatic CRC generation and checking External Sync option Data encoding decoding options Biphase Space FM1 Biphase Mark NRZ NRZI Programmable Baud Rate Generator 9 Auto Echo and Local Loopback modes Autobaud Detectors Each USART has its own Autobaud detector capable of baud rate detection up to 921 6 kbaud The detectors can be prog
24. INTEGRATED CIRCUITS DATA V 4 Single chip 16 bit microcontroller Preliminary specification 1999 Sep 24 IC28 Data Handbook Philips PHILIPS Semiconductors H LI DS Philips Semiconductors Preliminary specification Single chip 16 bit microcontroller XA H4 DESCRIPTION The powerful 16 bit XA CPU core and rich feature set make the XA H3 and XA H4 devices ideal for high performance real time applications such as industrial control and networking By supporting of up to 32 MB of external memory these devices provide a low cost solution to embedded applications of any complexity Features like DMA memory controller and four advanced USARTS help solve I O intensive tasks with a minimum of CPU load FEATURES Large Memory Support De multiplexed Address Data Bus 9 Six Programmable Chip Selects Support for Unified Memory allows easy user modification of all code External ISP Flash support for easy code download Dynamic Bus Sizing each of 6 Chip Selects be programmed for 8 bit or 16 bit bus The XA H3 feature set is a subset of the XA H4 see Table 1 The XA H3 H4 devices are members of the Philips XA eXtended Architecture family of high performance 16 bit microcontrollers The XA H3 and XA H4 are designed to significantly minimize the need for external components Dynamic Bus Timing each of 6 chip selects has individual programmable bus timing 32 Progr
25. Pin Low Profile Quad Flat Package LQFP 30 SOT407 1 NOTE K 30 MHz F 40 to 85 BE LQFP 1999 Sep 24 3 Philips Semiconductors Preliminary specification Single chip 16 bit microcontroller XA H4 PIN CONFIGURATION DRAM CAS bits NOTE Address lines output during various DRAM CAS cycles are shown in parenthesis See DRAM Controller chapter in User Manual for details goj 0 0 Synco BRGO 0 2 CTSO RTSO 2 6 RTS3 2 5 CTS3 Po 3 CDO PO 4 gal P2 4 CD3 P2 7 Sync3 BRG3 PO 5 RTCIKO P2 2 RTCIK3 TxD3 P2 0 RxD3 into 78 CD1 Int2 92 91 83 2 3 ComCIk TRCIK3 97 RxDO 81 80 79 7 BRG2 Sync2 6 RTS2 5 CTS2 4 CD2 3 2 2 RTCIK2 I TxD2 0 A1 MOLD MARK A2 A3 A4 A5 A6 A7 A21 22 UU UU UU 0 RxD2 P3 7 Int IN Io Jou e P3 6 TxD1 8 A19 A20 5 RxD1 A9 A0 A18 4 P3 4 CTS1 A10 Top View 100 Pin LQFP Base Part Number 11 A2 Current Part 4 VDD A12 A3 K 30 MHz 40 to 485 C BE LQFP pkg XTALOUT LQFP Package SOT407 1 A13 A4 XTALIN P3 3 Timer BRG1 Synci A14 A5 VSS A15 A6_A22 P3 2_Timer0_ResetOut vss P3 1_CS5_RAS5_RTS1 VDD A16 A7_A20_A21 A17 A8 A18 A19 A18 A19 DO MOLD MARK P3 0 CS4 Reset In BLE CASL BHE CASH WAIT Size16 OE 50 49 WE 50
26. Read Only Size Offset Description Value Wrap Reload Value for A15 A8 A7 AO reloaded Buffer Base Register Ch 1 Rx R W ES 114h to zero by hardware Buffer Bound Register Ch 1 Rx R W 16 116h Upper Bound plus 1 on A15 AO 0000h Address Pointer Reg Ch 1 Rx R W 16 118h Current Address pointer A15 AO 0000h Corresponds to A15 Byte Count generates Byte Count Register Ch 1 Lid is TIAN interrupt if enabled and byte count exceeded nen 11Ch Byte 0 older 00h Data FIFO Register Ch 1 Lo Rx R W 16 11Ch 11Dh Byte 1 younger 00h 11Eh Byte 2 older 00h Data FIFO Register Ch 1 Hi Rx R W 16 11Eh 11Fh Byte 3 younger 00h DMA Control Register Ch 2 Rx R W 8 120 Control Register FIFO Control amp Status Register Ch 2 Rx R W 121 Control amp Status Register Segment Register Ch 2 Rx RW 8 122h Points to 64 k data segment Wrap Reload Value for 15 A8 A7 reloaded to Buffer Base Register Ch 2 Rx R W E 124h zero by hardware Buffer Bound Register Ch 2 Rx 126h Upper Bound plus 1 on A15 AO 0000h Address Pointer Reg Ch 2 Rx R W 16 128h Current Address pointer A15 AO 0000h Corresponds to A15 0 Byte Count generates Byte Count Register Ch 2 PME Ton interrupt if enabled and byte count exceeded 12Ch Byte 0 older 00h Data FIFO Register Ch 2 Lo Rx R W 16 12Ch 12Dh Byte 1 younger 00h 12Eh Byte 2 older 00h Data FIFO Register Ch 2 Hi Rx R W 16 12Eh
27. USART2 Write Register 7 R W 8 88Eh HDLC SDLC flag or Match Character 1 XX USART2 Write Register 9 R W 8 892h Master Interrupt control XX USART2 Write Register 11 R W 8 896h Clock Mode Control XX USART2 Write Register 13 R W USART2 Write Register 14 USART2 Write Register 15 8 89Ah Upper Byte of Baud rate time constant 00h R W 8 89Ch Miscellaneous Control bits XX USART2 Write Register 16 USART2 Write Register 17 USART2 Read Register 0 USART2 Read Register 1 Reserved USART2 Read Register 3 see WR16 and WR17 USART2 Read Register 6 USART2 Read Register 7 USART2 Read Register 8 Reserved USART2 Read Register 10 Reserved 1999 Sep 24 R W 89Eh External Status interrupt control f8h R W Ho RC Match Character 2 WR16 00h RW 8 S8AAh Match Character WR17 s m R buferamBexemalstaus s ean Receive condionsaus J 9m LL Ro san mempPexmgBis s sach s sh SDLCbytecountiowregister 78 saen SDLC byte count hign and FIFO sus s son ReweBe _ sm CSCC s sem toposes ses 14 Philips Semiconductors Preliminary specification Single chip 16 bit microcontroller XA H4 MMR Name oad on Size jeg Description e USARTS Write Register 0 USARTS Registers USARTS Write Register 1 USARTS Write Register 2 R W 8 8COh Command register 00h R W 8 8C2h Tx Rx Interrupt amp data transfer mode XX
28. a 94088 3409 Date of release 09 99 Telephone 800 234 7381 Document order number 9397 750 06432 Left make things PHILIPS
29. ammable General Purpose I O Pins 9 Four USARTS with 230 4 kbps capability Eight DMA Channels ADDITIONAL XA H4 FEATURES NOT AVAILABLE ON XA H3 Complete DRAM controller supports up to four banks of 8 MB each Memory controller supports 16 MB in Unified Mode Memory controller supports 32 MB in Harvard Mode 9 Serial ports are USARTs Synchronous capability up to 1 Mbps and include HDLC SDLC support 1999 Sep 24 Four Match Characters are supported on each USART in Async Mode Hardware Autobaud on all four USARTs in Async Mode USARTS are improved 85C30 style Philips Semiconductors Preliminary specification Single chip 16 bit microcontroller 4 Table 1 XA H3 features comparison 02 Kana k Harvard Memory Mode 16 MB Code 16 MB Data Unified Memory Mode WAOmmes Programeve rip Sefes 5 LLL Interrupts programmable priority 7 Standard SW 7 Standard SW 4 High Priority SW 4 High Priority SW 9 Hardware Event 9 Hardware Event Serial Ports 4 UARTs 4 USARTs Maximum Serial Data Rates asynch to 230 4 kbps no sync asynch to 230 4 kbps sync to 1 Mbps Match Characters 4 async chars per USART Hardware Autobaud up to 230 4 kbps NOTE 1 Can be used as additional counters if not needed as BRGs ORDERING INFORMATION ROMless Only Temperature range and Package Freq MHz Package Drawing Number PXAH40KFBE 40 to 85 C 100
30. cessor loads byte count into DMA DMA sends each fragment Tx DMA stops that number of bytes generates maskable interrupt and stops Periodic Interrupt Porcessor loads Byte Count Register When Byte Counter DMA runs until commanded to stop by processor only once reaches zero and is Every time byte counter rolls over a new reloaded by DMA maskable interrupt is generated hardware from the byte count register 1999 Sep 24 22 Philips Semiconductors Preliminary specification Single chip 16 bit microcontroller 4 Receive DMA Channel Modes The Rx DMA channels have four DMA modes specifically designed summarized in Table 6 For full details on implementation and use for various applications of the attached USARTs These modes are see the XA H4 User Manual Table 6 Rx DMA modes summary SDLC HDLC DMA stores byte count in headerin At end of received packet When a complete or aborted SDLC HDLC packet has Rx Chaining memory with data packet been received the packet byte count and status information are stored in memory with the packet A maskable interrupt is generated Periodic Loaded by processor into DMA When Byte Counter reaches The DMA channel runs until commanded to stop by the Interrupt used only to determine the number zero and is reloaded by processor It generates a maskable interrupt once per n of bytes between interrupts DMA hardware from the byte bytes where n is the number written once into the byte
31. cks 6 9 12 and 15 in this example Figure 18 DRAM FPM Fast Page Mode Burst Code Fetch on 8 Bit Bus W W W W CAS ADDR CAS ADDR _ rasaooness fl s ue 1999 Sep 24 tavsL tcHSL CE Soe Wl sss tcHSH icHsL 4 Byte Fetch is shown on 8 bit bus burst can be 2 to 16 bytes To meet Hold Time EDO DRAM drives Data until OE rises or until a new falling edge of CAS CAS ADDR EVEN CASADDR V M ODD A Data bus is sampled on the rising edge of clock 6 and every three clocks thereafter clocks 6 8 10 and 12 in this example Figure 19 EDO DRAM Burst Code Fetch on 8 Bit Bus 37 5001285 SU01286 Philips Semiconductors Preliminary specification Single chip 16 bit microcontroller 4 ClkOut icHsL W m NECCNE LI M tchan 7 lavsL 5001287 Figure 20 DRAM 16 Bit Write 8 Bit Bus FPM or EDO DRAMs RAS and CAS terminate together The active low portion of RAS can be programmed to last from 3 to 6 clock cycles The high portion of RAS after Refresh can be programmed to last from 2 to 4 clock cycles See Chapter 3 of the XA H4 User Manual 5001588 Figure 21 REFRESH RAS NOTE trp minimum is specified for each of the 5 individual RAS pins 5 RAS 5 1 It is the minimum h
32. e cause of the last XA reset One bit will be set to 1 the others will be 0 RSTSRC 7 enables the ResetOut function 1 Enabled 0 Disabled See XA H4 User Manual for details RSTSRC 7 differs in function from most other XA derivatives The XA guards writes to certain bits typically interrupt flags that may be written by a peripheral function This prevents loss of an interrupt or other status if a bit was written directly by a peripheral action between the read and write of an instruction that performs a read modify write operation 4 SFR bits that are guarded in this manner are TF1 TFO IE1 and IEO in and WDTOF WDCON 1999 Sep 24 12 Philips Semiconductors Preliminary specification Single chip 16 bit microcontroller 4 Table 3 Memory Mapped Registers MMR Name Size Description rei USARTO Registers USARTO Write Register 0 R W 8 800h Command register 00h USARTO Write Register 1 R W 8 802h Tx Rx Interrupt amp data transfer mode USARTO Write Register 3 R W 8 806h Receive Parameter and Control 00h USARTO Write Register 5 R W 8 80Ah Tx parameter and control 00h USARTO Write Register 7 RAW 8 80Eh HDLC SDLC flag or Match Character 1 Xx USARTO Write Register 9 mw sm fe USARTO Write Register 10 USARTO Write Register 11 USARTO Write Register 12 USARTO Write Register 13 R W R W R W 814h Miscellaneous Tx Rx c
33. e read Some 8 bit VO devices especially FIFOs cannot operate correctly with 2 bytes being read for a 1 Byte Read The most common and least expensive solution is to operate these 8 bit devices on a 16 bit bus and access them in software on all odd byte or all even byte boundaries An added benefit of this technique is that byte Reads are faster than on an 8 bit bus because only 1 word is fetched a single Read instead 2 consecutive bytes 1999 Sep 24 20 Philips Semiconductors Preliminary specification Single chip 16 bit microcontroller XA H4 Clock Output The ClkOut pin allows easier external bus interfacing in some ClkOut to be output enabled at reset but it may be turned off situations This output reflects the XTALIn clock input to the XA tri state disabled by software via the MICFG MMR referred to internally as or System Clock but is delayed to WARNING The capacitive loading on this output must not match the external bus outputs and strobes The default is for exceed 40 pf 128 k x 8 ROM 256 k x 16 DRAM HM514260DI 1 16 DRAM MT4C1M16C3 32kx 16 SRAM NOTE The 16 bit wide RAM does not need the 0 pin from the processor During byte writes to the RAM the 0 value will cause either BLE or BHE pin to go active from the XA H3 but not to both For all Word Writes Wo
34. ernal appear to the XA as external resets See the XA H4 User Manual for a full discussion of the reset functions Resetin The Resetin function is the standard XA G3 Resetin function The Resetin signal does NOT get passed on to ResetOut See the XA H4 User Manual for details on reset RSTSRC Reg Type and Address SFR 463h Not Bit Addressable Reset Value see below MSB Preliminary specification ResetOut The P3 2 ResetOut pin provides an external indication if the ResetOut function is enabled in the RSRSRC register via an active low output when an internal reset occurs internal reset is Reset instruction or Watchdog time out If the ResetOut function is enabled the ResetOut pin will be driven low when a Watchdog reset occurs or the Reset instruction is executed This signal may be used to inform other devices in the system that the XA H4 has been internally reset The Resetin signal does NOT get passed on to ResetOut When activated the duration of the ResetOut pulse is 256 system clocks WARNING At power on time from the time that power coming up is valid the 3 2 Timero ResetOut pin may be driven low for any period from zero nanoseconds up to 258 system clocks This is true independently of whether Resetln is active or not Reset Source Register The Reset Source Identification Register RSTSRC indicates the cause of the most recent XA reset The cause may have been an exte
35. for all odd or even address accesses BHE CASH will not go active during any accesses on an 8 bit bus 2 The bus timing is designed to make meeting hold time very straightforward without glue logic On all generic reads and fetches in order to meet hold time the slave should hold data valid on the bus until the earliest of CS BHE BLE OE goes high inactive or until the address changes On all FPM DRAM reads and fetches hold data valid on the bus until a new CAS is asserted or until OE goes high inactive To avoid 3 State fights during read cycles and fetch cycles do not drive data bus until OE goes active To meet hold time EDO DRAM drives data onto the bus until OE rises or until a new falling edge of CAS WARNING ClkOut is specified at 40 pF max More than 40 pf on ClkOut may significantly degrade the ClkOut waveform Load capacitance for all outputs except ClkOut 80 pF Not all combinations of bus timing configuration values result in valid bus cycles Please refer to the XA H4 User Manual for details When code is being fetched on the external bus a burst mode fetch is used This burst can be from 2 to 16 bytes long On a 16 bit bus A1 are incremented for each new word of the burst On an 8 bit bus are incremented for each new byte of the burst code fetch Ls 5 a Pw 1999 Sep 24 30 Philips Semiconductors Preliminary specification Single chip 16 bit microcontroller XA H
36. gister 10 R W 8 854h Miscellaneous Tx Rx control register 00h USART1 Write Register 12 R W 8 858h Lower Byte of Baud rate time constant 00h 13 Philips Semiconductors Preliminary specification Single chip 16 bit microcontroller XA H4 MMR Name or Orb Size jg Description un USART1 Write Register 14 USART1 Write Register 15 USART1 Write Register 16 USART1 Write Register 17 R W 85Ch Miscellaneous Control bits R W 8 85Eh External Status interrupt control Rw 8 868h__ Match Character 2 WR16 USART1 Read Register 0 USART1 Read Register 1 R W 8 86Ah Match Character 3 WR17 00h RO 8 860h Tx Rx buffer and external status Reserved USART1 Read Register 3 862h Receive condition status residue code 864h see WR16 and WR17 USART1 Read Register 6 8 866 Interrupt Pending Bits 8 86Ch see WR16 and 17 above USART1 Read Register 7 USART1 Read Register 8 RO 8 86Eh SDLC byte count low register R 8 86Eh SDLC byte count high and FIFO status Reserved USART1 Read Register 10 870h Receive Buffer 872h Reserved 874h Loop clock status 876 87Eh USART2 Registers USART2 Write Register 0 R W 8 880h Command register 00h USART2 Write Register 1 R W 8 882h Tx Rx Interrupt amp data transfer mode XX USART2 Write Register 2 R W 884h XX USART2 Write Register 3 R W 8 886h Receive Parameter and Control 00h USART2 Write Register 5 R W 8 88Ah Tx parameter and control 00h
37. i fazor B5AM R W 8 295h MIF Bank 5 Base Address Lii Fi pcm gens MBCL R W 8 2BEh MIF Memory Bank Configuration Lock Register E Ls pip mm Deme J Miscellaneous Registers Hi Pri Soft Ints amp Pin Mux Control Reg 0 2DOh Control bits for Hi Priority Soft Ints and Pin Mux 0000h XInt2 2D2h External Interrupt 2 Control 00h FUNCTIONAL DESCRIPTION The XA H4 functions are described in the following sections Because all blocks are thoroughly documented in either the C25 XA Data Handbook or the XA H4 User Manual only brief descriptions are given in this datasheet in conjunction with references to the appropriate document XA CPU The CPU is a 30 MHz implementation of the standard XA CPU core See the XA Data Handbook 1C25 for details The CPU core is identical to the G3 core See the caveat in the next paragraph about the Bus Interface Unit Internal CPU Bus Bus Interface Unit BIU emoy 4 Marana us Interface Unit and JO Bus ontroller x8 This is the internal Bus not the bus at the pins This internal bus connects the CPU to the MIF Memory and DRAM Controller WARNING Immediately after reset always write BTRH 51h followed by BTRL 40h in that order Once written do not change Figure 1 XA CPU core BIU Bus Interface Unit the values in these registers Follow these two writes with five NOPS Never write to the BCR register It co
38. igh time thus RAS inactive between two DRAM bus cycles on the same RAS 5001289 Figure 22 RAS Time 1999 Sep 24 38 Philips Semiconductors Single chip 16 bit microcontroller 1999 Sep 24 XTALIN 4 tcHcx pe tcLcH Preliminary specification Figure 23 External Clock Input Drive ClkOut WARNING ClkOut is specified into 40 pF max do not over Figure 24 ClkOut Duty Cycle ClkOut tws Setup time of WAIT to rising edge of ClkOut Hold time of WAIT after ClkOut High Figure 25 External WAIT Pin Timing 39 5001146 5001147 5001148 Philips Semiconductors Preliminary specification Single chip 16 bit microcontroller LQFP100 plastic low profile quad flat package 100 leads body 14 x 14 x 1 4 mm SOT407 1 DIMENSIONS mm are the original dimensions Note 1 Plastic or metal protrusions of 0 25 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN ISSUE DATE 1999 Sep 24 40 Philips Semiconductors Preliminary specification Single chip 16 bit microcontroller 4 5 1999 Sep 24 41 Philips Semiconductors Preliminary specification Single chip 16 bit microcontroller Data sheet status Data sheet Product Definition 1 status status Objective Development This data sheet contains the design ta
39. it Functions and Addresses Reset Bus Configuration Reg RESERVED see Warning BTRH Bus Timing Reg High WARNING Never write to the BCR register in the it is initialized to 07h the only legal value This is not the same as for some other XA derivatives WARNING Immediately after reset always write BTRH 51h followed by writing BTRL 40h in that order Follow these two writes with five NOPS This is BTRL Bus Timing Reg Low MRBH ClkOut Tri St Enable not the same as for some other XA derivatives MRBL MMR Base Address Low 15 Ma MMR Base Address High 23 16 1 Enabled Code Segment Data Segment Extra Segment Interrupt Enable High Interrupt Enable Low Interrupt Priority AO Interrupt Priority A1 Interrupt Priority A2 Interrupt Priority A3 Interrupt Priority A4 Interrupt Priority A5 Interrupt Priority A6 Interrupt Priority A7 33F 33E 33D 33C 33B 33A 339 338 Jese eese ess sse 337 336 335 334 333 332 331 330 e e m J 1 E P o onem 387 386 385 384 383 382 381 380 EE E 1 1999 Sep 24 Philips Semiconductors Single chip 16 bit microcontroller Bit Functions and Addresses Description SFR Reset Address MSB LSB Value POCFGA P1
40. it microcontroller XA H4 AC ELECTRICAL CHARACTERISTICS 3 3 V 10 Vpp 3 3 V 10 Tamp 40 C to 85 C industrial james rem ae Tos T L Min All Cycles o Fo System Clock internally called CCIK Frequency Po 30 amp 8 WmemcekPebde ww 25 XTALIN Rise Time umm 111217481920 OWSPusewanHgs uw 9 OSRieWdhiw DRAM Cycles RAS precharge time thus minimum RAS high time n tc 168 m Data Read Only 7 14 Address hold A19 A1 only not AO after CS BLE rise at ic 12 ns end of Data Read Cycle not code fetch Data Read and Instruction Fetch Cycles 7 8 10 11 12 14 15 Data In Valid setup to ClkOut rising edge pope 17 18 19 7 8 10 14 15 17 18 Data In Valid hold after ClkOut rising edge 2 0 8 10 11 14 18 OE high to XA Data Bus Driver Enable 6 19 Write Cycles um 5 mwewwavad ww 1620 Data ValdprortoStobetow Lt Mime Aadress Hold Tre ater stebo goes nacie to 25 Data hold after strobes CS and BHE BLE high 16 25 9Seemem Wait Input NOTE 1 On a 16 bit bus if only one byte is being written then only one of BLE CASL or BHE CASH will go active On an 8 bit bus BLE CASL goes active
41. ither EDO or FPM DRAM modes up style and 68000 bus style SRAMs and peripherals to a total of 32 MB of DRAM WARNING Future 4 derivatives may not support separate code and data spaces CS5 or RASS or P3 1 RTS1 CS4 or RASA or P3 0 RTCIk1 CS3 or RAS3 Memory Interface DRAM Controller 52 or RAS2 SRAM Controller CST or RAST Dynamic Bus Sizing Progammable Bus Timing CSO 19 0 DRAM cycle 22 0 Time Multiplexed for RAS CAS D15 DO WAIT SIZE16 5001274 Figure 3 Memory bus interface signal pins Bus Interface Pins Chip Select Pins For the following discussion see Figure 3 There are six chip select pins CS5 CS0 mapped to six sets of bank control registers The following attributes are individually programmable for each bank and associated chip select or RAS if DRAM bank on off address range external device access time detailed bus strobe sequence DRAM cycle or generic bus cycle DRAM size if DRAM and bus width Pin 50 is always generic in order to service the boot device thus 50 cannot be connected to DRAM WARNING On the external bus ALL XA H4 reads 16 bit Reads If the CPU instruction only specifies 8 bits then the CPU uses the appropriate byte and discards the extra byte Thus 8 Bit Reads and 16 Bit Reads appear to be identical on the bus On an 8 bit bus this will appear as two consecutive 8 bit reads even though the CPU instruction specified a byt
42. its RFSH Refresh Timing Contains the refresh time constant and DRAM Refresh Timer enable bit 8 bits EIGHT CHANNEL DMA CONTROLLER The XA H3 H4 has eight DMA channels one Rx DMA channel Transmit DMA Channel Modes dedicated to each USART Receive Rx channel and one Tx DMA The four Tx channels have four DMA modes specifically designed channel dedicated to each USART Transmit Tx channel All DMA for various applications of the attached USARTs These modes are channels are optimized to support memory efficient circular data summarized in Table 5 Full details for all DMA functions can be buffers in external memory All DMA channels can also support found in the DMA chapter of the XA H4 User Manual traditional linear data buffers Table 5 Tx DMA modes summary Non SDLC HDLC Header in memory DMA channel picks up header from memory at the Tx Chaining end of transmission If the byte count in the header is greater than zero then DMA transmits the number of bytes specified in the byte count If byte count equals 0 then a maskable interrupt is generated This process repeats until the byte count in the data header is zero See XA H4 User Manual for details SDLC HDLC Header in memory End of packet not end Same as above except DMA header distinguishes Tx Chaining of fragment between fragment of packet and full pack See XA H4 User Manual for details Stop on TC Processor loads Byte Count Register for Byte count completed Pro
43. mes out of reset initialized to 07h which is the only value that will work Timers 0 and 1 Timers 0 and 1 are the standard XA G3 Timer 0 and 1 Each has an associated I O pin and interrupt See the XA G3 data sheet in the C25 XA Data Handbook for details Many XA derivatives include a standard XA Timer 2 and standard UARTs These blocks have been removed in order to provide other functions on the XA H4 There is no Timer 2 and the UARTs have been replaced with full function USARTs 5001273 1999 24 18 Philips Semiconductors Single chip 16 bit microcontroller Watchdog Timer This timer is a standard XA G3 Watchdog Timer See the G3 datasheet IC25 Also if you intend to use the Watchdog Timer to assert the ResetOut pin see ResetOut in the XA H4 User Manual The Watchdog Timer is enabled at reset and must be periodically fed to prevent timeout If the watchdog times out it will generate an internal reset if ResetOut is enabled the internal reset will generate a ResetOut pulse active low pulse on ResetOut pin Reset On the XA H4 there are two pins associated with reset The Resetin pin provides an external reset into the XA H4 The port pin P3 2 0 ResetOut output can be configured as ResetOut Because ResetOut does not reflect ResetIn the ResetOut pin can be tied directly back into the ResetIn pin without other PC board logic This configuration will make all resets internal or ext
44. nt Register Ch 0 Tx rU M een interrupt if enabled and byte count exceeded pogon 14C ByteO older Data FIFO Register Ch 0 Tx R W 16 14Ch 0000h 1999 Sep 24 14D Byte 1 younger Philips Semiconductors Preliminary specification Single chip 16 bit microcontroller XA H4 MMR Name or end Orb Size jg Description Dua Data FIFO Register Ch 0 Tx DMA Control Register Ch 1 Tx FIFO Control amp Status Register Ch 1 Tx Segment Register Ch 1 Tx Buffer Base Register Ch 1 Tx Buffer Bound Register Ch 1 Tx Address Pointer Reg Ch 1 Tx Byte Count Register Ch 1 Tx 14E Byte2 older 14Eh i 0000h 14F Byte3 younger 150h Control Register 00h 151h Control amp Status Register 00h 152h Points to 64 k data segment 00h Wrap Reload Value for A15 A8 A7 A0 reloaded 154h to zero by hardware 156h Upper Bound plus 1 on A15 AO 158h Current Address pointer A15 AO 15Ah Corresponds to A15 0 Byte Count generates interrupt if enabled and byte count exceeded 00h 0000h 0000h 0000h Data FIFO Register Ch 1 Lo Tx Data FIFO Register Ch 1 Hi Tx DMA Control Register Ch 2 Tx FIFO Control amp Status Register Ch 2 Tx Segment Register Ch 2 Tx Buffer Base Register Ch 2 Tx 0 161h Control amp Status Register 0 162h Points to 64 k data segment 0 Wrap Reload Value for A15 A8 A7 A0 reloaded oh oh oh to zero by hardyvare m 164h Buffer Bound Register Ch 2 Tx
45. obal DMA Interrupt Register which is shared by all eight DMA channels each DMA channel has seven control registers and a four byte Data FIFO The four Rx DMA channels have one additional register the Rx Character Time Out Register All DMA registers can be read and written in Memory Mapped Register MMR space These registers are summarized below Global DMA Interrupt Register not shown in figure DMA interrupt flags are in this register DMA Control Register Contains the master mode select and interrupt enable bits for the channel 9 Segment Register Holds 23 16 the current segment of the 24 bit data buffer address Buffer Base Register Holds a pointer A15 A8 to the lowest byte in the memory buffer Buffer Bound Register Points to the first out of bounds address above a circular buffer Address Pointer Register Points to a single byte or word in the data buffer in memory The 24 bit DMA address is formed by concatenating the contents of the Segment Register A23 A16 with the contents of the Address Pointer Register A15 A0 Byte Count Register Holds the initial number of bytes to be transferred In Tx Chaining mode this register is not used because the byte count is brought into the byte counter from buffer headers in memory FIFO Control amp Status Register Holds the queuing order and full empty status for the Data FIFO Registers Data FIFO Registers A four byte data F
46. oltage all ports 24 V V Output high voltage all ports 3 2 mA 4 5 V 2 4 lou 1 0 mA Vpp 3 0V 2 2 Logical 1 to 0 transition current all ports IL IH OL lu TL NOTE 1 Vpp must be raised to within the operating range before power down mode is exited 2 Ports in quasi bidirectional mode with weak pullup 3 Ports in PUSH PULL mode both pullup and pulldown assumed to be the same strength 4 all output modes 5 Port pins source a transition current when used in quasi bidirectional mode and externally driven from 1 to 0 This current is highest when Vin is approximately 2 V 6 Measured with port in high impedance mode 7 Measured with port in quasi bidirectional mode 8 Under steady state non transient conditions lo must be externally limited as follows Maximum lo per port pin 15 mA NOTE This is 85 C specification for Vpp 5 V Maximum lo per 8 bit port 26 mA Maximum total lo for all outputs 71mA If loj exceeds the test condition may exceed the related specification Pins are not guaranteed to sink current greater than the listed test conditions 1999 Sep 24 28 Philips Semiconductors Preliminary specification Single chip 16 bit microcontroller 4 PRELIMINARY AC ELECTRICAL CHARACTERISTICS 5 0 V 10 Vpp 5 0 V 10 Tamp 40 C to 85 industrial 000 Cycles
47. ontrol register 816h Clock Mode Control 818h Lower Byte of Baud rate time constant USARTO Write Register 14 USARTO Write Register 15 81Ah Upper Byte of Baud rate time constant 00h 81Ch Miscellaneous Control bits XX USARTO Write Register 16 USARTO Write Register 17 81Eh External Status interrupt control f8h 828h Match Character 2 WR16 00h USARTO Read Register 0 USARTO Read Register 1 Reserved do not write USARTO Read Register 3 see WR16 and 17 USARTO Read Register 6 USARTO Read Register 7 USARTO Read Register 8 Reserved USARTO Read Register 10 Reserved 8 8 8 8 8 82Ah Match Character 3 WR17 00h Tx Rx buffer and external status m RO 98 8221 Receiecondtionstatusresiduecode s sm memptemdmBis _ sm sn s sem 0 s SDLC byte count high ara FIFO status DU s so JReceive Buter 1 7771 s sm toposes USART1 Registers 1999 Sep 24 USART1 Write Register 0 R W 8 840h Command register 00h USART1 Write Register 2 R W 8 844h Extended Features Control USART1 Write Register 4 R W 8 848h Tx Rx miscellaneous parameters amp mode 00h USART1 Write Register 6 R W 8 84Ch HDLC SDLC address field or Match Character 0 00h USART1 Write Register 8 R W 8 850h Transmit Data Buffer USART1 Write Re
48. ort 1 Bit 3 or USART2 TR Clock input 2 P1 4 CD2 Port 1 Bit 4 or USART2 Carrier Detect input 1 5 CTS2 Port 1 Bit 5 or USART2 Clear To Send input 1 6 RTS2 Port 1 Bit 6 or USART2 Request Send output 1 7 VO 1 7 BRG2 Sync2 Port 1 Bit 7 or USART2 Sync input or output or BRG output or TxClk output see USART diagrams in the user manual P20 P2 0 RxD3 Port 2 Bit 0 or USARTS Rx Data input P2 1 TxD3 Port 2 Bit 1 or USART3 Tx Data output 2 2 RTCIK3 Port 2 Bit 2 USART3 RT Clock input 2 P2 3 ComCIk TRCIK3 Port 2 Bit 3 or USART3 TR Clock input P2 4 CD3 Port 2 Bit 4 or USART3 Carrier Detect input 2 5 CTS3 Port 2 Bit 5 or USART3 Clear To Send input NINE GU P2 6 RTS3 Port 2 Bit 6 or USART3 Request To Send output 2 7 P2 7 n BRG3 Port 2 Bit 7 or USART3 Sync input or output or BRG output TxCIk output see SART clock diagrams in the user manual 3 0 0 CS4 RASA Port Bit 0 or CS4 or RAS 4 output or USART1 RT Clock input Active low chip selects CS1 through CS5 come out of reset disabled They can be programmed to function as normal chip selects or as RAS strobes to DRAM CS2 through CS5 are not used with the SWAP operation see the Memory Controller chapter in the XA H4 User Manual They are mappable to any region of the 16 MB address space P3 1 CS5 RTS Port
49. r Reload WFEED1 Watchdog Feed 1 WFEED2 Watchdog Feed 2 TES SFRs marked with an asterisk are bit addressable SFRs marked with a pound sign are additional SFR registers specific to the XA H3 and XA H4 The XA H4 implements 8 bit SFR bus as stated in Chapter 8 of the C25 Data Handbook XA User Guide All SFR accesses must be 8 bit operations Attempts to write 16 bits to an SFR will actually write only the lower 8 bits 16 bit SFR reads will return undefined data in the upper byte SFR is loaded from the reset vector F1 FO and P reset to 0 All other bits are loaded from the reset vector Unimplemented bits in SFRs are X unknown at all times 1 5 should not be written to these bits since they be used for other purposes in future XA derivatives The reset value shown for these bits is 0 Port configurations default to quasi bidirectional when the XA begins execution after reset Thus all registers will contain FFh and PnCFGB register will contain 00h See warning XA H4 User Manual about P3 2 0 ResetOut pin during first 258 clocks after power up Basically during this period this pin may output a strongly driven low pulse If the pulse does occur it will terminate in a transition to high at a time no later than the 259th system clock after valid Vec power up The WDCON reset value is E6 for a Watchdog reset E4 for all other reset causes The RSTSRC register reflects th
50. rammed to automatically echo the industry standard autobaud sequences They can be programmed to update the necessary control registers in the USARTS and turn on the receiver which in turn will automatically initiate DMA into memory of received data Thus once the baud rate is determined reception begins without intervention from the processor When the baud rate is detected a maskable interrupt is sent to the processor See the Autobaud chapter in the XA H4 User Manual for details VO Port Output Configuration Port input output configurations are the same as standard XA ports open drain quasi bidirectional push pull and off off means tri state Hi Z and allows the pin to be used as an input WARNING At power on time from the time that power coming up is valid the P3 2 Timero ResetOut pin may be driven low for any period from zero nanoseconds up to 258 system clocks This is true independently of whether Resetln is active or not Power Reduction Modes The XA H4 supports Idle and Power Down modes of power reduction The idle mode leaves most peripherals running in order to allow them to activate the processor when an interrupt is generated The power down mode stops the oscillator in order to absolutely minimize power The processor can be made to exit power down mode via a reset or one of the external interrupt inputs INTO or INT1 This will occur if the interrupt is enabled and its priority is higher than that defined by IM3
51. rd Reads Code Fetches and Byte Reads both BLE and BHE will go active During DRAM cycles only the appropriate CAS Address will be multiplexed onto pins A17 A7 after the assertion of RAS and prior to the assertion of BHE CASH and BLE CASL See AC timing diagrams and the XA H4 User Manual for complete details SUO1275 Figure 4 Typical system bus configuration 1999 Sep 24 21 Philips Semiconductors Preliminary specification Single chip 16 bit microcontroller XA H4 Table 4 Memory interface control registers Reg Base Address High This SFR is used to relocate the MMRs It contains address bits a23 a16 of the base address for the 4 Memory Mapped Register space See the XA H4 User Manual for using this SFR to relocate the MMRs MRBL MMR Base Address Low SFR Contains address bits a15 a12 of the base address for the 4 kB Memory Mapped 8bits Register space MICFG MIF Configuration Contains the ClkOut Enable bit 8 bits MBCL Memory Bank Configuration MMR Contains the bits for locking and unlocking the BICFG Registers Lock 8 bits BiCFG Bank i Configuration Contains the size type bus width and enable bits for Memory Bank i 8 bits BiAM Bank i Base Address DRAM Contains the base address bits and address multiplex control bits for Address Multiplexer Control 8 bits Memory Bank i BiTMG Banki Timing MMR Contains the timing control bits for Memory Bank i 8 b
52. rget or goal specifications for product development specification Specification may change in any manner without notice Preliminary Qualification This data sheet contains preliminary data and supplementary data will be published at a later date specification Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product Product Production This data sheet contains final specifications Philips Semiconductors reserves the right to make specification changes at any time without notice in order to improve design and supply the best possible product 1 Please consult the most recently issued datasheet before initiating or completing a design Definitions Short form specification The data in a short form specification is extracted from a full data sheet with the same type number and title For detailed information see the relevant data sheet or data handbook Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System IEC 134 Stress above one or more of the limiting values may cause permanent damage to the device These are stress ratings only and operation of the device at these or atany other conditions above those given in the Characteristics sections of the specification is not implied Exposure to limiting values for extended periods may affect device reliability Application information
53. rnally applied reset signal execution of the RESET instruction or a Watchdog reset Figure 2 shows the fields in the RSTSRC register If the ResetOut function is tied back into the Resetin pin then all resets will be external resets and will thus appear as external resets in the reset source register RSTSRC 7 enables the ResetOut function 1 Enabled 0 Disabled See XA H4 User Manual for details RSTSRC 7 differs in function from most other XA derivatives LSB BIT SYMBOL FUNCTION RSTSRC 7 ROEN RSTSRC 6 RSTSRC 5 RSTSRC 4 RSTSRC 3 RSTSRC 2 R WD RSTSRC 1 CMD RSTSRC 0 R EXT WARNING ResetOut function enable bit see XA H3 User Manual for details Reserved for future use Should not be set to 1 by user programs Reserved for future use Should not be set to 1 by user programs Reserved for future use Should not be set to 1 by user programs Reserved for future use Should not be set to 1 by user programs Indicates that the last reset was caused by a watchdog timer overflow see WARNING Indicates that the last reset was caused by execution of the RESET instruction see WARNING Indicates that the last reset was caused by the external Resetin input If ResetOut function is tied back into ResetIn pin RSTSRC will always show external reset ONLY because external reset always takes precedence over internal reset 5001237 Figure 2 RSTSRC reset source register DRAM CONTROLLER AND MEMORY I O BUS
54. t in the Memory Controller chapter of the XA H4 User Manual CS1 is usually mapped to be based at 000000h after the swap but is capable of being based anywhere in the 16 MB space Chip Select 2 or RAS2 Active low Chip Selects CS1 through CS5 come out of reset disabled They can be programmed to function as normal chip selects or as RAS strobes to DRAM CS2 through CS5 are not used with the SWAP operation see the Memory Controller chapter in the XA H4 User Manual They are mappable to any region of the 16 MB address space CS3 or RAS3 See Chip Select 2 for description ee Pins 56 57 for 2 additional Chip Selects WE Write Enable Goes active low during all bus write cycles only Output Enable Goes active low during all bus read cycles only 54 Byte Low Enable or CAS Low Byte Goes active low during all bus cycles that access D7 DO read or write Generic or DRAM Functions as CAS during DRAM cycles CASH Byte High Enable or CAS High Byte Goes active low during all bus cycles that access data bus lines D15 D8 read or write Generic or DRAM Functions as CAS during DRAM cycles ClkOut 45 Clock Output This pin outputs a buffered version of the internal CPU clock The clock output may be used in conjunction with the external bus to synchronize WAIT state generators etc The clock output may be disabled by software WARNING The capacitive loading on this output must not exceed 40 pf A19 A0 24 21 Address 19 0
55. tiple OR from DMA IE2 MMR 2D2 0 TF1 SFR 410 7 287 IE1 SFR 410 3 283 TFO SFR 410 5 285 SOFTWARE INTERRUPTS 009 0098 0097 0094 0093 0090 008 008 008 0088 0087 0084 0083 0080 42717 33F PHSVVR3 4A7 6 4 PHSWR2 4A7 2 0 PHSWR1 4 6 6 4 PHSWRO 4A6 2 0 PSC23 4 4 6 4 5 01 4 4 2 0 4 3 2 0 PDMAL 4A2 6 4 PX2 4A2 2 0 PTI 4A1 6 4 PX1 4A1 2 0 PTO 4 0 6 4 PXO 4A0 2 0 IN Em zx m o AR 1999 Sep 24 27 Philips Semiconductors Preliminary specification Single chip 16 bit microcontroller 4 ABSOLUTE MAXIMUM RATINGS Operating temperature under bias 55 to 4125 Storage temperature range 65 to 150 Voltage on any other pin to Vss 0 5 to VDD20 5 V Power dissipation based on package heat transfer not device power consumption PRELIMINARY DC ELECTRICAL CHARACTERISTICS Vpp 5 0 V 10 or 3 3 V 10 unless otherwise specified Tamb 40 C to 85 C for industrial unless otherwise specified Limits Symbol Parameter Test Conditions sme ane Min Typ Me m ame ea C ovome m ie Power supply curent Power Bown mode sousov 59 ve RAW Koepalvevotage CE mugs rah ota reo RT V Output low voltage all ports T Vou Output high v
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