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DAS-429P104/Mx User`s Manual, Rev A

1. e Update Counter Trigger registers not required Start e Write to the Module Start Register setting the appropriate channel s start bits Each channel can be started individually at different times See Start Stop Register page 2 4 Read the Receive Status registers i e Word Counter e Read the Receiver Status registers to know how many words have been received Read the Rev Data block e Read the ARINC words and RCV Status and Time Tag Words from the on board memory Excalibur Systems Inc 2 2 Module Memory Map Figure 2 1 illustrates the module memory usage Channel Control Register Block 5 0170 019E H Area Used For TX Instruction Stacks 01A0 7FFE H TX Data Blocks RCV Data Blocks RCV Look up Tables Figure 2 1 Module M429R4T2 Memory Map DAS 429P104 Mx User s Manual Module Operation page 2 3 Module Operation 2 3 Module Control Registers Figure 2 2 Module Control Registers Map NOTE For an explanation of these registers see Receiver Merge Mode Control Registers page 2 9 2 3 1 Start Stop Register Address 0010 H READ WRITE The Start Stop register starts and stops channel operation You can start one or more channels at the same time Writing a 1 to bit 00 starts channel 0 operation writing a 1 to the next location starts channel 1 etc Writing a 0 to the bit location will stop that channel s operation You should wait a minimum
2. 2 3 5 Module Operation Receiver Data Storage Mode Register Address 0018 H WRITE The Receiver Data Storage Mode register is used to select the Receiver Data Storage Mode and the Merge Mode option ARINC 429 data words can be stored with Time Tag and Status words appended to the data block or they can be stored without these additional words Set bit 00 to a logic 0 to select the standard mode which appends both Time Tag and Status Words to each ARINC 429 word stored in memory Set register bit 00 to a logic 1 to select Data Only mode Bit 01 controls the Receiver Merge Mode selection A logic 0 selects the standard independent mode which utilizes different receive buffer areas for each receive channel A logic 1 selects the Merge Mode which utilizes a single receiver buffer for all channels Each Receive Status Word in this case is tagged with Channel Code information The Merge Module Control registers are used only when the Merge Mode option is selected See Receiver Merge Mode Control Registers page 2 9 Bit Description 02 15 0 01 Merge Mode Option 0 Independent Mode 1 Merge Mode 00 Receive Data Storage Mode 0 Standard Mode 1 Store Only Data Receiver Data Storage Mode Register NOTE 1 If Data Only Storage Mode is selected bit 00 set to 1 storage will be per independent channel regardless of the state of bit 01 2 Data Only Storage Mode is not available in Lookup Table Mode 3 The Receiver Data
3. Hi Data Word Lo TX Data Buffers 1st Word in Instruction Block 1st word in Instruction Block 3 3 1 Control Word Definition Bit Bit Name Description 01 15 Reserved 0 00 Parity Error 0 Normal Odd Parity Standard ARINC 429 parity 1 Even Parity Error Injection Control Word Definition 3 3 2 Word Count The Word Count is used to specify the number of 32 bit ARINC 429 data words in this instruction block 1 65535 page 3 6 Excalibur Systems Inc Transmit Mode 3 3 3 Interword Delay The Interword delay is used to set the delay 4 65504 between words in the block and between the final word in this block and the first word in the following block Its resolution is 1 bit time For high speed this gives it a range of 40 microseconds interword value 4 to just over 655 milliseconds interword value 65504 For low speed the range is 320 microseconds interword value 4 to over 5 seconds interword value 65504 NOTE The ARINC 429 specification does not allow interword times less than 4 bit times so interword delay values of less than 4 will be interpreted as the minimum legal interword time 3 3 4 Tx Data Pointer The Transmit Data Pointer register is used to set the start address of the transmit data buffer The address must be a word boundary The size of the buffer is determined by the Word Count value 3 4 Transmit Data Block Format Figure 3 4 below illustrates the format of the TX data words in the
4. Mechanical and Electrical Specifications 5 3 5 3 1 page 5 4 Connectors The DAS 429P104 Mx card contains all communication I O signals on two Box Header connectors J1 J2 Mating connectors including crimp pins are supplied The connectors pinouts and signals description are described in the following sections Connectors J1 J2 Pinout The 16 pin connectors layout front view is illustrated in Figure 5 3 below Figure 5 3 Connectors J1 J2 Layout Front View Each module s six channels are grouped similarly and each module is assigned a dedicated connector Tables 5 2 and 5 3 list the pin assignment and signals description Excalibur Systems Inc Mechanical and Electrical Specifications rm gt mm ero 4 ri oer e ee 7 mere ran mn io fra oer Lee reso aa mo Tam ae fre RXH10 RXL10 RXH11 RXL11 SHIELD SHIELD RXH12 RXL12 CS EA EN HE Ed pe EL 12 Ea EA 7 SHIELD SHIELD TXH10 TXL10 TXH11 TXL11 Table 5 2 Connectors J1 J2 Pin Assignments RXHOO 03 Module 0 Receive channels 0 3 Hi connection RXL00 03 Module 0 Receive channels 0 3 Lo connection TXH00 01 Module_0 Transmit channels 0 1 Hi connection TXLOO 01 Module_0 Transmit channels 0 1 Lo connection RXH10 13 Module_1 Receive channels 0 3 Hi connection RXL10 13 Module_1 Receive channels 0 3 Lo connection TXH10 11 Module_1 Transmit channels 0 1 Hi connection TXL10 11 Module_1 Transmit channels 0 1 Lo connection SH
5. memory Nth Word e e e 2nd ARINC Word gt Data Word Hi Fourth Word 2nd ARINC Word gt Data Word Lo Third Word 1st ARINC Word gt Data Word Hi Second Word ist ARINC Word 3 Data Word Lo First Word Location in the TX Data Area Figure 3 4 Transmit Data Words Memory Format DAS 429P 104 Mx User s Manual page 3 7 Transmit Mode Figure 3 5 below defines the locations and bit definitions of the data bytes in the memory The numbers shown in the four bytes represent the ARINC 429 bit locations in the 32 bit word MSB Hi Byte Lo Byte LSB 15 8 7 0 BRIE ENDS SE H NS EE GSO 15 8 7 0 e MSB Hi Byte Lo Byte Label LSB Data Word Hi Data Word Lo Figure 3 5 Data Bytes in Memory NOTE 1 The data in ARINC 429 bit 32 is ignored and instead a value calculated using the selected parity is transmitted over the bus 2 The ARINC word bits are transmitted in the following order Serial Data Out Label E MSB LSB LSB MSB 3 Bits 09 through 29 are ordered from LSB to MSB opposite from the Label field which is organized MSB to LSB It is for this reason that the data block is built the way it is page 3 8 Excalibur Systems Inc 4 1 Receive Monitor Mode Receive Monitor Mode Chapter 4 describes receiver monitor operation The following topics are covered e General Information page 4 1 e Sequential Merge Mode Operation page 4 2 e
6. Control Registers You can select the Merge Mode option via bit 01 in the Receiver Data Storage Mode register see page 2 7 This section describes the Merge Mode Control registers which are used only when the Merge Mode option is selected Receiver Merge Start Pointer Address 0020 H WRITE The Receiver Merge Start pointer sets the start address of the Receive Data buffer The address must be on a word boundary within the Rev Data Blocks area For example to cause the Merge buffer to begin at byte offset 1A0 H write a 1A0 H to this register Receiver Merge End Pointer Address 0022 H WRITE The Receiver Merge End pointer sets the End Address of the Receive Data buffer The data will wrap around or stop when the buffer is full when the end address is reached depending upon the contents of the Receiver Wrap Around bit Receiver Merge Configuration Register Receiver Merge Current Pointer The Receiver Merge Current pointer indicates the current address where the next ARINC receive word is to be placed in the Receiver buffer This pointer value is incremented after the entire receiver block ARINC word time tag and status is written into memory Receiver Merge Filter Table Start Address Address 0026 H WRITE The Receiver Merge Filter Table Start address sets the start address of the 256 x 8 Label Filter Table as described in the Sequential storage mode See Rev Sequential Mode Filter Table Diagram on page 4 6 Th
7. Select JUMPErs ii 5 2 5 2 3 Interrupt Select Jumpers ee ee ee AR ee Re Re ge ee RA ee 5 3 5 2 4 Factory Default Jumpers Settings iii ese ee ee ke Re ke ge ge eg ee 5 3 59 GOMMOCIONS EE EE ES GE A ge 5 4 5 3 1 Connectors J1 J2 Pinout oo ee ee ee ee 5 4 5 3 2 PC 104 Bus Connectors Pinout Re Re Re ee ek ee 5 6 5 4 Power Requirements see ee ee ee ee ee ee ee ee 5 7 6 Ordering Information sesse dee ek KS KEENAN ek EK de Ge ee 6 1 page ii Excalibur Systems Inc Contents Figures Figure 1 1 DAS 429P104 Mx Block Diagram 1 3 Figure 1 2 M429R4T2 Module Block Diagram essence 1 3 Figure 1 3 General Memory Map se ses ee dee ee ee ee ee ee Ee ee ee ee 1 5 Figure 2 1 Module M429R4T2 Memory Map 2 3 Figure 2 2 Module Control Registers Map 2 4 Figure 3 1 Channel 2 Control Register Block Map 3 1 Figure 3 2 Channel 5 Control Register Block Map 3 2 Figure 3 3 Tx Instruction Stack Structure ii 3 6 Figure 3 4 Transmit Data Words Memory Format sesse ee ese ee 3 7 Figure 3 5 Data Bytes in Memory 3 8 Figure 4 1 Rev Sequential Mode Buffer Structure 4 3 Figure 4 2 Rev Data Ward Formal een eli 4 3 Figure 4 3 Time Tag Word Description ee RR ee RE ee ee RE 4 4 Figure 4 4 Rev Sequential Mode Filter Table 4
8. Storage Mode register can only be changed when all channels are turned off Start Stop register 0 4 Merge mode merges the 4 receive channels in each bank DAS 429P 104 Mx User s Manual page 2 7 Module Operation 2 3 6 2 3 7 2 3 8 page 2 8 Interrupt Status Busy Register Address 001A H READ The Interrupt Status Busy register indicates whether you can access a particular channel s interrupt status register A 1 in the appropriate bit position indicates that the channel s interrupt status register is busy and you should not access it A 0 in the appropriate bit position indicates that the contents of interrupt status register are valid and you may access it Bit 06 corresponds to whether the Receiver Merge Mode Interrupt Status register is busy Bit Bit Name 07 15 Reserved 06 Merge Mode Busy Bit 05 Channel 5 Busy Bit 04 Channel 4 Busy Bit 03 Channel 3 Busy Bit 02 Channel 2 Busy Bit 01 Channel 1 Busy Bit 00 Channel 0 Busy Bit Interrupt Status Busy Register Reset Time Tag Register Address 001C H WRITE Writing any non zero value to the Reset Time Tag register resets the time tag to 0 Module ID Register Address 001E H READ The module will write the value E429 H into the Module ID register when it has finished its initialization sequence and is ready to be accessed by the Host Excalibur Systems Inc 2 4 2 4 1 2 4 2 2 4 3 2 4 4 2 4 5 Module Operation Receiver Merge Mode
9. index 0 3 j Transmit channel index 0 1 77 Module_0 is a logical module built onto the DAS 429P104 Mx base card not a physical add in module as it is on other cards in the Mx family PC 104 BUS i I pre zap BUFFER di dui ARINC 429 RXO 1 1 MODULE 0 TXOG J1 eg M429R4T2 gt CNTRL gt INTERFACE ARINC 429 CONNECTIONS 1 CONTROLLER ARINC 429 RX1 i MODULE 1 l Ka i M429R4T2 10 gt de 40 MHz OSC I I I I I I I Figure 1 1 DAS 429P104 Mx Block Diagram Figure 1 2 below illustrates the block diagram of a single M429R4T2 module LOCAL BUS 20MHz AE icro i Controller I Il I lt RX0 i 128K x 8 Boot lt ENCIDEC RX1 i Flash gt ARINC 429 TX0 i DRIVER 128K x 16 ARINC 429 i Program 4 RX2 CHANNELS RAM sl ENC DEC RX3 i ARINC 429 TX1 CTRL Local Bus DRIVER Interface S Logic i h Block i 16K x 16 FPGA ADDR gt DualPort 4 DATA id RAM Figure 1 2 M429R4T2 Module Block Diagram DAS 429P104 Mx User s Manual page 1 3 Introduction 1 2 page 1 4 Installation Before installing the card it is very important to determine which half segment of memory is available Programs such as Symantec Corporation s SYSINFO EXE or Microsoft Corporation s MSD EXE may be used to determine which memory segme
10. lookup table 2 To activate the Interval Count Trigger interrupt you must also set the Channel x Rev Interval Counter Trigger Register See Channel x Rev Interval Counter Trigger Register page 4 16 3 To activate the Data Word Count Trigger interrupt you must also set the Channel x Rev Word Counter Trigger Register See Channel x Rev Data Word Counter Trigger Register page 4 16 DAS 429P104 Mx User s Manual page 4 17 Receive Monitor Mode 4 5 13 Channel x Status Register READ WRITE The Channel x Status register indicates the operational status of the channel You can use this register to poll the status of the channel or it can be used with interrupts When used in conjunction with interrupts the register indicates the condition s which caused the interrupt A logic 1 indicates an active bit You must reset the status bits by writing a 0 to this register Only the two least significant bits are used for transmit channels and only bits 02 through 06 are used for receive channels See Channel x Status Register in Transmit Mode page 3 5 Bit Description Interrupt Condition 07 15 0 06 Receiver Stopped on Buffer Full 05 Receiver Error Word Received 04 Receiver Data Word Count Trigger 03 Receiver Interval Count Trigger 02 Receiver Label Received 00 01 Not used in Receive mode Channel x Status Register Receive Mode In Look Up Mode the Label Received Status bit is set upon rece
11. operation and describes transmit channel control register block maps transmit channel control registers the transmit instruction stack and the transmit data block format Chapter 4 Receive Monitor Mode describes the general principle of receiver monitor operation This includes a description of sequential merge mode and look up table mode operation receive channel control register block maps and receive channel control registers Chapter 5 Mechanical and Electrical Specifications describes the mechanical and electrical specifications of the DAS 429P104 Mx board This includes a description of board layout board case ground jumpers connectors and power requirements Chapter 6 Ordering Information explains how to indicate which options you want when ordering a DAS 429P104 Mx card DAS 429P104 Mx User s Manual page v Contents page vi Excalibur Systems Inc 1 1 Introduction Introduction Chapter 1 provides an overview of the DAS 429P104 Mx avionics communication board The following topics are covered e Overview page 1 1 e Installation page 1 4 e General Memory Map page 1 5 e Global Registers page 1 6 Overview The DAS 429P104 Mx is a modular ARINC 429 memory mapped 12 channel test simulation and monitor card for PC 104 systems The DAS 429P104 Mx provides a total solution for developing and testing ARINC 429 interfaces and for performing system simulation o
12. 1 Data received over channel 1 000 Data received over channel 0 Global Bit Indicates that the received ARINC 429 word was valid in all respects Indicates that a parity error was detected in the ARINC 429 word A logic 1 This bit is cleared while data is in the process of being updated When the bit is set valid data is in memory Receive Merge Mode Status Word page 4 6 Excalibur Systems Inc 4 3 Look Up Table Mode Operation 4 3 1 Receive Look Up Table Storage Sequence Receive Monitor Mode In the Look up table mode the word s label is used by the module as an offset to a 256 word look up table You can program the table with address pointers indicating where to write the Receiver Data Block Each block contains the 32 bit ARINC word 32 bit Time Tag and status word The 256 word table can be placed anywhere in the memory via a Receiver Look up Table Pointer that you can program You can poll the operational status of each channel and generate interrupts in various circumstances 4 3 2 Rev Look Up Table Mode Diagram RCV Look up Table Pointer 256 x 16 Table per channel Label 377 octal Address Pointer Label x Address Pointer Label x Address Pointer Label 0 Address Pointer Figure 4 6 Rcv Look Up Table Mode Structure DAS 429P104 Mx User s Manual page 4 7 Receive Monitor Mode 4 3 3 page 4 8 Receive Look Up Table Status Control Word READ WRITE Bit Bit Name Description 15 Enable L
13. 4 Receiver Merge Mode Control Registers 2 9 2 4 1 Receiver Merge Start Pointer iese i 2 9 2 4 2 Receiver Merge End Pointer AA 2 9 2 4 3 Receiver Merge Current Pointer ese ee ee ee ee Re Re Re ee ee ee 2 9 2 4 4 Receiver Merge Filter Table Start Address AA 2 9 2 4 5 Receiver Merge Word Counter ii 2 9 2 4 6 Receiver Merge Buffer Wraparound Register AAA 2 10 2 4 7 Receiver Merge Word Count Trigger Register ee ee ee 2 10 2 4 8 Receiver Merge Interval Count Trigger Register i 2 10 2 4 9 Receiver Merge Label Trigger Register ii 2 11 2 4 10 Receiver Merge Configuration Register ee ee RR ee ee 2 11 2 4 11 Receiver Merge Interrupt Condition Register A 2 12 2 4 12 Receiver Merge Status Register ee ee RR ee Re ee ee 2 13 3 Transmit Mode issie ede iii 3 1 3 1 Transmit Channel Control Register Block Maps 3 1 3 1 1 Channel 2 Control Register Block Map 3 1 3 1 2 Channel 5 Control Register Block Map 3 2 3 2 Transmit Channel Control RegistersS 3 2 3 2 1 Channel x Configuration Register ii 3 2 3 2 2 Channel x Tx Instruction Stack Pointer i 3 3 3 2 3 Channel x Tx Instruction Counter i 3 3 3 2 4 Channel x Tx Loop CGounter i 3 3 3 2 5 Channel x Tx Current Word Register ee ke ee
14. 5 Figure 4 5 Label Control Byte Structure WRITE 4 5 Figure 4 6 Rev Look Up Table Mode Structure ees esse ee se ee ee ee 4 7 Figure 4 7 Channel 0 Control Register Block Map 4 9 Figure 4 8 Channel 1 Control Register Block Map 4 10 Figure 4 9 Channel 3 Control Register Block Map 4 11 Figure 4 10 Channel 4 Control Register Block Map 4 12 Figure 5 iGard bavobl s storielle Ge dossi ne fia 5 1 Figure 5 2 Base Address Select Jumpers AAA 5 2 Figure 5 3 Connectors J1 J2 Layout Front VieW ee ee ee ee 5 4 DAS 429P104 Mx User s Manual page iii Contents Tables page iv Table 5 1 Interrupt Select JUMPeErs 5 3 Table 5 2 Connectors J1 J2 Pin Assignments iss ss ee RR EE ee 5 5 Table 5 3 J1 J2 Signals Description ii 5 5 Table 5 4 Connectors PC 104 Bus Pmout iese ss ee ee ee ee ke eeeee 5 6 Excalibur Systems Inc Contents What is in this manual This manual is divided into the following six chapters Chapter 1 Introduction provides an overview of the DAS 429P104 Mx board and discusses card installation external connections the memory usage and card registers Chapter 2 Module Operation describes the general principle of module operation the module memory map and the module control registers Chapter 3 Transmit Mode explains how to implement transmitter
15. 5 8 Receive Monitor Mode Channel x Receive Filter Table Start Address WRITE SEQUENTIAL MODE The Channel x Receive Filter Table Start address sets the start address of the 256 x 8 Label Filter Table as described in Sequential Merge Mode Operation page 4 2 The address must be a word boundary It is valid for several channels to use the same filter table This table is only valid if the Configuration Register Receiver Enable Filter Table bit is set see bit 09 in Channel x Configuration Register Receive Mode page 4 13 Channel x Rev Data Word Count Register READ WRITE SEQUENTIAL MODE The Channel x Rev Data Word Count register indicates the number of ARINC words received 0 65535 This register wraps around to 0 after it reaches 65535 You can reset it only when the channel is stopped Channel x Rev Buffer Wraparound Register READ WRITE The Channel x Rev Buffer Wraparound register contains 2 bits for synchronization with the host If bit 14 is set to 1 the receive buffer has wrapped around once since the last time this register was cleared If bit 15 is set to 1 there have been multiple wraparounds You are expected to clear bit 14 each time the first word of the buffer is read When the module wraps around it checks bit 14 If bit 14 is not set the module sets it otherwise the module sets bit 15 NOTE Excalibur C drivers handle these bits If you use these drivers you don t need to deal with them B
16. Count Trigger register See Receiver Merge Interval Count Trigger Register page 2 10 3 In order to activate the Data Word Count Trigger interrupt you must also set the Receiver Merge Word Count Trigger register See Receiver Merge Word Count Trigger Register page 2 10 Excalibur Systems Inc Module Operation 2 4 12 Receiver Merge Status Register Address 0038 H READ WRITE The Receiver Merge Status register indicates the operational status of the Merge Mode receive buffer You can use this register to poll the status of the channel or it can be used with interrupts When used in conjunction with interrupts the register indicates the condition s which caused the interrupt A logic 1 indicates an active bit You can reset status bits by writing a 0 to this register Bit Description 07 15 Reserved 06 Stopped on Buffer Full 05 Error Word Received 04 Data Word Count Trigger 03 Interval Count Trigger 02 Label Received 00 01 Reserved Receiver Merge Status Register NOTE The Label Received Status bit is set upon receipt of any label for which an interrupt has been requested via the filter table DAS 429P104 Mx User s Manual page 2 13 Module Operation page 2 14 Excalibur Systems Inc 3 1 3 1 1 Transmit Mode Transmit Mode Chapter 3 describes transmitter operation The following topics are covered e Transmit Channel Control Register Block Maps page 3 1 e Transmit Channel Contr
17. DAS 429P104 Mx MULTI CHANNEL ARINC 429 Test and Simulation Board for PC 104 Computers User s Manual eh XOA LIS U EXCALIBUR SYSTEMS 311 Meacham Avenue e Elmont NY 11003 Tel 516 327 0000 Fax 516 327 4645 e mail excalibur mil 1553 com website www mil 1553 com Contents Contents 1 e De E 1 1 NNN EE EE EE ee 1 1 1 2 Installation EE ED OER OT OE ON DON OR DEER Pr 1 4 1 3 General Memory Map esse i 1 5 1 4 Global EE 1 6 1 4 1 Global Bank Select Register 1 6 1 4 2 Global Software Reset Register ee i 1 6 1 4 3 Global Interrupt Reset Register i 1 7 1 4 4 Global Interrupt Status Register i 1 7 2 Module Operation ua 2 1 2 1 Module General Operation ee ee 2 1 2 2 Module Memory Map 2 3 2 3 Module Control Registers n 2 4 RAS oa IS AA N RE EE EE EEN OE EN 2 4 2 3 2 Module Status Register iese ese ee Re Re Re ee ge ge ge ee 2 5 2 3 3 Firmware Revision Register ee iii 2 6 2 3 4 Channel Interrupt Register rrrrrnrnnnnvnnonvrnenvnnnnvrnenvrnervrnnnnrnnsnrnnenrenenrnnennnen 2 6 2 3 5 Receiver Data Storage Mode Register ee ee Re Re Re ge ee 2 7 2 3 6 Interrupt Status Busy Register iii 2 8 2 3 7 Reset Time Tag Register ee ee ae ee ee ee ee ee Ge ee ee 2 8 2 3 8 Module ID Register sm san ENEE Fe Dek ee EES ame dees SEER GEKEER 2 8 2
18. IELD Provided for cable shield connection this signal is connected on the card to the mechanical pads see Shield Signal Jumper page 5 2 If used you should provide a connection between the pads and the computer mainframe Table 5 3 J1 J2 Signals Description DAS 429P 104 Mx User s Manual page 5 5 Mechanical and Electrical Specifications 5 3 2 PC 104 Bus Connectors Pinout The following PC 104 signals are used by the DAS 429P104 Mx CONNECTOR P1 CONNECTOR P2 D7 D6 D5 D4 D3 D2 D1 DO 12V VOCHRDY lt lt KEY gt gt MEMW MEMR Table 5 4 Connectors PC 104 Bus Pinout page 5 6 Excalibur Systems Inc 5 4 Mechanical and Electrical Specifications Power Requirements The card s maximum power supply requirements are defined below DAS 429P104 M1 DAS 429P104 M2 5V 600mA 5V 1 0A 12V 90mA see Note 12V 180mA see Note 12V 90mA see Note 12V 180MA see Note NOTE Conditions Both transmit channels at full speed and full load DAS 429P 104 Mx User s Manual page 5 7 Mechanical and Electrical Specifications page 5 8 Excalibur Systems Inc Ordering Information Ordering Information Chapter 6 explains how to indicate which options you want when ordering a DAS 429P104 Mx card The x indicates the number of modules required up to 2 The suffix E can be added to the name of the card DAS 429P104 Mx to indicate the extended temperature option PAR
19. KHz Lo speed 0 100 KHz Hi speed Available for channels 0 and 3 only see Note 5 below Channel x Configuration Register Receive Mode NOTE 1 It is recommended that you set up all active channel Configuration Registers before programming any other DAS 429P104 Mx User s Manual parameters 2 You can only write to this register when all channels are turned off via the Start Register 3 You should start the module via the Start Register only after a minimum of 500 usec from the time that the contents of this register have been modified 4 Receiver Label Trigger See Channel x Rev Label Trigger Register page 4 16 5 The selected speed for channels 0 and 1 must be the same Similarly the selected speed for channels 3 and 4 must be the same Therefore bit 00 of the Channel Configuration Register is not used for channels 1 and 4 page 4 13 Receive Monitor Mode 4 5 2 Channel x Receive Data Start Pointer WRITE The Channel x Receive Data Start pointer register sets the start address of the Receive Data buffer The address must be a word boundary within the Rev Data Blocks area For example to cause the Receive Data buffer to begin at byte offset 1A0 H write a 1A0 H to this register This register is used in the sequential mode of operation 4 5 3 Channel x Receive Data End Pointer WRITE The Channel x Receive Data End pointer sets the End Address of the Receiver Data buffer This is used i
20. Look Up Table Mode Operation page 4 7 e Receive Channel Control Register Block Maps page 4 9 e Receive Channel Control Registers page 4 12 General Information You can set up each receiver channel s mode of operation by writing to the various Channel Control Registers one per channel Each receiver channel has three basic modes of operation e Sequential mode Stores data in sequential locations in the receive data area e Look up table mode Lets you store words in specific locations of memory according to the Label e Merge Mode Siphons all receiver channel data into one receiver buffer area In all modes the data words are stored with a 16 bit Receiver Status Word and a 32 bit time tag value In the Merge Mode the channel code information indicating on which channel the data was received is contained in the Receiver Status Word The Sequential mode also has a data only option which will not write the status and time tag along with each data word Sequential Mode Overview The sequential mode has a software selectable feature which filters the storage of specific user defined Labels or stores all Labels into a buffer The data buffer s size and location in the memory is programmed via a Start and End pointer Each received ARINC data word is tagged with a Status word indicating the status of the receive word and a 32 bit Time Tag value The ARINC data word Time Tag and Status word make up a
21. Re ee ee 3 4 3 2 6 Channel x Tx Current Loop Register ee ee Re ke ge ee 3 4 3 2 7 Channel x Interrupt Condition Register iese ee ek ge ee 3 4 3 2 8 Channel x Status Register i 3 5 DAS 429P104 Mx User s Manual page i Contents 3 3 Transmit Instruction Stack sesse ee RR 3 5 3 3 1 Control Word Definition i 3 6 3 3 2 Word e LEE 3 6 3 3 3 Interword Delay ER Aachen ie Ara iii 3 7 3 3 4 Tx RENE NEE 3 7 3 4 Transmit Data Block Fommat sesse esse ee ee ee 3 7 4 Receive Monitor Mode asssvvnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 4 1 4 1 General Information i 4 1 4 1 1 Sequential Mode OvervieW i 4 1 4 1 2 Look Up Table Mode Overview ee ee ek Re Re Re ee ee 4 2 4 1 3 Merge Mode OvervieW 4 2 4 2 Sequential Merge Mode Operation se see ee ee 4 2 4 2 1 Receive Buffer Storage Sequence ee ee ke ee RA ee RA ee ee 4 2 4 22 Rev Data Word Formati niariaaio aisi ai 4 3 4 2 3 Time Tag Word Description i 4 4 4 2 4 Rev Sequential Mode Filter Table Diagram ii 4 5 4 2 5 Receive Sequential Mode Status Word ee ee Re Re ee ee 4 6 4 2 6 Receive Merge Mode Status Word 4 6 4 3 Look Up Table Mode Operation Re 4 7 4 3 1 Receive Look Up Table Storage Sequence ee ee Re 4 7 4 3 2 Rev Look Up Table Mode Diagram AA 4 7 4 3 3 Rec
22. Register in Receive Monitor Mode page 4 18 Bit Description Interrupt Conditions 07 15 0 02 06 Not used in Transmit mode 01 Transmitter End of Frame 00 Transmitter End of Block Channel x Status Register Transmit Mode Transmit Instruction Stack The Transmit Instruction Stack is divided into Instruction Blocks each containing 8 words Each Instruction Block is associated with a Data Buffer A data buffer contains one or more ARINC 429 words that you want to transmit with the same amount of delay time between each word The first word in each instruction block is the Control Word which contains error injection parameters i e parity type The second word is the Word Count which instructs the module as to the number of ARINC words in a data buffer to transmit The third word the Interword Delay determines the delay time between words from the same data buffer The fourth word contains a 16 bit user supplied data pointer This TX Data Pointer is a 16 bit address byte offset into the module which points to the beginning of the data words in the memory The remaining four words are reserved DAS 429P104 Mx User s Manual page 3 5 Transmit Mode Transmit Data Pointer Transmit Data Pointer TX Instruction Stack Instruction Block 2 Instruction Block 1 TX Instruction Stack Pointer gt Figure 3 3 Tx Instruction Stack Structure Data Word Hi Data Word Lo Data Word
23. T NUMBER DAS 429P104 Mx DAS 429P104 Mx E M429R4T2 Ordering examples DAS 429P104 M2 DAS 429P104 M1 E DAS 429P104 Mx User s Manual DESCRIPTION ARINC 429 interface card for PC 104 systems Supports 4x Receive and 2x Transmit channels As above with extended temperature operation 40 to 85 C Number of modules required up to 2 minimum 1 Each module is configured as R4T2 Additional Mx modules ARINC 429 interface card for PC 104 systems with 2 modules Supports 8 Receive and 4 Transmit channels ARINC 429 interface card for PC 104 systems with 1 module and extended temperature operation Supports 4 Receive and 2 Transmit channels at 40 to 85 C temperature ranges page 6 1 The information contained in this document is believed to be accurate However no responsibility is assumed by Excalibur Systems Inc for its use and no license or rights are granted by implication or otherwise in connection therewith Specifications are subject to change without notice May 1998 Rev A 1
24. _1 Memory Area 0010 7FFF H BANK 0 BANK 1 Figure 1 3 General Memory Map DAS 429P 104 Mx User s Manual page 1 5 Introduction 1 4 1 4 1 1 4 2 page 1 6 Global Registers Global Bank Select Register Address 0000 H READ WRITE The Global Bank Select register sets the Bank Select for the desired Module access Writing a zero will give the host access to bank 0 and 1 to bank 1 This register is set to 0 at power up WRITE DEFINITION Bit Bit Name Description 01 15 X Dont Care 00 BSO 0 Bank 0 Module_0 1 Bank 1 Module 1 READ DEFINITION Bit Bit Name 01 15 X Don t Care 00 BSO Global Bank Select Register Global Software Reset Register Address 0002 H WRITE The Global Software Reset register is used to reset the card Writing a value of 1 to the appropriate bit will reset the corresponding Module Writing a value of 0 has no effect WARNING Reset erases all memory locations in the dual port RAM The Module Status Firmware Revision Module ID and Channel x RCV Look Up Table Start Address registers are written by the card after reset operation has been completed Bit Description 02 15 X Don t Care 01 Module_1 Software Reset 00 Module_0 Software Reset Global Software Reset Register Excalibur Systems Inc 1 4 3 1 4 4 Introduction Global Interrupt Reset Register Address 0004 H WRITE The Global Interrupt Reset register is used to reset the card interrupt request Writing a va
25. abel Enables the interrupt on label received capability This bit is Interrupt used in conjunction with the interrupt Condition Register 08 14 Reserved 07 Valid Word Global Bit Indicates that the received ARINC 429 word was valid in all respects 04 06 Reserved 03 Parity Error Indicates that an even parity error was detected in the ARINC 429 word 01 02 Reserved 00 Word Received A logic 1 This bit is cleared while data is in the process of being updated When the bit is set valid data is in memory Receive Look Up Table Status Control Word Excalibur Systems Inc Receive Monitor Mode 4 4 Receive Channel Control Register Block Maps 4 4 1 Channel 0 Control Register Block Map Channel 0 Interrupt Condition Register 0080 H 0082 H 0084 H 0086 H 0088 H 008A H 008C H 008E H 0090 H 0092 H 0094 H 0096 H 0098 H 009A H 009C H 009E H OOAO H 00A2 H 00A4 H 00A6 H 00A8 H OOAA H 00AC H OOAE H Figure 4 7 Channel 0 Control Register Block Map DAS 429P104 Mx User s Manual page 4 9 Receive Monitor Mode 4 4 2 Channel 1 Control Register Block Map Figure 4 8 Channel 1 Control Register Block Map page 4 10 Excalibur Systems Inc 4 4 3 Channel 3 Control Register Block Map 0110 H 0112 H 0114H 0116 H 0118H 011A H 011C H 011E H 0120 H 0122 H 0124 H 0126 H 0128 H 012A H 012C H 012E H 0130 H 0132 H 0134 H 0136 H 0138 H 013A H 013C H 013E H Figure 4 9 Channel 3 Control Reg
26. cking all non reserved bits for current value For example statreg amp 0x807F 0x007F 2 The Self Test Fail is set when the channel self test fails or when the channel is not present on the module 3 The module will continue to operate on condition of Channel Self Test Failures but will not continue to operate on condition of a Memory failure 4 The memory and channel self tests are performed once immediately after the module is reset On the other hand Internal Error status is monitored continuously If the module detects an illegal condition during normal module operation this register will be cleared except for the Internal Error bit which will be set An example of an illegal condition would be setting a pointer register to a byte boundary address odd address Firmware Revision Register Address 0014 H READ The Firmware Revision register indicates the revision level of the firmware For example 0100 H Rev 1 00 Channel Interrupt Register Address 0016 H READ WRITE The Channel Interrupt register indicates which channel issued the interrupt 1 Active You can reset the status bits by writing to this register or to the reset register Bit 06 15 05 04 03 02 01 00 Bit Name Reserved Channel 5 Interrupt Bit Channel 4 Interrupt Bit Channel 3 Interrupt Bit Channel 2 Interrupt Bit Channel 1 Interrupt Bit Channel 0 Interrupt Bit Channel Interrupt Register Excalibur Systems Inc
27. ddress line as shown in Figure 5 2 below A19 A18 A17 A16 A15 I SEGMENT Figure 5 2 Base Address Select Jumpers NOTE 1 Jumper short equates to a 0 2 Jumper open equates to a 1 3 Jumpers JP12 through JP15 refer to the required segment 64K in the DOS environment Jumper JP16 lets you select in which half segment to locate the card Example To place the card at Seg D800 JP12 OPEN JP13 OPEN JP14 SHORT JP15 OPEN JP16 OPEN Excalibur Systems Inc 5 2 3 5 2 4 Mechanical and Electrical Specifications Interrupt Select Jumpers JP17 JP27 The Interrupt Select jumper group is used to select the desired PC 104 Interrupt line in case when interrupt mode is used Each jumper selects one interrupt line as shown in Table 5 1 below Jumper Interrupt Line Jumper Interrupt Line JP17 IRQ2 9 JP23 IRQ10 JP18 IRQ3 JP24 IRQ11 JP19 IRQ4 JP25 IRQ12 JP20 IRQ5 JP26 IRQ14 JP21 IRQ6 JP27 IRQ15 JP22 IRQ7 Table 5 1 Interrupt Select Jumpers NOTE 1 When using interrupt mode Only one jumper should be shorted at one time 2 When not using interrupts All the jumpers should be left open Example To select the IRQ7 interrupt line JP22 SHORT JP17 21 OPEN JP23 27 Factory Default Jumpers Settings JP17 JP27 OPEN No interrupts JP12 OPEN JP13 OPEN JP14 SHORT Base address DOOOH JP15 OPEN JP16 SHORT JP11 OPEN No digital ground connection to shield signals DAS 429P104 Mx User s Manual page 5 3
28. e MSB Hi Byte Lo Byte LSB 15 8 7 0 EE PEP PE PPP 15 8 7 0 e MSB Hi Byte Lo Byte Label LSB Data Word Hi Data Word Lo Figure 4 2 Rcv Data Word Format DAS 429P 104 Mx User s Manual page 4 3 Receive Monitor Mode NOTE 1 The data in ARINC 429 bit 32 is not a parity bit but a parity status bit 0 denotes odd parity received while 1 denotes even parity received 2 The ARINC word bits are received in the following order Serial Data In Label MSB LSB LSB MSB 3 Bits 09 through 29 are ordered from LSB to MSB opposite from the Label field which is organized MSB to LSB It is for this reason that the data block is built the way it is 4 2 3 Time Tag Word Description The Time Tag is a 32 bit word made up of two 16 bit words Time Tag Hi and Time Tag Lo The resolution of the time tag is 10 usec bit EE EE 15 8 7 0 e MSB Hi Byte Lo Byte LSB Time Tag Word Lo Time Tag Word Hi Figure 4 3 Time Tag Word Description NOTE There is a latency between the time a word is received on the bus and the time that word is recorded in dual port RAM This latency is affected by the number of channels and data rate of these channels The time tag reflects the time the word is written to dual port RAM rather than the time the word is received over the bus In no event shall this latency exceed a single hi speed word time i e 360 microsecond
29. e address must be on a word boundary Receiver Merge Word Counter Address 0028 H READ WRITE The Receiver Merge Word counter indicates the number of ARINC words received 0 65535 This register wraps around to 0 after it reaches 65535 You can reset it only when the channel is stopped DAS 429P 104 Mx User s Manual page 2 9 Module Operation 2 4 6 2 4 7 2 4 8 page 2 10 Receiver Merge Buffer Wraparound Register Address 002A H READ WRITE The Receiver Merge Buffer Wraparound register contains 2 bits for synchronization with the host If bit 14 is set to 1 the receive buffer has wrapped around once since the last time this register was cleared If bit 15 is set to 1 there have been multiple wraparounds You are expected to clear bit 14 each time the first word of the buffer is read When the module wraps around it checks bit 14 If bit 14 is not set the module sets it otherwise the module sets bit 15 NOTE Excalibur C drivers handle these bits If you use these drivers you don t need to deal with them Bit Description 15 Multiple Wraparound Data Lost 14 Single Wraparound 00 13 0 Receiver Merge Buffer Wraparound Register Receiver Merge Word Count Trigger Register Address 002C H WRITE The Receiver Merge Word Count Trigger register lets you generate an interrupt and set a flag which indicates when a specific number of words have been received 1 65535 If you want to generate an interrupt you must al
30. eive Look Up Table Status Control Word 4 8 4 4 Receive Channel Control Register Block Maps 4 9 4 4 1 Channel 0 Control Register Block Map 4 9 4 4 2 Channel 1 Control Register Block Map 4 10 4 4 3 Channel 3 Control Register Block Map 4 11 4 4 4 Channel 4 Control Register Block Map 4 12 4 5 Receive Channel Control Heosiers sesse ee ee 4 12 4 5 1 Channel x Configuration Register i 4 12 4 5 2 Channel x Receive Data Start Pointer ee ee Re ee ee 4 14 4 5 3 Channel x Receive Data End Pointer ee ee ee ke ee ke 4 14 4 5 4 Channel x Receive Data Current Pointer ii 4 14 4 5 5 Channel x Receive Look Up Table Start Address eke ee 4 14 4 5 6 Channel x Receive Filter Table Start Address 4 15 4 5 7 Channel x Rev Data Word Count Register i 4 15 4 5 8 Channel x Rev Buffer Wraparound Register iese ese ee ek ke 4 15 4 5 9 Channel x Rev Data Word Counter Trigger Register sees esse ee ee 4 16 4 5 10 Channel x Rev Interval Counter Trigger Register sesse ese ee 4 16 4 5 11 Channel x Rev Label Trigger Register i 4 16 4 5 12 Channel x Interrupt Condition Register ii 4 17 4 5 13 Channel x Status Heglster see ee Re Re ee RR Re Re ee ee 4 18 5 Mechanical and Electrical Specifications 5 1 SG 10 Layout Eeer 5 1 luet 5 2 5 2 1 Shield Signal Jumper 5 2 5 2 2 Base Address
31. errupt Condition Register WRITE The Channel x Interrupt Condition register sets which conditions cause interrupts to be generated by the module Only the two least significant bits are used for transmit channels and only bits 02 through 06 are used for receive channels See Channel x Interrupt Condition Register in Receive Monitor Mode page 4 17 Bit Description Interrupt Conditions 07 15 0 02 06 Not used in Transmit mode 01 Transmitter End of Frame See Note 2 below 00 Transmitter End of Block See Note 1 below Channel x Interrupt Condition Register Transmit Mode NOTE 1 The End of Block interrupt will occur at the completion of transmission of each Instruction Block 2 The End of Frame interrupt will occur at the completion of transmission of the final Instruction Block or in loop mode at the end of each loop cycle Excalibur Systems Inc 3 2 8 3 3 Transmit Mode Channel x Status Register READ WRITE The Channel x Status register indicates the operational status of the channel You can use this register to poll the status of the channel or it can be used with interrupts When used in conjunction with interrupts the register indicates the condition s which caused the interrupt A logic 1 indicates an active bit You must reset the status bits Only the two least significant bits are used for transmit channels and only bits 02 through 06 are used for receive channels See Channel x Status
32. f the ARINC 429 bus both in the lab and in the field The DAS 429P104 Mx is based on the latest Surface Mount Technology which substantially reduces the area required The card occupies 32K bytes of the host computer s memory map The DAS 429P104 Mx comes configured with 2 x transmit and 4 x receive channels where x number of modules ordered The channels are organized in two independent modules P N M429R4T2 each configured with 4 receive and 2 transmit channels Each module contains an on board hi speed controller and 16K x 16 true dual port RAM Each module is accessed through a banking mechanism and operates independently You can set up each module to generate interrupts to the host in a variety of circumstances through an extensive interrupt structure Both transmit and receive channels may be programmed for Hi 100Khz or Lo 12 5Khz speed bit rates In addition either odd or even parity may be programmed for transmit channels All control registers and data blocks can be accessed directly in real time The card supports filtering of receive data and multiple data storage modes Status and time tag information are appended to each word The transmit channels operate via a transmitter instruction stack which allows scheduling of data transmissions and reduces the need for host computer intervention The DAS 429P104 Mx comes complete with C driver software libraries including source code The DAS 429P104 Mx is ideally
33. figuration Register Receive Mode in Receive Monitor Mode page 4 13 The module ignores unused bits e g receiver related bits for a transmitter channel Bit Bit Name Description 10 15 0 09 Receiver Enable Filter Not used in Transmit mode Table 08 0 07 Receiver Label Trigger Not used in Transmit mode 06 Receiver Wrap Around Not used in Transmit mode 05 Receiver Storage Mode Not used in Transmit mode 03 04 0 02 Transmit Rise Fall Time 1 Low Speed 10 5 usec 0 High Speed 1 5 0 5 usec 01 0 00 Bit Rate 12 5 KHz Lo speed 1 0 100KHz Hi speed Channel x Configuration Register Transmit Mode Excalibur Systems Inc Transmit Mode 3 2 2 3 2 3 3 2 4 NOTE 1 It is recommended that you set up all active channel Configuration Registers before programming any other parameters 2 You can only write to this register when all channels are turned off via the Start Register 3 You should start the module via the Start Register only after a minimum of 500 usec from the time that the contents of this register have been modified Channel x Tx Instruction Stack Pointer WRITE The Channel x Transmit Instruction Stack pointer sets the starting address of the TX Instruction Stack The address must be a word boundary within the Tx Instruction Stack area For example to place the Transmit Instruction stack at location 300 H write a 300 H to this register Channel x Tx Inst
34. ious run parameters for Merge Mode Bit Bit Name Description 10 15 Reserved 0 09 Enable 1 Enable filter table Stores Labels per table Receive Filter 0 Disables table Stores all Labels Table 08 Reserved 0 07 Receive Label 1 Start data storage upon receipt of Label xx Trigger 0 Receiver stores data without Start Label Trigger 06 Receiver Wrap 1 Data storage is halted when the buffer is full Around 0 Receiver wraps around the data in the block 00 05 Reserved 0 Receiver Merge Configuration Register DAS 429P 104 Mx User s Manual page 2 11 Module Operation 2 4 11 Receiver Merge Interrupt Condition Register Address 0036 H WRITE The Receiver Merge Interrupt Condition register selects which conditions will cause an interrupt to be generated Bits 02 06 are the Interrupt Condition bits Bit 07 15 06 05 04 03 02 00 01 Description Interrupt Conditions 0 Stopped on Buffer Full see bit 06 in Receiver Merge Configuration Register page 2 11 Error Word Received Data Word Count Trigger Interval Count Trigger Label Received see Figure 4 5 Label Control Byte Structure page 4 5 Reserved Receiver Merge Interrupt Condition Register NOTE 1 The Label Received interrupt only occurs upon reception of page 2 12 a label which has been marked for interrupt in the filter table 2 To activate the Interval Count Trigger interrupt you must also set the Receiver Merge Interval
35. ipt of any label for which an interrupt has been requested via the label s Control byte In Sequential Mode it is set upon receipt of any label for which an interrupt has been requested via the filter table Excalibur Systems Inc page 4 18 Mechanical and Electrical Specifications 5 Mechanical and Electrical Specifications Chapter 5 describes the mechanical and electrical specifications of the DAS 429P104 Mx card The following topics are discussed e Card Layout page 5 1 e Jumpers page 5 2 e Connectors page 5 4 e Power Requirements page 5 7 5 1 Card Layout MODULE 1 MU2 7 e STEEN EE Al EE Figure 5 1 Card Layout DAS 429P104 Mx User s Manual page 5 1 Mechanical and Electrical Specifications 5 2 5 2 1 5 2 2 page 5 2 Jumpers Jumpers are provided on the card for various functions These jumpers are occupied with jumper headers and are shorted with shorting blocks at default places See Factory Default Jumpers Settings page 5 3 Jumpers not appearing on Card Layout are factory set and should not be used Shield Signal Jumper JP11 The Shield Signal jumper allows you to short the Shield signal on connectors J1 and J2 to Digital Ground Use this option only if connection at the mechanical pads cannot be provided Base Address Select Jumpers JP12 JP16 The Base Address Select jumper group selects the Card Base Address Each jumper selects one a
36. ister Block Map DAS 429P104 Mx User s Manual Receive Monitor Mode page 4 11 Receive Monitor Mode 4 4 4 Channel 4 Control Register Block Map Figure 4 10 Channel 4 Control Register Block Map 4 5 Receive Channel Control Registers 4 5 1 Channel x Configuration Register The Channel x Configuration register sets up various run parameters for both the receive and transmit channels see Channel x Configuration Register in Transmit Mode page 3 2 Bits which are unused e g transmit related bits for a receiver channel are ignored by the module page 4 12 Excalibur Systems Inc Bit 10 15 09 08 07 06 05 03 04 02 01 00 Receive Monitor Mode Bit Name Description 0 Receiver Enable 1 Enable Filter Table Stores labels per table Filter Table 0 Disables table Stores all labels 0 Receiver Label 1 Start data storage upon receipt of Label xx Trigger 0 Receiver stores data without Start Label Trigger see Receiver Wrap Around Receiver Storage Mode Note 4 below 1 Data storage is halted when the buffer is full 0 Receiver wraps around the data in the block This bit is used in the Sequential Storage Mode only See Sequential Merge Mode Operation page 4 2 1 Sequential Storage Mode 0 Look up Table Mode see Channel x Receive Look Up Table Start Address page 4 14 0 Transmit Not used in Receive mode Rise Fall Time 0 Bit Rate 1 12 5
37. it Description 15 Multiple Wraparound Data Lost 14 Single Wraparound 00 13 0 Channel x Rcv Buffer Wraparound Register DAS 429P104 Mx User s Manual page 4 15 Receive Monitor Mode 4 5 9 4 5 10 4 5 11 page 4 16 Channel x Rev Data Word Counter Trigger Register WRITE SEQUENTIAL MODE The Channel x Rev Data Word Counter Trigger register lets you generate an interrupt and set a flag which indicates when a specific number of words have been received 1 65535 If you want to generate an interrupt you must also set the appropriate bit in the Channel x Interrupt Condition Register See Channel x Interrupt Condition Register page 4 17 NOTE This trigger is set when the value in the Channel x Receive Data Word Counter matches the value set in this register Channel x Rev Interval Counter Trigger Register WRITE SEQUENTIAL MODE The Channel x Rev Interval Counter Trigger register lets you generate an interrupt and set a flag upon reception of every n number of words where n is the value written to this register For example to request an interrupt after every 5 ARINC words write 05 to this register If you want to generate an interrupt you must also set the appropriate bit in the Channel x Interrupt Condition Register See Channel x Interrupt Condition Register page 4 17 Channel x Rev Label Trigger Register WRITE SEQUENTIAL MODE The Channel x Rev Label Trigger register is used in conjuncti
38. k in an identical manner Perform the following procedure after every time you power up or reset the software To determine whether a module is installed and ready to operate 1 Check the Module ID register test for value E429 H 2 Check the Module Status Register see Module Status Register Note 1 page 2 6 The module is installed and ready when both registers contain the correct values as written above For software reset operations set these values to 0 immediately prior to writing to the Card Software Reset register Module General Operation The M429R4T2 module operation makes extensive use of pointers for setting up the size and location of both receiver and transmitter data blocks transmitter instruction stacks and receiver look up tables Pointers on the card represent byte offsets into the memory area of the card Each channel has its own pointer registers so that unique memory areas may be allocated for each channel It is also possible for multiple channels to share memory areas For example more than one receiver channel may point to and use the same Label Look Up Table which controls which labels will be stored by the card After power up or reset the module is initialized in a wait loop looking for a Start command from the host computer This command issued by writing to the Module Start Register instructs the module to begin operation on the active channel s DAS 429P 104 Mx User s Ma
39. lue of 1 to the appropriate bit will reset the corresponding Module interrupt request Writing a value of 0 has no effect Bit Description 02 15 X Don t Care 01 Module_1 Interrupt Reset 00 Module_0 Interrupt Reset Global Interrupt Reset Register Global Interrupt Status Register Address 0006 H READ The Global Interrupt Status register indicates the card pending interrupts status A value of 1 at the appropriate bit indicates a corresponding Module active interrupt A value of 0 indicates no interrupt has been generated Bit Description 02 15 X Don t Care 01 Module_1 Interrupt Status 00 Module 0 Interrupt Status Global Interrupt Status Register DAS 429P 104 Mx User s Manual page 1 7 Introduction page 1 8 Excalibur Systems Inc 2 1 Module Operation Module Operation Chapter 2 describes the general principle of module operation the module memory map and the module control registers The following topics are covered e Module General Operation page 2 1 e Module Memory Map page 2 3 e Module Control Registers page 2 4 e Receiver Merge Mode Control Registers page 2 9 Each bank Module handles 4 receive and 2 transmit channels is controlled by its own processor and works independently of the other banks All 12 channels may be run simultaneously although you may only access one bank six channels at a time The manual describes the functionality of a single bank all banks wor
40. n the sequential mode of operation The data will wrap around or stop when the buffer is full when the end address is reached depending upon the contents of the Receiver Wrap Around control bit in the Configuration Register 4 5 4 Channel x Receive Data Current Pointer READ The Channel x Receive Data Current pointer indicates the current address where the next ARINC receive word is to be placed in the buffer This pointer value is incremented after the entire receiver block ARINC word time tag and status is written into memory 4 5 5 Channel x Receive Look Up Table Start Address WRITE LOOK UP TABLE MODE The Channel x Receive Look Up Table Start address sets the start address of the 256 x 16 Receiver Look Up Table see bit 05 in Channel x Configuration Register Receive Mode page 4 13 This address represents the byte offset into the modules memory of the first location of the look up table The module will store one ARINC 429 data block for each Label received The data block contains 32 bit ARINC 429 word 32 bit Time Tag and the 16 bit Receive Status word The 429 data block will be overwritten by the subsequent reception and storage of another ARINC 429 word with the same ARINC Label The address must be a word boundary see Figure 4 6 NOTE After reset the Channel x Receive Look Up Table Start Address register is loaded with a default value of 7E00 H page 4 14 Excalibur Systems Inc 4 5 6 4 5 7 4
41. nts are in use by the BIOS and any other adapter cards already installed on your computer WARNING If a segment is already in use and it is also used for DAS 429P104 Mx the card will exhibit unpredictable behavior It may work in some modes but not others it may seem to work fine yet exhibit intermittent errors it may not function at all Once a free segment is found the Base Address Select jumpers JP12 JP16 should be set accordingly The Interrupt Select jumpers JP17 JP27 should be set to the required interrupt line if using interrupts Once all the jumpers are correctly set make certain the computer power source is disconnected While using a suitably grounded electrostatic discharge wrist strap install the DAS 429P104 Mx card on top of the other cards in your system Once the card is installed the mating 16 pin header socket wired with the ARINC 429 connections should be attached to the card Excalibur Systems Inc Introduction 1 3 General Memory Map The DAS 429P104 Mx occupies 32K bytes of the host computer s memory map This is divided into two sections Module Memory Area and four Global Registers The Module Memory Area contains 64Kb of dual port RAM divided into 2 banks of 32Kb each You can change banks via the Global Bank Select Register defined below The Global Registers are independent of the selected bank and include appropriate control bits for all the banks Modules Module 0 Memory Area Module
42. nual page 2 1 Module Operation page 2 2 The transmitter and receiver operations necessary to operate the card are described below in general terms See Transmit Mode page 3 1 and Receive Monitor Mode page 4 1 for details Perform these steps after power on 1 Set and verify the Module Control registers e You can check the results of the power on self test by reading the Module Status register Set the Transmitter related Channel Control registers e Program the Channel Configuration registers bit rate rise time etc e Update the Transmit Instruction Stack pointer for each channel e Update the Transmit Instruction counter Set the Tx Instruction blocks e Update the Instruction Blocks with information relating to each ARINC TX data block Ge parity pointer to the Tx Data blocks delay between data blocks See Transmit Instruction Stack page 3 5 for details Write the Tx Data blocks e Write the ARINC words into the on board memory at locations pointed to by the instruction stack s TX Data pointers Set up the Receiver related Channel Control registers e Program the Channel Configuration registers bit rate etc e Update the receive data Start and End pointers e Update the Look Up Table Start Address register if using this mode e Update the Filter Table Start Address register e Update the Label Trigger register if using a Label to start storage
43. of 350 usec between writes to the Start Stop register page 2 4 Excalibur Systems Inc Bit 06 15 05 04 03 02 01 00 Bit Name 0 Channel 5 Start Bit Channel 4 Start Bit Channel 3 Start Bit Channel 2 Start Bit Channel 1 Start Bit Channel 0 Start Bit Start Stop Register Module Operation NOTE 1 A change in a channel s Configuration register or in the Receiver Data Storage Mode register is acted upon by the firmware only after the Start Stop register contains a 0 for at least 1 msec 2 When a transmit channel channels 2 or 5 has completely finished transmitting all of its data its start bit is automatically cleared Address 0012 H READ The Module Status register indicates the result of the self test of the 2 3 2 Module Status Register module Bit Bit Name 15 Internal Error 07 14 Reserved 06 Memory 05 Channel 5 Status Bit 04 Channel 4 Status Bit 03 Channel 3 Status Bit 02 Channel 2 Status Bit 01 Channel 1 Status Bit 00 Channel 0 Status Bit Module Status Register DAS 429P104 Mx User s Manual Description 1 Error 0 OK 1 OK 0 Memory Test Fail 1 Self Test OK 0 Self Test Fail 1 Self Test OK 0 Self Test Fail 1 Self Test OK 0 Self Test Fail 1 Self Test OK 0 Self Test Fail 1 Self Test OK 0 Self Test Fail 1 Self Test OK 0 Self Test Fail page 2 5 Module Operation 2 3 3 2 3 4 page 2 6 NOTE 1 Module status should be tested by che
44. ol Registers page 3 2 e Transmit Instruction Stack page 3 5 e Transmit Data Block Format page 3 7 Perform the following procedure to implement the transmit mode 1 Create an instruction stack for the transmitter channel 2 Write the data into the dual port RAM 3 Start transmission by writing to the Start register found in the Module Control Register area The sequence of writes to memory is not important except that writing to the Module Start Register step 3 above must be performed last Transmit Channel Control Register Block Maps Channel 2 Control Register Block Map Channel 2 Configuration Register 00E0 H Figure 3 1 Channel 2 Control Register Block Map DAS 429P 104 Mx User s Manual page 3 1 Transmit Mode 3 1 2 3 2 3 2 1 page 3 2 Channel 5 Control Register Block Map Channel 5 Configuration Register 0170H Reserved 0172 018A H Channel 5 TX Instruction Stack Pointer 018C H Channel 5 TX Instruction Counter 018E H Channel 5 TX Loop Counter 0190 H Channel 5 TX Current Word Register 0192 H Channel 5 TX Current Loop Register 0194 H Channel 5 Interrupt Condition Register 0196 H Channel 5 Status Register 0198 H Reserved 019A 019E H Figure 3 2 Channel 5 Control Register Block Map Transmit Channel Control Registers Channel x Configuration Register The Channel x Configuration register sets up various run parameters for both the receive and transmit channels see Channel x Con
45. on with the Receiver Label Trigger bit in the Channel x Configuration Register see Channel x Configuration Register in Transmit Mode page 3 2 and Channel x Configuration Register Receive Mode page 4 13 This register enables the reception and storage of data upon receipt of a unique ARINC 429 label All ARINC words received prior to the first instance of this label will not be stored by the board ov J w 15 8 r 0 Channel x Rev Label Trigger Register Excalibur Systems Inc Receive Monitor Mode 4 5 12 Channel x Interrupt Condition Register WRITE The Channel x Interrupt Condition register selects which conditions will cause an interrupt to be generated Only the two least significant bits are used for transmit channels and only bits 02 through 06 are used for receive channels See Channel x Interrupt Condition Register in Transmit Mode page 3 4 Bit 07 15 06 05 04 03 02 01 00 Description Interrupt Conditions 0 Receiver Stopped on Buffer Full Receiver Error Word Received Receiver Data Word Count Trigger see Note 3 below Receiver Interval Count Trigger see Note 2 below Receiver Label Received see Note 1 below Not used in Receiver mode Not used in Receiver mode Channel x Interrupt Condition Register Receive Mode NOTE 1 The Label Received interrupt only occurs upon reception of a label which has been marked for interrupt in a filter table or
46. ruction Counter WRITE The Channel x Transmit Instruction counter sets the number of TX Instruction blocks to process These instruction blocks taken together comprise a frame Channel x Tx Loop Counter WRITE The Channel x Transmit Loop counter sets the number of times to execute the TX instruction blocks the frame N Times or Continuous Loop If the continuous value is selected the channel s operation can be terminated by setting the related channel bit in the Module Start Stop register to a 0 Value 0000 Continuous 0001 One Time 0002 Two Times FFFF 65535 Times DAS 429P104 Mx User s Manual page 3 3 Transmit Mode 3 2 5 3 2 6 3 2 7 page 3 4 Channel x Tx Current Word Register READ The Channel x Transmit Current Word register contains the number of words that have already been sent in the current loop This allows you to determine which word is currently being sent out The register is updated as the last bit of the word is transmitted After the first word in a loop goes out the register will be incremented to 1 After the final word in a loop goes out the register will be updated to 0 Channel x Tx Current Loop Register READ The Channel x Transmit Current Loop register contains the number of times the TX instruction blocks have been executed i e the number of loops completed NOTE The TX Current Word register is cleared before the TX Current Loop register is incremented Channel x Int
47. s page 4 4 Excalibur Systems Inc Receive Monitor Mode 4 2 4 Rev Sequential Mode Filter Table Diagram Figure 4 4 below illustrates the structure of the filter table 256 x 8 Receiver Filter Table Control Byte for Label 377 octal Control Byte for Label x Control Byte for Label 1 RCV Filter Table Pointer gt Control Byte for Label 0 Sets the start address of the label filter table Figure 4 4 Rev Sequential Mode Filter Table Bit Description 02 07 Reserved 01 1 Interrupt 0 Don t Interrupt 00 1 Store Word 0 Don t Store Figure 4 5 Label Control Byte Structure WRITE DAS 429P 104 Mx User s Manual page 4 5 Receive Monitor Mode 4 2 5 Receive Sequential Mode Status Word READ Bit Bit Name Description 08 15 Reserved 07 Valid Word Global Bit Indicates that the received ARINC 429 word was valid in all respects 04 06 Reserved 03 Parity Error Indicates that a parity error was detected in the ARINC 429 word 01 02 Reserved 00 Word Received A logic 1 This bit is cleared while data is in the process of being updated When the bit is set valid data is in memory Receive Sequential Mode Status Word READ 4 2 6 Receive Merge Mode Status Word READ Bit Bit Name Description 11 15 Reserved 08 11 Merge Channel 100 Data received over channel 4 07 04 06 03 01 02 00 Code Valid Word Reserved Parity Error Reserved Word Received 011 Data received over channel 3 00
48. s Word received is tagged with a Channel code indicating on which channel the data was received Each data block contains a Time Tag word as in the standard Sequential Mode of operation Sequential Merge Mode Operation Receive Buffer Storage Sequence Figure 4 1 below illustrates the way in which the receive data blocks are stored in the dual port RAM while in the sequential mode of operation The Start and End pointers set up the buffer size The receive data storage will stop when the end pointer is reached or will wrap around to the beginning of the buffer depending upon the condition of the Receiver Wrap Around bit in the Channel Configuration Register The Time Tag resolution is 10 usec bit The contents of the Receiver Status Word are described in this section in Receive Sequential Mode Status Word page 4 6 and Receive Merge Mode Status Word page 4 6 Excalibur Systems Inc 4 2 2 Receive Monitor Mode ROV Daa Eng Pomer IE TEN Written by user Tine Tg Wor NIE EN Nth block scie Saus Word BERN ET EN O Daawa Second block Seeche BERN ET EN Soen Fov Daa san Pomer gt Data Word Lo rusboa Written by user Figure 4 1 Rev Sequential Mode Buffer Structure Rev Data Word Format The received 32 bit ARINC 429 word is stored as two 16 bit words in the memory Lo Word followed by Hi Word The numbers shown in the two words represent the ARINC 429 bit locations in the 32 bit word
49. single receive data block Alternatively the sequential mode offers you the capability of storing just the ARINC 429 data without the Time Tag and Status Words via the Receiver Data Storage Mode Register described in Module Control Registers page 2 4 Interrupts and pollable status registers allow for numerous types of event recognition and are described in Receive Channel Control Registers page 4 12 DAS 429P 104 Mx User s Manual page 4 1 Receive Monitor Mode 4 1 2 4 2 4 2 1 page 4 2 Look Up Table Mode Overview In the Look up table mode the word s label is used by the module as an offset to a 256 word look up table You can program the table with address pointers indicating where to write the Receiver Data Block Each block contains the 32 bit ARINC word 32 bit Time Tag word and status word The 256 word table can be placed anywhere in the memory via Receiver Look up Table Pointer which you can program You can poll the operational status of each channel and generate interrupts in various circumstances see Channel x Interrupt Condition Register page 4 17 Merge Mode Overview The Merge Mode operates in the same manner as the Sequential Mode except that all receive channels are merged into one data buffer area The control registers for the Merge Mode are located and defined in Module Control Registers page 2 4 In this mode the receive data blocks are stored in sequential order and each Statu
50. so set the appropriate bit in the Receiver Merge Interrupt Condition Register See Receiver Merge Interrupt Condition Register page 2 12 NOTE This trigger is set when the value in the Receiver Merge Word Counter matches the value set in this register Receiver Merge Interval Count Trigger Register Address 002E H WRITE The Receiver Merge Interval Count Trigger register a 16 bit value lets you generate an interrupt and set a flag upon reception of every n number of words where n is the value written to this register For example to request an interrupt after every 5 ARINC words write 05 to this register If you want to generate an interrupt you must also set the appropriate bit in the Receiver Merge Interrupt Condition Register See Receiver Merge Interrupt Condition Register page 2 12 Excalibur Systems Inc 2 4 9 2 4 10 Module Operation Receiver Merge Label Trigger Register Address 0032 H WRITE The Receiver Merge Label Trigger register is used in conjunction with the Receiver Label Trigger bit in the Receiver Merge Configuration Register to begin the reception and storage of data upon receipt of a unique ARINC 429 label All ARINC words received prior to the first instance of this label will not be stored by the board RIET 15 8 7 0 Receiver Merge Label Trigger Register Receiver Merge Configuration Register Address 0034 H WRITE The Receiver Merge Configuration register sets up var
51. suited for developing simulating testing and monitoring ARINC 429 interfaces for multi channel applications requiring a single PC 104 card For industrial environment applications the DAS 429P104 Mx is available in an extended temperature 40 to 85 C version See Ordering Information page 6 1 for the exact part numbers DAS 429P 104 Mx User s Manual page 1 1 Introduction page 1 2 DAS 429P104 Mx Card Features Up to 8 Receive and 4 Transmit channels on a PC 104 card Organized in 2 modules each containing e 4 Receive channels e 2 Transmit channels e 16k x16 true dual port RAM e On board 32 bit processor 12 5k bit and 100k bit data rates Selectable even odd parity Programmable interword gap Transmission modes e One shot e Loop e N times Two Receive Monitor modes e Sequential e Look up table 82 bit time tagging per word Merge mode stores data from multiple receive channels in one buffer Label filtering Start triggers Receive count interval triggers Interrupt and polling modes of operation PC 104 compliance e Occupies 32K 1 2 segment of the memory map e All interrupt lines selectable Real time operation Extended temperature 40 to 85 C version available Excalibur Systems Inc Introduction Figure 1 1 below illustrates the DAS 429P104 Mx s block diagram i Receive channel

DAS-429P104/Mx User`s Manual, Rev A

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