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User`s Manual (Rev.1.05)

1. Li a a s Povenpeisocas s 5 s weno Pomo Ls p creme fon TA WEN CRM a a e 7 Pn 0208 REC eU gt JCPU2 Connector USER S MANUAL Rev 1 05 13 RTE V850E MA1 CB USER S MANUAL Rev 1 05 6 6 1 CONNECTION WITH THE HOST PC RS 232C CONNECTION Serially connect the host machine using the monitor ROM by means of the following procedure lt 1 gt lt 2 gt lt 3 gt lt 4 gt Get an optional RS 232C cable and a power supply Set and check the setting of the switches on the board Specify a baud rate by using SW1 see Sections 12 1 2 and 13 1 1 Connect the JSIO1 connector and host machine with the RS 232C cable and supply power to the JPOWER connector Confirm that the POWER LED on the board lights and that the 7 segment LED indicating that the monitor has started lights F If the LED does not light turn off the power immediately and l check the connection Start the debugger on the host machine and connect it via the RS 232C interface If an error occurs confirm the connection of the serial cable and the setting of the switches especially baud rate For the method and procedure of starting the debugger see the debugger manual Place the board on an insulating material If a conductive material touches the board while power is supplied to the board the board
2. 13 1 2 Connection of Board Connect the board to the PC serially by referring to Chapter 6 43 RTE V850E MA1 CB USER S MANUAL Rev 1 05 13 2 PARTNER MONITOR 13 2 1 13 2 2 13 2 3 13 2 4 13 2 5 13 2 6 7 Segment LED on Startup The 7 segment LED of the ROM monitor for PARTNER operates as follows when power is supplied to the board black indicates the segment that lights 1 Check operation of 7 segment LED See figure below If SW1 8 is OFF E EH If SW1 8 is ON 2 Number counting by simple RAM memory check Not executed if SW1 8 is OFF 3 Connection wait status 4 Connection s tatus ll ROM Monitor Work RAM The ROM monitor uses the first 32K byte area 4F8000H to 4FFFFFH in the SRAM as work RAM In other words user programs are not allowed to use this area or its image area Monitor Interrupt The interrupt selected by SW2 5 is used for monitor communication and forced break ESC button SP Setting The stack pointer initial value is set to 4F 7FFOH by the monitor The monitor uses a 32 byte stack area set by the user program Initializing Hardware The ROM monitor performs initialization so that the resources on the board can be directly accessed Special Instruction The monitor uses the following instruction for the single step breakpoint and system call functions BRKTRAP instruction Oxnn40 Do not use a code that may be interpreted as a break instruction in the use
3. 40 12 L3 Connection OF BOAO Et A bee ee EE oa x ERR 40 12 2 Multi MONTOR cte beet t aa e c crate E Ra tO ies 41 12 2 1 7 Segment LED on 41 12 2 2 ROM Monitor Work 00000006000000000000 00000000 000000 nnne nn 41 12 2 3 Monitor Interr pt i i reete t Edd YR ee Aene tives 41 12 24 INU SP Setting t te at AR UR 41 13 14 RTE V850E MA1 CB USER S MANUAL Rev 1 05 12 2 5 Timer Interrupt i ed e HA e Re E Hg eb ebd get 41 12 2 6 Initializing nnns 41 12 2 7 Special Instr clion Lore e Lo Le 42 129 RIE COMMANDS cotilla lo 42 12 91 HELP einen 42 12 3 2 INET aiite NN 42 RCM IL id 42 12 3 4 SFR Command iie 42 APPENDIX B PARTNER MONITOR nennen nn 43 13 1 22 2 ennemi reet rennen eeu pa eee dee En due 43 13 1 1 SW 1 Setting ore tee Ph Rn rE RE n ene d 43 13 1 2 Connection of 9 43 13 2 court ES 44 13 2 1 7 Segment LED on 9 44 13 2 2 ROM Monitor Work nhe nnns nnne 44 13 2 8 Mo
4. RESTRICTIONS NOTES ON BREAKPOINTS Note that the following restrictions and notes must be observed when a breakpoint is set or executed single step in an interrupt handling routine 1 During a break all maskable interrupts are rejected 2 The single step function sets a temporary breakpoint in the next instruction As a result even though the user program in the El enable interrupt status is executed on a single step basis execution can branch to the interrupt handler for handling of an interrupt while one instruction is being executed Be sure therefore to observe the points noted regarding breakpoints during single step execution 3 Exiting from the interrupt handling routine by single stepping is impossible Specifically single stepping based on the last of the interrupt handling routine is disabled Similarly reti instruction single stepping is impossible The Return function of the debugger does not support return from an interrupt handling routine to the original routine 29 RTE V850E MA1 CB USER S MANUAL Rev 1 05 10 CPU PIN CONNECTION This chapter explains the uses of the CPU pins in the RTE V850E MA1 CB 10 1 PIN CONNECTION LIST The table below lists the uses of the main CPU pins Details are given in the subsequent sections Pin name Use Section AAA A 5 PDLO 15 D0 15 Used asthesystemdatabus 0 15 0 15 0 9 16 25 Used as the system address bus f PCT4 RD Used as the system
5. ee a 9 5 12 AVDD AVREF SELECTOR JUMPER 4 2 9 DIC RO LAC AM RT wt CE E TN 9 5 14 SELF WRITING POWER CONNECTOR JVPP ssscsccsesseseesesseststsetsesstsetstseeseseeees 9 5 15 FLASH WRITING CONNECTOR JFLASH The JFLASH connector is used to write data to the CPU s internal flash ROM by using a flash programmer device To use JFLASH SW4 must be set see Section 5 6 10 5 16 SERIAL CONNECTOR JSIO1 2 11 5 17 JGBUS CONNECTOR 5 11 5 18 CPU CONNECTOR JCPU1 2 12 6 CONNECTION WITH THE 1 nn nn nnns nnns nnne nnn 14 6 1 85 2320 CONNECTION ai Qoae ee dn RR va 14 7 HARDWARE REFERENCES 15 7 1 MEMORY ipod 15 7 2 RECOMMENDED SETTING S nisreen ia iei eea 17 7 21 MEMG Registara a a ia 17 7 MEMORY RESQURGES esta 18 7 3 1 SDRAM CS1 0800000 to 18 7 3 2 SRAM CS2 0400000 to 07 5 18 7 3 3 UV EPROM CS0 0000000 to 18
6. The contents of GETC 7 0 including the direction and contents of the signals are determined by the CPU board The CPU board uses these signals to exchange special signals with the motherboard e Upper address valid signal e f this signal is low and if the CPU board is the bus master the CPU board drives a valid value on GADDR 31 26 If this signal is high the CPU board does not drive a valid signal on GADDR 31 26 and the circuits on the motherboard perform processing with all of GADDR 31 26 low Motherboard detection signal e This signal is pulled up on the CPU board and is connected to GND on the motherboard The CPU board uses this signal when it must determine if the motherboard is connected for example time over ready generation circuit of the CPU board GUSE_ Input e f this signal is low the CPU board has resources that can be accessed by the DIRECT_ACC motherboard GCLK_LOW GBLOCK 1 0 e If this signal is low the frequency of GCLK is 16 67 MHz or less If it is high the frequency of GCLK is 16 67 to 33 33 MHz e The circuits on the motherboard use this signal to determine the number of wait cycles required for accessing the resources on the motherboard Bus lock signals These signals must be valid during a bus cycle and for bus cycles that must be locked e f a bus lock signal is output by the CPU the bus lock signal is connected to the motherboard using these pins The GBLOCKO signal is vali
7. N ke ala A A E a N A oj o E A The following connectors are used CPU board side connector Kell 8817 180 170L Motherboard side connector straight Kell 8807 180 170S Motherboard side connector L angle Kell 8807 180 170L 50 RTE V850E MA1 CB USER S MANUAL Rev 1 05 14 4 14 5 PROCESSING OF UNUSED PINS Signals that are not input to the GBUS motherboard are pulled up or down on the motherboard and can be unconnected on the CPU board Signals that can be unconnected and the processing performed on the motherboard for those pins are shown below Signal name Processing GADDR S1 26 e If GADDR 31 26 are not used GADDR 31 26 can be unconnected by making the GAHI_EN signal high or by disconnecting it In this case if the CPU is the bus master all the bits of GADDR 31 26 are treated as 0 on the motherboard e Pulkup processing is performed e Pulkup processing is performed e Pulkup processing is performed e Pulkup processing is performed Pulkup processing is performed Pulkup processing is performed e Pulkup processing is performed Pulkup processing is performed Pulkup processing is performed e Pulkup processing is performed e Pulkup processing is performed e Pulkup processing is performed ALLOCATING GCS 7 0 The following table shows the allocation of the chip select signals GCS 7 0 All of
8. 0 ON input e 7 6 5 4 3 2 1 1 OFF SW2 1 corresponds to bit 1 of SW2 and SW2 8 corresponds to bit 8 of SW2 When a bit of the corresponding switch is set to ON 0 is read when it is set to OFF 1 is read SW2 is used to switch the hardware operation For the function of each switch see Section 5 4 19 RTE V850E MA1 CB USER S MANUAL Rev 1 05 7 4 4 7 Segment LED Display Data Output Port 7SEG LED 7802000H Write Only This port sets the data to be displayed on the four 7 segment LED The table below indicates the data format When a bit is set to 0 the corresponding segment is turned on Data bus Logic tas gt EM 7802000H LEDi LED1 1 01 LED1 LED1 LED1 LED1 7802001H LED2 LED2 LED2 LED2 LED2 LED2 LED2 LED2 1 Turned off output DP G F E D C B A The figure below illustrates the correspondence between the bits and the segments of the 7 segment LED DP 7 4 5 Time Over Ready LED Clear Pulse TOVRDY LED CLRPLS 7803000H Write Only If data is written to the port the TOV RDY LED which lights when time over ready occurs on the board goes off and the written data is ignored Once the TOV RDY LED is on it does not go off until data is written to the port or the board is reset 20 RTE V850E MA1 CB USER S MANUAL Rev 1 05 7 4 6 Interrupt Controller PIC 7804000H to 7804020H Read Write The PIC supports the Multi and PARTNER interrupts necessary for mo
9. 7 4 MR T 19 MOM UR 19 74 2 SW Read Port SW1 7800000H Read 19 7 4 3 SW2 Read Port SW2 7801000H Read Only sse 19 RTE V850E MA1 CB USER S MANUAL Rev 1 05 10 11 12 7 4 4 7 Segment LED Display Data Output Port 7SEG LED 7802000H Write Only 20 7 4 5 Time Over Ready LED Clear Pulse TOVRDY LED CLRPLS 7803000H Write 20 7 4 6 Interrupt Controller PIC 7804000 to 7804020H Read Write 21 7 4 7 UART TL16C550C 7807000H to 7807070 22 7 4 8 uPD71054 7808000H to 7808030FH 22 7 4 9 GBUS ACCESS CONTROL 7809000H 23 SOFTWARE 0 iaa 24 8 1 INITIALIZATION EN 24 8 2 SUCCESSIVE ACCESSES 071054 24 8 3 LIBRARIES ccc 24 8 4 EXAMPLE OF USING 5 25 DEVELOPMENT OF APPLICATIONS USING MASKABLE INTERRUPTS 26 9 1 INTERRUPT VECTOR 26 9 2 GENERAL 5 6 28 9 3 REWRITING THE ALTERNATE VECTOR AREA DURING DOWNLOADING 28 9 4 RESTRICTIONS NOTES ON 5
10. GHOLD signal indicates to the CPU board that the motherboard has no resources that can be accessed In this case the CPU board does not have to support GHOLD Bus hold acknowledge signal This signal indicates that the CPU board releases bus mastership of GBUS to the motherboard It is then asserted low The CPU board that asserts the DIRECT signal high can disconnect the GHLDA signal Bus mastership release request signal When the motherboard has bus mastership from asserting GHLDA low the CPU board asserts GBREQ low when it requires bus mastership If GBREQ is asserted low and the motherboard is in bus cycle GBLAST must be asserted in the next micro cycle the bus cycle must be completed in the next micro cycle and GHOLD must be deasserted is used to return bus mastership to the CPU board temporarily if the number of bursts in the bus cycle is large when the motherboard is the bus master or if a bus cycle with a high priority such as a refresh cycle is pending on the CPU board DMA request signals Only two cycle DMA is supported Fly by DMA is not supported These signals are asserted low if a DMA request is generated on the motherboard The CPU board must support all four DMA signals The number of DMA signals that can be asserted at the same time and can be supported by the GDMAAK signal depends on the CPU board The CPU board uses the DMAAK signal in preference to DMAAK 3 2 if correspo
11. Pulled down at 470 10 13 RESET The factors listed below trigger a CPU reset These factors reset the CPU They also system reset the board Power on reset Occurs when the power to the board is switched on e Reset request received from JROM EM Reset by input from the RESET pin of the JROMEM connector See Section 5 9 e Reset by the SW RESET Generated by the reset switch SW RESET on the rear panel See Section 5 1 Reset from JGBUS Reset signal from the board connected to JGBUS Reset from JCPU Reset signal from the board connected to JCPU e Reset from JFLASH Reset signal from the flash programmer The figure below outlines the reset signal generation logic GRESETI JROM_EML RESET r3 JFLASH RESET 31 RTE V850E MA1 CB USER S MANUAL Rev 1 05 10 3 PCMO WAITO The PCMO WAITO pin drives a READY signal if a resource in the board is accessed A time over ready occurs if the bus cycle does not close after a specific time or if a space allocated to GBUS is accessed when the GMOTHER_DETECT signal of GBUS is high when a board is not connected to GBUS If time over ready occurs TOVER_LED on the board lights and an interrupt is issued to the PIC TOVER_LED remains lit until a time over ready LED clear pulse is generated by software or the board is reset see Section 7 4 5 The configuration of the READY drive block is shown below 10 4 PCM5 SELFREF The PCM5 SELFREF pin fu
12. ROM are separated Be sure to set this signal to OFF when monitor is used OFF Upper and lower halves of ROM are separated ON Upper and lower halves of ROM are used as a contiguous area 4 BANK_LOW OFF Specifies whether either the upper or lower half of the ROM is valid when the ROM is used in bank mode OFF Selects lower half ON Selects upper half Caution To use the monitor ROM do not change the factory setting RTE V850E MA1 CB USER S MANUAL Rev 1 05 5 6 SWITCH 4 SW4 SWA specifies the mode of a CPU pin When a signal of this switch is set to OFF the corresponding CPU pin is 1 when itis set to ON the pin is O MODEO oN Directly connected to the MODEO pin of the CPU 2 ON Directly connected to the pin of the CPU CKSEL YN Directly connected to the CKSEL pin of the CPU FLASH ON when the programmer is connected to JFLASH otherwise OFF lt lt Cautions gt gt 1 Use MODE 1 0 under the following operating conditions MODE1 MODEO MODEI MODEO Operating conditions _____ conditions ROM less mode 0 16 bits Monitor can be used factory set condition ROMless mode 1 8 bits Setting prohibited Single chip mode O 0 address or FLASH Monitor cannot be used program mode Single chip mode 1 1M addresses or Monitor can be used FLASH program mode To set SW4 4 to ON set SW4 2 to OFF FLASH program mode RTE V850E MA1 CB
13. Signal name pin No output MOMO 3 TODD Oupt 2 3 4 rrr 16 68 __5 125 27 56 27 __ rss 5 a __ m mt JSIO1 Connector Signals JSIO2 CPU pin Signal name Input Connector pin number on the host side pin No output D SUB9 D SUB25 seen A Output JSIO2 Connector Signals Note JSIO2 pins 1 and 9 not used on board 5 17 JGBUS CONNECTOR JGBUS This is a 32 bit bus connector for expansion For details see Chapters 11 and 14 11 RTE V850E MA1 CB USER S MANUAL Rev 1 05 5 18 CPU CONNECTOR JCPU1 JCPU2 The CPU connector signals are connected directly to the V850E MA1 Many signals are used on the board So be careful when extracting signals from the JCPU s muss de 3 o s rue 1 A E oOo o e a _PoriTProamwance PoemnTPraaroManae s s o we J o sw 9e ema ___ P45 SCK1 ER P44 SM RXD1 67 P43 SO1 TXD1 P42 SCK0 P41 SIO RXDO P40 SO0 TXDO JCPU1 Connector Note RESET_REQ is a reset request signal line from JCPC low active 12 RTE V850E MA1 CB in 3 s as s a
14. Timer uPD71054 500 ns resolution port LED 7 segment display switch input Others CPU connector Connector with all function pins of the V850E MA1 connected GBUS connector RTE CB standard 32 bit interface 4G bytes 32 bit bus correspond to DMA FLASH interface Interface for connecting FLASH Writer Reset switch Push type RTE V850E MA1 CB USER S MANUAL Rev 1 05 5 5 1 5 2 5 3 BOARD CONFIGURATION The physical layout of the major components on the RTE V850E MA1 CB board is shown below This chapter explains each component RTE V850E MA1 CB Components Layout RESET SWITCH SW_RESET SW_RESET is a reset switch for the entire board Pressing this switch causes all the circuits including the CPU to be reset POWER CONNECTOR JPOWER The power supplied to the JPOWER connector should be one rated as listed below Voltage 5 Current Maximum of 2 A Mating connector Type A 5 5 mm in diameter Polarity Note the polarity when attaching the power connector To supply power from the JGBUS connector do not connect a power source to JPOWER SWITCH 1 SW1 SW1 is a general purpose input port switch The setting status can be read from an input port see Section 7 4 2 When the port is read a switch being set to OFF represents 1 while its being to ON represents 0 When the monitor ROM is used all SW1 switches except some are already set Set this switch for assignment with the monitor ROM by referrin
15. To rewrite these areas when the program is downloaded however rewrite only the interrupts that are used All peripherals including interrupt related peripherals can be initialized only with the reset switch on the board This means that if after a program is executed another program is loaded the peripherals will still be in the statuses set by the previous program So use the procedure below when for a program that uses a peripheral another program is to be loaded and executed 1 Disconnect the monitor 2 For resetting the board press the reset switch of the RTE V850E MA1 CB 3 Connect the monitor 4 Load and execute another program Before setting the El interrupt enable state set the DI interrupt disable state at the start of program execution then set the peripherals and vectors To disable DI or enable El an interrupt during a break with the I O register manipulation function of the debugger use the corresponding bit of the interrupt mask register IMRn the interrupt control register PICn or PnniCn is manipulated with the I O register manipulation function of the debugger during a break do nothing to the interrupt control register since the interrupt operation may not be performed correctly REWRITING THE ALTERNATE VECTOR AREA DURING DOWNLOADING A vector can be rewritten in various ways while a program is being downloaded This section shows an example in the Multi environment of GHS The method u
16. as part of the I O space This section explains mapping of the on board l O and l O devices 7 4 1 10 List The table below lists the I O areas and functions The number of wait cycles changes depending on the setting of SW2 3 BCLK LOW Number of wait Number of wait cycles 7800000 E 78000 fewe wo 7 780000 o f 7 MR JS www roo ven ones 3 7 MIO _ 7 uant eoe ___ esus evre access CONTROL 10 7 7 4 2 SW1 Read Port SW1 7800000H Read Only This port is used to read the status of SW1 The table below indicates the data format N Data bus Daabs os oo o ve pe p Physical address Setting 7800000H SW1 SW1 SW1 SW1 SW1 SW1 SW1 0 ON input 8 7 6 5 4 3 2 1 1 SW1 1 corresponds to switch 1 of SW1 while SW1 8 corresponds to switch 8 of SW1 When a bit of the corresponding switch is set to ON 0 is read When it is set to OFF 1 is read SW1 is used to set the operation of the monitor For how to set this switch see Sections 12 1 2 and 13 1 1 7 4 3 SW2 Read Port SW2 7801000H Read Only This port is used to read the status of SW2 The data format of this port is shown in the table below Data bus po Daabs sd Physical address Setting A A A 7801000 sw2 sw2 sw2 sw2 swe sw2 swe
17. down counter mode 0 By determining the counter values before and after a routine whose execution time is to be measured the execution time can be calculated Note that both timers function as down counters Note also that command recovery ROM area dummy read is required for successive accesses to the external timer Sample execution time measurement using timers define TIMERCLK 2000000 7 2 MHz define INTERVAL TIMERCLK 10 1000 10 ms 1 100 define char 0x3D80050 For I O command recovery InitTimer Timer initialization outb 0x7808030 0x74 IOWAIT Timer 1 set to mode 2 outb 0x7808010 INTERVAL IOWAIT Lower digit count of timer 1 outb 0x7808010 INTERVAL 256 IOWAIT Higher digit count of timer 1 outb 0x7808030 0 0 IOWAIT Timer 2 set to mode 0 outb 0x7808020 OxFF IOWAIT Lower digit count of timer 2 outb 0x7808020 OxFF IOWAIT Higher digit count of timer 2 return 0 LatchTimer Count latch int counti count2 counts outb 0x7808030 OxDC Timer 1 2 multiple latch countl inb 0x7808010 countl inb 0x7808010 256 Count of timer 1 count2 inb 0x7808020 count 2 inb 0x7808020 256 Count of timer 2 counts INTERVAL OxFFFF count2 INTERVAL countl return counts double total time main int
18. first micro cycle in the burst cycle of a write cycle In other words the roles of the read cycle and write cycle are switched but GREADY and GWAITI serve as data transmission ready and data reception ready signals The following charts show that a wait cycle is inserted by the GWAITI signal Read cycle GCLK GCSx GDMAAKx GADDR 31 2 GBE 3 0 GWIR GADS GBLAST GWATTI GREADY GBTERM GDATA 31 0 53 RTE V850E MA1 CB Write cycle GCLK GCSx GDMAAKx GADDRI31 2 GBE 3 0 GW R GADS GBLAST GWAITI GREADY GBTERM GDATA 31 0 14 6 4 GBTERM 3 waits 0 2 waits USER S MANUAL Rev 1 05 ES Ed E If both the GBTERM signal and GREADY signal become active at the same time the bus master completes the bus cycle after the current micro cycle ends and then starts the burst cycle again by asserting GADS active The GBTERM signal is asserted active if the target of the access does not support burst cycles or accesses are made more than the supported number of bursts Asserting the GBTERM signal only without also asserting the GREADY signal is not allowed The following chart shows that the burst cycle is canceled by the GBTERM signal GCLK GCSx GDMAAKx GADDR 31 2 GBE 3 0 GW R GADS GBLAST GWAITI GREADY GBTERM GDATA 31 0 read GDATA 31 0 write ADDR3 54 RTE V850E MA1 C
19. int addr address where we re storing the jr int jmpdest address where the jr jumps to int offset unsigned inst unsigned int offset jmpdest addr inst 0 07800000 jr opcode offset amp Ox003fffff UINT16 addr inst gt gt 16 amp Oxffff UINT16 addr 2 inst 8 OXffff __interrupt IntEntry lt Interrupt handling routine SetAJump int 0x080 0 4 8000 int IntEntry T Exception code of specified interrupt 27 RTE V850E MA1 CB USER S MANUAL Rev 1 05 9 2 9 3 GENERAL RESTRICTIONS NOTES This section describes restrictions and notes relating to the debugging of an application using a maskable interrupt 1 4 If an interrupt is generated before alternate vector setting or if an interrupt is generated with other than a valid alternate vector set a break occurs at the point where the interrupt is generated This is because the initial value of the alternate vector is an instruction for causing a branch to the break handling routine of the monitor If the relative address from an alternate vector area to the interrupt handling routine exceeds 22 bits the contents of at least one register must be destroyed or a branch relay point must be created to cause a branch to the interrupt handling routine The alternate vector area can be rewritten by the program or when the program is downloaded see Section 9 3
20. may malfunction 14 RTE V850E MA1 CB USER S MANUAL Rev 1 05 7 HARDWARE REFERENCES This chapter describes the hardware of the RTE V850E MA1 CB 7 1 MEMORY AND I O MAP The figure below shows the memory and I O mapping on the board 00000 rd UV EPROMI space lt In SINGLE CHIP MODE the internal ROM area of the CSO space taking precedence 0400000H SRAM CS2 space over the external space is mapped 0800000H SDRAM CS1 space SEH 4000000H GCS5 5000000H GCSO CS3 space 6000000H GCS1 3 7000000H On board and GCS2 4 6 8000000H Not used FFFFFFFH ROMLESS MODE space Memory Map 15 RTE V850E MA1 CB USER S MANUAL Rev 1 05 CS0 space UV EPROM GCS1 0000000 to O3FFFFF 4M bytes UV EPROM is allocated to the CSO space or the CSO space is reserved as a space for GCS 1 of GBUS On board UV EP ROM is allocated to the space when SW2 1 FBOOT is OFF When SW2 1 FBOOT is ON it is reserved as a space for GCS1 of GBUS The GCS1 space can be accessed from the CS3 6000000 to 6FFFFFF spaces By locating a flash ROM in the GCS1 space of GBUS therefore the flash ROM can be rewritten by using the monitor ROM of UV EPROM Thereafter a program can be booted from the flash ROM For GBUS see Chapters 11 and 14 In single chip mode the internal ROM space cannot be accessed from an external source CS2 space SRAM 0400000 to 07FFFFF 4M bytes SRAM is allocated to
21. read from the register is displayed When a register name is specified and data is specified after the data is written to the register The size of data is automatically determined according to the valid size of the specified register For details of the internal registers refer to the manual provided with the V850E MA1 CPU Example 1 gt SFR A list of registers is displayed Example 2 gt SFR IMR The contents of the IMR register are displayed Example 3 gt SFR IMR 55AA Data 55AAH is written into the IMR register 42 RTE V850E MA1 CB USER S MANUAL Rev 1 05 13 APPENDIX PARTNER MONITOR This chapter describes how to make the settings required to establish a connection between the PARTNER monitor stored in ROM and the PARTNER on the host It also provides notes on the use of the PARTNER monitor 13 1 BOARD SETTING 13 1 1 SW1 Setting SW1 is a switch for general purpose input ports For the PARTNER monitor in the factory installed ROM SW1 is used as shown below ON Setting ON 115 200 baud OFF ON 38 400 baud 19 200 baud 9 600 baud Factory set Baud Rate Setting Always use this switch in this status Setting ON Monitor is started in test mode OFF Normal use state Factory set Debug Mode Setting SW1 5 to SW1 7 are not used with the PARTNER monitor If SW1 8 is set to ON it takes some time to start the monitor The monitor also lights the LED Usually keep this switch set to OFF
22. start_count stop_count InitTimer start_count LatchTimer Start count value func stop_count LatchTimer Stop count value total_time double stop_count start_count double TIMERCLK Seconds return 0 include lt time h gt func Time measurement routine 25 RTE V850E MA1 CB USER S MANUAL Rev 1 05 9 9 1 DEVELOPMENT OF APPLICATIONS USING MASKABLE INTERRUPTS This chapter describes the methods of developing an application on the RTE V850E MA1 CB by using a maskable interrupt and related restrictions INTERRUPT VECTOR The V850E MA1 interrupt vector area of addresses 000000H to 0007FFH is fixed in the ROM and cannot be rewritten So for the monitor the following two vector areas are allocated in the SRAM Alternate vector area This vector area can be rewritten by the user program It is used if a relative jump can be executed from the interrupt vector area The branch instruction for the relative jump is placed in the vector area in this case Relay vector area This vector area is used by the monitor if a relative jump from the interrupt vector area cannot be executed In this case an instruction that saves the registers and a branch instruction for an absolute jump are placed in the interrupt vector area and an instruction that restores the registers and a branch instruction for a relative jump to the alternate area are placed in this area Because the mon
23. the CS2 space The actual capacity is 1M byte An image is generated every 1M byte within this space When the monitor is used part of this space is reserved for the monitor work area see Sections 12 2 2 and 13 2 2 CS1 space SDRAM 0800000 to 3FFFFFF 56M bytes SDRAM is allocated to the CS1 space The actual capacity is 32M bytes An image is generated every 32M bytes within this space Access to the internal resources for an internal RAM or SFR area takes precedence over access to SDRAM CS3 space GCS5 4000000 to 4FFFFFF 16M bytes The CS3 space is reserved as a space for GCS5 of GBUS For GBUS see Chapters 11 and 14 CS3 space 0 50 5000000 to 5FFFFFF 16M bytes The CS3 space is reserved as a space for GCSO of GBUS For GBUS see Chapters 11 and 14 CS3 space GCS1 GCS3 6000000 to 6FFFFFF 16M bytes The CS3 space is reserved as an area for GCS1 and GCS3 of GBUS For GBUS see Chapters 11 and 14 CS3 space I O GCS2 GCS4 GCS6 7000000 to 7FFFFFF 16M bytes CS3 space is used as an I O space There are reserved spaces for the board s I O and GCS2 GCS4 and GCS6 of GBUS For the I O map see Section 7 4 1 For GBUS see Chapters 11 and 14 CS4 to CS7 spaces not used 8000000 to FFFFFFF 128M bytes The CS4 to CS7 spaces are not used on the board 16 RTE V850E MA1 CB USER S MANUAL Rev 1 05 7 2 RECOMMENDED SETTINGS This section explains the recommended setting values of each registe
24. the spaces can be accessed in a burst cycle A space marked l O under the heading Recommended space means that if the CPU has an I O space it is recommended that the space be allocated as an I O space Minimum range indicates that the CPU board must allocate at least the indicated area for the corresponding chip select space Maximum range indicates that if the CPU board has an extra address range addresses can be allocated for the indicated range Signal Recommended Minimum Maximum name space range range GCSO Memory 1M byte GcS0 tMbyte GCS1 2M bytes 64K bytes GCS3 64Kbytes 16M bytes 64K bytes 16M bytes Remark Bus lock possible with GLOCKO Because a flash ROM is allocated to this space on the motherboard the program must be able to be booted from this space instead of from UV EPROM on the CPU board via a switch Memory 2G bytes ecse 0 5t2bytes Bus lock possible with GLOCK1 Bus lock possible with GLOCK1 51 RTE V850E MA1 CB USER S MANUAL Rev 1 05 14 6 BUS CYCLE 14 6 1 Single Cycle The following chart shows the single cycle when GBWAITI and GBTERM are always inactive and the CPU board is the bus master If the motherboard is the bus master the GCSx GDMAAK and GWAITI signals are not used GCLK GCSx GDMAAKx GADDR 31 2 GBE 3 0 GW R GADS GBLAST GWAITI GREADY GBTERM GDATA 31 0 read GDATA 31 0 write 14
25. 29 CPU CONNECTION cerraran en napine Arana p AE ALONE EAEn INFRE PONAT CA ANID AERONA RAEES PEFEA EONA AEE 30 10 1 CONNECTION LIST enanar a a ea a 30 10 2 RESE RR 31 10 32 POMO WATO uite inet e RE tiet tees te Dax aa tO NE Fox DRE ED ES 32 10 42 eco thet cuoc ara 32 10 5 P20 NMI 00 33 10 6 P2 INTP001 P11 INTPO10 P12 INTP011 21 20 33 10 7 PA0 SOO TXDO iit io i tet coe teen do CO Mal De Ded 34 10 8 P44 SIO RXDO dern iter tetto uten Pot ra rode 34 10 9 42 5 P43 SO1 TXD1 P44 SI1 TXDO 45 5 1 34 10 10 100 103 35 10 11 35 10 12 2 4 110 0 113 3 36 10 13 OTHER SIGNALS 0 ada aa 36 SPECIFIC GBUS SPECIFICATIONS eene n nnn nn nnne nn nn nnn 37 114 GENERAL grec tere eei 37 11 25 pue 38 11 32 SELEG oo 39 APPENDIX A MULTI MONITOR rre 40 121 BOARD SETTING intere teste ced teo t teta to tb et tena ee LE a tte a Ee De ale REA EE ebd 40 12 1 1 RTE for Win 32 metalation 2 40 12 1 2 SWI Setting te d RAE e AEn
26. 6 2 Burst Cycle The following rules apply to a burst cycle e The addresses in the burst cycle can be in any sequence allowed by the GBUS specifications However the address sequence may be specified according to what is to be accessed e n a burst cycle all of GBE 3 0 must be active The number of bursts the number of micro cycles is not limited If the target of the access limits the number of bursts use the GBTERM signal see Section 14 6 4 to request canceling of the burst The following charts show the burst cycle when GBWAITI and GBTERM are always inactive and the CPU board is the bus master If the motherboard is the bus master the GCSx GDMAAK and signals are not used Owait 0 wait 0 wait GCLK GCSx GDMAAKx GADDRI31 2 GBE 3 0 GW R GADS GBLAST GWATTI GREADY GBTERM GDATA 31 0 read GDATA 31 0 write 52 RTE V850E MA1 CB GCLK GCSx GDMAAKx GADDA 31 2 GBE 3 0 GW R GADS GBLAST GWAITI GREADY GBTERM GDATA 31 0 read GDATA 31 0 write 14 6 3 GWAITI USER S MANUAL Rev 1 05 The GWAITE signal can be used as follows in a cycle in which the CPU board is the bus master e To delay sampling of data by a specific number of clocks because the data cannot be sampled in the read cycle e To hold the target of an access by the specific number of clocks because data for the next micro cycle is not ready immediately after completion of the
27. B 14 7 TIMING USER S MANUAL Rev 1 05 This chapter describes the timing of Midas lab s motherboard The CPU board is designed to satisfy this timing 14 7 1 Setup Time 14 7 2 Delay Time 0 1 0 GADS GREADY GWAITH GBTERM GCS 7 0 GDMAAK 3 0 GLOCK 1 0 Tdelay Max ns T 7 55 RTE V850E MA1 CB USER S MANUAL Rev 1 05 Memo RTE V850E MA1 CB User s Manual 912 101 56
28. CI Cont register ADDR 23 19 10011 of CS3 space 39 RTE V850E MA1 CB USER S MANUAL Rev 1 05 12 APPENDIX A Multi MONITOR This chapter describes how to make the settings required to establish a connection between the Multi monitor stored in ROM and the Multi debugger on the host It also provides notes on the use of the Multi monitor 12 1 BOARD SETTING 12 1 1 RTE for Win 32 Installation When the board is used with the Multi debugger communication software called RTE for Win32 must be installed in the PC Refer to the RTE for Win32 Installation Manual supplied with this product for installation and test methods 12 1 2 SW1 Setting SW1 is a switch for general purpose input ports For the Multi monitor in the factory installed ROM SW1 is used as shown below 115 200 baud 38 400 baud 19 200 baud 9 600 baud Factory set Baud Rate Setting ON Timer is not used 200 Hz 5 ms 100 Hz 10 ms OFF 60 2 16 67 ms Factory set Profiler Period Setting Setting ON Monitor is started in test mode OFF Normal use state Factory set Debug Mode Setting 5 1 5 to SW1 7 are not used with the Multi monitor If SW1 8 is set to ON it takes some time to start the monitor The monitor also lights the LED Usually keep this switch set to OFF 12 1 3 Connection of Board Connect the board to the PC serially by referring to Chapter 6 40 RTE V850E MA1 CB USER S MANUAL Rev 1 05 12 2 Multi MONITO
29. E V850E MA1 CB USER S MANUAL Rev 1 05 5 15 FLASH WRITING CONNECTOR JFLASH The JFLASH connector is used to write data to the CPU s internal flash ROM by using a flash programmer device To use JFLASH SW4 must be set see Section 5 6 JFLASH Pin Arrangement AO 3 soo Input _ Synchronous serial clock input CMOS level 4 RESET Input__ Resetinput s we s ow core s e o wem a9 Ne connection JFLASH Connector Signals 10 RTE V850E MA1 CB USER S MANUAL Rev 1 05 5 16 SERIAL CONNECTOR JSIO1 JSIO2 The JSIO1 connector is used for the RS 232C interface that is controlled by the serial controller TL16C550CPT on the board The JSIO2 connector is used for the RS 232C interface that is controlled by the built in serial controller ofthe CPU JSIO1 and JSIO2 are 9 pin D SUB RS 232C connectors male like that commonly used on the PC AT All signals on both of these connectors are converted to the RS 232C level The figure and table below indicate the pin and signal arrangement of these connectors For the signals to be connected to the host the table indicates two modes of wiring on the host one for a 9 pin D SUB connector and the other for a 25 pin D SUB connector Regular cross cable wiring is used for these connections Pin Arrangement of JSIO1 and JSIO2 Male Input Connector pin number on the host side 4
30. ERM must be asserted at the same time as GREADY This signal is used to complete the bus cycle if the accessed side does not support burst cycles or if a burst cycle exceeding the supported number of bursts is requested 46 RTE V850E MA1 CB USER S MANUAL Rev 1 05 GW R GDMARQ 3 0 Input output e Write Read signal This signal indicates the direction of the data bus It is always driven by a valid value during the bus cycle This signal indicates the direction of the data bus for the bus master Chip select signals These signals are always driven by a valid value during the bus cycle The CPU board makes the corresponding chip select signal active to specify the resources on the motherboard when the CPU board is the bus master Each chip select signal specifies the type of memory l O space and the width of the space see Section 14 5 Read timing signal This signal is asserted when the CPU board is the bus master This signal is not used by the motherboard If the CPU has an RD command signal that signal is usually connected Write timing signal This signal is asserted when the CPU board is the bus master This signal is not used by the motherboard If the CPU has a WR command signal that signal is usually connected Bus hold request signal This signal is asserted low when the motherboard accesses the resources on the CPU board to acquire bus mastership If the GUSE DIRECT signal is high the
31. I is sampled high on the rising edge of GCLK during a micro cycle the end of the micro cycle is indicated Time over ready when the CPU board accesses the motherboard is generated by the motherboard The reason is to avoid collision with the GREADY signal Wait request signal This signal is sampled on the rising edge of GCLK If the CPU board cannot support a cycle with a few wait cycles the CPU board samples low at the sample timing of GREADY so that the motherboard cannot handle GREADY as a ready signal even though it is low at the time Usually this signal is used if the CPU board cannot support zero wait burst see Section 14 6 3 This signal is valid only in a cycle in which the CPU board is the bus master Bus cycle completion notification signal This signal is sampled on the rising edge of GCLK This signal is asserted low by the bus master when a micro cycle that completes the bus cycle starts The bus cycle is completed if the low level of GBLAST low level of GREADY and high level of GWAITI are sampled on the rising edge of GCLK Bus cycle completion request signal This signal is sampled on the rising edge of GCLK If the accessed side requests completion of the bus cycle the GREADY and GBTERM signals go low If the bus master samples GBTERM as low when it samples GREADY as low it must complete the bus cycle even though GBLAST has not been asserted and start the bus cycle again by asserting GADS again GBT
32. R 12 2 1 12 2 2 12 2 3 12 2 4 12 2 5 12 2 6 7 Segment LED on Startup The 7 segment LED of the ROM monitor for Multi operates as follows when power is supplied to the board black indicates the segment that lights 1 Check operation of 7 segment LED See figure below If SW1 8 is OFF zs If SW1 8 is gt hy IS E ST SL Number counting by simple SRAM memory check Not executed if SW1 8 is OFF 3 Connection wait status The dot does not blink if the profiler timer is stopped 9 9 4 Connection status The status of the dot is retained on connection or H H ROM Monitor Work RAM The ROM monitor uses the first 32K byte area 4F8000H to 4FFFFFH in the SRAM as work RAM In other words user programs are not allowed to use this area or its image area Monitor Interrupt The interrupt selected by SW2 5 is used for monitor communication the timer and forced break _INIT_SP Setting _INIT_SP stack pointer initial value is set to 4F7FFOH immediately before monitor work RAM by the monitor _INIT_SP can be changed in the Multi environment The monitor uses a 32 byte stack area set by the user program Timer Interrupt If the timer interrupt is disabled the profiler function of Multi cannot be used for how to set the timer interrupt see Section 12 1 2 Initializing Hardware The ROM monitor performs initialization so that the resources on the board can be directly accesse
33. RTE V850E MA1 CB USER S MANUAL Rev 1 05 RTE V850E MA1 CB USER S MANUAL Rev 1 05 Midas lab RTE V850E MA1 CB USER S MANUAL Rev 1 05 REVISION HISTORY Pmimmayveson Supported by exponent board sy 18 7666 10 __ verson Supper by mass produced RTE V850E MA1 CB USER S MANUAL Rev 1 05 CONTENTS 1 dNTHOBECTON Llao 1 116 JMUMERIGINOTATION prieta a 1 DS 1 oben 2 3 MAJOR FEATURES coccion 3 4 BASIC SPECIFICATIONS 2 4 4 rra 3 5 BOARD CONFIGURATION 4 54 RESET SWITCH SW RESET i onset e ete too ote eet 4 5 2 CONNECTOR 4 50 SWITCH TM 4 BAY SWITCH a UN 5 5 SWITCH 5 5 6 SWITOHA 94 m aequ DD de 6 57 SWITCHES 5 TO 8 SW5 TO 8 7 BE SPSEG BED aub to tes M i 8 5 9 TEST PINS FOR ROM EMULATOR 1 8 5 10 CLOCK SOCKET OSC Us odes aka b eine 8 5 11 CRYSTAL SOCKET JP1 aah
34. USER S MANUAL Rev 1 05 5 7 SWITCHES 5 TO 8 SW5 SW8 SW5 to SW8 physically cuts the board s signal lines connected to CPU pins All the switches are factory set to ON connected Set a switch to OFF only when the corresponding signal line is used for an external source but only if the internally used resources are not necessary Remark The following tables show the CPU pins and final internal resource names SW5 CPU pin name Factory setting Internally used resource P40 SO0 TXDO SIO2 TXD P41 SIO RXDO SIO2 RXD PAMSCKO SIO2RTS s o eom wwe _ OOOO s o 1 SW6 s TIT ON s Pooma omas oras SW7 SW8 CPU pin name Factory setting Internally used resource PO2 INTPO01 TIOO1 of GBUS P11 INTPO10 TIO10 GINT2 of GBUS P12 INTPO11 TIO11 GINT3 of GBUS P21 INTP020 T1020 OUT1 of TIC RTE V850E MA1 CB USER S MANUAL Rev 1 05 5 8 5 9 5 10 7SEG LED xxx LED The LEDs are used to indicate statuses as listed below The two 7 segment LEDs are used by the monitor at startup After that they can be used for any user application _ ________ _________ POWER Lights when power is supplied to the RTE V850E MA1 CB board TOVRDY Lights when time over ready occurs and does not go off until cleared by software see Section E NET 4 5 cso Lights when CS0 space is acce
35. block of the 850 1 is shown below Serial 3 RS 232C pue driver uPD71054 FLASH interface 16 bit UV AY SDRAM SRAM V850E MA1 Local bus Serial interface 28 5 Bus controller Address Port etc CPU CONE RTE V850E MA1 CB Block Diagram Local bus is a bus that buffers the CPU bus and is synchronized with the CPU Gbus is independent of the CPU and is fixed at 33 MHz RTE V850E MA1 CB USER S MANUAL Rev 1 05 3 MAJOR FEATURES Two types of monitor ROM are provided one is used for the Green Hills Multi and the other for the NEC PARTNER Real time execution and evaluation at a high level language level using Multi or PARTNER A ROM emulator can be connected 1M byte of high speed SRAM and 32M bytes of SDRAM are provided as standard Two serial interfaces are provided One channel uses an external controller and the other channel uses the internal controller of the CPU The serial channel of an external controller is used as the monitor e Three timer channels are provided One channel is used for the monitor 4 BASIC SPECIFICATIONS Processor V850E MA1 CPU clock 50 MHz Bus clock 50 MHz Power supply 5 V 2 A max Memory EPROM 128 64K x16 bits 40 pin DIP x 1 512K bytes max SRAM 1MB 512 K x8 bitsx2 SDRAM 32MB 4M x4 bits x 4 banks x 4 Serial 2 ch Internal CPU UART DB9 connector Equivalent to NS16550 DB9 connector
36. bus control signals PCT7 BCYST PCTO LCAS LWR LDQM Used by the system bus and SDRAM SEN PCT1 UCAS UWR UDQM PCTS WE Used by SDRAM PCT6 OE PCDO SDCKE PCD1 SDCLK PCD2 LBE SDCAS PCD3 UBE SDRAS PCSO CSO Used by system bus as CSx PCS1 CS1 RAS1 PCS2 CS2 PCS3 CS3 RAS3 PCMO WAIT Used as WAIT Pulled up at 1K PCM5 SELFREF Functions as SELFREF Pulled down at 47K P20 NMI Used as interrupt line 10 5 P1 INTP000 T1000 P2 INTPO01 TIOO1 Reserved as interrupt line can be disconnected by P11 INTPO10 TIO10 SW8 P12 INTP011 T1011 P21 INTPO20 TIO20 P40 SO0 TXDO Reserved as SIO2 TXD can be disconnected by 10 7 SW5 P41 SIO RXDO Reserved as SIO2 RXD can be disconnected by SW5 P42 SCKO Reserved as port to control SIO2 can be disconnected 10 9 P43 SO1 TXD1 by SW5 P44 SH RXD1 P45 SCK1 P4 INTP100 DMARQO Reserved as DMARQ P5 INTP101 DMARQ1 Connected to GBUS DMARQO 3 can be disconnected P6 INTP102 DMARQ2 by SW6 P7 INTP103 DMARQ3 PBDO DMAAKO Reserved as DMAAK PBD1 DMAAK1 Connected to GBUS DMAAKO 3 can be disconnected PBD2 DMAAK2 by SW6 PBD3 DMAAK3 P24 INTP110 TCO Connected to reserve pin of GBUS can be P25 INTP111 TC1 disconnected with SW7 P26 INTP112 TC2 P27 INTP113 TC3 RTE V850E MA1 CB USER S MANUAL Rev 1 05 10 2 Pin name Use Section reference P22 INTPO21 TIO21 Used as port to turn ON OFF VPP for self writing of EE flash P70 77 ANIO 7 Not used
37. d 41 RTE V850E MA1 CB USER S MANUAL Rev 1 05 12 2 7 Special Instruction The monitor uses the following instruction for the single step breakpoint and system call functions BRKTRAP instruction Oxnn40 Do not use a code that may be interpreted as a break instruction in the user program 12 3 RTE COMMANDS When the monitor and server are connected the TARGET window is opened The RTE commands can be issued in this window The following table lists the RTE commands HELP Displays help messages INT Displays the version number Displays or sets the internal I O RTE Commands Some commands require parameters All numeric parameters such as addresses and data are assumed to be hexadecimal numbers The following numeric representations are invalid 0 1234 1234H 1234 12 3 1 HELP Format HELP command name Displays a list of RTE commands and their formats A question mark can als o be used in place of the character string HELP If no command name is specified in the parameter part the HELP command lists all usable commands Example HELP SFR Displays help messages for the SFR command 12 3 2 INIT Format INIT Initializes the RTE environment Usually this command should not be used 12 3 3 VER Format VER Displays the version number of the current RTE environment 12 3 4 SFR Command Format SFR register name data When a register name is specified with data omitted the data
38. d cycle of the V850E MA1 is executed in half word units regardless of the access size of an instruction Depending on the resources on the GBUS however some devices request an access only in byte units At the time of access to such a device please set this bit 1 and access in byte size from CPU Word Set this bit to 1 to access GBUS in word 32 Bit units Usually keep this bit set to 0 This is used to access GBUS in word units The external bus of V850E MA is 16 Bit However depending on the resources on the GBUS some devices request an access only in word units At the time of access to such a device please set this bit 1 and access in word size from CPU Caution Please do not set 1 as Bit of both Byte and Word After setting change should surely do IOWAIT dummy read of ROM area The function of Word Bit is applied to what has the version of a board newer than 2 2 23 RTE V850E MA1 CB USER S MANUAL Rev 1 05 8 SOFTWARE This chapter describes the initialization of the hardware of the RTE V850E MA1 CB board and explains how to use peripheral devices 8 1 INITIALIZATION To write a program that is booted from ROM without using the monitor initialize the internal bus controller of the V850E MA1 in the first routine of the program For the values to be set for initialization see Section 7 2 8 2 SUCCESSIVE ACCESSES TO uPD71054 To successively access the 1 PD71054 access other spaces at least once between the
39. d for the GCSO space GBLOCK1 is valid for the GCS5 and GCS7 spaces Output e Power supply Supplies 5 V 5 from the motherboard to the CPU board 48 RTE V850E MA1 CB USER S MANUAL Rev 1 05 12V Output Power supply Supplies 12 V 10 from the motherboard to the CPU board However if the CPU board does not require 12 V the motherboard does not have to supply 12 V 49 RTE V850E MA1 CB USER S MANUAL Rev 1 05 14 3 PIN ASSIGNMENTS The following table shows the GBUS pin assignments Reserve indicates a reserved pin N C indicates that a pin is not connected No No GADDRZ 6 7 GADDR 8 GADORS GADDR22 30 caos er 22 46 27 48 v 58 57 5 6 6 coama 67 ___ 68 vw GND 78 v 80 GDATA6 86 GDATA0 8 GND 88 GNb o GWR GBTERM 92 CRERDY GRESETF 94 GADS 66 GBLAST 9 GWAITF 3 o 102 103 104 5V EM F5 oo o 774 715 2 122 123 124 135 136 74 744 3 15 185 SUSE DIRECT ROC 156 TNC re Ne 75 176 77 178 179 180 E un N al A
40. first and second accesses to the PD71054 These accesses ensure the recovery time of the 71054 Recovery time is also assured by a dummy read of a resource such as ROM other than the yPD71054 8 3 LIBRARIES Libraries are required for programming using the C compiler for I O accesses and other purposes However the methods of writing these libraries and passing their parameters are specific to the GHS So modifications may be required for example when another compiler is used I O library GHS V800 compiler parameter passing arg0 r6 argl r7 arg2 r8 10 inb int addr Byte 8 bits input __ 1 O r6 10 inh int addr Half word 16 bits input __ 6 10 inw int addr Word 32 bits input __ 1 O r6 10 outb int addr int data Byte 8 bits output __ st b r7 O r6 outh int addr int data Half word 16 bits output __ st h r7 O r6 outw int addr int data Word 32 bits output __ st w r7 O r6 24 RTE V850E MA1 CB USER S MANUAL Rev 1 05 8 4 EXAMPLE OF USING TIMERS A sample time measurement is indicated below which uses timer 1 and timer 2 cascaded with each other by an external timer 1PD71054 on the board Timer 1 is initialized as an interval counter mode 2 and timer 2 is initialized as a
41. g to the following sections and in accordance with your environment When using Multi see Section 12 1 2 When using PARTNER see Section 13 1 1 RTE V850E MA1 CB USER S MANUAL Rev 1 05 5 4 5 5 SWITCH 2 SW2 SW2 selects an operation of the board by hardware The setting of the switch can be read from an input port see Section 7 4 3 Factory setting 1 FBOOT OFF Specifies resources to be allocated to the CSO space OFF The on board UV EPROM is allocated to the CSO space ON GCS1 space of GBUS is allocated to the CSO space see Section 7 1 TEST Set this signal to OFF BCLK_LOW Selects frequency of oscillator mounted on OSC1 Depending on the value set the monitor ROM changes the number of ROM and SRAM wait cycles In addition the number of I O wait cycles is changed by hardware OFF Bus clock exceeds 33 MHz ON Bus clock is kept at 33 MHz or less 5 o oa Specifies interrupt to be used by the monitor OFF NMIO ON 000 FF FF SW2 5 is read only to set the interrupt controller by the monitor SWITCH 3 SW3 SW3 selects the type of ROM inserted in the ROM socket and performs setting related to banks 1 ROM_TYPEO OFF Selects the type of ROM OFF OFF When monitor ROM is used 2 ROM TYPE1 OFF OFF ON When 27 4096 is used ON OFF When 27 2048 is used When 27 1024 is used 3 BANK_DIS OFF Specifies whether the upper and lower halves banks of
42. h time an interrupt has been serviced when more than one interrupt occurs If the CPU detects an interrupt reception using the edge execute the processing that first sets the INTEN bit to 1 and then clears it to 0 at the last step of the interrupt handler This allows a pending interrupt to be acknowledged Caution Do not change the contents of the PIC while the monitor is being used 21 RTE V850E MA1 CB USER S MANUAL Rev 1 05 7 4 7 7 4 8 UART TL16C550C 7807000H to 7807070H The Texas Instruments TL16C550C LSI is used as the UART controller The TL16C550C has an UART channel It also has 16 character FIFO buffer in the transmission reception block of the UART and a function for automatically controlling RTS CTS flow Therefore an overrun error of communication can be suppressed by the minimum interrupt Each register of the TL16C550C is assigned as listed below For an explanation of the function of each register refer to the manual provided with the TL16C550C The manual for the TL16C550C is available from the TI amp ME of the Texas Instruments home page http www ti com TL16C550C Register Arrangement The XIN input of the TL16C550C is connected to the 16 MHz clock The UART interrupt can be input to NMI1 of the CPU via PIC of the CPU The UART is connected to the JSIO1 connector of the board The UART is used to communicate with the host when the remote debugger is used TL16C550C is
43. high speed SRAM and high capacity SDRAM are provided as standard The SDRAM is controlled by using the internal memory controller of the V850E MA1 These functions enable the RTE V850E MA1 CB to be used for a wide variety of applications including processor performance evaluation and application program development at the initial stage and to also be used as an engine for demonstration and simulation The GHS Multi or NEC PARTNER source level debugger be used as a development software tool with the RTE V850E MA1 CB The type of monitor to be stored in ROM depends on the debugger type In ROM the monitor specified at the time of purchase is stored Even when neither of the debuggers is purchased together with the RTE V850E MA1 CB they can be purchased at anytime subsequently NUMERIC NOTATION This manual represents numbers according to the notation described in the following table Hexadecimal and binary numbers may be hyphenated at every four digits if they are difficult to read because of many digits being in each number Only numerals are indicated 10 represents number 10 in decimal Hexadecimal A number is suffixed with letter H 10H represents number 16 in decimal number A number is suffixed with letter B 10B represents number 2 in decimal Number Notation Rules Multi is a trademark of Green Hills Software Inc in the US RTE V850E MA1 CB USER S MANUAL Rev 1 05 2 FUNCTIONS The overview of each function
44. in is used for Tx of 5102 via an RS 232C transmitter driver as shown below 053383 JSIO2 TX SW5 1 RS 232C driver JFLASH 10 8 P41 SI0 RXDO A signal that is Rx of SIO2 converted to TTL level by an RS 232C receiver driver is connected to the P41 SIO RXDO pin via a switch as shown below JSIO2 RX SW5 2 RS 232C driver JFLASH 10 9 P42 SCKO P43 SO1 TXD1 P44 SI1 TXDO 5 5 1 These pins are used for CTS DTR RTS and DTR of SIO2 via an RS 232C transmitter receiver driver as shown below JFLASH SIO2 CTS SIO2 DSR SIO2 RTS SIO2 DTR RS 232C driver 34 RTE V850E MA1 CB USER S MANUAL Rev 1 05 10 10 P4 INTP100 DMARQO P7 INTP103 DMARQ3 These signal pins connect the DMARQ request from GBUS via a switch as shown below 74VHC541 GBUS DMARQO GBUS DMARQ1 GBUS DMARQ2 GBUS DMARQ3 10 11 PBDO DMAAKO PBD3 DMAAK3 These signal pins connect the signal output by the CPU via switch to DMAAK of GBUS as shown below 74VHC541 GBUS DMAAKO GBUS DMAAK1 GBUS DMAAK2 GBUS DMAAK3 35 RTE V850E MA1 CB USER S MANUAL Rev 1 05 10 12 P24 INTP110 TCO P27 INTP113 TC3 These signal pins invert the logic of a signal output by the CPU and are connected to a reserve pin of GBUS via a switch as shown below 7AVHC541 9 GBUS 129 pin GBUS 130 pin GBUS 131 pin GBUS 132 pin 10 13 OTHER SIGNALS Board signals not used are c
45. itor can execute a relative jump from the interrupt vector area addresses 0000000H to 00007FFH to the alternate vector area it branches to the alternate vector area via relay vector area Alternate vector area Relay vector area 4F8000H to 4F87FFH 4F8800H to 4F8 FFH If for example an interrupt with exception code 0080H is generated the CPU interrupt function causes a branch to address 000080H where an instruction for causing a branch to 0080H the offset of alternate vector area is placed It branches to offset address 0080H of the alternate vector area via that vector By rewriting the alternate vector area in the destination a branch to the user program interrupt handling routine can be caused when an interrupt is generated If an exception code 0080H interrupt occurs therefore write an instruction that branches execution to the specified interrupt processing at address 4F8080H The difference from an ordinary V850E MA1 program is that a vector area is fixed in ROM and no setting rewriting by a program is required However a program using the monitor on the RTE V850E MA1 CB must rewrite the vector area by the program to enable an interrupt 26 RTE V850E MA1 CB USER S MANUAL Rev 1 05 A sample program for alternate vector rewriting is given below when the relative address from the interrupt handling routine to an alternate vector area is within 22 bits void SetAJump int addr int jmpdest Vector setting routine
46. motherboard The direction written first is the signal direction when the CPU board is the bus master and the direction written later is the signal direction when the motherboard is the bus master AGBUS signal is a 5 V TTL level signal The motherboard is always little endian GCLK Input Synchronization clock of GBUS The maximum frequency is 33 33 MHz and the minimum frequency is 10 0 MHz GBUS operates synchronized with the rising edge of this clock Since on the motherboard this clock is terminated at 330 with respect to 5V and GND the circuit on the CPU board must be able to drive this resistance If GCLK is less than 16 67 MHz GCLK_LOW goes low In this way the motherboard can adjust the number of wait cycles Because a PLL Phase Lock Loop zero delay buffer may be used if the frequency of GCLK is changed the motherboard must not be accessed for at least 1 ms after the frequency has been changed to allow the PLL to be locked GRESETE Input Reset signal of GBUS If a reset occurs on the CPU board this signal goes low The motherboard is reset by this signal the motherboard can also be reset for other causes on the motherboard GRESETO Output This signal goes low if the motherboard is reset The motherboard ORs the reset signal on the motherboard with GRESETI as GRESETO Accordingly the CPU board resets the circuits on the CPU board by ORing GRESETI and GRESETO GRESETI and GRESETO are ORed because there is a pos
47. nctions as a SELFREF pin when an external bus is used and is pulled down at 47 on board JCPU 47 32 RTE V850E MA1 CB USER S MANUAL Rev 1 05 10 5 10 6 20 P1 INTPOO0 P20 NMI and P1 INTPOOO are used as interrupts NMI and 000 are interrupts to the monitor and the following interrupt sources are combined by hardware via the PIC For how to select an interrupt see Section 7 4 6 e UART_INT Interrupt issued by UART of the TL16C550C See Section 7 4 7 e TOUTO INT Interrupt issued by TOUT of CH 0 of the TIC uPD71054 See Section 7 4 8 e TO_RDY_INT Interrupt resulting from time over ready occurrence See Section 10 3 e GINTO Interrupt from GINTO of GBUS See Chapter 14 The concept of the NMI1 generation logic is shown below The xxx_MASK signal in this figure indicates setting of the registers of the PIC see Section 7 4 6 From JROMEM ROM_EMLT_NMI TOUTO INT TOUTO_INT MASK 5 E TO RDY INT 12 TO RDY INT MASK GINTOO GINTO_MASK P2 INTPOO1 P11 INTP010 P12 INTP011 P21 INTPO20 P2 INTP001 P11 INTPO10 P12 INTPO11 and P21 INTPO20 are used as an interrupt and connected to GBUS INTO 1 2 and OUT1 output of timer CH1 via a switch Connection of each pin is shown below 74NHC541 NTP001 010 INTPO11 TIC_OUT1 20 21 33 RTE V850E MA1 CB USER S MANUAL Rev 1 05 10 7 P40 SO0 TXDO The P40 SO0 TXDO p
48. ndence between all four GDMARQ signals and GDMAAK signals cannot be established 47 RTE V850E MA1 CB Signal name GDMAAK 3 0 GINTO 3 0 GINTH 1 0 GETC 7 0 GAHI_EN GMOTHER_ DETECT Input output USER S MANUAL Rev 1 05 DMA acknowledge signals These signals are asserted low to acknowledge DMA requests from the motherboard The CPU board uses the DMAAK signal in preference to DMAAK 3 2 if correspondence between all four GDMARQ signals and GDMAAK signals cannot be established The motherboard is designed to operate even though there is no GDMAAK signal Interrupt request signals GINTOO be used as a level sensitive signal Whether GINTO 3 1 can be used as level sensitive signals or edge sensitive signals depends on the CPU board since they may be directly connected to the CPU The motherboard can support both level and edge sensitive signals Occurrence of an interrupt is indicated when these signals are low or on the falling edges of these signals Interrupt request signals These interrupt signals are used to combine an interrupt on the CPU board with an interrupt on the other motherboard and return the combined signal to GINTO 3 0 Usually OUTO and OUT1 of TIC 1PD71054 on the CPU board connected The motherboard can select the type of sensitivity and polarity of these interrupt signals CPU board dependent signals
49. nitor INSULAR 44 13 2 4 SP Selling PO 44 13 2 5 Initializing Hardwae s eso e e d a b uet 44 13 2 6 Special Instruction essen eene nnne 44 APPENDIX C GBUS COMMON SPECIFICATIONS eene 45 144 TERMINOLOGY arenarie eean aA eti ie MER ER et bee Pea et Lie ee pir et Mae F e M etie an 45 14 1 1 CPU Board and Motherboard 2 45 14 1 2 Bus Cycle Micro 2 45 142 SIGNALS iiie eto as 45 14 3 PIN ASSIGNMENLCS 2 etse t teta to esee tee Led het ea Pod e ate t na ee Ee ain 50 14 4 PROCESSING OF UNUSED PINS see een m ener 51 14 5 ALLOGCATING GCS 7 0 anie davies dite te idee ctt dee ete dee ieee 51 146 BUS CY CEE s ed ER bin 52 EA RS Cycle iste tto E E E 52 14 6 2 Burst Cycle de n nd d nd ges 52 14 6 3 GWAITI t esL ede or d 53 14 6 4 GBTERM iiid 54 14 7 TIMING55 14 71 e ect ete oe lage i aer ERES ER Re 55 14 7 2 Delay Time RTE V850E MA1 CB USER S MANUAL Rev 1 05 1 1 INTRODUCTION The RTE V850E MA1 CB is a CPU board that is designed to evaluate the NEC V850E MA1 RISC processor The board features a V850E MA1 capable of operating at a maximum speed of 50 MHz memory serial interface and bus connector for expansion As the memories a
50. nitor program execution The interrupts that can be connected are as follows Communication interrupt from RS 232C devices UART TL16C550C Timer interrupt request of TOUTO of the timer TIC uPD71054 Occurrence of time over ready GINTO interrupt 1 2 3 4 Data bus Pe A 5 III 7804020H INTEN INTP INT 000 EN The INT MASK register masks interrupts applied to its bits When an INT_MASK bit is set to 1 the interrupt is enabled When multiple bits are selected each OR value activates an interrupt The INTR register is an interrupt status register for which 1 is read whenever there is an interrupt request This does not depend on the state of masking To clear an edge interrupt request the corresponding bit of this register must be setto 1 The table below indicates the interrupt source assigned to each bit of IM 0 3 and IR O 3 PIC INT MASK Interrupt source Request level STATUSI o The INTEN register enables or disables all interrupts INTEN Disables the interrupt to be used by the monitor by hardware At this time the interrupt request pin is low INTEN NMIO INTPOO0 o Sets a mask Reset value Does not set a mask INTPOOO Selects the interrupt to be used by the monitor INTO NMI Interrupt for monitor o NM0 is used Reset value INTPOOO is used INTEN is used to create an edge for an interrupt request signal to the CPU eac
51. o select the clock supplied to the CPU and it also acts as the connector for the crystal oscillator To use OSC1 as CPU clock Short circuit JP1 pins 1 and 2 In this case do not mount the crystal To mount crystal on JP1 and use the CPU oscillation circuit Mount the crystal between pins 1 and 3 on JP1 Do not short circuit pins 1 and 2 AVDD AVREF SELECTOR JUMPER JP2 The JP2 jumper is used to select the voltage for AD AVDD AVREF to be supplied to the CPU To supply voltage from board Factoryset condition Jumper pins 1 and 2 of JP1 3 3 V will be supplied To supply voltage from external source JCPU Jumper pins 2 and 3 of JP1 Supply the voltage from pin JCPU2 78 ROM SOCKETS The RTE V850E MA1 CB has ROM sockets to hold 40 ROM chips to provide standard 128K bytes 64K x 16 bits When the ROM chips used here are to be replaced their type should be 27C1024 27C2048 or 27C4096 and the access time should be 120 ns or less SELF WRITING POWER CONNECTOR JVPP To execute self writing of the CPU s internal flash ROM a power supply capable of supplying 7 8 V is necessary The JVPP connector is used to connect such a power supply To execute self writing connect 10 to 12 V power supply to this connector and output a low level to pin P22 of the CPU This supplies 7 8 V to the VPP pin of the CPU thus enabling self writing The pin configuration of JVPP is as shown below ERES 10 12V Inputs voltage of 10 to 12 V RT
52. onnected to the JCPU connector as shown below 36 RTE V850E MA1 CB 11 11 1 GENERAL USER S MANUAL Rev 1 05 SPECIFIC GBUS SPECIFICATIONS This chapter explains how GBUS is used with the RTE V850E MA1 CB specifications see Chapter 14 The following table shows the GBUS signal lines used by the RTE V850E MA1 CB GADDR 31 2 Used as address lines GADDR 26 31 are not connected GADDR 25 24 are don t care GDATA 31 0 Used as data lines In a read cycle the signal that is latched on the rising edge of VBCLK is supplied to the CPU GADS GREADY GBLAST GW R GWAITE GBTERM GRD GWR GHOLD GHLDA GBREQ GDMARQ 3 0 GDMAAK 3 0 GINTO 3 0 GINTE 1 0 GETC 7 0 GAHI_EN Used as bus control signals Not connected Not connected RD and WR signals generated from the GBUS control signals are connected OUTO and OUT1 of TIC uPD71054 are connected to GINTIO and GINTH Not connected Not connected See 10 10 10 11 10 6 10 6 For the general GBUS 37 RTE V850E MA1 CB 11 2 BUS CYCLE A 33 MHz clock that is asynchronous with CLK of the CPU is connected to GCLK of GBUS In addition because GAHI_EN is not connected GADDR 26 31 are not connected GADDR 24 25 are always 0 0 USER S MANUAL Rev 1 05 A read cycle from GBUS can be executed on GBUS without a wait cycle The CPU_xxx signal shown in the timing charts below is a CPU signal The Gxxx signal i
53. r program 44 RTE V850E MA1 CB USER S MANUAL Rev 1 05 14 APPENDIX C GBUS COMMON SPECIFICATIONS This appendix explains the GBUS specifications that are not dependent on the type ofboard 14 1 14 1 1 14 1 2 14 2 TERMINOLOGY Terminology used in this appendix is explained below CPU Board and Motherboard A board in the RTE CB series is called a CPU board and a Midas lab board connected to GBUS of the CPU board is called a motherboard Bus Cycle and Micro Cycle GBUS is a general bus that can be accessed in burst mode A bus cycle consists of a series of cycles including a one in which a burst access occurs that is completed asserting of GADS is necessary to mark the end of a bus cycle Bus cycles are classified into single cycles and a burst cycles A single cycle is a bus cycle in which data transfer occurs only once A burst cycle is a bus cycle in which data transfer occurs two or more times One cycle for each data transfer in a burst cycle is called a micro cycle SIGNALS The GBUS signals are listed below The input output direction of each GBUS signal is indicated as viewed from the motherboard Therefore input means that a signal output from the CPU board is input to the motherboard this also applies to signal names Bidirectional signals change direction depending on the status of the bus cycle Input output signals also change direction depending on whether the bus master is the CPU board or
54. r related to memory and resource access 7 2 1 MEMC Registers Make the following register settings for the system bus Note that the setting for some registers differs depending on the setting of SW2 3 BCLK_LOW DWCO BCLK_LOW OFF OxFFFF484 0x1111 50 3 1 wait DWCO BCLK_LOW ON ped CS0 3 0 wait VSWC BCLK LOW OFF OxFFFFO6E 0x14 VPB BCLK gt 33 MHz 0x14 VSWC BCLK_LOW ON lt 33 MHz 0x12 OXFFFF48C Normal bus cycle OxFFFFO60 OxFCF3 Chip Select Control Register0 OxFFFFO62 0x2C11 Chip Select Control Register1 Same as the CPU initial value P OxFFFFO66 0x5555__ All 16 bit Same as the CPU initial value OXFFFFO68 0x0000 AI little endian Same as the CPU initial value OxFFFF4A4 0x2096 SDRAM 2 BOW 2 SSO 16 RAW 12 RFS1 BCLK LOW OFF OxFFFF4A6 0x8017 50 MHz 15 4 us RFS1 BCLK LOW 33 MHz 15 5 us Caution For the setting procedure of SDRAM related registers SCR1 and SFR1 refer to the CPU manual RTE V850E MA1 CB USER S MANUAL Rev 1 05 7 3 7 3 1 7 3 2 7 3 3 MEMORY RESOURCES RTE V850E MA1 CB has SDRAM SRAM and UV EPROM as on board memory resources As part of the memory space the GBUS chip select space is reserved This section explains these resources and memory devices SDRAM CS1 0800000 to 3FFFFFF Four SDRAM devices uPD4564441G5 each consisting of 4M words x 4 bits x 4 banks are provided as SDRAM The total capaci
55. reset when the system is reset Caution Do not change the contents of the UART while the monitor is being used TIC uPD71054 7808000H to 7808030FH The NEC 71054 is installed as a TIC The uPD71054 is compatible with the Intel 18254 It has three timers counters These timers counters are used to generate monitor timer interrupts Each register of the TIC is assigned as listed below 7808000H COUNTER 0 COUNTER 0 7808010H COUNTER 7808020H COUNTER 2 COUNTER 2 7808030H Control Word TIC Register Arrangement The channels of the TIC are connected as shown in the figure below Channel 0 is used as the interval timer for the Multi ROM monitor program Channels 1 and 2 can be used by a user program as necessary Channel 2 is connected to channel 1 by means of a cascade connection 22 RTE V850E MA1 CB USER S MANUAL Rev 1 05 To PIC GBUS GINTI 0 To GBUS GINTI 1 To INTP020 P21 of the CPU via SW8 4 NC Examples of modes CH 0 Mode 2 rate generator CH 1 Mode 2 rate generator CH 2 Mode 0 down counter Caution Do not change the contents of the CHO while the monitor is being accessed 7 4 9 GBUS ACCESS CONTROL 7809000H Read Write This register is used when accessing in access sizes other than half WORD 16 Bit to GBUS Byte Set this bit to 1 to read GBUS in byte units Usually keep this bit set to O This is used to access GBUS in byte units The rea
56. s a GBUS signal The following chart shows a read cycle CPU_CSn CPU_BCYST CPU_RD CPU_A 25 0 CPU_D 15 0 CPU WAIT Q1 GCSn GADS GW R GBLAST GREADY Q2 GDATA 31 0 GRD CPU_CLKOUT CPU_CSn CPU_BCYST CPU xWR CPU_A 250 Q1 GCSn GADS GW R GBLAST GREADY Q2 GDATA 31 0 GRD Ey deg Bp 27 74 m 34 38 RTE V850E MA1 CB USER S MANUAL Rev 1 05 11 3 CHIP SELECT On the board the following spaces are allocated to GBUS chip select In all the following spaces set the internal bus configuration register of the CPU to 16 bit data bus width and O or 1 wait cycle see Section 7 2 1 GBUS signal name CPU address space Physical address range RTE MB A resources GCSO0 Space of ADDR 25 24 0 1 of CS3 space 5000000 to 5FFFFFF SRAM 2M Space of ADDR 25 24 1 0 ADDR 23 6000000 to 67FFFFF Flash ROM 8M 0 of CS3 space 0000000 to O3FFFFF Space of CSO if SW2 1 FBOOT is ON GCS2 Space of ADDR 25 24 1 1 7900000 to 797FFFF l O register ADDR 23 19 10010 of CS3 space GCS3 Space of ADDR 25 24 1 0 ADDR 23 6800000 to 6FFFFFF EXT bus memory 1 of CS3 space space GCS4 Space of ADDR 25 24 1 1 ADR 23 21 7 00000 to 7BFFFFF EXT Bus space 101 of CS3 space GCS5 Space of ADDR 25 24 0 0 of CS3 space 4000000 to 4FFFFFF PCI bus space GCS6 Space of ADDR 25 24 1 1 7980000 to 798FFFF P
57. sed can be thought of as being similar to a program stored to ROM Also see the program example shown above 1 Defining program for rewriting the interrupt vector area ASM language Define a program consisting of only the branch instructions to be placed in the interrupt vector as shown below For details of the coding refer to the manual for the language processor Section intvct text Defined section name align globl _Int80 _Int80 jr _IntEntry jump to handler nop nop Note however that the program cannot be defined in such a way that it exceeds the vector boundary for one interrupt 28 RTE V850E MA1 CB USER S MANUAL Rev 1 05 9 4 2 Defining the section map Define the section map that is used during linking as follows An example of placing a program in the internal ROM area is shown below For details of the coding refer to the manual for the language processor intvct 0x80 text 0x1000 data align 0x10 First define the section of the program to be placed in the vector To use more than one interrupt define one section if the vectors are contiguous the interrupt vector boundaries must match If the vectors are not contiguous define a section for each interrupt and specify all the sections in the section map In this way a specific location for the alternate vector area can be rewritten when the program is downloaded and no code is necessary to rewrite the interrupt vector
58. sibility that the motherboard is not connected 45 RTE V850E MA1 CB USER S MANUAL Rev 1 05 GADDR 31 2 GBEN 3 0 GDATA 31 0 GADS GREADY GWAITE GBLAST GBTERM Input output Input output Bidirectional Input output Output input Input output Output input e Address signals of GBUS These signals are driven by a valid value during a cycle GADDR S31 is ignored on the motherboard if the CPU is the bus master The low order addresses A1 and AO use a byte enable signal GADDR 31 26 from the CPU board can be treated as 0 by using the EN signal If the bus master is the motherboard and if GADDR 25 is 0 the resources on the motherboard are selected if GADDR 25 is 1 the resources on the CPU board is selected Byte enable signals of GBUS These signals are always driven by a valid value during a cycle GBENO 1 GBEN2 and GBENG correspond to byte lanes GDATA 7 0 GDATA 15 8 GDATA 23 16 and GDATA 31 24 and the corresponding byte lane is valid if GBENx is low Bus data signals of GBUS These signals are pulled up to 10 kQ on the motherboard The direction of these signals is determined by GW R Address strobe signal of GBUS If this signal is sampled low on the rising edge of GCLK the start of a bus cycle is indicated The motherboard ignores GADS if none of the chip select signals GCS 7 0 is active Ready signal of GBUS If this signal is sampled low and GWAIT
59. ssed Lights when CS1 space is accessed Lights when CS2 space is accessed Lights when CS3 space is accessed Board LED Status TEST PINS FOR ROM EMULATOR JROM EM1 Test pins JROM EM1s are used to connect a ROM emulator They accept control signals listed below The following table lists the signal names and functions Input Signal name Function output RESET Input When a low level is supplied to this test pin the CPU is reset 1 A reset request signal from the ROM emulator is connected to the test pin The test pin is pulled up with 1 NMI Input When a low level is supplied to this test pin an NMI signal is given to the CPU See 2 Section 10 5 An NMI request signal from the ROM emulator is connected to the test pin The test pin is pulled up with 1 kQ fe AA 3 to the test pin JROM EM1 Pin Functions CLOCK SOCKET OSC1 An oscillator for generating the clock signal to be supplied to the CPU is mounted in the OSC1 socket OSC1 is converted to the 3 3 V level and is connected to the CPUCLK pin of the CPU Accepts DIP 8 pin half type oscillators When you have to cut an oscillator pin for convenience be careful not to cut it too short or otherwise the frame housing of the oscillator may touch a pin in the socket resulting in a short circuit occurring RTE V850E MA1 CB USER S MANUAL Rev 1 05 5 11 5 12 5 13 5 14 CRYSTAL SOCKET JP1 JP1 has two functions it is used t
60. ty is 32M bytes SRAM CS2 0400000 to 07FFFFF Two high speed SRAM devices each having a capacity of 512K words x 8 bits and a speed of 15 ns are provided as SRAM The total SRAM capacity therefore is 1M byte If the bus clock exceeds 33 MHz insert one wait cycle by using the wait controller of the CPU Ata clock frequency up to 33 MHz it can be accessed without a wait cycle Because the high order bits of the address lines are not decoded an image appears every 1M byte The second half 32 KB of the SRAM is used by the monitor as a work area and cannot be used by a user program see Sections 12 2 2 and 13 2 2 UV EPROM CS0 0000000 to 03FFFFF A ROM of 128K bytes 64K words x 16 bits 256K bytes 128K words x 16 bits or 512K bytes 256K words x 16 bits with an access time of 120 ns or less can be mounted as UV EPROM The type of ROM to be mounted and conditions are specified with SW3 see Section 5 5 Because the high order bits of the address lines are not decoded an image appears for each ROM capacity Depending on the setting of SW2 3 BCLK_LOW the number of ROM wait cycles is changed forcibly by hardware as shown below SW2 3 BCLK_LOW OFF 7 wait cycles SW2 3 BCLK_LOW ON 5 wait cycles 18 RTE V850E MA1 CB USER S MANUAL Rev 1 05 7 4 On board for the RTE V850E MA1 CB includes a serial controller TL16C550CPT timer uPD71054 LEDs and switches Also the chip select space of GBUS is reserved

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