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P89LPC920/921/922/9221 8-bit microcontrollers with two

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1. frcoosc internal RC oscillator frequency trimmed to 1 7 189 7 557 7 189 7 557 MHz nominal f 7 3728 MHz at Tamb 25 C fwoosc internal Watchdog oscillator 320 520 320 520 kHz frequency nominal f 400 kHz fosc oscillator frequency 0 12 MHz tote clock cycle see Figure 13 83 ns foLkp CLKLP active frequency 0 8 MHz Glitch filter glitch rejection P1 5 RST pin 3 50 R 50 ns signal acceptance P1 5 RST pin 125 125 ns glitch rejection any pin except 15 15 ns P1 5 RST signal acceptance any pin except 50 E 50 ns P1 5 RST External clock tCHCX HIGH time see Figure 13 33 tetcL tctcx 33 ns teLcx LOW time see Figure 13 33 tetcL tcHex 33 ns tcLcH rise time see Figure 13 8 8 ns tcHcL fall time see Figure 13 8 8 ns Shift register UART mode 0 txLXL serial port clock cycle time 16 tcc 1333 ns tavxH output data set up to clock rising 13tcitce 1083 ns edge txHax output data hold after clock rising teLcL 20 103 ns edge XHDX input data hold after clock rising edge 0 0 ns tovxH input data valid to clock rising edge 150 150 ns 1 Parameters are valid over operating temperature range unless otherwise specified Parts are tested to 2 MHz but are guaranteed to operate down to 0 Hz 9397 750 14469 Product data Koninklijke Philips Electronics N V 2004 All rights reserved 38 of 46 Rev 08 15 December 2004 Phili
2. 8 20 1 9397 750 14469 Internal reference voltage An internal reference voltage generator may supply a default reference when a single comparator input pin is used The value of the internal reference voltage referred to as Vref is 1 23 V 10 Koninklijke Philips Electronics N V 2004 All rights reserved Product data Rev 08 15 December 2004 29 of 46 Philips Semiconductors P89 LPC920 921 1922 9221 9397 750 14469 8 20 2 8 20 3 8 21 8 bit microcontrollers with two clock 80C51 core Comparator interrupt Each comparator has an interrupt flag contained in its configuration register This flag is set whenever the comparator output changes state The flag may be polled by software or may be used to generate an interrupt The two comparators use one common interrupt vector If both comparators enable interrupts after entering the interrupt service routine the user needs to read the flags to determine which comparator caused the interrupt Comparators and power reduction modes Either or both comparators may remain enabled when Power down or Idle mode is activated but both comparators are disabled automatically in Total Power down mode If a comparator interrupt is enabled except in Total Power down mode a change of the comparator output state will generate an interrupt and wake up the processor If the comparator output to a pin is enabled the pin should be configured in the push pull
3. P3M2 1 P3M2 0 00l xxxxxx00 PCON Power control register 87H SMOD1 SMODO BOPD BOI GF1 GFO PMOD1 PMODO 00 00000000 PCONA Power control register A B5H RTCPD VCPD I2PD SPD ool 00000000 Bit address D7 D6 D5 D4 D3 D2 D1 DO PSW Program status word DOH CY AC FO RS1 RSO OV F1 P 00H 00000000 PTOAD Port 0 digital input disable F6H PTOAD 5 PTOAD 4 PTOAD 3 PTOAD 2 PTOAD 1 00H xx00000x RSTSRC Reset source register DFH BOF POF R_BK R_WD R_SF R_EX 3 RTCCON Real time clock control D1H RTCF RTCS1 RTCSO ERTC RTCEN 6017I 6 RTCH Real time clock register D2H oo 00000000 HIGH RTCL Real time clock register LOW D3H oo s 00000000 SADDR Serial port address register AQH 00 00000000 SADEN Serial port address enable B9H 00 00000000 SBUF Serial Port data buffer 99H XX XXXXXXXX register Bit address OF 9E 9D 9C 9B 9A 99 98 SCON Serial port control 98H SMO FE SM1 SM2 REN TB8 RB8 TI RI 00 00000000 SSTAT Serial port extended status BAH DBMOD INTLO CIDIS DBISEL FE BR OE STINT 00 00000000 register SP Stack pointer 81H 07 00000111 TAMOD Timer 0 and 1 auxiliary mode 8FH T1M2 TOM2 00 xXX0xxx0 Bit address 8F 8E 8D 8C 8B 8A 89 88 TCON Timer 0 and 1 control 88H TF1 TR1 TFO TRO IE1 IT1 IEO ITO 00 00000000 THO Timer 0 HIGH 8CH 00 00000000 TH1 Timer 1 HIGH 8DH 00 00000000 TLO Timer 0 LOW 8AH 00 00000000 TL1 Timer 1 LOW 8BH 00 00000000 TMOD Timer 0 and 1 mode 89H T1GATE T1C M T1M1 TIMO TOGATE TOCAM TOM1 TOMO 00 00000000
4. W gt BS W C 0 P89LPC920 921 922 9221 8 bit microcontrollers with two clock 80C51 core 2 kB 4 kB 8 kB 3 V low power Flash with 256 byte data RAM Rev 08 15 December 2004 Product data 1 General description 2 Features The P89LPC920 921 922 9221 are single chip microcontrollers designed for applications demanding high integration low cost solutions over a wide range of performance requirements The P89LPC920 921 922 9221 is based on a high performance processor architecture that executes instructions in two to four clocks six times the rate of standard 80C51 devices Many system level functions have been incorporated into the P89LPC920 921 922 9221 in order to reduce component count board space and system cost 2 1 Principal features E 2kB 4kB 8 kB Flash code memory with 1 kB erasable sectors 64 byte erasable page size and single byte erase E 256 byte RAM data memory Two 16 bit counter timers Each timer may be configured to toggle a port output upon timer overflow or to become a PWM output E Real Time clock that can also be used as a system timer Two analog comparators with selectable inputs and reference source E Enhanced UART with fractional baud rate generator break detect framing error detection automatic address detection and versatile interrupt capabilities E 400 kHz byte wide I C bus communication port E Configurable on chip oscillator wi
5. 0 0000 17 8 10 Data RAM arrangement 00 18 8 11 Interu OTS a cates ecient dade aa a aa e ia 18 8 11 1 External interrupt inputs 00 18 8 12 VO DONS ers face See eaea a S TEE EAR N Chat 19 8 12 1 Port configurations 0 000000 19 8 12 2 Quasi bidirectional output configuration 20 8 12 3 Open drain output configuration 20 8 12 4 Input only configuration 00 20 8 12 5 Push pull output configuration 20 8 12 6 Port 0 analog functions 00 20 8 12 7 Additional port features 00 21 8 13 Power monitoring functions 21 8 13 1 Brownout detection 0 0000 21 8 13 2 Power on detection 0 000000 eee 21 8 14 Power reduction modes 00005 21 8 14 1 Idle Mode cee teen eee 22 8 14 2 Power down mode 0 0 0 0 cee eee 22 8 14 3 Total Power down mode 005 22 8 15 ROSCL i caerra meega nar ea haa debe meen 22 8 15 1 Reset veto sies rieres tees ea tia seis 23 8 16 Timers counters 0 and 1 0000 23 8 16 1 M d 0 rerrcsare edi tiaada sada aa aA 23 8 16 2 M deTreccciinieda meitats niri naian CREN 23 8 16 3 Mode 2i acer niena nae tea ii a e a i 24 8 16 4 Mode 3 oc deterred es snarpi ieda EEn 24 Koninklijke Philips Electronics N V 2004 Printed in the U S A All rights are reserved Reproduction in who
6. 3109 14908 490 9 OM YM 19 04 U0D0191W 1q 8 SIOJONPUOIDIWIIS Sdijiud L2c6 c6 1 c6 0c60d 168d p00z Jequiaseq GL 80 AeH elep yoNpold 9t JO EL 69tt L OSL L6E6 pansased S 4Su Ily 700 A N S91U0I 09 9 Sdillyd ay UI Table 4 Special function registers continued indicates SFRs that are bit addressable TRIM Internal oscillator trim register 96H ENCLK TRIM 5 TRIM 4 TRIM 3 TRIM 2 TRIM 1 TRIM 0 5 6 WDCON Watchdog control register A7H PRE2 PRE1 PREO WDRUN WDTOF WDCLK 4 6 WDL Watchdog load C1H FF 11111111 WFEED1_ Watchdog feed 1 C2H WFEED2_ Watchdog feed 2 C3H 1 All ports are in input only high impedance state after power up 2 BRGR1 and BRGRO must only be written if BRGEN in BRGCON SFR is 0 If any are written while BRGEN 1 the result is unpredictable 3 The RSTSRC register reflects the cause of the P89LPC920 921 922 9221 reset Upon a power up reset all reset source flags are cleared except POF and BOF the power on reset value is xx110000 4 After reset the value is 111001x1 i e PRE2 PREO are all 1 WORUN 1 and WDCLK 1 WDTOF bit is 1 after watchdog reset and is 0 after power on reset Other resets will not affect WDTOF 5 On power on reset the TRIM SFR is initialized with a factory preprogrammed value Other resets will not cause initialization of the TRIM register 6 The only reset source that affects these SF
7. 8 16 4 8 16 5 8 16 6 8 17 8 18 8 18 1 8 bit microcontrollers with two clock 80C51 core Mode 2 Mode 2 configures the Timer register as an 8 bit Counter with automatic reload Mode 2 operation is the same for Timer 0 and Timer 1 Mode 3 When Timer 1 is in Mode 3 it is stopped Timer 0 in Mode 3 forms two separate 8 bit counters and is provided for applications that require an extra 8 bit timer When Timer 1 is in Mode 3 it can still be used by the serial port as a baud rate generator Mode 6 In this mode the corresponding timer can be changed to a PWM with a full period of 256 timer clocks Timer overflow toggle output Timers 0 and 1 can be configured to automatically toggle a port output whenever a timer overflow occurs The same device pins that are used for the TO and T1 count inputs are also used for the timer toggle outputs The port outputs will be a logic 1 prior to the first timer overflow when this mode is turned on Real Time clock system timer The P89LPC920 921 922 9221 has a simple Real Time clock that allows a user to continue running an accurate timer while the rest of the device is powered down The Real Time clock can be a wake up or an interrupt source The Real Time clock is a 23 bit down counter comprised of a 7 bit prescaler and a 16 bit loadable down counter When it reaches all 0 s the counter will be reloaded again and the RTCF flag will be set The clock source for this counter can be
8. Koninklijke Philips Electronics N V 2004 All rights reserved Product data Rev 08 15 December 2004 20 of 46 Philips Semiconductors P89 LPC920 921 1922 9221 9397 750 14469 8 12 7 8 13 8 13 1 8 13 2 8 14 8 bit microcontrollers with two clock 80C51 core Additional port features After power up all pins are in Input Only mode Please note that this is different from the LPC76x series of devices e After power up all I O pins except P1 5 may be configured by software e Pin P1 5 is input only Pins P1 2 and P1 3 and are configurable for either input only or open drain Every output on the P89LPC920 921 922 9221 has been designed to sink typical LED drive current However there is a maximum total output current for all ports which must not be exceeded Please refer to Table 8 DC electrical characteristics for detailed specifications All ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals The slew rate is factory set to approximately 10 ns rise and fall times Power monitoring functions The P89LPC920 921 922 9221 incorporates power monitoring functions designed to prevent incorrect operation during initial power up and power loss or reduction during operation This is accomplished with two hardware functions Power on Detect and Brownout detect Brownout detection The Brownout detect function determines
9. XTAL1 P3 1 6 CLKOUT XTAL2 P3 0 P89LPC920FDH INT1 P1 4 8 SDA INTO P1 3 9 SCL TO P1 2 Fig 2 TSSOP20 pin configuration P89LPC921FDH P89LPC922FDH P89LPC9221FDH 002aaa408 PO 1 CIN2B KBI1 PO 2 CIN2A KBI2 P0 3 CIN1B KBI3 PO 4 CIN1A KBI4 P0 5 CMPREF KBI5 VDD P0 6 CMP1 KBI6 PO 7 T1 KBI7 P1 0 TXD P1 1 RXD KBIO CMP2 P0 0 XTAL1 P3 1 6 CLKOUT XTAL2 P3 0 INT1 P1 4 8 SDA INTO P1 3 9 SCL TO P1 2 Fig 3 DIP20 pin configuration P89LPC922FN P89LPC9221FN 002aaa407 PO 1 CIN2B KBI1 PO 2 CIN2A KBI2 PO 3 CIN1B KBI3 PO 4 CIN1 A KBI4 PO 5 CMPREF KBI5 VDD P0 6 CMP1 KBI6 PO 7 T1 KBI7 P1 0 TXD P1 1 RXD Koninklijke Philips Electronics N V 2004 All rights reserved Product data Rev 08 15 December 2004 Philips Semiconductors P89LPC920 921 1922 9221 8 bit microcontrollers with two clock 80C51 core 5 2 Pin description Table 3 Pin description P0 0 to P0 7 I O Port 0 Port 0 is an 8 bit I O port with a user configurable output type During reset Port 0 latches are configured in the input only mode with the internal pull up disabled The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected Each port pin is configured independently Refer to Section 8 12 1 Port configurations and Table 8 DC electrical characteristics for details The Keypad Interrupt feature operates with Port
10. Baud rate generator and selection Baud rate generator and selection The P89LPC920 921 922 9221 enhanced UART has an independent Baud Rate Generator The baud rate is determined by a baud rate preprogrammed into the BRGR1 and BRGRO SFRs which together form a 16 bit baud rate divisor value that works in a similar manner as Timer 1 but is much more accurate If the baud rate generator is used Timer 1 can be used for other timing functions The UART can use either Timer 1 or the baud rate generator output see Figure 7 Note that Timer T1 is further divided by 2 if the SMOD1 bit PCON 7 is set The independent Baud Rate Generator uses OSCCLK SMOD1 1 Timer 1 Overflow SBRGS 0 s A PCLK based o Baud Rate Modes 1 and 3 SMOD1 0 SBRGS 1 Baud Rate Generator 002aaa419 CCLK based Fig 7 Baud rate sources for UART Modes 1 3 Framing error Framing error is reported in the status register SSTAT In addition if SMODO PCON 6 is 1 framing errors can be made available in SCON 7 respectively If SMODO is 0 SCON 7 is SMO It is recommended that SMO and SM1 SCON 7 6 are set up when SMODO is 0 Koninklijke Philips Electronics N V 2004 All rights reserved Product data Rev 08 15 December 2004 25 of 46 Philips Semiconductors P89 LPC920 921 1922 9221 9397 750 14469 8 18 7 8 18 8 8 18 9 8 18 10 8 bit microcontrollers with two clock 80C51
11. V VIL LOW level input voltage SCL SDA only 0 5 0 3Vpp V Vih LH positive going threshold voltage except SCL SDA 0 6Vpp 0 7Vpp V Vin HIGH level input voltage SCL SDA only 0 7Vpp 5 5 V Vhys hysteresis voltage Port 1 0 2Vpp V VoL LOW level output voltage all ports lo 20 mA 0 6 1 0 V all modes except Hi Z 9 lo 3 2 mA 0 2 0 3 V VoH HIGH level output voltage lon 20 mA 0 8Vpp V push pull mode P0 3 to PO 7 P1 4 P1 6 P1 7 loH 3 2 mA Vpp 0 7 Vpp 0 4 V push pull mode all other ports loH 20 uA Vpp 0 3 Vpp 0 2 V quasi bidirectional mode all ports Cig input output pin capacitance 4 15 pF liL logical 0 input current all ports Vin 0 4 V 5 80 uA lui input leakage current all ports Vin Vic or Vin 6 10 uA Ire logical 1 to 0 transition current Vin 2 0 V at 7 8 30 450 uA all ports Vpp 3 6 V Rrst internal reset pull up resistor 10 30 kQ 9397 750 14469 Koninklijke Philips Electronics N V 2004 All rights reserved Product data Rev 08 15 December 2004 36 of 46 Philips Semiconductors P89 LPC920 921 1922 9221 8 bit microcontrollers with two clock 80C51 core Table 8 DC electrical characteristics continued Vpop 2 4 V to 3 6 V unless otherwise specified Tamb 40 C to 85 C for industrial unless otherwise specified Veo brownout trip voltage with 2 4 V lt Vpp lt 3 6 V 2 40 2 70 V BOV 0 BOPD 1 VREF bandg
12. 1 73 0 53 0 36 26 92 6 40 3 60 8 25 10 0 mm j 42 051 32 i30 o38 0o23 26 54 622 254 762 305 z780 a3 0754 2 r 0 068 0 021 0 014 1 060 0 25 0 14 0 32 0 39 inches 0 17 0 02 013 9051 0 015 0 009 1 045 o24 03 o142 o31 0o33 001 0 078 Note 1 Plastic or metal protrusions of 0 25 mm 0 01 inch maximum per side are not included REFERENCES OUTLINE EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99 42 27 SOT146 1 MS 001 SC 603 E ere Fig 16 DIP20 SOT146 1 9397 750 14469 Koninklijke Philips Electronics N V 2004 All rights reserved Product data Rev 08 15 December 2004 43 of 46 Philips Semiconductors P89LPC920 921 922 9221 8 bit microcontrollers with two clock 80C51 core 14 Revision history Table 13 Revision history 08 20041215 Product data 9397 750 14469 Modification e Added 18 MHz information 07 20041203 Product data 9397 750 14251 06 20031121 Product data 9397 750 12285 ECN 853 2403 01 A14557 of 18 November 2003 05 20031007 Product data 9397 750 12121 ECN 853 2403 30391 of 30 September 2003 04 20030909 Product data 9397 750 11945 ECN 853 2403 30305 of 5 September 2003 03 20030811 Preliminary data 9397 750 11786 02 20030522 Objective data 9397 750 11532 01 20030505 Preliminary data 9397 750 11387 9397 750 14469 Koninklijke Philips Electronics N V 2004 All
13. IEO 7 TFO ETO a ET1 TL amp RIRI j INTERRUPT ES ESR TO CPU a Do EST a J oo El2C 002aaa418 9397 750 14469 8 12 8 12 1 I O ports The P89LPC920 921 922 9221 has three I O ports Port 0 Port 1 and Port 3 Ports 0 and 1 are 8 bit ports and Port 3 is a 2 bit port The exact number of I O pins available depend upon the clock and reset options chosen as shown in Table 6 Table 6 Number of I O pins available On chip oscillator or No external reset except during power up 18 watchdog oscillator External RST pin supported 17 External clock input No external reset except during power up 17 External RST pin supported 16 Low medium high No external reset except during power up 16 speed oscillator External RST pin supported 15 external crystal or resonator 1 Required for operation above 12 MHz Port configurations All but three I O port pins on the P89LPC920 921 922 9221 may be configured by software to one of four types on a bit by bit basis These are quasi bidirectional standard 80C51 port outputs push pull open drain and input only Two configuration registers for each port select the output type for each port pin P1 5 RST can only be an input and cannot be configured Koninklijke Philips Electronics N V 2004 All rights reserved Product data Rev 08 15 December 2004 19 of 46 Phili
14. 2004 All rights reserved Product data Rev 08 15 December 2004 21 of 46 Philips Semiconductors P89 LPC920 921 1922 9221 9397 750 14469 8 14 1 8 14 2 8 14 3 8 15 8 bit microcontrollers with two clock 80C51 core Idle mode Idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated Any enabled interrupt source or reset may terminate Idle mode Power down mode The Power down mode stops the oscillator in order to minimize power consumption The P89LPC920 921 922 9221 exits Power down mode via any reset or certain interrupts In Power down mode the power supply voltage may be reduced to the RAM keep alive voltage Vram This retains the RAM contents at the point where Power down mode was entered SFR contents are not guaranteed after Vpp has been lowered to Vraw therefore it is highly recommended to wake up the processor via reset in this case Vpp must be raised to within the operating range before the Power down mode is exited Some chip functions continue to operate and draw power during Power down mode increasing the total power used during Power down These include Brownout detect Watchdog Timer Comparators note that Comparators can be powered down separately and Real Time Clock RTC System Timer The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock AND the RTC is enabled Total Power d
15. 2004 34 of 46 Philips Semiconductors P89LPC920 921 922 9221 9 Limiting values Table 7 Limiting values 8 bit microcontrollers with two clock 80C51 core In accordance with the Absolute Maximum Rating System IEC 60134 Tamb bias Operating bias ambient temperature 55 125 C Tstg storage temperature range 65 150 C Vxtal voltage on XTAL1 XTAL2 pin to Vss Vpop 0 5 V Vh voltage on any other pin to Vss 0 5 5 5 V loH 1 0 HIGH level output current per I O pin P0 3 to P0 7 P1 4 P1 6 20 mA P89LPC9221 P1 7 all other I O pins 8 mA HIGH level output current per I O pin 8 mA P89LPC920 921 922 loL vo LOW level output current per I O pin 20 mA IVo tot max maximum total I O current 160 mA P89LPC9221 maximum total I O current 80 mA P89LPC920 921 922 Ptot pack total power dissipation per package based on package heat 1 5 W transfer not device power consumption 1 The following applies to Limiting values a Stresses above those listed under Table 7 may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any conditions other than those described in Table 8 DC electrical characteristics Table 9 AC characteristics and Table 10 AC characteristics of this specification are not implied b This product includes circuitry specifically designed for the protection of its internal dev
16. 85 C 0 MHz to 18 MHz P89LPC9221FDH 8 kB 40 C to 85 C 0 MHz to 18 MHz Koninklijke Philips Electronics N V 2004 All rights reserved Product data Rev 08 15 December 2004 3 of 46 Philips Semiconductors P89LPC920 921 922 9221 8 bit microcontrollers with two clock 80C51 core 4 Block diagram Fig 1 P89LPC920 921 922 9221 HIGH PERFORMANCE LN 2 kB 4 kB 8 kB N K UART CODE FLASH l internal bus i i 256 BYTE N K REAL TIME CLOCK DATA RAM SYSTEM TIMER PORT 3 N lt 2c CONFIGURABLE I Os e PORT 1 N TIMER 0 l r CONFIGURABLE I Os TIMER 1 l I I a PORT 0 K WATCHDOGTIMER CONFIGURABLE I Os AND OSCILLATOR l I I KEYPAD lt ANALOG i INTERRUPT COMPARATORS PROGRAMMABLE OSCILLATOR DIVIDER CPU lt 7 l clock POWER MONITOR I CRYSTAL OR RESONATOR Block diagram BROWNOUT RESET ON CHIP RC OSCILLATOR 002aaa410 l I l I i I POWER ON RESET I l l 9397 750 14469 Koninklijke Philips Electronics N V 2004 All rights reserved Product data Rev 08 15 December 2004 4 of 46 P89LPC920 921 922 9221 8 bit microcontrollers with two clock 80C51 core Philips Semiconductors 5 Pinning information 9397 750 14469 5 1 Pinning KBIO CMP2 P0 0
17. Each port pin is configured independently Refer to Section 8 12 1 Port configurations and Table 8 DC electrical characteristics for details All pins have Schmitt triggered inputs Port 3 also provides various special functions as described below 7 VO P3 0 Port 3 bit 0 O XTAL2 Output from the oscillator amplifier when a crystal oscillator option is selected via the FLASH configuration O CLKOUT CPU clock divided by 2 when enabled via SFR bit ENCLK TRIM 6 It can be used if the CPU clock is the internal RC oscillator watchdog oscillator or external clock input except when XTAL1 XTAL2 are used to generate clock source for the real time clock system timer 6 VO P3 1 Port 3 bit 1 l XTAL1 Input to the oscillator circuit and internal clock generator circuits when selected via the FLASH configuration It can be a port pin if internal RC oscillator or watchdog oscillator is used as the CPU clock source and if XTAL1 XTAL2 are not used to generate the clock for the real time clock system timer Vss 5 l Ground 0 V reference Vpp 15 l Power Supply This is the power supply voltage for normal operation as well as Idle and Power down modes 1 Input Output for P1 0 P1 4 P1 6 P1 7 Input for P1 5 6 Logic symbol KBIO KBI1 gt KBI2 _ gt KBS gt KBI4 gt KBI5 gt KBI6 gt KBI7 gt CLKOUT lt Fig 4 L
18. On chip data memory usages Type DATA M Memory that can be addressed directly and indirectly 128 IDATA Memory that can be addressed indirectly 256 Interrupts The P89LPC920 921 922 9221 uses a four priority level interrupt structure This allows great flexibility in controlling the handling of the many interrupt sources The P89LPC920 921 922 9221 supports 12 interrupt sources external interrupts 0 and 1 timers 0 and 1 serial port Tx serial port Rx combined serial port Rx Tx brownout detect watchdog real time clock 12C keyboard and comparators 1 and 2 Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers IENO or IEN1 The IENO register also contains a global disable bit EA which disables all interrupts Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers IPO IPOH IP1 and IP1H An interrupt service routine in progress can be interrupted by a higher priority interrupt but not by another interrupt of the same or lower priority The highest priority interrupt service cannot be interrupted by any other interrupt source If two requests of different priority levels are pending at the start of an instruction the request of higher priority level is serviced If requests of the same priority level are pending at the start of an instruction an i
19. V 2004 All rights reserved Product data Rev 08 15 December 2004 16 of 46 Philips Semiconductors P89 LPC920 921 1922 9221 9397 750 14469 8 6 8 7 8 8 8 9 8 bit microcontrollers with two clock 80C51 core CPU Clock CCLK wake up delay The P89LPC920 921 922 9221 has an internal wake up timer that delays the clock until it stabilizes depending to the clock source used If the clock source is any of the three crystal selections low medium and high frequencies the delay is 992 OSCCLK cycles plus 60 to 100 us If the clock source is either the internal RC oscillator watchdog oscillator or external clock the delay is 224 OSCCLK cycles plus 60 to 100 us CPU Clock CCLK modification DIVM register The OSCCLK frequency can be divided down up to 510 times by configuring a dividing register DIVM to generate CCLK This feature makes it possible to temporarily run the CPU at a lower rate reducing power consumption By dividing the clock the CPU can retain the ability to respond to events that would not exit Idle mode by executing its normal program at a lower rate This can also allow bypassing the oscillator start up time in cases where Power down mode would otherwise be used The value of DIVM may be changed by the program at any time without interrupting code execution Low power select The P89LPC920 921 922 9221 is designed to run at 18 MHz CCLK maximum However if CCLK is 8 MHz or slower the CLKLP
20. chip oscillator requiring no external components The watchdog prescaler is selectable from eight values Low voltage reset Brownout detect allows a graceful system shutdown when power fails May optionally be configured as an interrupt Idle and two different Power down reduced power modes Improved wake up from Power down mode a low interrupt input starts execution Typical Power down current is 1 uA total Power down with voltage comparators disabled Active LOW reset On chip power on reset allows operation without external reset components A reset counter and reset glitch suppression circuitry prevent spurious and incomplete resets A software reset function is also available Oscillator Fail Detect The watchdog timer has a separate fully on chip oscillator allowing it to perform an oscillator fail detect function Programmable port output configuration options quasi bidirectional open drain push pull input only Port input pattern match detect Port 0 may generate an interrupt when the value of the pins match or do not match a programmable pattern LED drive capability 20 mA on all port pins A maximum limit is specified for the entire chip 160 mA for the P89LPC9221 80 mA for the P89LPC920 921 922 Controlled slew rate port outputs to reduce EMI Outputs have approximately 10 ns minimum ramp times Only power and ground connections are required to operate the P89LPC920 921 922 9221 when inter
21. either the CPU clock CCLK or the XTAL oscillator provided that the XTAL oscillator is not being used as the CPU clock If the XTAL oscillator is used as the CPU clock then the RTC will use CCLK as its clock source Only power on reset will reset the Real Time clock and its associated SFRs to the default state UART The P89LPC920 921 922 9221 has an enhanced UART that is compatible with the conventional 80C51 UART except that Timer 2 overflow cannot be used as a baud rate source The P89LPC920 921 922 9221 does include an independent Baud Rate Generator The baud rate can be selected from the oscillator divided by a constant Timer 1 overflow or the independent Baud Rate Generator In addition to the baud rate generation enhancements over the standard 80C51 UART include Framing Error detection automatic address recognition selectable double buffering and several interrupt options The UART can be operated in 4 modes shift register 8 bit UART 9 bit UART and CPU clock 32 or CPU clock 16 Mode 0 Serial data enters and exits through RxD TxD outputs the shift clock 8 bits are transmitted or received LSB first The baud rate is fixed at 1 46 of the CPU clock frequency Koninklijke Philips Electronics N V 2004 All rights reserved Product data Rev 08 15 December 2004 24 of 46 Philips Semiconductors P89 LPC920 921 1922 9221 9397 750 14469 8 18 2 8 18 3 8 18 4 8 18 5 8 18 6 8 bit microcontrol
22. if the power supply voltage drops below a certain level The default operation is for a Brownout detection to cause a processor reset however it may alternatively be configured to generate an interrupt Brownout detection may be enabled or disabled in software If Brownout detection is enabled the brownout condition occurs when Vpop falls below the brownout trip voltage Vgo see Table 8 DC electrical characteristics and is negated when Vpp rises above Vego If the P89LPC920 921 922 9221 device is to operate with a power supply that can be below 2 7 V BOE should be left in the unprogrammed state so that the device can operate at 2 4 V otherwise continuous brownout reset may prevent the device from operating For correct activation of Brownout detect the Vpp rise and fall times must be observed Please see Table 8 DC electrical characteristics for specifications Power on detection The Power on Detect has a function similar to the Brownout detect but is designed to work as power comes up initially before the power supply voltage reaches a level where Brownout detect can work The POF flag in the RSTSRC register is set to indicate an initial power up condition The POF flag will remain set until cleared by software Power reduction modes The P89LPC920 921 922 9221 supports three different power reduction modes These modes are Idle mode Power down mode and total Power down mode Koninklijke Philips Electronics N V
23. kB sector from 1C00H to 1FFFH in the P89LPC922 9221 or the 1 kB sector from OCOOH to OFFFH in the P89LPC921 or the 1 kB sector from 0400H to 07FFH in the P89LPC920 Instead the page erase function can be used to erase the eight 64 byte pages which comprise the lower 512 bytes of the sector A custom boot loader can be written with the Boot Vector set to the custom boot loader if desired Hardware activation of the boot loader The boot loader can also be executed by forcing the device into ISP mode during a power on sequence see the P89LPC920 921 922 9221 User s Manual for specific information This has the same effect as having a non zero Boot Status Bit This allows an application to be built that will normally execute user code but can be manually forced into ISP operation If the factory default setting for the Boot Vector is changed it will no longer point to the factory pre programmed ISP boot loader code If this happens the only way it is possible to change the contents of the Boot Vector is through the parallel programming method provided that the end user application does not contain a customized loader that provides for erasing and reprogramming of the Boot Vector Koninklijke Philips Electronics N V 2004 All rights reserved Product data Rev 08 15 December 2004 33 of 46 Philips Semiconductors P89 LPC920 921 1922 9221 8 25 8 26 9397 750 14469 8 bit microcontrollers with two clock 80C51 core and Bo
24. rights reserved Product data Rev 08 15 December 2004 44 of 46 Philips Semiconductors P89LPC920 921 922 9221 15 Data sheet status 8 bit microcontrollers with two clock 80C51 core I Objective data Development This data sheet contains data from the objective specification for product development Philips Semiconductors reserves the right to change the specification in any manner without notice Il Preliminary data Qualification This data sheet contains data from the preliminary specification Supplementary data will be published at a later date Philips Semiconductors reserves the right to change the specification without notice in order to improve the design and supply the best possible product lll Product data Production This data sheet contains data from the product specification Philips Semiconductors reserves the right to make changes at any time in order to improve the design manufacturing and supply Relevant changes will be communicated via a Customer Product Process Change Notification CPCN 1 Please consult the most recently issued data sheet before initiating or completing a design 2 The product status of the device s described in this data sheet may have changed since this data sheet was published The latest information is available on the Internet at URL http www semiconductors philips com 3 For data sheets describing multiple type numbers the highest level product status determines t
25. specified operating voltage When using an oscillator frequency above 12 MHz in some applications an external brownout detect circuit may be required to hold the device in reset when Vpp falls below the minimum specified operating voltage 8 2 6 Clock output The P89LPC920 921 922 9221 supports a user selectable clock output function on the XTAL2 CLKOUT pin when crystal oscillator is not being used This condition occurs if another clock source has been selected on chip RC oscillator watchdog oscillator external clock input on X1 and if the Real Time clock is not using the crystal oscillator as its clock source This allows external devices to synchronize to the P89LPC920 921 922 9221 This output is enabled by the ENCLK bit in the TRIM register The frequency of this clock output is Y that of the CCLK If the clock output is not needed in Idle mode it may be turned off prior to entering Idle saving additional power 8 3 On chip RC oscillator option The P89LPC920 921 922 9221 has a 6 bit TRIM register that can be used to tune the frequency of the RC oscillator During reset the TRIM value is initialized to a factory pre programmed value to adjust the oscillator frequency to 7 373 MHz 1 at room temperature End user applications can write to the Trim register to adjust the on chip RC oscillator to other frequencies 8 4 Watchdog oscillator option The watchdog has a separate oscillator which has a frequency of 400 kHz This oscilla
26. unless otherwise specified Parts are tested to 2 MHz but are guaranteed to operate down to 0 Hz 2 When using an oscillator frequency above 12 MHz the reset input function of P1 5 must be enabled An external circuit is required to hold the device in reset at power up until Vpp has reached its specified level When system power is removed Vpp will fall below the minimum specified operating voltage When using an oscillator frequency above 12 MHz in some applications an external brownout detect circuit may be required to hold the device in reset when Vpp falls below the minimum specified operating voltage 9397 750 14469 Koninklijke Philips Electronics N V 2004 All rights reserved Product data Rev 08 15 December 2004 39 of 46 Philips Semiconductors P89 LPC920 921 1922 9221 8 bit microcontrollers with two clock 80C51 core tQVXH Output Data Write to SBUF ee cali ale Ft AAA RA AO ARAA Clear RI Set RI 002aaa425 Fig 12 Shift register mode timing Vpp 0 5V 0 2 Vpp 0 9 0 45 V 0 2 Vpp 0 1 V tCHCL 002aaa416 Fig 13 External clock timing Table 11 AC characteristics ISP entry mode Vpop 2 4 V to 3 6 V unless otherwise specified Tamb 40 C to 85 C for industrial unless otherwise specified tyr RST delay from Vpp active 50 us tRH RST HIGH time 1 32 us taL RST LOW time 1 us VDD RST 002aaa426 Fig 14 ISP entry wa
27. 0 pins All pins have Schmitt triggered inputs Port 0 also provides various special functions as described below 1 VO P0 0 Port 0 bit 0 O CMP2 Comparator 2 output l KBIO Keyboard input 0 20 VO P0 1 Port 0 bit 1 l CIN2B Comparator 2 positive input B l KBI1 Keyboard input 1 19 V0 P0 2 Port 0 bit 2 l CIN2A Comparator 2 positive input A l KBI2 Keyboard input 2 18 VO P0 3 Port 0 bit 3 High current source P89LPC9221 l CIN1B Comparator 1 positive input B l KBI3 Keyboard input 3 17 VO P0 4 Port 0 bit 4 High current source P89LPC9221 l CIN1A Comparator 1 positive input A l KBI4 Keyboard input 4 16 I O P0 5 Port 0 bit 5 High current source P89LPC9221 l CMPREF Comparator reference negative input l KBI5 Keyboard input 5 14 VO P0 6 Port 0 bit 6 High current source P89LPC9221 O CMP1 Comparator 1 output l KBI6 Keyboard input 6 13 I O P0 7 Port 0 bit 7 High current source P89LPC9221 1 0 T1 Timer counter 1 external count input or overflow output l KBI7 Keyboard input 7 9397 750 14469 Koninklijke Philips Electronics N V 2004 All rights reserved Product data Rev 08 15 December 2004 6 of 46 Philips Semiconductors P89LPC920 921 922 9221 8 bit microcontrollers with two clock 80C51 core Table 3 Pin description contin
28. 2004 All rights reserved Product data Rev 08 15 December 2004 27 of 46 Philips Semiconductors P89LPC920 921 922 9221 9397 750 14469 8 bit microcontrollers with two clock 80C51 core L o ERTE ADDRESS REGISTER INPUT FILTER P1 3 SDA OUTPUT STAGE INTERNAL BUS BIT COUNTER ARBITRATION amp SYNC LOGIC TIMING amp CONTROL P1 2 SCL LOGIC SERIAL CLOCK pla GENERATOR TIMER 1 pi eee eee OVERFLOW I P1 2 o 12CON CONTROL REGISTERS amp H I2SCLH L DUTY CYCLE REGISTER I2SCLL SCL DUTY CYC GIS S INTERRUPT STATUS STATUS BUS DECODER I2STAT STATUS REGISTER A Fig 9 1 C bus serial interface block diagram 002aaa421 Koninklijke Philips Electronics N V 2004 All rights reserved Product data Rev 08 15 December 2004 28 of 46 Philips Semiconductors P89LPC920 921 922 9221 8 bit microcontrollers with two clock 80C51 core 8 20 Analog comparators Two analog comparators are provided on the P89LPC920 921 922 9221 Input and output options allow use of the comparators in a number of different configurations Comparator operation is such that the output is a logical one which may be read ina register and or routed to a pin when the positive input one of two selectable pins is greater than the negative input selectable from a pin or an internal reference voltage Otherwise the out
29. 2ADR 4 I2ADR 3 I2ADR 2 2ADR 1 I2ADR O GC 00 00000000 Bit address DF DE DD DC DB DA D9 D8 I2CON 12C control register D8H I2EN STA STO Sl AA CRSEL 00 x00000x0 I2DAT 12C data register DAH I2SCLH Serial clock generator SCL DDH 00 00000000 duty cycle register HIGH 9109 14908 490 9 OM YUM S19 04 U0D0191W 1q 8 SIOJONPUODIWIIS Ssdijiud L2c6 c6 1 c6 0c60d 168d p00z Jequiaceq GL 80 AeH elep yONpold 9b JO LL 69br L OSL L6E6 pansasel SIYGU Ily 700 AN S91U0I 09 9 Sdillyd Oxf UU Table 4 Special function registers continued indicates SFRs that are bit addressable I2SCLL Serial clock generator SCL DCH 00 00000000 duty cycle register LOW I2STAT 12C status register D9H STA4 STA 3 STA 2 STA 1 STA O 0 0 0 F8 11111000 Bit address AF AE AD AC AB AA A9 A8 IENO Interrupt enable 0 A8H EA EWDRT EBO ES ESR ET1 EX1 ETO EXO o0 00000000 Bit address EF EE ED EC EB EA E9 E8 IEN1 Interrupt enable 1 E8H EST EC EKBI El2C ool 00x00000 Bit address BF BE BD BC BB BA B9 B8 IPO Interrupt priority 0 B8H PWDRT PBO PS PSR PT1 PX1 PTO PXO ool x0000000 IPOH Interrupt priority 0 HIGH B7H PWDRT PBOH PSH PT1H PX1H PTOH PXOH ool x0000000 H PSRH Bit address FF FE FD FC FB FA F9 F8 IP1 Interrupt priority 1 F8H PST PC PKBI Pl2C ool 00x00000 IP1H Interrupt priority 1 HIGH F7H PSTH PCH PKBIH PI2CH 00l 00x00000 KBCON
30. ISP mode during power on see P89LPC920 921 922 9221 User s Manual Otherwise instructions will be fetched from address 0000H Timers counters 0 and 1 The P89LPC920 921 922 9221 has two general purpose counter timers which are upward compatible with the standard 80C51 Timer 0 and Timer 1 Both can be configured to operate either as timers or event counter An option to automatically toggle the TO and or T1 pins upon timer overflow has been added In the Timer function the register is incremented every machine cycle In the Counter function the register is incremented in response to a 1 to 0 transition at its corresponding external input pin TO or T1 In this function the external input is sampled once during every machine cycle Timer 0 and Timer 1 have five operating modes modes 0 1 2 3 and 6 Modes 0 1 2 and 6 are the same for both Timers Counters Mode 3 is different Mode 0 Putting either Timer into Mode 0 makes it look like an 8048 Timer which is an 8 bit Counter with a divide by 32 prescaler In this mode the Timer register is configured as a 13 bit register Mode 0 operation is the same for Timer 0 and Timer 1 Mode 1 Mode 1 is the same as Mode 0 except that all 16 bits of the timer register are used Koninklijke Philips Electronics N V 2004 All rights reserved Product data Rev 08 15 December 2004 23 of 46 Philips Semiconductors P89 LPC920 921 1922 9221 9397 750 14469 8 16 3
31. Keypad control register 94H PATN KBIF o0 XXXXXX00 _SEL KBMASK Keypad interrupt mask 86H 00 00000000 register KBPATN Keypad pattern register 93H FF 11111111 Bit address 87 86 85 84 83 82 81 80 PO Port 0 80H T1 KB7 CMP1 CMPREF CINIA CIN1B CIN2A CIN2B CMP2 m KB6 KB5 KB4 KB3 KB2 KB1 KBO Bit address 97 96 95 94 93 92 91 90 P1 Port 1 90H RST INT1 INTO TO SCL RXD TXD M SDA Bit address B7 B6 B5 B4 B3 B2 B1 Bo P3 Port 3 BOH XTAL1 XTAL2 m POM1 Port 0 output mode 1 84H POM1 7 POM1 6 POM1 5 POM1 4 POM1 3 POM1 2 POM1 1 POM1 0 FF 11111111 POM2 Port 0 output mode 2 85H POM2 7 POM2 6 POM2 5 POM2 4 POM2 3 POM2 2 POM2 1 POM2 0 00 00000000 P1M1 Port 1 output mode 1 91H P1M1 7 P1M1 6 P1M1 4 P1M1 3 P1M1 2 P1M1 1 P1M1 0 D30 11x1xx11 9109 14908 490 9 OM YUM S19 04 U0D0191W 1q 8 SIOJONPUOIDIWIIS Sdijiud L2c6 c6 1 c6 0c60d 168d p00z Jequiaseq GL 80 AeH elep yONpold 9b JO ZL 69br L OSL L6E6 pansased S 4Su Ily POO AN S91U0I 09 9 Sdiliyd Oy HUIUOY Table 4 indicates SFRs that are bit addressable Special function registers continued P1M2 Port 1 output mode 2 92H P1M2 7 P1M2 6 P1M2 4 P1M2 3 P1M2 2 P1M2 1 P1M2 0 00l 00x0xx00 P3M1 Port 3 output mode 1 BiH P3M1 1 P3M1 0 O03 xxxxxx11 P3M2 Port 3 output mode 2 B2H
32. LIPS Let make things beter
33. LPC920 921 922 9221 Contents 1 General description 00ee eee ee eens 1 2 Features e siccacs scare au css nea nie EErEE EENES 1 2 1 Principal features 00 0 000000 e eee 1 2 2 Additional features 000000000005 2 3 Ordering information 00eee cence eee 3 3 1 Ordering options 0 2 eee eee 3 4 Block diagram 000 c eee eee eee eee 4 5 Pinning information 00e cece eee 5 5 1 PINNING soc aa ast aona anaa E A EAA A 5 5 2 Pin AESC eses idara bead 6 6 Logic symbol 0 0 c eee eee eee 8 7 Special function registers 000eeee eee 9 8 Functional description 00e0e eee 14 8 1 Enhanced CPU 0 cece eee ee eee 14 8 2 COCKS ad icernd erage cheese tinea aE 14 8 2 1 Clock definitions 00 0 eee eee ee eee 14 8 2 2 CPU clock OSCCLK 0 000 e ee eee 14 8 2 3 Low speed oscillator option 14 8 2 4 Medium speed oscillator option 14 8 2 5 High speed oscillator option 14 8 2 6 Clock OUtpUts a creea eae ees are 15 8 3 On chip RC oscillator option 15 8 4 Watchdog oscillator option 0 15 8 5 External clock input option 0 15 8 6 CPU Clock CCLK wake up delay 17 8 7 CPU Clock CCLK modification DIVM register 17 8 8 Low power select 02000 cee eee 17 8 9 Memory organization
34. Rs is power on reset 9109 14908 490 9 OM YM S19 04 U090191W 1q 8 SIOJONPUODIWIAS Sdijiud L2c6 c6 1 c6 0c60d 168d Philips Semiconductors P89 LPC920 921 1922 9221 8 bit microcontrollers with two clock 80C51 core 8 Functional description 9397 750 14469 8 1 8 2 8 2 1 8 2 2 8 2 3 8 2 4 8 2 5 Remark Please refer to the P89LPC920 921 922 9221 User s Manual for a more detailed functional description Enhanced CPU The P89LPC920 921 922 9221 uses an enhanced 80C51 CPU which runs at 6 times the speed of standard 80C51 devices A machine cycle consists of two CPU clock cycles and most instructions execute in one or two machine cycles Clocks Clock definitions The P89LPC920 921 922 9221 device has several internal clocks as defined below OSCCLK Input to the DIVM clock divider OSCCLK is selected from one of four clock sources see Figure 5 and can also be optionally divided to a slower frequency see Section 8 7 CPU Clock CCLK modification DIVM register Note fosc is defined as the OSCCLK frequency CCLK CPU clock output of the clock divider There are two CCLK cycles per machine cycle and most instructions are executed in one to two machine cycles two or four CCLK cycles RCCLK The internal 7 373 MHz RC oscillator output PCLK Clock for the various peripheral devices and is CCLK 2 CPU clock OSCCLK The P89LPC920 921 922 9221 provides several user selecta
35. SFR bit AUXR1 7 can be set to 1 to lower the power consumption further On any reset CLKLP is 0 allowing highest performance access This bit can then be set in software if CCLK is running at 8 MHz or slower Memory organization The various P89LPC920 921 922 9221 memory spaces are as follows e DATA 128 bytes of internal data memory space 00h 7Fh accessed via direct or indirect addressing using instruction other than MOVX and MOVC All or part of the Stack may be in this area e IDATA Indirect Data 256 bytes of internal data memory space 00h FFh accessed via indirect addressing using instructions other than MOVX and MOVC All or part of the Stack may be in this area This area includes the DATA area and the 128 bytes immediately above it e SFR Special Function Registers Selected CPU registers and peripheral control and status registers accessible only via direct addressing e CODE 64 kB of Code memory space accessed as part of program execution and via the MOVC instruction The P89LPC920 921 922 9221 has 2 kB 4 kB 8 kB of on chip Code memory Koninklijke Philips Electronics N V 2004 All rights reserved Product data Rev 08 15 December 2004 17 of 46 Philips Semiconductors P89 LPC920 921 1922 9221 9397 750 14469 8 bit microcontrollers with two clock 80C51 core 8 10 Data RAM arrangement 8 11 8 11 1 The 256 bytes of on chip RAM are organized as shown in Table 5 Table 5
36. T360 1 j E gt A eo X 4 N i 7 f Fi 3 7 we I lt He v A Y o oao A2 A Ai A3 i al T Lp f HHHH B il X n a JL Sw detai e p 0 25 5mm l t i r i li a scale DIMENSIONS mm are the original dimensions A 1 2 1 UNIT nax At A2 As bp c DM E e He L Lp v w y 2M 6 0 15 0 95 0 30 0 2 6 6 4 5 6 6 0 75 0 4 0 5 8 mm 11 oos oso 019 ot 64 aa 28 62 osa os 202 03 01 o2 o Notes 1 Plastic or metal protrusions of 0 15 mm maximum per side are not included 2 Plastic interlead protrusions of 0 25 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN ISS EDATE VERSION IEC JEDEC JEITA PROJECTION SOT360 1 MO 153 E soi 4 Fig 15 TSSOP20 SOT360 1 9397 750 14469 Product data Rev 08 15 December 2004 Koninklijke Philips Electronics N V 2004 All rights reserved 42 of 46 Philips Semiconductors P89LPC920 921 922 9221 DIP20 plastic dual in line package 20 leads 300 mil 8 bit microcontrollers with two clock 80C51 core SOT146 1 seating plane in 1 index we 1 10 0 5 10mm l rails ss s scale DIMENSIONS inch dimensions are derived from the original mm dimensions A A1 A2 1 1 z UNIT max min max b by c D E e e1 L Me My w max
37. ap reference voltage 1 11 1 23 1 34 V TCvvreF bandgap temperature coefficient 10 20 ppm C 1 Typical ratings are not guaranteed The values listed are at room temperature 3 V 2 The lpp oper IDD idie aNd lpp pp Specifications are measured using an external clock with the following functions disabled comparators brownout detect and Watchdog timer 3 See Table 7 Limiting values on page 35 for steady state non transient limits on Io or loH If loL loH exceeds the test condition Vot Von may exceed the related specification 4 Pin capacitance is characterized but not tested 5 Measured with port in quasi bidirectional mode 6 Measured with port in high impedance mode 7 Ports in quasi bidirectional mode with weak pull up applies to all port pins with pull ups Does not apply to open drain pins 8 Port pins source a transition current when used in quasi bidirectional mode and externally driven from 1 to 0 This current is highest when Vin is approximately 2 V 9397 750 14469 Koninklijke Philips Electronics N V 2004 All rights reserved Product data Rev 08 15 December 2004 37 of 46 P89LPC920 921 922 9221 8 bit microcontrollers with two clock 80C51 core Philips Semiconductors 11 Dynamic characteristics Table 9 AC characteristics Vpop 2 4 V to 3 6 V unless otherwise specified Tamb 40 C to 85 C for industrial unless otherwise specified
38. ble oscillator options in generating the CPU clock This allows optimization for a range of needs from high precision to lowest possible cost These options are configured when the FLASH is programmed and include an on chip watchdog oscillator an on chip RC oscillator an oscillator using an external crystal or an external clock source The crystal oscillator can be optimized for low medium or high frequency crystals covering a range from 20 kHz to 12 MHz Low speed oscillator option This option supports an external crystal in the range of 20 kHz to 100 kHz Ceramic resonators are also supported in this configuration Medium speed oscillator option This option supports an external crystal in the range of 100 kHz to 4 MHz Ceramic resonators are also supported in this configuration High speed oscillator option This option supports an external crystal in the range of 4 MHz to 18 MHz Ceramic resonators are also supported in this configuration When using an oscillator frequency above 12 MHz the reset input function of P1 5 must be enabled An external circuit is required to hold the device in reset at power up until Vpp has reached its specified level When system power is removed Vpp will fall below Koninklijke Philips Electronics N V 2004 All rights reserved Product data Rev 08 15 December 2004 14 of 46 Philips Semiconductors P89 LPC920 921 1922 9221 8 bit microcontrollers with two clock 80C51 core the minimum
39. bled Modes 1 2 and 3 26 The 9t bit bit 8 in double buffering Modes 1 2 and e S E sane Se eed edie a Ree ea eet 26 l2C bus serial interface 0 00 cece 27 Analog comparators 0000 29 Internal reference voltage 0 00 29 Comparator interrupt 00 0 0 ee ee eee 30 Comparators and power reduction modes 30 Keypad interrupt KBI 0000 30 Watchdog timM l iicinsectasidanercede Gade cud 31 Additional features 0 000 eee 31 Software reset 0 0 0 0 000 cece 31 Dual data pointers 0 00000 eee eee 31 Flash program memory 200000ee eee 32 General description 00 00 ee eee ee 32 FR AtUNOS ainiin E aeaa ra Sete anes Rabe elena mom eee 32 ISP and IAP capabilities of the P89LPC920 921 922 9221 32 User configuration bytes 0000 34 User sector security bytes 34 Limiting valueS 0 00 c cece eee eee 35 Static characteristics 0 0c eee eee eee 36 Dynamic characteristics 20200e0ee 38 Comparator electrical characteristics 41 Package outline 00 cess eee eee eee 42 Revision history 0c cece ee eee 44 Data sheet status 0 00sec eee eee eee 45 Definitions esner stoga ditest epin una 45 DISCIAIME S 2 sick see sae renra ee es 45 Licenses 2 sccsscc chad eniaddnreeteeee ewes 45 PHI
40. core Break detect Break detect is reported in the status register SSTAT A break is detected when 11 consecutive bits are sensed LOW The break detect can be used to reset the device and force the device into ISP mode Double buffering The UART has a transmit double buffer that allows buffering of the next character to be written to SBUF while the first character is being transmitted Double buffering allows transmission of a string of characters with only one stop bit between any two characters as long as the next character is written between the start bit and the stop bit of the previous character Double buffering can be disabled If disabled DBMOD i e SSTAT 7 0 the UART is compatible with the conventional 80C51 UART If enabled the UART allows writing to SnBUF while the previous data is being shifted out Double buffering is only allowed in Modes 1 2 and 3 When operated in Mode 0 double buffering must be disabled DBMOD 0 Transmit interrupts with double buffering enabled Modes 1 2 and 3 Unlike the conventional UART in double buffering mode the Tx interrupt is generated when the double buffer is ready to receive new data The 9th bit bit 8 in double buffering Modes 1 2 and 3 If double buffering is disabled TB8 can be written before or after SBUF is written as long as TB8 is updated some time before that bit is shifted out TB8 must not be changed until the bit is shifted out as indicated by th
41. e Feeding the watchdog requires a two byte sequence If PCLK is selected as the watchdog clock and the CPU is powered down the watchdog is disabled The Watchdog timer has a time out period that ranges from a few us to a few seconds Please refer to the P89LPC920 921 922 9221 User s Manual for more details MOV WFEED1 0A5H MOV WFEED2 05AH uate BIT DOWN oscillator z 8 ator oe PRESCALER Lo SOUNTER RESET i ry ry ry i see note 1 j SHADOW CONTROL REGISTER REGISTER ry ry ry FOR WDCON AAA AA WDCON A7H PReo WDRUN wproF WDCLK y feed sequence 1 Watchdog reset can also be caused by an invalid feed sequence or by writing to WDCON not immediately followed by a Fig 11 Watchdog timer in watchdog mode WDTE 1 002aaa423 8 23 8 23 1 8 23 2 9397 750 14469 Additional features Software reset The SRST bit in AUXR1 gives software the opportunity to reset the processor completely as if an external reset or watchdog reset had occurred Care should be taken when writing to AUXR1 to avoid accidental software resets Dual data pointers The dual Data Pointers DPTR provides two different Data Pointers to specify the address used with certain instructions The DPS bit in the AUXR1 register selects one of the two Data Pointers Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS bit may be toggled thereby switch
42. e Tx interrupt If double buffering is enabled TB8 must be updated before SBUF is written as TB8 will be double buffered together with SBUF data Koninklijke Philips Electronics N V 2004 All rights reserved Product data Rev 08 15 December 2004 26 of 46 Philips Semiconductors P89 LPC920 921 922 9221 8 bit microcontrollers with two clock 80C51 core 8 19 1 C bus serial interface 2C bus uses two wires SDA and SCL to transfer information between devices connected to the bus and it has the following features e Bidirectional data transfer between masters and slaves e Multimaster bus no central master e Arbitration between simultaneously transmitting masters without corruption of serial data on the bus e Serial clock synchronization allows devices with different bit rates to communicate via one serial bus e Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer e The 2C bus may be used for test and diagnostic purposes A typical 1 C bus configuration is shown in Figure 8 The P89LPC920 921 922 9221 device provides a byte oriented I C bus interface that supports data transfers up to 400 kHz SDA 12C BUS SCL P1 3 SDA P1 2 SCL OTHER DEVICE OTHER DEVICE WITH I2C BUS WITH I2C BUS Po9LFC920 921 922 INTERFACE INTERFACE 002aaa420 Fig 8 1 C bus configuration 9397 750 14469 Koninklijke Philips Electronics N V
43. eset input if selected via FLASH configuration A LOW on this pin resets the microcontroller causing I O ports and peripherals to take on their default states and the processor begins execution at address 0 When using an oscillator frequency above 12 MHz the reset input function of P1 5 must be enabled An external circuit is required to hold the device in reset at power up until Vpp has reached its specified level When system power is removed Vpp will fall below the minimum specified operating voltage When using an oscillator frequency above 12 MHz in some applications an external brownout detect circuit may be required to hold the device in reset when Vpp falls below the minimum specified operating voltage 1 0 P1 6 Port 1 bit 6 High current source P89LPC9221 9397 750 14469 1 0 P1 7 Port 1 bit 7 High current source P89LPC9221 Koninklijke Philips Electronics N V 2004 All rights reserved Product data Rev 08 15 December 2004 7 of 46 Philips Semiconductors P89LPC920 921 1922 9221 Table 3 Pin description continued P3 0 to P3 1 1 0 8 bit microcontrollers with two clock 80C51 core Port 3 Port 3 is an 2 bit I O port with a user configurable output type During reset Port 3 latches are configured in the input only mode with the internal pull up disabled The operation of Port 3 pins as inputs and outputs depends upon the port configuration selected
44. he data sheet status 16 Definitions Short form specification The data in a short form specification is extracted from a full data sheet with the same type number and title For detailed information see the relevant data sheet or data handbook Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System IEC 60134 Stress above one or more of the limiting values may cause permanent damage to the device These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied Exposure to limiting values for extended periods may affect device reliability Application information Applications that are described herein for any of these products are for illustrative purposes only Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification 17 Disclaimers Life support These products are not designed for use in life support appliances devices or systems where malfunction of these products can reasonably be expected to result in personal injury Philips Semiconductors Contact information customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such app
45. ices from the damaging effects of excessive static charge Nonetheless it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum c Parameters are valid over operating temperature range unless otherwise specified All voltages are with respect to Vss unless otherwise noted 9397 750 14469 Koninklijke Philips Electronics N V 2004 All rights reserved Product data Rev 08 15 December 2004 35 of 46 Philips Semiconductors P89LPC920 921 922 9221 10 Static characteristics Table 8 DC electrical characteristics Vpop 2 4 V to 3 6 V unless otherwise specified Tamb 40 C to 85 C for industrial unless otherwise specified Parameter power supply current operating 8 bit microcontrollers with two clock 80C51 core 3 6 V 12 MHz 2 mA lDD oper 3 6 V 18 MHz 2 11 5 20 mA IDD idle power supply current Idle mode 3 6 V 12 MHz 2 3 25 5 mA 3 6 V 18 MHz 2 5 7 mA lpp PD power supply current Power down 3 6 V 2 55 80 uA mode voltage comparators powered down IDD TPD power supply current Total 3 6 V 2 1 5 uA Power down mode dVpp dt Vpop rise rate 2 mV us dVpp dt Vpop fall rate 50 mV us Vpor Power on reset detect voltage 0 2 V VRAM RAM keep alive voltage 1 5 V Vih HL negative going threshold voltage except SCL SDA 0 22Vbp 0 4Vpp
46. ing Data Pointers simply by incrementing the AUXR1 register without the possibility of inadvertently altering other bits in the register Koninklijke Philips Electronics N V 2004 All rights reserved Product data Rev 08 15 December 2004 31 of 46 Philips Semiconductors P89 LPC920 921 1922 9221 9397 750 14469 8 bit microcontrollers with two clock 80C51 core 8 24 Flash program memory 8 24 1 General description The P89LPC920 921 922 9221 Flash memory provides in circuit electrical erasure and programming The Flash can be read erased or written as bytes The Sector and Page Erase functions can erase any Flash sector 1 kB or page 64 bytes The Chip Erase operation will erase the entire program memory In System Programming and standard parallel programming are both available On chip erase and write timing generation contribute to a user friendly programming interface The P89LPC920 921 922 9221 Flash reliably stores memory contents even after 10 000 erase and program cycles The cell is designed to optimize the erase and programming mechanisms The P89LPC920 921 922 9221 uses Vpp as the supply voltage to perform the Program Erase algorithms 8 24 2 Features 8 24 3 e Parallel programming with industry standard commercial programmers e In Circuit serial Programming ICP with industry standard commercial programmers e IAP Lite allows individual and multiple bytes of code memory to be used for data
47. le or in part is prohibited without the prior written consent of the copyright owner The information presented in this document does not form part of any quotation or contract is believed to be accurate and reliable and may be changed without notice No liability will be accepted by the publisher for any consequence of its use Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights Date of release 15 December 2004 Document order number 9397 750 14469 8 bit microcontrollers with two clock 80C51 core 8 16 5 8 16 6 8 17 8 18 8 18 1 8 18 2 8 18 3 8 18 4 8 18 5 8 18 6 8 18 7 8 18 8 8 18 9 8 18 10 8 19 8 20 8 20 1 8 20 2 8 20 3 8 21 8 22 8 23 8 23 1 8 23 2 8 24 8 24 1 8 24 2 8 24 3 8 25 8 26 10 11 12 13 14 15 16 17 18 ModE G wie occa ted sewavbee danin iiia Ea 24 Timer overflow toggle output 24 Real Time clock system timer 24 UART oc cecacGeadetereeteed tones oe hie avg eat 24 ModE OS ascsatocteeh alana ata nett acta a EEN A ata 24 Mode Wives ecacsaee edad ea dreasa niemiin 25 Mode 2 erdira aiaia ee ake sae AEE 25 Mode 32 0 vscetvie eeyedie tiene Bean E ied 25 Baud rate generator and selection 25 Framing Error sacr k eee tees 25 Break detect c 2c c7ecrdente eoeaa beaade cos 26 Double buffering 0 00 0 000 26 Transmit interrupts with double buffering ena
48. lers with two clock 80C51 core Mode 1 10 bits are transmitted through TxD or received through RxD a start bit logical 0 8 data bits LSB first and a stop bit logical 1 When data is received the stop bit is stored in RB8 in Special Function Register SCON The baud rate is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator described in Section 8 18 5 Baud rate generator and selection Mode 2 11 bits are transmitted through TxD or received through RxD start bit logical 0 8 data bits LSB first a programmable 9t data bit and a stop bit logical 1 When data is transmitted the 9t data bit TB8 in SCON can be assigned the value of 0 or 1 Or for example the parity bit P in the PSW could be moved into TB8 When data is received the 9th data bit goes into RB8 in Special Function Register SCON while the stop bit is not saved The baud rate is programmable to either 4g or 1 2 of the CPU clock frequency as determined by the SMOD1 bit in PCON Mode 3 11 bits are transmitted through TxD or received through RxD a start bit logical 0 8 data bits LSB first a programmable 9t data bit and a stop bit logical 1 In fact Mode 3 is the same as Mode 2 in all respects except baud rate The baud rate in Mode 3 is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator described in Section 8 18 5
49. lication Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits standard cells and or software described or contained herein in order to improve design and or performance When the product is in full production status Production relevant changes will be communicated via a Customer Product Process Change Notification CPCN Philips Semiconductors assumes no responsibility or liability for the use of any of these products conveys no licence or title under any patent copyright or mask work right to these products and makes no representations or warranties that these products are free from patent copyright or mask work right infringement unless otherwise specified 18 Licenses a Purchase of Philips 12C components conveys a license 2 J under the Philips 12C patent to use the components in the F 12C system provided the system conforms to the 12C BUS specification defined by Philips This specification can be ordered using the code 9398 393 40011 For additional information please visit http www semiconductors philips com For sales office addresses send e mail to sales addresses www semiconductors philips com 9397 750 14469 Fax 31 40 27 24825 Koninklijke Philips Electronics N V 2004 All rights reserved Product data Rev 08 15 December 2004 45 of 46 Philips Semiconductors P89
50. mode in order to obtain fast switching times while in Power down mode The reason is that with the oscillator stopped the temporary strong pull up that normally occurs during switching on a quasi bidirectional port pin does not take place Comparators consume power in Power down and Idle modes as well as in the normal operating mode This fact should be taken into account when system power consumption is an issue To minimize power consumption the user can disable the comparators via PCONA 5 or put the device in Total Power down mode Keypad interrupt KBI The Keypad Interrupt function is intended primarily to allow a single interrupt to be generated when Port 0 is equal to or not equal to a certain pattern This function can be used for bus address recognition or keypad recognition The user can configure the port via SFRs for different tasks The Keypad Interrupt Mask Register KBMASk is used to define which input pins connected to Port 0 can trigger the interrupt The Keypad Pattern Register KBPATN is used to define a pattern that is compared to the value of Port 0 The Keypad Interrupt Flag KBIF in the Keypad Interrupt Control Register KBCON is set when the condition is matched while the Keypad Interrupt function is active An interrupt will be generated if enabled The PATN_SEL bit in the Keypad Interrupt Control Register KBCON is used to define equal or not equal for the comparison In order to use the Keypad Interrupt as an o
51. mory A user program simply calls the common entry point in the Boot ROM with appropriate parameters to accomplish the desired operation The Boot ROM include operations such as erase sector erase page program page CRC program security bit etc The Boot ROM occupies the program memory space at the top of the address space from FFOOH to FEFFH thereby not conflicting with the user program memory space Power on reset code execution The P89LPC920 921 922 9221 contains two special Flash elements the Boot Vector and the Boot Status Bit Following reset the P89LPC920 921 922 9221 examines the contents of the Boot Status Bit If the Boot Status Bit is set to zero power up execution starts at location OOOOH which is the normal start address of the user s application code When the Boot Status Bit is set to a one the contents of the Boot Vector is used as the high byte of the execution address and the low byte is set to OOH The factory default setting is 1FH for the P89LPC9221 and P89LPC922 and corresponds to the address 1FOOH for the default ISP boot loader The factory default setting is OFH for the P89LPC921 and corresponds to the address OFOOH for the default ISP boot loader The factory default setting for the LPC920 is 07H and corresponds to the address 0700H This boot loader is pre programmed at the factory into this address space and can be erased by the user Users who wish to use this loader should take precautions to avoid erasing the 1
52. nal reset option is selected Four interrupt priority levels Eight keypad interrupt inputs plus two additional external interrupt inputs Second data pointer Schmitt trigger port inputs Emulation support Koninklijke Philips Electronics N V 2004 All rights reserved Product data Rev 08 15 December 2004 2 of 46 Philips Semiconductors P89LPC920 921 922 9221 3 Ordering information 9397 750 14469 3 1 8 bit microcontrollers with two clock 80C51 core Table 1 Ordering information P89LPC920FDH TSSOP20 plastic thin shrink small outline package SOT360 1 20 leads body width 4 4 mm P89LPC921FDH TSSOP20 plastic thin shrink small outline package SOT360 1 20 leads body width 4 4 mm P89LPC922FDH TSSOP20 plastic thin shrink small outline package SOT360 1 20 leads body width 4 4 mm P89LPC922FN DIP20 plastic dual in line package 20 leads 300 mil SOT146 1 P89LPC9221FN DIP20 plastic dual in line package 20 leads 300 mil SOT146 1 P89LPC9221FDH TSSOP20 plastic thin shrink small outline package SOT360 1 20 leads body width 4 4 mm Ordering options Table 2 Part options P89LPC920FDH 2 kB 40 C to 85 C 0 MHz to 18 MHz P89LPC921FDH 4kB 40 C to 85 C 0 MHz to 18 MHz P89LPC922FDH 8 kB 40 C to 85 C 0 MHz to 18 MHz P89LPC922FN 8 kB 40 C to 85 C 0 MHz to 18 MHz P89LPC9221FN 8 kB 40 C to
53. nternal polling sequence determines which request is serviced This is called the arbitration ranking Note that the arbitration ranking is only used to resolve pending requests of the same priority level External interrupt inputs The P89LPC920 921 922 9221 has two external interrupt inputs as well as the Keypad Interrupt function The two interrupt inputs are identical to those present on the standard 80C51 microcontrollers These external interrupts can be programmed to be level triggered or edge triggered by setting or clearing bit IT1 or ITO in Register TCON In edge triggered mode if successive samples of the INTn pin show a HIGH in one cycle and a LOW in the next cycle the interrupt request flag IEn in TCON is set causing an interrupt request If an external interrupt is enabled when the P89LPC920 921 922 9221 is put into Power down or Idle mode the interrupt will cause the processor to wake up and resume operation Refer to Section 8 14 Power reduction modes for details Koninklijke Philips Electronics N V 2004 All rights reserved Product data Rev 08 15 December 2004 18 of 46 Philips Semiconductors P89 LPC920 921 1922 9221 8 bit microcontrollers with two clock 80C51 core RTCF ERTC RTCCON 1 WDOVF Fig 6 Interrupt sources interrupt enables and power down wake up sources IEO EX0 a D on EX1 EN EBO KBIF WAKE UP EKBI IF IN POWER DOWN EWDRT CMF2 CMF1 EG EA
54. o PGM_MTP at FFOOH Please see the P89LPC920 921 922 9221 User s Manual for additional details In Circuit Programming ICP In Circuit Programming is a method intended to allow commercial programmers to program and erase these devices without removing the microcontroller from the system The In Circuit Programming facility consists of a series of internal hardware resources to facilitate remote programming of the P89LPC920 921 922 9221 through a two wire serial interface Philips has made in circuit programming in an embedded application possible with a minimum of additional expense in components and circuit board area The ICP function uses five pins Vpp Vss P0 5 P0 4 and RST Only a small connector needs to be available to interface your application to an external programmer in order to use this feature User configuration bytes A number of user configurable features of the P89LPC920 921 922 9221 must be defined at power up and therefore cannot be set by the program after start of execution These features are configured through the use of the Flash byte UCFG1 Please see the P89LPC920 921 922 9221 User s Manual for additional details User sector security bytes There are two four eight User Sector Security Bytes each corresponding to one sector Please see the P89LPC920 921 922 9221 User s Manual for additional details Koninklijke Philips Electronics N V 2004 All rights reserved Product data Rev 08 15 December
55. ogic symbol CMPREF gt gt TxD lt RxD lt _ gt T0 _ gt SCL lt 4 INTO 4 gt SDA lt _ INTI lt RST CMP2 CIN2B gt CIN2A gt CIN1B gt CINIA gt PORT 0 PORT 1 CMP1 lt T lt gt XTAL2 lt P89LPC920 921 922 9221 PORT 3 XTALI gt 002aaa409 9397 750 14469 Koninklijke Philips Electronics N V 2004 All rights reserved Product data Rev 08 15 December 2004 8 of 46 Philips Semiconductors P89 LPC920 921 1922 9221 8 bit microcontrollers with two clock 80C51 core 7 Special function registers Remark Special Function Registers SFRs accesses are restricted in the following ways e User must not attempt to access any SFR locations not defined e Accesses to any defined SFR locations must be strictly for the functions for the SFRs e SFR bits labeled 0 or 1 can only be written and read as follows Unless otherwise specified must be written with 0 but can return any value when read even if it was written with 0 It is a reserved bit and may be used in future derivatives 0 must be written with 0 and will return a when read 1 must be written with 1 and will return a 1 when read 9397 750 14469 Koninklijke Philips Electronics N V 2004 All righ
56. ot Status Bit After programming the Flash the Boot Status Bit should be programmed to zero in order to allow execution of the user s application code beginning at address OOOOH In System Programming ISP In System Programming is performed without removing the microcontroller from the system The In System Programming facility consists of a series of internal hardware resources coupled with internal firmware to facilitate remote programming of the P89LPC920 921 922 9221 through the serial port This firmware is provided by Philips and embedded within each P89LPC920 921 922 9221 device The Philips In System Programming facility has made in system programming in an embedded application possible with a minimum of additional expense in components and circuit board area The ISP function uses five pins Vpp Vss TXD RXD and RST Only a small connector needs to be available to interface your application to an external circuit in order to use this feature Please see the P89LPC920 921 922 9221 User s Manual for additional details In Application Programming IAP Several In Application Programming IAP calls are available for use by an application program to permit selective erasing and programming of Flash sectors pages security bits configuration bytes and device identification All calls are made through a common interface PGM_MTP The programming functions are selected by setting up the microcontroller s registers before making a call t
57. own mode This is the same as Power down mode except that the brownout detection circuitry and the voltage comparators are also disabled to conserve additional power The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock and the RTC is enabled If the internal RC oscillator is used to clock the RTC during Power down there will be high power consumption Please use an external low frequency clock to achieve low power with the Real Time Clock running during Power down Reset The P1 5 RST pin can function as either an active LOW reset input or as a digital input P1 5 The RPE Reset Pin Enable bit in UCFG1 when set to 1 enables the external reset input function on P1 5 When cleared P1 5 may be used as an input pin Remark During a power up sequence the RPE selection is overridden and this pin will always function as a reset input An external circuit connected to this pin should not hold this pin LOW during a power on sequence as this will keep the device in reset After power up this input will function either as an external reset input or as a digital input as defined by the RPE bit Only a power up reset will temporarily override the selection defined by RPE bit Other sources of reset will not override the RPE bit Remark During a power cycle Vpp must fall below Vpor see Table 8 DC electrical characteristics on page 36 before power is reapplied in order to ensure a po
58. ps Semiconductors P89 LPC920 921 1922 9221 9397 750 14469 8 12 2 8 12 3 8 12 4 8 12 5 8 12 6 8 bit microcontrollers with two clock 80C51 core P1 2 SCL TO and P1 3 SDA INTO may only be configured to be either input only or open drain Quasi bidirectional output configuration Quasi bidirectional output type can be used as both an input and output without the need to reconfigure the port This is possible because when the port outputs a logic HIGH it is weakly driven allowing an external device to pull the pin LOW When the pin is driven LOW it is driven strongly and able to sink a fairly large current These features are somewhat similar to an open drain output except that there are three pull up transistors in the quasi bidirectional output that serve different purposes The P89LPC920 921 922 9221 is a 3 V device but the pins are 5 V tolerant In quasi bidirectional mode if a user applies 5 V on the pin there will be a current flowing from the pin to Vpp causing extra power consumption Therefore applying 5 V in quasi bidirectional mode is discouraged A quasi bidirectional port pin has a Schmitt triggered input that also has a glitch suppression circuit Open drain output configuration The open drain output configuration turns off all pull ups and only drives the pull down transistor of the port driver when the port latch contains a logic 0 To be used as a logic output a port configured in this manne
59. ps Semiconductors P89LPC920 921 1922 9221 8 bit microcontrollers with two clock 80C51 core Table 10 AC characteristics Vpp 3 0 V to 3 6 V unless otherwise specified Tamb 40 C to 85 C for industrial unless otherwise specified frcosc internal RC oscillator frequency trimmed to 1 7 189 7 557 7 189 7 557 MHz nominal f 7 3728 MHz at Tamb 25 C fwoosc internal Watchdog oscillator 320 520 320 520 kHz frequency nominal f 400 kHz fosc oscillator frequency 2 0 18 MHz teLcL clock cycle see Figure 13 55 ns fcLkP CLKLP active frequency 0 8 MHz Glitch filter glitch rejection P1 5 RST pin 50 50 ns signal acceptance P1 5 RST pin 125 125 ns glitch rejection any pin except 15 15 ns P1 5 RST signal acceptance any pin except 50 50 E ns P1 5 RST External clock tcHcx HIGH time see Figure 13 22 tetcL tctcx 22 ns cici LOW time see Figure 13 22 tcLcL tcHcx 22 ns CLCH rise time see Figure 13 5 5 ns tcHcL fall time see Figure 13 5 5 ns Shift register UART mode 0 tise serial port clock cycle time 16 tcc 888 ns tavxH output data set up to clock rising 13tcic 722 ns edge txHQX output data hold after clock rising toto 20 75 ns edge XHDX input data hold after clock rising edge 0 0 ns tovxH input data valid to clock rising edge 150 150 ns 1 Parameters are valid over operating temperature range
60. put is a zero Each comparator may be configured to cause an interrupt when the output value changes The overall connections to both comparators are shown in Figure 10 The comparators function to Vpp 2 4 V When each comparator is first enabled the comparator output and interrupt flag are not guaranteed to be stable for 10 microseconds The corresponding comparator interrupt should not be enabled during that time and the comparator interrupt flag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service When a comparator is disabled the comparator s output COx goes HIGH If the comparator output was LOW and then is disabled the resulting transition of the comparator output from a LOW to HIGH state will set the comparator flag CMFx This will cause an interrupt if the comparator interrupt is enabled The user should therefore disable the comparator interrupt prior to disabling the comparator Additionally the user should clear the comparator flag CMFx after disabling the comparator CP1 i Comparator 1 i OE1 P0 4 CIN1A i P0 3 CIN1B cot p EEN P0 5 CMPREF g VREF SS a i Change Detect p oN 1 Interrupt Change Detect CP2 EC Comparator 2 gt lt P0 2 CIN2A i P0 1 CIN2B or CMP2 P0 0 a co2 i i I vee 002aaa422 CN2 Fig 10 Comparator input and output connections
61. r must have an external pull up typically a resistor tied to Vpp An open drain port pin has a Schmitt triggered input that also has a glitch suppression circuit Input only configuration The input only port configuration has no output drivers It is a Schmitt triggered input that also has a glitch suppression circuit Push pull output configuration The push pull output configuration has the same pull down structure as both the open drain and the quasi bidirectional output modes but provides a continuous strong pull up when the port latch contains a logic 1 The push pull mode may be used when more source current is needed from a port output A push pull port pin has a Schmitt triggered input that also has a glitch suppression circuit The P89LPC9221 device has high source current on eight pins in push pull mode See Table 8 DC electrical characteristics Port 0 analog functions The P89LPC920 921 922 9221 incorporates two Analog Comparators In order to give the best analog function performance and to minimize power consumption pins that are being used for analog functions must have the digital outputs and digital inputs disabled Digital outputs are disabled by putting the port output into the Input Only high impedance mode as described in Section 8 12 4 Digital inputs on Port 0 may be disabled through the use of the PTOAD register bits 1 5 On any reset PTOAD1 5 defaults to 0 s to enable digital functions
62. riginal KBI function like in 87LPC76x series the user needs to set KBPATN OFFH and PATN_SEL 1 not equal then any key connected to Port 0 which is enabled by the KBMASK register will cause the hardware to set KBIF and generate an interrupt if it has been enabled The interrupt may be used to wake up the CPU from Idle or Power down modes This feature is particularly useful in handheld battery powered systems that need to carefully manage power consumption yet also need to be convenient to use In order to set the flag and cause an interrupt the pattern on Port 0 must be held longer than 6 CCLKs Koninklijke Philips Electronics N V 2004 All rights reserved Product data Rev 08 15 December 2004 30 of 46 Philips Semiconductors P89LPC920 921 922 9221 8 22 8 bit microcontrollers with two clock 80C51 core Watchdog timer The Watchdog timer causes a system reset when it underflows as a result of a failure to feed the timer prior to the timer reaching its terminal count It consists of a programmable 12 bit prescaler and an 8 bit down counter The down counter is decremented by a tap taken from the prescaler The clock source for the prescaler is either the PCLK or the nominal 400 kHz Watchdog oscillator The Watchdog timer can only be reset by a power on reset When the watchdog feature is disabled it can be used as an interval timer and may generate an interrupt Figure 11 shows the Watchdog timer in watchdog mod
63. storage and programmed under control of the end application e Internal fixed boot ROM containing low level In Application Programming IAP routines that can be called from the end application in addition to AP Lite e Default serial loader providing In System Programming ISP via the serial port located in upper end of user program memory e Boot vector allows user provided Flash loader code to reside anywhere in the Flash memory space providing flexibility to the user e Programming and erase over the full operating voltage range e Read Programming Erase using ISP IAP IAP Lite e Any flash program or erase operation in 2 ms e Programmable security for the code in the Flash for each sector e gt 100 000 typical erase program cycles for each byte e 10 year minimum data retention ISP and IAP capabilities of the P89LPC920 921 922 9221 Flash organization The P89LPC920 921 922 9221 program memory consists of two four eight 1 kB sectors Each sector can be further divided into 64 byte pages In addition to sector erase page erase and byte erase a 64 byte page register is included which allows from 1 to 64 bytes of a given page to be programmed at the same time substantially reducing overall programming time An In Application Programming IAP interface is provided to allow the end user s application to erase and reprogram the user code memory In addition erasing and reprogramming of user programmable bytes including UCFG1
64. th frequency range and RC oscillator options selected by user programmed Flash configuration bits The RC oscillator factory calibrated to 1 option allows operation without external oscillator components Oscillator options support frequencies from 20 kHz to the maximum operating frequency of 18 MHz The RC oscillator option is selectable and fine tunable E 2 4V to 3 6 V Vpp operating range I O pins are 5 V tolerant may be pulled up or driven to 5 5 V E High drive current 20 mA on eight I O pins on the P89LPC9221 P0 3 to PO 7 P1 4 P1 6 P1 7 PHILIPS Philips Semiconductors P89 LPC920 921 1922 9221 9397 750 14469 8 bit microcontrollers with two clock 80C51 core 2 2 Additional features 15 I O pins minimum Up to 18 I O pins while using on chip oscillator and reset options 20 pin TSSOP and DIP packages A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns for all instructions except multiply and divide when executing at 18 MHz This is six times the performance of the standard 80C51 running at the same clock frequency A lower clock frequency for the same performance results in power savings and reduced EMI In Application Programming of the Flash code memory This allows changing the code in a running application Serial Flash programming allows simple in circuit production coding Flash security bits prevent reading of sensitive application programs Watchdog timer with separate on
65. the Boot Status Bit and the Boot Vector are supported As shipped from the factory the upper 512 bytes of user code space contains a serial In System Programming ISP routine allowing for the device to be programmed in circuit through the serial port Koninklijke Philips Electronics N V 2004 All rights reserved Product data Rev 08 15 December 2004 32 of 46 Philips Semiconductors P89 LPC920 921 1922 9221 9397 750 14469 8 bit microcontrollers with two clock 80C51 core Flash programming and erasing There are three methods of erasing or programming of the Flash memory that may be used First the Flash may be programmed or erased in the end user application by calling low level routines through a common entry point Second the on chip ISP boot loader may be invoked This ISP boot loader will in turn call low level routines through the same common entry point that can be used by the end user application Third the Flash may be programmed or erased using the parallel method by using a commercially available EPROM programmer which supports this device This device does not provide for direct verification of code memory contents Instead this device provides a 32 bit CRC result on either a sector or the entire 2 kB 4 kB 8 kB of user code space Boot ROM When the microcontroller programs its own Flash memory all of the low level details are handled by code that is contained in a Boot ROM that is separate from the Flash me
66. tor can be used to save power when a high clock frequency is not needed 8 5 External clock input option In this configuration the processor clock is derived from an external source driving the XTAL1 P3 1 pin The rate may be from 0 Hz up to 12 MHz The XTAL2 P3 0 pin may be used as a standard port pin or a clock output When using an oscillator frequency above 12 MHz the reset input function of P1 5 must be enabled An external circuit is required to hold the device in reset at power up until Vpp has reached its specified level When system power is removed Vpp will fall below the minimum specified operating voltage When using an oscillator frequency above 12 MHz in some applications an external brownout detect circuit may be required to hold the device in reset when Vpp falls below the minimum specified operating voltage 9397 750 14469 Koninklijke Philips Electronics N V 2004 All rights reserved Product data Rev 08 15 December 2004 15 of 46 Philips Semiconductors P89 LPC920 921 1922 9221 9397 750 14469 8 bit microcontrollers with two clock 80C51 core XTAL1 High freq XTAL2 Med freq gt RTC E Low freq gt OSCCLK CCLK DIVM CPU RC OSCILLATOR 7 3728 MHz WATCHDOG gt OSCILLATOR 400 kHz PCLK TIMER 0 and BAUD RATE TIMER 1 FG GENERATOR UART 002aaa424 Fig 5 Block diagram of oscillator control is 4 Koninklijke Philips Electronics N
67. ts reserved Product data Rev 08 15 December 2004 9 of 46 p00z Jequiaceq GL 80 9H elep yoNpold 9t J0 OL 69tt L OSL L6E6 pansased S 4Su Ily 700 AN S91U01199 3 Sdillyd Oyf HULL Table 4 Special function registers indicates SFRs that are bit addressable Bit address E7 E6 E5 E4 E3 E2 E1 E0 ACC Accumulator EOH 00 00000000 AUXR1 Auxiliary function register A2H CLKLP EBRR ENT1 ENTO SRST 0 DPS ool 000000x0 Bit address F7 F6 F5 F4 F3 F2 F1 FO B B register FOH 00 00000000 BRGRO Baud rate generator rate BEH 00 00000000 LOW BRGR1 Baud rate generator rate BFH 00 00000000 HIGH BRGCON Baud rate generator control BDH SBRGS BRGEN 00 XXXXXX00 CMP1 Comparator 1 control register ACH CE1 CP1 CN1 OE1 CO1 CMF1 00l xx000000 CMP2 Comparator 2 control register ADH CE2 CP2 CN2 OE2 CoO2 CMF2 00l xx000000 DIVM CPU clock divide by M 95H 00 00000000 control DPTR Data pointer 2 bytes DPH Data pointer HIGH 83H 00 00000000 DPL Data pointer LOW 82H 00 00000000 FMADRH Program Flash address HIGH E7H 00 00000000 FMADRL_ Program Flash address LOW E6H 00 00000000 FMCON Program Flash control Read E4H BUSY z HVA HVE SV Ol 70 01110000 Program Flash control Write E4H FMCMD FMCMD FMCMD FMCMD FMCMD FMCMD FMCMD FMCMD 7 6 5 4 3 2 1 0 FMDATA Program Flash data E5H 00 00000000 I2ADR 12C slave address register DBH I2ADR 6 I2ADR 5 I
68. ued P1 0 to P1 7 I O 1 01 Port 1 Port 1 is an 8 bit I O port with a user configurable output type except for three pins as noted below During reset Port 1 latches are configured in the input only mode with the internal pull up disabled The operation of the configurable Port 1 pins as inputs and outputs depends upon the port configuration selected Each of the configurable port pins are programmed independently Refer to Section 8 12 1 Port configurations and Table 8 DC electrical characteristics for details P1 2 P1 3 are open drain when used as outputs P1 5 is input only All pins have Schmitt triggered inputs Port 1 also provides various special functions as described below 12 1 0 P1 0 Port 1 bit 0 TXD Transmitter output for the serial port 11 1 0 P1 1 Port 1 bit 1 RXD Receiver input for the serial port 10 1 0 P1 2 Port 1 bit 2 open drain when used as output 1 0 TO Timer counter 0 external count input or overflow output open drain when used as output 1 0 SCL I C serial clock input output 1 0 P1 3 Port 1 bit 3 open drain when used as output INTO External interrupt 0 input 1 0 SDA I C serial data input output 1 0 P1 4 Port 1 bit 4 High current source P89LPC9221 INT1 External interrupt 1 input P1 5 Port 1 bit 5 input only RST External R
69. veform 9397 750 14469 Koninklijke Philips Electronics N V 2004 All rights reserved 40 of 46 Product data Rev 08 15 December 2004 Philips Semiconductors P89LPC920 921 1922 9221 8 bit microcontrollers with two clock 80C51 core 12 Comparator electrical characteristics Table 12 Comparator electrical characteristics Vpop 2 4 V to 3 6 V unless otherwise specified Tamb 40 C to 85 C for industrial unless otherwise specified Vio offset voltage comparator inputs 20 mV Vor common mode range comparator inputs 0 Vpp 0 3 V CMRR common mode rejection ratio m 50 dB response time 250 500 ns comparator enable to output valid 10 us lit input leakage current comparator 0 lt Vin lt Vpop 10 uA 1 This parameter is characterized but not tested in production 9397 750 14469 Koninklijke Philips Electronics N V 2004 All rights reserved Product data Rev 08 15 December 2004 41 of 46 Philips Semiconductors P89LPC920 921 922 9221 8 bit microcontrollers with two clock 80C51 core 13 Package outline TSSOP20 plastic thin shrink small outline package 20 leads body width 4 4 mm SO
70. wer on reset Reset can be triggered from the following sources Koninklijke Philips Electronics N V 2004 All rights reserved Product data Rev 08 15 December 2004 22 of 46 Philips Semiconductors P89 LPC920 921 1922 9221 9397 750 14469 8 15 1 8 16 8 16 1 8 16 2 8 bit microcontrollers with two clock 80C51 core e External reset pin during power up or if user configured via UCFG1 This option must be used for an oscillator frequency above 12 MHz e Power on detect e Brownout detect e Watchdog Timer e Software reset e UART break character detect reset For every reset source there is a flag in the Reset Register RSTSRC The user can read this register to determine the most recent reset source These flag bits can be cleared in software by writing a 0 to the corresponding bit More than one flag bit may be set e During a power on reset both POF and BOF are set but the other flag bits are cleared e For any other reset previously set flag bits that have not been cleared will remain set Reset vector Following reset the P89LPC920 921 922 9221 will fetch instructions from either address 0000h or the Boot address The Boot address is formed by using the Boot Vector as the high byte of the address and the low byte of the address 00h The Boot address will be used if a UART break reset occurs or the non volatile Boot Status bit BOOTSTAT 0 1 or the device is forced into

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