ad500 manual
Contents
1. 20 3 4 Continuous Convert Mode 3 6 Starting Conversions 346 Reading the A D Data 3 7 Terminating Conversions 3 7 Strobed Convert Mode 2225255 38 A D Converter Data Format ra 3 9 Analog input Channel Selection 3 9 Gain Selection ee aa e o een 3 10 Programming the Digital Ports 3 12 Selecting the Direction of Port C 3 12 Outputting Data on Port B and Port C 3 13 inputting Data from Port 3 14 interrupt Considerations E 3 14 Chapter 4 Theory of Rug E 4 1 Multiplexer eo 9 9 4 n v a pg 4 2 4 2 Control 4 2 Operation 4 3 Programmable Gain Amplifier Pod aue a 4 3 Description 99 o9 e s oe n s e n e Rn 4 3 Control ee ee ae da 4 3 Operation 9 e e 9 2929 4 3 Reference YE OE Uo Moa nc 4 4 A D Converter eee eere eere err wes 4 4 Description2. mau stata AA um i a gt i START e CONVEAT MEER och Fig 4 5 Conversion Timing Single Convert and Strobed Convert Modes Compliments of Maxim Integrated Products Inc copyright 1985 4 5 As discussed in Chapter 3 the START CONVERT signal should remain high until the zero crossing detection occurs and the A D result has been strobed into the PPI This insures that the START CONVERT signal will be recognized by the A D converter The conversion rate in the Single Convert and Strobed Convert Modes of operation will be proportional to the magnitude of the input signal The conversion rate will range from a maximum of 15 Hz for a volt input to a minimum of 7 5 Hz for a full scale input of 5 volts when switch 51 is set for 7 5 60 Hz to 30 Hz when switch S1 is set for 30 To determine the actual conversion speed of the AD500 in the Single Convert and Strobed Convert modes of operation you can monitor the ICL7109 STATUS output signal This signal is available at pin 2 of U3 and a low to high transition will indicate the beginning of each conversion cycle The timing diagram in Figure 4 5 illustrates the activity of the STATUS output signal in the Single Convert and Strobed Convert Modes Operation Figure 4 6 shows a block diagram of the analog section of the ICL7109 A D converter Fig 4 6 ICL7109 Analog Section
3. o UN ee 15 700 4 4 Control 00000 we we ww we we wwe eee 4 4 Operation XII 4 6 Auto Zero Phase 4 7 Signal Integrate Phase 4 7 De Integrate Phase eee ee eee o ewe 4 7 Zero Integrator Phase ee ee eee eee 4 7 Integrating Converter Features 4 8 Chapter 5 Calibration 5 1 Equipment Required oi are eae E Tus ds mire 5 2 Calibration Procedure ees 0 0 0 5 2 Offset Adjustment 5 2 Full Scale Adjustment o ee ee o 5 3 Appendix A Specifications ADSOO Specifications taU acce eire rie Ww S wie fe el 19 SE ene A 1 8255 Specifications 2 A 3 Harris HI 508A Specifications 4 4 4 4 4 5 A 6 Burr Brown PGA102 Specifications eene 8 Appendix Connector Figure B 1 AD500 Connector Pin Assignment o B 1 Table B 1 AD500 Connector Type o o B 1 Appendix C References Appendix D Warranty Illustrations Page 2 1 AD500 Component Locations rn 2 2 2 2 AD500 I O Port Address 2 3 2 3 Interrupt Disable Jumper Position 2 4
4. AD500 User s Manual Real Time Devices 1509001 and AS9100 Certified AD500 User s Manual A User s Guide to the AD500 12 Bit Data Acquisition System Time Devices Inc P O Box 906 State College PA 16804 Second Printing March 1988 Copyright c 1988 All rights reserved Real Time Devices Inc Printed in U S A Contents Page Mlustrations gt 200000 rn ni Tables obo E t m RUN EC AUG Ute ut aat Chapter 1 Introduction lt lt o 1 1 Chapter 2 installation m 2 1 Jumper Settings e roe use weh 283 Base Address Selection Connector 2 2 3 Interrupt Channel Selection Connector P3 2 4 Selecting Conversion Speed Switch S1 e 2 4 Board installation rs 2 5 External Connections Connector P4 Se e S pe LR 2 5 Calibration 2 6 Chapter 3 Programming the 500 e 3 1 Using the ADSOO Application Software 3 1 Programming the 8255 PPI 3 2 Initializing the 3 2 Interfacing With the A D 3 3 Initializing the A D Converter 3 4 Single Convert Mode
5. Analog Analog Out put Input Connector P4 Fig 3 11 Gain Control Bit Assignment These bits are controlled using the Bit Set Reset feature of the PPI To change PGA gain first reset both PCO and PCI then set either PCO or 1 if necessary by writing data to the Control Register as indicated in Tables 3 3 and 3 4 Table 3 3 Gain Control Table 3 4 Set Reset of Bit Settings PCO and 1 SET RESET your application requires gain changes when the AD500 is in the continuous or strobed convert modes the new gain should be selected before reading the MSB of the most recent A D converter value The new gain will be effective for all future A D conversions This will prevent PPI Control Word Data 3 11 gain change during the conversion process which may result in an erroneous A D reading This procedure is illustrated in the DEMO software on he Program Disk PROGRAMMING THE DIGITAL I O PORTS The seven bits of digital 1 O available at the AD500 P4 connector organized as shown in Figure 3 12 5 2 ET PC6 PC7 Fig 3 12 0500 Digital 1 0 The group of five lines PB3 PB7 are connected to Port B of the PPI and are programmed as all outputs on the AD500 The remaining two lines PC6 and PC 7 are connected to Port C of the and may be programmed as both inputs or both outputs In addition each of the Port C bits when programmed as outputs may be indiv
6. C c IN NOTES 1 Gam maccuracy is percent error between the actual and idesi gain selected It may be esterratly adjusted to zero for gans of 10 and 100 2 Offset voltage can be adjusted tor any one crarne Adjustment attecis temperature antt by approximately 20 34V C tor each 100uV offset TYPICAL PERFORMANCE CURVES Ta 25 C 1 15VDC unless otherwise noted SMALL SIGNAL STEP RESPONSE Output mv Teme Unec INPUT VOLTAGE NOISE VS FREQUENCY Voltage Norse nV y Hz 1 10 100 1 10 1002 1 frequency H2 SMALL SIGNAL FREQUENCY RESPONSE SLUT I IE NN 10 100 Tk 10 Frequency GAIN ERROR VS TEMPERATURE Error Temperature LARGE SIGNAL STEP RESPONSE Output tv INPUT CURRENT NOISE vS FREQUENCY Current Noise pA Hr 1 10 100 ve 1008 Frequency LAAGE SIGNAL FREQUENCY RESPONSE AI Input Crosstatk 88 10 100 105 1008 1 Frequency 42 NONLINEARITY VS TEMPERATURE 40 0 40 80 120 Temperature A 9 Overload Recovery Time usec OVEALOAN RECOVERY VS INPUT OVERLOAD Appendix Connector AIN8 AIN Analog Gnd AIN3 AIN1 SO Lun amp 11 7 15 7 16 PBS 17 19 12 Vol
7. Port C data C AND amp HCO Mask PC6 and PC7 Note that the data read from the Port C address was AND ed with the bit pattern 1100 0000 to mask PC and PC7 Additional examples of reading and writing data with the PPI digital 1 O ports are given in the DEMO software on the Program Disk INTERRUPT CONSIDERATIONS The interrupt generated by the AD500 PPI may be jumpered to any of the PC interrupt channels 2 7 The channel selection is made by jumpering pins on the AD500 P3 connector as explained in the interrupt Channel Selection description in Chapter 2 An interrupt occurs each time the A D converter writes a byte of data into the PPI Port A Therefore two interrupts are generated for each conversion one for the MSB data and one for the LSB data The timing of the interrupt signal generated by the is shown in the Timing Diagrams in Figures 3 6 3 7 and 3 8 Before using the PPI interrupt it must first be enabled by writing a 1 to the PPI Port A interrupt Enable bit INTE A This is done by setting bit PC4 using the Port C Bit Set Reset function of the PPI Table 3 5 lists the data that must be written to the PPI Control Word to set or reset the INTE A mask bit Table 3 5 Set Reset of INTE A INTE A Control Word Data Set X 09 Reset X 08 The INTE A mask bit is disabled during power up reset and whenever the Control Word is written to when changing the PPI mode Before you attempt to us
8. 508 5 0 C lo 75 C 20 Storage Temperature Range 65 C to 150 C Derate 12 8 mW C above 75 C ELECTRICAL CHARACTERISTICS Suppiies 15 V 15 V Logic Level High 40 V VAL Logic Level Low 08 V uniess otherwise specified TRUTH TABLE 508 v nA nA nA nA A A nA oF 009 wend ter Dash 0 Leshoyo curent net watag 06 ts Mirco ng s yew Functenet appe we due gray el pre deum ry of vue cordiam 2 qu a loue tens 10096 amp he PERICO Met ww 5 Anting Overeoego 133 V Performance Characteristics and Test Circuits Uniess Otherwise Specified TA 25 C VSupply 15 4V VAL 08V TEST CIRCUIT NO 1 ON RESISTANCE vs ANALOG INPUT VOLTAGE on Rewnence Reterred to RESISTANCE vs INPUT SIGNAL LEVEL SUPPLY VOLTAGE NORMALIZED ON RESISTANCE vs SUPPLY VOLTAGE ym suson vean TEST CIRCUIT TEST CIRCUIT NO 4 WheSeUIPEeOnks por channel 910 V 10 V and 10 V 10 V Two messurements per device tor 10 V 10 V and 10 V 10 V ANALOG INPUT OVERVOLTAGE CHARACTERISTI
9. The new channel will be in effect for all future A D conversions until the channel is changed again This will prevent the input channel from changing during the conversion process which may result in an erroneous A D reading This procedure is illustrated in the DEMO software on the Program Disk After a different input channel is selected a minimum of 5 microseconds of delay is required before initiating a conversion to allow the analog input to the A D converter to stabilize This is not a consideration when programming from high level languages such as BASIC FORTRAN or Pascal However if your application program will be written in a very fast language such as assembler or FORTH you will need to allow for a delay after changing channels When using any of the 5 available PPI Port B digital output bits PB3 PB7 you may want to preserve their logic states when changing the input channel This can be done by first reading the Port data then AND ing its contents with X F8 This will reset the 3 least significant bits Next OR this result with the data needed to select the analog channel desired from Table 3 2 and write this value back to Port B This ensures that the 5 most significant bits of Port B will remain stable when changing the input channel This procedure is illustrated in the DEMO software GAIN SELECTION The programmable gain amplifier is controlled by bits PCO and PCI of the PPI as shown in Figure 3 11
10. Bit 7 6 5 4 3 2 10 Control Word Set Select Bit PC2 t Fig 3 3 Control Word Data to Set START CONVERT Once the START CONVERT signal is set conversion of the analog input begins When the conversion is completed the A D converter will strobe the most significant byte MSB of data into Port A of the PPI When this occurs the PPI input Buffer Full signal PC5 will be set The status of the IBF signal is checked by reading the PPI Status Word as shown in Figure 3 4 Bit 7 6 5 4 3 2 1 0 x xjie xj Status Word Fig 3 4 PPI Status Word IBF Indication Remember to mask off all but bit 5 of the status word if necessary when checking the IBF signal Once the IBF signal is set reset the START CONVERT signal as shown in Figure 3 5 Bt 7 6 5 4 3 2 1 0 fo i oTo PPI Control Word Select Bit PC2 Reset Bit Figure 3 5 Control Word Data to Reset START CONVERT The MSB of data is now read from the AD500 by inputting the contents of the PPI Port A using the I O address defined in Table 3 1 After the MSB of data is read the IBF signal will go low until the A D converter automatically transfers the least significant byte LSB of data to the PPI Port A When the IBF Signal is again set the LSB of data can now be input by reading the contents of the PPI Port A a second time The timing diagram in Figure 3 6 illustrates
11. Compliments of Maxim Integrated Products Inc copyright 1985 Each measurement cycle is divided into four phases Auto Zero AZ Signal Integrate INT De integrate DE Zero Integrator 21 The timing for these four phases is shown in Figure 4 4 or 4 5 above depending of the AD500 conversion mode selected 4 6 Auto Zero Phase The buffer and the integrator inputs are disconnected from input high and input low and connected to analog COMMON The reference capacitor is charged to the reference voltage A feedback loop is closed around the system to charge the auto zero capacitor Caz to compensate for offset voltage in the buffer amplifier integrator and comparator Since the comparator is included in the loop the A Z accuracy is limited only by the noise of the system The of set referred to the input is less than 10 microvolts Signal Integrate Phase The buffer and integrator inputs are removed from COMMON and connected to input high and input low The auto zero loop is opened The auto zero capacitor is placed in series in the loop to provide an equal and opposite compensating offset voltage The differential voltage between input high and input low is integrated for a fixed time of 2048 clock periods At the end of this phase the polarity of the integrated signal is determined De Integrate Phase The reference voltage is applied to the buffer and integrator inputs Circuitry within the ch
12. a single A D conversion is performed each time the START CONVERT signal is pulsed high and low The length of each conversion cycle is proportional to the amplitude of the analog input signal Continuous Convert Mode Conversions are initiated automatically in this mode The START CONVERT signal is pulsed high and remains high for as long as conversions are desired Conversion cycles are the same in length and are performed at a consistent rate Strobed Convert Mode This mode of operation allows conversions to be performed continuously at a rate proportional to the analog input signal amplitude The START CONVERT signal is repeatedly pulsed high and low to initiate each conversion Your AN500 is switch selectable to convert at a minimum rate of either 7 5 Hz or 30 Hz Refer to Chapter 2 for details on selecting the conversion speed Regardless of the configuration of your AD500 or the mode used perform A D conversions the data for each conversion is read back through the PPI in two 8 bit transfers consisting first of a most significant byte MSB then a least significant byte LSB These uansfers are initiated automatically by the A D converter after each conversion is finished and depend upon a sequence of handshaking signals between the and A D converter For this reason you should structure your application software so that two bytes of data are always read from the PPI after each conversion is completed Whene
13. 3 1 AD500 PPI Interface Configuration 3 2 3 2 AD500 PPI Control Word Initialization 3 3 3 3 Control Word Data to Set START CONVERT Sr 2 2 is 3 5 3 4 PPI Status Word IBF 3 5 3 5 Control Word Data to Reset START 3 5 3 6 0500 Single Convert Mode Timing 3 6 3 7 500 Continuous Convert Mode Timing Diagram Segre 7 3 8 500 Strobed Convert Mode Timing 3 8 3 9 ADSOO A D Converter Data Byte Format 3 9 3 10 MUX Channel Selection Bit Assignment 3 10 3 11 PGA Gain Control Bit Assignment 3 1 3 12 ADSOO Digital 3 12 3 13 Selecting Port C Direction e 3 13 3 14 Set Reset of PC6 and 7 NAAA 3 14 4 1 AD500 Analog Circuitry Block Diagram ea 4 4 2 HI 508A Functional Block Diagram 4 3 PGA102 Functional Block Diagram 4 4 4 4 Conversion Timing Continuous Convert ia od 4 5 4 5 Conversion Timing Single Convert and Strobed Convert Mode A e 4 5 4 6 ICL7109 Analog 4 6 4 7 integrator Output for Overrange Input 4 7 4 8 Normal Mo
14. 7 5 Hz 500 Chapter 5 Calibration The AD500 is factory calibrated to maximize its performance over all three gain ranges The following procedure is provided to allow you to quickly verify the performance of your AD500 This should be done approximately every six months or whenever inaccurate readings are suspected You may want to recalibrate your AD500 if your application will require the use of only one or two gains or you will be using all positive or all negative input voltages Also because the AD500 is factory calibrated for a 7 5 Hz conversion rate you may need to recalibrate your board if you select a 30 Hz rate using switch S1 5 1 EQUIPMENT REQUIRED The following equipment is required for calibration Precision voltage source 0 to 5 volts Digital Volt Meter DVM 5 1 2 digit 4 Jumper wire A voltage source may be assembled using a 9 volt battery and precision 10 turn trimming potentiometer as shown in the following circuit Figure 5 1 Volts V 0 to Y 6 Volts Fig 5 1 Adjustable Voltage Source CALIBRATION PROCEDURE Calibration is performed with a properly configured AD500 installed in the PC Apply power to the computer and allow the AD500 circuitry to stabilize for 15 minutes Connections will need to be made to some of the analog inputs at the P4 connector see Figure B 1 in Appendix B There are only two adjustments necessary to completely cali
15. DOC This documentation may be printed using the DOS TYPE command or any word processor which utilizes standard text document files 3 1 PROGRAMMING THE 8255 PPI Although the software included with your 0500 will satisfy many of your application requirements it may be necessary for you to become more familiar with the details of controlling the PPI Figure 3 1 illustrates how the I O ports are interfaced with the other components of the 0500 PB3 PB7 5 PC6 PC7 Y 5 amp AIN1 5 AIN8 E Fig 3 1 0500 PPI Interface Configuration The PPI contains four registers which are used to communicate with its three 8 bit 1 O ports see Table 3 1 These registers are located at the 1 addresses determined by the base address you selected in Chapter 2 however all the BASICA examples presented use a base address of X 200 Table 3 1 ADSOO PPI internal Register Definition 8255 PPI 0500 Base Address Function Function Port A Read Read Data From A D Port B Write Select Analog Input Write Digital Status Word Read Read A D Status Port C Read Port C Digital Input Write Mode to Control Word Configure AD500 Port C Bit Set Reset Write A D Gain Control Port C Digital Output INITIALIZING THE PPI Before the PPI can be used to control the components it interfaces with its operating modes must first be initialized This is required only once by the software after
16. Mode with gain of 1 and display the conversion results The Program Disk contains a routine that can be used while performing the full scale adjustment Apply the output of the voltage source between analog input AIN1 P4 6 and analog ground P4 1 Use the DVM and adjust the voltage source so that a full scale voltage minus 1 LSB is applied at the P4 connector Table 5 1 lists the voltages that correspond to this input for a 12 bit A D converter for gains of 1 10 and 100 The A D converter results for these input voltages and gain settings should flicker between all ones X FFF and X FFE Adjust trimpot TR until the values 4095 and 4094 are displayed Also listed in Table 5 1 are the ideal voltages that correspond to each bit weight of a 12 bit A D converter Refer to the analog input and A D specifications for the 0500 in Appendix A when checking the performance of your AD500 with these input voltages Table 5 1 12 Bit A D Couverter Weights A D Bit Weight Ideal Input Voltage mV 4095 5 14 LSB 2048 1024 512 15 6250 1 5625 7 8125 0 7813 3 9063 0 3906 19 5313 1 9531 0 1953 9 7656 0 9766 0 0977 4 8828 0 4883 0 0488 2 4414 0 2441 0 0244 1 2207 0 1221 0 0122 Appendix A Specifications AD500 SPECIFICATIONS Interface IBM PC XT AT compatible jumper selectable base address 1 O mapped hex 200 300 240 340 280 380 2 0 3CO Jumper selectable inter
17. conversions are desired The START CONVERT signal is set by writing the data shown in Figure 3 3 to the PPI Control Word Each time a conversion is completed the A D converter strobes the MSB of data into Port A of the PPI The PPI Input Buffer Full IBF signal will indicate when this data is available to be read from Port A The status of the IBF signal is checked by reading the PPI Status Word as shown in Figure 3 4 3 6 Reading the A D Data After the MSB of data is read from the PPI Por A see Table 3 1 the IBF signal will then indicate when the LSB of A D data is available Once the LSB of data is read the A D converter will automatically strobe the MSB of the next conversion result into the PPI New data will not be strobed into the PPI until both an MSB and LSB are read therefore the PPI data that is read will always be of the first conversion performed after the last PPI read operation Terminating Conversions When the Continuous Convert Mode is to be terminated the START CONVERT signal should be reset after detecting the IBF signal for the MSB of the last A D conversion desired The START CONVERT signal is reset by writing the data shown in Figure 3 5 to the PPI Control Word The timing diagram in Figure 3 7 iliustrates the handshaking signals required to perform A D conversions and read the results in the Continuous Convert Mode START pi ff CONVERT 7 m LSB A D Data Hp it Strobe ke
18. to the A D converter which is selected with bits PBO PB2 does not change when writing data to digital lines PB3 PB7 you will need to preserve the bit pattern on PBO PB2 when writing to Port B This can be done by first reading the Port B data then AND ing its contents with X 07 This will reset the 5 most significant bits while maintaining the bit pattern on PBO PB2 If you wish to preserve any of the other bits of Port B add their bit weights to the value X 07 when AND ing the Port data Next this result with the data you wish to output on PB3 PB7 after it has been properly justified to correspond to the correct Port B bit positions Finally this value should be written back to the Port B register This procedure is illustrated in the DEMO software The two bits of Port C are programmed individually using the Bit Set Reset function of the PPI Figure 3 14 lists the data that must be written to the Control Word to set or reset PC6 and PC7 3 13 Bit 7 6 5 4 3 2 1 0 FPI Control Word d Bit Set 1 Set Reset O Reset Bit Select 110 PC6 111 PC7 ES X OE Fig 3 14 Set Reset of PC6 and PC7 Control Word Data inputting Data from Port C Data is read from Port C by reading the PPI Port C register Its address was defined in Table 3 1 The following BASICA INP statements illustrate how the Port C data is input C INP amp H202 C lt
19. where the analog inputs originate from separately powered circuitry The HI 508A is fabricated with 44 volt dielectrically isolated CMOS technology Control As shown in the HI 508A Functional Block Diagram Figure 4 2 the multiplexer is controlled using three of the 5 Port B 1 O signals Details of controlling the channel selection were explained in Chapter 3 AINI A1N2 MIO 1 8 CLAMP ISOLATION INPUT PROTECTION 5 Fig 4 2 508 Functional Block Diagram Compliments of Harris Semiconductor copyright 1986 Operation The portions of the Harris data sheet for the HI 508A which contain the specifications of concern to your application are reprinted in Appendix A Specifications PROGRAMMABLE GAIN AMPLIFIER Description The Burr Brown PGA102 is a precision digitally programmable gain amplifier One of three gains 1 10 or 100 can be software selected High performance thin film resistors with excellent temperature tracking assure low gain drift and high stability The high accuracy is very beneficial in test equipment and instrumentation applications where programmable or fixed gain is required Control As shown in the PGA102 Functional Block Diagram Figure 4 3 the PGA is controlled using two of the PPI s Port signals Details of controlling the gain setting were explained in Chapter 3 Operation The por
20. 20 usec max PPI IBF 4 Farm MSB read LSB rea MSB read LSB from PPI from PPI from PPI read from PPI INTR s Last 1 Conversion k Cycle Conversior gt Fig 3 7 AD500 Continuous Convert Mode Timing Diagram The following programming model summarizes the sequence of events required to perform conversions in the Continuous Convert Mode Set START CONVERT Check IBF until set Read A D MSB data Repeat to read Check IBF until set each conversion Read A D LSB data Check IBF until set Reset START CONVERT Read A D MSB data Used to read Check IBF until set last conversion Read A D LSB data 3 7 A sample BASICA program for using the AD500 in the Continuous Convert Mode is contained on the Program Disk Strobed Convert Mode The Strobed Convert Mode will perform conversions continuously at a rate proportional to the analog input voltage This is done by taking advantage of a unique feature of the ICL7109 A D converter By pulsing the START CONVERT signal low then high after a conversion is completed the speed of the conversion cycle will be optimized This allows another conversion to start sooner Details on the operation of the ICL7109 A D converter are given in Chapter 4 Theory of Operation This mode is actually a series of single conversions similar to the those performed in the Single Convert Mode First the START CONVERT signal must be set to initiate a conversion This is done by w
21. All replaced parts and products become the property of REAL TIME DEVICES THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY PRODUCTS WHICH HAVE BEEN DAMAGED AS A RESULT OF ACCIDENT MISUSE ABUSE such as use of incorrect input voltages improper or insufficient ventilation failure to follow the operating instructions that are provided by REAL TIME DEVICES acts of God or other contingencies beyond the contro of REAL TIME DEVICES OR AS A RESULT OF SERVICE OR MODIFICATION BY ANYONE OTHER THAN REAL TIME DEVICES EXCEPT AS XPRESSLY SET FORTH ABOVE NO OTHER WARRANTIES ARE EXPRESSED OR IMPLIED INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE AND REAL TIME DEVICES EXPRESSLY DISCLAIMS ALL WARRANTIES NOT STATED HEREIN ALL IMPLIED WARRANTIES INCLUDING IMPLIED WARRANTIES FOR MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE LIMITED TO THE DURATION OF THIS WARRANTY IN THE EVENT THE PRODUCT IS NOT FREE FROM DEFECTS AS WARRANTED ABOVE THE PURCHASER S SOLE REMEDY SHALL REPAIR OR REPLACEMENT AS PROVIDED ABOVE UNDER NO CIRCUMSTANCES WILL REAL TIME DEVICES LIABLE TO THE PURCHASER OR ANY USER FOR ANY DAMAGES INCLUDING ANY INCIDENTAL OR CONSEQUENTIAL DAMAGES EXPENSES LOST PROFITS LOST SAVINGS OR OTHER DAMAGES ARISING OUT OF THE USE OF OR INABLILITY TO USE THE PRODUCT SOME STATES DO ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR CO
22. CS TEST CIRCUIT NO 6 ON CHANNEL CURRENT vs VOLTAGE Burr Brown 102 Programmable Gain Amplifier PIN CONFIGURATION x10 SELECT Vec x100 SELECT Vour LOGIC THRESHOLD 3 NC COMMON FORCE 4 Ve COMMON SENSE 5 OFFSET ADJUST V xt 8 OFFSET AQJYST Vos 30x10 7 GAIN ADJ x10 0 GAIN ADJ x100 3 0100 NO INTERNAL CONNECTION SPECIFICATIONS ELECTRICAL At 25 C 15 0 uniess otherwise specihed 260 10 100 v3 Temperature G 1 G 10 G 100 20 6 G x 10 6 100 INPUT VOLTAGE 10 G 100 1 G 10 G 100 25 lt z 18V 10 100 vs Temperature vs Supply Voltage INPUT NOISE Voltage Noise fe 0142 to 10Hz uN G 10 uN G 100 BV voltage Density fo 142 1 AW y Hz G 10 6 100 AVI Mz lo 1092 1 nw Ha G 10 6 100 avi Ma Current Noise fe 0 142 to 10Mz Current Norse Density fo tz DAV Hz fo 1092 pas fo 100M2 pas VA fo pa TEMPERATURE RANGE Overanng Storage Therma Resistance um IO Ta
23. ING CONVERSION SPEED SWITCH S1 Your AD500 will perform A D conversions at either a 7 5 Hz or 30 Hz rate A 7 5 Hz rate provides maximum rejection of 60 Hz line noise while a 30 Hz rate will allov maximum speed of conversions Le To select 7 5 Hz rate all four positions of switch SI must towards the bottom of the switch labeled 7 5 see Figure 2 1 A 30 Hz rate is selected by sliding all four switch positions towards the top of the switch labeled 30 The conversion speed must be selected before the board is installed in the computer the switch setting should not be changed while the AD500 is operating Your board is factory calibrated and configured for the 7 5 Hz rate If you will be using a 30 Hz rate you may need to recalibrate the ADSOO Refer to Chapter 5 Calibration for details on calibrating the A D converter BOARD INSTALLATION After selecting the base address and interrupt capability the AD500 may be installed inside the computer 1 TURN OFF THE POWER TO YOUR COMPUTER FIRST Refer to the owner s manual for your computer and remove the top cover 2 Select the expansion slot you wish to use and remove the corresponding blank bracket from the rear panel of the computer 3 Close both ejector latches on the ADSOO P4 I O connecter and orient the board inside the computer so that the connector protrudes through the rear of the computer and the card edge connector lines up with the selected e
24. NSUMER PRODUCTS AND SOME STATES DO NOT ALLOW LIMITATIONS ON HOW LONG AN IMPLIED WARRANTY LASTS SO THE ABOVE LIMITATIONS OR EXCLUSIONS MAY NOT APPLY TO YOU THIS WARRANTY GIVES YOU SPECIFIC LEGAL RIGHTS AND YOU MAY ALSO HAVE OTHER RIGHTS WHICH VARY FROM STATE TO STATE Real Time Devices Inc P O BOX 906 STATE COLLEGE PENNSYLVANIA 16804 814 234 8087 TELEX 4948141 SEDACOG
25. The conversion speed of the A D converter must also be selected with the switch Before installing the board into your computer the jumper selections and switch settings must be made All connections to external signals are made through one 40 pin 1 0 connector which can be accessed through the rear the computer after the board is installed U3 TRI P2 Fig 2 1 TR2 0500 12 Bit Data i a b D P3 0500 Component Locations 2 2 JUMPER SETTINGS Base Address Selection Connector P2 To select the board s base 1 O address the jumper on the connector labeled P2 must be positioned to correspond to the address desired The jumper should be placed horizontally across the pair of header pins beside the base address you select see Figure 2 1 The base addresses labeled beside connector P2 are hexadecimal values When choosing a base address be careful not to use one that will cause contention with another peripheral The AD500 occupies 16 addresses beginning with the base address selected however only four addresses are actually used Chapter 3 Programming the AD500 explains the function of these four addresses Figure 2 2 shows how the PC s 1 0 port address bits are decoded by the AD500 Address Bit X Don t Care 10 O R d U L X 1 o x x aijao Selected Base Address Selected BIATIAG rora poj
26. and 100 However if your application will require only one or two gain settings you may wish to recalibrate your board for a particular gain You may also need to recalibrate the A D converter if you will be using the 30 Hz conversion rate The procedure is straightforward and is described in Chapter 5 Calibration Chapter 3 A ee SEE Programming the AD500 The 0500 uses an 8255 Programmable Peripheral Interface PPI chip to control the on board A D converter input multiplexer programmable gain amplifier and 7 TTL compatible digital 1 O lines By utilizing a PPI the chip count of the design is minimized without sacrificing any loss of performance The software included with your AD500 performs all the necessary interfacing functions with the PPI These routines allow you to initialize the AD500 take readings select the input channel change gain and control the digital I O lines USING THE AD500 APPLICATION SOFTWARE Before you begin to use the software be sure to make a backup copy of the Program Disk included with your AD500 and store your original disk in a safe place You may make as many copies of the Program Disk as you need A description of the software included with your AD500 is given in the file README DOC on the Program Disk Considerations for programming the AD500 are also included Specific documentation for the language interfaces is contained in all files having the extension
27. brate the AD500 These affect the offset and full scale performance of the AD500 circuitry Both calibration steps are performed using trimpots TR1 and TR2 which are located at the top of the AD500 PC board see Figure 2 1 in Chapter 2 Trimpot is used for full scale adjustment and trimpot TR2 is used to zero the offset error of the PGA Offset Adjustment The offset adjustment on the AD500 may be used to compensate for the inherent offset output voltage of the PGA This adjustment effects the offset for all three gains all offsets move as the potentiometer is adjusted By compromising you can adjust for the average offset of all three gains or a compromise for just the X10 and X100 gains can be made considering the unity gain channel s offset is insignificant for high level inputs The AD500 is factory calibrated to minimize the effect of the offset voltage when gain of X100 is selected However your application may require that the offset be minimized for another gain setting To adjust the offset error of the AD500 the analog input will be connected to analog ground and trimpot TR2 will be adjusted while continuously taking A D conversions The Program Disk contains a calibration routine that will allow the gain to be changed interactively while displaying the results of each A D conversion Refer to the description in the README DOC file on the Program Disk for details on using this routine To perform the offset adju
28. de Rejection of Dual Slope Converter as a Function of Frequency 4 8 4 9 AD500 Conversion Period T Relative to 60 Hz Line Frequency 7 5 Hz AD500 4 9 5 1 Adjustable Voltage Source 5 2 B 1 AD500 Connector Pin Assignment B 1 Tables Page 2 1 AD500 User Selected Options 2 4 3 1 500 PPI Internal Register Definition _ __ 3 2 3 2 Input Channel Selection Bit 5 __ 3 10 3 3 Gain Control Bit Settings 3 11 3 4 Set Reset of PCO and PC1 3 11 3 5 Set Reset of INTE 3 15 5 1 12 Bit A D Converter Bit WeightS 5 4 1 ADS00 Connector Mating Connector LL B 1 Chapter 1 Introduction Many computer applications today require real time input of real world signals To connect a computer to the real physical world specialized analog interfaces are used to digitize voltages These voltages often represent the outputs of transducers or analytical instruments Transducers are devices that convert a real world physical quantity into an electrical signal that accurately reflects the value of a particular real world phenomena such as temperature humidity or sunlight analog to digital converter interface abbreviated A D or ADC is simply a piece of electrical hardware that p
29. e Between READ and or WRITE 150 intel A C CHARACTERISTICS Continued WRITE Dome Pe ss Sabi eto wane ta __ m RE tow ore veigtownrre Er eo 6 tercie uad wa o ____ o in Perser Da Ann no NOTES Test Conditions C 150pF 2 Period of Reset puise must be at isasi SOus during or after power on Subsequent Reset puise can be 500 ns TESTING INPUT OUTPUT WAVEFORM A C TESTING LOAD CIRCUIT gt POmTS lt TESTING meus ARE MS 113 AT VARIOUS VOLTAGES DUINO TESTING TO GUARANTEE THE ano 06v FOR LOGE WRITE TIMING MGH MIPCDANCE on band A 4 intel WAVEFORMS MODE 0 BASIC INPUT MODE 0 BASIC OUTPUT Harris HI 508A Analog Input Multiplexer SPECIFICATIONS Pinout M 6N0 Vsup 5 mo IN 8 508 plastic ABSOLUTE MAXIMUM RATINGS Note 1 Voltage between Supply Pins 44V Continuous Current S or D 20 mA V to Ground 5 22 Peak Current 5 V Ground 25 Pulsed at 1 ms 10 duty cycle max 40 mA Power Dissipation CERDIP 1 28 W Analog input Overvoltage Operating Temperature Range Vs vs 4 20 V
30. e interrupts be certain you are familiar with the procedure for initializing the interrupt vectors and the PC s interrupt controller and setting up the interrupt handling routines Reference 1 in Appendix C contains a very good description of the PC s system interrupts 3 15 Chapter 4 Theory of Operation A block diagram of the AD500 analog circuitry is shown is Figure 4 1 Functionally there are four major analog components the multiplexer MUX programmable gain amplifier PGA A D converter and voltage reference The PPI digital ports are used to control the analog components and read data from the A D converter REFERENCE Analog Inputs Connector P4 Fig 4 1 AD500 Analog Circuitry Block Diagram 4 1 A brief description of each of the major components of the AD500 is outlined below HI 508A An input protected single ended analog MUX made by Harris Corporation that allows the AD500 to monitor several analog channels 102 A very high quality PGA manufactured by Burr Brown Its gains are not controlled by the usual discrete feedback resistors but by two digital lines that provide gains of 1 10 and 100 by selecting internal precision resistors REFO2 A precision voltage reference manufactured by Precision Monolithics It provides a relatively temperature independent voltage reference for the A D converter that gives the AD500 excellent stability characteristics ICL7109 A 12 b
31. eger Kevin MS DOS Developer s Guide Howard W Sams amp Co Indianapolis IN 1986 ISBN 0 672 22409 7 Duncan Ray Advanced MSDOS Microsoft Press Redmond WA 1986 ISBN 0 914845 77 2 Kugg Tom and Feldman Phil Turbo Pascal Program Library Que Corporation Indianapolis IN 1986 ISBN 0 88022 244 1 Robinson Phillip R Using Turbo Prolog Osborne McGraw Hill Berkeley CA 1987 ISBN 0 07 881253 4 Koffman Elliot B Turbo Pascal A Problem Solving Approach Addison Wesley Publishing Company Inc Reading MA 1986 ISBN 0 201 11743 6 Dooley George and Szybist Daniel interface Projects For the IBM PC Real Time Devices Inc State College PA Dooley George Forth For Robot Control Robotics Age Sep Vol 7 No 9 7 8 1985 Dooley George and Szybist Daniel Accessing the Analog World Chemical Engineering Aug 22 1983 Appendix D Warranty LIMITED WARRANTY Real Time Devices Inc warrants the hardware and software products it manufactures and produces to be free from defects in materials and workmanship for one year following the date of shipment from REAL TIME DEVICES This warranty is limited to the original purchaser of product and is not transferable During the one year warranty period REAL TIME DEVICES will repair or replace at its option any defective products or parts at no additional charge provided that the product is returned shipping prepaid to REAL TIME DEVICES
32. ermits a computer to read or digitize the value of a voltage Real Time Devices AD500 is an 8 channel 12 bit analog interface board based on the ICL7109 CMOS A D converter and designed for use in an IBM PC XT AT or compatible computer The AD500 is highly accurate stable and resistant to interference from common noise sources A 7 5 Hz conversion rate provides 60 dB rejection of 60 Hz line noise Its high immunity to interference also makes the AD500 ideal for industrial environmental or laboratory data acquisition The AD500 is switch selectable for either a 7 5 Hz or 30 Hz conversion rate A 7 5 Hz conversion rate will provide significant rejection of 60 Hz line noise If line noise is not a consideration in your application a 30 Hz rate will allow maximum conversion speed Chapter 2 describes how to select either the 7 5 Hz or 30 Hz rate Eight analog inputs are software selectable and overvoltage protection circuitry prevents transients from damaging the inputs A prog rammable gain amplifier PGA eliminates the need to preamplify the input signals and permits measurement of a wide range of voltages The input ranges selectable by the PGA are 5 volts 500 millivolts and 50 millivolts 1 1 The seven digital lines are TTL compatible and are configured as two groups consisting of 5 lines and 2 lines The group of 2 lines may be assigned as input or output while the remaining 5 lines are configured as output
33. he multiplexer PGA A D converter and digital I O lines Some considerations are also given if you require the use of interrupts CHAPTER 4 explains the theory of operation of the various components which comprise the AD500 A discussion of the characteristics of the integrating A D converter technique as well as the performance of the multiplexer and PGA are included CHAPTER 5 provides the procedure for calibrating the AD500 This may be used for checking the operation of your 0500 for fine tuning its performance for your particular application APPENDICES contain technical information related to your AD500 This includes the AD500 and component specifications the P4 I O connector pin assignment and connector types References and warranty information are also provided Every effort has been made to design a quality easy to use yet low cost A D converter interface board We are certain that you will find the AD500 to be a valuable interfacing tool for your PC 1 2 Chapter 2 Installation The AD500 plugs into any expansior slot including a short slot of an IBM PC XT AT or compatible computer It may be advantageous therefore to choose an available short slot inside your computer The board s I O address and interrupt channel are jumper selectable Preventing possible contention with other devices simply involves changing two jumpers If the board address is unjumpered or incorrect the AD500 will not operate
34. i Pore iji Conr Fig 2 2 0500 Port Address Decode The AD500 base address has been preset to 200 For future reference you may wish to record the base address you selected in Table 2 1 the base address is changed from the preset value of X 200 the example software provided with the 0500 will need to be modified to reflect the new value The procedure to do this is explained in the comments which accompany each of the sample programs 2 3 Interrupt Channel Selection Connector The AD500 may be configured to generate an interrupt upon completion of an A D conversion To select which PC interrupt channel is used to service the interrupt position the jumper on the connecter labeled P3 to correspond to the desired interrupt channel number The jumper should be placed horizontally across the pair of header pins beside the interrupt channel number If interrupts are not used this jumper must be ser as shown in Figure 2 3 IRQ 2 4 005 DO 6 DD 7 Fig 2 3 Interrupt Disable Jumper Position The 0500 interrupt is preset to the disabled position For future reference you may wish to record the interrupt channel used in Table 2 1 Table 2 1 ADSOO User Selected Options 1 Base Address hex decimal INTR IRQ Channel Selection IRQ INTR Chapter 3 describes considerations for using the AD500 interrupts SELECT
35. idually programmed to be set or reset without effecting the state of the other bit Selecting the Direction of Port C Two different configurations may be used for transferring data using Ports B and C To select the mode you wish to use it may be necessary to write a different value to the PPI Control Word than was used in Initializing the PPI Figure 3 13 shows the Control Word data format for configuring Port C as input or output This data must be written to the Control Word whenever Port C is to be reconfigured Whenever one of these values is written to the PPI Control Word the PGA will be set to a gain of 1 and the MUX will select analog input channel AINI In addition whenever the PPI Control Word is written to with bit 7 set all digital outputs and status flags will be reset 7 6 5 4 3 2 1 0 1 PPI Control Word Port C l Input 0 Out put Direction Port Direction Control Word Data gt 6 2 5 3 rion PB 2 die INPUT JPC pC7 x X B8 7 OUTPUT E Fig 3 13 Selecting Port C Direction Outputting Data on Port B and Port C Data is output by Port B by writing to the PPI Port B register address This address was defined in Table 3 1 The following BASICA OUT statement will output the bit pattern 1010 1010 to Port B OUT amp H201 amp HAA Output X AA to Port B To ensure that the analog input channel
36. ing Size 3 875 H X 5 25 W Short slot Warranty 1 year 8255 SPECIFICATIONS intel ABSOLUTE MAXIMUM RATINGS NOTICE Stresses above those listed under Absolute Maximum Ratings may cause permanent to the Gevice This 15 a stress rating only end functione Ambient Temperature Under Biss A 0 C to 70 C tion of the device at these or any other conditions above Storage Temperatura EN 65 C to 150 C those indicated in the operational sections of this Voltage on Any Pin cation is not implied Exposure to absolute maximum With Respect to Ground 70 5V to 7V rating conditions for extended periods may affect device Power Dissipation ne ER Us 2501 mW reliability Vo Output Low Voltage Data Bus Output Low Voltage Peripheral Port High Vonage Dou 2a Output High Voltage For 42 want Darlington Drive Current te Power supo curen pur tosd Cumo NOTE 1 Avalisbie on any 8 pins from Port B and CAPACITANCE Ta 25 C Vec GNO OV A C CHARACTERISTICS 1 Vec 5V 5 GND OV Bus Parameters READ wu Address Sable Before READ ins cres Subi Alte READ Data Valid From READ Data Fioat After READ o Tim
37. ip ensures that the reference capacitor voltage will be connected with the correct polarity to cause the integrator output to return to the zero crossing established by Auto Zero with a fixed slope The time represented by the number of clock periods counted for the output to return to zero is proportional to the input signal Zero Integrator Phase Input low is shorted to analog Common and the reference capacitor is charged to the reference voltage A feedback loop is closed around the system to input high causing the integrator output to return rapidly to zero See Figure 4 7 This phase normally lasts between 16 and 32 clock pulses but is extended to 1552 clock pulses after an overrange conversion ZERO 5 ZERO INTEGRATOR PHASE 1 s RAPIOLY BRINGS INTEGRATOR INT OUTPUT ZERO OVERRANGE At INPUT PE POLARITY i i DETECTO Fig 4 7 integrator Output for Overrange Input Compliments of Maxim integrated Products Inc copyright 1985 4 7 This phase will remcve any residual charge left on the integrator capacitor after an overload reading This Zero Integrator phase virtually eliminates the problem of interaction or crosstalk between the various channels of a multiple channel data acquisition system Without the zero integrator phase an overload on one channel would leave charge on the integrator capacitor which would then be transferred to the autozero ca
38. it plus sign dual slope integrating CMOS A D converter manufactured by Maxim It digitizes the output of the PGA and converts it to a format that is read into the computer through the 8255 PPI 8255 A programmable peripheral interface PPI manufactured by many companies but originally developed by Intel Corporation The PPI serves as a general digital interface component to dramatically reduce the chip count of Real Time Devices boards It buffers the data bus selects the input channel controls the PGA gain starts conversions and reads data from the A D converter The PPI also controls the external digital lines Details on controlling the PPI were presented in Chapter 3 MULTIPLEXER Description The Harris HI 508A is an eight channel single ended analog multiplexer with active overvoltage protection Analog input levels may greatly exceed either power supply 12V without damaging the device or disturbing the signal path of other channels Active protection circuitry assures that signal fidelity is maintained even under fault conditions that would destroy other multiplexers Analog inputs can withstand constant 64 volt peak to peak levels and typically survive static discharges beyond 4 000 volts In addition signal sources are protected from short circuiting should multiplexer supply loss occur each input presents 1 of resistance under this condition These features make the HI 508A ideal for use in systems
39. ode that is selected will determine the conversion rate Figure 4 4 shows the A D conversion timing in the Continuous Convert Mode i e when the START CONVERT signal is held high ZERO CROSSING Occuns MTEGAATOR OUTPUT NORMA i 1 i 1 1 b zenoc 1 o po 2 PHASE tampa INT PHASE eM DENT PHASE 2 cuoca nu UAL UU Ur aoe Hz 16 20us 1 D Laren T 30 Hz 4 07 5 t u LI p i Counts CUM OF COUNTS TO reao 2 71 OFTER ZERO CROSSING amp nALOG SECTION PROPORTIONAL TO ve N ZERO Int WTLGRATOR GO AUTO AO CONFIGURATION Fig 4 4 Conversion Timing Continuous Convert Mode Compliments of Maxim Integrated Products Inc copyright 1985 In this mode of operation a conversion cycle consists of a fixed number of 8192 clock cycles Regardless of input signal voltage this conversion rate is a consistant 7 5 or 30 conversions per second depending upon the hardware configuration of the AD500 This is a period of 133 33 milliseconds for a 7 5 Hz rate or 33 33 milliseconds for a 30 Hz rate Refer to Chapter 2 to determine how to select the conversion speed Figure 4 5 shows the conversion timing when the AD500 is in the Single Convert or Strobed Convert Mode In these modes the START CONVERT signal is pulsed high and then low to initiate each conversion Tee
40. only The analog and digital lines as well as 12 volts the PC s reset signal and digital and analog grounds are accessible through a 40 pin header connector at the end of the board This connector is compatible with Real Time Devices XB40 1 extender board and XC40 expansion cable The XB40 consists of two 20 pin screw terminals and a prototype area The screw terminals allow easy connection of signals to the AD500 and the prototype area allows development of unique analog front end circuitry The XC40 is a cable assembly which terminates in a 40 pin wire wrap header connector This connector is suitable for installation in standard perf board material The Program Disk included with your AD500 contains software routines to control the A D converter input multiplexer PGA and digital 1 0 lines Detailed information is also provided to permit you to write your own routines for controlling the AD500 This manual has been organized into five main chapters with a group of Appendices that contain information that you may need to refer to from time to time CHAPTER 1 briefly describes the AD500 operating features 1 0 capability and software CHAPTER 2 explains how to install the AD500 in your computer This includes selecting the base address interrupt capability and conversion speed and connecting signals to the I O connector CHAPTER 3 describes in detail the procedure for programming the AD500 which includes controlling t
41. pacitor during the autozero cycle tesulting in an erroneous reading for the next channel that is measured after the channel with the overload Integrating Converter Features The output of integrating A D converters represents the integral or average of an input voltage over a fixed period of time Compared with techniques in which the input is sampled and held the integrating converter will average the effects of noise A second important characteristic is that time is used to quantise the answer resulting in extremely small nonlinearity errors and no missing output codes The integrating converter also has very good rejection of frequencies that are an integral multiple of the measurement frequency see Figure 4 8 Bi NORMAL MODE RDECTION 68 Fig 4 8 Normal Mode Rejection of Dual Slope Converter as a Function of F Compliments of Teledyne Semiconductor When using an AD500 that is configured for a 7 5 Hz conversion rate this feature can be used to advantage in reducing line frequency noise Referring to Figures 4 4 or 4 5 you will notice that the conversion period T of the ICL7109 the time spent in the Signal Integrate Phase is 33 185 milliseconds As shown in Figure 4 9 this is very close to two full periods of 60 Hz line frequency noise 4 8 60 Hz Line Frequency 16 667 msec T 2 33 333 msec T Fig 4 9 ADSOO Conversion Period T Relative to 60 Hz Line Frequency
42. power up and each time the digital 1 0 ports are to be reconfigured and is done by writing data to the Control Word as shown in Figure 3 2 3 2 Bit 7 6 5 4 3 2 1 0 PPI Control Word Port C Port Input Output Figure 3 2 500 PPI Control Word Initialization Data Whenever data is written to the Control Word with bit 7 set the PGA will be set to a gain of 1 and the multiplexer will select analog input AINI Using BASICA executing the OUT statement OUT amp H203 amp HB8 will correctly initialize the PPI In this example the AD500 digital lines were configured as Port B output and Port C input Refer to the section in this chapter entitled Programming the Digital Ports Selecting the Direction of Port C to determine the data that is written to configure Port C as output INTERFACING WITH THE A D CONVERTER The 500 may perform A D conversions in any of three modes single continuous or strobed Each mode offers its own unique advantages but all three modes offer high rejection of 60 Hz line noise when converting at a rate of 7 5 Hz The modes differ in the way the START CONVERT signal is used to initiate an A D conversion The mode selected also determines the speed conversions are performed The following paragraphs explain the characteristics of each mode and will help you decide how to best utilize the AD500 for your application Single Convert Mode In this mode of operation
43. riting the data shown in Figure 3 3 to the PPI Control Word When the conversion is completed the PPI s Input Buffer Full IBF signal will be set The status of the IBF signal is checked by reading the PPI Status Word as shown in Figure 3 4 Once the IBF is set reset then set the START CONVERT signal by writing the data shown in Figures 3 5 and 3 3 respectively to the PPI Control Word This must be done after detecting the completion of each conversion Now the MSB and LSB of A D data can be read from Port A Refer to the Continuous Convert Mode description for details on the procedures for reading the A D data and terminating conversions The timing diagram in Figure 3 8 illustrates the handshaking signals required to perform A D conversions and read the results in the Strobed Convert Mode START CONVERT J A D Data sp 1 5 Strobe p 20 PPI IBF 7 A MSB of data LSB of data read from PPI read from PPI PPI INTR 5 SS Ll L k 1 Conversion Cycle Fig 3 8 500 Strobed Convert Mode Timing Diagram The following programming model summarizes the sequence of events required to perform conversions in the Strobed Convert Mode Set START CONVERT Check IBF until set Reset START CONVERT Set START CONVERT Repeat to read Read A D MSB data each conversion Check IBF until set Read A D LSB data Check IBF until set Reset START CONVERT Read A D MSB data U
44. rupt PC IRQ channels supported 2 7 Analog inputs 8 channels single ended Impedance 700 Megohms Gains software 9grammable 1 10 100 n 0 5 typ 1 max Input range 5 V 500 mV 50 mV Zero shift with gain change 5 bits max Overvoltage protection 35 Vdc Settling time 5 usec max A D Specifications Type Dual slope integrating with auto zero ICL7109 Resolution 12 bits plus sign Conversion rate 7 5 30 switch selectable Min Hz Relative accuracy 1 bit gain 1 Linearity 1 bit 7 5 Hz gain 1 3 bits 30 Hz Rollover error 1 bit Digital 1 0 7 TTL compatible lines Input or output 2 lines Output 5 lines Miscellaneous Outputs PC bus sourced Reset Driver 12 Vdc Digital ground Software Features Interactive programs are included that allow immediate verification of the operation of the AD500 BASIC examples are provided which demonstrate the control of the A D converter input MUX and gain selection A complete directory of all software included with the ADSOO is listed on the accompanying disk Electrical Current requirements 5V 20 mA 12V 15 mA 12V 13 mA Mechanical Connectors 40 pin right angle shrouded header with ejector tabs Edge connector IBM PC XT AT compatible Environmental Operating temperature to 50 Centigrade Storage temperature 20 to 70 deg Centigrade Humidity 0 to 90 non condens
45. sed to read Check IBF until set last conversion Read A D LSB data A sample BASICA program for using the AD500 in the Strobed Convert Mode is contained on the Program Disk A D Converter Data Format Figure 3 8 shows the format of the MSB and LSB A D converter data Polarity 1 Overrange 1 P o Neg Por ova x x Dil Dio 09 08 a o mse Bit 7 6 5 4 3 2 1 0 9 vs 05 4 pi po X Don t Care Fig 3 9 AD500 A D Converter Data Byte Format The MSB of the A D converter data contains polarity and overrange status indications along with the four most significant bits of the A D converter data The LSB contains the eight least significant bits of the A D converter data ANALOG INPUT CHANNEL SELECTION The analog input multiplexer channel is selected using the three least significant bits of the PPI Port B bits PBO PB2 as shown in Figure 3 10 AINI Analog Output Connector P4 A2 AO PB2 PB1 Fig 3 10 MUX Channel Selection Bit Assignment The data written to Port B for each channel selection is shown in Table 3 2 Table 3 2 input Channel Selection Bit Settings Analog inpar 0 0 0 1 0 0 0 1 1 0 1 1 1 0 1 1 If your application requires changing the input channel when the 0500 is in the continuous or strobed convert modes the new channel should be selected before reading the MSB of the most recent A D converter value
46. stment jumper AINI P4 6 to analog ground 4 1 at the P4 connector Refer to Appendix B for the pin assignment of the P4 connector Run the calibration routine and adjust potentiometer T2 to trim the offset voltage to minimize its effect for the gain s of interest Because the offset voltage is related soley to the performance of the PGA its adjustment will be independent of input channel However the offset adjustment will effect the rollover performance of the A D converter Rollover is the difference in the conversion results between voltages having the same amplitude but different polarities Any gains which do not have a zero of set will give readings that are shifted from an ideal zero reference causing positive and negative readings of the same voltage to be slightly different This difference is a direct effect of the offset adjustment Full Scale Adjustment The full scale adjustment calibrates the reference voltage used by the A D converter to compensate for the analog input circuitry of the 0500 It is performed while a voltage equal to Full Scale 14 Least Significant Bit is applied to the analog input of the AD500 I O connector This voltage represents the ideal input voltage corresponding to the last code change between Full Scale reading and 14 LSB below FS The A D converter will be calibrated by monitoring the conversion results while adjusting trimpot TR1 Place the A D converter in the Continuous Convert
47. the handshaking signals required to perform a single A D conversion and to read the results 3 5 START een CONVERT S Bi gr EP EM Strobe ESB 20 usec max PPI IBF MSB of data LSB of data read from PPI read from PPI PPI INTR o _ Fig 3 6 0500 Single Convert Mode Timing Diagram The following programming model summarizes the sequence of events required to perform a conversion in the Single Convert Mode Set START CONVERT Check IBF until set Reset START CONVERT Read A D MSB data Check IBF until set Read A D LSB data A sample BASICA program for using the ADSOO in the Single Convert Mode is contained on the Program Disk Continuous Convert Mode This mode of operation automatically allows for an A D conversion to be performed after each conversion result is read The conversion cycles will be a fixed length of time and provided the data is read promptly after each conversion is completed conversions will be performed at a constant rate of 7 5 or 30 Hz depending on the hardware configuration of your AD500 Refer to Chapter 2 for details on selecting the conversion speed New data will not be strobed into the by the A D converter until both bytes of the previous conversion are read This ensures that the A D data will not be corrupted Starting Conversions onversions To utilize the Continuous Convert Mode the START CONVERT signal is set high and should remain high as long as
48. tions of the Burr Brown data sheet for the PGA102 which contain the specifications of concern to your application are reprinted in Appendix A Specifications 4 3 Common Common SENSE Ya 2120 Va 3 ANALOG INPUT M uw T tec 1 ne 12 12 SELECT SELECT conten Fig 4 3 102 Functional Block Diagram Compliments of Burr Brown Corporation copyright 1986 REFERENCE The Precision Monolithics REF 02 provides a stable voltage reference for the A D converter Its low noise and excellent temperature stability which is achieved with a band gap design contribute to the overall performance of the converter A D CONVERTER Description The Maxim ICL7109 12 bit A D converter digitizes an analog input signal into a 12 bit word plus a sign bit to indicate the polarity of the signal It is a low power CMOS dual slope integrating A D converter The ICL7109 has a very high input impedance reflected by its input bias current of about 1 picoamp a sophisticated auto zero circuit to minimize internal offset voltages and a low input noise specification of about 15 microvolts peak to peak The integrating A D s method of conversion is characterized by high accuracy and noise immunity Control The ADSOO will perform A D conversions continuously using the Continuous Convert or Strobed Convert Mode or on demand in the Single Convert Mode The m
49. ts 20 12 Volts Fig B 1 ADSOO Connector Pin Assignment Manufacturer KEL AM Inc 3M Robinson Nugent MIL C 83503 AIN7 AINS5 AIN4 AIN2 Analog Gnd PC6 PB6 Pin PB4 RESET DRV Digital Gnd Pin 20 AD500 Connector P4 Mating Connector 6201 040 258 6230 040 601 3417 7040 IDS C40PK C SR TG M83503 7 09 Appendix C References 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Eggebrecht Lewis C Interfacing To The IBM Personal Computer Howard W Sams amp Co Inc Indianapolis IN 1983 ISBN 0 672 22027 X Jourdain Robert Programmer s Problem Solver for the IBM amp AT Prentice Hall Press New York NY 1986 ISBN 0 89303 787 7 Morgan Christopher L and Waite Mitchell 8086 8088 16 Bit Microprocessor Primer BYTE McGraw Hill Peterborough NH 1982 ISBN 0 07 043109 4 Lafore Robert Assembly Language Primer for the IBM PC amp XT New American Library New York NY 1984 ISBN 0 452 25711 5 Norton Peter and Socha john Peter Norton s Assembly Language Book for the IBM PC Prentice Hall Press New York NY 1986 ISBN 0 13 661901 0 Abel Peter Assembler for the IBM PC and PC XT Reston Publishing Company Inc Reston VA 1984 ISBN 0 8359 0153 X Scanlon Leo J IBM PC Assembly Language Kobert J Brady Co Bowie MD 1983 ISBN 0 89303 241 7 Angermeyer john and Ja
50. ver you are uncertain of the state of the A D converter data transfer such as after breaking from a BASIC program you should execute the sequence described in the following section before initiating more conversions Initializing the A D Converter Before the A D converter can be used in any conversion mode it must first be initialized so that the data transfers will be properly sequenced This is required only once after power up or whenever you need to resynchronize the A D data transfers After initializing the PPI as described above the following sequence must be performed to initialize the A D converter Set START CONVERT See Figure 3 3 Read PPI Port A Delay 20 microseconds Read Status Word Check Status Word IBF indication See Figure 3 4 If IBF is reset If IBF is set Check IBF until set Reset START CONVERT See Read Port A Figure 3 5 Check IBF until set Delay 90 milliseconds Reset START CONVERT Read PPI Port A See Figure 3 5 Delay 90 milliseconds Read Port A A BASICA routine for the A D initialization is contained in the DEMO programs on the Program Disk Single Convert Mode An A D conversion of the input voltage is performed each time the START CONVERT signal is pulsed high This is done by setting and resetting bit PC2 of the PPI Using the Port C Bit Set Reset feature of the PPI the START CONVERT signal is set by writing the data shown in Figure 3 3 to the Control Word 3 4
51. xpansion slot connector 4 After you are certain the board lines up correctly push down on the metal bracket tab and the top of the board until the board is seated firmly in the expansion slot connector 5 Reinstall the screw that was removed with the blank bracket and replace the cover to your computer EXTERNAL CONNECTIONS Connector P4 All external connections to the AD500 are made to the I O connector labeled P4 see Figure 2 1 which is accessible through the rear panel of the computer The P4 mating connector type is listed in Appendix B as well as the pin assignment of all signals associated with the AD500 To attach the mating connector first open the ejector tabs on the AD500 I O connector Then observing the keying of both connectors install the mating connector and push firmly until the ejector tabs snap closed securing the connector in place The AD500uses a CMOS programmable peripheral interface chip The digital 1 O lines of this device may be permanently damaged if they are subjected to high energy electrostatic fields When making connections to the associated P4 pins be careful that they are not exposed to electro static discharge ESD 2 5 CALIBRATION Two trimpots are located near the of the AD500 see Figure 2 1 These trimpots are used for calibrating the A D converter The AD500 is factory calibrated to maximize the performance of the A D converter over all three gain ranges 1 10
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