AN11174 DALI slave using the LPC111x
Contents
1. 1k0 a fo Hy TX Tx RX a iH RESETN RESEN PWM4 Pen PWM a ar me PWM menas 10 2 J SDA SOA 1 SCL s NG 2 3V3 GND Fig 10 Microcontroller connections The OM13026 board can derive its microcontroller clock from a an external connected crystal circuit Q2 C4 C5 or b an internal RC oscillator This is configurable in the application software The function of header X4 is twofold it contains the 3 3 V supply on pins 13 and 14 and contains many input output controls on pins 1 to 11 The board should be powered by an external 3 3 V supply The current consumed is in the range between 2 mA and 15 mA depending on the clock configuration of the microcontroller internally clocked vs external crystal vs clock speed running up to 48 MHz AN11174 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 1 March 2012 10 of 29 NXP Semiconductors AN1 1 1 14 AN11174 DALI slave using the LPC111x The input output controls are listed in Table 1 It shows the default function of the pins on header X4 Table 1 Header X4 description Pin Description Direction LPC1114 pin Remark 1 TX O PIO1_7 TXD CT32B0_ UART MAT1 2 RX PIO1_6 RXD CT32B0_ UART MATO 3 ON_OFF O PIOO_3 4 RESETN O nReset PIOO_0 5 PWM1 O PIO0_8 MISO0 CT16B 0_MATO 6 PWM2 O PIO0_9 MOSI0 CT16B 0_MATI1 7 PW2. Fig 3 DALI wires combined with mains power wires 1 2 2 Physical layer The DALI bus consists of two wires on which data is transmitted in frames There are two different frame types a forward frame 2 bytes sent by the master to the slave anda backward frame 1 byte sent by the slave to the master on request of the master DALI uses a bi phase also called Manchester encoding which means that the data is transmitted using the edges of the signal A rising edge indicates a 1 and a falling edge indicates a 0 see Fig 4 AN11174 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 1 March 2012 4 of 29 NXP Semiconductors AN11174 DALI slave using the LPC111x 2TE Fig 4 Bi phase encoding of data Logico Logic 1 2TE The encoded bits are actually represented by high and low voltage levels on the bus Typically the low voltage is 0 V and the high voltage is 16 V The maximum and minimum bus voltage at both the transmitting unit and the receiving unit are given in Fig 5 transmitting unit control line 1 power supply i voltage range threshold 1 power supply i 0 V typ l voltage range I 1 Fig 5 Bus voltage levels receiving unit 1 22 5 V max 20 5 V max i l l l high level S S 8 0 V typical low level l undefined receiver
3. NXP Semiconductors AN1 1 1 74 DALI slave using the LPC111x 2 Hardware description AN11174 2 1 This section describes the hardware of the DALI slave board First the physical layer of the board will be discussed followed the complete board description Physical layer The schematic of the DALI physical layer from board OM13026 is depicted in Fig 9 The DALI bus connects to the connections D The microcontroller LPC111x is connected to the signals DALI1_TX and DALI1_RX B1 2 MB1S AJN E X3 N gt AN u1 PSS12021SAY olL JZ OK1 aye 1 vs 4 aK 2 aa PC357N4 Fig 9 Physical layer schematic By usage of bridge rectifier B1 the design is made polarity independent Both terminals D are interchangeable The upper part of Fig 9 contains the transmission part of the DALI slave It is created around T1 R2 R3 OK2 and R4 The signal DALI1_ TX is driven by the microcontroller at 0 V or 3 3 V For high signals of DALI1_TX Optocoupler OK2 will connect the junction of R2 and R3 to the DALI bus This will create a drive current for the base of T1 that will start to conduct and short circuit the DALI bus via bridge B1 When the signal DALI1_TX is low transistor T1 will not conduct and the bus will be in the high state The resistor R3 of 390 Ohm is chosen such that T1 will sufficiently go into saturation and thus create
4. high level Mm undefined Mm receiver low level MM undefined gt voltage range voltage range AN11174 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 1 March 2012 5 of 29 NXP Semiconductors AN1 1 1 74 DALI slave using the LPC111x The bus is powered via a bus power supply which can be part of the master on the bus and has a current limit of 250 mA Whenever a control gear on the bus wants to modulate the bus voltage it will short circuit the bus to create a low voltage level If a high level is desired it will put its transmission stage in a high impedance state 1 2 3 Logical layer In a typical application a DALI bus consists of one controller master and multiple slaves normally TL ballasts It can control up to 64 different slaves ballasts within the same control system It s possible to transmit commands to single ballasts or to a group of ballasts Every bit takes two periods TE The defined bit rate of DALI is 1200 bps So a 1 bit period 2TE is 834 usec A frame is started by a start bit and ends with two high level stop bits no change of phase Data is transmitted with the MSB first Between frames the bus is in idle high state see Fig 6 s 8 address bits 8 command bits stop a 8 data bits stop 1jafojojo olols s ojrj1i1 sjololo rj 1 0 o o a o
5. DALI component has one main control flow shown in the left side of Fig 14 After initialization the DALI component waits for a forward frame from a control device This forward frame is received by the Interrupt Service Routine ISR shown on the right side of Fig 14 When the ISR has a complete forward frame it puts the message in a queue for the waiting main loop The main loop unblocks and executes the desired actions depending on the contents of the forward frame If the receiving command in the forward frame requires a response the ISR is instructed to generate a backward frame init board init DALI init ballast wait for command handle command normal execution interrupt driven receive forward frame transmit backward frame Fig 14 Simplified execution flow All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 1 March 2012 16 of 29 NXP Semiconductors AN1 1 1 14 AN11174 3 4 3 4 1 3 4 2 3 4 3 DALI slave using the LPC111x By default the ISR routine is in receive mode and will switch to transmit mode when instructed by the main loop When the transmission of the backward frame is ready the ISR routine automatically switches back to receive mode The interrupt driven reception of DALI frames is done bit by bit multiple calls of the ISR routine concatenate the received bits until
6. DALI fade features the software can calculate intermediate steps for creation of smooth fade effects This is done in the function Fade TickHandler Coupling of lamp failure information is lighting driver dependent Any lamp failure information can be coupled to the DALI stack in the function LampFailure in DALI src DALI_ballast c 3 6 Supported commands The following tables give an overview of the supported commands of the accompanying software If there is no remark the command is implemented Table 4 Indirect arc power control commands Command nr Description Remarks OFF UP DOWN STEP UP STEP DOWN RECALL MAX LEVEL RECALL MIN LEVEL STEP DOWN AND OFF ON AND STEP UP ENABLE DAPC SEQUENCE unsupported 10 19 RESERVED COMMANDS 16 31 GO TO SCENE ON Oa fF WwW NM O o Table 5 Configuration commands Command nr Description Remarks 32 RESET 33 STORE ACTUAL LEVEL IN DTR 34 41 RESERVED COMMANDS 42 STORE DTR AS MAX LEVEL 43 STORE DTR AS MIN LEVEL 44 STORE DTR AS SYSTEM FAILURE 45 STORE DTR AS POWER ON LEVEL 46 STORE DTR AS FADE TIME 47 STORE DTR AS FADE RATE 48 63 RESERVED COMMANDS AN11174 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 1 March 2012 19 of 29 NXP Semiconductors AN11174 DALI slave using the LPC111x Command nr Description Remarks 64 79 STORE DTR AS SCENE 80 95 R
7. Forward frame reception eeen 17 Command handling ccecceeeceeeeeeeeeeeeneereaes 17 Backward frame transmission eeeeee 18 Iter Upis hinini keinatu Ease 18 Lighting driver control seeen 18 Supported COMMANAS cceeceeeeeeesteeeeteeeeaes 19 Command extensions eeceeeeeeeneteneereaes 21 NVM storage cc eeeeseeeeseneeeeeeneeerenneeeeeeneeeeeeas 22 Configuration Options eceeeeeeeeeeeneeeneeeeees 22 Building the Software ee eeeeeeeeneeeeeeneeeeeeee 23 Document ManageMeNt cseseceseseeeeeseeeeeeeee 25 Abbreviations cccccceeeeeeecceeeeeeeeeeesenneeeees 25 References wees crocecssteeeecnede Seessbedtenceeveseesigceseatees 25 Legal information ccsssseesseeeessseeeensseeneeneee 26 Deftonesia eenia 26 DiSCIAIMETS cccccceeeceeeeeeeeeeeeeeeeeeeeeeeeeeeeaee 26 Trademarks aiipata nleii 26 List Of FIQUIES csesteeeesseeeeesseeeeneeeeeeensenennenes 27 List of 8 C 0 ee 28 CONTGINNS cerisa essens Esnean streeado nesant eeees 29 Please be aware that important notices concerning this document and the product s described herein have been included in the section Legal information NXP B V 2012 All rights reserved For more information visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com Date of release 1 March 2012 Document identifier AN11174
8. 10V X7R 0805 not mounted c9 2u2 6V3 X7R 0805 not mounted D1 LED0805 CHIPLED_0805 D2 BZX84C3V0 NXP Semiconductors T0236 IC2 SA57000 33D NXP Semiconductors not mounted L1 BLM18AG601S 0603 not mounted OK1 PC357N4 Sharp OK2 PC357N4 Sharp Q2 12MHz optional Q4 BSH205 NXP Semiconductors SOT23 R1 560R 0805 R2 1k 0805 R3 390R 0805 R4 390R 0805 R5 3k3 0805 R6 10k 0805 R8 1k0 0805 R12 33R 0805 not mounted R13 1k5 0805 not mounted R14 33R 0805 not mounted R15 nc 0805 S1 KMR211G C amp K Components not mounted T1 BCX56 16 NXP Semiconductors SOT89 BCE U1 PSSI2021SAY NXP Semiconductors SOT353 U2 LPC111x NXP Semiconductors LQFP48 x1 565790519 MOLEX MINI AB USB not mounted X2 MKDSN1 5 2 5 X3 MA04 1R not mounted X4 MA14 1W pin 12 removed X5 FTSH 105 01 SAMTEC X6 MA04 1R not mounted All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 1 March 2012 13 of 29 NXP Semiconductors AN1 1174 DALI slave using the LPC111x 3 Software description AN11174 3 1 This chapter describes the structure and components of the software project for usage with hardware board OM13026 to create a DALI control gear After a small software overview the DALI stack will be explained in detail The other components of the example software project are not discussed in depth Decomposition The decomposition of the software is given in Fig 1
9. 2 Inclusion of shaded parts into the DALI control gear can be selected at compile time For the software interface to the hardware peripherals of the LCP111x the Cortex Microcontroller Software Interface Standard CMSIS is used o Aleatoneame ULM WM namm DALI1_TX PWM1 PWM2 PWM3 PWM4 ON_OFF IO DALI2_TX DALI1_RX DALI2_RX 1 shaded striped items are optional Fig 12 System decomposition The DALI component handles the reception and transmission of DALI frames using the CT32B0 timer capture unit For ballast control the 16 bit timer units CT16B0 and CT16B1 are used to generate pulse width modulated PWM signals General purpose IO pins can be used to signal a lighting driver to switch on or off or to read lamp failure information into the DALI component The DALI stack and the example application use a small operating system abstraction layer OSAL This OSAL provides service like message transfers via queues and thread creation The complete set of functions of the OSAL layer is not topic of this application note and is not discussed The functions of the OSAL layer map to multiple operating systems OS The target OS can be selected at compile time The software described supports two mappings a version without an OS version and a version that maps onto the FreeRTOS OS The version without OS support implements a minimal set of functions to enable the DALI stack to run It does not support multiple threads or o
10. AN11174 DALI slave using the LPC111x Rev 1 1 March 2012 Application note Document information Info Content Keywords Abstract Lighting networks DALI CORTEX MO ARM LPC111x Microcontroller This application note describes how to create a DALI slave device with the OM13026 LPC111x DALI slave board NXP Semiconductors AN1 1174 DALI slave using the LPC111x Revision history Rev Date Description 1 20120301 Initial version Contact information For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com AN11174 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 1 March 2012 2 of 29 NXP Semiconductors AN1 1174 DALI slave using the LPC111x 1 Introduction AN11174 1 1 1 2 The aim of this document is to describe how to create a DALI slave device with the OM13026 DALI slave board It covers the following aspects e Short introduction into DALI lighting networks e OM13026 LPC111x DALI slave board design description Global software overview Supported DALI command set e Software configuration items This application note does not include items covering the light generation aspect especially e Description of lighting drivers CFL SSL e Lamp feedback color temperature Overview This application note is intended fo
11. EMOVE FROM SCENE 96 111 ADD TO GROUP 112 127 REMOVE FROM GROUP 128 STORE DTR AS SHORT ADR 64 79 STORE DTR AS SCENE 80 95 REMOVE FROM SCENE 96 11 ADD TO GROUP 112 127 REMOVE FROM GROUP 128 STORE DTR AS SHORT ADR 129 ENABLE WRITE MEMORY unsupported 130 131 RESERVED COMMANDS Table 6 Query commands Command nr Description Remarks 144 QUERY STATUS 145 QUERY CONTROL GEAR 146 QUERY LAMP FAILURE 147 QUERY LAMP POWER ON 148 QUERY LIMIT ERROR 149 QUERY RESET STATE 150 QUERY MISSING SHORT ADR 151 QUERY VERSION NUMBER 152 QUERY CONTENT DTR 153 QUERY DEVICE TYPE 154 QUERY PHYS MIN LEVEL 155 QUERY POWER FAILURE 156 QUERY CONTENT DTR1 157 QUERY CONTENT DTR2 158 159 RESERVED COMMANDS 160 QUERY ACTUAL LEVEL 161 QUERY MAX LEVEL 162 QUERY MIN LEVEL 163 QUERY POWER ON LEVEL 164 QUERY SYSTEM FAILURE LEVEL 165 QUERY FADE TIME RATE 166 175 RESERVED COMMANDS 176 191 QUERY SCENE LEVEL 192 QUERY GROUPS 0 7 193 QUERY GROUPS 8 15 AN11174 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 1 March 2012 20 of 29 NXP Semiconductors AN11174 AN11174 3 7 DALI slave using the LPC111x Command nr Description Remarks 194 QUERY RANDOM ADDRESS H 195 QUERY RANDOM ADDRESS M 196 QUERY RANDOM ADDRESS L 197 READ MEMORY LOCATION unsupported 198 223 RESERVED COMMANDS 224 254 APPLICATION EX
12. M3 O PIO1_9 CT16B1_MATO 8 PWM4 O PIO1_10 AD6 CT16B1 _MAT1 9 IO 1 0 PIO0_7 nCTS 10 SDA O PIOO_5 SDA 12C 11 SCL O PIOO_4 SCL 12C 12 nc 13 3V3 VDD1 2 14 GND VSS1 2 Up to four PWM signals are available to independently drive different lighting units The frequency and resolution of the signals is software programmable The ON_OFF signal can be used independently from the PWM signals to switch a lighting driver into an OFF or ON state The I C bus pins can be used to externally connect other devices like EEPROM or a temperature sensor An analog A D input is available via pin 8 The IO signal is left open for the end user UART I C and A D converter functionality is not included in the software release All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 1 March 2012 11 of 29 NXP Semiconductors AN1 1174 DALI slave using the LPC111x 2 3 Board layout The layout of the board is given in Fig 11 On header X4 pin 12 is removed to function as key to circumvent misplacement when attaching it to a lighting driver Fig 11 PCB layout In Fig 11 the optical isolated DALI physical interface is placed on the left side of the dotted line On the right side of the board the LPC1114 microcontroller with the 10 pin SWD debug programming header is placed The middle part of the printed circuit board is not populated and n
13. MMANAG cc cccceeeceeeessteeeesenees 21 Pre defined ballast configuration options 22 Additional configuration options e 23 DALI slave firmware SIZ c cceesseeeeeeees 24 Abbreviations cccccccccesceceeesseeesseseeeseneeees 25 References aoea eaan aeaaea E anai ai 25 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 1 March 2012 28 of 29 NXP Semiconductors AN11174 8 Contents DALI slave using the LPC111x 3 4 1 3 4 2 3 4 3 3 4 4 3 4 5 3 5 3 6 3 7 3 8 3 9 3 10 4 1 4 2 5 1 5 2 5 3 Introduction sissisccccssisccssesccecnsaesneaeessasenccsacnanersntnnen 3 OVERVIEW ra oia aaae a A Ea 3 DAUT e E 3 Bus structure sssseneeeeeeeenereneeesrrrnneresrrrrnrneene 4 Physical layer cccesecseeesseeeeeeseeeeeeseeeeesesenees 4 Logical layer cccceeeeeeeeceeeeeeeeeeeeeeeneeeeeeeeeeeeeaee 6 Hardware description Physical layer isieniseiisnnsuanrenineiisnnrsannisniseinnnnnn Microcontrollers iiine Board layout ccceceeeeeeeceeeeeeeeeeeeneeeeeeeeeeeeeaee Component Stiir Software Aescription cccsecsseceseesseeeeeeeees DECOMPOSITION iviiissiissiininiesriiaiiris Component structure Run time POW weestesievesetliices Aosstesesceecdepsiezenetiect DALI reception and transmission 26 17 Inter frame timing eseese 17
14. TENDED unsupported COMMANDS 255 QUERY EXTENDED VERSION unsupported NUMBER Table 7 Special commands Command nr Description Remarks 256 TERMINATE 257 DATA TRANSFER REGISTER 258 INITIALIZE 259 RANDOMIZE 260 COMPARE 261 WITHDRAW 262 RESERVED1 263 RESERVED2 264 SEARCH ADDRESS H 265 SEARCH ADDRESS M 266 SEARCH ADDRESS L 267 PROGRAM SHORT ADDRESS 268 VERIFY SHORT ADDRESS 269 QUERY SHORT ADDRESS 270 PHYSICAL SELECTION lighting driver coupling open 271 RESERVED 271 RESERVED 272 ENABLE DEVICE TYPE X unsupported 273 DATA TRANSFER REGISTER 1 unsupported 274 DATA TRANSFER REGISTER 2 unsupported Command extensions In general two command extension types are possible e unsupported commands e multi byte commands The first extension of unsupported commands complements the software of this application note with non supported commands that are part of the DALI specification The second extension of multi byte commands is intended for three byte manufacturer specific commands All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 1 March 2012 21 of 29 NXP Semiconductors AN1 1 1 14 3 8 DALI slave using the LPC111x To extend the software with unsupported commands the functions DALI_ProcessNormalCommand and DALI_ProcessSpecialCommand in DALI src DALI_Command c should be extended The actual command defi
15. USB Universal Serial Bus 4 2 References Table 12 References Title 1 2 3 4 Version Author Edition 1 0 IEC IEC62386 101 Digital addressable lighting ae interface General requirements system ition 1 IE IEC62386 102 Digital addressable lighting ee 0 i interface General requirements control gear http www dali ag org Rev 7 NXP UM10398 LPC111x LPC11Cxx User manual Issue Date 2009 2009 2011 AN11174 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 1 March 2012 25 of 29 NXP Semiconductors AN11174 5 Legal information DALI slave using the LPC111x 5 1 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information 5 2 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequ
16. a low voltage level on the bus while having a low voltage drop on T1 This keeps the power dissipation of T1 limited as it should be able to sink the maximum DALI bus current of 250 mA Also for this reason T1 should have a high hre of minimum 100 In this way no additional cooling area is needed The reception path is shown in the lower part of Fig 9 It is created around optocoupler OK1 U1 R1 R5 and zener diode D2 When the DALI bus is idle high a constant current source of about 1 mA is created using U1 and R1 This current is used to drive All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 1 March 2012 8 of 29 NXP Semiconductors AN1 1 1 14 AN11174 2 2 DALI slave using the LPC111x optocoupler OK1 that signals the level of the DALI bus to the microcontroller via DALI1_ RX The current source limits the maximal current load the circuit creates when not in transmission mode Zener D2 and bridge rectifier B1 drop the received bus voltage to a level to guarantee that a low level voltage of 6 5 V does not drive the optocoupler The circuit around OK1 and R3 creates an inverted signal to the microcontroller A high DALI bus level will connect DALI1_RX to low A low DALI bus level will create a high signal on DALI1_RX All components are chosen to withstand several factors 70 V to 80 V of the highest allowed DALI bus voltage level
17. a full frame is received The same holds for the transmission part of the ISR it generates a frame on the bus on the basis of subsequent invocations of the ISR and at each invocation the bus is driven to create bi phase coded bits on the bus Additionally the system contains a system tick ISR routine for creating a system time lighting fading effects and an ISR to enable interpolation steps between DALI arc power levels The init board init DALI and init ballast are in the main function located in file DALIDemo main c The endless loop that waits for forward frames and the handling forward frames is performed by the function DALI_CommandHandler in DALI src DALI_Commana c The interrupt service DALI_IRQHandler for frame reception and transmission is located in DALI src DALI_PhysDriver c DALI reception and transmission The physical layer circuit of Fig 9 is connected to three pins of the microcontroller unit The incoming DALI signal is connected to a capture input of the timer capture unit and to a GPIO input The DALI TX signal is connected a GPIO output Inter frame timing The match register 0 MRO of the timer capture unit is used to create the minimal frame delay between forward frames see Fig 7 The MRO is set to 22Te When this match register creates an interrupt the ISR reception state is set to receive mode and capture interrupts are enabled Forward frame reception The capture function of the timer capture unit is used
18. ences of use of such information NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors In no event shall NXP Semiconductors be liable for any indirect incidental punitive special or consequential damages including without limitation lost profits lost savings business interruption costs related to the removal or replacement of any products or rework charges whether or not such damages are based on tort including negligence warranty breach of contract or any other legal theory Notwithstanding any damages that customer might incur for any reason whatsoever NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in life support life critical or safety critical systems or equipment nor in applications where failure or malfunction of an NXP Semiconductors produc
19. f these projects in debug mode the debug versions of the libraries are used Table 10 shows the size of the firmware in Release mode for different configurations of the software Note that this does not contain the stack size and the size of the flash sector used for storage of NVM configuration which is 4 kB on the LPC111x device Table 10 DALI slave firmware size Configuration control gear Firmware size Flash bytes Ram bytes CFL 1 9156 276 SSL1523 1 9060 276 UBA3070_1CH 1 9052 276 UBA3070_4CH 4 9860 732 DRIVER_3CH 3 9700 580 Using Table 10 it can be seen that the LPC1112 with 16 kB of flash is sufficient for creating a DALI slave device AN11174 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 1 March 2012 24 of 29 NXP Semiconductors AN11174 DALI slave using the LPC111x 4 Document management 4 1 Abbreviations Table 11 Abbreviations Acronym Description CMSIS Cortex Microcontroller Software Interface Standard CPU Central Processing Unit CT Counter Timer DALI Digital Addressable Lighting Interface GPIO General Purpose Input Output HW Hardware IDE Integrated Development Environment IRQ Interrupt Request LED Light Emitting Diode MCU Micro Controller Unit NVM Non Volatile Memory PC Personal Computer PCB Printed Circuit Board PIO Input Output Pin PLL Phase Locked Loop SW Software
20. hen using multiple DALI addresses in one physical device all variables of each logical DALI address are stored separately When one of the DALI variables is changed writing into the flash memory is delayed until the device does not receive commands for UPDATE_DEVICE_CONF_TIMEOUT milliseconds This prevents the DALI device from not responding to DALI frames during flash erase write no other tasks can be done on the processor core of the microcontroller 3 9 Configuration options To simplify the usage of the software several pre configured ballast configurations are included The ballast configurations vary the numbers of DALI devices in the slave the frequency of the PWM signals and enable usage of the on off signal These configurations can be set in the file DALI inc DALI h Only one configuration can be active at any time Table 8 _Pre defined ballast configuration options Configuration control gear Ballast drive PWM signals On off signal Frequency Hz Inverted CFL 1 2200 No Yes SSL1523 1 300 No No UBA3070_1CH 1 732 Yes No UBA3070_4CH 4 732 Yes No DRIVER_3CH 3 732 No No AN11174 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 1 March 2012 22 of 29 NXP Semiconductors AN1 1 1 14 DALI slave using the LPC111x The options of Table 8 set several ballast and communication configurations A more elaborate overvie
21. ins power wires 4 Bi phase encoding of data ee 5 Bus voltage levels 20 0 cesceeeeesseeeeeneeeseneeees 5 Physical encoding cesceeesesseeeeeneeeeeeneeees 6 Timing of forward and backward frames 6 DALI addressing tyPe S ccsceeeeeeeeteeeeeeeaes 7 Physical layer schematic 8 Microcontroller Connections eeeeeeeeeees 10 PCB layout reiini ee ea eE 12 System decomposition eee eeeeeeeteeeeeees 14 DALI component file structure 15 Simplified execution flow Physical encoding decoding using capture timer UNM ihc Ghia tie aelehi ae 18 Start LPCXpresso and select the DALI SDK folder AS workspace oo eeeeeeeneeeeeesteeereneeeees 23 Importing projects for DALI slave 24 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 1 March 2012 27 of 29 NXP Semiconductors AN11174 7 List of tables DALI slave using the LPC111x Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 AN11174 Header X4 description eeeeeeeeeeeeeeees 11 List Of COMPONENS eeeeeeeeeeeeeeeeeteeeeeeeeeee 13 DALI slave interrupts in USC eeeeeeeeeeee 18 Indirect arc power control commands 19 Configuration Commands c cseeeeeeeeeee 19 QUETY commands iisisti 20 Special CO
22. interface 2 not used on demoboard SysTick Generates system time Lighting driver control The software provides two ways to control lighting drivers a high low ON OFF signal and up to four pulse width modulated PWM signals to steer the brightness level of a light device Usage of the ON OFF signal is optional The PWM signals are generated using the 16 bit timer units All the functionality of lighting driver control is contained in the file DALI src DALI_ballast c Timer capture unit CT16B0 is used for PWM signals 1 and 2 timer capture unit CT16B1 is used for generating PWM signal 3 and 4 For each of these timer capture units the match register MR3 is used to set the PWM frequency Match registers MRO and MR1 are used in both timer units to set the duty cycle of the PWM signal Once setup the resulting PWM signal is generated without software intervention For more information on All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 1 March 2012 18 of 29 NXP Semiconductors AN1 1 1 14 DALI slave using the LPC111x the mode of operation of the timer capture unit refer to the timer chapter in the LPC111x user manual Each DALI arc power level is translated via a look up table to a duty cycle setting of the timer unit For each output a separate lookup table can be used The lookup tables are defined in DALI Dimcurve c When using the
23. nitions are in DALI inc DALL h To extend the software with three byte commands the function DALI_TRQHandler should be extended to support three byte commands First the stop bit detection should be altered to discriminate between two and three byte commands Second the function DALI_Decode should be changed to decode three byte commands Third the CommandHandler in DALI src DALI_Command c should be extended to handle the incoming three byte commands NVM storage Each DALI ballast has a series of properties called variables see table 6 IEC 62386 e g actual level power level min max level short address etc These properties are persistently stored in the nonvolatile flash memory of the microcontroller For this sector 7 of the flash memory is used as storage All nonvolatile variables are stored in one record in the flash sector When one of the variables is changed the complete record is stored in the flash sector As the record is relatively small in respect to the sector size multiple records fit in one sector The software routines in DALI src DALI_ Flash c ensure that only the last valid record is used The record contains a version indicator As the contents of the flash sector are OxFF after an erase it is guaranteed that the software always finds the first valid records when searching downwards from the highest address of the flash sector 7 Nonvolatile records are stored incrementally from the start of the sector W
24. of 22 5 V The physical layer does not contain overvoltage protection or suppression components This is left up to the reader The optocouplers create isolation between the microcontroller side and the DALI bus The isolation is sufficient for evaluation of the DALI software stack when the microcontroller is connected in a non isolated way to the mains supply any re use of this design should be made compliant to the isolation requirements as specified in section 5 4 of Reference 1 Microcontroller The section of the design which handles the incoming and outgoing DALI messages and controls the lighting is shown in Fig 10 The DALI1_RX signal from the DALI physical interface is connected to a 32 bit timer capture unit CT32B0 of U2 The DALI1_ TX signal is connected to a general purpose IO pin that is software controlled to generate the DALI signal timing Connector X6 makes is possible to connect a second different physical interface to the timer capture unit CT32B1 of U2 Debugging and flashing connection is provided by means of header X5 which complies with the 10 pin SWD standard as supported by many flash and software tools All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 1 March 2012 9 of 29 NXP Semiconductors AN1 1174 DALI slave using the LPC111x u2 LPC4413 149 GFP48 A g
25. oja UU UUUULI OUUU UUU U UULI ULI DALI forward frame DALI backward frame Fig 6 Physical encoding Additional protocol timing requirements for transmission are e The settling time between two subsequent forward frames shall be at least 9 17 ms This means that 4 forward frames with accompanying periods of 9 17 ms shall fit exactly in 100 ms e The settling time between forward and backward frames transition from forward to backward shall be between 2 92 ms and 9 17 ms After sending the forward frame the master unit will wait for 9 17 ms If no backward frame has been started after 9 17 ms this is interpreted as no answer from slave The settling time between backward and forward frames transition from backward to forward shall be at least 9 17 ms see Fig 7 29 17 ms 29 17 ms 2 92 9 17 ms 29 17 ms forward forward forward ahi forward frame frame j frame frame 15 83 ms 15 83 ms 15 83 ms 9 17 ms 15 83 ms Fig 7 Timing of forward and backward frames AN11174 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 1 March 2012 6 of 29 NXP Semiconductors AN1 1174 DALI slave using the LPC111x Every DALI slave is able to react to a short address 16 group addresses and broadcast For addressing the following scheme is shown in Fig 8 type of address Short or group add
26. on When the main loop decides that a backward frame should be transmitted it encodes the response into a Manchester encoded message and sets the ISR state to SEND mode while enabling the interrupt match register 2 MR2 with an initial time of 7 Te On the first time MR2 fires the ISR is triggered and the MR2 value is set to Te On each subsequent interrupt by MR2 the DALI1_TX GPIO is set by the ISR to the corresponding high low level of the Manchester encoded backward frame When all bits of the backward frame are transmitted the ISR state is set to RECEIVE mode This is illustrated in Fig 15 DALI forward frame DALI backward frame S 8 address bits 8 command bits stop s 8 data bits stop 1 1 o o ololo 1 1 ol1 1 1 1Jo oJo 1 1 0 o fo a fo oji x A yY capture register CRO MR2 4Te MR2 7 Te MR2 Te Capture timer unit running on 1MHz Fig 15 Physical encoding decoding using capture timer unit Interrupts The following table shows the interrupts that are handled by the software Table 3 DALI slave interrupts in use Interrupt Description IMER16_0_IRQ Generates signals PWM1 and PWM2 Used for driving lighting units IMER16_1_TIRO Generates PWM2 and PWMS3 signals Used for driving lighting units IMER32_0_IROQ Handles DALI interface 1 IMER32_1_TRQ Handles DALI
27. or not based on tort including negligence strict liability breach of contract breach of warranty or any other theory even if advised of the possibility of such damages Notwithstanding any damages that customer might incur for any reason whatsoever including without limitation all damages referenced above and all direct or general damages the entire liability of NXP Semiconductors its affiliates and their suppliers and customer s exclusive remedy for all of the foregoing shall be limited to actual damages incurred by customer based on reasonable reliance up to the greater of the amount actually paid by customer for the product or five dollars US 5 00 The foregoing limitations exclusions and disclaimers shall apply to the maximum extent permitted by applicable law even if any remedy fails of its essential purpose 5 3 Trademarks Notice All referenced brands product names service names and trademarks are property of their respective owners NXP B V 2012 All rights reserved Application note Rev 1 1 March 2012 26 of 29 NXP Semiconductors AN11174 6 List of figures DALI slave using the LPC111x Fig 1 Fig 2 Fig 3 Fig 4 Fig 5 Fig 6 Fig 7 Fig 8 Fig 9 Fig 10 Fig 11 Fig 12 Fig 13 Fig 14 Fig 15 Fig 16 Fig 17 AN11174 OM13026 LPC111x DALI Slave board 3 Example bus of control device and multiple control gear See 4 DALI wires combined with ma
28. ot folder the SDK installation path Make sure to uncheck the tick mark copy projects into workspace and select the projects that are shown in Fig 17 AN11174 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 1 March 2012 23 of 29 NXP Semiconductors AN1 1 1 14 DALI slave using the LPC111x r nl E Import exisiting projects Sa Import exisiting projects ie Select a directory to search for existing Eclipse projects i a Select root directory C nxp lighting DALI_ SDK_v1 0 Browse Select archive file I Projects V CMSISv1p30_LPC11x C nxp lighting DALILSDK_v1 0 LPC111xSla Select All F CMSISv1p30_LPC13x C nxp lighting DALI_SDK_v1 0 LPC134xMz V DALI C nxp lighting DALL_SDK_v1 0 LPC111xSlave DALI Deselect All l F dali_master_Ipc13x C nxp lighting DALI_SDK_v1 0 LPC134xMasi Refresh V DALIDemo C nxp lighting DALL_SDK_v1 0 LPC111xSlave DALIDe OSAL C nxp lighting DALI_SDK_v1 0 LPC111xSlave OSAL D Finish Cance L gt Fig 17 Importing projects for DALI slave DALIDemo is the example application that uses the DALI library project The DALIDemo project is configured to automatically build and include the DALI OSAL and CMSIS library projects In release mode the DAL IDemo project uses the release builds o
29. ot necessary for use as DALI slave unit Header X6 is meant to connect a second different DALI physical layer or can be used for an additional GPIO or 32 bit timer output The other components are used when U2 is mounted with the pin compatible LPC1343 The PCB does not have milling at the isolation border between the microcontroller side and the DALI bus interface It is advised to recheck the layout design to comply with the isolation requirements as specified in section 5 4 of Reference 1 AN11174 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 1 March 2012 12 of 29 NXP Semiconductors AN11174 AN11174 DALI slave using the LPC111x 2 4 Component list The list of components is given in Table 2 The oscillator circuit around C4 C5 and Q2 is listed as optional the microcontroller can also use its internal reference clock to generate its internal clock This is configurable by software The USB circuitry around components IC2 L1 X1 Q4 R15 R12 R14 R13 C8 and C9 is not mounted this part of the circuit only applies when the footprint of U2 is mounted with the pin compatible LPC1343 which is not the case for the OM13026 board Table 2 List of components Part ref Description Manufacturer Package Remarks B1 MB1S SOIC 4 C1 100nF 0805 C2 100nF 0805 C3 100nF 0805 C4 22pF 0805 optional C5 22pF 0805 optional C8 4u7
30. r usage with the DALI slave board OM13026 as depicted in Fig 1 er pave ieee e RS Fig 1 OM13026 LPC111x DALI Slave board The OM13026 board contains an example implementation of an isolated physical layer for the DALI bus with a Cortex MO LPC111x microcontroller for the DALI protocol handling and many I O functions to steer external lighting drivers for solid state or compact fluorescent lighting applications DALI This section briefly describes the Digital Addressable Lighting Interface DALI to understand the terms and concepts used in the other chapters of this document For more information on the DALI standard see References 1 2 and 3 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 1 March 2012 3 of 29 NXP Semiconductors AN1 1 1 14 DALI slave using the LPC111x 1 2 1 Bus structure DALI uses a wired bus structure to create a communication path between control devices switches or central gateways and control gear lighting units The topology is not specified it can be a star bus or point to point A ring structure is not allowed Fig 2 Example bus of control device and multiple control gear For installation purposes the DALI signal wiring can be combined with mains connections in one cable as shown in Fig 3 D PE q rn CU D L
31. ress Short addresses 0 63 Group addresses 0 15 Broadcast 11111115 Special command 101CCCC1 Special command 110CCCC1 address byte S selector bit 0 direct arc power level following command following short address Y short or group address group address or broadcast S S 1 Y 0 Y 1 A significant address bit C significant command bit Fig 8 DALI addressing types After the address byte a second byte follows the forward frame This second byte contains the direct arc power level for the ballast or a command byte depending on the selector bit There are four types of commands 1 Direct Indirect arc power control commands used to set ballast power level 2 Configuration commands configures the ballast for example add to a group or store level Command must be repeated within 100 ms otherwise it s ignored 3 Query commands ask slave ballast for status information for example power level or version number The slave can send a backward frame 4 Special commands used to initialize and setup the ballast some must be repeated within 100 ms and some require an answer from the slave Most commands are only processed within 15 minutes after an INITIALIZE command is received AN11174 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 1 March 2012 7 of 29
32. s applications or products or the application or use by customer s third party customer s Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer s NXP does not accept any liability in this respect Export control This document as well as the item s described herein may be subject to export control regulations Export might require a prior authorization from competent authorities Evaluation products This product is provided on an as is and with all faults basis for evaluation purposes only NXP Semiconductors its affiliates and their suppliers expressly disclaim all warranties whether express implied or statutory including but not limited to the implied warranties of non infringement merchantability and fitness for a particular purpose The entire risk as to the quality or arising out of the use or performance of this product remains with customer In no event shall NXP Semiconductors its affiliates or their suppliers be liable to customer for any special indirect consequential punitive or incidental damages including without limitation damages for loss of business business interruption loss of use loss of data or information and the like arising out the use of or inability to use the product whether
33. sh c All the files of the DALI component are located in the directory DALI The subdirectories inc and src contain the respective header files and source files The relationship between the files is given in Fig 13 gt depends implements 1 Filenames are prefixed with DALI_ except for DALI c and DALI h Fig 13 DALI component file structure All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 1 March 2012 15 of 29 NXP Semiconductors AN1 1 1 74 AN11174 3 3 DALI slave using the LPC111x The DALI h contains the global definitions used in the component It defines the external interfaces of the component and all type definition for the internal administration of the component All DALI component internal administration is held in a workspace that is used in all files For each physical interface called channel the administration holds the status of that channel and a compound of timer channel_config driver and device class in which timer is a reference to the timer capture unit in use for this interface channel_config holds the PIO port and pins of the interface driver is the internal interrupt driver workspace and device class holds all DALI device configuration information This setup makes it possible to create multiple logical DALI devices using the same physical bus interface Run time flow The
34. t can reasonably be expected to result in personal injury death or severe property or environmental damage NXP Semiconductors and its suppliers accept no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is at the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products and NXP AN11174 All information provided in this document is subject to legal disclaimers Semiconductors accepts no liability for any assistance with applications or customer product design It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned as well as for the planned application and use of customer s third party customer s Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products NXP Semiconductors does not accept any liability related to any default damage costs or problem which is based on any weakness or default in the customer
35. ther advanced functions of the OSAL The FreeRTOS version supports all the standard functions like queues All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 1 March 2012 14 of 29 NXP Semiconductors AN1 1 1 14 AN11174 DALI slave using the LPC111x semaphores threads and their scheduling The default configuration of the software is to not use an OS The applications example the main of the program is started on top of the OSAL and directly calls the DALI stack It does not provide any other services in the case the OSAL uses the OS less version In the case the OSAL maps to real OS the application layer can implement multiple applications using different threads 3 2 Component structure The DALI component is responsible for e receiving and transmitting DALI frames from the physical interface e acting upon received commands e driving the connected lighting unit e persistent storage of parameters The functions for the physical DALI bus interface for forward frame and backward frame transmission are bundled in the file DALI _PhysDriver c The physical drives passes the commands on to DALI c that executes a command handling loop The command parsing and backward frame information assembly is done in DALI_Commanas c The actual control of the ballast is done in DALI _Ballast c Storage of nonvolatile parameters is done using Fla
36. to measure the pulse width of the incoming DALI message the timer capture unit is set to a clock of 1 MHz Upon the first transition of the DALI1_RX line the timer counter is reset During each following DALI1_RX transition either to low or to high the ISR is triggered and the width of the pulse is measured using capture register 0 CRO A bitstream is generated of which the contents depend on the width of the pulse due to the Manchester encoding of the DALI bus signal After receiving 17 manchester encoded bits the ISR detects the stopbits with a duration of 4 Te using match register 2 MR2 When the ISR triggers on MR2 after 4 Te and there has been no DALI line activity the forward frame bi phase bits are put in the reception queue by the ISR for processing by the main loop Fig 15 illustrates the relation between the bus timing and the corresponding timer capture and match registers In use Command handling The main loop blocks until a bi phase encoded forward frame is put in the reception queue by the ISR It copies the forward frame and decodes it to a command with data This command is then parsed and the corresponding action is performed All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved Application note Rev 1 1 March 2012 17 of 29 NXP Semiconductors AN1 1 1 14 AN11174 3 4 4 3 4 5 3 5 DALI slave using the LPC111x Backward frame transmissi
37. w of the configuration options is given in Table 9 Table 9 Additional configuration options Configuration Description File location TE Bit length in microseconds DALI inc DALI h MIN_TE Minimal Te length DALI inc DALI h MAX_TE Maximal Te length DALI inc DALI h MIN_2TE Minimal length for 1 bit DALI inc DALI h MAX_2TE Maximal length for 1 bit DALI inc DALI h Nr of physical layer DALI inc DALI h MAX_DALI_CHANNELS interfaces MAX_DALI_DEVICES PER _CHANNEL Nr of control gear DALI inc DALI h Fade interpolation using DALI inc DALI_Ballast h USE_FADE_MR3_INTERRUPT PWM timer Fade interpolation using DALI inc DALI_Ballast h USE_FADE_INTERRUPT system timer PWM_OUTPUT_INVERTED inverts PWM outputs DALI inc DALI_Ballast h Various default DALI inc DALI_Ballast h DEFAULT_ control gear properties 3 10 Building the software The software tree includes project files for LPC Xpresso v4 0 6_151 When using LPCXpresso for building the DALI slave use the workspace location C nxp lighting DALlL_SDK_v1 0 as shown in Fig 16 r E Workspace Launcher 5S Select a workspace LPCXpresso stores your projects in a folder called a workspace Choose a workspace folder to use for this session Workspace SANESA a a E _ Use this as the default and do not ask again ee Fig 16 Start LPCXpresso and select the DALI SDK folder as workspace Use the quick link import existing project and select as ro
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