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MSP430x1xx Family User`s Guide (Rev. F)

1. cU Note Disable Interrupt If any code sequence needs to be protected from interruption the DINT should be executed at least one instruction before the beginning of the uninterruptible sequence or should be followed by a NOP instruction LLLLLLLLLL v RISC 16 Bit CPU 3 39 Instruction Set EINT Syntax Operation Emulation Description Status Bits Mode Bits Example Enable general interrupts EINT 19 GIE or 0008h OR SR SR src OR dst gt dst BIS 8 SR All interrupts are enabled The constant 08h and the status register SR are logically ORed The result is placed into the SR Status bits are not affected GIE is set OSCOFF and CPUOFF are not affected The general interrupt enable GIE bit in the status register is set Interrupt routine of ports P1 2 to P1 7 P1IN is the address of the register where all port bits are read P1IFG is the address of the register where all interrupt events are latched MaskOK PUSH B amp P1IN BIC B SP amp P1IFG Reset only accepted flags EINT Preset port 1 interrupt flags stored on stack other interrupts are allowed BIT Mask SP JEQ MaskOK Flags are present identically to mask jump BIC Mask SP INCD SP Housekeeping inverse to PUSH instruction at the start of interrupt subroutine Corrects
2. 2 0 0 c cece eee ees 18 2 4 Auto Power Down ssssssssssse teeta 18 2 5 Sample and Conversion Timing 00 cece eee teen eee 18 2 6 Conversion Modes 00 sussa sranna naarn s 18 2 7 ADC10 Data Transfer Controller illie eens 18 2 8 Using the Integrated Temperature Sensor 0 0000 eee eee ees 18 2 9 ADC10 Grounding and Noise Considerations 18 2 10 ADC10 Interrupts nessuna oea teenies 18 3 ADC10 Registers 19 DAC12 19 4 DAC12 Introduction sssusseseseee RR RR RR RR Ras 19 2 DAC12 Operation 19 21 DAGIZ CO uoo Binet RR i e e a TT weno r rebedbqertpe di ees 19 2 2 DAC12 Reference sssuussssssesssee nn 19 2 3 Updating the DAC12 Voltage Output 0 eee eee 19 2 4 DAC12 xDAT Data Format seessssesses ne 19 2 5 DAC12 Output Amplifier Offset Calibration 0000 eee eee eee 19 2 6 Grouping Multiple DAC12 Modules 0 0 e cece eee eee 19 2 7 DAC12 Int rruptS verime ces uu E Rex RR ee sess dee ta D TYPE baled 19 3 DAC12 Registers xii Chapter 1 Introduction This chapter describes the architecture of the MSP430 Topic Page Wao PATChiteCtinG e a cree eue nee eee mee ere eee 1 2 12 Flexible Clock System o lt sc220ca ceca roux esses IEEE NR ES 1 2 1 3 EmbeddediEmulationigs ore III 1 3 uch Address Space peccosnposnns seeacechaokeoognopancnespapeounede
3. USART Peripheral Interface IC Mode 12C Module Operation 15 2 7 Using the I2C Module with Low Power Modes The I2C module can be used with MSP430 low power modes When the internal clock source for the I2C module is present the module operates normally regardless of the MSP430 operating mode When the internal clock source for the I2C module is not present automatic clock activation is provided When the 12C module is in the idle state I2CBUSY 0 and the 12C clock source I2CIN is disconnected from the I2C module state machine saving power When the 12C clock source is inactive the 12C module automatically activates the selected clock source when needed regardless of the control bit settings for the clock source The clock source remains active until the 12C module returns to idle condition After the 12C module returns to the idle condition control of the clock source reverts to the settings of its control bits Automatic I2C clock activation occurs when In master mode clock activation occurs when I2CSTT 1 and remains active until the transfer completes and the 12C module returns to the idle condition In slave mode clock activation occurs when a START condition is detected and remains active until the transfer completes and the 12C module returns to the idle condition After detection of the START condition the STTIFG flag is set and the module holds the SCL line low until the clock source becomes active On
4. Error handler start ipid Continue with normal program flow Branch to STL2 if byte STATUS contains 1 or 0 CMP B 2 STATUS JLO STL2 STATUS lt 2 M STATUS 2 2 continue here 3 50 RISC 16 Bit CPU JNE JNZ Syntax Operation Description Status Bits Example Instruction Set Jump if not equal Jump if not zero JNE label JNZ label If Z 0 PC 2 x offset gt PC If Z 1 execute following instruction The status register zero bit Z is tested If it is reset the 10 bit signed offset contained in the instruction LSBs is added to the program counter If Z is set the next instruction following the jump is executed Status bits are not affected Jump to address TONI if R7 and R8 have different contents CMP R7 R8 COMPARE R7 WITH R8 JNE TONI if different jump ME if equal continue RISC 16 Bit CPU 3 51 Instruction Set MOV W MOV B Syntax Operation Description Status Bits Mode Bits Example Loop Example Loop Move source to destination Move source to destination MOV src dst or MOV W src dst MOV B src dst src gt dst The source operand is moved to the destination The source operand is not affected The previous contents of the destination are lost Status bits are not affected OSCOFF CPUOFF and GIE are not affected The contents of table EDE word data are copied to table TOM The length of the tables must be 020h locations MOV EDE R10 Pr
5. SOMI Slave out master in Master mode SOMI is the data input line Slave mode SOMI is the data output line J UCLK USART SPI clock Master mode UCLK is an output Slave mode UCLK is an input STE Slave transmit enable Used in 4 pin mode to allow multiple masters on a single bus Not used in 3 pin mode 4 Pin master mode When STE is high SIMO and UCLK operate normally When STE is low SIMO and UCLK are set to the input direction 4 pin slave mode When STE is high RX TX operation of the slave is disabled and SOMI is forced to the input direction When STE is low RX TX operation of the slave is enabled and SOMI operates normally 14 2 1 USART Initialization and Reset 14 4 The USART is reset by a PUC or by the SWRST bit After a PUC the SWRST bit is automatically set keeping the USART in a reset condition When set the SWRST bit resets the URXIEx UTXIEx URXIFGx OE and FE bits and sets the UTXIFGx flag The USPIEx bit is not altered by SWRST Clearing SWRST releases the USART for operation See also chapter USART Module I2C mode for USARTO when reconfiguring from 12C mode to SPI mode V7 Note Initializing or Re Configuring the USART Module The required USART initialization re configuration process is 1 Set SWRST BIS B SWRST amp UxCTL 2 Initialize all USART registers with SWRST 1 including UxCTL 3 Enable USART module via the MEx SFRs USPIEx 4 Clear SWRST via software BIC B SWRST amp Ux
6. I2CBB Is Set XA 1 I2CSTT Is Cleared 8x SCL Send Slave Address No ACK Bits 9 8 Extended XA 0 with R W 0 8x SCL 8 x SCL Send Slave Address Bits 6 0 NACKIFG Is Set Send Slave Address e ou its 7 I2CBUSY Is Cleared with R W 0 Bits 7 0 Ack C NOME Ack Ack I2CRM 0 Yes DM I2CNDAT Repeat Mode Number Of Bytes STOP State Sent I2CRM 1 No No I2CDR Empty Yes I2CSTP 1 Yes STOP State I2CDR Loaded 10 x I2CPSC No Generate STOP No No Yes 8xgsci 2CDR Written 8 x l2CPSC Send I2CDR C I2CBB Is Cleared Low Byte Ack No Ack 8 x I2CPSC v Beck f2CSTP I2CMST Ack and Are Cleared I2CWORD 0 IDLE I2CBUSY Is Cleared C aJ USART Peripheral Interface IC Mode 15 9 12C Module Operation Figure 15 9 Master Receiver Mode 15 10 Yes I2CSTT 1 4 x l2CPSC T 8 x I2CPSC I2CBB Is Set I2CSTT Is Cleared XA 1 8x SCL Send Slave Address Bits 9 8 Extended With RAW 0 XA 0 8x SCL No Ack Send Slave Address Bits 7 0 NACKIFG Is Set 4 x l2CPSC No Generate 2nd START IDLE I2CBUSY Is Cleared Send Slave Send Slave Address J Address Bits 6 0 Bits 9 8 Extended with R W 1 With RW 1 Repeat Mode I2CNDAT l2CRM 1 Number Of Bytes Received STOP State Ye 1x SCL No No B STOP State Y ecieterPed 10 x l2CPSC Generate STOP I2CW
7. Timer A 11 9 Timer_A Operation Changing the Period Register TACCRO Use of the Up Down Figure 11 9 OFFFFh TACCRO TACCR1 TACCR2 Oh 11 10 Timer_A TAIFG When changing TACCRO while the timer is running and counting in the down direction the timer continues its descent until it reaches zero The new period takes affect after the counter counts down to zero When the timer is counting in the up direction and the new period is greater than or equal to the old period or greater than the current count value the timer counts up to the new period before counting down When the timer is counting in the up direction and the new period is less than the current count value the timer begins counting down However one additional count may occur before the counter begins counting down Mode The up down mode supports applications that require dead times between output signals See section Timer_A Output Unit For example to avoid overload conditions two outputs driving an H bridge must never be in a high state simultaneously In the example shown in Figure 11 9 the tgeag is tdead ttimer X TACCR1 TACCR2 With tdead Time during which both outputs need to be inactive ttimer Cycle time of the timer clock TACCRx Content of capture compare register x The TACCRx registers are not buffered They update immediately when written to Therefore any required dead time will not be maintained automatically Output Unit i
8. 5 0 t Does not apply to MSP430x12xx devices See IE2 for the MSP430x12xx USARTO interrupt enable bits IE2 Interrupt Enable Register 2 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 Bits These bits may be used by other modules See device specific datasheet 7 6 UTXIE1 Bit 5 USART1 transmit interrupt enable This bit enables the UTXIFG1 interrupt 0 Interrupt not enabled 1 Interrupt enabled URXIE1 Bit 4 USART1 receive interrupt enable This bit enables the URXIFG1 interrupt 0 Interrupt not enabled 1 Interrupt enabled Bits These bits may be used by other modules See device specific datasheet 3 2 14 20 USART Peripheral Interface SPI Mode USART Registers SP Mode UTXIEOt Bit 1 USARTO transmit interrupt enable This bit enables the UTXIFGO interrupt 0 Interrupt not enabled 1 Interrupt enabled URXIEOt Bit 0 USARTO receive interrupt enable This bit enables the URXIFGO interrupt for USARTO 0 Interrupt not enabled 1 Interrupt enabled t MSP430x12xx devices only USART Peripheral Interface SPI Mode 14 21 USART Registers SPI Mode IFG1 Interrupt Flag Register 1 7 6 5 4 3 2 1 0 rw 1 rw 0 UTXIFGOT URXIFGOT Bit 7 Bit 6 Bits 5 0 USARTO transmit interrupt flag UTXIFGO is set when UOTXBUF is empty 0 No interrupt pending 1 Interrupt pending USARTO receive interrupt flag URXIFGO is set when UORXBUF has received a complete character 0 No interrupt pending 1 Interrupt pending These bits may be used by othe
9. OICSOOIQ Timer B is configurable to operate as an 8 10 12 or 16 bit timer with the CNTLx bits The maximum count value TBR max for the selectable lengths is OFFh O3FFh OFFFh and OFFFFh respectively Data written to the TBR register in 8 10 and 12 bit mode is right justified with leading zeros Clock Source Select and Divider 12 4 Timer B The timer clock can be sourced from ACLK SMCLK or externally via TBCLK or INCLK The clock source is selected with the TBSSELx bits The selected clock source may be passed directly to the timer or divided by 2 4 or 8 using the IDx bits The clock divider is reset when TBCLR is set Timer_B Operation 12 2 2 Starting the Timer The timer may be started or restarted in the following ways The timer counts when MCx gt 0 and the clock source is active When the timer mode is either up or up down the timer may be stopped by loading 0 to TBCLO The timer may then be restarted by loading a nonzero value to TBCLO In this scenario the timer starts incrementing in the up direction from zero 12 2 3 Timer Mode Control The timer has four modes of operation as described in Table 12 1 stop up continuous and up down The operating mode is selected with the MCx bits Table 12 1 Timer Modes MCx Mode Description 00 Stop The timer is halted 01 Up The timer repeatedly counts from zero to the value of compare register TBCLO 10 Continuous The timer repeatedly cou
10. EINT Enable interrupts 5 6 Flash Memory Controller Initiating an Erase from RAM Flash Memory Operation Any erase cycle may be initiated from RAM In this case the CPU is not held and can continue to execute code from RAM The BUSY bit must be polled to determine the end of the erase cycle before the CPU can access any flash address again If a flash access occurs while BUSY 1 it is an access violation ACCVIFG will be set and the erase results will be unpredictable The flow to initiate an erase from RAM is shown in Figure 5 6 Figure 5 6 Erase Cycle from Within RAM Disable all interrupts and watchdog Set LOCK 1 re enable interrupts and watchdog Segment Erase from RAM Assumes ACCVIE WDTPW WDTHOLD amp WDTCTL MOV DINT BIT JNZ MOV MOV MOV CLR BIT JNZ MOV L1 L2 EINT NMIIE OFIE BUSY amp FCTL3 L1 FWKEY FSSEL1 FNO amp FCTL2 FWKEY amp FCTL3 FWKEY ERASE amp FCTL1 amp 0FC10h BUSY amp FCTL3 L2 FWKEY LOCK amp FCTL3 Flash Memory Controller 514 kHz lt 0 SMCLK 952 kHz Disable WDT Disable interrupts Test BUSY Loop while busy SMCLK 2 Clear LOCK Enable erase Dummy write erase S1 Test BUSY Loop while busy Done set LOCK Re enable WDT Enable interrupts 5 7 Flash Memory Operation 5 3 3 Writing Flash Memory The write modes selected by the WRT and BLKWRT bits are listed in Table 5 1 Table 5 2 Write Modes Byte Wo
11. Note RLA Substitution The assembler does not recognize the instruction RLA R5 RLA B R5 or RLA B R5 It must be substituted by ADD R5 2 R5 ADD B R5 1 R5 or ADD B R5 3 58 RISC 16 Bit CPU RLC W RLC B Syntax Operation Emulation Description Instruction Set Rotate left through carry Rotate left through carry RLC dst or RLC W dst RLC B dst C lt MSB lt MSB 1 LSB 1 lt LSB lt C ADDC dst dst The destination operand is shifted left one position as shown in Figure 3 15 The carry bit C is shifted into the LSB and the MSB is shifted into the carry bit C Figure 3 15 Destination Operand Carry Left Shift Status Bits Mode Bits Example Example Example 0 eee E Byte 7 0 Set if result is negative reset if positive Set if result is zero reset otherwise Loaded from the MSB Set if an arithmetic overflow occurs the initial value is 04000h lt dst lt 0C000h reset otherwise Set if an arithmetic overflow occurs the initial value is 040h lt dst lt OCOh reset otherwise OSCOFF CPUOFF and GIE are not affected R5 is shifted left one position RLC R5 R5 x 2 C gt R5 The input P11N 1 information is shifted into the LSB of R5 BIT B 2 amp P1IN Information Carry RLC R5 Carry P0in 1 gt LSB of R5 The MEM LEO content is shifted left one position RLC B LEO Mem LEO x 2 C gt Mem LEO Note RLC and RLC
12. 0 DMAABORT 2 x MCLI ENNMI 1 AND NMI event OR DMALEVEL 1 AND Trigger 0 DMAABORT 0 0 DMAEN 1 DMAxSZ T Size DMAxSA T SourceAdd DMAxDA T DestAdd 1 DMA Operation DMAREQ 0 T Size 2 DMAxSZ Wait for Trigger K Hold CPU Transfer one word byte Decrement DMAxSZ Modify T SourceAdd DMAxSA T SourceAdd DMAxDA T DestAdd Trigger 1 AND DMALEVEL 1 DMAxSZ gt 0 DMADTx 5 AND DMAxSZ 0 Trigger AND DMALEVEL 0 ANDDMREN OR Modify T_DestAdd DMA Controller 8 9 DMA Operation Burst Block Transfers In burst block mode transfers are block transfers with CPU activity interleaved The CPU executes 2 MCLK cycles after every four byte word transfers of the block resulting in 20 CPU execution capacity After the burst block CPU execution resumes at 100 capacity and the DMAEN bit is cleared DMAEN must be set again before another burst block transfer can be triggered After a burst block transfer has been triggered further trigger signals occurring during the burst block transfer are ignored The burst block transfer state diagram is shown in Figure 8 5 The DMAxSZ register is used to define the size of the block and the DMADSTINCRx and DMASRCINCR x bits select if the destination address and the source address are incremented or decremented after each transfer of the block If DMAxSZ 0 no transfers occur The
13. 00004h 00008h 00000h 00001h 00002h OFFFFh No special instructions required Remarks Register mode Absolute address mode 4 bit processing 8 bit processing 0 word processing 1 2 bit processing 1 word processing No additional code word for the six constants No code memory access required to retrieve the constant The assembler uses the constant generator automatically if one of the six constants is used as an immediate source operand Registers R2 and R3 used in the constant mode cannot be addressed explicitly they act as source only registers Constant Generator Expanded Instruction Set The RISC instruction set of the MSP430 has only 27 instructions However the constant generator allows the MSP430 assembler to support 24 additional emulated instructions For example the single operand instruction CLR dst is emulated by the double operand instruction with the same length MOV R3 dst where the 0 is replaced by the assembler and R3 is used with As 00 INC is replaced by ADD dst 0 R3 dst RISC 16 Bit CPU 3 7 CPU Registers 3 2 5 General Purpose Registers R4 R15 The twelve registers RA R15 are general purpose registers All of these registers can be used as data registers address pointers or index values and can be accessed with byte or word instructions as shown in Figure 3 7 Figure 3 7 Register Byte Byte Register Operations Register Byte Operation
14. ADC10 18 29 ADC10 Registers ADC10DTCO Data Transfer Control Register 0 7 ro Reserved ADC10TB ADC10CT ADC10B1 ADC10 FETCH 18 30 6 ro Bits 7 4 Bit 3 Bit 2 Bit 1 Bit 0 ADC10 5 4 3 2 1 0 ADC10 rw 0 rw 0 rw 0 rw 0 ro ro Reserved Always read as 0 ADC10 two block mode 0 One block transfer mode 1 Two block transfer mode ADC10 continuous transfer 0 Data transfer stops when one block one block mode or two blocks two block mode have completed 1 Data is transferred continuously DTC operation is stopped only if ADC10CT cleared or ADC10SA is written to ADC10 block one This bit indicates for two block mode which block is filled with ADC10 conversion results ADC10B1 is valid only after ADC10IFG has been set the first time during DTC operation ADC10TB must also be set 0 Block 2 is filled 1 Block 1 is filled This bit should normally be reset ADC10 Registers ADC10DTC1 Data Transfer Control Register 1 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 DTC Bits DTC transfers These bits define the number of transfers in each block Transfers 7 0 0 DTC is disabled O1h OFFh Number of transfers per block ADC10SA Start Address Register for Data Transfer ADC10SAx Bits ADC10 start address These bits are the start address for the DTC A write 15 1 to register ADC10SA is required to initiate DTC transfers Unused Bit 0 Unused Read on
15. Internal MUX on input resistance C Input capacitance Ci Vc Capacitance charging voltage The resistance of the source Rg and R4 affect tsample The following equation can be used to calculate the minimum sampling time tsample for a 12 bit conversion t Rg R x In 213 x C 800ns sample Substituting the values for Rj and C given above the equation becomes tsample gt Rg 2K9 x 9 011 x 40pF 800ns For example if Rg is 10 KQ tsample must be greater than 5 13 us ADC12 17 9 ADC 12 Operation 17 2 6 Conversion Memory There are 16 ADC12MEMXx conversion memory registers to store conversion results Each ADC12MEM x is configured with an associated ADC12MCTLx control register The SREFx bits define the voltage reference and the INCHx bits select the input channel The EOS bit defines the end of sequence when a sequential conversion mode is used A sequence rolls over from ADC12MEM15 to ADC12MEMO when the EOS bit in ADC12MCTL15 is not set The CSTARTADDx bits define the first ADC12MCTLx used for any conversion If the conversion mode is single channel or repeat single channel the CSTARTADDx points to the single ADC12MCTLx to be used If the conversion mode selected is either sequence of channels or repeat sequence of channels CSTARTADDx points to the first ADC12MCTLx location to be used in a sequence A pointer not visible to software is incremented automatically to the next ADC12MCTLx in a sequence wh
16. Unused Read only Always read as 0 Capture mode 0 Compare mode 1 Capture mode Output mode Modes 2 3 6 and 7 are not useful for TACCRO because EQUx EQUO 000 OUT bit value 001 Set 010 Toggle reset 011 Set reset 100 Toggle 101 Reset 110 Toggle set 111 Reset set CCIE Bit 4 CCl Bit 3 OUT Bit 2 COV Bit 1 CCIFG Bit 0 Timer A Registers Capture compare interrupt enable This bit enables the interrupt request of the corresponding CCIFG flag 0 Interrupt disabled 1 Interrupt enabled Capture compare input The selected input signal can be read by this bit Output For output mode 0 this bit directly controls the state of the output 0 Output low 1 Output high Capture overflow This bit indicates a capture overflow occurred COV must be reset with software 0 No capture overflow occurred 1 Capture overflow occurred Capture compare interrupt flag 0 No interrupt pending 1 Interrupt pending TAIV Timer A Interrupt Vector Register ro 7 15 14 13 12 11 10 9 8 ro ro ro ro ro ro ro 5 4 3 2 1 0 ro ro ro ro r 0 r 0 r 0 ro TAIVx Bits Timer A Interrupt Vector value 15 0 Interrupt TAIV Contents Interrupt Source Interrupt Flag Priority 00h No interrupt pending 02h Capture compare 1 TACCR1 CCIFG Highest 04h Capture compare 2 TACCR2 CCIFG 06h Reserved 08h Reserved OAh Timer overflow TAIFG OCh Reserved OEh Reserved Lowest Timer A 11 23 Chapter 12 Timer B Timer B is a
17. 0123h POP R8 Oxxxh Oxxxh 2 Oxxxh 4 Oxxxh 6 Oxxxh 8 SP The special cases of using the SP as an argument to the PUSH and POP instructions are described and shown in Figure 3 5 Figure 3 5 PUSH SP POP SP Sequence PUSH SP SPoid SP4 SP4 POP SP SP2 SP4 The stack pointer is changed after The stack pointer is not changed after a POP SP a PUSH SP instruction instruction The POP SP instruction places SP1 into the stack pointer SP SP2 SP1 RISC 16 Bit CPU 3 5 CPU Registers 3 2 3 Status Register SR The status register SR R2 used as a source or destination register can be used in the register mode only addressed with word instructions The remain ing combinations of addressing modes are used to support the constant gen erator Figure 3 6 shows the SR bits Figure 3 6 Status Register Bits 15 9 8 7 0 OSC CPU rw n Table 3 1 describes the status register bits Table 3 1 Description of Status Register Bits Bit V SCG1 SCGO OSCOFF CPUOFF GIE N 3 6 RISC 16 Bit CPU Description Overflow bit This bit is set when the result of an arithmetic operation overflows the signed variable range Set when Positive Positive Negative Negative Negative Positive otherwise reset ADD B ADDC B Set when Positive Negative Negative Negative Positive Positive otherwise reset SUB B SUBC B CMP B System clock generator 1 T
18. ACLK is software selectable for individual peripheral modules J MCLK Master clock MCLK is software selectable as LFXT1CLK XT2CLK if available or DCOCLK MCLK is divided by 1 2 4 or 8 MCLK is used by the CPU and system SMCLK Sub main clock SMCLK is software selectable as LFXT1CLK XT2CLK if available on chip or DCOCLK SMCLK is divided by 1 2 4 or 8 SMCLK is software selectable for individual peripheral modules The block diagram of the basic clock module is shown in Figure 4 1 Basic Clock Module Figure 4 1 Basic Clock Block Diagram LFXT1CLK Basic Clock Module Introduction DIVAx Divider LI OSCOFF XT1 Off 1 2 4 8 ACLK Auxillary Clock SELMx DIVMx CPUOFF Divider 1 2 4 8 1 XT2CLK XT20FF XT2IN L C XT2OUT XT2 Oscillator m MODx DCOR SCGO RSELx off DC Generator P2 5 Rosc MCLK Main System Clock SELS DIVSx Divider 1 2 4 8 Sub System Clock Note XT2 Oscillator The XT2 Oscillator is not present on MSP430x11xx or MSP430x12xx devices The LFXT1CLK is used in place of XT2CLK Basic Clock Module 4 3 Basic Clock Module Operation 4 2 Basic Clock Module Operation 4 2 1 4 4 After a PUC MCLK and SMCLK are sourced from DCOCLK at 800 kHz see device specific datasheet for
19. Architecture 1 1 Architecture The MSP430 incorporates a 16 bit RISC CPU peripherals and a flexible clock system that interconnect using a von Neumann common memory address bus MAB and memory data bus MDB Partnering a modern CPU with modular memory mapped analog and digital peripherals the MSP430 offers solutions for demanding mixed signal applications Key features of the MSP430x1xx family include Ultralow power architecture extends battery life BI 0 1 uA RAM retention B 0 8 uA real time clock mode mM 250 uA MIPS active High performance analog ideal for precision measurement 12 bit or 10 bit ADC 200 ksps temperature sensor Vner B 12 bit dual DAC B Comparator gated timers for measuring resistive elements B Supply voltage supervisor 16 bit RISC CPU enables new applications at a fraction of the code size B Large register file eliminates working file bottleneck mM Compact core design reduces power consumption and cost B Optimized for modern high level programming B Only 27 core instructions and seven addressing modes B Extensive vectored interrupt capability In system programmable Flash permits flexible code changes field upgrades and data logging 1 2 Flexible Clock System The clock system is designed specifically for battery powered applications A low frequency auxiliary clock ACLK is driven directly from a common 32 kHz watch crystal The ACLK can be used for a background real time clock s
20. Bit 6 Bit 5 Bit 4 ADC120VIE Bit 3 ADC12 TOVIE ENC ADC12SC 17 22 Bit 2 Bit 1 Bit 0 ADC12 Multiple sample and conversion Valid only for sequence or repeated modes The sampling timer requires a rising edge of the SHI signal to trigger each sample and conversion 1 The first rising edge of the SHI signal triggers the sampling timer but further sample and conversions are performed automatically as soon as the prior conversion is completed Reference generator voltage REFON must also be set 0 15V 1 2 5V Reference generator on 0 Reference off 1 Reference on ADC12 on 0 ADC12 off 1 ADC12 on ADC12MEMXx overflow interrupt enable The GIE bit must also be set to enable the interrupt 0 Overflow interrupt disabled 1 Overflow interrupt enabled ADC12 conversion time overflow interrupt enable The GIE bit must also be set to enable the interrupt 0 Conversion time overflow interrupt disabled 1 Conversion time overflow interrupt enabled Enable conversion 0 ADC12 disabled 1 ADC12 enabled Start conversion Software controlled sample and conversion start ADC12SC and ENC may be set together with one instruction ADC12SC is reset automatically 0 No sample and conversion start 1 Start sample and conversion ADC 12 Registers ADC12CTL1 ADC12 Control Register 1 15 14 13 12 11 10 9 8 rw 0 rw 0 7 6 rw 0 rw 0 rw 0 rw 0 rw 0 5 4 3 2 1 rw 0 0 ADC12 rw 0 rw 0
21. Comparator_A Control Register 1 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 CAEX Bit 7 Comparator_A exchange This bit exchanges the comparator inputs and inverts the comparator output CARSEL Bit 6 Comparator A reference select This bit selects which terminal the VcAREF is applied to When CAEX 0 0 VCAREF is applied to the terminal VCAREF S applied to the terminal When CAEX 1 0 VCAREF S applied to the terminal 1 VCAREF is applied to the terminal CAREF Bits Comparator A reference These bits select the reference voltage VcAnEF 5 4 00 Internal reference off An external reference can be applied 01 0 25 Vcc 10 0 50 Vcc 11 Diode reference is selected CAON Bit 3 Comparator_A on This bit turns on the comparator When the comparator is off it consumes no current The reference circuitry is enabled or disabled independently 0 Off 1 On CAIES Bit 2 Comparator_A interrupt edge select 0 Rising edge 1 Falling edge CAIE Bit 1 Comparator A interrupt enable 0 Disabled 1 Enabled CAIFG Bit 0 The Comparator_A interrupt flag 0 No interrupt pending 1 Interrupt pending 16 10 Comparator A Comparator_A Registers CACTL2 Comparator_A Control Register 7 6 5 4 3 2 1 0 o mem 00 few ime car caour rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 r 0 Unused Bits Unused 7 4 P2CA1 Bit 3 Pin to CA1 This bit selects the CA1 pin function 0 The pin is not connected to CA1
22. DC Generator Off SCG1 SCGO OSCOFF CPUOFF Mode CPU and Clocks Status 0 Active CPU is active all enabled clocks are active LPMO CPU MCLK are disabled SMCLK ACLK are active 0 1 0 1 LPM1 CPU MCLK DCO osc are disabled DC generator is disabled if the DCO is not used for MCLK or SMCLK in active mode SMCLK ACLK are active 1 0 0 1 LPM2 CPU MCLK SMCLK DCO osc are disabled DC generator remains enabled ACLK is active 1 1 0 1 LPM3 CPU MCLK SMCLK DCO osc are disabled DC generator disabled ACLK is active 1 1 1 1 LPM4 CPU and all clocks disabled System Resets Interrupts and Operating Modes 2 15 Operating Modes 2 3 1 Entering and Exiting Low Power Modes An enabled interrupt event wakes the MSP430 from any of the low power operating modes The program flow is Enter interrupt service routine m The PC and SR are stored on the stack B The CPUOFF SCG1 and OSCOFF bits are automatically reset Options for returning from the interrupt service routine B The original SR is popped from the stack restoring the previous operating mode B The SR bits stored on the stack can be modified within the interrupt service routine returning to a different operating mode when the RETI instruction is executed Enter LPMO Example BIS GIE CPUOFF SR Enter LPMO 2 uad Program stops here Exit LPMO Interrupt Service Routine BIC CPUOFF 0 SP Exit LPMO on RETI RETI Enter LPM3 Example BIS GIE CPUOFF SCG1
23. Interrupt Service Requested IRACC Interrupt Request Accepted TBIV Interrupt Vector Generator 12 18 Timer B The TBIFG flag and TBCCRx CCIFG flags excluding TBCCRO CCIFG are prioritized and combined to source a single interrupt vector The interrupt vector register TBIV is used to determine which flag requested an interrupt The highest priority enabled interrupt excluding TBCCRO CCIFG generates a number in the TBIV register see register description This number can be evaluated or added to the program counter to automatically enter the appropriate software routine Disabled Timer B interrupts do not affect the TBIV value Any access read or write of the TBIV register automatically resets the highest pending interrupt flag If another interrupt flag is set another interrupt is immediately generated after servicing the initial interrupt For example if the TBCCR1 and TBCCR2 CCIFG flags are set when the interrupt service routine accesses the TBIV register TBCCR1 CCIFG is reset automatically After the RETI instruction of the interrupt service routine is executed the TBCCR2 CCIFG flag will generate another interrupt Timer_B Operation TBIV Interrupt Handler Examples The following software example shows the recommended use of TBIV and the handling overhead The TBIV value is added to the PC to automatically jump to the appropriate routine The numbers at the right margin show the necessary CPU clock cycles for each
24. Li Resetting ENC during a sequence or repeat sequence mode stops the converter at the end of the sequence L Any conversion mode may be stopped immediately by setting the CONSEQx 0 and resetting the ENC bit Conversion data is unreliable 18 14 ADC10 ADC10 Operation 18 2 7 ADC10 Data Transfer Controller The ADC10 includes a data transfer controller DTC to automatically transfer conversion results from ADC10MEM to other on chip memory locations The DTC is enabled by setting the ADC10DTC1 register to a nonzero value When the DTC is enabled each time the ADC10 completes a conversion and loads the result to ADC10MEM a data transfer is triggered No software intervention is required to manage the ADC10 until the predefined amount of conversion data has been transferred Each DTC transfer requires one CPU MCLK To avoid any bus contention during the DTC transfer the CPU is halted if active for the one MCLK required for the transfer A DTC transfer must not be initiated while the ADC10 is busy Software must ensure that no active conversion or sequence is in progress when the DTC is configured ADC10 activity test BIC W ENC amp ADC10CTLO busy test BIT W BUSY amp ADC10CTL1 JNZ busy test MOV W dxxx amp ADC10SA Safe MOV B xx amp ADC1ODTC1 continue setup ADC10 18 15 ADC10 Operation One Block Transfer Mode The one block mode is selected if the ADC10TB is reset The value n in ADC10DTC1 defines t
25. RISC 16 Bit CPU 3 27 Instruction Set BR BRANCH Syntax Operation Emulation Description Status Bits Example Branch to destination BR dst dst gt PC MOV dst PC An unconditional branch is taken to an address anywhere in the 64K address space All source addressing modes can be used The branch instruction is a word instruction Status bits are not affected Examples for all addressing modes are given BR EXEC Branch to label EXEC or direct branch e g 0A4h Core instruction MOV PC PC BR EXEC Branch to the address contained in EXEC Core instruction MOV X PC PC Indirect address BR amp EXEC Branch to the address contained in absolute address EXEC Core instruction MOV X 0 PC Indirect address BR R5 Branch to the address contained in R5 Core instruction MOV R5 PC Indirect R5 BR R5 Branch to the address contained in the word pointed to by R5 Core instruction MOV R5 PC Indirect indirect R5 BR R5 Branch to the address contained in the word pointed to by R5 and increment pointer in R5 afterwards The next time S W flow uses R5 pointer it can alter program execution due to access to next address in a table pointed to by R5 Core instruction MOV R5 PC Indirect indirect R5 with autoincrement BR X R5 Branch to the address contained in the address pointed to by R5 X e g table with address starting at X X can be an address or a
26. RRA B SP TOS x 0 5 0 5 x R5 x 0 5 0 25 x R5 gt TOS ADD B SP R5 R5x0 5 R5 x 0 25 0 75 x R5 gt R5 3 60 RISC 16 Bit CPU RRC W RRC B Syntax Operation Description Instruction Set Rotate right through carry Rotate right through carry RRC dst or RRC W dst RRC dst C gt MSB gt MSB 1 LSB 1 gt LSB gt C The destination operand is shifted right one position as shown in Figure 3 17 The carry bit C is shifted into the MSB the LSB is shifted into the carry bit C Figure 3 17 Destination Operand Carry Right Shift Status Bits Mode Bits Example Example Word 15 0 mugs Byte 7 0 Setif result is negative reset if positive Set if result is zero reset otherwise Loaded from the LSB Reset SON OSCOFF CPUOFF and GIE are not affected R5 is shifted right one position The MSB is loaded with 1 SETC Prepare carry for MSB RRC R5 R5 2 8000h gt R5 R5 is shifted right one position The MSB is loaded with 1 SETC Prepare carry for MSB RRC B R5 R5 2 80h gt R5 low byte of R5 is used RISC 16 Bit CPU 3 61 Instruction Set SBC W SBC B Syntax Operation Emulation Description Status Bits Mode Bits Example Example Subtract source and borrow NOT carry from destination Subtract source and borrow NOT carry from destination SBC dst or SBC W dst SBC B dst dst OFFFFh C gt dst dst OFFh C dst SUBC 0 d
27. TBCCR1 CLLDXx bits control the update TBCL3 TBCL4 TBCCR3 CLLDx bits control the update TBCL5 TBCL6 TBCCR5 CLLDx bits control the update TBCLO independent 10 TBCL1 TBCL2 TBCL3 TBCCR1 CLLDx bits control the update TBCL4 TBCL5 TBCL6 TBCCR4 CLLDx bits control the update TBCLO independent 11 TBCLO TBCL1 TBCL2 TBCL3 TBCL4 TBCL5 TBCL6 TBCCR1 CLLDx bits control the update CNTLx Bits Counter Length 12 11 00 16 bit TBR max OFFFFh 01 12 bit TBR may OFFFh 10 10 bit TBR max O3FFh 11 8 bit TBR max OFFh Unused Bit 10 Unused TBSSELx Bits Timer B clock source select 9 8 00 TBCLK 01 ACLK 10 SMCLK 11 Inverted TBCLK IDx Bits Input divider These bits select the divider for the input clock 7 6 00 1 01 2 10 4 11 4 8 MCx Bits Mode control Setting MCx 00h when Timer B is not in use conserves 5 4 power 00 Stop mode the timer is halted 01 Up mode the timer counts up to TBCLO 10 Continuous mode the timer counts up to the value set by TBCNTLx 11 Up down mode the timer counts up to TBCLO and down to 0000h Timer B 12 21 Timer_B Registers Unused Bit 3 Unused TBCLR Bit 2 Timer_B clear Setting this bit resets TBR the clock divider and the count direction The TBCLR bit is automatically reset and is always read as zero TBIE Bit 1 Timer_B interrupt enable This bit enables the TBIFG interrupt request 0 Interrupt disabled 1 Interrupt enabled TBIFG Bit 0 Timer_B interrupt flag 0 No interrupt pending 1
28. When VLDx 1111 the external SVSIN channel is selected The voltage on SVSIN is compared to an internal level of approximately 1 2 V 6 2 2 SVS Comparator Operation A low voltage condition exists when AVcc drops below the selected threshold or when the external voltage drops below its 1 2 V threshold Any low voltage condition sets the SVSFG bit The PORON bit enables or disables the device reset function of the SVS If PORON 1 a POR is generated when SVSFG is set If PORON 0 a low voltage condition sets SVSFG but does not generate a POR The SVSFG bit is latched This allows user software to determine if a low voltage condition occurred previously The SVSFG bit must be reset by user software If the low voltage condition is still present when SVSFG is reset it will be immediately set again by the SVS 6 4 Supply Voltage Supervisor SVS Operation 6 2 3 Changing the VLDx Bits When the VLDx bits are changed two settling delays are implemented to allows the SVS circuitry to settle During each delay the SVS will not set SVSFG The delays tq svSon and tsettle are shown in Figure 6 2 The ta SVSon delay takes affect when VLDx is changed from zero to any non zero value and is a approximately 50 us The tserje delay takes affect when the VLDx bits change from any non zero value to any other non zero value and is a maximum of 12 us See the device specific datasheet for the delay parameters During the delays the SVS will
29. When the output amplifier has a positive offset a digital inout of zero does not result in a zero output voltage The DAC12 output voltage reaches the maximum output level before the DAC12 data reaches the maximum code This is shown in Figure 19 5 Figure 19 5 Positive Offset Output Voltage eo DAC Data Full Scale Code The DAC12 has the capability to calibrate the offset voltage of the output amplifier Setting the DAC12CALON bit initiates the offset calibration The calibration should complete before using the DAC12 When the calibration is complete the DAC12CALON bit is automatically reset The DAC12AMPx bits should be configured before calibration For best calibration results port and CPU activity should be minimized during calibration DAC12 19 7 DAC 12 Operation 19 2 6 Grouping Multiple DAC12 Modules Multiple DAC12s can be grouped together with the DAC12GRP bit to synchronize the update of each DAC12 output Hardware ensures that all DAC12 modules in a group update simultaneously independent of any interrupt or NMI event On the MSP430x15x and MSP430x16x devices DAC12_0 and DAC12_1 are grouped by setting the DAC12GRP bit of DAC12_0 The DAC12GRP bit of DAC12_1 is don t care When DAC12 0 and DAC12_1 are grouped Li The DAC12 1 DAC12LSELx bits select the update trigger for both DACs The DAC12LSELx bits for both DACs must be gt 0 The DAC12ENC bits of both DACs must be set to 1 When DAC12_0 and DA
30. rw 0 rw 0 rw 0 rw 0 rw 0 r 0 m Modifiable only when ENC 0 CSTART Bits ADDx 15 12 SHSx Bits 11 10 SHP Bit 9 ISSH Bit 8 ADC12DIVx Bits 7 5 Conversion start address These bits select which ADC12 conversion memory register is used for a single conversion or for the first conversion in a sequence The value of CSTARTADDx is 0 to OFh corresponding to ADC12MEMO to ADC12MEM15 Sample and hold source select 00 ADC12SC bit 01 Timer A OUT1 10 Timer B OUTO 11 Timer B OUT1 Sample and hold pulse mode select This bit selects the source of the sampling signal SAMPCON to be either the output of the sampling timer or the sample input signal directly 0 SAMPCON signal is sourced from the sample input signal 1 SAMPCON signal is sourced from the sampling timer Invert signal sample and hold 0 The sample input signal is not inverted 1 The sample input signal is inverted ADC12 clock divider 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111 7 8 ADC12 17 23 ADC 12 Registers ADC12 Bits ADC 12 clock source select SSELx 4 3 00 ADC120SC 01 ACLK 10 MCLK 11 SMCLK CONSEQx Bits Conversion sequence mode select 2 1 00 Single channel single conversion 01 Sequence of channels 10 Repeat single channel 11 Repeat sequence of channels ADC12 Bit 0 ADC12 busy This bit indicates an active sample or conversion operation BUSY 0 No operation is active 1 A sequence sample or conversion is active ADC12ME
31. the program continues at label EDE CMP R7 R6 R6 R7 compare on signed numbers JGE EDE Yes R6 gt R7 No proceed 3 46 RISC 16 Bit CPU JL Syntax Operation Description Status Bits Example Instruction Set Jump if less JL label If N XOR V 1 then jump to label PC 2 x offset gt PC If N XOR V 0 then execute following instruction The status register negative bit N and overflow bit V are tested If only one is set the 10 bit signed offset contained in the instruction LSBs is added to the program counter If both N and V are set or reset the instruction following the jump is executed This allows comparison of signed integers Status bits are not affected When the content of R6 is less than the memory pointed to by R7 the program continues at label EDE CMP QR7 R6 R6 R7 compare on signed numbers JL EDE Yes R6 R7 ione No proceed RISC 16 Bit CPU 3 47 Instruction Set JMP Jump unconditionally Syntax JMP label Operation PC 2x offset gt PC Description The 10 bit signed offset contained in the instruction LSBs is added to the program counter Status Bits Status bits are not affected Hint This one word instruction replaces the BRANCH instruction in the range of 511 to 512 words relative to the current program counter 3 48 RISC 16 Bit CPU JN Syntax Operation Description Status Bits Example L 1 Instruction Set
32. 0 N Q o gt x Bits I2C own address The I2COA register contains the local address of the 15 0 MSP430 I C controller The I2COA register is right justified Bit 6 is the MSB Bits 15 7 are always 0 I2COA I2C Own Address Register 10 Bit Addressing Mode 15 14 13 12 11 10 9 8 ro ro ro ro ro ro rw 0 rw 0 T 6 5 4 3 2 1 0 I2COAx rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Modifiable only when I2CEN 0 N Q o gt x Bits I2C own address The I2COA register contains the local address of the 15 0 MSP430 IC controller The I2COA register is right justified Bit 9 is the MSB Bits 15 10 are always 0 USART Peripheral Interface I C Mode 15 27 12C Module Registers I2CSA 12C Slave Address Register 7 Bit Addressing Mode 15 14 13 12 11 10 9 8 ro ro ro ro ro ro rO ro 7 6 5 4 3 2 1 0 BENE RN ro rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 I2CSAx Bits I2C slave address The I2CSA register contains the slave address of the 15 0 external device to be addressed by the MSP430 It is only used in master mode The I2CSA register is right justified Bit 6 is the MSB Bits 15 7 are always 0 I2CSA I2C Slave Address Register 10 Bit Addressing Mode 15 14 13 12 11 10 9 8 ro ro ro ro ro ro rw 0 rw 0 7 6 5 4 3 2 1 0 I2CSAx rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 I2CSAx Bits I2C slave address The I2CSA register contains the slave address of the 15 0 external device to be addressed by the MSP430 It is only used in master mode The I2CSA
33. 0 00 eee eens 16 2 9 Output Filter herren cogites iat dda Rea eee 3 dE ed 16 2 4 Voltage Reference Generator 00 00 cece eee eens 16 2 5 Comparator_A Port Disable Register CAPD 00000 cues 16 2 0 Comparator A Interrupts 0 0 ete es 16 2 7 Comparator A Used to Measure Resistive Elements 16 3 Comparator A Registers 0c eee enn TZ ADCT2 Introduction i pRertbe rb RO RO bi ReSvaeRPPerb best dr 17 2 ADC1i20peration sssssssessssssssss eh 17 2 4 12 Bit ADO COME iussi iaceo tud end ROC noa E OR ta i m Eos s 17 2 2 ADC12 Inputs and Multiplexer 0 00 cece es 17 2 3 Voltage Reference Generator 0 0 cece eect tenes 17 2 4 Auto Power Down sisis soer asami niamini een nh 17 2 5 Sample and Conversion Timing 0 0c cece e eee eee es 17 2 6 Conversion Memory 0c cee eee eee ene eens 17 2 7 ADC12 Conversion Modes 20000 cece eee es 17 2 8 Using the Integrated Temperature Sensor suuuuuue 17 2 9 ADC12 Grounding and Noise Considerations 17 2 10 ADC12 Interrupts 0 0 0 he 1753 ADCI2 Registers uie e adda obe dde kaw dbo ew eara xi Contents 18 ADC10 18 1 ADC10 Introduction 00 0 0 cee ras 18 2 ADC10 Operation 18 2 1 10 Bit ADC Gore cana iad na ec ded ea eet eR Ree eaves 18 2 2 ADC10 Inputs and Multiplexer 0 0 ccc eee 18 2 3 Voltage Reference Generator
34. 04292h PC OFF12h 04292h 0A123h OFO16h 0A123h 01234h 01114h 0A123h This address mode is mainly for hardware peripheral modules that are located at an absolute fixed address These are addressed with absolute mode to ensure software transportability for example position independent code RISC 16 Bit CPU 3 13 Addressing Modes 3 3 5 Indirect Register Mode The indirect register mode is described in Table 3 8 Table 3 8 Indirect Mode Description Assembler Code Content of ROM MOV R10 0 R11 MOV R10 0 R11 Length One or two words Operation Move the contents of the source address contents of R10 to the destination address contents of R11 The registers are not modified Comment Valid only for source operand The substitute for destination operand is 0 Rd Example MOV B R10 0 R11 Before After Address Register Address Register Space Space Oxxxxh Oxxxxh PC OFF16h OFF14h OFF12h 0000h R10 OFA33h OFF16h 0000h R10 OFA33h O4AEBh PC R11 002A7h OFF14h O4AEBh R11 002A7h OFAS32h 05BC1h OFA32h 05BC1h 002A8h 002A8h 002A7h 002A7h 002A6h 002A6h 3 14 RISC 16 Bit CPU Indirect Autoincrement Mode Addressing Modes The indirect autoincrement mode is described in Table 3 9 Table 3 9 Indirect Autoincrement Mode Description Assembler Code MOV R10 0 R11 Content of ROM MOV R10 0 R11 Move the contents of the source address contents of R10 to the destinati
35. 1 requires an erase cycle The smallest amount of flash that can be erased is a segment There are three erase modes selected with the ERASE and MERAS bits listed in Table 5 1 Table 5 1 Erase Modes MERAS ERASE Erase Mode 0 1 Segment erase 1 0 Mass erase all main memory segments 1 1 Erase all flash memory main and information segments Any erase is initiated by a dummy write into the address range to be erased The dummy write starts the flash timing generator and the erase operation Figure 5 4 shows the erase cycle timing The BUSY bit is set immediately after the dummy write and remains set throughout the erase cycle BUSY MERAS and ERASE are automatically cleared when the cycle completes The erase cycle timing is not dependent on the amount of flash memory present on a device Erase cycle times are equivalent for all MSP430F1xx devices Figure 5 4 Erase Cycle Timing 4 7 1 T E i gt oa Erase Operation Active eT Programming Voltage Programming Voltage 4 Erase Time Vcc Current Consumption is Increased gt BUSY tall Erase tMass Erase 9297 fETG tseg Erase 4819 fFTG A dummy write to an address not in the range to be erased does not start the erase cycle does not affect the flash memory and is not flagged in any way This errant dummy write is ignored Interrupts should be disabled before a flash erase cycle After the erase cycle has completed interrupts may be re enabled Any inte
36. 14 USART Initialization and Reset 14 2 2 Master Mode a aa a eee E ER 14 23 Slave MOC sis chee ces nae cere edie Re OR a Gea ee EES 1424 SPI Ena Ble s iiiu iaia yids E dei aa i vekoa ee dele a eTa Phe vada a4 14 2 5 Serial Clock Control 0 0 0 anaana ees 14 2 6 SPIIntetr pts ihe iamini bik Ur Latet hae Lee dened meee wt 14 8 USART Registers SPI Mode 0 00 cece tenet eae USART Peripheral Interface I2C Mode sssesesee nnn 151 12C Module Introduction uoces dopebx os rpm Eas nar bna ron na Bet od rre 15 2 12C Module Operation 22455 2 rrrbpE IM E LEER EDI CS EUER SE e RSEVEE ER 15 2 1 12C Module Initialization 00 cece cece eee e eet e eee 1522 120 Seidl ala 3 2 emon anie E E E 15 2 3 12C Addressing Modes su 222sicedexsevacididsnddasendsansnseaeweedds 15 2 4 12C Module Operating Modes 15 2 5 The 12C Data Register IZCDR 15 2 6 12C Clock Generation and Synchronization 0c0c cee ee eee 15 2 7 Using the I2C Module with Low Power Modes 0000eeseaee 15 28 12C Iniernr piS serorei d bdce d daaoex doe seta guinem acia Sra espace qid 15 3 12C Module Registers xsecexexe brdessiqe und 41x DRE ERA AERE RR eran acd Comparator A eon pe rete Venue dne cn ees su ERE Rue D ee a 16 1 Comparator A Introduction 0 0 cece nn 16 2 Comparator A Operation 0 nn 16 2 1 Comparator mrpr pian aa a eee e ee eens 16 2 2 Input Analog Switches
37. 2 2 Starting the Timer 2 0 ai a a nh 1122 3 Timer Mode Comal secede esta Sack tes dese Sareea i epe eae hk Caldas 11 2 4 Capture Compare Blocks 11 2 5 Outp L Unit i2 reae ERR REPE tha bere PSOE dera redd 11 2 6 Timer A Interrupts 11 3 Timer A Registers TIMOR Be cem 12 4 TimerB ntroductiQEy opo edente extet ee pr dad Pe dus 12 1 1 Similarities and Differences From Timer A 12 2 Timer B Operation eie nce en ed Rose nr ned dues a hee Ree Ru don 12 2 1 16 Bit Timer Counter 12 2 2 Starting the TIMER uote aat Pr ed b e td a Pons 12 2 8 Timer Mode Control 2 0 0 cee een s 12 2 4 Capture Compare Blocks 12 2 5 Outp t UNIE seeker ERR RERRERERERZTREREEGGGOGGG eek eee Rae 12 2 6 Timer B Interrupts 12 3 Timer B Registers USART Peripheral Interface UART Mode 13 1 USART Introduction UART Mode 13 2 USART Operation UART Mode 000s cee eens 13 2 1 USART Initialization and Reset 13 2 2 Character Format iiis cane ew eee eee kd RE aa 13 2 3 Asynchronous Communication Formats 13 2 4 USART Receive Enable 13 2 5 USART Transmit Enable ssseeee RII 13 2 6 UART Baud Rate Generation 13 2 7 USART Interrupts reccs kanena eee eens 13 8 USART Registers UART Mode 14 15 16 Contents USART Peripheral Interface SPI Mode 0 02cc cece e eee e eee eee 14 1 USART Introduction SPI Mode anaana anaana 14 2 USART Operation SPI Mode 2 0 cece ete 14 2
38. 37 Parity bit Error rate X 9 1 x UxBR 7 10 x 100 3 42 The results show the maximum per bit error to be 5 08 of a BITCLK period USART Peripheral Interface UART Mode 13 13 USART Operation UART Mode Receive Bit Timing Receive timing consists of two error sources The first is the bit to bit timing error The second is the error between a start edge occurring and the start edge being accepted by the USART Figure 13 9 shows the asynchronous timing errors between data on the URXDx pin and the internal baud rate clock Figure 13 9 Receive Error i 0 1 2 tideal to t 11 213 4 5le 7 8 oto 12 53 14 1 2 3 4 5 e 8 oltoli r2liali4 1 2 3 4 5 6 URXDx st DO D1 URXDS ST DO D1 tactual i to t t2 9 amp Synchronization Error 0 5x BRCLK Sample URXDS Int UxBR 2 m0 UxBR m1 13 1 14 UxBR m2 13 0 13 LN int 13 2 2641 17 lA Majority Vote Taken Majority Vote Taken Majority Vote Taken The ideal start bit timing tiqeai 0 is half the baud rate timing tbaud rate because the bit is tested in the middle of its period The ideal baud rate timing tigeaj i for the remaining character bits is the baud rate timing tpaudrate The individual bit errors can be calculated by Error baud rale x 2 x mo int BR x UxBR m x 100 Where baud rate is the required baud rate BRCLK is the input frequency sele
39. CAOUT used to gate Timer A CCI1B capturing capacitor discharge time More than one resistive element can be measured Additional elements are connected to CAO with available I O pins and switched to high impedance when not being measured Comparator A 16 7 Comparator_A Operation The thermistor measurement is based on a ratiometric conversion principle The ratio of two capacitor discharge times is calculated as shown in Figure 16 6 Figure 16 6 Timing for Temperature Measurement Systems Vc Voc 0 25 x Vcc Phase I Charge Phase Il Phase III Phase IV t Discharge Charge ie Discharge 4 tret timeas gt The Vcc voltage and the capacitor value should remain constant during the conversion but are not critical since they cancel in the ratio V f Rmeas X C x In Nmeas _ Voc Nref R X Cx In viet re V CC Nmeas _ Rmeas N ref Fret Nmeas Rmeas Pref X N 16 8 Comparator_A ref Comparator_A Registers 16 3 Comparator_A Registers The Comparator_A registers are listed in Table 16 1 Table 16 1 Comparator A Registers Register Short Form Register Type Address Initial State Comparator_A control register 1 CACTL1 Read write 059h Reset with POR Comparator_A control register 2 CACTL2 Read write 05Ah Reset with POR Comparator_A port disable CAPD Read write 05Bh Reset with POR Comparator A 16 9 Comparator_A Registers CACTL1
40. Considerations Digital Power Supply 7x Decoupling 10uF 100nF Analog 2 Power Supply 7T Decoupling MSP430F13x MSP430F14x Ve MSP430F15x REF MSP430F16x Using an External Positive 7m T Reference 10 Using the Internal n Reference 7m To Of Generator 10 Using an External H Vrer_ Vengr t mu Negative T Ay Reference 1lOuF 100nF ADC12 17 17 ADC 12 Operation 17 2 10 ADC12 Interrupts The ADC12 has 18 interrupt sources ADC12IFGO ADC12IFG15 g ADC120V ADC12MEMXx overflow Ly ADC12TOV ADC12 conversion time overflow The ADC12IFGx bits are set when their corresponding ADC12MEMx memory register is loaded with a conversion result An interrupt request is generated if the corresponding ADC12IEx bit and the GIE bit are set The ADC120V condition occurs when a conversion result is written to any ADC12MEMx before its previous conversion result was read The ADC12TOV condition is generated when another sample and conversion is requested before the current conversion is completed ADC12IV Interrupt Vector Generator 17 18 ADC12 All ADC 12 interrupt sources are prioritized and combined to source a single interrupt vector The interrupt vector register ADC12IV is used to determine which enabled ADC12 interrupt source requested an interrupt The highest priority enabled ADC12 interrupt generates a number in the A
41. DAC12 enable conversion This bit enables the DAC12 module when DAC12LSELx gt 0 when DAC12LSELx 0 DAC12ENC is ignored 0 DAC12 disabled 1 DAC12 enabled DAC12 group Groups DAC12_x with the next higher DAC12 x Not used for DAC12 1 on MSP430x15x and MSP430x1 6x devices 0 Not grouped 1 Grouped DAC 12 Registers DAC12_xDAT DAC12 Data Register 15 14 13 12 11 10 9 8 r 0 r 0 r 0 r 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Unused Bits Unused These bits are always 0 and do not affect the DAC12 core 15 12 DAC12 Data Bits DAC12 data 11 0 DAC12 Data Format DAC12 Data 12 bit binary The DAC12 data are right justified Bit 11 is the MSB 12 bit 2 s complement The DAC12 data are right justified Bit 11 is the MSB sign 8 bit binary The DAC12 data are right justified Bit 7 is the MSB Bits 11 8 are don t care and do not effect the DAC12 core 8 bit 2 s complement The DAC12 data are right justified Bit 7 is the MSB sign Bits 11 8 are don t care and do not effect the DAC12 core DAC12 19 13 Manual Update Sheet l TEXAS SLAZ671 April 2015 INSTRUMENTS Corrections to MSP430x1xx Family User s Guide SLAU049 Document Being Updated MSP430x1xx Family User s Guide Literature Number Being Updated SLAUO49F Page Change or Add 146 5 20 In FCTL3 Flash Memory Control Register FCTL3 the BUSY bit is shown as r w 0 The correct value is r 0 SLAZ6
42. DMA DMA DMA rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Reserved DMADTx DMA DSTINCRx DMA SRCINCRx DMA DSTBYTE Bit 15 Bits 14 12 Bits 11 10 Bits 9 8 Bit 7 Reserved DMA Transfer mode 000 Single transfer 001 Block transfer 010 Burst block transfer 011 Burst block transfer 100 Repeated single transfer 101 Repeated block transfer 110 Repeated burst block transfer 111 Repeated burst block transfer DMA destination increment This bit selects automatic incrementing or decrementing of the destination address after each byte or word transfer When DMADSTBYTE 1 the destination address increments decrements by one When DMADSTBYTE 0 the destination address increments decrements by two The DMAXDA is copied into a temporary register and the temporary register is incremented or decremented DMAxDA is not incremented or decremented 00 Destination address is unchanged 01 Destination address is unchanged 10 Destination address is decremented 11 Destination address is incremented DMA source increment This bit selects automatic incrementing or decrementing of the source address for each byte or word transfer When DMASRCBYTE 1 the source address increments decrements by one When DMASRCBYTE 0 the source address increments decrements by two The DMAXSA is copied into a temporary register and the temporary register is incremented or decremented DMAXxSA is not incremented or decremented 00 S
43. DMAEO is selected as the trigger DMA transfers are triggered as long as the trigger signal is high and the DMAEN bit remains set The trigger signal must remain high for a block or burst block transfer to complete If the trigger signal goes low during a block or burst block transfer the DMA controller is held in its current state until the trigger goes back high or until the DMA registers are modified by software If the DMA registers are not modified by software when the trigger signal goes high again the transfer resumes from where it was when the trigger signal went low When DMALEVEL 1 transfer modes selected when DMADTx 0 1 2 3 are recommended because the DMAEN bit is automatically reset after the configured transfer Halting Executing Instructions for DMA Transfers The DMAONFETCH bit controls when the CPU is halted for a DMA transfer When DMAONFETCH 0 the CPU is halted immediately and the transfer begins when a trigger is received When DMAONFETCH 1 the CPU finishes the currently executing instruction before the DMA controller halts the CPU and the transfer begins Note DMAONFETCH Must Be Used When The DMA Writes To Flash If the DMA controller is used to write to flash memory the DMAONFETCH bit must be set Otherwise unpredictable operation can result LLLLLLS A O O e M 8 12 DMA C
44. Deas 6 2 2 SVS Comparator Operation 6 23 Changing the VLDx Bits 2 0 ccc teens 6 24 SVS Operating Range 0 cece teen eee 6 3 SVS R6glslets 5 viua gaa CUM RP UePS ERI RR ATH Oud aea Pe qu 7 Hardware Multiplier lsleleeeeeeeee IRI IIIA 7 1 Hardware Multiplier Introduction 0 00 c cece eee eet ae 7 2 Hardware Multiplier Operation 0 00 cece eet ee 7 2 1 Operand Registers 0 0 eee eens 7 2 2 Result Registers 0 02 eee enn 72 3 Software Examples 5s ioco be dhe bide ide bee 7 2 4 Indirect Addressing of RESLO 0 00 eee F250 Using Interr pts iu sse eee omes dani de acces err anni ing 7 3 Hardware Multiplier Registers issssssssselsssse III 8 DMA Controller euer ERE ER a dee menie tatu Ru deu e eaa E aas 8 1 DMA Irtroductlon 2issssesek zoe e ku RR ERR REESE REL RPRE E RETE REESE X RE 9 2 DMAOpelaltiol asc sere Rev REG RAE ERR ERREUR Ur ERU ERR MEE 8 2 1 DMA Addressing Modes 0 ccc eee eee 8 22 DMA Transfer Modes 0 0 cece eee cnet e eee 8 2 3 Initiating DMA Transfers 0 0000 aeaaeae 8 24 Stopping DMA Transfers 00 ccc eee eee 8 25 DMA Channel Priorities 0 0 0 ccc eee 8 26 DMA Transfer Cycle Time ssssssssssese e 8 2 7 Using DMA with System Interrupts 0 06000 c cece eee ee 8 28 DMA Controller Interrupts 00 ccs 8 2 9 Using the 12C Mo
45. GIE bits are set the DAC12IFG generates an interrupt request The DAC12IFG flag is not reset automatically It must be reset by software DAC12 19 9 DAC 12 Registers 19 3 DAC12 Registers The DAC12 registers are listed in Table 19 2 Table 19 2 DAC12 Registers Register Short Form Register Type Address Initial State DAC12_0 control DAC12 OCTL Read write 01COh Reset with POR DAC12_0 data DAC12 ODAT Read write 01C8h Reset with POR DAC12_1 control DAC12_1CTL Read write 01C2h Reset with POR DAC12_1 data DAC12_1DAT Read write 01CAh Reset with POR 19 10 DAC12 DAC 12 Registers DAC12_xCTL DAC12 Control Register 15 Reserved rw 0 7 rw 0 14 13 12 11 10 9 8 DAC12 DAC12SREFx DAC12RES DAC12LSELx CALON DAC12IR rw 0 6 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 5 4 3 2 1 0 DAC12 DAC12AMPx DAC12DF DAC12IE DAC12IFG DAC12ENC rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 ER Modifiable only when DAC12bENC 0 Reserved DAC12 SREFx DAC12 RES DAC12 LSELx DAC12 CALON DAC12IR Bit 15 Bits 14 13 Bit 12 Bits 11 10 Bit 9 Bit 8 Reserved DAC12 select reference voltage 00 VREF 01 VREF 10 VeREF 11 Vener DAC12 resolution select 0 12 bit resolution 1 8 bit resolution DAC12 load select Selects the load trigger for the DAC12 latch DAC12ENC must be set for the DAC to update except when DAC12LSELx 0 00 DAC12 latch loads when DAC12 xDAT written DAC12
46. MOD the fpco frequency is used Not useable when DCOx 7 BCSCTL1 Basic Clock System Control Register 1 7 5 4 3 2 1 0 XT20FF XTS DIVAx XT5V RSELx rw 1 XT20FF XTS DIVAx XT5V RSELx rw 0 Bit 7 Bit 6 Bits 5 4 Bit 3 Bits 2 0 rw 0 rw 0 rw 0 rw 1 rw 0 rw 0 XT2 off This bit turns off the XT2 oscillator 0 XT2 is on 1 XT2 is off if it is not used for MCLK or SMCLK LFXT1 mode select 0 Low frequency mode 1 High frequency mode Divider for ACLK 00 A 01 2 10 4 11 8 Unused XT5V should always be reset Resistor Select The internal resistor is selected in eight different steps The value of the resistor defines the nominal frequency The lowest nominal frequency is selected by setting RSELx 0 Basic Clock Module 4 15 Basic Clock Module Registers BCSCTL2 Basic Clock System Control Register 2 SELMx DIVMx SELS DIVSx DCOR 4 16 BitS 5 4 Bit 3 BitS Bit 0 Select MCLK These bits select the MCLK source 00 DCOCLK 01 DCOCLK 10 XT2CLK when XT2 oscillator present on chip LFXT1CLK when XT2 oscillator not present on chip 11 LFXT1CLK Divider for MCLK 00 A 01 2 10 4 11 7 8 Select SMCLK This bit selects the SMCLK source 0 DCOCLK 1 XT2CLK when XT2 oscillator present on chip LFXT1CLK when XT2 oscillator not present on chip Divider for SMCLK 00 A 01 2 10 4 11 7 8 DCO resistor select 0 Internal resistor 1 External resistor
47. MSP430x1xx system resets interrupts and operating modes Topic 2 1 System Reset and Initialization 0 eee eee e eee eee 2 2 INterr pts 77 5 ee eee nE SEE EEEE EA EEEE E a eius 2 3 Opera No MO deS e E E T 2 4 Principles for Low Power Applications 2 5 Connection of Unused Pins 2 1 System Reset and Initialization 2 1 System Reset and Initialization The system reset circuitry shown in Figure 2 1 sources both a power on reset POR and a power up clear PUC signal Different events trigger these reset signals and different initial conditions exist depending on which signal was generated Figure 2 1 Power On Reset and Power Up Clear Schematic Vcc Voc Voc pu POR Reset Detect Delay POR oV OV 50us OV ucc ee Fe RST NMI WDTNMIT mU 3 WDTQn WDTIEGT Resetwd1 PUC EQUT Resetwd2 KEYV from flash module MCLK T From watchdog timer peripheral module Devices with BOR only Devices without BOR only Devices with SVS only A POR is a device reset A POR is only generated by the following three events Powering up the device A low signal on the RST NMI pin when configured in the reset mode Li An SVS low condition when PORON 1 A PUC is always generated when a POR is generated but a POR is not generated by a PUC The following events trigger a PUC _ A POR signal Wat
48. Operation Pulse Sample Mode The pulse sample mode is selected when SHP 1 The SHI signal is used to trigger the sampling timer The SHTOx and SHT1x bits in ADC12CTLO control the interval of the sampling timer that defines the SAMPCON sample period tsample The sampling timer keeps SAMPCON high after synchronization with AD12CLK for a programmed interval tsampje The total sampling time is tsample plus tsync See Figure 17 4 The SHTx bits select the sampling time in 4x multiples of ADC12CLK SHTOx selects the sampling time for ADC12MCTLO to 7 and SHT1x selects the sampling time for ADC12MCTL8 to 15 Figure 17 4 Pulse Sample Mode Start Stop Start Conversion Sampling Sampling Conversion Complete SHI 4 4 sample gt 4 Iconvert 3 isync 17 8 ADC12 ADC 12 Operation Sample Timing Considerations When SAMPCON 0 all Ax inputs are high impedance When SAMPCON 1 the selected Ax input can be modeled as an RC low pass filter during the sampling time tsample as shown below in Figure 17 5 An internal MUX on input resistance Rj max 2 KQ in series with capacitor Cj max 40 pF is seen by the source The capacitor C voltage Vc must be charged to within 1 2 LSB of the source voltage Vs for an accurate 12 bit conversion Figure 17 5 Analog Input Equivalent Circuit Vs Rs MSP430 V Input voltage at pin Ax RI Vs External source voltage VI Rg External source resistance Vc R
49. R7 Example R7 203h Mem R7 low byte of system stack Example R7 20Ah Mem R7 low byte of system stack POP SR Last word on stack moved to the SR rm Note The System Stack Pointer The system stack pointer SP is always incremented by two independent of the byte suffix a 3 54 RISC 16 Bit CPU PUSH W PUSH B Syntax Operation Description Status Bits Mode Bits Example Example Instruction Set Push word onto stack Push byte onto stack PUSH src or PUSH W src PUSH B SIC SP 2SP src SP The stack pointer is decremented by two then the source operand is moved to the RAM word addressed by the stack pointer TOS Status bits are not affected OSCOFF CPUOFF and GIE are not affected The contents of the status register and R8 are saved on the stack PUSH SR save status register PUSH R8 save R8 The contents of the peripheral TCDAT is saved on the stack PUSH B amp TCDAT save data from 8 bit peripheral module address TCDAT onto stack HE S C ICEOd Note The System Stack Pointer The system stack pointer SP is always decremented by two independent of the byte suffix LLLLLSS S S AIAOA RISC 16 Bit CPU 3 55 Instruction Set RET Return from subroutine
50. RISC 16 Bit CPU BIC W BIC B Syntax Operation Description Status Bits Mode Bits Example Example Instruction Set Clear bits in destination Clear bits in destination BIC src dst or BIC W src dst BIC B src dst NOT src AND dst dst The inverted source operand and the destination operand are logically ANDed The result is placed into the destination The source operand is not affected Status bits are not affected OSCOFF CPUOFF and GIE are not affected The six MSBs of the RAM word LEO are cleared BIC 0FC00h LEO Clear 6 MSBs in MEM LEO The five MSBs of the RAM byte LEO are cleared BIC B 0F8h LEO Clear 5 MSBs in Ram location LEO RISC 16 Bit CPU 3 25 Instruction Set BIS W BIS B Syntax Operation Description Status Bits Mode Bits Example Example Set bits in destination Set bits in destination BIS src dst or BIS W src dst BIS B src dst src OR dst dst The source operand and the destination operand are logically ORed The result is placed into the destination The source operand is not affected Status bits are not affected OSCOFF CPUOFF and GIE are not affected The six LSBs of the RAM word TOM are set BIS 003Fh TOM set the six LSBs in RAM location TOM The three MSBs of RAM byte TOM are set BIS B 0E0h TOM set the 3 MSBs in RAM location TOM 3 26 RISC 16 Bit CPU BITLW BIT B Syntax Operation Description Status Bits Mode Bi
51. RXRDYIFG ISR Vector 10 RXRDYIFG JMP TXRDYIFG ISR Vector 12 TXRDYIFG JMP GCIFG ISR Vector 14 GCIFG STTIFG ISR Vector 16 a Task starts here RETI Return ALIFG_ISR Vector 2 m Task starts here RETI Return NACKIFG ISR Vector 4 Task starts here RETI Return OAIFG ISR Vector 6 Task starts here RETI Return ARDYIFG ISR Vector 8 P Task starts here RETI Return RXRDYIFG ISR Vector 10 eee Task starts here RETI Return TXRDYIFG ISR Vector 12 iu Task starts here RETI Return GCIFG ISR Vector 14 is Task starts here RETI Return USART Peripheral Interface I C Mode 15 19 12C Module Registers 15 3 12C Module Registers The 12C module registers are listed in Table 15 4 Table 15 4 12C Registers Register Short Form Register Type Address Initial State I2C interrupt enable I2CIE Read write 050h Reset with PUC 12C interrupt flag I2CIFG Read write 051h Reset with PUC 12C data count I2CNDAT Read write 052h Reset with PUC USART control UOCTL Read write 070h 001h with PUC 12C transfer control I2CTCTL Read write 071h Reset with PUC 12C data control I2ZCDCTL Read only 072h Reset with PUC 12C prescaler I2CPSC Read write 073h Reset with PUC 12C SCL high I2CSCLH Read write 074h Reset with PUC 12C SCL low I2CSCLL Read write 075h Reset with PUC 12C data I2CDRW I2CDRB Read write 076h Reset with PUC 12C own address I2COA Read write 0118h Reset with PUC 12C slave address I2CSA
52. Read write 011Ah Reset with PUC I2C interrupt vector I2CIV Read only 011Ch Reset with PUC 15 20 USART Peripheral Interface 2C Mode 12C Module Registers UOCTL USARTO Control Register I2C Mode 7 rw 0 RXDMAEN TXDMAEN 12C XA LISTEN SYNC MST I2CEN Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 1 Receive DMA enable This bit enables the DMA controller to be used to transfer data from the I2C module after the 12C modules receives data When RXDMAEN 1 RXRDYIE is ignored 0 Disabled 1 Enabled Transmit DMA enable This bit enables the DMA controller to be used to provide data to the I2C module for transmission When TXDMAEN 1 TXRDYIE is ignored 0 Disabled 1 Enabled 12C mode enable This bit select I2C or SPI operation when SYNC 1 0 SPI mode 1 12C mode Extended Addressing 0 7 bit addressing 1 10 bit addressing Listen This bit selects loopback mode LISTEN is only valid when MST 1 and I2CTRX 1 master transmitter 0 Normal mode 1 SDA is internally fed back to the receiver loopback Synchronous mode enable 0 UART mode 1 SPlor 12C mode Master This bit selects master or slave mode The MST bit is automatically cleared when arbitration is lost or a STOP condition is generated 0 Slave mode 1 Master mode 12C enable The bit enables or disables the 12C module The initial condition for this bit is set a
53. Table 7 2 RESHI Contents Mode MPY MPYS MAC MACS RESHI Contents Upper 16 bits of the result The MSB is the sign of the result The remaining bits are the upper 15 bits of the result Two s complement notation is used for the result Upper 16 bits of the result Upper 16 bits of the result Two s complement notation is used for the result The sum extension registers SUMEXT contents depend on the multiply operation and are listed in Table 7 3 Table 7 3 SUMEXT Contents MACS Underflow and Overflow 74 Mode MPY MPYS MAC MACS SUMEXT SUMEXT is always 0000h SUMEXT contains the extended sign of the result 00000h Result was positive or zero OFFFFh Result was negative SUMEXT contains the carry of the result 0000h No carry for result 0001h Result has a carry SUMEXT contains the extended sign of the result 00000h Result was positive or zero OFFFFh Result was negative The multiplier does not automatically detect underflow or overflow in the MACS mode The accumulator range for positive numbers is 0 to 7FFF FFFFh and for negative numbers is OFFFF FFFFh to 8000 0000h An underflow occurs when the sum of two negative numbers yields a result that is in the range for a positive number An overflow occurs when the sum of two positive numbers yields a result that is in the range for a negative number In both of these cases the SUMEXT register contains the sign of the result OFFFFh for overflow and 0000h for under
54. UTXIFG1 bit 1011 Multiplier ready 1100 No action 1101 No action 1110 DMAOIFG bit triggers DMA channel 1 DMA1IFG bit triggers DMA channel 2 DMA2IFG bit triggers DMA channel 0 1111 External trigger DMAEO DMA1 Bits Same as DMA2TSELx TSELx 7 4 DMAO Bits Same as DMA2TSELx TSELx 3 0 DMA Controller 8 19 DMA Registers DMACTL1 DMA Control Register 1 15 ro 7 6 14 13 12 11 10 9 8 ro ro ro ro ro ro ro 5 4 3 2 1 0 DMA ROUND ONFETCH ROBIN rw 0 rw 0 rw 0 ro ro Reserved Bits 15 3 DMA Bit 2 ONFETCH ROUND Bit 1 ROBIN ENNMI Bit 0 ro ro ro Reserved Read only Always read as 0 DMA on fetch 0 The DMA transfer occurs immediately 1 The DMA transfer occurs on next instruction fetch after the trigger Round robin This bit enables the round robin DMA channel priorities 0 DMA channel priority is DMAO DMA1 DMA2 1 DMA channel priority changes with each transfer Enable NMI This bit enables the interruption of a DMA transfer by an NMI interrupt When an NMI interrupts a DMA transfer the current transfer is completed normally further transfers are stopped and DMAABORT is set 0 NMI interrupt does not interrupt DMA transfer 1 NMI interrupt interrupts a DMA transfer 8 20 DMA Controller DMA Registers DMAxCTL DMA Channel x Control Register 15 Reserved rw 0 14 13 12 11 10 9 8 DMADTx DMADSTINCRx DMASRCINCRx rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 il 0
55. Unchanged SFR module enable register 1 ME1 Read write 004h 000h with PUC SFR interrupt enable register 1 IE1 Read write 000h 000h with PUC SFR interrupt flag register 1 IFG1 Read write 002h 082h with PUC T Does not apply to 12xx devices Refer to the register definitions for registers and bit positions for these devices Table 13 4 USAHT1 Control and Status Registers Register Short Form Register Type Address Initial State USART control register U1CTL Read write 078h 001h with PUC Transmit control register U1TCTL Read write 079h 001h with PUC Receive control register U1RCTL Read write 07Ah 000h with PUC Modulation control register U1MCTL Read write 07Bh Unchanged Baud rate control register 0 U1BRO Read write 07Ch Unchanged Baud rate control register 1 U1BR1 Read write 07Dh Unchanged Receive buffer register U1RXBUF Read 07Eh Unchanged Transmit buffer register U1TXBUF Read write 07Fh Unchanged SFR module enable register 2 ME2 Read write 005h 000h with PUC SFR interrupt enable register 2 IE2 Read write 001h 000h with PUC SFR interrupt flag register 2 IFG2 Read write 003h 020h with PUC aS Note Modifying SFR bits To avoid modifying control bits of other modules it is recommended to set or clear the IEx and IFGx bits using BIS B or BIC B instructions rather than MOV B Or CLR B instructions _ SSSSSS SS __ USART Peripheral Interface UART Mode 13 21 USART Registers UART Mode UxCTL USART Control Register 7 6 5 4 3 2 1 0
56. and R10 MSBs are in R12 and R9 SUB W R13 R10 16 bit part LSBs SUBC B HR12 R9 8 bit part MSBs The 16 bit counter pointed to by R13 is subtracted from a 16 bit counter in R10 and R11 MSD SUB B R13 R10 Subtract LSDs without carry SUBC B Q9R13 R11 Subtract MSDs with carry resulting from the LSDs Note Borrow Implementation The borrow is treated as a NOT carry Borrow Carry bit Yes 0 No 1 RISC 16 Bit CPU 3 67 Instruction Set SWPB Syntax Operation Description Status Bits Mode Bits Swap bytes SWPB dst Bits 15 to 8 bits 7 to 0 The destination operand high and low bytes are exchanged as shown in Figure 3 18 Status bits are not affected OSCOFF CPUOFF and GIE are not affected Figure 3 18 Destination Operand Byte Swap Example Example 15 8 7 0 MOV 040BFh R7 0100000010111111 R7 SWPB R7 1011111101000000 in R7 The value in R5 is multiplied by 256 The result is stored in R5 R4 SWPB R5 MOV R5 R4 Copy the swapped value to R4 BIC 0FFOOh R5 Correct the result BIC 00FFh R4 Correct the result 3 68 RISC 16 Bit CPU SXT Syntax Operation Description Status Bits Mode Bits Instruction Set Extend Sign SXT dst Bit 7 Bit 8 Bit 15 The sign of the low byte is extended into the high byte as shown in Figure 3 19 N Set if result is negative reset if positive Z Set if result is zero reset otherwise C Set if result is not
57. and a framing error parity error or break condition is detected no character is received into UxRXBUF When URXEIE 1 characters are received into UXRXBUF and any applicable error bit is set When any of the FE PE OE BRK or RXERR bits is set the bit remains set until user software resets it or UXRXBUF is read USART Peripheral Interface UART Mode USART Operation UART Mode 13 2 4 USART Receive Enable The receive enable bit URXEx enables or disables data reception on URXDx as shown in Figure 13 5 Disabling the USART receiver stops the receive operation following completion of any character currently being received or immediately if no receive operation is active The receive data buffer UxRXBUF contains the character moved from the RX shift register after the character is received Figure 13 5 State Diagram of Receiver Enable No Valid Start Bit Not Completed URXEx 1 Valid Start Bit Idle State Receiver Enabled Receiver Collects Character Receive Disable Handle Interrupt Conditions URXEx 0 Character Received URXEx 0 a hs Note Re Enabling the Receiver Setting URXEx UART Mode When the receiver is disabled URXEx 0 re enabling the receiver URXEx 1 is asynchronous to any data stream that may be present on URXDx at the time Synchronization can be performed by testing for an idle line condition before receiving a valid character see
58. any RC type oscillator frequency varies with temperature voltage and from device to device The DCO frequency can be adjusted by software using the DCOx MODx and RSELx bits The digital control of the oscillator allows frequency stabilization despite its RC type characteristics Software can disable DCOCLK by setting SCGO when it is not used to source SMCLK or MCLK in active mode as shown in Figure 4 4 Figure 4 4 On Off Control of DCO cone DCOCLK_on XSELM1 e 1 on SCGim gt 0 off SELS D Q DCOCLK gt CL POR SMCLK DCO_Gen_on SCccGom 1 on 0 off 4 6 Basic Clock Module Basic Clock Module Operation Adjusting the DCO frequency After a PUC the internal resistor is selected for the DC generator RSELx 4 and DCOx 3 allowing the DCO to start at a mid range frequency MCLK and SMCLK are sourced from DCOCLK Because the CPU executes code from MCLK which is sourced from the fast starting DCO code execution begins from PUC in less than 6 us The typical DCOx and RSELx ranges and steps are shown in Figure 4 5 The frequency of DCOCLK is set by the following functions Ll The current injected into the DC generator by either the internal or external resistor defines the fundamental frequency The DCOR bit selects the internal or external resistor The three RSELx bits select one of eight nominal frequency ranges for the DCO These ranges are defined for an individual device i
59. clock distribution and divider system is provided to fine tune the individual clock requirements Basic Clock Module Basic Clock Module Operation 4 2 2 LFXT1 Oscillator The LFXT1 oscillator supports ultralow current consumption using a 32 768 Hz watch crystal in LF mode XTS 0 A watch crystal connects to XIN and XOUT without any other external components Internal 12 pF load capacitors are provided for LFXT1 in LF mode The capacitors add serially providing a match for standard 32 768 Hz crystals requiring a 6 pF load Additional capacitors can be added if necessary The LFXT1 oscillator also supports high speed crystals or resonators when in HF mode XTS 1 and OSCOFF is cleared The high speed crystal or resonator connects to XIN and XOUT and requires external capacitors on both terminals These capacitors should be sized according to the crystal or resonator specifications LFXT1 may be used with an external clock signal on the XIN pin in either LF or HF mode When used with an external signal the external frequency must meet the datasheet parameters for the chosen mode and OSCOFF must be reset Software can disable LFXT1 by setting OSCOFF if this signal does not source SMCLK or MCLK as shown in Figure 4 2 Figure 4 2 Off Signals for the LFXT1 Oscillator XTS m OSCOFF m LFoff CPUOFF SELMO amp SELM1 E e XT2 joe ES 0 gt XT1off EI gt XT2 is an Inte
60. clock module incorporates an oscillator fault detection fail safe feature The oscillator fault detector is an analog circuit that monitors the LFXT1CLK in HF mode and the XT2CLK An oscillator fault is detected when either clock signal is not present for approximately 50 us When an oscillator fault is detected and when MCLK is sourced from either LFXT1 in HF mode or XT2 MCLK is automatically switched to the DCO for its clock source This allows code execution to continue even though the crystal oscillator has stopped When OFIFG is set and OFIE is set an NMI interrupt is requested The NMI interrupt service routine can test the OFIFG flag to determine if an oscillator fault occurred The OFIFG flag must be cleared by software Note No Oscillator Fault Detection for LFXT1 in LF Mode Oscillator fault detection is only applicable for LFXT1 in HF mode and XT2 There is no oscillator fault detection for LFXT1 in LF mode LLLLLLLLLL DS A 3Q OFIFG is set by the oscillator fault signal XT OscFault XT OscFault is set at POR when LFXT1 has an oscillator fault in HF mode or when XT2 has an oscillator fault When XT2 or LFXT1 in HF mode is stopped with software the XT OscFault signal becomes active immediately remains active until the oscillator is r
61. contents of the destination are lost N Set if result is negative reset if positive Z Set if result is zero reset otherwise C Set if there is a carry from the result cleared if not V Set if an arithmetic overflow occurs otherwise reset OSCOFF CPUOFF and GIE are not affected R5 is increased by 10 The jump to TONI is performed on a carry ADD 10 R5 JC TONI Carry occurred PET No carry R5 is increased by 10 The jump to TONI is performed on a carry ADD B 10 R5 Add 10 to Lowbyte of R5 JC TONI Carry occurred if R5 gt 246 OAh 0F6h Paco No carry 3 22 RISC 16 Bit CPU ADDC W ADDC B Syntax Operation Description Status Bits Mode Bits Example Example Instruction Set Add source and carry to destination Add source and carry to destination ADDC src dst or ADDC W src dst ADDC B src dst src dst C gt dst The source operand and the carry bit C are added to the destination operand The source operand is not affected The previous contents of the destination are lost N Set if result is negative reset if positive Z Set if result is zero reset otherwise C Set if there is a carry from the MSB of the result reset otherwise V Set if an arithmetic overflow occurs otherwise reset OSCOFF CPUOFF and GIE are not affected The 32 bit counter pointed to by R13 is added to a 32 bit counter eleven words 20 2 2 2 above the pointer in R13 ADD R13 20 R13 ADD LS
62. edet A edd 1 42 RAM ubere ee EDe deben Pad gy des dud ep rdwd peices dene 1 4 3 Peripheral Modules sssssesssssssess eee eens 1 4 4 Special Function Registers SFRs 00 cece eee eee eee 1 4 5 Memory Organization 00 ccc ete e 2 System Resets Interrupts and Operating Modes 2 1 System Reset and Initialization 0 0 cece eee 2 1 1 Power On Reset POR 000 cece eens 2 1 2 Brownout Reset BOR 00 ccc cette eens 2 1 3 Device Initial Conditions After System Reset P Mini ERE 2 2 1 Non Maskable Interrupts NMI 000 0c cece eee ete 2 2 2 Maskable Interrupts 0 002 eee eee 2 2 3 Interrupt Processing 2 cece eects 2 2 4 Interrupt Vectors 2 esie ced El cR hee ee nee ed 2 9 Operating Modes cuis herbe edhe AR PA UE redu Ped du 2 3 1 Entering and Exiting Low Power Modes 0 eee cence entree 2 4 Principles for Low Power Applications 00sec eee eee ee 2 5 Connection of Unused Pins 0 00 eee vii Contents 3 RISC 16 Bit CPU eoo REI a EPI setiece TR EE Emm 3 1 CPU lritroduction iiie reed dee dedi msd adde dee dame ce 3 2 CPURegisters ssuuusssssssssles ete hs 3 2 1 Program Counter PC 00 ccc cee eee es 3 2 3 Stack Pointer SP 0 0 a tenes 3 2 3 Status Register SR esa ter os chads d ded ener pee aoc d dive wed d
63. flag 0 No interrupt pending 1 Interrupt pending GCIFG Bit 6 General call interrupt flag 0 No interrupt pending 1 Interrupt pending TXRDYIFG Bit 5 Transmit ready interrupt flag 0 No interrupt pending 1 Interrupt pending RXRDYIFG Bit 4 Receive ready interrupt flag 0 No interrupt pending 1 Interrupt pending ARDYIFG Bit 3 Access ready interrupt flag 0 No interrupt pending 1 Interrupt pending OAIFG Bit 2 Own address interrupt flag 0 No interrupt pending 1 Interrupt pending NACKIFG Bit 1 No acknowledge interrupt flag 0 No interrupt pending 1 Interrupt pending ALIFG Bit 0 Arbitration lost interrupt flag 0 No interrupt pending 1 Interrupt pending 15 30 USART Peripheral Interface 2C Mode I2CIV 12C Interrupt Vector Register 15 ro 12C Module Registers 14 13 12 11 10 9 8 ro ro ro ro ro ro ro 7 6 5 4 3 2 1 0 ro ro ro r 0 r 0 r 0 r 0 ro I2CIVx Bits 12C interrupt vector value 15 0 I2CIV Interrupt Interrupt Contents Interrupt Source Flag Priority 000h No interrupt pending 002h Arbitration lost ALIFG Highest 004h No acknowledgement NACKIFG 006h Own address OAIFG 008h Register access ready ARDYIFG 00Ah Receive data ready RXRDYIFG 00Ch Transmit data ready TXRDYIFG OOEh General call GCIFG 010h START condition received STTIFG Lowest USART Peripheral Interface I C Mode 15 31 Chapter 16 Comparator A Comparator A is an analog voltage comparator This chapter describes Comparator A Comparator A is implemen
64. following 1 Any currently executing instruction is completed 2 The PC which points to the next instruction is pushed onto the stack 3 The SR is pushed onto the stack 4 The interrupt with the highest priority is selected if multiple interrupts occurred during the last instruction and are pending for service 5 The interrupt request flag resets automatically on single source flags Multiple source flags remain set for servicing by software 6 The SR is cleared This terminates any low power mode Because the GIE bit is cleared further interrupts are disabled 7 The content of the interrupt vector is loaded into the PC the program continues with the interrupt service routine at that address Figure 2 7 Interrupt Processing Before After Interrupt Interrupt TOS System Resets Interrupts and Operating Modes 2 11 System Reset and Initialization Return From Interrupt The interrupt handling routine terminates with the instruction RETI return from an interrupt service routine The return from the interrupt takes 5 cycles to execute the following actions and is illustrated in Figure 2 8 1 The SR with all previous settings pops from the stack All previous settings of GIE CPUOFF etc are now in effect regardless of the settings used during the interrupt service routine 2 The PC pops from the stack and begins execution at the point where it was interrupted Figure 2 8 Return From Interrupt Before A
65. for Trigger SAMPCON 4 4 8 16 64 x ADC10CLK Sample Input Channel Ax If x gt 0 then x x 1 We seg CU Sa a 12 x ADC10CLK MSC 1 and xz0 1 x ADC10CLK Conversion Completed Result to ADC10MEM ADC1OIFG is Set x input channel Ax ADC10 18 11 ADC10 Operation Repeat Single Channel Mode A single channel selected by INCHx is sampled and converted continuously Each ADC result is written to ADC10MEM Figure 18 7 shows the repeat single channel mode Figure 18 7 Repeat Single Channel Mode x INCHx Wait for Enable SHS 0 and ENC 1 or 4 and ADC10SC 4 Wait for Trigger SAMPCON _4 ENC 0 4 8 16 64 x ADC10CLK K Sample Input Channel Ax 12 x ADC10CLK MSC 1 ENC 1 1 x ADC10CLK Conversion Completed Result to ADC10MEM ADC1OIFG is Set x input channel Ax 18 12 ADC10 ADC10 Operation Repeat Sequence of Channels Mode A sequence of channels is sampled and converted repeatedly The sequence begins with the channel selected by INCHx and decrements to channel AO Each ADC result is written to ADC10MEM The sequence ends after conversion of channel AO and the next trigger signal re starts the sequence Figure 18 8 shows the repeat sequence of channels mode Figure 18 8 Repeat Sequence of Channels Mode x INCHx Wait for Enable SHS 0 and ENC 1 or 4 and ADC10SC 4 Wait f
66. from 0001h to 0000h Figure 12 8 shows the flag set cycle Figure 12 8 Up Down Mode Flag Setting Timer Clock Timer Up Down Set TBIFG Set TBCCRO CCIFG Timer B 12 9 Timer_B Operation Changing the Value of Period Register TBCLO Use of the Up Down When changing TBCLO while the timer is running and counting in the down direction and when the TBCLO load mode is immediate the timer continues its descent until it reaches zero The new period takes effect after the counter counts down to zero If the timer is counting in the up direction when the new period is latched into TBCLO and the new period is greater than or equal to the old period or greater than the current count value the timer counts up to the new period before counting down When the timer is counting in the up direction and the new period is less than the current count value when TBCLO is loaded the timer begins counting down However one additional count may occur before the counter begins counting down Mode The up down mode supports applications that require dead times between output signals see section Timer B Output Unit For example to avoid overload conditions two outputs driving an H bridge must never be in a high state simultaneously In the example shown in Figure 12 9 the tgeagq is tdead ttimer x TBCL1 TBCL3 With tgeag Time during which both outputs need to be inactive ttimer Cycle time of the timer clock TBCLx Content of c
67. instruction The software overhead for different interrupt sources includes interrupt latency and return from interrupt cycles but not the task handling itself The latencies are Capture compare block CCRO 11 cycles Capture compare blocks CCR1 to CCR6 16 cycles Timer overflow TBIFG 14 cycles The following software example shows the recommended use of TBIV for Timer B3 Interrupt handler for TBCCRO CCIFG Cycles CCIFG 0 HND Start of handler Interrupt latency 6 RETI Interrupt handler for TBIFG TBCCR1 and TBCCR2 CCIFG TB HND od Interrupt latency 6 ADD amp TBIV PC Add offset to Jump table 3 RETI Vector 0 No interrupt 5 JMP CCIFG 1 HND Vector 2 Module 1 2 JMP CCIFG 2 HND Vector 4 Module 2 2 RETI Vector 6 RETI Vector 8 RETI Vector 10 RETI Vector 12 TBIFG HND Vector 14 TIMOV Flag s Task starts here RETI 5 CCIFG_2_HND Vector 4 Module 2 E Task starts here RETI Back to main program 5 The Module 1 handler shows a way to look if any other interrupt is pending 5 cycles have to be spent but 9 cycles may be saved if another interrupt is pending CCIFG 1 HND Vector 6 Module 3 Task starts here JMP TB HND Look for pending ints 2 Timer B 12 19 Timer_B Registers 12 3 Timer_B Registers The Timer B registers are listed in Table 12 5 Table 12 5 Timer B Registers Register Short Form Register Type Address Initial State Timer B control TBCTL Read write 01
68. interrupt vector and the interrupt vector is shared with the DAC12 module Software must check the DMAIFG and DAC12IFG flags to determine the source of the interrupt The DMAIFG flags are not reset automatically and must be reset by software 8 16 DMA Controller DMA Operation 8 2 9 Using the I2C Module with the DMA Controller The 12C module provides two trigger sources for the DMA controller The 12C module can trigger a transfer when new 12C data is received and the when the transmit data is needed The TXDMAEN and RXDMAEN bits enable or disable the use of the DMA controller with the 12C module When RXDMAEN 1 the DMA controller can be used to transfer data from the 12C module after the 12C modules receives data When RXDMAEN 1 RXRDYIE is ignored and RXRDYIFG will not generate an interrupt When TXDMAEN 1 the DMA controller can be used to transfer data to the 12C module for transmission When TXDMAEN 1 TXRDYIE is ignored and TXRDYIFG will not generate an interrupt 8 2 10 Using ADC12 with the DMA Controller MSP430 devices with an integrated DMA controller can automatically move data from any ADC12MEMX register to another location DMA transfers are done without CPU intervention and independently of any low power modes The DMA controller increases throughput of the ADC12 module and enhances low power applications allowing the CPU to remain off while data transfers occur DMA transfers can be triggered from any ADC121FG
69. label Core instruction MOV X R5 PC Indirect indirect R5 X 3 28 RISC 16 Bit CPU CALL Syntax Operation Description Status Bits Example Instruction Set Subroutine CALL dst dst tmp dst is evaluated and stored SP 2 gt SP PC gt SP PC updated to TOS tmp gt PC dst saved to PC A subroutine call is made to an address anywhere in the 64K address space All addressing modes can be used The return address the address of the following instruction is stored on the stack The call instruction is a word instruction Status bits are not affected Examples for all addressing modes are given CALL CALL CALL CALL CALL CALL CALL EXEC X Call on label EXEC or immediate address e g 0A4h SP 2 2 SP PC 2 2 SP PC PC EXEC Call on the address contained in EXEC SP 2 5 SP PC 2 5 SP X PC gt PC Indirect address amp EXEC Call on the address contained in absolute address EXEC SP 2 2 SP PC 2 5 SP X 0 5 PC Indirect address R5 Call on the address contained in R5 SP 2 5 SP PC 2 5 SP R5 5 PC Indirect R5 R5 Call on the address contained in the word pointed to by R5 SP 2 2 SP PC 2 5 SP R5 5 PC Indirect indirect R5 R5 Call on the address contained in the word pointed to by R5 and increment pointer in R5 The next time S W flow uses R5 pointer it can alter the program execution due to access to next address i
70. low power modes The now active BRCLK allows the USART to receive the balance of the character After the full character is received and moved to UxRXBUF URXIFGx is set and an interrupt service is again requested Upon ISR entry URXIFGx 1 indicating a character was received The URXIFGx flag is cleared when user software reads UxRXBUF Interrupt handler for start condition and Character receive BRCLK DCO UORX Int BIT B URXIFGO amp IFG2 Test URXIFGx to determine JNE ST COND If start or character MOV B amp UxRXBUF dst Read buffer RETI i ST COND BIC B URXSE amp UOTCTL Clear URXS signal BIS B URXSE amp U0TCTL Re enable edge detect BIC SCG0 SCG1 0 SP Enable BRCLK DCO RETI p B Note Break Detect With Halted UART Clock When using the receive start edge detect feature a break condition cannot be detected when the BRCLK source is off LLLLLLLL USART Peripheral Interface UART Mode 13 19 USART Operation UART Mode Receive Start Edge Detect Conditions When URXSE 1 glitch suppression prevents the USART from being accidentally started Any low level on URXDx shorter than the deglitch time t approximately 300 ns will be ignored by the USART and no interrupt request will be generated as shown in Figure 13 12 See the device specific datasheet for parameters Figure 13 12 Glitch Suppression USART
71. not take place LLLLL Figure 11 1 Timer_A Block Diagram TASSELx i TACLK 00 Divider 16 bit Timer i ACLK 01 1 2 4 8 gt TAR i Clear SMCLK 10 INCLK 11 TACLR CCISx CMx COV CCI2A 00 Capture CCI2B 01 Mode EY GND 10 Timer Clock f gt Sync i VCC 11 CCl SCCI Y 15 Timer A Introduction Count Set TAIFG V Comparator 2 EQU2 OUT OUT Signal Timer A I I I I Li I i i I i i CAP I i Set TACCR2 CCIFG I I I I Li I i I 11 3 Timer_A Operation 11 2 Timer_A Operation The Timer_A module is configured with user software The setup and operation of Timer_A is discussed in the following sections 11 2 1 16 Bit Timer Counter The 16 bit timer counter register TAR increments or decrements depending on mode of operation with each rising edge of the clock signal TAR can be read or written with software Additionally the timer can generate an interrupt when it overflows TAR may be cleared by setting the TACLR bit Setting TACLR also clears the clock divider and count direction for up down mode 7 1 Note Modifying Timer A Registers It is recommended to stop the timer before modifying its operation with exception of the interrupt enable interrupt flag
72. occurred 12C bus busy bit A START condition sets I2CBB to 1 I2CBB is reset by a STOP condition or when I2ZCEN 0 O C bus not busy 1 12C bus busy USART Peripheral Interface I C Mode 15 23 12C Module Registers I2CDRW I2CDRB I2C Data Register 15 14 13 12 11 10 9 8 I2CDRW High Byte rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 I2CDRW Low Byte I2CDRB rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 I2CDRW Bits I2C Data When I2CWORD 1 the register name is IICDRW When I2ZCDRB 15 8 I2CWORD 0 the name is I2ZCDRB When I2CWORD 1 any attempt to modify the register with a byte instruction will fail and the register will not be updated I2CNDAT I C Transfer Byte Count Register 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 I2ZCNDATx Bits I2C number of bytes This register supports automatic data byte counting for 7 0 master mode In word mode I2CNDATx must be an even value 15 24 USART Peripheral Interface I7C Mode 12C Module Registers I2CPSC I2C Clock Prescaler Register 7 6 5 4 3 2 1 0 I2CPSCx rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 mE Modifiable only when I2CEN 0 I2CPSCx Bits 12C clock prescaler The 12C clock input I2CIN is divided by the IPCPSCx value 7 0 to produce the internal 12C clock frequency The division rate is I2CPSCx 1 I2CPSCx values gt 4 are not recommended The I2CSCLL and I2CSCLH registers should be used to set the SCL frequency 000h Divide by 1 001h Divide by 2
73. overflow occurs otherwise reset OSCOFF CPUOFF and GIE are not affected See example at the SBC instruction See example at the SBC B instruction p Note Borrow Is Treated as a NOT The borrow is treated as a NOT carry Borrow Carry bit Yes 0 No 1 LLLLLLS O O e MMMMM V 3 66 RISC 16 Bit CPU SUBC W SBB W SUBC B SBB B Syntax Operation Description Status Bits Mode Bits Example Example Instruction Set Subtract source and borrow NOT carry from destination Subtract source and borrow NOT carry from destination SUBC src dst or SUBC W src dst or SBB src dst or SBB W src dst SUBC B src dst or SBB B src dst dst NOT src C dst or dst src 1 C dst The source operand is subtracted from the destination operand by adding the source operand s 1s complement and the carry bit C The source operand is not affected The previous contents of the destination are lost N Set if result is negative reset if positive Z Set if result is zero reset otherwise C Set if there is a carry from the MSB of the result reset otherwise Set to 1 if no borrow reset if borrow V Setif an arithmetic overflow occurs reset otherwise OSCOFF CPUOFF and GIE are not affected Two floating point mantissas 24 bits are subtracted LSBs are in R13
74. parameters and ACLK is sourced from LFXT1 in LF mode Status register control bits SCGO SCG1 OSCOFF and CPUOFF configure the MSP430 operating modes and enable or disable portions of the basic clock module See Chapter System Resets Interrupts and Operating Modes The DCOCTL BCSCTL1 and BCSCTL2 registers configure the basic clock module The basic clock can be configured or reconfigured by software at any time during program execution for example BIS B RSEL2 RSEL1 RSELO amp BCSCTL1 BIS B DCO2 DCO1 DCO0 amp DCOCTL Set max DCO frequency Basic Clock Module Features for Low Power Applications Conflicting requirements typically exist in battery powered MSP430x1xx applications Low clock frequency for energy conservation and time keeping j High clock frequency for fast reaction to events and fast burst processing capability The basic clock module addresses the above conflicting requirements by allowing the user to select from the three available clock signals ACLK MCLK and SMCLK For optimal low power performance the ACLK can be configured to oscillate with a low power 32 768 Hz watch crystal providing a stable time base for the system and low power stand by operation The MCLK can be configured to operate from the on chip DCO that can be only activated when requested by interrupt driven events The SMCLK can be configured to operate from a crystal or the DCO depending on peripheral requirements A flexible
75. prevent unintended results For example if MOV 0 R4 O R4 is used and the value in R4 is 120h then a security violation will occur with the watchdog timer address 120h because the security key was not used LLLLLL RISC 16 Bit CPU 3 53 Instruction Set POP W POP B Syntax Operation Emulation Emulation Description Status Bits Example Example Example Example Pop word from stack to destination Pop byte from stack to destination POP dst POP B dst SP temp SP 2 gt SP temp dst MOV SP dst or MOVW SP3 dst MOV B SP dst The stack location pointed to by the stack pointer TOS is moved to the destination The stack pointer is incremented by two afterwards Status bits are not affected The contents of R7 and the status register are restored from the stack POP R7 POP SR Restore R7 Restore status register The contents of RAM byte LEO is restored from the stack POP B LEO The low byte of the stack is moved to LEO The contents of R7 is restored from the stack POP B R7 The low byte of the stack is moved to R7 the high byte of R7 is 00h The contents of the memory pointed to by R7 and the status register are restored from the stack POP B 0 R7 The low byte of the stack is moved to the the byte which is pointed to by
76. register ADC12IFG Read write 01A4h Reset with POR ADC12 interrupt enable register ADC12IE Read write 01A6h Reset with POR ADC12 interrupt vector word ADC12IV Read 01A8h Reset with POR ADC12 memory 0 ADC12MEMO Read write 0140h Unchanged ADC12 memory 1 ADC12MEM 1 Read write 0142h Unchanged ADC12 memory 2 ADC12MEM2 Read write 0144h Unchanged ADC12 memory 3 ADC12MEM3 Read write 0146h Unchanged ADC12 memory 4 ADC12MEM4 Read write 0148h Unchanged ADC12 memory 5 ADC12MEM5 Read write 014Ah Unchanged ADC12 memory 6 ADC12MEM6 Read write 014Ch Unchanged ADC12 memory 7 ADC12MEM7 Read write 014Eh Unchanged ADC12 memory 8 ADC12MEM8 Read write 0150h Unchanged ADC12 memory 9 ADC12MEM9 Read write 0152h Unchanged ADC12 memory 10 ADC12MEM10 Read write 0154h Unchanged ADC12 memory 11 ADC12MEM11 Read write 0156h Unchanged ADC12 memory 12 ADC12MEM12 Read write 0158h Unchanged ADC12 memory 13 ADC12MEM13 Read write 015Ah Unchanged ADC12 memory 14 ADC12MEM14 Read write 015Ch Unchanged ADC12 memory 15 ADC12MEM15 Read write 015Eh Unchanged ADC12 memory control 0 ADC12MCTLO Read write 080h Reset with POR ADC12 memory control 1 ADC12MCTL1 Read write 081h Reset with POR ADC12 memory control 2 ADC12MCTL2 Read write 082h Reset with POR ADC12 memory control 3 ADC12MCTL3 Read write 083h Reset with POR ADC12 memory control 4 ADC12MCTL4 Read write 084h Reset with POR ADC12 memory control 5 ADC12MCTL5 Read write 085h Reset with POR ADC12 memory control 6 ADC12MCTL6 Read write 086h Reset
77. rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 1 PENA Bit 7 Parity enable 0 Parity disabled 1 Parity enabled Parity bit is generated UTXDx and expected URXDx In address bit multiprocessor mode the address bit is included in the parity calculation PEV Bit 6 Parity select PEV is not used when parity is disabled 0 Odd parity 1 Even parity SPB Bit 5 Stop bit select Number of stop bits transmitted The receiver always checks for one stop bit 0 One stop bit 1 Two stop bits CHAR Bit 4 Character length Selects 7 bit or 8 bit character length 0 7 bit data 1 8 bit data LISTEN Bit 3 Listen enable The LISTEN bit selects loopback mode 0 Disabled 1 Enabled UTXDx is internally fed back to the receiver SYNC Bit 2 Synchronous mode enable 0 UART mode 1 SPI Mode MM Bit 1 Multiprocessor mode select 0 Idle line multiprocessor protocol 1 Address bit multiprocessor protocol SWRST Bit 0 Software reset enable 0 Disabled USART reset released for operation 1 Enabled USART logic held in reset state 13 22 USART Peripheral Interface UART Mode USART Registers UART Mode UxTCTL USART Transmit Control Register 7 rw 0 Unused CKPL SSELx URXSE TXWAKE Unused TXEPT Bit 7 Bit 6 Bits 5 4 Bit 3 Bit 2 Bit 1 Bit 0 5 4 3 2 1 0 unused CKPL SSELx TXWAKE uet TXEPT rw 0 rw rw 1 rw 0 rw 0 rw 0 rw 0 0 Unused Clock polarity select 0 UCLKI UCLK 1 UCLKI inverted UCLK Source select These bits se
78. set 0 1 1 Unchanged 120 0 Unchanged 10 1 May be set LLLLLLL Interrupt Enable P1IE P2IE Each PxIE bit enables the associated PxIFG interrupt flag Bit 0 The interrupt is disabled Bit 1 The interrupt is enabled 9 2 6 Configuring Unused Port Pins Unused I O pins should be configured as I O function output direction and left unconnected on the PC board to reduce power consumption The value of the PxOUT bit is don t care since the pin is unconnected See chapter System Resets Interrupts and Operating Modes for termination unused pins 9 6 Digital I O 9 3 Digital I O Registers Table 9 1 Digital V O Registers Port P1 P2 P3 P4 P5 P6 Digital I O Registers Seven registers are used to configure P1 and P2 Four registers are used to configure ports P3 P6 The digital I O registers are listed in Table 9 1 Register Input Output Direction Interrupt Flag Interrupt Edge Select Interrupt Enable Port Select Input Output Direction Interrupt Flag Interrupt Edge Select Interrupt Enable Port Select Input Output Direction Port Select Input Output Direction Port Select Input Output Direction Port Select Input Output Direction Port Select Short Form P1IN P1OUT P1DIR P1IFG P1IES P1IE P1SEL P2IN P2OUT P2DIR P2IFG P2IES P2IE P2SEL P3IN P3OUT P3DIR P3SEL P4IN P4OUT P4D
79. shown in Table 12 3 The CLLDx bits of the controlling TBCCRx must not be set to zero When the CLLDx bits of the controlling TBCCRx are set to zero all compare latches update immediately when their corresponding TBCCRx is written no compare latches are grouped Two conditions must exist for the compare latches to be loaded when grouped First all TBCCRx registers of the group must be updated even when new TBCCRx data old TBCCRx data Second the load event must occur Table 12 3 Compare Latch Operating Modes TBCLGRPx Grouping Update Control 00 None Individual 01 TBCL1 TBCL2 TBCCR1 TBCL3 TBCL4 TBCCR3 TBCL5 TBCL6 TBCCR5 10 TBCL1 TBCL2 TBCL3 TBCCR1 TBCL4 TBCL5 TBCL6 TBCCR4 11 TBCLO TBCL1 TBCL2 TBCCR1 TBCL3 TBCL4 TBCL5 TBCL6 Timer_B 12 13 Timer_B Operation 12 2 5 Output Unit Each capture compare block contains an output unit The output unit is used to generate output signals such as PWM signals Each output unit has eight operating modes that generate signals based on the EQUO and EQUXx signals The TBOUTH pin function can be used to put all Timer_B outputs into a high impedance state When the TBOUTH pin function is selected for the pin and when the pin is pulled high all Timer_B outputs are in a high impedance state Output Modes The output modes are defined by the OUTMODx bits and are described in Table 12 4 The OUTx signal is changed with the rising edge of the timer clock for all modes except mode 0 Outp
80. the addressing modes used not the instruction itself The number of clock cycles refers to the MCLK Interrupt and Reset Cycles Table 3 14 lists the CPU cycles for interrupt overhead and reset Table 3 14 Interrupt and Reset Cycles No of Length of Action Cycles Instruction Return from interrupt RETI 5 1 Interrupt accepted 6 WDT reset 4 Reset RST NMI 4 E Format ll Single Operand Instruction Cycles and Lengths Table 3 15 lists the length and CPU cycles for all addressing modes of format ll instructions Table 3 15 Format ll Instruction Cycles and Lengths No of Cycles Addressing RRA RRC Length of Mode SWPB SXT PUSH CALL Instruction Example Rn 1 3 4 1 SWPB R5 Rn 3 4 4 1 RRC R9 Rn 3 5 5 1 SWPB R10 N See note 4 5 2 CALL 0F000h X Rn 4 5 5 2 CALL 2 R7 EDE 4 5 5 2 PUSH EDE amp EDE 4 5 5 2 SXT amp EDE Note Instruction Format Il Immediate Mode Do not use instructions RRA RRC SWPB and SxT with the immediate mode in the destination field Use of these in the immediate mode results in an unpredictable program operation Cd Format lll Jump Instruction Cycles and Lengths All jump instructions require one code word and take two CPU cycles to execute regardless of whether the jump is taken or not 3 72 RISC 16 Bit CPU Instruction Set Format l Double Operand Instruction Cycles and Lengths Table 3 16 lists the length and CPU cycles for all addressing modes of format l instr
81. the stack pointer RETI Note Enable Interrupt The instruction following the enable interrupt instruction EINT is always executed even if an interrupt service request is pending when the interrupts are enable eee 3 40 RISC 16 Bit CPU INCLW INC B Syntax Operation Emulation Description Status Bits Mode Bits Example Instruction Set Increment destination Increment destination INC dst or INC W dst INC B dst dst 1 dst ADD 1 dst The destination operand is incremented by one The original contents are lost N Set if result is negative reset if positive Z Set if dst contained OFFFFh reset otherwise Set if dst contained OFFh reset otherwise C Set if dst contained OFFFFh reset otherwise Set if dst contained OFFh reset otherwise V Set if dst contained 07FFFh reset otherwise Set if dst contained 07Fh reset otherwise OSCOFF CPUOFF and GIE are not affected The status byte STATUS of a process is incremented When it is equal to 11 a branch to OVFL is taken INC B STATUS CMP B 11 STATUS JEQ OVFL RISC 16 Bit CPU 3 41 Instruction Set INCD W INCD B Syntax Operation Emulation Emulation Example Status Bits Mode Bits Example Example Double increment destination Double increment destination INCD dst or INCD W dst INCD B dst dst 2 gt dst ADD 2 dst ADD B 2 dst The destination operand is incremented by two The original co
82. the start byte is initiated I2CSTB is automatically cleared 0 No action 1 Send START condition and start byte 01h but no STOP condition STOP bit This bit is used to generate STOP condition After the STOP condition the I2CSTP is automatically cleared 0 No action 1 Send STOP condition START bit This bit is used to generate a START condition After the start condition the I2CSTT is automatically cleared 0 No action 1 Send START condition USART Peripheral Interface 2C Mode 12C Module Registers I2CDCTL I2C Data Control Register 7 Unused I2CBUSY 12C SCLLOW I2ZCSBD I2CTXUDF I2CRXOVR I2CBB Bits 7 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 5 4 3 2 1 0 12C used I2CBUSY SCLLOW I2CSBD I2CTXUDF I2CRXOVR I2CBB r 0 r 0 r 0 r 0 r 0 r 0 ro ro Unused Always read as 0 12C busy O 12C module is idle 1 12C module is not idle 12C SCL low This bit indicates if a slave is holding the SCL line low while the MSP430 is the master and is unused in slave mode 0 SCL is not being held low 1 SCL is being held low I2C single byte data This bit indicates if the receive register IICDRW holds a word or a byte I2CSBD is valid only when I2CWORD 1 0 A complete word was received 1 Only the lower byte in I2CDR is valid 12C transmit underflow 0 No underflow occurred 1 Transmit underflow occurred l2C receive overrun 0 No receive overrun occurred 1 Receiver overrun
83. the temperature sensor automatically turns on the on chip reference generator as a voltage source for the temperature sensor However it does not enable the Vref output or affect the reference selections for the conversion The reference choices for converting the temperature sensor are the same as with any other channel Figure 17 10 Typical Temperature Sensor Transfer Function 17 16 ADC12 Volts 1 300 1 200 1 100 1 000 0 900 VTEMP 0 00355 TEMPC 0 986 0 800 0 700 Celsius ADC 12 Operation 17 2 9 ADC12 Grounding and Noise Considerations As with any high resolution ADC appropriate printed circuit board layout and grounding techniques should be followed to eliminate ground loops unwanted parasitic effects and noise Ground loops are formed when return current from the A D flows through paths that are common with other analog or digital circuitry If care is not taken this current can generate small unwanted offset voltages that can add to or subtract from the reference or input voltages of the A D converter The connections shown in Figure 17 11 help avoid this In addition to grounding ripple and noise spikes on the power supply lines due to digital switching or switching power supplies can corrupt the conversion result A noise free design using separate analog and digital ground planes with a single point connection is recommend to achieve high accuracy Figure 17 11 ADC 12 Grounding and Noise
84. this manual Status register SR is reset The watchdog timer powers up active in watchdog mode Program counter PC is loaded with address contained at reset vector location OFFFEh CPU execution begins at that address After a system reset user software must initialize the MSP430 for the application requirements The following must occur m m m Initialize the SP typically to the top of RAM Initialize the watchdog to the requirements of the application Configure peripheral modules to the requirements of the application Additionally the watchdog timer oscillator fault and flash memory flags can be evaluated to determine the source of the reset System Resets Interrupts and Operating Modes 2 5 System Reset and Initialization 2 2 Interrupts The interrupt priorities are fixed and defined by the arrangement of the modules in the connection chain as shown in Figure 2 4 The nearer a module is to the CPU NMIRS the higher the priority Interrupt priorities determine what interrupt is taken when more than one interrupt is pending simultaneously There are three types of interrupts System reset J Non maskable NMI Maskable Figure 2 4 Interrupt Priority Priority High Low PUC OSCfault Flash ACCV Circuit Reset NMI WDT Security Key Weed Flash Security Key _ 7 NA hv XZ Z Sf lt MAB 5LSBs gt 2 6 S
85. when SWRST 1 The operation is shown is Figure 13 10 Figure 13 10 Transmit Interrupt Operation UTXIEx PUC or SWRST ice R uec dais Service Requested a SWRST Voc Character Moved From Buffer to Shift Register Data written to UXTXBUF IRQA USART Peripheral Interface UART Mode 13 17 USART Operation UART Mode USART Receive Interrupt Operation The URXIFGx interrupt flag is set each time a character is received and loaded into UXRXBUF An interrupt request is generated if URXIEx and GIE are also set URXIFGx and URXIEx are reset by a system reset PUC signal or when SWRST 1 URXIFGx is automatically reset if the pending interrupt is served when URXSE 0 or when UxRXBUF is read The operation is shown in Figure 13 11 Figure 13 11 Receive Interrupt Operation From URXD URXWIE RXWAKE 13 18 SYNC m e Valid Start Bit Receiver Collects Character URXSE E DH URXIEx Interrupt Service a Requested URXIFGx 6 m SWRST PUC UxRXBUF Read URXSE IRQA Character Received or Break Detected URXEIE is used to enable or disable erroneous characters from setting URXIFGx When using multiprocessor addressing modes URXWIE is used to auto detect valid address characters and reject unwanted data characters Two types of characters do not set URXIFGx Erroneous characters when URXEIE 0 L Non address char
86. with POR ADC12 memory control 7 ADC12MCTL7 Read write 087h Reset with POR ADC12 memory control 8 ADC12MCTL8 Read write 088h Reset with POR ADC12 memory control 9 ADC12MCTL9 Read write 089h Reset with POR ADC12 memory control 10 ADC12MCTL10 Read write 08Ah Reset with POR ADC12 memory control 11 ADC12MCTL11 Read write 08Bh Reset with POR ADC12 memory control 12 ADC12MCTL12 Read write 08Ch Reset with POR ADC12 memory control 13 ADC12MCTL13 Read write 08Dh Reset with POR ADC12 memory control 14 ADC12MCTL14 Read write 08Eh Reset with POR ADC12 memory control 15 ADC12MCTL15 Read write 08Fh Reset with POR 17 20 ADC12 ADC 12 Registers ADC12CTLO ADC12 Control Register 0 15 14 13 12 11 10 9 8 mm rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 oe mm wes avcizone did ene ee rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 m Modifiable only when ENC 0 SHT1x Bits Sample and hold time These bits define the number of ADC12CLK cycles in 15 12 the sampling period for registers ADC12MEM8 to ADC12MEM 15 SHTOx Bits Sample and hold time These bits define the number of ADC12CLK cycles in 11 8 the sampling period for registers ADC12MEMO to ADC12MEM7 SHTx Bits ADC12CLK cycles 0000 4 0001 8 0010 16 0011 32 0100 64 0101 96 0110 128 0111 192 1000 256 1001 384 1010 512 1011 768 1100 1024 1101 1024 1110 1024 1111 1024 ADC12 17 21 ADC 12 Registers MSC REF2_5V REFON ADC120N Bit 7
87. xxh amp MPY 1 1 before using the hardware multiplier Disable interrupts Required for DINT Load 1st operand Load 2nd operand Interrupts may be enable before Process results Hardware Multiplier Registers 7 3 Hardware Multiplier Registers The hardware multiplier registers are listed in Table 7 4 Table 7 4 Hardware Multiplier Registers Register Short Form Register Type Address Initial State Operand one multiply MPY Read write 0130h Unchanged Operand one signed multiply MPYS Read write 0132h Unchanged Operand one multiply accumulate MAC Read write 0134h Unchanged Operand one signed multiply accumulate MACS Read write 0136h Unchanged Operand two OP2 Read write 0138h Unchanged Result low word RESLO Read write 013Ah Undefined Result high word RESHI Read write 013Ch Undefined Sum Extension register SUMEXT Read 013Eh Undefined Hardware Multiplier 7 7 Chapter 8 DMA Controller The DMA controller module transfers data from one address to another without CPU intervention This chapter describes the operation of the DMA controller The DMA controller is implemented in MSP430x15x and MSP430x16x devices Topic Page Bile HOMAIlninoductlonie des rct cL Ped 8 2 DMA Operation meeen eenean I6 ET ESTEE ET 8 3 DMA Heglsters erre rer Ree ae emi rere ai 8 18 8 1 DMA Introduction 8 1 DMA Introduction The direct memory access DMA controller transfers data from one address to another wit
88. zero reset otherwise NOT Zero V Reset OSCOFF CPUOFF and GIE are not affected Figure 3 19 Destination Operand Sign Extension Example 15 8 7 0 R7 is loaded with the P1IN value The operation of the sign extend instruction expands bit 8 to bit 15 with the value of bit 7 R7 is then added to R6 MOV B amp P1IN R7 P1IN 080h 1000 0000 SXT R7 R7 OFF80h 1111 1111 1000 0000 RISC 16 Bit CPU 3 69 Instruction Set TST W TST B Syntax Operation Emulation Description Status Bits Mode Bits Example Example Test destination Test destination TST dst or TST W dst TST B dst dst OFFFFh 1 dst OFFh 1 CMP 0 dst CMP B 0 dst The destination operand is compared with zero The status bits are set accord ing to the result The destination is not affected N Set if destination is negative reset if positive Z Set if destination contains zero reset otherwise C Set V Reset OSCOFF CPUOFF and GIE are not affected R7 is tested If it is negative continue at R7NEG if it is positive but not zero continue at R7POS TST R7 Test R7 JN R7NEG R7 is negative JZ R7ZERO R7 is zero R7POS J R7 is positive but not zero RZNEG xs R7 is negative R7ZERO R7 is zero The low byte of R7 is tested If it is negative continue at R7NEG if it is positive but not zero continue at R7POS TST B R7 Test low byte of R7 JN R7NEG Low byte of R7 is ne
89. 1 AND NMI event T Size gt DMAxSZ OR DMAxSA T SourceAdd DMALEVEL 1 DMAxDA T DestAdd AND Trigger 0 DMAxSZ 0 Decrement DMAxSZ Modify T SourceAdd Modify T DestAdd DMAxSZ 0 AND i DMAxSZ gt 0 a multiple of 4 words bytes were transferred DMADTx 6 7 AND DMAxSZ 0 2x MCLK J A Burst State release CPU for 2x MCLK DMA Controller 8 11 DMA Operation 8 2 3 Initiating DMA Transfers Each DMA channel is independently configured for its trigger source with the DMAXxTSELx bits as described in Table 8 2 The DMAxTSELx bits should be modified only when the DMACTLx DMAEN bit is 0 Otherwise unpredictable DMA triggers may occur When selecting the trigger the trigger must not have already occurred or the transfer will not take place For example if the TACCR2 CCIFG bit is selected as a trigger and it is already set no transfer will occur until the next time the TACCR2 CCIFG bit is set Edge Sensitive Triggers When DMALEVEL 0 edge sensitive triggers are used and the rising edge of the trigger signal initiates the transfer In single transfer mode each transfer requires its own trigger When using block or burst block modes only one trigger is required to initiate the block or burst block transfer Level Sensitive Triggers When DMALEVEL 1 level sensitive triggers are used For proper operation level sensitive triggers can only be used when external trigger
90. 1 The pin is connected to CA1 P2CAO Bit 2 Pin to CAO This bit selects the CAO pin function 0 The pin is not connected to CAO 1 The pin is connected to CAO CAF Bit 1 Comparator_A output filter 0 Comparator_A output is not filtered 1 Comparator_A output is filtered CAOUT Bit 0 Comparator_A output This bit reflects the value of the comparator output Writing this bit has no effect CAPD Comparator A Port Disable Register rw 0 CAPDx Bits 7 0 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Comparator_A port disable These bits individually disable the input buffer for the pins of the port associated with Comparator A For example if CAO is on pin P2 3 the CAPDx bits can be used to individually enable or disable each P2 x pin buffer CAPDO disables P2 0 CAPD1 disables P2 1 etc 0 The input buffer is enabled 1 The input buffer is disabled Comparator A 16 11 ADC12 The ADC12 module is a high performance 12 bit analog to digital converter This chapter describes the ADC12 The ADC12 is implemented in the MSP430x13x MSP430x14x MSP430x15x and MSP430x16x devices Topic Page 17 1 ADC12 Introduction seses ea semet 989 eo MEETS 17 2 17 2 ADC12 Operation EE MEER 17 4 17 3 ADC12 Registers Ta a a a E reper iar E a eve esete e aE 17 20 17 1 ADC 12 Introduction 17 1 ADC12 Introduction 17 2 ADC12 The ADC12 module supports fast 12 bit analog to digital c
91. 10 9 8 rw rw rw rw rw rw rw rw T 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw DMAxDAx Bits DMA destination address The destination address register points to the 15 0 destination address for single transfers or the first address for block transfers The DMAxDA register remains unchanged during block and burst block transfers DMAxSZ DMA Size Address Register 15 14 13 12 11 10 9 8 rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw DMAxSZx Bits DMA size The DMA size register defines the number of byte word data per 15 0 block transfer DMAxSZ register decrements with each word or byte transfer When DMAxSZ decrements to 0 it is immediately and automatically reloaded with its previously initialized value 00000h Transfer is disabled 00001h One byte or word is transferred 00002h Two bytes or words are transferred OFFFFh 65535 bytes or words are transferred DMA Controller 8 mm Co Chapter 9 Digital 1 0 This chapter describes the operation of the digital I O ports Ports P1 P2 are implemented in MSP430x11xx devices Ports P1 P3 are implemented in MSP430x12xx devices Ports P1 P6 are implemented in MSP430x13x MSP430x14x MSP430x15x and MSP430x16x devices Topic Page Sree Digltalil Introduction estrone greene c cme 92 bigitallLO Operation o990 9090209 enema de Tus 9 3aeDigitalll OiBegistersz ecce I II 9 7 9 1 Digital I O Introduction 9 1 Digital I O Introduction 9 2 Digital I O
92. 111 Vg Verner and Vp Vngr VeREF ADC10 Bits ADC10 sample and hold time SHTx 12 41 00 4xADC10CLKs 01 8x ADC10CLKs 10 16x ADC10CLKs 11 64x ADC10CLKs ADC1OSR Bit10 ADC10 sampling rate This bit selects the reference buffer drive capability for the maximum sampling rate Setting ADC10SR reduces the current consumption of the reference buffer 0 Reference buffer supports up to 200 ksps 1 Reference buffer supports up to 50 ksps REFOUT Bit 9 Reference output 0 Reference output off 1 Reference output on REFBURST Bit 8 Reference burst REFOUT must also be set 0 Reference buffer on continuously 1 Reference buffer on only during sample and conversion ADC10 18 25 ADC10 Registers MSC REF2_5V REFON ADC100N ADC10IE ADC10IFG ENC ADC10SC 18 26 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADC10 Multiple sample and conversion Valid only for sequence or repeated modes The sampling requires a rising edge of the SHI signal to trigger each sample and conversion 1 The first rising edge of the SHI signal triggers the sampling timer but further sample and conversions are performed automatically as soon as the prior conversion is completed Reference generator voltage REFON must also be set 0 15V 1 2 5 V Reference generator on 0 Reference off 1 Reference on ADC10 on 0 ADC10 off 1 ADC10 on ADC10 interrupt enable 0 Interrupt disabled 1 interrupt enabled ADC10 int
93. 16 bit timer counter with multiple capture compare registers This chapter describes Timer B Timer B3 three capture compare registers is implemented in MSP430x13x and MSP430x1 5x devices Timer B7 seven capture compare registers is implemented in MSP430x14x and MSP430x16x devices Topic Page 12 1 Timer B Introduction conenaacpenoeeneedoenpoonessauoneuccacdad 12 2 122 Timer B Operation s ane ee ae ese E ED MEE ET 12 3 fimar B Registers ccc 92 0rd cee een ee ee ees re 12 20 12 1 Timer_B Introduction 12 1 Timer_B Introduction Timer_B is a 16 bit timer counter with three or seven capture compare registers Timer_B can support multiple capture compares PWM outputs and interval timing Timer_B also has extensive interrupt capabilities Interrupts may be generated from the counter on overflow conditions and from each of the capture compare registers Timer_B features include 1 Asynchronous 16 bit timer counter with four operating modes and four selectable lengths Selectable and configurable clock source Three or seven configurable capture compare registers Configurable outputs with PWM capability Double buffered compare latches with synchronized loading LE Lu Q Interrupt vector register for fast decoding of all Timer B interrupts The block diagram of Timer B is shown in Figure 12 1 Note Use of the Word Count Count is used throughout this chapter It means the counter must be in the p
94. 35 fFTG When a byte word write is executed from RAM the CPU continues to execute code from RAM The BUSY bit must be zero before the CPU accesses flash again otherwise an access violation occurs ACCVIFG is set and the write result is unpredictable 5 8 Flash Memory Controller Flash Memory Operation In byte word mode the internally generated programming voltage is applied to the complete 64 byte block each time a byte or word is written for 32 of the 35 feta cycles With each byte or word write the amount of time the block is subjected to the programming voltage accumulates The cumulative programming time tcpr must not be exceeded for any block If the cumulative programming time is met the block must be erased before performing any further writes to any address within the block See the device specific datasheet for specifications Initiating a Byte Word Write from Within Flash Memory The flow to initiate a byte word write from flash is shown in Figure 5 8 Figure 5 8 Initiating a Byte Word Write from Flash Disable all interrupts and watchdog Setup flash controller and set WRT 1 Write byte or word Set WRT 0 LOCK 1 re enable interrupts and watchdog Byte word write from flash Assumes OFF1Eh is already erased Assumes ACCVIE NMIIE OFIE WDTPW WDTHOLD amp WDTCTL m Disable WDT FWKEY FSSEL1 FNO amp FCTL2 FWKEY amp FCTL3 FWKEY WRT amp FCTL1 0123h amp OFF
95. 71 April 2015 Corrections to MSP430x1xx Family User s Guide SLAU049 1 Submit Documentation Feedback Copyright 2015 Texas Instruments Incorporated IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the right to make corrections enhancements improvements and other changes to its semiconductor products and services per JESD46 latest issue and to discontinue any product or service per JESD48 latest issue Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All semiconductor products also referred to herein as components are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its components to the specifications applicable at the time of sale in accordance with the warranty in Tl s terms and conditions of sale of semiconductor products Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by applicable law testing of all parameters of each component is not necessarily performed TI assumes no liability for applications assistance or the design of Buyers products Buyers are responsible for their products and applications using Tl components To minimize the risks associated with Buyers products and applications Buyers should provide adequate design and operatin
96. 80h Reset with POR Timer B counter TBR Read write 0190h Reset with POR Timer B capture compare control 0 TBCCTLO Read write 0182h Reset with POR Timer B capture compare 0 TBCCRO Read write 0192h Reset with POR Timer B capture compare control 1 TBCCTL1 Read write 0184h Reset with POR Timer B capture compare 1 TBCCR1 Read write 0194h Reset with POR Timer B capture compare control 2 TBCCTL2 Read write 0186h Reset with POR Timer B capture compare 2 TBCCR2 Read write 0196h Reset with POR Timer B capture compare control 3 TBCCTLS3 Read write 0188h Reset with POR Timer B capture compare 3 TBCCRS3 Read write 0198h Reset with POR Timer B capture compare control 4 TBCCTL4 Read write 018Ah Reset with POR Timer_B capture compare 4 TBCCR4 Read write 019Ah Reset with POR Timer_B capture compare control 5 TBCCTL5 Read write 018Ch Reset with POR Timer B capture compare 5 TBCCR5 Read write 019Ch Reset with POR Timer B capture compare control 6 TBCCTL6 Read write 018Eh Reset with POR Timer B capture compare 6 TBCCR6 Read write 019Eh Reset with POR Timer B Interrupt Vector TBIV Read only 011Eh Reset with POR 12 20 Timer B Timer_B Registers Timer_B Control Register TBCTL 15 14 13 12 11 10 9 8 ue mnm o ome m m rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 T 6 5 4 3 2 1 0 oo ee rw 0 rw 0 rw 0 rw 0 rw 0 w 0 rw 0 rw 0 Unused Bit i5 Unused TBCLGRP Bit TBCLx group 14 13 00 Each TBCLx latch loads independently 01 TBCL1 TBCL2
97. A capture compare control 2 Timer_A capture compare 2 Short Form TACTL TAR TACCTLO TACCRO TACCTL1 TACCR1 TACCTL2 TACCR2 TAIV Register Type Address Read write Read write Read write Read write Read write Read write Read write Read write 0160h 0170h 0162h 0172h 0164h 0174h 0166h 0176h 012Eh Timer_A Registers Initial State Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Timer_A interrupt vector Read only Reset with POR Timer_A 11 19 Timer_A Registers TACTL Timer_A Control Register 15 14 13 12 11 10 9 8 met O o CER rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 o m m mom are rw 0 rw 0 rw 0 rw 0 rw 0 w 0 rw 0 rw 0 Unused Bits Unused 15 10 TASSELx Bits Timer_A clock source select 9 8 00 TACLK 01 ACLK 10 SMCLK 11 INCLK IDx Bits Input divider These bits select the divider for the input clock 7 6 00 A 01 2 10 4 11 8 MCx Bits Mode control Setting MCx 00h when Timer A is not in use conserves 5 4 power 00 Stop mode the timer is halted 01 Up mode the timer counts up to TACCRO 10 Continuous mode the timer counts up to OFFFFh 11 Up down mode the timer counts up to TACCRO then down to 0000h Unused Bit 3 Unused TACLR Bit 2 Timer A clear Setting this bit resets TAR the clock divider and the count direction The TACLR bit is automatically reset and is al
98. ADC10CT bit is set The DTC will not stop after block one in one block mode or block two two block mode has been transferred The internal address pointer and transfer counter are set equal to ADC10SA and n respectively Transfers continue starting in block one If the ADC10CT bit is reset DTC transfers cease after the current completion of transfers into block one in the one block mode or block two in the two block mode have been transfer DTC Transfer Cycle Time For each ADC10MEM transfer the DTC requires one or two MCLK clock cycles to synchronize one for the actual transfer while the CPU is halted and one cycle of wait time Because the DTC uses MCLK the DTC cycle time is dependent on the MSP430 operating mode and clock system setup If the MCLK source is active but the CPU is off the DTC uses the MCLK source for each transfer without re enabling the CPU If the MCLK source is off the DTC temporarily restarts MCLK sourced with DCOCLK only during a transfer The CPU remains off and after the DTC transfer MCLK is again turned off The maximum DTC cycle time for all operating modes is show in Table 18 2 Table 18 2 Maximum DTC Cycle Time 18 20 ADC10 CPU Operating Mode Clock Source Maximum DTC Cycle Time Active mode MCLK DCOCLK 3 MCLK cycles Active mode MCLK LFXT1CLK 3 MCLK cycles Low power mode LPMO 1 MCLK DCOCLK 4 MCLK cycles Low power mode LPM3 4 MCLK DCOCLK 4 MCLK cycles 6 ust Low power mode LPMO 1
99. Assembler Code Content of ROM MOV 2 R5 6 R6 MOV X R5 Y R6 X22 Y 6 Length Two or three words Operation Move the contents of the source address contents of R5 2 to the destination address contents of R6 6 The source and destination registers R5 and R6 are not affected In indexed mode the program counter is incremented automatically so that program execution continues with the next instruction Comment Valid for source and destination Example MOV 2 R5 6 R6 Before After Address Register Address Register Space Space Oxxxxh PC OFF16h 00006h R5 01080h OFF16h 00006h R5 01080h OFF14h 00002h R6 0108Ch OFF14h 00002h R6 0108Ch OFF12h 04596h PC OFF12h 04596h 0108Ch 01094h 0006h 01094h 01092h 05555h 01092h o109on 01234h 01080h 01082h 01234h angees 01082h 01234h RISC 16 Bit CPU 3 11 Addressing Modes 3 3 8 Symbolic Mode The symbolic mode is described in Table 3 6 Table 3 6 Symbolic Mode Description Assembler Code Content of ROM MOV EDE TONI MOV X PC Y PC X EDE PC Y TONI PC Length Two or three words Operation Move the contents of the source address EDE contents of PC X to the destination address TONI contents of PC Y The words after the instruction contain the differences between the PC and the source or destination addresses The assembler computes and inserts offsets X and Y automatically With symbolic mode the program counter PC i
100. B Substitution The assembler does not recognize the instruction RLC QR5 RLC B R5 or RLC B R5 It must be substituted by ADDC R5 2 R5 ADDC B R5 1 R5 or ADDC B R5 RISC 16 Bit CPU 3 59 Instruction Set RRA W Rotate right arithmetically RRA B Rotate right arithmetically Syntax RRA dst or RRA W dst RRA B dst Operation MSB gt MSB MSB gt MSB 1 LSB 1 gt LSB LSB gt C Description The destination operand is shifted right one position as shown in Figure 3 16 The MSB is shifted into the MSB the MSB is shifted into the MSB 1 and the LSB 1 is shifted into the LSB Figure 3 16 Destination Operand Arithmetic Right Shift Status Bits N Setif result is negative reset if positive Z Setif result is zero reset otherwise C Loaded from the LSB V Reset Mode Bits OSCOFF CPUOFF and GIE are not affected Example R5 is shifted right one position The MSB retains the old value It operates equal to an arithmetic division by 2 RRA R5 R5 2 gt R5 The value in R5 is multiplied by 0 75 0 5 0 25 PUSH R5 Hold R5 temporarily using stack RRA R5 R5x0 5 gt R5 ADD SP R5 R5x0 5 R5 1 5xR5 gt R5 RRA R5 1 5 x R5 x0 52 0 75 x R5 gt R5 Example The low byte of R5 is shifted right one position The MSB retains the old value It operates equal to an arithmetic division by 2 RRA B R5 R5 2 gt R5 operation is on low byte only High byte of R5 is reset PUSH B R5 R5x0 5 gt TOS
101. Basic Clock Module Basic Clock Module Registers IE1 Interrupt Enable Register 1 7 6 5 4 3 2 1 0 rw 0 OFIE Bits 7 2 Bit 1 Bits 0 These bits may be used by other modules See device specific datasheet Oscillator fault interrupt enable This bit enables the OFIFG interrupt Because other bits in IE1 may be used for other modules it is recommended to set or clear this bit using BIS B or BIC B instructions rather than MOV B or CLR B instructions 0 Interrupt not enabled 1 Interrupt enabled This bit may be used by other modules See device specific datasheet IFG1 Interrupt Flag Register 1 7 6 5 4 3 2 1 0 rw 1 OFIFG Bits 7 2 Bit 1 Bits 0 These bits may be used by other modules See device specific datasheet Oscillator fault interrupt flag Because other bits in IFG1 may be used for other modules it is recommended to set or clear this bit using BIS B or BIC B instructions rather than MOV B or CLR B instructions 0 No interrupt pending 1 Interrupt pending This bit may be used by other modules See device specific datasheet Basic Clock Module 4 17 Chapter 5 Flash Memory Controller This chapter describes the operation of the MSP430 flash memory controller Topic Page 5 1 Flash Memory Introduction essere 5 2 5 2 Flash Memory Segmentation Lssuueueeeeeeeeeeeee 5 3 5 3 Flash Memory Operallon 5590 0809 ue eee Sree 5 4 5 4 Flash Memory Regi
102. Broadband www ti com broadband Interface interface ti com Digital Control www ti com digitalcontrol Logic logic ti com Military www ti com military Power Mgmt power ti com Optical Networking www ti com opticalnetwork Microcontrollers microcontroller ti com Security www ti com security Telephony www ti com telephony Video amp Imaging www ti com video Wireless www ti com wireless Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2006 Texas Instruments Incorporated About This Manual Preface Read This First This manual discusses modules and peripherals of the MSP430x1 xx family of devices Each discussion presents the module or peripheral in a general sense Not all features and functions of all modules or peripherals are present on all devices In addition modules or peripherals may differ in their exact implementation between device families or may not be fully implemented on an individual device or device family Pin functions internal signal connections and operational paramenters differ from device to device The user should consult the device specific datasheet for these details Related Documentation From Texas Instruments FCC Warning For related documentation see the web site http Awww ti com msp430 This equipment is intended for use in a laboratory test environment only It gen erates uses and can radiate radio frequency energy and has not been tested for compliance
103. Byte Register Operation High Byte Low Byte High Byte Low Byte Example Register Byte Operation Example Byte Register Operation R5 0A28Fh R5 01202h R6 0203h R6 0223h Mem 0203h 012h Mem 0223h 05Fh ADD B R5 0 R6 ADD B R6 R5 08Fh 05Fh 012h 002h OA1h 00061h Mem 0203h OAth R5 00061h C 0 Z 0 N 1 C 0 Z 0 N 0 Low byte of register Addressed byte Addressed byte Low byte of register Addressed byte Low byte of register zero to High byte 3 8 RISC 16 Bit CPU Addressing Modes 3 3 Addressing Modes Seven addressing modes for the source operand and four addressing modes for the destination operand can address the complete address space with no exceptions The bit numbers in Table 3 3 describe the contents of the As source and Ad destination mode bits Table 3 3 Source Destination Operand Addressing Modes As Ad Addressing Mode Syntax Description 00 0 Register mode Rn Register contents are operand 01 1 Indexed mode X Rn Rn X points to the operand X is stored in the next word 01 1 Symbolic mode ADDR PC X points to the operand X is stored in the next word Indexed mode X PC is used 01 1 Absolute mode amp ADDR The word following the instruction contains the absolute address X is stored in the next word Indexed mode X SR is used 10 Indirect register Rn Rn is used as a pointer to the mode operand 11 Indirect Rn Rnis used as a pointer to the autoincremen
104. C12_1 are grouped both DAC12_xDAT registers must be written to before the outputs update even if data for one or both of the DACs is not changed Figure 19 6 shows a latch update timing example for grouped DAC12_0 and DAC12_1 When DAC12_0 DAC12GRP 1 and both DAC12_x DAC12LSELx gt 0 and either DAC12ENC 0 neither DAC12 will update Figure 19 6 DAC12 Group Update Example Timer_A3 Trigger 19 8 DAC12_0 DAC12GRP DAC12_0 DAC12ENC TimerA_OUT1 DAC12 ODAT New Data DAC12 1DAT New Data DAC12 0 Latch Trigger DAC12 0 and DAC12 1 Updated Simultaneously Na a DAC 12 0 Updated DAC12 DAC12_0 DAC12LSELx gt 0 AND DAC12_1 DAC12LSELx 2 DAC12_0 DAC12LSELx 2 rm Note DAC12 Settling Time The DMA controller is capable of transferring data to the DAC12 faster than the DAC12 output can settle The user must assure the DAC12 settling time is not violated when using the DMA controller See the device specific data sheet for parameters et DAC 12 Operation 19 2 7 DAC12 Interrupts The DAC12 interrupt vector is shared with the DMA controller Software must check the DAC12IFG and DMAIFG flags to determine the source of the interrupt The DAC12IFG bit is set when DAC12LSELx gt 0 and DAC12 data is latched from the DAC12_xDAT register into the data latch When DAC12LSELx 0 the DAC12IFG flag is not set A set DAC12IFG bit indicates that the DAC12 is ready for new data If both the DACA12IE and
105. CLK frequency specified in the datasheet even though the DCO is capable of exceeding it Figure 4 6 DCO Frequency vs Temperature 4 8 fpco External Internal Celsius Basic Clock Module Basic Clock Module Operation 4 2 5 DCO Modulator The modulator mixes two DCO frequencies fpco and fpco 1 to produce an intermediate effective frequency between fpco and fpco 4 and spread the clock energy reducing electromagnetic interference EMI The modulator mixes fpco and fpco 1 for 33 DCOCLK clock cycles and is configured with the MODx bits When MODx 0 the modulator is off The modulator mixing formula is t 82 MODx x tpco MODx x tpco 1 Because fpcois lower than the effective frequency and fpco 4 is higher than the effective frequency the error of the effective frequency integrates to zero It does not accumulate The error of the effective frequency is zero every 32 DCOCLK cycles Figure 4 7 illustrates the modulator operation The modulator settings and DCO control are configured with software The DCOCLK can be compared to a stable frequency of known value and adjusted with the DCOx RSELx and MODx bits See http www msp430 com for application notes and example code on configuring the DCO Figure 4 7 Modulator Patterns MODx Lower DCO Tap Frequency fpco Upper DCO Tap Frequency fpco 1 Basic Clock Module 4 9 Basic Clock Module Operation 4 2 6 Basic Clock Module Fail Safe Operation The basic
106. COFF CPUOFF and GIE are not affected R10 is decremented by 2 DECD R10 Decrement R10 by two Move a block of 255 words from memory location starting with EDE to memory location Starting with TONI Tables should not overlap start of destination address TONI must not be within the range EDE to EDE 0FEh 3 Example MOV EDE R6 MOV 510 R10 L 1 MOV R6 TONI EDE 2 R6 DECD R10 JNZ L 1 Memory at location LEO is decremented by two DECD B LEO Decrement MEM LEO Decrement status byte STATUS by two DECD B STATUS 3 38 RISC 16 Bit CPU DINT Syntax Operation Emulation Description Status Bits Mode Bits Example Instruction Set Disable general interrupts DINT 0 2 GIE or OFFF7h AND SR SR NOT src AND dst gt dst BIC 8 SR All interrupts are disabled The constant 08h is inverted and logically ANDed with the status register SR The result is placed into the SR Status bits are not affected GIE is reset OSCOFF and CPUOFF are not affected The general interrupt enable GIE bit in the status register is cleared to allow a nondisrupted move of a 32 bit counter This ensures that the counter is not modified during the move by any interrupt DINT All interrupt events using the GIE bit are disabled NOP MOV COUNTHIRS5 Copy counter MOV COUNTLO R6 EINT All interrupt events using the GIE bit are enabled q
107. CTL 5 Enable interrupts optional via the IEx SFRs URXIEx and or UTXIEx Failure to follow this process may result in unpredictable USART behavior MA USART Peripheral Interface SPI Mode USART Operation SPI Mode 14 2 2 Master Mode Figure 14 2 USART Master and External Slave MASTER Receive Buffer UXRXBUF Transmit Buffer UXTXBUF Receive Shift Register Data Shift Register DSR LSB MSB SCLK MSP430 USART COMMON SPI Figure 14 2 shows the USART as a master in both 3 pin and 4 pin configurations The USART initiates data transfer when data is moved to the transmit data buffer UXTXBUF The UxTXBUF data is moved to the TX shift register when the TX shift register is empty initiating data transfer on SIMO starting with the most significant bit Data on SOMI is shifted into the receive shift register on the opposite clock edge starting with the most significant bit When the character is received the receive data is moved from the RX shift register to the received data buffer UXRXBUF and the receive interrupt flag URXIFGx is set indicating the RX TX operation is complete A set transmit interrupt flag UTXIFGx indicates that data has moved from UxTXBUF to the TX shift register and UXTXBUF is ready for new data It does not indicate RX TX completion To receive data into the USART in master mode data must be written to UxTXBUF because receive and transmit operations operate concurrently Four
108. Conversion Timing An analog to digital conversion is initiated with a rising edge of sample input signal SHI The source for SHI is selected with the SHSx bits and includes the following The ADC10SC bit The Timer A Output Unit 1 The Timer A Output Unit 0 The Timer A Output Unit 2 The polarity of the SHI signal source can be inverted with the ISSH bit The SHTx bits select the sample period tsampje to be 4 8 16 or 64 ADC10CLK cycles The sampling timer sets SAMPCON high for the selected sample period after synchronization with ADC10CLK Total sampling time is tsample plus tgync The high to low SAMPCON transition starts the analog to digital conversion which requires 13 ADC10CLK cycles as shown in Figure 18 3 Figure 18 3 Sample Timing Start Stop Start Conversion Sampling Sampling Conversion Complete SHI SAMPCON a 13 x ADC10CLKs sample gt lt 4 tconvert j gt gt gt Isync ADC10 18 7 ADC10 Operation Sample Timing Considerations When SAMPCON 0 all Ax inputs are high impedance When SAMPCON 1 the selected Ax input can be modeled as an RC low pass filter during the sampling time tsample as shown below in Figure 18 4 An internal MUX on input resistance Rj max 2 KQ in series with capacitor C max 20 pF is seen by the source The capacitor C voltage Vc must be charged to within 1 2 LSB of the source voltage Vg for an accurate 10 bit conversion Figure 18 4 A
109. DC12IV register see register description This number can be evaluated or added to the program counter to automatically enter the appropriate software routine Disabled ADC12 interrupts do not affect the ADC12IV value Any access read or write of the ADC12IV register automatically resets the ADC12OV condition or the ADC12TOV condition if either was the highest pending interrupt Neither interrupt condition has an accessible interrupt flag The ADC12IFGx flags are not reset by an ADC12IV access ADC12IFGx bits are reset automatically by accessing their associated ADC12MEMXx register or may be reset with software If another interrupt is pending after servicing of an interrupt another interrupt is generated For example if the ADC12OV and ADC12IFG3 interrupts are pending when the interrupt service routine accesses the ADC12IV register the ADC120v interrupt condition is reset automatically After the RETI instruction of the interrupt service routine is executed the ADC12IFG3 generates another interrupt ADC 12 Operation ADC12 Interrupt Handling Software Example The following software example shows the recommended use of ADC12IV and the handling overhead The ADC12IV value is added to the PC to automatically jump to the appropriate routine The numbers at the right margin show the necessary CPU cycles for each instruction The software overhead for different interrupt sources includes interrupt latency and return from interrupt cycles bu
110. DMACTL1 Read write 0124h Reset with POR DMA channel 0 control DMAOCTL Read write 01E0h Reset with POR DMA channel 0 source address DMAOSA Read write 01E2h Unchanged DMA channel 0 destination address DMAODA Read write 01E4h Unchanged DMA channel 0 transfer size DMAOSZ Read write 01E6h Unchanged DMA channel 1 control DMA1CTL Read write 01E8h Reset with POR DMA channel 1 source address DMA1SA Read write 01EAh Unchanged DMA channel 1 destination address DMA1DA Read write 01ECh Unchanged DMA channel 1 transfer size DMA1SZ Read write 01EEh Unchanged DMA channel 2 control DMA2CTL Read write 01FOh Reset with POR DMA channel 2 source address DMA2SA Read write 01F2h Unchanged DMA channel 2 destination address DMA2DA Read write 01F4h Unchanged DMA channel 2 transfer size DMA2SZ Read write 01F6h Unchanged 8 18 DMA Controller DMA Registers DMACTLO DMA Control Register 0 15 14 13 12 1 10 9 8 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Reserved Bits Reserved 15 12 DMA2 Bits DMA trigger select These bits select the DMA transfer trigger TSELx 11 8 0000 DMAREQ bit software trigger 0001 TACCR2 CCIFG bit 0010 TBCCR2 CCIFG bit 0011 URXIFGO UART SPI mode USARTO data received I2C mode 0100 UTXIFGO UART SPI mode USARTO transmit ready 12C mode 0101 DAC12 OCTL DAC12IFG bit 0110 ADC12 ADC12IFGx bit 0111 TACCRO CCIFG bit 1000 TBCCRO CCIFG bit 1001 URXIFG1 bit 1010
111. DMAxSA DMAxDA and DMAxSZ registers are copied into temporary registers The temporary values of DMAxSA and DMAxDA are incremented or decremented after each transfer in the block The DMAxSZ register is decremented after each transfer of the block and shows the number of transfers remaining in the block When the DMAxSZ register decrements to zero it is reloaded from its temporary register and the corresponding DMAIFG flag is set In repeated burst block mode the DMAEN bit remains set after completion of the burst block transfer and no further trigger signals are required to initiate another burst block transfer Another burst block transfer begins immediately after completion of a burst block transfer In this case the transfers must be stopped by clearing the DMAEN bit or by an NMI interrupt when ENNMI is set In repeated burst block mode the CPU executes at 2096 capacity continuously until the repeated burst block transfer is stopped 8 10 DMA Controller DMA Operation Figure 8 5 DMA Burst Block Transfer State Diagram DMAEN 0 DMAREQ 0 T Size DMAxSZ OR DMAEN 0 DMADTx 2 3 AND DMAxSZ 0 DMAEN 0 DMAEN 1 DMAxSZ T Size DMAxSA T SourceAdd DMAxDA T DestAdd DMAABORT 1 DMAABORT 0 Wait for Trigger Trigger AND DMALEVEL 0 OR i 1 AND DMALEVEL 1 2x MCLK Trigger 1 Hold CPU Transfer one word byte y ENNMI
112. Ds with no carry in ADDC R13 20 R13 ADD MSDs with carry resulting from the LSDs The 24 bit counter pointed to by R13 is added to a 24 bit counter eleven words above the pointer in R13 ADD B R13 10 R13 ADD LSDs with no carry in ADDC B R13 10 R13 ADD medium Bits with carry ADDC B R13 10 R13 ADD MSDs with carry resulting from the LSDs RISC 16 Bit CPU 3 23 Instruction Set AND W AND B Syntax Operation Description Status Bits Mode Bits Example Example Source AND destination Source AND destination AND src dst or AND W src dst AND B src dst src AND dst dst The source operand and the destination operand are logically ANDed The result is placed into the destination N Setif result MSB is set reset if not set Z Setif result is zero reset otherwise C Set if result is not zero reset otherwise NOT Zero V Reset OSCOFF CPUOFF and GIE are not affected The bits set in R5 are used as a mask 0AA55h for the word addressed by TOM If the result is zero a branch is taken to label TONI MOV 0AA55h R5 Load mask into register R5 AND R5 TOM mask word addressed by TOM with R5 JZ TONI m Result is not zero or AND 0AA55h TOM JZ TONI The bits of mask 0A5h are logically ANDed with the low byte TOM If the result is zero a branch is taken to label TONI AND B 0A5h TOM mask Lowbyte TOM with 0A5h JZ TONI sites Result is not zero 3 24
113. E bit is set all non address characters are assembled but not transferred into the UxRXBUF and interrupts are not generated When an address character is received the receiver is temporarily activated to transfer the character to UXRXBUF and sets the URXIFGx interrupt flag Any applicable error flag is also set The user can then validate the received address If an address is received user software can validate the address and must reset URXWIE to continue receiving data If URXWIE remains set only address characters will be received The URXWIE bit is not modified by the USART hardware automatically For address transmission in idle line multiprocessor format a precise idle period can be generated by the USART to generate address character identifiers on UTXDx The wake up temporary WUT flag is an internal flag double buffered with the user accessible TXWAKE bit When the transmitter is loaded from UxTXBUF WUT is also loaded from TXWAKE resetting the TXWAKE bit The following procedure sends out an idle frame to indicate an address character will follow 1 Set TXWAKE then write any character to UXTXBUF UxTXBUF must be ready for new data UTXIFGx 1 The TXWAKE value is shifted to WUT and the contents of UxTXBUF are shifted to the transmit shift register when the shift register is ready for new data This sets WUT which suppresses the start data and parity bits of a normal transmission then transmits an idle period of exactl
114. ENC is ignored 01 DAC12 latch loads when DAC12 xDAT written or when grouped when all DAC12 xDAT registers in the group have been written 10 Rising edge of Timer A OUT1 TA1 11 Rising edge of Timer B OUT2 TB2 DAC12 calibration on This bit initiates the DAC12 offset calibration sequence and is automatically reset when the calibration completes 0 Calibration is not active 1 Initiate calibration calibration in progress DAC12 input range This bit sets the reference input and voltage output range 0 DAC12 full scale output 3x reference voltage 1 DAC12 full scale output 1x reference voltage DAC12 19 11 DAC 12 Registers DAC12 AMPx DAC12DF DAC12IE DAC12IFG DAC12 ENC DAC12 GRP 19 12 Bits 7 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DAC12 DAC12 amplifier setting These bits select settling time vs current consumption for the DAC12 input and output amplifiers DAC12AMPx Input Buffer 000 Off 001 Off 010 Low speed current 011 Low speed current 100 Low speed current 101 Medium speed current 110 Medium speed current 111 High speed current DAC 12 data format 0 Straight binary 1 2 s compliment DAC12 interrupt enable 0 Disabled 1 Enabled DAC12 Interrupt flag 0 No interrupt pending 1 Interrupt pending Output Buffer DAC12 off output high Z DAC12 off output 0 V Low speed current Medium speed current High speed current Medium speed current High speed current High speed current
115. ETC Prepare carry 1 DADD R5 R6 Emulate subtraction by addition of 010000h R5 1 Rez R6 R5 1 R62 0150h RISC 16 Bit CPU 3 63 Instruction Set SETN Syntax Operation Emulation Description Status Bits Mode Bits Set negative bit SETN 1 gt N BIS 4 SR The negative bit N is set N Set Z Not affected C Not affected V Not affected OSCOFF CPUOFF and GIE are not affected 3 64 RISC 16 Bit CPU Instruction Set SETZ Set zero bit Syntax SETZ Operation 1 gt Z Emulation BIS 2 SR Description The zero bit Z is set Status Bits N Not affected Z Set C Not affected V Not affected Mode Bits OSCOFF CPUOFF and GIE are not affected RISC 16 Bit CPU 3 65 Instruction Set SUBLW SUB B Syntax Operation Description Status Bits Mode Bits Example Example Subtract source from destination Subtract source from destination SUB src dst or SUB W src dst SUB B src dst dst NOT src 1 dst or dst src dst The source operand is subtracted from the destination operand by adding the source operand s 1s complement and the constant 1 The source operand is not affected The previous contents of the destination are lost N Setif result is negative reset if positive Z Setif result is zero reset otherwise C Set if there is a carry from the MSB of the result reset otherwise Set to 1 if no borrow reset if borrow V Setif an arithmetic
116. Flash memory control register 3 FCTL3 Read write 012Ch 09618h with PUC Interrupt Enable 1 IE1 Read write 000h Reset with PUC Flash Memory Controller 5 17 Flash Memory Registers FCTL1 Flash Memory Control Register 15 14 13 12 1d 10 9 8 FRKEY Read as 096h FWKEY Must be written as 0A5h 7 6 5 4 3 2 1 0 rw 0 rw 0 ro ro ro rw 0 rw 0 ro FRKEY FWKEY BLKWRT Reserved MERAS ERASE Reserved 5 18 Bits 15 8 Bit 7 Bit 6 Bits 5 3 Bit 2 Bit 1 Bit 0 FCTLx password Always read as 096h Must be written as 0A5h or a PUC will be generated Block write mode WRT must also be set for block write mode BLKWRT is automatically reset when EMEX is set 0 Block write mode is off 1 Block write mode is on Write This bit is used to select any write mode WRT is automatically reset when EMEX is set 0 Write mode is off 1 Write mode is on Reserved Always read as 0 Mass erase and erase These bits are used together to select the erase mode MERAS and ERASE are automatically reset when EMEX is set MERAS ERASE Erase Cycle 0 0 No erase 0 1 Erase individual segment only 1 0 Erase all main memory segments 1 1 Erase all main and information memory segments Reserved Always read as 0 Flash Memory Controller Flash Memory Registers FCTL2 Flash Memory Control Register 15 14 13 12 11 10 9 8 FWKEYx Read as 096h Must be written as 0A5h FWKEYx FSSELx Bits 15 8 Bits 7 6 Bit
117. Gx All applicable error status flags are also set If an address is received user software must reset URXWIE to continue receiving data If URXWIE remains set only address characters address bit 1 will be received The URXWIE bit is not modified by the USART hardware automatically Figure 13 4 Address Bit Multiprocessor Format Blocks of edem o Characters Dee Ed Idle Periods of No Significance UTXDx URXDx Expanded UTXDx URXDx First Character Within Block AD Bit Is 0 for Is an Address AD Bit Is 1 Data Within Block Idle Time Is of No Significance For address transmission in address bit multiprocessor mode the address bit of acharacter can be controlled by writing to the TXWAKE bit The value of the TXWAKE bit is loaded into the address bit of the character transferred from UxTXBUF to the transmit shift register automatically clearing the TXWAKE bit TXWAKE must not be cleared by software It is cleared by USART hardware after it is transferred to WUT or by setting SWRST USART Peripheral Interface UART Mode 13 7 USART Operation UART Mode Automatic Error Detection Glitch suppression prevents the USART from being accidentally started Any low level on URXDx shorter than the deglitch time t approximately 300 ns will be ignored See the device specific datasheet for parameters When a low period on URXDx exceeds t a majority vote is taken for the start bit If the majority vote fails to detect a va
118. H PCi n 4 PCi n 2 PCi n RETI RISC 16 Bit CPU 3 57 Instruction Set RLAL W RLA B Syntax Operation Emulation Description Rotate left arithmetically Rotate left arithmetically RLA dst Of RLA W dst RLA B dst C lt MSB lt MSB 1 LSB 1 lt LSB lt 0 ADD dst dst ADD B dst dst The destination operand is shifted left one position as shown in Figure 3 14 The MSB is shifted into the carry bit C and the LSB is filled with 0 The RLA instruction acts as a signed multiplication by 2 An overflow occurs if dst gt 04000h and dst lt 0C000h before operation is performed the result has changed sign Figure 3 14 Destination Operand Arithmetic Shift Left Status Bits Mode Bits Example Example Word 15 0 pesos es Byte 7 0 An overflow occurs if dst gt 040h and dst lt OCOh before the operation is performed the result has changed sign N Setif result is negative reset if positive Z Setif result is zero reset otherwise C Loaded from the MSB V Setif an arithmetic overflow occurs the initial value is 04000h lt dst lt 0C000h reset otherwise Set if an arithmetic overflow occurs the initial value is 040h lt dst lt OCOh reset otherwise OSCOFF CPUOFF and GIE are not affected R7 is multiplied by 2 RLA R7 Shift left R7 x 2 The low byte of R7 is multiplied by 4 RLA B R7 Shift left low byte of R7 x2 RLA B R7 Shift left low byte of R7 x 4
119. IEh FWKEY amp FCTL1 FWKEY LOCK amp FCTL3 Flash Memory Controller 514 kHz lt SMCLK lt 952 kHz Disable interrupts SMCLK 2 Clear LOCK Enable write 0123h gt OFF1Eh Done Clear WRT Set LOCK Re enable WDT Enable interrupts 5 9 Flash Memory Operation Initiating a Byte Word Write from RAM The flow to initiate a byte word write from RAM is shown in Figure 5 9 Figure 5 9 Initiating a Byte Word Write from RAM Disable all interrupts and watchdog Set WRT 0 LOCK 1 re enable interrupts and watchdog Byte word write from RAM 514 kHz lt SMCLK lt 952 kHz Assumes OFF1Eh is already erased Assumes ACCVIE NMIIE OFIE O MOV WDTPW WDTHOLD amp WDTCTL Disable WDT DINT Disable interrupts L1 BIT BUSY amp FCTL3 Test BUSY JNZ L1 Loop while busy MOV FWKEY FSSEL1 FNO amp FCTL2 SMCLK 2 MOV FWKEY amp FCTL3 Clear LOCK MOV FWKEY WRT amp FCTL1 Enable write MOV 0123h amp OFF1Eh 0123h gt OFFIEh L2 BIT BUSY amp FCTL3 Test BUSY JNZ L2 Loop while busy MOV HFWKEY amp FCTL1 Clear WRT MOV FWKEY LOCK amp FCTL3 Set LOCK i34 Re enable WDT EINT Enable interrupts 5 10 Flash Memory Controller Block Write Flash Memory Operation The block write can be used to accelerate the flash write process when many sequential bytes or words need to be programmed The flash programming voltage remains on for the duration of writing the 64 byte bl
120. IEx 0 And Last Buffer Entry Is Transmitted Figure 14 5 Slave Transmit Enable State Diagram USPIEx 0 No Clock at UCLK Not Completed USPIEx 1 Idle State Transmitter Enabled Transmit USPIEX Disable Transmission Active Handle Interrupt Conditions External Clock USPIEx 0 Present Character USPIEx 1 Transmitted PUC USPIEx 0 USART Peripheral Interface SPI Mode 14 7 USART Operation SPI Mode Receive Enable The SPI receive enable state diagrams are shown in Figure 14 6 and Figure 14 7 When USPIEx 0 UCLK is disabled from shifting data into the RX shift register Figure 14 6 SPI Master Receive Enable State Diagram USPIEx 0 No Data Written to UxTXBUF Not Completed USPIEx 1 Idle State Receiver Enabled Receive Disable Receiver Collects Character USPIEx 1 Handle Interrupt Conditions Data Written USPIEx 0 to UxTXBUF Character Received PUC USPIEx 1 USPIEx 0 Figure 14 7 SPI Slave Receive Enable State Diagram No Clock LK USPIEx 0 0 Clockat UG Not Completed USPIEx 1 Receive Idle State USPIEx 1 PECEIVET Handle Interrupt Receive Collects Conditions Disable Enabled External Clock Character USPIEx 0 Present Character USPIEx 1 Received
121. IFG flag providing a way to generate a software initiated interrupt Bit 0 No interrupt is pending Bit 1 An interrupt is pending Only transitions not static levels cause interrupts If any PxIFGx flag becomes set during a Px interrupt service routine or is set after the RETI instruction of a Px interrupt service routine is executed the set PxIFGx flag generates another interrupt This ensures that each transition is acknowledged f a V5 SS OSSSSSNGsese lt 7 Note PxIFG Flags When Changing PxOUT or PxDIR Writing to P1OUT P1DIR P2OUT or P2DIR can result in setting the corresponding P1IFG or P2IFG flags ee E a a Note Length of I O Pin Interrupt Event Any external interrupt event should be at least 1 5 times MCLK or longer to ensure that it is accepted and the corresponding interrupt flag is set es Digital I O 9 5 Digital I O Operation Interrupt Edge Select Registers P1IES P2IES Each PxIES bit selects the interrupt edge for the corresponding I O pin Bit 0 The PxIFGx flag is set with a low to high transition Bit 1 The PxIFGx flag is set with a high to low transition _ uaerwneerrererreeweewrxsrreeerweeeerreeervrennnnwwrwrwrnnnwwwmw wvwemwjr vivnnaa nnewennnnnwnnwnanaaannnanaannnjl llrwws Note Writing to PxIESx Writing to P1IES or P2IES can result in setting the corresponding interrupt flags PxIESx PxINx PxIFGx 0 1 0 May be
122. IR P4SEL P5IN P5OUT P5DIR P5SEL P6IN P6OUT P6DIR P6SEL Address 020h 021h 022h 023h 024h 025h 026h 028h 029h 02Ah 02Bh 02Ch 02Dh 02Eh 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh 030h 031h 032h 033h 034h 035h 036h 037h Register Type Read only Read write Read write Read write Read write Read write Read write Read only Read write Read write Read write Read write Read write Read write Read only Read write Read write Read write Read only Read write Read write Read write Read only Read write Read write Read write Read only Read write Read write Read write Initial State Unchanged Reset with PUC Reset with PUC Unchanged Reset with PUC Reset with PUC Unchanged Reset with PUC Reset with PUC Unchanged Reset with PUC Reset with PUC Unchanged Reset with PUC Reset with PUC Unchanged Reset with PUC Reset with PUC Unchanged Reset with PUC Reset with PUC Unchanged Reset with PUC Reset with PUC Digital I O 9 7 Watchdog Timer The watchdog timer is a 16 bit timer that can be used as a watchdog or as an interval timer This chapter describes the watchdog timer The watchdog timer is implemented in all MSP430x1xx devices Topic Page 10 1 Watchdog Timer Introduction eueeee 10 2 Watchdog Timer Operation sssssseseeee eene 10 4 10 2 Watchdog Timer Registers sssseeseeseeeeeeee 10 1 Watchdog Timer Int
123. Interrupt pending TBR Timer_B Register 15 14 13 12 11 10 9 8 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 TBRx Bits Timer B register The TBR register is the count of Timer B 15 0 12 22 Timer B Timer_B Registers TBCCTLx Capture Compare Control Register 15 rw 0 CMx CCISx scs CLLDx OUTMODx 14 Bit 15 14 Bit 13 12 Bit 11 Bit 10 9 Bit 8 Bits 13 12 11 10 9 8 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 5 4 3 2 1 0 rw 0 r rw 0 rw 0 rw 0 rw 0 rw 0 Capture mode 00 Nocapture 01 Capture on rising edge 10 Capture on falling edge 11 Capture on both rising and falling edges Capture compare input select These bits select the TBCCRx input signal See the device specific datasheet for specific signal connections 00 CCIxA 01 CCIxB 10 GND 11 Vcc Synchronize capture source This bit is used to synchronize the capture input signal with the timer clock 0 Asynchronous capture 1 Synchronous capture Compare latch load These bits select the compare latch load event 00 TBCLx loads on write to TBCCRx 01 TBCLx loads when TBR counts to 0 10 TBOLx loads when TBR counts to 0 up or continuous mode TBCLx loads when TBR counts to TBCLO or to 0 up down mode 11 TBCLx loads when TBR counts to TBCLx Capture mode 0 Compare mode 1 Capture mode Output mode Modes 2 3 6 and 7 ar
124. Jump if negative JN label if N 1 PC 2x offset gt PC if N 0 execute following instruction The negative bit N of the status register is tested If it is set the 10 bit signed offset contained in the instruction LSBs is added to the program counter If N is reset the next instruction following the jump is executed Status bits are not affected The result of a computation in R5 is to be subtracted from COUNT If the result is negative COUNT is to be cleared and the program continues execution in another path SUB R5 COUNT COUNT R5 gt COUNT JN L 1 If negative continue with COUNT 0 at PC L 1 m Continue with COUNT20 RISC 16 Bit CPU 3 49 Instruction Set JNC JLO Syntax Operation Description Status Bits Example ERROR CONT Example Jump if carry not set Jump if lower JNC label JLO label if C 0 PC 2 x offset gt PC if C 1 execute following instruction The status register carry bit C is tested If it is reset the 10 bit signed offset contained in the instruction LSBs is added to the program counter If C is set the next instruction following the jump is executed JNC jump if no carry lower is used for the comparison of unsigned numbers 0 to 65536 Status bits are not affected The result in R6 is added in BUFFER If an overflow occurs an error handling routine at address ERROR is used ADD R6 BUFFER BUFFER R6 gt BUFFER JNC CONT No carry jump to CONT
125. KPL 0 0 UCLK Cyle 1 2 8 4 5 6 7 8 0 1 UCLK 1 0 UCLK 1 1 UCLK 1 X Move to UxTXBUF TX Data Shifted Out RX Sample Points 14 10 USART Peripheral Interface SPI Mode USART Operation SPI Mode 14 2 6 SPI Interrupts The USART has one interrupt vector for transmission and one interrupt vector for reception SPI Transmit Interrupt Operation The UTXIFGx interrupt flag is set by the transmitter to indicate that UXTXBUF is ready to accept another character An interrupt request is generated if UTXIEx and GIE are also set UTXIFGx is automatically reset if the interrupt request is serviced or if a character is written to UXTXBUF UTXIFGx is set after a PUC or when SWRST 1 UTXIEx is reset after a PUC or when SWRST 1 The operation is shown is Figure 14 10 Figure 14 10 Transmit Interrupt Operation UTXIEx r a SYNC 1 L 4 PUC or SWRST Voc UTXIFGX ze ea Service Requested Character Moved From SWRST Buffer to Shift Register Data moved to UxTXBUF IRQA Note Writing to UxTXBUF in SPI Mode Data written to UXTXBUF when UTXIFGx 0 and USPIEx 1 may result in erroneous data transmission es USART Peripheral Interface SPI Mode 14 11 USART Operation SPI Mode SPI Receive Interrupt Operation The URXIFGx interrupt flag is set each time a character is received and loaded into UXRXBUF as shown in Figure 14 11 and Figure 14 12 An int
126. LRN Syntax Operation Emulation Description Status Bits Mode Bits Example SUBR SUBRET Clear negative bit CLRN 0 N or NOT src AND dst dst BIC 4 SR The constant 04h is inverted OFFFBh and is logically ANDed with the destination operand The result is placed into the destination The clear negative bit instruction is a word instruction N Reset to 0 Z Not affected C Not affected V Not affected OSCOFF CPUOFF and GIE are not affected The Negative bit in the status register is cleared This avoids special treatment with negative numbers of the subroutine called CLRN CALL SUBR JN SUBRET If input is negative do nothing and return RET 3 32 RISC 16 Bit CPU CLRZ Syntax Operation Emulation Description Status Bits Mode Bits Example Instruction Set Clear zero bit CLRZ 02Z or NOT src AND dst dst BIC 2 SR The constant 02h is inverted OFFFDh and logically ANDed with the destination operand The result is placed into the destination The clear zero bit instruction is a word instruction N Not affected Z Reset to 0 C Not affected V Not affected OSCOFF CPUOFF and GIE are not affected The zero bit in the status register is cleared CLRZ RISC 16 Bit CPU 3 33 Instruction Set CMP W CMP B Syntax Operation Description Status Bits Mode Bits Example Example Example Compare source and destination Compa
127. LSELx gt 0 DAC12 19 5 DAC 12 Operation 19 2 4 DAC12_xDAT Data Format The DAC12 supports both straight binary and 2 s compliment data formats When using straight binary data format the full scale output value is OFFFh in 12 bit mode OFFh in 8 bit mode as shown in Figure 19 2 Figure 19 2 Output Voltage vs DAC 12 Data 12 Bit Straight Binary Mode Output Voltage Full Scale Output DAC Data OFFFh When using 2 s compliment data format the range is shifted such that a DAC12_xDAT value of 0800h 0080h in 8 bit mode results in a zero output voltage 0000h is the mid scale output voltage and 07FFh 007Fh for 8 bit mode is the full scale voltage output as shown in Figure 19 3 Figure 19 3 Output Voltage vs DAC 12 Data 12 Bit 2s Compliment Mode Output Voltage Full Scale Output Mid Scale Output 0 DAC Data 0800h 2048 0 07FFh 2047 19 6 DAC12 DAC 12 Operation 19 2 5 DAC12 Output Amplifier Offset Calibration The offset voltage of the DAC12 output amplifier can be positive or negative When the offset is negative the output amplifier attempts to drive the voltage negative but cannot do so The output voltage remains at zero until the DAC12 digital input produces a sufficient positive output voltage to overcome the negative offset voltage resulting in the transfer function shown in Figure 19 4 Figure 19 4 Negative Offset Output Voltage 0 Negative Offset a DAC Data
128. MCLK LFXT1CLK 4 MCLK cycles Low power mode LPM3 MCLK LFXT1CLK 4 MCLK cycles Low power mode LPM4 MCLK LFXT1CLK 4 MCLK cycles 6 ust t The additional 6 us are needed to start the DCOCLK It is the t L PMx Parameter in the datasheet ADC10 Operation 18 2 8 Using the Integrated Temperature Sensor To use the on chip temperature sensor the user selects the analog input channel INCHx 1010 Any other configuration is done as if an external channel was selected including reference selection conversion memory selection etc The typical temperature sensor transfer function is shown in Figure 18 13 When using the temperature sensor the sample period must be greater than 30 us The temperature sensor offset error can be large and may need to be calibrated for most applications See the device specific datasheet for the parameters Selecting the temperature sensor automatically turns on the on chip reference generator as a voltage source for the temperature sensor However it does not enable the Vpgr output or affect the reference selections for the conversion The reference choices for converting the temperature sensor are the same as with any other channel Figure 18 14 Typical Temperature Sensor Transfer Function Volts 1 300 1 200 1 100 1 000 0 900 0 800 0 700 VTEMp 0 00355 TEMPc 0 986 Celsius ADC10 18 21 ADC10 Operation 18 2 9 ADC10 Grounding and Noise Considerations As with any high resolu
129. MSP430 devices have up to 6 digital I O ports implemented P1 P6 Each port has eight I O pins Every I O pin is individually configurable for input or output direction and each I O line can be individually read or written to Ports P1 and P2 have interrupt capability Each interrupt for the P1 and P2 I O lines can be individually enabled and configured to provide an interrupt on a rising edge or falling edge of an input signal All P1 I O lines source a single interrupt vector and all P2 I O lines source a different single interrupt vector The digital I O features include Independently programmable individual I Os Any combination of input or output E Individually configurable P1 and P2 interrupts n Independent input and output data registers Digital I O Operation 9 2 Digital l O Operation The digital I O is configured with user software The setup and operation of the digital I O is discussed in the following sections 9 2 1 Input Register PxIN Each bit in each PxIN register reflects the value of the input signal at the corresponding I O pin when the pin is configured as I O function Bit 2 0 The input is low Bit 1 The input is high p 1 Note Writing to Read Only Registers PxIN Writing to these read only registers results in increased current consumption while the write attempt is active ELLIIL I ILlL 9 2 2 Output Registers PxOUT Each bit in e
130. Modes Instr uction Get ree anean a E E EE elei els 3 1 CPU Introduction 3 1 CPU Introduction 3 2 The CPU incorporates features specifically designed for modern programming techniques such as calculated branching table processing and the use of high level languages such as C The CPU can address the complete address range without paging The CPU features include m E m E RISC architecture with 27 instructions and 7 addressing modes Orthogonal architecture with every instruction usable with every addressing mode Full register access including program counter status registers and stack pointer Single cycle register operations Large 16 bit register file reduces fetches to memory 16 bit address bus allows direct access and branching throughout entire memory range 16 bit data bus allows direct manipulation of word wide arguments Constant generator provides six most used immediate values and reduces code size Direct memory to memory transfers without intermediate register holding Word and byte addressing and instruction formats The block diagram of the CPU is shown in Figure 3 1 RISC 16 Bit CPU CPU Introduction Figure 3 1 CPU Block Diagram MDB Memory Data Bus Memory Address Bus MAB 15 0 RO PC Program Counter oL 16 Zero Z Carry C Overflow V Negative N RISC 16 Bit CPU 3 3 CPU Registers 3 2 CPU Registers The CPU incorporates sixteen 16 bit r
131. Mx ADC12 Conversion Memory Registers i s 13 12 11 10 9 8 eleje e omemm ro ro ro ro m 7 6 5 4 3 2 i rw rw rw rw m en i Conversion Bits The 12 bit conversion results are right justified Bit 11 is the MSB Bits 15 12 Results 15 0 are always 0 Writing to the conversion memory registers will corrupt the results 17 24 ADC12 ADC 12 Registers ADC12MCTLx ADC12 Conversion Memory Control Registers az Modifiable only when ENC 0 EOS Bit 7 End of sequence Indicates the last conversion in a sequence 0 1 Not end of sequence End of sequence SREFx Bits Select reference 6 4 000 001 010 011 100 101 110 111 INCHx Bits Input 3 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Vn AVcc and Vp AVss VR VREF and Vg AVss VR Vener and Vp AVss VR Vener and Vp AVss VR AVcc and Vp VREF Vener VR VREF and Vg VREF Vengr VR Vengr and Vp VREF Vengr VR Vengr and Vp VREF Vengr channel select VenEF VREF VeREF Temperature sensor AVcc AVss 2 AVcc AVss AVcc AVss a AVss 2 2 2 AVcc AVss 2 ADC12 17 25 ADC 12 Registers ADC12IE ADC12 Interrupt Enable Register 15 14 13 12 11 10 9 8 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 0 rw 0 rw 0 rw 0 rw 0 rw ADC12IEx Bits Interrupt ena
132. N INCHx 0AI VeREF VREF i oni 1 5 Vor 2 5 V AVCC VREF VeREF Reference gt AVCC SREF1 rnb lads SREFO ADC120SC AO SREF2 1 of ADC120N ADC12SSELx A1 AS ADC12DIVx P Sample 00 A5 and Divider 01 ACLK 12 bit SAR fe tioi 1 18 10 MCLK S H Convert ADCI2CLK 11 SMCLK BUSY SHSx Sup SHTOx ISSH A ENC SH 00 ADC12S Sample Timer 01 TAY 4 1024 T AVoc SAMPCON n I9 p T50 11 TB1 SHT1x MSC tf INCHx 0Bh Ref x ADC12MEMO ADC12MCTLO 2 CSTARTADDx _ 16x 12 16x8 i Memory Memory m iu Buffer Control Sr CONSEQx i n i Li WY Y ADC12MEM15 ADC12MCTL15 ADC12 17 3 ADC 12 Operation 17 2 ADC12 Operation The ADC12 module is configured with user software The setup and operation of the ADC12 is discussed in the following sections 17 2 1 12 Bit ADC Core The ADC core converts an analog input to its 12 bit digital representation and stores the result in conversion memory The core uses two programmable selectable voltage levels VR and Vp to define the upper and lower limits of the conversion The digital output NApc is full scale OFFFh when the input signal is equal to or higher than Vg and zero when the input signal is equal to or lower than Vp_ The input channel and the reference voltage levels VR and Vg are defined in the conversion control memory The conversion formula for the ADC result Napc is Vin V V R N R T VR ape 4095 x The ADC12 core is configured by two control r
133. OAIFG Set If Not RESTART Receive Slave Address Bits 9 8 with R W 1 2nd Start Detected STTIFG Is Set Data on SDA No OAIFG Set If Not RESTART 8x SCL Ack and I2ZCWORD 0 4 x l2CPSC USART Peripheral Interface IC Mode I2CDR Empty I2CDR Loaded Yes No Send Data Low Byte To Master No Ack Send Data High Byte To Master Ack No Ack STOP Detected RESTART Yes Detected IDLE Vos Enter Slave Receive mode at 1 15 13 12C Module Operation Figure 15 12 Slave Receiver START Detected Yes Yes 5 RESTART STTIFG Is Set I2CBUSY Is Set 4 x l2CPSC I2CBB Is Set XAs1 XA 0 8 x SCL 8 x SCL Receive Slave Address Bits 9 8 with R W 0 Receive Slave Address Bits 6 0 with R W 0 Matched I2COA Matched I2COA 1x SCL Send Acknowledge Send Acknowledge 8x SCL Receive Slave Address Bits 7 0 Matched I2COA LA Send Acknowledge OAIFG Set If Not RESTART 1x SCL 15 14 USART Peripheral Interface 12C Mode Detected From Slave Transmit Mode Receive Data Low Byte From Master Send Acknowledge Receive Data High Byte From Master I2CWORD 0 Byte Mode Send Acknowledge Stop State Yes 4 x l2CPSC I2CBB Is Cleared 1 x l2CPSC I2CBUSY Is C
134. OFFh Divide by 256 USART Peripheral Interface I C Mode 15 25 12C Module Registers I2CSCLH I2C Shift Clock High Register 7 6 5 4 3 2 1 0 I2CSCLHx rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Modifiable only when I2CEN 0 I2CSCLHx Bits I2C shift clock high These bits define the high period of SCL when the 12C 7 0 controller is in master mode The SCL high period is I2CSCLH 2 x IBCPSC 1 000h SCL high period 5 x I2CPSC 1 001h SCL high period 5 x IBCPSC 1 002h SCL high period 5 x IBCPSC 1 003h SCL high period 5 x IBCPSC 1 004h SCL high period 6 x IBCPSC 1 OFFh SCL high period 257 x IPCPSC 1 I2CSCLL I2C Shift Clock Low Register 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Modifiable only when I2CEN 0 I2CSCLLx Bits I2C shift clock low These bits define the low period of SCL when the 12C 7 0 controller is in master mode The SCL low period is I2CSCLL 2 x I2CPSC 1 000h SCL low period 5 x IBCPSC 1 001h SCL low period 5 x IBCPSC 1 002h SCL low period 5 x IBCPSC 1 003h SCL low period 5 x IBCPSC 1 004h SCL low period 6 x IBCPSC 1 OFFh SCL low period 257 x l2CPSC 1 15 26 USART Peripheral Interface 2C Mode 12C Module Registers I2COA I2C Own Address Register 7 Bit Addressing Mode 15 14 18 12 11 10 9 8 ro ro ro ro ro ro ro ro 74 6 5 4 3 2 1 0 I2COAx ro rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Modifiable only when I2CEN
135. ON 1 Sample Input Channel Defined in If EOS x 1 then x ADC12MCTLx CSTARTADDx T else if x lt 15 then x x 1 else SAMPCON Y x 0 If EOS x 1 then x 12 x ADC12CLK CSTARTADDx else if x lt 15 then x x 1 else MSC 0 xX 0 or SHP 0 i l and SHP 1 1 x ADC12CLK ENC 1 and Conversion of ENC 1 Completed EOS x 0 or Result Stored Into ADC12MEMx EOS x 0 ADC12IFG x is Set x pointer to ADC12MCTLx 17 14 ADC12 ADC 12 Operation Using the Multiple Sample and Convert MSC Bit To configure the converter to perform successive conversions automatically and as quickly as possible a multiple sample and convert function is available When MSC 1 CONSEQx gt 0 and the sample timer is used the first rising edge of the SHI signal triggers the first conversion Successive conversions are triggered automatically as soon as the prior conversion is completed Additional rising edges on SHI are ignored until the sequence is completed in the single sequence mode or until the ENC bit is toggled in repeat single channel or repeated sequence modes The function of the ENC bit is unchanged when using the MSC bit Stopping Conversions Stopping ADC12 activity depends on the mode of operation The recommended ways to stop an active conversion or conversion sequence are Resetting ENC in single channel single conversion mode stops a conve
136. ORD 0 No I2CP 1x SCL 8x leer se I2CBB Is Cleared USART Peripheral Interface I7C Mode 8 x l2CPSC I2CSTP I2CMST Are Cleared IDLE I2CBUSY Is Cleared Arbitration 12C Module Operation If two or more master transmitters simultaneously start a transmission on the bus an arbitration procedure is invoked Figure 15 10 illustrates the arbitration procedure between two devices The arbitration procedure uses the data presented on SDA by the competing transmitters The first master transmitter that generates a logic high is overruled by the opposing master generating a logic low The arbitration procedure gives priority to the device that transmits the serial data stream with the lowest binary value The master transmitter that lost arbitration switches to the slave receiver mode and sets the arbitration lost flag ALIFG If two or more devices send identical first bytes arbitration continues on the subsequent bytes Figure 15 10 Arbitration Procedure Between Two Master Transmitters Bus Line SCL Data From Device 1 Data From Device 2 Bus Line SDA cht a7 We ao LU Device 1 Lost Arbitration x and Switches Off n If the arbitration procedure is in progress when a repeated START condition or STOP condition is transmitted on SDA the master transmitters involved in arbitration must send the repeated START condition or STOP condition at the same position in the format frame Arbitration is not allowed b
137. PUC USPIEx 0 14 8 USART Peripheral Interface SP Mode USART Operation SPI Mode 14 2 5 Serial Clock Control UCLK is provided by the master on the SPI bus When MM 1 BITCLK is provided by the USART baud rate generator on the UCLK pin as shown in Figure 14 8 When MM 0 the USART clock is provided on the UCLK pin by the master and the baud rate generator is not used and the SSELx bits are don t care The SPI receiver and transmitter operate in parallel and use the same clock source for data transfer Figure 14 8 SPI Baud Rate Generator UCLKI ACLK SMCLK SMCLK Compare 0 or 1 hu h BITCLK gt R Modulation Data Shift Register R LSB first mX m7 8 m0 A UxMCTL Bit Start The 16 bit value of UxBRO UxBR 1 is the division factor of the USART clock source BRCLK The maximum baud rate that can be generated in master mode is BRCLK 2 The maximum baud rate that can be generated in slave mode is BRCLK The modulator in the USART baud rate generator is not used for SPI mode and is recommended to be set to 000h The UCLK frequency is given by _ BRCLK E Baud rate 4gp with UxBR UxBR1 UxBRO USART Peripheral Interface SPI Mode 14 9 USART Operation SPI Mode Serial Clock Polarity and Phase The polarity and phase of UCLK are independently configured via the CKPL and CKPH control bits of the USART Timing for each case is shown in Figure 14 9 Figure 14 9 USART SPI Timing CKPH C
138. Peripheral Interface SPI Mode USART Registers SP Mode UxBRO USART Baud Rate Control Register 0 7 6 5 4 3 2 1 0 Pee EP ESESEES rw rw rw rw rw rw rw rw UxBR1 USART Baud Rate Control Register 1 7 6 5 4 3 2 1 0 EAE SESE SEE ue rw rw rw rw rw rw rw rw UxBRx The baud rate generator uses the content of UxBR1 UxBR0 to set the baud rate Unpredictable SPI operation occurs if UxBR 2 UxMCTL USART Modulation Control Register 7 6 5 4 3 2 1 0 Pusop seg e de res pr ram oes rw rw rw rw rw rw rw rw UxMCTLx Bits The modulation control register is not used for SPI mode and should be set 7 0 to 000h USART Peripheral Interface SPI Mode 14 17 USART Registers SPI Mode UxRXBUF USART Receive Buffer Register 7 6 5 4 3 2 1 0 EA ESESESZESESERED r r r r r r r r UxRXBUFx Bits The receive data buffer is user accessible and contains the last received 7 0 character from the receive shift register Reading UXRXBUF resets the OE bit and URXIFGx flag In 7 bit data mode UxRXBUF is LSB justified and the MSB is always reset UxTXBUF USART Transmit Buffer Register 7 6 5 4 3 2 1 0 ERESESESERESERES rw rw rw rw rw rw rw rw UxTXBUFx Bits The transmit data buffer is user accessible and contains current data to be 7 0 transmitted When seven bit character length is used the data should be MSB justified before being moved into UxTXBUF Data is transmitted MSB first Writing to UXTXBUF clears UTXIFGx 14 18 USART Peripheral Interface SPI Mo
139. Pin SPI Master Mode In 4 pin master mode STE is used to prevent conflicts with another master The master operates normally when STE is high When STE is low SIMO and UCLK are set to inputs and no longer drive the bus The error bit FE is set indicating a communication integrity violation to be handled by the user A low STE signal does not reset the USART module The STE input signal is not used in 3 pin master mode USART Peripheral Interface SPI Mode 14 5 USART Operation SPI Mode 14 2 3 Slave Mode Figure 14 3 USART Slave and External Master MASTER MSB COMMON SPI SPI Receive Buffer Data Shift Register DSR LSB SCLK MSP430 USART Figure 14 3 shows the USART as a slave in both 3 pin and 4 pin configurations UCLK is used as the input for the SPI clock and must be supplied by the external master The data transfer rate is determined by this clock and not by the internal baud rate generator Data written to UXTXBUF and moved to the TX shift register before the start of UCLK is transmitted on SOMI Data on SIMO is shifted into the receive shift register on the opposite edge of UCLK and moved to UxRXBUF when the set number of bits are received When data is moved from the RX shift register to UXRXBUF the URXIFGx interrupt flag is set indicating that data has been received The overrun error bit OE is set when the previously received data is not read from UxRXBUF before new data is moved to
140. R Receive Shift Register I2CSTP I2CSTT I2CSTB Transmit Shift Register I2CTXUDF I2ZCWORD I2CSBD I2CSA USART Peripheral Interface IC Mode 15 3 12C Module Operation 15 2 12C Module Operation The I2C module supports any slave or master I2C compatible device Figure 15 2 shows an example of an 12C bus Each 12C device is recognized by a unique address and can operate as either a transmitter or a receiver A device connected to the 12C bus can be considered as the master or the slave when performing data transfers A master initiates a data transfer and gener ates the clock signal SCL Any device addressed by a master is considered a slave 12C data is communicated using the serial data pin SDA and the serial clock pin SCL Both SDA and SCL are bidirectional and must be connected to a positive supply voltage using a pull up resistor Figure 15 2 12C Bus Connection Diagram Vcc MSP430 Device A Serial Data SDA t i t Serial Clock SCL Note SDA and SCL Levels The MSP430 SDA and SCL pins must not be pulled up above the MSP430 Vcc level 15 4 USART Peripheral Interface 12C Mode 12C Module Operation 15 2 1 12C Module Initialization The 12C module is part of the USART peripheral Individual bit definitions when using USARTO in 12C mode are different from that in SPI or UART mode The default value for the UOCTL register is the UART mode To select 12C o
141. RT Module for UART or SPI Operation When re configuring the USART module for UART or SPI operation from 12C operation the required process is 1 Clear I2C SYNC and I2CEN CLR B amp UOCTL 2 Set SWRST MOV B SWRST amp UOCTL 3 Continue with UART or SPI initialization procedure Failure to follow this process may result in unpredictable USART behavior ee USART Peripheral Interface IC Mode 15 5 12C Module Operation 15 2 2 12C Serial Data One clock pulse is generated by the master device for each data bit transferred The I2C module operates with byte data Data is transferred most significant bit first as shown in Figure 15 3 The first byte after a START condition consists of a 7 bit slave address and the R W bit When R W 0 the master transmits data to a slave When R W 1 the master receives data from a slave The ACK bit is sent from the receiver after each byte on the 9th SCL clock Figure 15 3 12C Module Data Transfer rf i sb soa I ZX XX XN YS NOXOCGUXOCN MI v MSB Acknowledgement Acknowledgement Signal From Receiver Signal From Receiver s TADS DDN _PDDDPPDDS TT are 1 2 7 8 9 1 2 8 9 eem START ER STOP Condition S R W ACK ACK Condition P START and STOP conditions are generated by the master and are shown in Figure 15 3 A START condition is a high to low transition on the SDA line while SCL is high A STOP condition is a low to high transition on the SDA line while SCL is high The bus
142. Read write 073h Unchanged Baud rate control register 0 UOBRO Read write 074h Unchanged Baud rate control register 1 UOBR1 Read write 075h Unchanged Receive buffer register UORXBUF Read 076h Unchanged Transmit buffer register UOTXBUF Read write 077h Unchanged SFR module enable register 1t ME1 Read write 004h 000h with PUC SFR interrupt enable register 1t IE1 Read write 000h 000h with PUC SFR interrupt flag register 1t IFG1 Read write 002h 082h with PUC t Does not apply to MSP430x12xx devices Refer to the register definitions for registers and bit positions for these devices Table 14 2 USAHT1 Control and Status Registers Register Short Form Register Type Address Initial State USART control register U1CTL Read write 078h 001h with PUC Transmit control register U1TCTL Read write 079h 001h with PUC Receive control register U1RCTL Read write 07Ah 000h with PUC Modulation control register U1MCTL Read write 07Bh Unchanged Baud rate control register 0 U1BRO Read write 07Ch Unchanged Baud rate control register 1 U1BR1 Read write 07Dh Unchanged Receive buffer register U1RXBUF Read 07Eh Unchanged Transmit buffer register U1TXBUF Read write 07Fh Unchanged SFR module enable register 2 ME2 Read write 005h 000h with PUC SFR interrupt enable register 2 IE2 Read write 001h 000h with PUC SFR interrupt flag register 2 IFG2 Read write 003h 020h with PUC p T Note Modifying the SFR bits To avoid modifying control bits for other modules it is recommended to
143. Receive Not Started URXDx URXS LM o When a glitch is longer than t or a valid start bit occurs on URXDx the USART receive operation is started and a majority vote is taken as shown in Figure 13 13 If the majority vote fails to detect a start bit the USART halts character reception If character reception is halted an active BRCLK is not necessary A time out period longer than the character receive duration can be used by software to indicate that a character was not received in the expected time and the software can disable BRCLK Figure 13 13 Glitch Suppression USART Activated 13 20 Majority Vote Taken USART Peripheral Interface UART Mode USART Registers UART Mode 13 3 USART Registers UART Mode Table 13 3 lists the registers for all devices implementing a USART module Table 13 4 applies only to devices with a second USART module USART1 Table 13 3 USARTO Control and Status Registers Register Short Form Register Type Address Initial State USART control register UOCTL Read write 070h 001h with PUC Transmit control register UOTCTL Read write 071h 001h with PUC Receive control register UORCTL Read write 072h 000h with PUC Modulation control register UOMCTL Read write 073h Unchanged Baud rate control register 0 UOBRO Read write 074h Unchanged Baud rate control register 1 UOBR1 Read write 075h Unchanged Receive buffer register UORXBUF Read 076h Unchanged Transmit buffer register UOTXBUF Read write 077h
144. SCG0O SR Enter LPM3 mass Program stops here Exit LPM3 Interrupt Service Routine BIC CPUOFF SCG1 SCG0 0 SP Exit LPM3 on RETI RETI Extended Time in Low Power Modes The negative temperature coefficient of the DCO should be considered when the DCO is disabled for extended low power mode periods If the temperature changes significantly the DCO frequency at wake up may be significantly different from when the low power mode was entered and may be out of the specified operating range To avoid this the DCO can be set to it lowest value before entering the low power mode for extended periods of time where temperature can change Enter LPM4 Example with lowest DCO Setting BIC RSEL2 RSEL1 RSELO amp BCSCTL1 Lowest RSEL BIS GIE CPUOFF OSCOFF SCG1 SCG0O SR Enter LPM4 E Program stops Interrupt Service Routine BIC CPUOFF OSCOFF SCG1 SCG0 0 SR Exit LPM4 on RETI RETI 2 16 System Resets Interrupts and Operating Modes Principles for Low Power Applications 2 4 Principles for Low Power Applications Often the most important factor for reducing power consumption is using the MSP430 s clock system to maximize the time in LPM3 LPM3 power consumption is less than 2 uA typical with both a real time clock function and all interrupts active A 32 kHz watch crystal is used for the ACLK and the CPU is clocked from the DCO normally off which has a 6 us wake up _j Use interrupts to wake the processor and control prog
145. Syntax RET Operation SP PC SP 2 SP Emulation MOV SP PC Description The return address pushed onto the stack by a CALL instruction is moved to the program counter The program continues at the code address following the subroutine call Status Bits Status bits are not affected 3 56 RISC 16 Bit CPU RETI Syntax Operation Description Status Bits Mode Bits Example Instruction Set Return from interrupt RETI TOS SR SP 2 SP TOS PC SP 2 SP The status register is restored to the value at the beginning of the interrupt service routine by replacing the present SR contents with the TOS contents The stack pointer SP is incremented by two The program counter is restored to the value at the beginning of interrupt service This is the consecutive step after the interrupted program flow Restoration is performed by replacing the present PC contents with the TOS memory contents The stack pointer SP is incremented N restored from system stack Z restored from system stack C restored from system stack V restored from system stack OSCOFF CPUOFF and GIE are restored from system stack Figure 3 13 illustrates the main program interrupt Figure 3 13 Main Program Interrupt PC 6 eoo PC 4 Interrupt Request PC 2 d PC Interrupt Accepted Y PC 2 PC 2 is Stored PC PCi eco Onto Stack PC 4 PCi 2 PC 6 PCi 4 PC 8 e M
146. TINCRx control bits The DMASRCINCRx bits select if the source address is incremented decremented or unchanged after each transfer The DMADSTINCRx bits select if the destination address is incremented decremented or unchanged after each transfer Transfers may be byte to byte word to word byte to word or word to byte When transferring word to byte only the lower byte of the source word transfers When transferring byte to word the upper byte of the destination word is cleared when the transfer occurs Figure 8 2 DMA Addressing Modes 8 4 DMA Cont Fixed Address To Fixed Address D Cont Block Of Addresses To Fixed Address roller MA roller DMA Address Space Address Space Fixed Address To Block Of Addresses DMA Address Space Address Space Block Of Addresses To Block Of Addresses DMA Controller DMA Operation 8 2 2 DMA Transfer Modes The DMA controller has six transfer modes selected by the DMADTx bits as listed in Table 8 1 Each channel is individually configurable for its transfer mode For example channel 0 may be configured in single transfer mode while channel 1 is configured for burst block transfer mode and channel 2 operates in repeated block mode The transfer mode is configured independently from the addressing mode Any addressing mode can be used with any transfer mode Table 8 1 DMA Tr
147. Timer A interrupt priority and has a dedicated interrupt vector as shown in Figure 11 15 The TACCRO CCIFG flag is automatically reset when the TACCRO interrupt request is serviced Figure 11 15 Capture Compare TACCRO Interrupt Flag Capture IRQ Interrupt Service Requested IRACC Interrupt Request Accepted TAIV Interrupt Vector Generator The TACCR1 CCIFG TACCR2 CCIFG and TAIFG flags are prioritized and combined to source a single interrupt vector The interrupt vector register TAIV is used to determine which flag requested an interrupt The highest priority enabled interrupt generates a number in the TAIV register see register description This number can be evaluated or added to the program counter to automatically enter the appropriate software routine Disabled Timer A interrupts do not affect the TAIV value Any access read or write of the TAIV register automatically resets the highest pending interrupt flag If another interrupt flag is set another interrupt is immediately generated after servicing the initial interrupt For example if the TACCR 1 and TACCR2 CCIFG flags are set when the interrupt service routine accesses the TAIV register TACCR1 CCIFG is reset automatically After the RETI instruction of the interrupt service routine is executed the TACCR2 CCIFG flag will generate another interrupt Timer A 11 17 Timer_A Operation TAIV Software Example The following software example shows th
148. URXWIE Lal USART Peripheral Interface UART Mode 13 9 USART Operation UART Mode 13 2 5 USART Transmit Enable When UTXEx is set the UART transmitter is enabled Transmission is initiated by writing data to UxTXBUF The data is then moved to the transmit shift register on the next BITCLK after the TX shift register is empty and transmission begins This process is shown in Figure 13 6 When the UTXEx bit is reset the transmitter is stopped Any data moved to UxTXBUF and any active transmission of data currently in the transmit shift register prior to clearing UTXEx will continue until all data transmission is completed Figure 13 6 State Diagram of Transmitter Enable 13 10 UTXEx 0 No Data Written Transmit Disable to Transmit Buffer Not Completed UTXEx 1 Data Written to Idle State Transmit Buffer Transmission Handle Interrupt Transmitter Acti Conditions Enabled i UTXEx 0 Character Transmitted UTXEx 0 And Last Buffer Entry Is Transmitted When the transmitter is enabled UTXEx 1 data should not be written to UxTXBUF unless it is ready for new data indicated by UTXIFGx 1 Violation can result in an erroneous transmission if data in UXTXBUF is modified as it is being moved into the TX shift register It is recommended that the transmitter be disabled UTXEx 0 only after any active transmission is complete This is indicated by a set transmitter empty bit TXEPT 1 Any data writte
149. UxRXBUF Four Pin SPI Slave Mode In 4 pin slave mode STE is used by the slave to enable the transmit and receive operations and is provided by the SPI master When STE is low the slave operates normally When STE is high Lj Any receive operation in progress on SIMO is halted SOMI is set to the input direction A high STE signal does not reset the USART module The STE input signal is not used in 3 pin slave mode 14 6 USART Peripheral Interface SPI Mode USART Operation SPI Mode 14 2 4 SPI Enable The SPI transmit receive enable bit USPIEx enables or disables the USART in SPI mode When USPIEx 0 the USART stops operation after the current transfer completes or immediately if no operation is active A PUC or set SWRST bit disables the USART immediately and any active transfer is terminated Transmit Enable When USPIEx 0 any further write to UXTXBUF does not transmit Data written to UXTXBUF will begin to transmit when USPIEx 1 and the BRCLK source is active Figure 14 4 and Figure 14 5 show the transmit enable state diagrams Figure 14 4 Master Mode Transmit Enable USPIEx 0 No Data Written to Transfer Buffer Not Completed USPIEx 1 Data Written to USPIEx 1 Idle State i Transmit Transmitter Transmit Buiter Transmission sies Interrupt i i onditions Disable Enabled Active USPIEx 0 Character Transmitted PUC USP
150. ace conditions as shown in Figure 4 11 1 The current clock cycle continues until the next rising edge 2 The clock remains high until the next rising edge of the new clock 3 The new clock source is selected and continues with a full high period Figure 4 11 Switch MCLK from DCOCLK to LFXT1CLK Select LFXT1CLK v DCOCLK LFXTICLK MCLK pcocik p gt Walt for LFXT1CLK 9 LFXT1CLK Basic Clock Module 4 13 Basic Clock Module Registers 4 3 Basic Clock Module Registers The basic clock module registers are listed in Table 4 1 Table 4 1 Basic Clock Module Registers Register Short Form Register Type Address Initial State DCO control register DCOCTL Read write 056h 060h with PUC Basic clock system control 1 BCSCTL1 Read write 057h 084h with PUC Basic clock system control 2 BCSCTL2 Read write 058h Reset with POR SFR interrupt enable register 1 IE1 Read write 000h Reset with PUC SFR interrupt flag register 1 IFG1 Read write 002h Reset with PUC 4 14 Basic Clock Module Basic Clock Module Registers DCOCTL DCO Control Register DCOx MODx Bits 7 5 Bits 4 0 DCO frequency select These bits select which of the eight discrete DCO frequencies of the RSELx setting is selected Modulator selection These bits define how often the fpco 1 frequency is used within a period of 32 DCOCLK cycles During the remaining clock cycles 32
151. ach PXOUT register is the value to be output on the corresponding I O pin when the pin is configured as I O function and output direction Bit 0 The output is low Bit 1 The output is high 9 2 3 Direction Registers PxDIR Each bit in each PxDIR register selects the direction of the corresponding I O pin regardless of the selected function for the pin PxDIR bits for I O pins that are selected for other module functions must be set as required by the other function Bit 0 The port pin is switched to input direction Bit 1 The port pin is switched to output direction Digital I O 9 3 Digital I O Operation 9 2 4 Function Select Registers PxSEL 9 4 Digital I O Port pins are often multiplexed with other peripheral module functions See the device specific data sheet to determine pin functions Each PxSEL bit is used to select the pin function I O port or peripheral module function Bit 0 I O Function is selected for the pin Bit 1 Peripheral module function is selected for the pin Setting PxSELx 1 does not automatically set the pin direction Other peripheral module functions may require the PxDIRx bits to be configured according to the direction needed for the module function See the pin schematics in the device specific datasheet Output ACLK on P2 0 on MSP430F11x1 BIS B 01h amp P2SEL Select ACLK function for pin BIS B 01h amp P2DIR Set direction to output Required a a a a ae Note P1
152. acters when URXWIE 1 When URXEIE 1 a break condition will set the BRK bit and the URXIFGx flag USART Peripheral Interface UART Mode USART Operation UART Mode Receive Start Edge Detect Operation The URXSE bit enables the receive start edge detection feature The recommended usage of the receive start edge feature is when BRCLK is sourced by the DCO and when the DCO is off because of low power mode operation The ultra fast turn on of the DCO allows character reception after the start edge detection When URXSE URXIEx and GIE are set and a start edge occurs on URXDx the internal signal URXS will be set When URXS is set a receive interrupt request is generated but URXIFGx is not set User software in the receive interrupt service routine can test URXIFGx to determine the source of the interrupt When URXIFGx 0 a start edge was detected and when URXIFGx 1 a valid character or break was received When the ISR determines the interrupt request was from a start edge user software toggles URXSE and must enable the BRCLK source by returning from the ISR to active mode or to a low power mode where the source is active If the ISR returns to a low power mode where the BRCLK source is inactive the character will not be received Toggling URXSE clears the URXS signal and re enables the start edge detect feature for future characters See chapter System Resets Interrupts and Operating Modes for information on entering and exiting
153. als can be produced with other modes as well where TACCRO is used as the period register Their handling is more complex since the sum of the old TACCRx data and the new period can be higher than the TACCRO value When the previous TACCRx value plus t is greater than the TACCRO data the TACCRO value must be subtracted to obtain the correct time interval Timer_A Operation Up Down Mode The up down mode is used if the timer period must be different from OFFFFh counts and if symmetrical pulse generation is needed The timer repeatedly counts up to the value of compare register TACCRO and back down to zero as shown in Figure 11 7 The period is twice the value in TACCRO Figure 11 7 Up Down Mode OFFFFh TACCRO Oh The count direction is latched This allows the timer to be stopped and then restarted in the same direction it was counting before it was stopped If this is not desired the TACLR bit must be set to clear the direction The TACLR bit also clears the TAR value and the clock divider In up down mode the TACCRO CCIFG interrupt flag and the TAIFG interrupt flag are set only once during a period separated by 1 2 the timer period The TACCRO CCIFG interrupt flag is set when the timer counts from TACCRO 1 to TACCRO and TAIFG is set when the timer completes counting down from 0001h to 0000h Figure 11 8 shows the flag set cycle Figure 11 8 Up Down Mode Flag Setting Up Down Set TAIFG j j Set TACCRO CCIFG j
154. ample Example Instruction Set Jump if equal jump if zero JEQ label JZ label IfZ 1 PC 2x offset gt PC If Z 0 execute following instruction The status register zero bit Z is tested If it is set the 10 bit signed offset contained in the instruction LSBs is added to the program counter If Z is not set the instruction following the jump is executed Status bits are not affected Jump to address TONI if R7 contains zero TST R7 Test R7 JZ TONI if zero JUMP Jump to address LEO if R6 is equal to the table contents CMP R6 Table R5 Compare content of R6 with content of MEM table address content of R5 JEQ LEO Jump if both data are equal No data are not equal continue here Branch to LABEL if R5 is O TST R5 JZ LABEL RISC 16 Bit CPU 3 45 Instruction Set JGE Syntax Operation Description Status Bits Example Jump if greater or equal JGE label If N XOR V 0 then jump to label PC 2 x offset gt PC If N XOR V 1 then execute the following instruction The status register negative bit N and overflow bit V are tested If both N and V are set or reset the 10 bit signed offset contained in the instruction LSBs is added to the program counter If only one is set the instruction following the jump is executed This allows comparison of signed integers Status bits are not affected When the content of R6 is greater or equal to the memory pointed to by R7
155. and P2 Interrupts Are Disabled When PxSEL 1 When any P1SELx or P2SELx bit is set the corresponding pin s interrupt function is disabled Therefore signals on these pins will not generate P1 or P2 interrupts regardless of the state of the corresponding P1IE or P2IE bit LLLLLLL When a port pin is selected as an input to a peripheral the input signal to the peripheral is a latched representation of the signal at the device pin While PxSELx 1 the internal input signal follows the signal at the pin However if the PxSELx 0 the input to the peripheral maintains the value of the input signal at the device pin before the PxSELx bit was reset Digital I O Operation 9 2 5 P1 and P2 Interrupts Each pin in ports P1 and P2 have interrupt capability configured with the PxIFG PxIE and PxIES registers All P1 pins source a single interrupt vector and all P2 pins source a different single interrupt vector The PxIFG register can be tested to determine the source of a P1 or P2 interrupt Interrupt Flag Registers P1IFG P2IFG Each PxIFGx bit is the interrupt flag for its corresponding I O pin and is set when the selected input signal edge occurs at the pin All PxIFGx interrupt flags request an interrupt when their corresponding PxIE bit and the GIE bit are set Each PxIFG flag must be reset with software Software can also set each Px
156. and TACLR to avoid errant operating conditions When the timer clock is asynchronous to the CPU clock any read from TAR should occur while the timer is not operating or the results may be unpredictable Alternatively the timer may be read multiple times while operating and a majority vote taken in software to determine the correct reading Any write to TAR will take effect immediately LLLLLLLL A M AU Clock Source Select and Divider 11 4 Timer A The timer clock can be sourced from ACLK SMCLK or externally via TACLK or INCLK The clock source is selected with the TASSELx bits The selected clock source may be passed directly to the timer or divided by 2 4 or 8 using the IDx bits The clock divider is reset when TACLR is set Timer_A Operation 11 2 2 Starting the Timer The timer may be started or restarted in the following ways The timer counts when MCx gt 0 and the clock source is active When the timer mode is either up or up down the timer may be stopped by writing O to TACCRO The timer may then be restarted by writing a nonzero value to TACCRO In this scenario the timer starts incrementing in the up direction from zero 11 2 3 Timer Mode Control The timer has four modes of operation as described in Table 11 1 stop up continuous and up down The operating mode is selected w
157. ansfer Modes DMADTx Transfer Description Mode 000 Single transfer Each transfer requires a trigger DMAEN is automatically cleared when DMAxSZ transfers have been made 001 Block transfer A complete block is transferred with one trigger DMAEN is automatically cleared at the end of the block transfer 010 011 Burst block CPU activity is interleaved with a block transfer transfer DMAEN is automatically cleared at the end of the burst block transfer 100 Repeated Each transfer requires a trigger DMAEN remains single transfer enabled 101 Repeated A complete block is transferred with one trigger block transfer DMAEN remains enabled Toon ded CPU activity is interleaved with a block transfer nbi DMAEN remains enabled transfer DMA Controller 8 5 DMA Operation Single Transfer In single transfer mode each byte word transfer requires a separate trigger The single transfer state diagram is shown in Figure 8 3 The DMAxSZ register is used to define the number of transfers to be made The DMADSTINCRx and DMASRCINCRx bits select if the destination address and the source address are incremented or decremented after each transfer If DMAxSZ 0 no transfers occur The DMAxSA DMAxDA and DMAxSZ registers are copied into temporary registers The temporary values of DMAxSA and DMAxDA are incremented or decremented after each transfer The DMAxSZ register is decremented after each transfer When the DMAxSZ register decrements t
158. are Oscillator Fault Flash Access External NMI Handler Violation Handler Handler Optional RETI End of NMI Interrupt Handler DE Note Enabling NMI Interrupts with ACCVIE NMIIE and OFIE To prevent nested NMI interrupts the ACCVIE NMIIE and OFIE enable bits should not be set inside of an NMI interrupt service routine sss 2 2 2 Maskable Interrupts Maskable interrupts are caused by peripherals with interrupt capability including the watchdog timer overflow in interval timer mode Each maskable interrupt source can be disabled individually by an interrupt enable bit or all maskable interrupts can be disabled by the general interrupt enable GIE bit in the status register SR Each individual peripheral interrupt is discussed in the associated peripheral module chapter in this manual 2 10 System Resets Interrupts and Operating Modes System Reset and Initialization 2 2 3 Interrupt Processing When an interrupt is requested from a peripheral and the peripheral interrupt enable bit and GIE bit are set the interrupt service routine is requested Only the individual enable bit must be set for non maskable interrupts to be requested Interrupt Acceptance The interrupt latency is 6 cycles starting with the acceptance of an interrupt request and lasting until the start of execution of the first instruction of the interrupt service routine as shown in Figure 2 7 The interrupt logic executes the
159. as been triggered further trigger signals occurring during the block transfer are ignored The block transfer state diagram is shown in Figure 8 4 The DMAxSZ register is used to define the size of the block and the DMADSTINCRx and DMASRCINCRx bits select if the destination address and the source address are incremented or decremented after each transfer of the block If DMAxSZ 0 no transfers occur The DMAxSA DMAxDA and DMAxSZ registers are copied into temporary registers The temporary values of DMAxSA and DMAxDA are incremented or decremented after each transfer in the block The DMAxSZ register is decremented after each transfer of the block and shows the number of transfers remaining in the block When the DMAxSZ register decrements to zero it is reloaded from its temporary register and the corresponding DMAIFG flag is set During a block transfer the CPU is halted until the complete block has been transferred The block transfer takes 2 x MCLK x DMAxSZ clock cycles to complete CPU execution resumes with its previous state after the block transfer is complete In repeated block transfer mode the DMAEN bit remains set after completion of the block transfer The next trigger after the completion of a repeated block transfer triggers another block transfer 8 8 DMA Controller Figure 8 4 DMA Block Transfer State Diagram DMAEN DMAEN 0 DMAREQ 0 T Size 2 DMAxSZ DMADTx 1 AND DMAxSZ 0 OR DMAEN
160. ble These bits enable or disable the interrupt request for the 15 0 ADC12IFGx bits 0 Interrupt disabled 1 Interrupt enabled ADC12IFG ADC12 Interrupt Flag Register 15 14 13 12 11 10 9 8 ADC12 ADC12 ADC12 ADC12 ADC12 ADC12 ADC12 ADC12 IFG15 IFG14 IFG13 IFG12 IFG11 IFG10 IFG9 IFG8 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 7 6 5 4 3 2 1 0 ADC12 ADC12 ADC12 ADC12 ADC12 ADC12 ADC12 ADC12 IFG7 IFG6 IFG5 IFG4 IFG3 IFG2 IFG1 IFGO rw 0 rw 0 rw 0 0 rw 0 rw 0 rw 0 rw 0 ADC12IFGx Bits ADC12MEMXx Interrupt flag These bits are set when corresponding 15 0 ADC12MEMx is loaded with a conversion result The ADC12IFGx bits are reset if the corresponding ADC12MEM x is accessed or may be reset with software 0 No interrupt pending 1 Interrupt pending 17 26 ADC12 ADC 12 Registers ADC12IV ADC12 Interrupt Vector Register 15 14 13 12 11 10 9 8 ro ro ro rO ro ro ro ro 7 6 5 4 3 2 1 0 ro ro r 0 r 0 r 0 r 0 r 0 ro ADC12IVx Bits ADC12 interrupt vector value 15 0 ADC12IV Contents 000h 002h 004h 006h 008h 00Ah 00Ch OOEh 010h 012h 014h 016h 018h 01Ah 01Ch 01Eh 020h 022h 024h Interrupt Source No interrupt pending ADC12MEMXx overflow Conversion time overflow ADC12MEMO interrupt flag ADC12MEM interrupt flag ADC12MEN2 interrupt flag ADC12MEMs3 interrupt flag ADC12MEM4 interrupt flag ADC12MEM5 interrupt flag ADC12MEM6 interrupt flag ADC12MEN7 interrupt flag ADC12MEMS8 in
161. ce the source is active the 12C module releases the SCL line to the master When the 12C module activates an inactive clock source the clock source becomes active for the whole device and any peripheral configured to use the clock source may be affected For example a timer using SMCLK will increment while the 12C module forces SMCLK active USART Peripheral Interface I C Mode 15 17 12C Module Operation 15 2 8 12C Interrupts The 12C module has one interrupt vector for eight interrupt flags listed in Table 15 3 Each interrupt flag has its own interrupt enable bit When an interrupt is enabled and the GIE bit is set the interrupt flag will generate an interrupt request Table 15 3 12C Interrupts Interrupt Interrupt Condition Flag ALIFG Arbitration lost Arbitration can be lost when two or more transmitters start a transmission simultaneously or when the software attempts to initiate an 12C transfer while I2CBB 1 The ALIFG flag is set when arbitration has been lost When ALIFG is set the MST and I2CSTP bits are cleared and the 12C controller becomes a slave receiver NACKIFG No acknowledge interrupt This flag is set when an acknowledge is expected but is not received in master mode NACKIFG is used in master mode only OAIFG Own address interrupt This flag is set when another master has addressed the I2C module OAIFG is used in slave mode only ARDYIFG Register access ready interrupt This flag is set as descr
162. ces only Timer B 12 25 Chapter 13 USART Peripheral Interface UART Mode The universal synchronous asynchronous receive transmit USART peripheral interface supports two serial modes with one hardware module This chapter discusses the operation of the asynchronous UART mode USARTO is implemented on the MSP430x12xx MSP430x13xx and MSP430x15x devices In addition to USARTO the MSP430x14x and MSP430x16x devices implement a second identical USART module USART1 Topic Page 13 1 USART Introduction UART Mode 13 2 13 2 USART Operation UART Mode Luee 13 4 13 3 USART Registers UART Mode sssesseeseeeee 13 21 13 1 USART Introduction UART Mode 13 1 USART Introduction UART Mode 13 2 In asynchronous mode the USART connects the MSP430 to an external system via two external pins URXD and UTXD UART mode is selected when the SYNC bit is cleared UART mode features include L 7 or 8 bit data with odd even or non parity Independent transmit and receive shift registers Separate transmit and receive buffer registers LSB first data transmit and receive L O tL Built in idle line and address bit communication protocols for multiprocessor systems Receiver start edge detection for auto wake up from LPMx modes Programmable baud rate with modulation for fractional baud rate support Status flags for error detection and suppress
163. chdog timer expiration when in watchdog mode only n Watchdog timer security key violation c A Flash memory security key violation 2 2 System Resets Interrupts and Operating Modes System Reset and Initialization 2 1 1 Power On Reset POR When the Vcc rise time is slow the POR detector holds the POR signal active until Vcc has risen above the Vpop level as shown in Figure 2 2 When the Vcc supply provides a fast rise time the POR delay ttpog DELAY provides active time on the POR signal to allow the MSP430 to initialize On devices with no brownout reset circuit If power to the MSP430 is cycled the supply voltage Vcc must fall below Vmin to ensure that a POR signal occurs when Vcc is powered up again If Vcc does not fall below Vmin during a cycle or a glitch a POR may not be generated and power up conditions may not be set correctly In this case a low level on RST NMI may not cause a POR and a full power cycle will be required See device specific datasheet for parameters Figure 2 2 POR Timing V Vcc Vec min k 5 7 f J4 VORP fe a re gp eye Vmin i oc ee a a ee N Set Signal for POR circuitry l l C gt POR DELAY POR DELAY System Resets Interrupts and Operating Modes 2 3 System Reset and Initialization 2 1 2 Brownout Reset BOR Some devices have a brownout reset circuit see device specific datasheet that replaces
164. cted for UCLK ACLK or SMCLK j 0 for the start bit 1 for data bit DO and so on UxBR is the division factor in registers UXBR1 and UxBRO 13 14 USART Peripheral Interface UART Mode USART Operation UART Mode For example the receive errors for the following conditions are calculated Baud rate 2400 BRCLK 32 768 Hz ACLK UxBR 13 since the ideal division factor is 13 65 UxMCTL 6B m7 0 m6 1 m5 1 m4 0 m3 1 m2 0 m1 1 and m0 1 The LSB of UxMCTL is used first Start bit Error Paua raie rate x 2x 1 6 0 x UxBR 0 1 0 x 100 2 54 Data bit DO Error Data bit D1 Error Data bit D2 Error Data bit D3 Error Data bit D4 Error Data bit D5 Error Data bit D6 Error Data bit D7 Error BRCLK baud rate aaae BRGLK eX 6 1 x UxBR 1 1 4 x 100 5 08 baud rate X ox 1 6 2 x UxBR 1 1 2 x 100 0 29 Gers BRCLK grate sauc rate x 2x 1 6 3 x UxBR 2 I 1 3 x 100 2 83 Paste x 2x 1 6 4 x UxBR 2 I 1 4 x 100 1 9596 gute x 2x 1 6 5 x UxBR 3 1 5 x 100 0 59 Fog te x 2x 1 6 6 x UxBR 4 I 1 6 x 100 3 13 z audiate x 2x 1 6 7 x UxBR 4 1 7 x 100 1 66 z e x 2x 1 6 8 x UxBR 5 1 8 x 100 0 88 Parity bit Error Paua raie x 2x 1 6 9 x UxBR 1 9 x 100 3 42 Stop bit 1 Error BRCLK BRCLK 5 Emira
165. d URXIEOt Bit 0 USARTO receive interrupt enable This bit enables the URXIFGO interrupt 0 Interrupt not enabled 1 Interrupt enabled t MSP430x12xx devices only 13 28 USART Peripheral Interface UART Mode USART Registers UART Mode IFG1 Interrupt Flag Register 1 rw 1 UTXIFGOT Bit7 URXIFGOT Bit 6 Bits 5 0 7 6 5 4 3 2 1 0 rw 0 USARTO transmit interrupt flag UTXIFGO is set when UOTXBUF is empty 0 No interrupt pending 1 Interrupt pending USARTO receive interrupt flag URXIFGO is set when UORXBUF has received a complete character 0 No interrupt pending 1 Interrupt pending These bits may be used by other modules See device specific datasheet t Does not apply to MSP430x12xx devices See IFG2 for the MSP430x12xx USARTO interrupt flag bits IFG2 Interrupt Flag Register 2 7 6 5 4 3 2 1 0 rw 1 rw 0 rw 1 rw 0 Bits 7 6 UTXIFG1 Bit 5 URXIFG1 Bit 4 Bits 3 2 These bits may be used by other modules See device specific datasheet USART1 transmit interrupt flag UTXIFG1 is set when U1TXBUF empty 0 No interrupt pending 1 Interrupt pending USART1 receive interrupt flag URXIFG1 is set when U1RXBUF has received a complete character 0 No interrupt pending 1 Interrupt pending These bits may be used by other modules See device specific datasheet USART Peripheral Interface UART Mode 13 29 USART Registers UART Mode UTXIFGO Bit 1 USARTO transmit interrupt flag UTXIFGO is set when UOTXBUF is
166. d internally is in the 5 MHz range but varies with individual devices supply voltage and temperature See the device specific datasheet for the ADC10OSC specification The user must ensure that the clock chosen for ADC10CLK remains active until the end of a conversion If the clock is removed during a conversion the operation will not complete and any result will be invalid ADC10 Operation 18 2 2 ADC10 Inputs and Multiplexer The eight external and four internal analog signals are selected as the channel for conversion by the analog input multiplexer The input multiplexer is a break before make type to reduce input to input noise injection resulting from channel switching as shown in Figure 18 2 The input multiplexer is also a T switch to minimize the coupling between channels Channels that are not selected are isolated from the A D and the intermediate node is connected to analog ground Vss so that the stray capacitance is grounded to help eliminate crosstalk The ADC10 uses the charge redistribution method When the inputs are internally switched the switching action may cause transients on the input signal These transients decay and settle before causing errant conversion Figure 18 2 Analog Multiplexer Ax Analog Port Selection R 1000hm INCHx e ESD Protection The ADC10 external inputs AO to A4 and Vepgr and Vpgr share terminals with I O port P2 which are digital CMOS gates Optional inp
167. de USART Registers SPI Mode ME1 Module Enable Register 1 7 6 5 4 3 2 1 0 rw 0 USPIEOT Bit 7 Bit 6 Bits 5 0 This bit may be used by other modules See device specific datasheet USARTO SPI enable This bit enables the SPI mode for USARTO 0 Module not enabled 1 Module enabled These bits may be used by other modules See device specific datasheet t Does not apply to MSP430x12xx devices See ME2 for the MSP430x12xx USARTO module enable bit ME2 Module Enable Register 2 7 6 5 4 3 2 1 0 rw 0 rw 0 USPIE1 USPIEO MSP430x12xx devices only Bits 7 5 Bit 4 Bits 3 1 Bit 0 These bits may be used by other modules See device specific datasheet USART1 SPI enable This bit enables the SPI mode for USART1 0 Module not enabled 1 Module enabled These bits may be used by other modules See device specific datasheet USARTO SPI enable This bit enables the SPI mode for USARTO 0 Module not enabled 1 Module enabled USART Peripheral Interface SPI Mode 14 19 USART Registers SPI Mode IE1 Interrupt Enable Register 1 7 6 5 4 3 2 1 0 pepe qo oq qp E rw 0 rw 0 UTXIEOT Bit 7 USARTO transmit interrupt enable This bit enables the UTXIFGO interrupt 0 Interrupt not enabled 1 Interrupt enabled URXIEOT Bit 6 USARTO receive interrupt enable This bit enables the URXIFGO interrupt 0 Interrupt not enabled 1 Interrupt enabled Bits These bits may be used by other modules See device specific datasheet
168. dule with the DMA Controller 8 2 10 Using ADC12 with the DMA Controller llle 8 2 11 Using DAC12 With the DMA Controller 0000 cee eee ee 8 39 DMA Registos sordos dorus qe Modos AIONA EAEEREN DAE Vds 9 Digitall O wie cient ede lege cements whee abe okie eee O cm 9 1 Digital O Introduction i i ssec mew em x ca ene evade dr baa i 9 2 Digital O Operation 0 III 9 2 1 Input Register PAIN 0 0 cee eee eee nan 9 2 2 Output Registers PROUT 0c cette 9 2 3 Direction Registers PnDIR 00 eens 9 2 4 Function Select Registers PnSEL 0 00 c cece eee 9 25 Pleand P2 Interrupts 22s sese toe Lm ere RR RREER ED ERR 9 2 6 Configuring Unused Port Pins 0 000 sere 9 3 Digital l O Registers a csovees gRgecks de diea ERE eee E ee eid ey Ed Contents 10 Watchdog Timer 11 12 13 10 1 Watchdog Timer Introduction 10 2 Watchdog Timer Operation 0 eee eens 10 2 1 Watchdog Timer Counter 10 2 2 Watchdog Mode meena aiia aa aa ia tenes 10 2 3 Interval Timer Mode 0 00 a a a iini a Gii 10 2 4 Watchdog Timer Interrupts 0 0 eee 10 2 5 Operation in Low Power Modes 10 2 6 Software Examples 10 3 Watchdog Timer Registers TIMEA esse testis ence eet nani ERR recedere m RU CEPR IRE UAE IRL we ease amass eae 11 1 Timer A Introduction 11 2 Timer A Operation iusssssssssssssssssess sh 11 2 1 16 Bit Timer Counter 11
169. e Switching Between Output Modes When switching between output modes one of the OUTMODX bits should remain set during the transition unless switching to mode 0 Otherwise output glitch ing can occur because a NOR gate decodes output mode 0 A safe method for switching between output modes is to use output mode 7 as a transition state BIS BIC OUTMOD_7 amp TBCCTLx Set output mode 7 OUTMODx amp TBCCTLx Clear unwanted bits LLLLLLLL Timer B 12 17 Timer_B Operation 12 2 6 Timer_B Interrupts Two interrupt vectors are associated with the 16 bit Timer_B module O TBCCRO interrupt vector for TBCCRO CCIFG Lj TBIV interrupt vector for all other CCIFG flags and TBIFG In capture mode any CCIFG flag is set when a timer value is captured in the associated TBCCRx register In compare mode any CCIFG flag is set when TBR counts to the associated TBCLx value Software may also set or clear any CCIFG flag All CCIFG flags request an interrupt when their corresponding CCIE bit and the GIE bit are set TBCCRO Interrupt Vector The TBCCRO CCIFG flag has the highest Timer_B interrupt priority and has a dedicated interrupt vector as shown in Figure 12 15 The TBCCRO CCIFG flag is automatically reset when the TBCCRO interrupt request is serviced Figure 12 15 Capture Compare TBCCRO Interrupt Flag Capture EQUO IRQ
170. e 1 2 See the device specific data sheets for specific memory maps Code access are always performed on even addresses Data can be accessed as bytes or words The addressable memory space is 64 KB with future expansion planned Figure 1 2 Memory Map OFFFFh OFFEOh OFFDFh 0200h 01FFh 0100h OFFh 010h OFh Oh 1 4 44 Flash ROM 1 4 22 RAM 1 4 Introduction Access Interrupt Vector Table Word Byte Flash ROM Word Byte Word Byte 16 Bit Peripheral Modules Word 8 Bit Peripheral Modules Byte Special Function Registers Byte The start address of Flash ROM depends on the amount of Flash ROM present and varies by device The end address for Flash ROM is OFFFFh Flash can be used for both code and data Word or byte tables can be stored and used in Flash ROM without the need to copy the tables to RAM before using them The interrupt vector table is mapped into the upper 16 words of Flash ROM address space with the highest priority interrupt vector at the highest Flash ROM word address OFFFEh RAM starts at 0200h The end address of RAM depends on the amount of RAM present and varies by device RAM can be used for both code and data Address Space 1 4 3 Peripheral Modules Peripheral modules are mapped into the address space The address space from 0100 to 01FFh is reserved for 16 bit peripheral modules These modules should be accessed with word instructions If byte instructions are used only even addre
171. e asynchronous to the timer clock and cause a race condition Setting the SCS bit will synchronize the capture with the next timer clock Setting the SCS bit to synchronize the capture signal with the timer clock is recommended This is illustrated in Figure 12 10 Figure 12 10 Capture Signal SCS 1 CCI Capture j A Set TBCCRx CCIFG l Overflow logic is provided in each capture compare register to indicate if a second capture was performed before the value from the first capture was read Bit COV is set when this occurs as shown in Figure 12 11 COV must be reset with software Timer_B 12 11 Timer_B Operation Figure 12 11 Capture Cycle in Register TBCCTLx Idle Capture Capture Read No Capture Taken Read Taken Capture Capture Capture Read and No Capture Capture Clear Bit COV Second Capture Taken COV 1 Idle Capture Capture Initiated by Software Compare Mode 12 12 Timer_B Captures can be initiated by software The CMx bits can be set for capture on both edges Software then sets bit CCIS1 1 and toggles bit CCISO to switch the capture signal between Vcc and GND initiating a capture each time CCISO changes state MOV CAP SCS CCIS1 CM_3 amp TBCCTLx Setup TBCCTLx XOR CCISO amp TBCCTLx TBCCTLx TBR The compare mode is selected when CAP 0 Compare mode is used to generate PWM output signals or interrupts at specific time interval
172. e e eee eee eee 7 3 Hardware Multiplier Registers leues 7 1 Hardware Multiplier Introduction 7 1 Hardware Multiplier Introduction The hardware multiplier is a peripheral and is not part of the MSP430 CPU This means its activities do not interfere with the CPU activities The multiplier registers are peripheral registers that are loaded and read with CPU instructions The hardware multiplier supports Unsigned multiply Signed multiply Signed multiply accumulate c m Unsigned multiply accumulate n cl 16x16 bits 16x8 bits 8x16 bits 8x8 bits The hardware multiplier block diagram is shown in Figure 7 1 Figure 7 1 Hardware Multiplier Block Diagram a MPY 0000 MPY 130h MPYS 132h MAC 134h MACS 136h Accessible Register MACS MPYS MPY MPYS MAC MACS 32 bit Multiplexer RESHI 13Ch RESLO 13Ah 31 rw rw 0 7 2 Hardware Multiplier Hardware Multiplier Operation 7 2 Hardware Multiplier Operation The hardware multiplier supports unsigned multiply signed multiply unsigned multiply accumulate and signed multiply accumulate operations The type of operation is selected by the address the first operand is written to The hardware multiplier has two 16 bit operand registers OP1 and OP2 and three result registers RESLO RESHI and SUMEXT RESLO stores the low word of the result RESHI stores the high word of the result and SUMEXT
173. e not useful for TBCLO because EQUx EQUO 000 OUT bit value 001 Set 010 Toggle reset 011 Set reset 100 Toggle 101 Reset 110 Toggle set 111 Reset set Timer_B 12 23 Timer_B Registers CCIE CCl OUT COV CCIFG 12 24 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Timer_B Capture compare interrupt enable This bit enables the interrupt request of the corresponding CCIFG flag 0 Interrupt disabled 1 Interrupt enabled Capture compare input The selected input signal can be read by this bit Output For output mode 0 this bit directly controls the state of the output 0 Output low 1 Output high Capture overflow This bit indicates a capture overflow occurred COV must be reset with software 0 No capture overflow occurred 1 Capture overflow occurred Capture compare interrupt flag 0 No interrupt pending 1 Interrupt pending Timer_B Registers TBIV Timer_B Interrupt Vector Register 15 14 13 12 11 10 9 8 ro ro ro rO ro ro ro ro 7 6 5 4 3 2 1 0 ro ro ro ro r 0 r 0 r 0 ro TBIVx Bits Timer B interrupt vector value 15 0 Interrupt TBIV Contents Interrupt Source Interrupt Flag Priority 00h No interrupt pending 02h Capture compare 1 TBCCR1 CCIFG Highest 04h Capture compare 2 TBCCR2 CCIFG 06h Capture compare 3f TBCCR3 CCIFG 08h Capture compare 4t TBCCR4 CCIFG OAh Capture compare 5t TBCCR5 CCIFG OCh Capture compare 6t TBCCR6 CCIFG OEh Timer overflow TBIFG Lowest T MSP430x14x MSP430x16x devi
174. e recommended use of TAIV and the handling overhead The TAIV value is added to the PC to automatically jump to the appropriate routine The numbers at the right margin show the necessary CPU cycles for each instruction The software overhead for different interrupt sources includes interrupt latency and return from interrupt cycles but not the task handling itself The latencies are Capture compare block TACCRO 11 cycles Capture compare blocks TACCR1 TACCR2 16 cycles Timer overflow TAIFG 14 cycles Interrupt handler for TACCRO CCIFG Cycles CCIFG 0 HND r T Start of handler Interrupt latency 6 RETI Interrupt handler for TAIFG TACCR1 and TACCR2 CCIFG TA HND ids Interrupt latency 6 ADD amp TAIV PC Add offset to Jump table 3 RETI Vector 0 No interrupt 5 JMP CCIFG 1 HND Vector 2 TACCR1 2 JMP CCIFG 2 HND Vector 4 TACCR2 2 RETI Vector 6 Reserved 5 RETI Vector 8 Reserved 5 TAIFG HND Vector 10 TAIFG Flag Task starts here RETI 5 CCIFG 2 HND Vector 4 TACCR2 P Task starts here RETI Back to main program 5 CCIFG 1 HND Vector 2 TACCR1 oe Task starts here RETI Back to main program 5 11 18 Timer_A 11 3 Timer_A Registers The Timer_A registers are listed in Table 11 3 Table 11 3 Timer A Registers Register Timer_A control Timer_A counter Timer_A capture compare control 0 Timer_A capture compare 0 Timer_A capture compare control 1 Timer_A capture compare 1 Timer_
175. e started and becomes inactive approximately 50 us after the oscillator re starts as shown in Figure 4 8 Figure 4 9 Oscillator Fault Signal 4 10 XT1OFF XT2OFF LFXT1CLK XT2CLK XT_OscFault P software enables OSC software disables OSC ELS OSC faults Basic Clock Module Oscillator Fault Detection Basic Clock Module Operation Signal XT_OscFault triggers the OFIFG flag as shown in Figure 4 10 The LFXT1_OscFault signal is low when LFXT1 is in LF mode On devices without XT2 the OFIFG flag cannot be cleared when LFXT1 is in LF mode MCLK may be sourced by LFXT1CLK in LF mode by setting the SELMx bits even though OFIFG remains set On devices with XT2 the OFIFG flag can be cleared by software when LFXT1 is in LF mode and it remains cleared MCLK may be sourced by LFXT1CLK in LF mode regardless of the state of the OFIFG flag Figure 4 10 Oscillator Fault Interrupt n P v I ne XT1off Oscillator Fault Interrupt Request t1 LFXT1 OscFault e XT OscFault POR XT2off e OF IRQ NMI l XT2_OscFault e ee s e xr e IFG1 1 IE1 1 Clear PUC IRQA ln A costo I E ETES E nee ills ee ee oe E eS SS Eu LLL zi Oscillator Fault Fail Safe Logic e SELM1 am
176. e x is used to indicate which DAC12 module is being discussed In cases where operation is identical the register is simply referred to as DAC12 xCTL LLLL X X The block diagram of the two DAC12 modules in the MSP430F15x 16x devices is shown in Figure 19 1 DAC 12 Introduction Figure 19 1 DAC 12 Block Diagram Ve REF gt __ _ _ _ To ADC 12 module VREF e e 2 5V or 1 5V reference from ADC12 DAC12SREFx DAC12AMPx DAC12IR e 00 3 01 oO 10 11 VR VR DAC12LSELx DAC12_0 DAC12_0OUT Latch Bypass DAC12RES DAC12DF DAC12 OLatch 4 DAC12_0DAT DAC12GRP DAC12ENC DAC12_0DAT Updated DAC12SREFx DAC12AMPx DAC12IR 00 3 01 10 DAC12LSELx DAC12_1 DAC12 1OUT gt DAC12RES DAC12DF gt DAC12_1Latch DAC12GRP DAC12ENC DAC12_1DAT DAC12_1DAT Updated DAC12 19 3 DAC 12 Operation 19 2 DAC12 Operation The DAC12 module is configured with user software The setup and operation of the DAC12 is discussed in the following sections 19 2 1 DAC12 Core The DAC12 can be configured to operate in 8 or 12 bit mode using the DAC12RES bit The full scale output is programmable to be 1x or 3x the selec
177. egisters ADC12CTLO and ADC12CTL1 The core is enabled with the ADC12ON bit The ADC12 can be turned off when not in use to save power With few exceptions the ADC12 control bits can only be modified when ENC 0 ENC must be set to 1 before any conversion can take place Conversion Clock Selection 17 4 ADC12 The ADC12CLK is used both as the conversion clock and to generate the sampling period when the pulse sampling mode is selected The ADC12 source clock is selected using the ADC12SSELx bits and can be divided from 1 8 using the ADC12DIVx bits Possible ADC12CLK sources are SMCLK MCLK ACLK and an internal oscillator ADC12O0SC The ADC12OSC generated internally is in the 5 MHz range but varies with individual devices supply voltage and temperature See the device specific datasheet for the ADC12OSC specification The user must ensure that the clock chosen for ADC12CLK remains active until the end of a conversion If the clock is removed during a conversion the operation will not complete and any result will be invalid ADC 12 Operation 17 2 2 ADC12 Inputs and Multiplexer The eight external and four internal analog signals are selected as the channel for conversion by the analog input multiplexer The input multiplexer is a break before make type to reduce input to input noise injection resulting from channel switching as shown in Figure 17 2 The input multiplexer is also a T switch to minimize the coupling between channel
178. egisters RO R1 R2 and R3 have dedicated functions R4 to R15 are working registers for general use 3 2 1 Program Counter PC The 16 bit program counter PC RO points to the next instruction to be executed Each instruction uses an even number of bytes two four or six and the PC is incremented accordingly Instruction accesses in the 64 KB address space are performed on word boundaries and the PC is aligned to even addresses Figure 3 2 shows the program counter Figure 3 2 Program Counter 15 1 0 Program Counter Bits 15 to 1 ES The PC can be addressed with all instructions and addressing modes A few examples MOV LABEL PC Branch to address LABEL MOV LABEL PC Branch to address contained in LABEL MOV R14 PC Branch indirect to address in R14 3 4 RISC 16 Bit CPU 3 2 2 Stack Pointer SP CPU Registers The stack pointer SP R1 is used by the CPU to store the return addresses of subroutine calls and interrupts It uses a predecrement postincrement scheme In addition the SP can be used by software with all instructions and addressing modes Figure 3 3 shows the SP The SP is initialized into RAM by the user and is aligned to even addresses Figure 3 4 shows stack usage Figure 3 3 Stack Pointer 15 1 0 Stack Pointer Bits 15 to 1 ET MOV 2 SP R6 MOV R7 0 SP PUSH 0123h POP R8 Figure 3 4 Stack Usage Item I2 R6 Overwrite TOS with R7 Put 0123h onto TOS R8 0123h Address PUSH
179. elf wake up function An integrated high speed digitally controlled oscillator DCO can source the master clock MCLK used by the CPU and high speed peripherals By design the DCO is active and stable in less than 6 us MSP430 based solutions effectively use the high performance 16 bit RISC CPU in very short bursts J Low frequency auxiliary clock Ultralow power stand by mode 41 High speed master clock High performance signal processing 1 2 Introduction Embedded Emulation Figure 1 1 MSP430 Architecture ACLK Flash ROM RAM SMCLK ININ ANAA MAB 16 Bit RISC CPU 16 Bit JTAG Debug MDB 16 Bit us MDB 8 Bit 3 1 bes ee oe eed 1 3 Embedded Emulation Dedicated embedded emulation logic resides on the device itself and is accessed via JTAG using no additional system resources The benefits of embedded emulation include Unobtrusive development and debug with full speed execution breakpoints and single steps in an application are supported _j Development is in system subject to the same characteristics as the final application L Mixed signal integrity is preserved and not subject to cabling interference Introduction 1 3 Address Space 1 4 Address Space The MSP430 von Neumann architecture has one address space shared with special function registers SFRs peripherals RAM and Flash ROM memory as shown in Figur
180. empty 0 No interrupt pending 1 Interrupt pending URXIFGO Bito USARTO receive interrupt flag URXIFGO is set when UORXBUF has received a complete character 0 No interrupt pending 1 Interrupt pending t MSP430x12xx devices only 13 30 USART Peripheral Interface UART Mode Chapter 14 USART Peripheral Interface SPI Mode The universal synchronous asynchronous receive transmit USART peripheral interface supports two serial modes with one hardware module This chapter discusses the operation of the synchronous peripheral interface or SPI mode USARTO is implemented on the MSP430x12xx MSP430x13xx and MSP430x15x devices In addition to USARTO the MSP430x14x and MSP430x16x devices implement a second identical USART module USART1 Topic Page 14 1 USART Introduction SPI Mode uuuue 14 2 14 2 USART Operation SPI Mode LLssseuuee 14 4 14 3 USART Registers SPI Mode sssuuessesse 14 13 14 1 USART Introduction SPI Mode 14 1 USART Introduction SPI Mode In synchronous mode the USART connects the MSP430 to an external system via three or four pins SIMO SOMI UCLK and STE SPI mode is selected when the SYNC bit is set and the 12C bit is cleared SPI mode features include 7 or 8 bit data length 3 pin and 4 pin SPI operation Master or slave modes Independent transmit and receive shift registers Separate transmit and receive buffer reg
181. en each conversion completes The sequence continues until an EOS bit in ADC12MCTLx is processed this is the last control byte processed When conversion results are written to a selected ADC12MEMx the corresponding flag in the ADC12IFGx register is set 17 2 7 ADC12 Conversion Modes The ADC12 has four operating modes selected by the CONSEQx bits as discussed in Table 17 1 Table 17 1 Conversion Mode Summary 17 10 CONSEQx Mode Operation 00 Single channel A single channel is converted once single conversion 01 Sequence of A sequence of channels is converted once channels 10 Repeat single A single channel is converted repeatedly channel 11 Repeat sequence A sequence of channels is converted of channels repeatedly ADC12 ADC 12 Operation Single Channel Single Conversion Mode A single channel is sampled and converted once The ADC result is written to the ADC12MEMXx defined by the CSTARTADDx bits Figure 17 6 shows the flow of the Single Channel Single Conversion mode When ADC12SC triggers a conversion successive conversions can be triggered by the ADC12SC bit When any other trigger source is used ENC must be toggled between each conversion Figure 17 6 Single Channel Single Conversion Mode CONSEQx 00 ADC120N 1 x CSTARTADDx Pd Wait for Enable SHSx 0 l and ENC 1or4 l and N ADC12SC 4 IN U ENS SAMPCON amp N SAMPCON 1 nw Sample Input C
182. ence it must be enabled and configured via the applicable ADC12 control bits see the ADC 12 chapter Once the ADC12 reference is configured the reference voltage appears on the Vref signal DAC12 Reference Input and Voltage Output Buffers The reference input and voltage output buffers of the DAC12 can be configured for optimized settling time vs power consumption Eight combinations are selected using the DAC12AMPx bits In the low low setting the settling time is the slowest and the current consumption of both buffers is the lowest The medium and high settings have faster settling times but the current consumption increases See the device specific data sheet for parameters 19 2 3 Updating the DAC12 Voltage Output The DAC12_xDAT register can be connected directly to the DAC12 core or double buffered The trigger for updating the DAC12 voltage output is selected with the DAC12LSELx bits When DAC12LSELx 0 the data latch is transparent and the DAC12_xDAT register is applied directly to the DAC12 core the DAC12 output updates immediately when new DAC 12 data is written to the DAC12 xDAT register regardless of the state of the DAC12ENC bit When DAC12LSELx 1 DAC12 data is latched and applied to the DAC12 core after new data is written to DAC12 xDAT When DAC12LSELx 2 or 3 data is latched on the rising edge from the Timer A CCR1 output or Timer B CCR 2 output respectively DAC12ENC must be set to latch the new data when DAC12
183. ended This is illustrated in Figure 11 10 Figure 11 10 Capture Signal SCS 1 CCI Capture j Set TACCRx CCIFG l Overflow logic is provided in each capture compare register to indicate if a second capture was performed before the value from the first capture was read Bit COV is set when this occurs as shown in Figure 11 11 COV must be reset with software Timer_A 11 11 Timer_A Operation Figure 11 11 Capture Cycle Idle Capture Capture Read No Capture Taken Read Taken Capture Capture Taken Capture Capture Read and No Capture Capture Clear Bit COV in Register TACCTLx Second Capture Taken COV 1 Idle Capture Capture Initiated by Software Captures can be initiated by software The CMx bits can be set for capture on both edges Software then sets CCIS1 1 and toggles bit CCISO to switch the capture signal between Vcc and GND initiating a capture each time CCISO changes state MOV CAP SCS CCIS1 CM_3 amp TACCTLx Setup TACCTLx XOR CCISO amp TACCTLx TACCTLx TAR Compare Mode The compare mode is selected when CAP 0 The compare mode is used to generate PWM output signals or interrupts at specific time intervals When TAR counts to the value in a TACCRx Interrupt flag CCIFG is set Internal signal EQUx 1 Lj EQUXx affects the output according to the output mode O The input signal CCI is latched into SCCI 11 12 T
184. enerate a STOP condition at the end of transmission This is used for RESTART conditions I2CNDAT is used to determine length of transmission Setting I2CSTT initiates activity A STOP condition is automatically generated after I2CNDAT number of bytes have been transferred I2CNDAT is not used to determine length of transmission Software must control the length of the transmission Setting the I2CSTT bit initiates activity Software must set the I2CSTP bit to initiate a STOP condition and stop activity This mode is useful if gt 255 bytes are to be transferred This mode may not be used when a RESTART is required I2ZCRM must be reset to generate a RESTART condition Setting the I2CSTP bit generates a STOP condition on the bus after IACNDAT number of bytes have been sent or immediately if I2CNDAT number of bytes have already been sent Setting the I2CSTP bit generates a STOP condition on the bus after the current transmission completes or immediately if no transmission is currently active and a STOP has not already been generated Setting I2CSTP after a STOP has already been generated will not result in another STOP condition Reserved no bus activity 12C Module Operation Figure 15 8 Master Transmitter Mode IDLE l2CSTT 1 When I2RM 1 I2CSTP must be set before the last ICDR value is written Othwerwise correct STOP generation will not occur fx tecPsc 8 x l2CPSC Generate START I2CBUSY Is Set
185. epare pointer MOV 020h R9 Prepare counter MOV R10 TOM EDE 2 R10 _ Use pointer in R10 for both tables DEC R9 Decrement counter JNZ Loop Counter 0 continue copying Copying completed The contents of table EDE byte data are copied to table TOM The length of the tables should be 020h locations MOV EDE R10 Prepare pointer MOV 4020h R9 Prepare counter MOV B QQR10 TOM EDE 1 R10 Use pointer in R10 for both tables DEC R9 Decrement counter JNZ Loop Counter z 0 continue copying TA Copying completed 3 52 RISC 16 Bit CPU NOP Syntax Operation Emulation Description Status Bits Instruction Set No operation NOP None MOV 0 R3 No operation is performed The instruction may be used for the elimination of instructions during the software check or for defined waiting times Status bits are not affected The NOP instruction is mainly used for two purposes L To fill one two or three memory words _j To adjust software timing cca Note Emulating No Operation Instruction Other instructions can emulate the NOP function while providing different numbers of instruction cycles and code words Some examples are Examples MOV 0 R3 1 cycle 1 word MOV 0 R4 0 R4 6 cycles 3 words MOV R4 0 R4 5 cycles 2 words BIC 0 EDE R4 4 cycles 2 words JMP 42 2 cycles 1 word BIC 0 R5 1 cycle 1 word However care should be taken when using these examples to
186. er_B Operation Continuous Mode In continuous mode the timer repeatedly counts up to TBR may and restarts from zero as shown in Figure 12 4 The compare latch TBCLO works the same way as the other capture compare registers Figure 12 4 Continuous Mode TBR max Oh The TBIFG interrupt flag is set when the timer counts from TBR max to Zero Figure 12 5 shows the flag set cycle Figure 12 5 Continuous Mode Flag Setting Timer Set TBIFG l Timer B 12 7 Timer_B Operation Use of the Continuous Mode The continuous mode can be used to generate independent time intervals and output frequencies Each time an interval is completed an interrupt is generated The next time interval is added to the TBCLx latch in the interrupt service routine Figure 12 6 shows two separate time intervals ty and ty being added to the capture compare registers The time interval is controlled by hardware not software without impact from interrupt latency Up to three Timer_B3 or 7 Timer_B7 independent time intervals or output frequencies can be generated using capture compare registers Figure 12 6 Continuous Mode Time Intervals 12 8 TBR max TBCLOa Oh EQUO Interrupt EQUI Interrupt Timer_B TBCL1b TBCLic TBCLOb TBCLOc TROLON TBCLia TBCLid t i t i t Time intervals can be produced with other modes as well where TBCLO is used as the period register Their handling is more complex si
187. eration with 05Ah WDTPW in the upper byte Periodically clear an active watchdog MOV WDTPW WDTCNTCL amp WDTCTL Change watchdog timer interval MOV WDTPW WDTCNTL SSEL amp WDTCTL Stop the watchdog MOV WDTPW WDTHOLD amp WDTCTL Change WDT to interval timer mode clock 8192 interval MOV WDTPW WDTCNTCL WDTTMSEL WDTISO amp WDTCTL 10 6 Watchdog Timer Watchdog Timer Registers 10 3 Watchdog Timer Registers The watchdog timer module registers are listed in Table 10 1 Table 10 1 Watchdog Timer Registers Register Short Form Register Type Address Initial State Watchdog timer control register WDTCTL Read write 0120h 06900h with PUC SFR interrupt enable register 1 IE1 Read write 0000h Reset with PUC SFR interrupt flag register 1 IFG1 Read write 0002h Reset with PUCH t WDTIFG is reset with POR Watchdog Timer 10 7 Watchdog Timer Registers WDTCTL Watchdog Timer Register 15 14 13 12 11 10 9 8 Read as 069h WDTPW must be written as 05Ah 0 7 6 5 4 3 2 DTHOLD WDTNMIES WDTNMI WDTTMSEL WDTCNTCL WDTSSEL rw 0 rw 0 rw 0 rw 0 rO w rw 0 WDTPW WDTHOLD WDTNMIES WDTNMI WDTTMSEL WDTCNTCL WDTSSEL WDTISx Bits 15 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bits 1 rw 0 rw 0 Watchdog timer password Always read as 069h Must be written as 05Ah or a PUC will be generated Watchdog timer hold This bit stops the watchdog timer Setting WOTHOLD 1 when the WDT is
188. errupt request is generated if URXIEx and GIE are also set URXIFGx and URXIEx are reset by a system reset PUC signal or when SWRST 1 URXIFGx is automatically reset if the pending interrupt is served or when UxRXBUF is read Figure 14 11 Receive Interrupt Operation SYNC g 5 b ev 12 YNC 1 Valid Start Bit URXS eee Receiver Collects Character URXSE m o From URXD URXIEX Interrupt Service PEm Requested URXEIE URXIFGx URXWIE me RXWAKE m e m SWRST Character Received PUC UxRXBUF Read URXSE IRQA Figure 14 12 Receive Interrupt State Diagram SWRST 1 URXIFGx 0 URXIEx 0 Wait For Next Start SWRST 1 Receive USPIEx 0 USPIEx 0 Character i Interrupt uiid deri USPIEx 1 and Service Started C leted URXIEx 1 and GIE 0 em GIE 1 and URXIFGx 0 Priority Valid USART Peripheral Interface SP Mode 14 12 USART Registers SP Mode 14 3 USART Registers SPI Mode The USART registers shown in Table 14 1 and Table 14 2 are byte structured and should be accessed using byte instructions Table 14 1 USARTO Control and Status Registers Register Short Form Register Type Address Initial State USART control register UOCTL Read write 070h 001h with PUC Transmit control register UOTCTL Read write 071h 001h with PUC Receive control register UORCTL Read write 072h 000h with PUC Modulation control register UOMCTL
189. errupt flag This bit is set if ADC10MEM is loaded with a conversion result It is automatically reset when the interrupt request is accepted or it may be reset by software When using the DTC this flag is set when a block of transfers is completed 0 No interrupt pending 1 Interrupt pending Enable conversion 0 ADC10 disabled 1 ADC10 enabled Start conversion Software controlled sample and conversion start ADC10SC and ENC may be set together with one instruction ADC10SC is reset automatically 0 No sample and conversion start 1 Start sample and conversion ADC10 Registers ADC10CTL1 ADC10 Control Register 1 15 14 13 12 11 10 9 8 o ow O r rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 r 0 m Modifiable only when ENC 0 INCHx Bits Input channel select These bits select the channel for a single conversion or 15 12 the highest channel for a sequence of conversions 0000 AO 0001 A1 0010 A2 0011 A3 0100 A4 0101 A5 0110 A6 0111 A7 1000 VeREF 1001 VReF eREF 1010 Temperature sensor 1011 Voc Vsg 2 1100 Vcc Vsg 2 1101 Vcc Vsg 2 1110 Voc Vsg 2 1111 Vcc Vsg 2 SHSx Bits Sample and hold source select 11 10 00 ADC10SC bit 01 Timer A OUT1 10 Timer A OUTO 11 Timer A OUT2 ADC10DF Bit 9 ADC10 data format 0 Straight binary 1 2 s complement ISSH Bit 8 Invert signal sample and hold 0 The sample input signal is not inver
190. errupt request The CAIFG flag is automatically reset when the interrupt request is serviced or may be reset with software Figure 16 4 Comparator A Interrupt System 16 6 SET CAIFG IRQ Interrupt Service Requested IRACC Interrupt Request Accepted Comparator A Comparator_A Operation 16 2 7 Comparator_A Used to Measure Resistive Elements The Comparator_A can be optimized to precisely measure resistive elements using single slope analog to digital conversion For example temperature can be converted into digital data using a thermistor by comparing the thermistor s capacitor discharge time to that of a reference resistor as shown in Figure 16 5 A reference resister Rref is compared to Rmeas Figure 16 5 Temperature Measurement System CAO CCHB Capture Input Of Timer A re 0 25xVCC The MSP430 resources used to calculate the temperature sensed by Rmeas are Two digital I O pins to charge and discharge the capacitor I O set to output high Vcc to charge capacitor reset to discharge I O switched to high impedance input with CAPDx set when not in use One output charges and discharges the capacitor via Rref One output discharges capacitor via Rmeas The terminal is connected to the positive terminal of the capacitor The terminal is connected to a reference level for example 0 25 x Vcc The output filter should be used to minimize switching noise t 0
191. eset UxTXBUF USART Transmit Buffer Register 7 6 5 4 3 2 1 0 ERESESESERESERES rw rw rw rw rw rw rw rw UxTXBUFx Bits The transmit data buffer is user accessible and holds the data waiting to be 7 0 moved into the transmit shift register and transmitted on UTXDx Writing to the transmit data buffer clears UTXIFGx The MSB of UxTXBUF is not used for 7 bit data and is reset 13 26 USART Peripheral Interface UART Mode USART Registers UART Mode ME1 Module Enable Register 1 7 6 5 4 3 2 1 0 rw 0 rw 0 UTXEot Bit 7 URXEot Bit 6 Bits 5 0 USARTO transmit enable This bit enables the transmitter for USARTO 0 Module not enabled 1 Module enabled USARTO receive enable This bit enables the receiver for USARTO 0 Module not enabled 1 Module enabled These bits may be used by other modules See device specific datasheet t Does not apply to MSP430x12xx devices See ME for the MSP430x12xx USARTO module enable bits ME2 Module Enable Register 2 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 Bits 7 6 UTXE1 Bit 5 URXE1 Bit 4 Bits 3 2 UTXEOt Bit 1 URXEOt Bit 0 t MSP430x12xx devices only These bits may be used by other modules See device specific datasheet USART1 transmit enable This bit enables the transmitter for USART1 0 Module not enabled 1 Module enabled USART1 receive enable This bit enables the receiver for USART1 0 Module not enabled 1 Module enabled These bits may be used by other modules See d
192. esets the URXIEx UTXIEx URXIFGx RXWAKE TXWAKE RXERR BRK PE OE and FE bits and sets the UTXIFGx and TXEPT bits The receive and transmit enable flags URXEx and UTXEx are not altered by SWRST Clearing SWRST releases the USART for operation See also chapter USART Module I2C mode for USARTO when reconfiguring from 12C mode to UART mode a Note Initializing or Re Configuring the USART Module The required USART initialization re configuration process is 1 Set SWRST BIS B SWRST amp UxCTL 2 Initialize all USART registers with SWRST 1 including UxCTL 3 Enable USART module via the MEx SFRs URXEx and or UTXEx 4 5 Clear SWRST via software BIC B SWRST amp UxCTL Enable interrupts optional via the IEx SFRs URXIEx and or UTXIEx Se WH Failure to follow this process may result in unpredictable USART behavior P 13 2 2 Character Format The UART character format shown in Figure 13 2 consists of a start bit seven or eight data bits an even odd no parity bit an address bit address bit mode and one or two stop bits The bit period is defined by the selected clock source and setup of the baud rate registers Figure 13 2 Character Format Mark zu SP SP Space 2nd Stop Bit SP 1 Parity Bit PENA 1 Address Bit MM 1 Optional Bit Condition Bth Data Bit CHAR 1 13 4 USART Peripheral Interface UART Mode USART Operation UART Mode 13 2 3 Asynchrono
193. ess Violation Oscillator Fault The flash ACCVIFG flag is set when a flash access violation occurs The flash access violation can be enabled to generate an NMI interrupt by setting the ACCVIE bit The ACCVIFG flag can then be tested by NMI the interrupt service routine to determine if the NMI was caused by a flash access violation The oscillator fault signal warns of a possible error condition with the crystal oscillator The oscillator fault can be enabled to generate an NMI interrupt by setting the OFIE bit The OFIFG flag can then be tested by NMI the interrupt service routine to determine if the NMI was caused by an oscillator fault A PUC signal can trigger an oscillator fault because the PUC switches the LFXT1 to LF mode therefore switching off the HF mode The PUC signal also switches off the XT2 oscillator System Resets Interrupts and Operating Modes 2 9 System Reset and Initialization Example of an NMI Interrupt Handler The NMI interrupt is a multiple source interrupt An NMI interrupt automatically resets the NMIIE OFIE and ACCVIE interrupt enable bits The user NMI service routine resets the interrupt flags and re enables the interrupt enable bits according to the application needs as shown in Figure 2 6 Figure 2 6 NMI Interrupt Handler Start of NMI Interrupt Handler Reset by HW OFIE NMIIE ACCVIE gt Reset OFIFG Reset ACCVIFG Reset NMIIFG User s Software User s Software User s Softw
194. ete ded 4 2 4 Digitally Controlled Oscillator DCO 0 eee eee ees 4 2 5 DCOModulator 0 hh 4 2 6 Basic Clock Module Fail Safe Operation 000 0c cece eee eee 4 2 7 Synchronization of Clock Signals 00 cece eee eee tees 4 3 Basic Clock Module Registers cece ee cece sees 5 Flash Memory Controller uluseeeeeeee eee eens 5 1 Flash Memory Introduction sisssssssseees III 5 2 Flash Memory Segmentation ssssssssssssssssssse e 5 3 Flash Memory Operation 0 0 cece eee sen 5 3 1 Flash Memory Timing Generator 0 00 0c eee eee esses 5 3 2 Erasing Flash Memory ssssssssssssssss nn 5 3 8 Writing Flash Memory 0 0 0c cece eee mn 5 3 4 Flash Memory Access During Write or Erase 00000ee eee eee 5 3 5 Stopping a Write or Erase Cycle 0 ccc cece enna 5 3 6 Configuring and Accessing the Flash Memory Controller 5 3 7 Flash Memory Controller Interrupts 000 cece eee eee eee 5 3 8 Programming Flash Memory Devices 0 cece eee eee 5 4 Flash Memory Registers anisat eee ee eee eee eed viii Contents 6 Supply Voltage Supervisor seseeeeeeeeee nnn n n nnn 6 1 SVSIntroduction n REC o Ret dome dean d od on UR E erede 6 2 SVS Operation 0 ent hh 6 21 Configuring the SVS 2 2 4 becc6ese steer sed de bee a da dad ee
195. etween J Arepeated START condition and a data bit A STOP condition and a data bit L Arepeated START condition and a STOP condition USART Peripheral Interface I C Mode 15 11 12C Module Operation Automatic Data Byte Counting Slave Mode Automatic data byte counting is supported in master mode with the I2CNDAT register When I2CRM 0 the number of bytes to be received or transmitted is written to I2CNDAT A STOP condition is automatically generated after I2CNDAT number of bytes have been transferred when I2CSTP 1 Note I2CNDAT Register Do not change the I2CNDAT register after setting I2CSTT and before I2CNDAT number of bytes have been transmitted Otherwise unpredictable operation may occur If the I2CNDAT contents must be updated for a RESTART wait for ARDYIFG to become set before modifying the contents of I2CNDAT LLLLL A In slave mode transmit and receive operations are controlled automatically by the IC module The slave transmitter and slave receiver modes are shown in Figure 15 11 and Figure 15 12 In slave receiver mode serial data bits received on SDA are shifted in with the clock pulses that are generated by the master device The slave device does not generate the clock but it can hold SCL low if intervention of the CPU is required after a byte has been recei
196. evice specific datasheet USARTO transmit enable This bit enables the transmitter for USARTO 0 Module not enabled 1 Module enabled USARTO receive enable This bit enables the receiver for USARTO 0 Module not enabled 1 Module enabled USART Peripheral Interface UART Mode 13 27 USART Registers UART Mode IE1 Interrupt Enable Register 1 7 6 5 4 3 2 1 0 eese qp EE rw 0 rw 0 UTXIEOT Bit 7 USARTO transmit interrupt enable This bit enables the UTXIFGO interrupt 0 Interrupt not enabled 1 Interrupt enabled URXIEOT Bit 6 USARTO receive interrupt enable This bit enables the URXIFGO interrupt 0 Interrupt not enabled 1 Interrupt enabled Bits These bits may be used by other modules See device specific datasheet 5 0 T Does not apply to MSP430x12xx devices See IE2 for the MSP430x12xx USARTO interrupt enable bits IE2 Interrupt Enable Register 2 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 Bits These bits may be used by other modules See device specific datasheet 7 6 UTXIE1 Bit 5 USART1 transmit interrupt enable This bit enables the UTXIFG1 interrupt 0 Interrupt not enabled 1 Interrupt enabled URXIE1 Bit 4 USART1 receive interrupt enable This bit enables the URXIFG1 interrupt 0 Interrupt not enabled 1 Interrupt enabled Bits These bits may be used by other modules See device specific datasheet 3 2 UTXIEOt Bit 1 USARTO transmit interrupt enable This bit enables the UTXIFGO interrupt 0 Interrupt not enabled 1 Interrupt enable
197. flow User software must detect and handle these conditions appropriately Hardware Multiplier Hardware Multiplier Operation 7 2 8 Software Examples Examples for all multiplier modes follow All 8x8 modes use the absolute address for the registers because the assembler will not allow B access to word registers when using the labels from the standard definitions file 16x16 Unsigned Multiply MOV 01234h amp MPY Load first operand MOV 405678h amp OP2 Load second operand Process results 8x8 Unsigned Multiply Absolute addressing MOV B 012h amp 0130h Load first operand MOV B 034h amp 0138h Load 2nd operand AE Process results 16x16 Signed Multiply MOV 01234h amp MPYS Load first operand MOV 405678h amp OP2 Load 2nd operand TE Process results 8x8 Signed Multiply Absolute addressing MOV B 012h amp 0132h Load first operand SXT amp MPYS Sign extend first operand MOV B 034h amp 0138h Load 2nd operand SXT amp OP2 Sign extend 2nd operand triggers 2nd multiplication aas Process results 16x16 Unsigned Multiply Accumulate MOV 01234h amp MAC Load first operand MOV 405678h amp OP2 Load 2nd operand ages Process results 8x8 Unsigned Multiply Accumulate Absolute addressing MOV B 012h amp 0134h Load first operand MOV B 034h amp 0138h Load 2nd operand Process results 16x16 Signed Multiply Accumulate MOV 01234h am
198. fter Return From Interrupt Interrupt Nesting Interrupt nesting is enabled if the GIE bit is set inside an interrupt service routine When interrupt nesting is enabled any interrupt occurring during an interrupt service routine will interrupt the routine regardless of the interrupt priorities 2 12 System Resets Interrupts and Operating Modes System Reset and Initialization 2 2 4 Interrupt Vectors The interrupt vectors and the power up starting address are located in the address range OFFFFh OFFEOh as described in Table 2 1 A vector is programmed by the user with the 16 bit address of the corresponding interrupt service routine See the device specific data sheet for the complete interrupt vector list Table 2 1 Interrupt Sources Flags and Vectors INTERRUPT SYSTEM WORD INTERRUPT SOURCE FLAG INTERRUPT ADDRESS PRIORITY Power up external reset watchdog ee Reset OFFFEh 15 highest flash password NMI oscillator fault NMIIFG non maskable flash memory access OFIFG non maskable OFFFCh 14 violation ACCVIFG non maskable device specific OFFFAh 13 device specific OFFF8h 12 device specific OFFF6h 11 Watchdog timer WDTIFG maskable OFFF4h 10 device specific OFFF2h 9 device specific OFFFOh 8 device specific OFFEEh 7 device specific OFFECh 6 device specific OFFEAh 5 device specific OFFE8h 4 device specific OFFE6h 3 device specific OFFE4h 2 device specific OFFE2h 1 device specific OFFEOh 0 lowest Some modu
199. g edge of UCLK input data is latched with the falling edge of UCLK 1 The inactive level is high data is output with the falling edge of UCLK input data is latched with the rising edge of UCLK Source select These bits select the BRCLK source clock 00 External UCLK valid for slave mode only 01 ACLK valid for master mode only 10 SMCLK valid for master mode only 11 SMCLK valid for master mode only Unused Unused Slave transmit control 0 4 pin SPI mode STE enabled 1 3 pin SPI mode STE disabled Transmitter empty flag The TXEPT flag is not used in slave mode 0 Transmission active and or data waiting in UXTXBUF 1 UxTXBUF and TX shift register are empty USART Peripheral Interface SPI Mode 14 15 USART Registers SPI Mode UxRCTL USART Receive Control Register 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 FE Bit 7 Framing error flag This bit indicates a bus conflict when MM 1 and STC 0 FE is unused in slave mode 0 No conflict detected 1 A negative edge occurred on STE indicating bus conflict Undefined Bit6 Unused OE Bit 5 Overrun error flag This bit is set when a character is transferred into UxRXBUF before the previous character was read OE is automatically reset when UxRXBUF is read when SWRST 1 or can be reset by software 0 No error 1 Overrun error occurred Unused Bit 4 Unused Unused Bit 3 Unused Unused Bit 2 Unused Unused Bit 1 Unused Unused Bit 0 Unused 14 16 USART
200. g safeguards TI does not warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right relating to any combination machine or process in which TI components or services are used Information published by TI regarding third party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices TI is not responsible or liable for such altered documentation Information of third parties may be subject to additional restrictions Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice Tl is not responsible or liable for any such statements Buyer acknowledges and agrees that it is solely responsible for compliance with all legal regulatory and safety
201. g the WDTTMSEL bit to 1 selects the interval timer mode This mode can be used to provide periodic interrupts In interval timer mode the WDTIFG flag is set at the expiration of the selected time interval A PUC is not generated in interval timer mode at expiration of the selected timer interval and the WDTIFG enable bit WDTIE remains unchanged When the WDTIE bit and the GIE bit are set the WDTIFG flag requests an interrupt The WDTIFG interrupt flag is automatically reset when its interrupt request is serviced or may be reset by software The interrupt vector address in interval timer mode is different from that in watchdog mode p BB B BB B BB mm iii rrt1l Note Modifying the Watchdog Timer The WDT interval should be changed together with WDTCNTCL 1 ina single instruction to avoid an unexpected immediate PUC or interrupt The WDT should be halted before changing the clock source to avoid a possible incorrect interval p I 1 Watchdog Timer Watchdog Timer Operation 10 2 4 Watchdog Timer Interrupts The WDT uses two bits in the SFRs for interrupt control J The WDT interrupt flag WDTIFG located in IFG1 0 J The WDT interrupt enable WDTIE located in IE1 0 When using the WDT in the watchdog mode the WDTIFG f
202. gative JZ R7ZERO Low byte of R7 is zero R7POS J Low byte of R7 is positive but not zero R7NEG Low byte of R7 is negative R7ZERO Low byte of R7 is zero 3 70 RISC 16 Bit CPU XOR W XOR B Syntax Operation Description Status Bits Mode Bits Example Example Example Instruction Set Exclusive OR of source with destination Exclusive OR of source with destination XOR src dst or XOR W src dst XOR B src dst src XOR dst dst The source and destination operands are exclusive ORed The result is placed into the destination The source operand is not affected N Set if result MSB is set reset if not set Z Set if result is zero reset otherwise C Set if result is not zero reset otherwise NOT Zero V Set if both operands are negative OSCOFF CPUOFF and GIE are not affected The bits set in R6 toggle the bits in the RAM word TONI XOR R6 TONI Toggle bits of word TONI on the bits set in R6 The bits set in R6 toggle the bits in the RAM byte TONI XOR B R6 TONI Toggle bits of byte TONI on the bits set in low byte of R6 Reset to 0 those bits in low byte of R7 that are different from bits in RAM byte EDE XOR B EDE7 Set different bit to 1s INV B R7 Invert Lowbyte Highbyte is Oh RISC 16 Bit CPU 3 71 Instruction Set 3 4 4 Instruction Cycles and Lengths The number of CPU clock cycles required for an instruction depends on the instruction format and
203. ger a transfer A transfer is triggered when the URXIFG1 flag is set URXIFG1 is automatically reset when the transfer starts If URXIE1 is set the URXIFG1 flag will not trigger a transfer A transfer is triggered when the UTXIFG1 flag is set UTXIFG1 is automatically reset when the transfer starts If UTXIE1 is set the UTXIFG1 flag will not trigger a transfer A transfer is triggered when the hardware multiplier is ready for a new operand No transfer is triggered No transfer is triggered A transfer is triggered when the DMAxIFG flag is set DMAOIFG triggers channel 1 DMA1IFG triggers channel 2 and DMA2IFG triggers channel 0 None of the DMAxIFG flags are automatically reset when the transfer starts A transfer is triggered by the external trigger DMAEO DMA Controller 8 13 DMA Operation 8 2 4 Stopping DMA Transfers There are two ways to stop DMA transfers in progress _j A single block or burst block transfer may be stopped with an NMI interrupt if the ENNMI bit is set in register DMACTL1 A burst block transfer may be stopped by clearing the DMAEN bit 8 2 5 DMA Channel Priorities The default DMA channel priorities are DMA0 DMA1 DMAQA If two or three triggers happen simultaneously or are pending the channel with the highest priority completes its transfer single block or burst block transfer first then the second priority channel then the third priority channel Transfers in progress are not halted if a
204. gnated is solely at the Buyer s risk and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use TI has specifically designated certain components as meeting ISO TS16949 requirements mainly for automotive use In any case of use of non designated products TI will not be responsible for any failure to meet ISO TS16949 Products Applications Audio www ti com audio Automotive and Transportation www ti com automotive Amplifiers amplifier ti com Communications and Telecom www ti com communications Data Converters DLP Products DSP Clocks and Timers Interface Logic Power Mgmt Microcontrollers RFID OMAP Applications Processors Wireless Connectivity dataconverter ti com www dlp com www ti com clocks interface ti com logic ti com microcontroller ti com www ti rfid com www ti com omap Computers and Peripherals Consumer Electronics Energy and Lighting Industrial Medical Security Space Avionics and Defense Video and Imaging TI E2E Community www ti com wirelessconnectivity www ti com computers www ti com consumer apps www ti com energy www ti com industrial www ti com medical www ti com security www ti com space avionics defense www ti com video Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2015 Texas Instruments Incorporated
205. h bit the cumulative bit error is reduced The individual bit error can be calculated by Error E x o 1 x UxBR m j x 100 With baud rate Desired baud rate BRCLK Input frequency UCLKI ACLK or SMCLK J Bit position 0 for the start bit 1 for data bit DO and so on UxBR Division factor in registers UxBR1 and UxBRO For example the transmit errors for the following conditions are calculated Baud rate 2400 BRCLK 32 768 Hz ACLK UxBR 13 since the ideal division factor is 13 65 UxMCTL 6Bh m7 0 m6 1 m5 1 m4z0 m3 1 m2 0 m1 1 and mO 1 The LSB of UxMCTL is used first Start bit Error gs x 0 1 x UxBR 1 1 x 100 2 54 Data bit DO Error audiate x 1 1 x UxBR 2 2 x 100 5 08 baud rate a BRCLK X 2 1 x UxBR 2 3 x 100 0 29 baud rate BRCLK S 1 x UxBR 3 4 Data bit D1 Error Data bit D2 Error x 100 2 83 Data bit D3 Error Paua rate x 4 1 x UxBR 3 5 x 100 1 95 Data bit D4 Error BRCLK Data bit D5 Error Paudrate y t6 1 x UxBR 5 7 x 100 3 13 BRCLK baud rate y 7 4 x UxBR 5 8 x 100 1 66 Data bit D6 Error BRCLK baud rate 6 1 x UxBR 4 e x 100 0 59 x 100 0 88 Data bit D7 Error Pud rate x 8 1 x UxBR 6 9 BRCLK Stop bit 1 Error Paud ale x 10 1 x UxBR 7 11 x 100 1
206. h positive signs The source operand and the carry bit C are added decimally to the destination operand The source operand is not affected The previous contents of the destination are lost The result is not defined for non BCD numbers N Setif the MSB is 1 reset otherwise Z Setif result is zero reset otherwise C Setif the result is greater than 9999 Set if the result is greater than 99 V Undefined OSCOFF CPUOFF and GIE are not affected The eight digit BCD number contained in R5 and R6 is added decimally to an eight digit BCD number contained in R3 and R4 R6 and R4 contain the MSDs CLRC clear carry DADD R5 R3 add LSDs DADD R6 R4 add MSDs with carry JC OVERFLOW If carry occurs go to error handling routine The two digit decimal counter in the RAM byte CNT is incremented by one CLRC clear carry DADD B 1 CNT increment decimal counter or SETC DADD B 0 CNT DADC B CNT 3 36 RISC 16 Bit CPU DEC W DEC B Syntax Operation Emulation Emulation Description Status Bits Mode Bits Example Instruction Set Decrement destination Decrement destination DEC dst or DEC W dst DEC B dst dst 1 dst SUB 1 dst SUB B 1 dst The destination operand is decremented by one The original contents are lost N Set if result is negative reset if positive Z Set if dst contained 1 reset otherwise C Reset if dst contained 0 set otherwise V Set if an arithmetic o
207. h programmable sample periods Conversion initiation by software or Timer_A Software selectable on chip reference voltage generation 1 5 V or 2 5 V Software selectable internal or external reference Eight external input channels Conversion channels for internal temperature sensor Vcc and external references Selectable conversion clock source Single channel repeated single channel sequence and repeated sequence conversion modes ADC core and reference voltage can be powered down separately Data transfer controller for automatic storage of conversion results The block diagram of ADC10 is shown in Figure 18 1 ADC10 Introduction Figure 18 1 ADC 10 Block Diagram REFOUT REFBURST T VeREF ADC10SR REF2_5V REFON hd INCHx 0Ah V on a 1 5 Vor 2 5 V Vcc Reference VREFL Vengr Ref_x Vcc SREF1 CONSEQx ygg 11 10 01 00 SREFO nem A0 SREF2 1 o ADC100N ADC10SSELx A1 A2 ADC10DIVx A3 V V Od AS i 01 ACLK A5 Divider A7 11 SMCLK convent gt ADC10CLK SHSx BUSY ISSH ENC a 00 ADC10SC a bad siei Sample Timer a TA 1418 16 64 10 TAO a 11 TA2 ADC10DF ADC10SHTx MSC INCHx 0Bh ADC10MEM Ref x y A Data Transfer mE Controller H RAM Flash Peripherials ADC10SA Halt CPU Vss ADC10CT ADC10TB ADC10B1 ADC10 18 3 ADC10 Operation 18 2 ADC10 Operation The ADC10 module is configured wit
208. h user software The setup and operation of the ADC10 is discussed in the following sections 18 2 1 10 Bit ADC Core The ADC core converts an analog input to its 10 bit digital representation and stores the result in the ADC10MEM register The core uses two programmable selectable voltage levels VR and Vp to define the upper and lower limits of the conversion The digital output Napc is full scale O3FFh when the input signal is equal to or higher than Vr and zero when the input signal is equal to or lower than Vp_ The input channel and the reference voltage levels VR and Vg are defined in the conversion control memory Conversion results may be in straight binary format or 2s complement format The conversion formula for the ADC result when using straight binary format is Vin V V R N R T VR Apc 1023 x The ADC10 core is configured by two control registers ADC10CTLO and ADC10CTL1 The core is enabled with the ADC10ON bit With few exceptions the ADC10 control bits can only be modified when ENC 0 ENC must be set to 1 before any conversion can take place Conversion Clock Selection 18 4 ADC10 The ADC10CLK is used both as the conversion clock and to generate the sampling period The ADC10 source clock is selected using the ADC10SSELx bits and can be divided from 1 8 using the ADC10DIVx bits Possible ADC10CLK sources are SMCLK MCLK ACLK and an internal oscillator ADC100OSC The ADC10OSC generate
209. hannel Defined in i ENC ot ADC12MCTLx x SAMPCON Y Si 12 x ADC12CLK EN ENC ot 1 x ADC12CLK Conversion N Completed xN Result Stored Into ADC12MEMXx ADC12IFG x is Set x pointer to ADC12MCTLx tConversion result is unpredictable ADC 12 Operation Sequence of Channels Mode A sequence of channels is sampled and converted once The ADC results are written to the conversion memories starting with the ADCMEMXx defined by the CSTARTADDx bits The sequence stops after the measurement of the channel with a set EOS bit Figure 17 7 shows the sequence of channels mode When ADC12SC triggers a sequence successive sequences can be triggered by the ADC12SC bit When any other trigger source is used ENC must be toggled between each sequence Figure 17 7 Sequence of Channels Mode CONSEQx 01 ADC120N 1 ENC 4 x CSTARTADDx Wait for Enable SHSx 0 and ENC 10r and ADC12SC Wait for Trigger SAMPCON 4 EOS x 1 SAMPCON 1 Sample Input Channel Defined in ADC12MCTLx Ifx lt 15thenx x 1 else x 0 SAMPCON Y MSC 1 and SHP 1 and EOS x 0 Ifx lt 15thenx x 1 else x 0 12 x ADC12CLK 1 x ADC12CLK Conversion Completed Result Stored Into ADC12MEMXx ADCA2IFG x is Set X pointer to ADC12MCTLx 17 12 ADC12 ADC 12 Operation Repeat Single Channel Mode A single channel is sampled and converted continuou
210. he total number of transfers for a block The block start address is defined anywhere in the MSP430 address range using the 16 bit register ADC10SA The block ends at ADC10SA 2n 2 The one block transfer mode is shown in Figure 18 9 Figure 18 9 One Block Transfer 18 16 ADC10 TB 0 n th transfer ADC10SA 2n 2 ADC10SA 2n 4 In 2nd transfer ADC10SA 2 1st transfer ADC10SA The internal address pointer is initially equal to ADC10SA and the internal transfer counter is initially equal to n The internal pointer and counter are not visible to software The DTC transfers the word value of ADC10MEM to the address pointer ADC10SA After each DTC transfer the internal address pointer is incremented by two and the internal transfer counter is decremented by one The DTC transfers continue with each loading of ADC10MEM until the internal transfer counter becomes equal to zero No additional DTC transfers will occur until a write to ADC10SA When using the DTC in the one block mode the ADC1OIFG flag is set only after a complete block has been transferred Figure 18 10 shows a state diagram of the one block mode ADC10 Operation Figure 18 10 State Diagram for Data Transfer Control in One Block Transfer Mode Write to ADC10SA or n 0 Write to ADC10MEM completed Write to ADC10SA Write to ADC10SA Transfer data to Address AD AD AD 2 I c 1x MCLK cycle n 0 Wait for wr
211. higher priority channel is triggered The higher priority channel waits until the transfer in progress completes before starting The DMA channel priorities are configurable with the ROUNDROBIN bit When the ROUNDROBIN bit is set the channel that completes a transfer becomes the lowest priority The order of the priority of the channels always stays the same DMA0 DMA1 DMA2 for example DMA Priority Transfer Occurs New DMA Priority DMAO DMA1 DMA2 DMA1 DMA2 DMAO DMA1 DMA2 DMAO DMA1 DMA2 DMAO DMA1 DMA2 DMAO DMA1 DMA2 DMAO DMA1 DMA2 DMAO When the ROUNDROBIN bit is cleared the channel priority returns to the default priority 8 14 DMA Controller DMA Operation 8 2 6 DMA Transfer Cycle Time The DMA controller requires one or two MCLK clock cycles to synchronize before each single transfer or complete block or burst block transfer Each byte word transfer requires two MCLK cycles after synchronization and one cycle of wait time after the transfer Because the DMA controller uses MCLK the DMA cycle time is dependent on the MSP430 operating mode and clock system setup If the MCLK source is active but the CPU is off the DMA controller will use the MCLK source for each transfer without re enabling the CPU If the MCLK source is off the DMA controller will temporarily restart MCLK sourced with DCOCLK for the single transfer or complete block or burst block transfer The CPU remains off and after the transfer com
212. his bit when set turns off the SMCLK System clock generator 0 This bit when set turns off the DCO dc generator if DCOCLK is not used for MCLK or SMCLK Oscillator Off This bit when set turns off the LFXT1 crystal oscillator when LFXT1CLK is not use for MCLK or SMCLK CPU off This bit when set turns off the CPU General interrupt enable This bit when set enables maskable interrupts When reset all maskable interrupts are disabled Negative bit This bit is set when the result of a byte or word operation is negative and cleared when the result is not negative Word operation N is set to the value of bit 15 of the result N is set to the value of bit 7 of the result Byte operation Zero bit This bit is set when the result of a byte or word operation is 0 and cleared when the result is not 0 Carry bit This bit is set when the result of a byte or word operation produced a carry and cleared when no carry occurred 3 2 4 Constant Generator Registers CG1 and CG2 CPU Registers Six commonly used constants are generated with the constant generator registers R2 and R3 without requiring an additional 16 bit word of program code The constants are selected with the source register addressing modes As as described in Table 3 2 Table 3 2 Values of Constant Generators CG1 CG2 Register R2 R2 R2 R2 R3 R3 R3 R3 The constant generator advantages are As 00 01 10 11 00 01 10 11 Constant 0
213. hout CPU intervention across the entire address range For example the DMA controller can move data from the ADC12 conversion memory to RAM Using the DMA controller can increase the throughput of peripheral modules It can also reduce system power consumption by allowing the CPU to remain in a low power mode without having to awaken to move data to or from a peripheral The DMA controller features include Three independent transfer channels Configurable DMA channel priorities Requires only two MCLK clock cycles Byte or word and mixed byte word transfer capability Block sizes up to 65535 bytes or words Configurable transfer trigger selections Selectable edge or level triggered transfer Four addressing modes D COUDLUDUDODLDZCLDoL Single block or burst block transfer modes The DMA controller block diagram is shown in Figure 8 1 8 2 DMA Controller Figure 8 1 DMA Controller Block Diagram DMAOTSELx DMAREQ TACCR2_CCIFG TBCCR2_CCIFG USARTO data received USARTO transmit ready DAC12_0IFG ADC12IFGx TACCRO CCIFG TBCCRO CCIFG USART1 data received USART1 transmit ready Multiplier ready No trigger No trigger DMA2IFG DMAEO DMAREQ TACCR2 CCIFG TBCCR2 CCIFG USARTO data received USARTO transmit ready DAC12 OIFG ADC12IFGx TACCRO CCIFG TBCCRO CCIFG USART1 data received USART1 transmit ready Multiplier ready No trigger No trigger DMAOIFG DMAEO DMAREQ TACCR2 CCIFG TBCCR2 CCIFG USARTO data
214. ibed for the below conditions Master transmitter I2CRM 0 All data sent Master transmitter I2CRM 1 All data sent and I2CSTP set Master receiver I2CRM 0 I2CNDAT number of bytes received and all data read from I2CDR Master receiver I2CRM 1 Last byte of data received I2CSTP set and all data read from I2CDR Slave transmitter STOP condition detected Slave receiver STOP condition detected and all data read from I2CDR RXRDYIFG Receive ready interrupt status This flag is set when the I2C module has received new data RXRDYIFG is automatically cleared when I2CDR is read and the receive buffer is empty A receiver overrun is indicated if bit ICRXOVR 1 RXRDYIFG is used in receive mode only TXRDYIFG Transmit ready interrupt status This flag is set when the I2C module is ready for new transmit data master transmit mode or when another master is requesting data slave transmit mode TXRDYIFG is automatically cleared when I2CDR and the transmit buffer are full A transmit underflow is indicated if IICTXUDF 1 Unused in receive mode GCIFG General call interrupt This flag is set when the I2C module received the general call address 00h GCIFG is used in receive mode only STTIFG START condition detected interrupt This flag is set when the 12C module detects a START condition while in slave mode This allows the MSP430 to be in a low power mode with the IC clock source inactive until a master initiates 12C commu
215. igure 15 13 V7 Il Note I2CCLK Maximum Frequency I2CIN must be at least 10x the SCL frequency x the I2CPSC divider rate in both master and slave modes For example with an I2CPSC value of 02h I2CIN must be 3 kHz x 3 x 10 or 90 Khz for a 3 kHz SCL LLLLLLL ELLE OCA AGcs 7T Note I2CPSC Value When I2CPSC gt 4 unpredictable operation can result The I2CSCLL and I2CSCLH registers should be used to set the SCL frequency LLLLA e 12C Module SCL Generation TUUUULVUUUULUUUUUUU L cesc LI LI LANT LT WLS LT LT L I2CCLK o ee M oc IBCPSC 1 x IPCSCLH 2 IPCPSC 1 x IPCSCLL 2 During the arbitration procedure the clocks from the different masters must be synchronized A device that first generates a low period on SCL overrules the other devices forcing them to start their own low periods SCL is then held low by the device with the longest low period The other devices must wait for SCL to be released before starting their high periods Figure 15 14 illustrates the clock synchronization This allows a slow slave to slow down a fast master Figure 15 14 Synchronization of Two I2C Clock Generators During Arbitration 15 16 SCL From Device 1 SCL From Device 2 Bus Line SCL Wait K Start HIGH State Period
216. imer A 11 2 5 Output Unit Timer_A Operation Each capture compare block contains an output unit The output unit is used to generate output signals such as PWM signals Each output unit has eight operating modes that generate signals based on the EQUO and EQUXx signals Output Modes The output modes are defined by the OUTMODx bits and are described in Table 11 2 The OUTx signal is changed with the rising edge of the timer clock for all modes except mode 0 Output modes 2 3 6 and 7 are not useful for output unit 0 because EQUx EQUO Table 11 2 Output Modes OUTMODx 000 001 010 011 100 101 110 111 Mode Output Set Toggle Reset Set Reset Toggle Reset Toggle Set Reset Set Description The output signal OUTx is defined by the OUTx bit The OUTx signal updates immediately when OUTx is updated The output is set when the timer counts to the TACCRx value It remains set until a reset of the timer or until another output mode is selected and affects the output The output is toggled when the timer counts to the TACCRx value It is reset when the timer counts to the TACCRO value The output is set when the timer counts to the TACCRx value It is reset when the timer counts to the TACCRO value The output is toggled when the timer counts to the TACCRx value The output period is double the timer period The output is reset when the timer counts to the TACCRx value It remain
217. in Figure 12 12 using TBCLO and TBCL1 Figure 12 12 Output Example Timer in Up Mode TBR max TBCLO TBCL1 Output Mode 1 Set Output Mode 2 Toggle Reset Output Mode 3 Set Reset Output Mode 4 Toggle Output Mode 5 Reset Output Mode 6 Toggle Set Output Mode 7 Reset Set EQUO EQUi EQUO EQUI EQUO Interrupt Events TBIFG TBIFG TBIFG P Timer_B 12 15 Timer_B Operation Output Example Timer in Continuous Mode The OUTx signal is changed when the timer reaches the TBCLx and TBCLO values depending on the output mode An example is shown in Figure 12 13 using TBCLO and TBCL1 Figure 12 13 Output Example Timer in Continuous Mode TBR max TBCLO TBCL1 Oh TBIFG EQU1 EQUO TBIFG EQU1 EQUO Interrupt Events 12 16 Timer_B Timer_B Operation Output Example Timer in Up Down Mode The OUTx signal changes when the timer equals TBCLx in either count direction and when the timer equals TBCLO depending on the output mode An example is shown in Figure 12 14 using TBCLO and TBCL3 Figure 12 14 Output Example Timer in Up Down Mode TBR max TBCLO TBCL3 TBIFG EQU3 EQUO TBIFG EQUO Output Mode 1 Set Output Mode 2 Toggle Reset Output Mode 3 Set Reset Output Mode 4 Toggle Output Mode 5 Reset Output Mode 6 Toggle Set Output Mode 7 Reset Set EQUS FQUS FQUS Interrupt Events p TT Not
218. ination Push source onto stack Return from subroutine Return from interrupt Rotate left arithmetically Rotate left through C Rotate right arithmetically Rotate right through C Subtract not C from destination Set C Set N Set Z Subtract source from destination Subtract source and not C from dst Swap bytes Extend sign Test destination Exclusive OR source and destination dst C gt dst src dst 5 dst src dst C gt dst src and dst dst not src and dst dst src or dst dst src and dst dst PC PC 2 stack dst PC 0 2 dst 02C 0 gt N 02Z dst src dst C dst decimally src dst C 5 dst decimally dst 1 dst dst 2 gt dst 0 GIE 1o GIE dst 1 dst dst 2 dst not dst dst PC 2 x offset 2 PC src gt dst SP dst SP 2 5 SP SP 2 gt SP src 2 SP SP PC SP 2 gt SP dst OFFFFh C dst 12C 1 gt N 12C dst not src 1 gt dst dst not src C dst dst OFFFFh 1 src xor dst dst Oo o Instruction Set N Z c x x 0 0 0 e a 4 1 E 1 E 1 RISC 16 Bit CPU 3 75 Chapter 4 Basic Clock Module The basic clock module provides the clocks for MSP430x1 xx devices This chapter describes the operation of
219. ing TXRDYIFG with software will not trigger a transfer If TXRDYIE is set the transmit ready condition will not trigger a transfer In UART or SPI mode a transfer is triggered when the UTXIFGO flag is set UTXIFGO is automatically reset when the transfer starts If UTXIEO is set the UTXIFGO flag will not trigger a transfer A transfer is triggered when the DAC12 OCTL DAC12IFG flag is set The DAC12 OCTL DAC12IFG flag is automatically cleared when the transfer starts If the DAC12 OCTL DAC12lE bit is set the DAC12 OCTL DAC12IFG flag will not trigger a transfer A transfer is triggered by an ADC12IFGx flag When single channel conversions are performed the corresponding ADC12IFGx is the trigger When sequences are used the ADC12IFGx for the last conversion in the sequence is the trigger A transfer is triggered when the conversion is completed and the ADC12IFGx is set Setting the ADC12IFGx with software will not trigger a transfer All ADC121FGx flags are automatically reset when the associated ADC12MEMXx register is accessed by the DMA controller A transfer is triggered when the TACCRO CCIFG flag is set The TACCRO CCIFG flag is automatically reset when the transfer starts If the TACCRO CCIE bit is set the TACCRO CCIFG flag will not trigger a transfer A transfer is triggered when the TBCCRO CCIFG flag is set The TBCCRO CCIFG flag is automatically reset when the transfer starts If the TBCCRO CCIE bit is set the TBCCRO CCIFG flag will not trig
220. intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice TI is not responsible or liable for such altered documentation Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice TI is not responsible or liable for any such statements Following are URLs where you can obtain information on other Texas Instruments products and application solutions Products Applications Amplifiers amplifier ti com Audio www ti com audio Data Converters dataconverter ti com Automotive www ti com automotive DSP dsp ti com
221. internal reference is 2 5 V the reference is 1 5 V when REF2_5V 0 The reference can be turned off to save power when not in use For proper operation the internal voltage reference generator must be supplied with storage capacitance across Vref and Ayss The recommended storage capacitance is a parallel combination of 10 uF and 0 1 uF capacitors From turn on a minimum of 17 ms must be allowed for the voltage reference generator to bias the recommended storage capacitors If the internal reference generator is not used for the conversion the storage capacitors are not required Note Reference Decoupling Approximately 200 uA is required from any reference used by the ADC12 while the two LSBs are being resolved during a conversion A parallel combination of 10 uF and 0 1 uF capacitors is recommended for any reference used as shown in Figure 17 11 LLLLLLL External references may be supplied for VR and Vg through pins Verner and Vner Vener respectively 17 2 4 Auto Power Down 17 6 ADC12 The ADC12 is designed for low power applications When the ADC12 is not actively converting the core is automatically disabled and automatically re enabled when needed The ADC12OSC is also automatically enabled when needed and disabled when not needed The refe
222. ion and address detection L L L L Independent interrupt capability for receive and transmit Figure 13 1 shows the USART when configured for UART mode USART Peripheral Interface UART Mode USART Introduction UART Mode Figure 13 1 USART Block Diagram UART Mode SWRST URXEx URXEIE URXWIE FE PE OE BRK Receive Control Receive Status Receiver Buffer UxRXBUF RXERR RXWAKE Receiver Shift Register SSELO SP CHAR Baud Rate Generator Prescaler Dvider UxBPx UxBRx Modulator UXMCTL SP CHAR SYNC 0 LISTEN MM SYNC SSEL1 UCLKS eo OO PEV PENA Transmit Shift Register Transmit Buffer UXTXBUF Transmit Control SWRST UTXEx TXEPT STC iir uo Clock Phase and Polarity Refer to the device specific datasheet for SFR locations gt Ql SIMO TXWAKE UTXIFGx SYNC CKPH CKPL USART Peripheral Interface UART Mode 13 3 USART Operation UART Mode 13 2 USART Operation UART Mode In UART mode the USART transmits and receives characters at a bit rate asynchronous to another device Timing for each character is based on the selected baud rate of the USART The transmit and receive functions use the same baud rate frequency 13 2 1 USART Initialization and Reset The USART is reset by a PUC or by setting the SWRST bit After a PUC the SWRST bit is automatically set keeping the USART in a reset condition When set the SWRST bit r
223. ions There is no difference in the operation of the main and information memory sections Code or data can be located in either section The differences between the two sections are the segment size and the physical addresses The information memory has two 128 byte segments MSP430F 1101 devices have only one The main memory has two or more 512 byte segments See the device specific datasheet for the complete memory map of a device The segments are further divided into blocks A block is 64 bytes starting at 0xx00h Oxx40h 0xx80h or OxxCOh and ending at Oxx3Fh Oxx7Fh OxxBFh or OxxFFh Figure 5 2 shows the flash segmentation using an example of 4 KB flash that has eight main segments and both information segments Figure 5 2 Flash Memory Segments 4 KB Example FFFFh F000h 10FFh 1000h 4 KB 256 byte 4 kbyte Flash Main Memory 256 byte Flash Information Memory xxFFh xxBFh xx7Fh xx3Fh SegmentA SegmentB Flash Memory Controller 5 3 Flash Memory Operation 5 3 Flash Memory Operation The default mode of the flash memory is read mode In read mode the flash memory is not being erased or written the flash timing generator and voltage generator are off and the memory operates identically to ROM MSP430 flash memory is in system programmable ISP without the need for additional external voltage The CPU can program its own flash memory The flash memory write erase modes are selected wi
224. isters Selectable UCLK polarity and phase control Programmable UCLK frequency in master mode oo L L L L Independent interrupt capability for receive and transmit Figure 14 1 shows the USART when configured for SPI mode 14 2 USART Peripheral Interface SPI Mode USART Introduction SPI Mode Figure 14 1 USART Block Diagram SPI Mode SWRST USPIEx URXEIE URXWIE Receive Control SYNC 1 URXIFGx FE PE OE BRK LISTEN RXERR RXWAKE PENA 1 URXD SSEL1 SSELO SP CHAR UCLKS i UCLKI Baud Rate Generator 0 C STE ak ex SMCLK Prescaler Dvider UxaR UxBRx SMCLK Modulator UxMCTL T SP CHAR Transmit Shift Register Transmit Buffer UXTXBUF Transmit Control SWRST USPIEx TXEPT STC ii ds Clock Phase and Polarity Refer to the device specific datasheet for SFR locations PEV PENA TXWAKE UTXIFGx SYNC CKPH CKPL USART Peripheral Interface SPI Mode 14 3 USART Operation SPI Mode 14 2 USART Operation SPI Mode In SPI mode serial data is transmitted and received by multiple devices using a shared clock provided by the master An additional pin STE is provided as to enable a device to receive and transmit data and is controlled by the master Three or four signals are used for SPI data exchange J SIMO Slave in master out Master mode SIMO is the data output line Slave mode SIMO is the data input line
225. ite to ADC10SA Initialize Write to ADC10SA nis latched in counter x Wait until ADC10MEM is written Synchronize with MCLK x gt 0 n 0 ADC10DTC1 Start Address in ADC10SA ADC10TB 0 and ADC10CT 1 ADC10TB 0 and ADC10CT 0 DTC DTC operation ADC10 Prepare 18 17 ADC10 Operation Two Block Transfer Mode The two block mode is selected if the ADC10TB bit is set The value n in ADC10DTC1 defines the number of transfers for one block The address range of the first block is defined anywhere in the MSP430 address range with the 16 bit register ADC10SA The first block ends at ADC10SA 2n 2 The address range for the second block is defined as SA 2n to SA 4n 2 The two block transfer mode is shown in Figure 18 11 Figure 18 11 Two Block Transfer 18 18 ADC10 TB 1 2 x n th transfer ADC10SA 4n 2 ADC10SA 4n 4 DTC n th transfer ADC10SA 2n 2 ADC10SA 2n 4 2nd transfer ADC10SA 2 1st transfer ADC10SA The internal address pointer is initially equal to ADC10SA and the internal transfer counter is initially equal to n The internal pointer and counter are not visible to software The DTC transfers the word value of ADC10MEM to the address pointer ADC10SA After each DTC transfer the internal address pointer is incremented by two and the internal transfer counter is decremented by one The DTC transfers continue with each loading of ADC10MEM
226. ith the MCx bits Table 11 1 Timer Modes MCx Mode Description 00 Stop The timer is halted 01 Up The timer repeatedly counts from zero to the value of TACCRO 10 Continuous The timer repeatedly counts from zero to OFFFFh 11 Up down The timer repeatedly counts from zero up to the value of TACCRO and back down to zero Timer A 11 5 Timer_A Operation Up Mode The up mode is used if the timer period must be different from OFFFFh counts The timer repeatedly counts up to the value of compare register TACCRO which defines the period as shown in Figure 11 2 The number of timer counts in the period is TACCRO 1 When the timer value equals TACCRO the timer restarts counting from zero If up mode is selected when the timer value is greater than TACCRO the timer immediately restarts counting from zero Figure 11 2 Up Mode OFFFFh TACCRO Oh The TACCRO CCIFG interrupt flag is set when the timer counts to the TACCRO value The TAIFG interrupt flag is set when the timer counts from TACCRO to zero Figure 11 3 shows the flag set cycle Figure 11 3 Up Mode Flag Setting Timer Set TAIFG j l Set TACCRO CCIFG l j l j Changing the Period Register TACCRO 11 6 Timer A When changing TACCRO while the timer is running if the new period is greater than or equal to the old period or greater than the current count value the timer counts up to the new period If the new period is less than the current c
227. ki TEXAS INSTRUMENTS MSP430x1xx Family User s Guide 2006 Mixed Signal Products SLAUO49F IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using TI components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI
228. lag sources a reset vector interrupt The WDTIFG can be used by the reset interrupt service routine to determine if the watchdog caused the device to reset If the flag is set then the watchdog timer initiated the reset condition either by timing out or by a security key violation If WDTIFG is cleared the reset was caused by a different source When using the WDT in interval timer mode the WDTIFG flag is set after the selected time interval and requests a WDT interval timer interrupt if the WDTIE and the GIE bits are set The interval timer interrupt vector is different from the reset vector used in watchdog mode In interval timer mode the WDTIFG flag is reset automatically when the interrupt is serviced or can be reset with software Watchdog Timer 10 5 Watchdog Timer Operation 10 2 5 Operation in Low Power Modes The MSP430 devices have several low power modes Different clock signals are available in different low power modes The requirements of the user s application and the type of clocking used determine how the WDT should be configured For example the WDT should not be configured in watchdog mode with SMCLK as its clock source if the user wants to use low power mode 3 because SMCLK is not active in LPM3 and the WDT would not function When the watchdog timer is not required the WDTHOLD bit can be used to hold the WDTCNT reducing power consumption 10 2 6 Software Examples Any write operation to WDTCTL must be a word op
229. le Registers esses nnne 15 1 12C Module Introduction 15 1 12C Module Introduction The inter IC control 12C module provides an interface between the MSP430 and l2C compatible devices connected by way of the two wire 12C serial bus External components attached to the 12C bus serially transmit and or receive serial data to from the USART through the 2 wire 12C interface The 12C module has the following features Compliance to the Philips Semiconductor 12C specification v2 1 Byte word format transfer 7 bit and 10 bit device addressing modes General call START RESTART STOP Multi master transmitter slave receiver mode Multi master receiver slave transmitter mode Combined master transmit receive and receive transmit mode Standard mode up to100 kbps and fast mode up to 400 kbps support Built in FIFO for buffered read and write Programmable clock generation 16 bit wide data access to maximize bus throughput Automatic data byte counting Designed for low power Slave receiver START detection for auto wake up from LPMx modes Extensive interrupt capability L L LL L L Implemented on USARTO only The 12C block diagram is shown in Figure 15 1 15 2 USART Peripheral Interface 2C Mode 12C Module Introduction Figure 15 1 USART Block Diagram 12C Mode l2CSSELx I2CEN SYNC 1 I2CBUSY 2c 1j ACLK SMCLK PERAG I2CSCLLOW SMCLK o R W MST I2CTRX LISTEN I2CRXOV
230. le enable bits interrupt enable bits and interrupt flags are located in the SFRs The SFRs are located in the lower address range and are implemented in byte format SFRs must be accessed using byte instructions See the device specific datasheet for the SFR configuration System Resets Interrupts and Operating Modes 2 13 Operating Modes 2 3 Operating Modes The MSP430 family is designed for ultralow power applications and uses different operating modes shown in Figure 2 10 The operating modes take into account three different needs _j Ultralow power Speed and data throughput Minimization of individual peripheral current consumption The MSP430 typical current consumption is shown in Figure 2 9 Figure 2 9 Typical Current Consumption of 13x and 14x Devices vs Operating Modes 315 270 225 180 135 90 45 ICC uA 1 MHz AM LPMO LPM2 LPM3 LPM4 Operating Modes The low power modes 0 4 are configured with the CPUOFF OSCOFF SCGO and SCG1 bits in the status register The advantage of including the CPUOFF OSCOFF SCGO and SCG1 mode control bits in the status register is that the present operating mode is saved onto the stack during an interrupt service routine Program flow returns to the previous operating mode if the saved SR value is not altered during the interrupt service routine Program flow can be returned to a different operating mode by manipulating the saved SR value on the stack inside of the in
231. leared 12C Module Operation 15 2 5 The I C Data Register IZCDR The I2CDR register can be accessed as an 8 bit or 16 bit register selected by the I2CWORD bit The I2CDR register functions as described in Table 15 2 When I2CWORD 1 any attempt to modify the register with a byte instruction will fail and the register will not be modified Table 15 2 I2CDR Register Function Transmit Underflow Receive Overrun I2ZCWORD 2CTRX I2CDR Function 0 1 Byte mode transmit Only the low byte is used The byte is double buffered If a new byte is written before the previous byte has been transmitted the new byte is held in a temporary buffer before being latched into the I2CDR low byte TXRDYIFG is set when I2CDR is ready to be accessed I2CDR should be written after I2CSTT is set 0 0 Byte mode receive Only the low byte is used The byte is double buffered If a new byte is received before the previous byte has been read the new byte is held in a temporary buffer before being latched into the I2CDR low byte RXRDYIFG is set when I2CDR is ready to be read 1 1 Word mode transmit The low byte of the word is sent first then the high byte The register is double buffered If a new word is written before the previous word has been transmitted the new word is held in a temporary buffer before being latched into the I2CDR register TXRDYIFG is set when I2CDR is ready to be accessed I2CDR should be written after IZCSTT is set 1 0 Word m
232. lect the BRCLK source clock 00 UCLKI 01 ACLK 10 SMCLK 11 SMCLK UART receive start edge The bit enables the UART receive start edge feature 0 Disabled 1 Enabled Transmitter wake 0 Next character transmitted is data 1 Next character transmitted is an address Unused Transmitter empty flag 0 UART is transmitting data and or data is waiting in UxTXBUF 1 Transmitter shift register and UxTXBUF are empty or SWRST 1 USART Peripheral Interface UART Mode 13 23 USART Registers UART Mode UxRCTL USART Receive Control Register 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 FE Bit 7 Framing error flag 0 No error 1 Character received with low stop bit PE Bit 6 Parity error flag When PENA 0 PE is read as 0 0 No error 1 Character received with parity error OE Bit 5 Overrun error flag This bit is set when a character is transferred into UxRXBUF before the previous character was read 0 No error 1 Overrun error occurred BRK Bit 4 Break detect flag 0 No break condition 1 Break condition occurred URXEIE Bit 3 Receive erroneous character interrupt enable 0 Erroneous characters rejected and URXIFGx is not set 1 Erroneous characters received will set URXIFGx URXWIE Bit 2 Receive wake up interrupt enable This bit enables URXIFGx to be set when an address character is received When URXEIE 0 an address character will not set URXIFGx if it is received with errors 0 All received characters set URXIFGx 1 On
233. led and added to the program counter PCnew PColg 2 PCoffset x 2 3 20 RISC 16 Bit CPU ADC W ADC B Syntax Operation Emulation Description Status Bits Mode Bits Example Example Instruction Set Add carry to destination Add carry to destination ADC dst or ADC W dst ADC B dst dst C dst ADDC 0 dst ADDC B 0 dst The carry bit C is added to the destination operand The previous contents of the destination are lost N Set if result is negative reset if positive Z Set if result is zero reset otherwise C Set if dst was incremented from OFFFFh to 0000 reset otherwise Set if dst was incremented from OFFh to 00 reset otherwise V Set if an arithmetic overflow occurs otherwise reset OSCOFF CPUOFF and GIE are not affected The 16 bit counter pointed to by R13 is added to a 32 bit counter pointed to by R12 ADD R13 0 R12 Add LSDs ADC 2 R12 Add carry to MSD The 8 bit counter pointed to by R13 is added to a 16 bit counter pointed to by R12 ADD B R13 0 R12 Add LSDs ADC B 1 R12 Add carry to MSD RISC 16 Bit CPU 3 21 Instruction Set ADD W ADD B Syntax Operation Description Status Bits Mode Bits Example Example Add source to destination Add source to destination ADD src dst or ADD W Ssrc dst ADD B src dst src dst dst The source operand is added to the destination operand The source operand is not affected The previous
234. lid start bit the USART halts character reception and waits for the next low period on URXDx The majority vote is also used for each bit in a character to prevent bit errors The USART module automatically detects framing errors parity errors overrun errors and break conditions when receiving characters The bits FE PE OE and BRK are set when their respective condition is detected When any of these error flags are set RXERR is also set The error conditions are described in Table 13 1 Table 13 1 Receive Error Conditions 13 8 Error Condition Description A framing error occurs when a low stop bit is detected When two stop bits are used only the first stop bit is checked for framing error When a framing error is detected the FE bit is set A parity error is a mismatch between the number of 1s in a character and the value of the parity bit Parity error When an address bit is included in the character it is included in the parity calculation When a parity error is detected the PE bit is set An overrun error occurs when a character is loaded Receive overrun error into UxRXBUF before the prior character has been read When an overrun occurs the OE bit is set A break condition is a period of 10 or more low bits received on URXDx after a missing stop bit When a Break condition break condition is detected the BRK bit is set A break condition can also set the interrupt flag URXIFGx Framing error When URXEIE 0
235. ly Always read as 0 ADC10 18 31 DAC12 The DAC12 module is a 12 bit voltage output digital to analog converter This chapter describes the DAC12 Two DAC12 modules are implemented in the MSP430x15x and MSP430x16x devices Topic Page 19 1 DAC12 Introduction 5 9 e rrr eee eters ES 19 2 19 2 DAC12 Operation EE lates ele eer TO 19 4 19 3 DAC 12 Registers cc cae ose sas ee senecmenet cca was 19 10 19 1 DAC 12 Introduction 19 1 DAC12 Introduction 19 2 DAC12 The DAC12 module is a 12 bit voltage output DAC The DAC12 can be configured in 8 or 12 bit mode and may be used in conjunction with the DMA controller When multiple DAC12 modules are present they may be grouped together for synchronous update operation Features of the DAC12 include 12 bit monotonic output 8 or 12 bit voltage output resolution Programmable settling time vs power consumption Internal or external reference selection Straight binary or 2 s compliment data format Self calibration option for offset correction LL oe L BU Synchronized update capability for multiple DAC12s Note Multiple DAC12 Modules Some devices may integrate more than one DAC12 module In the case where more than one DAC12 is present on a device the multiple DAC12 modules operate identically Throughout this chapter nomenclature appears such as DAC12 xDAT or DAC12 xCTL to describe register names When this occurs th
236. ly received address characters set URXIFGx RXWAKE Bit 1 Receive wake up flag 0 Received character is data 1 Received character is an address RXERR Bit 0 Receive error flag This bit indicates a character was received with error s When RXERR 1 on or more error flags FE PE OE BRK is also set RXERR is cleared when UxRXBUF is read 0 No receive errors detected 1 Receive error detected 13 24 USART Peripheral Interface UART Mode USART Registers UART Mode UxBRO USART Baud Rate Control Register 0 7 6 5 4 3 2 1 0 Pees ESE ESERED rw rw rw rw rw rw rw rw UxBR1 USART Baud Rate Control Register 1 7 6 5 4 3 2 1 0 ze pe peg eese ee rw rw rw rw rw rw rw rw UxBRx The valid baud rate control range is 3 lt UxBR lt OFFFFh where UxBR UxBR1 UxBRO0 Unpredictable receive and transmit timing occurs if UxBR 3 UxMCTL USART Modulation Control Register 7 6 5 4 3 2 1 0 ae e ae ee et rw rw rw rw rw rw rw rw UxMCTLx Bits Modulation bits These bits select the modulation for BRCLK 7 0 USART Peripheral Interface UART Mode 13 25 USART Registers UART Mode UxRXBUF USART Receive Buffer Register 7 6 5 4 3 2 1 0 RIESE ESZESESERES r r r r r r r r UxRXBUFx Bits The receive data buffer is user accessible and contains the last received 7 0 character from the receive shift register Reading UXRXBUF resets the receive error bits the RXWAKE bit and URXIFGx In 7 bit data mode UxRXBUF is LSB justified and the MSB is always r
237. ly reset when the interrupt request is serviced or may be reset by software Figure 18 17 ADC10 Interrupt System Set ADC10IFG nN 0 ADC10IE IRQ Interrupt Service Requested ADC10CLK IRACC Interrupt Request Accepted ADC10 18 23 ADC10 Registers 18 3 ADC10 Registers The ADC10 registers are listed in Table 18 3 Table 18 3 ADC10 Registers Register Short Form Register Type Address Initial State ADC10 Input enable register ADC10AE Read write 04Ah Reset with POR ADC10 control register 0 ADC10CTLO Read write 01BOh Reset with POR ADC10 control register 1 ADC10CTL1 Read write 01B2h Reset with POR ADC10 memory ADC10MEM Read 01B4h Unchanged ADC10 data transfer control register 0 ADC10DTCO Read write 048h Reset with POR ADC10 data transfer control register 1 ADC10DTC1 Read write 049h Reset with POR ADC10 data transfer start address ADC10SA Read write 01BCh 0200h with POR 18 24 ADC10 ADC10 Registers ADC10CTLO ADC10 Control Register 0 15 14 13 12 11 10 9 8 sre oosa nee merour nere rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 m Modifiable only when ENC 0 SREFx Bits Select reference 15 13 000 VR Vcc and Vp Vss 001 VR VREF and Vp Vss 010 Vg Vengr and Vn Vss 011 Vn VeREF and Vn Vss 100 VR Vcc and Vp VREF Vengr 101 VR Vngr and Vp Vngr VeREF 110 Vg VerReF and Vp VREfF VeREF
238. n Up Down Mode gt mw Dead Time Output Mode 6 Toggle Set Output Mode 2 Toggle Reset EQUI EQUI ic EQUI EQUI Interrupt Events EQUO EQUO EQU2 EQU2 EQU2 EQU2 Timer_A Operation 11 2 4 Capture Compare Blocks Capture Mode Three identical capture compare blocks TACCRx are present in Timer A Any of the blocks may be used to capture the timer data or to generate time intervals The capture mode is selected when CAP 1 Capture mode is used to record time events It can be used for speed computations or time measurements The capture inputs CCIxA and CCIxB are connected to external pins or internal signals and are selected with the CCISx bits The CMx bits select the capture edge of the input signal as rising falling or both A capture occurs on the selected edge of the input signal If a capture occurs The timer value is copied into the TACCRx register The interrupt flag CCIFG is set The input signal level can be read at any time via the CCI bit MSP430x1xx family devices may have different signals connected to CCIxA and CCIxB Refer to the device specific datasheet for the connections of these signals The capture signal can be asynchronous to the timer clock and cause a race condition Setting the SCS bit will synchronize the capture with the next timer clock Setting the SCS bit to synchronize the capture signal with the timer clock is recomm
239. n a table pointed to by R5 SP 2 2 SP PC 2 5 SP R5 gt PC Indirect indirect R5 with autoincrement X R5 Call on the address contained in the address pointed to by R5 X e g table with address starting at X X can be an address or a label SP 2 5 SP PC 2 5 SP X R5 2 PC Indirect indirect R5 X RISC 16 Bit CPU 3 29 Instruction Set CLR W CLR B Syntax Operation Emulation Description Status Bits Example Example Example Clear destination Clear destination CLR dst or CLR W dst CLR B dst 0 dst MOV 0 dst MOV B 0 dst The destination operand is cleared Status bits are not affected RAM word TONI is cleared CLR TONI 0 gt TONI Register R5 is cleared CLR R5 RAM byte TONI is cleared CLR B TONI 0 gt TONI 3 30 RISC 16 Bit CPU CLRC Syntax Operation Emulation Description Status Bits Mode Bits Example Instruction Set Clear carry bit CLRC 0 gt C BIC 1 SR The carry bit C is cleared The clear carry instruction is a word instruction N Not affected Z Not affected C Cleared V Not affected OSCOFF CPUOFF and GIE are not affected The 16 bit decimal counter pointed to by R13 is added to a 32 bit counter pointed to by R12 CLRC C 0 defines start DADD R13 0 R12 add 16 bit counter to low word of 32 bit counter DADC 2 R12 add carry to high word of 32 bit counter RISC 16 Bit CPU 3 31 Instruction Set C
240. n the device specific data sheet The three DCOx bits divide the DCO range selected by the RSELx bits into 8 frequency steps separated by approximately 10 The five MODx bits switch between the frequency selected by the DCOx bits and the next higher frequency set by DCOx 1 When DCOx 07h the MODx bits have no effect because the DCO is already at the highest setting for the selected RSELx range Figure 4 5 Typical DCOx Range and RSELx Steps fpco 10000 kHz 1000 kHz 100 kHz RSEL 7 RSEL 6 RSEL 5 RSEL 4 RSEL 3 RSEL 2 RSEL 1 RSEL 0 DCO 0 DCO 1 DCO 2 DCO 3 DCO 4 DCO 5 DCO 6 DCO 7 Basic Clock Module 4 7 Basic Clock Module Operation Using an External Resistor Rosc for the DCO The DCO temperature coefficient can be reduced by using an external resistor Rosc tied to DVcc to source the current for the DC generator Figure 4 6 shows the typical relationship of fpco vs temperature for both the internal and external resistor options Using an external Rosc reduces the DCO temperature coefficient to approximately 0 1 C See the device specific data sheet for parameters Rosc also allows the DCO to operate at higher frequencies For example the internal resistor nominal value is approximately 300 kQ allowing the DCO to operate up to approximately 5 MHz When using an external Rosc of approximately 100 kQ the DCO can operate up to approximately 10 MHz The user should take care to not exceed the maximum M
241. n to UXTXBUF while the transmitter is disabled will be held in the buffer but will not be moved to the transmit shift register or transmitted Once UTXEx is set the data in the transmit buffer is immediately loaded into the transmit shift register and character transmission resumes USART Peripheral Interface UART Mode USART Operation UART Mode 13 2 6 UART Baud Rate Generation The USART baud rate generator is capable of producing standard baud rates from non standard source frequencies The baud rate generator uses one prescaler divider and a modulator as shown in Figure 13 7 This combination supports fractional divisors for baud rate generation The maximum USART baud rate is one third the UART source clock frequency BRCLK Figure 13 7 MSP430 Baud Rate Generator SSEL1 SSELON 215 28 a UCLKI ACLK SMCLK suck J11 8 L S 0 or 1 Compare 0 or 1 Toggle FE BITCLK Modulation Data Shift Register R LSB first lt mA m7 8 m0 A UxMCTL Bit Start Timing for each bit is shown in Figure 13 8 For each bit received a majority vote is taken to determine the bit value These samples occur at the N 2 1 N 2 and N 2 1 BRCLK periods where N is the number of BRCLKs per BITCLK Figure 13 8 BITCLK Baud Rate Timing Majority Vote m 0 v y Bit Start 1 m vvyv 1 pup o y yy c 4 ERU N 2 N 2 1 N 2 2 N 2 N 2 1 Cou
242. nalog Input Equivalent Circuit 18 8 Vs MSP430 V Input voltage at pin Ax Rs T RI Vs External source voltage l V Rs External source resistance C R Internal MUX on input resistance C C Input capacitance ADC10 Vc Capacitance charging voltage v The resistance of the source Rg and Hj affect tsample The following equations can be used to calculate the minimum sampling time tsample for a 10 bit conversion When ADC10SR 0 t Rg Rj x In 211 x C 800ns gt sample When ADC10SR 1 t Rg R x In211 x C 2 5us gt sample Substituting the values for Rj and C given above the equation becomes t gt Rg 2k x 7 625 x 20pF 800ns ADC10SR 0 sample t Rg 2k x 7 625 x 20pF 2 5us ADC10SR 1 gt sample For example if Rs is 10 kQ tsample must be greater than 2 63 us when ADC10SR 0 or 4 33 us when ADC10SR 1 18 2 6 Conversion Modes ADC10 Operation The ADC10 has four operating modes selected by the CONSEQx bits as discussed in Table 18 1 Table 18 1 Conversion Mode Summary CONSEQx Mode 00 Single channel single conversion 01 Sequence of channels 10 Repeat single channel 11 Repeat sequence of channels Operation A single channel is converted once A sequence of channels is converted once A single channel is converted repeatedly A sequence of channels is converted repeatedly ADC10 18 9 ADC10 Operation Single Cha
243. nce the sum of the old TBCLx data and the new period can be higher than the TBCLO value When the sum of the previous TBCLx value plus t is greater than the TBCLO data the old TBCLO value must be subtracted to obtain the correct time interval Up Down Mode Timer_B Operation The up down mode is used if the timer period must be different from TBR may counts and if symmetrical pulse generation is needed The timer repeatedly counts up to the value of compare latch TBCLO and back down to zero as shown in Figure 12 7 The period is twice the value in TBCLO Note TBCLO TBR max If TBCLO gt TBR max the counter operates as if it were configured for continuous mode It does not count down from TBR max to zero LLLLLLLLL Figure 12 7 Up Down Mode TBCLO Oh The count direction is latched This allows the timer to be stopped and then restarted in the same direction it was counting before it was stopped If this is not desired the TBCLR bit must be used to clear the direction The TBCLR bit also clears the TBR value and the clock divider In up down mode the TBCCRO CCIFG interrupt flag and the TBIFG interrupt flag are set only once during the period separated by 1 2 the timer period The TBCCRO CCIFG interrupt flag is set when the timer counts from TBCLO 1 to TBCLO and TBIFG is set when the timer completes counting down
244. nd D reg As The addressing bits responsible for the addressing mode used for the source src S reg The working register used for the source src Ad The addressing bits responsible for the addressing mode used for the destination dst D reg The working register used for the destination dst B W Byte or word operation 0 word operation 1 byte operation Note Destination Address Destination addresses are valid anywhere in the memory map However when using an instruction that modifies the contents of the destination the user must ensure the destination address is writable For example a masked ROM location would be a valid destination address but the contents are not modifiable so the results of the instruction would be lost LLL JJ RISC 16 Bit CPU 3 17 Instruction Set 3 4 4 Double Operand Format I Instructions Figure 3 9 illustrates the double operand instruction format Figure 3 9 Double Operand Instruction Format Table 3 11 lists and describes the double operand instructions Table 3 11 Double Operand Instructions Mnemonic S Reg Operation Status Bits D Reg V N Z C MOV B src dst src dst ADD B src dst src dst dst i E ADDC B src ds
245. nd SWRST function for UART or SPI When the I2C and SYNC bits are first set after a PUC this bit becomes I2CEN function and is automatically cleared O 12C operation is disabled 1 12C operation is enabled USART Peripheral Interface I C Mode 15 21 12C Module Registers I2CTCTL I2C Transmit Control Register 7 rw 0 6 rw 0 5 4 3 2 1 0 I2CWORD I2CRM I2CSSELx I2CTRX I2CSTB I2CSTP I2CSTT rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Modifiable only when I2CEN 0 I2CWORD I2CRM I2CSSELx I2CTRX I2CSTB I2CSTP I2CSTT 15 22 Bit 7 Bit 6 Bits Bit 3 Bit 2 Bit 1 Bit 0 12C word mode Selects byte or word mode for the 12C data register 0 Byte mode 1 Word mode 12C repeat mode 0 I2CNDAT defines the number of bytes transmitted 1 Number of bytes transmitted is controlled by software I2CNDAT is unused 12C clock source select When MST 1 and arbitration is lost the external SCL signal is automatically used 00 Noclock 12C module is inactive 01 ACLK 10 SMCLK 11 SMCLK I2C transmit This bit selects the transmit or receive function for the 12C controller when MST 1 When MST 0 the R W bit of the address byte defines the data direction I2CTRX must be reset for proper slave mode operation 0 Receive mode Data is received on the SDA pin 1 Transmit mode Data transmitted on the SDA pin Start byte Setting the I2CSTB bit when MST 1 initiates a start byte when I2CSTT 1 After
246. negative otherwise reset OSCOFF CPUOFF and GIE are not affected Content of R5 is negated twos complement MOV OOAEh R5 R5 000AEh INV R5 Invert R5 R5 OFF51h INC R5 Rb is now negated R5 OFF52h Content of memory byte LEO is negated MOV B 0AEh LEO MEM LEO OAEh INV B LEO Invert LEO MEM LEO 051h INC B LEO MEM LEO is negated MEM LEO 052h RISC 16 Bit CPU 3 43 Instruction Set JC JHS Syntax Operation Description Status Bits Example Example Jump if carry set Jump if higher or same JC label JHS label If C 1 PC 2x offset gt PC If C 2 0 execute following instruction The status register carry bit C is tested If it is set the 10 bit signed offset contained in the instruction LSBs is added to the program counter If C is reset the next instruction following the jump is executed JC jump if carry higher or same is used for the comparison of unsigned numbers 0 to 65536 Status bits are not affected The P1IN 1 signal is used to define or control the program flow BIT 01h amp P1IN State of signal Carry JC PROGA If carry 1 then execute program routine A eerste Carry 0 execute program here R5 is compared to 15 If the content is higher or the same branch to LABEL CMP 15 R5 JHS LABEL Jump is taken if R5 2 15 ins Continue here if R5 15 3 44 RISC 16 Bit CPU JEQ JZ Syntax Operation Description Status Bits Example Ex
247. nfigured as either a watchdog or interval timer with the WDTCTL register The WDTCTL register also contains control bits to configure the RST NMI pin WDTCTL is a 16 bit password protected read write register Any read or write access must use word instructions and write accesses must include the write password O5Ah in the upper byte Any write to WDTCTL with any value other than 05Ah in the upper byte is a security key violation and triggers a PUC system reset regardless of timer mode Any read of WDTCTL reads 069h in the upper byte 10 2 1 Watchdog Timer Counter The watchdog timer counter WDTCNT is a 16 bit up counter that is not directly accessible by software The WDTCNT is controlled and time intervals selected through the watchdog timer control register WDTCTL The WDTONT can be sourced from ACLK or SMCLK The clock source is selected with the WDTSSEL bit 10 2 2 Watchdog Mode After a PUC condition the WDT module is configured in the watchdog mode with an initial 32 ms reset interval using the DCOCLK The user must setup halt or clear the WDT prior to the expiration of the initial reset interval or another PUC will be generated When the WDT is configured to operate in watchdog mode either writing to WDTCTL with an incorrect password or expiration of the selected time interval triggers a PUC A PUC resets the WDT to its default condition and configures the RST NMI pin to reset mode 10 2 3 Interval Timer Mode 10 4 Settin
248. nges when the timer equals TACCRx in either count direction and when the timer equals TACCRO depending on the output mode An example is shown in Figure 11 14 using TACCRO and TACCR2 Figure 11 14 Output Example Timer in Up Down Mode OFFFFh TACCRO TACCR2 Oh EQU2 EQU2 EQU2 EQU2 TAIFG EQUO TAIFG EQUO InIeAmiprENenIS EURO H B8l Note Switching Between Output Modes When switching between output modes one of the OUTMODx bits should remain set during the transition unless switching to mode 0 Otherwise output glitching can occur because a NOR gate decodes output mode 0 A safe method for switching between output modes is to use output mode 7 as a transition state BIS OUTMOD_7 amp TACCTLx Set output mode 7 BIC OUTMODx amp TACCTLxX Clear unwanted bits beo 11 16 Timer_A Timer_A Operation 11 2 6 Timer_A Interrupts TACCRO Interrupt Two interrupt vectors are associated with the 16 bit Timer_A module TACCRO interrupt vector for TACCRO CCIFG TAIV interrupt vector for all other CCIFG flags and TAIFG In capture mode any CCIFG flag is set when a timer value is captured in the associated TACCRx register In compare mode any CCIFG flag is set if TAR counts to the associated TACCRx value Software may also set or clear any CCIFG flag All CCIFG flags request an interrupt when their corresponding CCIE bit and the GIE bit are set The TACCRO CCIFG flag has the highest
249. nication STTIFG is used in slave mode only 15 18 USART Peripheral Interface IC Mode 12C Module Operation I2CIV Interrupt Vector Generator The 12C interrupt flags are prioritized and combined to source a single interrupt vector The interrupt vector register I2CIV is used to determine which flag requested an interrupt The highest priority enabled interrupt generates a number in the I2CIV register that can be evaluated or added to the program counter to automatically enter the appropriate software routine Disabled 12C interrupts do not affect the I2CIV value When RXDMAEN 1 RXRDYIFG will not affect the I2CIV value and when TXDMAEN 1 TXRDYIFG will not affect the I2CIV value regardless of the state of RXRDYIE or TXRDYIE Any access read or write of the I2CIV register automatically resets the highest pending interrupt flag except for TXRDYIFG and RXRDYIFG Those flags are reset as described in Table 15 3 If another interrupt flag is set another interrupt is immediately generated after servicing the initial interrupt I2CIV Software Example The following software example shows the recommended use of I2CIV The I2CIV value is added to the PC to automatically jump to the appropriate routine I2C ISR ADD amp I2CIV PC Add offset to jump table RETI Vector 0 No interrupt JMP ALIFG ISR Vector 2 ALIFG JMP NACKIFG ISR Vector 4 NACKIFG JMP OAIFG ISR Vector 6 OAIFG JMP ARDYIFG ISR Vector 8 ARDYIFG JMP
250. nnel Single Conversion Mode A single channel selected by INCHx is sampled and converted once The ADC result is written to ADC10MEM Figure 18 5 shows the flow of the single channel single conversion mode When ADC10SC triggers a conversion successive conversions can be triggered by the ADC10SC bit When any other trigger source is used ENC must be toggled between each conversion Figure 18 5 Single Channel Single Conversion Mode x input channel Ax t Conversion result is unpredictable 18 10 ADC10 CONSEQx 00 ADC100N 1 Wait for Enable SHS 0 and ENC 1o0r4 and ADC10SC 4 Wait for Trigger 4 8 16 64 x ADC10CLK Sample Input Channel 12 x ADC10CLK 1 x ADC10CLK Conversion Completed Result to ADC10MEM ADC1OIFG is Set ADC10 Operation Sequence of Channels Mode A sequence of channels is sampled and converted once The sequence begins with the channel selected by INCHx and decrements to channel AO Each ADC result is written to ADC10MEM The sequence stops after conversion of channel AO Figure 18 6 shows the sequence of channels mode When ADC10SC triggers a sequence successive sequences can be triggered by the ADC10SC bit When any other trigger source is used ENC must be toggled between each sequence Figure 18 6 Sequence of Channels Mode x INCHx Wait for Enable SHS 0 and ENC 1 or 4 and ADC10SC 4 Wait
251. not flag a low voltage condition or reset the device and the SVSON bit is cleared Software can test the SVSON bit to determine when the delay has elapsed and the SVS is monitoring the voltage properly Figure 6 2 SVSON state When Changing VLDx VLDx 15 SVSON VLD vs Time tsettle Supply Voltage Supervisor 6 5 SVS Operation 6 2 4 SVS Operating Range Each SVS level has hysteresis to reduce sensitivity to small supply voltage changes when AVcc is close to the threshold The SVS operation and SVS Brownout interoperation are shown in Figure 6 3 Figure 6 3 Operating Levels for SVS and Brownout Reset Circuit Software Sets VLD gt 0 Abe Msvs IT MsVSstart Mu tet saan gt ck ieee 0 S OS X hys SVS IT MB IT 6C start RE pe IRIE TE CESE SAGE SERIE SSR REE E DESIST SRS a pen poss pss s cp pee Brownout ion Out gt Brownout Pe Region 1 Lil 0 t SVSOUT A td BOR SVSCircuit Active d BOR 1 0 B TORE a SVSon Set POR 14 0 eee Be 1 undefined 6 6 Supply Voltage Supervisor SVS Registers 6 3 SVS Registers The SVS registers are listed in Table 6 1 Table 6 1 SVS Registers Register Short Form Register Type Address Initial State SVS Control Register SVSCTL Read write 055h Reset with BOR SVSCTL SVS Control Register 7 6 5 4 3 2 1 0 r rw ot rw ot rw ot rw ot r
252. not in use conserves power 0 Watchdog timer is not stopped 1 Watchdog timer is stopped Watchdog timer NMI edge select This bit selects the interrupt edge for the NMI interrupt when WDTNMI 1 Modifying this bit can trigger an NMI Modify this bit when WDTNMI 0 to avoid triggering an accidental NMI 0 NMI on rising edge 1 NMI on falling edge Watchdog timer NMI select This bit selects the function for the RST NMI pin 0 Reset function 1 NMI function Watchdog timer mode select 0 Watchdog mode 1 Interval timer mode Watchdog timer counter clear Setting WOTCNTCL 1 clears the count value to 0000h WDTCNTCL is automatically reset 0 No action 1 WDTCNT 0000h Watchdog timer clock source select 0 SMCLK 1 ACLK Watchdog timer interval select These bits select the watchdog timer interval to set the WDTIFG flag and or generate a PUC 00 Watchdog clock source 32768 01 Watchdog clock source 8192 10 Watchdog clock source 512 11 Watchdog clock source 64 10 8 Watchdog Timer Watchdog Timer Registers IE1 Interrupt Enable Register 1 7 6 5 4 3 2 1 0 rw 0 rw 0 NMIIE WDTIE Bits 7 5 Bit 4 Bits 3 1 Bit 0 These bits may be used by other modules See device specific datasheet NMI interrupt enable This bit enables the NMI interrupt Because other bits in IE1 may be used for other modules it is recommended to set or clear this bit using BIS B or BIC B instructions rather than MOV B or CLR B instruc
253. npredictable Also if a write to flash is attempted with WRT 0 the ACCVIFG interrupt flag is set and the flash memory is unaffected When a byte word write or any erase operation is initiated from within flash memory the flash controller returns op code OSFFFh to the CPU at the next instruction fetch Op code O3FFFh is the JMP PC instruction This causes the CPU to loop until the flash operation is finished When the operation is finished and BUSY 0 the flash controller allows the CPU to fetch the proper op code and program execution resumes The flash access conditions while BUSY 1 are listed in Table 5 3 Table 5 3 Flash Access While BUSY 1 Flash Flash WAIT Result Operation Access Read 0 ACCVIFG 0 OSFFFh is the value read Any erase or Write 0 ACCVIFG 1 Write is ignored Byte word write inctruction 0 ACCVIFG 0 CPU fetches 03FFFh This fetch is the JMP PC instruction Any 0 ACCVIFG 1 LOCK 1 Read 1 ACCVIFG 0 O3FFFh is the value read Block write Write 1 ACCVIFG 0 Flash is written Instruction 1 ACCVIFG 1 LOCK 1 fetch All interrupt sources should be disabled before initiating any flash operation If an enabled interrupt were to occur during a flash operation the CPU would fetch O3FFFh as the address of the interrupt service routine The CPU would then execute the JMP PC instruction while BUSY 1 When the flash operation finished the CPU would begin executing code at address O3FFFh not the correct address f
254. ntents are lost N Setif result is negative reset if positive Z Set if dst contained OFFFEh reset otherwise Set if dst contained OFEh reset otherwise C Set if dst contained OFFFEh or OFFFFh reset otherwise Set if dst contained OFEh or OFFh reset otherwise V Set if dst contained O7FFEh or 07FFFh reset otherwise Set if dst contained 07Eh or 07Fh reset otherwise OSCOFF CPUOFF and GIE are not affected The item on the top of the stack TOS is removed without using a register PUSH R5 R5 is the result of a calculation which is stored in the system stack INCD SP Remove TOS by double increment from stack Do not use INCD B SP is a word aligned register RET The byte on the top of the stack is incremented by two INCD B 0 SP Byte on TOS is increment by two 3 42 RISC 16 Bit CPU INVLW INV B Syntax Operation Emulation Emulation Description Status Bits Mode Bits Example Example Instruction Set Invert destination Invert destination INV dst INV B dst NOT dst dst XOR OFFFFh dst XOR B 0FFh dst The destination operand is inverted The original contents are lost N Set if result is negative reset if positive Z Set if dst contained OFFFFh reset otherwise Set if dst contained OFFh reset otherwise C Set if result is not zero reset otherwise NOT Zero Set if result is not zero reset otherwise NOT Zero V Set if initial destination operand was
255. nter i N 2 N 2 1 N 2 2 i H H 1 0 N2 N21 1 0 N2 BITCLK gt i INT N 2 m 0 gt j NEVEN INT N 2 i j INT N 2 m 1 Nopp INT N 2 R 1 lt Bit Period ee gt m corresponding modulation bit R Remainder from N 2 division USART Peripheral Interface UART Mode 13 11 USART Operation UART Mode Baud Rate Bit Timing The first stage of the baud rate generator is the 16 bit counter and comparator At the beginning of each bit transmitted or received the counter is loaded with INT N 2 where N is the value stored in the combination of UXBRO and UxBR1 The counter reloads INT N 2 for each bit period half cycle giving a total bit period of N BRCLKs For a given BRCLK clock source the baud rate used determines the required division factor N N BRCLK baud rate The division factor N is often a non integer value of which the integer portion can be realized by the prescaler divider The second stage of the baud rate generator the modulator is used to meet the fractional part as closely as possible The factor N is then defined as N UxBR 1 5m i 0 Where N Target division factor UxBR 16 bit representation of registers UxBRO and UxBR1 I Bit position in the character n Total number of bits in the character mj Data of each corresponding modulation bit 1 or 0 Ba d rate BEE _ BRCLK UxBR 15 m i 0 The BITCLK can be adjusted from bit to bi
256. nts from zero to the value selected by the TBCNTL x bits 11 Up down The timer repeatedly counts from zero up to the value of TBCLO and then back down to zero Timer B 12 5 Timer_B Operation Up Mode The up mode is used if the timer period must be different from TBR max counts The timer repeatedly counts up to the value of compare latch TBCLO which defines the period as shown in Figure 12 2 The number of timer counts in the period is TBCLO 1 When the timer value equals TBCLO the timer restarts counting from zero If up mode is selected when the timer value is greater than TBCLO the timer immediately restarts counting from zero Figure 12 2 Up Mode TBR max TBCLO Oh The TBCCRO CCIFG interrupt flag is set when the timer counts to the TBCLO value The TBIFG interrupt flag is set when the timer counts from TBCLO to zero Figure 11 3 shows the flag set cycle Figure 12 3 Up Mode Flag Setting Timer Clock fe FT a Timer Set TBIFG l i l Set TBCCRO CCIFG j j Changing the Period Register TBCLO 12 6 Timer B When changing TBCLO while the timer is running and when the TBCLO load mode is immediate if the new period is greater than or equal to the old period or greater than the current count value the timer counts up to the new period If the new period is less than the current count value the timer rolls to zero However one additional count may occur before the counter rolls to zero Tim
257. o zero it is reloaded from its temporary register and the corresponding DMAIFG flag is set When DMADTx 0 the DMAEN bit is cleared automatically when DMAxSZ decrements to zero and must be set again for another transfer to occur In repeated single transfer mode the DMA controller remains enabled with DMAEN 1 and a transfer occurs every time a trigger occurs 8 6 DMA Controller Figure 8 3 DMA Single Transfer State Diagram DMAEN 0 DMAREQ 0 T_Size gt DMAxSZ DMAEN 0 DMAEN 1 DMAxSZ o T Size DMAxSA T SourceAdd DMAxDA T DestAdd DMA Operation lt gt DMAxSZ gt 0 AND DMAEN 1 T Size DMAxSZ DMADTx 4 AND DMAxSZ 0 AND DMAEN 1 DMAxSA T SourceAdd DMADTx 0 DMAxDA T DestAdd AND DMAxSZ 0 OR DMAEN 0 DMAABORT 1 DMAABORT 0 DMAREQ 0 Wait for Trigger Trigger AND DMALEVEL 0 OR i 1 AND DMALEVEL 1 2x MCLK Trigger Hold CPU Transfer one word byte ENNMI 1 AND NMI event OR DMALEVEL 1 AND Trigger 0 Decrement DMAxSZ Modify T SourceAdd Modify T DestAdd DMA Controller 8 7 DMA Operation Block Transfers In block transfer mode a transfer of a complete block of data occurs after one trigger When DMADTx 1 the DMAEN bit is cleared after the completion of the block transfer and must be set again before another block transfer can be triggered After a block transfer h
258. oa 1 i ogic T i i o omo EQUO UP DOWN EQU6 cap i i 1 LI e i Set TBCCR6 i CCIFG 1 i i i 1 OUT 1 i i i i OUT6 Signal i 1 L 1 I 1 I i i i E lu mu On re ee ee Timer_B 12 3 Timer_B Operation 12 2 Timer_B Operation The Timer_B module is configured with user software The setup and operation of Timer_B is discussed in the following sections 12 2 1 16 Bit Timer Counter TBR Length The 16 bit timer counter register TBR increments or decrements depending on mode of operation with each rising edge of the clock signal TBR can be read or written with software Additionally the timer can generate an interrupt when it overflows TBR may be cleared by setting the TBCLR bit Setting TBCLR also clears the clock divider and count direction for up down mode F7 1l Note Modifying Timer B Registers It is recommended to stop the timer before modifying its operation with exception of the interrupt enable interrupt flag and TBCLR to avoid errant operating conditions When the timer clock is asynchronous to the CPU clock any read from TBR should occur while the timer is not operating or the results may be unpredictable Alternatively the timer may be read multiple times while operating and a majority vote taken in software to determine the correct reading Any write to TBR will take effect immediately LLLLLLLS X O YYAY Y MC CC
259. ock The cumulative programming time tcpr must not be exceeded for any block during a block write A block write cannot be initiated from within flash memory The block write must be initiated from RAM only The BUSY bit remains set throughout the duration of the block write The WAIT bit must be checked between writing each byte or word in the block When WAIT is set the next byte or word of the block can be written When writing successive blocks the BLKWRT bit must be cleared after the current block is complete BLKWRT can be set initiating the next block write after the required flash recovery time given by teng BUSY is cleared following each block write completion indicating the next block can be written Figure 5 10 shows the block write timing Figure 5 10 Block Write Cycle Timing BLKWRT bit Write to Flash e g MOV 123h amp Flash Y mum 3 1 3 3 4 Generate Programming Voltage Cumulative Programming Ti Programming Operation Active Remove pee od Programming Voltage me tcpT lt 4ms Vcc Current Consumption is Increased BUSY e tBlock 0 S0 fFTG tBlock 1 63 21 fFTG __ tBlock 1 63 2 FTG_ tend 6 fFTG WAIT Flash Memory Controller 5 11 Flash Memory Operation Block Write Flow and Example A block write flow is shown in Figure 5 8 and the following example Figure 5 11 Block Write Flow Disable all interrup
260. ode receive The low byte of the word was received first then the high byte The register is double buffered If a new word is received before the previous word has been read the new word is held in a temporary buffer before being latched into the I2CDR register RXRDYIFG is set when I2CDR is ready to be accessed In master mode underflow occurs when the transmit shift register and the transmit buffer are empty In slave mode underflow occurs when the transmit shift register and the transmit buffer are empty and the external 12C master still requests data When transmit underflow occurs the I2CTXUDF bit is set Writing data to the I2CDR register or resetting the I2CEN bit resets I2CTXUDF I2CTXUDF is used in transmit mode only Receive overrun occurs when the receive shift register is full and the receive buffer is full The I2CRXOVR bit is set when receive overrun occurs No data is lost because SCL is held low in this condition which stops further bus activity Reading the I2CDR register or resetting I2CEN resets I2CRXOVR The I2CRXOVR bit is used in receive mode only USART Peripheral Interface I C Mode 15 15 12C Module Operation 15 2 6 12C Clock Generation and Synchronization Figure 15 13 I2CIN The 12C module is operated with the clock source selected by the IZCSSELx bits The prescaler I2CPSC and the I2CSCLH and I2CSCLL registers determine the frequency and duty cycle of the SCL clock signal for master mode as shown in F
261. off to reduce current consumption The voltage reference generator can generate a fraction of the device s Vcc or a fixed transistor threshold voltage of 0 55 V Comparator A 16 5 Comparator_A Operation 16 2 5 Comparator_A Port Disable Register CAPD The comparator input and output functions are multiplexed with the associated I O port pins which are digital CMOS gates When analog signals are applied to digital CMOS gates parasitic current can flow from Vcc to GND This parasitic current occurs if the input voltage is near the transition level of the gate Disabling the port pin buffer eliminates the parasitic current flow and therefore reduces overall current consumption The CAPDx bits when set disable the corresponding P2 input buffer as shown in Figure 16 3 When current consumption is critical any P2 pin connected to analog signals should be disabled with their associated CAPDx bit Figure 16 3 Transfer Characteristic and Power Dissipation in a CMOS Inverter Buffer Voc VI 6 ee Vo lcc loc v VI V T e 0 Voc L O P gt o CAPD x 1 Ves 16 2 6 Comparator A Interrupts One interrupt flag and one interrupt vector are associated with the Comparator A as shown in Figure 16 4 The interrupt flag CAIFG is set on either the rising or falling edge of the comparator output selected by the CAIES bit If both the CAIE and the GIE bits are set then the CAIFG flag generates an int
262. ompare latch x The ability to simultaneously load grouped compare latches assures the dead times Figure 12 9 Output Unit in Up Down Mode 12 10 TBR max TBCLQ eene rte TBCL1 JN f LN ee TBCL3 t f Qe fhe ep N Mw Oh Dead Time Output Mode 6 Toggle Set Output Mode 2 Toggle Reset EQU1 EQU1 EQU1 EQU1 Interrupt Events TBIFG EQUO TBIFG EQUO p EQU3 EQU3 EQU3 EQU3 Timer_B Timer_B Operation 12 2 4 Capture Compare Blocks Capture Mode Three or seven identical capture compare blocks TBCCRx are present in Timer_B Any of the blocks may be used to capture the timer data or to generate time intervals The capture mode is selected when CAP 1 Capture mode is used to record time events It can be used for speed computations or time measurements The capture inputs CCIxA and CCIxB are connected to external pins or internal signals and are selected with the CCISx bits The CMx bits select the capture edge of the input signal as rising falling or both A capture occurs on the selected edge of the input signal If a capture is performed The timer value is copied into the TBCCRx register The interrupt flag CCIFG is set The input signal level can be read at any time via the CCI bit MSP430x1xx family devices may have different signals connected to CCIxA and CCIxB Refer to the device specific datasheet for the connections of these signals The capture signal can b
263. on address contents of R11 Register R10 is incremented by 1 for a byte operation or 2 for a word operation after the fetch it points to the next address without any overhead This is useful for table processing Valid only for source operand The substitute for destination operand is 0 Rd plus second instruction INCD Rd Length One or two words Operation Comment Example MOV R10 0 R11 Before Address Register Space OFF18h OFF16h OFF14h OFF12h OFA34h OFA32h OFA30h 010AAh 010A8h 010A6h Address Space Cowan Pc Register OFF18h OFF16h OFF14h OFF12h R10 OFA34h R11 010A8h OFA34h OFA32h OFA30h 010AAh 010A8h 010A6h The autoincrementing of the register contents occurs after the operand is fetched This is shown in Figure 3 8 Figure 3 8 Operand Fetch Operation Instruction Address RISC 16 Bit CPU 3 15 Addressing Modes 3 3 7 Immediate Mode The immediate mode is described in Table 3 10 Table 3 10 Immediate Mode Description Assembler Code Content of ROM MOV 45h TONI MOV PC X PC 45 X TONI PC Length Two or three words It is one word less if a constant of CG1 or CG2 can be used Operation Move the immediate constant 45h which is contained in the word following the instruction to destination address TONI When fetching the source the program counter points to the word following the instruction and moves the contents to the des
264. ontroller DMA Operation Table 8 2 DMA Trigger Operation DMAxTSELx Operation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 A transfer is triggered when the DMAREQ bit is set The DMAREQ bit is automatically reset when the transfer starts A transfer is triggered when the TACCR2 CCIFG flag is set The TACCR2 CCIFG flag is automatically reset when the transfer starts If the TACCR2 CCIE bit is set the TACCR2 CCIFG flag will not trigger a transfer A transfer is triggered when the TBCCR2 CCIFG flag is set The TBCCR2 CCIFG flag is automatically reset when the transfer starts If the TBCCR2 CCIE bit is set the TBCCR2 CCIFG flag will not trigger a transfer A transfer is triggered when USARTO receives new data In I2C mode the trigger is the data received condition not the RXRDYIFG flag RXRDYIFG is not cleared when the transfer starts and setting RXRDYIFG with software will not trigger a transfer If RXRDYIE is set the data received condition will not trigger a transfer In UART or SPI mode a transfer is triggered when the URXIFGO flag is set URXIFGO is automatically reset when the transfer starts If URXIEO is set the URXIFGO flag will not trigger a transfer A transfer is triggered when USARTO is ready to transmit new data In I2C mode the trigger is the transmit ready condition not the TXRDYIFG flag TXRDYIFG is not cleared when the transfer starts and sett
265. onversions The module implements a 12 bit SAR core sample select control reference generator and a 16 word conversion and control buffer The conversion and control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU intervention ADC12 features include Greater than 200 ksps maximum conversion rate Monotonic 12 bit converter with no missing codes Sample and hold with programmable sampling periods controlled by software or timers Conversion initiation by software Timer_A or Timer_B Software selectable on chip reference voltage generation 1 5 V or 2 5 V Software selectable internal or external reference Eight individually configurable external input channels L L DL Conversion channels for internal temperature sensor AVcc and external references L Independent channel selectable reference sources for both positive and negative references Selectable conversion clock source Li Single channel repeat single channel sequence and repeat sequence conversion modes ADC core and reference voltage can be powered down separately Interrupt vector register for fast decoding of 18 ADC interrupts 16 conversion result storage registers The block diagram of ADC12 is shown in Figure 17 1 ADC 12 Introduction Figure 17 1 ADC 12 Block Diagram AVsS REF2 5V REFO
266. ootstrap loader BSL Every MSP430 flash device contains a bootstrap loader The BSL enables users to read or program the flash memory or RAM using a UART serial interface Access to the MSP430 flash memory via the BSL is protected by a 256 bit user defined password For more details see the Application report Features of the MSP430 Bootstrap Loader at www ti com sc msp430 Programming Flash Memory via a Custom Solution The ability of the MSP430 CPU to write to its own flash memory allows for in system and external custom programming solutions as shown in Figure 5 12 The user can choose to provide data to the MSP430 through any means available UART SPI etc User developed software can receive the data and program the flash memory Since this type of solution is developed by the user it can be completely customized to fit the application needs for programming erasing or updating the flash memory Figure 5 12 User Developed Programming Solution 5 16 Host Flash Memory Commands data etc a L MSP430 CPU executes user software Read write flash memory Flash Memory Controller Flash Memory Registers 5 4 Flash Memory Registers The flash memory registers are listed in Table 5 4 Table 5 4 Flash Memory Registers Register Short Form Register Type Address Initial State Flash memory control register 1 FCTL1 Read write 0128h 09600h with PUC Flash memory control register 2 FCTL2 Read write 012Ah 09642h with PUC
267. or Trigger 4 8 16 64 x ADC10CLK Sample Input Channel Ax If x 0 then x INCH else x x 1 If x 0 then x INCH else x x 1 x ADC10CLK ENC 0 and x 0 MSC 1 and ENC 1 1 x ADC10CLK or x 0 Conversion Completed Result to ADC10MEM ADC10IFG is Set x input channel Ax ADC10 18 13 ADC10 Operation Using the MSC Bit To configure the converter to perform successive conversions automatically and as quickly as possible a multiple sample and convert function is available When MSC 1 and CONSEQx gt 0 the first rising edge of the SHI signal triggers the first conversion Successive conversions are triggered automatically as soon as the prior conversion is completed Additional rising edges on SHI are ignored until the sequence is completed in the single sequence mode or until the ENC bit is toggled in repeat single channel or repeated sequence modes The function of the ENC bit is unchanged when using the MSC bit Stopping Conversions Stopping ADC10 activity depends on the mode of operation The recommended ways to stop an active conversion or conversion sequence are Resetting ENC in single channel single conversion mode stops a conversion immediately and the results are unpredictable For correct results poll the ADC10BUSY bit until reset before clearing ENC Li Resetting ENC during repeat single channel operation stops the converter at the end of the current conversion
268. or interrupt service routine 5 14 Flash Memory Controller Flash Memory Operation 5 3 5 Stopping a Write or Erase Cycle Any write or erase operation can be stopped before its normal completion by setting the emergency exit bit EMEX Setting the EMEX bit stops the active operation immediately and stops the flash controller All flash operations cease the flash returns to read mode and all bits in the FCTL1 register are reset The result of the intended operation is unpredictable 5 3 6 Configuring and Accessing the Flash Memory Controller The FCTLx registers are 16 bit password protected read write registers Any read or write access must use word instructions and write accesses must include the write password OA5h in the upper byte Any write to any FCTLx register with any value other than OA5h in the upper byte is a security key violation sets the KEYV flag and triggers a PUC system reset Any read of any FCTLx registers reads 096h in the upper byte Any write to FCTL1 during an erase or byte word write operation is an access violation and sets ACCVIFG Writing to FCTL1 is allowed in block write mode when WAIT 1 but writing to FCTL1 in block write mode when WAIT 0 is an access violation and sets ACCVIFG Any write to FCTL2 when the BUSY 1 is an access violation Any FCTLx register may be read when BUSY 1 A read will not cause an access violation 5 3 7 Flash Memory Controller Interrupts The flash controller has two interru
269. ount value the timer rolls to zero However one additional count may occur before the counter rolls to zero Timer_A Operation Continuous Mode In the continuous mode the timer repeatedly counts up to OFFFFh and restarts from zero as shown in Figure 11 4 The capture compare register TACCRO works the same way as the other capture compare registers Figure 11 4 Continuous Mode OFFFFh Oh The TAIFG interrupt flag is set when the timer counts from OFFFFh to zero Figure 11 5 shows the flag set cycle Figure 11 5 Continuous Mode Flag Setting Tmer X rrr y rem Qo Yah reren ree X os Set TAIFG l l Timer_A 11 7 Timer_A Operation Use of the Continuous Mode The continuous mode can be used to generate independent time intervals and output frequencies Each time an interval is completed an interrupt is generated The next time interval is added to the TACCRx register in the interrupt service routine Figure 11 6 shows two separate time intervals tg and t4 being added to the capture compare registers In this usage the time interval is controlled by hardware not software without impact from interrupt latency Up to three independent time intervals or output frequencies can be generated using all three capture compare registers Figure 11 6 Continuous Mode Time Intervals 11 8 Timer A OFFFFH TACCROa TACCR1b TACCR1c TACCROb TACCROc TACCROJ TACCR1a TACCRid j Time interv
270. ource address is unchanged 01 Source address is unchanged 10 Source address is decremented 11 Source address is incremented DMA destination byte This bit selects the destination as a byte or word 0 Word 1 Byte DMA Controller 8 21 DMA Registers DMA Bit 6 DMA source byte This bit selects the source as a byte or word SRCBYTE 0 Word 1 Byte DMA Bit 5 DMA level This bit selects between edge sensitive and level sensitive LEVEL triggers 0 Edge sensitive rising edge 1 Level sensitive high level DMAEN Bit 4 DMA enable 0 Disabled 1 Enabled DMAIFG Bit 3 DMA interrupt flag 0 No interrupt pending 1 Interrupt pending DMAIE Bit 2 DMA interrupt enable 0 Disabled 1 Enabled DMA Bit 1 DMA Abort This bit indicates if a DMA transfer was interrupt by an NMI ABORT 0 DMA transfer not interrupted 1 DMA transfer was interrupted by NMI DMAREQ Bit 0 DMA request Software controlled DMA start DMAREQ is reset automatically 0 No DMA start 1 Start DMA DMAxSA DMA Source Address Register 15 14 13 12 11 10 9 8 rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw DMAxSAx Bits DMA source address The source address register points to the DMA source 15 0 address for single transfers or the first source address for block transfers The source address register remains unchanged during block and burst block transfers 8 22 DMA Controller DMA Registers DMAxDA DMA Destination Address Register 15 14 13 12 11
271. output signal from the comparator is inverted This allows the user to determine or compensate for the comparator input offset voltage 16 4 Comparator_A 16 2 3 Output Filter Comparator_A Operation The output of the comparator can be used with or without internal filtering When control bit CAF is set the output is filtered with an on chip RC filter Any comparator output oscillates if the voltage difference across the input terminals is small Internal and external parasitic effects and cross coupling on and between signal lines power supply lines and other parts of the system are responsible for this behavior as shown in Figure 16 2 The comparator output oscillation reduces accuracy and resolution of the comparison result Selecting the output filter can reduce errors associated with comparator oscillation Figure 16 2 RC Filter Response at the Output of the Comparator Terminal Terminal Comparator Inputs Comparator Output WIT Unfiltered at CAOUT Comparator Output Filtered at CAOUT 16 2 4 Voltage Reference Generator The voltage reference generator is used to generate VcaReF which can be applied to either comparator input terminal The CAREFx bits control the output of the voltage generator The CARSEL bit selects the comparator terminal to which VcAgEr is applied If external signals are applied to both comparator input terminals the internal reference generator should be turned
272. p g XSELM1 a o o SELMO mE Fault_from XT2 Fault from XT1 1 DCOR mw T o J XT2 Is an internal signal XT2 0 on devices without XT2 MSP430x11xx and MSP430x12xx XT2 1 on devices with XT2 MSP430F13x MSP430F14x MSP430F15x and MSP430F16x IRQA Interrupt request accepted LFXT1_OscFault Only applicable to LFXT1 oscillator in HF mode Basic Clock Module 4 11 Basic Clock Module Operation Sourcing MCLK from a Crystal 4 12 After a PUC the basic clock module uses DCOCLK for MCLK If required MCLK may be sourced from LFXT1 or XT2 The sequence to switch the MCLK source from the DCO clock to the crystal clock LFXT1CLK or XT2CLK is 1 Switch on the crystal oscillator 2 Clear the OFIFG flag 3 Wait at least 50 us 4 Test OFIFG and repeat steps 1 4 until OFIFG remains cleared Select LFXT1 HF mode for MCLK BIC HOSCOFF SR Turn on osc BIS B XTS amp BCSCTL1 HF mode L1 BIC B 0OFIFG amp IFG1 Clear OFIFG MOV HOFFh R15 Delay L2 DEC R15 i JNZ L2 j BIT B OFIFG amp IFG1 Re test OFIFG JNZ L1 Repeat test if needed BIS B SELM1 SELM0 amp BCSCTL2 Select LFXT1CLK Basic Clock Module Basic Clock Module Operation 4 2 7 Synchronization of Clock Signals When switching MCLK or SMCLK from one clock source to the another the switch is synchronized to avoid critical r
273. p MACS Load first operand MOV 405678h amp OP2 Load 2nd operand be Process results 8x8 Signed Multiply Accumulate Absolute addressing MOV B 012h amp 0136h Load first operand SXT amp MACS Sign extend first operand MOV B 034h R5 Temp location for 2nd operand SXT R5 Sign extend 2nd operand MOV R5 amp OP2 Load 2nd operand oe Process results Hardware Multiplier 7 5 Hardware Multiplier Operation 7 2 4 7 2 5 7 6 Indirect Addressing of RESLO When using indirect or indirect autoincrement addressing mode to access the result registers At least one instruction is needed between loading the second operand and accessing one of the result registers Access multiplier results with indirect addressing RESLO address in R5 for indirect MOV RESLO R5 MOV amp OPER1 amp MPY MOV amp OPER2 amp OP2 NOP MOV R5 amp XXX MOV R5 amp XXX Using Interrupts ri ri ri Load Load Need Move Move 1st operand 2nd operand one cycle RESLO RESHI If an interrupt occurs after writing OP1 but before writing OP2 and the multiplier is used in servicing that interrupt the original multiplier mode selection is lost and the results are unpredictable To avoid this disable interrupts before using the hardware multiplier or do not use the multiplier in interrupt service routines Disable interrupts DINT NOP MOV xxh amp OP2 EINT Hardware Multiplier i 1 MOV
274. parator_A module is configured with user software The setup and operation of comparator_A is discussed in the following sections The comparator compares the analog voltages at the and input terminals If the terminal is more positive than the terminal the comparator output CAOUT is high The comparator can be switched on or off using control bit CAON The comparator should be switched off when not in use to reduce current consumption When the comparator is switched off the CAOUT is always low 16 2 2 Input Analog Switches The analog input switches connect or disconnect the two comparator input terminals to associated port pins using the P2CAx bits Both comparator terminal inputs can be controlled individually The P2CAx bits allow L Application of an external signal to the and terminals of the comparator Routing of an internal reference voltage to an associated output port pin Internally the input switch is constructed as a T switch to suppress distortion in the signal path F7 1 Note Comparator Input Connection When the comparator is on the input terminals should be connected to a signal power or ground Otherwise floating levels may cause unexpected interrupts and increased current consumption Cd The CAEX bit controls the input multiplexer exchanging which input signals are connected to the comparator s and terminals Additionally when the comparator terminals are exchanged the
275. peration the SYNC and 12C bits must be set After module initialization the 12C module is ready for transmit or receive operation Setting I2CEN releases the 12C module for operation Configuring and re configuring the 12C module must be done when I2CEN 0 to avoid unpredictable behavior Setting I2CEN 0 has the following effects I2C communication stops SDA and SCL are high impedance I2CTCTL bits 3 0 are cleared and bits 7 4 are unchanged I2CDCTL and I2CDR register is cleared Transmit and receive shift registers are cleared UOCTL I2CNDAT I2CPSC I2CSCLL I2CSCLH registers are unchanged I2COA I2CSA I2CIE I2CIFG and I2CIV registers are unchanged D O UD D D D UD When re configuring the USART from I2C mode to UART or SPI mode the 12C SYNC and I2CEN bits must first be cleared then the SWRST must be set and the UART or SPI initialization procedure must be followed Failure to follow this procedure could result in unpredictable operation V7 1 Note Configuring the USART Module for I2C Operation After Reset The required 12C configuration process is 1 Select 12C mode with SWRST 1 BIS B I2C SYNC amp UOCTL 2 Disable the I2C module BIC B I2CEN amp UOCTL 3 Configure the 12C module with I2CEN 0 4 Set I2CEN via software BIS B I2CEN amp UOCTL Failure to follow this process may result in unpredictable USART behavior cl UU Note Re Configuring the USA
276. pletes MCLK is turned off The maximum DMA cycle time for all operating modes is shown in Table 8 3 Table 8 3 Maximum Single Transfer DMA Cycle Time CPU Operating Mode Clock Source Maximum DMA Cycle Time Active mode MCLK DCOCLK 4 MCLK cycles Active mode MCLK LFXT1CLK 4 MCLK cycles Low power mode LPMO 1 MCLK DCOCLK 5 MCLK cycles Low power mode LPM3 4 MCLK DCOCLK 5 MCLK cycles 6 ust Low power mode LPMO0 1 MCLK LFXT1CLK 5 MCLK cycles Low power mode LPM3 MCLK LFXT1CLK 5 MCLK cycles Low power mode LPM4 MCLK LFXT1CLK 5 MCLK cycles 6 ust t The additional 6 us are needed to start the DCOCLK It is the t L PMx Parameter in the data sheet DMA Controller 8 15 DMA Operation 8 2 7 Using DMA with System Interrupts DMA transfers are not interruptible by system interrupts System interrupts remain pending until the completion of the transfer NMI interrupts can interrupt the DMA controller if the ENNMI bit is set System interrupt service routines are interrupted by DMA transfers If an interrupt service routine or other routine must execute with no interruptions the DMA controller should be disabled prior to executing the routine 8 2 8 DMA Controller Interrupts Each DMA channel has its own DMAIFG flag Each DMAIFG flag is set in any mode when the corresponding DMAxSZ register counts to zero If the corresponding DMAIE and GIE bits are set an interrupt request is generated All DMAIFG flags source only one DMA controller
277. ppt Note Holding RST NMI Low When configured in the NMI mode a signal generating an NMI event should not hold the RST NMI pin low If a PUC occurs from a different source while the NMI signal is low the device will be held in the reset state because a PUC changes the RST NMI pin to the reset function ee Note Modifying WDTNMIES When NMI mode is selected and the WDTNMIES bit is changed an NMI can be generated depending on the actual level at the RST NMI pin When the NMI edge select bit is changed before selecting the NMI mode no NMI is generated LLLLLSS A OOOUOOLO KIFKRUU System Resets Interrupts and Operating Modes 2 7 System Reset and Initialization Figure 2 5 Block Diagram of Non Maskable Interrupt Sources ACCV ACCVIFG FCTL1 1 ACCVIE IE1 5 Clear PUC Flash Module RST NMI POR PUC N KEYV Voc PUC System Reset Generator POR WDTTMSEL WDTNMIES WDTNMI WDTQn EQU PUC POR TUFT NMIIFG NMIIE IE1 4 IRQ Clear IFG1 0 PUC hi WDT Counter OSCFault POR OFIFG E IFG1 1 IRQA OFIE WDTTMSEL WDTIE IE1 1 IE1 0 NMI IRQA Clear PUC J Watchdog Timer Module PUC IRQA Interrupt Request Accepted 2 8 System Resets Interrupts and Operating Modes System Reset and Initialization Flash Acc
278. pt sources KEYV and ACCVIFG ACCVIFG is set when an access violation occurs When the ACCVIE bit is re enabled after a flash write or erase a set ACCVIFG flag will generate an interrupt request ACCVIFG sources the NMI interrupt vector so it is not necessary for GIE to be set for ACCVIFG to request an interrupt ACCVIFG may also be checked by software to determine if an access violation occurred ACCVIFG must be reset by software The key violation flag KEYV is set when any of the flash control registers are written with an incorrect password When this occurs a PUC is generated immediately resetting the device 5 3 8 Programming Flash Memory Devices There are three options for programming an MSP430 flash device All options support in system programming J Program via JTAG Program via the Bootstrap Loader L Program via a custom solution Flash Memory Controller 5 15 Flash Memory Operation Programming Flash Memory via JTAG MSP430 devices can be programmed via the JTAG port The JTAG interface requires four signals 5 signals on 20 and 28 pin devices ground and optionally Vcc and RST NMI The JTAG port is protected with a fuse Blowing the fuse completely disables the JTAG port and is not reversible Further access to the device via JTAG is not possible For more details see the Application report Programming a Flash Based MSP430 Using the JTAG Interface at www ti com sc msp430 Programming Flash Memory via the B
279. r modules See device specific datasheet T Does not apply to MSP430x12xx devices See IFG2 for the MSP430x12xx USARTO interrupt flag bits IFG2 Interrupt Flag Register 2 7 6 5 4 3 2 1 0 rw 1 rw 0 rw 1 rw 0 UTXIFG1 URXIFG1 UTXIFGOt URXIFGOt t MSP430x12xx devices only 14 22 Bits 7 6 Bit 5 Bit 4 Bits 3 2 Bit 1 Bit 0 These bits may be used by other modules See device specific datasheet USART1 transmit interrupt flag UTXIFG1 is set when U1TXBUF is empty 0 No interrupt pending 1 Interrupt pending USART1 receive interrupt flag URXIFG1 is set when U1RXBUF has received a complete character 0 No interrupt pending 1 Interrupt pending These bits may be used by other modules See device specific datasheet USARTO transmit interrupt flag UTXIFGO is set when UOTXBUF is empty 0 No interrupt pending 1 Interrupt pending USARTO receive interrupt flag URXIFGO is set when UORXBUF has received a complete character 0 No interrupt pending 1 Interrupt pending USART Peripheral Interface SPI Mode USART Peripheral Interface 12C Mode The universal synchronous asynchronous receive transmit USART peripheral interface supports 12C communication in USARTO This chapter describes the 12C mode The I2C mode is implemented on the MSP430x1 5x and MSP430x1 6x devices Topic Page 15 1 12C Module Introduction sesessesese enne 15 2 5 282ciModulelOperationge ECCE LED 15 3 I C Modu
280. ram flow J Peripherals should be switched on only when needed Use low power integrated peripheral modules in place of software driven functions For example Timer A and Timer B can automatically generate PWM and capture external timing with no CPU resources 2 5 Connection of Unused Pins Calculated branching and fast table look ups should be used in place of flag polling and long software calculations 4 Avoid frequent subroutine and function calls due to overhead For longer software routines single cycle CPU registers should be used The correct termination of all unused pins is listed in Table 2 2 Table 2 2 Connection of Unused Pins Pin AVcc AVss VREF VeREF Vner Vengr XIN XOUT XT2IN XT20UT Px 0 to Px 7 RST NMI Test Vpp Test TDO TDI TMS TCK Potential DVcc DVss Open DVss DVss DVcc Open DVss Open Open DVcc or Voc DVss DVss Open Open Open Open Open Comment 13x 14x 15x and 16x devices 13x 14x 15x and 16x devices Switched to port function output direction Pullup resistor 47 kQ P11x devices Pulldown resistor 30K 11x1 devices 11x1A 11x2 12x 12x2 devices System Resets Interrupts and Operating Modes 2 17 Chapter 3 RISC 16 Bit CPU This chapter describes the MSP430 CPU addressing modes and instruction set Topic 3 1 3 2 3 3 3 4 CPU Introduction CPU Registers o o mae oe erem ane el everstvaeserclarein sists E Addressing
281. rd Write BLKWRT WRT Write Mode 0 1 Byte word write 1 1 Block write Both write modes use a sequence of individual write instructions but using the block write mode is approximately twice as fast as byte word mode because the voltage generator remains on for the complete block write Any instruction that modifies a destination can be used to modify a flash location in either byte word mode or block write mode A flash word low high byte must not be written more than twice between erasures Otherwise damage can occur The BUSY bit is set while a write operation is active and cleared when the operation completes If the write operation is initiated from RAM the CPU must not access flash while BUSY 1 Otherwise an access violation occurs ACOVIFGi is set and the flash write is unpredictable A byte word write operation can be initiated from within flash memory or from RAM When initiating from within flash memory all timing is controlled by the flash controller and the CPU is held while the write completes After the write completes the CPU resumes code execution with the instruction following the write The byte word write timing is shown in Figure 5 7 Figure 5 7 Byte Word Write Timing 4 E 4 gt lt gt Programming Operation Active sy Generate Remove Programming Voltage Programming Voltage Programming Time Vc c Current Consumption is Increased lt BUSY a tWord
282. re source and destination CMP src dst Or CMP W src dst CMP B src dst dst NOT src 1 or dst src The source operand is subtracted from the destination operand This is accomplished by adding the 1s complement of the source operand plus 1 The two operands are not affected and the result is not stored only the status bits are affected N Set if result is negative reset if positive src gt dst Z Set if result is zero reset otherwise src dst C Set if there is a carry from the MSB of the result reset otherwise V Set if an arithmetic overflow occurs otherwise reset OSCOFF CPUOFF and GIE are not affected R5 and R6 are compared If they are equal the program continues at the label EQUAL CMP R5 R6 R5 R6 JEQ EQUAL YES JUMP Two RAM blocks are compared If they are not equal the program branches to the label ERROR MOV NUM R5 number of words to be compared MOV ZBLOCK1 R6 BLOCK1 start address in R6 MOV ZBLOCK2 R7 BLOCK start address in R7 L 1 CMP R6 0 R7 Are Words equal R6 increments JNZ ERROR No branch to ERROR INCD R7 Increment R7 pointer DEC R5 Are all words compared JNZ L 1 No another compare The RAM bytes addressed by EDE and TONI are compared If they are equal the program continues at the label EQUAL CMPB EDE TONI MEM EDE MEM TONI JEQ EQUAL YES JUMP 3 34 RISC 16 Bit CPU DADC W DADC B Syntax Operation Emulation Descrip
283. received USARTO transmit ready DAC12 OIFG ADC12IFGx TACCRO CCIFG TBCCRO CCIFG USART1 data received USART1 transmit ready Multiplier ready No trigger No trigger DMA1IFG DMAEO Jo3uoo puy Auoug YNG C E DMADSTINCRx DMADTx DMADSTBYTE 3 ROUNDROBIN DMA Channel 0 DMAOSA DMAODA DMAOSZ DMASRSBYTE DMASRCINCRx DMAEN DMADSTINCRx DMADTx DMADSTBYTE DMA Channel 1 DMA1SA DMA1DA DMA1SZ DMASRSBYTE DMASRCINCRx DMAEN DMADSTINCRx DMADTx DMADSTBYTE DMA Channel 2 DMA2SA DMA2DA DMA2SZ DMASRSBYTE DMASRCINCRx DMAEN DMAONFETCH DMA Introduction C JTAG Active NMI Interrupt Request ENNMI Address Space Ls Halt CPU DMA Controller 8 Co DMA Operation 8 2 DMA Operation 8 2 1 The DMA controller is configured with user software The setup and operation of the DMA is discussed in the following sections DMA Addressing Modes The DMA controller has four addressing modes The addressing mode for each DMA channel is independently configurable For example channel 0 may transfer between two fixed addresses while channel 1 transfers between two blocks of addresses The addressing modes are shown in Figure 8 2 The addressing modes are Fixed address to fixed address Lj Fixed address to block of addresses Block of addresses to fixed address 1 Block of addresses to block of addresses The addressing modes are configured with the DMASRCINCRx and DMADS
284. register is right justified Bit 9 is the MSB Bits 15 10 are always 0 15 28 USART Peripheral Interface 2C Mode 12C Module Registers I2CIE I2C Interrupt Enable Register 7 6 5 4 3 2 1 0 STTIE GCIE TXRDYIE RXRDYIE ARDYIE owe NACKIE ALIE rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 STTIE GCIE TXRDYIE RXRDYIE ARDYIE OAIE NACKIE ALIE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 START detect interrupt enable 0 Interrupt disabled 1 Interrupt enabled General call interrupt enable 0 Interrupt disabled 1 Interrupt enabled Transmit ready interrupt enable When TXDMAEN 1 TXRDYIE is ignored and TXRDYIFG will not generate an interrupt 0 Interrupt disabled 1 Interrupt enabled Receive ready interrupt enable When RXDMAEN 1 RXRDYIE is ignored and RXRDYIFG will not generate an interrupt 0 Interrupt disabled 1 Interrupt enabled Access ready interrupt enable 0 Interrupt disabled 1 Interrupt enabled Own address interrupt enable 0 Interrupt disabled 1 Interrupt enabled No acknowledge interrupt enable 0 Interrupt disabled 1 Interrupt enabled Arbitration lost interrupt enable 0 Interrupt disabled 1 Interrupt enabled USART Peripheral Interface I C Mode 15 29 12C Module Registers I2CIFG I2C Interrupt Flag Register 7 6 5 4 3 2 1 0 sme core none mows amowwo ours vacara aura rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 STTIFG Bit 7 START detect interrupt
285. related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures monitor failures and their consequences lessen the likelihood of failures that might cause harm and take appropriate remedial actions Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety critical applications In some cases TI components may be promoted specifically to facilitate safety related applications With such components TI s goal is to help enable customers to design and create their own end product solutions that meet applicable functional safety standards and requirements Nonetheless such components are subject to these terms No TI components are authorized for use in FDA Class III or similar life critical medical equipment unless authorized officers of the parties have executed a special agreement specifically governing such use Only those TI components which TI has specifically designated as military grade or enhanced plastic are designed and intended for use in military aerospace applications or environments Buyer acknowledges and agrees that any military or aerospace use of Tl components which have not been so desi
286. rence is not automatically disabled but can be disabled by setting REFON 0 When the core oscillator or reference are disabled they consume no current ADC 12 Operation 17 2 5 Sample and Conversion Timing An analog to digital conversion is initiated with a rising edge of the sample input signal SHI The source for SHI is selected with the SHSx bits and includes the following The ADC12SC bit The Timer A Output Unit 1 The Timer B Output Unit 0 The Timer B Output Unit 1 The polarity of the SHI signal source can be inverted with the ISSH bit The SAMPCON signal controls the sample period and start of conversion When SAMPCON is high sampling is active The high to low SAMPCON transition starts the analog to digital conversion which requires 13 ADC12CLK cycles Two different sample timing methods are defined by control bit SHP extended sample mode and pulse mode Extended Sample Mode The extended sample mode is selected when SHP 0 The SHI signal directly controls SAMPCON and defines the length of the sample period tsample When SAMPCON is high sampling is active The high to low SAMPCON transition starts the conversion after synchronization with ADC12CLK See Figure 17 3 Figure 17 3 Extended Sample Mode Start Stop Start Conversion Sampling Sampling Conversion Complete a SHI SAMPCON 13 x ADC12CLK lt sample gt lt 4 teonvert 3 synci ADC12 17 7 ADC 12
287. reports See RISC 16 Bit CPU See Basic Clock Module See RISC 16 Bit CPU See FLL in MSP430x4xx Family User s Guide See System Resets Interrupts and Operating Modes See Digital I O See System Resets Interrupts and Operating Modes See Basic Clock Module See System Resets Interrupts and Operating Modes See RISC 16 Bit CPU See System Resets Interrupts and Operating Modes See System Resets Interrupts and Operating Modes See System Resets Interrupts and Operating Modes See Basic Clock Module See RISC 16 Bit CPU See RISC 16 Bit CPU See RISC 16 Bit CPU See RISC 16 Bit CPU See Watchdog Timer Register Bit Conventions Register Bit Conventions Each register is shown with a key indicating the accessibility of the each individual bit and the initial condition Register Bit Accessibility and Initial Condition Key Bit Accessibility Read write Read only Read as 0 Read as 1 Write only Write as 0 Write as 1 No register bit implemented writing a 1 results in a pulse The register bit is always read as 0 Cleared by hardware Set by hardware Condition after PUC Condition after POR vi Contents UE cep tne mE 14 Archiecture i oosococs ooo e Ev ee EE eESRRPRDIPDIRPOLRER CAI FEES PY 1 2 Flexible Clock System ssssueessssssseslsss e nn 1 3 Embedded Emulation 0 0 ccc cece EEEN nee 14 Address Space rne beu Pc han deae db ud Baad doe WAST ast BOM us iud y cei dL dene aet ERR RUE
288. rite Access violation interrupt flag 0 No interrupt pending 1 Interrupt pending Flash security key violation This bit indicates an incorrect FCTLx password was written to any flash control register and generates a PUC when set KEYV must be reset with software 0 FCTLx password was written correctly 1 FCTLx password was written incorrectly Busy This bit indicates the status of the flash timing generator 0 Not Busy 1 Busy Flash Memory Controller Flash Memory Registers IE1 Interrupt Enable Register 1 7 6 5 4 3 2 1 0 rw 0 ACCVIE These bits may be used by other modules See device specific datasheet Flash memory access violation interrupt enable This bit enables the ACCVIFG interrupt Because other bits in IE1 may be used for other modules it is recommended to set or clear this bit using BIS B or BIC B instructions rather than MOV B or CLR B instructions 0 Interrupt not enabled 1 Interrupt enabled Flash Memory Controller 5 21 Chapter 6 Supply Voltage Supervisor This chapter describes the operation of the SVS The SVS is implemented in MSP430x15x and MSP430x16x devices Topic Page S SVS InITOdUCUOH E coco coteoee cem dud eue E 5 2 622 SVS Operalon c cco mi eee enema E MS 5 4 6 3 SVS Registers o e e rer steve caters lean eels ee 6 1 SVS Introduction 6 1 SVS Introduction The supply voltage supervisor SVS is used to monitor the AVcc supply voltage or an e
289. rnal Signal XT2 0 MSP430x11xx MSP430x12xx devices SCG1 E SELS XT2 1 MSP430x13x MSP430x14x MSP430x15x and MSP430x16x devices Note LFXT1 Oscillator Characteristics Low frequency crystals often require hundreds of milliseconds to start up depending on the crystal Ultralow power oscillators such as the LFXT1 in LF mode should be guarded from noise coupling from other sources The crystal should be placed as close as possible to the MSP430 with the crystal housing grounded and the crystal traces guarded with ground traces The LFXT1 oscillator in LF mode requires a 5 1 MQ resistor from XOUT to Vss when Vcc lt 2 5 V Laaa Basic Clock Module 4 5 Basic Clock Module Opera tion 4 2 3 XT2 Oscillator Some devices have a second crystal oscillator XT2 XT2 sources XT2CLK and its characteristics are identical to LFXT1 in HF mode The XT2OFF bit disables the XT2 oscillator if XT2CLK is not used for MCLK or SMCLK as shown in Figure 4 3 XT2 may be used with external clock signals on the XT2IN pin When used with an external signal the external frequency must meet the datasheet parameters for XT2 and XT2OFF must be reset Figure 4 3 Off Signals for Oscillator XT2 XT2OFF CPUOFF SELM1 SELMO SCG1 SELS 4 2 4 Digitally Cont Disabling the DCO E y D gt XT20ff Internal signal rolled Oscillator DCO The DCO is an integrated ring oscillator with RC type characteristics As with
290. rocess of counting for the action to take place If a particular value is directly written to the counter then an associated action does not take place LLLLL 12 1 1 Similarities and Differences From Timer A 12 2 Timer B Timer B is identical to Timer A with the following exceptions The length of Timer B is programmable to be 8 10 12 or 16 bits Timer B TBCCRx registers are double buffered and can be grouped All Timer B outputs can be put into a high impedance state The SCCI bit function is not implemented in Timer B Timer_B Introduction Figure 12 1 Timer_B Block Diagram Pe a ere eg Dg Re ee eT ae Te ae ee ete ee ete EY Timer Clock Timer Block TBSSELx IDx MCx i 15 0 I LI Li n LI ed B gt TBR RC Count e auo 1 2 4 8 M i AGER e M Clear 8 10 12 16 ila SMCLK A 10 CNTLx LY gt A 11 TBCLR LI TBCLGRPx 00 01 i Set TBIFG i i 10 i Group T i Load Logic i a a a a MN a a a ac lee ence CCRO MED n CCR1 O EEEE EEEREN CCR2 a ea eae ee ae CCR3 NIMM A CCR4 Bases at EE CCR5 We ee pe ga ee ee ep ge Cor E LOU CAUTE OUO 1 1 LI R CCISx CMx COV CCR6 1 LI SCS CCI6A 00 Capture CCle8 01 Mode 1 LI GND 19 Timer Clock gt Sync a a i VCC 11 iy i CLLDx CCI L e Compare Latch TBCL6 i
291. roduction 10 1 Watchdog Timer Introduction 10 2 The primary function of the watchdog timer WDT module is to perform a controlled system restart after a software problem occurs If the selected time interval expires a system reset is generated If the watchdog function is not needed in an application the module can be configured as an interval timer and can generate interrupts at selected time intervals Features of the watchdog timer module include Four software selectable time intervals Watchdog mode Interval mode Access to WDT control register is password protected Control of RST NMI pin function Selectable clock source OU oO oo oO U L Can be stopped to conserve power The WDT block diagram is shown in Figure 10 1 i ae Note Watchdog Timer Powers Up Active After a PUC the WDT module is automatically configured in the watchdog mode with an initial 32 ms reset interval using the DCOCLK The user must setup or halt the WDT prior to the expiration of the initial reset interval Watchdog Timer Watchdog Timer Introduction Figure 10 1 Watchdog Timer Block Diagram WDTCTL MSB MDB 16 bit Password Pulse Counter Compare Generator 16 bit Write Enable Low Byte R W SMCLK WDTHOLD ACLK WDTNMIES WDTNMI WDTTMSEL Watchdog Timer 10 3 Watchdog Timer Operation 10 2 Watchdog Timer Operation The WDT module can be co
292. rrupt that occurred during the erase cycle will have its associated flag set and will generate an interrupt request when re enabled Flash Memory Controller 5 5 Flash Memory Operation Initiating an Erase from Within Flash Memory Any erase cycle can be initiated from within flash memory or from RAM When a flash segment erase operation is initiated from within flash memory all timing is controlled by the flash controller and the CPU is held while the erase cycle completes After the erase cycle completes the CPU resumes code execution with the instruction following the dummy write When initiating an erase cycle from within flash memory it is possible to erase the code needed for execution after the erase If this occurs CPU execution will be unpredictable after the erase cycle The flow to initiate an erase from flash is shown in Figure 5 5 Figure 5 5 Erase Cycle from Within Flash Memory Disable all interrupts and watchdog Setup flash controller and erase mode Set LOCK 1 re enable Interrupts and watchdog Segment Erase from flash 514 kHz SMCLK 952 kHz Assumes ACCVIE NMIIE OFIE O MOV WDTPW WDTHOLD amp WDTCTL Disable WDT DINT Disable interrupts MOV FWKEY FSSEL1 FNO amp FCTL2 SMCLK 2 MOV FWKEY amp FCTL3 Clear LOCK MOV FWKEY ERASE amp FCTL1 Enable segment erase CLR amp OFC10h Dummy write erase S1 MOV FWKEY LOCK amp FCTL3 Done set LOCK Re enable WDT
293. rsion immediately and the results are unpredictable For correct results poll the busy bit until reset before clearing ENC Resetting ENC during repeat single channel operation stops the converter at the end of the current conversion Resetting ENC during a sequence or repeat sequence mode stops the converter at the end of the sequence _j Any conversion mode may be stopped immediately by setting the CONSEQx 0 and resetting ENC bit Conversion data are unreliable 71 Note No EOS Bit Set For Sequence If no EOS bit is set and a sequence mode is selected resetting the ENC bit does not stop the sequence To stop the sequence first select a single channel mode and then reset ENC LLLLLLLS A O ADC12 17 15 ADC 12 Operation 17 2 8 Using the Integrated Temperature Sensor To use the on chip temperature sensor the user selects the analog input channel INCHx 1010 Any other configuration is done as if an external channel was selected including reference selection conversion memory selection etc The typical temperature sensor transfer function is shown in Figure 17 10 When using the temperature sensor the sample period must be greater than 30 us The temperature sensor offset error can be large and may need to be calibrated for most applications See device specific datasheet for parameters Selecting
294. s 3 2 4 Constant Generator Registers CG1 and CG2 Lssssuuu 3 2 5 General Purpose Registers R4 R15 2c eee 33 Addressing Modas cs sotodnr eR ER Ew Rr a4 ede eae keen ed ee ree eee eee 3 3 1 Register Mod hevateersteeewsbewsetev de tee deed Qupe3 Rb e d eR 3 9 2 Indexed Mode cute de i EIA ER rete age et cia BM m ee 3 3 8 Symbolic Mode fos ahebwi davies Boies dan i a a li eri pua 3 9 4 Absolute Mode uec er dated eed ees ER Menus eere remus 3 3 5 Indirect Register Mode 00 cece eee eee 3 3 6 Indirect Autoincrement Mode 0 0000 cece eects 3 3 7 Immediate Mode 2 00 ccc eee tent eens 3 4 Instruction Set iiicise mee eet aep baka uc dede e ed Rd de ao 3 4 1 Double Operand Format I Instructions 0 0 0 0 cece eee eee 3 4 2 Single Operand Format Il Instructions leslie 3 4 9 Ju mps monies edet ited Oe eet deste eee ste 3 4 4 Instruction Cycles and Lengths 0 0 cece eee teens 3 4 5 Instruction Set Description 0 0 eee 4 Basic Clock Module mr area wie ee E ERE tee hee ee eee E 4 1 Basic Clock Module Introduction 00 cece eee eee teens 4 2 Basic Clock Module Operation 0 00 cc cece eee teen eee eee 4 2 1 Basic Clock Module Features for Low Power Applications 4 2 2 LFXT1 OsolllatOl i iei de cg atiii nimii av aer eee e dtr Faces 42 39 XIZ OSMAN osx Hie cs E Bsn Rotes Bui tee i a a s
295. s 5 0 BEEN NNI FCTLx password Always read as 096h Must be written as 0A5h or a PUC will be generated Flash controller clock source select 00 ACLK 01 MCLK 10 SMCLK 11 SMCLK Flash controller clock divider These six bits select the divider for the flash controller clock The divisor value is FNx 1 For example when FNx 00h the divisor is 1 When FNx OSFh the divisor is 64 Flash Memory Controller 5 19 Flash Memory Registers FCTL3 Flash Memory Control Register FCTL3 15 14 13 12 11 10 9 8 FWKEYx Read as 096h Must be written as 0A5h 7 6 5 4 3 2 l 0 ro ro rw 0 rw 1 r 1 rw 0 rw 0 r w 0 FWKEYx Reserved EMEX LOCK WAIT ACCVIFG KEYV BUSY 5 20 Bits 15 8 Bits 7 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FCTLx password Always read as 096h Must be written as 0A5h or a PUC will be generated Reserved Always read as 0 Emergency exit 0 No emergency exit 1 Emergency exit Lock This bit unlocks the flash memory for writing or erasing The LOCK bit can be set anytime during a byte word write or erase operation and the operation will complete normally In the block write mode if the LOCK bit is set while BLKWRT WAIT 1 then BLKWRT and WAIT are reset and the mode ends normally 0 Unlocked 1 Locked Wait Indicates the flash memory is being written to 0 The flash memory is not ready for the next byte word write 1 The flash memory is ready for the next byte word w
296. s Channels that are not selected are isolated from the A D and the intermediate node is connected to analog ground AVss so that the stray capacitance is grounded to help eliminate crosstalk The ADC12 uses the charge redistribution method When the inputs are internally switched the switching action may cause transients on the input signal These transients decay and settle before causing errant conversion Figure 17 2 Analog Multiplexer R 100 Ohm ADC12MCTLx 0 3 e Ax d xi ESD Protection Analog Port Selection The ADC12 inputs are multiplexed with the port P6 pins which are digital CMOS gates When analog signals are applied to digital CMOS gates parasitic current can flow from Voc to GND This parasitic current occurs if the input voltage is near the transition level of the gate Disabling the port pin buffer eliminates the parasitic current flow and therefore reduces overall current consumption The P6SELx bits provide the ability to disable the port pin input and output buffers P6 0 and P6 1 configured for analog input BIS B 3h amp P6SEL P6 1 and P6 0 ADC12 function ADC12 17 5 ADC 12 Operation 17 2 3 Voltage Reference Generator The ADC12 module contains a built in voltage reference with two selectable voltage levels 1 5 V and 2 5 V Either of these reference voltages may be used internally and externally on pin VREF Setting REFON 1 enables the internal reference When REF2_5V 1 the
297. s When TBR counts to the value in a TBCLx Interrupt flag CCIFG is set Internal signal EQUx 1 Li EQUXx affects the output according to the output mode Timer_B Operation Compare Latch TBCLx The TBCCRx compare latch TBCLx holds the data for the comparison to the timer value in compare mode TBCLx is buffered by TBCCRx The buffered compare latch gives the user control over when a compare period updates The user cannot directly access TBCLx Compare data is written to each TBCCRx and automatically transferred to TBCLx The timing of the transfer from TBCCRx to TBCLx is user selectable with the CLLDx bits as described in Table 12 2 Table 12 2 TBCLx Load Events CLLDx Description 00 New data is transferred from TBCCRx to TBCLx immediately when TBCCRx is written to 01 New data is transferred from TBCCRx to TBCLx when TBR counts to 0 10 New data is transferred from TBCCRx to TBCLx when TBR counts to 0 for up and continuous modes New data is transferred to from TBCCRx to TBCLx when TBR counts to the old TBCLO value or to 0 for up down mode 11 New data is transferred from TBCCRx to TBCLx when TBR counts to the old TBCLx value Grouping Compare Latches Multiple compare latches may be grouped together for simultaneous updates with the TBCLGRPx bits When using groups the CLLDx bits of the lowest numbered TBCCRx in the group determine the load event for each compare latch of the group except when TBCLGRP 3 as
298. s incremented automatically so that program execution continues with the next instruction Comment Valid for source and destination Example MOV EDE TONI Source address EDE OF016h Dest address TONI 01114h Before After Address Register Address Register Space Space Oxxxxh PC OFF16h O11FEh OFF16h O11FEh OFF14h OF102h OFF14h OF102h OFF12h 04090h PC OFF12h 04090h OFF14h OF018h 0F102h OF018h OFO16h OA123h OF016h gFo16h 0A123h OFF16h 1114 01114h 05555h 0 i 01114h OA123h 3 12 RISC 16 Bit CPU 3 3 4 Absolute Mode Addressing Modes The absolute mode is described in Table 3 7 Table 3 7 Absolute Mode Description Assembler Code Content of ROM Length Operation Comment Example Before OFF16h OFF14h OFF12h OF018h OF016h OF014h 01116h 01114h 01112h MOV amp EDE amp TONI MOV X 0 Y 0 X EDE Y TONI Two or three words Move the contents of the source address EDE to the destination address TONI The words after the instruction contain the absolute address of the source and destination addresses With absolute mode the PC is incremented automatically so that program execution continues with the next instruction Valid for source and destination MOV amp EDE amp TONI Source address EDE 0F016h dest address TONI 01114h After Address Register Address Register Space Space Oxxxxh PC 01114h OFF16h 01114h OF016h OFF14h OFO16h
299. s reset until another output mode is selected and affects the output The output is toggled when the timer counts to the TACCRx value It is set when the timer counts to the TACCRO value The output is reset when the timer counts to the TACCRx value It is set when the timer counts to the TACCRO value Timer A 11 13 Timer_A Operation Output Example Timer in Up Mode The OUTx signal is changed when the timer counts up to the TACCRx value and rolls from TACCRO to zero depending on the output mode An example is shown in Figure 11 12 using TACCRO and TACCR1 Figure 11 12 Output Example Timer in Up Mode OFFFFh TACCRO TACCRt Oh Output Mode 1 Set Output Mode 2 Toggle Reset Output Mode 3 Set Reset Output Mode 4 Toggle Output Mode 5 Reset Output Mode 6 Toggle Set Output Mode 7 Reset Set EQUO EQUI EQUO EQUI EQUO TAIFG TAIFG TAIFG IRISITUPPEVBITIS 11 14 Timer A Timer_A Operation Output Example Timer in Continuous Mode The OUTx signal is changed when the timer reaches the TACCRx and TACCRO values depending on the output mode An example is shown in Figure 11 13 using TACCRO and TACCR1 Figure 11 13 Output Example Timer in Continuous Mode OFFFFh TACCRO TACCR1 Oh TAIFG EQU1 EQUO TAIFG EQU1 EQUO Interrupt Events Timer A 11 15 Timer_A Operation Output Example Timer in Up Down Mode The OUTx signal cha
300. set or clear the IEx and IFGx bits using BIS B or BIC B instructions rather than MOV B or CLR B instructions ee USART Peripheral Interface SPI Mode 14 13 USART Registers SPI Mode UxCTL USART Control Register 7 6 5 4 3 2 1 0 eet wot oan umm swe om 9mm rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 1 Unused Bits Unused 7 6 I2ct Bit 5 I2C mode enable This bit selects 12C or SPI operation when SYNC 1 0 SPI mode 1 12C mode CHAR Bit 4 Character length 0 7 bit data 1 8 bit data LISTEN Bit 3 Listen enable The LISTEN bit selects the loopback mode 0 Disabled 1 Enabled The transmit signal is internally fed back to the receiver SYNC Bit 2 Synchronous mode enable 0 UART mode 1 SPI mode MM Bit 1 Master mode 0 USART is slave 1 USART is master SWRST Bit 0 Software reset enable 0 Disabled USART reset released for operation 1 Enabled USART logic held in reset state t Applies to USARTO on MSP430x15x and MSP430x16x devices only 14 14 USART Peripheral Interface SPI Mode USART Registers SPI Mode UxTCTL USART Transmit Control Register 7 rw 0 rw 0 CKPH CKPL SSELx Unused Unused STC TXEPT Bit 7 Bit 6 Bits 5 4 Bit 3 Bit 2 Bit 1 Bit 0 5 4 3 2 1 0 rw 0 rw 1 rw 0 rw 0 rw 0 rw 0 Clock phase select Controls the phase of UCLK 0 Normal UCLK clocking scheme 1 UCLK is delayed by one half cycle Clock polarity select 0 The inactive level is low data is output with the risin
301. sly The ADC results are written to the ADC12MEMXx defined by the CSTARTADDx bits It is necessary to read the result after the completed conversion because only one ADC12MEMx memory is used and is overwritten by the next conversion Figure 17 8 shows repeat single channel mode Figure 17 8 Hepeat Single Channel Mode CONSEQx 10 ADC120N 1 ENC 4 x CSTARTADDx Wait for Enable SHSx 0 and ENC 10r4 and ADC12SC Wait for Trigger SAMPCON 4 ENC 0 SAMPCON 1 Sample Input Channel Defined in ADC12MCTLx SAMPCON Y 12 x ADC12CLK MSC 1 and SHP 1 and ENC 1 1 x ADC12CLK Conversion Completed Result Stored Into ADC12MEMXx ADC12IFG x is Set x pointer to ADC12MCTLx ADC 12 17 13 ADC 12 Operation Repeat Sequence of Channels Mode A sequence of channels is sampled and converted repeatedly The ADC results are written to the conversion memories starting with the ADC12MEMx defined by the CSTARTADDx bits The sequence ends after the measurement of the channel with a set EOS bit and the next trigger signal re starts the sequence Figure 17 9 shows the repeat sequence of channels mode Figure 17 9 Repeat Sequence of Channels Mode CONSEQx 11 ADC120N 1 ENC 4 x CSTARTADDx Wait for Enable SHSx 0 and ENC 10r and ADC12SC 4 Wait for Trigger ENC 0 and EOS x 1 SAMPCON 4 SAMPC
302. source and a separate buffer The current consumption of each is specified separately in the device specific datasheet When REFON 1 both are enabled and when REFON 0 both are disabled The total settling time when REFON becomes set is lt 30 us When REFON 1 but no conversion is active the buffer is automatically disabled and automatically re enabled when needed When the buffer is disabled it consumes no current In this case the band gap voltage source remains enabled When REFOUT 1 the REFBURST bit controls the operation of the internal reference buffer When REFBURST 0 the buffer will be on continuously allowing the reference voltage to be present outside the device continuously When REFBURST 1 the buffer is automatically disabled when the ADC10 is not actively converting and automatically re enabled when needed The internal reference buffer also has selectable speed vs power settings When the maximum conversion rate is below 50 ksps setting ADC10SR 1 reduces the current consumption of the buffer approximately 5096 18 2 4 Auto Power Down 18 6 ADC10 The ADC10 is designed for low power applications When the ADC10 is not actively converting the core is automatically disabled and automatically re enabled when needed The ADC10OSC is also automatically enabled when needed and disabled when not needed When the core or oscillator are disabled they consume no current ADC10 Operation 18 2 5 Sample and
303. src dst AND B src dst BIC B src dst BIS B src dst BIT B sre dst BR dst CALL dst CIR B dst cuRct CLRNT CLRZ CMP B src dst DADC B T dst DADD B src dst pnEC B T dst DECD B T dst pintt EINT Nc B T dst Ncp B T dst Nv B T dst JC JHS abe JEQ JZ abe JGE abe JL abe JMP abe JN abe JNC JLO abe JNE JNZ abe MOV B src dst nopt POP B T dst PUSH B src nETT RETI RLA B T dst RLC B T dst RRA B dst RRC B dst sBC B T dst sETCT SETN SETZ SUB B src dst SUBC B src dst SWPB dst SXT dst TsT B T dst XOR B src dst T Emulated Instruction Description Add C to destination Add source to destination Add source and C to destination AND source and destination Clear bits in destination Set bits in destination Test bits in destination Branch to destination Call destination Clear destination Clear C Clear N Clear Z Compare source and destination Add C decimally to destination Add source and C decimally to dst Decrement destination Double decrement destination Disable interrupts Enable interrupts Increment destination Double increment destination Invert destination Jump if C set Jump if higher or same Jump if equal Jump if Z set Jump if greater or equal Jump if less Jump Jump if N set Jump if C not set Jump if lower Jump if not equal Jump if Z not set Move source to destination No operation Pop item from stack to dest
304. sses are permissible and the high byte of the result is always 0 The address space from 010h to OFFh is reserved for 8 bit peripheral modules These modules should be accessed with byte instructions Read access of byte modules using word instructions results in unpredictable data in the high byte If word data is written to a byte module only the low byte is written into the peripheral register ignoring the high byte 1 4 4 Special Function Registers SFRs Some peripheral functions are configured in the SFRs The SFRs are located in the lower 16 bytes of the address space and are organized by byte SFRs must be accessed using byte instructions only See the device specific data sheets for applicable SFR bits 1 4 5 Memory Organization Bytes are located at even or odd addresses Words are only located at even addresses as shown in Figure 1 3 When using word instructions only even addresses may be used The low byte of a word is always an even address The high byte is at the next odd address For example if a data word is located at address xxx4h then the low byte of that data word is located at address xxx4h and the high byte of that word is located at address xxx5h Figure 1 3 Bits Bytes and Words in a Byte Organized Memory xxxAh xxx9h xxx8h xxx7h xxx6h Word High Byte xxxbh Word Low Byte xxx4h Introduction 1 5 IET a System Resets Interrupts and Operating Modes This chapter describes the
305. st PC TOS gt SR SP 2 gt SP TOS gt PC SP 2 gt SP Bit 7 gt Bit 8 Bit 15 The status bit is affected The status bit is not affected 0 The status bit is cleared 1 The status bit is set Status Bits V N Z C 0 0 All addressing modes are possible for the CALL instruction If the symbolic mode ADDRESS the immediate mode N the absolute mode amp EDE or the indexed mode x RN is used the word that follows contains the address information RISC 16 Bit CPU 3 19 Instruction Set 3 4 3 Jumps Figure 3 11 shows the conditional jump instruction format Figure 3 11 Jump Instruction Format i15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 3 13 lists and describes the jump instructions Table 3 13 Jump Instructions Mnemonic S Reg D Reg Operation JEQ JZ Label Jump to label if zero bit is set JNE JNZ Label Jump to label if zero bit is reset JC Label Jump to label if carry bit is set JNC Label Jump to label if carry bit is reset JN Label Jump to label if negative bit is set JGE Label Jump to label if N XOR V 2 0 JL Label Jump to label if N XOR V 1 JMP Label Jump to label unconditionally Conditional jumps support program branching relative to the PC and do not affect the status bits The possible jump range is from 511 to 512 words relative to the PC value at the jump instruction The 10 bit program counter offset is treated as a signed 10 bit value that is doub
306. st SUBC B 0 dst The carry bit C is added to the destination operand minus one The previous contents of the destination are lost N Set if result is negative reset if positive Z Set if result is zero reset otherwise C Set if there is a carry from the MSB of the result reset otherwise Set to 1 if no borrow reset if borrow V Set if an arithmetic overflow occurs reset otherwise OSCOFF CPUOFF and GIE are not affected The 16 bit counter pointed to by R13 is subtracted from a 32 bit counter pointed to by R12 SUB R13 0 R12 Subtract LSDs SBC 2 R12 Subtract carry from MSD The 8 bit counter pointed to by R13 is subtracted from a 16 bit counter pointed to by R12 SUB B R13 0 R12 Subtract LSDs SBC B 1 R12 Subtract carry from MSD Note Borrow Implementation The borrow is treated as a NOT carry Borrow Carry bit Yes 0 No 1 3 62 RISC 16 Bit CPU SETC Syntax Operation Emulation Description Status Bits Mode Bits Example DSUB Instruction Set Set carry bit SETC 1 gt C BIS 1 SR The carry bit C is set N Not affected Z Not affected C Set V Not affected OSCOFF CPUOFF and GIE are not affected Emulation of the decimal subtraction Subtract R5 from R6 decimally Assume that R5 03987h and R6 04137h ADD 06666h R5 Move content R5 from 0 9 to 6 0Fh R5 03987h 06666h 09FEDh INV R5 Invert this result back to 0 9 R5 NOT R5 06012h S
307. sters sseeseeeen nnn 5 1 Flash Memory Introduction 5 1 Flash Memory Introduction The MSP430 flash memory is bit byte and word addressable and programmable The flash memory module has an integrated controller that controls programming and erase operations The controller has three registers a timing generator and a voltage generator to supply program and erase voltages MSP430 flash memory features include Lj Internal programming voltage generation Bit byte or word programmable Ultralow power operation _j Segment erase and mass erase The block diagram of the flash memory and controller is shown in Figure 5 1 V7 1 Note Minimum Vcc During Flash Write or Erase The minimum Vcc voltage during a flash write or erase operation is 2 7 V If Vcc falls below 2 7 V during a write or erase the result of the write or erase will be unpredictable Figure 5 1 Flash Memory Module Block Diagram 5 2 Address Latch Data Latch t Enable Address Latch Timing Generator Enable Data Latch Programming Voltage Generator Flash Memory Controller Flash Memory Segmentation 5 2 Flash Memory Segmentation MSP430 flash memory is partitioned into segments Single bits bytes or words can be written to flash memory but the segment is the smallest size of flash memory that can be erased The flash memory is partitioned into main and information memory sect
308. stores information about the result The result is ready in three MCLK cycles and can be read with the next instruction after writing to OP2 except when using an indirect addressing mode to access the result When using indirect addressing for the result a NOP is required before the result is ready 7 2 1 Operand Registers The operand one register OP1 has four addresses shown in Table 7 1 used to select the multiply mode Writing the first operand to the desired address selects the type of multiply operation but does not start any operation Writing the second operand to the operand two register OP2 initiates the multiply operation Writing OP2 starts the selected operation with the values stored in OP1 and OP2 The result is written into the three result registers RESLO RESHI and SUMEXT Repeated multiply operations may be performed without reloading OP1 if the OP1 value is used for successive operations It is not necessary to re write the OP1 value to perform the operations Table 7 1 OP1 addresses OP1 Address Register Name Operation 0130h MPY Unsigned multiply 0132h MPYS Signed multiply 0134h MAC Unsigned multiply accumulate 0136h MACS Signed multiply accumulate Hardware Multiplier 7 3 Hardware Multiplier Operation 7 2 2 Result Registers The result low register RESLO holds the lower 16 bits of the calculation result The result high register RESHI contents depend on the multiply operation and are listed in Table 7 2
309. structions 0 No interrupt pending 1 Interrupt pending Watchdog Timer Chapter 11 Timer_A Timer_A is a 16 bit timer counter with three capture compare registers This chapter describes Timer_A Timer_A is implemented in all MSP430x1xx devices Topic Page 11 1 Timer A Introduction ree riis Eee 11 2 11 2 TIMER A Operation toe MT 11 3 fimsr A Registers eoe ue onu mE Eo ere d 11 19 Timer_A Introduction 11 1 Timer_A Introduction 11 2 Timer_A Timer_A is a 16 bit timer counter with three capture compare registers Timer_A can support multiple capture compares PWM outputs and interval timing Timer_A also has extensive interrupt capabilities Interrupts may be generated from the counter on overflow conditions and from each of the capture compare registers Timer_A features include Asynchronous 16 bit timer counter with four operating modes Selectable and configurable clock source Three configurable capture compare registers Configurable outputs with PWM capability Asynchronous input and output latching L LOL iD Interrupt vector register for fast decoding of all Timer A interrupts The block diagram of Timer A is shown in Figure 11 1 Note Use of the Word Count Count is used throughout this chapter It means the counter must be in the process of counting for the action to take place If a particular value is directly written to the counter then an associated action will
310. t first stopping a transfer by issuing a repeated START condition This is called a RESTART After a RESTART is issued the slave address is again sent out with the new data direction specified by the R W bit The RESTART condition is shown in Figure 15 7 Figure 15 7 12C Module Addressing Format with Repeated START Condition DEL o esse gg us ED Slave Address L Slave Address a ale Any gt le ole Any Number Number USART Peripheral Interface I C Mode 15 7 12C Module Operation 15 2 4 12C Module Operating Modes The 12C module operates in master transmitter master receiver slave transmitter or slave receiver mode Master Mode In master mode transmit and receive operation is controlled with the I2CRM I2CSTT and I2CSTP bits as described in Table 15 1 The master transmitter and master receiver modes are shown in Figure 15 8 and Figure 15 9 SCL is held low when the intervention of the CPU is required after a byte has been received or transmitted Table 15 1 Master Operation I2CRM lI2CSTP X 0 0 0 0 1 1 0 0 1 I2CSTT 0 15 8 USART Peripheral Interface 2C Mode Condition Or Bus Activity The 12C module is in master mode but is idle No START or STOP condition is generated Setting I2CSTT initiates activity IACNDAT is used to determine length of transmission A STOP condition is not automatically generated after the I2CNDAT number of bytes have been transferred Software must set I2CSTP to g
311. t not the task handling itself The latencies are LJ ADC12IFGO ADC121FG14 ADC12TOV and ADC12OV 16 cycles J ADC12IFG15 14 cycles The interrupt handler for ADC121FG15 shows a way to check immediately if a higher prioritized interrupt occurred during the processing of ADC12IFG15 This saves nine cycles if another ADC12 interrupt is pending Interrupt handler for ADC12 INT ADC12 Enter Interrupt Service Routine 6 ADD amp ADC121V PC Add offset to PC 3 RETI Vector 0 No interrupt 5 JMP ADOV Vector 2 ADC overflow 2 JMP ADTOV Vector 4 ADC timing overflow 2 JMP ADMO Vector 6 ADCI2IFGO 2 ae Vectors 8 32 2 JMP ADM14 Vector 34 ADC12IFG14 2 Handler for ADC12IFG15 starts here No JMP required ADM15 MOV amp ADC12MEM15 xxx Move result flag is reset aed Other instruction needed JMP INT ADC12 Check other int pending ADC12IFG14 ADC12IFG1 handlers go here f ADMO MOV amp ADC12MEM0 xxx Move result flag is reset Other instruction needed RETI Return 5 ADTOV m Handle Conv time overflow RETI Return 5 ADOV das Handle ADCMEMx overflow RETI Return 5 ADC12 17 19 ADC 12 Registers 17 3 ADC12 Registers The ADC12 registers are listed in Table 17 2 Table 17 2 ADC12 Registers Register Short Form Register Type Address Initial State ADC12 control register 0 ADC12CTLO Read write 01A0h Reset with POR ADC12 control register 1 ADC12CTL1 Read write 01A2h Reset with POR ADC12 interrupt flag
312. t operand Rn is incremented afterwards by 1 for B instructions and by 2 for W instructions 11 Immediate mode N The word following the instruction contains the immediate constant N Indirect autoincrement mode PC is used The seven addressing modes are explained in detail in the following sections Most of the examples show the same addressing mode for the source and destination but any valid combination of source and destination addressing modes is possible in an instruction Note Use of Labels EDE TONI TOM and LEO Throughout MSP430 documentation EDE TONI TOM and LEO are used as generic labels They are only labels They have no special meaning RISC 16 Bit CPU 3 9 Addressing Modes 3 3 4 Register Mode The register mode is described in Table 3 4 Table 3 4 Register Mode Description Assembler Code Content of ROM MOV R10 R11 MOV R10 R11 Length One or two words Operation Move the content of R10 to R11 R10 is not affected Comment Valid for source and destination Example MOV R10 R11 Before After Note Data in Registers The data in the register can be accessed using word or byte instructions If byte instructions are used the high byte is always 0 in the result The status bits are handled according to the result of the byte instruction 3 10 RISC 16 Bit CPU Addressing Modes 3 3 2 Indexed Mode The indexed mode is described in Table 3 5 Table 3 5 Indexed Mode Description
313. t src dst C dst SUB B src dst dst not src 1 dst SUBC B src dst dst not src C dst CMP B src dst dst src DADD B src dst Src dst C dst decimally BIT B src dst src and dst 0 d t BIC B src dst notsrc and dst dst BIS B src dst src or dst dst XOR B src dst Src xor dst gt dst s n B AND B src dst src and dst dst 0 2 ii 7 The status bit is affected The status bit is not affected O The status bit is cleared The status bit is set rss v_sv_s s serernwr vr vsvreereeerrersrerswrerererrereree s raererereeeeerwererrerereeeerererrrseeererereermeeererereeererereeerrrerreeererwrwvet Note Instructions CMP and SUB The instructions CMP and SUB are identical except for the storage of the result The same is true for the BIT and AND instructions Ea i i sss 3 18 RISC 16 Bit CPU 3 4 2 Single Operand Format Il Instructions Figure 3 10 illustrates the single operand instruction format Figure 3 10 Single Operand Instruction Format 15 14 13 12 10 9 8 7 6 5 4 Instruction Set 3 2 1 0 Table 3 12 lists and describes the single operand instructions Table 3 12 Single Operand Instructions Mnemonic S Reg D Reg RRC B dst RRA B dst PUSH B src SWPB dst CALL dst RETI SXT dst Operation C gt MSB LSB gt C MSB gt MSB 5 LSB5 C SP 2 gt SP src SP Swap bytes SP 2 gt SP PC 2 5 SP d
314. t with the modulator to meet timing requirements when a non integer divisor is needed Timing of each bit is expanded by one BRCLK clock cycle if the modulator bit m is set Each time a bit is received or transmitted the next bit in the modulation control register determines the timing for that bit A set modulation bit increases the division factor by one while a cleared modulation bit maintains the division factor given by UxBR The timing for the start bit is determined by UxBR plus mO the next bit is determined by UxBR plus m1 and so on The modulation sequence begins with the LSB When the character is greater than 8 bits the modulation sequence restarts with mO and continues until all bits are processed Determining the Modulation Value 13 12 Determining the modulation value is an interactive process Using the timing error formula provided beginning with the start bit the individual bit errors are calculated with the corresponding modulator bit set and cleared The modulation bit setting with the lower error is selected and the next bit error is calculated This process is continued until all bit errors are minimized When a character contains more than 8 bits the modulation bits repeat For example the 9th bit of a character uses modulation bit 0 USART Peripheral Interface UART Mode USART Operation UART Mode Transmit Bit Timing The timing for each character is the sum of the individual bit timings By modulating eac
315. ted 1 The sample input signal is inverted ADC10 18 27 ADC10 Registers ADC10DIVx Bits ADC10 clock divider 7 5 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111 8 ADC10 Bits ADC10 clock source select SSELx 4 3 00 ADC100SC 01 ACLK 10 MCLK 11 SMCLK CONSEQx Bits Conversion sequence mode select 2 1 00 Single channel single conversion 01 Sequence of channels 10 Repeatsingle channel 11 Repeat sequence of channels ADC10 Bit 0 ADC10 busy This bit indicates an active sample or conversion operation BUSY O No operation is active 1 A sequence sample or conversion is active ADC10AE Analog Input Enable Control Register T 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 ADC10AEx Bits ADC10 analog enable 7 0 0 Analog input disabled 1 Analog input enabled 18 28 ADC10 ADC10 Registers ADC10MEM Conversion Memory Register Binary Format 15 14 13 12 11 10 9 8 ro ro ro ro ro ro r r 7 6 5 4 3 2 1 0 Conversion Results r r r r r r r r Conversion Bits The 10 bit conversion results are right justified straight binary format Bit 9 Results 15 0 is the MSB Bits 15 10 are always 0 ADC10MEM Conversion Memory Register 2 s Complement Format 1 5 14 13 12 11 10 9 8 r r r r r r r r 7 6 5 4 3 2 1 0 I III r r ro ro ro ro ro ro Conversion Bits The 10 bit conversion results are left justified 2 s complement format Bit 15 Results 15 0 is the MSB Bits 5 0 are always 0
316. ted in MSP430x11x1 MSP430x12x MSP430x13x MSP430x14x MSP430x15x and MSP430x16x devices Topic Page 16 1 Comparator A Introduction Lssleuueseeeuuee 16 2 16 2 Comparator A Operation eee 16 4 16 34 GomparatorSAdRegistersuq ccc P CPPEPPEPEEIS EIE Eee 16 9 16 1 Comparator_A Introduction 16 1 Comparator_A Introduction The comparator A module supports precision slope analog to digital conversions supply voltage supervision and monitoring of external analog signals Features of Comparator_A include Inverting and non inverting terminal input multiplexer Software selectable RC filter for the comparator output Output provided to Timer_A capture input Software control of the port input buffer Interrupt capability Selectable reference voltage generator LE L L S Oo Q Comparator and reference generator can be powered down The Comparator A block diagram is shown in Figure 16 1 16 2 Comparator A Comparator_A Introduction Figure 16 1 Comparator A Block Diagram Voc 0V P2CA0 CAEX NU of CAON O l CAF CA0 O EN r CCI1B CAOUT CA1 O NE 19 1 t X Set CAIFG P2CA1 Tau 2 0us CAREFx CARSEL 0 5x VCC 0 25x Voc KEW ac Comparator_A 16 3 Comparator_A Operation 16 2 Comparator_A Operation 16 2 1 Comparator The com
317. ted reference voltage via the DAC12 IR bit This feature allows the user to control the dynamic range of the DAC12 The DAC12DF bit allows the user to select between straight binary data and 2 s compliment data for the DAC When using straight binary data format the formula for the output voltage is given in Table 19 1 Table 19 1 DAC12 Full Scale Range Vref VaRer or VREF Resolution DAC12RES DAC12IR Output Voltage Formula 12 bit 0 0 DAC12_xDAT 12 bit 0 1 DAC12_xDAT Vout Vref x 1096 BO a Vout Vref x 3 x DACIA XDA 256 8 bit 1 1 DAC12_xDAT Vout Vref x 956 In 8 bit mode the maximum useable value for DAC12 xDAT is OFFh and in 12 bit mode the maximum useable value for DAC12 xDAT is OFFFh Values greater than these may be written to the register but all leading bits are ignored DAC12 Port Selection The DAC12 outputs are multiplexed with the port P6 pins and ADC12 analog inputs When DAC12AMPx gt 0 the DAC12 function is automatically selected for the pin regardless of the state of the associated PeSELx and P6DIRx bits 19 4 DAC12 DAC 12 Operation 19 2 2 DAC12 Reference The reference for the DAC12 is configured to use either an external reference voltage or the internal 1 5 V 2 5 V reference from the ADC12 module with the DAC12SREFx bits When DAC12SREFx 0 1 the Vgef signal is used as the reference and when DAC12SREFx 2 3 the Vengr signal is used as the reference To use the ADC12 internal refer
318. terrupt flag ADC12MENG interrupt flag ADC12MEM 10 interrupt flag ADC12MEM11 interrupt flag ADC12MEM 12 interrupt flag ADC12MEM 13 interrupt flag ADC12MEM 14 interrupt flag ADC12MEM 15 interrupt flag Interrupt Interrupt Flag Priority ADC12IFGO ADC12IFG1 ADC12IFG2 ADC12IFGS3 ADC12IFG4 ADC12IFG5 ADC12IFG6 ADC12IFG7 ADC12IFG8 ADC12IFG9 ADC12IFG10 ADC12IFG11 ADC12IFG12 ADC12IFG13 ADC12IFG14 ADC12IFG15 ADC12 Highest Lowest 17 27 ADC10 The ADC10 module is a high performance 10 bit analog to digital converter This chapter describes the ADC10 The ADC10 is implemented in the MSP430x11x2 MSP430x12x2 devices Topic Page 18 1 ADC10 Introd ction 5 9 verre UU 18 2 18 2 ADC10 Operation EE el ete eee rel E 18 4 18 3 ADC IO Registers cee ca E mesa eens 18 24 18 1 ADC10 Introduction 18 1 ADC10 Introduction 18 2 ADC10 The ADC10 module supports fast 10 bit analog to digital conversions The module implements a 10 bit SAR core sample select control reference generator and data transfer controller DTC The DTC allows ADC10 samples to be converted and stored anywhere in memory without CPU intervention The module can be configured with user software to support a variety of applications ADC10 features include L L1 L O m m Greater than 200 ksps maximum conversion rate Monotonic10 bit converter with no missing codes Sample and hold wit
319. terrupt service routine The mode control bits and the stack can be accessed with any instruction When setting any of the mode control bits the selected operating mode takes effect immediately Peripherals operating with any disabled clock are disabled until the clock becomes active The peripherals may also be disabled with their individual control register settings All I O port pins and RAM registers are unchanged Wake up is possible through all enabled interrupts 2 14 System Resets Interrupts and Operating Modes Operating Modes Figure 2 10 MSP430x1xx Operating Modes For Basic Clock System RST NMI Reset Active WDT Time Expired Overflow WDTIFG 1 WDTIFG 1 WDT Active Security Key Violation WDTIFG 0 RST NMI is Reset Pin WDT is Active RST NMI NMI Active Active Mode CPUOFF 1 CPU Is Active CPUOFF 1 SCG0 0 Peripheral Modules Are Active OSCOFF 1 SCG1 0 SCGO 1 LPMO CPU Off MCLK Off SMCLK On ACLK On CPUOFF 1 SCGO 1 SCG1 0 SCGO LPM1 CPU Off MCLK Off SMCLK On ACLK On DC Generator Off if DCO not used in active mode CPUOFF 1 0 SCG1 1 CPU Off MCLK Off SMCLK Off DCO Off ACLK On SCG1 1 LPM4 CPU Off MCLK Off DCO Off ACLK Off CPUOFF 1 DC Generator Off SCGO 1 SCG1 1 LPM3 CPU Off MCLK Off SMCLK Off DCO Off ACLK On LPM2
320. th the BLKWRT WRT MERAS and ERASE bits and are Byte word write Block write Segment Erase Mass Erase all main memory segments L L L L All Erase all segments Reading or writing to flash memory while it is being programmed or erased is prohibited If CPU execution is required during the write or erase the code to be executed must be in RAM Any flash update can be initiated from within flash memory or RAM 5 3 4 Flash Memory Timing Generator Write and erase operations are controlled by the flash timing generator shown in Figure 5 3 The flash timing generator operating frequency f FTG must be in the range from 257 kHz to 476 kHz see device specific datasheet Figure 5 3 Flash Memory Timing Generator Block Diagram ACLK MCLK SMCLK SMCLK FSSELx Reset Divider 1 64 Flash Timing Generator BUSY WAIT The flash timing generator can be sourced from ACLK SMCLK or MCLK The selected clock source should be divided using the FNx bits to meet the frequency requirements for ffrae If the fprG frequency deviates from the specification during the write or erase operation the result of the write or erase may be unpredictable or the flash memory may be stressed above the limits of reliable operation 5 4 Flash Memory Controller Flash Memory Operation 5 3 2 Erasing Flash Memory The erased level of a flash memory bit is 1 Each bit can be programmed from 1 to 0 individually but to reprogram from O0 to
321. the POR detect and POR delay circuits The brownout reset circuit detects low supply voltages such as when a supply voltage is applied to or removed from the Vcc terminal The brownout reset circuit resets the device by triggering a POR signal when power is applied or removed The operating levels are shown in Figure 2 3 The POR signal becomes active when Vcc crosses the Vcc start level It remains active until Vcc crosses the V g jr threshold and the delay t BOR elapses The delay t gop is adaptive being longer for a slow ramping Vcc The hysteresis Vnys g jr ensures that the supply voltage must drop below V B_IT to generate another POR signal from the brownout reset circuitry Figure 2 3 Brownout Timing VCC start Set Signal for POR circuitry lt gt BOR As the V g jr level is significantly above the Vmin level of the POR circuit the BOR provides a reset for power failures where Vcc does not fall below Vmin See device specific datasheet for parameters 2 4 System Resets Interrupts and Operating Modes System Reset and Initialization 2 1 3 Device Initial Conditions After System Reset After a POR the initial MSP430 conditions are Ll m Software Initialization The RST NMI pin is configured in the reset mode I O pins are switched to input mode as described in the Digital I O chapter Other peripheral modules and registers are initialized as described in their respective chapters in
322. the basic clock module The basic clock module is implemented in all MSP430x1xx devices Topic Page 4 1 Basic Clock Module Introduction 4 4 2 Basic Clock Module Operation 00cceeee eee 4 4 4 3 Basic Clock Module Registers 02 00200eee eee 4 14 4 1 Basic Clock Module Introduction 4 1 Basic Clock Module Introduction 4 2 The basic clock module supports low system cost and ultralow power consumption Using three internal clock signals the user can select the best balance of performance and low power consumption The basic clock module can be configured to operate without any external components with one external resistor with one or two external crystals or with resonators under full software control The basic clock module includes two or three clock sources J LFXT1CLK Low frequency high frequency oscillator that can be used either with low frequency 32768 Hz watch crystals or standard crystals or resonators in the 450 kHz to 8 MHz range XT2CLK Optional high frequency oscillator that can be used with standard crystals resonators or external clock sources in the 450 kHz to 8 MHz range DCOCLK Internal digitally controlled oscillator DCO with RC type characteristics Three clock signals are available from the basic clock module ACLK Auxiliary clock The ACLK is the buffered LFXT1CLK clock source divided by 1 2 4 or 8
323. tination Comment Valid only for a source operand Example MOV 45h TONI Before After Address Register Address Register Space Space OFF18h Oxxxxh PC OFF16h 01192h OFF16h 01192h OFF14h 00045h OFF14h 00045h OFF12h 040B0h PC OFF12h 040BOh OFF16h 010AAh 401192h 010AAh 010A8h 01234h 010A8h dtoash 00045h 3 16 RISC 16 Bit CPU Instruction Set 3 4 Instruction Set The complete MSP430 instruction set consists of 27 core instructions and 24 emulated instructions The core instructions are instructions that have unique op codes decoded by the CPU The emulated instructions are instructions that make code easier to write and read but do not have op codes themselves instead they are replaced automatically by the assembler with an equivalent core instruction There is no code or performance penalty for using emulated instruction There are three core instruction formats Dual operand Single operand _j Jump All single operand and dual operand instructions can be byte or word instructions by using B or W extensions Byte instructions are used to access byte data or byte peripherals Word instructions are used to access word data or word peripherals If no extension is used the instruction is a word instruction The source and destination of an instruction are defined by the following fields src The source operand defined by As and S reg dst The destination operand defined by Ad a
324. tion Status Bits Mode Bits Example Example Instruction Set Add carry decimally to destination Add carry decimally to destination DADC dst or DADC W src dst DADC B dst dst C gt dst decimally DADD 0 dst DADD B 0 dst The carry bit C is added decimally to the destination N Set if MSB is 1 Z Set if dst is 0 reset otherwise C Set if destination increments from 9999 to 0000 reset otherwise Set if destination increments from 99 to 00 reset otherwise V Undefined OSCOFF CPUOFF and GIE are not affected The four digit decimal number contained in R5 is added to an eight digit deci mal number pointed to by R8 CLRC Reset carry next instruction s start condition is defined DADD R5 0 R8 Add LSDs C DADC 2 R8 Add carry to MSD The two digit decimal number contained in R5 is added to a four digit decimal number pointed to by R8 CLRC Reset carry next instruction s start condition is defined DADD B R5 0 R8 Add LSDs C DADC 1 R8 Add carry to MSDs RISC 16 Bit CPU 3 35 Instruction Set DADD W DADD B Syntax Operation Description Status Bits Mode Bits Example Example Source and carry added decimally to destination Source and carry added decimally to destination DADD src dst or DADD W src dst DADD B src dst src dst C gt dst decimally The source operand and the destination operand are treated as four binary coded decimals BCD wit
325. tion ADC appropriate printed circuit board layout and grounding techniques should be followed to eliminate ground loops unwanted parasitic effects and noise Ground loops are formed when return current from the A D flows through paths that are common with other analog or digital circuitry If care is not taken this current can generate small unwanted offset voltages that can add to or subtract from the reference or input voltages of the A D converter The connections shown in Figure 18 15 help avoid this In addition to grounding ripple and noise spikes on the power supply lines due to digital switching or switching power supplies can corrupt the conversion result A noise free design is important to achieve high accuracy Figure 18 16 ADC10 Grounding and Noise Considerations 18 22 ADC10 gt Power Supply Decoupling Moe agn MSP430F12x2 MSP430F11x2 Ve REF External Reference VREF ADC10 Operation 18 2 10 ADC10 Interrupts One interrupt and one interrupt vector are associated with the ADC10 as shown in Figure 18 17 When the DTC is not used ADC10DTC1 0 ADC10IFG is set when conversion results are loaded into ADC10MEM When DTC is used ADC10DTC1 gt 0 ADC1OIFG is set when a block transfer completes and the internal transfer counter n 0 If both the ADC10IE and the GIE bits are set then the ADC10IFG flag generates an interrupt request The ADC10IFG flag is automatical
326. tions 0 Interrupt not enabled 1 Interrupt enabled These bits may be used by other modules See device specific datasheet Watchdog timer interrupt enable This bit enables the WDTIFG interrupt for interval timer mode It is not necessary to set this bit for watchdog mode Because other bits in IE1 may be used for other modules it is recommended to set or clear this bit using BIS B or BIC B instructions rather than MOV B or CLR B instructions 0 Interrupt not enabled 1 Interrupt enabled Watchdog Timer 10 9 Watchdog Timer Registers IFG1 Interrupt Flag Register 1 7 6 5 4 3 2 1 0 rw 0 rw 0 NMIIFG WDTIFG 10 10 Bits 7 5 Bit 4 Bits 3 1 Bit 0 These bits may be used by other modules See device specific datasheet NMI interrupt flag NMIIFG must be reset by software Because other bits in IFG1 may be used for other modules it is recommended to clear NMIIFG by using BIS BOrBIC B instructions rather than MOV B or CLR B instructions 0 No interrupt pending 1 Interrupt pending These bits may be used by other modules See device specific datasheet Watchdog timer interrupt flag In watchdog mode WDTIFG remains set until reset by software In interval mode WDTIFG is reset automatically by servicing the interrupt or can be reset by software Because other bits in IFG1 may be used for other modules it is recommended to clear WDTIFG by using BIS B Or BIC B instructions rather than MOV B or CLR B in
327. ts Example Example Example Instruction Set Test bits in destination Test bits in destination BIT src dst or BITW src dst src AND dst The source and destination operands are logically ANDed The result affects only the status bits The source and destination operands are not affected N Set if MSB of result is set reset otherwise Z Set if result is zero reset otherwise C Set if result is not zero reset otherwise NOT Zero V Reset OSCOFF CPUOFF and GIE are not affected If bit 9 of R8 is set a branch is taken to label TOM BIT 0200h R8 bit 9 of R8 set JNZ TOM Yes branch to TOM No proceed If bit 3 of R8 is set a branch is taken to label TOM BIT B 8 R8 JC TOM A serial communication receive bit RCV is tested Because the carry bit is equal to the state of the tested bit while using the BIT instruction to test a single bit the carry bit is used by the subsequent instruction the read information is shifted into register RECBUF Serial communication with LSB is shifted first XXXX XXXX XXXX XXXX BIT B RCV RCCTL Bit info into carry RRC RECBUF Carry gt MSB of RECBUF 5 CXXX XXXX T repeat previous two instructions PET 8 times CCCC CCCC A A MSB LSB Serial communication with MSB shifted first BIT B RCV RCCTL Bit info into carry RLC B RECBUF Carry gt LSB of RECBUF XXXX XXXC X repeat previous two instructions mM 8 times CCCC CCCC il LSB MSB
328. ts and watchdog gt Setup flash controller gt Set BLKWRT WRT 1 Write byte or word Block Border Set BLKWRT 0 Set WRT 0 LOCK 1 re enable interrupts and WDT 5 12 Flash Memory Controller L1 L2 L3 L4 Flash Memory Operation Write one block starting at OFOOOh Must be executed from RAM Assumes Flash is already erased 514 kHz SMCLK 952 kHz Assumes ACCVIE NMIIE OFIE 0 MOV 32 R5 Use as write counter MOV 0F000h R6 Write pointer MOV WDTPW WDTHOLD amp WDTCTL Disable WDT DINT Disable interrupts BIT BUSY amp FCTL3 Test BUSY JNZ L1 Loop while busy MOV FWKEY FSSEL1 FNO amp FCTL2 SMCLK 2 MOV FWKEY amp FCTL3 Clear LOCK MOV FWKEY BLKWRT WRT amp FCTL1 Enable block write MOV Write Value 0 R6 Write location BIT WAIT amp FCTL3 Test WAIT JZ L3 Loop while WAIT 0 INCD R6 Point to next word DEC R5 Decrement write counter JNZ L2 End of block MOV FWKEY amp FCTL1 Clear WRT BLKWRT BIT BUSY amp FCTL3 Test BUSY JNZ L4 Loop while busy MOV FWKEY LOCK amp FCTL3 Set LOCK m Re enable WDT if needed EINT Enable interrupts Flash Memory Controller 5 13 Flash Memory Operation 5 3 4 Flash Memory Access During Write or Erase When any write or any erase operation is initiated from RAM and while BUSY 1 the CPU may not read or write to or from any flash location Otherwise an access violation occurs ACCVIFG is set and the result is u
329. ts x 2x 1 6 10 x UxBR 6jI 1 10 x 10095 1 3796 The results show the maximum per bit error to be 5 0896 of a BITCLK period USART Peripheral Interface UART Mode 13 15 USART Operation UART Mode Typical Baud Rates and Errors Standard baud rate frequency data for UxBRx and UxMCTL are listed in Table 13 2 for a 32 768 Hz watch crystal ACLK and a typical 1 048 576 Hz SMCLK The receive error is the accumulated time versus the ideal scanning time in the middle of each bit The transmit error is the accumulated timing error versus the ideal time of the bit period Table 13 2 Commonly Used Baud Rates Baud Rate Data and Errors 1200 13 16 Divide Divide by A BRCLK 32 768 Hz B BRCLK 1 048 576 Hz Max ae d Max Max TX TX RX ias Ea KH z z Ka KA A B Error 96 2T 27 31 873 81 81 an 3 2 0 03 3 2 USART Peripheral Interface UART Mode USART Operation UART Mode 13 2 7 USART Interrupts The USART has one interrupt vector for transmission and one interrupt vector for reception USART Transmit Interrupt Operation The UTXIFGx interrupt flag is set by the transmitter to indicate that UXTXBUF is ready to accept another character An interrupt request is generated if UTXIEx and GIE are also set UTXIFGx is automatically reset if the interrupt request is serviced or if a character is written to UXTXBUF UTXIFGx is set after a PUC or when SWRST 1 UTXIEx is reset after a PUC or
330. uctions Table 3 16 Format 1 Instruction Cycles and Lengths Addressing Mode No of Length of Src Dst Cycles Instruction Example Rn Rm 1 1 MOV R5 R8 PC 2 1 BR R9 x Rm 4 2 ADD R5 4 R6 EDE 4 2 XOR R8 EDE amp EDE 4 2 MOV R5 amp EDE Rn Rm 2 1 AND R4 R5 PC 2 1 BR R8 x Rm 5 2 XOR R5 8 R6 EDE 5 2 MOV R5 EDE amp EDE 5 2 XOR R5 amp EDE Rn Rm 2 1 ADD R5 R6 PC 3 1 BR R9 x Rm 5 2 XOR R5 8 R6 EDE 5 2 MOV R9 EDE amp EDE 5 2 MOV R9 amp EDE N Rm 2 2 MOV 20 R9 PC 3 2 BR 2AEh x Rm 5 3 MOV 0300h 0 SP EDE 5 3 ADD 33 EDE amp EDE 5 3 ADD 33 amp EDE x Rn Rm 3 2 MOV 2 R5 R7 PC 3 2 BR 2 R6 TONI 6 3 MOV 4 R7 TONI x Rm 6 3 ADD 4 RA4 6 R9 amp TONI 6 3 MOV 2 R4 amp TONI EDE Rm 3 2 AND EDE R6 PC 3 2 BR EDE TONI 6 3 CMP EDE TONI x Rm 6 3 MOV EDE O SP amp TONI 6 3 MOV EDE amp TONI amp EDE Rm 3 2 MOV amp EDE R8 PC 3 2 BRA amp EDE TONI 6 3 MOV amp EDE TONI x Rm 6 3 MOV amp EDE 0 SP amp TONI 6 3 MOV amp EDE amp TONI RISC 16 Bit CPU 3 73 Instruction Set 3 4 5 Instruction Set Description The instruction map is shown in Figure 3 20 and the complete instruction set is summarized in Table 3 17 Figure 3 20 Core Instruction Map 000 040 080 0O0CO 100 140 180 1CO 200 240 280 2C0 300 340 380 3C0 3 74 RISC 16 Bit CPU Table 3 17 MSP430 Instruction Set Mnemonic apc B T dst ADD B src dst ADDC B
331. until the internal transfer counter becomes equal to zero At this point block one is full and both the ADC10IFG flag the ADC10B1 bit are set The user can test the ADC10B1 bit to determine that block one is full The DTC continues with block two The internal transfer counter is automatically reloaded with n At the next load of the ADC10MEM the DTC begins transferring conversion results to block two After n transfers have completed block two is full The ADC10IFG flag is set and the ADC10B1 bit is cleared User software can test the cleared ADC10B1 bit to determine that block two is full Figure 18 12 shows a state diagram of the two block mode ADC10 Operation Figure 18 12 State Diagram for Data Transfer Control in Two Block Transfer Mode n 0 ADC10DTC1 DTC reset gt ADC10B1 0 ADC10TB 1 n 0 Wait for write to ADC10SA Initialize Start Address in ADC10SA Write to ADC10SA x n If ADC10B1 0 then AD SA n is latched in counter x Write to ADC10SA e Wait until ADC10MEM n 0 is written Write to ADC10MEM completed Write to ADC10SA a CPU ready with MCLK x gt 0 Write to ADC10SA 1 x MCLK cycle Transfer data to Address AD AD AD 2 ADC10B1 1 x 0 or ADC10CT 1 ADC10IFG 1 ee OCT 0 and Toggle ADC10B1 0 ADC10B1 Prepare DTC DTC operation ADC10 18 19 ADC10 Operation Continuous Transfer A continuous transfer is selected if
332. us Communication Formats When two devices communicate asynchronously the idle line format is used for the protocol When three or more devices communicate the USART supports the idle line and address bit multiprocessor communication formats Idle Line Multiprocessor Format When MM 0 the idle line multiprocessor format is selected Blocks of data are separated by an idle time on the transmit or receive lines as shown in Figure 13 3 An idle receive line is detected when 10 or more continuous ones marks are received after the first stop bit of a character When two stop bits are used for the idle line the second stop bit is counted as the first mark bit of the idle period The first character received after an idle period is an address character The RXWAKE bit is used as an address tag for each block of characters In the idle line multiprocessor format this bit is set when a received character is an address and is transferred to UXRXBUF Figure 13 3 Idle Line Format Blocks of pes Characters oo XS LS r 5 me Idle Periods of 10 Bits or More UTXDX URXDx Expanded UTXDx URXDx First Character Within Block Character Within Block Character Within Block Is Address It Follows Idle Period of 10 Bits or More Idle Period Less Than 10 Bits USART Peripheral Interface UART Mode 13 5 USART Operation UART Mode 13 6 The URXWIE bit is used to control data reception in the idle line multiprocessor format When the URXWI
333. ut modes 2 3 6 and 7 are not useful for output unit 0 because EQUx EQUO Table 12 4 Output Modes OUTMODx Mode Description 000 Output The output signal OUTx is defined by the OUTx bit The OUTx signal updates immediately when OUTx is updated 001 Set The output is set when the timer counts to the TBCLx value It remains set until a reset of the timer or until another output mode is selected and affects the output 010 Toggle Reset The output is toggled when the timer counts to the TBCLx value It is reset when the timer counts to the TBCLO value 011 Set Reset The output is set when the timer counts to the TBCLx value It is reset when the timer counts to the TBCLO value 100 Toggle The output is toggled when the timer counts to the TBCLx value The output period is double the timer period 101 Reset The output is reset when the timer counts to the TBCLx value It remains reset until another output mode is selected and affects the output 110 Toggle Set The output is toggled when the timer counts to the TBCLx value It is set when the timer counts to the TBCLO value 111 Reset Set The output is reset when the timer counts to the TBCLx value It is set when the timer counts to the TBCLO value 12 14 Timer B Timer_B Operation Output Example Timer in Up Mode The OUTx signal is changed when the timer counts up to the TBCLx value and rolls from TBCLO to zero depending on the output mode An example is shown
334. uts A5 to A7 are shared on port P3 on selected devices see device specific datasheet When analog signals are applied to digital CMOS gates parasitic current can flow from Vcc to GND This parasitic current occurs if the input voltage is near the transition level of the gate Disabling the port pin buffer eliminates the parasitic current flow and therefore reduces overall current consumption The ADC10AEx bits provide the ability to disable the port pin input and output buffers P2 3 configured for analog input BIS B 08h amp ADC10AE P2 3 ADC10 function and enable ADC10 18 5 ADC10 Operation 18 2 3 Voltage Reference Generator The ADC10 module contains a built in voltage reference with two selectable voltage levels Setting REFON 1 enables the internal reference When REF2 5V 1 the internal reference is 2 5 V When REF2_5V 0 the reference is 1 5 V The internal reference voltage may be used internally and when REFOUT 0 externally on pin VREF External references may be supplied for VR and Vg through pins A4 and A3 respectively When external references are used or when Vcc is used as the reference the internal reference may be turned off to save power External storage capacitance is not required for the ADC10 reference source as on the ADC12 Internal Reference Low Power Features The ADC10 internal reference generator is designed for low power applications The reference generator includes a band gap voltage
335. ved In slave receiver mode every byte received will be acknowledged There is no way for a slave to generate a NACK condition for received data Slave transmitter mode is entered when the slave address byte transmitted by the master is the same as its own address and a set R W bit has been transmitted indicating a request to send data to the master The slave transmitter shifts the serial data out on SDA with the clock pulses that are generated by the master device The slave device does not generate the clock but it will hold SCL low while intervention of the CPU is required after a byte has been transmitted ccu E I I mv6a_ uaa __wau_ u6 lt _ _ _ _ Note I2CTRX Bit In Slave Mode The I2CTRX bit must be cleared for proper slave mode operation LLLLL 15 12 USART Peripheral Interface 2C Mode Figure 15 11 Slave Transmitter 12C Module Operation START Detected Yes STTIFG Is Set I2CBUSY Is Set 4 x l2CPSC I2CBB Is Set XA 1 Jt 8x SCL Receive Slave Address Bits 9 8 with R W 0 Receive Slave Address Bits 6 0 with R W 1 Match Matched I2COA Matched I2COA 1x SCL Send Acknowledge Send Acknowledge Receive Slave Address Bits 7 0 Matched I2COA 1x SCL Send Acknowledge Send Acknowledge
336. verflow occurs otherwise reset Set if initial value of destination was 08000h otherwise reset Set if initial value of destination was 080h otherwise reset OSCOFF CPUOFF and GIE are not affected R10 is decremented by 1 DEC R10 Decrement R10 Move a block of 255 bytes from memory location starting with EDE to memory location starting with TONI Tables should not overlap start of destination address TONI must not be within the range EDE to EDE OFEh L 1 MOV EDE R6 MOV 255 R10 MOV B R6 TONI EDE 1 R6 DEC R10 JNZ L 1 Do not transfer tables using the routine above with the overlap shown in Figure 3 12 Figure 3 12 Decrement Overlap EDE 4 TONI EDE 254 TONI 254 RISC 16 Bit CPU 3 37 Instruction Set DECD W DECD B Syntax Operation Emulation Emulation Description Status Bits Mode Bits Example Double decrement destination Double decrement destination DECD dst or DECD W dst DECD B dst dst 2 gt dst SUB 2 dst SUB B 2 dst The destination operand is decremented by two The original contents are lost N Setif result is negative reset if positive Z Setif dst contained 2 reset otherwise C Reset if dst contained 0 or 1 set otherwise V Setif an arithmetic overflow occurs otherwise reset Set if initial value of destination was 08001 or 08000h otherwise reset Set if initial value of destination was 081 or 080h otherwise reset OS
337. w ot rw ot r t Reset by a brownout reset only not by a POR or PUC VLDx Bits Voltage level detect These bits turn on the SVS and select the nominal SVS 7 4 threshold voltage level See the device specific datasheet for parameters 0000 SVSis off 0001 1 9 V 0010 2 1 V 0011 2 2 V 0100 2 3 V 0101 2 4 V 0110 2 5V 0111 2 65V 1000 28V 1001 2 9 V 1010 3 05 1011 3 2 V 1100 3 35 V 1101 3 5V 1110 3 7 V 1111 Compares external input voltage SVSIN to 1 2 V PORON Bit 3 POR on This bit enables the SVSFG flag to cause a POR device reset 0 SVSFG does not cause a POR 1 SVSFG causes a POR SVSON Bit 2 SVS on This bit reflects the status of SVS operation This bit DOES NOT turn on the SVS The SVS is turned on by setting VLDx gt 0 0 SVS is Off 1 SVS is On SVSOP Bit 1 SVS output This bit reflects the output value of the SVS comparator 0 SVS comparator output is low 1 SVS comparator output is high SVSFG Bit 0 SVS flag This bit indicates a low voltage condition SVSFG remains set after a low voltage condition until reset by software or a brownout reset 0 No low voltage condition occurred 1 A low condition is present or has occurred Supply Voltage Supervisor 6 7 Chapter 7 Hardware Multiplier This chapter describes the hardware multiplier The hardware multiplier is implemented in MSP430x14x and MSP430x16x devices Topic Page 7 1 Hardware Multiplier Introduction 7 2 Hardware Multiplier Operation 00eee ee
338. ways read as zero TAIE Bit 1 Timer A interrupt enable This bit enables the TAIFG interrupt request 0 Interrupt disabled 1 Interrupt enabled TAIFG Bit 0 Timer A interrupt flag 0 No interrupt pending 1 Interrupt pending 11 20 Timer A Timer_A Registers TAR Timer_A Register 15 14 13 12 11 10 9 8 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 TARx Bits Timer_A register The TAR register is the count of Timer_A 15 0 Timer_A 11 21 Timer_A Registers TACCTLx Capture Compare Control Register 15 14 13 12 11 10 9 8 rw 0 rw 0 rw 0 rw 0 rw 0 r ro rw 0 7 6 rw 0 CMx Bit 15 14 CCISx Bit 13 12 SCS Bit 11 SCCI Bit 10 Unused Bit 9 CAP Bit 8 OUTMODx Bits 7 5 11 22 Timer A 5 4 3 2 1 0 0 r rw 0 rw 0 rw 0 rw 0 rw 0 rw Capture mode 00 No capture 01 Capture on rising edge 10 Capture on falling edge 11 Capture on both rising and falling edges Capture compare input select These bits select the TACCRx input signal See the device specific datasheet for specific signal connections 00 CCIxA 01 CCIxB 10 GND 11 Vcc Synchronize capture source This bit is used to synchronize the capture input signal with the timer clock 0 Asynchronous capture 1 Synchronous capture Synchronized capture compare input The selected CCI input signal is latched with the EQUx signal and can be read via this bit
339. with the limits of computing devices pursuant to subpart J of part 15 of FCC rules which are designed to provide reasonable protection against radio frequency interference Operation of this equipment in other en vironments may cause interference with radio communications in which case the user at his own expense will be required to take whatever measures may be required to correct this interference Notational Conventions Program examples are shown ina special typeface Glossary Glossary ACLK Auxiliary Clock ADC Analog to Digital Converter BOR Brown Out Reset BSL Bootstrap Loader CPU Central Processing Unit DAC Digital to Analog Converter DCO Digitally Controlled Oscillator dst Destination FLL Frequency Locked Loop GIE General Interrupt Enable INT N 2 Integer portion of N 2 O Input Output ISR Interrupt Service Routine LSB Least Significant Bit LSD Least Significant Digit LPM Low Power Mode MAB Memory Address Bus MCLK Master Clock MDB Memory Data Bus MSB Most Significant Bit MSD Most Significant Digit NMI Non Maskable Interrupt PC Program Counter POR Power On Reset PUC Power Up Clear RAM Random Access Memory SCG System Clock Generator SFR Special Function Register SMCLK Sub System Master Clock SP Stack Pointer SR Status Register src Source TOS Top of Stack WDT Watchdog Timer See Basic Clock Module See System Resets Interrupts and Operating Modes See www ti com msp430 for application
340. x flag When CONSEQx 0 2 the ADC12IFGx flag for the ADC12MEMX used for the conversion can trigger a DMA transfer When CONSEQXx 1 3 the ADC12IFGx flag for the last ADC12MEMx in the sequence can trigger a DMA transfer Any ADC12IFGx flag is automatically cleared when the DMA controller accesses the corresponding ADC 12MEMXx 8 2 11 Using DAC12 With the DMA Controller MSP430 devices with an integrated DMA controller can automatically move data to the DAC12 xDAT register DMA transfers are done without CPU intervention and independently of any low power modes The DMA controller increases throughput to the DAC12 module and enhances low power applications allowing the CPU to remain off while data transfers occur Applications requiring periodic waveform generation can benefit from using the DMA controller with the DAC12 For example an application that produces a sinusoidal waveform may store the sinusoid values in a table The DMA controller can continuously and automatically transfer the values to the DAC12 at specific intervals creating the sinusoid with zero CPU execution The DAC12_xCTL DAC12IFG flag is automatically cleared when the DMA controller accesses the DAC12_xDAT register DMA Controller 8 17 DMA Registers 8 3 DMA Registers The DMA registers are listed in Table 8 4 Table 8 4 DMA Registers Register Short Form Register Type Address Initial State DMA control 0 DMACTLO Read write 0122h Reset with POR DMA control 1
341. xternal voltage The SVS can be configured to set a flag or generate a POR reset when the supply voltage or external voltage drops below a user selected threshold The SVS features include AVcc monitoring Selectable generation of POR Output of SVS comparator accessible by software Low voltage condition latched and accessible by software 14 selectable threshold levels L D LL oo External channel to monitor external voltage The SVS block diagram is shown in Figure 6 1 6 2 Supply Voltage Supervisor Figure 6 1 SVS Block Diagram SVSIN SVS Introduction VCC Brownout Reset ad 1 25V i SVS POR L LOW gt tReset 50us e SVSOUT gt Set SVSFG SVSCTL Bits Supply Voltage Supervisor 6 3 SVS Operation 6 2 SVS Operation The SVS detects if the AVcc voltage drops below a selectable level It can be configured to provide a POR or set a flag when a low voltage condition occurs The SVS is disabled after a brownout reset to conserve current consumption 6 2 1 Configuring the SVS The VLDx bits are used to enable disable the SVS and select one of 14 threshold levels V sys rr for comparison with AVcc The SVS is off when VLDx 0 and on when VLDx gt 0 The SVSON bit does not turn on the SVS Instead it reflects the on off state of the SVS and can be used to determine when the SVS is on
342. y 11 bits When two stop bits are used for the idle line the second stop bit is counted as the first mark bit of the idle period TXWAKE is reset automatically 2 Write desired address character to UXTXBUF UxTXBUF must be ready for new data UTXIFGx 1 The new character representing the specified address is shifted out following the address identifying idle period on UTXDx Writing the first don t care character to UxTXBUF is necessary in order to shift the TXWAKE bit to WUT and generate an idle line condition This data is discarded and does not appear on UTXDx USART Peripheral Interface UART Mode USART Operation UART Mode Address Bit Multiprocessor Format When MM 1 the address bit multiprocessor format is selected Each processed character contains an extra bit used as an address indicator shown in Figure 13 4 The first character in a block of characters carries a set address bit which indicates that the character is an address The USART RXWAKE bit is set when a received character is a valid address character and is transferred to UXRXBUF The URXWIE bit is used to control data reception in the address bit multiprocessor format If URXWIE is set data characters address bit 0 are assembled by the receiver but are not transferred to UxRXBUF and no interrupts are generated When a character containing a set address bit is received the receiver is temporarily activated to transfer the character to UxRXBUF and set URXIF
343. y bit I2CBB is set after a START and cleared after a STOP Data on SDA must be stable during the high period of SCL as shown in Figure 15 4 The high and low state of SDA can only change when SCL is low otherwise START or STOP conditions will be generated Figure 15 4 Bit Transfer on the 12C Bus Data Line Stable Data SCL N ko Change of Data Allowed 15 6 USART Peripheral Interface 2C Mode 12C Module Operation 15 2 3 12C Addressing Modes The 12C module supports 7 bit and 10 bit addressing modes 7 Bit Addressing In the 7 bit addressing format shown in Figure 15 5 the first byte is the 7 bit slave address and the R W bit The ACK bit is sent from the receiver after each byte Figure 15 5 12C Module 7 Bit Addressing Format M 4 oT IE 8 xem 8 UA Slave Address ACK Data ACK P 10 Bit Addressing In the 10 bit addressing format shown in Figure 15 6 the first byte is made up of 11110b plus the two MSBs of the 10 bit slave address and the R W bit The ACK bit is sent from the receiver after each byte The next byte is the remaining 8 bits of the 10 bit slave address followed by the ACK bit and the 8 bit data Figure 15 6 12C Module 10 Bit Addressing Format Ball ae ee i Ta ames Slave Address 1st byte Slave Address 2nd byt ACK Data ACK P l4 44 10 X X Repeated START Conditions The direction of data flow on SDA can be changed by the master withou
344. ystem Resets Interrupts and Operating Modes System Reset and Initialization 2 2 1 Non Maskable Interrupts NMI Reset NMI Pin Non maskable NMI interrupts are not masked by the general interrupt enable bit GIE but are enabled by individual interrupt enable bits NMIIE ACCVIE OFIE When a NMI interrupt is accepted all NMI interrupt enable bits are automatically reset Program execution begins at the address stored in the non maskable interrupt vector OFFFCh User software must set the required NMI interrupt enable bits for the interrupt to be re enabled The block diagram for NMI sources is shown in Figure 2 5 A non maskable NMI interrupt can be generated by three sources An edge on the RST NMI pin when configured in NMI mode An oscillator fault occurs Lj An access violation to the flash memory At power up the RST NMI pin is configured in the reset mode The function of the RST NMI pins is selected in the watchdog control register WDTCTL If the RST NMI pin is set to the reset function the CPU is held in the reset state as long as the RST NMI pin is held low After the input changes to a high state the CPU starts program execution at the word address stored in the reset vector OFFFEh If the RST NMI pin is configured by user software to the NMI function a signal edge selected by the WDTNMIES bit generates an NMI interrupt if the NMIIE bit is set The RST NMI flag NMIIFG is also set i gt

MSP430x1xx Family User`s Guide (Rev. F)

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