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MicroWind manual Lite v35

1. Contact Metal5 metal8 Contact poly metal1 metal8 Contact P diff metal1 metal5 Contact poly metal1 metal3 Figure 2 21 Examples of layer connection using the complex contact command from Microwind Contacts MSK A metal7 metal8 contact is depicted in Fig 2 20 Additionally access to complex stacked contacts is proposed thanks to the icon complex contacts situated in the palette in the second column of the second row The screen shown in Fig 2 20 appears when you click on this icon By default it creates a contact from poly to metall and from metall to metal2 Tick more boxes between metals to build more complex stacked contacts as illustrated in the 2D cross section reported in Fig 2 21 29 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 2 The MOS device Each layer is embedded into a low dielectric oxide referred to as interconnect layer permittivity K in Table 2 which isolates the layers from each other A cross section of a 45 nm CMOS technology is shown in Fig 2 21 In 45 nm technology the layers metall metal4 have almost identical characteristics Concerning the design rules the minimum width w of the interconnect is 3 A The minimum spacing is 4 Layers metal5 and metal6 are a little thicker and wider while layers metal7 and metals are significantly thicker and wider to drive high currents for power supplies The design ru
2. Verifies the layout and highlight the Winalysis Help ANALYSIS MENU design rule violations Ek Design Rule Checker Ctrl D Find Floating Nodes Compile a Verilog file generated by DSCH2 Evaluate the crosstalk effect in all conductors using analytical formulations Global Crosstalk Evaluation Evaluate the RC delay in all Global Delay Evaluation l f conductors using analytical f Parametric Analysis e Ea O ae delay frequency etc formulations 2 Measure Distance Measure the distance in the Resonant Frequency 1 l I E sis with FEM E OU mindo piana PEE Compute the capacitance lambda resistance and inductance of Computes the influence of one parameter such as VDD t two conductors above grout Compute the resonant frequency of LC components planes 121 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL Contact Poly metal PALETTE H MOS generator Stacked contacts VDD VDD_high VSS properties Clock pulse properties Name of the selected node MM Navigator Crosstalk Props p_4 NAVIGATOR e WINDOW Property of the Node Yrefi selected node Property variable Visible unvisible lt Notin sim at simulation 325 ohm 6 um 0 00 nH MA CAPA 0 221F Metal Capa 0 14 fF Crosstalk 0 00 Diffusion 0 00 Gate 0 09 fF RESISTANCE 325ohm Hides the navigator window DEL AV Vin AJo Frequency vs time All vo
3. As for Chapter 7 analog cells are presented including voltage references current mirrors operational amplifiers and phase lock loops Chapter 8 concerns analog to digital digital to analog converter principles Radio frequency circuits are introduced in Chapter 9 The input output interfacing principles are illustrated in Chapter 10 The detailed explanation of the design rules is in Chapter 11 The program operation and the details of all commands are given at the end of this document INSTALLATION Connect to the web page www microwind net for the latest information about how to download the lite version of the software Once installed two directories are created one for MICROWIND35 one for DSCH35 as illustrated below 41 4 na 14 h 11 ata A V i i N V i y ra I i b Li l MSK Help files SCH A t Help files Symbol Vv Vv VY Y library RUL EXE TEC EXE Figure 0 1 The architecture of Microwind and Dsch Once installed two directories are created one for MICROWIND35 one for DSCH35 In each directory a sub directory called html contains help files In MICROWIND35 other sub directories include example files MSK design rules RUL and system files mainly microwind35 exe In DSCH35 other sub directories include example files SCH and SYM design rules TEC and system files mainly dsch35 exe 8 21 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL 1 TECHNOLOGY SC
4. ELLES ee Loo 2A GRESI AR AAAA AA a eee AAA IAAL ISS eee Figure 9 19 The layout corresponding to the improved differential amplifier AmpliDiffFollow MSK 90 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 8 Analog Cells Lu Analog simulation of DiDocuments and SettingsisicardiMes documentsisofware Micron ICO ax 0 20 0 40 0 60 0 80 Voltage vs time Voltages and currents Voltage vs voltage Frequency vs time Eye diagram Figure 9 20 DC simulation of the differential amplifier as follower AmpliDiffFollow MSK 91 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 8 Analog Cells Added Features in the Full version Amplifiers The push pull amplifier is built using a voltage comparator and a power output stage Its schematic diagram and performances are detailed Improved layout A set of design techniques can improve the current mirror behavior MOS orientation techniques channel length modulation effects dummy devices MOS matching Resistor There exist efficient techniques to reduce the resistance variations within the same chip Layout techniques which minimize the effects of process variations are presented Capacitor The multiplication of metal layers create lateral and vertical capacitance effects of rising importance The spared silicon area in upper metal layers may be used for small size capacitance The implementation of these capacitor is described Current Mirror The current mirr
5. Briana scans series Jan 2007 ISBN GRA Hunan dinon DOI 10 1036 0071488391 1 0071488367 DOI 10 1036 0071488367 Cell Design Web information e www microwind org for general information about MICROWIND e www microwind net to download the lite version and order the professional version About ni2designs ni2designs develop design manufacture and market a broad range of EDA tools and complete system solutions targeted at worldwide audience Their diverse product portfolio serves applications in Microelectronics VLSI Embedded Systems DSP Modeling amp Simulation and EM amp Antenna Designs Head Office ni logic Pvt Ltd Pune India Tele Fax 91 20 25286947 8 Email info ni2designs com URL www ni2designs com 3 21 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL Table of Contents PAO OU TG ANNO Zaten etten eee beden Gabe eben Matern benden lo Coal 2 Oy AE pe A A A E 2 Books Sms MICGOwWNd aaa dicta 3 WW Gb 1 FOR E 10 PTA PS RP PI a lee een cae i ae ete cat 3 POO UWE MID O CST OS secs tanace tii taaeeces ie aetia sat hae alaaaaimercensenes isa une sean caaaamuuaiensetae son untetanalaeda auseeaaqstmanion Rustatenataea neers 3 INSTALLA TION Sila mataceoiene 8 EF Technoloow scale DOWN 9 TR MOD DAN tr aia 9 Scaling Benefits das 9 Gate Material and ORAGE 10 A tenet eene neel 11 Ji Pi e A e A endeldarm O 12 A Seni PEOCESS Y AMS a a a 13 2 E IN OS ennen 15 EA E A Pu T 15 MEMOS daS asii lali di
6. Clock led VSS VDD supply Hexadecimal display Inv Inv 3state buffer p Po AND gates Tp De Hexadecimal keyboard OR gates NAND gates E oY Full D latch NOR gates i Tip si gates NMOS and PMOS Memory i EN Complex gates Silicon Menu Silicon Atom Selection Si Alone Si atoms Si lattice Si lattice Boron Si lattice Phosp Atoms 5 Close Move the mouse inside the window Left button down to move Si Figure 13 1 the silicon main menu 126 21 09 2009 MICROWIND DSCH v3 5 LITE USER S MANUAL 15 References silicon Atam re F z A x Selecta Si Alone Si atoms sil E m C Si lattice Silattice Boron ES Si lattice Phosp Atoms E Rows 4 Hove the mouse inside the window Left button down to move 51 Figure 13 2 the silicon lattice and a boron dopant The software silicon is able to give a user s controlled 3D view of silicon atoms such as S102 figure 12 1 The 3D view of the lattice shown in figure 12 2 shows the regular aspect of Si atoms and the very specific properties of the material One boron atom acts as a dopant in the structure 127 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 15 References 14 Student Projects on line www microwind org students The goal of this practical training is to illustrate the design of CMOS circuits with the help of Microwind The list
7. LITE USER S MANUAL 4 Basic Gates In DSCH a transmission gate symbol exists Figure 4 7 It includes the nMOS pMOS and inverter cells Concerning the layout the channel length is usually the minimum length available in the technology and the width is set large in order to reduce the parasitic on resistance of the gate Added Features in the Full version Basic Gates Truth table and schematic diagram of the three input OR gate AND 4 inputs Generalization Complex Gates The technique produces compact cells with higher performances in terms of spacing and speed than conventional logic circuits The concept of complex gates is illustrated through concrete examples The logic implementation of complex gates in DSCH is also described Multiplexor Description of a 2 input lines and n selection lines whose bit combinations determine which input is selected Transmission gate implementation of the 8 to 1 multiplexor Interconnect layers and Description of the interconnect materials metall metal6 supply metals via RC effects in RC behavior interconnects as well as basic formulations for the resistance inductance and capacitance Illustration of the crosstalk effect in interconnects XOR complex gates design considerations 46 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 5 Arithmetics 5 Arithmetics This chapter introduces basic concepts concerning the design of arithmetic gates The adder circuit is
8. Table 4 1 The list of basic gates The Nand Gate The truth table and logic symbol of the NAND gate with 2 inputs are shown below In DSCH select the NAND symbol in the palette add two buttons and one lamp as shown above Add interconnects if necessary to link the button and lamps to the cell pins Verify the logic behavior of the cell inl in2 Out 0 0 1 0 1 1 0 1 1 1 0 Figure 4 1 The truth table and symbol of the NAND gate In CMOS design the NAND gate consists of two nMOS in series connected to two pMOS in parallel The schematic diagram of the NAND cell is reported below The nMOS in series tie the output to the ground for one single combination A 1 B 1 41 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 4 Basic Gates Nand Figure 4 2 The truth table and schematic diagram of the CMOS NAND gate design NandCmos SCH For the three other combinations the nMOS path is cut but a least one pMOS ties the output to the supply VDD Notice that both nMOS and pMOS devices are used in their best regime the nMOS devices pass 0 the pMOS pass 1 You may load the NAND gate design using the command File Read NAND MSK You may also draw the NAND gate manually as for the inverter gate An alternative solution is to compile directly the NAND gate into layout with MICROWIND In this case complete the following procedure In MICROWIND click on Compile gt Compile One CMOS Cell Compiler
9. Get Truth Table 2 Inject Fault 3 Analyse vectors Information Step 2 Select faults and compute response Selectthe type of fault and the list of pins on which the faults will be applied Also selectthe outputto be tested Parameters RT vectar G T gt Type of fault Stuck at 0 0 and at 1 y Apply to Inputs amp Outputs v Teston output jc v RCA Generate Faults SIEM generated in the table L Simulate fault n 6 C 1 a Chronograms Previous De Next X Close 1 Get Truth Table 2 Inject Fault 3 Analyse vectors Information Step 3 Analyse test vectors Click Highlight detection vectors to display which value is different from the reference truth table The command also counts how many fault each vector is able to detect A Highlight detection vectors 100 coverage efect iest vectar in the Ast io acheve He highest CONerage A Previous Next X Close Figure 5 16 Detection score for all test patterns And2_test SCH Click Next The tool moves to 3 section 3 Analyse Vectors Click Highlight Detection Vectors From the results computed in Fig 5 15 we may see that not all test vectors have the same detection efficiency The test vector lt 11 gt last column is able to detect 4 faults upon the total of 6 This means that applying 11 to inputs A B leads to a result on C different from the r
10. Sicard2005b Sicard2006b to speed up the carrier mobility which boosts both the n channel and p channel transistor performances PMOS transistor channel strain has been enhanced by increasing the Germanium Ge content in the compressive SiGe silicium germanium film Both transistors employ ultra shallow source drains to further increase the drive currents 11 21 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL 1 TECHNOLOGY SCALE DOWN Gate Horizontal Gate strain created YS i A REE by the silicon nitride capping layer oxide Drain Drain Si Source Si Source Si 1 I 1 D v 1 Y x ae art nn a Electron movement is slow ES Electron movement is faster as the distance between Si as the distance between Si atoms is small atoms is increased Figure 1 5 Tensile strain generated by a silicon nitride capping layer which increases the distance between atoms underneath the gate which speeds up the electron mobility of n channel MOS devices Gate Horizontal Gate pressure oxide created by the uniaxial SiGe strain Si Hole movement is slow as Hole movement is faster as the distance between Si the horizontal distance atoms is large between Si atoms is reduced Figure l 6 Compressive strain to reduce the distance between atoms underneath the gate which speeds up the hole mobility of p channel MOS devices Let us assume that
11. and voltage overstress are described The design of output buffers is also presented with focus on current drive The Bonding Pad The bonding pad is the interface between the integrated circuit die and the package The pad has a very large surface Almost giant compared to the size of logic cells because it is the place where the connection wire 1s attached to build the electrical link to the outside word The pad is approximately 50 um x 50 um The basic design rules for the pad are shown in figure 10 1 Soldier ball Metal 1 8 area Passivation Via 1 5 area opening limits Passivation opening Passivation Rp04 Last metal Via 1 Metal 1 Rp01 50um Active area Figure 11 1 The bonding pad design rules The cross section shown in figure 10 2 gives an illustration of the passivation opening and associated design rule Rp04 on top of the metal and via stack The thick oxide used for passivation is removed so that a bonding wire or a bonding ball can be connected by melting to the package The pad can be generated by MICROWIND using the command Edit Generate I O pads The menu gives access to a single pad with a default size given by the technology around 50um in this case or to a complete pad rind as detailed later 105 21 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL 10 I O Interfacing The Pad ring The pad ring consists of several pads on each of the four sides of the integrated circ
12. etc Ideally the value of the capacitor should not depend on the bias conditions so that the filtering effect would be situated at constant frequencies Diodes in reverse mode exhibit a capacitor behavior however the capacitance value is strongly dependent on the bias conditions A simple N diffusion on a P substrate is a NP diode which may be considered as a capacitor as long as the N region is polarized at a voltage higher than the P substrate voltage which is usually the case as the substrate is grounded OV In 0 12um the capacitance is around 300aF um2 1 atto Farad is equal to 107 Farad The typical variation of the capacitance with the diffusion voltage Vy is given in figure 8 6 The capacitance per um provided in the electrical rules is a rude approximation of the capacitance variation A large voltage difference between Vy and the substrate result in a thick zone with empty charges which corresponds to a thick insulator and consequently to a small capacitance When Vy is lowered the zone with empty charges is reduced and the capacitance increases If Vy goes lower than the substrate voltage the diode starts to conduct P N Vo Ve Very small current Large current Figure 9 5 The diffusion over substrate as a non linear capacitor Capa MSK 82 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 8 Analog Cells Zone empty of C aF um2 ae The diode is Vy gt 0 charges insulator
13. l gt D gt gt Xo gt gt B 4 4 E gt 3 Hd Symbol list Figure 5 10 testing an AND gate 92 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL Circuit Testing Truth Table Test Vectors e wonnsoreonnnanvenonnnneeneonnnseneensnnnveennsnnencennsen nd Information Step 1 Generate Reference Truth Table The list of inputs and outputs is extracted lOs are classified by alphabetic order Press Logic Simulation to execute the clock assignement and simulate the circuit All inputs will be assigned clocks 5 Arithmetics 5 x Ind Parameters Basic clock period 1 0 ns Ba Update lO List gt Logic Simulation lm Chronograms Extract Truth table Previous X Close Figure 5 11 Building the reference truth table And2_test SCH Click Logic Simulation click Chronograms to see how DSCH has simulated the circuit clocks have been automatically assigned to inputs with period multiplied by 2 in order to cover the whole truth table in one single simulation Click Extract Truth table to feed the table with the values obtained in the chronograms of the circuit logic simulation Fig 5 12 Click Next The tool moves to 2 section 2 Inject Fault The menu shown in Fig 10 corresponds to the fault injection Select the type of fault stuck at 0 stuck at 1 both the nodes on which these models will
14. nwell diode or the N P substrate diode By default the diode is quite large and connected to the upper metal by a row of 10 contacts The N diode region is surrounded by a polarization ring made of P diffusion The large number of rows ensures a large current capability which is very important in the case of ESD protection devices Layout Generator P ihhwell H P sub P A e A Local Polarization rows C None NE DiffN polarization on Mwell wae am aids a Generate Diode x Cancel Figure 10 5 The diode generating menu in Microwind By default a P well diode 108 21 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL 10 I O Interfacing 5 00 mA iddmax 0 000mA 400 Hlddinred I N1 62 x 2 1 039mA 3 00 Maximum current around 1mA IO supply E is 2 5V A lA en 1 6 0 0 0 5 1 0 15 2 0 ny 3 0 3 5 40 4 5 Time ns Figure 11 5 The diodes clamp the positive and negative overstress so that the internal voltage keeps close to the voltage range 0 VDDH IoPadIN MSK A protection circuit example is simulated in figure 10 5 It consists of a pad 50 x 50 um a serial resistor around 200 2 and two diodes When a very high sinusoidal waveform 10 V is injected the diodes exhibit a clamping effect both for the positive and negative overstress The best
15. turned on varies depending on Vy 600 Capacitance extracted by Microwind gt T 300 1 0 Vt 0 VDD 2 VDD Vy Figure 9 6 The diffusion capacitance varies with the polarization voltage Poly Poly2 Capacitor Most deep submicron CMOS processes incorporate a second polysilicon layer poly2 to build floating gate devices for EEPROM An oxide thickness around 20 nm is placed between the poly and poly2 materials which induces a plate capacitor around 1 7 fF um In MICROWIND the command Edit gt Generate gt Capacitor gives access to a specific menu for generating capacitor Figure 8 7 The parameter in the design rule file cmos43nm RUL for the 45 nm technology used to configure the poly poly2 capacitor is CPZEO The poly poly2 capacitor simply consists of a sheet of polysilicon and a sheet of poly2 separated by a specific dielectric oxide which is 20 nm in the case of the default CMOS 45 nm process Layout Generator Eifel x Fads Inductor Contacts MOS Path Logo Aus Res Diode Cana Fix here the target Ype OT Cabs Pararaeter capacitance PolwPolr Capacitance value fil nier metal Capa Using metal layers Metal E Metal 8 F Metals Metal 7 md ma Metal 4 Metal 3 polypolys m2 fetal 2 eee 11 he Metali ka Generate Capa x Cancel Figure 9 7 The generator menu handles the design of poly poly2 capacitor and in
16. 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL 6 Latches As can be seen the register is built up from one single call to the primitive dreg For simulation e Reset 1s active on a level 1 Reset is activated twice at the beginning and later using a piece wise linear description included in the pulse property e Clk is aclock with 10ns at O and 10ns at 1 e D is the data chosen here not synchronized with Clk in order to observe various behaviors of the register To compile the DREG file use the command Compile gt Compile Verilog Text The corresponding layout is reported below The piece wise linear data is transferred to the text label Reset appearing in the lower corner of the D flip flop layout of figure 6 6 For testing the Dreg the Reset signal is activated twice at the beginning and later using a piece wise linear property figure 6 6 The Clock signal has a 2 ns period D is the data chosen here not synchronized with Clock in order to observe various behaviors of the register The simulation of the edge trigged D register is reported in figure 6 6 The signals Q and nQ always act in opposite When Reset is asserted the output O is 0 nQ is 1 When Reset is not active O takes the value of D at a fall edge of the clock For all other cases O and nQ remain in memory state The latch is thus sensitive to the fall edge of the clock Master memory loop Slave memory loop I VZ ITE ms El sad EL ALA e
17. 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL 8 Analog Cells Vin Gain Vout Load Load load out T Amplifier with resistor load Amplifier with pMOS load Amplifier with inductor laad Figure 9 13 Single stage amplifier design with MOS devices AmpliSingle SCH Most interesting zone Output voltage V The gain slope is high in this region Vin tow Vin Vin_high Input voltage V Figure 9 14 The amplifier has a high gain in a certain input range where a small input signal vin is amplified to a large signal vout The single stage amplifier characteristics between Vin and Vout have a general shape shown in figure 8 14 The most interesting zone corresponds to the input voltage range where the transfer function has a linear shape that is between VIN low and VIN high Outside this voltage range the behavior of the circuit does not correspond anymore to an amplifier If we add a small sinusoidal input v to V a small variation of current ij 18 added to the static current ps which induces a variation v of the output voltage Vorr The link between the variation of current i and the variation of voltage v can be approximated by equation 8 2 RINA Equ 8 2 87 21 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL 8 Analog Cells SE SO pict TET OL UCT ECR ECP ANO CROC IO hac ae HO AO het WACHT ter ere tote ach URO feta Chae Cece ED VOUT 4vout VINAvin Active l
18. LLL LLL 2240 AAA DADA DA DADAS AA PERRE TA CEPEEELAEEE LALALA AA AAA A A AR EEEE A ALLA AA A A AAA AAA A A VEER i Mht de 4 ABE xor Figure 4 6 Layout and simulation of the XOR gate XOR MSK 44 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 4 Basic Gates You may use DSCH to create the cell generate the Verilog description and compile the resulting text In MICROWIND the Verilog compiler is able to construct the XOR cell as reported in Figure 4 6 You may add a visible property to the intermediate node which serves as an input of the second inverter See how the signal called internal is altered by Vin when the nMOS is ON and Vip when the pMOS is ON Fortunately the inverter regenerates the signal However the output signal Xor is not a clean CMOS signal and this type of compact design may be abandoned and replaced by more conventional XOR circuits Multiplexor Multiplexing means transmitting a large amount of information through a smaller number of connections A digital multiplexor is a circuit that selects binary information from one of many input logic signals and directs it to a single input line The main component of the multiplexor is a basic cell called the transmission gate The transmission gate let a signal flow if Enable is asserted sel 0 Hint sel 1 Finl sel Figure 4 7 The transmission gate used as a multiplexor MUX SCH 45 21 09 2009 MICROWIND DSCH V3 5
19. MOS device The physical properties of the source and of the drain are exactly the same Theoretically the source is the origin of channel impurities In the case of this nMOS device the channel impurities are the electrons Therefore the source is the diffusion area with the lowest voltage The metal gate floats over the channel and splits the diffusion into 2 zones the source and the drain The gate controls the current flow from the drain to the source both ways A high voltage on the gate attracts electrons below the gate creates an electron channel and enables current to flow A low voltage disables the channel Static Mos Characteristics E Click on the MOS characteristics icon The screen shown in Figure 2 5 appears It represents the d Vd static characteristics of the nMOS device The MOS size width and length of the channel situated at the intersection of the polysilicon gate and the diffusion has a strong influence on the value of the current In Figure 2 5 the MOS width is 580 nm and the length is 40 nm A high gate voltage Vg 1 0V corresponds to the highest d Vd curve For Vg 0 almost no current flows Ids is close to 0 You may change the voltage values of Vd Vg Vs by using the voltage cursors situated on the right side of the window A maximum current around 0 55 mA is obtained for Ve 1 0 V Vd 1 0 V with Vs 0 0 The MOS parameters correspond to SPICE model BSIM4 Liu2001 U Nmos Width 0 580 Length 0
20. Metal contact macros situated in the upper part of the Palette menu to link the layers together LAYOUT _ Load the layout design of the Half Adder using File Open and loading LIBRARY the file Hal fAdder MSK VERILOG COMPILING Use DSCH to create the schematic diagram of the half adder Verify the circuit with buttons and lamps Save the design under the name HalfAdder sch using the command File Save As Generate the Verilog text by using the command File Make Verilog File The text file HalfAdder v is created In MICROWIND click on the command Compile gt Compile Verilog File Select the text file Hal fAdder v Click Compile When the compiling is complete the resulting layout appears shown below The XOR gate is routed on the left and the AND gate is routed on the right Now click on Simulate Start Simulation The timing diagrams of figure 5 3 appear and you should verify the truth table of the half adder e as Carry FF p 77 FITIART aa Ee EE GA VOLLE 0 950ns 4 000ns gt um 1 056 0 256 O kee Se ee ee Fe 2 ea oo 3 0 20 30 40 50 BO Figure 5 3 Compiling and simulation of the half adder gate HalfAdder MSK Full Adder Gate The truth table and schematic diagram for the full adder are shown in Figure 5 4 The SUM is made with two XOR gates and the CARRY is a combination of NAND gates as shown below The most straightforward implementation of the CARRY cell is AB BC AC
21. Strain 8 Metal copper loaded from file default rul Figure 12 1 illustration of design rules using the command Help gt Design Rules 113 21 09 2009 10 x Summary wells Difusions Polysilicon Contact Metal Via Metal2 Vie Metal vias Metals vied Metall Metals Metal Metals Pads MICROWIND DSCH V3 5 LITE USER S MANUAL 11 Design Rules Lambda Units The MICROWIND software works is based on a lambda grid not on a micro grid Consequently the same layout may be simulated in any CMOS technology The value of lambda is half the minimum polysilicon gate length Table 11 1 gives the correspondence between lambda and micron for all CMOS technologies available in version 3 5 Technology file available in Minimum gate Value of lambda version ses MANON eigen pee OF tama soi012 rul S01 version Table 11 1 correspondence between technology and the value of lambda in um N Well r101 Minimum well size 122 ee eee po r102 Between wells 12 ie r110 Minimum well area 144 R101 nwell Diffusion r201 Minimum N and P diffusion width An Nwell r202 Between two P and N diffusions 44 ee r203 Extra nwell after P diffusion 6 r204 Between N diffusion and nwell 62 r205 Border of well after N polarization 2 1206 Between N and P polarization 0A i r207 Border of Nwell for P polarization aN r210 Minimum diffusion area AN r201 r206 a
22. Vadc 2 bit Flash Analog to digital converter Sample output Thermometer to binary decoder Vin Analog input Figure 10 17 The schematic diagram of the 2 bit flash ADC converter AdcFlash2bits SCH Unsalicide Poly more Tesistive S aana Figure 10 18 Design of the analog digital converter ADC MSK The analog to digital converter is considered as an encoding device where an analog sample is converted into a digital quantity with a number N of bits ADCs can be implemented by employing a variety of architectures The 2 bit analog digital converter converts an analog value Vin into a two bit digital value A coded on 2 bit Aj Ao 102 21 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL 9 Radio frequency Circuits Fast response of CO C1 Slow response 0 D0 of C2 NN C2 6 0 70 8 0 9Time ns Figure 10 19 Simulation of the analog digital converter ADC MSK The flash converter uses three amplifiers which produce results Co C and C3 connected to a coding logic to produce A and A in a very short delay Figure 9 19 The flash converters are widely used for very high sampling rates a the cost of very important power dissipation The resistor ladder generates intermediate voltage references used by the voltage comparators located in the middle of the layout An unsalicide option layer multiplies the sheet resistance of the polysilicon ladder for an area efficient implementa
23. aat r207 P polarization 114 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 11 Design Rules Polysilicon Metal Gate Starting 45 nm the polysilicon gate material has been replaced by metal such as NiSi We keep the name polysilicon for convenience r301 Polysilicon width 2 r302 Polysilicon gate on 2A diffusion r303 Polysilicon gate on 4A diffusion for high voltage MOS r304 Between two 3A polysilicon boxes r305 Polysilicon vs other 22 diffusion r306 Diffusion after 4 polysilicon r307 Extra gate after 3 polysilicon r310 Minimum surface 8 7 High voltage MOS 2 Polysilicon Metal gate Design Rules r311 Polysilicon2 width 24 r312 Polysilicon2 gate on 2A diffusion 1320 Polysilicon2 minimum 824 surface MOS option rOpt Border of option layer over diff N 7A and diff P 115 21 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL Contact r401 Contact width 24 r402 Between two contacts 5 r403 Extra diffusion over contact 2A r404 Extra poly over contact 24 r405 Extra metal over contact ZN r406 Distance between contact and 3 poly gate r407 Extra poly2 over contact 24 Metal 1 r501 Metal width 44 r502 Between two metals 4 r510 Minimum surface 16 X Via r601 Via width 24 r602 Between two Via SA r603 Between Via and OA contact r604 Extra metal over via 24 r605 Extra metal2 over via 24 Metal 2 r701 Metal width 44 r702 Between two me
24. al EHE ut ET hi tat ap AS 2 ria Baene a in TER LL a FE i E H N B imi i It l RER tie Hi Ie mia i ish EEH it a E ae ae HAR qL u EL tin FEI Bman e a e SEEEEREEE EE HF A E inva dal ne a or ie de Bebi fla a H TIH FLR ELIK IHH OENE MERE NUR Ee Kl LUEI E 1 wang a ai IA Al LE a L ow i 5 HE ia Leid it Te AAA im i ian a An Jo CFTE anit in Na I sal ol Eis Tr EJ TE AE KJ ET Sait Fat ie i i aa ilat iati ri wi da di Figure 8 10 The complete RAM layout RAM64 MSK 74 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 7 Memory circuits Dynamic RAM Memory The dynamic RAM memory has only one transistor in order to improve the memory matrix density by almost one order of magnitude The storage element is no longer the stable inverter loop as for the static RAM but only a capacitor Cs also called the storage capacitor The write and hold operation for a 1 is shown in figure 7 11 The data is set on the bit line the word line is then activated and Cs is charged As the pass transistor is n type the analog value reaches VDD Vt When WL is inactive the storage capacitor Cs holds the 1 Precharged to Vp Precharged to Vp Vp AV BL Poor 0 Figure 8 11 Simulation of the Read cycle for the 1 transistor dynamic RAM cell RAMIT SCH The reading cycle is destructive for the stored information Suppose that Cs hol
25. and simulate an integrated circuit at physical 5 lambda Ee vee en a Wn Gb Tai a vans n 4 n P ae LES x a F EE ARA 90s description level The package contains a library of g BES B boye E traue common logic and analog ICs to view and simulate MICROWIND includes all the commands for a mask editor as well as original tools never gathered before in a single module 2D and 3D process view Verilog compiler tutorial on MOS devices You can gain Editing D Documents and Settinas sicard Mes documents software Micr Hit 18 ICMOS 45nm HighkMetal Strain B17 access to Circuit Simulation by pressing one single key The electric extraction of your circuit is automatically performed and the analog simulator produces voltage and current curves immediately 7 21 09 2009 MICROWIND DSCH V3 1 LITE USER S MANUAL INTRODUCTION The chapters of this manual have been summarized below Chapter 2 is dedicated to the presentation of the single MOS device with details on the device modeling simulation at logic and layout levels Chapter 3 presents the CMOS Inverter the 2D and 3D views the comparative design in micron and deep submicron technologies Chapter 4 concerns the basic logic gates AND OR XOR complex gates Chapter 5 the arithmetic functions Adder comparator multiplier ALU The latches and memories are detailed in Chapter 6
26. be replaced by physical components The time domain simulation Figure 9 11 shows a warm up period around Ins where the DC supply rises to its nominal value and where the oscillator effect reaches a permanent state after some nano seconds The Fourier transform of the output s reveals a main sinusoidal contribution at f0 3 725 GHz as expected and some harmonics at 2 x fO and 3 x fO Figure 9 12 The remarkable property of this circuit is its ability to remain in a stable frequency even if we change the supply voltage or the temperature which features a significant improvement as compared to the ring oscillator Furthermore the variations of the MOS model parameters have almost no effect on the frequency Eneray w o ii Meeden hetis 0 25 SS a Cal A el en en en o el glia tee et ew wipe lil pl 0 20 is e A A s id di pleated led eal ade pelt tied a alte beled all shet 3F37MHz 180 52mV A pa 0 9v 100 C PA eee a 0 10 0 05 A A AA AR E A A PAS Ee Figure 10 12 The frequency spectrum of the oscillator OscillatorDiff MSK 99 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 9 Radio frequency Circuits Analog to digital and digital to analog converters The analog to digital converters ADC and digital to analog converters DAC are the main links between the analog signals and the digital world of signal processing The ADC and DAC viewed as black boxes are shown in figure 9 13 On th
27. be applied and the output considered for test By default s O is applied to all inputs and the first output declared in the list is observed A circuit Testing Truth Table Test Vectors gposcosessccosesecososesovcescssosososecsecsssosessessescen evseseoseoeeossoseoseoseosooseseosseseoseoessesoseseeese lol xl Information Step 1 Generate Reference Truth Table The list of inputs and outputs is extracted lOs are classified by alphabetic order Press Logic Simulation to execute the clock assignement and simulate the circuit All inputs will be assigned clocks ha Parameters Basic clock period 1 0 ns 22 Update IO List Pe Logic Simulation jag Chronograms Extract Truth table Pe Next Previous X Close Figure 5 12 Computing the reference truth table from logic simulation And2_test SCH 93 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 5 Arithmetics A circuit Testing lolx Tab E Te st Ve cto rs goceeseccoescococesoeosocosococessessosesoos Information Step 2 Select faults and compute response Selectthe type of fault and the list of pins on which the faults will be applied Also selectthe output to be tested Parameters Aight vectar C E gt Type of fault Stuck at 0 0 y Apply to Inputs v Teston output c v RA Generate Faults PIES
28. by MICROWIND if you draw the slope manually At the bottom of the screen the equivalent resistance appears together with the voltage and current n MOS connected as a diode p MOS connected as a diode Figure 9 9 Schematic diagram of the MOS connected as a diode ResMos MSK 84 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 8 Analog Cells Amos 44 0 140 L 1 400 pm loj x wow TO po Too The slope is equal to 1 R As Vd Vg Ids follows this unique curve Draw the slope with nd the mouse to display the equivalent R Figure 9 10 Using the Simulation on Layout to follow the characteristics of the diode connected MOS ResMos MSK In summary the MOS connected as a diode is a capacitance for Vgs lt Vt a high resistance when Vgs is higher than the threshold voltage Vt The resistance obtained using such a circuit can easily reach 100KQ in a very small silicon area Voltage Reference The voltage reference is usually derived from a voltage divider made from resistance The output voltage Vref is defined by equation 8 1 gt Ky ref R 4 R DD Eq 8 1 with Vpp power supply voltage 1 0 V in 65 nm Ry equivalent resistance of the n channel MOS Q Rp equivalent resistance of the p channel MOS Q Notice that two n MOS or two p MOS properly connected feature the same function P MOS devices offer higher resistance due to lower mobility compared to n channel MOS Four voltage ref
29. directory in which the Microwind35 exe Microwind3 5 INSA software has been copied By default Microwind35 Double click on the MICROWIND icon The MICROWIND display window includes four main windows the main menu the layout display window the icon menu and the layer palette The layout window features a grid scaled in lambda A units The lambda unit is fixed to half of the minimum available lithography of the technology The default technology is a CMOS 8 metal layers 45 nm technology In this technology lambda is 0 02 um 40 nm u Microwind35 example ifai O x File View Edit Simulate Compie Analysis Help Bau s rataan Slambda 2 E wee mw DA EA Show palette menu Hit 18 CMOS 45nm Highk Metal Strain 81 4 Figure 2 2 The MICROWIND window as it appears at the initialization stage The palette is located in the lower right corner of the screen A red color indicates the current layer Initially the selected layer in the palette is polysilicon By using the following procedure you can create a manual design of the n channel MOS O Fix the first corner of the box with the mouse While keeping the mouse button pressed move the mouse to the opposite corner of the box Release the button This creates a box in polysilicon layer as shown in Figure 2 3 The box width should not be inferior to 2 A which is the minimum width of the polysilicon box O Change the current layer
30. frequency Circuits Gilbert mixer The Gilbert mixer is used to shift the frequency of an input signal Vin to a high frequency The Gilbert cell consists of only six transistors and performs a high quality multiplication of the sinusoidal waves The schematic diagram and the physical implementation are described in the full version Phase Lock Loop Each basic component of the PLL Phase comparator filter VCO and the design issues are described supported by a large set of simulations Digital to analog The R 2R ladder consists of a network of resistors alternating between R and converter 2R For a N bits DAC only N cells based on 2 resistors R and 2R in series are required The 4 bit and 8 bit implementation of this circuit are described Sample and Hold The sample and hold main function is to capture the signal value at a given instant and hold it until the ADC has processed the information The principles and parasitic effects of the circuit are described Analog to digital Successive approach analog to digital converter converter 104 21 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL 10 I O Interfacing 11 Input Output Interfacing This chapter is dedicated to the interfacing between the integrated circuit and the external word After a brief justification of the power supply decrease the input output pads used to import and export signals are dealt with Then the input pad protections against electrostatic discharge
31. given in Figure 7 4 The BL and BL signals are made with metal2 and cross the cell from top to bottom The supply lines are horizontal made with metal3 This allows easy matrix style duplication of the RAM cell 70 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 7 Memory circuits Word Line Bit Line Bit Line Figure 8 4 The layout of the static RAM cell RAM6T MSK WRITE CYCLE Values 1 or 0 must be placed on Bit Line and the data inverted value on Bit Line Then the selection Word Line goes to 1 The two inverter latch takes the Bit Line value When the selection Word Line returns to 0 the RAM is in a memory state READ CYCLE The selection signal Word Line must be asserted but no information should be imposed on the bit lines In that case the stored data value propagates to Bit Line and its inverted value Data propagates to Bit Line SIMULATION The simulation parameters correspond to the read and write cycle in the RAM The proposed simulation steps consist in writing a 0 a 1 and then reading the 1 In a second phase we write a 1 a 0 and read the 0 The Bit Line and Bit Line signals are controlled by pulses Figure 7 5 The floating state is obtained by inserting the letter x instead of or 0 in the description of the signal x Label name Bit Line BL Floating state described by x DC Supply Clock Fulse Sinus Varlanle SFONN0 Fr
32. of projects is described below For each project a report in PDF format is on line Year Institute Country Student name Advisor name Project title C M R Prabhu Ajay poa AE cell tor Malaysia low power consumption Kumar Singh i during write operation Etude et impl mentation 2008 ISSAT Sousse Tunisie MOUNA Karmani Hamdi BELGACEM gun ama lied operationnel CMOS auto contr lable par test IddQ Etude et impl mentation 2008 ISSAT Sousse Tunisie CHIRAZ Khedhiri Hamdi BELGACEM d une unit arithm tique auto contr lable 2008 INSA Toulouse France i A e TEAST OMe Etienne SICARD je sel urore pe gain Colin J rome Radio Frequency 2008 INSA Toulouse France i Sonia Ben Dhia mplifier 90nm and Facchin David 65nm 2008 INSA Toulouse France Fabien Bonnneau Jos Perez Sonia Ben Dhia ORD lee Digital Converter R alisation d un RDAN Ana s convertisseur 2008 INSA Toulouse France BA Mouhamadou Siradji Etienne SICARD Analogique Num rique R 2007 INSA Toulouse France eae ue e Etienne SICARD stage binary counter Calvignac 2007 INSA Toulouse France E Thomas Etienne SICARD Bas ace A Oller David Interconnect Point He Maria MARTIN I l ay of Very simple 2007 INSA Toulouse France Mathieu LE MERRER Sonia Ben Dhia microprocessor Nicole Dos Santos Ga l 2007 INSA Toulouse France GESSLER Etienne SICARD 4 bit Flash 2007 INSA Toulouse France a e E Etienne SICARD ey at ee hits Nguyen Thanh H Gian
33. of the circuit Za F vddHV vddHV vddHV Vi l tragu Page Low voltage inverter Level shifter Buffer stage Figure 11 8 Schematic diagram of a level shifter IOPadOut SCH 111 21 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL 10 I O Interfacing Vout 0 0 0 5 1 0 15 2 0 25 3 0 3 5 A0 45 Timetns Figure 11 9 Layout and simulation of the level shifter LevelShift MSK The layout of the level shifter is shown in figure 10 10 The left part works at low voltage 1 0 V the right part works with high voltage MOS devices at a supply of 2 5V VddHigh The data signal Data_Out has a 0 1 0 V voltage swing The output Vout has a 0 2 5V voltage swing This time no DC consumption appears except during transitions of the logic signals as shown in the simulation of figure 10 9 Added Features in the Full version Pad Core limitation When the active area of the chip is the main limiting factor the pad structure may be designed in such a way that the width is large but the height is as small as possible This situation called Core Limited as well as its opposite Pad limited are detailed Schmitt trigger Using a Schmitt trigger instead of an inverter helps to transform a very noisy input signal into a clean logic signal The Schmitt trigger circuit switching is illustrated and compared to the normal inverter IBIS is a standard for electronic behavioral specifications of integrated circuit input ou
34. pointed by the mouse CTRL X al Changes the size of one box or moves the layout included in the given area COPY al Edit Menu Copies the layout included in the given area CTRL C VIEW La View Menu Verifies the electrical net connections ELECTRICAL NODE CTRL N 2D CROSS Simulate Menu Shows the aspect of the circuit in SECTION vertical cross section Figure 3 8 A set of useful editing tools Create inter layer contacts As the gate material has a high resistivity metal is preferred to interconnect signals and supplies Consequently the input connection of the inverter is made with metal Metal and TiN are separated by an oxide which prevents electrical connections Therefore a box of metal drawn across a box of TiN does not allow an electrical connection Figure 3 9 34 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 3 The Inverter Metal 4 min Contact 2x2 Je Enlarged TiN area E 5 Gate material QA 4x4 BS min pol y in 65 nm and above TinN in 45 nm Figure 3 9 Physical contact between metal and TiN Terr Tr err Metal bridge between nMOS and pMOS gates drains sO sO so Metal extension for future interconnection Figure 3 10 Adding a poly contact poly and metal bridges to construct the CMOS inverter InvSteps MSK Thick oxide C ZE HfO2 oc A es NMOS gate TiN Ground ee polarization EA EET ecos WN 2222 ess
35. test vectors and therefore reduce the number of test patterns Faults considered in DSCH are called stuck at faults We consider two types of Stuck at stuck at 0 and stuck at 1 faults Figure 5 9 illustrates a possible origin for a node stuck at O voltage the implementation is close to a VSS node here situated close same layer and a faulty metal bridge makes a robust connection to the ground Node under test AL Designed Fabricated interconnects interconnects with stuck at 0 fault Figure 5 9 Physical origin of a node fault stuck at 0 There are several ways to nominate stuck at faults all having the same meaning In DSCH we shall use N 0 for node N stuck at O and NO 1 for node N stuck at 1 In DSCH version 3 5 build a simple circuit as shown in Fig 5 10 including 2 inputs and one output and click Simulate Logic Circuit Testing The screen shown in Fig 5 11 corresponds to the construction of the reference truth table In the table situated in the left part of the screen all inputs and outputs are displayed and the input values are pre positioned In the case of the AND gate two inputs A and B are listed 5 Dsch3 5 D Documents and Settings sicard Mes documents software Dsch Dschaatdsch35 fulhexamples test and2_test sch _ lol x File Edit Insert View Simulate Help coal raf Bo SAR gt mw MARK 4 Sree xi Basic Advanced D 9 mo e e p D p
36. the list of pins right side A set of drawing options is also reported in the same window Notice the gate delay 3 pico second in the 45 nm technology the fanout that represents the number of cells connected to the output pin 1 cell connected and the wire delay due to this cell connection an extra 2 ps delay The CMOS inverter The CMOS inverter design is detailed in the figure below Here the p channel MOS and the n channel MOS transistors function as switches When the input signal 1s logic O Figure 3 4 left the nMOS is switched off while PMOS passes VDD through the output When the input signal is logic 1 Figure 3 4 right the pMOS is switched off while the nMOS passes VSS to the output Figure 3 4 The MOS Inverter File CmosInv sch The fanout corresponds to the number of gates connected to the inverter output Physically a large fanout means a large number of connections that is a large load capacitance If we simulate an inverter loaded with one single output the switching delay is small Now if we load the inverter by several outputs the delay and the power consumption are increased The power consumption linearly increases with the load capacitance This is mainly due to the current needed to charge and discharge that capacitance Manual Layout of the Inverter In this paragraph the procedure to create manually the layout of a CMOS inverter is described Click the icon MOS generator on the palette The following wi
37. the silicon atoms form a regular lattice structure inside which the carriers participating to the device current have to flow In the case of electron carriers stretching the lattice by applying tensile strain allows the electrons to flow faster from the source to the drain as depicted in Fig 1 5 The mobility improvement exhibits a linear dependence on the tensile film thickness In a similar way compressing the lattice slightly speeds up the p type transistor for which current carriers consist of holes Fig 1 6 The combination of reduced channel length decreased oxide thickness and strained silicon achieves a substantial gain in drive current for both nMOS and pMOS devices Market The integrated circuit market has been growing steadily since many years due to ever increasing demand for electronic devices The production of integrated circuits for various technologies over the years is illustrated in Fig 1 7 It can be seen that a new technology has appeared regularly every two years with a ramp up close to three years The production peak is constantly increased and similar trends should be observed for novel technologies such as 45nm forecast peak in 2010 12 21 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL 1 TECHNOLOGY SCALE DOWN Production 45nm 65nm Year 1995 2000 2005 2010 2015 Figure 1 7 Technology ramping every two years introducing the 45 nm technology Prototype 45 nm processes have been intr
38. trigged latch is one of the most widely used cells in microelectronics circuit design The cell structure comprises two master slave basic memory stages The most compact implementation of the edge trigged latch is reported below figure 6 5 The schematic diagram is based on inverters and pass transistors On the left side the two chained inverter are in memory state when the pMOS loop transistor P is on that is when Clk 0 The two chained inverters on the right side act in an opposite way The reset function is obtained by a direct ground connection of the master and slave memories using nMOS devices When clock is high the master latch is updated to a new value of the input D The slave latch produces to the output Q the previous value of D When clock goes down the master latch turns to memory state The slave circuit is updated The change of the clock from 1 to O is the active edge of the clock This type of latch is a negative edge flip flop Use the Verilog compiler to generate the edge trigged latch description in Verilog format or by creating a schematic diagram including the D register symbol in the symbol palette of DSCH DFF with pass transistors Fall edge sensitive Slave transparent if Master 0 P lock EE Slave 0 Clock 1 Fall edge of the clock Slave transparent Master 1 a Q updated to 1 Clack Clock 0 Figure 7 5 The edge trigged latch and its logic simulation Dreg MSK 66 21 09
39. which v Bus value the delay counter is started at between each crossing of VDD 2 _j Vin y Th a j and e delay counter is stopped at each crossing of JAC x VDD 2 and the delay is lata t A Min max Ar Frequency fao Lili FFT Time Scale drawn The minimum and maximum voltage of the selected node are displayed At each period of the selected node the frequency is displayed Show the FFT of the selected signal Select the time scale within a list in the menu Shift the time Computational simulation step Restart simulation from time 0 More simulation 50 6 0 70 80 9Time ns Stop simulation Voltage vs time Voltages and currents Voltage vs voltage Frequency vs time Eye pe gram Eye diagram A zoom at each visible node at the switching of a selected node 122 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 15 References LIST OF ICONS a Open a layout file MSK format B Extract and simulate the circuit Save the layout file in MSK format ae Measure the distance in lambda and micron EE between two points Draw a box using the selected layer of the palette Delete boxes or text Animated 3D view of the layout using OpenGL 2D vertical aspect of the device Copy boxes or text Stretch or move elements Design rule checking of the circuit Errors are notified in the layout a Zoom In Add a text to the layout The text may include sim
40. 0 while port input pins are tested through the instruction such as JB P2 2 URG See table 2 for the complete code embedded in the 8051 processor fi Tratti bigots Ey Sicard FJ1 ACALL TEMPO E Aller 0d MOV P3 50H L1 MOV P3 84H ACALL TEMPO ACALL TEMPO a ae Feul r F2 vert MOV P3 90H JB P2 2 URG ACALL TEMPO JB P2 yl Pu E Be AJMP L1 MOV P3 84H FJ ACALL TEMPO AJMP L1 MOV P3 88H Feul r F2 jaune ACALL TEMPO MOV P3 90H ACALL TEMPO r r L2 MOV P3 30H LP ys oe of JB P2 2 URG JB P2 0 EFJ1 AJMP L2 Temporisation TEMPO NOP NOP NOP NOP NOP NOP NOP RET Urgence URG MOV P3 48H NOP MOV P3 0 JNB P2 2 L1 AJMP URG Table 6 2 Code embedded in the traffic light controller 8051_traffic_lights sch 61 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 6 Microcontroller Model Model of the PIC 16f84 DSCH3 includes the model of the PIC16f84 micro controller Activating Ports of the 16f84 The following program is used to activate the Port B as output The schematic diagram which implements this code is 16f84 SCH Fig 6 6 The corresponding simulation is reported in Fig 6 7 PIC16f84 by Etienne Sicard for Dsch 7 Simple program to put 10101010 on port B 01010101 on port B 7 PortB equ 0x06 declares the address of output port B org 0 loop movlw 0x55 load W with a pattern hexa format movwf PortB Moves the pattern to port B movlw Oxaa load W with an
41. 040 um 29x2 lambda Id vs Vd ld vs va log id vs Vg Threshold voltage Capacitance tei re vTHO fo190 400 ko pro A 500 0 er ve roo A 450 0 er l Toxe 3500 A 400 0 _ _0 80 pyro 2300 lt rr pv fosso A 350 0 y a et teen 200 Af 300 0 A 2 at NFACT roo af en 4 mr 60 PSCBE1 230 000 2 200 0 ns eo agii pe pa 150 0 A a 0 40 merri aie ff A Temp C 27 000 m EAS Vd Va Vs Vb A ca2oS III IIA BIEDERS PUB TT de 0 00 0 20 0 40 vag 280 0 80 A Y El El vafromoto 1 000 For vg from Oto 1 000 Stepvg 0 200 all Dump Ibis _ lt Aad measure y OK la Draw l Fit fret um L 0 040yrr y low leakage v 4 Ninos 4c Pmos Figure 2 5 N Channel MOS characteristics 18 21 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL 2 The MOS device Dynamic MOS behavior This paragraph concerns the dynamic simulation of the MOS to exhibit its switching properties The most convenient way to operate the MOS is to apply a clock to the gate another to the source and to observe the drain The summary of available properties that can be added to the layout is reported below VDD property High voltage property Noise VSS property Sinusoidal wave Clock property Pulse property O Apply a clock to the gate Click on the Clock icon and then click on the polysilicon gate The clock menu appears again Change the name into Vgate and cl
42. 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL 8 Analog Cells 1 00 Offset 150 mV VIN vn ARIAS NS NS YNN Yi a High gain at low Gain reduced frequency due to load capacitance 0 0 0 0 5 0 10 0 15 0 20 0 25 0 30 0 35 0 40 0 Time ns Figure 9 17 Simulation with Vin input offset tuned to optimum gain AmpliSingle MSK Simple Differential Amplifier The goal of the differential amplifier is to compare two analog signals and to amplify their difference The differential amplifier formulation is reported below Equation 8 3 Usually the gain K is high ranging from 10 to 1000 The consequence is that the differential amplifier output saturates very rapidly because of the supply voltage limits Vout K Vp Vm Equ 8 3 The schematic diagram of a basic differential amplifier 1s proposed in figure 8 18 An nMOS device has been inserted between the differential pair and the ground to improve the gain The gate voltage Vbias controls the amount of current that can flow on the two branches This pass transistor permits the differential pair to operate at lower Vds which means better analog performances and less saturation effects The best way to measure the input range is to connect the differential amplifier as a follower that is Vout connect to Vm The Vm property is simply removed and a contact poly metal is added at the appropriate place to build the bridge between Vout and Vm A slow ramp is applied on th
43. 3 15 The truth table is verified as follows A logic 0 corresponds to 0 V a logic 1 to a 1 0 V When the input rises to 1 the output falls to 0 with a 7 pico second delay 7 10 12 second The reason why the delay is larger before time 1 0 ns is that the circuit is warming up as the voltage supply suddenly rises from O to VDD at time 0 0ns The steady state is reached at time 1 0 ns Ring Inverter Simulation The ring oscillator made from 3 inverters has the property of oscillating naturally We observe the oscillating outputs in the circuit of Fig 3 15 and measure their corresponding frequency The ring oscillator circuit can be simulated easily at layout level with Microwind using various technologies The time domain waveform of the output is reported in Fig 3 16 for 0 8 um 0 18 um and 45 nm technologies high speed option Although the supply voltage VDD has been reduced VDD is 5V in 0 8 um 2V in 0 18um and 1 0 V in 45 nm the gain in frequency improvement is significant 38 21 09 2009 MICROWIND DSCH v3 5 LITE USER S MANUAL 3 The Inverter Ring oscillator with 5 inverters Figure 3 15 Schematic diagram and layout of the ring oscillator used for simulation INV5 MSK Use the command File Select Foundry to change the configuring technology Select sequentially the cmos08 RUL rule file which corresponds to the CMOS 0 8 um technology the cmos018 RUL rule file 0 18um technology and
44. 5 3 A Metal6 width 8 A Between two metal6 15 Minimum surface 300 A Via6 width 4A Between two Via6 6 Extra metal6 over via6 3 A Extra metal7 over via6 3 A Metal7 width 8 A Between two metal7 15 A Minimum surface 300 A rd01 Metal5 rg01 Metal7 11 rd02 A Via6 rh02 Design Rules Metal5 re04 rg04 Metal7 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 11 Design Rules Via 7 ri01 Via7 width 4 E aa ri02 Between two Via7 6 A a ri04 Extra metal7 over via7 3 A ee ri05 Extra metal8 over via7 3 Via7 ri01 Metal 8 rj01 Metal8 width 8 A rj02 Between two metal8 15 rjl0 Minimum surface 300 47 Pads The rules are presented below in um In RUL files the rules are given in lambda As the pad size has an almost constant value in um each technology gives its own value in A rp01 Pad width 50 um rp02 Between two pads 50 um rp03 Opening in passivation v s via Sum rp04 Opening in passivation v s metals Sum rp05 Between pad and unrelated active 20 um area rp01 119 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 15 References 13 MICROWIND and DSCH Menus Microwind 3 5 menus PP EE EEE EE E memo o Fie View Edit Simulate Compile An New Ctrl N FILE MENU Open Fa l PAP insert layout Import Layout onvert Into E the ave layout Ctl S Save As Select Foundr
45. ALE DOWN 1 Technology Scale Down The Moore s Law Recognizing a trend in integrated circuit complexity Intel co founder Gordon Moore extrapolated the tendency and predicted an exponential growth in the available memory and calculation speed of microprocessors which he said in 1965 would double every year Moore With a slight correction 1 e doubling every 18 months see figure 1 1 Moore s Law has held up to the Itanium 2 processor which has around 400 million transistors Circuit Complexity 1 GIGA os Itanium ie Moore s law with a E OS AS _P ntium Ter 100 MEG doubling each 18 2 X months Pentium NO A i t 10 MEG Moore law witha Pai A doubling each year EA TE TA E e e e eS 100K nd hs 1970 1975 1980 1985 1990 1995 2000 2005 2010 Figure 1 1 Moore s law compared to Intel processor complexity from 1970 to 2010 Scaling Benefits The trend of CMOS technology improvement continues to be driven by the need to integrate more functions within a given silicon area Table 1 gives an overview of the key parameters for technological nodes from 180 nm introduced in 1999 down to 22 nm which is supposed to be in production around 2011 Technology node 130nm 90nm_ 65nm_ 45nm_ 32 nm 22mm 2001 2003 2005 2007 2009 2011 Effective gate 70 nm 50 nm 35 nm 25 nm 17 nm 12 nm length High K High K High K Kgates mm 240 480 9001500 2800 4500 Memory poin
46. ANUAL 2 The MOS device 0 1 C 1 A o 1 o A4 Good 0 1 AN A Poorl VDD Vt Figure 2 8 The nMOS device behavior summary The MOS Models Mos Level 1 For the evaluation of the current ds between the drain and the source as a function of Vd Vg and Vs you may use the old but nevertheless simple LEVELI described below The parameters listed in table 2 1 correspond to low leakage MOS option which is the default MOS option in 45 nm technology When dealing with sub micron technology the model LEVELI is more than 4 times too optimistic regarding current prediction compared to real case measurements 8 85 10 F m is the absolute permittivity relative permittivity equal to 10 in the case of HfO no unit Mode Expression for the current Ids LINEAR Vds lt Vgs Vt ce W Vv y Ids v0 EL Hay 0 v Lely TOX de Z SATURATED Vds gt Vgs Vt Mos Levell parameters Parameter Definition Typical Value 45nm NMOS PMOS Threshold voltage 0 18 V 0 15 V TOXE Equivalent gate oxide thickness 3 5 nm Surface potential at strong 0 15 V 0 15 V inversion Bulk threshold parameter 0 4 VP MOS channel width 80 nm minimum a MOS channel length 40 nm minimum Table 2 1 Parameters of MOS level 1 implemented into Microwind Carrier mobilit 0 016 m7 V s 0 012 m7 V s EO UO PHI L The High K dielectric enabled a thinner equivalent oxide thickness while keeping leakage current low The equivalent
47. Line Select the line corresponding to the 2 input NAND description as shown above The input and output names can be by the user modified Click Compile The result is reported above The compiler has fixed the position of VDD power supply and the ground VSS The texts A B and S have Pmos devices also been fixed to the layout Default clocks are assigned to inputs A and B NAND2 output Nmos devices AA y TARA VENDES PETT ey Anan Input A Figure 4 3 A NAND cell created by the CMOS compiler 42 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 4 Basic Gates The cell architecture has been optimized for easy supply and input output routing The supply bars have the property to connect naturally to the neighboring cells so that specific effort for supply routing is not required The input output nodes are routed on the top and the bottom of the active parts with a regular spacing to ease automatic channel routing between cells The AND gate As can be seen in the schematic diagram and in the compiled results the AND gate is the sum of a NAND2 gate and an inverter The layout ready to simulate can be found in the file AND2 MSK In CMOS the negative gates NAND NOR INV are faster and simpler than the non negative gates AND OR Buffer The cell delay observed in the simulation of figure 4 4 are significantly higher than for the NAND2 gate alone due to the inverter stage delay Notice th
48. N gate lt bat dle ES gt Ee Meee 30 nm effective channel channel Figure 2 13 Cross section of the nMOS devices allMosDevices MSK Parameter NMOS NMOS Low leakage High speed Drawn length nm 400 Effective length nm EX EN 7 Threshold voltage V 0 18 lon mA um at VDD 1 0V__ 09 2 40 30 12 Ioff nA um Table 3 nMOS parameters featured in the CMOS 45 nm technology provided in Microwind 25 21 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL 2 The MOS device Ids ua High speed Ion lds uA I 290 0 Imax 0 9 mA 25 increase of the maximum current a Low leakage W l um Leff 35nm b High speed W lum Leff 30nm Figure 2 14 Id Vd characteristics of the low leakage and high speed nMOS devices Ids A lds A Id Vg for Vb 0 Vds 1 V a low leakage MOS Leff 35 nm b high speed MOS W 1 um Leff 30 nm Figure 2 15 Id Vg characteristics log scale of the low leakage and high speed nMOS devices The drawback of the high speed MOS current drive is the leakage current which rises from 7 nA um low leakage to 200 nA um high speed as seen in the Id Vg curve at the X axis location corresponding to Vg O V Fig 2 15 b High Voltage MOS At least three types of MOS devices exist within the 45 nm technology implemented in Microwind the low leakage MOS default MOS dev
49. NIN RK ek N CIN ek eae Y LL A LA aman Mi 2 columns SRS ROR OKOKER EPR RRR AAA TA VALLA LANA SSR a EMV N CANIN IY D NAALD GX Yaa y PTI DD if Selected column a a Column Select Column it iT I y LIVE ZARZA TA a wa Rt pT NI NNN INNA NITTANY OO N address Read Write Circuit I M gil LI DataOut Dataln Figure 8 1 Typical memory organization RAM Memory The basic cell for static memory design is based on 6 transistors with two pass gates instead of one The corresponding schematic diagram is given in Figure 7 2 The circuit consists of the 2 cross coupled inverters but uses two pass transistors instead of one 69 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 7 Memory circuits Bit Line BL Memory Cel et Line BL Data Data Word ine Parl i Figure 8 2 The layout of the 6 transistor static memory cell RAM6T SCH 4x4 Matrix of ET memory cells ebay thiol al WILTS BL 0 BL 1 BL 2 BL 3 Figure 8 3 An array of 6T memory cells with 4 rows and 4 columns RAM6T SCH The cell has been designed to be duplicated in X and Y in order to create a large array of cells Usual sizes for Megabit SRAM memories are 256 column x 256 rows or higher A modest arrangement of 4x4 RAM cells is proposed in figure 7 3 The selection lines WL concern all the cells of one row The bit lines BL and BL concern all the cells of one column The RAM layout is
50. O iNsn M TOULOUSE de Toulouse Microwind amp Dsch Version 3 5 3D Package Viewer 3D information gt coordinates in 199 gt coordinates in Y 67 gt y starts 2 User s Manual Lite Version Etienne Sicard www microwind org September 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL About the author Etienne SICARD was born in Paris France June 1961 He received the B S degree in 1984 and the PhD in Electrical Engineering from the University of Toulouse in 1987 in the laboratory LAAS of Toulouse He was granted a Monbusho scholarship and stayed 18 months at Osaka University Japan 1988 1989 Previously a professor of electronics in the Department of Physics University of Balearic Islands Spain 1990 Etienne SICARD is currently a professor at INSA of Toulouse France Department of Electrical and Computer Engineering He is a visiting professor at the electronic department of Carleton University Ottawa in 2004 His research interests include several aspects of integrated circuits ICs for improved electromagnetic compatibility EMC and the development of tools for speech processing applied to speech therapy Etienne SICARD is the author of several books as well as software for CMOS design Microwind EMC of ICs signal processing MentorDSP speech therapy Vocalab and EMC of integrated circuits IC EMC He is a member of French SEE and senior member of the IEEE EMC society He w
51. SCH V3 5 LITE USER S MANUAL 7 Memory circuits 8 Memory Circuits Basic Memory Organization Figure 7 1 shows a typical memory organization layout Sharma It consists of a memory array a row decoder a column decoder and a read write circuit The row decoder selects one row from 2 thanks to a N bit row selection address The column decoder selects one row from 2 thanks to a M bit column selection address The memory array is based on 2 rows and 2 columns of a repeated pattern the basic memory cell A typical value for N and M 1s 10 leading to 1024 rows and 1024 columns which corresponds to 1048576 elementary memory cells 1Mega bit 2 rows Selected Selected row memory cell 2N x 2 bit of XA dg memory 4 4 ae 7 VREE a g ZS RSLS Spe ses SSS SESSA SRR SSSR OV IV IV ITY IN NINA IN PEPER AD 4 NON IN ININININ IN AA LAILALA m4 a ASAAN ANAN ANAN aD a Nan anak Ser Wa lt aten Z SARK SAS IRN SR KS ok an Y TA Yaa NJ a han LIN K gt IY xe AN A HO a AN one PPP man SRS S HAL AYNA PRE Se y RR A ALLA LA ok NI SESS Sh a TT LAL sa SC vi Y lt P lt gt HER aan NNT Soe SS PTY TV a NANA ANA ARANA AN AN IA AS nal Na Na lt gt gt gt AYT N a RSRS SAS aks U NI PISA LS LS gE eR one Se lt S AA SS Y MAL ASAS Nu an Y YY LRE ANARAN ANAN ANA OEE EA O
52. The weakness of such a circuit is the use of positive logic gates leading to multiple stages A more efficient circuit consists in the same function but with inverting gates 48 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 5 Arithmetics Full Adder A B C Sum Carr 0 0 0 0 0 LI A mn 0 0 1 1 0 0 l 0 l 0 Ol Sum 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 L C f 1 1 0 0 1 1 1 1 1 1 m 5 i ea LJ LJ In Carry Figure 5 4 The truth table and schematic diagram of a full adder FADD SCH Full Adder Symbol in DSCH When invoking File Schema to new symbol the screen of figure 5 5 appears Simply click OK The symbol of the full adder is created with the name fadd sym in the current directory A Verilog description of the circuit 1s attached to the symbol We see that the XOR gates are declared as primitives while the complex gate is declared using the Assign command as a combination of AND amp and OR I operators If we used AND and OR primitives instead the layout compiler would implement the function in a series of AND and OR CMOS gates loosing the benefits of complex gate approach in terms of cell density and switching speed Use the command Insert gt User Symbol to include the full adder symbol into a new circuit For example a 4 bit adder is proposed in figure 5 6 The two displays are connected to the identical data but are configured in different mode hexadecimal format for the right most display and integer mode
53. WN 77722 RAR gt e s WWE 7 2 Source N diffusion Drain N diffusion Figure 3 11 The 2D process section of the inverter circuit near the nMOS device InvSteps MSK 35 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 3 The Inverter To build an electrical connection a physical contact is needed The corresponding layer is called contact You may insert a metal to TiN contact in the layout using a direct macro situated in the palette The Process Simulator shows the vertical aspect of the layout as when fabrication has been completed This feature is a significant aid to understand the circuit structure and the way layers are stacked on top of each other A click of the mouse on the left side of the n channel device layout and the release of the mouse at the right side give the cross section reported in figure 3 10 Supply Connections The next design step consists in adding supply connections that is the positive supply VDD and the ground supply VSS We use the metal2 layer Second level of metallization to create horizontal supply connections Enlarging the supply metal lines reduces the resistance and avoids electrical overstress The simplest way to build the physical connection is to add a metal 1 metal 2 contact that may be found in the palette The connection is created by a plug called via between metal 2 and metal layers The final layout design step consists in adding polarization contacts These contact
54. advanced MOS model called BSIM4 has been introduced in 2000 Liu A simplified version of this model is supported by MICROWIND in its full version and recommended for nanoscale technology simulation BSIM4 still considers the operating regions described in MOS level 3 linear for low Vds saturated for high Vds subthreshold for Vgs lt Vt but provides a perfect continuity between these regions BSIM4 introduces a new region where the impact ionization effect is dominant 22 21 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL 2 The MOS device The number of parameters specified in the official release of BSIM4 is as high as 300 A significant portion of these parameters is unused in our implementation We concentrate on the most significant parameters for educational purpose The set of parameters is reduced to around 20 shown in the right part of figure 2 10 H Nmos Width 0 580 Length 0 040 um 29x2 lambda ld vs Vd 1d vs va log a vs va Threshold voltage Capacitance Levelt Levera ESIN Ids uA 550 0 l l VTHO 0 190 nes Ki 0 750 a 500 0 ef dl K2 0 100 E an Toxe 3500 lt 450 0 ae ovo 2300 af a pyri fosso Af 400 0 at arn LPeo 2200 A e ee NrACT 0 100 af 350 0 a as pscgesf230 000 el a ug 0 020 4 300 0 L j e i ua feso Af rs 0 60 UC 0 047 250 0 ES A vsat 100 000 Af i ee Perm 1 100 Al 200 0 he unt ooo A
55. al Create a line Add a connection between lines Add text in the schematic diagram 21 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL Insert Menu Insert a user symbol or a library symbol not accessible from the symbol palette View Menu Redraw all the schematic diagral Zoom In Zoom out the window Extract the electrical nodes Show the timing diagrams Show the palette of symbols Simulate Menu Detect unconnected lines Simulate options 125 eck Floating Line TNI Insert View Simulate Help User Symbol SMT Another Schema SCH View Simulate Help o All Cheles VIE Same zoom In 4 Zoom Cut List of symbols Design hierarch Electrical Met Timing Diagram Le Symbol Library Unelect All Simulate Help Show Critical Path Ctrl I Er Pe Start simulation Logic Circuit Testing ATPG Simulate Options 15 References Insert an other schematic diagram Redraw the screen Give the list of symbols Describes the design structure Show details about the critical path Unselect all the design Show the critical path Longest switching path Start stop logic simulation Inject fault and optimize test vectors 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 15 References Symbol Palette Advanced logic symbol library Basic logic Symbol library symbol library na Basie aawbhced Button gt
56. al 1 for drain and source Connection between Devices Within CMOS cells metal and polysilicon are used as interconnects for signals Metal is a much better conductor than polysilicon Consequently polysilicon is only used to interconnect gates such as the bridge 1 between pMOS and nMOS gates as described in the schematic diagram of figure 3 6 Polysilicon is rarely used for long interconnects except if a huge resistance value is expected 5 Connexion to a power supply VDD 1 Bridge between nMos 3 Bridge between and pMos gates a nMos and pMos 4 Connexion to Yo output 2 Contact to input A 6 Connexion to ground Figure 3 6 Connections required to build the inverter CmosInv SCH 33 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 3 The Inverter 1 Polysilicon Bridge between pMOS and nMOS gates 2 lambda polysilicon gate size to achieve fastest switching Figure 3 7 Polysilicon bridge between nMOS and pMOS devices InvSteps MSK In the layout shown in figure 3 7 the polysilicon bridge links the gate of the n channel MOS with the gate of the p channel MOS device The polysilicon serves as the gate control and the bridge between MOS gates Useful Editing Tools The following commands may help you in the layout design and verification processes Icon Short cut Description UNDO CTRL U Cancels the last editing operation pee eee Erases some layout included in the given area or
57. and digital to analog CONnVerers iii eee Rds ees 100 Added Beatuires in the Full VErslO mater neer ea dende 103 EE InputlOutput Interface alae oe el aa 105 The Bonds Pad A didas 105 A A RE O PES OO o A A 106 NS A e ledenbestand a beeke 106 5 21 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL Mpat STUC Mres A Ot 107 Frehvoltase MO Sis A A A A edn 109 A 111 Added Features in the EU da idad 112 12 Design Rules alarcon 113 Selecta Desion Rule Ple A eee eee aie 113 DE AU AS GTS ancien EN 114 PENN e eee eneen 114 A O E O A A 114 PolysiliconiMeta Gata ao 115 2 Polysilicon Metal gate Design Rules ccsessssssesesssssvscsescsesssssvscsescscesscsavavscscscecssavavavssecsesssavavavseseneeseees 115 INO SOO iS A EA a 115 COCA asta TA E 116 Metal ene aoe te eee ee a Wn moe Or Taree a OTe 116 KOEN 116 ME A ad 116 en 117 Metal Sitioco 117 VA dende elden a ea ld o de 117 Meta Arne A a 117 A An 117 Meta doo 118 A A A TACT EA GIT Te N 118 Metal ad 118 A occa cece tc ae te et ta seca 118 IMIG TAN Poems a pete nennen eben erebaan 118 Nae O A eeen E 119 Metal Sa E Ad 119 A O E noaded kontante 119 13 MICROWIND and DSCH MENUS a 120 NUCLEO Md MEN ta 120 DCH MENUS unit idad 124 Silicon Menos a tos 126 WW WV INICFOW AAA naer ehelemaal 128 14 Student Rrojeclts ONAME raien a A a aaia 128 IS Ren o 129 6 21 09 2009 MICROWIND amp DSCH V3 1 LITE USER S MANUAL INTRODUCTION Introduction The present document introduces the
58. as elected in 2006 distinguished IEEE lecturer for EMC of ICs Email etienne sicard insa toulouse fr Copyright Copyright 1997 2009 by INSA Toulouse University of Toulouse FRANCE ISBN ISBN 13 numbers 978 2 87649 057 4 Published by INSA Toulouse University of Toulouse 135 Av de Ranguell 31077 Toulouse France First print October 2009 Legal deposit October 2009 2 21 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL Books Using Microwind Chip Design for Submicron Basic CMOS cell Design VLSI CMOS Layout and by Etienne Sicard and Sonia Simulation by John B ds C S of Bendhia McGraw Hill Uyemura Georgia Institute j Faka India _ of Technology USA p 2005 ISBN 0 07 059933 5 AE We http www engineering tho only available in India RER VESI msonlearning com Cell Design 2005 IBSN 053446629X ETIENME SICARO TONA DELMAE DEN DHIA i A book about design of This book is about advanced ail examens CMOS integrated circuits in p mer design of CMOS integrated deep submicron Advanced circuits in deep submicron technologies based on E technologies It deals with CMOS Microwind and DSCH CMOS microprocessors embedded Basics of written by Etienne SICARD Mapa gn memories RF cells and Sonia BEN DHIA converters FPGAs McGraw Hill professional ie packaging SOI and future series USA Jan 2007 ha McGraw Hill professional A ISBN 007148839
59. ayout Prentice Hall 2001 ISBN 0 13 087061 7 Lee1993 K Lee M Shur T A Fjeldly T Ytterdal Semiconductor Device Modeling for VLSI Prentice Hall 1993 ISBN 0 13 805656 0 Lee2005 Lee B H Challenges in implementing high k dielectrics in the 45nm technology node 2005 International Conference on Integrated Circuit Design and Technology ICICDT May 2005 pp 73 76 Liu2001 W Liu Mosfet Models for SPICE simulation including Bsim3v3 and BSIM4 Wiley amp Sons 2001 ISBN 0 471 39697 4 Moore1965 Moore G E 1965 Cramming more components onto integrated circuits Electronics Volume 38 N 8 Nec2007 M Tada Feasibility Study of 45 nm Node Scaled Down Cu Interconnects With Molecular Pore Stacking MPS SIOCH Films IEEE Trans On Electron Devices Vol 54 No 4 April 2007 Osishi2005 Oishi A High performance CMOSFET technology for 45nm generation and scalability of stress induced mobility enhancement technique IEEE International Electron Devices Meeting 2005 IEDM Technical Digest 2005 pp 229 232 Razavi2001 B Razavi Design of Analog CMOS integrated circuits McGraw Hill ISBN 0 07 238032 2 2001 www mhhe com Sicard 2005 E Sicard S Ben Dhia Basic CMOS cell design Tata McGraw Hill 2005 ISBN 0 07 059933 5 Sicard2005b E Sicard Introducing 90 nm technology in Microwind3 application note July 2005 www microwind org Sicard 2006 E Sicard M Aziz Introducin
60. d simulation of the FRAM is proposed Interfacing Some information is provided about the Double data Rate memories which involve both the rise and fall edge of the clock 79 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 8 Analog Cells 9 Analog Cells This chapter deals with analog basic cells from the simple resistor and capacitor to the operational amplifier A very complete description of analog cells may be found in Razavi and details on analog layout techniques may be found in Hastings Resistor An area efficient resistor available in CMOS process downto 65 nm consists of a strip of polysilicon The resistance between s and s2 is usually counted in a very convenient unit called ohm per square noted Q The default value polysilicon resistance per square is 10Q which is quite small but rises to 200Q if the salicide material 1s removed Figure 8 1 Metal poly contact polysilicon 7x10Q 70Q E VW S1 S2 Al One square ne accounts for 10Q Option layer which removes the salicide 7x2000 14000 NANA Sl S2 One square accounts for 2000 Figure 9 1 The polysilicon resistance with unsalicide option As the default technology in Microwind 3 5 1s 45 nm where polysilicon has been replaced by metal use File gt Select Foundry and choose cmos65nm RUL to reconfigure the software to a CMOS process using polysilicon as gate material In the cross section shown in figu
61. dacci d 15 MOS TO ita 16 Verea las pec Ol me MOS e eed 17 Static Mos GNAFACLE nto E cia 18 Dynamic MOS Dear os lla ltda talado etica 19 AOS Id tiara cieia 20 The MOS Model da a a en 21 The PMOS Insisto out ocasionada enciendes arias 23 MOS device OPUS ii dolia etica 24 PAIS VO ACS MO Sita A odds 26 The Tet AMS MSS 1 OU Gate eo alce 27 MA AE 28 Added Peatlites a hell VEESTON iia 30 3 The Inverto aene Ni 31 The Lovic iverne ie A ici 31 The CMOS 10verter hs 32 Manual Layout ofthe vete sntersteorverrraotenrrotodedanterdordeedentedendedenboederhee enen eenuoleneen delende dienden 32 COMME CHOM DELWEEN DEMO erneer lede lee 33 WISE EUN LOOS enaa aen onnisee nessen entente de enatioe nde enn annen tdeanaiensneenieennidens ten 34 Create Ief la Ver contada a aia 34 SU LC OMMCC HONS iesse a a dai 36 Process steps to DUNG ING venere id 36 yeer o ATO VELA OEE 37 Rine Inverter Simulation idilio 38 Added Features in the Full VEO iaa 40 4 DOO Gl es eos 41 tod eren neer tee hetere 41 4 21 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL CAN Tt AE eaten ace sees eae aoe aaa oa crane ae ieetatace aceon E E O 4 AREND EME da eetbaar dear tanende sede sta a doa edet 43 Fe NONE mre tere tenet tenten eet R 43 NADIE OL shi er as shoe eae dean ae 45 Added Eeatures ti the Bulk Verstoten A AS 46 OEE A aaislecutensacsetunidedntuncete tues decianssesptensdetutuneeteiasdecsasgss 47 Unsienca Tine Wer LOMA zen A A a A 4 Hit Adder Gate O A SA eee 4 F
62. design and simulation of CMOS integrated circuits in an attractive way thanks to user friendly PC tools DSCH and MICROWIND The lite version of these tools only includes a subset of available commands The lite version is freeware available on the web site www microwind net The complete version of the tools is available through ni2designs India www ni2designs com About DSCH The DSCH program is a logic editor and simulator Bll Dsch3 5 DADocuments and Settings sicarc Mes documents software Dsch Dschsa dschaa full examplesitest inandar faultalnjectorsen EE lolx a cas ewes oe DSCH is used to validate the architecture of the logic ry Fault injection ae circuit before the microelectronics design is started a DSCH provides a user friendly environment for A En ZEE An a Dm e ne hierarchical logic design and fast simulation with delay analysis which allows the design and validation of a MA T i H a a tes gt an i complex logic structures DSCH also features the w E Fn an EEE J symbols models and assembly support for 8051 and 18f64 microcontrollers DSCH also includes an interface to WinSPICE About MICROWIND The MICROWIND program allows the student to design L Microwind35 DiDocuments and SettingsisicardiMes documents sortware Microwind microwindsa exainples en inters Cle ck JiV2 ME lo x EE ees ee Ee
63. ds a 1 The bit line is precharged to a voltage Vp Usually around VDD 2 When the word line is active a communication is established between the bit line loaded by capacitor CBL and the memory loaded by capacitor CS The charges are shared between these nodes and the result is a small increase of the voltage Vp by AV thanks to the injection of some charges from the memory The cross section of the DRAM capacitor is given in figure 7 12 The bit line is routed in metal2 and is connected to the cell through a metall and diffusion contact The word line is the polysilicon gate On the right side the storage capacitor is a sandwich of conductor material connected to the diffusion a thin oxide S102 in this case and a second conductor that fills the capacitor and is connected to ground by a contact to the first level of metal 19 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 7 Memory circuits Fe Lites iel E Bini ignis Ie i CNCR ACA te 15 Sie Ema Maia la ld e LI lm nl ml ml ei S Sd al ll AA EN OO OEE On E A eo ee E e a gt A skeereeerrrd Li Bee ed HEEE ll e el al ahd a rel pa EE BE d B sl O la ee ee baaa len A ee gt 2 EE eed i uoa u m m ie GIN ed Figure 8 12 The stacked capacitor cell and its cross section DramEdram MSK The capacitance is around 20fF in this design Higher capacitance values may be obtained using larger option lay
64. e warm up phase due to the progressive setup of the power supply followed by a steady state time 1 0ns 50 lee 5 b i TUL ii HUE ii 1 00 0 040 a ae SA mae DA FI Fo ZEE o E EEEREN EE EE APAA and 10ps RT i ips TEM E AAA ia AAA AAA Fl HOH IES J 0 040 Pans D l 00 01 02 0 9 Time ns Figure 4 4 Layout and simulation of the AND gate and2 msk The XOR Gate The truth table and the schematic diagram of the CMOS XOR gate are shown above There exist many possibilities for implementing the XOR function into CMOS The least efficient design but the most forward consists in building the XOR logic circuit from its Boolean equation 43 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 4 Basic Gates Et XOR 2 inputs al A B OUT out 0 0 0 b 0 1 1 1 0 1 Or 1 1 0 The proposed solution consists of a transmission gate implementation of the XOR operator The truth table of the XOR can be read as follow IF B 0 OUT A IF B 1 OUT Inv A The principle of the circuit presented below is to enable the A signal to flow to node N if B 1 and to enable the nv A signal to flow to node N if B 0 The node OUT inverts N1 so that we can find the XOR operator Notice that the nMOS and pMOS devices situated in the middle of the gate serve as pass transistors i y E Aare Figure 4 5 The schematic diagram of the XOR gate XORCmos SCH nxor A CES LTL LLL AZ LLL LLL EZ LZ
65. e CMOS inverter at logic level using the logic editor and simulator DSCH and at layout level using the tool MICROWIND The Logic Inverter In this section an inverter circuit is loaded and simulated Click File Open in the main menu Select INV SCH in the list In this circuit are one button situated on the left side of the design the inverter and a led Click Simulate gt Start simulation in the main menu Lhe Det Zn o F A Figure 3 1 The schematic diagram including one single inverter Inverter SCH Now click inside the buttons situated on the left part of the diagram The result is displayed on the leds The red value indicates logic 1 the black value means a logic 0 Click the button Stop simulation shown in the picture below You are back to the editor En Simulation Contra e Show wire state Pin state Symbol state Figure 3 2 The button Stop Simulation Click the chronogram icon to get access to the chronograms of the previous simulation Figure 3 3 As seen in the waveform the value of the output is the logic opposite of that of the input 0 0 eU0 400 600 0 0 1000 2 Ons dur biaia ai A Button n light Figure 3 3 Chronograms of the inverter simulation CmosInv SCH 31 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 3 The Inverter Double click on the INV symbol the symbol properties window is activated In this window appears the VERILOG description left side and
66. e input Vin and the result is observed on the output We use again the Voltage vs Voltage to draw the static characteristics of the follower 89 21 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL 8 Analog Cells PifLarge L P2fLarge L out MifLarge L Controled dissipation with Wbias blas Figure 9 18 An improved differential amplifier AmpliDiff SCH The simulation of the circuit is performed here using the CMOS 45 nm technology You may also simulate the circuit in other technologies using the command File Select Foundry As can be seen from the resulting simulation reported in figure 8 19 a low Vbias features a larger voltage range specifically at high voltage values The follower works properly starting 0 2 V independently of the Vbias value Fig 8 20 A high Vbias leads to a slightly faster response but reduces the input range and consumes more power as the associated nMOS transistor drives an important current The voltage Vbias is often fixed to a value a little higher than the threshold voltage Vin This corresponds to a good compromise between switching speed and input range Label used to force BSIM4 model at simulation rather than Model 3 p BSIM4 Used to force BSIM4 model by default PMOS current mirror with large length nMOS differential pair with large length OpAmp connected as a follower Voltage control of the global current consumption oo i
67. e of the design The inverter and NOR gates are at the right side After the initialization A B rises to 1 The clocks A and B produce the combinations 00 01 10 and 11 50 21 09 2009 MICROWIND DSCH v3 5 LITE USER S MANUAL 5 Arithmetics PATATA TIA III PIT ITT FE Be i EEE ZE esseede E COCPLLRELL LL AA OEE ERE E LILELIALA AA ALA EEE EE Bir E man A y AA SS TAPA AAA AAA EA A AA Y stb ah A A A ZZZ Bean Tipar Hop et HER i a AeB AIB ASB Jak r f 7 f 0 000 1 0 1 1 12 1 3 14 1 5 1 6 1 7 1 8 1 9 Time ns Figure 5 8 Simulation of a comparator COMP MSK Fault Injection and test vector extraction Design of logic integrated circuits in CMOS technology is becoming more and more complex since VLSI is the interest of many electronic IC users and manufacturers A common problem to be solved by designers manufacturers and users is the testing of these ICs In DSCH 3 5 we introduce the concept of fault concentrate on stuck at 0 and stuck at l hypothesis and show how these faults may appear Then using DSCH we show how to build a reference truth table and how to simulate these faults applied to input and output nodes of the circuit under test We investigate how test patterns detect these faults The ultimate goal 91 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 5 Arithmetics is to classify the efficiency of test patterns in order to select the most efficient
68. e right side the ADC takes an analog input signal Vin and converts it to a digital output signal A The digital signal A is a binary coded representation of the analog signal using N bits Ayn Ao The maximum number of codes for N bits is 2 The digital signal is usually treated by a microprocessor unit MPU or by a specific digital signal processor DSP before being restituted as an output B Then the DAC which has the opposite function compared to the ADC converts the digital signal to the final analog output signal Vout PES OUT Figure 10 13 Basic principle of N bits analog to digital and digital to analog converters The most basic DAC is based on a resistance ladder This type of DAC consists of a simple resistor string of 2 identical resistors and a binary switch array whose inputs are a binary word The analog output is the voltage division of the resistors flowing via pass switches figure 9 14 In the implementation shown in figure 9 15 the resistance ladder includes 8 identical resistors which generate 8 reference voltage equally distributed between the ground voltage and Vdac The digital analog converter uses the three bit input B B 2 B 1 B 0 to control the transmission gate network which selects one of the voltage references A portion of Vdac which is then transferred to the output Vout A long path of polysilicon between VDD and VSS may give intermediate voltage references required for the DAC circ
69. ect all Generate MOS contacts es Unprotect All Ctrl P pads diodes resistors capacitors etc menerate Virtual RL or E i Connect layers at a desired Duplicate x Y B location Laver connection Ctrl HE invert Diffusion M lt gt P Protect and unprotect layers from copying moving erasing Add a virtual R L C for simulation purpose uplicate in X and Y a election of elements Invert the diffusion type from N to P and vice versa in a given area i Run the simulation and Select model 1 model 3 or 2 SIMUL ATE MENU 2 choose the appropriate mode BSIM4 E o VA E Simulate Compile is Help _ Run simulatigy Simulate directly on the Using mod layout with a palette of Simulation on Layout colors representing voltage With crosstalk Simulation parameters UY exposure to dischar Access to the SPICE model sand some simulation options VDD value temperature simulation step Discharge floating gates Include crosstalk effects in simulation IE mos characteris 2 2D vertical cross section 3D Process steps in 3D 3D view of the IC Opencl Access to static characteristics of the MOS devices 2D view of the circuit at View the process steps of the hedesired location layout fabrication in static 3D Real time view of the IC in full animated 3D Compile Analysis Help COMPILE MEN U Compile one Line Compile one single A Compile Verilog Eile line on line
70. eference logic value 1 line C Fault Free which enables the test vector 11 to alert the user from the possibility of 4 possible faults AGO BO0 B 1 COO All faults may be tested 100 coverage using three vectors 01 10 and 11 55 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 5 Arithmetics Added Features in the Full version Adders Full layout of the 4 bit adder Structure of the carry look ahead adder Details on the routing and supply strategy Arithmetic and Logic Basic principles of micro operations on 8 bit format Units Complete case studies with full adder complex gates 56 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 6 Microcontroller Model 6 Microcontroller Model This chapter details the implementation of a simplified model of two microcontroller the 8051 from Intel and the 16f54 from PIC 8051 Model The 8051 core includes an arithmetic and logic unit to support a huge set of instructions Most of the data format is in 8 bit format We consider here the following instructions listed in table 1 Some instructions do not appear in this list such as the multiplication and division Clear the accumulator Complements the accumulator a bit or a memory contents All the bits will be reversed resulting value in the accumulator Subtracts the operand to the value of the accumulator leaving the resulting value in the accumulator memory memory operand leaving the resu
71. er areas at the price of a lower cell density EEPROM The basic element of an EEPROM Electrically Erasable PROM memory is the floating gate transistor The concept was introduced several years ago for the EPROM Erasable PROM It is based on the possibility of trapping electrons in an isolated polysilicon layer placed between the channel and the controlled gate The charges have a direct impact on the threshold voltage of a double gate device When there is no charge in the floating gate Figure 7 13 upper part the threshold voltage is low meaning that a significant current may flow between the source and the drain if a high voltage is applied on the gate However the channel is small as compared to a regular MOS and the Ion current is 3 to 5 times lower for the same channel size Floating gate discharged d On Of 5 Floating gate charged with electrons Ee oe Figure 8 13 The two states of the double gate MOS EepromExplain SCH 76 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 7 Memory circuits nT la Eer aate control Controlled ae eee ee a Ze poly2 gate Ey Ey Ey ly Ey A Oce MiM Ll Poly2 metal EE oe ee eee ener ED ee contact E tw oate SUR te Floating poly poly gate gun Ultra thin gate oxide underneath poly2 co o Poly Poly2 oxide Floating RAVENA EA E A Pee I ics Bee vereert DENIA aod rie PRISA eee OEREN vereer CR TER AEL Far arn te A ep Poly2 on
72. ere the speed factor is not critical The leakage current 1s one order of magnitude lower than for the high speed variant with gate switching Parasitic leakage current Microwind 45 nm rule file High end High x 10 l servers Computing Servers Mobile Computing x High speed Moderate variant x 1 General Purpose variant Speed Low p x 0 1 Low Moderate Fast 50 0 50 Figure 1 8 Introducing three variants of the 45 nm technology decreased by 50 Only this technology has been implemented in Microwind There may also exist a third variant called low leakage bottom left of Fig 1 8 This variant concerns integrated circuits for which the leakage current must remain as low as possible a criterion that ranks first in applications such as embedded devices mobile phones or personal organizers The operational voltage is usually from 0 8 V to 1 2 V depending on the technology variant In Microwind we decided to fix VDD at 1 0 V in the cmos45nm RUL rule file which represents a compromise between all possible technology variations available for this 45 nm node 14 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 2 The MOS device 2 The MOS device This chapter presents the CMOS transistor its layout static characteristics and dynamic characteristics The vertical aspect of the device and the three dimensional sketch of the fabrication are also described Logic Levels Th
73. erence designs are shown in figure 8 11 The most common design uses one p channel MOS and one n channel MOS connected as diodes 85 21 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL 8 Analog Cells Voltage reference scale q RP vref WreRniRn Rp dd aman WE large L EN amos te Increase the resistance 77 DFS dd Alternative designs O5 dd 025 dd ref ref Figure 9 11 Voltage reference using PMOS and NMOS devices as large resistance ms EE a TO B Two pMOS Figure 9 12 Voltage reference circuits a with one nMOS and one pMOS b with two pMOS Vref MSK The alternative solutions consist in using two n channel MOS devices only Left lower part of figure 8 12 or their opposite built from p channel devices only Not only one reference voltage may be created but also three as shown in the right part of the figure which use four n channel MOS devices connected as diodes Amplifier The goal of the amplifier is to multiply by a significant factor the amplitude of a sinusoidal voltage input Vin and deliver the amplified sinusoidal output Vout on a load The single stage amplifier may consist of a MOS device we choose here a n channel MOS and a load The load can be a resistance or an inductance In the circuit we use a resistance made with a p channel MOS device with gate and drain connected Figure 8 13 The pMOS which replaces the passive load is called an active resistance 86 21 09
74. ers in 45nm technology range from metall to metal8 The layer metall is situated at the lowest altitude close to the active device while metalS is nearly 10um above the silicon surface Metal layers are labeled according to the order in which they are fabricated from the lower level metal to the upper level metals In Microwind specific macros are accessible to ease the addition of contacts in the layout These macros can be found in the palette As an example you may instantiate a design error free metal7 metal8 contact by selecting metalS followed by a click on the upper left corner icon in the palette CRE x LECE E E MEJO tts lve Metal layers used for short distance interconnects Layer used to connect metal to TinN metal to N 4 Mm Figure 2 19 Microwind window with the palette of layers including 8 levels of metallization 28 21 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL 2 The MOS device Metal 1 Metal2 contact macro Metall Metal2 Via amp Layout Generator Between metal Metal to Metal ith Poly and di f Polyto Metal 1 C N Diff to Metal 1 P Diffto Metal 1 None Metal amp to Metal Columns fi Metal5 to Metal Metald to Metals Metal3 to Metal4 to meta rows Hi to diff column an Generate Contact x Cancel Metal to Metal3 e Metall to Metal Figure 2 20 Access to contact macros between metal layers
75. es 3 active clock edges in the example shown in figure 7 17 The row address selection is active at the first rise edge followed by the column address selection The data 1s valid at the third fall edge of the system clock Read cycle trc New cycle Active edge yes Ni l i System Clock Clock A E eae ee E A l I l l i l l l Row Address Selection RAS 2 re O E Y ee i i Column Address Selection CAS l we DEEP l l l l wrie Enable w Rea l l l Data Out Dout Valid Dout l l Column Access Cycle tcac l 6 gt gt l l l i Row Access Cycle trac Figure 8 17 Synchronous RAM timing diagram Added Features in the Full version World of Semiconductor memories are vital components in modern integrated circuits The introductory memories part details the main families of memories Memories Compact memory cell obtained by sharing all possible contacts the supply contact the ground contact and the bit line contacts Detailed information about ROM memories Double gate The programming of a double poly transistor involves the transfer of electrons from the source MOS to the floating gate through the thin oxide Details are provided on the programming and charge removal Ferroelectric FRAM memories are the most advanced of the Flash memory challengers The FRAM RAM memory point is based on a two state ferroelectric insulator A complete description an
76. esign is saved under that filename Analog Simulation Click on Simulate Start Simulation The timing diagrams of the nMOS device appear as shown in Figure 2 7 Select the appropriate time scale 500 ps to see the chronograms of the simulation Click Reset to restart simulation at any time Y Analog simulation of example B lol x Display 1 00 0 960 a Delay o Bus value between E y vdrain and 1 v Evaluate E Min max Av Frequency vgate T F Poor 1 Ist y LIL FFT Vi ri r 3 kz More mn XX Close Good 0 MELIA ON EE 50ps 53ps P Onw Time Scale 0 000 0 050 0 100 0 150 0 200 0 250 0 300 0 350 0 400 Ee Voltage vs time AVoltages and currents Voltage vs voltage Step ps 1 p 100 0 45Time ns Figure 2 7 Analog simulation of the MOS device When vgate is at zero no channel exists so the node vsource is disconnected from the drain When the gate is on vgate 1 0 V the source copies the drain It can be observed that the nMOS device drives well at zero but poorly at the high voltage The highest value of vsource is around 0 6 V that is VDD minus the threshold voltage This means that the n channel MOS device do not drives well logic signal 1 as summarized in figure 2 8 Click on More in order to perform more simulations Click on Close to return to the editor 20 21 09 2009 MICROWIND DSCH V3 5 LITE USER S M
77. eventually cmos45nm RUL which configures Microwind to the CMOS 45 nm technology When you run the simulation observe the change of VDD and the significant change in oscillating frequency Technology Supply _ Oscillation 0 76 GHz 1 310ns 0 766 95 Time ns 0 134ns 7 466 1 0V 1 050 1 100 1 150 1 200 1 250 1 300 1 350 Figure 3 16 Oscillation frequency improvement with the technology scale down Inv5 MSK 39 21 09 2009 MICROWIND DSCH v3 5 LITE USER S MANUAL 3 The Inverter Added Features in the Full version Analysis of the inverter consumption the leakage etc 3 state inverter A complete description of the 3 state circuits with details on the structure behavior Inverter sizing effects Impact of the width and length of MOS devices on the inverter characteristics Real time 3D view 30 Pathog aaa Highlight layer option v Exercises Some basic exercises related to the inverter design and its static dynamic performances 40 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 4 Basic Gates 4 Basic Gates Introduction Table 4 1 gives the corresponding symbol to each basic gate as it appears in the logic editor window as well as the logic description In this description the symbol amp refers to the logical AND to Or to INVERT and to XOR A complete description of basic gate implementation may be found in Backer ogic symbol Logic equation INVERTER pe
78. f fi i WINT 0 020 lt 150 0 mr de j 7 0 40 km foos lt 7 E ute iso A vl 100 0 Tempe 27 000 50 0 4 ipa 9 bis ns a a keh dk ek ek ee A AAA AAA oe 0 00 J 0 00 0 20 0 40 pe 0 60 0 80 NS EN El E varomoto 1 000 Forvgromoto f1 000 stepvg 0 200 elf pumpiis _ LE Ads measure y OK la Draw LE Fit vi 1um L 0 040urr low leakage y E Nmos e Pmos Figure 2 10 Implementation of BSIM4 within Microwind full version only The PMOS Transistor The p channel transistor simulation features the same functions as the n channel device but with opposite voltage control of the gate For the nMOS the channel is created with a logic 1 on the gate For the pMOS the channel is created for a logic O on the gate Load the file pmos msk and click the icon MOS characteristics The p channel MOS simulation appears as shown in Figure 2 11 23 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 2 The MOS device 1 00 Vdrain 0 983 Vout 0 0 05 i 0 i 5 on m a T ui i Time ns Figure 2 11 Layout and simulation of the p channel MOS mypmos MSK Note that the pMOS gives approximately half of the maximum current given by the nMOS with the same device size The highest current is obtained with the lowest possible gate voltage that is 0 From the simulation of figure 2 11 we see that the pMOS device is able to pass well the logic level 1 But the logic level O is transformed into a
79. for the left most display Schema to Symbol x Os Verilog symbol preview A ssusenensesesanessesenans module fadd C B 4 Carry Sum input C B A output Carry Sum wire 15 16 8 v10 xor 18 xor2_1 w5 1 B nand 18 nand2_2 w6 4 C nand 18 nand2_3 wd B A xor 18 xor2_4 Sum w5 C nand 18 nand3_5 Carry w8 w10 w6 nand 18 nand2 6 w10 B C endmodule 1 Refresh al Symbol Properties Name fadd Title fadd Save as D Dacuments and x Cancel Figure 5 5 Verilog description of the full adder fadd SYM 49 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 5 Arithmetics Figure 5 6 Schematic diagram of the four bit adder and some examples of results Add4 SCH Comparator The truth table and the schematic diagram of the comparator are given below The A B equality represents an XNOR gate and A gt B A lt B are operators obtained by using inverters and AND gates Comparator A B A gt B A lt B A B 0 0 0 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 Figure 5 7 The truth table and schematic diagram of the comparator COMP SCH Using DSCH the logic circuit of the comparator is designed and verified at logic level Then the conversion into Verilog is invoked File Make verilog File MICROWIND compiles the verilog text into layout The simulation of the comparator is given in Figure 5 8 The XNOR gate 1s located at the left sid
80. frequency behavior High frequency behavior Figure 10 4 The behavior of a RLC circuit at low and high frequencies Inductor SCH 94 21 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL 9 Radio frequency Circuits The sinusoidal input reaches 3GHz sinus1 The sinusoidal input starts The input frequency is at 1000MHz around 2 4GHz here 7 T The coil resonance multiplies the output voltage by more than 10 KO OX X x 420ns 0 396ns 0 378ns 0 361ns 0 346ns 2 52G 2656 277G 289G ite 80 0 90 0 Time ns 1066 1166 1296 1416 153G 1666 1796 191G 20 The coil output follows j ii Y wi 0 0 10 0 20 0 30 0 40 0 50 0 de x x out 0 947ns 0 860ns 0 774ns 0 709ns 0 652ns 0 603ns 0 560ns 0 522ns 0 492 wil 65 Figure 10 5 The behavior of a RLC circuit near resonance Inductor3nHighQ MSK At a very specific frequency the LC circuit features a resonance effect The theoretical formulation of this frequency is given by equation 9 2 l 27 LUCI C2 Equ 9 2 We may see the resonance effect of the coil and an illustration of the quality factor using the following procedure The node A is controlled by a sinusoidal waveform with increased frequency Also called chirp signal We specify a very small amplitude 0 1 V and a zero offset The resonance can be observed when the voltage at nodes B and C is higher than the input voltage A The ratio between B and A is equal t
81. g 65 nm technology in Microwind3 application note available on www microwind org August 2006 Sicard2006b E Sicard Introducing 65 nm technology in Microwind3 application note July 2006 www microwind org Song2006 S C Song Highly Manufacturable Advanced Gate Stack Technology for Sub 45 nm Self Aligned Gate First CMOSFETs IEEE Trans On Electron Devices Vol 53 pp 979 989 May 2006 Sharma1996 A K Sharma Semiconductor Memories IEEE Press 1996 ISBN 0 7803 1000 4 Tsmc2004 Yang F L and al 45nm node planar SOI technology with 0 296um2 6T SRAM cell Digest of Technical Papers Symposium on VLSI Technology 15 17 June 2004 pp 8 9 Tsai2003 W Tsai Performance Comparison of Sub 1 nm Sputtered TiN HfO2 nMOS and pMOSFETs IEDM Tech Digest p 311 2003 129 21 09 2009 ISBN 13 digit 978 2 87649 057 4 First print October 2009 Achev d imprimer October 2009 Legal deposit D cembre 2009 D p t legal D cember 2009 Published by INSA Toulouse University of Toulouse 135 Av de Ranguell 31077 Toulouse France 130 21 09 2009
82. g amplifiers l Marcos Sanchez Felipe ae LOGICAS CON 2007 Univ of Oviedo Spain Caballo uan Diaz RANSISTORES MOS 2007 Univ of Oviedo Spain ed ES Juan D az DISE O DE MEMORIAS Marcos S nchez Felipe T 2007 Univ of Oviedo Spain cabello uan Diaz SECUENCIALES 2006 INSA Toulouse France Sele ai Dee ESSE Etienne SICARD Study operational on see in French ae Remi Fa A D converter in 2006 INSA Toulouse France COUSINI Mathieu Sonia BEN DHIA French 2009 128 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 15 References 15 References Backer1998 R J Backer H W Li D E Boyce CMOS design layout and simulation IEEE Press 1998 www ieee org Chau2004 R Chau Gate Dielectric Scaling for High Performance CMOS From S102 to High K IEDM Technical Digest 2004 Common2007 The Common Platform technology model is focused on 90 nm 65 nm and 45 nm technology http www commonplatform com home Fujitsu2005 Okuno M and al 45 nm Node CMOS Integration with a Novel STI Structure and Full NCS Cu Interlayers for Low Operation Power LOP Applications Fujitsu Laboratories Ltd proceedings of IEDM 2005 Ghani2003 T Ghani et al A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors Digest of International Electron Devices Meeting 2003 IEDM 03 Hastings2001 A Hastings The Art of Analog L
83. generated in the table l Simulate fault n 2 B 0 gg Chronograms 0 2 0ns El ER Extract Fault Response d Previous Pe Next X Close Figure 5 13 Two logic simulations are necessary to extract the response to the A 0 and BOO faults And2_test SCH Click Generate Faults to list the desired faults in the test vector grid situated on the left of the screen Notice that each column corresponds to one test vector As we have 2 inputs we have 4 columns each corresponding to one test vector for inputs AB respectively 00 01 10 and 11 The two faults considered here are A O and BOO In order to compute the response of the circuit to the AGO and B 0 faults proceed as follow Click Simulate fault n 1 A O Click Chronograms to see the response The node A is stuck at 0 and consequently the output C is 0 Figure 5 14 Chronograms showing the node A stuck at 0 And2_test SCH Click Extract Fault Response The logic values are transferred to the corresponding line Click Simulate fault n 2 BOO Click Extract Fault Response The circuit response to the 2 fault is also transferred By selecting Stuck at O amp stuck at 1 and applying it to Inputs amp Outputs we obtain the following response to the 6 faults 94 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 5 Arithmetics Circuit Testing E ES D x Truth Table TestVectors 1
84. gure 11 7 Layout of the input MOS device IOPadMos MSK The high voltage MOS layout differs slightly from the normal MOS The high voltage MOS uses a gate width which is much larger than that of the regular MOS Usually the lateral drain diffusion which aims at limiting the hot carrier effect at boosting the device lifetime is removed in high voltage MOS devices In 45 nm the gate oxide of the high voltage MOS is around 3 nm The gate oxide is twice thicker than the low voltage MOS The high voltage device performance corresponds approximately to a 0 18 um MOS device To turn a normal MOS into a high voltage MOS the designer must add an option layer The dot rectangle in figure 10 7 The tick in front of High voltage MOS assigns high voltage properties to the device double oxide removed LDD different rules for minimum length and different MOS model parameters 110 21 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL 10 I O Interfacing Level shifter The role of the level shifter is to translate the low voltage logic signal Data_Out into a high voltage logic signal which controls the buffer devices Figure 10 8 gives the schematic diagram of a level shifter circuit which has no problem of parasitic DC power dissipation The circuit consists of a low voltage inverter the level shifter itself and the buffer The circuit has two power supplies a low voltage VDD for the left most inverter and a high voltage VddHV for the rest
85. he window as well as the parasitic resistance and the resulting quality factor Q oa a 12nH 20 10pF L1 R1 10pF C1 C2 Figure 10 2 The equivalent model of the 12nH default coil and the approximation of the quality factor Q 93 21 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL 9 Radio frequency Circuits Far end of the coil Virtual symbol for the serial inductor Near end of the coil the serial resistor Figure 10 3 The inductor generated by default inductorl2nH MSK Using the default parameters the coil inductance approaches 12 nH with a quality factor of Q 1 15 The corresponding layout is shown in figure 9 3 Notice the virtual inductance L and resistance R symbols placed in the layout The serial inductor is placed between A and B and a serial resistance between B and C If these symbols were omitted the whole inductor would be considered as a single electrical node The coil can be considered as a RLC resonant circuit At very low frequencies the inductor is a short circuit and the capacitor is an open circuit Figure 9 4 left This means that the voltage at node C is almost equal to A if no load is connected to node C as almost no current flows through R7 At very high frequencies the inductor is an open circuit the capacitor a short circuit Figure 9 4 right Consequently the link between C and A tends towards an open circuit L1 A En C A De R1 R1 C1 E ir Ci C2 Low
86. ice the high speed MOS higher switching performance but higher leakage and the high voltage MOS used for input output interfacing In Microwind s cmos45nm rule file the I O supply is 1 8 V Most foundries also propose 2 5 V and 3 3 V interfacing 26 21 09 2009 MICROWIND DSCH v3 5 LITE USER S MANUAL 2 The MOS device 5 lambda nl 0 175pm DR eae eee eee ee re orm xil f Device Options 4 gt i 1 Double click in Iv low leakage the option box high speed f F high voltage ___ 7 Embedded DRAM L L OO option as low FT Remove salicide I El to increase resistance E 4 leakage Mas options ES mi p 2 Modify the MOS h IF Embedded FRAM Extract diode inside box HE oH MIM capacitor Node Properties a i CAPA 0 00fF Metal Capa 0 00 fF Crosstalk 0 00 fF Diffusion 0 00 fF a a Metal Res 0 Ohm out out3 out Poly Res 0 Ohm A 3 T J El al El E m Cont ia Res 0 Ohm i y Diff Res 0 Ohm uEnableOsc AS IU i E Sel l DELAY Rise delay 0 000 ns x i BSIM4 f Hide Unselect Figure 2 16 Changing the MOS type through the option layer The MOS type is changed using an option layer situated at the upper part of the palette The option layer b
87. ich features a higher permittivity and consequently improves the device performances while keeping the parasitic leakage current within reasonable limits Starting with the 45 nm technology leakage reduction has been achieved through the use of various high K dielectrics such as Hafnium Oxide HfO 12 Zyrconium Oxide ZrO 20 Tantalum Oxide Ta Os er 25 or Titanium Oxide TiO er 40 This provides much higher device performance as if the device was fabricated in a technology using conventional SiO with much reduced equivalent SiO thickness For the first time in 40 years of CMOS manufacturing the poly gate has been abandoned Nickel Silicide NiSi Titanium Nitride TiN etc are the types of gate materials that provide acceptable threshold voltage and alleviate the mobility degradation problem Fig 3 In combination with Hafnium Oxide HfO e 12 the metal high k transistors feature outstanding current switching capabilities together with low leakage Increased on current decreased off current and significantly decreased gate leakage are obtained with this novel combination The sheet resistance is around 52 square for the metal gate 10 21 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL Polysilicon Low resistive o EA en Si02 Gate oxide K 3 9 Source i I t 1 1 I I I t 7 Low capacitance a ae slow device High gate leakage 5 90 nm generation 1 TECHNOLOGY SCALE DOWN Lo
88. ick on OK to apply a clock with 0 1 ns period 45 ps at 0 5 ps rise 45 ps at 1 5 ps fall Add a Clock Label name DC Supply Clock Pulse Sinus Variable Ground PAL Math Parameters Level 1 6 1 000 Level 0 A 0 000 Time low tl Rise time tr Time high a Fall time ee 10 045 ns 10 005 ns lo 045 lo 005 TU Slower TUU Faster gt Last Clock X Cancel a Visible in simu Figure 2 6 The clock menu and the clock property insertion directly on the MOS layout Apply a clock to the drain Click on the Clock icon click on the left diffusion The Clock menu appears Change the name into Vdrain and click on OK A default clock with 0 2 ns period is generated The Clock property is sent to the node and appears at the right hand side of the desired location with the name Vdrain 19 21 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL 2 The MOS device Watch the output Click on the Visible icon and then click on the right diffusion Click OK The Visible property is then sent to the node The associated text s1 is in italic meaning that the waveform of this node will appear at the next simulation Always save BEFORE any simulation The analog simulation algorithm may cause run time errors leading to a loss of layout information Click on File Save as A new window appears into which you enter the design name Type for example Mosn MSK Then click on Save The d
89. immediate consequence is a more simple design which leads to a more compact memory array and more dense structures Flash memories are commonly used in micro controllers for the storage of application code which gives the advantage of non volatile memories and the possibility of reconfiguring and updating the code many times 77 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 7 Memory circuits Discharged Charged Read a 0 Read a 1 Charge No charge HVDD a Discharge Discharge Figure 8 15 The flash memory point and the principles for charge discharge FlashMemory SCH The Flash memory point usually has a T shape due to an increased size of the source for optimum tunneling effect The horizontal polysilicon2 is the bit line the vertical metal2 is the word line which links all drain regions together The horizontal metal line links all sources together 7 16 2 lambda eee Flash memory point 2 folded flash memory points Figure 8 16 The flash memory point and the associated cross section Flash8x8 MSK 78 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 7 Memory circuits Memory Interface All inputs and outputs of the RAM are synchronized to the rise edge of the clock and more than one word can be read or written in sequence The typical chronograms of a synchronous RAM are shown in figure 7 17 The active edge of the clock is usually the rise edge One read cycle includ
90. implementation the pulse is positive 1 Select the Pulse icon Click on the node Reset 2 Click the brush to clear the existing pulse properties of the pulse Enter the desired start time 0 48 ns in this example and pulse duration and click Insert see figure 6 3 64 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 6 Latches Add a Pulse Label name Reset DC Supply Clock Pulse sinus variable Ground Pvt Math Parameters Level 1 0 fi O00 Level 0 05 fo 000 level Do Time start tts Rise time tr Time pulse tp Falltirme it 0 480 ns 0 020 ns 0 480 ns 0 020 ns TL Larger EL Shorter b Last Pulse 1 00 Reset ae EEn NCEE Fe EX Figure 7 4 Layout of the RS latch made RSNor MSK 4 Repeat the same procedure to change the clock into a pulse for node Set The start time is now fixed to 1 48 ns to generate a pulse later than for the Reset signal 5 Click on Simulate gt Start Simulation The timing diagrams of figure 6 4 appear In the simulation of figure 6 4 a positive pulse on Set turns O to a stable high state Notice that when Set goes to 0 O remains at 1 which is called the memory state When a positive pulse occurs on Reset O goes low nO goes high In this type of simulation the combination Reset Set l is not present 65 21 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL 6 Latches Edge Trigged Latch This edge
91. into N diffusion by a click on the palette of the Diffusion N button Make sure that the red layer is now the N Diffusion Draw a n diffusion box at the bottom of the drawing as in Figure 2 3 N diffusion boxes are represented in green The intersection between diffusion and polysilicon creates the channel of the nMOS device 16 21 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL 2 The MOS device Figure 2 3 Creating the N channel MOS transistor Vertical aspect of the MOS i ga Click on this icon to access process simulation Command Simulate Process section in 2D The cross section is given by a click of the mouse at the first point and the release of the mouse at the second point In the example of Figure 2 4 three nodes appear in the cross section of the n channel MOS device the gate red the left diffusion called source green and the right diffusion called drain green over a substrate gray A thin oxide called the gate oxide isolates the gate Various steps of oxidation have lead to stacked oxides on the top of the gate Inter layer oxide low permittivity Compressive strain around the NMOS gate field oxide MOS gate S102 TIN NMOS drain N doped NMOS source N doped Shallow trench isolation STI built in SiO2 Silicon substrate lightly doped P Figure 2 4 The cross section of the nMOS devices 17 21 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL 2 The
92. ion Circuits The row selection circuit decodes the row address and activates one single row This row is shared by all word line signals of the row The row selection circuit is based on a multiplexor circuit One line is asserted while all the other lines are at zero In the row selection circuit for the 16x4 array we simply need to decode a two bit address Using AND gates is one simple solution In the case of a very large number of address lines the decoder is split into sub decoders which handle a reduced number of address lines The column decoder selects a particular column in the memory array to read the contents of the selected memory cell Figure 7 8 or to modify its contents The column selector is based on the same principles as those of the row decoder The major modification is that the data flows both ways that is either from the memory cell to the DataOut signal Read cycle or from the Dataln signal to the cell Write cycle 72 21 09 2009 7 Memory circuits MICROWIND amp DSCH V3 5 LITE USER S MANUAL 2N rows Row Selected row Word Line address lt gt SK ET US gt STS TN IV IY ES Y NA a O 2 2 gt 4 SU 2 the Mem size eee ASAS ASAS DEERD EYP PAE Van an an an AN AN an ana an an an eK SK NY Mem Free width width Figure 8 7 The row selection circuit Selected memory cell 2M columns RARO AY wai
93. ith the voltage parameters as Vgs varies from 0 3 V to 1 1 V Ids fluctuates between 10 mA and 30 mA The MOS device is always conducting which corresponds to class A amplifiers Oscillator The role of oscillators is to create a periodic logic or analog signal with a stable and predictable frequency Oscillators are required to generate the carrying signals for radio frequency transmission but also for the main clocks of processors The ring oscillator is a very simple oscillator circuit based on the switching delay existing between the input and output of an inverter If we connect an odd chain of inverters we obtain a natural oscillation with a period which corresponds roughly to the number of elementary delays per gate The fastest oscillation is obtained with 3 inverters One single inverter connected to itself does not oscillate The usual implementation consists in a series of five up to one hundred chained inverters Figure 9 9 97 21 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL 9 Radio frequency Circuits out out out3 Ring oscillator with 3 inverters 5 stage ring oscillator with enable Figure 10 9 A ring oscillator is based on an odd number of inverters Inv3 SCH The main problem of this type of oscillators is the very strong dependence of the output frequency on virtually all process parameters and operating conditions This means that any supply fluctuation has a significant impact on the oscillator freq
94. les for metal8 are 25 0 5um width 25 A 0 5um spacing Added Features in the full version High Speed Mos High Voltage MOS Temperature Effects Process Variations 30 The state of the art MOS model for accurate simulation of nano scale technologies including a tutorial on key parameters of the model New kinds of MOS device has been introduced in deep submicron technologies starting the 0 18um CMOS process generation The MOS called high speed MOS HS is available as well as the normal one recalled Low leakage MOS LL For I Os operating at high voltage specific MOS devices called High voltage MOS are used The high voltage MOS is built using a thick oxide two to three times thicker than the low voltage MOS to handle high voltages as required by the I O interfaces Three main parameters are concerned by the sensitivity to temperature the threshold voltage VTO the mobility UO and the slope in sub threshold mode The modeling of the temperature effect is described and illustrated Due to unavoidable process variations during the hundreds of chemical steps for the fabrication of the integrated circuit the MOS characteristics are never exactly identical from one device to another and from one die to an other Monte carlo simulation min max typ simulations are provided in the full version 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 3 The Inverter 3 The Inverter This chapter describes th
95. lock on input Clock 2 Add a button on input RST Double click on the symbol and click Assembly so that the editable text of the code is converted into assembly code 4 Run the logic simulator Click the RST button RST 1 button red so that Reset is INACTIVE In the chronograms of Fig 6 4 the accumulator variations versus the time are displayed It can be noticed that this core operates with one single clock cycle per instruction except for some instructions such as MOV Move data and AJMP Jump to a specific address Code Assembly Symbols gt MOV A 0 MOV P3 A AJMP L1 ORL A 0F Or with 0x0F Click Assembly to compute Assembly O Help ciki 1 Rezet Actiwelow IE A 8051 x Figure 6 4 The simulation of the arithmetic and logic operation using the 8051 micro controller 8051 SCH Traffic light Example An example of code and schematic diagram for traffic light control is proposed below Notice the subroutine call through the instruction AJUMP 60 21 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL 10 PS 0 Pit oe a 12 P32 15 ESO 14 P3 4 ais sai P3 5 a16 P3 6 ali P3 7 PO 0 P2 0 02 05 P2 3 a0 4 PEA v2 Os P2 o9 L a0 6 P2 E vy aP P2 7 l Clock rst ot O RST 6 Microcontroller Model Figure 6 5 A simple code for 8051 micro controller for traffic light control 8051_traffic_lights sch Ports are activated using control commands such as MOV P3
96. ltage on the bottom the switching frequency of the selected node on the top Voltage versus voltage Only a DC simulation ideal for inverter OpAmp static characteristics co Voltage and Currents versus time All voltage on the bottom all currents on the top el Voltage versus time Each visible node is displayed 4 0 Qe x E atl EG ee Tes gt Options Node Properties u Analog simulation of D Documents and Settings sicard Mes documents software Microwind microwindso microwindss Ite amples 0 0 Node selected for min max freq and FFT calculation 15 References Contact diffn metal Contact diffp metal Y Pae via metal Add virtual R or L on the layout for simulation as ap of Add virtual capacitor Mejaf8 y as Makes a node visible at etal 3 simulation Metal 6 Metal 5 Sinus property Metal 4 Metal 3 Metal 2 Metal 1 TiN gate ll Protect unprotect the ia layer from editing TiN gate PM P Diffusion MN Text layer Access to the node properties Define an area in the bird s view to control the zoom Evaluation of the capacitor resistor length and inductor Details on the node properties Width 5 5um 273 lambda Height 5 2um 258 lambda Surf 28 2um2 0 0 mm2 Details on the node capacitance f Hide Unselect Display V Delay Select the node from
97. lting value in the accumulator leaving the resulting value in accumulator leaving the resulting value in accumulator a eee Shifts the bits of the accumulator to the right The bit O is loaded into bit 7 Shifts the bits of the accumulator to the left The bit 7 is loaded into bit 0 Table 1 Some important instructions implemented in the ALU of the 8051 micro controller 97 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 6 Microcontroller Model Immediate value Registers RO R7 Accumulator A J Pd 8 bits Memory contents OpCode input Arithmetic and Logic Unit 8 bits Result S CarryOut Figure 6 1 The arithmetic and logic unit of the 8051 For example ADD A RO Opcode 0x28 overwrites the accumulator with the result of the addition of A and the content of RO SUBB A 2 Opcode 0x94 0x02 overwrites the accumulator with the result of the subtraction of A and the sum of the Carry and the byte 0x02 INC A 0x04 increments the content of the accumulator DEC A 0x14 Decrements the content of the accumulator ANL A 10 Ox54 overwrites the accumulator with by the AND gating of A and the constant Ox 10 ORL A R7 Ox4F overwrites the accumulator with by the OR gating of A and the content of R7 XRL A R1 0x69 overwrites the accumulator with the result of the XOR gating of A and the content of the internal register R1 Inside the 8051 A simplified model of the 8 bit micro con
98. ma a EZ En mere ted ted Le FAF CT CON A OT a TCT ZEE Reset master OE OTOL OE OOOO EEE EEE O ENNE ENNE ON ON 5 ET E PO ed IEEE EL A EGC AP GRRE cP RP PRC CCA GPRS A EA VE Figure 7 6 Compiled version of the Edge trigged D Flip Flop DregCompile MSK 67 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 6 Latches Add a Piece wise linear x Label name Reset Parameters Level O fut ja 400 0 000 Level 1 yi ooo 000 insert sequence in table Sed o1 O x stste random O l ss f Vod 2 A Vda Insert E8 Figure 7 7 Piece wise linear property used for sophisticated control of input signals DregCompile MSK Esen EE E T clock daa A EN EN RNN Ean i A A a 0 0 Data transferred to Q at i y ls the fall edge of Clock Data i r r Asynchronous reset of the D Flip Flop a eee 70 30 30 Timer Figure 7 8 Simulation of the DREG cell DregCompile MSK Added Features in the Full version Latches The truth table and schematic diagram of the static D latch also called Static D Flip Flop are described The main characteristics of the latch switching are presented Counters The one bit counter 1s able to produce a signal featuring half the frequency of a clock The implementation is detailed Up and down counters are also described Registers Shift registers serial registers are described 68 21 09 2009 MICROWIND D
99. math Add a Piece wise linear Parameters Level 04 0 000 Level 1 AA 1 000 Insert sequence in table Seq o1 0 x state randam O Vse 1 1 dd 2 H lod Insert ER 2 clear gt lt invert x Cancel TL Visible in simu Figure 8 5 The bit Line pulse used the x floating state to enable the reading of the memory cell RamStatic6T MSK 71 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 7 Memory circuits Bit Line 0 Bit Line 1 Bit Line floating Bit Line 0 Write cycle Write cycle Read cycle Write cycle Cell activated Write Write 1 Keeps 0 3 Keeps 1 et end ede Ade WE ae ted SNe ERA A AE Ct eet Rls 8 S Min cto AS My Se de 1 1 r 5 1 4 1 0 0 0 0 0 5 1 0 1 5 2 0 25 3 0 3 5 40 4 5 Timetns Figure 8 6 Write cycle for the static RAM cell RamStatic6T MSK The simulation of the RAM cell is proposed in figure 7 6 At time 0 0 Data reaches an unpredictable value of 1 after an unstable period Meanwhile Data reaches O At time 0 5 ns the memory cell is selected by a l on Word Line As the Bit Line information is O the memory cell information Data goes down to 0 At time 1 5 ns the memory cell is selected again As the Bit Line information is now 1 the memory cell information Data goes to 1 During the read cycle in which Bit Line and Bit Line signals are floating the memory sets these wires respectively to and 0 corresponding to the stored values Select
100. ndow appears By default the proposed length is the minimum length available in the technology 2 lambda and the width is 10 lambda In 45 nm technology where lambda is 20 nm 0 02 um the corresponding size is 0 02 um for the length and 0 04 um for the width Simply click Generate Device and click on the middle of the screen to fix the MOS device 32 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 3 The Inverter EN Layout Generator o x generator 5 Pads Inductor Contacts MOS l Path Logo Bus Fes Diode Capa hos Parameters x width mos 0 200 e HEF Length mos 0 040 In En Serge Mbroffingers 1 Y AE T o tially nMOS pMOS Double gate Options Units Ei sE dL a low leakage fe in micron um C high speed C in lambda Imax0 156MA C high voltage zie Generate Device Figure 3 5 Generating a nMOS device Add polarization Click again the icon MOS generator on the palette Change the type of device by a tick on p channel and click Generate Device Click on the top of the nMOS to fix the pMOS device The MOS generator is the safest way to create a MOS device compliant to design rules The programmable parameters are the MOS width length the number of gates in parallel and the type of device n channel or p channel By default metal interconnects and contacts are added to the drain and source of the MOS You may add a supplementary metal 2 interconnect on the top of met
101. o the quality factor Q Fig 9 5 Power Amplifier The power amplifier is part of the radio frequency transmitter and is used to amplify the signal being transmitted to an antenna so that it can be received at the desired distance Most CMOS power amplifiers are based on a single MOS device loaded with a Radio Frequency Choke inductor Lrrc as shown in figure 9 6 The inductor serves as a load for the MOS device At a given frequency f the inductor is equivalent to a resistance L 27 f with two significant advantages as compared to the resistor the inductor do not consume DC power and the combination of the inductor and the load capacitor CL creates a resonance The power is delivered to the load RL which 1s often fixed to 50 Q This load is for example the antenna monopole which can be assimilated to a radiation resistance as described in the previous section The resonance effect is obtained between Lrrc and C 95 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 9 Radio frequency Circuits Oscillation of Vout On chip inductor Radio frequency choke ss Input signal VrfIn MAA VRFIn Sater 7 co Y N N S N Pi On chip capacitor fA Model of the antenna Figure 10 6 The basic diagram of a power amplifier PowerAmp SCH An example of powerful MOS device is shown in figure 9 7 The maximum current is close to 10 mA in 45 nm technology A convenient way to generate the polari
102. oad pMOS HRH Figure 9 15 Single stage amplifier layout with a pMOS as a load resistor AmpliSingle MSK In figure 8 15 a nMOS device with large width and minimum length is connected to a high resistance pMOS load A 50 mV sinusoidal input vin is superimposed to the static offset 0 5 V Vm What we expect is a 500 mV sinusoidal wave vout with a certain DC offset Vour What we need now is to find the characteristics Vout Vin in order to tune the offset voltage Vy In the simulation window click Voltage vs voltage and More to compute the static response of the amplifier Figure 8 16 The range of voltage input that exhibits a correct gain appears clearly For Vm higher than 0 1 V and lower than 0 25 V the output gain is around 6 Therefore an optimum offset value could be 0 15 V Change the parameter Offset of the input sinusoidal wave to place the input voltage in the correct polarization and verify the amplification of the output signal according to DC predictions By increasing the Vin frequency you may observe the cut off frequency of the amplifier Fig 8 17 VOUT vout 1 00 0 90 0 80 Linear amplification Gain maximum eee around 6 0 0 60 0 50 90 3 VA 0 40 0 30 0 20 eects Valid input voltage range 0 10 l 8 8 nt 0 20 0 40 0 60 0 80 Figure 9 16 Single stage amplifier static response showing the valid input voltage range AmpliSingle MSK 88 21
103. oduced by TSMC in 2004 Tsmc2004 and Fujitsu in 2005 Fujitsu2005 In 2007 Intel announced its 45 nm CMOS industrial process and revealed some key features about metal gates The Common Platform Common2007 including IBM Chartered Semiconductor The transistor channels range from 25 nm to 40 nm in size 25 to 40 billionths of a meter Some of the key features of the 45 nm technologies from various providers are given in Table 2 SiON HfO2 ZrO Ta Os TiO Equivalent oxide thickness 11 15 nm of metal layers permittivity K Table 2 Key features of the 45 nm technology Compared to 65 nm technology most 45 nm technologies offer 30 increase in switching performance 30 less power consumption 2 times higher density X 2 reduction of the leakage between source and drain and through the gate oxide 45 nm process variants There may exist several variants of the 45 nm process technology One corresponds to the highest possible speed at the price of a very high leakage current This technology is called High speed as it is dedicated to applications for which the highest speed is the primary objective fast microprocessors fast DSP etc 13 21 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL 1 TECHNOLOGY SCALE DOWN This technology has not been addressed in Microwind s 45nm rule file The second technological option called General Purpose Fig 1 8 is targeted to standard products wh
104. or is one of the most useful basic blocs in analog design It is primarily used to copy currents The principles and behavior of current mirrors are given in the full version The cascode current mirror is also presented which has several advantages over the simple current mirror 92 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 9 Radio frequency Circuits 10 Radio Frequency Circuits On Chip Inductors Inductors are commonly used for filtering amplifying or for creating resonant circuits used in radio frequency applications The inductance symbol in DSCH and MICROWIND is as follows Figure 9 1 SVVN L1 10nH Inductor Figure 10 1 The inductance symbol The quality factor Q is a very important metric to quantify the resonance effect A high quality factor Q means low parasitic effects compared to the desired inductance effect The formulation of the quality factor is not as easy as it could appear An extensive discussion about the formulation of Q depending on the coil model is given in Lee We consider the coil as a serial inductor Ll a parasitic serial resistor R and two parasitic capacitors C and C2 to the ground as shown in figure 9 2 Consequently the Q factor is approximately given by equation 9 1 LI C1 C2 A A Equ 9 1 Q T Equ 9 1 The inductor can be generated automatically by MICROWIND using the command Edit Generate Inductor The inductance value appears at the bottom of t
105. other pattern movwf PortB Moves the pattern to port B goto loop and again symbol n 1 16f84 properties 2084 po Code Assembly Symbols PIC16 84 by Etienne Sicard for Dsch iin Simple program to put 10101010 on port B RAS 01010101 on port B 16f84 RA4 PortB equ 0x06 declares the address of output port B a org 0 eii a MCLR loop movlw 0x55 load Y with a pattern hexa format novut PortB Moves the pattern to port B VSS movlw Oxaa load W with an other pattern novwt PortB Moves the pattern to port B T goto loop and again RBO Figure 6 7 Activating output ports of the PIC 16f84 16f84 SCH 62 21 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL 6 Latches 7 Latches This chapter details the structure and behavior of latch circuits The RS Latch the D Latch the edge sensitive register and the counter are presented Basic Latch The basis for storing an elementary binary value is called a latch The simplest CMOS circuit is made from 2 inverters Q 1 2 stable Q 0 memory l states Figure 7 1 Elementary memory cell based on an inverter loop RS Latch The RS Latch also called Set Reset Flip Flop SR FF transforms a pulse into a continuous state The RS latch can be made up of two interconnected NOR or NAND gates inspired from the two chained inverters of figure 6 2 In the case of RS NOR the Reset and Set inputs are active high The memory state cor
106. ox should completely surround the MOS device layout Double click the option layer The Navigator menu is set to the Options menu Fig 2 16 The default MOS type corresponds to the option low leakage Fig 2 16 Change the option to High Speed and lauch the simulation again The Transmission Gate Both NMOS devices and PMOS devices exhibit poor performances when transmitting one particular logic information The nMOS degrades the logic level 1 the pMOS degrades the logic level 0 Thus a perfect pass gate can be constructed from the combination of nMOS and pMOS devices working in a complementary way leading to improved switching performances Such a circuit presented in figure 2 17 is called the transmission gate In DSCH the symbol may be found in the Advance menu in the palette The transmission gate includes one inverter one nMOS and one pMOS Enable Transmission gate Da VV a Good 0 1 AAA Good 1 Figure 2 17 Schematic diagram of the transmission gate Tgate SCH 2 21 09 2009 MICROWIND DSCH v3 5 LITE USER S MANUAL 2 The MOS device Figure 2 18 Layout of the transmission gate TGATE MSK The layout of the transmission gate is reported in figure 2 18 The n channel MOS 1s situated on the bottom the p channel MOS on the top Notice that the gate controls are not connected as Enable is the opposite of Enable Metal Layers As seen in the palette Fig 2 19 the available metal lay
107. oxide thickness TOXE is defined by Equ 1 For the 45 nm technology the high K 21 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 2 The MOS device permittivity declared in the rule file is 10 Parameter GateK close to HfO gate dielectric permittivity The physical oxide thickness is 3 5 nm and by applying equ 1 TOXE is 1 4nm These parameters are in close agreement with those in Song s review on 45 nm gate stacks Song2006 TOXE En ue Equ 1 high k Where Esio2 dielectric permittivity of S102 3 9 no unit Enich k High K dielectric permittivity thigh k High K oxide thickness m The MOS Level 3 For the evaluation of the current ds as a function of Vd Vg and Vs between drain and source we commonly use the following equations close from the SPICE LEVEL 3 formulations Lee The formulations are derived from the LEVEL1 and take into account a set of physical limitations in a semi empirical way Ids Model would do this y o mee Saturation in SI een model 3 Cutt off Vgs lt Vt Vdsar Vds Figure 2 9 Introduction of the saturation voltage VdSat which truncates the equations issued from model 1 One of the most important change is the introduction of Vdsar a saturation voltage from which the current saturates and do not rise as the LEVEL1 model would do figure 2 9 This saturation effect 1s significant for small channel length The BSIM4 MOS Model An
108. palette menu Simply click the desired property and click on the desired location in the layout Add a clock on the inverter input node The default node name clock has been changed into Vin and a visible property on the output node Vout VDD property Visible node property A clock property should be added to this node Bn pemos in i out nmos VDD High VDD VSS property el 8 vss Clock Pulse Figure 3 14 Adding simulation properties InvSteps MSK 37 21 09 2009 MICROWIND DSCH v3 5 LITE USER S MANUAL 3 The Inverter MW Analog simulation of DADocuments and Settings sicard Mes documents software Microwine micrawindgavn crowindas liteke 1 00 y V Delay v Bus value between Evaluate IT Minimax Av IF Frequency finv y lili FFT Time Scale X Close 8 Print P 0 816 uw 0 0 02 04 06 OB 10 12 14 16 Time ns Voltage vs time A Voltages and currents Voltage vs voltage Frequency vs time Eye diagram Figure 3 15 Transient simulation of the CMOS inverter InvSteps MSK The command Simulate Run Simulation gives access to the analog simulation Select the simulation mode Voltage vs Time The analog simulation of the circuit is performed The time domain waveform proposed by default details the evolution of the voltages in and out versus time This mode is also called transient simulation as shown in figure
109. positive voltage equal to the threshold voltage of the MOS device 0 35 V The summary of the p channel MOS performances is reported in figure 2 12 0 0 Poor 0 Good 1 A 0 Vt i N a 0 1 PMOS ca Y 0 Figure 2 12 Summary of the performances of a pMOS device MOS device options The default MOS device in Microwind 3 5 is the low leakage MOS There exist a possibility to use a second type of MOS device called High speed The device I V characteristics of the low leakage and high speed MOS devices listed in Table 3 are obtained using the MOS model BSIM4 See Sicard2005a for more information about this model The cross section of the low leakage and high speed MOS devices do not reveal any major difference Fig 2 13 except a reduction of the effective channel length Concerning the low leakage MOS the I V characteristics reported in Fig 2 14 demonstrate a drive current 24 21 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL 2 The MOS device capability of around 0 9 mA um for W 1 0um at a voltage supply of 1 0 V For the high speed MOS the effective channel length is slightly reduced as well as the threshold voltage to achieve an increased drive current of around 1 2 mA um Low leakage High speed Contact to IMOB ERS metall TETE ee Metall layer High stress film to induce channel strain nMOS gate Shallow trench isolation STI a Y 555 High k oxide A ae ae and Ti
110. presented with its corresponding layout created manually and automatically Then the comparator multiplier and the arithmetic and logic unit are also discussed This chapter also includes details on a student project concerning the design of binary to decimal addition and display Unsigned Integer format The two classes of data formats are the integer and real numbers The integer type is separated into two formats unsigned format and signed format The real numbers are also sub divided into fixed point and floating point descriptions Each data is coded in 8 16 or 32 bits We consider here unsigned integers as described in figure 5 1 Y 2 1024 2 32768 2 1048576 230 1073741824 2 2147483648 Unsigned integer 32 bit Figure 5 1 Unsigned integer format Half Adder Gate The Half Adder gate truth table and schematic diagram are shown in Figure 5 2 The SUM function is made with an XOR gate the Carry function is a simple AND gate HALF ADDER A B SUM CARRY 00 0 0 01 1 0 10 1 0 11 0 l Figure 5 2 Truth table and schematic diagram of the half adder gate HADD MSK 47 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 5 Arithmetics FULL You may create the layout of the half adder fully by hand in order to CUSTOM create a compact design Use the polysilicon and metall layers for short LAYOUT connections only because of the high resistance of these materials Use Poly Metal Diff
111. re 8 2 the salicide material deposited on the upper interface between the polysilicon layer and the oxide creates a metal path for current that reduces the resistance dramatically Notice the shallow trench isolation and surrounding oxide that isolate the resistor from the substrate and other conductors enabling very high voltage biasing up to 100V However the oxide is a poor thermal conductor which limits the power dissipation of the polysilicon resistor The salicide is part of the default process and is present at the surface of all polysilicon areas However it can be removed thank to an option layer programmed by a double click in the option layer box and a tick at 80 21 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL 8 Analog Cells Remove Salicide In the example shown in figure 8 3 the default resistance is 76 Q and the unsalicide resistance rises to 760 Q Resistor contacts mir Default salicide deposit Low R No salicide deposit High R Trench isolation Substrate Figure 9 2 Removing the salicide material to increase the sheet resistance ResPoly MSK Default poly low resistance per square due to salicide o gt Navigator Device Options INIA Mos options e low leakage high speed Option layer A pat used to remove FM high voltage Unsalicide poly high resistance per square gt the salicidation to increase yesistance Fig
112. ree logic levels 0 1 and X are defined as follows Logical value Voltage Symbol in DSCH Symbol in MICROWIND 0 0V VSS E Green in logic simulation Green in analog simulation l 1 0V in cmos VDD A Red in logic simulation Red in analog simulation Undefined Gray in simulation Gray in simulation The MOS as a switch The MOS transistor is basically a switch When used in logic cell design it can be on or off When on a current can flow between drain and source When off no current flow between drain and source The MOS is turned on or off depending on the gate voltage In CMOS technology both n channel or nMOS and p channel MOS or pMOS devices exist The nMOS and pMOS symbols are reported below The symbols for the ground voltage source 0 or VSS and the supply 1 or VDD are also reported in figure 2 1 The n channel MOS device requires a logic value 1 or a supply VDD to be on In contrary the p channel MOS device requires a logic value 0 to be on When the MSO device is on the link between the source and drain is equivalent to a resistance The order of range of this on resistance is 100 2 5 KO The off resistance is considered infinite at first order as its value is several Mega Q Figure 2 1 the MOS symbol and switch 15 21 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL 2 The MOS device MOS layout Li We use MICROWIND to draw the MOS layout and simulate its behavior Go to the
113. responds to Reset Set 0 The combination Reset Set 1 should not be used as it means that O should be Reset and Set at the same time 63 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 6 Latches RS Latch NOR R S Q nQ 0 0 Q nQ 0 1 1 0 1 0 0 1 1 l 1 l Figure 7 2 The truth table and schematic diagram of a RS latch made RSNor SCH FULL CUSTOM LAYOUT You may create the layout of RS latch manually The two NOR gates may share the VDD and VSS supply achieving continuous diffusions LAYOUT COMPILING Use DSCH to create the schematic diagram of the RS latch Verify the circuit with buttons and lamps Save the design under the name RS sch using the command File Save As Generate the Verilog text file v appendix by using the command File Make Verilog File In MICROWIND click on the command Compile gt Compile Verilog File Select the text file RS v Click on Compile When the compiling is complete the resulting layout appears as shown below The NOR implementation of the RS gate is completed module RSNor Reset Set 0 n0 input Reset Set output Q nQ nor norl 0 n0 Reset NOT HOEZO roet endmodule With the Reset and Set signals behaving like clocks the memory effect is not easy to illustrate A much better approach consists in declaring pulse signals with an active pulse on Reset followed by an active pulse on Set Consequently you must change the clock property into a pulse property For NOR
114. s convey the VSS and VDD voltage supply close to the bulk regions of the device Remember that the n well region should always be polarized to a high voltage to avoid short circuit between VDD and VSS Adding the VDD polarization in the n well region is a very strict rule Via to connect metal2 and metal 1 N Nwell contact and bridge to VDD P Pwell contact and bridge to VSS Figure 3 12 Adding polarization contacts Process steps to build the Inverter At that point it might be interesting to illustrate the steps of fabrication as they would sequence in a foundry MICROWIND includes a 3D process viewer for that purpose Click Simulate Process steps in 3D The simulation of the CMOS fabrication process is performed step by step by a click on Next Step 36 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 3 The Inverter P Substrate Figure 3 13 The step by step fabrication of the Inverter circuit InvSteps MSK On figure 3 13 the picture on the left represents the nMOS device pMOS device common polysilicon gate and contacts The picture on the right represents the same portion of layout with the metal layers stacked on top of the active devices Inverter Simulation The inverter simulation is conducted as follows Firstly a VDD supply source 1 0 V is fixed to the upper metal 2 supply line and a VSS supply source 0 0 V is fixed to the lower metal2 supply line The properties are located in the
115. simulation mode is Voltage and Currents The internal voltage remains within the voltage range 0 VDDH while the voltage near the pad is 10 to 10 V wide Notice that the current flowing in the diodes is around ImA Figure 10 5 High voltage MOS The general diagram of an input structure is given in figure 10 6 A high voltage buffer is used to handle voltage overstress issued from electrostatic discharges The logic signal is then converted into a low voltage signal to be used in the core logic For interfacing with input output specific high voltage MOS are introduced These MOS devices are called high voltage MOS They use a double gate oxide to handle the high voltage of the I Os The high voltage device symbols are drawn with a double line The symbol Vdd_HV represents the I O voltage which is usually 2 5 V in CMOS 65 nm 109 21 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL 10 I O Interfacing VES iik pad1 Rpoly N P High voltage inv vdd_HV to core Low voltage inv Figure 11 6 The basic principles for an input circuit including the ESD protection and the voltage translator IOPadIn SCH Gate contact Option layer to turn this device ats Sees Cee into a high er voltage MOS ki kn MER ki Local polarization to ground and ground contact _ et et et a Sree Ee Bie bey ee ae ee _ et et 4 4 E noin Large poly gate over 5nm oxide nMOS high voltage for input pad Fi
116. t 1 24 13 106 J03 S008 Table 1 Technological evolution and forecast up to 2011 9 21 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL 1 TECHNOLOGY SCALE DOWN Gate Dielectric High voltage Thickness nm MOS double feeen gate oxide addressed in 10nm BE ge et tae args ey ey oa Microwind 3 5 Asa A 0 18 um Tape mere ne RAS Low voltage MOS minimu gate oxide O lnm 4 SION 4 2 6 5 S102 3 9 A ear 1995 2000 2005 2010 2015 Figure 1 2 The technology scale down towards nano scale devices At each lithography scaling the linear dimensions are approximately reduced by a factor of 0 7 and the areas are reduced by factor of 2 Smaller cell sizes lead to higher integration density which has risen to nearly 1 5 million gates per mm in 45 nm technology table 1 Gate Material and Oxide For 40 years the S102 gate oxide combined with polysilicon have been serving as the key enabling materials for scaling MOS devices down to the 90nm technology node Fig 1 One of the struggles the IC manufacturers went through was being able to scale the gate dielectric thickness to match continuous requirements for improved switching performance The thinner the gate oxide the higher the transistor current and consequently the switching speed However thinner gate oxide also means more leakage current Starting with the 90nm technology S102 has been replaced by SiON dielectric wh
117. tal2 4 r710 Minimum surface 16 X 116 11 Design Rules r404 r401 contact polysilicium r405 i B os diffusio metal gate r501 metal r502 metal r604 A r602 via Stacked via ove gt lt contact rou when r603 is 0 r603 contact L metal2 metal2 21 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL Via 2 r801 r802 r804 r805 Metal 3 r901 r902 r910 Via 3 ra01 ra02 ra04 ra05 Metal 4 rb01 rb02 rb10 Via 4 rc0l rc02 rc04 rc05 117 Via2 width 2A Between two Via2 5 Extra metal2 over via2 2 Extra metal3 over via2 2 A Metal3 width 4 A Between two metal3 4 Minimum surface 32 A Via3 width 2A Between two Via3 5 Extra metal3 over via3 2 A Extra metal4 over via3 2 A Metal4 width 4 A Between two metal4 4A Minimum surface 32 A Via4 width 2A Between two Via4 5 Extra metal4 over via2 3 A Extra metal5 over via2 3 A r c01 rc02 mm gt lt 11 Design Rules r804 via E rc04 A Via 21 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL Metal 5 rd01 rd02 rd10 Via 5 re0l re02 re04 re05 Metal 6 rf01 rf02 rf10 Via 6 rg01 rg02 rg04 rg05 Metal 7 rh01 rh02 rh10 118 Metal5 width 8 A Between two metal5 8 A Minimum surface 100 A Via5 width 4A Between two Via5 6 Extra metal5 over via5 3 Extra metal6 over via
118. ter metal capacitors 83 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 8 Analog Cells Diode connected MOS The schematic diagram of the diode connected MOS is proposed in figure 8 8 This circuit features a high resistance within a small silicon area The key idea is to build a permanent connection between the drain and the gate Most of the time the source is connected to ground in the case of n channel MOS and to VDD in the case of p channel MOS T LA g dsl a High R Figure 9 8 Schematic diagram of the MOS connected as a diode MosRes SCH To create the diode connected MOS the easiest way is to use the MOS generator Enter a large length and a small width for example W 0 14um and L 1 4um This sizing corresponds to a long channel featuring a very high equivalent resistance Add a poly metal contact and connect the gate to one diffusion Add a clock on that node Add a VSS property to the other diffusion The layout result is shown in figure 8 9 Now click Simulation on Layout In a small window the MOS characteristics are drawn with the functional point drawn as a color dot Figure 8 10 It can be seen that the I V characteristics correspond to a diode The resistance is the invert value of the slope in the Id Vd characteristics For Vds larger than 0 6V the resistance is almost constant As the current ds increases of 10uA in 0 4V the resistance can be estimated around 40KQ A more precise evaluation is performed
119. the Ee E top of poly A a end be a ate Clit at iv Te Figure 8 14 The double gate MOS generated by Microwind Eeprom MSK When charges are trapped in the floating polysilicon layer Figure 7 14 left the threshold voltage is high almost no current flows through the device independently of the gate value As a matter of fact the electrons trapped in the floating gate prevent the creation of the channel by repealing channel electrons Data retention is a key feature of EEPROM as it must be guaranteed for a wide range of temperatures and operating conditions Optimum electrical properties of the ultra thin gate oxide and inter gate oxide are critical for data retention The typical data retention of an EEPROM is 10 years The double gate MOS layout is shown in figure 7 14 The structure is very similar to the n channel MOS device except for the supplementary poly2 layer on top of the polysilicon The lower polysilicon is unconnected resulting in a floating node Only the poly2 upper gate is connected to a metal layer through a poly2 metal contact situated at the top The cross section of figure 7 14 right reveals the stacked poly poly2 structure with a thin oxide in between Flash Memories Flash memories are a variation of EEPROM memories Flash arrays can be programmed electrically bit by bit but can only be erased by blocks Flash memories are based on a single double poly MOS device without any selection transistor Figure 7 15 The
120. tion The resistance symbol R poly is inserted in the layout to indicate to the simulator that an equivalent resistance must be taken into account for the analog simulation This approach is no more valid for 45 nm for which polysilicon has been replaced by low resistance metal layer Open loop amplifiers are used as voltage comparators The comparators address the decoding logic situated to the right and that provides correct Ag and A coding In the simulation shown in figure 9 19 the comparators Co and C work well but the comparator C is used in the lower limit of the voltage input range The generation of combinations 01 10 and 11 is produced rapidly but the generation of 00 is slow The comparator Co may be modified to provide a faster response in comparison with low voltage by changing the biasing conditions An alternative is to reduce the input voltage range which means that the resistance scale would be supplied by Vdac larger than VSS and Vdac smaller than VDD Added Features in the Full version Voltage Controlled The voltage controlled oscillator VCO generates a clock with a controllable oscillator frequency The VCO is commonly used for clock generation in phase lock loop circuits as described later in this chapter The clock may vary typically by 50 of its central frequency A current starved voltage controlled oscillator is detailed 103 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 9 Radio
121. tput analog characteristics MICROWIND uses IBIS to pilot the generation of pads 112 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 11 Design Rules 12 Design Rules Select a Design Rule File The software can handle various technologies The process parameters are stored in files with the appendix RUL The default technology corresponds to a generic 8 metal 45 nm CMOS process The default file is CMOS45n RUL To select a new foundry click on File Select Foundry and choose the appropriate technology in the list To set a specific foundry as the default foundry click File gt Properties Set as Default Technology Click Help Design Rules to display the design rules figure 11 1 Li Design rules for CMOS 45nm HighkMetalStrain e Metal copper LET PIPART ret or Se 207 Minimum M and P diffusion width r207 3 lambda 0 06 um a 202 Between two P and M diffusions r202 3 lambda 0 06 um 203 Extra nwell after P diffusion r 03 3 lambda 0 06 um reO4 Between M diffusion and rive re04 3 lambda 0 06 urn re05 Border of well after M polarization r 205 0 lambda 0 00 urn r20b6 Between N and F polarization r206 4 lambda 0 08 um r207 Border of Mwell for P polarization r20 1 lambda 0 02 um P polarization re 10 Minimum difusion area r210 16 lambda 0 01 ume wl Y yf OK Techno CMOS 45nrn HighK Metal
122. troller 8051 exists through the symbol 8051 SYM accessible using the command Insert User Symbol The symbol is also directly accessible through the symbol palette starting version 3 5 58 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 6 Microcontroller Model lee X Basic Advanced Electrical pal Hd mn gt Sources 8 0 Display Os B amp Switches p Figure 6 2 Access to the 8051 symbol from the palette in the Advanced list The symbol consists mainly of general purpose input output ports PO P1 P2 and P3 a clock and a reset control signals The basic connection consists of a clock on the Clock input and a button on the Reset input Figure 5 Pio P11 Pr Pi Pia P15 PIS Pi POO PO poz Pos Pos P05 P06 P07 5051 Figure 6 3 The 8051 symbol and its embedded software 8051 SCH 59 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 6 Microcontroller Model After a double click in the symbol the embedded code appears That code may be edited and modified Figure 6 3 When the button Assembly is pressed the assembly text is translated into executable binary format Once the logic simulation is running the code is executed as soon as the reset input is deactivated The value of the program counter the accumulator A the current op_code and the registers is displayed Minimum features for running the 8051 The user should 1 Add a c
123. uency The LC oscillator proposed below is not based on the logic delay as with the ring oscillator but on the resonant effect of a passive inductor and capacitor circuit In the schematic diagram of figure 9 10 the inductor L resonates with the capacitor C7 connected to S1 combined with C2 connected to S2 The layout implementation is performed using a 3 nH virtual inductor and two 1 pF capacitor The large width of active devices to ensure a sufficient current to charge and discharge the huge capacitance of the output node at the desired frequency Zi ES o o C2 C1 1 pF 1 pF Capa Capa Figure 10 10 A differential oscillator using an inductor and companion capacitor OscillatorDiff SCH 98 21 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL 9 Radio frequency Circuits og Frequency GEz 2 353 369 371 3 72 373 3 74 2a Permanent DC current is regime established Oscillation or starts Gan Volt y i l z ien q HVA AAA 1 00 Ny if gt gt nnn b H 282ns 0 27 djs Hide He D BS 0 5 102ns 0 206 Figure 10 11 Simulation of the differential oscillator OscillatorDiff MSK Using virtual capacitors instead of on chip physical coils is recommended during the development phase It allows an easy tuning of the inductor and capacitor elements in order to achieve the correct behavior Once the circuit has been validated the L and C symbols can
124. uit B 2 B 1 B O Vout Analog output Vout V with Vdac 1 0V o 0 JO O B Vdac 0 O AB Vda OS o 1 jo 28WVde 05 ______ o H pr 3 8Vde 05 d 0 JO 48Vde O5 1 0 pr S 8Vdae 065 Ld OB dae Figure 10 14 The specifications of a 3 bit digital to analog converter 100 21 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL 9 Radio frequency Circuits eelde beh eee EEEN T ee ai lend 1843 EET al i RHET Se En E ee ei PER AHORA u En be dn er Fe a ETE de F LEF Ez R poly 397 HEH ennen Pee Alii i 3922 Bin Sa Ati e Figure 10 15 The sheet resistance is increased by removing the salicide deposit thanks to an option layer for technologies above 65 nm DAC MSK The simulation of the R ladder DAC Figure 9 16 shows a regular increase of the output voltage Vout with the input B 0 B 2 from 000 0 V to 111 nearly 1 0 V Each input change provokes a capacitance network charge and discharge The analog level Vout increases regularly with increasing digit input B The converter is monotonic B1 B2 4 00 0 000 Vout 0 0 05 10 15 20 25 3 0 35 40 4Time ns Figure 10 16 Simulation of the digital analog converter DAC MSK 101 21 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL 9 Radio frequency Circuits Vin lt Vref0 o jo jo jo Vrefo lt Vin lt Vrefl Ot p Q Vrefl lt Vin lt Vref2 Ot n jo Resistor scale
125. uit to interface with the outside world The default menu for an automatic generation of a pad ring is shown in figure 10 2 The proposed architecture is based on 5 pads on each side meaning a total of 20 pads 5 pads north Layout Generator Options Padting C Single pad with size um 28 0 5 pads west Core area Pad Ring Generator Pads in xX E Total 20 pads size 412x412um 5y TT l en Usually VSS Pads in Y E Ydd ss pairs 2 3 34 E Inner supply ring 2 5 Usually VDD Ring Width 1 5 um 1 8 E 1 24 FO list described in IBIS file i die 5 pads Wath Figure 11 2 The menu for generating the pad ring and the corresponding architecture The supply rails The supply voltage may be 5 V 3 3 V 2 5 V 1 8 V or 1 2 V as listed in the menu shown in figure 10 2 Most designs in 45 nm use 1 0 V for the internal core supply and 2 5V for the interfacing This is because the logic circuits of the core operate at low voltage to reduce power consumption and the I O structures operate at high voltage for external compatibility and higher immunity to e
126. ulation properties a Zoom Out Connect the lower to the upper layers at the desired location using appropriate contacts EN View all the drawing a Static MOS characteristics La Extract and view the electrical node ro View the palette pointed by the cursor Step by step fabrication of the layout in 3D 123 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 15 References DSCH MENUS File Menu Edit Menu 124 Reset the program and starts with a clean screen FIN Edit Insert View Simulate Help Read a schematic file he Save the current schematic UY Save ctrl s diagram into the current Saye As filename et Foundry Generates a VERILOG Ee Configure DSCH text file corresponding to Make Verilog File CUE to a given the schematic diagram Generate SPICE File Colo foundry o EP Szhema to new symbol Transform this diagram Properties into a user symbol Design properties Mongchrome Color FS number of symbols Switch to PAE nodes etc monochrom Color mode Lo4ve Dsch3 colo Print the schematic diagram Quit DSCH and returns to Windows Cancel last editing command Edit Insert wiew Simulate Help i Undo Ctrl 2 Move elements included in Cut elements included in an area _ AT Cut Ctrl an area Paste Ctrl V Duplicate elements included ql Copy Ctrl bl in an area of Move Ctrl M f otate Left Ctrl F Flip or rotate elements T included in an area Rotate Right Flip Horizontal Ctrl F olm Flip vertic
127. ull der Gatti iii 48 Bull Adder S ymbolm DSC a nerve tnt eisai E 49 COMPA aen renee ec PER eenden 50 Fault injector and Test Vector extracto A eee etndaandelke 51 Added Peartites ato Full VELSOM never A ezel evana aan seeden Eede entend aast 56 6 Microcontroller Model lt N dead A a 57 SUN NOA lndurten eme heee eene nen eeens eeeh eel 57 Model or the PIC IOS eaa E e A A ao 62 E Lale A eae ee eee 63 Baste Lat ns ii A za 63 BN 1 Nn 63 Edse mood lAs 66 Added Features in the EU A A AEN E 68 S Memory CIRCUS tota 69 Basic Memory OfsamzZalOi enteren a E r de 69 RAM MEMON AAA A cana dsera des cache uansah al cteainstes 69 SEICCHOM COUS eenen ou ae cai tee ae cata es ie bani Mert teed aan ns ee cin Gul Citas 72 PR Complete 64 Di SAME ii Sales ad eenander dada 74 Dynamics RAM Memorias 75 PERRO Min A nnee eenhoorn naden densan eerden 76 Flash NIemOBeS arten A Roir eee eet 1 Memory mter ul ii A di ida idea 79 Added Features tithe Holl Version a eltinten take 79 JE AROS COSA etende eentiende 80 INE SUSI OR 900 POPE POE A O ed eene bd debet dahensed tah lst ua cuseheoacts 80 Capac lOP di iii 82 Poly Roly Capac iO unda eenen ee daa alate dees 83 Prede conneeted MO Sii A eeen AT 84 VOAS eR SLT AT 85 PRIMM CT Sau veslo seta ii 86 Simple Diferenta API caidncesean A A cha A Aia 89 Added Features tthe Boll VETO NS cate atid 92 10 Radio Frequency Cir CU A A dense 93 On C vif IES A A A nnee eene ede 93 POWER as 95 A A A A N 97 Amalog to diertal
128. ure 9 3 Removing the salicide material thanks to an option layer Other resistors consist of N or P diffusions An interesting feature of diffusion resistor 1s the ability to combine a significant resistance value and a diode effect The diffusion resistor is used in input output protection devices In 45 nm technology the metal gate has a low resistance 5 2 square thus N diffusion material might be used to generate resistances instead of gate layer The resistor value varies because of lithography and process variations In the case of the poly resistance the width height and doping may vary Figure 8 4 left Polysilicon resistors are rarely designed with the minimum 2 lambda width but rather 4 or 6 lambda so that the impact of the width variations is smaller But the equivalent resistance is smaller meaning less silicon efficiency A variation AW of 0 2A on both edges results in a 20 variation of the resistance on a 2A width resistor but only a 10 variation for a larger resistor designed with a width of 4A 81 21 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL 8 Analog Cells AW AW 0 2A AW 0 22 gt it AN doping 20 variation 10 variation Figure 9 4 Resistance variations with the process In CMOS 45 nm technology the gate material features a low resistivity as it 1s based on metal materials See section 1 Capacitor Capacitors are used in analog design to build filters compensation decoupling
129. ve nanasan ananas PILI SLA LA K AVANAN P 5 ananas E OSCAR E PASAS WS SSK ananas RARA LIALATALAL Column address Read Write Circuit ig DataOut mm Control LI Dataln Figure 8 8 The column selection circuit principles 21 09 2009 73 MICROWIND DSCH V3 5 LITE USER S MANUAL 7 Memory circuits A Complete 64 bit SRAM The 64 bit SRAM memory interface is shown in figure 7 9 The 64 bits of memory are organized in words of 4 bits meaning that Dataln and DataOut have a 4 bit width Each data D0 DI5 occupies 4 contiguous memory cells in the array Four address lines are necessary to decode one address among 16 The memory structure requires two address lines 40 and A for the word lines WLE 0 WL 3 and two address lines 42 and A3 for the bit line selection The final layout of the 64 bit static RAM is proposed in Figure 7 10 Chip Enable As D3 1 D7 Dili DIS I i I I i i I I i i I I WL LA EE 2a iI i ii i ANDA Da pio pia bus I l I I I I I l we AL Aa Bie di ins DIS Read Write LOAD Data Out WL oe i ot 4 E bus I i I I i I i i I l i I i i i I I D4 D8 1 1 Dil21 J w Pe I I I Data In a bus Each Data has a 4 bit size EL ETELE AULA gt Be THEE aA mn SS E D E E ie r an TIRA POT RS E E Gf HE F ri 3 TH BALT sine BEL FL
130. voltage and under voltage protections due to external voltage stress electrostatic discharge ESD coupling with external electromagnetic sources etc Such protections are required as the oxide of the gate connected to the input can easily be destroyed by over voltage The electrostatic discharges may attain 1000 to 5000 V One of the most simple ESD protections is made up of one resistance and two diodes Figure 10 4 The resistor helps to dissipate the parasitic energy and reduces the amplitude of the voltage overstress One diode handles the negative voltage flowing inside the circuit N P substrate diode the other diode P N well handles the positive voltage The combination of the serial resistor and the diode bridge represents an acceptable protection circuit against transient voltage overstress around 50 V 107 21 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL 10 I O Interfacing T rT very low voltage very high voltage Nwell Bi ae Nditt Psub Figure 11 4 Input protection circuit IOPadIn SCH Diodes are essential parts of the ESD protection Used since the infancy stage of microelectronics the diodes are still widely used because of their efficiency and simplicity Dabral The native diodes in CMOS technology consist of an N diffusion in the p substrate and a P diffusion in the n well The command used to generate a protection diode in MICROWIND is Edit Generate Diode Click either the P
131. w resistive layer SiN Novel METAL gate Nickel Hafnium Silicide Gate oxide 2 0 nm K 12 0 i Source i 1 Drain Equivalent to 0 6 nm f SiO2 which means a y a higher capacitance ae fast device Reduced gate leakage os Figure 1 3 The metal gate combined with High K oxide material enhance the MOS device performance in terms of switching speed and significantly reduce the leakage Drain current A um lon current Effective Electron mobility cm V s Optimized Poly SiO IIE GSS TiN HfO Rn O 103 gt NN gt e ne 250 gt Poly SiOz Lz 10 A p 10 200 Tee 107 e eu f m Poly HfOz 10 i loff current 150 m decrease L 10 zene 1 MV cm as 100 0 0 0 5 1 0 Gate voltage V 0 0 1 0 2 0 Equivalent Gate Oxide nm Figure 1 4 The metal gate combined with High K oxide material enhances the Ion current and drastically reduces the loff current left Electron mobility vs Equivalent gate oxide thickness for various materials right The effective electron mobility is significantly reduced with a decrease of the equivalent gate oxide thickness as seen in Fig 1 4 which compiles information from Chau2004 Lee2005 Song2006 It can be seen that the highest mobility is obtained with optimized TiN HfO while Poly HfO do not lead to suitable performances Strained Silicon Strained silicon has been introduced starting with the 90 nm technology
132. xternal perturbations Usually an on chip voltage regulator converts the high voltage into an internal low voltage A metal wire cannot drive an unlimited amount of current When the average current density is higher than 2 10 A m Hastings the grains of the polycrystalline aluminum interconnect start to migrate The phenomenon is called electro migration and the conductor ultimately melts To handle very high current density the supply metal lines must be enlarged A typical rule of thumb is 2 mA um width for aluminum supply lines and 5 mA um for copper which means that a copper interconnect is superior to aluminum in sustaining large currents 106 21 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL 10 I O Interfacing Block smeten ES to VDD VSS MA Metal 5 grid a Metal 6 grid Space left for routing aa Figure 11 3 The supply rails are routed in metal5 and metal6 with a regular grid to provide power supply in all regions of the integrated circuit A complex logic core may consume amperes of current In that case the supply lines must be enlarged in order to handle very large currents properly The usually design approach consists in creating a regular grid structure as illustrated in figure 10 3 which provides the supply current at all points of the integrated circuit In that test circuit the VDD supply is assigned to metals VSS to metal6 Input Structures The input pad includes some over
133. y Ctrl F nto Colors roperties Print Layout 1D examples ADC MSK 2 D examples DAC MSK 3 D examples WCO MSK Leave Microwind ctrl 9 e d o eee moped RAVE MICTQWI DG ennen d Unselect all layers VIEW MENU and redraw the layout Fit the window with Unselect All all the edited layout Val 7 In Z i Zogm In Extract the electrical a ae om Out node starting at the the layout window cursor location Y View electrical Node v Lambda grid Give the label list Routing Grid Toa E List Give the list of nMOS ie ist and pMOS devices Show Hide the lambda grid or the cell compiler grid View one interconnect witho extracting the whole circuit a window Zoom window Show the palette of i Palere of Layers Show the navigator layers the layout window to display the macro and the node properties simulation properties Enable the zoom window to pilot large 120 21 09 2009 MICROWIND DSCH V3 5 LITE USER S MANUAL 15 References CAERE gommand Edit Simulate Compile Analysis Help EDIT MENU ae Cut elements included in an area _ Bae Ctr Move elements included in an area Ctrl or stretch the selected box border op ctrl E Duplicate elements included in Faste Ctrl V an area Move rea or Stretch ove step by step a Move Step by Step ak Ctrl M lection of elements Flip or rotate elements Flin and Rotate b included in an area lt A Prot
134. zation ring consists in using the Path generator command and selection the option Metal and p diffusion Then draw the location for the polarization contacts in order to complete the ring The distinction between class A B AB etc amplifiers is mainly given with the polarization of the input signal A Class A amplifier is polarized in such a way that the transistor is always conducting The MOS device operates almost linearly set ele NOE Figure 10 7 The layout of the power MOS also includes a polarization ring and the contacts to metal2 connections to VRF_in and VOut PowerAmplifier MSK 96 21 09 2009 MICROWIND amp DSCH V3 5 LITE USER S MANUAL 9 Radio frequency Circuits H Nmos W 66 400 L 0 080 ym lol x Ids 0 mA 70 0 1 80 65 0 60 0 Leet 55 0 T 50 0 45 0 a ee 40 0 l 35 0 1 44 a 09 25 0 ES 20 0 s 15 0 de ay 10 0 E y s 5 50 ff s 0 0 DD Ne ee 0 00 0 50 1 00 1 50 vds E E varromoto 1 800 Forvg tom oto f1 800 4 54944 saya elfe m x lei N1 66 400x0 080urr w Figure 10 8 The class A amplifier has a sinusoidal input PowerAmplifierClassA MSK The sinusoidal input offset is 0 7 V the amplitude is 0 4V The power MOS functional point trajectory is plotted in figure 9 8 and is obtained using the command Simulate on Layout We see the evolution of the functional point w

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