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Microcomputer based electronic trip system for circuit breakers

1. amp amp ROM LOOKUP ROUTINE FOR BREAKER AMP RATING ENTER AMPI amp amp amp amp amp amp amp amp amp amp amp amp amp amp amp amp amp amp amp 888 amp amp amp amp amp amp amp ORG DB 080 020 0 4 022 8 2 060 000H 032H DB 040 00 DB 4 057 05 O5DH 061H 068H D6DH 075H 07 082 088H DB OBCHJO9CH AMP13 LAMT RT 15355555555555555555555555555555555555555555555555555555555555555555555555555 5 8 5 TRANSFER TEMPORARY DATA INTO PERMANENT LOCATIONS 5 M SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS XFER TRANSFER ONLY DATA IN THIS PACKET XADR PAK LADR PAK SKAEI 02H GJMP XFER PACKET 2 DATA LADR TSD XADR LADR TRPID XADR CRPID LADR XADR COPT RT XFER PACKET DATA XF 5 GJMP XF2 LADR 115 XADR CLTS RT EEE KEKE KEE KE KEE KEKE KEKE KEE KEKE KEKE RE REE RE KR ER amp Uu ROM LOOKUP ROUTINE FOR LCD DATA RIGHT SIDE OF CHAR 8 88 8 8 85 5 8 8 85 5 8 8 8 5 8 8 8 8 4 8 5 88 8 8 8 8 2 8 8 8 8 8 8 8 5 8 8 8 8 8 8 8 8 8 8 8 8 8 8 5 136 458 167 168 ORG 4001 DRIGHT DB 66464226660 RIGHT LAMT RT 4 XFER PACKET 0 OR 1 DATA XF2 MERGE MERGE 2X7 BYTES IN
2. Se se we READREADREADREADREADREADREADREADREADREADREADREADRERDREADREADREADREADREADRERAD THIS ROUTINE READS THE EEPROM AND STORES THE DATA INTO THE CORRECT RAM LOCATIONS FOR HISTORICAL DATA ADDRESS WEE MUST BE CALLED FIRST 19 POSITION THE DATA POINTER TO THE CORRECT DATA BYTE CALLED WITH ACCA ACCB IX OR IY SET TO ANYTHING ALL VARIABLES IN THESE LOCATIONS ARE DESTROYED dt dt e e de e e c e e e c e e e de e e e e e ie e dr n e e e e e de e e de ic e de de e e e e e de e e e e e e e e de fefe de efe e de READ EE EQU 5 value to indicate sending address LDX REGSTART location for port D BSET PORTD X SDA set clock 6 data lines high BSET DDRD X SCL SDA set data amp clock for output BSET PORID X SCL set the clock high NOP need to add delay for EE timing 5 136 458 69 70 this is to make sure start timing NOP has sufficient time BCLR PORTD X SDA set data line low for start bit LDAA 1 address for reading data JSR SEND ADDR go send read command after returning the scl line is low TRIP start of historical RAM locations UNLOAD EE EQU LDAB 08 78 bits byte GET NEXT BIT EQU 5 BSET PORTD X SCL set clock high to hold data BRCLR PORTD X SDA CLRC BIT see if this works to replace 3 lin brset takes 2 less instruction cycles SEC set c
3. BCD VALUE A CALCULATE RUNNING CURRENT TIMES TEN amp 1 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 888888 88 88 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8888888888 sINITIALIZE MEMORY STORAGE AND SUMI VALUE TAMP LAI TAE LHLI 09H COUNTFOR TE INITIALZE DATA TO 00 TEMPI TEMP2 TEMPS 5 GJMP 2 amp P ROM LOOKUP ROUTINE FOR BREAKER AMP RATING ENTER AT AMP amp amp ORG DB DB DB DB AMP9 LAMT DORT DAOH D10H DF2H 36H DY2H O98 5 O1FH027H 28H D2DH 2 Tun 5 136 458 161 162 CONTINUE WITH 10X RATING CALCULATION TAMP ADD NUMBER TO ITSELF FOR TEN ITTERATIONS TAMP2 RC RESET CARRY TEMPI LADR LSN DLS 5 GJMP TAMPI RT RETURN IF OVERFLOW ERROR 88888888888888888888888338 8 8838888888888888888888888 amp ROM LOOKUP ROUTINE FOR BREAKER RATING ENTER AMP10 y DB 098H 05 0 020 05 078H DB 064 0 8 00 DB 027 030 036 038 03AH O3DH 041H 049 051 055 DB 057H 061H 10 LAMT RT CONTINUE WITH TEN TIMES CURRENT CALCULATION TAMP T
4. 01 if packet is 1 BEQ LOAD NEXT PACKET next packet from packet holder LDAA TRIP STATUS BYTE we in trip ANDA 570 mask all but trip bits BEQ NORM DATA 0 we are not tripping CMPA 570 sis this test data BEQ DATA yes transmit normally JMP SEND PACKET2 no we are tripping NORM DATA EQU CLR PACKET PTR no trip so clear packet pointer JMP SEND CHECKSUM go send the checksum INC_PACKET EQU 5 handles constant transition of packet 0 to 1 Bypassed if tripping INC PACKET packet pointer 0 set to 1 JMP SEND CHECKSUM 240 send the checksum LOAD NEXT PACKET EQU 5 Packet holder keeps track of packets 2 7 Packet pointer is used to point into the correct position in the Serial buffer for the packet being sent Packet pointer values will follow a 0 1 2 0 1 3 0 1 4 pattern Hope the pattern looks familiar Se Me vo e LDAA PACKET HOLDER get next packet to send STAA PACKET PTR store to pointer for use CMPA 07 116 packet 7 BLO TO TOP YET don t reset not at top of buffer yet LDAA 2 load reset value STAA PACKET HOLDER save it to packet holder JMP SEND CHECKSUM packet holder is reset go send checksum NOT TO TOP YET EQU INC PACKET HOLDER gt packet 7 so increment packet JMP SEND CHECKSUM 2409 send checksum SEND PACKET2 EQU When tripping we come here It s a good place to eat LDAA 2 load packet 2 for trip communication S
5. 024 JVWB3H1 31038 13538 8 09 291 8059436 110 NI 2 901271 2 i 1NIVH1S3H inivaisay 201 8 bli 90 i V bil 901 N 40 Sol 901 U S Patent Aug 4 1992 Sheet 2 of 10 5 136 458 210 5 136 458 Aug 4 1992 U S Patent O T 05532044 AV1dSI0 918 clea OLE e e N 218 U S Patent 2 Aug 4 1992 4 of 10 5 136 458 376 BEGIN 378 INTERRUPT 1 380 INITIALIZE MEMORY RESET TIMER WAIT FOR DATA READY FLAG BEGIN INTERRUPT 2 400 DETERMINE PHASE SELECTOR WAIT FOR SWITCH RELEASE DEBOUNCE SWITCH RETURN FROM INTERRUPT STORE DATA AND RESET FLAG 382 CONVERT DATA TO BCD FORMAT SEND DATA TO LCD DISPLAY DETERMINE OF TRIP RATING 402 404 384 406 386 CHECKSUM CORRECT 388 DETERMINED TO LCD MIA DISPLAY GRAPH E 398 RETURN FROM INTERRUPT FIG 3b Sheet 5 of 10 5 136 458 Aug 4 1992 U S Patent 66 8 914 9191 66 2 r913 egg 689 965 A6 2997 3 666 80 leos USS Patent Aug 4 1992 S
6. 5 136 458 137 138 LT RATIO TABLE 6D A4 F7 181 25D 5371 44E 52B LT_RATIO_SE DW 565 4 5 7 5181 5250 5371 5530 57 8 dee ee de dede deed LONG TIME 973 RATIO TABLES d do dede fe dede e dee e LT 97 RATIO DW 104 155 234 365 574 836 1046 1256 5 ROW AND SE LT 97 RATIO 104 158 237 370 582 852 1275 1729 THIS ROW MUST CONTIGUOUS de dee ede e de e ee ee e e e je e dee dee de e eee e e e e e ee e ee ede de e de ee je e ee 522127777773 LT DEL TBL LT LE LONG 7161217 10777994 16203159 25245100 LONG 39712206 57796089 72263195 86730301 LT ME LONG 7161217 10777994 16203159 25245100 LONG 39712206 57796089 72263195 86730301 LT NE LONG 7144197 10760974 16186138 25228080 LONG 39695186 57779069 72246175 86713281 LT PE LONG 7076116 10692893 16118058 25159999 LONG 39627106 57710988 72178095 86645201 LT SE LONG 7114412 10731188 16156353 25198295 LONG 39665401 57749284 86683496 130084815 LT DS LONG 6999526 10616302 16041467 25083409 LONG 39550515 57634398 86568610 129969929 THIS IS THE TABLE FOR CONVERTING RAW A D TO CURRENT VALUES Tables have been adjusted 3 high for low communication values Single bit accuracy can be found by dividing table value by 256 CURRENT EQU 5 I 200 AMP DW 244 303 342 354 363 380 406 416 457 487 507 533 549 609 I 250 AMP DW 304 380 429
7. ee The 3 timers are staggered at l6mSec intervals to allow system time to catch up with any exceptionally long RMS calculations LDAA 48 begin A PHASE 8 48 mS to stagger RMS calc 5 PHASEA RMS store to A PHASE timer LDAA 32 begin B PHASE 8 32 mS to stagger RMS calc STAA T PHASEB RMS store to B PHASE timer LDAA 416 begin C PHASE 6 16 mS to stagger RMS calc 5 PHASEC RMS Store to C PHASE timer LDAA 1 STAA T 2MS ST set ST 2mS timer to 1 mS READ MEMORY EQU 2 IF OVERLOAD MEMORY CAP VOLTS IS gt 3 VOLTS SET SO OVERLOAD ACCUMULATOR IS CALCULATED lst PASS THRU 7mSEC ROUTINE sexxxxxx LDAB 1034 get A D into ACCB CMPB 510 to 10 hex FAST TIMERS if low bypass setting flag BSET LT FLAGS SET ACCUM set bit so Ovld Accum is calculated SET FAST TIMERS EQU SET SHORT TIME FAST TRIP TIMER TO 33MS STARTUP TIME 27MS 1 SET GROUND FAULT FAST TRIP TIMER TO 33MS STARTUP TIME 18MS 2 RETENTION TIMERS ARE STARTED TO RESET THE FAST UNRESTRAINED GF amp ST TIMERS LDAA 33 6 load ST unrestrained timer value STAA ST FTIMER save into unrestrained timer location DO ST RETN EQU 5 5 136 458 37 38 REE EERE QUE THE SHORT TIME MEMORY RETENTION TIMER FOR 36 MS RETENTION timer is loaded so that after 3
8. CLEAR FOR CHECKSUM CODESTART bottom of PROM 5 0 X add byte to ACCA decrement IX 141 BNE _ ADD NEXT BYTE ADCB 0 STAB I 5 136 458 142 add next byte add carry back in all done so save it pss EEPROM TEST DONE HERE de d de fe e de Je de de 5 JSR _ RESET COP LDAA PORTA REGSTART ANDA 504 BEQ EEPROM TEST yere THIS SECTION LOOPED BY PULLING EEPROM TEST keep the puppy happy read portA mask for SC restraint sloop back THE ST RESTRAINT LINE HIGH xxx 2 RESTART INTERRUPTS AT THIS POINT 3 eede eee e e de de de de de de k ke set for prod test start of onboard registers set up portd data direction up portd data read interrupts Clear interrupts value for SmSec interrrupt load output compare register allow timer 1 interrupt shut down instantaneous shut down watchdog allow interrupts MULTI TESTING DONE HERE 88 eke ede ec de eee e dede e ed ede dee if 0 don t corrupt data start of retrieval _ storage location start move raw A D data get packet for check subtract 1 to check for data conflict if go read porta input retrieve from imove raw A D data save to serial buffer if clr restraint is high no restraint so clear get start of registers clr restraint line set flag for desense get 2 mSec timer check for 50 mSec start repeating tests again
9. STX SOFT DOG TIMER save it back again BNE CHECK SOFT 2 stimer 1 hasn t timed out go do 2 LDX DOG TIMER2 get timer 2 value STX SOFT DOG TIMERl put it into timer 1 0000 load 0 to clear STD 5 DOG TIMER2 clear timer 2 DEC SOFT DOG CNTR decrement the softdog counter BNE HOME we still have more errors LDAA 5 get softdog reset value STAA SOFT DOG reset the counter JMP HOME return to routine CHECK SOFT T2 LDX 5 DOG TIMER2 get timer 2 BEQ HOME timer is already 0 so leave DEX decrement counter STX SOFT DOG TIMER2 restore timer GO HOME EQU 5 RTS return PAGE PPTTTTTTTTTTTT ALL PICK UP AND DELAY TABLES ARE IN THIS LOCATION COMMENT BBBB L EEEEEEE SSSSSSS T A B B L E S T AA L E S T AARAA BBBB L EEEEEEE SSSSSSS T A A B B L E S T A A B B L 5 T A BBBB LLLLLLL EEEEEEE SSSSSSS FOR ALL BREAKERS EXCEPT THE PE EQU DW INST PU TBL FOR THE PE BREAKER TTTTTTTTTTTTTTTTTTTTTT INSTANTANEOUS PICK UP TABLES 41 61 82 102 123 164 205 246 INST PE EQU 5 DW 41 51 61 82 102 123 143 164 INST 2000A PE EQU Dw 41 51 61 72 82 92 103 123 LI INST 2500 PE EQU 5 DW 41 45 51 61 72 82 92 102 5 136 458 133 134 stable is shifted to allow for working of INST routine with ST INPU switch value is shifted
10. Se 5 Se Se ne e e e e e e e e e ice e e de fe e fe e e e e dede de ie e dee de de dede dede dn CHECK ST 12MS EQU BRSET ST FLAGS NO ST BIT SHORT TIME NOT INSTALLED IF ST NOT INSTALLED JUST CLEAR STPU BIT DON T CHECK FOR PU LOX ST TABLE POS get saved table position LDD ST PEAK latest ST peak _ 0 to pu tbl BLS SHORT TIME NOT INSTALLED lt table no pick up clear flac if in STPU turn super desense BSET FLAGS SUPER DESENSE turn on super desense BRA SET DESENSE FLAG turn on normal flag pp ee GET WE DO NOT HAVE A SHORT TIME PICK UP SHORT TIME NOT INSTALLED EQU BCLR ST_FLAGS ST_PU_BIT WE DON T HAVE PU SO CLEAR BCLR SC PU GF PU 07 pickup so clear all phase pickups 17 MOTOR PROTECTION WILL CALL AT THIS POINT TO CLEAR PEAK OF PHASES RETURN CLEARED EQU 100 ST_PEAK GET PEAK OF LAST 11 mSEC BRSET INST FLAGS INST OFF BIT CHECK FOR 3XP 2 INST OFF DCN T CHE LDX INST TABLE VAL get inst PU value 2 turn Desense ON or OFF as appropriate via the ST PEAK value determined in the MAIN task This gives the desense a less reactive appearance CPD 0 to Inst pick up value CHECK FOR check for norm desense BSET GF FLAGS SUPER V DESENSE turn on super desense BRA SET
11. go to top amp run again TEST SUBROUTINES ARE HERE e e e de e fe e dn le de ie eed d MOVE TO SERIAL DO NEXT BYTE X IS OK EQU LDAA STAA CLRA EQU LDAB LSLD LSRB STAB INX INY CPX BNE INX EQU DEC BNE RTS 5 4 RATIO X IS OK 5 DO NEXT BYTE 0 Y 2 OF PASSES save it clr for rebuilding data load ACCB from pointer format data finish format save off ACCB increment pointers are we pointing at memory ratio no move to correct position count down move next byte all done store high bits ee de de dede ee dee dede RAM RETENTION TEST DONE HERE 3t c ife c e de e e e e e e e le t e de dede ede eoe CHECK RAM RETENTIO RAM FAILURE RAM REMEMBERS PAGE ORIGIN FFCO RESERVED1 RESERVED2 RESERVED3 RESERVED4 RESERVEDS RESERVED6 RESERVED RESERVED8 RESERVED9 RESERVEDA RESERVEDB SCI INT SPIE INT INT PAOVI INT E N EQU EQU 0 X RAM_FAILURE 5 00 CHECK RAM RETENTION RAM REMEMBERS 5 5210 0 SOFTDOG INTERRUPT SOFTDOG INTERRUPT SOFTDOG INTERRUPT SOFTDOG INTERRUPT SOFTDOG INTERRUPT SOFTDOG INTERRUPT SOFTDOG INTERRUPT SOFTDOG INTERRUPT SOFTDOG INTERRUPT SOFTDOG INTERRUPT SOFTDOG INTERRUPT SOFTDOG INTERRUPT SOFTDOG INTERRUPT SOFTDOG INTERRUPT SOFTDOG INTERRUPT COMPARE DATA FOR GOOD VALUE 7if not 0 RAM was bad
12. storage for phase unbalance ST PEAK RMB 2 speak of all phases for ST ST TABLE POS RMB 2 stable position for STPU 115 GF PEAK RMB 2 current to transmit GF TABLE POS RMB 2 stable pos for GF PU 13 5 LAST APHASE RMB 1 storage pass location LAST BPHASE 1 peak storage pass location LAST CPHASE RMB 1 storage pass location PHASEX6 RMB 2 Storage for phase pickup B PHASEX6 RB 2 for phase pickup C PHASEX6 RB 2 storage for phase pickup CHANNELS MUST STAY CONTIGUOS CCCCCCCCCCCCCCCCCCCCCC 1 L PHASEA RMB 1 phase low gain A D L PHASEB RMB 1 B phase low gain A D L PHASEC RMB 1 C phase low gain A D z 5 MEM_RATIO RB 2 channel one atod multiplexor HI PHASEA RMB 1 phase high gain A D PHASEB RMB 1 2 phase high gain A D HI PHASEC RMB 1 phase high gain A D NEW GF RMB 1 for trip routine usage 3 CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC 16 5 136 458 29 30 CUR ATOD PTR RMB 0 Start of the current working A D vals CUR RMB 2 This area contains the current CUR PHASEB RMB 2 A D values that are used for CUR PHASEC RB 2 all calculations CUR GF RMB 2 e 5 SQRT MUST STAY CONTIGUOS PHAS SQRTS RMB 0 POINTER TO ALL 3 SQ ROOTS PHASA SORT RMB 2 SQRT PHAS A PHASB SQRT RMB 2 SQRT PHAS B PHASC SQRT RM
13. 0 1 THE LDAB ABOVE IS TO ALLOW TIME FOR THE SLEW RATE OF THE RESTRAINT OUT LINZ The filter slows the restraint line down so much that 2mSec pass before TU realizes it is self restrained TEST GF DELAYS EQU 5 test for GFRI line active here active low LDX REGSTART get start of onboard registers BRCLR PORTA X GF RES IN GF RESTRN DELAYS if active use restrain WE DO NOT HAVE RESTRAINED DELAYS USE GF FAST TIMER DEC GF_FTIMER decrement fast timer DEC decrement fast timer BGT EXIT GF timer 0 branch JMP GF TRIP else go trip GF RESTRN DELAYS EQU 5 THE VALUE IN ACCB FROM BEFORE TEST GF DELAYS IS USED HERE SO BE CAREFUL CMPB 06 IF gt 6 I 2 DELAY BHI GF 15 GF I 2 IN RUN ON 13mSEC TIME FRAM 1 GROUND FAULT RESTRAINED FIXED DELAYS CHECK FOR ACTIVE TIMER LDD GF LONG TIME Isq out timer CPD SFFFF we even have a timer BEQ GP SCHED TIMER go start a timer BCLR GF LONG TIME T INACTIVE wake timer up if asleep JMP EXIT GF CONTINUE IN MAIN FLOW GF SCHED TIMER EQU 5 LOX GF FIXED_DEL START LOCATION OF FIXED DELAY GFDELSW GF SWITCH ADDRESS LDAA 8 MULT BY 8 FOR ENTRIES PER ROW BSET FLAGSS WRD ALIGN 1 WORD BOUNDARY JSR SET TBL INDX CALL INDEX ROUTINE LDX 0 X LOAD TIMER VALUE FROM TABLE STX GF LONG TIME save to timer EXIT GF DONE GO BACK MAIN FLOW GF OFF EQU EXIT GF
14. D REGISTER XADR TSH ACCUMULATOR SERIAL LOW TAE REGISTER x SERIAL LOW TDA ACCUMULATOR D REG SERIAL HIGH 5 136 458 13 174 TEST FOR PACKET NUMBER BYTE 0 2 IF SO SETUP CHECKSUM AND BYTE COUNT 11 p21 P3 P31 P4 SKABT GJMP TEA XADR TEA SKAEI GJMP XADR LAI XADR SKAEI CALL XADR LAI XADR GJMP GJMP XADR LADR GJMP LADR SKAEI GJMP LAI GJMP SKAEI GJMP GJMP GJMP GJMP GJMP 3 STATUS PACKET BYTE 3 SET PACKET NUM BYTE TEST BYTE COUNT x SERIAL LOW PTEMP SAVE TEMP PACKET NUMBER 02 P2 CHK RDY XFER OOH XFER 01H Pit PACKET 2 BYTE PACKET O OR 1 CHECKSUM BYTE 0 READY FLAG 0 RESET DATA READY FLAG WAS XFER PREVIOUS PACKET 4 0 1 0 CHECKSUM BYTE 5 FOR DATA READY FLAG FLAG NOT SET CONTINUE FLAG 15 SET RETURN PHASE SELECT BYTE PHASE x FOR C PHASE NEITHER C OR GF RETURN FOR GF PHASE BYTE CHECKSUM BYTE 0 FOR DATA READY FLAG FLAG NOT SET CONTINUE FLAG IS SET RETURN PHASE SELECT BYTE A PHASE 1 FOR A PHASE PHASE NEITHER OR B RETURN
15. PHASE I point to storage JSR 1 CONVERSION 240 convert to xmit format CHECK TRIP V EQU m x BRSET FLAGSS KILL WATCHDOG BIT KILL TRIP V if soft trip don t send tri signal LDX REGSTART get start of onboard regs LDY TRIP SUPPLY get trip supply location BRCLR O0 Y TRIP VOLTS OK KILL TRIP V if low voltage kill trip coil voi LDAB TRIP FLAG get cause of trip LDAA read the portA lines ANDA O for trip bit ABA add in trip cause STAA PORTA X write out to portA BSET PORTA X TRIP turn or keep trip volts on JMP CHECK SERIAL see if ready for next byte KILL TRIP V EQU 5 BCLR PORTA X TRIP BIT O low voltage kill trip signal CHECK SERIAL EQU BRCLR SCSR X TRANSMIT DONE CHECK RESET if is not set wait JSR SERIAL TDRE 15 set so transmit CHECK_RESET EQU 5 HI_PHASEA get pointer for current A D CHECK_AGAIN EQU LDAB 0 current A D value 510 to A D value of 10 allow for noise BLS NEXT PHASE if lower check next phase CLR 250MS Clear timer not time to re initialize veti NEXT_PHASE EQU P INX 1 for 8 bit words to memory location BLS CHECK AGAIN check until all phases have been checked LDAA T 250MS get timer for reinitialize BMI RE INIT if we go 128 mSec w no current initialize TU REPETE EQU 5 JMP EE WRITE play it again Sam till we die
16. SORT CPD 0 BHS LT_PICK_UP BCLR LT FLAGS LT PU BIT LDX 90 LDAB TEMP ABX LDD PEAK SQRT CPD 0 BHS LT GT 90 BCLR LT FLAGS LT 090 JMP SWITCHES LT PICK UP EQU BSET BSET LT FLAGS LT GIZ BIT BCLR LT FLAGS LT 090 LDX BSET PORTA X LED LDX SQRT SORT JSR SQUARE LDD RESULT 2 LDX ACCUM JSR ACCUM4 ADD 100 RESULT ADDD ACCUM STD ACCUM LDX DEL TBL LDY LTDELSW LDAA 32 BCLR FLAGSS WRD ALIGN JSR SET TBL INDX COMPARE THE LT ACCUMULATOR TO THE DELAY TABLE LT_ACCUM JSR WORD 00 TRIP JMP SWITCHES LT 90 BSET FLAGS LT 090 BIT DO SWITCHES EQU 65 SWITCH COMMUNICATIONS MUST BE KEPT HERE OR TEMP MUST HOLD LT SWITCH VALUE DO SERIAL COMM FOR SWITCHES TURN TO MAIN FLOW WE EXCEED LT DELAY VALUE WE END UP HERE dedede d eie ineo MORE INTERUUPTS PLEASE 290 reset the softdog CLEAR TRIP CAUSE SET CAUSE OF TRIP AS LT TRIP increment of LT trips mask off unused bits max trip if high bit clear leave still room increment counters clear counter for rollover JSR DO LT FLC SW COMM RTS P TE LT TRIP SEI JSR RESET COP LDX amp REGSTART BCLR TRIP STATUS 570 BSET TRIP STATUS BYTE 10 COMMON LONG EQU 5 LDAA LT TRIP ANDA 63
17. lt 14 GF IS INSTALLED BSET FLAGSS NO GF WE HAVE NO GROUND FAULT CLR GF SWITCHES no GF installed so clear switch values BSET OPTIONS NO GF 5 TO SHOW GF NOT INSTALLED JMP GF EQU 5 LSRB LDAA GFDELSW ANDA SW POS LSLA LSLA STAA SWITCHES branch around switch set code do shift to get PU to low 3 bits delay value mask off unused bits shift to bits 3 5 shift to bits 3 5 add to PU switch value store in xmit location BCLR 55 GF CLEAR FLAG TO SHOW GF INSTALLED EQU BCLR OPTIONS SOF LDAA RATING PLUG ANDA SWITCH_MASK LSRA ORAA RP OPTIONS STAA RP OPTIONS RTS xmm ALL E SQUARED CODE IS IN THIS SECTION EEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE THIS SUBROUTINE ERASES THE EEPROM ttdi ieee de Ied dede dede weee BCLR RP OPTIONS NO CLEAR BIT TO SHOW GF INSTALLED clear rating plug bits read the rating plug mask off unused bits move to correct location for xmit byte combine with rest of the byte it back to xmit byte the party s over bye bye Only IX is used besides doesn t make any difference Breaker is tripped after E 2 is erased CALLED This is called when breaker type switch is set to 50 on power up RETURNS NEVER Trips the breaker 5 136 458 65 66 e e e e e e e e e
18. ve THE INTERRUPT CODE DOES THE FOLLOWING EVERY HALF MILLISECOND 1 CLEAR TIMER INTERRUPTS AND RESET THE OUTPUT COMPARE REGISTER TO ANOTHER 500 MICRO SECONDS BY ADDING 970 DECIMAL TO THE CURRENT FREE RUNNING 16 TIMER COUNTER 970 takes into account interrupt latency time Sa Me ve 5e e 5 136 458 119 120 2 IF THERE ISN T SOFTDOG TRIP STROBE HARDWARE WATCHDOG ON INITIATE THE ATOD HI GAIN READ 4 READ AND STORE ALL 3 LOW GAIN A D CHANNELS amp MEMORY CAP e 44 va ve 4 5 TURN SPI OFF AND TURN DESENSE ON or OFF AS REQUIRED RUN INSTANTANEOUS TIMER AND PICKUP READ EACH PHASE OF HI GAIN ATOD COMPARE EACH PHASE TO THE MAXIMUM HI GAIN VALUE OF HEX F6 TO SELECT HI OR LOW GAIN A D VALUE TO SUM INTO RMS SQUARED SUMMATION TABLE 4 e 8 READ THE GROUND FAULT ATOD VALUE 9 RESET A D HARDWARE FOR READING LOW GAIN CONTINUOSLY 10 TEST THE ONE MILLISECOND BIT IF BIT IS ON GOTO 11 ELSE GOTO 13 EVERY ONE MILLISECOND 11 INCREMENT ALL FIXED DELAY TIMERS BY ONE MILLISECONDS 12 GOTO 14 13 DECREMENT ALL VARIABLE QUE TIMERS BY ONE MILLISECOND 14 STROBE HARDWARE WATCHDOG OFF SET PORT BIT LOW 15 TURN SPI ON 16 RETURN FROM TIMER INTERRUPT Sa 5e Se 44 Se Se Se ta Se Se ve de t e e e e 1 e ec de fe dee e e e e fe cc le fe Pe e e c e e le e e e e e e ee e e e e e c e e e e e P e e e ee
19. Se Se Se Se se ve E v Qc CLEAR PEAK CLEAR GF PEAK TESTU PHASEA 2MS HJ Se Se Se Se 54 Se Se Se Se gt e e Se Se Se Se Se Se be e Se Se va ve TEST PHASEB e REY PHASEB 2MS t 5 Se Ge ove gt e gt e Se Se Se Se ta Se Sa gt e Se Se fe Se Se Se a Se 5e Se Se Se Ss e 7 Se 5 Se Se ye we IF 0 GOTO CLEAR GF ELSE IF GF RES IN 1 CLEAR PEAK RESTRAINT LINE HAVE INVERTERS ON INPUTS ELSE IF GF DELAY SWITCH lt 6 ELSE GF 150 1800 CHECK 13MS PHASE A 64 MS TIMER IF T PHASEA RMS 64 GOTO TEST PHASEA 2MS A PHASE 1 T_PHASEA RMS RMS 64 AVG RMS SUMSQH 1 PHASEA SORT RMS SOROOT GOTO 64 5 IF T RMS lt 8 GOTO TEST ELSE IF A PHASE 0 TEST PHASES ELSE PHASE_UNBALENCE SQRT IF SERIAL POINTER PHASE ELSE I CONVERSION PHASA SQRT A PEASZ A PHASE CONV 0 GOTO TEST_64Ms IF T_PHASEB FMS lt 64 GOTO TEST PHASEB 2MS B_PHASE_CONV 1 T PHASEB RMS PHASEB RMS 64 AVG RMS 2 PHASEB SORT RMS SQROOT GOTO TEST 64MS IF T PHASEB RMS 8 GOTO TEST PHASEC ELSE B PHASE CONV 0 TEST PHASEC ELSE UNBALENCE PHASB SORT IF SERIAL POINTER amp B
20. 3 FOR B PHASE 3 BYTE CHECKSUM BYTE READY FLAG 0 RESET DATA READY FLAG WAS SET XFER PREVIOUS PACKET 1 LONG TIME SWITCH TEST FOR BYTE COUNT lt 6 IF NOT RETURN IF IT IS PROCESS THE DATA LADR SKAEI GJMP GJMP BC 07H B2 El 7 RETURN B2 5 136 458 175 176 XAE IES E BC XADR BC STORE NEW BC LADR BC ACC NEW SKAEI 07H 77 VERIFY CHECKSUM AND SET DATA READY FLAG IF CORRECT GJMP B5 TEA ACC SERIAL LOW CHECKSUM HL TO POINT TO CHECKSUM SKAEM ACC CHECKSUM GJMP LAI OIH SET DATA READY FLAG XADR LADR PTEMP XADR TPAK GJMP 1 e ADD CHECKSUM SAVE DATA IF REQUIRED B3 HLPOINT TO CHECKSUM TEA SERIAL LOW NIBBLE ASC SERIAL LOW CHECKSUM ST STORE CHECKSUM HL POINT TO BYTE COUNT SELECTOR LADR BC BC 1 GJMP B4 LAI 04 SENSORBYTE SKAEM GJMP HB GJMP B5 STORE HIGH DATA BYTE HB PACKET 3 SAVE ONLY HIGH BYTE 0 2 LAI TOTHELONG TIME DATA BYTE SKAEM GJMP HBI TEA ACC SERIAL HIGH BYTE XADR 115 LAI 07H MASKBIT3 175 ANL XADR TLTS GJMP 1 EXIT HB SERIAL HIGH BYTE LOW NIBBLE XADR THLSN TEMP HIGH BYTE LSN TDA SERIAL HIGH BYTE HIGH NIBBLE XAD
21. TIMR 0 ELSE DEC SOFT CHECK ALL TIMERS GOTO MAIN FLOW PSUEDO CODE 4 EXEC F LOW 555555555555555555555555 BRSET GF FLAGS GF PU BIT CHK GF RESTRAINT if set go check for restrai JMP SCPU SHORT CIRCUIT PICK UP check odd even mSec 5 136 458 47 48 GF RESTRAINT EQU 5 WE GET HERE WE HAVE gf PICK UP SO ADJUST THE RESTRAINT HOLD TIMER LDAA 11 RESTRN TIME start restart a SC restraint timer DO SCPU CHK EQU 5 2 IF INST OR ST PU FLAGS ARE SET RESET THE RESTRAINT HOLD TIMER n BRSET INST FLAGS INST PU BIT CHK RESTRAINT 1 set go check for restraint BRSET ST_FLAGS ST PU_BIT CHK_ RESTRAINT if set go check for restrai JMP CHECK FOR ST NO SHORT CIRCUIT PICK UP check odd even mSec CHK RESTRAINT EQU 5 IF WE GET HERE WE HAVE SC PICK UP SO ADJUST THE RESTRAINT HOLD TIMER LDAA 10 STAA SC RESTRN TIMER start restart a SC restraint timer CODE HERE CHECKS 2MS TIMER FOR ST IF TIMER gt 2 DO SHORT TIME CODE CEECK FOR ST EQU 5 LDAA T 2MS ST get 2 mS short time timer CMPA 2 check for expired ST timer BHS DO PEAK COMM if ST timer is greater run ST JMP CHK EVEN MS else do GF routines DO PEAK COMM EQU 5 SUBA 2 subtract 2 from timer to reset 5 T 2MS ST save timer again JSR SET PHASEA PEAK routines ST amp Communicatn IS ST INSTALLED EQU DO
22. e e e ie dee de e de e e e de EK 5 136 458 11 112 211t2939t 99 312a ar P P RESULT USED 9 99 9t9z 99 1t9 T 2 2ITI Stc e de je fe e e e le de e dee e e e ie e fe r e e e e c de ec se de e e ee e de e e e e e dede de ede e e I CONVERSION EQU 5 PSHX save storage location for later use LDAB SENSOR the sensor size ANDB SWITCH MASK mask unused bits CMPB 51 max sensor size BLS BY 14 is OK go multiply LDAB 51 load max sensor MULT BY 14 EQU 5 ACCB IS ALREADY SET FOR WORD MULTIPLY SO EQUALS OF WORDS LDAA 14 714 words per row MUL find correct starting row ADDD CURRENT CONV TBL add to start of conversion multiplier table XGDX put into IX for index use BRCLR GE FLAGS USE XS BIT READ THE RPLUG if GF bit clear read the R LDAB 1 value for GF calculations JMP HAVE PLUG do calculations READ THE RPLUG EQU 5 PT T LDAB RATING PLUG read rating plug value ANDB SWITCH_MASK mask it 51 check for UTS or PROD tester BLO HAVE PLUG have an honest to goodness RP LDAB 100 if tester default to 4 multiplier WE HAVE PLUG 5 plug to row offset points to value JSR MUL 16X16 go do multiplication PI T RESULT IS NOW IN 32 RESULT LOCATION PULX get st
23. 63 BHS CLR LT TRIPS INC LT TRIP CNT JMP GO GLBAL continue CLR LT TRIPS EQU rS CLR LT TRIP CNT GO GLBAL EQU 5 gt BCLR FLAGSS KILL WATCHDOG not a soft trip so clr kill bit 5 136 458 83 84 LDX REGSTART register locations LDAA 1 BIT O get value to turn on LT trip line STAA PORTA X turn line on STAA TRIP FLAG SAVE FOR TRIP OUTDICATOR BSET _TRIP_CNT 40 of trip long time BCLR PU_TRIP_CNT 40 cause of trip phase unbal BCLR 5 TRIP CNT 40 cause of trip short circuit BCLR TRIP 540 cause of trip gnd fault BCLR SOFT TRIP CNT 40 cause of trip soft dog DELAY_32Ms 7 JMP VT CHECK GO CHECK TRIP VOLTAGE de e e fe je e ie e ce ie de e e e e e e de de e e ACCUM ADD he de de de e e de e e e ie je je e e e e de de ce e e e e fe de fe e de o e X POINTS TO ANY 4 BYTE ACCUMULATOR ADDS I 2 IN THE DBL ACCUM TO THE 4 BYTE ACCUM POINTED TO BY X H DBL REGISTER CONTAINS THE 16 BIT VALUE TO ADD TO THE ACCUMULATOR ACCUM4 ADD ADDD 2 X ADD DBL ACCUM TO LOW WORD STD 2 STORE LOW WORD OF 4 BYTE ACCUM 4 RET CARRY BIT ALL DONE LDD 0 HI WORD OF 4 BYTE ACCUM ADDD 1 ADD CARRY BIT TO HI WORD STD 0 STORE DBL ACCUM IN HI WORD ACCUM4_RET EQU 5 RTS e Ye e e e he e ce e de dece e dece e e e e e d e ACCUM eoe de de de oie de de e de e
24. BSET TRIP_STATUS_BYTE 70 LDX REGSTART BSET DDRD X 3E BSET PORTD X S3E LDAA 161 STAA TFLG1 X LDD TCNT X get timer ADDD 970 STD 1 BSET TMSK1 X 80 BSET IFLAGS TRIPPING BSET FLAGSS KILL WATCHDOG BIT CLI PAGE 2 e c Se fe hc fe fe e e ce e e e e e e e de e e e MULTI TEST EQU LD A PACKET BEQ TRY NEXT ATD VAL LDX PHASEA PHASE RMS JSR TO SERIAL TRY NEXT VAL LDAA PACKET PTR DECA BEQ READ PORTA LDX PHASEA PHASE RMS store to JSR TO SERIAL READ PORTA EQU 5 LDAA PORTA REGSTART read port MAX IDENT CHECK FOR DESENSE EQU BRCLR IDENT 02 DESENSE THE CLR FLAGS LDX REGSTART BCLR PORTD X GF_DESENSE_BIT_OUT BRA 5 SET DESENSE_THE_GF EQU BSET FLAGS TURN ON DESENSE GF DESENSE SET EQU TRY TRANSMIT LDAA 2MS ST 2 BLO PORTA if lt 2 branch CLR 2MS ST JSR SERIAL JSR _ RESET COP TOGGLE PORTA EQU LDAA T 250MS get timer CMPA 50 RETURN TO TEST CLR 250MS PClr timer LDAA PORTA REGSTART get portA values STORE INVERSE RETURN TO TEST TOP PAGE 143 COMA BRSET IDENT S04 STORE INVERSE ANDA EQU 5 136 458 SB8 PORTA REGSTART EQU MULTI_TEST 144 complement portA values SC restr off don t mask don t reset watchdog 7store the inverse
25. DESENSE FLAG turn on normal flag FOR 3XP EQU 5 BCLR GF FLAGS SUPER DESENSE if lt 6xP turn super desense off CPD DESENSE THRESHOLD compare to Desense threshold BLO CLR DESENSE zif below jump SET DESENSE FLAG EQU BSET FLAGS TURN ON DESENSE turn on desense JMP CLR PK VALS go clear ST peaks for next llmS values LR DESENSE EQU FLAGS TURN ON DESENSE turn off desense LDX REGSTART point to registers PORTD X GF_DESENSE OUT turnoff desense CLR_PK_VALS EQU 5 LDD 00 GET VALUE OF 0 FOR PEAK RESET STD ST PEAK ST PEAK FOR NEXT 12 mSEC PEAK STD A PHASEX6 1 phase STD B PHASEX6 Clear peak of B phase STD PHASEX6 Clear peak of C phase RTS STPU IS EITHER CLEARED OR LEFT SET SO RETURN 5 136 458 93 94 ST RETN TIMOUT CALLED From a 36mSec ST retention timer time out Unrestrained ST timer amp Double Accumulator flag cleared USED ACCA amp ACCB RESTORED NOTHING fe e e e e Se dede e de P e ee e e e e c e e e e e e e de e e e e e e e c fe e e e sie e ie fe c fe e de e e e e sl d e e RETURNS ST accumulator cleared ST 172 out timer cleared 54 54 Sa Sa Se gt e 5e ST RETN TIMOUT EQU LDAA 33 st fast timer value 33m
26. HERE WE DO NOT BAVE SEORT TIME PICK UP ST OFT CHECK FOR ACTIVE TIMER TEEN LEAVE ST ROUTINE WE DO HAVE SHORT TIME PICK UP WHEN WE REACH HERE ST UP EQU REGSTART set x to 6811 io 3 BSET PORTA Y SC CUT curn on restraint out restraint is turned on here to allow for slew rate in self restrained brkrs BSET ST FLAGS ST PU SET ST PICK UP FLAG BIT START RESET TEE ST MEMORY RETENTICN TIMER LDAA 36 retention time is 36 mSec ST RETN TIMER Start reset timer 5 136 458 49 TEST_RESTRAINT EQ NOW TEST FOR A RESTRAINT INPUT TO BYPASS THE ST FAST TIMER BRCLR PORTA Y SC RESTRAINT BIT IN RESTRN DELAY 50 290 we have restrained Gelays DEC ST FTIMER no restraint use fast DEC ST FTIMER Laid BGT EXIT ST atimer has not expired JMP ST_TRIP timer has expired so trip EXIT_ST EQU JMP EXIT_SHORT_TIME 260 LEAVE ST ROUTINE RESTRN DELAY LDAB STDELSW READ ST DELAY SWITCH ANDB SW POS MASK ZERO BIT CMPB 06 IF SW gt 6 I 2 IN EXIT SHORT TIME 5 SET FOR I 2 IN WAIT FOR 115 ROUTINE 2 SHORT TIME SWITCH IS SET FOR FIXED DELAY ST FIX DELAY EQU LDD ST I2 OUT TIMER get I squared out timer CPD 5 to null value BEQ SCHED TIMER no timer so start one BCLR ST 12 _ TIMER T INACTIVE timer may be asleep wake JMP EXIT SHORT TIME we have an active timer so leave i SCHED_TIME
27. TIMER 2 07 6 gt 7 07 5 T 07MS 7 GET INST IF KILL SERIAL 1 GOTO CHECK LT MEMORY SERIAL CHECK LT MEMORY _ _ 0 CHECK ADJUST LT VOLTS amp LT 97 RATIO GOTO CHECK 11MS CHECK GTZ BIT TIF LT GTZ 0 CHECK 11MS ADJUST LT VOLTS amp LT RATIO TABLE IF T 11MS TIMER 11 GOTO CHECK 12MS T 11 5 T 11 5 11 IF SERIAL POINTER MAX PHASE CURRENT TEST ST INSTALLED I CONVERSION ST TEST ST INSTALLED LEAR ST PEAK CLEAR ST PEAK CHECK 12MS CHECK 13MS CHECK GF ISQ IF ST PU 0 CLEAR ST ELSE IF SC RESTRAINT BIT IN 0 ELSE IF SW POS lt 6 GOTO CLEAR 57 ELSE ST 150 CHECK ST 12MS IF T 12MS 12 GOTO CHECK 13MS T 12MS T 12MS 12 IF LT GTZ 0 13 5 ELSE IF PU BIT 1 CHECK 13MS LT DEC ACCUM 0 13MS lt 13 CHECK 17MS T 13MS T 13MS 13 RESET GF 0 GOTO CHECK GF 150 GF_CURRENT 0 GOTO CHECK_64MS IF SERIAL POINTER amp GF CURRENT DO GF SERIAL CONV GOTO TEST FOR GF PU BIT SERIAL CONV 5 136 458 43 44 DO GF USE XS 0 5 FOR GF
28. a mechanism which causes a set of circuit breaker contacts to release thereby breaking the circuit path Many simple trip systems also employ a slower re sponding bi metallic strip which is useful for detecting a more subtle overload fault This is because the extent of the strip s deflection represents an accurate thermal history of the circuit breaker and therefore even slight current overloads Generally the heat generated by the current overload will cause the bi metallic strip to de flect into the tripping mechanism to break the circuit path The tripping systems described above are generally adequate for many simple circuit breaker applications but there has been an increasing demand for a more intelligent and precise iripping system For example many businesses today use expensive 3 phase power equipment which provides critical functions to the busi ness and its customers Due to the cost of the equipment and the functions that the equipment provides the power supplied to the equipment must be precisely measured and controlled For this reason processor based tripping systems have been developed to attempt to provide programmable control to the equipment operator user A major problem in the design of processor based tripping systems has been to accurately and reliably measure the power provided to the equipment On the other hand small size and low cost are also desirable characteristics for the tripping sys
29. z FOR PEAK OF 12 mSEC SCRIN_CODE LESS THAN PREVIOUS PEAKS BRANCH ST PEAK IS GREATER SO SAVE MAX 503 new peak phase so clear MAX IDENT combine max phase with comm location MAX IDENT save back to comm buffer controls SC restraint bit in comm buffer REGSTART get start of onboard registers 5 136 458 61 62 SC RESTRAINT BIT IS HIGH THERE IS NO SC RESTRAINT COMING IN BRSET PORTA X SC RESTRAINT BIT IN CLR SCRINBIT BSET OVPU_SCRIN 40 is low we have restraint JMP RETURN TO CALLER go return CLR_SCRINBIT EQU BCLR OVPU_SCRIN 40 SC restraint so clear bit amp chk ST RETURN TO CALLER EQU 5 RTS return to main motor PPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPP CALLED Relies on PE BRKR BIT and NO ST BIT to be set correctly RETURNS INST TABLE VAL points to table location of INST PU INST SWITCH holds value of INSTPU switch INST OFF bit is set cleared depending on ST amp INST switch pos INST switch value in serial comm buffer for transmission 36 Se 44 USES All registers except IY Uses TEMP RAM location to pass row value through routine No used registers are restored v fe de se de e de fe e de de e e e fe e fe e e e fe e e de le e e e fe de e e fe e e e e fe de de de ie e de e e e e e e e e ie e e e e ede ee je ye T ta e GET
30. 1005 AND 10005 DIGITS ARE 0 SUPRESS CHARACTER GJMP 4 10005 DIGIT FOR SUPRESSION SKAEI OAH GJMP CTI GJMP CT2 TEA 181 XADR BCD3 SAVE HUNDREDS DIGIT n COUNT VALUE ZERO 5 136 458 182 TENS RC RESET CARRY LHL POINTTO VALUE TO BE CONVERTED LOW BYTE LSN LAI BE ADDED FOR 10 TO LOW BYTE LSN ACSC VALUES NOP LHL POINT TO TEMP STORAGE FOR CONVERTED VALUE ST STORE CONVERTED VALUE LHLI 872 POINTTO VALUE TO BE CONVERTED LOW BYTE MSN LAI BE ADDED FOR 10 LOW BYTE MSN ACSC ADD VALUES NOP LHL TEMP2 POINT TO TEMP STORAGE FOR CONVERTED VALUE ST STORE CONVERTED VALUE a 813 POINTTO VALUE TO CONVERTED HIGH BYTE LSN LAI OFH VALUE TO BE ADDED FOR 10 TO HIGH BYTE LSN ACSC ADD VALUES NOP LHLI POINT TO TEMP STORAGE FOR CONVERTED VALUE ST TEMP STORE CONVERTED VALUE m 0 POINTTO VALUE TO BE CONVERTED HIGH BYTE LSN LAI OFH VALUE TO BE ADDED FOR 10 TO HIGH BYTE LSN ACSC ADD VALUES GJMP CONES CALCULATE HUNDREDS VALUE GETCON GJMP TENS REMAINING LOW NIBBLE OF VALUE IS EQUAL TO ONES DIGIT CONES TEA TENS SKAEI OOH 105 AND 1005 DIGITS ARE 0 SUPRESS CHARACTER GJMP LADR BCD3 TEST 1005 DIGIT FOR SUPRESSION SKAEI OAH GJMP GJMP CC2 1 CO2 XADR BCD2 5 TENS DIGIT X
31. 64 HAS PHASE MS TIMER EXPIRED YET BLO TEST PHASEA 2MS GO SEE IF 2 MS HAVE EXPIRED SINCE A PEASE PMS SUBA 464 reset the timer STAA T PEASEA RMS save the reset timer BSET FLAGS PHASE CONV ido conv so set FLAG LDX RMS SUMSQH 1 location of the SUM 2 FOR CHAN 1 JSR AVG AVERAGE I 2 VALUE CHAN 1 LDD RMS SQROOT 250 ROOT FROM AVG ROUTINE STD PHASA SQRT LAST 64 MS SQ ROOT OF CURRENT FOR CHAN 1 JMP TEST_64MS CONTINUE MAIN EXEC LOOP TEST_PHASEA 2MS EQU 5 HAS 2 MS EXPIRED YET 8 HAS PHASE MS TIMER EXPIRED YET BLO TEST PHASEB SEE IF TIME TO DO PHASE B RMS BRCLR LT FLAGS A PHASE CONV TEST PHASEB IF A PHASE CONVERSION FLAG IS SET DO SERIAL CONVERSION BCLR LT FLAGS A PHASE CONV CONV DONE SO CLEAR FLAG LDX SQRT GET STORAGE LOCATION FOR A PHASE RMS VALUE JSR PHASE UNBALENCE UNBALENCE FOR DISPLAY LSRB convert to 1 value for serial comm STAB PHASEA UNBAL STORE TO DISPLAY BUFFER LDX SERIAL POINTER check to see if we are sending A phase curren CPX PHASE RMS BNE SERIAL CONV ok to convert JMP TEST 64MS GO CHECK FOR 64 mS DO SERIAL CONV EQU 5 SORT a phase square root location IDX PHASE RMS storage location JSR I _ CONVERSION go do transmit conversion amp storage BCLR 5 CONV DONE SO CLEAR FLAG JMP TEST 64MS 7GO CHECK FOR 64 mS TEST PHASEB EQU 5 T
32. DO_SC_TRIP to finish setting up historic data before jimping to GLOBAL TRIP RETURNS Jumps to GLOBAL TRIP with historic data locations read stored to EEPROM T USED RESTORED NOTHING TRIPS BREAKER de dt fe dc dee eoe dee e ee e e e eee ede e de oe eee e e e ee qe ye e e ede de e ee de e e e e e ee e de e e e e e e e dc dede de ST TRIP SEI NO MORE INTERUUPTS PLEASE THIS SECTION CONTAINS TRIP CODE FOR SHORT TIME exea COMMON ST EQU BCLR SC_PU_GF_PU 07 1 SC PU bits to set phase s gt PU 57_ POS saved table position LDD 0 pick up value in double CPD PHASEX6 to A phase for comm bits BHI TEST NEXT PHASE if PU gt value try next phase BSET 5 PU GF 501 SET PHASE SC BIT TEST NEXT PHASE EQU 5 PHASEX6 to B phase for comm bits BHI TEST C PHASE NEXT if PU value try next phase BSET SC PU GF PU 502 5 B PHASE SC TEST C PHASE NEXT EQU 5 m T PHASEX6 to C phase for comm bits BHI SC TRIP if PU gt value try next phase BSET 5 PU GF 0 504 C PHASE SC BIT INST LRC TRIP USE COMMON CODE FROM THIS POINT ON xereeeenee DO SC TRIP EQU g JSR COP reset the softdog keep it happy LDX REGSTART BCLR TRIP_STATUS_BYTE 70 CLEAR TRIP CAUSE BSET STATUS 520 SET CA
33. IX RESTORED NOTHING Se Sa Se ve Sa a Se COMMENTS THE CALLING ROUTINE IS RESPONSIBLE TO MAKE SURE THE SCI REGISTER IS CLEAR BEFORE CALLING THIS ROUTINE TDRE in SCSR is set P dms dws styr This routine automatically runs through transmit buffer and sends out according to the serial comm spec Data is sent out SPI SCI ports Data is sent out in 8 byte packets Data transmission is in groups of rotating packets packet 0 1 2 0 1 3 0 1 4 0 1 5 0 1 6 0 1 7 5 Se Se se Sa Sa Se Se a Se a Se Se Se Sy 5e Se Se Initial section checks byte pointer for byte 0 6 or 7 exception bytes Byte 0 is always trip status byte amp packet Byte 6 is the trip unit address upward compatability Byte 7 is always the checksum of the previous bytes Bytes 1 thru 5 are trip unit data see serial comm spec for details Se SERIAL LDX SERIAL BUF pointer for serial buffer LDAB BYTE PTR pointer for byte to send BEQ SEND STATUS BYTE if byte 0 send status byte CMPB 06 zif byte 6 send address BEQ SEND ADDRESS address right before check sum LINDA SUE send checksum and go to next packet This section picks the correct byte from the correct packet saves the pointer to check for word wide conversion conflicts and masks the high bit of the byte being sent bytes 1 5 ce ve LDAB PACKET set to packet 0 LDAA 45
34. MUL multiply low byte by low byte ADDD RMS SUMSQ 1 double to low 16 bits STD RMS SUMSQ 1 save it BCC HI WORD OK IDX 5 SUMSQH 1 if carry set increment INX the high byte STX 5 SUMSQH 1 save it HI WORD OK EQU 5 LDAA CUR_PHASEA 1 low byte LDAB CUR PHASEA _ get high byte for 0 check SQUARE DONE 1 high byte 0 we s done result is shifted to multiply by 2 same as 2 multiblies add PE ADDD RMS SUMSQH 1 1 add low high to middle 16 bits STD RMS SUMSQH 1 1 sand save BCC LAST ADD INC RMS SUMSQH 1 Carry was set increment the high byte 5 136 458 125 126 LAST A ADD EQU 5 LDAA CUR PHASEA get high byte 1 500 DONE 1 0 we re finished TAB move to ACCB MUL multiply for last value ADDD RMS SUMSQH 1 add to high 16 bits STD RMS SUMSQH 1 store back to accumulator I SQUARE DONE EQU AT THIS POINT A PHASE 172 SUMMATION IS FINISHED AND B PHASE IS STARTED LDAB ADR2 REGSTART GET PHASE B HIGH GAIN A D STAB HI PHASEB save value for check in trip routine CMPB 6 BLS USE HI PHASEB 1 USE LOW GAIN PHASEB SQUARE ADD TO THE SUM OF PHASEB SQUARES LDAA PHASEB LDAB 6 MUL STD PHASEB DO PHASEB SUMMATION igo do 172 summation USE HI PHASEB EQU 5 CLR PHASEB STAB CUR 1 DO PHASEB SUMMATION EQU THIS POINT EITHER LOW OR HIGH GAIN
35. RE INIT EQU JMP INITIALIZE no current flowing so reinitialize the TU 5 136 458 dede de ode de de ede de ede ge ee de de dede de de FRR I I TTI III ROUTINE TO CHECK VT LINE BEFORE TRIPPING Called with IY set for delay 1 pass equals 7uSec e de fe e t e e fe e ide e e e e e de e e e e e c e e e e e oe e se de e e e e e oe e oie e e e c e e e c e e e e c e e je le n c n e e e e e de e dee e x VT CHECK EQU LDX TRIP_SUPPLY IS_CAP_CHARGED EQU BRCLR 0 X TRIP_VOLTS_OK 7 if low voltage decrement amp try BRA GLOBAL JUMP return amp trip get trip supply location RECHECK CAP EQU 5 DEY 4 IS CAP CHARGED 3 check cap voltage again GLOBAL JUMP EQU 5 LDX REGSTART BSET UMP GLOBAL TRIP start of registers TRIP BREAKER ee e ee fe e ide e eode de e ee e de de ee L N G T I M E de fe fe de de fe e e ede defe fece dei e nx THIS SUB ROUTINE IS CALLED EVERY 64 MS BY THE EXEC IF PEAK SQRT IS ABOVE PICK UP TABLE VALUE PEAK SQUARE IS ADDED TO LT ACCUM IT COMPARES THE LT ACCUM TO THE TRIP ACCUMULATION TABLE VALUE IF THE LT ACCUM IS TABLE A TRIP SEQUENCE IS EXEXCUTED CALLED When all 3 phase RMS values have been computed Se Se v ve ve ve 5 S
36. result 16 temp2 rms sqroot get 2nd result remainder temp2 rms sqroot get 2nd remainder temp3 remainder 16 get next dividend result result 16 temp3 rms sqroot final result remainder temp3 rms sqroot final remainder remainder 2 double the remainder if remainder gt rms sqroot if remainder gt 5 increment result result result rms sqroct 2 find next guess temp rt rms sqroot temporary storage 2 SQRCAL 107 rms sqroot result put result into rms sqroot for next while remainder gt 1 5 136 458 108 iteration remainder abs result temp rt find guess amp iteration difference end of do while loop iterations are 1 end of average square root routine e End of simulation of square root routine dde dede dede dede XGDX LSRB ADDD XGDX LSLD 0 X CONT AVG 2 X 57 get high word for 0 check if not 0 continue get low word amp check for 0 low 7 bits get masked off so 57 0 if gt 57 do square root 0 for result store 0 for result shift low byte for carry mult by 2 rotate next byte for carry rotate to pull in carry rotate to get carry bit change word boundary to drop lowest byte store into mean variable location get high byte of a
37. row entry sACCD row offset for brkr amp sensor table location move to IX AT THIS POINT IX POINTS TO THE CORRECT ROW OF THE CORRECT 172 IN DELAY TABLE LDAB ANDB SUBB LSLB ABX GFDELSW SW POS 508 get the del switch setting mask off bit 0 amp high nibble align for GF 1 2 table values are 4 bytes so shift left 2x location to row pointer ACCX now holds the location of the 1721 trip value s x CHECK FOR GFTRIP EQU LDY JSR CMPA BGE RTS pode Ree USED 54 4 Se 4 Se 4 se 5e EQU SEI JSR BCLR BSET BSET LDAA ANDA BHS INC JMP 5 GF_ACCUM COMP_DBL_WORD 00 GF_TRIP get accumulator location go compare accumulator to trip value compare if positive trip return from routine G R 1 1 T T R I P tfe fe e e fe e e e e e de e e e e de CALLED From any Ground Fault routines that are allowed to generate a Ground Fault trip ACCA amp IX 5 RESET COP TRIP STATUS BYTE 70 TRIP STATUS BYTE 40 MAX IDENT 503 GF TRIP CNT 63 63 CLR GF CNT GF TRIP CNT G GLBAL GF TRIP CNT 5 amp REGSTART RES OUT PORTA X RETURNS Doesn t trips the breaker RESTORES NOTHING e e ie de t e de e e ee e e e e Ye e e e e ee e e de je e e e e eee de e eee eoe e de de dede de
38. straint in restraint out electrical distribution systems reference may be made to U S Pat No 4 706 155 to Durivage et al Other circuits are used along with the above circuits to provide reliability and integrity to the tripping sys tem 100 For instance the microcomputer 120 utilizes the analog input circuit 108 along with a gain circuit 134 to measure precisely the RMS Root Mean Squared current on each phase of the lines 106 The accuracy of 50 55 60 65 4 this measurement is maintained even in presence of non linear loads The analog input circuit 108 develops phase signals and C that are representative of the current lines 106 The gain circuit 134 amplifies each phase signal A B and C through respective dual gain sec tions from which the microcomputer 120 measures each amplified signal using its A D circuitry By pro viding two gain stages for each signal A B and C the microcomputer 120 can immediately perform a high gain or low gain measurement for each current phase depending on the resolution needed at any given time The analog input circuit 108 is also utilized to provide a reliable power source to the tripping system 100 Using current developed from the lines 106 the analog input circuit 108 operates with a power supply 122 to provide three power signals VT 9 v and 5 v to the tripping system 100 The power signal VT is moni tored by the microcomputer 120 through deco
39. 2 swith ST on INST table moves up 1 value JMP FINISH TABLE POINTER has correct position so finish INST IS OFF BRSET INST FLAGS I TIMR BIT FINISH TABLE POINTER if INST active don t CLR INST CNTR 4 clear INST PU counter LDAA 2 100 INST timer reset value STAA INST TIMER reset the INST timer BCLR INST FLAGS INST PU correct flag bits INST FLAGS INST OFF 1 INST is off so set bit ABX switch pos 8 so set to max STX INST TABLE VAL store trip value JMP INST HOMEWORK DONE all done so leave FINISH TABLE POINTER EQU 5 LDX TEMP get row value ABX column position to row STX INST TABLE VAL znow points to INST PU value BCLR INST FLAGS INST OFF BIT be sure INST is on INST HOMEWORK DONE EQU RTS 60 BACK TO MAIN SIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIITIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII STTTTT Se Se ve 4 4 63 5 136 458 64 THIS SUBROUTINE READS PU SWITCHES AND DETERMINES TYPE OF TRIP UNIT ACCA amp ACCB are used in this routine and not restored CALLED Without any preset conditions Reads ST amp GF pickup and delay switches RETURNS Serial communications buffers set for switch positions If ST or GF is not installed that bit is set RP OPTIONS for communications SET TYPE OF TRIP UNIT EQU ALLOW OFF WE HAVE ST NO ST WE HAVE GF NO GF
40. 240736 57 206 42436 1564727 47 23 0 68 45 4686 07 245422 64 175 30625 1595352 48 23 5 53 58 2871 12 248293 76 137 18769 1614121 49 24 0 36 81 1355 17 249648 93 94 8836 1622957 50 24 5 18 74 351 12 250000 05 48 2304 1625261 MEAN OF THE SUM 5000 00103 MEAN OF THE SUM 32505 MATION MATION CALC RMS VALUE 70 7106854 CALC RMS VALUE 180 Amps Binary ACTUAL RMS 70 7106781 ACTUAL RMS 180 312229 VALUE VALUE APPENDIX A H t e e e ee e ie e e je e e efe e e e e e e e e e ee e e e e he e e e e e e e e ee e e e e de e de e de de fe e e e e e dee ie e e dede eje SERIES THREE TRIP SYSTEM fk fee e ee e e ee de hc e e je eee de e e dee e e e c e e e se c e e e e e e e dee e Y o ee de e He Fe We TITLE DATA pere Memory Map for SERIES III BOARD exse RAM START RAM END REGSTART RATING PLUG TRIP SUPPLY LTPUSW LTDELSW FLCPUSW FLCDELSW STPUSW STDELSW LRCPUSW LRCDELSW INPUSW PUPUSW GFPUSW GFDELSW SENSOR BRKR TYPE EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL 0000 00FF 1000 2000 2001 4000 4001 4000 4001 4002 4003 4002 4003 4004 4005 4006 4007 8000 58001 END OF MEMORY de de dee de eder Start of 256 bytes of RAM end of 256 byte RAM memory Start
41. 30 3 0 1 CALC LT ACCUM EQU LDAB LTDELSW read the delay switch ANDB SW POS mask off invalid ABX to index JSR READ BREAKER SW find if brkr SE or PB CMPB 4508 70A SE BLS READ RATIO index correct so read ratio LDAB 16 get offset for next row ABX it to index READ RATIO 1 X REGISTER IS NOW POINTING TO THE PROPER TABLE POSITION LDY MEM RATIO Y points to A D MEM DELAY CAP VALUE JSR MUL 16X16 7GO FIGURE MEM DELAY DIGITAL VALUE mem ratio drops the least significant byte so adjust the result one byte to the left multiply by SFF LoD RESULT 1 GET LOW BYTE HIGH WORD STD RESULT STORE TO HIGH BYTE HIGH WORD LDD RESULT 3 LOW BYTE LOW WORD EXTRA BYTE STD RESULT 2 STORE TO LOW WORD DATA HAS BEEN SHIFTED LDAB RATIO 1 get memory ratio LDAA 4564 get 100 into ACCA MUL multiply for percent 5 LT MEM RATIO store byte for transmission 5 Gk deed d o UNBALANCE d de de de geo eR eR e THIS SUBROUTINE CALCULATES PHASE UNBALANCE FOR ANY OF THE THREE PHASES CALLED IX points to phase of unbalance wanted RETURNS ACCB holds percent of unbalance 2 used for 5 precision USED ACCA ACCB IX TEMP USED Se Sa Se Se 5e Seo 5e Yen Se 54 54 gt e Se gt e 5e 5 136 458 75 76 111 01 ors USLED 0 000 ee ee 666 4
42. 342 which allows the battery 338 to provide power at Vcc so long as a diode 344 is forward biased diode 344 is forward biased whenever the second condition is also present Thus when the output voltage level of the 5 V power supply is less than the voltage level from the battery 338 the diode 344 is forward biased and the battery 338 provides power to the local display 150 In addition the diode 344 is forward biased until a switch 346 activated by a power up circuit 348 allows the 5 V signal to provide power at Vcc The power up circuit 348 activates the electronic switch 346 only after resetting the display processor 316 The pow er up circuit 348 for example is part No ICL7665 working in connection with resistors 349 351 and 353 having values of 620 K ohms 300 K ohms and 10 meg ohms respectively Power is provided from only to latch 320 the LCD driver 326 the LCD driver 330 and the oscil lator circuit 328 The LCD driver 330 and the oscillator circuit 328 receive power from either the battery 338 or the 5 V power supply output via diodes 350 and 352 This arrangement minimizes current drain from the 5 136 458 20 25 30 battery 338 while allowing the user to view the status of 35 the tripping system 100 during any power fault situa tion 9 Power cannot drawn from the battery 338 unless the battery 338 is interconnected with the remaining portion of the tripping system via conn
43. 5 data bytes packet MUL get packet base ADDB BYTE PTR pointer to correct byte ABX zadd to serial buffer base STX SERIAL POINTER store for compare for 2 byte values INC BYTE set for next byte LDAA 0 put byte in ANDA 57 mask off high bit JMP DO CHECKSUM 290 do checksum before transmission SEND STATUS BYTE EQU up status byte here and start of checksum generation BCLR TRIP STATUS BYTE SOF packet in status LDAB PACKET packet being sent ORAB TRIP STATUS BYTE correct status bits 5 136 458 115 116 STAB TRIP STATUS BYTE store back to location BSET TRIP STATUS BYTE 80 set high bit to indicate byte 0 LDAA 0 status byte INC BYTE point to next byte CLR CHECK SUM new packet clear checksum JMP DO CHECKSUM start checksum SEND_ADDRESS EQU 5 not used in present series3 communications INC BYTE_PTR set for next byte LDAA ADDRESS 1 the address into ANDA 57 off high bit JMP DO CHECKSUM 240 do checksum before transmission LINDA SUE EQU Clears byte and serial pointers checks for packet pointer increment and if tripping locks at packet 2 Does housekeeping for pointers CLR BYTE PTR new packet so clear byte pointer CLR SERIAL POINTER 1 clear pointer to 0 before checksum LDAA PACKET PTR get packet pointer BEQ PACKET 0 so increment to 1
44. 54 75 73 21 22 51 52 58 56 UA US005136458A United States Patent 19 11 Patent Number 5 136 458 Durivage III 45 Date of Patent Aug 4 1992 MICROCOMPUTER BASED ELECTRONIC 4 794 484 12 1988 Matsko et al 361 93 TRIP SYSTEM FOR CIRCUIT BREAKERS 4 803 635 2 1989 Andow 364 483 4 833 564 5 1989 Pardue et al 361 93 Inventor Leon W Durivage III Marion Iowa 4 853 819 8 1989 Suwa et al 361 96 Assignee Square D Company Palatine Ill FOREIGN PATENT DOCUMENTS Appl 403 506 2400084 8 1974 Fed Rep of Germany 361 94 EN 0169152 3 1922 United Kingdom 361 94 Filed Aug 31 1989 0387476 2 1933 United Kingdom 361 93 UNG CU oeste s H02H 3 26 US o 361 93 364 481 CHER PUBLICATIONS 364 483 Schmeatic of test circuit of Square D no date Field of Search 361 93 94 96 54 General Electric Publication GEH 4291 364 481 483 Primary Examiner Steven L Stephan References Cited Assistant Examiner Thomas M Dougherty U S PATENT DOCUMENTS Attorney Agent o or Firm Jose W Jimenez Robert J Crawford 4 096 539 6 1978 Scaturro 361 93 4 121 269 10 1978 Hobson 361 44 57 ABSTRACT 4 208 693 6 1980 Dickens et al 361 94 Drocessor based tripping system uses a precise three 4 331 997 5 1982 Engel et al 361 93 4
45. CAUSE OF TRIP amp PACKET 2 STAA TRIP STATUS BYTE SAVE TO TRIP CAUSE LOCATION 131 LDAA SOFT TRIP ANDA 63 63 CLRiSF INC SOFT TRIP JMP TRIP CLR SF CNT EQU CLR SOFT_TRIP_CNT GO_TRIP EQU T LDX REGSTART CLR PORTA X BCLR TRIP CNT 40 BCLR TRIP CNT 40 BCLR SC TRIP CNT 40 BCLR GF TRIP 40 BSET SOFT TRIP CNT 40 JMP GLOBAL TRIP timer 5 136 458 132 get of trips max trips to store of trips clear count increment of SC TRIPS 7if high bit clear leave else clear soft trips start of onboard regs wait for watchdog trip cause of trip long time cause of trip phase unbal cause of trip short circuit cause of trip fault cause of trip soft dog igo to global trip amp wait for watch dog DECREMENT ROUTINE x xx Ie Ie We Fe Fe Fe Ie Ie Fe Me We e Ie Me Me Ie FE Ke e E Te Ke CALLED From the one second timer whenever there active scftdog RETURNS Clears any errors that have timed out If no remaining errors exist resets the error counter USED ACCB RESTORED NOTHING zs qe coe e e ge de e e e de e fe de e de e e de de de fe fe dee e e de e de e e e e e de e e e e ic e sie e e Pe e e e e e e e de e eee DEC SOFT DOG EQU 5 LDX SOFT_DOG_TIMERL get timer value DEX decrement
46. HAS BEEN STORED TO CUR PHASEB FOR USE TBA move low byte to ACCA for 0 check BEQ LAST B ADD multiply low byte by low byte ADDD RMS SUMSQ 2 add double to low 16 bits STD RMS SUMSQ 2 save it BCC HI WORD B OK LDX RMS SUMSQH 2 if carry set increment INX the high byte STX RMS SUMSQH 2 and save WORD B OK EQU 5 LDAA 1 low byte LDAB CUR PHASEB get high byte for 0 check BEQ SQUARE DONE if high byte 0 we s done MUL LSLD result is shifted to multiply by 2 same as 2 multiplies amp an add ADDD RMS SUMSQH 2 1 add low high to middle 16 bits STD RMS SUMSQH 2 1 and save it LAST B ADD INC RMS 50 5 2 Carry was set increment the high byte LAST B ADD EQU LDAA CUR_PHASEB high byte BEQ I SQUARE DONE if 0 we re finished TAB move to ACCB MUL multiply for last value ADDD 5 SUMSQH 2 add to high 16 bits STD SUMSQH 2 store back to accumulator I SQUARE DONE EQU 5 AT THIS POINT B PHASE I 2 SUMMATION IS FINISHED AND C PHASE IS STARTED LDAB ADR3 REGSTART PHASE C HIGH GAIN A D STAB HI PHASEC save value for check in trip routine CMPB 6 BLS USE PHASEC USE LOW GAIN PHASEC SQUARE IT AND ADD IT TO THE PHASEC SQUARE SUM LDAA 1 PHASEC LDAB 6 STD CUR PHASEC JMP DO_PHASEC SUMMATION do I 2 summation USE HI PHASEC 5 CLR PHASEC STAB 1 DO PHA
47. INTERRUPT ENABLE REGISTER ALL ENABLED XADR TCNT 0 RESET SOFTDOG TIMER GJMP INIT JUMP TO MEMORY INITALIZATION Re amp amp amp 8 amp 88 8 8 8 8 8 8 88 8 B8 toto B B B c B B BB B BR 55885588858 TISR SOFTDOG TIMER INTERRUPT ROUTINE amp amp EE KEKE KKK RRR ERE EKER RRR EK KKK RR EKER RRR RRR ERK TISR XADR ACCTMP RC LHL LAI 03H ACSC GJMP TS GJMP RESET 75 ST XADR ACCTMP RT BB EEE 8 8 88 8 8 EK KG RRR TORRA RARA B B B B B8 B KEKE ER R AAA amp ROM LOOKUP ROUTINE FOR BREAKER AMP RATING ENTER amp amp ORG 80H DB 020 065 OBFH OBOH OE2H 035H 078H 40H D83H DB 008H 000H 0 0 DB 4 05H 05H 05H 06H 06H 06H 07H 07H 5 136 458 149 150 amp amp CALCULATE BREAKER AMP RATING USING LONG TIME MULTILIER amp 288 8 8 8 8 88 8 8 8 8 8 KE SEK 8 8 B8 8 RE KEKE KE KEK KEKE 8 8 8 Rc THE LONG TIME OR FULL LOAD SWITCH VALUE BRAT LHL LTEMPL POINT TO LONG TIME SWITCH TEMP MEM LOCATION LADR x PACKET NUMBER SC SKABT O CHECK FOR MOTOR PROTECT TU RC NOT MOTOR PROTECT TU RESET CARRY LADR LTS ACC LONG
48. Keystone PTC Resettable Fuse part No RL3510 110 120 PTF The test winding 550 eliminates the need for a separate test transformer which has been utilized by systems in the prior art The operation of the ground fault sensing toroid 508 is best understood by considering the operation of the tripping system with a ground fault and without a ground fault In a balanced three phase system without a ground fault the current magnitude in each phase is equal but 120 degrees out of phase with the other pha ses and no neutral current exists thus the output wind ing 509 produces no current As the current through any phase A B or C increases the current in the neu tral path is vectorially equal in magnitude but opposite in direction to the increase in phase current and the magnetic summation is still zero When a ground fault is present current flows through an inadvertent path to an earth grounded object by passing the neutral trans former 506 and creating a current signal in the trans former 509 Thus the transformer 509 produces a cur rent signal only when a ground fault is present The current signal from the output transformer 509 of the ground fault sensing toroid 508 is routed through the rectifier bridge 522 the power supply 122 and re turned through the burden resistor arrangement 530 The burden resistor arrangement 530 and the rectifier bridge 522 convert that current signal into an A C rectified signal 558 that is inve
49. LDX ACCUM X TO ADDRESS OF LT ACCUM JSR SUB 2 16 DEC LT ACCUM BY 2 16 RTS ALL DONE RETURN TO EXEC LT_GT_22SECS EQU 1 SUBTRACT 2 19 FROM LT ACCUM 100 ACCUM LOAD HI WORD LT ACCUM 5 136 458 85 86 1560 DIVIDE BY 2 LSRD DIVIDE BY 4 LSRD DIVIDE BY 2 2 19 STD TEMP SAVE 2 16 IN TEMP LDD 2 get LT ACCUM SUBD TEMP psubtract LTA 2 19 STD 2 TO LT ACCUM DONE SUBT no carry needed so done LDX ACCUM SET X BACK TO LT ACCUM DEX STX LT ACCUM SET X BACK TO LT ACCUM DONE W SUBT RTS e e le e he e e de ede de sic e dee n SUB 2 16 SUBROUTINE SUBTRACTS 2 16 FROM ANY 4 BYTE ACCUM POINTED TO BY SUB 2 16 EQU LDD 2 X GET LOW WORD OF 4 BYTE ACCUM SUBD 0 X SUBTRACT HI WORD OF 4 BYTE ACCUM STD 2 X STORE LOW WORD OF 4 BYTE ACCUM BCC SUB RETRN 1F CARRY CLEAR ALL DONE LDD 0 GET HI WORD OF 4 BYTE ACCUM SUBD 1 SUBTRACT CARRY STD 0 X 5 HI WORD OF 4 BYTE ACCUM SUB RETRN EQU RTS MMR KEE END OF LONG TIME ACCUMULATOR DECREMENT sedes esee ARX E DWRXWRNANTERWERME FIND SQRT PK t se e e ie e e de de e e e ee ede ede dn dde d
50. MIDDLE NIBBLE RATING LOW NIBBLE CHECKSUM 4 NUMBER OF TEN PERCENT OF BREAKER RATING 32H INTERRUPT ROUTINE ACCUMULATOR STORAGE VERY MSN FOR 10X CALC HIGH BYTE MSN HIGH BYTE LSN BYTE MSN BYTE LSN TRIP UNIT OPTIONS PACKET NUMBER sEIGHT VALUE MEMORY LOCATION TEMPORARY BINARY VALUE BINARY VALUE TEMPORARY BINARY VALUE TEMPORARY BINARY VALUE BINARY VALUE MODULO LOW NIBBLE FOR TIMER SENSOR LOOKUP ID RATING PLUG LOOKUP ID NIBBLE NIBBLE NIBBLE NIBBLE NIBBLE TIME SWITCH SETTING 61H TIME SWITCH STORAGE HIGH NIBBLE iONG TIME SWITCH STORAGE LOW NIBBLE 5 136 458 193 I claim 1 A tripping system for interrupting a three phase current path having a ground path coincident there with comprising a set of current sensors each situated adjacent the current path for sensing a respective phase of cur rent therein and each providing a respective cur rent signal therefrom summation means coupled to the set of current sen sors for adding the current signals from the set of current sensors and for producing an output cur rent signal therefrom in the presence of a ground fault a set of gain circuits each responsive to a respective one of the current signals and each having a first gain section for amplifying the respective current signal by a first predetermi
51. PHASE RMS GCTO ELSE I CONVERSION PHASB SQRT B PHASE _R Bj PHASE CONV 0 GOTO TEST 64MS IF T PHASEC RMS 64 GOTO TEST PHASEC 2MS 45 Ta Se ve 49 Se ve ve TEST PHASEC 2MS TEST 64 5 4 TEST_ 64MS ELSE CHECK 25075 ELSE i i CRECE 1 5 ELSE CHECK TIMR Q Se Se gt e Sa Se Se Se Se Se Se 3e Se Se 5e Se Se Se Se Se Se s si Se Se So Sa Se Se 5e 5e Se Ve Se Se Se Sa Se Se Se Se Ye Se Se Se Se Se Se 5e Se Se gt e gt e E MAIN FLOW EW 5 555555555555555555555 MA I OF 5 136 458 C_PHASE CONV 1 T PHASEC RMS AVG RMS SUMSQH 3 PHASEC SQRT RMS SQROOT GOTO TEST 64MS ELSE T 64MS T 64MS 64 LT SERIAL BITS FIND SQRT PK LONG T PHASEC RMS 64 IF T PHASEC RMS 8 TEST 64MS ELSE IF C PHASE CONV 0 TEST 64 5 PHASE UNBALENCE PHASC SQRT IF SERIAL POINTER PHASE RMS 6070 ELSE I CONVERSION PHASC SQRT C PHASE PHASE CONV 0 IF T 64MS lt 64 GOTO CHECK 250 5 250 MS TIMER lt 250 CHECK 1 SEC T 250MS T 250MS 250 1000 5 KILL SERIAL BIT 0 CHECK _ LED SET TYPE _ OF TRIP UNIT GOTO CHECK TIMR 0 1000MS lt 4 CHECK 0 T 1000MS T 1000MS 4 SENSOR BREAKR IF SOFT DOG_CNTR RESET GOTO CHECK
52. PHASEB RMS GET B PHASE TIMER CMPA 64 HAS PHASE B MS TIMER EXPIRED YET BLO TEST PHASEB 2MS GO SEE IF 2 MS HAVE EXPIRED 50 64 STAA PHASEB RMS CLEAR THE TIMER E LDX RMS SUMSQH 2 location of squared SUM FOR CHAN 2 JSR AVERAGE I 2 VALUE 2 LDD RMS SQROOT gt 250 ROOT FROM AVG ROUTINE STD PHASB SQRT LAST 64 MS SQ ROOT OF I FOR CHAN 2 BSET FLAGS B PHASE CONV CONV DONE SO CLEAR FLAG JMP TEST 64MS CONTINUE MAIN EXEC LOOP TEST PHASEB 2MS 8 2 5 PHASE B RMS TIMER EXPIRED YET BLO TEST PHASEC GO SEE IF TIME TO DO PHASE B RMS BRCLR LT FLAGS B PHASE CONV TEST PHASEC Conversion bit is set do serial comm and phase unbalance routines BCLR LT FLAGS B PHASE CONV CONV DONE SO CLEAR FLAG LDX PHASB SQRT PHASE B RMS VALUE LOCATION JSR PHASE UNBALENCE CALCULATE B PHASE UNBALANCE 5 136 458 55 56 LSRB convert to 1 value for serial comm STAB PHASEB UNBAL STORE PHASE UNBALANCE IDX SERIAL POINTER to see if are sending A phase curren CPX PHASE RMS BNE DO SERIAL CONV B ok to convert JMP TEST 64MS GO CHECK FOR 64 mS DO SERIAL CONV B EQU 5 gt LDY PHASB SORT get a phase square root location LOX PHASE RMS storage location JSR I CONVERSION go do transmit conversion amp storage BCLR FLAGS B PHASE CONV DONE SO CLEAR FLAG JMP TEST 64MS CHECK FOR 64 mS TEST PHASEC EQU 5 LDAA T P
53. RESET LOW GN 014 is larger so leave is STAB CUR GF new is larger so save it RESET TEE FOR THE LOW GAIN READ RESET LOW GN EQU 5 LDAA 534 GET VALUE TO SET A Ds FOR LOW GAIN AMPs STAA ADCTL REGSTART STORE TO ONBOARD TO DO CORRECT A Ds TEST FOR ONE MS TOGGLE FLAG TO DECREMENT ALL TIMERS TEST FOR 1MS EQU 5 BRSET IFLAGS ONE MSBIT ONE MILS IF lmSEC BIT SET DO 1 mSEC STUFF BSET IFLAGS ONE MSBIT SET 1 mSEC JMP DECREMENT TIMERS 7go do the Que timers ONE MILS EQU BCLR IFLAGS ONE_MSBIT WE ARE 1 mSEC SO CLEAR 1 mSEC BIT INCREMENT ALL POSITIVE MS TIMERS FROM SMALLEST TO LARGEST xx INC T_2MS_ST increment 2ms ST timer INC T_2MS GF increment 2ms GF timer INC T 07MS INCREMENT 17 mSEC TIMER INC T 11MS INCREMENT 11 mSEC TIMER INC T 12MS INCREMENT 12 mSEC TIMER INC T 13MS INCREMENT 13 mSEC TIMER INC T PHASEA RMS 7 INCREMENT PHASE RMS TIMER INC T RMS INCREMENT PHASE RMS TIMER INC PHASEC 5 INCREMENT PHASE C RMS TIMER INC T 64MS INCREMENT 64 mSEC TIMER INC 250MS 1 250 mSEC TIMER JMP STROBE WDOG leave interrupt e e e de de e e e e oe Pe de t e e he de deje je dde de ee d DECREMENT ALL QUEUED TIMERS DECREMENT Q TIMERS RETAIN ST TRY TO RESTRAIN YO EQU LDAA INST RESET TIMER get the timer BLE RETAIN ST if negative bit set it is asleep off if 0
54. RMB 2 x I E E B E E E E E E E M FLAGS ACCUMULATORS 6 TIMERS FOR FUNCTION USE texte IN GENERAL TIMERS USE 7 580 FOR THE SLEEP BIT xxx voee eoe BND THE VALUE SEF FOR THE RESET CONDITION deye iese veve deed CHECK ROUTINES FOR ACTUAL CONDITIONS INST TABLE VAL RMB INST RESET TIMER RMB storage for table pointer resets the inst timer to 100mS FLC FLAGS RMB 0 FLC pointer for flags LT FLAGS RMB 1 BITS USED FOR LT LOGIC FLC ACCUM RMB 0 pointer for FLC accumulator LT ACCUM RMB 4 24 BYTE I 2 ACCUM FOR LONG TIME ST FTIMER RMB 1 ST FIXED UNRESTRAINED DELAY AT 33 MS LRC ACCUM RMB 0 pointer for LRC accumulator ST ACCUM 4 SHORT TIME I 2 4 BYTE ACCUMULATOR MER ROU ST i RETN TIMER 1 Short time retention timer ST 12 OUT TIMER RMB 2 restrained ST delay timer SC RESTRN TIMER RMB 1 short circuit restraint timer LRC FLAGS RMB 0 high bits used for locked rotor logic ST FLAGS RMB 0 HIGH BITS USED FOR SHORT TIME LOGIC INST FLAGS RMB 1 LOW BITS USED FOR INSTANTANEOUS LOGIC INST_SWITCH RMB 1 storage for INST switch position 2 1 INST TIMER RMB i 2100 MS INSTANTANEOUS TIMER INST CNTR 4 RMB 1 INST COUNTER FOR 4 PU S IN ROW PU 5 RMB 0 HIGH BITS FOR PHASE UNBALANCE LOGIC FLAGS RMB 1 LOW
55. Se 4 4 Se so LDAB STPUSW ANDB SWITCH_MASK MAX SW 1 POS BLS WE HAVE If LRC in position 9 or 10 LRC is forced to on in position 1 2 e e e c e e de sic le ie e fe e c fe 1722 e de e e e e e e e e e e e ne e e de eic e je e e e fe de ie e e de dee ine STPU SWITCH VALUE MASK OFF BIT 0 CHECK FOR OFF POSITION IF lt 14 WE HAVE ST INSTALLED BRCLR RP OPTIONS MOTOR PROT BIT ALLOW OFF ANDB MAX SW_POS HAVE ST EQU mask high bit if switch is OK do LRC comm BSET FLAGSS NO ST SET FLAG TO SHOW ST NOT INSTALLED CLR ST SWITCHES JMP ST EQU LSRB LDAA STDELSW ANDA MAX_SW_POS LSLA LSLA ABA STAA ST SWITCHES no ST installed so clear switch values BSET OPTIONS NO_ST_BIT TO SHOW ST NOT INSTALLED branch around switch set code do shift to get PU in correct position get delay value mask off unused bits shift to bits 3 5 shift to bits 3 5 add to PU switch value store in xmit location BCLR FLAGSS NO ST CLEAR FLAG TO SHOW ST INSTALLED BCLR OPTIONS NO ST BIT CLEAR BIT TO SHOW ST INSTALLED LDAB GFPUSW ANDB SWITCH_MASK SW POS BLS WE HAVE SWITCH VALUE OFF BIT 0 CHECK FOR OFF POSITION
56. Se vo ve Se 4 ve 9 PPTTTITITTITTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTITTTTTTTTTTTTTTTTTTTTTTTTTTTTTT GF RETN TIMOUT EQU 0000 STD ACCUM HI WORD OF GF ACCUMULATER STD GF ACCUM 2 LOW WORD OF GF ACCUMULATER LDAA 33 34 MS GF FAST TIMER VALUE FTIMER 7 SET IN GF FAST TIMER CHECK FOR GROUND FAULT FIXED DELAY TIMER ACTIVE IF SO THEN CANCEL IT LDD 5 GET NULL VALUE STD GF LONG TIME RESET FIXED RSTRN DELAY STD GF RETIN TIME NULL RETENTION TIMER BCLR GF FLAGS DOUBLE I2 BIT don t double 172 calculations RIS I SQUARE MUL 16X16 5 136 458 103 104 2 GROUND FAULT ROUTINES se fe fe e de de fe e eee e Pe le e oe cie e e ee d d dew d e m eoe eoe de oe ee deed e MUT 16 16 cfe e or CALLED From long time accum calculation serial data conversicz routine amp locked rotor routines with IX and IY pointing to the memory location of the 16 bit multiplier and multiplicand RETURNS Result of the multiplication in 32 bit location called RESULT If called at I SQUARE the rout ne will do an 172 on the values 1 TEST FOR I SQUARE ADD RESULT MUL NEXT BYTE MUL LAST BYTE MUL RETURN PAGE a both amp IY must point to same
57. TIME SWITCH CALL 15 SWITCH VALUE XADR LTEMPH sLONG TIME SWITCH HIGH NIBBLE SET TEMP STORAGE LOCATIONS TO ZERO 0 BRL LOW TRIP CURRENT SETTING NIBBLE ST LHLI BRM MIDDLE TRIP CURRENT SETTING NIBBLE ST HIGH TRIP CURRENT SETTING NIBBLE GJMP TCS gaa aa nee cero ale ROM LOOKUP ROUTINE FOR BREAKER AMP RATING ENTER AT AMP1 ORG DB 0E2H 07EH 2 083H 0D6H 053H 023H 08CH DB DB 03 04 05 0 06 06H 07H 07H 08H OBH 08H O9H AMP1 RT ADD COMPLEMENTED LTS VALUE TO AMP RATING TO CALCULATE BREAKER LT CURRENT TCS ST 5 DATA RC TEMPI POINT TO AMP LOW NIBBLE LADR LTEMPL ACC COMPLEMENTED LONG TIME SWITCH LOW NIBBLE ACSC C ST DLS AMP MIDDLE NIBBLE TEMP2 LADR LTEMPH COMPLEMENTED LONG TIME SWITCH HIGH NIBBLE ACSC HL ST DLS IPOINT TO AMP HIGH NIBBLE TEMP3 LAI OFH COMPLEMENTED LONG TIME SWITCH HIGH NIBBLE ACSC ACC HO di d ST a DLS POINT TO AMP VERY HIGH NIBBLE 4 NIBBLE FOR LOW 2 NIBBLES ACSC HD ST DLS POINT TO AMP SUPER HIGH NIBBLE TEMPS LAI 5 RT CARRY STOP ITTERATIONS CALCULATION DONE ST GJMP TCS2 5 136 458 151 152 8888888888888888888888
58. The ground fault sensing toroid 508 sums the out put currents from the transformers 510 512 and 514 In a system utilizing a neutral N line 106 the ground fault sensing toroid also sums the output current from a trans former 506 which is coupled to the neutral line N to sense any return current signal representing this current summation is produced at an output winding 509 and is carried to a fourth rectifier bridge 522 The rectifier bridge 522 is used to detect ground fault condi tions and is discussed in the second part of this section On the right positive side of the rectifier bridges 516 522 positive phase current signals are produced and added together at lead 524 The current at lead 524 is used for the power supply 122 which is discussed in the third part of this section On the left negative side of the rectifier bridges 516 520 negative phase current signals are carried through the burden resistor arrangement 530 and trip ping system ground and are returned to the rectifier bridges 516 520 through the power supply 122 This current path establishes voltage signals and each referred to as a burden voltage for measurement by the microcomputer 120 via the gain circuit 134 In FIG 4 the signals A B and C are presented to the respective dual gain sections for inversion and am plification The gain circuit 134 of FIG 4 is shown with one of its three identical dual gain sections generally des
59. and 65 the rating plug 531 is shown to include the resistors 527 mounted on a printed circuit board 587 A connector 588 is used to interconnect the rating plug with the remaining portion of the tripping system 100 When the rating plug is absent from the tripping system the system reverts to its minimum rat ing The rating plug 531 further includes copper fusible printed circuit links A B C and D which are selectively disconnected opened from a printed circuit connec tion 589 to inform the microcomputer 120 of the resistor values or the burden voltage current ratio in the bur den resistor arrangement 530 The printed circuit con nection 589 is connected to the 5 V signal via one of the contact points on the connector 588 This connec tion 589 allows the tripping system to encode the printed circuit links A B C and D in binary logic such that one of 16 values of each parallel resistor arrange ment is defined therefrom In a preferred arrangement the binary codes 11117 and 1110 are reserved for testing purposes and the fourteen codes 0000 to 1101 correspond to current rating multipliers of 0 400 to 1 000 as follows Current Rating Code Multiplier 0000 0 400 0001 0 500 0010 0 536 0011 0 583 0100 0 600 0101 0 625 0110 0 667 0111 0 700 1000 0 750 1001 0 800 1010 0 833 1011 0 875 1100 0 900 1101 1 000 The user select circuit 132 of FIG 9 includes the interface circuit used by the microc
60. bits LSLB 5 as above ABA combine bits from ACCA amp ACCB STAA LT SWITCHES save for xmit 10 4 RIS qp dete e ode LT SERIAL BITS FH e d de e e e 5 SECTION SETS LT PU COMMUNICATION iii 87 ve 4 USES ACCA ACCB IX 5 136 458 88 CALLED Without any values passed RETURNS Overload pick up information for each phase in OVPU_SCRIN communication buffer memory IY RESTORES Nothing eode RIK REEMA We dem dee go LT SERIAL BITS EQU BCLR PHASE IN PU NOT MTR CODE CLR COMM BITS BSET EQU LDD CPD BLO BSET JMP EQU BCLR LDD CPD BLO BSET EQU LDD CPD BLO BSET JMP EQU BCLR LDD CPD BLO BSET EQU RTS TRY BPHASE CLR SER BITS TRY CPHASE LEAR SER BITS BITS SET a SHORT 5 4 5o Ss Se 5 EQU LDX JSR EQU ST ISQ IN DOUBLE FOR INIT dt e fe ft ee e e e e e eoe dede END L N G TIME 5 BRSET LT FLAGS LT PU BIT PHASE IN PU BRSET LT FLAGS LT 90 OVPU_SCRIN 3F BITS SET 5 PU TBL 11 PUS0 TBL LTPUSW SW POS PHASA SORT 0 CLR COMM BITS OVPU_SCRIN 09 TRY_BPHASE OVPU_SCRIN 09 PHASA_SORT 0 Y UE TRY BPHASE OVPU SCRIN 01 PHASB SQRT 4 CLR SER BITS O
61. bypass DECA 5 INST RESET TIMER LDAA ST RETN TIMER get retention timer value BLE TO RESTRAIN YOURSELF negative it is asleep o t DECA STAA ST RETN TIMER URSELF EQU 5 5 136 458 129 130 LDAA SC RESTRN TIMER BLE TRY OUT 12 if negative we are asleep off DECA 5 SC RESTRN TIMER TRY OUT 12 EQU 5 LDX ST I2 OUT TIMER BLE GF TIMERS zbranch if asleep off or 0 DEX STX 65 I2 OUT TIMER DEC GF TIMERS 5 BRSET FLAGSS NO BIT STROBE if GF bypasss LDAA GF RESTRN TIME restraint timer BLE RETN TIMR if asleep or null bypass DECA decrement STAA GF_RESTRN_TIME Save value CHK_RETN_TIMR EQU 5 LDX RETN TIME get restraint timer BLE CHK LONG TIMR if asleep or null bypass DEX decrement STX GF RETN TIME save value LONG TIMR EQU 5 E M LDX LONG TIME get restraint timer BLE STROBE WDOG if asleep or null bypass DEX decrement STX GF LONG TIME save value pex eee ALI GF TIMERS DONE DECREMENTED AT THIS tete te de He de te we STROBE WDOG EQU LDX REGSTART BCLR PORTA X WATCHDOG set watchdog bit low BSET 5 55 turn SPI back on for transmissions RII OF 5mSEC INTERRUPT ROUTINE exse de de He Ie Se Fe Fe He de e de 3E Ie 1e PAGE e desees FOLLOWING ARE THE SOFTDOG ERROR TRIP ROUTINES fe fe e fe e cfe je e de e je dee CALLED F
62. de de e de dr de de e ST_PU_BIT EQUAL 01 short time pick up flag bit LRC PU BIT EQUAL 501 locked rotor pick up flag bit DOUBLE ST I2 BIT EQUAL 02 double ist 172 calculation INST PU BIT EQUAL 10 zinst pickup flag bit I TIMR BIT EQUAL 20 instantaneous timer is active bit INST OFF BIT EQUAL 40 bit set if ST installed amp INST is off SC LRC FLAGS BIT DEFINITIONS e kc Se de e fe je e fe e e de e de e e e e ic e e e e fe eee de e x START OF INTERRUPT FLAGS seeded dede de de de ie Fe de e de Fe Fe We dede ONE MSBIT EQUAL 01 BIT NUMBER FOR 1 MS IFLAGS TRIPPING EQUAL 80 BIT SET TO KEEP INST FROM RUNNING IN INTERRUP END OF FLAG BIT ASSIGNMENTS START OF PORT BITS USED de de d e dr dede vexe TRIP BIT O EQUAL 80 BIT OF PORTA FOR TRIP LED o EQUAL 08 OF PORTA FOR FLASHING LED SC RESTR OUT EQUAL 510 7INST ST restraint output bit sc RESTRAINT BIT_IN EQUAL 04 restraint input bit GE DESENSE BIT OUT EQUAL 04 PIN 2 PORT D ALSO MISO OF SPI GF RES OUT EQUAL 20 ground fault restraint output bit GF RES IN EQUAL 02 ground fault restraint input bit REST ACTIVE EQUAL 40 bit in serial comm for GF restraint status T INACTIVE BIT EQUAL 580 zif set to one timer is not active WATCHDOG BIT EQUAL 40 shardware watchdog bit MOTOR PROT BIT EQUAL 10 this bit set in serial comm for mo
63. e defe e eoe e e e de de e e e e e e e e e de KKK THIS ROUTINE IS CALLED BY EXEC EVERY 12 MS IF PEAK SQRT IS BELOW PICK UP IT WILL DEC ACCUM BY ONE OF THE FOLLOWING IF IT ACCUM 22 SECONDS IT WILL SUBTRACT LT 0 2 19 FROM LT ACCUM ELSE IT WILL SUBTRACT LT ACCUM 2 16 FROM THE LT ACCUM CALLED According to description above Se se va Se Se Na e Se Se Se te Se EM RETURNS Nothing works on LT ACCUM memory location USES ACCA ACCB RESTORES Nothing TEMP USED FLC DEC ACCUM EQU 5 LT DEC 5 1 TEST FOR LT ACCUM gt 22 SECONDS LDD ACCUM LOAD HI WORD LT ACCUM BEQ WORD IS ZERO hi word 0 branch CPD 5051 COMP TO 22 SECONDS BHI LT GT 22SECS YES IT S ABOVE 22 SECONDS BLO CONT LT DEC slower so dec by 1 2 16 LDD LT 1 ACCUM 2 LOW WORD OF LT ACCUM BNE LT 225 5 WORD 051C LOW WORD 20 JMP CONT ITI DEC zlow word 0 HI WORD IS ZERO EQU 5 2 SUBTRACT 1 FROM LOW WORD OF 4 BYTE ACCUM HI WORD 0 LOW lt gt 0 LDD LT ACCUM 2 GET LOW WORD 4 BYTE ACCUM BNE LT SUB 1 NOT ZERO YET BCLR LT FLAGS LT GTZ BIT CLEAR LT ACCUM GT ZERO BIT RTS LT_SUB_1 EQU SUBD 1 SUB ONE STD ACCUM 2 PUT IN LOW WORD OF 4 BYTE ACCUM BNE RETURN _ NOT ZERO BCLR LT FLAGS LT GTZ CLEAR LT ACCUM GT ZERO BIT LT RETURN EQU RTS 2ERO WORD RETURN CONT LT DEC EQU 2
64. e e e e e de e e ede e e e le de e ee he e dee de e e de fe de ee e ee e de ie dece PSEUDO CODE FOR MEAN SQUARE ROUTINE gd THIS IS WRITTEN IN ye ese qe e e e e le fe e e sic e de e e e j include lt stdlib h gt 7 include lt stdio h gt 3 include lt math h gt int x pass min pass max pass avg pass 2 global variables slong sum tb1 3 avg pass sum xms mean rms sqroot guess 18 255 443 572 677 768 849 923 991 1055 1116 1173 1228 1279 1330 1379 1425 1471 1511 global variables 7 2 int y long tempi temp2 temp3 result remainder temp rt routine dependant variables rms mean sum tbl x 128 find mean of sums for current channel rms mean 131072 find lookup table position amp 17 mask off any high bits rms sqroot guess y get guess into rms sqroot start of iteration loop templ rms mean 256 take only upper 16 bits temp2 rms mean 5 256 16 mask off low nibble of low byte D temp3 rms mean tempi 256 temp2 16 get final rera result templ 5 sqroot get result of initial division remainder templ rzs sqroot get remainder temp2 remainder 16 shift remainder and add next 4 bi i result
65. e e e e e ie die e de ie e de e e e e e c e 7 e de de qe dee ede EEPROM ERASE EQU 5 LDX TRIP GET START OF AREA TO ERASE KEEP CLRING EQU CLR 0 clear data location 2 CPX MEM RATIO to last location BLO CLRING JSR ADDRESS WEE address EEPROM to start write JSR WRITE EE all 05 to EEPROM SEI turn off interrupts WAIT FOR WDOG JSR RESET don t want softdog trips JSR WAIT delay WAIT FOR_WDOG branch to keep softdog happ 9 5 5 5 5 5 5 5 5 This routine sends 8 start pulses to reset the E 2 part before reading data IX and ACCB are used and not restored in this routine CALLED From initialization with SPI shut off Se e te RETURNS With E squared reset and ready to recieve the rest of the Code to read data from the EEPROM e te fe fe de e e cde e e de e e ne de e de e de e ee e e fe jede e e e e e e e e c e e e e le e e e e e e e e le Se e fe e e E e de e di se fe e dee e de de RESET EE 5 LDX REGSTART onboard register start BSET PORTD X SDA SCL set cloc
66. ee ce e de de n 4 T1 INTERRUPT EQU 5 LDX REGSTART set 6811 io base register address LDAA TFLGl X release all current interrupts STAA TFLG1 X 1 RESET THE 500 USEC TIMER LDD TCNT X timer count ADDD 970 970 Susec 30 usec 500usec interrupt ST TOCLX back into output compare register 1 strobe the watchdog bit high on each 500 usec interrupt BRSET FLAGSS KILL WATCHDOG BIT LOW GAIN RD if we are in trip don t str WD BSET PORTA X WATCHDOG set watchdog bit high NOW SET THE ATOD FOR HI GAIN READ THE AREA BETWEEN THE COMMENTED A MUST TO BE KEPT TOGETHER THE A D CONVERTER IS SWITCHED FROM LOW TO HIGH GAIN AND THE LOW GAIN VALUES MUST BE READ WITHIN 64 uSEC OR THEY WILL BE OVER WRITTEN WITH HIGH LDAA 530 VALUE TO SET FOR HIGH GAIN A D READ STAA ADCTL X STORE TO ONBOARD TO START CONVERSION ON HI GN A D RATA TRANSFER STARTS HERE FOR THE LOW GAIN A D eerexeeeeedeeier Store peak detect routine take 8uS phase A D conversions take 16uS phase LDAA READ LOW GAIN A D A PHASE 5 1 PHASEA 5 PHASE A D RAM LAST compare to last BLS DO if lower or same don t mess 5 LAST APHASE Jif higher save new value DO BEE EQU LDAA ADR2 X READ LOW GAIN A D PHASE STAA 1 PHASEB S
67. ie e e e Ae e de we Se 5 4 gt e RESET COP 5 LDX LDAA 555 LOAD A 01010101 TO ACCA 5 5 WRITE TO COP RESET REGISTER LDAA LOAD A 10101010 TO ACCA STAA COPRST X FINISH RESETTING THE COP RTS STISTISTISTISTISTISTISTISTISTISTISTISTISTISTISTISTISTISTISTISTISTISTISTISTI H 2 THIS SUBROUTINE SET TBL INDX READS THE BREAKER ID AND THE SWITCH i POSITION AND CALCULATES THE CORRECT POSITION IN A 1 WORD OR A 2 WORD DELAY TABLE CALLED 3 THE X REGISTER MUST CONTAIN THE CORRECT START OF TABLE H THE Y REGISTER MUST CONTAIN THE CORRECT SWITCH ADDRESS THE ACCUM CONTAINS THE NUMBER TO MULTIPLY ACCB BY TO FIND THE ROW IF 55 WORD ALIGN IS SET TO 1 CREATE 1 WORD INDEX IF FLAGSS WORD ALIGN IS A ZERO CREATE 2 WORD INDEX 5 136 458 71 72 RETURNS THE X REGISTER POINTS THE CORRECT TABLE VALUE UPON RETURN 6 ACCB are not set to any given value IY is not changed SET TBL INDX EQU JSR READ_BREAKER_SW go read the breakr type switch CONT TO SET INDX EQU 5 LSRB from wor
68. is programmed to simulate accurately the bi metal deflection mechanism that is commonly used in processor less tripping systems This is accomplished by accumulating the squared values of the measured current samples that are sensed by the analog input circuit 108 The sum of the squared values of that current is proportional to the accumulated heat in the tripping system 100 simulate the bi metal deflection during cooling the microcomputer 120 is programmed to decrement logarithmically the accumulated square of the current In other words during a sampling interval the accumu lated value A of I t is decremented by an amount proportional to A to account for the fact that the rate of heat loss is proportional to the temperature of the power system conductors above ambient temperature In particular the temperature in the tripping system 100 decreases in response to the current path in lines 106 being broken or intermittent When this occurs how ever the microcomputer 120 loses operating power and therefore can no longer maintain this numerical simula tion This problem is overcome by utilizing the thermal memory 138 of FIG 1 to maintain a history of the accu mulated current for a predetermined period of time during which the operating power to the microcom puter 120 is lost As illustrated in FIG 7 this is accom plished using an RC circuit 610 that is monitored and controlled by the microcomputer 120 to maintain a voltage
69. on lines 106 to the load As an alternative embodiment the bar segment 324 may be disabled by disconnecting the LCD driver 330 Additional bar segments 332 335 are driven by the display processor 316 to respectively indicate when at least 20 40 40 60 60 80 and 80 100 of the rated trip current is being carried on lines 106 to the load The oscillator 328 also uses part No 14070 standard CMOS oscillator circuit including resistors 329 336 and a capacitor 331 that have values for exam ple of 1 megohm 1 megohm and 0 001 microfarads respectively Even when a power fault causes the sys tem to trip and interrupt the current on lines 106 the local display is still able to operate on a limited basis This sustained operation is performed using the battery 7 338 as secondary power source The battery for ex ample is a 3 to 3 6 volt lithium battery having a pro jected seventeen year The battery 338 supplies power to portions of the loca display 150 only when two conditions are present 1 the latch 320 has re ceived a trip signal from the microcomputer 120 or the test switch 311 is activated and 2 the output voltage level of the 5 V power supply is less than the voltage level from the battery 338 When the latch 320 latches in any one of the four trip indication lines from the data lines 318 a control signal is generated on a latch output line 340 The control signal turns on an electronic switch
70. pe xeeeeeee START GF FLAGS DEFINITIONS PHASE UNBALANCE ereeseex PUPU BIT EQUAL 501 set when in Phase Unbal pick up P U flags DOUBLE I2 BIT EQUAL 08 indicates PUP taken into acct for 172 values USE XS EQUAL 510 for current conversion routine indicates GF TURN ON DESENSE EQUAL 20 zbit set to indicate to turn desense on GF PU EQUAL 40 ground fault pick up flag bit SUPER DESENSE EQUAL 580 if peak phase current 6xP super desense j eteeeextexe END OF FLAGS DEFINITIONS PHASE UNBALANCE adu dee START LT FLC FLAGS BIT DEFINITIONS de e e e de e e e e e de eee e e oe de dee e de dex 5 136 458 25 26 LT PU BIT EQUAL 01 CURRENT LEVEL IS ABOVE PICK UP LT 990 EQUAL 502 CURRENT LEVEL IS ABOVE 90 PICKUP FLC PU BIT EQUAL 01 CURRENT LEVEL IS ABOVE PICK UP FLC PU90 amp BIT EQUAL 02 CURRENT LEVEL IS ABOVE 90 OF PICKUP SET ACCUM BIT EQUAL 04 bit set until LT FLC accum is set on power LT GTZ BIT EQUAL 08 LT ACCUM ZERO FLC GTZ BIT EQUAL 08 FLC ACCUM gt ZERO A_PHASE_CONV EQUAL 10 flag to do A phase serial conversion B PHASE CONV EQUAL 20 flag to do phase serial conversion PHASE _ CONV EQUAL 40 i flag to do A phase serial conversion START OF LT FLC FLAGS DEFINITIONS dee d de de Ie A de de fe e Fe e de deje START OF SC LRC FLAGS BIT DEFINITIONS
71. to re spectively indicate the trip conditions listed above Each of these segments 370 373 is controlled by the latch 320 using an LCD driver circuit 326 and an oscil 0 20 25 30 35 45 50 55 60 65 6 lator circuit 328 The corresponding segment 370 373 illuminates when the associated output signal from the latch 320 is at a logic high level The display processor 316 controls four seven seg ment digits 317 as an ammeter to display the current in the lines 106 The display processor 316 for example is an NEC part No UPD7502 LCD Controller Driver which includes a four bit CMOS microprocessor and a 2 k ROM This NEC part is described in NEC UPD71501 02 03 CMOS 4 Bit Single Chip Microproces sor Users Manual available from NEC Mountain View Calif Other segments 375 of the LCD display 322 may be controlled by the display processor 316 or by other means to display various types of status mes sages For example a push button switch 311 may be uti lized to test a battery 338 To perform this test the battery 338 is connected through a diode 313 to one of the segments 375 so that when the switch 311 is pressed the condition of the battery is indicated The push but ton switch 311 preferably resets the latch 320 when the Switch is depressed For this purpose the switch 311 activates a transistor 315 The latch for example is a 40174 integrated circuit Additionally the switch 311 may be used to sel
72. trip memory 144 will reprogram its contents overwriting the old history information with the newly received data During normal operation after power up and without a trip the microcomputer 120 transmits opera tional information over the serial peripheral interface 191 Because this information does not contain the unique bit patterns required to activate the trip memory 144 the trip memory 144 ignores the normal transmis sions However other devices which may be connected to the serial peripheral interface 191 can receive and interpret the information correctly The microcomputer 120 for example is programmed to execute a communication procedure that permits the tripping system 100 to communicate with a relatively low power processor in the display processor 316 The procedure utilizes a software interrupt mechanism to track the frequency with which information is sent on the interfaces 151 and 191 During normal operation one 8 bit byte of information is sent every seven milli seconds During tripping conditions information is sent continuously as fast as the microcomputer 120 can transmit This procedure allows the display terminal 162 and the display processor 316 to display continu ously status messages from the tripping system 100 without dedicating their processors exclusively to this reception function Equally important this procedure permits the microcomputer 120 to perform a variety of tasks including continuou
73. up 1 position SHORT TIME PU TABLE ST PU TBL EQU DW 246 308 370 493 617 740 987 1234 ST PE PU TBL EQ 5 TABLE FOR PE BREAKER ONLY DW 246 308 370 493 617 740 863 987 ST 2000A PE PU TABLE FOR 2000A PE BREAKER ONLY DW 246 308 370 430 493 553 617 740 ST 2500A PE PU TABLE FOR 2500A PE BREAKER ONLY DW 246 270 308 370 430 493 553 617 PPTTTTTTTTTTTTTTTTTTTTTTSHORT TIME DELAY ST FIXED DEL EQU 5 FIXED DEL EQU 5 DW 78 173 287 458 DW 78 173 287 458 DW 74 169 283 454 DW 58 153 267 438 PE DW 67 162 276 447 5 40 135 249 420 05 SHORT TIME 172 IN TABLES ARE 5 ABOVE NOMINAL TO HELP ADJUST FOR EXTENDED BREAKER OPENNING TIMES AT CURRENT VALUES LESS THAN 12xP ST ISQ DEL EQU LONG 500000000 500000000 500000000 500000000 LE LONG 85756673 53672191 32282535 14457823 LONG 00000000 500000000 500000000 500000000 LONG 85756673 53672191 32282535 14457823 LONG 00000000 00000000 00000000 00000000 LONG 84964464 52879981 31490326 13665613 LONG 00000000 00000000 00000000 500000000 PE LONG 81795626 49711143 28321488 10496775 LONG 00000000 00000000 00000000 00000000 SE LONG 83578097 51493615 30103959 1227
74. 010 Data Byte 1 Maximum Phase Current High Byte H Appendices Data Byte 2 Maximum Phase Current Low Byte The attached appendices respectively illustrate the Data Byte 3 Maximum Phase Identification B or N preferred manner in which the microcomputer 120 of 4 Ground Fault FIG 1 and the display processor 316 of FIG 3a may be Data Byte 4 Trip Unit Aenor Paucis 45 programmed to implement the system as set forth above in the preferred embodiment TABLE 1 SAMPLE TIME 9 SQUARED SUMMATION SQUARED SUMMATION Number ms Amps Amps Amps Binary Binary Binary 1 0 0 0 00 0 00 0 00 0 0 0 2 0 5 18 74 351 12 351 12 48 2304 2304 3 10 36 81 1355 16 1706 27 94 8836 11140 4 1 5 53 58 2871 10 4577 38 137 18769 29909 5 2 0 68 45 4686 05 9263 42 175 30625 60534 6 2 5 80 90 6545 08 15808 51 206 42436 102970 7 30 90 48 8187 12 23995 62 231 53361 156331 8 3 5 96 86 9381 53 33377 16 247 61009 217340 9 40 99 80 9960 57 43337 73 254 64516 281856 10 4 5 99 21 9842 92 53180 65 253 64009 345865 5 0 95 11 9045 09 62225 73 243 59049 404914 12 5 5 87 63 7679 14 69904 87 223 49729 454643 13 60 77 05 5936 91 75841 78 196 38416 493059 14 6 5 63 74 4063 10 79904 88 163 26569 519628 15 70 48 18 2320 87 82225 75 123 15129 534757 16 7 5 30 90 954 92 83180 67 79 6241 540998 17 80 12 53 157 09 83337 75 32 1024 542022 18 8 5 6 28 39 43 83377 18 16 256 542278 19 9 0 24 87 618 46 83995 64 63 3969 546247 20 9 5 42 58 1
75. 130 for interfacing the microcom puter 120 with various circuits including the ROM 128 and a user select circuit 132 The address and data de coding circuit 130 for example includes an address decoder part 74HC138 and an eight bit latch part No 74HC373 to latch the lower eight address bits which are alternately multiplexed with eight data bits in conventional fashion The ROM for example is part 27C64 user select circuit 132 allows the user to designate tripping characteristics for the tripping sys tem 100 such as overload and phase imbalance fault conditions The tripping system 100 is operatively coupled with a 20 25 30 35 40 45 conventional electrical distribution system not shown through input and output restraint circuits 105 and 107 Signals received from the input restraint circuit 105 indicate that a downstream circuit breaker is in an over load or over current condition The output restraint circuit 107 is used to send signals to upstream circuit breakers to indicate the status of its own and all down stream circuit breaker conditions In general the trip ping system 100 will delay tripping of the contactors 114 when a downstream breaker is in an overload or over current condition assuming that the downstream circuit breaker opens and clears the condition Other wise the tripping system 100 should not delay tripping of the contactors 114 For further detail regarding re
76. 14 DB 015H 017H 8B 8888 8 8 88 8 88888 88 8 8 8 88 8 88 88 88 88888 8 848858 8 8 8 AAA CALCULATE BREAKER AMP RATING TIMES TEN 8 sINTIALIZE MEMORY STORAGE AND COUNT VALUE TRAT LAI O9H COUNTFOR TEN TAE 5 136 458 153 154 INITIALZE DATA TO 00 LHL TEMPI ST DLS 2 ST DLS ST LI 05 ST DLS 5 ST ADD NUMBER TO ITSELF FOR TEN ITTERATIONS TRAT2 RC CARRY LHL TEMPI LADR BTI ACSC NOP 2 ST DLS 2 LADR 2 ACSC NOP ST DLS GJMP GB B Bx B B 8 8 BB B B B B BK AAAA AAA KK KKK amp ROM LOOKUP ROUTINE FOR BREAKER AMP RATING ENTER amp amp amp amp amp amp amp amp amp amp amp 8 amp 8 amp amp amp amp amp amp amp amp 8 amp 8 amp amp amp amp amp 8 amp 8 amp amp amp amp amp amp amp amp amp amp amp amp 88 amp 8 amp amp amp 8 amp amp amp amp amp amp amp amp amp amp amp ORG 180H DB OD8H O4EH 56 064 D68H 07 082H 086H DB 026H 09CH 0 0 DB 9 DOEH 010H 01 1H 012H 013H O14H DB 016H 018H or MEMORY INITALZATION CONTINUED INTI SO SERIAL SETUP ZERO ZER
77. 18 520 and 522 to provide the current for the power supply 122 On the right side of the recti fier bridges 516 522 at lead 524 the output currents are summed and fed directly to a Darlington transistor 568 a 9 1 volts zener diode 570 and a bias resistor 572 Most of this current flows directly through the transistor 568 to ground to create a constant 9 1 volt level at the base of the transistor 568 Because it has a nominal emitter to 45 50 55 60 65 12 base voltage Veb of about 1 0 volts the emitter of the transistor 568 is at approximately 10 volts The transis tor 568 will strive to maintain 10 volts across it from emitter to collector regardless of the current through it Preferred component values are for example part No 2N6285 for Darlington transistor 568 1N4739 for zener diode 570 and 220 ohms for resistor 572 At the emitter of the transistor 568 the power signal VT trip voltage is provided The 5 v signal is a regulated 5 v power supply output signal that is provided using a voltage regulator 571 part No LP2950ACZ 5 0 and a capacitor 582 which prevents the output of the regulator 571 from oscillating The voltage regulator takes its input from via a diode 576 The diode 576 charges capacitor 584 to within one diode drop 0 6 v of VT and creates a second supply source of approximately 9 v which is referred to as 9 V power supply The energy stored in the capacitor 584 enables t
78. 331998 5 1982 Matsko et al 361 93 phase current detection circuit using a minimal number 4 331 999 5 1982 Engeletal 361 94 Of components set of current sensors is situated adja 4 335 413 6 1982 Engel et al 361 93 cent the current path to sense respective phases of cur 4 335 437 6 1982 Wilson et al 2 364 483 rent therein The current sensors provide respective 4 338 647 7 1982 Wilson 361 96 current signals therefrom which are fed to ground 4 al 27 2 fault transformer The ground fault transformer in cludes input inductors connected to respective ones of 4 377 836 3 1983 Elms et al 222222222 361 96 4 377 837 3 1983 Matsko et al 361 105 the current sensors such that current flowing through 4 380 785 4 1983 Demeyer et al 361 96 each respective current sensor also flows through one 4 419 619 12 1983 Jindrick et al 323 257 of the input inductors An output inductor in the ground 4 428 022 1 1984 Engel et al 361 96 fault transformer is coupled with the input inductors for 4 476 511 10 1984 Saletta et al 361 96 adding the current signals from the current sensors and eis for producing an output current signal in the presence 4 550 360 10 1985 Dougherty 361 93 of ground fault The output current signal is then 4 631 625 12 1986 Alexander et al 361 94 rectified to p
79. 389 3CE 5 540 542 5440 46A 487 54 5409 54 550 5525 53E 556 556 5585 559 5583 55 9 SDF 5522 gto ode dede jede de PRODUCTION TEST CODE IS HERE ft fe fe c fe e e e de nhe fe e e e fe e e e oe e fede PRODUCTION TEST EQU CLR LDAA ANDA BNE JMP WALK A 1 EQU LDX LDD DECREMENT AND STORE STD DEX DEX CPX CHECK RAM MEM RETENTION LDD LDX LDY JSR GF RAM TEST OK EQU JSR PAGE DDRD REGSTART set potrD to inputs PORTA REGSTART check for gf cap 501 mask all but WALK A 1 if 0 cap is discharged CHECK RAM MEM RETENTION RAM END 1 point to GF RAM locations 555 load value EQU 5 0 store bit pattern back up 1 it again 00 check for bottom DECREMENT AND STORE not done so store again END 3 point to RAM locations SWITCHES error storage n case of error CHECK RAM RETENTION IN PU SWITCHES 70 set to indicate not tested GF RAM TEST OK around test EQU 8 _ 55 gt load value LONG TIME 1 to GF RAM locations PU SWITCHES storage case of error CHECK RAM RETENTION RESET COP keep the puppy happy CHECKSUM TEST DONE HERE RRd dkk a de dee This test takes roughly 81 000 clock cycles 40 mSec will not trip COP CHECKSUM TEST EQU CLRB LDY ADD NEXT BYTE EQU ADDB INY
80. 444 456 475 508 533 571 609 634 665 679 761 400 DW 487 609 685 710 731 761 813 853 914 974 1015 1066 1096 1219 I 600 AMP DW 731 914 1030 1065 1096 1143 1219 1280 1370 1463 1523 1600 1644 1 I 630 AMP DW 767 960 1081 1119 1152 1199 1280 1344 1439 1536 1598 1679 1728 1 I 800 AMP DW 974 1219 1372 1421 1462 1524 1626 1706 1829 1950 2030 2133 2194 I 1200 AMP DW 1462 1829 2057 2131 2194 2285 2437 2540 2742 2925 3045 3200 3290 221222 DW 1524 1905 2144 2221 2285 2380 2540 2666 2857 3047 3173 3332 3427 I 1600 AMP DW 1949 2437 2748 2842 2924 3047 3252 3413 3656 3900 4060 4265 4392 2000 DW 2437 3047 3430 3553 3656 3808 4064 4265 4570 4875 5077 5332 5485 2500 DW 3047 3808 4289 4441 4570 4760 5081 5332 5712 6093 6345 6732 6925 I 3000 AMP DW 3656 4570 5146 5329 5485 5712 6096 6398 6856 7313 7614 7998 8227 I 3200 AMP DW 3900 4875 5490 5684 5850 6094 6503 6825 7313 7800 8122 8532 8774 I 4000 AMP DW 4975 6094 6862 7106 7313 7617 8129 8532 9142 9750 10153 10664 10970 12 DW 578 value to make current conversion usable w GF cick nk cin GUESS This is a first guess table for the seed for the square root 2 routine GUESS EQU 5 DW 50 DW 139 DW 194 DW 51 DW 521 DW 258 DW 28C DW 2BD DW 52 Dw 315 DW 5330 5 136 458 139 140 HEEEEEEEEEFFFEFEEFEEEFEEEEFE PAGE 364
81. 5 DIGIT LEFT SIDE CALL LEFT CHARACTER LEFT SIDE DATA AND STORE DISPLAY 1005 DIGIT CARRY LADR BCD3 ACC 1005 DIGT 1005 DIGIT RIGHT SIDE CALL RIGHT GET CHARACTER RIGHT SIDE DATA AND STORE LHL ONE POINTTO VALUE O1H LADR OAH ACC x CENTER OF CHAR ANL LOW 3 BITS QAH POINTTO CENTER ST STORE MASKED VALUE RC LADR BCD3 1005 DIGIT CALL CENTER CHARACTER CENTER DATA OAH POINT TO CENTER VALUE FOR 1005 CHAR ORL ST RESTORE BCD VALUE RC LADR BCD3 ACC 1005 DIGIT LHL OBH POINTTO 1005 DIGIT LEFT SIDE CALL LEFT CHARACTER LEFT SIDE DATA AND STORE DISPLAY 10008 DIGIT RC C RESET CARRY BCD4 1000S DIGIT LHL OCH POINT TO 10005 DIGIT RIGHT SIDE CALL RIGHT CHARACTER RIGHT SIDE DATA AND STORE ONE POINTTO VALUE LADR ACC CENTER OF CHAR 5 5 136 458 185 186 MASK LOW 3 BITS CENTER ST MASKED VALUE RC LADR BCD4 10005 DIGIT CALL CENTER GET CHARACTER CENTER DATA LHL POINT TO CENTER VALUE FOR 10005 CHAR ORL ST RESTORE BCD VALUE RC BCD4 ACC 10005 DIGIT OEH POINT TO 1000 S DIGT LEFT SIDE CALL LEFT GET CHARACTER LEFT SIDE DATA AND STORE RT sSSSSSSSSESSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS i 5 RATING CALCULATE AMPERE RATING 5 5 55
82. 55555555555555555555555555555555555555555555555555555555555555555555555555 UP THE RATING PLUG AND SENSOR VALUES RATING LAI 5100 501 902 5 03 SIDA 5105 XADR 90 LADR CSID SKAEM CALL RATI LADR CRPID SKAEM CALL LTS LADR CLTS i SKAEM CALL RATI SKAEM CALL XADR TEMPI SKAEI RT RC T LADR SI GET SENSOR ID TAE REG SENSOR RATING PLUG POINTER DES GJMP 900 GJMP ADDRO DES GJMP SD1 GJMP ADDR DES GJMP 502 GJMP ADOR2 DES GJMP 903 GJMP ADDR3 DES GJMP 904 GJMP ADDR4 DES GJMP 505 GJMP ADDRS5 DES 510 5107 5108 5 09 5010 SID11 GJMP GJMP DES GJMP GJMP DES GJMP GJMP DES GJMP GJMP DES GJMP GJMP DES GJMP GJMP DES GJMP GJMP 5 136 458 187 506 6 507 ADDR7 5 08 ADORS 509 ADDR9 5010 5011 ADDR ADDR13 ADOR12 RATING USING RATING PLUG AS OFFSET POINTER ADDRO RATING LOW NIBBLE CL RATING AMP RATING LOW NIBBLE GJMP CL GOT RATING BTI RATING LOW NIBBLE CL RATING BTI AMP RATING LOW NIBBLE CL GOT RATING BTI AMP RATING LOW NIBBLE CL RATING AMP RATING LOW NIBBLE CL GOT RATING LHL RATING LOW NIBBLE CL GOT RATIN
83. 555555555555555555555555555555555555555556555 5 ARAT GET AMP RATING MIDDLE AND HIGH NIBBLE 5 i 5 SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS DLS AMP RATING MIDDLE NIBBLE BT2 ST STORE MIDDLE AMP NIBBLE sc LADR RPID ACC RATING PLUG POINTER DLS RATING HIGH NIBBLE 873 RT CONTINUE WITH 10X RATING CALCULATION TRAT TRAT3 LADR 5 136 458 19 160 ACSC GJMP TRATI RT RETURN IF OVERFLOW ERROR TRATI ST DES cd TRAT2 ANOTHER ITTERATION CALCULATION DONE ROM LOOKUP ROUTINE FOR BREAKER AMP RATING ENTER A 8c 8B 888888 ORG DB DB DB DB AMP8 LAMT RT 280H O00H 040H 028H 072H 080H 0 10H 000 0 12H 040H 080H 0 0 019H 01 FH 023H 024H 025 027 029 02BH 02EH 032H 034H 036H 038 5555555555555555555555555555555555555555555555555555555555555555555555555555 5 GETCON GET BCD CONVERTED VALUE i 5 5555555555555555555555555555555555655555555555555555555555555555555555555555 GETCON XADR XADR XADR XADR XADR XADR IES ST STORE CONVERTED VALUE GET CONVERTED VALUE BTI STORE CONVERTED VALUE 2 GET CONVERTED VALUE BT2 STORE CONVERTED VALUE TEMP3 GET CONVERTED VALUE CONVERTED VALUE
84. 6mSec the initialization time is added to timers LDAA 0036 36 ms timer STAA ST RETN TIMER save it to retention timer 100 FFFF reset value STD ST I2 OUT TIMER set to reset 5 sc RESTRN TIMER reset the restraint timer LDAB STDELSW read the delay switch ANDB SW POS mask off bits not wanted 2 3 maximum I 2 out position BLS ST LONG TIME 172 out so branch BSET ST FLAGS DOUBLE ST I2 set flag to double first 172 valu JMP IS GF MEM ACTIVE 7 do GF initialization SET ST LONG TIME LDX 5 FIXED DEL START LOCATION OF FIXED DELAY TABLE STDELSW GF SWITCH ADDRESS LDAA 8 MULT BY 8 FOR OF ENTRIES PER ROW BSET FLAGSS WRD ALIGN 1 WORD BOUNDARY JSR SET TBL INDX CALL INDEX ROUTINE LDD 0 LOAD TIMER VALUE FROM TABLE SUBD 6 subtract INIT time for ST STD ST 12 OUT TIMER save to timer BSET ST I2 OUT TIMER T INACTIVE put timer to sleep IS GF MEM ACTIVE EQU 5 ij QUEUE 5 SECOND GF RETENTION TIMER IF G F MEMORY NOT ACTIVE OR CIC dede OK de Kod e XX JO XI RC CIC e AIT IA This section sets up Short Time to take into account the time to initialize the trip unit when powering up into a fault A reset ti
85. 812 87 85808 52 109 11881 558128 21 10 0 58 78 3454 91 89263 43 150 22500 580628 22 10 5 72 90 5313 94 186 34596 615224 94577 37 5 136 458 21 22 1 SAMPLE TIME SQUARED SUMMATION SQUARED SUMMATION Number ms Amps Amps Amps Binary Binary Binary 23 110 84 43 7128 89 101706 26 215 46225 661449 24 11 5 92 98 8644 84 110351 10 237 56169 717618 25 12 0 98 23 9648 88 119999 97 250 62500 780118 26 12 5 100 00 10000 00 129999 97 255 65025 845143 27 13 0 98 23 9648 89 139648 86 250 62500 907643 28 13 5 92 98 8644 85 148293 71 237 56169 963812 29 14 0 84 43 7128 91 155422 62 215 46225 1010037 14 5 72 90 5313 96 160736 58 186 34596 1044633 31 15 0 58 78 3454 93 164191 51 150 22500 1067133 32 15 5 42 58 1812 89 166004 40 109 11881 1079014 33 160 24 87 618 47 166622 87 63 3969 1082983 34 16 5 6 28 39 43 166662 30 16 256 1083239 35 17 0 12 53 157 08 166819 38 32 1024 1084263 36 17 5 30 90 954 91 167774 29 79 6241 1090504 37 18 0 48 18 2320 85 170095 14 123 15129 1105633 38 18 5 63 74 4063 08 174158 22 163 26569 1132202 39 19 0 77 05 5936 89 180095 11 196 38416 1170618 4 19 5 87 63 7679 12 187774 23 223 49729 1220347 41 20 0 95 11 9045 08 196819 31 243 59049 1279396 42 20 5 99 21 9842 91 206662 22 253 64009 1343405 43 21 0 99 80 9960 58 216622 79 254 64516 1407921 44 21 5 96 86 9381 54 226004 34 247 61009 1468930 45 22 0 90 48 8187 13 234191 47 231 53361 1522291 46 22 5 80 90 6545 10
86. 88 8888588888888888888888888 EEE amp ROM LOOKUP ROUTINE FOR BREAKER AMP RATING ENTER amp 868888888888888888888888888848888488482 ERR KKK RE RRR ORG DB 040 0 6 6 DFOH OBBH D80H 005H OACH DB 010 0 0 00 DB 006H 007H 008H 009H 009H 009H DOAH OOAH OOBH OOCH O0DH O0DH DB THE TRIP CURRENT SETTING COUNTER TCS2 RC LAI 1 _ BRL POINT TO TRIP CURRENT SETTING LOW NIBBLE GJMP TICS CARRY STORE AND DO ANOTHER ITTERATION ST 0 LHLI BRM POINT TO TRIP CURRENT SETTING MIDDLE NIBBLE GIMP TICS NO CARRY STORE AND DO ANOTHER ITTERATION LA 0 TRIP CURRENT SETTING HIGH NIBBLE TICS GIMP TCS CARRY STORE AND DO ANOTHER ITERATION RT CARRY ERROR AND CONTINUE PERCENT BAR GRAPH DISPLAY CONTINUED CALL AS ACSC GJMP CARRY THEN STOP ITTERATIONS ST IES INCREMENT COUNTER GJMP ANOTHER ITTERATION GJMP PCT2 5888888888888888888888888 8888 888888888888 88 88 8888888848 ROM LOOKUP ROUTINE FOR BREAKER AMP RATING ENTER AT ARSARARAMAARAARAAAAAAAAAAAS ARE SARAASAASABSABSARAARAAAAA ORG 140H DB Q60H 0B8H 034H DACH O10H OA6H DAOH D68H 094H 088 082 OB 018 070 00 DB 009H 00BH 00DH 00DH DOEH DOEH 01 1H 12 013 0
87. 9247 LONG 500000000 500000000 500000000 500000000 LONG 78230684 46146201 24756545 6931833 TABLES ARE PADDED WITH 0 s SO SET TBL INDEX ROUTINE WORKS CORRECTLY PPTTTTTTTTTTTTTTTTTTT GROUND FAULT PU TABLE TTTTTTTTTTTTTTTTTTTTTT GF PU TBL EQU 5 SENSOR lt 1600 DW 45 56 68 79 102 124 147 170 SENSOR 2000A DW 72 81 90 99 108 118 127 136 SENSOR 2500A DW 58 65 72 79 86 94 101 108 SENSOR 3000A Dw 48 54 60 66 72 78 85 90 SENSOR 3200A DW 45 50 57 62 68 73 79 85 SENSOR 400A DW 36 41 45 50 54 59 63 68 PPTTTTITTTTTTTTTT GROUND FAULT DELAY TABLE DW 4E AD 11F 1CA 4E SAD 11F 1CA DW 54 5 9 511 51 6 DW 3A 99 10B S1B6 DW 543 5 2 5114 51 DW 528 587 5 9 51 4 GF 150 DEL EaU 5 QE LONG 500000000 500000000 500000000 500000000 1 LONG 2115172 1323814 796242 356599 LONG 500000000 500000000 500000000 500000000 LONG 2115172 1323814 796242 356599 LONG 500000000 500000000 500000000 500000000 NE LONG 2095632 1304274 776703 337060 135 5 136 458 136 LONG 500000000 500000000 500000000 500000000 LONG 2017473 1226116 698544 258901 LONG 900000000 500000000 500000000 500000000 5 LONG 2061438 1270080 742508 302865 LONG 500000000 500000000 500000000 500000000 LONG 1929545 1138187 610615 170972 TABLES ARE PADDED WITH 0 s SO SET TBL INDEX ROUTINE WORKS CORRECTLY MAX GF ATO
88. ADR GET LAST CONVERTED VALUE XADR BCD STORE CONVERTED VALUE RT SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS 5 5 5 DSPLY DISPLAY BREAKER OPERATING CURRENT 5 5 5555555555555555555555555555555555555555555555555555555555555555555559555555 DISPLAY 15 DIGIT DSPLY RC RESET CARRY LADR 1 15 DIGT LHL POINTTO 15 DIGI RIGHT SIDE RIGHT CHARACTER RIGHT SIDE DATA AND STORE ONE POINTTO VALUE OIH LADR O4H CENTER OF CHAR 5 136 458 2183 _ 184 LOW 3 BITS 044 POINT TO CENTER ST STORE MASKED VALUE RC LADR 15 DIGIT CALL CENTER CHARACTER CENTER DATA LHL 04 POINTTO CENTER VALUE FOR 15 CHAR ST BCD VALUE 1 S DIGT OSH 15 DIGIT LEFT SIDE CALL LEFT CHARACTER LEFT SIDE DATA AND STORE DISPLAY 105 DIGIT RC RESET CARRY LADR BCD2 1050617 LHL OSH POINTTO 10 S DIGIT RIGHT SIDE CALL RIGHT GET CHARACTER RIGHT SIDE DATA AND STORE ONE POINTTO VALUE 07H CENTER OF CHAR ANL MASK LOW 3 BITS 07H POINT TO CENTER ST STORE MASKED VALUE RC LADR BCD2 ACC 10 S DIGI CALL CENTER CHARACTER CENTER DATA 07H CENTER VALUE FOR 10S CHAR ORL Sr RESTORE BCD VALUE RC LADR BCD2 ACC 105 DIGT POINT TO 10
89. AMPT DES GJMP TAMP2 ANOTHER RT CALCULATION DONE 5555555555555555555555555555555555555555555555555555555555555555555555555555 5 5 TURN OFF ALL BAR SEGMENTS 5 5 6 5555555555555555555555555555555555555555555555555555555555555555555555555555 BAROFF 40PERCENT SEGMENT LAI OEH ANL RESET BIT 0 ST STORE OAH 60 PERCENT SEGMENT LAI 2 GRESETBTO ST 074 80 PERCENT SEGMENT LA OEH ANL RESET BIT 0 ST LHU 100 PERCENT SEGMENT LAI 5 136 458 163 164 ANL RESET ST RT amp BEES EEE EEE EEE EEE EEE EEE EEE EEE EEE EEE EK EEE EEE LEER EE AE amp P ROM LOOKUP ROUTINE FOR BREAKER RATING ENTER 117 amp 18 8 amp amp 8 8 8 8 5 888 8 8 EI EEK KEKE ES B B 5686888886888 Rc Bc B ORG 340H DB 020 008 DB 078H 030H 0 0 DB 02 04 1H 44 049H 052 057 D5DH 061H 066H DB 069 075 AMP11 LAMT RT P a a aaa aan Dd a 5 5 COMPLEMENT THE BAR GRAPH DATA FOR SUBTRACTION 5 5 ZERO POINT TO ZERO VALUE SC sSET THE CARRY FLAG TO ADD 1 BRL BREAKER AMP LOW VALUE CMA ACCUMULATOR ACSC sADD 1 NOP XADR BRL COMPLEMENTED VALUE BRM
90. B 2 SQRT PHAS C END SQRTS RMB 0 POINTER TO END OF SQ ROOTS de deo os do dedo de dedo do RE ROGO OR OG C ae 1 MOTOR PROTECTION FUNCTION VARIABLE STORAGE PU APH RMB 1 5 phase unbalance PU BPH RMB 1 5 phase unbalance PU_CPH RMB 1 5 phase unbalance LRC_APHASE RMB 2 21 storage for LRC pick up check LRC_BPHASE RMB 2 I storage for LRC pick up check LRC_CPHASE RMB 2 21 storage for LRC pick up check UNBAL PEAK RMB 1 peak phase unbalance THREE PHASE SUM RMB 2 50 OF ADDING PHASE PEAK SQRT RMB 2 SQ ROOT FOR LAST 64 MS PEAK FLC RMB 2 PEAK OF MODIFIED SQRT FOR MOTOR CODE LRC PEAK RMB 2 of modified FLC 1 MOD POINTER RMB 2 pointer to modifier for T LRC code END OF MOTOR PROTECTION USED MEMORY START OF SQUARE ROOT CALCULATION USE AREA e x x RMS MEAN RMB 2 HIGH WORD 2 WORD MEAN RMS MEAN LW RMB 2 LOW BYTE 2 WORD MEAN RMS SQROOT RMB 2 REMAINDER RMB 2 location for remainder storage TEMP RMB 2 716 WORK AREA 2111 TEMP IS NOT CONFINED TO RMS CALCULATION USE ONLY SUM OF SQUARES nie e efe e e e e e e e e e e e dede ee x RMS SUMSQH 1 RMB 2 phase HIGHEST OF TWO WORDS X RMS SUMSQ 1 RMB 2 LOW BYTE OF LOW WORD RMS SUMSQH 2 RMB 2 X RMS SUMSQ 2 RMB 2 RMS SUMSQH 3 2 phase X RMS SUMSQ 3
91. BITS FOR GROUND FAULT LOGIC RESULT RMB 4 HOLDS ANSWER FOR MULT 16X16 RES BUF 1 buffer space SERIAL COMMUNICATIONS HOUSEKEEPING VARIABLES ARE HERE 5 136 458 31 32 PACKET PTR RMB 1 pointer for current packet being transmitted BYTE PTR RMB 1 POINTER TO NEXT DISP CHAR SERIAL POINTER RMB 2 pointer to byte that was last sent PACKET BOLDER RMB 1 holds 3rd packet to transmit INTERRUPT amp TRIP FLAG IFLAGS i RMB 1 CURRENT VAR MS TIMERS IN USE TRIP_FLAG RMB 1 STORAGE LOCATION FOR CAUSE OF TRIP UNBAL_CTR RMB 1 counter timer for phase unbalance delay TT 1 END RAM VARIABLES TO BE CLEARED TO ZERO AT STARTUP END VARS RMB 0 POINTER TO END OF MEMORY CLEAR SOFTDOG MEMORY AREA NOT CLEARED ON POWER UP eek This section not cleared so that on softdog errors the error counter isn t Cleared by accident SOFT DOG TIMER1 RMB 2 SOFT DOG TIMER2 RMB 2 SOFT DOG CNTR RMB 1 de de dee dede dee ADDRESS POINTER DEFINITIONS fe e fe de 454555455252 2253 RELATIVE CODE ORIGIN 5 000 CODESTART DB AAH 558 VER DB SERIES 3 ver 1 3 COPYRIGHT DB COPYRIGHT 1987 SQUARE D CO MAIN CODE STARTS HERE 9 01 INITIALIZE 1 POWER UP RESET STARTS HERE AND RESETS SOFTDOG COUNTERS AND TIMERS TO ZERO SEI Y disable all interrupts 0000 load double to cl
92. BREAKER AMP MIDDLE VALUE CMA COMPLEMENT ACCUMULATOR ACSC ADD CARRY NOP XADR BRM SAVE COMPLEMENTED VALUE LADR ACC BREAKER AMP HIGH VALUE CMA COMPLEMENT ACCUMULATOR ACSC ADD CARRY NOP XADR COMPLEMENTED VALUE RT PERCENT BAR GRAPH DISPLAY CONTINUED DES DECREMENT COUNTER TWICE CALL BARON UNDERFLOW DONT TURN ON ANY BAR SEG S ROM LOOKUP ROUTINE FOR BREAKER AMP RATING ENTER AT AMP12 AARKARAKRASERALABARAARSARNANARARAREAARKORA RA Guanes ORG DB 000 080 050 20H 52H 0 0 02 D60H DB 080 00080 0 DB 032H O03EH 046H D48H 04 053H 057H OSDH D64H D68H O6DH DB 070H07DH AMP12 LAMT RT 5555555555555555555555555555555555555555565555555555555555555555556555655555 5 5 MERGE MERGE TWO SEVEN BIT DATA BYTES 5 5 5555555555555555555555555555555555555555555555555555555555555555555555555555 MERGE LADR TLMSN ACC LOW BYTE MSN 5 136 458 165 166 RAR 4XRAR RAL RAR BIT 0 2 SHIFT 1 3 RAR RAR XADR TLMSN SHIFTED LEFT NIBBLE RO gt LADR THMSN ACC x HIGH BYTE MSN RAR RIGHT THRU CARRY XADR THMSN 5 ROTATED NIBBLE LADR THLSN ACC HIGH BYTE LSN RAR ROTATE RIGHT THRU CARRY XADR THLSN 5 ROTATED NIBBLE LADR TLMSN ACC LOW BYTE MSN SHIFTED LEFT RAR SHIFT CARRY INTO LMSN XADR TLMSN RT x
93. CTIVE MEMORY SO CLEAR ALL LOCATIONS sew CLR ALL MEM EQU 5 LDX 5 VARS X TO POINT TO VARS TO CLEAR CLR MEM EQU 5 CLEAR ALL VARIABLES IN RAM CIR 0 CLEAR A BYTE INX STEP TO NEXT BYTE CPX VARS HAVE WE CLEARED ALL VARS BLO CLR NO SO CONTINUE CLEARING RAM IS CLEARED AT THIS POINT TO ENSURE CORRECT INITIAL CONDITIONS CHECK FOR INSTALLATION OF ST 4 GF FUNCTIONS xxeeeeesseoeboene JSR OF TRIP UNIT 0 set trip unit type LDAA SOFTWARE VERSION software version revision level STAA SOFT VERS Save to transmit buffer location p SET INST FUNCTION FOR 94 mSEC ALLOW FOR POWER UP sexe e SET INST TO 20 mSEC IF SE DS WITH INST INSTALLED OR 90 mSEC IF INST NOT INSTALLED DISCRIMINATOR FUNCTION LDAA 188 2100 5 6mS for initialization time STAA INST TIMER the timer for all except ds ve 5 136 458 35 36 LDAB TYPE read type of breaker ANDB SWITCH MASK mask off bit 4 BEQ PE 20 is undefined brkr so set for PE CMPB 50 2 C IS maximum legal defined breaker type BHI SET_PE_BIT brkr type is greater than default 4 50 0A SE if SE or DS we need a discriminator BLO AN SE a discriminator isn t needed don t do one IP WE ARE HERE WE HAVE DS A SE BREAKER TEST FOR INSTANEOUS ON BRSET FLAGSS NO ST BIT SET DS AT 20 no ST so INST m
94. D EQU 52000 DW 252 52500 DW 201 53000 DW 168 53200 157 54000 DW 126 MAX 150 TEL EW SENS2000 DW 5 810 SENS2500 DW 59001 SENS3000 DW 56540 SENS3200 DW 56049 SENS4000 DW 53 04 GF I SQ DEL TBL 5 p tables below are used to limit I 2in values to 2000 A max for GF delay calculations e fe de fe c de e e e je fe ne de e e e e e eee ee dee eee x NG 2017473 1226116 698544 258901 PE 2000 SE 2000 LONG 2061438 1270080 742508 302865 DS 2000 LONG 1929545 1138187 610615 170972 SE 2500 LONG 1319320 812851 475205 193834 DS 2500 LONG 1234909 728440 390794 109422 SE 3000 LONG 916194 564480 330004 113460 DS 3000 LONG 857575 505861 271385 75988 SE 3200 LONG 805249 496125 290042 118307 05 3200 LONG 753728 444604 238522 66786 SE 4000 LONG 515359 317520 185627 75716 08 4000 LONG 482386 284547 152654 42743 PE2500 TRIP EQ 5 LONG 1291183 784714 these values are used with 2500A 447068 165697 PITTTTTTTTTTTITTTTTTTTTT LONG TIME PU TABLE LT PU TBL DW 45 55 64 68 73 82 88 91 PPTTTTTTTTTTTTTTITTTTTTT LONG TIME 90 PU TABLE TTTTTTTTTTTTTTTTTTTTTTTTTTTTTT LT PU90 amp 40 49 57 61 65 74 79 82 LONG TIME RATIO TABLES
95. D X SDA_ pull data line low for start bit LDAA SA0 send address for serial EE amp write to addr 0 JSR SEND_ADDR send first address byte CLRA Clear ACCA for data start location JSR SEND ADDR 290 send start address RIS return to calling routine ADDRADDRADDRADDRADDRADDRADDRADDRADDRADDRADDRADDRADDRADDRADDRADDRADDRADDRADDR WRIWRIWRIWRIWRIWRIWRIWRIWRIWRIWRIWRIWRIWRIWRIWRIWRIWRIWRIWRIWRIWRIWRIWRIWRIWRI THIS SUBROUTINE WRITES THE DATA POINTED TO BY IY TO THE EEPROM Se Se va 5 136 458 67 68 IF THE ROUTINE IS USED TO ADDRESS THE E 2 ACCA HOLDS THE DATA AND IY MUST BE SET TO 5 000 OR GREATER TO EXIT CORRECTLY THE ENTIRE HISTORICAL DATA FROM THE RAM WILL WRITTEN THE EEPROM IF THE ROUTINE IS ENTERED AT WRITE EE de fe e fe de e e e e ce ne ee e e fe eee fe de de he e dede ee e ec e e e e c c e e e fe fe fe e e e de e e e de e e e ic fe ne de e e e e e e o e f e ven WRITE EE GET FIRST BYTE ADDRESS TO STORE LDX REGSTART get onboard register address for clock amp data LOAD_NEXT_BYTE EQU 5 LDAA 0 load indexed from IY a jump to this point sends only what is already loaded into ACCA SEND ADDR EQU BCLR PORTD X SCL set clock line low BSET DDRD X SDA turn data into an output CLC clear carry to use hi low bit indicator LDAB 08 load of shifts for 1 byte SET_CLOCK EQU clock low for loading bit onto serial bus BCLR POR
96. D to get done INST PICK UP EQU BSET INST_FLAGS INST_PU_BIT set inst pu flag BSET INSTI FLAGS I_ TIMR BIT inst timer active bit LDX REGSTART set 6811 io reg base in x BSET 5 RESTR BIT OUT set restraint output INC INST CNTR 4 step pu counter LDAB INST CNTR 4 get current inst pu counter 2 test for limit of 2 f WAIT FOR HI not reached 2 yet H Li iiis THIS SECTION RUN ONLY IF WE ARE TRIPPING e fe e fe he ee she ee fe dex BCLR 5 PU GF PU 07 clear before setting phase s gt SCPU CMPA PHASEA check if phase gt INST PU CHECK B FOR PU 1 phase low check B phase BSET 5 PU GF PU 01 bit for phase gt SC PU 5 136 458 123 124 CHECK B FOR PU gt 1 check if B phase gt INST PU BHI CHECK C FOR PU if B phase low check C phase BSET SC PU GF 7502 set bit for B phase SC PU CHECK C FOR PU 5 1 PHASEC check if C phase gt INST PU BHI FINISH INST if C phase low continue BSET SC PU GF PU 04 set bit for C phase gt SC PU FINISH INST FIND THE PEAK 3 PHASES HERE eee LDAA PHASEA check if A phase max 1 PHASEB check if B phase max BHI IS C INST PEAK is gt so branch LDAA 1 PHASEB B is phase max IS C INST PEAK EQU 5 check if phase max BHI ISNT INST PEAK previou
97. DX TABLE POS get GFPU table position in IX CLRA clear high byte LDAB GF PEAK PEAK OF GF VALUES FOR LAST 13 mSEC CPD 0 X ATOD VALUE TO TABLE BHS GF_IN PU ATOD IS ABOVE THE TABLE LEAVE PU ON BCLR 5 PU GF PU GF PU BIT CLEAR PU BIT IN XMIT BUFFER BCLR GF FLAGS GF PU BIT CLEAR PU BIT BSET GF LONG TIME INACTIVE BIT put timer to sleep GF IN PU EQU CLR GF PEAK CLEAR FOR NEW 13mSEC GF PEAK RTS RETURN TO CALLING LOCATION AGE 11 5 RESTRAINT TIME OUT TT H CALLED When the restraint timer times out RETURNS GF restraint timer set to SFF RESET VALUE n USED IX RESTORED NOTHING X44 G4 Y CEA e Be e e e e E E E THIS CODE CAN ONLY BE REACHED VIA 11 MS GF RESTRAINT HOLD TIME OUT Gr RESTRN OFF EQU 5 LDX REGSTART BCLR PORTA X GF_RES OUT CLEAR GF RESTRAINT OUTPUT BSET GF_RESTRN_TIME SFF SET TIMER NUMBER TO NULL RTS TTTTTTTTTT GROUND FAULT RETENTION TIME OUT 4 7 ta CALLED When the GF retention timer counts down to 0 after GF pick up No registers are passed into the routine RETURNS GF accumulator cleared restrained delay timer set to SFFFF unrestrained timer set to 33 and the DOUBLE 12 bit cleared ot USED ACCB RESTORED Nothing e Se
98. EQU 5 136 458 97 98 RTS return to main motor routine 2 2 END OF MAIN GROUND FAULT ROUTINE goose dde G R U N D U L T I 2 de e fe che hn fe ee de e ec ee e e de e e ddr CALLED Every l3mSec from main motor flow when a GF 172 in accum calculation is needed Se Se 4 gt e va y Ss Se 49 Ys RETURNS Either updated accum value or never returns and trips If sensor is greater than 1600 Amps a branch H is taken to execute exception code USED ACCA ACCB IX IY RESTORED NOTHING 11111111111111 211171 RESULT USED 91 2219 9191912133 19 91 93 0 122 23 1 03 1 4 1 2 0 1 GF ISQ IN EQ LDAB SENSOR read GF sensor code ANDB SWITCH_MASK mask it to max switch 51 21 4000 sensor none bigger BLS GFISQ CALC LDAB 51 5 max sensor CONT GFISQ CALC EQU 5 512 to 2000A frame BHS SPECIAL if OE or gt frame size is gt 2000A TEE FOLLOWING CODE IS THE NORMAL GROUND FAULT I SQUARE SOFTWARE NORMAL GF ISQ LDAA PEAK get GF peak in TAB i move GF peak to MUL square it ACCB PNE STD RESULT suse RESULT as a holding register ADD AGAIN LDX ACCUM 5 5 X to the gf accumulater JSR 4 ADD i 2 to 4 byte gf accumulater BRCLR GF FLAGS DOUBLE 12 12 T
99. EQU 5 SUBB 510 SUBTRACT 510 for 1600 sensor BMI SET TO ZERO if sensor lt 1600A result is neg so branch LSRB SHIFT ACCUM B TO THE RIGHT DIVIDE BY 2 LDAA 16 116 BYTES IN TABLE FOR EACH SENSOR MUL GET TABLE POSITION FOR THIS SENSOR JMP ADD TEMP 160 ADD START OF TABLE PLACED IN TEMP CLEAR THE DOUBLE ACCUMULATOR IF SENSOR VALUE IS ZERO SET TO ZERO EQU 5 CLRA CLRB ADD TEMP EQU 5 ADDD PU TBL ADD GF PU TBL ADDRESS TO SENSOR XGDX TABLE POSITION IN DBL ACCUM SET IN X R LDAB GFPUSW READ GF PICK UP SWITCH IN ACCUM B ANDB SW POS MASK ALL BITS EXCEPT VALID SWITCH BITS ADD SWITCH VALUE TO TABLE INDEX STX GF TABLE POS save for comparison in GF 13mS routine CLRA clear high byte LDAB GF PEAK GET PEAK OF GF VALUES FOR LAST 1 2 CYCLE CPD 0 X ATOD VALUE TO TABLE BHS GF PICK UP ATOD IS ABOVE THE TABLE RUN GF ROUTINES JMP OFF GF PICK UP EQU i GF PICK UP BE SET HERE BUT ONLY CLEARED IN THE 13 mSEC PEAK ROUTINE LDX REGSTART 26811 REGISTER BASE ADDRESS BSET PORTA X GF_RES OUT TURN ON RESTRAINT LINE BSET 5 SET PU BIT WE GFPU BSET SC PU PU 40 SET FOR IN XMIT BUFFER 1 Set reset the 11 mSec restraint timer amp the retention timer LDAA 11 11 MS TIMER STAA RESTRN TIME LDX 5000 5 Sec TIMER STX RETN TIME LDAB GFDELSW READ GF DELAY SWITCH ANDB SW POS OFF
100. G AMPRATING LOW NIBBLE CL GOT RATING AMPRATING LOW NIBBLE CL RATING RATING LOW NIBBLE 188 5 136 458 189 190 CALL CALL CALL GJMP CL GOT RATING ADDRIO RATING LOW NIBBLE CALL AMPIO CALL CALL AMPIO GJMP CL GOT RATING ADDR11 LHU BTI AMP RATING LOW NIBBLE 1 CALL ARAT CALL GJMP CL GOT RATING ADDR12 AMP RATING LOW NIBBLE CALL 12 CALL ARAT CALL lt 12 GJMP CL GOT RATING OPER AMP RATING LOW NIBBLE CALL ARAT CL 05 POINT TO BT4 ST STORE RATING HIGH NIBBLE CALL TRAT SALCULATE RATING TIMES TEN CALL BRAT CALCULATE RATING BASED ON LTS CALL COMP COMPLEMENT TRIP CURRENT SETTING RT PRCNT PERCENT OF TRIP RATING BAR GRAPH DISPLAY 5 5 3555555555555555555555555555555555599555555555555555555555555555555555555555 COMPLEMENT THE RATING TO PERFORM SUBTRACTION PRCNT CALL CALCULATE CURRENT TIMES TEN THE COMPLEMENTED AMP RATING TO THE RUNNING CURRENT OVER AND OVER UNTIL CURRENT IS EQUAL TO ZERO THE NUMBER OF ITERATIONS 1S THE NUMBER TIMES PERCENT OF LAI 0 PERCENT 0 PC RC CARRY TEMPI POINT TO LOW BYTE LSN BRL COMPLEMENT RATING LOW NIBBLE CALL AS BRM COMPLEME
101. GF peak cleared 2mSec GF peak is passed to the 13 GF peak location maybe GF pick up bit set if in pick up GF switches stored for communication purposes Starts GF retention timer if needed and appropriate GF delay timer accumulator USED ACCA ACCB IX amp IY restored NOTHING 5 Se vo t t Se ve 1 11111 111 1111 TEMP USED 111111129129 112 193 2 09 92 3 f 2 0 31 2 2 0 9 1 2 0 0 CRECK FOR GF EQU 5 LDX REGSTART GET ONBOARD REGISTER START BRCLR PORTA X GF RES IN SET BIT 1F WE HAVE GF REST IN SET BCLR MAX IDENT GF 1 REST ACTIVE NO GF REST SO CLEAR GF REST XMIT JMP 15 GF INSTALLED DONE SO CONTINUE WITH GF CHECKS SET BIT EQU BSET IDENT GF REST_ACTIVE RECEIVING GF REST SO SET GF REST BIT IS GF INSTALLED EQU BRCLR FLAGSS NO GF BIT SET GF BIT 0 SET GO DO ST JMP EXIT GF 26 NOT INSTALLED LEAVE GF SECTION SET GF PEAK EQU LDAB CUR_GF LOAD CURRENT GF VALUE CLR CUR GF CLEAR 2mSEC GF PEAK MEMORY CMPB GF PEAK FCUMPARE NEW GF TO GF PEAK DATA BLS INSTALLED NEW VALUE IS LOWER BRANCH STAB PEAK NEW IS HIGHER SO MAKE IT PEAK 323 GF PEASE STORE NEW GF PEAK 2 22222222222222221142222217 GF INSTALLED E 5 136 458 95 96 LDAB SENSOR READ SENSOR SWITCH IN THE B ACCUM ANDB SWITCH_MASK mask bits above CMPB 1 1 sensor BLS CONTINUE WITH GFPU CHK LDAB 1 load max sensor CONTINUE WITH GFPU
102. GMENTS 5 5 5555555555555555555555555555555555555555555555555555555555555555555555555555 LHU 40 PERCENT SEGMENT LAI ORL SEF BITO ST DES GJMP BO2 RT BO2 DES DECREMENT COUNTER TWICE GJMP BON2 RT UNDERFLOW RETURN BON2 OAH 60 PERCENT SEGMENT LAI ORL SET BIT O ST DES GJMP RT DES DECREMENT COUNTER TWICE GJMP RT UNDERFLOW RETURN LHL 07H 80 PERCENT SEGMENT LAI OIH ORL BIT ST DES GJMP BO4 RT BO4 DES DECREMENT COUNTER TWICE GJMP BONA RT UNDERFLOW RETURN LHL O4H 100 PERCENT SEGMENT LAI OIH ORL 3 ST RT ISSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS 5 5 UPDATE BAR GRAPH VARIABLE LIST i ISSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS RATI ST STORE THE NEW VARIABLE LAI OIH SETTHE NEW VARIABLE CALCULATION FLAG XADR RT 78 8 8 8 8 8 8 8 AEBS SKE KEES BKK 888 8 8 KEKE 8 8 8c 98 8 RE ER K amp ROM LOOKUP ROUTINE FOR LCD DATA LEFT SIDE OF CHAR amp amp amp amp amp 8 8 8 8 8 8c EERE EERE KEKE EE KEKE KE BR EERE RAK ORG 480H DLEFT DB 60204450540 LEFT LAMT RT 5 136 458 171 172 MAIN DATA ROUTINE PROGRAM FLOW CONTROL PROCESSING SUBROUTINES CALLED TI
103. GND FAULT TRIPS LAST MAX I RMB PEAK CURRENT OF PHASE CAUSING TRIP SOFT TRIP CNT RMB OF SOFTWARE FAILURE TRIPS A_PHASE_TRIP_I RMB B PHASE TRIP I RMB PHASE CURRENT 8 LAST TRIP B PHASE B CURRENT 8 LAST TRIP B CON IN PIN IH P d I IE TRIP CAUSE RMB CAUSE OF LAST TRIP B C PHASE TRIP I RMB PHASE C CURRENT 8 LAST TRIP B GF TRIP CURRENT RMB GROUND FAULT CURRENT LAST TRIP LT MEM RATIO RMB LONG TIME MEMORY RATIO 0 1005 PHASEA UNBAL RMB BYTE 28 PHASE UNBALENCE B PHASEB UNBAL RMB BYTE 29 PHASE B UNBALENCE B PHASEC UNBAL RMB BYTE 30 PHASE C UNBALENCE B SOFT VERS RMB SOFTWARE VERSION B ADDR SS RMB BREAKER ADDRESS TO MAKE UPWARD COMPATIBLE CHECK SUM RMB CHECKSUM BYTE B SERIAL BUF END RMB POINTER TO END OF DISPLAY BUFFER BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB MILLISECOND TIMERS STORED IN THIS AREA T 2MS ST 1 2 mS short time timer T 2MS GF RMB 1 2 mS ground fault timer T 07MS RB 1 27 MS TIMER T 11MS RMB 1 211 MS TIMER T 12MS RMB 1 12 MS TIMER T 13MS RB 1 213 MS TIMER T PHASEA RMS FMB 1 TIMER FOR PHASE A SQUARE ROOT T PHASEB RMS RB 1 TIMER FOR PHASE B SQUARE ROOT T PHASEC RMS 1 TIMER FOR PHASE C SQUARE ROOT T 64 5 RMB 1 64 MS TIMER T 250 5 RMB 1 2250 MS TIMER T 1000 5 RMB 1 1 SEC TIMER SP END OF MILLISECOND TIMERS CCCCCCCCCCCCCC ATOD PEAK FOR PU RMB 2
104. HASEC RMS PHASE C RMS TIMER CMPA 64 HAS 60 MS EXPIRED YET BLO TEST PHASEC 2MS HAVE WE CYCLED ALL 64 MS SUBA 64 reset the timer STAA T PHASEC RMS CLEAR PHASE C TIMER LDX 5 50 50 3 location of squared SUM FOR CHAN 3 ATOD JSR AVG AVERAGE I 2 VALUE CHAN 3 LDD RMS SQROOT 50 FROM ROUTINE STD PHASC SQRT LAST 64 MS SQ ROOT OF I FOR CHAN 3 BSET FLAGS C PHASE CONV CONV DONE SO CLEAR FLAG JMP TEST 64MS CONTINUE MAIN EXEC LOOP TEST PHASEC 2MS EQU 8 HAS PHASE MS TIMER EXPIRED YET TEST 64MS 260 SEE IF TIME TO DO PHASE B RMS BRCLR LT FLAGS C PHASE CONV TEST 64MS Conversion bit is set so do serial comm and phase unbalance routines LDX PHASC SORT GET PHASE C RMS LOCATION JSR PHASE UNBALENCE PHASE UNBALANCE LSRB convert to 1 value for serial comm STAB PHASEC UNBAL STORE UNBALANCE FOR DISPLAY LDX SERIAL POINTER get location of byte last sent CPX PHASE RMS 215 ti the first half of A phase current BNE DO SERIAL CONV C if not OK to do serial conv rsion JMP TEST 64MS GO CHECK FOR 64 mS DO SERIAL CONV C EQU 5 LDY PHASC SQRT get a phase square root location LDX PHASE RMS storage location JSR CONVERSION 2940 do transmit conversion amp storage BCLR FLAGS C PHASE CONV CONV DONE SO CLEAR FLAG TEST 64MS EQU LDAA 64MS GET 64 mS TIMER VALUE 64 HAS ALL 64 MS EXPIRED FOR THIS CYCLE BLO CHECK 250MS CONTINUE MAIN FL
105. INST TABLE EQU LDAB INPUSW read INST PU switch ANDB SWITCH_MASK mask off all but switch actuated bits 2 7 switch position BLS INST SW GOOD value is good so don t reset it LDAB 00 set to minimum INST SW GOOD EQU 5 STAB INST SWITCH save for INST use TBA move data to ACCA BCLR PU SWITCHES 07 clear INST switch data LSRA shift to position for comm data PU SWITCHES with Phase Unbalance data STAA IN PU SWITCHES save to comm buffer Starts loading PU table location here LDX PU load x with inst pu table BRCLR FLAGSS PE BRKR BIT STORE TABLE IF NOT PE BREAKER GO READ INST SW LDX 5 TBL SET FOR PE BREAKER TYPE LDAB SENSOR SENSOR size ANDB SWITCH_MASK mask it off CMPB 2 9 18 is 2000A sensor STORE TABLE if less than use normal LDX 5 2000A 1 PE get 2000A PE table 2 9 zis it 2000A 2500A BEQ STORE TABLE if equal it is 2000A so branch LDX INST 25 0A PE have 2500A PE p seeeee THE CORRECT ROW IS FOUND SO SAVE TO MEMORY i ede aee wede iiae iewe xe STORE TABLE EQU STX TEMP Correct row so save it LDAB INST SWITCH get switch for positioning BRSET FLAGSS NO ST BIT FINISH TABLE POINTER STeoff do INST CMPB 2 7 compare to off position if ST on BHS INST IS OFF if switch gt position 8 INST off ADDB
106. IS ST INSTALLED IF SHORT TIME IS INSTALLED GOTO Se 5 se 256 Se Ss Se Se Se Se Se Se Se Se Se Se Se Se Se Se o se gt HORT_TIME_TEST_PU GOTO EXIT_SHORT_TIME SHORT_TIME_TEST_PU BREAKER TYPE INDEX ADDRESS BREAXE ABLE INDEX ADDRESS OF OTHER BREAKER TABLES IF PEAK PHASE ST PU TABLE GOTO ST PICK UP CLEAR PICK UP ST PU 0 ST OFF ST PICK UP ST_PU_BIT 1 RESTRAINT OUTPUT 1 B TEST INPUT RESTRAINT FOR RESTRAINT DELAYS IF RESTRAINT INPUT 1 GOTO SHORT TIME ST FTIMER 2 DECREMENT TIMER BY 2 IF ST_FTIMER 0 GOTO ST TRIP SHORT TIME ST RETN TIMER 36 ST_SWICHES I 2 GOTO EXIT SHORT TIME ST FIXED DELAY 51 I2 OUT TIMER RESET GOTO SCHEDULE TIMER ELSE IF ST I2 OUT TIMER INACTIVE RESTART T IMER EXIT SHORT TIME SCHEDULT TIMER ST I2 OUT TIMER DELAY TABLE DELAY SWITCH POSITION EXIT SHORT TIME 74 Se Se Se Se Se Ss Ne ta 4 Se Se 5e Ne Ye Se Se e 5e Ne Se Se Se Ne 54 Ne So Se ne Se 44 ta e 5 Se 5 4 Se Se Ne Se Se 5 5 56 59 Se Se Se e Se ve gt e Se Se 52 Se Se 5e Se e s CHECK EVEN MS CHECK 07MS CHECK 11MS 5 136 458 41 42 GROUND FAULT CODE IS EXECUTED HERE IF 2MS GF TIMER gt 2 4 2 5 TIMER 2MS
107. IT HAS NOT EXPIRED YET FOLLOWING CALLS ARE DONE EVERY 11 MS de hee e e ee e n n SUBA 11 reset timer 5 11 5 store reset timer LDX SERIAL POINTER get location of byte last sent CPX PHASE I 5 ti the first half of max current BNE MAX SERIAL CONV if not OK to do serial conversicn JMP TEST ST INSTALLED GO CHECK FOR 64 mS DO MAX SERIAL CONV EQU NB LDX PHASE I storage location for max phase current ST_PEAK max phase current to convert JSR I CONVERSION 7go do conversion for peak current xmit TEST ST INSTALLED EQU IF SHORT TIME PICKUP IS CLEAR BYPASS SHORT TIME SUBROUTINE e4x BRCLR ST FLAGS ST PU BIT CLEAR ST PEAK IF SHORT RESTRAINT IN IS SET WE DON T HAVE RESTRAINED DELAY LDX REGSTART start of registers BRSET PORTA X SC RESTRAINT BIT IN CLEAR ST PEAK LDAB STDELSW READ ST DELAY SWITCH ANDB SW POS MASK OFF BIT O CMPB 06 216 gt 6 i 2 in BLS CLEAR ST PEAK POSITIONS 0 3 ARE I 2 OUT FIXED TIMERS JSR 5 150 IN 60 DO 172 IN ST DELAY ROUTINE CLEAR ST PEAK EQU 5 JSR CHECK ST 12MS CLR ST PEAK amp STPU AS NEEDED 11 5 OPERATIONS e e e e e fe e e e e oic e e e de e le e e e e d x 12 MS TIMER CHECK de de de de de Serial communications and Long Time Accumulator decrement are run on this CHECK 12MS
108. LT STORE BACK TO RAM EQU T LDAA 0 BYTE OF MULTIPLIER BEQ MUL RETURN 0 WE RE DONE LDAB 0 7 BYTE OF MULTIPLICAND BEQ MUL RETURN 0 WE RE DONE MUL MULTIPLY HIGH BYTES ADDD RESULT ADD TO HIGH WORD STD RESULT STORE HIGH WORD BACK TO RAM EQU BCLR FLAGSS I 50 CLEAR SQUARE RTS RETURN AVG takes the values in SUMSQ and does 1 rotate left and drops the low byte to get the average of the square 128 X is loaded with the offset for sum location before the call The average is used to calculate the square root by the NEWTON RAPHSON METHOD CALLED From main with IX pointing to the memory location of the value to find the root mean square for Square sum location is assumed a 32 bit value 4 contiguous memory locations 5 136 458 105 106 5 RETURNS Root Mean Square root of number in location RMS SQROOT 7 Routine makes assumption that 128 values have squared and gt summed before this calculation is made COMMENTS Entered from MAIN with 128 values summed from the SQSUM routine takes the average and puts it in MEAN Then uses that value to calculate the square root Index X equals the location of the sum of the squares for the phase to be calculated h USED ACCA ACCB IX IY RESTORED IX fet e le e ie fe e
109. MR SOFTWARE WATCHDOG RESET PRCNT PERCENT OF RATING CALC AND DISPLAY BCD BCD CONVERSION DSPLY DISPLAY CURRENT IN AMPERES 490H MAIN TIMER START RESET THE SOFTWARE WATCHDOG TIMER LAI XADR FOR COMPLETE DATA PACKET TRANSMISSION THE SERIAL ISR SETS THE READY FLAG WANI LADR FOR SERIAL DATA AVAILABLE GJMP WANI NOT READY WAIT TRANSFER THE TEMPORARY CURRENT INFORMATION INTO PERMANENT MEMORY LOCATIONS AFTER ALL PACKET DATA HAS BEEN SENT BY TRIP UNIT XF CALL XFER THE DATA READY FLAG LAI 5 ACCUMULATOR TO ZERO XADR RDY EXCHANGE ACCUMLATOR WITH DATA READY ADDRESS DONT DISPLAY IF 2 OR 3 WERE LAST RCVD LADR PAK SKAEI GJMP 1 GJMP 1 GJMP MAIN CONVERT HEX DATA INTO BCD M3 BCD DISPLAY THE BREAKER OPERATION CURRENT CALL DSPLY CALCULATE AND DISPLAY THE PERCENT OF RATING BAR SEGMENTS RATING ae gt CALL PRCNT GJMP MAIN RESTART THE CYCLE 55555555555555555555555555555559993555555555999555555555555955995555555559 5 P SISR SERIAL INTERRUPT SERVICE ROUTINE 5 5 5555555555555555555555555595555555555555555555555555555555559555555555555555 557 XADR TSH POINT TEMP SERIAL HIGH BYTE TSIOAM TRANSFER SERIAL DATA INTO MEM HL AND ACCUMULATOR So REINITIALIZE SERIAL TAD TRANSFER SER HIGH
110. NITIALIZE OPTIONS TO INVALID VALUE FORCING RATING UPDATE GJMP INIT SYTEM ORG 10H SOFTDOG ROM VECTOR ADDRESS PSHHL PSHDE TSR TIMER INTERRUPT SERVICE ROUTINE POPDE POPHL OOH RTPSW ORG 20H INTO S SERIAL ROM VECTOR ADDRESS PSHHL PSHDE CALL 888 CALLSERIAL INTERRUPT SERVICE ROUTINE POPDE POPHL El OOH 5 136 458 147 148 ORG 30H INTI SWITCH ROM VECTOR ADDRESS PSHHL PSHDE CALL PSISR PHASE SELECT INTERRUPT SERVICE ROUTINE POPDE POPHL El OOH RTPSW 8 8 t KEE EKER KEKE KKK KR REE KK ERR KKK RRR KR RR ERE Rc EE ROM LOOKUP ROUTINE FOR LONG TIME SWITCH ENTER 15 amp amp EEE KEE 8 8 8 8 8 8 8 8 88 88 8 888 8 KERR BR Rc BR RB RR Rc ORG 40H DB 038H 059H 07 1H 07BH 083 091H 097H 09CH 000 0 0 0 0 0 DB 078H 080H 085H 089H 093 098H 09 LS LAMT RT SERIAL PORT INITIALIZATION INIT LAI 01018 SERIAL SETUP DATA OP ACCTO SERIAL MODE SELECT REGISTER MSR TIMER INITIALIZATION LAI OFH ACCUMULATOR WITH HIGH MODULO NIBBLE LHU LMOD LOAD HL WITH POINTER TO LOW MODULO NIBBLE ST STORE ACC IN MEM POINTED TO BY HL TAMMOD TRANSFER ACC AND HL TO MODULO REGISTER LAI 00008 LCD DISPLAY FRAME CLOCK FREQUENCY FCL 1024 OP OCH CLOCK MODE SELECT REGISTER TIMER RESET TIMER COUNT El 1 INTERRUPT MASTER ENABLE El 7
111. NT RATING MIDDLE NIBBLE CALL AS COMPLEMENT RATING HIGH NIBBLE CALL 5 LAI NIBBLE FOR LOW 3 NIBBLES GJMP PCTI COPYRIGHT MESSAGE DB CY 779787878 DB QUA amp RAM ADDRESS TABLE amp amp 8B 8 88 8 888 888 8 88 88 8 8 88 888 8 8 8 8 8 888 8 8 88 BB 88 8 88 8888 885A S a 555 1 SET PAK ONE BTS BT4 BT3 BT2 SET BTI SET b gaan assag 49 m LMOD SET SD SET RPID SET TEMPS SET SET TEMP3 SET 2 SET TEMP SET LTS SET LTEMPH LTEMPLSET END 47H 51H 52H 54H 57H 62H 5 136 458 191 CALCULATED RATING HIGH NIBBLE CALCULATED RATING MIDDLE NIBBLE CALCULATED RATING LOW NIBBLE 192 TRIP UNIT OPTIONS LONG TIME SWITCH RATING PLUG ID SENSOR ID TEMPORARY SERIAL DATA HIGH TIMER INTERRUPT COUNTER TEMPORARY PACKET NUMBER TEMPORARY PACKET NUMBER AFTER DATA READY COMPARE OPTIONS MEMORY COMPARE LTS COMPARE SID MOST SIG DIGT SIG DIGIT SERIAL DATA READY SERIAL BYTE COUNTER SERIAL BYTE COUNTER TEST VALUE HIGH BYTE MSN HIGH BYTE LSN LOW BYTE MSN LOW BYTE LSN VALUE MEMORY LOCATION AMPERE RATING HIGH NIBBLE RATING
112. O DATA ST 2 MEM LOC TO ZERO LAI ONE POINTTO ONE DATA MEM ST MEM LOC TO 1 LAI LHL TLLSN XADR HMSN INITIALIZE FOR BCD CONVERSION 5 136 458 155 156 PORTS INITIALZATION 00 PORT MODE SELECT REGISTER SET TO INPUT MODE OP OEH OUTPUTTO MSR gt LCD DISPLAY INITIALIZATION LAI 00108 DISPLAY SETUP DATA OP OBH ACCTO DISPLAY MODE SELECT REGISTER MSR GJMP MAIN JUMP TO MAIN ROUTINE ARRA ROM LOOKUP ROUTINE FOR BREAKER RATING ENTER 5 amp ORG 1 0 DB 080H OAOH 094H 03EH OCOH 088H 0D2H 07 058H DB 020H 040H 0 0 DB OOCH OO0FH O11H 012H 012H 013H 014H 015H 017H O19H 01AH DB O1CH O1FH 5555555555555555555555555555555555555555555555555555555555555555555555555555 5 5 5 PSISR PHASE SELECT INTERRUPT SERVICE ROUTINE 4 S 3555555555555555555555555555555555555555555555555555555555555555555555555555 ROTATE THE LCD PHASE ADDRESS RIGHT FOUR TIMES TO POINT NEXT PHASE PSISR XADR ACCTMP TIMER RESET SOFTWARE RESET TIMER LADR PHASE INDICATOR RC RESET CARRY RAR SKAEI ACC OSET FOR A PHASE GJMP PS PSII LAI O8H SET FOR PHASE A PSI XADR SAVESELECTED PHASE OFH SKAEI GF SELECT CHECK TO SEE IF GF IS INSTALLED GJMP PS2 LADR OPT SKABT 2 OPTION INSTALLED GJMP PS2 GJMP 511
113. OF PHASES CHK C PHASE FOUND ST PEAK SCRIN CODE LDAA STAA STAA LDX BHS LDX LDAA EQU CPX BHS LDX LDAA EQU BLS STX BCLR ORAA STAA EQU LDX LAST A B C PHASE cleared for next 2mSec peak in interrupt ST PEAK and max phase set for communications routine use Receiving SC restraint bit set cleared in comm buffer odo d He ede ede deed dede deed ede dedede eode deo LAST APHASE GET LAST PHASE PEAK 6 get multiplier amp multiply it A PHASEX6 TO PEAK OF PHASE TRY PHASE B IF RESULT lt SAVE VALUE BRANCH PHASEX6 and store it 5 LAST LAST B PHASE PEAK 16 PHASEX6 COMPARE TO PEAK OF PHASE TRY PHASE C RESULT lt SAVE VALUE BRANCH B 6 5 LAST CPHASE GET LAST C PHASE PEAK 6 PHASEX6 COMPARE TO PEAK OF PHASE FIND PEAK OF PHASES RESULT lt SAVE VALUE BRANCH PHASEXO EQU 5 00 Clear all last phases LAST APHASE CLEAR LAST 2mSec PEAK LAST BPHASE CLEAR LAST 2mSec LAST CPHASE CLEAR LAST 2mSec PEAK PHASEX6 get 6x low gain input is left at 0 for A phase max phase B PHASEX6 compare to B phase CHK C PHASE gt B so branch B PHASEX6 B phase 01 ACCA for B phase max 5 C PHASEX6 compare to C phase FOUND ST PEAK 21 gt phase branch 5 6 get phase C 02 set for C phase 5 5 _
114. OW SUBA 64 reset the timer STAA T 64MS RESET RMS 64 MS CYCLE TIMER HH RMS 64 MS TIMER HAS EXPIRED fe fe de e e e e e fe fe e e fe fe e e e e e e e ee e dee e e deed PLANER ke dei o FOLLOWING CALLS ARE DONE EVERY 64 MS ekesekeded ede JSR LT SERIAL BITS 290 set LT serial comm bits JSR FIND SQRT find peak of RMS for Long Time amp serial comm JSR LONG_TIME LONG TIME ROUTINES END 64 MS ROUTINES ee eee dee d de de RAKE FOLLOWING ROUTINES ARE DONE EVERY 250 MS se de ce e de dede ge e e d Every 1 4 Sec Long Time LED is flashed if needed 1 Second timer is incremented and Type of Trip Unit is read for serial comm CHECK 250MS EQU LDAA 250 5 LOAD 250 MS TIMER 250 215 IT DUE YET BLO CHECK 1 SEC NO IT IS NOT DUE SUBA 250 reset the timer STAA T 250MS ALL ROUTINES CLEAR TIMER INC 1000MS increment 1 sec timer BCLR FLAGSS KILL SERIAL after 25 Sec allow serial comm JSR CHECK LED SET LED OR OFF AS REQUIRED BY PICKUP JSR TYPE OF TRIP UNIT SWITCH POSITIONS DO TIMR 0 EQU 65 TIMR 0 OF 250 MS ROUTINES THE FOLLOWING SOFTWARE IS DONE EVERY SEC Every Second the Sensor and Breaker type is read for serial transmission and if there are any Softdog errors those routin
115. PS2 LAI OOH ST GJMP 521 28 8 88k 8 8 8 8 8c 8 85 8 8 8 8 8 8 8 8 8 88 8 8 8 8 8 8 8 8 8 8 88 8 5 8 8 8 8 8 8 8 58 8 8 8 8 88 8 68686 ROM LOOKUP ROUTINE FOR BREAKER RATING ENTER 6 8 ORG 200H DB 070 05 058 020 DACH 040H ODOH 028 080 1 004 DB DEOH 0 0 DB 012H 017H 01AH 01BH 01CH 01DH 01FH 020H 023 025 027 029 DB 2 02 5 136 458 157 158 PHASE SELECT ISR CONTINUED PS21 LAI OFH DEBOUNCE COUNT FOR 16 PS22 TAD LAI OFH TAE SKI OSH SKIP IF TIMER INTERRUPT OCCURRED GJMP PS3 LAI COUNTING ACSC GJMP 55 GJMP RESET 55 57 COUNT PS3 GET PORT 5 INPUTS SKABT SWITCH GJMP PS4 PS21 WAIT FOR SWITCH RELEASE 54 DES DECREMENT COUNTER RETURN IF UNDERFLOW GJMP PS3 TDA OFH GJMP PSEX GJMP 522 PSEX XADR Rm C 18 8 8 8 8 amp 888 8 8 8 8 8 8 888 8 8 8 8 8 8 8 KKK KEES KK KKK KKK EK A ROM LOOKUP ROUTINE FOR BREAKER AMP RATING ENTER 7 amp amp AT AET T ET IEN ORG 240H DB 088H6AH 080H 07AH DACH 082 094 02 O10H OAAH OBCH DB OF2H 0D4H 0 0 DB O13H 018H 01BH O1CH O1DH O1EH 020H 022H 024H 027H 028H 2 O2BH 030H S 15555555555555555555555555555
116. R 1000 HIGH BYTE LSN ACSC ADD VALUES GJMP CHUND CALCULATE HUNDREDS VALUE CALL GETCON GJMP THOUS SUBTRACT 100 UNTIL VALUE BECOMES NEGATIVE TO DETERMINE 1005 DIGIT CHUND TEA ACC THOUSANDS DIGIT SKAEI IF DIGT IS ZERO SUPRESS THE CHARACTER GJMP CH LAI OAH POINTTO BLANK CHARACTER BCD4 SAVE THOUSANDS DIGIT COUNT VALUE ZERO HUNDS RC CARRY BTI POINTTO VALUE TO BE CONVERTED LOW BYTE LSN LAI BE ADDED FOR 100 TO LOW BYTE LSN Y ACSC ADD VALUES NOP LHL TEMPI POINT TO TEMP STORAGE FOR CONVERTED VALUE ST TEMP STORE CONVERTED VALUE 2 POINTTO VALUE TO BE CONVERTED LOW BYTE MSN LAI O9H VKELUE TO BE ADDED FOR 100 TO LOW BYTE MSN ACSC ADD VALUES NOP 2 POINT TO TEMP STORAGE FOR CONVERTED VALUE ST STORE CONVERTED VALUE 813 POINTTO VALUE TO BE CONVERTED HIGH BYTE LSN OFH VALUE TO BE ADDED FOR 100 TO HIGH BYTE LSN ACSC ADD VALUES NOP POINT TO TEMP STORAGE FOR CONVERTED VALUE ST STORE CONVERTED VALUE POINTTO VALUE TO BE CONVERTED HIGH BYTE LSN LAI VALUE TO BE ADDED FOR 100 TO HIGH BYTE LSN ACSC ADD VALUES GJMP CTENS CALCULATE HUNDREDS VALUE CALL GETCON GJMP HUNDS SUBTRACT 10 UNTIL VALUE BECOMES NEGATIVE TO DETERMINE 105 DIGIT CTENS TEA x HUNDREDS DIGIT SKAEI
117. R EQU 5 LDX 5 FIXED DEL 5 FIXED DELAY TABLE START LDY STDELSW 7ST DELAY SW ADDRESS LDAA 8 MULT BY 8 BSET FLAGSS WRD ALIGN 21 WORD BOUNDARY REQUEST JSR SET TBL INDX CALL TABLE CREATE SUBROUTINE LDX 0 GET TIMER VALUE FROM TABLE STX ST I2 OUT TIMER start I 2 out timer JMP EXIT SHORT TIME CONTINUE IN MAIN FLOW ST OFF EQU 5 CHECK TIMER INACTIVE BIT FOR ANY FIXED DELAY TIMERS THAT ARE RUNNING PUT THEM TO SLE BRSET ST FLAGS ST PU BIT EXIT SHORT TIME BSET ST 12 OUT TIMER T INACTIVE 1 BIT zif have old PU don t cir any active timers to sl EXIT SHORT TIME EQU 5 THIS CODE IS EXECUTED EVERY TWO MIILISECONDS WHEN THE GROUND 2mSEC TIMER COMES DUE ALL GROUND FAULT PICKUP CODE IS EXECUTED TEST SEE IF GROUND FAULT IS INSTALALLED CHK EVEN MS EQU 5 T LDAA 2MS GF 2 mS ground fault timer 2 has 2 ms passed BLO CHECK 07 5 2 mS hasn t passed leave SUBA 2 reset timer STAA T 2MS GF save timer JSR CHECK FOR GF time up do GF check d Ke CC e e e de e Ke e e de e dede dede de Y YO e dede ode dede eee i TEST FOR ANY FIXED MS TIMERS fe fe it fe e e e he e e fe e e e ie ie e fe e e e fe de e e de e fc e e e ee e e e e e e c fe e e e e e e e le ce fe fe fe e e e de e EQU 5 LT memory cap is set on power up and adjusted on this time base E LDAA 07MS CMPA 07 BLO CHECK 11MS dea dede de THE FOLLO
118. R THMSN TEMP HIGH BYTE MSN GJMP AND STORE LOW DATA BYTE LHLI PACKET 3 RETURN LAI SKAEM GJMP 41 GJMP El 841 LADR BC XAE EXCHANGE ACC AND E REGISTERS DES DECREMENT E REG BC 1 GJMP B7 GJMP El RETURN IF UNDERFLOW EXCHANGE ACC AND E REGISTERS LHL BC SKAEM 1 BCI 1 LAI 04 RATING PLUG BYTE 1 SKAEM GJMP LB GJMP 86 5 136 458 177 178 LB TEA x SERIAL LOW BYTE LOW NIBBLE XADR TLLSN LOW BYTE LSN TDA SERIAL LOW BYTE HIGH NIBBLE XADR TLMSN LOW BYTE MSN GJMP El SENSORID BS LHL HLPOINT TO SENSOR ID TEA SERIAL LOW NIBBLE ST STORE SENSOR GJMP 1 RATING PLUG TEA ACC SERIAL LOW XADR TRPID STORE RATING PLUG TDA SERIAL HIGH XADR STORE TRIP UNIT OPTIONS XADR RT 3 48955955590555555585555 552952555295555555555555552555226655525655525555 BCD HEX TO BCD CONVERSION ROUTINE 5 1 558 5555555 55 555555555555555555555555555559555555555555555555555555555555 CURRENT gt 2700H SET DISPLAY VALUE TO 9999 BCD HIGH BYTE MSN OEH OF 2 FOR TEST RESET CARRY ACSC FOR VALUE gt 2 GJMP CONV LESS THAN 2 CONTINUE CONVERSION TAE RC DES DECREMENT TEST VALUE GJMP OFLW GREATER THAN 2 SET VALUE TO 9999 TEST VALUE x 2 TEST NEX
119. RANSMIT EQU data should be all set up by here so send it to SPI amp SCI transmit registers LDAB SCSR X read SCI status register 7 STAA SCDR X E put data in sci data register amp clr TDRE LDAB SPSR X read SPI status register LDAB SPDR X read data to clear SPIF flag SPI finished STAA 5 store to start transmission SERIAL DONE EQU 5 5 THIS ROUTINE RESETS THE INST TIMER 100 mSEC AFTER AN INITIAL 1005 CALLED When the INST RESET TIMER reaches 0 RETURNS INST TIMER reset to 200 or leaves if an active counter is cro Se 54 94 Se Se gt e gt e e encountered USED ACCA RESTORED NOTHING xxx OE OPERATION BAS BEEN COMPLETED de ede NST TIMER RST BRSET INST FLAGS I TIMR BIT GO TO MAIN Vif there is an active timer leave LDAA 200 get value to reset timer to 100 mSec STAA INST TIMER reset the timer GO TO MAIN EQU 5 LDAA 5 get value to null reset timer STAA INST RESET TIMER 11 the timer RTS RETURN TO MAIN PAGE 2 fe he de de de de e de he de e e e he de de e ee efe e ie e e dfe de fe e e dee e e je e fe nie die n de e e ie e he de e e e e dee INTERRUPT routine to handle Output Compare Register Interrupts THIS OUTPUT COMPARE REGISTER INTERRUPT IS PROGRAMMED TO OCCUR CONTINUOUSLY EVERY 500 MICRO SECONDS OR 5 MILLISECONDS e
120. RIP BCLR FLAGS DOUBLE 12 BIT clear double bit LDD RESULT get saved value back JMP IT AGAIN double 1 2 value for init time CHECK I2 TRIP EQU LDX 6 150 DEL address of gf i 2 table in X LDY GFDELSW saddress of gf delay switch in Y LDAA 32 MULT BY 16 SHIFT LEFT 4 BCLR FLAGSS WRD ALIGN set for double word boundary JSR TBL INDX call table index routine GF_ACCUM points to gf accum JSR DBL WORD gf accum to delay table CMPA 00 BLT TRIP RETURN not tripping so return JMP GF TRIP GF ACCUM gt DELAY TABLE NO TAiP RETURN RTS return to main flow p po CODE FOR SENSORS gt 1600 AMPS BEGINS HERE xeee e THE FOLLOWING CODE IS THE SPECIAL GF CODE FOR SENSOR gt 2000 AMPS JUMPED TO WITH ACCB HOLDING THE SENSOR SIZE OF THE BREAKER RESULT USED 1111111211211 919233111 123 13 1 01 1 f GF SPECIAL EQ SUBB 4512 convert to 0 2 4 6 for gt 2000A frame STAB TEMP SAVE SENSOR 50 IN TEMP LDX GF ATOD TBL location of max GF table frame offset to location LDD 0 GF value GF to max GF value BHS NORM ADD zif GF lt max GF run normal square SPZCIAL GF 150 2 LDX 150 TBL GF PEAK gt max allowed get max allowed LDAB TEMP GET SENSOR 50 FROM TEMP ABX ADD SENSOR OFFSET INTO INDEX LDD 0 X get
121. S RB 1 SYSTEM FLAG BITS GF ACCUM RB 4 GROUND FAULT I 2 ACCUMULATOR RB 1 GROUND FAULT UNRESTRAINED TIMER GF RESTRN TIME RMB 1 TIMER FOR 10 MS GF RESTRAINT HOLD GF_RETN_TIME RB 2 GF 5 SECOND RETENTION TIMER GF LONG TIME RMB 2 QUE TIMER FOR GF RESTRAINT DELAYS ABOVE GF VARS RB 0 Start of memory clear when G F mem high e e Ae e e e ded dede dele edo dede ee Rolle KR ROO ROO I tek SERIAL BUF 0 31 character sci transmit buffer 2 THE FOLLOWING 31 BYTE DEFINITIONS REPRESENT THE TRANSMIT BUFFER B TRIP STATUS BYTE RMB 1 BYTE 00 PICK UP TRIP INDICATOR B A PHASE RMS RMB 2 PBASE A CURRENT B B PHASE RMS 2 PHASE B CURRENT B 5 136 458 27 28 OVPU SCRIN RMB OVERLOAD PU SC RESTR IN B C PHASE RMS RMB PHASE C CURRENT B GF CURRENT RMB GROUND FAULT CURRENT B SC PU GF PU S C amp amp PICKUPS REPLACES PU MAX PHASE I RMB MAXIMUM PHASE CURRENT 256 IDENT RMB MAXIMUM PHASE IDENTIFIER SENSR TU ID RMB SENSOR BREAKER ID RP OPTIONS RMB RATING PLUG OPTIONS LT SWITCHES RMB LONG TIME SWITCHES ST SWITCHES RMB SHORT TIME SWITCHES IN_PU_SWITCHES RMB INST PU SWITCHES GF_SWITCHES RMB GF SWITCHES PU_TRIP_CNT RMB OF PHASE UNBAL TRIPS LT_TRIP_CNT RMB OF LT TRIPS SC_TRIP_CNT RMB OF ST TRIPS GF TRIP CNT RMB OF
122. SEC SUMMATION EQU 5 THIS POINT EITHER LOW OR HIGH GAIN HAS BEEN STORED CUR PHASEC FOR USE TBA move low byte to ACCA for 0 check BEQ LAST C ADD beng multiply low byte by low byte ADDD RMS SUMSQ 3 double to low 16 bits STD RMS SUMSQ 3 save it WORD C OK RMS SUMSQH 3 if carry set increment INX ithe high byte STX 5 SUMSQH 3 and save it HI WORD C 5 136 458 127 128 EQU 5 LDAA CUR 1 get low byte LDAB CUR PHASEC sget high byte for 0 check BEQ SQUARE DONE if high byte 0 we s done MUL 1510 result is shifted to multiply by 2 same as 2 multiplies amp ADDD RMS SUMSQH 3 1 add low high to middle 16 bits STD RMS SUMSQH 3 1 save it LAST C ADD INC RMS SUMSQH 3 Carry was set increment the high byte LAST C ADD EU 5 LDAA CUR PHASEC get high byte BEQ I SQUARE DONE if 0 we re finished TAB move to ACCB MUL multiply for last value ADDD RMS SUMSQH 3 to high 16 bits RMS SUMSQH 3 store back to accumulator C I SQUARE DONE EQU 5 2 Read the Ground fault data GET GRD FLT LDAB 4 GET GROUND FAULT A D in low byte BRCLR FLAGS SUPER DESENSE NORM read A D as normai 12 clear LSRB 3 shift LSRB rights to divide LSRB result by eight NORM GF 5 NEW GF save new value for trip use CMPB GF zis new GF larger BLS
123. T NIBBLE FOR gt 7 LHL HIGH BYTE LSN COMPLEMENT OF 7 FOR TEST RC ACSC FOR VALUE gt 7 GJMP CONV LESS THAN 7 CONTINUE CONVERSION CURRENT TOO HIGH SET VALUE TO 9999 LHU BCD4 BCD DATA STORAGE LAI 9 ST 210005 DIGT 9 POINT TO BCD DATA STORAGE 57 21005 DIGT 9 2 BCD DATA STORAGE ST 10S DIGIT 9 BCD1 POINTTO BCD DATA STORAGE ST iS DIGT 9 RT CONTINUE WITH COVERSION SUBTRACT 1000 UNTIL VALUE BECOMES NEGATIVE TO DETERMINE 10005 DIGIT RESET COUNT VALUE TO ZERO TAE THOUS RC CARRY POINTTO VALUE TO BE CONVERTED LOW BYTE LSN LAI 08 VALUETO BE ADDED FOR 1000 TO LOW BYTE LSN ACSC ADD VALUES NOP LHL TEMPI POINT TO TEMP STORAGE FOR CONVERTED VALUE ST TEMP STORE CONVERTED VALUE 5 136 458 179 180 72 POINTTO VALUE TO BE CONVERTED LOW BYTE MSN LAI OIH VALUE TO BE ADDED FOR 1000 TO LOW BYTE MSN ACSC sADD VALUES NOP LHLI 2 POINTTO TEMP STORAGE FOR CONVERTED VALUE ST STORE CONVERTED VALUE POINTTO VALUE TO BE CONVERTED HIGH BYTE LSN LAI BE ADDED FOR 1000 TO HIGH BYTE LSN ACSC ADD VALUES NOP POINT TO TEMP STORAGE FOR CONVERTED VALUE ST STORE CONVERTED VALUE 814 POINTTO VALUE TO BE CONVERTED HIGH BYTE LSN LAI VALUETO BE ADDED FO
124. TAA PACKET_PTR save to packet pointer for use BSET TRIP STATUS BYTE 82 set status byte NOW GO AHEAD AND SEND THE CHECKSUM dwst x SEND CHECKSUM LDAA SUM get the checksum ANDA 57 clear high bit JMP DO PARITY go check parity DO CHECKSUM EQU 5 value to send is transferred to ACCB then checksum value added to it and stored back for next calculation 5 136 458 117 118 FOR CHECKSUM TESTING ADDB CHECK SUM byte to checksum STAB CHECK SUM save result to checksum buffer DO_PARITY EQU 5 Temp holds the number of high bits for parity generation ACCB is set to 9 2 since all parity checking is done after checking for ACCB 0 CLR TEMP Clear locati n for checksum counting CLC clear carry for parity testing LDAB 09 set for 9 shifts PARITY CHK EQU 5 RORA bit zero in carry bit DECB we done all 8 bits BEQ PARITY SET 0 on 9th shift so parity is done PARITY this bit is a zero INC TEMP this bit is a one JMP PARITY CHK do all 8 bits PARITY SET EQU Parity bit is set or cleared here depending on the 0 bit of TEMP Bit 0 1 set parity bit bit 0 0 clear parity bit LDX REGSTART 76811 10 base address 1000 BRCLR TEMP l CLR P BIT is bit zero a 0 BSET SCCR1 X 40 no so set parity bit on JMP TRANSMIT CLR P BIT EQU 5 BCLR SCCR1 X 40 bits are even clear parity bit T
125. TD X SCL set clock line low LSLA shift high bit to carry LOW if carry is low branch BSET PORTD X SDA scarry is set so set data bit high JMP DEC B decrement bit counter DATA LOW EQU 5 BCLR PORTD X SDA carry was clear so clear data bit DEC B EQU 5 BSET PORTD X SCL set clock high to set in data DECB decrement byte loop counter BNE SET CLOCK if not 0 go send the next byte BCLR PORTD X SCL set clock low for acknowledge bit BCLR DDRD X SDA turn portd to input for ack bit LDAA a max wait LDAB SDA get mask WAIT FOR ACK EQU 5 DECA max time BEQ zif time out leave ANDB PORTD X read port d for ack bit BNE WAIT FOR EEPROM not ready yet NO ACK BSET PORTD X SCL set clock line high for acknowledge bit INY increment IY to next byte MEM RATIO first byte thats not history data BLO LOAD NEXT BYTE ready to write next byte 5 000 to address flag BLO SEND STOP 21 not address go send stop bite BCLR PORTD X SCL SDA 5 clock data lines low RTS return to address routine SEND STOP BCLR PORTD X SCL SDA set the clock low to prepare for stop command BSET DDRD X SDA zset data line to output BSET PORTD X SCL set clock biut high BSET PORTD X SDA set data bit high to signal stop BSET SPCR X 40 turn SPI on again RTS return to calling routine NUUS NAMUR se Se 5 Se Se Sa
126. TINE COMPARES TWO 4 BYTE VALUES IY POINTS TO FIRST 4 BYTE VALUE AND IX POINTS TO THE SECOND 4 BYTE VALUE ACCA RETURNS THE RESULT OF THE COMPARE AS FOLLOWS IF FIRST VALUE 2ND VALUE THEN ACCA 0 ON RETURN IF 15 VALUE gt gt 2ND VALUE THEN 2 ON RETURN 1ST VALUE lt lt 2ND VALUE THEN ACCAs 1 ON RETURN Ss ve Se Se COMP DBL WORD EQU 5 42 0 WORD OF 1ST VALUE cpp 0 WORD 2ND VALUE BHI SET HIGHER gt X SET HIGHER BLO SET LOWER X Y SET LOWER BIT HI WRD EQUAL EQU IDD 2 Y WORD OF 1ST VALUE BHI SET_HIGHER gt X SET HIGHER BIT WO CPD 2 LOW WORD 2ND VALUE SU BLO SET LOWER X gt Y SET LOWER LOW WRD EQUAL EQU 5 1ST AND 2ND ARE EQUAL RTS SET HIGHER EQU 5 LDAA 02 215 IS GREATER THAN 2ND RTS SET LOWER LDAA 580 1ST IS LESS THAN 2ND RTS CALC LT ACCUM THIS SUBROUTINE CALCULATES THE LONG TIME MEMORY CAPACITOR EQUIVALENT ACCUMULATOR VALUE THE LONG TIME DELAY SWITCH IS USED TO LOOK UP CORRECT MULTIPLIER FROM THE TABLE LOCATION IN IX T Sa ve e S e 4 4 o Se Te e THE MUL 16X16 SUBROUTINE IS USED FOR THE MULTIPLICATION THE RESULT IS PUT INTO A 4 BYTE RAM LOCATION CALLED RESULT CALLED WITH ACCX SET FOR EITHER LT OR FLC REBUILDING TABLE T ve EEECETTETEREEETEIEETET RESULT USED 03 92111 21 19 3
127. TO 1X4 AND 1X8 BIT BYTES LADR THMSN TEMPORARY DATA BYTES INTO ACCUMULATOR LHU HMSN HL TO ADDRESS OF PERM MEM LOCATION ST STORE THE ACCUMULATOR AT ADDRESS POINTED TO BY HL BT4 ST LADR THLSN ST LHL ST LADR TLMSN LHL ST BT2 ST LADR TLLSN LHL LLSN ST ST RT 5555555555555555555555555555555555555555555555555555555555555555555555655555 5 5 i AS DO AN ADDITION CALCULATION 5 i 5 5 5555555555555555555555955555555555555555555555555555555555555555555555565555 sADDITION SEQUENCE AS ACSC sACC C 4 ST STORE DLS DECREMENT DATA MEMORY POINTER RT BAR GRAPH DISPLAY CONTINUED LAI OAH OVERFLOW SET COUNTER TO TEN TAE TURN OFF ALL BAR SEGMENTS BO CALL BAROFF STURN ON ALL APPROPRIATE BAR SEGMENTS DES GJMP RT 18 888 8888888888888 88 8 8 8 5888 8 58 8 8 8 8 88 88 5 8 88 BB 8 88 BE amp ROM LOOKUP ROUTINE FOR LCD DATA CENTER OF CHAR amp amp amp amp 8 5 B 8 8 KEE GEEK 888 8 KEKE 6855088888888 B KK RRR REE Rc cR RR ORG 440H DCENT DB TEMP POINT TO TEMP STORAGE LAMT HL TEMPI RT 5 136 458 169 170 555555555555555555555555555555555555555555555555555555555555555555555555555 5 BARON TURN ON APPROPRIATE BAR SE
128. TORE B PHASE A D TO RAM CMPA LAST BPHASE to last BLS if lower or same don t mess STAA LAST BPHASE zif higher save new value DO CEE EQU 5 5 136 458 121 122 LDAA LOW GAIN A D C PHASE STAA PHASEC STORE C PHASE A D TO RAM CMPA LAST CPHASE to last BLS MEM RATIO 21 lower or same don t mess STAA LAST CPHASE if higher save new value THE VALUES LAST B CPHASE ARE LOW GAIN PASSED OUT WITHOUT 6x MULTIPLE THESE VALUES ARE USED ONLY IN SHORT TIME amp MULTIPLIED BEFORE USE RD MEM RATIO EQU LDAA ADR4 X READ MEMORY RATIO A D STAA RATIO 1 STORE MEMORY RATIO A D TO RAM dee ehe de e e e ee e de de de e de e e fede SPI IS TURNED OFF HERE e de e fe fe e e e e e e e de e e de de ie de de dede dex BSET DDRD X 3E set portD for all available outputs here BSET PORTD X SCL SDA set data clock lines high BRCLR GF FLAGS TURN DESENSE FINISH PORTD BSET PORTD X GF DESENSE OUT turn on the desense line FINISH PORTD EQU 5 5 BCLR 5 540 kill SPI and enable PORTD BRCLR IFLAGS TRIPPING I INSTANTANEOUS JMP WAIT FOR HI ATOD if we are tripping don t run INST I INSTANTANEOUS EQU BRSET INST FLAGS I TIMR BIT CHK TIMER if discriminator on timer i BRCLR INST FLAGS INST OFF I _ TIMER INST on check timer JMP WAIT FOR HI wait
129. TYPE IS SET TO PE No calling requirements reads and reports breaker type UPON RETURN ACCB is equal to 2x the breaker type If breaker type is PE then PE BRKR BIT is set in FLAGSS else PE BRKR BIT is cleared 55555555555555555555555555555555555555555555555555555555555555555555555555555 we oc ve READ BREAKER SW SET FOR PE BRKR SET 59 EQU LDAB ANDB BEQ CMPB BHI CMPB BEQ BCLR LDAB BSET EQU RTS 5 136 458 60 5 BRKR TYPE READ BREAKER TYPE SWITCH SWITCH_MASK mask unused bits SET FOR FE zif 0 default to PE 50 0C is DS breaker SET FOR PE zif gt 50 default type 508 PE is type 08 SET FOR PE set to _ FLAGSS PE BRKR clear PE bit in flags BRKR SET 5 1508 FLAGSS PE BRKR BIT get type for set PE b t in flags zall done return to calling routine 85555555555555555555555555555555555555555555555555555555555555555555555555555 PPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPP SET PHASEA PEAK TRY PHASE B TRY PHASE C SHORT TIME PRE CALCULATION FUNCTIONS ARE DONE HERE Only IY is not used for calculations in this routine CALLED With LAST A B and C PHASE holding RAW low gain A D valu RETURNS B and C PHASEX6 holding values to use for ST calculations EQU LDAA LDAB MUL CPD BLS STD EQU LDAA LDAB MUL CPD BLS STD EQU LDAA LDAB MUL CPD BLS STD FIND PEAK
130. USE OF TRIP AS SC TRIP SC TRIP CNT get of trips ANDA 63 imax trips to store 63 D to max of trips BHS SC clear count INC SC TRIP CNT zincrement of SC TRIPS JMP GLOBAL if high bit clear leave CLR SC CNT EQU 5 x CLR 5 TRIP clear counter for rollover GO GLOBAL EQU LDX REGSTART 5 136 458 91 92 LDAA 5 RESTR BIT OUT get value to turn on SC trip line PORTA X turn line on STAA TRIP FLAG save for trip outdicator display use BCLR TRIP CNT 40 cause of trip long time BCLR TRIP CNT S40 cause of trip phase unbal BSET SC TRIP CNT 40 cause of trip short circuit BCLR GF TRIP CNT 540 cause of trip gnd fault BCLR TRIP 540 cause of trip soft dog BCLR FLAGSS KILL WATCHDOG BIT inot a soft trip so kill bit LDY DELAY 2MS iget 2 mS delay JMP VT CHECK GO CHECK TRIP VOLTAGE H E C K 5 T 1 2 M S dee sedeo ode dee e ur n te CALLED Every 12 5 to Short Time peak function checks No preset conditions are required for calling Motor Protection shares part of the same routine to Clear its peak LRC values RETURNS Peak phase currents for all 3 phases are cleared ST PEAK is cleared GF desense and ST pick up are set or cleared as needed USED ACCA ACCB IX RESTORED NOTHING Me Se Se Se Se Sa Se va Se Ca 5e Se
131. VPU SCRIN 12 TRY CPHASE 5 OVPU 5 512 PHASB SQRT 0 Y TRY CPHASE SCRIN 02 5 PHASC SQRT 0 X CLEAR_SER_BITS OVPU_SCRIN 24 BITS SET 5 OVPU_SCRIN 24 PHASC SQRT 0 BITS SET OVPU SCRIN 04 ROUTINES e fe se le e e ie e cle je e e e e e in ie de e e ST ISQ IN e e de de de CALLED Every llmSec when a ST 172 in delay calculation is needed 1 1 zif in PU find phases BIT PHASE IN PU if gt 90 PU find phases clear all 90 amp PU bits zdone so leave TABLE LOCATION check 90 5 pu READ LONG TIME PU SWITCH mask off unused readings add offset directly to IX it to IY phase square root compare to pick up if lower no pickup set for A phase pick up go check next set 09 pu in communications get phase square root compare to pick up zif lower no pickup set for phase pick up go check next clear PU bits get value it if low do next phase set 09 pu in communications get A phase square root to pick up if lower no pickup set for A phase pick up 2 90 check next clear PU bits get value compare it if low do next phase set 09 pu in communications return to calling routine TIME ROUTINE S vssssodekeieeex START HERE RETURNS Returns with ST ACCUM increased by Ipeak 2 or nev
132. WE HAVE SHORT TIME INSTALLED IN TRIP SYSTEM BRCLR FLAGSS NO ST BIT SHORT TIME TEST PU IF BIT CLEAR CHECK FCR P U INSERT FOR SC PHASE BITS HERE IN CASE OF NO ST JM SHORT TIME NO ST SET SO DON T DO SHORT TIME SHORT ROUTINE TO TEST FOR SHORT TIME PICK UP SSSSSSSSSSSSSSSSSSSSSSSSSSSSS SHORT TIME TEST PU EQU 5 TEST SHORT TIME FOR PE BREAKER OR ALL OTHERS PU TBL set for usual brkr type FLAGSS PE 5 59 if bit set brkr type is PE LDX 5 PE PU TBL bit Was set so use the PE breaker table LDAB SENSOR get sensor size ANDB SWITCH MASK mask off unused bits 51 1A max sensor size BLS CHECK FOR PE2000 if less check for PE LDAB 1 load with max sensor 6 FOR 2000 200 5 512 compare to 2000A sensor BLO READ ST SW if lt 2000A sensor use normal LDX 5 20002 load 2000A table 512 to 2000A sensor BEQ READ ST SW if 2000A we have correct table LOX 5 2500 2500A load correct table 0 ST SW EQU 5 LDAB STPUSW load accb with ST switch ANDB SW POS mask off bit 0 ABX sw offset to x reg table position STX 5 TABLE POS save for use in 1195 routine O X get latest table value CED ST compare to ST peak BLO ST PICK UP gt table we have a pick up IF
133. WING CALLS ARE SUBA 7 STAA 07 5 JSR INST TABLE if serial isn t valid check LT memory sr de e e t fe ee e e e e e ie e je e c e e e e x 7 MS TIMER GET 17 MS TIMER 5 IT EXPIRED YET TIMER HAS NOT EXPIRED DONE EVERY 7MS RRKKKKKKKK reset timer ALL CALLS DONE CLEAR 7 MS TIMER read INST switches for interrupt use BRSET FLAGSS KILL SERIAL BIT CHECK LT MEMORY JSR SERIAL TPUT A CHAR TO DISP EVERY 12 MS EQU BRCLR LT FLAGS SET ACCUM BIT CHECK GTZ BIT LDX 97 RATIO IMP DO FIRST PASS CHECK_LT_MEMORY 5 136 458 51 52 if bit set first pass make sure we calculate LT accumulator CHECK GT2 BIT EQU BRCLR LT FLAGS LT GTZ BIT CHECK 11MS if LTA 0 check 64mS timer LDX RATIO TABLE DO FIRST PASS EQU 5 JSR 705 LT VOLTS ADJUST MEMORY DELAY CAP VOLTAGE Hi e e 3e se e fe e ie e e ee fe cie e END 5 MS CALLS e e e e e de dee deese 13 MS TIMER CHECK e e e e e e de ie cin cie e ne 4 Maximum current for communications Short Time 172 in is run and ST Peak Detectors are cleared on this time base CHECK 11MS EQU 5 11 5 G T 11 MS TIMER 11 HAS IT EXPIRED YET CHECK 12MS
134. armonics i e multiples of the fundamental frequency In practical implementations several factors affect the accuracy of the 5 calculation including the sample rate and the number of samples In the preferred embodiment the sample rate is 2 000 Hertz and at least 128 samples are taken before the current magnitude is estimated EE 2 Detecting The Presence Of A Ground Fault ground fault sensing toroid 508 magnetically adds the current signals from the input windings 540 542 544 and 546 to indicate whether or not a ground fault is present on lines 106 The toroid 508 is con structed with four identical input windings 540 542 544 and 546 one for each of the current transformers 510 512 and 514 and one for the neutral current path trans former 506 which is optional The toroid 508 has a single output winding 509 which provides a summed current signal The ground fault sensing toroid 508 includes another winding 550 to allow a test signal to be applied at termi nals 552 Using momentary switch 554 the test signal creates a pseudo ground fault for the tripping system The tripping system reacts to this pseudo ground fault 5 136 458 11 in the same manner as a true ground fault The test winding 550 is protected by a positive coefficient resis tor 556 that increases its resistance as it heats thereby limiting the current through it and the winding 550 The positive coefficient resistor is for example a
135. arry for 1 JMP ROTATE DATA 240 rotate data into CLRC BIT EQU 65 CLC clr carry to rotate 0 into RAM ROTATE DATA EQU ROL O Y rotate data into RAM pointed to by IY BCLR PORTD X SCL set the clock low DECB decrement bit counter BNE NEXT BIT snot 8 bits yet so get next bit THE ACKNOWLEDGE BIT IS SENT HERE BCLR PORTD X SDA data kline low BSET DDRD X SDA turn data to output BSET PORID X SCL set clock high to catch acknowledge INY increment the byte pointer MEM RATIO to lst non hysterical byte BHS STOP 1f all bytes recvd send stop bit BCLR PORTD X SCL the clock low BCLR DDRD X SDA return data line to an input JMP UNLOAD EE go get the next byte GO STOP EQU 5 BSET PORTD X SDA set data clk high for stop BSET SPCR X 40 turn SPI on again RTS all recalled so return READREADREADREADREADREADREADREADREADREADREADREADREADREADREADREADREADREADRERAD EE WAIT EQU RTS 5 A WAIT WHILE WAITING FOR E 2 ERASE TO TRIP COPCOPCOPCOPCOPCOPCOPCOPCOPCOPCOPCOPCOPCOPCOPCOPCOPCOPCOPCOPCOPCOPCOPCOPCOPCO This routine resets the microP onboard COP computer operating propperly CALLED With nothing preset to any conditions RETURNS With IX set to start of onboard registers ACCA equal to SAA e e je de e t de e e je je je e e t de de de de 33 4 4 ft e e e e e ee e e eee ee oe de e e je Fe e e vie de e e r
136. art to decay by approximately 63 2 every 5 4 min utes the time constant for the RC circuit 610 There fore after 5 4 minutes without current the voltage across the RC circuit 610 will be 36 8 of 2 5 v or 0 92 If the overload condition would occur again at this point the microcomputer 120 would power up and measure 0 92 v across the RC circuit 610 The mi crocomputer 120 would then initialize its internal cur rent accumulation to approximately 1896 0 92 v di vided by the maximum of 5 0 v of the pre programmed full trip delay time The accumulation calculations performed by the microcomputer are based on the formula N gt 10 where N the number of samples t time at discrete intervals determined by the accu mulation rate and I t the true RMS value of current through the breaker During a fault the trip unit will begin to sum the current squared value as soon as the current exceeds a predetermined level for a predetermined period of time the selected overload condition The electronic trip system will maintain an internal accumulation register to store a value that is proportional to the square of the current and that is incremented periodically based on the accumulation rate Assuming a constant fault level of current a fixed accumulation rate and a known con dition of the accumulation register at t 0 the value in the accumulation register will increase at a determinate rate and wi
137. bottom of RAM next 16 bit check 1 so error bit not set passed test for formatting up for transmit format set error bit store error return good or error set FFCO 7FFC2 4 6 2 0 FFD2 4 7FFD6 FFD8 FFDA 7FFDC 5 136 458 145 TOV INT FDB SOFTDOG INTERRUPT FFDE TOCS INT FDB SOFTDOG INTERRUPT FFEO TOC4 INT FDB SOFTDOG INTERRUPT FFE2 TOC3 INT FDB SOFTDOG INTERRUPT FFE4 TOC2 INT FDB SOFTDOG INTERRUPT FFE6 TOCl INT FDB 1 INTERRUPT FFE8 TIC3 INT FDB SOFTDOG INTERRUPT FFEA TIC2 INT FDB SOFTDOG INTERRUPT FFEC TICl INT FDB _ SOFTDOG INTERRUPT FFEE RTI INT FDB SOFTDOG INTERRUPT FFFO IRQ INT FDB SOFTDOG_INTERRUPT FFF2 XIRQ INT FDB SOFTDOG_INTERRUPT FFF4 SWI INT FDB SOFTDOG INTERRUPT 6 ILLEGAL OP INT FDB SOFTDOG_INTERRUPT COP FAIL INT FDB SOFTDOG INTERRUPT FFFA CLOCK FAIL INT FDB 5 INTERRUPT FFFC RESET VECTOR FDB INITIALIZE FFFE END APPENDIX B SERIES IIl TRIP UNIT ADD ON AMMETER MODULE LUSTING 12 21 88 ASSEMBLER NEC 5 75 DESIGNER ANDY HAUN SQUARE D PART NO 48155 166 01 146 ORG 00H NNIMAUZE THE SYSTEM ONLY DONE AT START UP INITIALIZE MEMORY RESET LA LHLI RI ST DLS GJMP RI LAI OBH INITIALZE STACK POINTER TAMSP ST POWER UP IN PHASE LAI XADR I
138. ccumulation rate in seconds predetermined final accumulation value and I the true RMS value of current flowing through the breaker D Reset Circuitry Referring now to FIG 8 an expanded view of the reset circuit 124 is shown to include a power up reset circuit 710 and a watch dog circuit 712 to maintain the integrity of the tripping system 100 The power up reset circuit 710 performs two functions both of which occur during power up it provides a reset signal asserted low on line 743 to maintain the microcomputer 120 in reset condition until the tripping system 100 develops sufficient operating power from the current lines 106 and it provides a reset signal asserted low via lead 744 to the watch dog circuit 712 to prevent the watch dog circuit from engaging the solenoid 112 during power up This latter function prevents nuisance tripping Preferably the power up reset circuit includes an under voltage sensing integrated circuit 745 that detects whether or not the output voltage of the 5 volt supply is less than a predetermined reference voltage at which the microcomputer 120 in FIG 1 may properly func tion The integrated circuit 745 is for example part No MC33064P 5 which holds the reset line 743 low until the output voltage of the 5 volt supply rises above 4 6 volts The microcomputer 120 may operate at 4 5 volts or above The preferred reset circuit also includes a pull up resistor 741 a capacitor 739 and a
139. ces 151 and 191 may be implemented using the SCI and SPI ports internal to the MC68HC11 The history 0 5 20 25 30 35 40 45 50 60 65 18 of the tripping system status information is stored in the nonvolatile trip memory 144 That history includes the specific cause and current level of the last trip and a running accumulation of the different trip causes The trip memory 144 is preferably an electrically erasable programmable ROM for exam ple a 24 041 available from Xicor Inc of Milpitas Calif In this case the serial peripheral interface 191 is used for bidirectional data transfer between the mi crocomputer 120 and the EEPROM 144 This data transfer is implemented using one line of the serial pe ripheral interface 191 to transfer the data and the other line to transmit a clock signal between the microcom puter 120 and the EEPROM 114 for synchronization During power up of the tripping system 100 the mi crocomputer 120 transmits to the trip memory 144 a unique bit pattern which is interpreted as a data request code The microcomputer 120 then sets the bidirec tional data line as an input and clocks the requested data in from the trip memory 144 The microcomputer 120 maintains a copy of the his tory data in its internal RAM and in the event of a trip updates it and transmits it back into trip memory 144 via the interface 191 again utilizing the unique bit pattern to set data
140. ck 388 the bar segments 324 and 332 335 of FIG 3a are driven by the display processor in response to this determination From block 388 flow returns to block 378 Blocks 400 406 of FIG 35 represent a second inter rupt routine which the display processor may be pro grammed to execute in response to the depression of the switch 311 At block 400 of this second interrupt rou tine the display processor determines which phase or ground fault current the operator has selected by de pressing the switch 311 At blocks 402 and 404 the display processor monitors its I O port to determine when the switch 311 is released and to debounce the signal received from the switch 311 At block 406 the display processor executes a return from interrupt com mand It should be noted that the display processor 316 is optional for the local display 150 and therefore not required for its operation Further the local display 150 is itself an option to the tripping system and is not re quired for operating the tripping system B Current and Ground Fault Detection FIG 4 illustrates an expanded view of the analog input circuit 108 the ground fault sensor 110 the power supply 122 and the gain circuit 134 of FIG 1 Each of these circuits receives power from the three phase cur rent lines 106 Using this power these circuits provide signals from which the tripping system 100 1 deter mines the phase and current levels on lines 106 2 detects t
141. d to byte boundary DECB make type 0 1 2 3 4 5 i BLE READ_SW_IN_REG Y MULT_BY_TWO EQU lt MUL MULTIPLY FIND CORRECT ROW FOR BREAKER TYPE ABX add breaker offset to x register read and calculate the switch position to add to the x resgister READ SW IN REG Y LDAB 0 read the switch value ANDE SW POS MASK OFF BIT 0 BRSET FLAGSS WRD ALIGN BIT NOT DBLWRD IF SET BRANCH 6 DON T SHIFT LSLB 2 word boundary NOT_DBLWRD 5 ADD TO INDEX X TO POINT TO CORRECT VALUE RTS GO HOME STISTISTISTISTISTISTISTISTISTISTISTISTISTISTISTISTISTISTISTISTISTISTISTISTI ADJUST LT VOLTSADJUST LT VOLTSADJUST LT VOLTSADJUST LT VOLTBADJUST LT VOLTS PX ROG CR RAO ADJUST VOLTS Se RRR THIS SUBROUTINE CALCULATES THE LONG TIME MEMORY ACCUMULATOR VALUE THEN COMPARES IT TO THE LONG TIME ACCUMULATOR AND ADJUSTS THE VOLTAGE ACCORDINGLY turns portD bit 5 on or off THIS ROUTINE IS CALLED WITH INDEX X SET FOR FLC OR LT RATIO or on power up to 978 ratio tables 54 44 v a Se 5e Se c o If SET ACCUM BIT is set we have powered up with a voltage the LT FLC memory cap and the LTA is restored RESULT is used to return accumulator value from memory cap 7 4 ADJUST FLC VOLTS EQU ADJUST SIT VOLTS EQU 5 BRCLR LT FLAGS SET ACCUM BIT ACCUM ALREADY SET If SET ACCUM BIT is high then we need to reconstruct LT FLC accumu
142. dede e NO MORE INTERUUPTS PLEASE stroeb SD CLEAR TRIP CAUSE CAUSE OF TRIP AS gf TRIP clear max phase get of trips trips to store check for max trips clear count increment of SC TRIPS set up for jump to global trip Clear counter for roilover get value to turn on GF trip line turn line 5 136 458 101 102 STAA TRIP FLAG for display BCLR LT TRIP CNT 40 cause of trip long time BCLR TRIP CNT 40 cause of trip phase unbal BCLR 5 TRIP CNT 40 cause of trip short circuit BSET GF TRIP CNT 40 cause of trip gnd fault BCLR SOFT TRIP CNT 40 cause of trip soft dog BCLR FLAGSS KILL WATCHDOG BIT not a soft trip so clr kill bit LDY amp DELAY 32MS 32mS delay JMP VT CHECK GO CHECK TRIP VOLTAGE de he e qe de de e e he de dede te ede de de dde CHECK GF 13MS ft fe e de e he te de det cde fe dee dede de e e fe de ie e he e ede ee e CALLED Every i3mSec from main or motor flow code RETURNS GF peak cleared set cleared as appropriate communicatiions bit set cleared as needed and sleeps 1 2 ovt timer if needed 2254 74 78 56 gt e c5 38 gt u USED RESTORED NOTHING 1 1 1 de e eve ee e e e e dn 777 de e e defe e de eee ie e e e e de e cfe e e e e e e de dee defe f ode e e e de dee e de ede dede dee HECK GF 13MS EQU 5 L
143. ding circuit 130 to enhance system dependability System dependability is further enhanced through the use of a thermal memory 138 which the microcomputer 120 interacts with to simulate a bi metal deflection mechanism The thermal memory 138 provides an accu rate secondary estimate of the heat in the tripping sys tem 100 in the event power to the microcomputer 120 is interrupted The ground fault sensor 110 is used to detect the presence of ground faults on one or more of the lines 106 and to report the faults to the microcomputer 120 Using user selected trip characteristics the microcom puter 120 determines whether or not the ground fault is present for a sufficient time period at a sufficient level to trip the contactors 114 The microcomputer 120 accu mulates the ground fault delay time in its internal RAM A RAM retention circuit 140 is used to preserve the ground fault history for a certain period of time during power interruptions The RAM retention circuit 140 exploits the built in capability of the microcomputer 120 to hold the con tents of its internal RAM provided that an external supply voltage is applied to its MOPDB Vstby input 141 This external supply voltage is stored on a 150 microfarad electrolytic capacitor 143 that is charged from the 9 volt supply through a 6 2 K ohm resistor 145 The capacitor 143 is charged from 9 volt supply and clamped by diodes to the 5 volt supply so that the capacitor will be ra
144. diode 753 connecting the integrated circuit 745 to the watchdog circuit 712 The resistor 741 for example has a value of 47 K ohms and the capacitor 739 has a value of 0 01 microfarads The diode 753 ensures that the reset circuit 710 affects the watchdog circuit 712 only when the microcomputer 160 is being reset The watch dog circuit 712 protects the tripping sys tem from microcomputer malfunctions Thus it is de signed to engage the solenoid 112 if the microcomputer 120 fails to reset the watch dog circuit 712 within a predetermined time period The microcomputer 120 resets the watch dog circuit 712 by regularly generating logic high pulses preferably about every 200 millisec onds on lead 714 These pulses are passed through a capacitor 718 to activate an IGFET transistor 720 which in turn discharges an RC timing circuit 724 through a circuit limiting resistor 733 A resistor 730 5 136 458 17 and clamping diode 732 used to reference pulses from the capacitor 718 to ground The pulses on lead 714 prevent the RC timing circuit 724 from charging up past a reference voltage Vref at the input of a comparator 726 If the RC timing circuit 724 charges up past Vref the comparator 726 sends a trip signal to the solenoid 112 to interrupt the current path in lines 106 The reference voltage for example is provided by a 4 3 volt zener diode 427 supplied with current through a resistor 729 Preferred component values ar
145. down portA outputs for successful output compares eeexieeee STAA don t set any bits in reg 1 for compares p kx shut down output compares for TOC2 thru TOCS STAA 1 output compare 2 5 are not used shut down input captures for thru TIC4 ssec 2 disable input capture 5 136 458 33 34 LDAA 580 STAA TMSK1 X allow only timer 1 output compare interrupts LDAA TFLG1 X read the interrupt flag register STAA TFLG1 X store to clear any pending timer interrup de ehe de ie je jede e mask off alil TFLAG2 interrupts c ie fe e he e ne e he e e de de je je dete CLR TMSK2 X off all TFLG2 interrupts CLR TFLG2 X turn off unwanted interrupts LDAA 580 STAA PortA bit 7 is set for output pulse accum o LDS END set stack at end of kkk FINISH SETTING REGISTERS UP HERE t e e e defe e e ee qe e e dee e ie 1 SET UP TEE ATOD FOR LOW GAIN CHANNEL ZERO SET A D TO 30 HEX HIGH GAIN amp GROUND FAULT 1 SET A D TO 34 HEX FOR LOW GAIN amp MEMORY DELAY BSET ADCTL X 34 start a conversion for 155 reading w MEM CHECK FOR PRODUCTION TEST DESIGNATOR HERE RATING PLUG DESIGNATOR LDAA RATING PLUG RP value ANDA 51 mask RP designator bits CMPA PROD TEST DESIGNATOR to prod
146. e THIS ROUTINE SETS THE PEAK RMS OF THE THREE PHASES CALLED No values passed uses square root memory values RETURNS With PEAK SORT holding maximum square root value 54 9 Se To USES IX RESTORES Nothing FIND SQRT PK EQU LDX 5 A phase root 5 SQRT compare it to B phase BRS CHECK PHASEC if is high or branch LDX SORT else load B phase CHECK PHASEC PHASC SQRT to C phase BHS STORE_NU_PEAK if current double still high go store it LDX SQRT else get phase C current STORE NU PEAK EQU 5 STX PEAK SQRT store double to SORT PEAK RTS RETURN WITH DATA e e de e e e e dee dede de e eie de dede de LT FLC SW COMM ft le sir ir fe de e e 1 fe e dee efe dee e fe de de dede THIS SECTION DOES THE COMMON SWITCH COMMUNICATIONS FOR LT amp FLC SWITCHES CALLED No variables passed to routine RETURNS LT SWITCHES set to Long Time PU amp delay values USES ACCA ACCB RESTORES NOTHING e de de e 777 ee de e e e e de ee t c c ee ee e e e e n ede de do e de dde d de 4 va Se LT FLC SW COMM EQU LDAA LTPUSW get PU position ANDA SW POS mask off unwanted bits LSRA zshift to low 3 bits LDAB LTDELSW get delay switch value MAX_SW_POS off unwanted bits LSLB shift to high 3
147. e for example 0 001 microfarads for capacitor 718 27 K ohms for resistor 730 part No 1N4148 for diode 732 part No BS170 for transistor 720 10 ohms for resistor 733 820 K megohms for resistor 737 0 22 microfarads for capacitor 735 part No LM29031 for comparator 726 part No 1N4687 for diode 727 100 ohms for resistor 729 and 10 ohms for resistor 751 E User Select Switches As introduced above the user select circuit 132 is illustrated in FIG 9 In addition to the buffer 820 for the rating plug the user select circuit 132 includes a plural ity of user interface circuits 810 each having a pair of BCD dials 812 and a tri state buffer 814 which is en abled through the address and data decoder 130 of FIG 1 Each BCD dial 812 allows the user to select one of several tripping system characteristics For example a pair of BCD switches may be used to designate the longtime pickup and the longtime delay overload trip ping characteristics and another pair of BCD switches may be used to designate the short time pickup and the short time delay short circuit tripping characteristics Other BCD switches may be used to designate sensor and breaker sizes an instantaneous pickup ground fault tripping characteristics and phase unbalance thresh olds F Energy validation For Solenoid Activation The user select circuit 132 of FIG 1 and 9 also deter mines if there is sufficient energy to activate the sole noid 112 Using t
148. e 54 se ve va ta n 5 136 458 82 RETURNS With any Long Time pick up flags set RESTORES nothing READ LT PU SW SETTING MASK OFF BIT ZERO SET X TO OFFSET IN LT PU TABLE FOR LAST 64 MS TO TABLE SW POSITION IN PICK UP STATE CLEAR PU STATE X TO POINT 90 PU TBL SAVED LT SWITCH VALUE ACCB IS SW INDEX RELOAD PEAK SQUARE ROOT TEST FOR 90 PICK UP WE ARE IN 905 PU STATE CLEAR 90 PU BIT ALL DONE SPARKY LT FLAGS LT PU BIT SET STATE TO LT PICK UP SET LT ACCUM gt ZERO IF 100 STATE CANT T BE IN 90 set index to start of 6811 registers we have pick up so set led on X REGISTER FOR MULTIPLY Y REGISTER FOR MULTIPLY SQUARE THE RMS ROOT GET THE I SQUARE LOW WORD X POINTS TO LT ACCUM ADD I 2 TO LT ACCUM HI WORD OF CURRENT SQUARED ADD HI WORD OF LT ACCUM STORE IN HI WORD OF LT ACCUM DELAY TABLE START ADDRESS IN X LT DELSW ADDRESS IN Y MULTIPLY BY 32 5 SHIFT LEFTS CLEAR BIT 1 FOR DBL WORD INDEX CREATE 4 BYTE INDEX POINTER 15 COMPARE VALUE IN Y COMP THE DOUBLE WORDS IF ACCA 0 TIME TO TRIP LT ACCUM gt gt TABLE DELAY VALUE ARE STILL ALIVE 790 PICK UP SEQUENCE STATE TO 90 PICK UP 81 p USES ACCA ACCB IX IY TEMP USED RESULT USED LONG TIME LDX PU TBL LDAB LTPUSW ANDB SW POS STAB TEMP ABX LDD
149. ear soft dog timers STD SOFT DOG TIMERl clear 15 softdog timer STD SOFT DOG TIMER2 2nd soft timer LDAA 5 set high bit to indicate no soft errors STAA SOFT DOG CNIR Clear soft error counter C de eo doe Fe de e e kc e e de e ee c c e e e e e e e e e e e e e e ee de oe e de dee e de e dede de de e dei e o de ede es de dee ee ALL INTERRUPTS EXCEPT RESET AND TIMER 1 JUMP TO THIS POINT s ANY INTERRUPTS OTHER THAN RESET AND TIMER 1 ARE ERRORS d sew ww INIT 1 EQU 5 uCONTROLLER REGISTERS SET UP HERE LDX REGSTART set x to point at bottom of registers LDAA 589 set softdog to 65 mSec reset time STAA powerup A D section amp clock monitor wait 100uS before doing A D LDAA 528 HPRIO X CLR PORTD X LDAA 53 STAA DDRD X highest priority interrupt Clear PORT D output bit enable PORT D as output to charge MEM DEL CAP amp turn on DESENSE 5474 LDAA 903 STAA PIOC X set up parallel I O registler not used in expanded LDAA 530 STAA BAUD X set for 9600 baud LDAA 550 STAA 5 for 9 data bits 1 start 1 stop bit LDAA 4508 5 SCCR2 X enable transmit mode on the sci LDAA 1 sets SPI for master idle high data true on STAA 5 125KHz amp set up SPI but don t turn it 00 clear to shut off P shut
150. ect the phase current to be displayed on the LCD display 322 and to control segments 375 such that they identify the phase current A B C or N on lines 106 being dis played on the four seven segment digits 317 For this purpose the switch 311 activates a transistor 327 to invert a signal provided from the battery and to inter rupt the display processor 316 Each time the display processor 316 is interrupted the phase current that is displayed changes for example from phase A to B to C to ground fault to A etc An optional bar segment 324 is included in the LCD display 322 to indicate a percentage of the maximum allowable continuous current in the current path The bar segment 324 is controlled by the 5 V signal viaa separate LCD driver 330 The LCD driver 330 operates in conjunction with the oscillator circuit 328 in the same manner as the LCD driver 326 However the LCD driver 330 and the oscillator circuit 328 will function at a relatively low operating voltage approximately two to three volts An MC14070 integrated circuit available from Motorola Inc may used to implement the LCD drivers 330 and 326 Thus when the tripping system fails to provide the display processor 316 with sufficient operating power or current the LCD driver 330 is still able to drive the bar segment 324 The LCD driver 330 drives the bar segment 324 whenever the tripping system detects that less than about 2090 of the rated trip current is being carried
151. ector 310 be cause the connector 310 provides the ground connec tion for the negative terminal of the battery 338 This aspect of the local display 150 further prolongs battery life and therefore minimizes system maintenance In FIG 36 a flow chart illustrates the preferred pro gramming of the display processor 316 The flow chart begins at block 376 where the memory internal to the display processor is initialized The memory initializa tion includes clearing internal RAM inputoutput ports and interrupt and stack registers At block 378 software timer is reset and display processor waits for a data ready flag which indicates that data has been received from the microcomputer 120 of FIG 1 The software timer provides a conven tional software watchdog function to maintain the san ity of the display processor If the software timer is not reset periodically within a certain time interval the display processor resets itself The data ready flag is set in an interrupt routine illustrated by blocks 390 through 398 of FIG 35 The display processor is programmed to execute the inter rupt routine when it receives data from the microcom puter 120 of FIG 1 At block 390 of the interrupt rou tine a test is performed to determine if the data byte just received is the last data byte of the packet sent from the microcomputer If the data byte just received is not the last data byte flow proceeds to block 398 where a tur
152. ent Low Byte Packet 5 0101 Data Byte 1 Software Failure Trips Data Byte 2 Last Phase A Current High Byte Data Byte 3 Last Phase A Current Low Byte Data Byte 4 Last Phase B Current High Byte Data Byte 5 Last Phase B Current Low Byte Packet 6 0110 Data Byte 1 Last Fault System Status Byte Data Byte 2 Phase C Current High Byte Data Byte 3 Last Phase C Current Low Byte Data Byte 4 Last Ground Fault Current High Byte Data Byte 5 Last Ground Fault Current Low Byte Packet 7 0111 Data Byte 1 Long Time Memory Ratio Data Byte 2 Phase A 95 Unbalance Data Byte 3 Phase B Unbalance Data Byte 4 Phase Unbalance Data Byte 5 Software Version Identifier Byte Accordingly the microcomputer 120 transmits infor mation in four substantive classes The first class consti tutes trip status information as set forth in the first byte of each packet The second and third classes involve current measurement information the second class in cluding current measurement information on each line 106 as set forth in packets 0 and 1 and the third class including the maximum current status information as Data Byte 4 Ground Fault Current Low Byte set forth in packet 2 The last class of information relates Data Byte 5 Short Circuit Phase Unbalance amp Ground Fault to the present configuration of the tripping system and Pickups 40 is contained in packets 3 through 7 acket 2 0
153. er returns and trips the breaker USED ACCA ACCB IX amp IY S 5 PEAK ST PEAK SQUARE 5 POINT TO LATEST PEAK PHASE IN X TO LATEST PEAK PHASE IN Y RE MULT X TIMES Y eo 5 136 458 9 2 90 LDX 57_ SET X REG TO ST ACCUMULATER RESULT 2 GET LOW WORD OF I SQUARE RESULT JSR 4 ADD ADD I 2 TO 4 BYTE ST ACCUMULATER LDD RESULT WORD OF I SQUARE ADDD ST ACCUM ADD HI WORD OF ST ACCUM STD ST ACCUM PUT RESULT IN ST 1 ACCUM BRCLR ST FLAGS DOUBLE 51 I2 BIT CALCULATE ST_TRIP px rx double bit not set don t double 172 addition BCLR ST FLAGS DOUBLE ST I2 clear before rerun 172 DOUBLE FOR INIT 7 double 172 accumulation CALCULATE_ST_TRIP LDX 457 150 DEL X REG TO ST I 2 DEL TABLE LDY STDELSW 5 Y REGISTER TO ST DELAY SW LDAA 32 MULT BY 16 SHIFT LEFT 4 BCLR FLAGSS WRD_ALIGN_BIT FOR DBL WORD BOUNDARY REQUEST JSR SET_TBL_INDX CALL TABLE INDEX ROUTINE LDY ST ACCUM 71ST COMPARE VALUE Y JSR COMP DBL WORD COMPARE ST ACCUM TO DELAY TABLE 00 BGE ST TRIP 5 ACCUM gt TABLE DELAY RTS RETURN FROM ST I 2 CODE TO MAIN 5 H R T T 1 M E T R I P secre ie e e e fe fe fe de e e he e e e e e ede e dn e dn doe CALLED From any SHORT TIME routine that needs to generate a trip INST amp LRC call the pertion of this routine that starts
154. ers time out the ST will be reset to norm values RESET INST EQU set up to reset INST function after 100 mSec have passed ide e d de de ie dex xx JSR GET_INST_TABLE read INST switches for interrupt use LDAA 100 set time before resetting inst timer STAA INST RESET TIMER set time to reset INST timer Historic data is read from the EEPROM before SPI is enabled JSR RESET reset to finish out bad data JSR ADDRESS WEE address the EEPROM for talking JSR READ read the EEPROM into RAM 5 136 458 39 40 Turn on SPI and set up the micro to start runnung breaker code LDX REGSTART SET 6811 INTERNAL REGISTERS AT 1000 HEX LDAA 55 this turns SPI on at 125kHz and as master STAA SPCR X turn it on LDAA TFLG1 X LOAD AND STORE TIMER INTERRUPTS STAA 1 CLEAR ALL INTERRUPTS LDD TCNT X get timer count ADDD 1000 1000 Susec 500usec interrupt STD TOC1 X 1 back into output compare register 1 BSET 5 1 580 sallow output compare register 1 interzupt CLI enable all interrupts H END ALL INITIALAZION FOR SERIES III 888 e ewe eee de ede de dede dee dee 2 10 PSUEDO CODE FOR MAIN MAIN FLOW IF GROUND FAULT PICKUP GF RESTRAINT TIMER 14 MS CIRCUIT PICKUP ST RESTRAINT TIMER 10 MS CHECK FOR ST IF 2MS ST TIMER gt 2 2MS ST TIMER 2MS ST 2 SET PHASEA PEAK
155. es are run 5 136 458 57 58 CHECK 1 SEC EQU LDAA T 1000MS LOAD 1 SEC TIMER 4 250 mS 1 Sec 4 IS IT DUE YET BLO CHECK TIMR IS NOT DUE SUBA 4 reset the timer T 1000MS timer back to memory JSR SENSOR BREAKR prepare sensor breaker for xmit buffer BRSET SOFT DOG 580 TIMR 0 21 no soft errors do timer checks JSR SOFT DOG decrement 10 min softdog timer CHECK TIMR Q e Yol dede ded de Rea dedo Re JR XII CR I ko dede o TEST FOR ANY VARIABLE MS TIMERS THAT HAVE EXPIRED RR RRA IHR IRR EEE e BE IE E DE e RIE IE E PE IE IE JSR 11 TIMERS check mSec timers JMP MAIN FLOW CONTINUE MAIN EXEC FLOW 555555555555555555555 END MAIN EXEC FLOW 555555555555555555 TTTTTTTT THIS SECTION CHECKS mSEC TIMERS FOR ANY THAT ARE DUE ACCA and IX do not have any guaranteed values upon exit of this routine ACCA amp IX are used to load timer values for timer due checks If any routines are called ACCB and IY may also be destroyed die e e t de de fe e e de fe e e oe de de de e d 23232322 e e e e de de e Se ede e e e e c ee ee ec e oce e e e e e de e CHECK ALL TIMERS EQU 5 oc Ss LDAA INST RESET TIMER timer to reset inst timer BNE R_U_RESTRAINED igo check SC rest
156. ff high nibble clear high byte of ADDD REMAINDER low nibble to the remainder LDX RMS SQROOT get divisor IDIV divide LSLD multiply remainder by 2 RMS_SQROOT 15 2xREMAINDER gt divisor BLS INC no don t increment quotient INX increment the quotient NO INC EQU 5 XGDX quotient ADDD RESULT finish result ADDD RMS SQROOT guess to quotient LSRD divide by 2 CPD RMS SQROOT 1 same we ve found the root BEQ QUIT 11 done quit LOX RMS SQROOT the original divisor STD RMS SQROOT store last iteration XGDX move old root into SUBD RMS SQROOT find the difference between old amp new ADDD 0001 1 to allow 1 bit difference 0002 15 result lt 2 BLS QUIT d if so we re close enough JMP SQRCAL otherwise try again QUIT EQU 5 PULX restore LDD 0000 get value to clear STD 0 Clear high word of squared sums STD 2 X clear low word RTS SQUARE ROOT ROUTINE fe e efe he defe e e le e je e he e e t e e e fe fe ede e fe e e d dee e ROUTINE CONVERT DATA FROM GF TO PHASE VALUES sxsdeks ek 2 CALLED From GF communications routine to begin conversion of data frs raw A D format to serial comm format RETURNS This routine goes to the I CONVERSION routine to finish HN converting from A D values to serial format values Passes GF CURRENT to next ro
157. for hi gain A D I TIMER BRCLR INST FLAGS I INST PU timer so check PU IF WE GET HERE THE TIMER MUST BE ACTIVE LDAA INST TIMER get INST timer DECA sub 1 ms from inst timer BEQ RESET TIMER timer 0 so reset INST function STAA INST TIMER get timer for compare 290 zis inst timer above 90ms BLS CHK INST PU so check for INST PU CLR INST _CNTR_4 reset inst pick up count JMP WAIT FOR HI ATOD so forget instantaneous IF TIMER IS 0 RESET INST TIMER TIMER FLAG AND PICK UP COUNTER RESET TIMER CLR INST CNTR 4 reset inst pick up count LDAA 2 100 RESET VALUE FOR INST TIMER STAA INST TIMER reset inst timer to 100 ms BCLR INST FLAGS I TIMR BIT make timer not active THIS SECTION GETS THE INST PU LOCATION FROM MEMORY STORED POINTERS CHK INST PU EQU LDX 5 TABLE VAL get table row amp column in IX LDAA 1 INST PU value in ACCA for compare 1 PHASEA to phase BLS INST PICK UP if phase current greater we have P U 1 PHASEB to B phase BLS INST PICK UP if phase current greater we have P U PHASEC E compare to C phase BLS INST PICK UP 216 phase current greater we have CLR INST CNTR 4 reset inst pu counter BCLR INST FLAGS INST PU clear inst pu bit JMP WAIT FOR ATOD GO wait for A
158. ging packet 2 tripping so only send packet 2 tripping so only send packet 2 to byte 0 checksum to start again send first byte to tell of trip check for UTS mask unused bits to tester RP if tester or UTS don t write to EE reset the softdog timer ALL THE CURRENT DATA BEFORE WRITING TO EEPROM POINTER FOR CURRENT get historical data pointer get current data store it to history is 16 bit word add to pointer add to pointer to odd byte see if all data xfered go past odd byte to me too are we pointing past the last byte no move next word load max peak of phases get phase causing trip max current mask for trip phases only compare for GF trip cause strip not caused by GF trip so save it to historical data store to EEPROM saved RAM phase bits phases gt ovid mask all but ovid save it SC pick up phases maskall but SCPU combine SC amp ovld saved onboard reg locations read restraints mask for restraint lines for restr no active restraints both high no restr set bit restraint is off the EEPROM for listening go write to EEPROM 240 reset the TURN INTERRUPTS BACK ON get max phase to send mask off unwanted data zis this GF no GF don t do prebyte multiply go d
159. he address and data decoding circuit 130 the buffer 820 is selected to read one of its input lines 830 The signal from the power supply 122 of FIG 1 feeds the input line 830 with the buffer 820 being protected from excessive voltage by a resistor 832 and a cl mping diode 834 The resistor 832 for example has a value of 620 K ohms Before the microcomputer 120 engages the solenoid 112 the input line 830 is accessed to determine if VT is read as a logic high or a logic low The buffer 820 pro vides a logic high at its output whenever the input is greater than 2 5 v to 3 v If VT is read as a logic high the microcomputer 120 determines that there is suffi cient power to activate the solenoid 112 and attempts to do so If VT is read as a logic low the microcomputer 120 determines that there is insufficient power to acti vate the solenoid 112 and waits while repeatedly checking VT in anticipation that an intermittent power fault caused VT to fall Once VT rises beyond the 2 5 3 0 volt level the microcomputer 120 attempts to activate the solenoid once again G Communication For Information Display microcomputer 120 sends identical tripping sys tem status information to the local display 150 and the display terminal 162 The information is sent synchro nously on a serial peripheral interface 191 to the local display 150 and asynchronously on a serial communica tion interface 151 to the display termina 162 The inter fa
160. he electronic cir cuitry being powered by the 9 V power supply to remain powered for some time after a trip occurs A capacitor 574 connected at the emitter of the transistor 568 aids in filtering voltage ripple The capacitor 574 is also utilized as the energy storage element for the sole noid 112 which is activated when a power IGFET 583 is turned on by trip signals from the microcomputer 120 in FIG 1 or from a watchdog circuit 712 in FIG 8 The trip signals are combined by respective diodes 591 593 The solenoid 112 is also activated by an over voltage condition sensed by a 16 volt zener diode 595 such as part No 1N5246 Preferred component values are for example 220 microfarads for capacitor 574 100 microfarads for capacitor 584 10 microfarads for ca pacitor 582 100 K ohms for resistor 585 10 K ohms for resistor 589 0 1 microfarads for capacitor 587 and part No 6660 for IGFET 583 Diodes 576 and 578 are used to receive current from an optional external power supply not shown 4 Establishing The Current Rating On the left side of the rectifier bridges negative phase signals A B and C from the bridges are provided to the burden resistor arrangement 530 including a rating plug 531 to set the current rating for the tripping sys tem As previously discussed when the primary current is 100 of the rated current or sensor size which is designated using the user select circuit 132 the current transfo
161. he presence of any ground fault 3 provides system power and 4 establishes its current rating 1 Determining Phase and Current Levels In FIG 4 the analog input and ground fault sensing circuits 108 and 110 include current transformers 510 512 and 514 that are suitably located adjacent the lines 106 for receiving energy from each respective phase current path A B and C Each current transformer 510 512 and 514 is constructed to produce a current output that is proportional to the primary current in a fixed ratio This ratio is set so that when the primary current is 100 of the rated current transformer size or sensor 5 136 458 9 size the current transformer is producing a fixed out put current level For example for a 200 Amp circuit breaker each current transformer 510 512 and 514 will produce the same current output signal when operating at 100 200 Amps as a current transformer in a 4000 Amp circuit breaker which it is operating at 100 4000 Amps The preferred construction yields a current transformer output current of 282 8 milliamperes RMS when the primary current is 100 of the rated current The output currents provided by the transformers 510 512 and 514 are routed through a ground fault sensing toroid 508 full wave rectifier bridges 516 518 and 520 and the power supply 122 to tripping system ground The output currents are returned from tripping system ground through a burden resistor arrangement 530
162. heet 6 of 10 5 136 458 0 0 2 5 5 0 7 5 10 0 12 5 150 175 200 225 TIME ms FIG 5 1 5 Patent Aug 4 1992 Sheet 7 of 10 5 136 458 siete Gea 5 136 458 Aug 4 1992 U S Patent Sheet 9 of 10 5 136 458 4 1992 U S Patent g Ww noui 424 814 ibh a et 64 esz 21 90200100 13538 6 900H21VM p 4 024 01 13538 192 4 bbl 64 bel 20940 L AS a n A6 d OI y VERRE 04 _ Aug 4 1992 Sheet 10 of 10 5 136 458 U S Patent b 913 O G 01 W033 5 136 458 1 MICROCOMPUTER BASED ELECTRONIC TRIP SYSTEM FOR CIRCUIT BREAKERS TECHNICAL FIELD The present invention relates generally to circuit breakers and more particularly to processor con trolled trip arrangements for circuit breakers BACKGROUND ART Trip systems are designed to respond to power faults detected in circuit breakers Most simple trip systems employ an electromagnet to trip the circuit in response to short circuit or overload faults The electromagnet provides a magnetic field in response to the current flowing through the breaker When the current level increases beyond a predetermined threshold the netic field trips
163. ignated as 533 in expanded form The dual gain section 533 receives phase signal A Each dual gain section includes a pair of low pass filters 532 and a pair of amplifiers 534 and 536 The low pass filters 532 pro vide noise suppression and the amplifiers 534 and 536 reduce the signal magnitude by 0 5 and increase the signal magnitude by a factor of 3 respectively for the desired resolution This arrangement allows the mi crocomputer 120 to instantaneously measure these cur rent levels without wasting time changing any gain circuitry Preferred component values are for example 10 K ohms for resistors 541 543 545 553 and 555 4 75 K ohms for resistors 547 and 559 60 K ohms for resistor 557 and 0 03 microfarads for capacitors 549 and 561 The amplifiers 551 and 663 are for example part No LM124 Using the gain circuit 134 the microcomputer 120 measures the true RMS current levels on lines 106 by sampling the burden voltages developed at signals A 20 30 35 45 50 55 65 B and C The RMS calculations are based on the for mula 2 TRMS where N the number of samples t time at discrete intervals determined by sample rate and 1 t the instantaneous value of the current flowing through the breaker The current flowing through the circuit breaker is sampled at fixed time intervals thereby developing I t The value of this instantaneous current sample is squared and summed with other sq
164. includes an output inductot coupled with the set of input inductors which adds the induced current from each current sensor and produces a current signal therefrom in the presence of a ground fault The added currents are provided to a bridge rectifier which provides a rectified signal corre sponding to the current signal The processor receives the rectified signal to detect a ground fault in the three phase current path and provides a trip signal to a sole noid to break the current path BRIEF DESCRIPTION OF THE DRAWINGS Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which FIG 1 is a block diagram of a microprocessor based circuit breaker tripping system according to the present invention FIG 2 is a perspective view of the circuit breaker tripping system as set forth in the block diagram of FIG FIG is a diagram illustrating a local display 150 FIG 1 FIG 35 is a flow chart illustrating a manner in which a display processor 316 of FIG 3a may be programmed to control an LCD display 322 of FIG 3a FIG 4 is a schematic diagram illustrating an analog input circuit 108 a ground fault sensor circuit 110 a gain circuit 134 and a power supply 122 of FIG 1 FIG 5 is a timing diagram illustrating the preferred manner in which signals received from the gain circuit 134 are sampled by the microc
165. isc INIT EQUAL 3D RAM and 1 0 Mapping Register TESTI EQUAL 3E Factory Test Register CONFIG EQUAL 3F Configuration Control Register usable only in bootstrap mode e 3e ve e e e de e de de fe e e de e e de de de die De e de de e fe dn de e e de e e fe de de de e de de de de ie fe de e fe e e e de die e de 2 SYSTEM CONSTANTS WHICH CAN CHANGE DURING DEVELOPMENT e e fe e dfe e e fe de de fe fe de e e k k fe e sie e e de e k e e e e e e e e e e e e k e e ede e fe de fe in k le e de e de dein de x E BIT ASSIGNMENTS FOR 55 GLOBAL FLAG REGISTER SERIAL EQUAL 501 is set until valid serial data is m E available flags WRD ALIGN BIT EQUAL 02 21 set to 1 word aligned off is dbl word fla REBUILD GF EQUAL 04 bit set when G F memory is true FLAGSS KILL WATCHDOG EQUAL 08 shutoff watchdog pulses during trip sequence flags I SQ BIT EQUAL 10 SET IN FLAGS FOR I SQ IN MUL 16X16 ST BIT EQUAL 20 this bit on in flags means no short time NO EQUAL 540 this bit on in flags means GF PE EQUAL 580 thigh bit of system flags set brkr 22272 END OF 55 DEFINITIONS x exeeees
166. ister CLRB clear ACCB for percent LSLA shift into carry 2 go check bit 2 ADDB 100 if set 27 1 BIT 2 EQU LSLA shift into carry go check bit 3 ADDB 50 if set add 2 2 BIT 3 EQU 5 LSLA shift into carry 4 290 check bit 4 ADDB 25 if set add 2 3 BIT 4 EQU 5 shift into carry 5 go check bit 5 ADDB 12 2 4 BIT 5 EQU 5 LSLA shift into carry 6 check bit 6 ADDB 6 2 5 BIT 6 EQU LSLA sshift into carry 7 zgo check bit 7 ADDB 3 2 6 BIT 7 EQU 5 LSLA shift into carry 8 all done so leave ADDB 2 2 7 BIT 8 EQU 5 LSLA 7shift into carry DONE zall done so leave ADDB 1 2 7 BIT DONE EQU 5 RTS result in 2x percent c de fe e e oie de de fe c e e c oe ee ie e e x GLOBAL TRIP fe fe e de e e tfe nhe de e die dese de de den THIS IS THE GLOBAL TRIP ROUTINE CALLED BY ALL THE INDIVIDUAL TRIP ROUTINES e CALLED MAX IDENT phase causing trip GF TRIP FLAG value for trip indicator r 9 oc v 6 5 136 458 78 RETURNS nothing reinitializes breaker code if current for more than 128 mSec resest the watchdog set tripping flag so INST isn t run in interr clear 250 mSec timer START OF ONBOARD REGISTERS turn off LT memory cap char
167. k data lines high BSET DDRD X SDA SCL set data direction to output BCLR SPCR X 40 disable SPI connect port D LDAB 08 set for 8 clock cycles SEND NEXT CLOCK EQU 5 BCLR PORTD X SCL clock low NOP NOP BSET PORTD X SDA clock high BSET PORTD X SCL z Clock high BCLR PORTD X SDA low start DECB count down to 0 BNE SEND NEXT CLOCK 12 not 8 clocks send next clock RTS return with clock high PRSTRSTRSTRSTRSTRSTRSTRSTRSRTRSTRSTRSTRSTRSTRSTRSTRSTRSTRSTRSTRSTRSTRSTRSTRSTR ADDRADDRADDRADDRADDRADDRADDRADDRADDRADDRADDRADDRADDRADDRADDRADDRADDRADDRADDR This Subroutine sends the correct address to send data to and tells the EEPROM to wake up Called with no parameters set ACCA ACCB IX amp IY not restored Uses portion of the WRITE EE routine to address the EEPROM IMPORTANT THIS ROUTINE MUST BE CALLED BEFORE CALLING EE READ or EE WRITE te ce e de le e de e e t i eee ee e de e e de oe e e ec e ed e c ee d jeje dede e Hee 54 54 ADDRESS WEE EQU 5 000 mark to leave after sending address LDX REGSTART sload IX with start of regs to send data BSET PORTD X SDA SCL set clock amp data line high to prepare for sta bit BSET DDRD X SDA SCL set serial data for output BCLR SPCR X 40 shut down spi amp connect portD to output NOP insert no ops for timing NOP to make sure delay is long enough for start BCLR PORT
168. ket 4 4 Packet 0 Packet Packet 5 5 Packet 0 Packet 1 Packet 6 6 Packet 0 Packet 1 Packet 7 During a trip condition the normal operation packet transmission sequence is interrupted and Packet number 2 is transmitted continuously until power is lost The transmission rate will be increased to the fastest rate possible The five bytes of each packet that vary according to packet number are configured for a total of eight differ ent packets 0 7 The information in these bytes is im plemented for each packet number as follows Packet 0 0000 Data Byte 1 Phase A Current High Byte Data Byte 2 Phase A Current Low Byte Data Byte 3 Phase B Current High Byte Data Byte 4 Phase B Current Low Byte Data Byte 5 Overload Pickups amp Short Circuit Restraint In Packet 1 0001 Data Byte 1 Phase C Current High Byte Data Byte 2 Phase C Current Low Byte Data Byte 3 Ground Fault Current High Byte 5 136 458 5 10 20 20 continued Data Byte 5 Rating Plug Options Packet 3 0011 Data Byte 1 Long Time Switches Data Byte 2 Short Time Switches Data Byte 3 Instantaneous Phase Unbalance Switches Data Byte 4 Ground Fault Switches Data Byt 5 Phase Unbalance Trips Packet 4 0100 Data Byte 1 Long Time Trips Data Byte 2 Short Circuit Trips Data Byte 3 Ground Fault Trips Data Byte 4 Last Maximum Phase Current High Byte Data Byte 5 Last Maximum Phase Curr
169. lator JSR LT ACCUM GO GET MEMORY RATIO VOLTAGE amp FIGURE ACCUMULA LDD RESULT load LT rebuilt accumulator result hi word STD LT ACCUM store LT accumulator into memory d LDD RESULT 2 load rebuilt low word STD LT 2 store low word to memory SET THE LT ACCUM GREATER THAN ZERO FLAG IN LT FLAGS BSET FLAGS LT GTZ BIT BCLR FLAGS SET j ACCUM 1 bit since Accum is calculated RTS 7all done so leave ACCUM ALREADY SET EQU JSR LT ACCUM GO GET MEMORY RATIO VOLTAGE amp FIGURE ACCUMULA LDY RESULT CALCULATED LT OR FLC ACCUMULATOR LDX LT_ACCUM WORD OF LT OR FLC ACCUMULATOR JSR COMP DBL WORD COMPARE ACCUMULATOR VALUES 00 ARE HIGH WORDS THE SAME BGT ADJUST_DOWN RATIO gt gt LT ACCUM FLC ACCUM BLT ADJUST_UP lt lt LT ACCUM FLC ACCUM IF WE GET HERE BOTH CALCULATED AND ACCUM ARE EQUAL RTS ADJUST UP EQU 5 1 SET PORT BIT HIGH TO ADJUST VOLT GE LEVEL UP LDX REGSTART ONBOARD REGISTER LOCATIONS BSET PORTD X 20 TURN ON OUTPUT TO INCREASE MEM DELAY RTS ADJUST DOWN EQU 5 2 SET PORT BIT LOW TO ADJUST VOLTAGE LEVEL DOWN LDX REGSTART GET ONBOARD REGISTER LOCATIONS BCLR PORTD X 20 TURN OFF OUTPUT TO DECREASE MEM DELAY RTS ADJUST LT VOLTSADJU ST LT VOLTSADJUST LT VOLTSADJUST LT VOLTSADJU ST LT VOLTS 5 136 458 73 74 dde de te fe e e e e COMP DBL WORDS THIS ROU
170. ll contain a known value at any given time t For example assume that a continuous fault is mea sured at 70 71 amperes RMS with an accumulation period of 64 milliseconds Further assume that the accu mulation register is at zero prior to the fault The mi crocomputer 120 will accumulate the squared value of the current every 64 milliseconds into the register caus ing it to increase at a constant rate With a continuous fixed level fault as time increases the internal accumulation register increases proportion ally In order to protect the system from this fault this 20 25 30 35 45 50 55 60 65 16 increasing accumulated value is compared periodically against a predetermined threshold value that has been chosen to represent the maximum allowed heat content of the system When the accumulated value equals or exceeds this predetermined threshold value the trip ping system will trip the breaker A valuable aspect of accumulating the current squared value is that as the current doubles the current squared value quadruples and the internal accumulation register increases at a more rapid rate resulting in a more rapid trip Thus if the delay time the period before the detected power fault causes a trip is x sec onds at some current level as the current doubles the delay time will be x 4 seconds The formula for calculating the delay time for any constant current is ARXK where a
171. location for 1 2 USED ACCA ACCB IX IY RESTORED IX amp IY return as se 1 111111111111111111 1 11 1 RESULT USED 1 1 11 1 11 9 923 2 323 92 9 02 2 23 1 1 1 092 0 0 EQU BSET FLAGSS I SQ BIT SET FOR SQUARE INSTEAD MUL 16 16 EQU 5 RESULT CLEAR HI BYTE OF HI WORD OF RESULT CLR RESULT 1 CLEAR LOW BYTE OF HI WORD OF RESULT LDAA 1 BYTE OF MULTIPLIER LDAB 1 LOW BYTE OF MULTIPLICAND MUL MULTIPLY IT STD RESULT 2 STORE IN LOW WORD OF RESULT LDAA 1 LOW BYTE OF MULTIPLIER LDAB 0 HI BYTE OF MULTIPLICAND BEQ MUL NEXT BYTE IF HIGH BYTE 0 WHY MULTIPLY GO TO NEXT ROUT MUL MULTIPLY BRCLR FLAGSS I SQ BIT ADD RESULT IF BIT CLEAR THIS ISN T A SQUARE LSLD WE HAVE I SQ REQUEST so double 2nd produc EQU ADDD RESULT 1 ADD RESULT IN TO COVER DOUBLE WORD BOUNDARY STD RESULT 1 STORE ANSWER BACK TO LOCATION LDAA RESULT HIGH BYTE HIGH WORD 00 ADD WITH CARRY TO BRING IN ANY CARRY STAA RESULT STORE BACK TO RAM BRSET FLAGSS I SQ BIT MUL LAST BYTE IF SQUARING DON T DO THIS MULTIFL LDAA 0 Hi BYTE OF MULTIPLIER BEQ RETURN HIGH BYTE 0 we are finished LDAB 1 LOW BYTE OF MULTIPLICAND MUL MULTIPLY IT ADDD RESULT 1 ADD RESULT TO COVER DOUBLE WORD BOUNDARY STD RESULT 1 STORE BACK INTO RAM LDAA RESULT HIGH BYTE HIGH WORD ADCA 00 ADD WITH CARRY TO BRING IN ANY CARRY STAA RESU
172. max GF 2 STD RESULT suse result as holding reg temp in use alread JMP ACCUMUL 8 90 add to G F A NORM ADD EQU 5 LDAB PEAK GF value it to 99 MUL STD EQU LDX JSR ACCUMUL 8 RESULT 5 amp GF ACCUM ACCUM4 ADD 5 136 458 100 it double now has GFI 2 suse result as holding reg temp in use alrez ADDRESS OF GF ACCUMULATER 7ADD GF I SQUARE TO THE ACCUMULATER BRCLR GF FLAGS DOUBLE I2 BIT CHECK SPEC I2 TRIP BCLR GF FLAGS DOUBLE I2 LDD JMP CHECK SPEC I2 TRIP ve JSR CMPB BHS LDAB EQU SUBB BNE CLRA LDAB BEQ LDX JME EQU LSRB ADDB LDAA MUL EQU ADDD XGDX EQU GOOD_BRKR NOT_A_PE ADD_DELSW READ DELAY VALU RESULT ACCUMUL_8 EQU READ_BREAKER_SW 508 6000 508 5 508 ADD DELSW 2500 TRIP TBL READ DELAY VALU 5 16 5 I SQ DEL TBL clear double bit saved value back double 1 2 value for init time 5 NOW CALCULATE THE INDEX INTO THE 150 DELAY TABLE TO TEST FOR TRIP go read the breaker type mask off bit 4 zif PE or gt value is good set for PE subtract PE amp below Brkrs breaker type is 8 zset top byte of ACCD to 0 get sensor size brkr is PE2000 get trip table for 2500A PE has start of 1 2 in table divide by 2 for 0 1 2 values sensor masked brkr type 16 bytes
173. mer is started to run normal times after 250 mSec Pe qe e e fe e e e e e oe je fefe e le i e ee e e e c ee e e Ye dn e e ie e e ee fe ic ce len BRCLR FLAGSS REBUILD GF RESET GF 4 5 te te JMP RESET INST 6 mem active so do INST RESET GF EQU 5 LDAA 33 15 load GF unrestrained timer value STAA FTIMER set GF unrestrained timer LDD 1250 reset GF after 1 4 second STD GF RETN TIME RESET RETENTION TIMER LDD 5 gt GET RESET VALUE NULL STD LONG TIME save to timer STAA GF RESTRN TIME RESET RESTRAINT TIMER LDAB GFDELSW read the delay switch SW POS off bits not wanted CMPB 2 3 maximum 172 out position BLS SET GF LONG TIME 172 out so branch BSET GF FLAGS DOUBLE I2 set flag to double first 172 valve JMP RESET INST do INST stuff SET GF LONG TIME 5 LDX FIXED DEL START LOCATION OF FIXED DELAY TABLE LDY GFDELSW GF SWITCH ADDRESS LDAA 8 MULT BY 8 FOR OF ENTRIES PER ROW BSET FLAGSS WRD ALIGN BIT 1 WORD BOUNDARY JSR SET TBL INDX CALL INDEX ROUTINE IDD O X LOAD TIMER VALUE FROM TABLE SUBD 15 subtract INIT time for GF STD GF LONG TIME save to timer BSET GF LONG INACTIVE put timer to sleep ALAC ALL AL LAL SALES When the retention tim
174. n from interrupt instruction is executed If the data gt 40 45 50 55 60 65 8 byte just received is last data byte flow proceeds to block 392 At block 392 a test is performed to determine the integrity of the received data packet This is accom plished by comparing the 8 bit sum of the previously received 7 bytes with the most recently received byte last byte If the 8 bit sum and the last byte are differ ent flow proceeds to block 398 If the 8 bit sum and the last byte are the same the display processor sets the previously referred to data ready flag depicted at block 396 and returns from the interrupt via block 398 to block 380 At block 380 the received data is stored in memory and the data ready flag is reset At blocks 382 and 384 the display processor utilizes a conventional conversion technique to convert the stored data to BCD format for display at the LCD display 322 of FIG 3a The data that is sent and dis played at the LCD display 322 is chosen by the operator using the switch 311 to sequence through each of the three phase currents and the ground fault current as indicated in the data that is received from the mi crocomputer 120 of FIG 1 At block 386 the display processor utilizes received data including the sensor identification the rating plug type and the long time pickup level to determine the percentage of rated trip current being carried on lines 106 of FIG 1 At blo
175. n lines 106 having source inputs 102 and load outputs 104 The tripping system 100 uses an analog input cir cuit 108 and a ground fault sensor 110 to detect three phase current on the current path 106 When the trip ping system detects an overload short circuit or ground fault condition or otherwise determines that the cur rent path should be interrupted it engages a solenoid 112 which trips a set of contactors 114 to break the current path carrying phases A B and C Consequently any ground fault circuit through the earth ground path or through an optional neutral line N is also broken tripping system 100 of FIG 1 utilizes a number of circuits to determine when the current path should be interrupted This determination is centralized at a mi crocomputer 120 preferably an MC68HC11A1 which is described in MC68HC11 HCMOS Single Chic Mi crocomputer Programmer s Reference Manual 1985 and MC68HC11A8 Advance Information HCMOS Single Chip Microcomputer 1985 all being available from Motorola Schaumburg Peripheral circuits that support the microcomputer 120 include a reset circuit 124 that verifies the sanity of the tripping system 100 a voltage reference circuit 126 that provides a stable and reliable reference for analog to digital A D circuitry located within the microcomputer 120 ROM 128 that stores the operating instructions for the microcomputer 120 and a conventional address and data decoding circuit
176. ned gain fac tor and a second gain section for amplifying the respective current signal by a second predetermined gain factor 10 20 25 30 35 45 55 65 194 processor responsive to the output current signal and the set of gain circuits for analyzing the three phase current path by selectively receiving the respective current signal from either the first gain section or the second gain section at each gain circuit according to a predetermined resolution criteria and for engaging the interruption means to interrupt the current path and data memory means coupled to said processor for storing data representative of tripping characteris tics wherein the processor compares the rectified signal to the data and engages the interruption means if the rectified signal exceeds a threshold data level 2 A tripping system according to claim 1 further including first second and third phase bridge rectifiers each responsive to the current signal from a respective one of the current sensors for rectifying the current signals before they are amplified by the set of gain cir cuits
177. o GF xmit conversion get conversion result store to max phase cause of trip current 71 TEMP USED GLOBAL TRIP s JSR RESET COP BSET IFLAGS TRIPPING CLR T250MS IDX REGSTART BCLR PORTD X MEM CAP LDAA 4502 STAA PACKET STAA PACKET HOLDER CLR BYTE PTR CLR CHECK SUM JSR SERIAL LDAA RATING PLUG ANDA SWITCH MASK 51 BGE EE WRITE JSR RESET THIS SECTION PASSES LDX PHASE RMS IDY PHASE TRIP I MOVE DATA EQU 65 LDD 0 0 9 LDAB 502 SCRIN BNE HISTORY CLASS OVER INX INY HISTORY CLASS OVER EQU 5 CPx 5 PU GF PU BLO MOVE IDX PHASE I LDAB IDENT ANDB 503 CMPB 4503 BLO GF CAUSE LDX CURRENT NOT GF CAUSE STX LAST CLR TRIP CAUSE LDAA OVPU SCRIN ANDA 538 STAA TRIP CAUSE IDAA SC GF ANDA 507 ORAA TRIP CAUSE STAA TRIP CAUSE IDX LDAA ANDA 506 CMPA 506 BEQ RESTRAINT BSET TRIP CAUSE 40 SAVE DATA NO_RESTRAINT EQU 5 BCLR TRIP_CAUSE 40 SAVE EQU 5 gt JSR ADDRESS WEE JSR WRITE NO EE WRITE EU JSR RESET COP CLI IDENT ANDB 503 CMPB 503 BLO DO NORM PEAK JSR CONV LDD GF CURRENT STD MAX PHASE 79 80 JMP CHECK TRIP V check trip voltage DO NORM PEAK EQ e z 5 PEAK point to value LDX
178. of 64 byte Register Block location of Rating Plug nibble 215 supply amp Motor sensor location Long Time Pickup Switch Long Time Delay Switch Full Load Pickup Switch Full Load Delay Switch Short Time Pickup Switch Short Time Delay Switch Locked Rotor Pickup Switch Locked Rotor Delay Switch Instantaneous Pickup Switch Phase Unbalance Pickup Switch Ground Fault Pickup Switch Ground Fault Delay Switch memory location of sensor nibble memory location of type of breaker PAGE T INTERNAL 6811 REGISTERS OFFSET VALUES FROM HEX 1000 Se Se Se a t Register Block Address Assignment xe de e dr de de 77 777 5 136 458 23 24 EQUAL 500 Port Data Register PIOC EQUAL 02 Parallel I O Control Register PORTC EQUAL 03 Port C Data Register PORTB EQUAL 04 Port B Data Register PORTCL EQUAL 05 C Latched Data Register DDRC EQUAL 07 Direction Register for Port C PORTD EQUAL 508 Port D Data Register DDRD EQUAL 09 Direction Register for Port D PORTE EQUAL SOA Port Data Register CFORC EQUAL 0B Timer Compare Force Register 1 EQUAL SOC Output Compare 1 Mask Register OC1D EQUAL 500 Output Compare 1 Data Register TCNT EQUAL 50 Timer Control Register EQUAL 10 Timer Input Capture Registe
179. omputer 120 of FIG 1 FIG 6a is a side view of a rating plug 531 of FIG 4 FIG 6b is a top view of the rating plug 531 of FIG 4 FIG 7 is a schematic diagram illustrating a thermal memory 138 of FIG 1 FIG 8 is a schematic diagram illustrating the reset circuit 124 of FIG 1 and FIG 9 is an illustration of a user select circuit 132 of FIG 1 5 While the invention is susceptible to various modifi cations and alternative forms a specific embodiment thereof has been shown by way of example in the draw ings and will herein be described in detail It should be understood however that it is not intended to limit the invention to the particular form disclosed but on the contrary the intention is to cover all modifications equivalents and alternatives falling within the spirit and Scope of the invention as defined by the appended claims BEST MODES FOR CARRYING OUT THE INVENTION System Overview The present invention has direct application for mon itoring and interrupting a current path in an electrical distribution system according to specifications that may be programmed by the user While any type of current path would benefit from the present invention it is 5 136 458 3 particularly useful for monitoring and interrupting a three phase current path Turning now to the drawings FIG 1 shows a block diagram of an integral microprocessor controlled trip ping system 100 for use with a three phase current path o
180. omputer 120 to read the binary coded resistor value from the rating plug 531 A tri state buffer 820 allows the microcomputer 120 to selectively read the logic level of each of the four leads representing the status of the four fusible printed circuit links on the rating plug 531 A logic high at the input of the buffer 820 provided by the connection between the fusible printed circuit link and 5 V signal indicates that the corresponding link is closed A logic low at the input of the buffer 820 provided by pull down resistors 826 at the input of the buffer 820 indicates that the corresponding link is open The fusible printed circuit links A B C and D may be opened using a current generator to send an excessive amount of current through the links thereby causing the copper links to burn This is preferably performed before the rating plug 531 is installed in the tripping system Thus once installed the rating plug 531 automatically informs the microcomputer 120 of its resistor values and there is no need to adjust any settings or otherwise inform the microcomputer of the type of rating plug being used The microcomputer may adjust the values read from its A D converter by a predetermined scale factor corre 30 35 50 60 14 sponding to the binary coded resistor value to compute actual current values which are independent of the resistor values in the rating plug 531 C Bi metal Deflection Simulation The microcomputer 120
181. on the capacitor 611 that is proportional to the accumulated square of the current When the mi crocomputer loses power the voltage across the circuit 610 logarithmically decays The decay is gov erned by the equation Voexp t RC Should the microcomputer power up again before the voltage reaches zero the microcomputer 120 reads the voltage across the RC circuit 610 using a conventional analog buffer 612 and initializes its delay accumulator to the correct value The analog buffer 612 for example in cludes an amplifier 627 such as part No LM714 and a 4 7 K ohm resistor 629 preferred RC circuit 610 including a 100 micro farad capacitor 611 and a 3 24 megohm resistor 613 provides a fixed time constant of 324 seconds or ap proximately 5 4 minutes Control over the voltage on the RC circuit 610 is provided using IGFET transistors 618 and 620 such as part Nos VPO808 and 5170 respectively During normal quiescent conditions the microcomputer 120 will not be in an overload condition and will drive a logic low at the gate of the transistor 620 thereby dis abling transistors 620 and 622 and allowing the capaci tor 611 to discharge to tripping system ground Transis tors 618 and 620 work in connection with resistors 621 623 and 625 which have values for example of 100 K ohms 47 K ohms and 5 1 K ohms respectively During overload conditions the microcomputer 120 accumulates current information in its in
182. onfiguration of the tripping system 100 and other related information is readily available from ROM 128 and the user select circuit 132 The information relating to the history of trip causes is available from a nonvolatile trip memory 144 Information of this type is displayed for the user either locally at a local display 150 or remotely at a conventional display terminal 162 via remote interface 160 To communicate with the display termina 162 the tripping system utilizes an asynchronous communica tion interface internal to the microcomputer 120 Using the 6 the seria communications interface SCI may be utilized FIG 2 is a perspective view of the tripping system 100 as utilized in a circuit breaker housing or frame 210 The lines 106 carrying phase currents A B and C are shown passing through line embedded current trans formers 510 512 and 514 in dashed lines which are part of the analog input circuit 108 Once the solenoid 112 also in dashed lines breaks the current path in lines 106 the user reconnects the current path using a circuit breaker handle 220 Except for the circuit breaker handle 220 the inter face between the tripping system 100 and the user is included at a switch panel 222 an LCD display panel 300 and a communication port 224 The switch panel 222 provides access holes 230 to permit the user to adjust binary coded decimal BCD dials FIG 8 in the user select circuit 132 The communication por
183. orage location LDD RESULT 1 get result low byte CPD SERIAL max transmission value BLS SERIAL DATA OK serial is in good range LDD SERIAL load max value to indicate full scale SERIAL DATA OK EQU 2 2 LSID low bit shift high bit to carry LSRB shift low byte back to 7 bits ANDA 57 mask off high bit STD 0 store high byte RTS JOE WE RE DONE GO HOME ek kee SENSOR BREAKER ROUTINE FOR TRANSMISSION i w ikd d se w CALLED Once every second no values are passed to routine 7 4 5 Se Se to se RETURNS Sensor and Breaker type information in serial comm buffer fo transmission 14 44 4 USED ACCB RESTORED NOTHING e fe e e ide fe ie die ee fe e le de e le le idee e e e e e ee e de e e fe e e fee e e ede e e e e e Me e PH e Pede e e d e oe d e e d dede o 5 te EN SENSOR BREAKR EQU 5 7 BCLR IDENT 3C clear breaker type in xmit byte JSR READ BREAKER SW 1518 shift into correct position for xmit byte ORAB MAX IDENT combine with max phase data STAB MAX IDENT store back to xmit byte LDAB SENSOR read the sensor ANDB SWITCH_MASK mask it CMPB 1 for gt max sensor BLS SHIFT IT sensor shift it LDAB 51 1 good sensor SHIFT IT EQU 3 LSRB shift for correct position in byte STAB SENSR TU ID save to xmit buffer BSET SENSR TU ID HARD VERSION ha
184. pe ee ee ee e deje de de de o e coe dc e ce e e e ee de e de c de dee e c de e dede de e e e e ee e de de dee doo ede PHASE UNBALENCE EQU LDD PHASA SORT GET A PHASE SQUARE ROOT ADDD PHASB SQRT B PHASE ADDD PHASC SQRT 7ADD C PHASE STD THREE PHASE SUM 5 THE RESULT WE HAVE SUMED UP ALL THREE PHASES NOW GET 3 PHASE VALUE LDD 0 LOAD PHASE UNBALANCE IS WANTED FOR ADDD 0 ADD IT TO ITSELF ADDD 0 DO IT AGAIN SAM STD TEMP save 3 phase value now see if sum Of phases or 3 phases is greater value CPD THREE PHASE SUM COMPARE SUM OF 3 PHASES 3 PHASE SUM 15 GREATER BRANCH 3 PHASE SUM IS GREATER SUBD THREE PHASE SUM SUBTRACT 3 PHASE SUM FROM 3 PHASE STD RESULT 3 phase three phase sum JMP CONT PHASE SUM IS GREATER EOU LDD THREE PHASE SUM 3 PHASE SUM SUBD TEMP SUBTRACT 3 PHASE FROM 3 PHASE SUM STD RESULT three phase sum 3 phase COMPARE RESULT TO THREE PHASE SUM CONT PHASE EQU CPD THREE PHASE SUM is ratio of phase gt sum BLO FIND_THE_ _ GO FIND UNBALANCE SET TO 99 WHICH IS THE MAXIMUM FOR PHASE UNBALENCE LDAB 199 maximum percent JMP DONE return to main FIND TEE EQU 5 E LDX THREE PHASE SUM diff of three phase sum amp 3 phase LDD RESULT numerator is three phase sum FDIV a fractional divide XGDX result into double reg
185. pidly charged during pow er up The ground fault delay time stored in internal RAM becomes insignificant after a power interruption that lasts longer than about 3 6 seconds To test whether such an interruption has occurred the RAM retention circuit 140 includes an analog timer 149 having a resis tor 161 and a capacitor 153 establishing a certain time constant and a Schmitt trigger inverter 155 sensing whether the supply of power to the microcomputer 120 has been interrupted for a time sufficient for the capaci tor 153 to discharge Shortly after the microcomputer reads the Schmitt trigger 155 during power up the capacitor 153 becomes recharged through a diode 157 and a pull up resistor 159 Preferred component values for example are 365 K ohms for resistor 161 10 micro farads for capacitor 153 part No 74HC14 for Schmitt trigger 155 1N4 148 for diode 157 and 47 K ohms for resistor 159 Another important aspect of the tripping system 100 is its ability to transfer information between itself and 5 136 458 5 the user This information includes the real time current and phase measurements on the lines 106 the system configuration of the tripping system 100 and informa tion relating to the history of trip causes reasons why the microcomputer 120 tripped the contactors 114 As discussed above the real time line measurements are precisely determined using the analog input circuitry 108 and the gain circuit 134 The system c
186. r 1 TIC2 EQUAL 12 Timer Input Capture Register 2 TIC3 EQUAL 14 Timer Input Capture Register 3 1 EQUAL 516 Timer Output Compare Register 1 TOC2 EQUAL 18 Timer Output Compare Register 2 TOC3 EQUAL 51 Timer Output Compare Register 3 4 EQUAL 510 Timer Output Compare Register 4 5 EQUAL 51 Timer Output Compare Register 5 1 EQUAL 520 Timer Control Register 1 TCTL2 EQUAL 21 Timer Control Register 2 TMSK1 EQUAL 22 Main Timer Interrupt Mask Reg 1 TFLG1 EQUAL 23 Main Timer Interrupt Flag Reg 1 TMSK2 EQUAL 24 Misc Timer Interrupt Mask Reg 2 TFLG2 EQUAL 25 Misc Timer Interrupt Flag Reg 2 PACTL EQUAL 26 Pulse Accumulator Control Register PACNT EQUAL 27 Pulse Accumulator Count Register SPCR EQUAL 28 SPI Control Register SPSR EQUAL 529 SPI Status Register SPDR EQUAL 2A SPI Data Register BAUD EQUAL 528 SCI Baud Rate Control Register SCCRi EQUAL 52 SCI Control Register 1 SCCR2 EQUAL 520 SCI Control Register 2 SCSR EQUAL 2E SCI Status Register SCDR EQUAL 52 SCI Data Register ADCTL EQUAL 30 A D Control Status Register EQUAL 531 A D Result Register 1 ADR2 EQUAL 32 A D Result Register 2 ADR3 EQUAL 33 A D Result Register 3 ADR4 EQUAL 34 A D Result Register 4 OPTION EQUAL 39 System Configuration Options COPRST EQUAL 53 ARM Reset COP Timer Circuitry PPROG EQUAL 53 EEPROM Programming Register HPRIO EQUAL 53 Highest Priority Interrupt and M
187. raint timer JSR INST TIMER RST go reset the instantaneous timer R U RESTRAINED EQU ect LDAA 5 RESTRN TIMER the SC restraint timer BNE HOLD ST 21 lt gt 0 check the ST retention timer JSR 5 RESTRN OFF get restraint timer HOLD ST EQU 5 LDAA ST RETN TIMER retention timer for ST BNE 5 TIME OUT if lt gt 0 check 172 out timer JSR ST_RETN_TIMOUT 240 run ST retention time out code ST TIME OUT EQU 5 2 LOX ST I2 OUT TIMER get ST 172 out timer BNE TIMERS if lt gt 0 continue timer check JMP ST TRIP go trip don t return GF TIMERS EQU GF timers here if any have timed out run correct routines BRSET FLAGS NO GF BIT RETURN TO if no GF bypass LDAA RESTRN TIME restraint time BNE CHECK FOR RETN if not 0 continue JSR GF RESTRN OFF timer 0 go kill restraint line CHECK FOR RETN EQU LDX RETN TIME get retention time BNE CHECK FOR FIXED if not 0 continue JSR GF RETN TIMOUT timer 0 go reset timers CHECK FOR FIXED 2 LDX LONG TIME get restraint timer BNE RETURN zif not 0 continue TRIP timer 0 go trip RETURN TO TOP EQU RTS return to main e END ALL TIMERS ROUTINE de de dede de de Fe d e SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS BREAKER TYPE SWITCH READ HERE AND ANY NON DEFINED
188. rdware is version 1 3 RTS all done go back to main e e de e Ae He e e e e CHECK LED SUBROUTINE fe fe e e he e de e de e e e e de e he e e he e de e e de e de dede de ke IDEM CALLED Every 25 Sec to check LTPU LED No conditions are passed into the routine Routine reads Long Time flags for its decisions 5 136 458 13 114 RETURNS Long Time LED either on off depending on condition 05 Long Time pick up flag 4 4 4 USED RESTORES IX not changed f CL CL e e e FE IE SE EE CE RRR we de HECK LED EQU LDX REGSTART set index to start of 6811 registers BRCLR LT FLAGS LT PU BIT TRY 90 if pickup bit is off try 905 BSET PORTA X LED we have pick up so set led on RTS TRY 905 5 BRSET LT FLAGS LT 090 BIT TOGL LED 16 90 pick up go BCLR PORTA X LED else no pickup so turn led off RTS TOGL LED BRSET PORTA X LED BIT O CLEAR LED BSET PORTA X LED led is now off so turn it on 5 CLEAR LED BCLR PORTA X LED turn led off RTS SERIAL TRANSMISSION SUBROUTINE 1 1 1111911J111 1111 0 Gt 1 10 PE 1 1 1 01 CALLED Every 7mSec in normal operating mode or as fast as possible if breaker is in a tripping tripped condition RETURNS No values only sends a byte out the SPI amp SCI ports USED ACCA ACCB
189. rmer output current will be 282 8 milliamperes RMS Thus when the microcomputer 120 reads the burden voltages using the gain circuit 134 FIG 1 the microcomputer 120 can calculate the actual current in the lines 106 FIG 4 illustrates parallel connections between re spective resistors 527 and 529 which are used to estab lish the maximum allowable continuous current passing through the lines 106 The resistors 527 are part of the rating plug 531 and the resistors 529 are separate from the rating plug 531 The resistors 529 for example are each 4 99 ohm 146 5 watt resistors This value should be compared to a corresponding value of 12 4 ohms for the burden resistor 525 for the ground fault signal The resistors 527 of the rating plug are connected in parallel with the resistors 529 and hence cause a decrease in the combined resistance Therefore the resistors 529 set the minimum current rating for the tripping system In a preferred arrangement for example the minimum cur rent rating corresponds to 40 of the maximum current rating The resistors 527 in the rating plug scale the voltages read by the microcomputer This 5 136 458 13 enables the resolution of the A D converter in mi crocomputer to be the same in terms of a fraction of the rated current for both the minimum and maximum cur rent rating Consequently there is not any sacrifice in converter resolution for the minimum current rating In FIGS 6a
190. rom any interrupt except timer output comparel TOC1 and RESET VECTOR RETURNS Doesn t return this routine reinitializes the trip unit to try to run code normally If 3 soft errors occur 10 minutes the breaker will trip USED RESTORED NOTHING EE SOFTDOG INTERRUPT EQU SEI set interrupts to stop any incoming LDX REGSTART get start of onboard regs LDAA TFLGl X clear timer any interrupt STAA TFLG1 X now it s clear LDAA 589 setup value for option register STAA OPTION X reset option register in case of trash LDAA SOFT DOG CNTR get of soft errors CMPA 5 compare to reset value BNE NEXT ERROR already have 1 or more errors LDD 600 600 seconds 10 minutes STD SOFT DOG start lst soft timer LDAA 5017 load 1 error STAA SOFT DOG CNTR clr flag 1 error JMP INIT 1 240 reinitialize the trip unit NEXT ERROR LDAA SOFT DOG CNTR of errors CMPA 4502 if we have 2 errors already BHS SOFT TRIP this is error 3 go trip INC SOFT DOG CNTR 2nd error inc counter LDD 600 value for 2nd timer STD SOFT DOG TIMER2 save it to the 2nd timer INIT 1 reinitialize trip unit SOFT_TRIP EQU SEI turn interrupts off JSR RESET COP reset the softdog BSET FLAGSS KILL WATCHDOG we in trip don t strobe WD LDAA 5 2
191. rovide a rectified signal corresponding to 4 680 706 7 1987 Bray 364 492 the output current The processor receives the rectified 4 682 264 7 1987 Demeyer 361 96 signal to detect the ground fault in the three phase cur Pe i pemeyer a rent path and provides trip signal to solenoid to urivage et al 4 709 339 11 1987 Fernandes 364 492 cak 4717985 1 1988 Demeyer 361 96 2150 includes a test input inductor for receiving exter 4 747 061 5 1988 Lagree et al 364 483 nal AC signal to simulate a ground fault 4 783 748 11 1988 Swarztrauber 364 483 4 794 369 12 1988 Haferd 344 166 2 Claims 10 Drawing Sheets 108 110 5 100 T i INPUT FAULT 106 1 1 i 445 A eiui Lum jA LOCAL es E 130 128 1 1 1 1 1 RETENTION 1 acu J 5 136 458 Sheet 1 of 10 Aug 4 1992 U S Patent J Erxl 7 E 913 EE A64 NOLIN313U HES fs AVX 4 l 19 2 J 1 Cw oi AG 0 9 100230 eb Wi 92 A6 0 14405 viva 53007 O T We day r BUMS 109412 123135 8360 4191 avy AV WOOT fort 09 gt rsm AHON3N
192. rted with respect to trip ping system ground and that has a voltage that is pro portional to the current in the transformer 509 The A C rectified signal 558 is filtered by filter 560 for noise suppression and then inverted using analog invertor 562 From the analog invertor 562 a positive going signal is carried to an A D input at the mi crocomputer 120 The microcomputer 120 measures the peak levels at the output of the analog invertor 562 to detect the presence of a ground fault A conventional 15 20 25 30 35 40 voltage divider switch 564 is controlled by the crocomputer 120 to selectively reduce that signal by two thirds as may be required under severe ground fault conditions Preferred component values are for example 10 K ohms for resistors 565 and 567 20 ohms for resistor 569 19 6 ohms for resistor 573 10 K ohms for resistor 575 0 033 microfarads for capacitor 577 part No LM124 for amplifier 579 and part No BS170 for IGFET 581 3 Providing System Power Power for the tripping system is provided directly from the current on lines 106 and current on any one of the lines 106 can be used This feature allows the trip ping system to power up on any one of the three phases and to be powered when a ground fault on one or more of the phase lines 106 is present The output currents which are induced by the trans formers 510 512 and 514 are routed through the recti fier bridges 516 5
193. s JMP CHECK 64MS don t do GF code GF not installed 1 IF NO GROUND FAULT PICK UP CONTINUE ON TO 17MS TIMER CHECK GF ISQ EQU 5 5 136 458 53 54 LDX SERIAL POINTER get location of byte last sent CURRENT did we send half of GF current BNE DO GF SERIAL CONV if not to do serial conversion JMP TEST TOR t GE CJ PU DO GF SERIAL CONV EQU JSR DO GF CONV go do ground fault conversions for xmit BCLR GF FLAGS USE XS BIT Clear for correct conversions TEST FOR GF PU BIT EQU E BRCLR FLAGS GF PU BIT CLEAR PEAK sno GFPU so branch LDX REGSTART onboard register addresses BRSET PORTA X GF RES IN CLEAR GF PEAK bit set if restr line is lo GFDELSW READ GF DELAY SWITCH ANDB MAX SW POS 2 5 OFF BIT 0 CMPB 06 CHECK FOR 172 IN DELAYS BLS CLEAR GF PEAK SWITCH lt 6 DON T DO GF I 2 IN JSR GF ISQ IN CALL GF I 2 DELAY ROUTINE CLEAR GF PEAK EQU JSR CHECK GF 13MS GO CHECK IF NEED TO CLR GFPU 64 mSEC CHECKS 1 Four 64 mSec timers are run here One timer for each phase and one for Long Time pick up check routines After each phase calculates its RMS value a flag is set to do serial comm conversion and phase unbalance CHECK 64MS EQU 5 LDAA PHASEA RMS CURRENT A PHASE TIMER VALUE TEST EQU 5
194. s STAA ST FTIMER reset st fast timer to 33ms FFFF load timer null value STD ST I2 OUT TIMER null 172 out timer STAA ST RETN TIMER null ST retention timer CLR ST ACCUM 5 clear I 2in accumulator here mE LDD 0000 STD ST ACCUM set hi word st accum to zero STD ST ACCUM 2 set low word st accum to zero BCLR ST FLAGS DOUBLE ST I2 don t double 172 values RTS return to 10 MS RESTRAINT TIME OUT CALLED From llmSec ST restraint timer time out RETURNS SC RESTRN TIMER reset to SFF USED IX RESTORED NOTHING SLE eee Cee CECE Le RESTRN OFF EQU IF WE GET HERE THERE ARE SC PICK UPS SO CLEAR SC RESTRAINT OUTPUT LDX REGSTART BCLR PORTA X SC_RESTR_BIT_OUT clear restraint bit BSET SC_RESTRN TIMER SFF set timer number to null RTS PERERA ERE RARE Y END OF SHORT TIME ROUTINES EX tribtrrrer ALL GROUND FAULT ROUTINES ARE HERE YU dee dede de eiie deesse CHECK FOR Skee eee eee eee 7 54 se sh Se CALLED Every 2mSec from breaker or motor protection code No preset conditions or values passed in any registers RETURNS Condition of Gr restr in line 2mSec
195. s analysis of the current on lines 106 Status messages are preferably transmitted using an 8 byte per packet multi packet transmission technique The type of information included in each packet may be categorized into eight different groups or eight differ ent packets packet 0 through packet 7 The first byte of each packet is used to identify the byte and packet num bers and the trip status of the tripping system 100 For example the first byte may contain one bit to identify the byte type four bits to identify the packet number and three bits to identify the trip status no trip condi tion current overload trip short circuit trip instanta neous trip ground fault trip and phase unbalance trip Bytes two through six of each packet vary depending on the packet number Byte 7 is used to identify the 19 tripping system sending the information for multiple system configuration and byte 8 is used as a checksum to verify the integrity of the data microcomputer alternates the type of informa tion included in each packet depending upon the prior ity type of the information During normal non trip ping conditions the trip unit will transmit Packet Number 0 followed by Packet Number 1 followed by one of the remaining defined Packet Numbers 2 through 7 The sequence is graphically shown as 1 Packet 0 Packet 1 Packet 2 Repeat until Trip 2 Packet 0 Packet 1 Packet 3 Occurs 3 Packet 0 Packet 1 Pac
196. s is gt so branch LDAA PHASEC is phase max C ISNT INST PEAK EQU a LDAB 06 multiplier MUL it STD ST_PEAK save max current of trip goto dee dede KK WE ARE TRIPPING SO CLEAN UP THE STACK ft e e le fe e he le e le he fe e e lee e de dede dne TSX move stack pointer to IX LDAB 09 79 bytes are on stack so load ACCB ABX add 9 to stack pointer TXS put it back in the Stack Pointer STACK IS CLEANED UP AT THIS POINT NOW GO TRIP ee x wx SEI so don t interrupt tripping Loy ST_PEAK point to value LDX PHASE I point to storage JSR CONVERSION 240 convert to xmit format JMP DO 5 TRIP tripping so leave don t finish A D PPRWAIT FOR ATOD READ TO COMPLETE WAIT FOR ATOD EQU 5 CUR PHASEA B or C ARE ONLY VALUES USED OUTSIDE OF INTERRUPT L PHASE amp HI PHASE ARE USED AS INTERMEDIATES IN INTERRUPT exws LDAB ADRi REGSTART GET PHASE A HIGH GAIN A D STAB HI PHASEA save value for check in trip routine CMPB 6 BLS USE HI PHASEA use the low gain A D value for I 2 summation LDAA PHASEA LDAB 6 STD CUR JMP PHASEA SUMMATION 240 do 172 summation USE HI PHASEA EQU CLR PHASEA STAB 1 PUT IN CUR ATOD PTR TABLE DO PHASEA SUMMATION EQU AT THIS POINT EITHER LOW OR HIGH GAIN HAS BEEN STORED TO CUR PHASEA FOR USE TBA move low byte to ACCA for 0 check BEQ LAST A ADD
197. t 224 may be used to transfer information to the display termi nal 162 via an optic link not shown In the following sections the tripping system 100 is further described in detail A Local Display FIG 3a is a schematic diagram of the loca display 150 of FIG 1 The local display 150 is physically sepa rated from the remaining portion of the tripping system 100 but coupled thereto using a conventional connec tor assembly 310 The connector assembly 310 carries a plurality of communication lines 312 from the mi crocomputer 120 to the local display 150 These lines 312 include tripping system ground the 5 V signal from the power supply 122 serial communication lines 314 for a display processor 316 and data lines 318 for a latch 320 The data lines 318 include four trip indication lines overload short circuit ground fault and phase unbalance which are clocked into the latch 320 by yet another one of the lin s 318 An LCD display 322 displays status information pro vided by the latch 320 and the display processor 316 Different segments of the LCD display 322 may be implemented using a variety of devices including a combination static drive multiplex custom or semi cus tom LCD available from Hamlin Inc Lake Mills Wis For additional information on custom or semi custom displays reference may be made to a brochure available from Hamlin Inc and entitled Liquid Crystal Display The latch 320 controls the segments 370 373
198. tems But the power measurement circuitry necessarily limits the size of the tripping system and is also relatively expensive due to the component tolerances and circuit complexity re quired for precise current measurement Accordingly in addition to requiring user flexibility to power distribution systems processor based tripping systems must also accurately and reliably measure the current provided to the loads Failing to perform in this manner often results in inadvertent nuisance trips or missed trips which may damage the equipment powered through the circuit breaker and the circuit breaker it self DISCLOSURE OF THE INVENTION In view of the above a preferred embodiment of the present invention includes a processor based circuit breaker tripping system for measuring and interrupting AC current The system utilizes a precise three phase current detection circuit which may be used to detect a ground fault condition A set of current sensors each situated adjacent the current path to sense a respective gt 10 20 25 30 35 45 50 55 60 65 2 phase of current therein provide respective current signals to a ground fault transformer The ground fault transformer includes a set of input inductors respec tively connected to the set of current sensors such that current flowing through each respective current sensor also flows through one of the associated input induc tors The ground fault transformer
199. ternal RAM to simulate the heat level and drives a logic high at the gate of the transistor 620 to allow the capacitor 611 to charge to a selected corresponding level While the capacitor 611 is charging the microcomputer 120 moni tors the voltage level using the analog buffer 612 When 5 136 458 15 the selected level is reached microcomputer drives a logic low at the gate of the transistor 620 to prevent further charging The voltage on the capacitor 611 is limited to five volts using a clamping diode 622 The forward voltage drop across the clamping diode 622 is balanced by the voltage drop through a series diode 625 For example assume that an overload condition sud denly occurs and the microcomputer 120 has been pro grammed to allow for a two minute delay before gener ating a trip signal at this overload fault level After one minute in this overload condition the microcomputer 120 will have accumulated current information which indicates that it is 5090 of the way to tripping The microcomputer will also have enabled the RC circuit 610 to charge to 2 5 v that is 50 of the maximum 5 v Assuming for the purpose of this example that the overload fault condition is removed at this point and the electronic trip system loses operating power when the power to microcomputer 120 drops to 0 v the inter nally stored current accumulation is lost However the voltage across the RC circuit 610 is still present and will st
200. test value BNE CONTINUE INIT ACCA x 1C 2 0E JMP PRODUCTION TEST go run production tests CONTINUE INIT EQU 5 CHECKS TO SEE GF MEMORY RETENTION IS STILL LIVE If this point is reached from a softdog error or is off aii memory is cleared If GF memory is still active REBUILD GF flag is set GF timers are put to sleep amp any active pick ups are cleared Ac e e e fe e eve e he e e ev e le e de e e die de e e fe die e e e e e e e e e e c e e e e e e e de de c se dfe Pe ede e e de f sic de e e dede e dede ede de t e LDAA SOFT DOG CNTR soft dog error counter BPL CLR ALL if not SFF this is softdog reset so clear LDAA GFPUSW read the GF pick up switch ANDA SWITCH MASK mask it CMPA SW POS maximum on position 8 BHI ALL GF is off so don t set memory flag LDAA PORTA X read portA inputs ANDA 501 check for GF memory BNE MEM if bit is set clear all memory CLR FLAGSS clr 55 so only rebuild bit is set BSET FLAGSS REBUILD GF SET TO rebuild GF accum BSET LONG TIME T INACTIVE BIT put trip timer to sleep BCLR FLAGS GF PU BIT turn off any GF pick up GF MEMORY IS STILL ACTIVE SO ONLY CLEAR RAM ABOVE GF VARIABLES WE RE FIXED EQU 5 memory active so don t clear GF RAM LDX GF VARS don t clear GF variables CLR MEM go clear memory NO A
201. time base LDAA T 12MS GET 12 MS TIMER 12 HAS IT EXPIRED YET BLO CHECK 13MS IT HAS NOT EXPIRED dede eei de ede THE FOLLOWING CALLS ARE DONE EVERY 12 MS Yo fe fee dede o x SUBA 12 reset the timer STAA 12MS save reset timer CHECK LT ACCUM EQU 5 37 LT ACCUM GT ZERO BIT IS NOT SET DON T CALL LT_DEC ACCUM BRCLR LT FLAGS LT BIT CHECK 13Ms 1f LTA 0 check 13mS timer BRSET LT FLAGS LT BIT CHECK 13 5 if LTPU set don t decrement JSR LT DEC ACCUM DEC LT ACCUM IF BELOW PICKUP dede de dede eee END OF THE 12 MS CALLS e fe he de je c e c he De e fe e e e de e e deje e je de dee EK 13 5 TIMER CHECK fe e e e e e e e e fe e e e de fe deje je de de e fe e le de dn de COP computer operating propperly reset Ground Fault comm GF I 2 in routine and GF Peak Detector clear are run this time base CHECK 13MS EQU LDAA T_13MS 13 mS TIMER VALUE CMPA 13 15 IT TIME FOR 13 mS ROUTINES BLO CHECK 64MS IT HAS NOT EXPIRED 45 de de dee n THE FOLLOWING CALLS ARE DONE EVERY 13 MS fec e e e e ge de fe de ge sie e de e dede de SUBA 13 reset the timer STAA T 13MS save the reset timer JSR RESET COP 7 IF GROUND FAULT IS INSTALLED go check if need to run I square GF routines BRCLR FLAGSS NO GF BIT CHECK GF ISQ CLR CURRENT ground fault not installed so CLR GF CURRENT 41 clear any current value
202. tor code TRIP VOLTS OK EQUAL 02 this bit set means we have 15 Volts for trip DESENSE THRESHOLD EQUAL 171 threshold 3xP peak MEM CAP BIT EQUAL 20 bit to charge memory capacitor SCL EQUAL 10 bit to toggle for EEPROM serial clock this amp SDA EQUAL 08 serial data bit for EEPROM SDA need switched TRANSMIT DONE EQUAL 80 transmit reg empty bit in SCSR register MAX SW POS EQUAL 2 7 maximum allowable switch position SWITCH MASK EQUAL 51 mask value for switches PROD TEST DESIGNATOR EQUAL 1C rating plug value to get to prod test SOFTWARE VERSION EQUAL 13 software version 1 3 Apr 25 1989 HARD VERSION EQUAL 10 hardware version 1 0 Feb 3 1989 MAX SERIAL I EQUAL S3FFF maximum current value that can be sent 16383 LOW GAIN EQUAL 34 VALUE TO SET A D to low gain inputs HIGH GAIN EQUAL 30 VALUE TO SET A D to high gain inputs DELAY 32MS EQUAL 11DB value for 32mS delay in VT CHECK routine DELAY 2MS EQUAL 11D value for 215 delay in VT CHECK routine e fe eoe eoe e e e ie e e e e e ie e n e e e e e de e ee de le e fe c e e e e fe e e e e cde fe e fe e e de e e e e e dede de dece e c ee e e e de de c e e RAM DATA AREA 5 RIO GR ORIGIN 0000 ABSOLUTE START VARS RB 0 POINTER TO START OF MEMORY CLEAR pr START OF MEMORY CLEAR WHEN G F MEMORY CAP IS NOT CHARGED e FLAGS
203. uared samples for a fixed number of samples N The mean of this summation is found by dividing it by N The final RMS current value is then found by taking the square root of the mean In FIG 5 an example of a rectified sinusoidal current waveform is illustrated for 1 5 cycles of a 60 hertz signal with a peak amplitude of 100 amps The sampled cur rent is full wave rectified The vertical lines represent the discrete points in time that a value of current is sampled With a sample rate of 0 5 milliseconds over 25 milliseconds of time 50 samples will be taken In TABLE 1 the data for the samples from FIG 4 are illustrated in the column labeled I t Amps The column labeled I t SQUARED Amps gives the squared values and the column labeled SUMMATION Amps shows the accumulation of the squared current values over time The mean of the summation depicted at the bottom of TABLE 1 is equal to the final accumu lation divided by the number of samples or 50 The square root of this value yields 70 7106854 which is less than 0 0000190 in error The other columns in TABLE 1 detail the binary equivalent data that the microcomputer would process using the ratio that 100 amps equals 255 binary The value 5 will accurately reflect the heating effect of the current waveform that existed from t 0 to t N This current waveform 15 typically waveform with a fundamental frequency of 50 to 60 Hertz but may contain many upper h
204. ust be on LDAB INPUSW ST is installed SO read the INST PU switch ANDB SW POS mask off unused bits CMPB SW POS tis INST in off position 8 BNE DS 20 no so set INST to 20 mSec LDAA 180 get 90 mSec value STAA INST TIMER set INST for 90 mSec to run discriminator JMP START DISCRIM igo turn on discriminator SET DS AT 20 EQU 5 gt Lid LDAA 40 DS instantaneous timerz20ms STAA INST TIMER store to INST timer START DISCRIM EQU 5 BSET INST FLAGS I TIMR BIT set INST timer bit start INST timer JMP EEPROM ERASE can t be PE cr erase EEPROM NOT AN SE EQU 5 p seeeieeeeieoeeee TE WE HAVE PE THE BREAKER BIT IS SET HERE deyer dee deek idet vew ew CHECK FOR PE EQU 5 08 gt Jis it pe breaker BNE CHECK EE ERASE no branch SET PE BIT 5 if brkr type is undefined then set to PE BSET FLAGSS PE set PE breaker bit 1f PE breaker check is moved then a LDAB must be added to the CHECK EE ERASE routine CHECK EE ERASE pr IP BREAKER TYPE CODE IS AN THEN CLEAR THE EEPROM eee CMPB SWITCH_MASK 21 breaker type erase all EEPROM BNE NO EEPROM ERASE type so don t erase EEPROM JMP EEPROM ERASE 240 erase the EEPROM amp trip the breaker NO EEPROM ERASE EQU JSR SENSOR BREAKR 4 breaker sensor conversion for t routin SET THE THREE RMS PHASE TIMERS AT STAGGERED TIMES
205. utine storage for result HS USED ACCA ACCB IX IY RESTORED NOTHING TEMP USED RESULT USED dodo dew deiode de dodo dede e ve dde c de c ede de Hee de de e e e e e e c de ede ede de ede dede de dee DO GF CONV EQU 5 LDAA PEAK get peak of GF STAA 1 store for use CLR TEMP clear high byte GO DO IT LDY get peak current location LDX TO PHASE get conversion value location JSR 16 16 conversion LDD RESULT41 get result 256 for integer math STD TEMP save for conversion to xmit value BSET FLAGS USE XS set bit for 1xS in I conv routine TEMP location of converted value LDX 5 CURRENT xmit buffer location CONTINUE TO CURRENT CONVERSION ROUTINE r ROUTINE TO CONVERT DATA FROM RAW A D TO SERIAL FORMAT CALLED With 4 IY LOCATION OF CURRENT TO CONVERT to serial format 2 IX LOCATION TO STORE CONVERTED CURRENT INTO USUALLY BUFFER Hn SENSOR SIZE AND RATING PLUG ARE USED TO DETERMINE THE 27 CONVERSION VALUE ES USE XS BIT is set if conversion is done on a GF value RETURNS Current in serial format in memory location pointed to by IX USED ACCA ACCB IX IY RESTORED NOTHING e ee e ee e e e eode de e
206. verage clear out high byte for mean value store high byte of the mean save X for later use AVERAGE IS FINISHED BEING CALCULATED GUESS 0 RMS_SQROOT RMS SOROOT RMS_MEAN 1 REMAINDER RESULT RMS_MEAN 3 REMAINDER RMS SOROOT REMAINDER RESULT RESULT shift left for guess value load Y with GUESS location add in offset from accb load indexed guess into store off initial quess in case of luck reload guess 7get mean for dividend the division start shifting to clear low nibble to bring in next nibble to continue division process zall shifts done low nibble is clear save remainder for use put ACCX into ACCD to work with quotient start shifting quotient to make room for next division result least significant nibble now clear store off the result get low byte of mean value do 4 shifts to move the high nibble to _ the low nibble shifts are all done out high byte add remainder to low nibble for new dividend get divisor again for next divide divide shift the remainder to make room for the final nibble low nibble now 0 store off remainder for later use swap to get quotient into add new result to last result four shifts to make room for the next nibble shifting all done save the result 5 136 458 109 110 LDAB RMS MEAN 3 low byte ANDB mask o

Microcomputer based electronic trip system for circuit breakers

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