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1. Use this clock ncikO frequency 50 000 MHz Clock Ep Settings A Setti incikO fr y 50 ctual Sett Operation Mode Normal d BO Enter output clock frequency 65 00000000 MHz 65 000000 Enter output clock parameters Tz Clock multiplication factor LU lt lt Copy Clock division factor v Clock phase shift Ta deg Clock duty cycle 50 00 Description rimary clock f Note The displayed internal settings of the Primary clock VCO frequency MHz PLL is recommended for use by advanced Modulus for M counter users only ai Koma bt satan Per Clock Feasibility Indicators c0 Figure 8 Selecting output clock frequency Press Finish again to generate the component The new component should now be visible in the design manager window Adding the generated PLL into the block diagram of VGA_ top is done by first selecting the green component symbol at the top of the VGA_top struct block diagram window then drag and drop the PLL component from the component browser window into the block diagram Select yes if asked about adding an additional library definition of altera_mf 1 5 4 Graphics_gen component The Graphic gen component contains the logic that controls the memory and the computer monitor It should consist of the two blocks Memory interface and VGA controller The Memory interface shall produce the SRAM address and control signals while VGA_ controller generates monitor c2. incikO frequency 50 000 MHz Able to implement the requested PLL Operation Mode Normal Cik Ratio Ph da DC 3 General cof 171 0 00 50 00 Which device speed grade will you be using Any Use military temperature range devices only What is the frequency of the incikO input MHz a Set up PLL in LVDS mode Data rate P Mbps PLL Type Which PLL type will you be using Fast PLL Enhanced PLL Select the PLL type automatically Operation Mode How will the PLL outputs be generated Use the feedback path inside the PLL In normal mode In source synchronous compensation Mode In zero delay buffer mode Connect the fbmimic port bidirectional C With no compensation Create an fbin input for an external feedback External Feedback Mode Which output clock will be compensated for a P Figure 7 Defining input frequency of the PLL The first of the windows used to specify parameters for the PLL 1s shown in Figure 6 Specify the input clock frequency 50 MHz Press Next Make sure there will be areset and locked signals on the component are shown in the next window and adjust the settings if necessary Then select the window tab named 3 Output clocks at the top of the window Select to specify output frequency and enter 65 MHz as shown in Figure 8 Press Finish MegaWizard Plug In Manager page 8 of 14 k pun c0 Core External Output Clock Able to implement the requested PLL
3. HTML R ModelSim Flow Visualization ga Precision Synthesis _ VGA_library Ms Precision Synthesis Flow GA_library New Add a sayeiduia psusel Project GA_library Tasks Templates Figure 4 Altera Megawizard available in the middle of the right column The dialog window shown in Figure 5 appears Make sure that the library definition is the library of lab2 If not select Specify library and select the correct library Press OK Read the warning that follows and remember to not change the directory path only add the component name in the window that is opened next The MegaWizard applications first window presented Select to create a new custom megafunction variation and select Next Altera MegaWizard Altera Installation Enter Altera installation path f not specified P4TH is used Installation Path GUARTUS_ROOTDIR Browse L Ce rg ab gD i fe A pte Create new megafunction variation Variation Mame aae HOL se Import existing megafunction variation impart from J impot core in a single directory for Gls synthesis x Application Use default library Yas library Quartus r Guartuys Il se Specify library KEYBOARD New se Max PLUS II Defaults OK Cancel Figure 5 Altera Megawizard start window F MegaWizard Plug In Manager page 2a x Which megafunction would you like to customize which device family will you be using Cyclo
4. T std logic vector The red component of the display rgb signal Always set 7 downto 0 the unused lower 2 bits to 0 vga g OUT std logic vector The green component of the display rgb signal Always 7 downto 0 set the unused lower 3 bits to 0 vga b OUT std logic vector The blue component of the display rgb signal Always set 7 downto 0 the unused lower 3 bits to 0 vga hsync n OUT std logic The display horizontal sync pulse active low vga vsync n OUT std logic The display vertical sync pulse active low sram data IN std_logic vector 15 downto 0 The display data from SRAM sram address OUT std_logic vector The address to display data SRAM Always set unused 19 downto 0 bits to 0 sram we n OUT std logic SRAM write enable Set to 1 while reading image sram oe n OUT std logic SRAM output enable Set to 0 while reading image sram ce n OUT std logic SRAM chip select Set to 0 while reading image sram lb n OUT std logic SRAM lower byte strobe Set to 0 while reading image sram ub n OUT std logic SRAM upper byte strobe Set to 0 while reading image HEX7 OUT std logic vector Most Significant Digit of your lab group number See 6 downto 0 labl for more information HEX6 OUT std logic vector Least Significant Digit of your lab group number See 6 downto 0 labl for more information GLED OUT std logic vector Two green LED one indicating PLL lock state the other 1 downto 0
5. VGA Graphics Controller using SRAM Memory TSTE12 version 0 3 This lab will introduce the use of IP units as well as hierarchical schematic entry This section discusses the design of a graphics controller driving a computer monitor Included is a description of the timing for the signals that drive a monitor and a description of an VHDL module that will let you drive a monitor with a picture stored in the SRAM memory The top level description of the design 1s shown below in Figure The system consists of the computer monitor connected to the FPGA board The FPGA board contains the SRAM with the image inside the FPGA and a 50 MHz clock source Inside the FPGA will a PLL structure create a 65 MHz clock used by all the logic VGA Controller and Memory Interface Two green LED will also indicate clock rate and reset state i FE a I rere ete ee ig VGA_top Graphic_gen 7 DiV65M Conmputer VGA Monitor reset_n Controller p gt vy zo y Oo Z ai Memory oom PLL Interface SIRAM FPGA Figure 1 Overview of the complete system 1 VGA Graphics Controller VGA_ top The XGA resolution computer monitor is connected to the FPGA board through a 15 pin mini DSUB VGA connector This connector contains three analog color information signal ground signals
6. and two synchronization signal HSYNC and VSYNC The image to be shown is stored in the SRAM memory 1 1 Requirements Here are the requirements to pass the laboratory e Implement the design using hdl designer e The two leftmost 7 segment displays shall indicate your lab group number e The rightmost right green LED should blink with a rate of 1 s and The second to right should indicate current lock signal of the PLL The blink rate should be controlled by the internal 65 MHz clock not the SOMHz clock e Declare a symbol and corresponding VHDL view e Create the model in hdldesigner with one block for each process Call the top level VGA top Use at least three hierarchy levels including the top level symbol VGA top For example divide the unit into a sync generation part and a color generation part e Itis not allowed to have more than one clock domain disregarding the PLL The best way to check this is to not have more than one signal appearing on statements using event or the rising edge function call e Synthesize the design and demonstrate the function on the DE2 115 FPGA board 1 2 VGA Color Signals There are three signals red green and blue that send color information to a VGA monitor In an CRT monitor drives each of these three signals an electron gun that emits electrons which paint one primary color at a point on the monitor screen Analog levels between 0 completely dark and 0 7 V maximum brightness on th
7. ata Use this in a testbench that you create and look at the red green and blue signals together with the blank and sync signals 1 7 Synthesis flow using Precision Follow the steps lined up in the keyboard laboratory exercise 1 8 Downloading the Design Follow the steps described in the keyboard laboratory exercise 2 Document history 120620 Add PLL change resolution to 1024x768 with pixel word switch to DE2 115 board using SRAM 100909 V0 2 Updated pin names to avoid clash with reset_n and clarify active level by adding n Fix pseudo code to indicate 4 pixels word Clarify the polarity of vga blank n 100902 V0 01 First version addressing the DE2 70 using FLASH 13
8. egin a minimum of 2 46 us 160 65e6 after the horizontal sync pulse ends So a single line occupies 15 75 us of a 20 68 us interval The other 4 93 us of each line is the horizontal blanking interval during which the screen is dark In an analogous fashion negative pulses on a vertical sync signal mark the start and end of a frame made up of video lines and ensure that the monitor displays the lines between the top and bottom edges of the visible monitor screen The lines are sent to the monitor within a 15 88 ms window The vertical sync signal drops low a minimum of 62 us 3 lines after the last line and stays low for 0 124 ms 6 lines The first line of the next frame can begin a minimum of 0 60 ms 29 lines after the vertical sync pulse ends So a single frame occupies 15 88 ms ofa 16 67 ms interval The other 0 79 ms of the frame interval is the vertical blanking interval during which the screen is dark 1 4 VGA Signal Generator Algorithm We now have to figure out a process that will send pixels to the monitor with the correct timing and framing We can store a picture in the SRAM of the DE2 115 Board Then we can retrieve the data from the SRAM format it into lines of pixels and send the lines to the monitor with the appropriate pulses on the horizontal and vertical sync pulses An example of pseudocode for a single frame of this process is shown in Figure 3 The pseudocode has two outer loops one which displays the L lines of visible pi
9. ese control lines tell the monitor what intensities of these three primary colors to combine to make the color of a dot or pixel on the monitor s screen Each individual analog color input can be set to one of 2 256 levels by controlling the corre sponding digital 8 bit input vector either vga r vga g or vga b to the digital to analog converters in the VGA DAC chip The 256 possible levels on each analog input are combined by the monitor to create a pixel with one of 256x256x256 16 M different colors 1 3 VGA Signal Timing The monitor image is painted by controlling the focal point of the electron gun focus point the color using deflection circuits The focal point is moved line by line on the monitor starting from the top left corner and ending at the bottom right corner The number of lines and the number of pixels on each line defines the resolution of the image in this lab it will be 1024x768 pixels XGA resolution The deflection circuits require two synchronization signals in order to start and stop the deflection circuits at the right times so that a line of pixels is painted across the monitor and the lines stack up from the top to the bottom to form an image The waveforms sent to the VGA 1s shown in Figure 2 with the expected frequency and times given in the DE2 115 user manual see also Table 1 XGA 60HZz is used in this lab mi iy RGB il an Vsync aaa PE Na
10. flashing with 1 second cycle time Pin location for these signals can be found in the board documentation available at sw altera kits DE2 DE2 user manual DE2 UserManual pdf sw altera kits DE2_ 70 SYSTEM cd v1 2 DE2 70 SYSTEN cd v1 2 DE2 70 user manual DE 2 70 User manual v107 pdf or sw altera kits DE2 115 v1 0 5 SystemCD DE2 115 user manual DE2 115 User manual pdf 1 5 2 Interface The synthesis tool needs to know how the FPGA is connected to the external world An attribute description included in the the VHDL description will be used for this purpose How to include this into the design was described in the keyboard exercise With guidance from the port definitions each group has to create its own attribute description All necessary information is found in the documentation of the DE2 115 education board users manual 1 5 3 Top level Structure of the VGA Signal Generator The pseudocode and pipeline timing in the last section will help us to understand the structure and create the VHDL code for a VGA signal generator 1 5 3 1 Inputs and outputs fpga_clk The input for the 50 MHz clock of the DE2 115 board It should only be used as input to the PLL that will use this clock as a reference and create a new 65 MHz clock that will be used in the rest of the design fpga_reset_n Reset the PLL Will stop the clock generation when fpga reset n 0 Connect this to one of the push buttons on the board vga_clk The vga clk is
11. lines are displayed The blanking signal is active high 11 blank_syncr This process describes the operation of the pipelined video blanking signal Within the process the blanking signal is stored in a register so it can be used during the next stage of the pipeline when the color is computed Computation of the combinatorial blanking signal The total blank is calculated as vga blank n not hblank OR vblank SRAM_control The SRAM is permanently selected and writing to the SRAM is disabled It stores the video data The image we will display is stored in a linear sequence of words inside the SRAM The address to the SRAM 1s a linear counter updated every clock cycle whenever the hblank is not active The counter can be reset to 0 whenever the vertical blanking is started pixel reg This process describes the operation of the register that holds the word 16 bits of pixel data read from SRAM The register is asynchronously cleared when the VGA circuit is reset The register is updated on the rising edge of each fpga clock 65M vga_gen This process describes the process by which the current active pixel is mapped into the 24 bits that drive the red green and blue color guns The register is set to zero which displays as the color black when the reset input is low The color register 1s clocked on the rising edge of the fpga clock 65M clock since this is the rate at which new pixel values arrive The value clocked into the regi
12. ne IV E 3 Select a megafunction from the list below O Which type of output file do you want to create ii AHDL D VHDL 4 ALTASMI_PARALLEL 4 ALTCLKCTRL Verilog HDL lt ALTDDIO_BIDIR 4 ALTDDIO_IN 2 What name do you want for the output file da ALTDDIO_OUT tmp megawizard PLL me Return to this page for another create operation aa 4 ALTDQ 4 ALTDQS N ae Note To compile a project successfully in the Quartus II software your ute design files must be in the project directory in a library specified in the Libraries page of the Options dialog box Tools menu or a library specified in the Libraries page of the Settings dialog box Assignments menu N 4 ALTINT_OSC S4 ALTIOBUF H4 ALTLVDS_RX 4 ALTLVDS_TX 4 ALTMEMPHY Your current user library directories are Phase locked loop PLL megafunction Cancel lt Back Next gt Finish Figure 6 Selecting name and type of IP block The 2 window of the MegaWizard is shown Carefully add the name PLL to the end of the output filename path should still point to tmp The device family should be set to Cyclone IV E and VHDL output file be selected Open the I O folder in the left subwindow and select the function ALTPLL as seen in Figure 6 Press Next MegaWizard Plug In Manager page 3 of 14 About Documentation Inputs Lock gt Bandwidth SS iove Currently selected device family Match project default
13. ontrol signals and translates the incoming sram_ data into red green and blue color data The following description shows one way to implement this functionality 10 1 5 4 1 Signals hent vent The counters that store the current horizontal position within a line of pixels and the vertical position of the line on the screen We will call these the horizontal or pixel counter and the vertical or line counter respectively The line period is 20 68 us that is 1344 vga_ clk cycles so the pixel counter needs at least eleven bits of resolution Each frame is composed of 806 video lines only 768 are visible the other 38 are blanked so a ten bit counter 1s needed for the line counter pixrg The 16 bit register that stores the pixel received from the SRAM hblank vblank pblank The video blanking signal and its registered counterpart that is used in the next pipeline stage 1 5 4 2 Processes pixelcounter This process describes the operation of the horizontal pixel counter The counter is synchronously set to zero when the fpga reset nis applied The counter increments on the rising edge of each fpga clock 65M cycle The range for the horizontal pixel counter is 0 1343 When the counter reaches 1343 it rolls over to zero on the next cycle Thus the counter has a period of 1344 pixel clocks With a pixel clock of 65 MHz this translates to a period of 20 68 us linecounter This process describes the operation of the vertical line c
14. ounter The counter is synchronously set to zero when the reset input is low The counter increments when the rising edge of the horizontal sync pulse is detected that is after a line of pixels is completed The range for the vertical line counter is 0 805 When the counter reaches 805 it rolls over to zero on the next cycle Thus the counter has a period of 806 lines Refer to the the tables in the end of 1 3 VGA Signal Timing for more information on the length of each subpart hsyncr This process describes the operation of the horizontal sync pulse generator The horizontal sync is set to its inactive high level when the reset is activated During normal operations the horizontal sync output is updated on every pixel clock Refer to the the tables in the end of 1 3 VGA Signal Timing for more information on the length of each subpart Here is also the hblank signal created The video is blanked after the 1024 pixels of a line are displayed The blanking signal is active high vsyncr This process describes the operation of the vertical sync pulse generator The vertical sync is set to its inactive high level when the reset is activated During normal operations the vertical sync output is updated after every line of pixels is completed Refer to the the tables in the end of 1 3 VGA Signal Timing for more information on the length of each subpart Here 1s also the vblank signal created The video is blanked after 768
15. r RGB Hsync Figure 2 VGA waveforms VGA mode Horizontal Timing Spec Configuration Resolution HxV a us b us c us d us Pixel clock MHz VGA 60Hz 640x480 3 8 1 9 25 4 0 6 25 VGA 85Hz 640x480 1 6 2 2 17 8 1 6 36 SVGA 60Hz 800x600 3 2 a2 20 1 40 SVGA 75Hz 800x600 1 6 3 2 16 2 0 3 49 SVGA 85Hz 800x600 By va d 14 2 0 6 56 XGA 60Hz 1024x768 2 1 2 5 15 8 0 4 65 XGA 70Hz 1024x768 1 8 1 9 13 7 0 3 75 XGA 85Hz 1024x768 1 0 a2 10 8 0 5 95 1280x1024 60Hz 1280x1024 1 0 2 3 11 9 0 4 108 VGA mode Vertical Timing Spec Configuration Resolution HxV a lines b lines c lines d lines Pixel clock MHz VGA 60HZz 640x480 2 33 480 10 25 VGA 85Hz 640x480 3 25 480 1 36 SVGA 60Hz 800x600 4 23 600 1 40 SVGA 75Hz 800x600 3 21 600 1 49 SVGA 85Hz 800x600 3 27 600 1 56 XGA 60Hz 1024x768 6 29 768 3 65 XGA 70Hz 1024x768 6 29 768 3 75 XGA 85Hz 1024x768 3 36 768 1 95 1280x1024 60Hz 1280x1024 3 38 1024 1 108 Table 1 Detailed timing for various screen resolutions Negative pulses on the horizontal sync signal mark the start and end of a line and ensure that the monitor displays the pixels between the left and right edges of the visible screen area The actual pixels are sent to the monitor within a 15 75 us 1024 65e6 window The horizontal sync signal drops low a minimum of 0 37 us 24 65e6 after the last pixel and stays low for 2 1 us 136 65e6 A new line of pixels can b
16. re one of 65536 levels of color or gray The mapping from the 16 bit pixel value to the actual values required by the monitor electronics is done by the COLOR MAP routine In this design we only make use of 65536 colours with 6 bits red bits 15 downto 10 and 5 bits each for green bits 9 downto 5 and blue 4 downto 0 Reading memory will take one clock cycle applying the address at one rising clock edge and reading data at the next rising clock edge Applying the color mapping and sending the pixel to the pins may take additional time It is therefore important to understand the timing of the design especially related to the blanking signals It may therefore be necessary to add additional delaty to the blanking signals Failing this may cause the image to lack color on the edges of the image or have duplicated pixels on the image edges 1 5 Problem definition Here are the definitions listed that are needed to complete the design 1 5 1 Port definitions The inputs and outputs of the circuit as defined are as follows Name Type Range Description fpga clk IN std logic The system clock fpga reset n IN std logic The circuit reset signal Reset is active low 1 e fpga reset n 0 gives reset vga clk OUT std logic The DAC clock signal Typically pixel clock signal vga sync OUT std logic Not in use Inactivate this with a logical 0 vga blank n OUT std logic The blank signal from the design vga r OU
17. self fpga_clock_65M Internal FPGA clock generated by the PLL component This should be the only clock signal used by the rest of the design excluding the 50 MHz clock used as input to the PLL component It is connected to the c0 output of the PLL reset_n Internal reset signal This is a copy of the locked signal from the PLL The rest of the design should be reset when reset_n is 0 This should also be shown on one of the green LEDs 1 5 3 3 Components These three components should be placed 1n the top level that is the structural description of the VGA _ top component The two components Div65M and Graphic gen is added by simply selecting the blue component block symbol while the PLL must first be created separately and then added to the structure Div65M Divides the 65MHz clock frequency by 65 000 000 thereby producing a alternating output signal blinking with a second cycle Build this as a counter that counts from 65 000 000 2 downto 0 and when reaching zero inverts the output bit and restarts counting Graphic_gen The part of the design that generates monitor control signals generates an SRAM memory address and output pixel color based on the data from the SRAM memory Details is described later PLL This is an example of an IP block This component creates a 65 MHz clock signal used in the rest of the design It is based on a hardware block in the FPGA consisting of both analog and digital circuitry such as
18. ster is a function of the pixel value and the blanking input When the pipelined blanking input is low inactive the color displayed on the monitor is a color value depending the input value from SRAM This means we send different parts of the SRAM value to all the RGB inputs to achieve a color image When the pipelined blanking input is high the color register is loaded with zero black 1 6 Tips and tricks To aviod a lot of trouble in the design phase a few hints are useful e Do not use multiple clock definitions i e use only one signal fpga clock 65M with EVENT or rising edge to define a clock The use of EVENT and LAST VALUE are not useful in the context of synthesis except for defining the rising or falling edge of the clock fpga clock 65M e Introductionto Megafunctions http www altera com literature ug ug intro to megafunctions pdf This document will explain how to create an function with mega wizard e Let the top level design only contain the PLL the LED driver and one block containing the total VGA controller This allows the VGA simulation to be run without having to simulate the PLL the PLL 1s time consuming to simulate e Usea simple model of the SRAM contents to figure out if the timing is correct The simulation model of the SRAM should have a signal update delay of approximately 4 ns and give different data outputs for each address e g copy the 16 least significant bits of 12 the address to the d
19. used by the DAC to clock the individual pixels Create this by inverting the internal 65 MHz clock The pixel and sync signals should then be stable when the positive edge of vga_clk reaches the DAC chip vga_hsync_n vga_vsync_n The outputs for the horizontal and vertical sync pulses vga_blank_n The output for the display blank signal A 0 on this signal forces the DAC chip to blank its outputs vga_r vga_g vga_b The outputs that is used by the DAC chip to create the red green and blue analog color gun signals Each pixel in the memory encodes the pixel color as three parts lt r5 r0 g4 g0 b4 g0 gt the 6 leftmost bits MSB bits should be used as MSB bits for vga r etc The remaining unused lower bits in the vga r vga g and vg b output should be set to 0 SRAM_address SRAM_ data The outputs for driving the address lines of the SRAM memory and the inputs for receiving the data from the SRAM SRAM_oe_n SRAM_we_n SRAM_ce_n SRAM_Ib_n SRAM_ub_n Control signals for the SRAM interface Forces the SRAM to be read all the time using 16 bit data interface More information is available in the DE2 115 users manual and SRAM datasheet 1 5 3 2 Signals Signal can be added directly into the block diagram The name and type of these signals are automatically set to be equal to the name and type of the port that they are connected to Names can be changed by double clicking on the name in the block diagram or on the wire it
20. voltage controlled oscillators dividers filters etc It is possible to create and synchronize multiple clocks using one input clock as a reference The IP block will not be synthesized is the usual way creating a netlist of lookup tables and flip flops The IP will instead consist of a simulation model useful for verifying the function using simulation and a post synthesis configuration information used to configure the PLL in the FPGA Creation of the simulation model and configuration information for the PLL is done using a special software package called Altera MegaWizard It 1s started from HDL designer by first pressing on Tasks templates on the right edge of the Design manager window Double click on the Altera MegaWizard icon as shown in Figure 4 Design Manager Project my_project File Edit View HDL Tasks Tools Options Window Help 8 8 B 14 exea anaa B S oe SRY B M Man Design Explorer Using viewpoint Default Viewpoint Filtered aA Z al Tasks Design Unit Extends PeGrPeECeMn Gi My Tasks Bs Generate HOL CY GA_library H E GA_top Component p B7 3 DesignChecker Bf S DesignChecker Flow be g Quartus Il Synthesis g Quartus Il Synthesis Flow Quartus Place and Route Quartus Programmer Altera SOPC Builder A Altera MegaWizard FPGA Technology Setup FPGA Library Compile Extends Size M7 ModelSim Compile ind DesignChecker Documentation amp Visualiz M MORRO Simulate LC
21. xels and another which inserts the V blank lines and the vertical sync pulse Within the first loop there are two more loops one which sends the P pixels of each video line to the monitor and another which inserts the H blank pixels and the horizontal sync pulse for line_cnt 1 to L send L lines of video to the monitor for pixel_cnt 1 to P send P pixels for each line data RAM address get pixel data from the memory address address I FLASH data word contains 4 pixels color COLOR _MAP data get the color for the right bit pixel send color to monitor pixel_cnt pixel cnt l for horiz blank cnt 1 to H blank the monitor for H pixels color BLANK send color to monitor pulse the horizontal sync at the right time if horiz _ blank cnt gt HB0 and horiz blank cnt lt HB1 hsync 0 else hsync 1 horiz blank cnt horiz blank cnt 1 line cnt line cnt 1 for vert_blank_cnt 1 to V blank the monitor for V lines and insert vertical sync color BLANK send color to monitor pulse the vertical sync at the right time if vert_blank_cnt gt VBO and vert_blank_cnt lt VB1 vsync 0 else vsync l vert_blank_cnt vert blank cnt I go back to start of picture in memory address 0 Figure 3 VGA signal generation pseudocode Within the pixel display loop there are statements to get the next word from the SRAM Each word contains one pixel Since it has only 16 bits each pixel can sto
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