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A10 User manual V1.20 20120409

1. 110 EINT12 111 CSI D12 15 PH11 SELECT 000 Input 001 Output 010 LCD1 D11 011 ATAD7 100 KP_IN3 101 MS_D3 14 12 R W 0 110 EINT11 111 CSI D11 11 PH10_SELECT 000 Input 001 Output 010 LCD1_D10 011 ATAD6 100 KP_IN2 101 MS_D2 10 8 R W 0 110 EINT10 111 CSI DIO 7 PH9 SELECT 000 Input 001 Output 010 LCD1_D9 011 ATADS 100 KP INI 101 MS DI 6 4 R W 0 110 EINT9 111 CSI1 D9 PH8 SELECT 000 Input 001 Output 010 LCD1_D8 011 ATAD4 100 KP INO 101 MS DO 2 0 R W 0 110 EINT8 111 CSI1 D8 30 3 66 PH Configure Register 2 Register Name PH CFG2 Offset 0x104 Default Value 0x0000 0000 Bit Read Write Default Description 31 PH23 SELECT 000 Input 001 Output 010 LCD D23 011 ATACSO 100 KP OUT3 101 SDC1 CLK 30 28 R W 0 110 Reserved 111 CSI1 D23 27 PH22 SELECT 000 Input 001 Output 26 24 R W 0 010 LCD D22 011 ATADACK A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 2012 04 09 322 Ou Allwinner Technology CO Ltd A10 100 KP OUT2 101 SDC1 CMD 110 Reserved 111 CSI1 D22 23 PH21 SELECT 000 Input 001 Output 010 LCD1_D21 011 ATADREQ 100 CAN RX 101 Reserved 22 20 R W 110 EINT21 111 CSH D21 19 PH20 SELECT 000 Input 001 Output 010 LCD1_D20 011 ATAOE 100 CAN TX 101 Reserved 18
2. A10 30 3 53 PF Pull Register 0 Register Name PF PULLO Offset 0xDO Default Value 0x0000 0000 Bit Read Write Default Description 31 12 PF PULL PF n Pull up down Select n 0 5 21 1 2i 00 Pull up down disable O1 Pull up i 0 5 R W 0x0 10 Pull down 11 Reserved 30 3 54 PF Pull Register 1 Register Name PF_PULL1 Offset 0xD4 Default Value 0x0000_0000 Bit Read Write Default Description 31 0 30 3 55 PG Configure Register 0 Register Name PG_CFG0 Offset 0xD8 Default Value 0x0000_0000 Bit Read Write Default Description 31 PG7_SELECT 000 Input 001 Output 010 TS1_D3 011 CSI D3 100 UART3 RX 101 CSIO_D11 30 28 R W 0 110 Reserved 111 Reserved 27 PG6_SELECT 000 Input 001 Output 010 TS1_D2 011 CSH_D2 100 UART3 TX 101 CSIO D10 26 24 R W 0 110 Reserved 111 Reserved 23 PG5 SELECT 000 Input 001 Output 010 TS1 DI 011 CSH_D1 100 SDC1_D3 101 CSIO_D9 22 20 R W 0 110 Reserved 111 Reserved A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 316 2012 04 09 N Allwinner Technology CO Ltd A10 19 PG4 SELECT 000 Input 001 Output 010 TS1 DO 011 CSII DO 100 SDC1_D2 101 CSIO D8 18 16 R W 0 110 Reserved 111 Reserved 15 PG3 SELECT 000 Input 001 Output 010 TS1 DVLD 011 CSI VSYNC 100 SDC1 DI 101 Reserved 14 12
3. 2 1 lge Te nsee ronpssso6assssra6 nss so aaS nsei donp Po sessa skoso 24 1 Feie 24 1 1 1 CPU gire 24 1 1 2 E BEE 25 1 1 3 K RE 25 1 1 44 Display Processing Ability cccciscccccccssscovasceessssesveostasceossssedsconuasstessouccuensvtodtenseetecsavtecteostasdoenes 25 LL Display Output Ability eee ettet tere t he ee eterne vet teen eae 25 1 1 6 Image Input Ability ndm n OSEE ES E rm E SEE 26 LET Mennene 26 1 1 8 Peripheral cy geteilt deele 26 1 1 9 SYSUEM EE 27 INL ME eiu 27 TLI SO 27 2 Pin Description eeeseceveeevvenneenneenneenneenneenneenneenneennesnneennnsnneennnsnneennnennnennnennnenneennnennnennnennnennnennnennnenenennnenesee 27 SE Pin Placement Tables T E 27 2 2 Pin Detail Descrpton i oce med aped n aE Se INTO NER PEERS NE 27 3 Architecture 28 3 1 General Block Didgr m e ie trente e eterne eet re o re e eben re e eres eee 28 32 Memory ET 29 4 Boot Mod R 32 LEE QST 32 GR EE EE 33 FEE irs MDC n 34 SEE eO ae 34 6 Clock Control Module eere eese esee eese eisien aas 35 Oli OVERVIEW 35 62 Clock Tree REG 35 63 CCM Register List et
4. CLKNOn Y Y 108MH2 1 1 nl i i i i CH2 D1 CH3 D1 CH4 D1 VDn 7 0 Figure31 7 31 4 5 CCIR656 Header Code CCIR656 Header Data Bit Definition Data Bit First Second Third Fourth Word Word 0xFF Word 0x00 Word 0x00 CS D 9 MSB 1 0 0 1 CS D 8 1 0 0 F CS D 7 1 0 0 V CS D 6 1 0 0 H CS D 5 1 0 0 P3 CS D 4 1 0 0 P2 CS D 3 1 0 0 P1 CS D 2 1 0 0 PO CS D 1 x x x x A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 337 2012 04 09 Allwinner Technology CO Ltd A10 CS D 0 x x x x For compatibility with an 8 bit interface CS D 1 and CS D 0 are not defined Decode F V H P3 P2 P1 PO Field 1 start of active video SAV 0 0 0 0 0 0 0 Field 1 end of active video EAV 0 0 1 1 1 0 1 Field 1 SAV digital blanking 0 1 0 1 0 1 1 Field 1 EAV digital blanking 0 1 1 0 1 1 0 Field 2 SAV 1 0 0 0 1 1 1 Field 2 EAV 1 0 1 1 0 1 0 Field 2 SAV digital blanking 1 1 0 1 1 0 0 Field 2 EAV digital blanking 1 1 1 0 0 0 1 Multi Channel Fourth Field V time H time F V H First Second Third Ch1 Ch2 Ch3 Ch4 EVEN BLANK EAV OxFF 0x00 0x00 OxFO OxF1 OxF2 OxF3 EVEN
5. TMR2 INTV VALUE REG 0x0034 Timer 2 Interval Value TMR2 CUR VALUE REG 0x0038 Timer 2 Current Value TMR3 CTRL REG 0x0040 Timer 3 Control TMR3 INTV VALUE REG 0x0044 Timer 3 Interval Value TMR4 CTRL REG 0x0050 Timer 4 Control TMR4 INTV VALUE REG 0x0054 Timer 4 Interval Value TMR4 CUR VALUE REG 0x0058 Timer 4 Current Value TMR5 CTRL REG 0x0060 Timer 5 Control TMR5 INTV VALUE REG 0x0064 Timer 5 Interval Value TMR5 CUR VALUE REG 0x0068 Timer 5 Current Value AVS CNT CTL REG 0x0080 AVS Control Register AVS CNTO0 REG 0x0084 AVS Counter 0 Register AVS CNT1 REG 0x0088 AVS Counter Register AVS CNT DIV REG 0x008C AVS Divisor WDOG CTRL REG 0x0090 Watchdog Control WDOG MODE REG 0x0094 Watchdog Mode CNT64 CTRL REG 0x00A0 64 bit Counter control CNT64 LO REG 0x00A4 64 bit Counter low CNT64 HI REG 0x00A8 64 bit Counter high LOSC CTRL REG 0x0100 Low Oscillator Control RTC YY MM DD REG 0x0104 RTC Year Month Day RTC HH MM SS REG 0x0108 RTC Hour Minute Second DD HH MM SS REG 0x010C Alarm Day Hour Minute Second ALARM WK HH MM SS 0x0110 Alarm Week HMS ALARM EN REG 0x0114 Alarm Enable ALARM IRQ EN 0x0118 Alarm IRQ Enable ALARM IRQ STA REG 0x011C Alarm IRQ Status TMR GP DATA REGO 0x0120 Timer general purpose register O TMR GP DATA REGI 0x0124 Timer general purpose register 1 TMR GP DATA REG2 0x0128 Timer general purpose register 2 TMR GP DATA REG3 0x012C Timer general purpose register 3 CPU CFG REG 0x
6. 11 4 16 Interrupt Enable Register 2 Default 0x00000000 Offset 0x48 Register Name INTC EN REG2 Bit Read Default Description Write Hex 31 0 R W 0x0 Interrupt Source 95 64 Enable Bits 0 Corresponding interrupt is disabled 1 Corresponding interrupt is enabled 11 4 17 Interrupt Mask Register 0 Default 0x00000000 Offset 0x50 Register Name INTC MASK REGO Bit Read Default Description Write Hex 31 0 R W 0x0 Interrupt Source 31 0 Mask Bits 0 No effect 1 interrupt is masked If interrupt is enabled and the interrupt occurred the interrupt pending bit will be set whether the corresponding interrupt mask bit is set 11 4 18 Interrupt Mask Register 1 Default 0x00000000 Offset 0x54 Register Name INTC_MASK_REG1 Bit Read Default Description Write Hex 31 0 R W 0x0 Interrupt Source 63 32 Mask Bits 0 No effect 1 interrupt is masked If interrupt is enabled and the interrupt occurred the interrupt pending bit will be set whether the corresponding interrupt mask bit is set 11 4 19 Interrupt Mask Register 2 Default 0x00000000 Offset 0x58 Register Name INTC_MASK_REG2 Bit Read Default Description Write Hex 31 0 R W 0x0 Interrupt Source 95 64 Mask Bits 0 No effect 1 interrupt is masked If interrupt is enabled and the interrupt occurred the interrupt pending A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 117 2012 04 09
7. 24 2 4 DAC TX DATA register Offset 0xC Register Name AC DAC TXDATA Bit Read Write Default Description TX DATA Transmitting left right channel sample data should be written this register one by one The left channel sample 31 0 W 0x0 data is first and then the right channel sample 24 2 5 DAC Analog Control Register Offset 0x10 Register Name AC_DAC_ACTRL Bit R W Default Description DACAREN Internal DAC Analog Right channel Enable 31 R W 0x0 0 Disable 1 Enable DACALEN 30 R W 0x0 Internal DAC Analog Left channel Enable 0 Disable A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 258 2012 04 09 Ou Allwinner Technology CO Ltd A10 1 Enable MIXEN Analog Output MP Enable 0 Disable 1 Enable 29 R W 0x0 28 27 LNG Line in gain stage to output MP Gain Control 0 1 5dB 1 0dB 26 R W Ox1 FMG 25 23 R W 0x3 FM Input to output MP Gain Control From 4 5dB to 6dB 1 5dB step default is OdB MICG 22 20 R W 0x3 MIC1 2 gain stage to output MP Gain Control From 4 5dB to 6dB 1 5dB step default is OdB LLNS Left LINEIN gain stage to left output MP mute 19 R W 0x0 0 mute 1 Not mute When LNRDF is 0 left select LINEINL When LNRDF is 1 left select LINEINL LINEINR RLNS Right LINEIN gain stage to right output MP mute 18 R W 0x0 0 mute 1 Not mut
8. Bit Read Default Description Write Hex 31 R W 0x0 SCLK2_GATING Gating Special Clock 2 0 Clock is OFF 1 Clock is ON This special clock 2 Special Clock 2 Source Divider M 30 26 25 24 R W 0x0 SCLK2 SEL Special Clock 2 Source Select 00 PLL3 1X 01 PLL7 1X 10 PLL3 2X 11 PLL7 2X 23 18 17 16 15 R W 0x0 SCLK1_GATING Gating Special Clock 1 0 Clock is OFF 1 Clock is ON This special clock 1 Special Clock 1 Source 14 12 11 R W 0 SCLK1_SRC_SEL Special Clock 1 Source Select 0 Special Clock 2 1 Speical Clock 2 divide by 2 10 4 3 0 R W 0x0 CLK_DIV_RATIO_M Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 16 6 4 49 LCD 1 CH1 Clock Default 0x00000000 Offset 0x130 Register Name LCD1_CH1_CLK_REG Bit Read Default Description Write Hex 31 R W 0x0 SCLK2 GATING Gating Special Clock 2 0 Clock is OFF 1 Clock is ON This special clock 22 Special Clock 2 Source Divider M A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 69 2012 04 09 Ou Allwinner Technology CO Ltd A10 30 26 25 24 R W 0x0 SCLK2_SRC_SEL Special Clock 2 Source Select 00 PLL3 1X 01 PLL7 1X 10 PLL3 2X 11 PLL7 2X 23 18 17 16 15 R W 0x0 SCLK1_GATING Gating Special Clock 1 0 Clock is OFF 1 Clock is
9. Mode Serial Clock Frequency Mhz MIR 0 576M 6 912 12 0 576 MIR 1 152M 13 824 12 1 152 FIR 4M 24 For saving CPU resource CIR receiver is implemented in hardware The CIR receiver samples the inputting signal on the programmable frequency and records these samples into RX FIFO when one CIR signal is found on the air The CIR receiver uses Run Length Code RLC to saving bandwidth The FIFO is 8 bits width in the depth of 16 levels The MSB bit is used to record the parity of the receiving CIR signal The high level is represented as 1 and the low level is represented as 0 The rest 7 bits are used for the length of RLC The maximum length is 128 If the duration of one level high or low level is more than 128 the another byte is used On the air there are always some noise One threshold can be set to filter these noise to reduce system loading and improve the system stability 19 2 IR Timing Diagram Please refer to IrDA Specification 19 3 IR Register List Module Name Base Address IRO 0x01C21800 IR1 0x01C21C00 Register Name Offset Description IR CTL 0x00 IR Control Register IR TXCTL 0x04 IR Transmitter Configure Register IR TXADR 0x08 IR Transmitter Address Register IR TXCNT Ox0C IR Transmitter Counter Register IR_RXCTL 0x10 IR Receiver Configure Register IR_RXADR 0x14 IR Receiver Address Register IR_RXCNT 0x18 IR Receiver Counter
10. Ou Allwinner Technology CO Ltd A10 bit will be set whether the corresponding interrupt mask bit is set 11 4 20 Interrupt Response Register 0 Default 0x00000000 Offset 0x60 Register Name INTC RESP REGO Bit Read Default Description Write Hex 31 0 R W 0x0 Interrupt response bit If the corresponding bit is set the interrupt with the lower or the same priority level is masked 11 4 21 Interrupt Response Register 1 Default 0x00000000 Offset 0x64 Register Name INTC RESP REGI Bit Read Default Description Write Hex 31 0 R W 0x0 Interrupt response bit If the corresponding bit is set the interrupt with the lower or the same priority level is masked 11 4 22 Interrupt Response Register 2 Default 0x00000000 Offset 0x68 Register Name INTC RESP REG2 Bit Read Default Description Write Hex 31 0 R W 0x0 Interrupt response bit If the corresponding bit is set the interrupt with the lower or the same priority level is masked 11 4 23 Interrupt Fast Forcing Register O Default 0x00000000 Offset 0x70 Register Name INTC FF REGO Bit Read Default Description Write Hex 31 0 W 0x0 Enables the fast forcing feature on the corresponding interrupt source 31 0 0 No effect A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 118 2012 04 09
11. Ou Allwinner Technology CO Ltd A10 1 Forcing the corresponding interrupt Setting this bit can be valid only when the corresponding interrupt enable bit is set 11 4 24 Interrupt Fast Forcing Register 1 Default 0x00000000 Offset 0x74 Register Name INTC_FF_REG1 Bit Read Default Description Write Hex 31 0 W 0x0 Enables the fast forcing feature on the corresponding interrupt source 63 32 0 No effect 1 Forcing the corresponding interrupt Setting this bit can be valid only when the corresponding interrupt enable bit is set 11 4 25 Interrupt Fast Forcing Register 2 Default 0x00000000 Offset 0x78 Register Name INTC FF REG2 Bit Read Default Description Write Hex 31 0 W 0x0 Enables the fast forcing feature on the corresponding interrupt source 95 64 0 No effect 1 Forcing the corresponding interrupt Setting this bit can be valid only when the corresponding interrupt enable bit is set 11 4 26 Interrupt Source Priority 0 Register Default 0x00000000 Offset 0x80 Register Name INTC PRIO REGO Bit Read Default Description Write Hex 31 30 R W 0x0 IRQ 15 Priority Set priority level for IRQ bit 15 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 119 2012 04 09 Ou Allwinner Technology CO Ltd Offset 0x80 Register Name INT
12. Ou Allwinner Technology CO Ltd A10 1111 1 biggest 7 5 4 0 R W 0000 Internal DACO Amplitude Control 00000 smallest 11111 biggest 34 4 10 TV Encoder Auto Detection Enable Register Offset 0x030 Register Name TVE_030_REG Bit Read Default Description Write Hex 31 20 19 R W 0 DAC3_Auto_Detect_Interrupt_En 18 R W 0 DAC2 Auto Detect Interrupt En 17 R W 0 DAC1 Auto Detect Interrupt En 16 R W 0 DACH Auto Detect Interrupt En 15 4 3 R W 0 DAC3_Auto_Detect_Enable 2 R W 0 DAC2 Auto Detect Enable 1 R W 0 DAC1_Auto_Detect_Enable 0 R W 0 DACO Auto Detect Enable 34 4 11 TV Encoder Auto Detection Interrupt Status Register Offset 0x034 Register Name TVE 034 REG Bit Read Default Description Write Hex 31 4 3 R W 0 DAC3_Auto_Detect_Interrupt_Active_Flag write 1 to inactive DACH auto detection interrupt 2 R W 0 DAC2 Auto Detect Interrupt Active Flag write 1 to inactive DAC2auto detection interrupt 1 R W 0 DACI Auto Detect Interrupt Active Flag write 1 to inactive DACI auto detection interrupt 0 R W 0 DACO Auto Detect Interrupt Active Flag write 1 to inactive DACO auto detection interrupt A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 434 2012 04 09 Allwinner Technology CO Ltd A10 34 4 12 TV Encoder Auto Detecti
13. 6 4 46 CSI ISP Default 0x00000000 Offset 0x120 Register Name CSI ISP CLK REG Bit Read Default Description A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 67 2012 04 09 Write Hex Ou Allwinner Technology CO Ltd A10 31 R W 0x0 SCLK_GATING Gating Special Clock 0 Clock is OFF 1 Clock is ON This special clock Clock Source Divider M 30 26 25 24 R W 0x0 SCLK2_SRC_SEL Special Clock 2 Source Select 00 PLL3 1X 01 PLL4 10 PLLS 11 PLL6 23 4 3 0 R W 0x0 CLK_DIV_RATIO_M Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 16 6 4 47 TVD Clock Default 0x00000000 Offset 0x128 Register Name TVD_CLK_REG Bit Read Default Description Write Hex 31 R W 0x0 SCLK GATING Gating Special Clock 0 Clock is OFF 1 Clock is ON This special clock Clock Source 30 25 24 R W 0x0 CLK SRC SEL Clock Source Select 0 PLL3 1 PLL7 23 18 17 16 15 4 3 0 6 4 48 LCD 0 CH1 Clock Default 0x00000000 Offset 0x12C Register Name LCDO0 CH1 CLK REG A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 68 2012 04 09 Ou Allwinner Technology CO Ltd A10
14. Allwinner Technology CO Ltd A10 17 4 7 SPI Wait Clock Register Offset 0x18 Register Name SPI WAIT Default Value 0x0000 0000 Bit Read Write Default Description 31 16 15 0 R W WCC Wait Clock Counter In Master mode These bits control the number of wait states to be inserted in data transfers The SPI module counts SPI_SCLK by WCC for delaying next word data transfer 0 No wait states inserted N N SPI SCLK wait states inserted 17 4 8 SPI Clock Control Register Offset 0x1C Register Name SPI_CCTL Default Value 0x0000_0002 Bit Read Write Default Description 31 13 12 DRS Divide Rate Select Master Mode Only 0 Select Clock Divide Rate I 1 Select Clock Divide Rate 2 CDR1 Clock Divide Rate 1 Master Mode Only This field selects the baud rate of the SPI SCLK based on a division of the AHB_CLK These bits allow SPI to synchronize with different external SPI devices The max frequency is one quarter of AHB_CLK The divide ratio is determined according to the following table using the equation 2 n 1 The SPI SCLK is determined according to the following equation SPI_CLK AHB CLK 2 n 1 7 0 0x2 CDR2 Clock Divide Rate 2 Master Mode Only The SPI_SCLK is determined according to the following equation SPI CLK AHB CLK 2 n 1 A10 User Manual V1 20 Co
15. Bit Read Default Description A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 276 2012 04 09 Ou Allwinner Technology CO Ltd A10 Write Hex 0x0000_0F00 31 19 18 R W 0x0 17 R W 0x0 TP_OVERRUN_IRQ_EN TP FIFO Over Run IRQ Enable 0 Disable 1 Enable 16 R W 0x0 TP DATA IRQ EN TP FIFO Data Available IRQ Enable 0 Disable 1 Enable 15 14 13 R W 0x0 TP_DATA_XY_CHANGE TP FIFO X Y Data interchange Function Select 0 Disable 1 Enable 12 8 R W OxF TP_FIFO_TRIG_LEVEL TP FIFO Data Available Trigger Level Interrupt and DMA request trigger level for TP or Auxiliary ADC Trigger Level TXTL 1 R W 0x0 TP_DATA_DRQ_EN TP FIFO Data Available DRQ Enable 0 Disable 1 Enable 6 5 R W 0x0 TP_FIFO_FLUSH TP FIFO Flush Write 1 to flush TX FIFO self clear to 0 3 2 R W 0x0 TP_UP_IRQ_EN Touch Panel Last Touch Stylus Up IRQ Enable 0 Disable 1 Enable R W 0x0 TP_DOWN_IRQ_EN Touch Panel First Touch Stylus Down IRQ Enable 0 Disable 1 Enable 26 4 2 TP Interrupt amp FIFO Status Register Offset 0x14 Register Name TP_FIFOCS Bit Read Default Description A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology
16. eer the Er E NEES EEN 330 30 3 81 PI Pull Register L nte HD e ETE eee aeree EE e ERE EE e 330 30 3 82 PIO Interrupt Configure Register 0 rtr t rre a i 331 30 3 83 PIO Interrupt Configure Register 1 essent nennen 331 30 3 84 PIO Interrupt Configure Register 2 essere ener entren 331 30 3 85 PIO Interrupt Configure Register 3 332 30 3 86 PIO Interrupt Control Register iier rtr rrr ted ieri teer b edente ias 332 30 3 87 PIO Interrupt Status Register reet fett ener ei rte tv etapa Pur dE 332 30 3 88 PIO Interrupt Debounce Register A 333 31 CSIO with ISP 334 EN E e E 334 EE E tects seeaed Godesvatandeaebcynins sate eceavichwdsteeayeiensd Gudevsaitedd ewkcbeioivedoeeretibedeleadban yeaa 334 BUDA eege Ge 334 3122 eech EE DLE 334 EE Block diagrami no danno ts seco vedsn re vesszcsaydudiscavedauedoslucdscsvetaascaviuctosstud aeesySadteatis 335 ILI ASSIA POE 335 SUA KE 335 SL L CSI e TE 335 3L4 2 Tobit YO V 422 Minin EE 336 31 4 3 CCIR6562 channel TEE 336 31 4 4 CCIR656 4 channel Timing 4 terere ehe eee Reb aeree o ENEE 337 31 45 CCIR656 Header E 337 31 5 CSIO Register E 338 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 16 2012 04 09 Ou N Allwinner Technology CO Ltd A10 31 6 CSIO Register RE le EE 343 SLO CSIEnable Reglstet neuro terere e eire der hr re i iro et bre e deg 343 31
17. DRQ_EN TX FIFO Empty DMA Enable 0 Disable 1 Enable When set to 1 the Transmitter FIFO DRQ is asserted if reaching TEL The DRQ is de asserted when condition fails or specified number data has been sent from host CPU TEI EN TX FIFO Empty Interrupt Enable 0 Disable 1 Enable When set to 1 the Transmitter FIFO interrupt is asserted if reaching TEL The interrupt is de asserted when condition fails or specified number data has been sent from host CPU TCI EN Transmit including the CRC and STO fields Complete Interrupt Enable 0 Disable 1 Enable SIPEI EN Transmitter SIP End Interrupt Enable 0 Disable 1 Enable TPEI_EN Transmitter Packet the address control and data fields End Interrupt Enable 0 Disable 1 Enable R W TUL EN Transmitter FIFO Under run Interrupt Enable A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 207 2012 04 09 Ou Allwinner Technology CO Ltd A10 0 Disable 1 Enable 19 4 11 IR Transmitter Status Register Offset 0x28 Register Name IR_TXSTA Default Value 0x0000_1000 Bit Read Write Default Description 31 13 12 8 0x10 TA TX FIFO Available Room Counter 0 TX FIFO full 1 TX FIFO 1 byte room for new data 2 TX FIFO 2 byte room for new data 15 TX FIFO 15 byte room for new data 16 TX FIFO 16 byte room for new
18. 0x0 TMR2_EN Timer 2 Enable 0 Stop Pause 1 Start If the timer is started it will reload the interval value to internal register and the current counter will count from interval value to 0 If the current counter does not reach the zero the timer enable bit is set to 0 the current value counter will pause At least wait for 2 Tcylces the start bit can be set to 1 In timer pause state the interval value register can be modified If the timer is started again and the Software hope the current value register to down count from the new interval value the reload bit and the enable bit should be set to 1 at the same time Note the time between the timer disabled and enabled should be larger than 2 Tcycles Tcycles Timer clock source pre scale 10 3 10 Timer 2 Interval Value Register Offset 0x34 Register Name TMR2_INTV_VALUE_REG Bit Read Default Description Write Hex 31 0 R W X TMR2 INTV VALUE Timer 2 Interval Value Note the value setting should consider the system clock and the timer clock source A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 92 2012 04 09 Allwinner Technology CO Ltd A10 10 3 11 Timer 2 Current Value Register Offset 0x38 Register Name TMR2 CUR VALUE REG Bit Read Default Description Write Hex 31 0 R W 0x0 TMR2 CUR VALUE Timer 2 Current Value
19. 0x00000000 Offset 0x20 Register Name INTC FIQ PEND REGO Bit Read Default Description Write Hex A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 114 2012 04 09 Ou Allwinner Technology CO Ltd A10 INT FIQ SRC PENDO Interrupt FIQ Source 31 0 Pending Clear Bit 0 Corresponding interrupt is not pending 1 Corresponding interrupt is pending 11 49 Interrupt FIQ Pending Clear Register 1 Default 0x00000000 Offset 0x24 Register Name INTC FIQ PEND REG1 Bit Read Default Description Write Hex 31 0 R 0x0 INT FIQ SRC PENDI Interrupt FIQ Source 63 32 Pending Clear Bit 0 Corresponding interrupt is not pending 1 Corresponding interrupt is pending 11 4 10 Interrupt FIQ Pending Clear Register 2 Default 0x00000000 Offset 0x28 Register Name INTC FIQ PEND REG2 Bit Read Default Description Write Hex 31 0 R 0x0 INT FIQ SRC PEND2 Interrupt FIQ Source 95 64 Pending Clear Bit 0 Corresponding interrupt is not pending 1 Corresponding interrupt is pending 11 4 11 Interrupt Select Register 0 Default 0x00000000 Offset 0x30 Register Name INTC IRQ TYPE SELO Bit Read Default Description Write Hex 31 0 R W 0x0 INT IRQ TYPE SELO Interrupt Source 31 0 irq type select 0 IRQ 1 FIQ A10 User Manual V1 20 Copyright O 2011 2012 Allwi
20. 31 24 23 22 18 17 16 R W Ox1 CPU CLK SRC SEL CPU Clock Source Select 00 32KHz OSC Internal 01 OSC24M 10 PLLI 11 200MHz source from the PLL6 If the clock source is changed at most to wait for 8 present running clock cycles 15 14 13 12 11 10 9 8 R W 0x0 APBO CLK RATIO APBO Clock divide ratio APBO clock source is AHB2 clock 00 2 01 2 10 4 11 8 7 6 5 4 R W Ox1 AHB CLK DIV RATIO AHB Clock divide ratio AHB clock source is AXI Clock 00 1 01 2 10 4 11 8 3 2 1 0 R W 0x0 AXI CLK DIV RATIO AXI Clock divide ratio AXI Clock source is CPU clock 00 1 01 2 10 3 11 4 6 4 14 APB1 Clock Divide Ratio Default 0x00000000 Offset 0x58 Register Name APB1 CLK DIV REG Bit Read Default Description Write Hex A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 46 2012 04 09 Ou Allwinner Technology CO Ltd A10 31 30 26 25 24 R W 0x0 APB1 CLK SRC SEL APBI Clock Source Select 00 OSC24M 01 PLL6 set to 1 2GHz 10 32KHz 11 This clock is used for some special module apbclk twi uart ps2 can scr Because these modules need special clock rate even if the apbclk changed 23 18 17 16 R W 0x0 CLK_RAT_N Clock pre divide ratio n The select clock source is pre divided by 2 n The divider is 1 2 4 8 15
21. PI DRV PI n Multi Driving Select n 0 12 21 1 21 00 Level 0 01 Level 1 120 12 R W Ox 10 Level 2 11 Level 3 30 3 79 PI Multi Driving Register 1 Offset 0x138 Register Name PI DRV1 Default Value 0x0000 0000 Bit Read Write Default Description 31 0 30 3 80 PI Pull Register 0 Offset 0x13C Register Name PI PULLO Default Value 0x0000 0000 Bit Read Write Default Description 31 26 PI PULL PI n Pull up down Select n 2 0 12 2i 1 2i 00 Pull up down disable 01 Pull up 120 12 R W 0x0 10 Pull down 11 Reserved 30 3 81 PI Pull Register 1 Offset 0x140 Register Name PI_PULL1 Default Value 0x0000_0000 Bit Read Write Default Description A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 330 2012 04 09 Ou Allwinner Technology CO Ltd A10 31 0 30 3 82 PIO Interrupt Configure Register 0 Register Name PIO INT CFGO Offset 0x200 Default Value 0x0000 0000 Bit Read Write Default Description PIO INT CFG External INTn Mode n 0 7 0x0 Positive Edge Ox1 Negative Edge 0x2 High Level 0x3 Low Level 41 3 41 0x4 Double Edge Positive Negative i 0 7 R W 0 Others Reserved 30 3 83 PIO Interrupt Configure Register 1 Register Name PIO_INT_CFG1 Offset 0x204
22. eee ittetecee nete trien ne rne Rr atu tpa Fon are earn runde 413 33 4 2 TCONI basic timing register eene rr nent rn ee tree teo eere toan 413 33 4 28 TCONI basic timing teglster2 iere rte a ree tree PER iN 413 33 4 29 TCONI basic timing Teglsteta EE 414 33 4 30 TCONI basic timing register4 sess en eere nne enne 414 33 431 TCONI b sic timing registers EE 414 33 4 32 TCONTIO polatity EE 415 33 433 CONI IO control register x i erre t rt eer EE t E ee 415 33 4 34 TCON ECC FIFO register ertet tree rete Rh ENEE Saone 416 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 20 2012 04 09 Ou Allwinner Technology CO Ltd A10 33 4 35 TCON CEU BO 416 33 4 36 TICON CEU coetficent register ean rp tre et irre p ret 416 33 4 37 TCONO Ivds panel analog register sess ener nens 419 33 4 38 TCONO Ivds panel analog register eese 420 33 4 39 TCONI fll data control register 2 rore rea e IH ED Ree rhe dene 420 33 4 40 TCONI fill data begin E 420 33 1 41 TCONI fill data end register tentent th ttr teen tI tenen Ri tnodo 421 33 4 42 TCONI fill data value register essere enne nnne nete nenne 421 3341 43 TCONI fill data begin register order rr pe ated eer edes eine 421 334 44 TCONT All data EE 421 33 4 45 TCONI fill data value register ener ener 421 33 4 46 TCONI fill data begin r
23. 2011 2012 Allwinner Technology All Rights Reserved 280 2012 04 09 Ou Allwinner Technology CO Ltd A10 Keypad Row Input Mask When set to 1 the corresponding input is masked Keypad Column Output Mask 15 8 R W 0 When set to 1 the corresponding output is masked T 1 IF ENB Keypad Interface enable 0 Disable 0 R W 0 1 Enable 27 3 2 Keypad Timing Register Offset 0x04 Register Name KP_TIMING Default Value 0x0200_0100 Bit Read Write Default Description DBC_CYCLE Keypad Debounce Clock Cycle n It is used for filter switching noises When row input is low level the Keypad Interface would delay n 1 clock to check whether it is still keeping on low level If it is true the Keypad Interface would scan the external keypad s state and get these state into internal registers After scan the interrupt is generated if enabled 31 16 R W 0x200 Notes The value below 0x10 can t be used SCAN_CYCLE Keypad Scan Period Clock Cycle n When the Keypad Interface is enabled it would scan the external keypad in period The period time is 8 n 1 kp_clk The kp_clk is input clock for Keypad Interface from CCM 15 0 R W 0x100 Notes The value below 0x10 can t be used 27 3 3 Keypad Interrupt Configure Register Register Name KP_INT_CFG Offset 0x08 Default Value 0x0000_0000 Bit Read Write Default Description 31 2 REDGE_
24. 2011 2012 Allwinner Technology All Rights Reserved 412 2012 04 09 Ou Allwinner Technology CO Ltd A10 1 0 TCONI Src Sel 00 DE CH1 FIFO2 enable 01 DE CH2 FIFO2 enable 1x BLUE data FIFO2 disable RGB 0000FF 33 4 26 TCONI basic timing register Offset 0x094 Register Name TCON1 BASICO REG Bit Read Default Description Write Hex 31 28 27 16 R W 0 TCONI XI source width is X 1 15 12 11 0 R W 0 TCONI YI source height is Y 1 33 4 27 TCONI basic timing register1 Offset 0x098 Register Name TCON1 BASIC1 REG Bit Read Default Description Write Hex 31 28 27 16 R W 0 LS XO width is LS_XO 1 15 12 11 0 R W 0 LS YO width is LS_YO 1 NOTE this version LS YO2 ZTCONI YI 33 4 28 TCONI basic timing register2 Offset 0x09C Register Name TCON1 BASIC2 REG Bit Read Default Description Write Hex 31 28 27 16 R W 0 TCONI1 XO width is TCON1_XO 1 15 12 11 0 R W 0 TCONI1 YO height is TCON1_YO 1 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 413 2012 04 09 Ou Allwinner Technology CO Ltd A10 33 4 29 TCONI basic timing register3 Offset 0x0A 0 Register Name TCON1 BASIC3 REG Bit Read Default Description Write Hex 31 29 28 16 R W 0 HT horizontal total time Thcycle
25. 2012 04 09 136 Ou Allwinner Technology CO Ltd A10 Normal DMA 4 End Transfer Interrupt Enable 0 Disable 1 Enable R W 0x0 NDMA4_HF_IRQ_EN Normal DMA 4 Half Transfer Interrupt Enable 0 Disable 1 Enable R W 0x0 NDMA3_END_IRQ_EN Normal DMA 3 End Transfer Interrupt Enable 0 Disable 1 Enable R W 0x0 NDMA3_HF_IRQ_EN Normal DMA 3 Half Transfer Interrupt Enable 0 Disable 1 Enable R W 0x0 NDMA2_END_IRQ_EN Normal DMA 2 End Transfer Interrupt Enable 0 Disable 1 Enable R W 0x0 NDMA2 HF IRQ EN Normal DMA 2 Half Transfer Interrupt Enable 0 Disable 1 Enable R W 0x0 NDMA1_END_IRQ_EN Normal DMA 1 End Transfer Interrupt Enable 0 Disable 1 Enable R W 0x0 NDMA1_HF_IRQ_ EN Normal DMA 1 Half Transfer Interrupt Enable 0 Disable 1 Enable R W 0x0 NDMAO_END_IRQ_EN Normal DMA 0 End Transfer Interrupt Enable 0 Disable 1 Enable R W 0x0 NDMAO HF IRQ EN Normal DMA 0 Half Transfer Interrupt Enable 0 Disable 1 Enable 12 3 2 DMA IRQ Pending Status Register Default 0x00000000 Offset 0x04 Register Name DMA IRQ PEND STA REG Bit Read Default Description Write Hex 31 R W 0x0 DDMA7 END IRQ PEND Dedicated DMA 7 End Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending 30 R W 0x0 DDMA7 HF IRQ PEND Dedicated DMA 7 Half Transfer Int
26. 7 0 R 0x0 STA DEC PROT OUT Show the status of the decode protection output 0 Decode region corresponding to the bit is secure 1 Decode region corresponding to the bit is non secure There is one bit of the register for each protection output 8 4 3 TZPC DECPORTOSet Register Default 0x00000000 Offset 0x08 Register Name TZPC DECPORTO SET REG Bit Read Default Description Write Hex 31 8 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 79 2012 04 09 Ou Allwinner Technology CO Ltd A10 7 0 R W 0x0 SET_DEC_PORT_OUT Sets the corresponding decode protection output 0 No effect 1 Set decode region to non secure There is one bit of the register for each protection output 8 4 4 TZPC DECPORTOCIear Register Default 0x00000000 Offset 0x0C Register Name TZPC DECPORTO CLR REG Bit Read Default Description Write Hex 31 8 7 0 R W 0x0 CLR DEC PROT OUT Clears the corresponding decode protection output 0 No effect 1 Set decode region to secure There is one bit of the register for each protection output 8 4 5 CPU Control Register Default 0x00000002 Offset 0x20 Register Name CPU CTRL REG Bit Read Default Description Write Hex 31 8 T 1 Reserved 0 R W 0x0 CPISSDISABLE Disable write access to certain
27. A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 234 2012 04 09 Ou Allwinner Technology CO Ltd A10 DA_SDO 1 OUT Digital Audio Serial Data Output DA_SDI 1 IN Digital Audio Serial Data Input DA_MCLK 1 OUT Digital Audio MCLK Output 22 5 2 Digital Audio Interface MCLK and BCLK The Digital Audio Interface can support sampling rates from 128fs to 768fs where fs is the audio sampling frequency typically 32kHz 44 1kHz 48kHz or 96kHz For different sampling frequency the tables list the coefficient value of MCLKDIV and BCLKDIV Sampling Rate kHz 128fs 192fs 256fs 384fs 512fs 768fs 8 24 16 12 8 6 4 16 12 8 6 4 X 2 32 6 4 X 2 X 1 64 X 2 X 1 X X 128 X 1 X X X X 12 16 X 8 X 4 X 24 8 X 4 X 2 X 48 4 X 2 X 1 A 96 2 X l X X X 192 1 A X X X X Table 22 1 MCLKDIV value for 24 576MHz Audio Serial Frequency Sampling Rate kHz 128fs 192fs 256fs 384fs 512fs 768fs 11 025 16 X 8 X 4 X 22 05 8 X 4 X 2 X 44 4 X 2 X 1 A 88 2 2 A 1 X X X 176 4 1 X X X X X Table 22 2 MCLKDIV value for 22 5792 MHz Audio Serial Frequency Word Select Size 128fs 192fs 256fs 384fs 512fs 768fs 16 4 6 8 12 16 X 24 X 4 X 8 X 16 32 2 X 4 6 8 12 Table 22 3 BCLKDIV value for Different Word Select Size A10 User Manual V1 20 Copyright 2011 2012 Allw
28. Allwinner Technology CO Ltd A10 A10 User Manual V1 20 2012 4 9 A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 2012 04 09 Ou Allwinner Technology CO Ltd A10 Revision History Version Date Section Page Changes compared to previous issue V1 00 2011 8 22 Initial version V1 01 2011 11 17 Format changes V1 10 2012 3 29 Audio Codec Revise some description V1 20 2012 4 9 USB Revise some description A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 1 2012 04 09 e Allwinner Technology CO Ltd A10 Technical Items NO Abbreviation Full Name Description ARM CortexTM A8 ARM CortexTM A8 A processor core designed by ARM Holdings implementing the ARM v7 instruction set architecture Mali 400 Mali 400 A 2D 3D graphic processor unit designed by ARM Holdings SDRAM Synchronous Dynamic Random Access Memory Dynamic random access memory DRAM that is synchronized with the system bus PWM Pulse Width Modulator A commonly used technique for controlling power to inertial electrical devices made practical by modern electronic power switches SPI Serial Peripheral Interface A synchronous serial data link standard named by Motorola that operates in full duplex mode Devices communicate in master slave mode where the master device initiates t
29. DAC FIFO Empty DRQ Enable 0 Disable 1 Enable 0x0 DAC_IRQ_EN DAC FIFO Empty IRQ Enable 0 Disable 1 Enable 0x0 FIFO UNDERRUN IRQ EN DAC FIFO Under Run IRQ Enable 0 Disable 1 Enable 0x0 FIFO_OVERRUN_IRQ_EN DAC FIFO Over Run IRQ Enable 0 Disable 1 Enable 0x0 FIFO_FLUSH DAC FIFO Flush Write 1 to flush TX FIFO self clear to 0 24 2 3 DAC FIFO Status Register Offset 0x8 Register Name AC_DAC_FIFOS Bit Read Write Default Description 31 24 TX_EMPTY TX FIFO Empty 23 R Ox1 0 No room for new sample in TX FIFO 1 More than one room for new sample in TX FIFO gt 1 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 257 2012 04 09 Ou Allwinner Technology CO Ltd A10 word TXE_CNT TX FIFO Empty Space Word Counter 22 8 R 0x80 7 4 TXE_INT TX FIFO Empty Pending Interrupt 0 No Pending IRQ 1 FIFO Empty Pending Interrupt Write 1 to clear this interrupt or automatic clear if 3 R W Ox1 interrupt condition fails TXU INT TX FIFO Under run Pending Interrupt 2 R W 0x0 0 No Pending Interrupt 1 FIFO Under run Pending Interrupt Write 1 to clear this interrupt TXO INT TX FIFO Overrun Pending Interrupt 1 R W 0x0 0 No Pending Interrupt 1 FIFO Overrun Pending Interrupt Write 1 to clear this interrupt 0
30. The default value of this field is 0 This field is zero if Port Power is zero R WC CSC Connect Status Change 1 Change in Current Connect Status 0 No change Default 0 Indicates a change has occurred in the port s Current Connect Status The host controller sets this bit for all changes to the port device connect status even if system software has not cleared an existing connect status change For example the insertion status changes twice A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 213 2012 04 09 Ou Allwinner Technology CO Ltd A10 before system software has cleared the changed condition hub hardware will be setting an already set bit Software sets this bit to 0 by writing a to it This field is zero if Port Power is zero 0 R 0 CCS Current Connect Status Device is present on port when the value of this field is a one and no device is present on port when the value of this field is a zero This value reflects the current state of the port and may not correspond directly to the event that caused the Connect Status Change Bit 1 to be set This field is zero if Port Power zero Note This register is only reset by hardware or in response to a host controller reset A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 214 2012 04 09 Ou Allwinner Te
31. eese 116 11 4 14 Interrupt Enable Register O Default 0x00000000 cessere 116 11 4 15 Interrupt Enable Register 1 Default 0x00000000 cessere 116 11 4 16 Interrupt Enable Register 2 Default 0x00000000 esses 117 11 4 17 Interrupt Mask Register O Default 0x00000000 eese 117 11 4 18 Interrupt Mask Register 1 Default 0x00000000 cene 117 11 4 19 Interrupt Mask Register 2 Default 0x00000000 cese 117 11 4 20 Interrupt Response Register O Default 0x00000000 esee 118 11 4 21 Interrupt Response Register 1 Default 0x00000000 eene 118 11 4 22 Interrupt Response Register 2 Default 0x00000000 cessere 118 11 4 23 Interrupt Fast Forcing Register O Default 0x00000000 eese 118 11 4 24 Interrupt Fast Forcing Register 1 Default 0x00000000 esee 119 11 4 25 Interrupt Fast Forcing Register 2 Default 0x00000000 eese 119 11 4 26 Interrupt Source Priority 0 Register Default 0x00000000 eene 119 11 4 27 Interrupt Source Priority I Register Default 0x00000000 eene 122 11 4 28 Interrupt Source Priority 2 Register Default 0x00000000 esee 124 11 4 29 Interrupt Source Priority 3 Register Default 0x00000000 eene 127 11 4 30 Interrupt Source Priority 4 Register
32. 2011 2012 Allwinner Technology All Rights Reserved 2012 04 09 FF TCONI output port D 23 0 output enable with independent bit Allwinner Technology CO Ltd A10 Offset 0x114 Register Name TCON_CEU_MUL_RG_REG Bit Read Default Description Write Hex 31 13 12 0 R W 0 Coef_Value signed 13bit value range of 16 16 Offset 0x118 Register Name TCON_CEU_MUL_RB_REG Bit Read W Default Description rite Hex 31 13 12 0 R W 0 Coef_Value signed 13bit value range of 16 16 Offset Ox11c Register Name TCON CEU ADD RC REG Bit Read Default Description Write Hex 31 19 18 0 R W 0 Coef_Value signed 19bit value range of 16384 16384 Offset 0x120 Register Name TCON_CEU_MUL_GR_REG Bit Read Default Description Write Hex 31 13 12 0 R W 0 Coef_Value signed 13bit value range of 16 16 Offset 0x124 Register Name TCON_CEU_MUL_GG_REG Bit Read Default Description Write Hex 31 13 12 0 R W 0 Coef_Value signed 13bit value range of 16 16 Offset 0x128 Register Name TCON_CEU_MUL_GB_REG Bit Read Default Description Write Hex 31 13 12 0 R W 0 Coef_Value signed 13bit value range of 16 16 Offset 0x12C Register Name TCON_CEU_ADD_GC_REG A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights
33. A disable on this bit overrides any other block or channel enables and flushes all FIFOs 0 Disable 1 Enable WARM_RST Warm reset 0 Normal 1 Wake up codec from power down Note Self clear to 0 23 7 2 AC97 Format Register Offset 0x04 Register Name AC_FAT Default Value 0x0000_0000 Bit Read Write Default Description A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 246 2012 04 09 Allwinner Technology CO Ltd A10 31 9 8 7 R W TX_AUDIO_MODE TX audio mode 00 2 channel PCM l r main 01 6 channel PCM Ur main l r surround center AFE 10 Reserved 11 Reserved R W DRA_SLOT_SEL DRA additional slots select available in 2 channel mode 0 select slot 10 slot 11 1 select slot 7 slot 8 R W DRA_MODE DRA mode 0 Non DRA 1 DRA R W VRA MODE VRA Mode 0 Non VRA 1 VRA 3 2 R W TX_RES TX Audio data resolution 00 16 bit 01 18 bit 10 20 bit 11 Reserved 1 0 R W RX_RES RX Audio data resolution 00 16 bit 01 18 bit 10 20 bit 11 Reserved 23 7 3 AC97 Codec Command Register Offset 0x08 Register Name AC_CMD Default Value 0x0000_0000 Bit Read Write Default Description 31 24 23 R W 0 OP Read enable 0 Command write 1 Status read A10 User Manual V1 20
34. BLANK SAV 1 1 0 OxFF 0x00 0x00 OxEO OxE1 OxE2 OxE3 EVEN ACTIVE 1 0 OxFF 0x00 0x00 OxDO OxD1 OxD2 OxD3 EVEN ACTIVE 1 0 0x00 0x00 OxCO OxC1 OxC2 OxC3 BLANK 1 BLANK 1 ACTIVE 0 ACTIVE 0 Figure39 8 31 5 CSIO Register List Module Name Base Address CSIO 0x01C09000 Register Name Offset Register name CSIO EN REG 0X000 CSI enable register CSIO CFG REG 0X004 CSI configuration register CSIO CAP REG 0X008 CSI capture control register CSIO SCALE REG 0X00C CSI scale register CSIO CO FO BUFA REG 0X010 CSI Channel 0 FIFO 0 output buffer A address register CSIO CO FO BUER REG 0X014 CSI Channel 0 FIFO 0 output buffer B address register A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 2012 04 09 338 Allwinner Technology CO Ltd A10 CSIO C0 F1 BUFA REG 0X018 CSI Channel 0 FIFO 1 output buffer A address register CSIO C0 F1 BUFB REG 0X01C CSI Channel 0 FIFO 1 output buffer B address register CSIO C0 F2 BUFA REG 0X020 CSI Channel 0 FIFO 2 output buffer A address register CSIO C0 F2 BUER REG 0X024 CSI Channel 0 FIFO 2 output buffer B address register CSIO C0 BUF CTL REG 0X028 CSI Channel 0 output buffer control register CSIO C0 BUF STA REG 0X02C CSI Channel 0 status register CSIO CH INT EN REG 0X030 CSI Channel O interrupt enable register CSIO C0 INT STA REG 0X034 CS
35. Note the active cycles should be no larger than the period cycles 9 3 3 PWM Channel 1 Period Register Offset 0x208 Register Name PWM CH1 PERIOD Bit Read Default Description Write Hex 31 24 23 16 R W x PWM_CH1_ENTIRE_CYS Number of the entire cycles in the PWM clock 0 1 cycle 1 2 cycles N N 1 If the register need to be modified dynamically the PCLK should be faster than the PWM CLK PWM CLK 24MHz prescale 15 8 7 0 R W X PWM CHI ENTIRE CYS Number of the active cycles in the PWM clock 0 2 O cycle 1 1 cycles N N cycles A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 84 2012 04 09 Ou Allwinner Technology CO Ltd A10 10 Timer Controller 10 1 Overview The chip implements 6 timers Timer 0 and 1 can take their inputs from internal RC oscillator external 32768Hz crystal or OSC24M They provide the operating system s scheduler interrupt They are designed to offer maximum accuracy and efficient management even for systems with long or short response time They provide 24 bit programmable overflow counter and work in auto reload mode or no reload mode Timer 2 is used for OS to generate a periodic interrupt The Watchdog timer is a timing device that resumes the controller operation after malfunctioning due to noise and system errors The watchdog timer can be used as a normal 16 bit interval timer to
36. Output data mode A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 479 2012 04 09 Ou Allwinner Technology CO Ltd A10 35 5 28 Output size register Offset OxE8 Register Name MP_OUTSIZE_REG Bit Read W Default Description rite Hex 28 16 R W OUT HEIGHT Height The value add 1 equal the actual output image height OUT WIDTH Width The value add 1 equal the actual output image width 35 5 20 Output address high 4bits register Offset OxXEC Register Name MP OUTH4ADD REG Read W Default Description rite Hex Ear E 19 16 R W OUTCH2 H4ADD Output channel 2 High 4bits address in bits EM OUTCH1_H4ADD Output channel 1 High 4bits address in bits Output channel 0 High 4bits address in bits 35 5 30 Output address low 32bits register Offset Register Name MP_OUTL32ADD_REG Out channel 0 0xF0 Out channel 1 0xF4 Out channel 2 0xF8 Bit Read W Default Description rite Hex A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 480 2012 04 09 Allwinner Technology CO Ltd A10 OUT L32ADD Output channel Low 32bits address in bits 35 5 31 Output line width register Offset Register Name MP OUTLINEWIDTH REG Out channel 0 0x100 Out channel 1 0x104 Out channel 2 0x108 Bit Read W Default Description
37. data data FIFO2 Blue pixel data Cr V pixel data 31 4 Timing 31 4 1 CSI timing vsync n frames n 1 frame hsyne active data 4 firstline data gt A i lastline data A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 335 2012 04 09 Ou N Allwinner Technology CO Ltd A10 Vref positive Href positive Figure31 2 vsync W H nframe W n 1 frame j n lines oe m lines hsyne 5 H H vertical stat line n vertical active line length m vertical size setting Figure31 3 A A am pt active data 4 C 0C OCOCOODCOCOCOCOCO M active in rising maen N J NN deeg AU horizontal start clock n horizontal active clocks length m horizontal size setting and pixel clock timing Href positive Figure3 1 4 31 4 2 16bit YUV422 Timing 16 bit YCbCr 4 2 2 with embedded syncs Figure31 5 31 4 3 CCIR656 2 channel Timing A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 336 2012 04 09 Ou N Allwinner Technology CO Ltd A10 CLKPOn ena CLKNOn 27MH2 sn CH2 veo Cr50 ver Joe ven eria Y53 osa v54 Cr54 ves cose vss crs6 I P vors EE Figure31 6 31 4 4 CCIR656 4 channel Timing CLKPOn 4 jj 4 f 108MHz i
38. luminance statistical value When frame done interrupt flag come value is ready and will last until next frame done For raw data value G gt gt 1 R G gt gt 8 For yuv422 value Y gt gt 8 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 362 2012 04 09 Ou Allwinner Technology CO Ltd A10 NEE E VCAP_STA Video capture in progress Indicates the CSI is capturing video image data multiple frames The bit is set at the start of the first frame after enabling video capture When software disables video capture it clears itself after the last pixel of the current frame is captured SCAP_STA Still capture in progress Indicates the CSI is capturing still image data single frame The bit is set at the start of the first frame after enabling still frame capture It clears itself after the last pixel of the first frame is captured For CCIR656 interface if the output format is frame planar YCbCr 420 mode the frame end means the field2 end the other frame end means filed end 31 6 52 CSI Channel 3 interrupt enable register Offset Address 0X0330 Register Name CSIO C3 INT EN REG Read Default Description Write Hex REM INT EN vsync flag The bit is set when vsync come And at this time load the buffer address for the coming frame So after this irq come change the buffer address could only effect next frame HB OF INT EN Hblank FIFO overflow The bit is
39. 0x000000C9 essent 107 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 7 Allwinner Technology CO Ltd A10 Euer 109 DIT e EE 109 112 o en Dee E 109 11 3 Interrupt Register EE 111 ILA Interrupt Programmable Register inier eme HORE EDO EISE HEISE R RE 112 11 4 1 Interrupt Vector Register Default 0x00000000 eese 112 11 4 2 Interrupt Base Address Register Default 0x00000000 esee 113 11 4 3 Interrupt Protection Register Default 0x00000000 eese 113 11 4 4 NMI Interrupt Control Register Default OsOOUOOO00 eene 113 11 4 5 Interrupt IRQ Pending Register O Default 0x00000000 cese 114 11 4 6 Interrupt IRQ Pending Register 1 Default 0x00000000 eene 114 11 4 7 Interrupt IRQ Pending Register 2 Default 0x00000000 eee 114 11 4 8 Interrupt FIQ Pending Clear Register 0 Default 0x00000000 eee 114 11 4 9 Interrupt FIQ Pending Clear Register 1 Default 0x00000000 esee 115 11 4 10 Interrupt FIQ Pending Clear Register 2 Default 0x00000000 eee 115 11 4 11 Interrupt Select Register O Default 0x00000000 eese 115 11 4 12 Interrupt Select Register 1 Default 0x00000000 eese 116 11 4 13 Interrupt Select Register 2 Default 0x00000000
40. 0x0000_0000 Bit Read Write Default Description 31 4 RPA Receiver Packet Abort bit Determines behavior of the RX FIFO upon detection of an illegal symbol When an illegal symbol is detected the DDE or CRCE bit in the receiver status register is set If the RPA bit is set the RX FIFO pointers are cleared and the receiver starts to search for the PA or STA fields for FIR and MIR mode respectively If RPA is cleared the receiver continues to write to the RX FIFO 0 Does not clear the RX FIFO upon detection of an illegal symbol 3 R W 0 1 Clears the RX FIFO upon detection of illegal symbol RPPI Receiver Pulse Polarity Invert 0 Not invert receiver signal 2 R W 1 1 Invert receiver signal 1 0 19 4 6 IR Receiver Address Register Register Name IR RXADR Offset 0x14 Default Value 0x0000_0000 Bit Read Write Default Description 31 9 RAM Receiver Address Match 0 Does not need match address RA When an new packet is received the address control and data fields are filled into RX FIFO 1 Should match packet address to RA bits when an new packet is received If address matched the control and data fields are filled into RX FIFO excluding the address field The value of this bit can be changed when the RXEN 8 R W 0 bit is cleared A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 205 2012 04 09 Ou Allwin
41. 0x1 level 2 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 132 2012 04 09 Ou Allwinner Technology CO Ltd Offset 0x90 Register Name INTC PRIO REG5 A10 Level3 Ox1 level 3 highest priority 3 2 R W 0x0 IRQ65_PRIO IRQ 65 Priority Set priority level for IRQ bit 65 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority 1 0 R W 0x0 IRQ64_PRIO IRQ 64 Priority Set priority level for IRQ bit 64 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 2012 04 09 133 Ou Allwinner Technology CO Ltd A10 12 DMA Controller 12 1 Overview Many peripherals on the A10 use direct memory access DMA transfers There are two kinds of DMA namely Normal DMA and Dedicated DMA For Normal DMA ONLY one channel can be activated and the sequence is determined by the priority level For Dedicated DMA at most 8 channels can be activated at the same time as long as there is conflict of their source or destination Both Normal DMA and Dedicated DMA can support 8 bit 16 bit 32 bit data width The data width of Source and Destination can be different but the address should be consistently a
42. 21 R W 0x0 DDMA2_END_IRQ_PEND Dedicated DMA 2 End Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending 20 R W 0x0 DDMA2_HF_IRQ_PEND Dedicated DMA 2 Half Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending 19 R W 0x0 DDMA1_END_IRQ_PEND Dedicated DMA 1 End Transfer Interrupt Pending Set 1 to the bit will A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 138 2012 04 09 Ou Allwinner Technology CO Ltd A10 clear it 0 No effect 1 Pending 18 R W 0x0 DDMA1_HF_IRQ_PEND Dedicated DMA 1 Half Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending 17 R W 0x0 DDMAO END IRQ PEND Dedicated DMA 0 End Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending 16 R W 0x0 DDMAO HF IRQ PEND Dedicated DMA 0 Half Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending 15 R W 0x0 NDMA7 END IRQ PEND Normal DMA 7 End Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending 14 R W 0x0 NDMA7 HF IRQ PEND Normal DMA 7 Half Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending 13 R W 0x0 NDMA6_END_IRQ_PEND Normal DMA 6 End Transfer Interrupt Pe
43. 21 USB Host Controller ssesesvessesvnvrsnesnesnennenesnesnennenesnesnennennsnesnennennsnesnesnennenesnesnennennsnesnennensnvesnesnennenesenen 211 e EE 21 2 USB Host Timing Diagram tete ete teh sett re NEEN EEN 22 Digital Audio Interface e ps T A N A A I E A A A A 22 2 Digital Audio Interface Timing Diagram eeneronnronnnennnvnnnennrennsennsennsennsnnnsnnsnrnsvnessresnresnnnssnnsnrnsnnee 22 3 Digital Audio Interface Register List 22 4 Digital Audio Interface Register Description eren nennen 22 4 14 Digital Audio Control Register 2 eret terree re enne eor ih eran 22 4 2 Digital Audio Format Register U N 22 4 3 Digital Audio Format Register 1 22 4 4 Digital Audio TX FIFO Registet nicer ter reser tante terrier ve ries diat 2245 Digital Audio RX EE 22 4 6 Digital Audio FIFO Control Register sese enne 22 4 7 Digital Audio FIFO Status Register AAA 22 4 8 Digital Audio DMA amp Interrupt Control Register A A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 11 2012 04 09 Ou Allwinner Technology CO Ltd A10 2012 04 09 22 4 9 Digital Audio Interrupt Status Register 228 22 4 10 Digital Audio Clock Divide Register AAA 229 22 4 11 Digital Audio TX Counter register nennen ener nnne 230 22 4 12 Digital Audio RX Counter regteter essent eere 230 22 4 13 Digital Audio TX Channel Select register eese 230
44. 22 4 14 Digital Audio TX Channel Mapping Register esee 231 22 4 15 Digital Audio RX Channel Select register sees 233 22 4 16 Digital Audio RX Channel Mapping Register AA 233 22 5 Digital Audio Interface Special Requirement essent 234 22 5 1 Digital Audio Interface Pin List rrrnrnrnnrnrrnrrvnnrnnrnrnnrnnvnrnesnrrnvnevennarnrsvvnnvesnesnenvvnsvesvesnrnsvesvesne 234 22 5 2 Digital Audio Interface MCLK and BCL 235 22 5 3 Digital Audio Interface Clock Source andFrequency esse 236 jn 237 23de e E 237 23 2 AACOT Block E EE 238 23 3 4A C97 Interface Clock tree uite Fe eder E RIT UR EAE Zeie 239 23 4 AC Link frame Pormat c rt ENEE NENNEN SEENEN EENEG 239 23 5 AC9T Interface Timing Diagrami intere hr Rr er Ee EI berbar 240 23 1 Cold Reset timing diagram nre erre net vredens 240 23 5 2 Warm Reset timing diagrami esses en eerte aaa aaa 241 23 5 3 Power Down timing diagram iruinarri nnetnet rennen ener ene nne nenne 241 2354 ACK Clocks etes a ERE EE EA E E EAE EE eie 242 23 5 5 Data transmission timing dageram essent nenne ioiii 243 23 6 AC97 Interface Register List eerte netten en neret e e EET ne eer eene eie 245 23 7 AC9T Interface Register Description nhe tir ep e bee rta 245 23 711 ACI Control Register Eege ee tet iter te dH ro a eese d E nodes aE a Eee EAE dite 245 23 1 2 AC97 Format Register t REED EE Ee 246 23 13 A
45. 7 R W 0 is set to 1 MCLK should be output BCLKDIV BCLK Divide Ratio from MCLK 000 Divide by 2 BCLK MCLK 2 001 Divide by 4 010 Divide by 6 011 Divide by 8 100 Divide by 12 101 Divide by 16 110 Divide by 32 6 4 R W 0 111 Divide by 64 MCLKDIV MCLK Divide Ratio from Audio PLL Output 0000 Divide by 1 0001 Divide by 2 0010 Divide by 4 0011 Divide by 6 0100 Divide by 8 3 0 R W 0 0101 Divide by 12 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 229 2012 04 09 Ou Allwinner Technology CO Ltd A10 0110 Divide by 16 0111 Divide by 24 1000 Divide by 32 1001 Divide by 48 1010 Divide by 64 Others Reserved 22 4 11 Digital Audio TX Counter register Offset 0x28 Register Name DA_TXCNT Default Value 0x0000_0000 Bit Read Write Default Description 31 0 R W TX_CNT TX Sample Counter The audio sample number of sending into TXFIFO When one sample is put into TXFIFO by DMA or by host IO the TX sample counter register increases by one The TX sample counter register can be set to any initial valve at any time After been updated by the initial value the counter register should count on base of this initial value 22 4 12 Digital Audio RX Counter register Offset 0x2C Register Name DA RXCNT Default Value 0x0000 0000 Bit Read Write Default Descrip
46. A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 130 2012 04 09 Ou Allwinner Technology CO Ltd Offset 0x90 Register Name INTC PRIO REG5 A10 Level3 Ox1 level 3 highest priority 27 26 R W 0x0 IRQ77_PRIO IRQ 77 Priority Set priority level for IRQ bit 77 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 Ox1 level 2 Level3 Ox1 level 3 highest priority 25 24 R W 0x0 IRQ76_PRIO IRQ 76 Priority Set priority level for IRQ bit 76 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority 23 22 R W 0x0 IRQ75_PRIO IRQ 75 Priority Set priority level for IRQ bit 75 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 Ox1 level 2 Level3 Ox1 level 3 highest priority 21 20 R W 0x0 IRQ74_PRIO IRQ 74 Priority Set priority level for IRQ bit 74 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority 19 18 R W 0x0 IRQ73_PRIO IRQ 73 Priority Set priority level for IRQ bit 73 Level0 0x0 level 0 lowest priority Levell 0x1 level 1 Level2 Ox1 level 2 Level3 0x1 level 3 highest priority 17 16 R W 0x0 IRQ72_PRIO IRQ 72 Priority Set priority level for IRQ bit 72 Level0 0x0 level 0 lowest priority Levell Ox1
47. All Rights Reserved 277 2012 04 09 Ou Allwinner Technology CO Ltd A10 Write Hex 31 19 18 R W 0x0 17 R W 0x0 FIFO_OVERRUN_PENDING TP FIFO Over Run IRQ pending 0 No Pending IRQ 1 FIFO Overrun Pending IRQ Write 1 to clear this interrupt or automatic clear if interrupt condition fails 16 R W 0x0 FIFO_DATA_PENDING TP FIFO Data Available pending Bit 0 NO Pending IRQ 1 FIFO Available Pending IRQ Write 1 to clear this interrupt or automatic clear if interrupt condition fails 15 13 12 8 0x0 RXA_CNT TP FIFO available Sample Word Counter 7 3 0x0 TP_IDLE_FLG Touch Panel Idle Flag 0 idle 1 not idle R W 0x0 TP_UP_PENDING Touch Panel Last Touch Stylus Up IRQ Pending bit 0 No IRQ 1 IRQ Notes Writing 1 to the bit will clear it and its corresponding interrupt if the interrupt is enable R W 0x0 TP_DOWN_PENDING Touch Panel First Touch Stylus Down IRQ Pending bit 0 No IRQ 1 IRQ Notes Writing 1 to the bit will clear it and its corresponding interrupt if the interrupt is enable 26 4 3 Common Data Register Offset Ox1c Register Name TP_CDAT Bit Read Default Description Write Hex 31 12 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 278 2012 04 09 Ou v Al
48. All Rights Reserved 314 2012 04 09 Ou Allwinner Technology CO Ltd A10 30 3 49 PF Configure Register 3 Offset 0xCO Register Name PF CFG3 Default Value 0x0000 0000 Bit Read Write Default Description 31 0 30 3 50 PF Data Register Register Name PF DAT Offset 0xC4 Default Value 0x0000 0000 Bit Read Write Default Description 31 6 PF DAT If the port is configured as input the corresponding bit is the pin state If the port is configured as output the pin state is the same as the corresponding bit The read bit value is the value setup by software If the port is configured as functional pin the undefined value will be 5 0 R W 0 read 30 3 51 PF Multi Driving Register 0 Register Name PF DRVO Offset 0xC8 Default Value 0x0000 0555 Bit Read Write Default Description 31 12 PF DRV PF n Multi Driving Select n 0 5 21 1 21 00 Level 0 01 Level 1 120 5 R W Ox1 10 Level 2 11 Level 3 30 3 52 PF Multi Driving Register 1 Offset OxCC Register Name PF_DRV1 Default Value 0x0000 0000 Bit Read Write Default Description 31 24 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 2012 04 09 315 Ou Allwinner Technology CO Ltd
49. Allwinner Technology CO Ltd A10 ILLATUM l 19 1 EE 10 2 IR mimine E PES NEBU Mulder M M 19 4 NR Ee Oe 19 4 1 gt IR Control E Eet iere rege tte rt TEE Ee 19 4 2 IR Transmitter Configure Register A 19 4 3 IR Transmitter Address Register snrnnnnrnnvnvnnnnnnnrnvrnrnnrnervrrevnrnenvrsnrevvnnvennrsvresvesvesnrssvevvennesn 19 4 4 IR Transmitter Counter Register nn ber menm rr D eo rr eder PER eda rette 19 45 IR Receiver Configure Register i eite ren erri Ren bre eei 19 4 6 IR Receiver Address Register essere ener neret 19 4 7 IR Receiver Counter Register esee ii eiii iiai seia 19 4 8 IR Transmitter FIFO Register nae ep an e HER E OR ERE tr RS 19 49 IR Receiver FIFO Reglster edeerrorert rer rt n rper ee rp ea ge oed ere 19 4 10 IR Transmitter Interrupt Control Register 19 4 11 IR Transmitter Status Register srrvrnnnnnnrrnrnvnnnnrnnrrvrnrnnnnervrrvvernenvesnrevvnrvesnrsverevesvesvrsvvevvennesn 19 4 12 IR Receiver Interrupt Control Register AAA 19 4 13 IR R ceiver Status Reglster E 194 14 CIR Configure Register irte enter tette a Rege kh a i e RR e RARE eR o AEn RR 20 USB OTG Controller snesesvesnervnnrenesnenennsnnsnesnennnvesvesnennnnnsnesnennennsvnsnesnennenesnesnennnnnsnesnennenssvnsnesneenennsneen 20 1 e EE 20 2 USB OTG Timing RE oce rr e ER C penssvaeutasgess tontasdutesansuvedeasavepessnates
50. Bit Read Default Description Write Hex 31 9 8 R W 0x0 WDOG IRQ PEND Watchdog IRQ Pending Set 1 to the bit will clear it 0 No effect 1 Pending Watchdog counter value is reached T6 5 R W 0x0 TMR5_IRQ_PEND A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 87 2012 04 09 Ou Allwinner Technology CO Ltd A10 Timer 5 IRQ Pending Set 1 to the bit will clear it 0 No effect 1 Pending timer 3 counter value is reached R W 0x0 TMR4_IRQ_PEND Timer 4 IRQ Pending Set 1 to the bit will clear it 0 No effect 1 Pending timer 3 counter value is reached R W 0x0 TMR3_IRQ_PEND Timer 3 IRQ Pending Set 1 to the bit will clear it 0 No effect 1 Pending timer 3 counter value is reached R W 0x0 TMR2_IRQ_PEND Timer 2 IRQ Pending Set 1 to the bit will clear it 0 No effect 1 Pending timer 2 counter value is reached R W 0x0 TMR1_IRQ_PEND Timer 1 IRQ Pending Set 1 to the bit will clear it 0 No effect 1 Pending timer 1 interval value is reached R W 0x0 TMRO IRQ PEND Timer 0 IRQ Pending Set 1 to the bit will clear it 0 No effect 1 Pending timer 0 interval value is reached 10 3 3 Timer 0 Control Register Default 0x00000004 Offset 0x10 Register Name TMRO_CTRL_REG Bit Read Write Default Hex Description 31 8
51. Copyright 2011 2012 Allwinner Technology All Rights Reserved 247 2012 04 09 Ou Allwinner Technology CO Ltd A10 22 16 R W 0x00 CC ADDR Codec command address 15 0 R W 0x0000 CC Codec command data 23 7 4 AC97 Codec Status Register Offset 0x0C Register Name AC CS Default Value 0x0000 0000 Bit Read Write Default Description 31 23 22 16 R 0x00 CS_ADDR Codec status address 15 0 R 0x0000 CS Codec status data 23 7 5 AC97 TX FIFO Register Offset 0x10 Register Name AC_TXFIFO Default Value 0x0000_0000 Bit Read Write Default Description 31 0 W 0 TX DATA Transmitting left right channel sample data should be written this register one by one The left channel sample data is first and then the right channel sample 23 7 6 AC97 RX FIFO Register Offset 0x14 Register Name AC_RXFIFO Default Value 0x0000_0000 Bit Read Write Default Description 31 0 R 0 RX DATA Host can get one sample by reading this register If in the PCM IN mode the left channel sample data is first and then the right channel sample 23 7 7 AC97 FIFO Control Register Offset 0x18 Register Name AC FCTL Default Value 0x0000 3078 A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 248 2012 04 09 Ou Allwinner Technology CO Ltd A10 Bit Read
52. G 0 15 R W Ox1 10 Level 2 11 Level 3 30 3 25 PC Multi Driving Register 1 Register Name PC DRV1 Offset 0x60 Default Value 0x0001 5555 Bit Read Write Default Description 31 18 PC DRV PC n Multi Driving Select n 16 24 21 1 21 00 Level 0 01 Level 1 120 8 R W Ox1 10 Level 2 11 Level 3 30 3 26 PC Pull Register 0 Register Name PC PULLO Offset 0x64 Default Value 0x0000 5140 Bit Read Write Default Description PC PULL PC n Pull up down Select n 0 15 21 1 2i 00 Pull up down disable 01 Pull up 120 15 R W 0x0000 5140 10 Pull down 11 Reserved 30 3 27 PC Pull Register 1 Register Name PC PULL1 Offset 0x68 Default Value 0x0000 4016 Bit Read Write Default Description 31 18 PC PULL 21 1 21 PC n Pull up down Select n 2 16 24 120 8 R W 0x0000_4016 00 Pull up down disable 01 Pull up A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 2012 04 09 A10 303 Allwinner Technology CO Ltd A10 10 Pull down 11 Reserved 30 3 28 PD Configure Register 0 Register Name PD CFGO Offset 0x6C Default Value 0x0000 0000 Bit Read Write Default Description 31 PD7 SELECT 000 Input 001 Output 010 LCDO D7 011 LVDSO_VNC 100 Reserved 101 Reserved 30 28 R W 0 110 Reserved 11
53. Inverted In DSP PCM mode 0 MSB is available on 2nd BCLK rising edge after LRC rising edge 1 MSB is available on Ist BCLK rising edge after LRC rising edge 6 R W BCP BCLK Parity 0 Normal 1 Inverted A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 222 2012 04 09 Ou Allwinner Technology CO Ltd A10 5 4 SR Sample Resolution 00 16 bits 01 20 bits 10 24 bits 11 Reserved 3 2 0x3 WSS Word Select Size 00 16 BCLK 01 20 BCLK 10 24 BCLK 11 32 BCLK 1 0 R W FMT Serial Data Format 00 Standard DS Format 01 Left Justified Format 10 Right Justified Format 11 Reserved 22 4 3 Digital Audio Format Register 1 Register Name DA_FAT1 Offset 0x08 Default Value 0x0000_4020 Bit Read Write Default Description 31 15 PCM_SYNC_PERIOD PCM SYNC Period Clock Number 000 16 BCLK period 001 32 BCLK period 010 64 BCLK period 011 128 BCLK period 100 256 BCLK period 14 12 R W 0x4 Others Reserved PCM_SYNC_OUT PCM Sync Out 0 Enable PCM_SYNC output in Master mode 1 Suppress PCM_SYNC whilst keeping PCM_CLK running Some Codec utilize this to enter a low power 11 R W 0 state PCM Out Mute 10 R W 0 Write 1 force PCM OUT to 0 9 R W 0 MLS A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 223 2012 04 09 Ou Al
54. LVDS up to 1920 1080 resolution A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 25 2012 04 09 Ou v Allwinner Technology CO Ltd A10 B CVBS YPbPr up to 1920 1080 resolution 1 1 6 Image Input Ability M Dual camera sensor interface CSIO supports ISP function 1 1 7 Memory W 16 32 bits SDRAM controller M support DDR2 SDRAM and DDR3 SDRAM up to 800Mbps B Memory Capacity up to 16 G bits WB 8 bits NAND Flash Controller with 8 chip select and 2 r b signals m Support SLC MLC TLC DDR NAND B ECC up to 64 bits 1 1 8 Peripheral m USB 2 0 OTG controller for general application 2 USB EHCI controller for host application 4 high speed Memory controller supports SD version 3 0 and MMC version 4 2 B 8 UARTs with 64 Bytes TX FIFO and 64 Bytes RX FIFO B One UART with full modem function B Two UARTs with RTS CTS hardware flow control B Five UARTS with two wires m 4SPI controller M 1 dedicated SPI controller for serial NOR Flash boot application B 3 SPI for general applications 4 SD3 0 Card controller 2 PS2 controller for connecting external PS2 mouse and PS2 keypad 3 Two Wire Interface up to 400Kbps Key Matrix 8x8 with internal debounce filter IR controller supports MIR FIR and IR remoter 2 CH 6 bits LRADC for line control Internal 4 wire touch panel controller with pressure sensor and 2 point touch I2S PCM controller for 8 channel output and 2 channel input AC97 controller compatib
55. PD DRVO Offset 0x80 Default Value 0x5555 5555 Bit Read Write Default Description PD DRV PD n Multi Driving Select n 0 15 21 1 21 00 Level 0 01 Level 1 G 0 15 R W Ox1 10 Level 2 11 Level 3 30 3 34 PD Multi Driving Register 1 Register Name PD DRV1 Offset 0x84 Default Value 0x0055 5555 Bit Read Write Default Description 31 24 PD DRV PD n Multi Driving Select n 16 27 21 1 21 00 Level 0 01 Level 1 i20 11 R W Ox1 10 Level 2 11 Level 3 30 3 35 PD Pull Register 0 Register Name PD PULLO Offset 0x88 Default Value 0x0000 0000 Bit Read Write Default Description PD PULL PD n Pull up down Select n 0 15 21 1 2i 00 Pull up down disable O1 Pull up 1 0 15 R W 0x0 10 Pull down 11 Reserved 30 3 36 PD Pull Register 1 Register Name PD_PULL1 Offset 0x8C Default Value 0x0000_0000 Bit Read Write Default Description 31 24 PD_PULL 21 1 21 PD n Pull up down Select n 16 27 1 0 11 R W 0x0 00 Pull up down disable 01 Pull up enable A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 2012 04 09 Ou Allwinner Technology CO Ltd A10 10 Pull down 11 Reserved 30 3 37 PE Configure Register 0 Register Name PE_CFG0 Offset 0x90 Default Value 0x0000 0000 Bit Read Write Default Descripti
56. Pl P3 P3 P2 P2 P2 P2 P2 P2 3 2 1 0 9 8 7 6 1 0 9 8 7 6 5 4 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PS xx11 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PO PO PO PO PO PO PO PO PO PO PI Pl Pl Pl Pl Pl 0 1 2 3 4 9 6 7 8 9 0 1 2 3 4 5 Pl Pl Pl Pl P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P3 P3 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 2 bpp mode PS xx00 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P15 P14 P13 P12 P11 P10 P09 P08 P07 P06 P05 P04 P03 P02 PO POO 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PS xx01 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P12 P13 P14 P15 P08 P09 P10 P11 P04 POS P06 P07 P00 P01 P02 P03 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 2012 04 09 488 Ou Allwinner Technology CO Ltd A10 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PS xx10 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P03 P02 POI POO P07 P06 P05 P04 P11 P10 P09 P08 P15 P14 P13 P12 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PS xx11 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 POO PO P02 P03 P04 POS P06 P07 P08 P09 P10 P11 P12 P13 P14 P15 15 14 13 12 11 10 09 08 07 06 0
57. Support 2 chip select signals 15 address lines and three bank address lines Data IO size can up to 32 bit for DDR2 and DDR3 x8 x16 Automatically generates initialization and refresh sequences Runtime configurable parameters setting for application flexibility Clock frequency can be chosen for different application Priority of transferring through multiple ports is programmable Random read or write operation is supported A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 150 2012 04 09 Ou Allwinner Technology CO Ltd A10 14 NAND Flash Controller 14 1 Overview The NFC is the NAND Flash Controller which supports all NAND MLC flash memory available in the market New type flash can be supported by software re configuration The NFC can support 8 NAND flash with 1 8 3 3 V voltage supply There are 8 separate chip select lines CE for connecting up to 8 flash chips with2 R B signals The On the fly error correction code ECC is built in NFC for enhancing reliability BCH is implemented and it can detect and correct up to 64 bits error per 512 or 1024 bytes data The on chip ECC and parity checking circuitry of NFC frees CPU for other tasks The ECC function can be disabled by software The data can be transferred by DMA or by CPU memory mapped IO method The NFC provides automatic timing control for reading or writing external Flash The NFC maintains the proper relativity for CLE CE a
58. Timer Interval Value Note the value setting should consider the system clock and the timer clock source 10 3 8 Timer 1 Current Value Register Offset 0x28 Register Name TMR1 CUR VALUE REG Bit Read Default Description Write Hex 31 0 R W 0x0 TMR1_CUR_VALUE Timer 1 Current Value Note Timer 1 current value is a 32 bit down counter from interval value to 0 This register can be read correctly if the PCLK is faster than 2 TimerFreq TimerFreq TimerClkSource pre scale 10 3 9 Timer 2 Control Register Default 0x00000004 Offset 0x30 Register Name TMR2_CTRL_REG Bit Read Default Description Write Hex 31 8 7 R W 0x0 TMR2 MODE Timer2 mode 0 Continous mode When interval value reaches the timer will not disable automatically 1 Single mode When interval value reaches the timer will disable automatically 6 4 R W 0x0 TMR2_CLK_PRES A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 91 2012 04 09 Ou Allwinner Technology CO Ltd A10 Select the pre scale of timer 2 clock source 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 3 2 R W Ox1 TMR2 CLK SRC Timer 2 Clock Source 00 Low speed OSC 01 OSC24M Ix R W 0x0 TMR2_RELOAD Timer 2 Reload 0 No effect 1 Reload timer 2 Interval value R W
59. disable 1 data inverted ref to REV signal 20 R W TTL_Data_Inv_Sel TTL data invert mode 0 bit inverted when REV is I 1 bit inverted when REV is 0 19 10 9 0 R W REVD HSYNC REV delay time in dclk Trevd REVD Taclk Note 1 When REV_SEL is 0 REV has a 2H period with 50 duty 2 When REV_SEL is 1 REV has a 2 Frame period with 50 duty 3 Make sure REV has different polarity at the beginning of every frame take VS YNC as reference 33 4 23 TCONO Ivds panel interface register Offset 0x084 Register Name TCONO LVDS IF REG Bit Read Default Description Write Hex 31 R W 0 TCONO0 LVDS En 0 disable 1 enable 30 29 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 410 2012 04 09 Ou Allwinner Technology CO Ltd A10 28 R W 0 TCONO LVDS Dir 1 normal 2 reverse NOTE LVDS direction 27 R W 0 TCONO LVDS Mode 0 NS mode 1 JEIDA mode 26 R W 0 TCONO LVDS BitWidth 0 24bit 1 18bit 25 Reserved 24 Reserved 23 R W 0 TCONO LVDS Correct Mode 0 mode 1 model 22 0 33 4 24 TCONO IO polarity register Offset 0x088 Register Name TCONO IO POL REG Bit Read Write Default Hex Description 31 30 29 28 R W 0 DCLK Sel 00 used DCLKO normal phase offset 01 used DCLK1
60. lowest priority Levell Ox1 level 1 Level2 Ox1 level 2 Level3 Ox1 level 3 highest priority 7 6 R W 0x0 IRQ35_PRIO IRQ 35 Priority Set priority level for IRQ bit 35 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 126 2012 04 09 Ou Allwinner Technology CO Ltd A10 Offset 0x88 Register Name INTC_PRIO_REG2 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority 5 4 R W 0x0 IRQ34_PRIO IRQ 34 Priority Set priority level for IRQ bit 34 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 Ox1 level 2 Level3 Ox1 level 3 highest priority 3 2 R W 0x0 IRQ33_PRIO IRQ 33 Priority Set priority level for IRQ bit 33 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 Ox1 level 2 Level3 0x1 level 3 highest priority 1 0 R W 0x0 IRQ32_PRIO IRQ 32 Priority Set priority level for IRQ bit 32 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority 11 4 29 Interrupt Source Priority 3 Register Default 0x00000000 Offset 0x8C Register Name INTC PRIO REG3 Bit Read Default Description Write Hex 31 30 R W 0x0 IRQ63_PRIO IRQ 63 Priority Set priority level for IRQ bit 63 Level0 0x0 level 0 lowest priori
61. must be even specify the width of the front porch in encoder clock cycles 6 bit unsigned even integer Allowed range is 10 to 62 Default value is 32 in 1080i mode is 44 34 4 6 TV Encoder HD mode VSYNC Register Offset 0x018 Register Name TVE 018 REG Bit Read Default Description Write Hex 31 28 27 16 R W 0 Broad_Plus_Cycle_Number_In_HD_Mode_VSYNC 15 12 11 0 R W 16 Front Porch Like In HD Mode VSYNC 34 4 7 TV Encoder Line Number Register Offset 0x01C Register Name TVE 01C REG Bit Read Default Description Write Hex 31 24 23 16 First_Video_Line Specify the index of the first line in a field frame to have active video 8 bit unsigned integer R W 16 E T For interlaced video When VSync5 B 0 FirstVideoLine is restricted to be greater than 7 When VSync5 B 1 FirstVideoLine is restricted to be greater than 9 Default value is 21 15 11 10 0 R W 20D Num Lines Specify the total number of lines in a video frame 11 bit unsigned integer Allowed range is 0 to 2048 Default value is 525 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 432 2012 04 09 Ou Allwinner Technology CO Ltd A10 For interlaced video When NTSC and FirstVideoLine is greater than 20 then NumLines is restricted to be greater than 2 FirstVideoLine 18 When NTSC and FirstVideoL
62. rite Hex 31 0 R W OUT LINEWIDTH Output channel Line width in bits 35 5 32 Output alpha control register Offset 0x120 Register Name MP OUTALPHACTL REG Bit Read W Default Description rite Hex 31 24 R W IMG_ALPHA Output image area alpha value the image area include A0 A1 and overlapping area A2 23 16 R W NONIMG ALPHA Output non image area alpha value the non image area means the pure fill color area 7 6 R W A2ALPHACTL A2 area alpha value control 0 using AO self pixel alpha AOpA 1 using A1 self pixel alpha AlpA 2 the alpha value AOpA AIpA 1 AOpA 3 using the Output image area alpha value bit31 24 5 4 R W A3ALPHACTL A3 area alpha value control 0 Oxff 1 using the Output non image area alpha value bit23 16 Other reserved 3 2 R W A1ALPHACTL A1 area alpha value control A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 481 2012 04 09 Ou Allwinner Technology CO Ltd A10 0 using A1 self pixel alpha 1 using the Output image area alpha value bit31 24 Other reserved AOALPHACTL AO area alpha value control 0 using AO self pixel alpha 1 using the Output image area alpha value bit3 1 24 Other reserved Description There is some area in output memory block The alpha color key module is enabled Only the high priority image area is called AO Only the low priority image area is called Al The high priority and
63. setting register MP ALPHACKCTL REG 0xCO Alpha Color key control register MP CKMIN REG OxC4 Color key min color register MP CKMAX REG OxC8 Color key max color register MP ROPOUTFILLCOLOR REG 0xCC Fill color of ROP output setting register MP CSC2CTL REG OxDO Color space converter 2 control register MP OUTCTL REG OxEO Output control register MP OUTSIZE REG OxE8 Output size register MP_OUTH4ADD_REG OxEC Output address high 4bits register MP_OUTL32ADD_REG OxFO OxF8 Output address low 32bits register MP_OUTLINEWIDTH_REG 0x100 0x108 Output line width register MP OUTALPHACTL REG 0x120 Output alpha control register MP ICSCYGCOEF REG 0x180 0x188 CSCO 1 Y G coefficient register MP ICSCYGCONS REG Ox18C CSCO 1 Y G constant register MP ICSCURCOEF REG 0x190 0x198 CSCO 1 U R coefficient register MP ICSCURCONS REG 0x19C CSC0 1 U R constant register MP ICSCVBCOEF REG Ox LAO CSCO 1 V B coefficient register Ox1A8 MP ICSCVBCONS REG Ox1AC CSCO 1 V B constant register MP OCSCYGCOEF REG Ox1CO CSC2 Y G coefficient register Ox1C8 MP_OCSCYGCONS_REG Ox1CC CSC2 Y G constant register MP OCSCURCOEF REG Ox1DO CSC2 U R coefficient register Ox1D8 MP OCSCURCONS REG OxIDC CSC2 U R constant register MP OCSCVBCOEF REG Ox1E0 CSC2 V B coefficient register Ox1E8 MP_OCSCVBCONS_REG Ox LEC CSC2 V B constant register 0x200 0x27C Scaling horizontal filtering coefficient RAM block 0x280 e Ox2FC Scaling vertical filtering
64. you should use copying nearest data The scaler uses a 16 bit integer and a16 bit fractional value for the X and Y increment values This allows a fractional value resolution of 1 64K Only the most significant 5 bits of the fractional value are used by the filter coefficient RAMs Scaling Filter New pixels are generated by interpolation or filtering of the original pixels Interpolation is the weighted average of the input pixels adjacent to the output pixel Filtering extends interpolation to include input pixels beyond the input pair adjacent to the output pixel The number of pixels used to generate the output defines the filter type Interpolation is a 2 tap filter A tap is equivalent to an original un scaled pixel of data A 4 tap filter would use the two pixels to the left and the two pixels to the right of the output pixel And the follow is the scaling algorithm A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 458 2012 04 09 Ou Allwinner Technology CO Ltd A10 Source Pixel Columns ucc 9 Pe Source Pixel Rows Target Pixel 9 9 9 9 Q d pr E P BE mea 9 9 9 9 e 9 LET 9 2 2 O Kimen Bh T m Vid m 1 n 35 4 Register list Module name Base address MP 0x01e80000 Register name Offset Description MP CTL REG 0x0 MP control register MP_STS_REG 0x
65. 0 R W DLL Divisor Latch Low Lower 8 bits of a 16 bit read write Divisor Latch register that contains the baud rate divisor for the UART This register may only be accessed when the DLAB bit LCR 7 is set and the UART is not busy USR 0 is zero The output baud rate is equal to the serial clock sclk frequency divided by sixteen times the value of the baud rate divisor as follows baud rate serial clock freq 16 divisor Note that with the Divisor Latch Registers DLL and DLH set to zero the baud clock is disabled and no serial communications occur Also once the DLL is set at least 8 clock cycles of the slowest UART clock should be allowed to pass before transmitting or receiving data 18 4 4 UART Divisor Latch High Register Offset 0x04 Register Name UART DLH Default Value 0x0000 0000 Bit Read Write Default Description A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 181 2012 04 09 Ou Allwinner Technology CO Ltd A10 31 8 DLH Divisor Latch High Upper 8 bits of a 16 bit read write Divisor Latch register that contains the baud rate divisor for the UART This register may only be accessed when the DLAB bit LCR 7 is set and the UART is not busy USR 0 is zero The output baud rate is equal to the serial clock sclk frequency divided by sixteen times the value of the baud rate divisor
66. 0 Disable 1 Enable If this bit is set to 1 only when the Alarm Week HH MM SS register valid bits is equal to RTC HH MM SS register and the register RTC HH MM SS bit 31 29 is 1 the week 1 alarm irq pending bit will be set to 1 R W 0x0 WKO_ALM_EN Week O Monday Alarm Enable 0 Disable 1 Enable If this bit is set to 1 only when the Alarm Week HH MM SS register valid bits is equal to RTC HH MM SS register and the register RTC HH MM SS bit 31 29 is 0 the week 0 alarm irq pending bit will be set to 1 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 105 2012 04 09 Allwinner Technology CO Ltd A10 10 3 35 Alarm IRQ Enable Offset 0x118 Register Name ALARM IRQ EN Bit Read Default Description Write Hex 31 2 1 R W 0x0 ALARM_WK_IRQ_EN Alarm Week IRQ Enable O disable 1 enable 0 R W 0x0 ALARM_CNT_IRQ_EN Alarm Counter IRQ Enable O disable 1 enable 10 3 36 Alarm IRQ Status Register Offset 0x11C Register Name ALARM IRQ STA REG Bit Read Default Description Write Hex 31 2 1 R W 0x0 WEEK IRQ PEND Alarm Week 0 1 2 3 4 5 6 IRQ Pending 0 No effect 1 Pending week counter value is reached If alarm week irq enable is set to 1 the pending bit will be sent to the interrupt controller 0 R W 0x0 CNT_IRQ_PEND Alarm Counter IRQ Pending
67. 001 Output 010 LCDO D23 011 SMC DET 100 Reserved 101 Reserved 30 28 R W 0 110 Reserved 111 Reserved 27 PD22 SELECT 000 Input 001 Output 010 LCDO D22 011 SMC VPPPP 26 24 R W 0 100 Reserved 101 Reserved A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 306 2012 04 09 Ou Allwinner Technology CO Ltd A10 110 Reserved 111 Reserved 23 PD21_SELECT 000 Input 001 Output 010 LCDO_D21 011 SMC_VPPEN 100 Reserved 101 Reserved 22 20 R W 110 Reserved 111 Reserved 19 PD20_SELECT 000 Input 001 Output 010 LCDO D20 011 CSI1 MCLK 100 Reserved 101 Reserved 18 16 R W 110 Reserved 111 Reserved 15 PD19 SELECT 000 Input 001 Output 010 LCDO D19 011 LVDS1_VN3 100 Reserved 101 Reserved 14 12 R W 110 Reserved 111 Reserved 11 PD18 SELECT 000 Input 001 Output 010 LCDO D18 011 LVDS1_VP3 100 Reserved 101 Reserved 10 8 R W 110 Reserved 111 Reserved 7 PD17 SELECT 000 Input 001 Output 010 LCDO D17 011 LVDS1_VNC 100 Reserved 101 Reserved 6 4 R W 110 Reserved 111 Reserved PD16 SELECT 000 Input 001 Output 010 LCDO D16 011 LVDS1_VPC 100 Reserved 101 Reserved 2 0 R W 110 Reserved 111 Reserved 30 3 31 PD Configure Register 3 Offset 0x78 Register Name PD CFG3 Default Value 0x0000 0000 A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Tech
68. 0x06C Register Name TCONO CPU RD1 REG Bit Read Default Description Write Hex 31 24 23 0 R Data Rd1 data read on 8080 bus without a new read operation on 8080 bus 33 4 18 TCONDO ttl panel timing register 0 Offset 0x070 Register Name TCONO TTLO REG Bit Read Default Description Write Hex 31 20 R W 0 STVH STV high plus width in delk Tstvh STVH 1 Tdclk Note STV has a period of one frame 19 0 R W 0 STVD VSYNC STV delay time Tstvd STVD 19 10 Thsync STVD 9 0 Tdclk 33 4 19 TCONDO tttl panel timing register 1 Offset 0x074 Register Name TCONO TTL1 REG Bit Read Default Description Write Hex 31 30 R W 0 CKVT CKV period in line Tckvt CKVT 1 Thsync 29 20 19 10 R W 0 CKVH CKV high plus width in delk Tckvh 2 CKVH 1 Tdclk 9 0 R W 0 CKVD VSYNC CKV delay time in dclk Tdskv CKVD Tdclk A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 408 2012 04 09 Ou Allwinner Technology CO Ltd A10 33 4 20 TCONDO ttl panel timing register 2 Offset 0x078 Register Name TCONO TTL2 REG Bit Read Default Description Write Hex 31 30 R W 0 OEVT OEV period in line Toevt OEVT 1 Thsync 29 20 19 10 R W 0 OEVH OEV high plus width in dclk Toevh OEVH 1 Tdclk 9 0 R W 0 OEVD VSYNC OEV delay ti
69. 1080P H 264 high profile encoding technology can become one of the benchmarks Besides its remarkable super HD 2160p video decoding capability A10 can stream smoothly HD video over internet including FLASH10 3 HTMLS5 3 APK Besides self developed display acceleration frame MALI400 2D 3D GPU has also been introduced to strengthen the connected smart HD SOC in terms of high profile display so that it can support popular smart systems such as Android2 3 3 0 better and improve the performance of Android loaded products as well as user experience There is no doubt that low power consumption and excellent user experience will be always on the top of end users wish list A10 has adopted Allwinnertech s most advanced technology of video CODEC and power consumption is much lower during 1080p decoding process What s more Allwinnertech will keep applying progressive VLSI design under new process so that end products can become even more competitive with shorter R amp D cycle and easier production advantages 1 1 Feature The A10 is featured as following 1 1 1 CPU B ARM Cortex A8 Core 32KB I Cache 32KB D Cache 256KB L2 Cache B Using NEON for video audio and graphic workloads eases the burden of supporting more dedicated accelerators across the SoC and enable the system to support the standards of tomorrow B RCT JAVA Accelerations to optimize just in time JIT and dynamitic adaptive compilation DAC and reduces memory footprint
70. 16 R W 110 EINT20 111 CS D20 15 PH19 SELECT 000 Input 001 Output 010 LCD1_D19 011 ATAD15 100 KP OUTI 101 SMC SDA 14 12 R W 110 EINT19 111 CSI Di 11 PH18 SELECT 000 Input 001 Output 010 LCD1 D18 011 ATAD14 100 KP OUTO 101 SMC SCK 10 8 R W 110 EINT18 111 CSI D18 7 PH17 SELECT 000 Input 001 Output 010 LCD1_D17 011 ATAD13 100 KP IN7 101 SMC_VCCEN 6 4 R W 110 EINT17 111 CSI D17 PH16 SELECT 000 Input 001 Output 010 LCD1_D16 011 ATADI2 100 KP IN6 101 Reserved 2 0 R W 110 EINT16 111 CSI1_D16 30 3 67 PH Configure Register 3 Offset 0x108 Register Name PH CFG3 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 2012 04 09 323 Ou Allwinner Technology CO Ltd A10 Default Value 0x0000_0000 Bit Read Write Default Description 31 16 15 PH27_SELECT 000 Input 001 Output 010 LCD1_ VSYNC 011 ATAIOW 100 KP_OUT7 101 SDC1_D3 14 12 R W 0 110 Reserved 111 CSU_VSYNC 11 Reserved PH26Select 000 Input 001 Output 010 LCD1_HSYNC 011 ATAIOR 100 KP_OUT6 101 SDC1_D2 10 8 R W 0 110 Reserved 111 CSII HSYNC 7 PH25 SELECT 000 Input 001 Output 010 LCD1_DE 011 ATAIORDY 100 KP OUT5 101 SDC1 DI 6 4 R W 0 110 Reserved 111 CSI1 FIELD 3 PH24 SELECT 000 Input 001 Output 010 LCD1 CLK 011 ATACS
71. 1e aseo br RR EST GRUT LEER Gee Seegen 318 30 3 59 PG Data eet ee Seed 318 30 3 60 PG Multi Driving Register U N 319 30 3 61 PG Multi Driving Register 1 eter ER ER USER a ENEE 319 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 15 2012 04 09 Ou Allwinner Technology CO Ltd A10 30 3 62 PG Pull Register 0 terrier PER rer ERREUR ER F RER EO COR e HERR E Re SR YER RS 319 30 3 63 PG PURE Sister I cii sere terere eeN aE redi iro ret lb ede dree 319 30 3 64 PH Configure Registet feed Nee deed 320 30 3 65 PH Configure Register 1 ue eee reete eee Ree aeree eo EE 321 30 3 66 PH Configure Register 2 reo te RED ECHTE ETE a EEE shi ducts 322 30 3 67 PH Configure Register 3 er err E PE RR REOR EE s 323 30 3 08 PH WE 324 30 3 69 PH Multi Driving Register U N 325 30 3 70 PH Multi Driving Register L S Eua b ea REUS 325 30 97 T PH Pull Resister Vassnes 325 30 3 72 PH Pull Register EE 325 30 3 73 PI Configure Register Q ert Eee e e ER EUN A NET ERR ERNE 326 30 3 74 PI Configure Register T eet cett re teo d repro i p ee rn Sedeevesaeates 327 30 32 75 toeerst dee eet dreet 328 30 3 76 PI Configure Registers sisino oniani ii oni Anea 329 30 3 77 PI Data Registe riisist ieaie ia io a iiai ratte 329 30 3 78 PI Multi Driving Register Oisin sainia aa Ea E i ES 330 30 33 79 Pl Multi Driving Register l i e terret rr reri e e eer ERR eee 330 30 3 80 PI Pull Register 0
72. 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 391 2012 04 09 Ou Allwinner Technology CO Ltd A10 Buffer selected at next storing for CSI 0 Next buffer selection is buffer A 1 Next buffer selection is buffer B DBS output buffer selected status 0 Selected output buffer A 1 Selected output buffer B DBE Double buffer mode enable 0 disable 1 enable If the double buffer mode is disabled the buffer A will be always selected by CSI module Offset Address 0X002C Register Name CSI1 BUF STA REG Read Default Description Write Hex LUM STATIS luminance statistical value When frame done interrupt flag come value is ready and will last until next frame done Video capture in progress Indicates the CSI is capturing video image data multiple frames The bit is set at the start of the first frame after enabling video capture When software disables video capture it clears itself after the last pixel of the current frame is captured SCAP STA Still capture in progress Indicates the CSI is capturing still image data single frame The bit is set at the start of the first frame after enabling still frame capture It clears itself after the last pixel of the first frame is captured For CCIR656 interface if the output format is frame planar YCbCr 420 mode the frame end means the field2 end the other frame end means filed end A10 User Manual V1 20 Copyright O 2011 2012 Allwinner
73. 2012 Allwinner Technology All Rights Reserved 457 2012 04 09 Ou Allwinner Technology CO Ltd A10 TapO Line O O Tap1 Line 444 O Q E lt dg i9 LE I io n Te 935 Line n2 O oS Tap3 Line n 3 O Q Vertical quantizing Each output pixel s location relative to the input pixel grid is given by X location of output pixel XO of input line output pixel number X Scale Factor Y location of output pixel 2 YO of input window output line number Y scale factor The X and Y locations may not be integer values depending on the scale factor The resulting X and Y pixel locations can be separated into an integer and a fractional part The integer part of the X and Y location selects the pixel and line number closest to the output pixel respectively The fractional part gives the fractional distance of the output pixel to the next X and Y input pixel values These fractional parts are the and B values shown in scaling algorithm diagram To perform scaling the X and Y locations of the output pixel relative to the input pixel grid must be generated This includes both the integer part to locate the adjacent pixels and the fractional part to choose the filter coefficients which generate the output value from the adjacent pixels This could be done by generating the output pixel X and Y numbers and dividing each by its associated scale factor A line may start and or end at the edge of the input image In this case
74. 2012 Allwinner Technology All Rights Reserved 57 2012 04 09 Ou Allwinner Technology CO Ltd A10 Clock Source Select 00 OSC24M 01 PLL6 10 PLL5 11 23 18 17 16 R W 0x0 CLK_DIV_RATIO_N Clock pre divide ratio n The select clock source is pre divided by 2 n The divider is 1 2 4 8 15 4 3 0 R W 0x0 CLK_DIV_RATIO_M Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 16 6 4 31 IR 1 Clock Default 0x00000000 Offset 0xB4 Register Name IR1_CLK_REG Bit Read Default Description Write Hex 31 R W 0x0 SCLK_GATING Gating Special Clock Max Clock 100MHz 0 Clock is OFF 1 Clock is ON This special clock Clock Source Divider N Divider M 30 26 25 24 R W 0x0 CLK_SRC_SEL Clock Source Select 00 OSC24M 01 PLL6 10 PLLS 11 23 18 17 16 R W 0x0 CLK_DIV_RATIO Clock pre divide ratio n The select clock source is pre divided by 2 n The divider is 1 2 4 8 15 4 3 0 R W 0x0 CLK_DIV_RATIO_M Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 58 2012 04 09 Ou Allwinner Technology CO Ltd A10 D ne SYS 6 4 32 1IS Clock Default 0x00000000 Offset 0xB8 Register Na
75. 22 20 R W 110 Reserved 111 Reserved 19 PB20_SELECT 000 Input 001 Output 010 TWI2_SCK 011 Reserved 100 Reserved 101 Reserved 18 16 R W 110 Reserved 111 Reserved 15 PB19_SELECT 000 Input 001 Output 010 TWI1_SDA 011 Reserved 100 Reserved 101 Reserved 14 12 R W 110 Reserved 111 Reserved 11 PB18_SELECT 000 Input 001 Output 010 TWII SCK 011 Reserved 100 Reserved 101 Reserved 10 8 R W 110 Reserved 111 Reserved 7 PB17 SELECT 000 Input 001 Output 010 SPR MISO 011 JTAG DIO 100 Reserved 101 Reserved 6 4 R W 110 Reserved 111 Reserved PB16 SELECT 000 Input 001 Output 010 SPI MOSI 011 JTAG DOO 100 Reserved 101 Reserved 2 0 R W 110 Reserved 111 Reserved 30 3 13 PB Configure Register 3 Offset 0x30 Register Name PB CFG3 Default Value 0x0000 0000 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 296 2012 04 09 Ou Allwinner Technology CO Ltd Bit Read Write Default Description A10 31 0 30 3 14 PB Data Register Register Name PB_DAT Offset 0x34 Default Value 0x0000_0000 Bit Read Write Default Description 31 24 PB_DAT If the port is configured as input the corresponding bit is the pin state If the port is configured as output the pin state is the same as the corresponding bit The read bit
76. 24 23 0 R W 0 Fill_Begin 33 4 44 TCONI fill data end register Offset 0x314 Register Name TCON1 FILL END1 REG Bit Read Default Description Write Hex 31 24 23 0 R W 0 Fill End 33 4 45 TCONI fill data value register Offset 0x318 Register Name TCON1_FILL_DATA1_REG Bit Read Default Description Write Hex 31 24 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 421 2012 04 09 Allwinner Technology CO Ltd A10 23 0 R W 0 Fill Value 33 4 46 TCONI fill data begin register Offset 0x31C Register Name TCON1 FILL BEG2 REG Bit Read Default Description Write Hex 31 24 23 0 R W 0 Fill_Begin 33 4 47 TCONI fill data end register Offset 0x320 Register Name TCON1 FILL END2 REG Bit Read Default Description Write Hex 31 24 23 0 R W 0 Fill_End 33 4 48 TCONI fill data value register Offset 0x324 Register Name TCON1 FILL DATA2 REG Bit Read Default Description Write Hex 31 24 23 0 R W 0 Fill_ Value 34 TV Encoder 34 1 Overview TV encoder supports SDTV and HDTV output and the latter up to 1080p 34 2 TV Encoder Register List Module Name Base Address A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights
77. 3 3 TP Control Register 2 areas bet rd e Fd ear Ea scar a ree RR 275 26 4 Median filter Control Register eese ener nnne enes ener EEan isna 276 26 4 1 TP Interrupt amp FIFO Control Register 276 26 4 2 TP Interrupt amp FIFO Status Register nennen entren 277 20 4 3 Common RE E 278 27 Keypad Interface esssessresnnesnnennnennnennnennnennnennnennnennnennnennnennnennnennnennnennneennennnennnennnennnennnennnennnennnesnnennneenee 280 Tla OVET 280 21 2 Keypad Interface Register List Autos ege Eege Eege ECO EE EAA 280 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 13 2012 04 09 Ou Allwinner Technology CO Ltd A10 27 3 Keypad Interface Register Description EE 280 27 9 1 Keypad Control RegISler aieo eterni dds E e tie de dee eR aS 280 2713 2 Keypad Timing Register ettam ere dee o n ete CE NENNEN 281 27 3 3 Keypad Interrupt Configure Register 281 21 34 Keypad Interrupt Status Register e reo rem etr Reo a RI OE esp aetate 282 213 9 Keypad Input Data Register aei tee e nep ror Hb eO eei 282 27 3 6 Keypad Input Data Register 1 sese ener etre nnne 282 27 4 Keypad Interface Pin List eerte her ERR e P eR ERNST Ea ee rhe race tao eee RENS 282 P METTUdsUENOrVu 284 p NPMES Ou EA 284 29 Security 285 29 1 ee
78. 4 Empty DMA Request Enable 0 Disable 11 R W 0 1 Enable TF_NF_DMA 10 R W 0 TXFIFO Not Full DMA Request Enable A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 172 2012 04 09 Ou Allwinner Technology CO Ltd A10 When enable if more than one free room for burst DMA request is asserted else de asserted 0 Disable 1 Enable TF_HE_DMA TXFIFO Half Empty DMA Request Enable 0 Disable 9 R W 0 1 Enable TF_EMP_DMA TXFIFO Empty DMA Request Enable 0 Disable R W 0 1 Enable 7 5 RF_FU34_DMA RXFIFO 3 4 Full DMA Request Enable This bit enables disables the RXFIFO 3 4 Full DMA Request 0 Disable 4 R W 0 1 Enable RF FU14 DMA RXFIFO 1 4 Full DMA Request Enable This bit enables disables the RXFIFO 1 4 Full DMA Request 0 Disable 3 R W 0 1 Enable RF FU DMA RXFIFO Full DMA Request Enable This bit enables disables the RXFIFO Half Full DMA Request 0 Disable 2 R W 0 1 Enable RF HF DMA RXFIFO Half Full DMA Request Enable This bit enables disables the RXFIFO Half Full DMA Request 0 Disable 1 R W 0 1 Enable RF RDY DMA RXFIFO Ready Request Enable This bit enables disables the RXFIFO Ready DMA Request when one or more than one words in RXFIFO 0 Disable 0 R W 0 1 Enable A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 173 2012 04 09
79. 5 4 0 R W 0x0 CLK RAT M Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 32 6 4 15 AXI Module Clock Gating Default 0x00000000 Offset 0x5C Register Name AXI GATING REG Bit Read Default Description Write Hex 31 1 0 R W 0x0 DRAM AXI GATING Gating AXI Clock for SDRAM 0 mask 1 pass 6 4 16 AHB Module Clock Gating Register O Default 0x00000000 Offset 0x60 Register Name AHB GATING REGO Bit Read Default Description Write Hex 31 30 29 28 277 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 47 2012 04 09 Allwinner Technology CO Ltd A10 26 Reserved 25 R W 0x0 Gating AHB Clock for NC 0 mask 1 pass 24 R W 0x0 Gating AHB Clock for PATA 0 mask 1 pass 23 R W 0x0 Gating AHB Clock for SPI3 0 mask 1 pass 22 R W 0x0 Gating AHB Clock for SPI2 0 mask 1 pass 21 R W 0x0 Gating AHB Clock for SPI1 0 mask 1 pass 20 R W 0x0 Gating AHB Clock for SPIO 0 mask 1 pass 19 18 R W 0x0 Gating AHB Clock for TS 0 mask 1 pass 17 R W 0x0 Gating AHB Clock for EMAC 0 mask 1 pass 16 R W 0x0 Gating AHB Clock for ACE 0 mask 1 pass 15 14 R W 0x
80. 5 6 7 12 3 DMA Programmable Register 12 3 1 DMA IRQ Enable Register Default 0x00000000 Offset 0x00 Register Name DMA IRQ EN REG Bit Read Default Description Write Hex 31 R W 0x0 DDMA7 END IRQ EN Dedicated DMA 7 End Transfer Interrupt Enable 0 Disable 1 Enable 30 R W 0x0 DDMA7 HF IRQ EN Dedicated DMA 7 Half Transfer Interrupt Enable 0 Disable 1 Enable 29 R W 0x0 DDMA6_END_IRQ_EN Dedicated DMA 6 End Transfer Interrupt Enable 0 Disable 1 Enable 28 R W 0x0 DDMA6_HF_IRQ_EN Dedicated DMA 6 Half Transfer Interrupt Enable 0 Disable 1 Enable 27 R W 0x0 DDMA5 END IRQ EN Dedicated DMA 5 End Transfer Interrupt Enable 0 Disable 1 Enable 26 R W 0x0 DDMAS HF IRQ EN Dedicated DMA 5 Half Transfer Interrupt Enable 0 Disable 1 Enable 25 R W 0x0 DDMA4_END_IRQ_EN Dedicated DMA 4 End Transfer Interrupt Enable 0 Disable 1 Enable 24 R W 0x0 DDMA4_HF_IRQ_EN Dedicated DMA 4 Half Transfer Interrupt Enable 0 Disable 1 Enable A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 135 2012 04 09 Allwinner Technology CO Ltd 23 R W 0x0 DDMA3_END_IRQ_EN Dedicated DMA 3 End Transfer Interrupt Enable 0 Disable 1 Enable A10 22 R W 0x0 DDMA3 HF IRQ EN Dedicated DMA 3 Half Transfer Interrupt Enable 0 Disable 1 Enable 21 R W 0x0 DDMA2_END_I
81. 6 2 CSL configuration feglSter iu siete terre d eee SEENEN 343 31 6 3 CSI capture control register i eere eee ee ree eee Meere eben e taser ERR e 345 31 64 CSI horizontal scale tegistet cen citet rp E TREO CERIS a E FORE Eaa 346 31 6 5 CSI Channel 0 FIFO 0 output buffer A address register eese 346 31 6 6 CSI Channel 0 FIFO 0 output buffer B address register esses 346 31 6 7 CSI Channel 0 FIFO I output buffer A address register esse 347 31 6 8 CSI Channel 0 FIFO 1 output buffer B address register eese 347 31 6 9 CSI Channel 0 FIFO 2 output buffer A address register essen 347 31 6 10 CSI Channel 0 FIFO 2 output buffer B address register essen 347 31 6 11 CSI Channel 0 output buffer control register rsrrrnnnnrrnrrvvnrnnnnrnnrrvnrnennrrnrevvnrnervesvrervesnennne 347 31 6 12 CSI Channel 0 status register Dite reo i re rr EH vea E Ea a 348 31 6 13 CSI Channel 0 interrupt enable register essere 349 31 6 14 CSI Channel 0 interrupt status register rurnrnrrvrrvrnvvnrnrrnrnvvnrvnrnrrnrrrvnrnernernrevvnrvesvesnrevvnsvennee 350 31 6 15 CSI Channel 0 horizontal size register nennen nennen 350 31 6 16 CSI Channel 0 vertical size register essere ener enne 350 31 6 17 CSI Channel 0 buffer length regteter cece ee ceeeeeeesecseseeeeeesesseseeseaeeaesseseeseaeeas 351 31 6 1
82. 64 64 bytes in TXFIFO 15 7 RF_CNT RXFIFO Counter These bits indicate the number of words in RXFIFO 0 0 byte in RXFIFO 1 1 byte in RXFIFO 63 63 bytes in RXFIFO 6 0 R 0x0 64 64 bytes in RXFIFO 17 4 12 SPI Special Requirement 17 4 13 SPI Pin List The direction of SPI pin is different in two work modes Master Mode and Slave Mode Port Name Width Direction M Direction S Description SPI_SCLK 1 OUT IN SPI Clock SPI MOSI 1 OUT IN SPI Master Output Slave Input Data Signal SPI MISO 1 IN OUT SPI Master Input Slave Output Data Signal SPI SS 3 0 4 OUT IN SPI Chip Select Signal Notes SPIO module has four chip select signals and SPI1 module has only one chip select signal for pin saving 17 4 14 SPI Module Clock Source and Frequency The SPI module uses two clock source AHB CLK and SPI CLK The SPI SCLK can in the range from 3Khz to 100 MHZ and AHB_CLK gt 2xSPI SCLK Clock Name Description Requirement AHB CLK AHB bus clock as the clock source of SPI AHB_CLK gt 2xSPI SCLK module SPI CLK SPI serial input clock A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 2012 04 09 176 Allwinner Technology CO Ltd A10 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 177 2012 04 09 Ou Allwinner Technology CO Lt
83. All Rights Reserved 476 2012 04 09 Ou Allwinner Technology CO Ltd A10 1 color key mode using the high priority layer as matching condition if it is true the low priority layer pass 2 color key mode using the low priority layer as matching condition if it is true the high priority layer pass 3 Reserved ALPHACK_EN Enable control 0 the ROP data will by pass the alpha ck module 1 enable Note if the module is disabled the data of channel 3 will be ignored and only the ROP data will pass through to CSC2 module 35 5 23 Color key min color register Offset 0xC4 Register Name MP_CKMIN_REG Read W Default Description rite Hex aah hoo Mo 23 16 R W CKMIN R Red 15 8 R W CKMIN G Green 7 0 R W CKMIN B Blue 35 5 24 Color key max color register Offset 0xC8 Register Name MP CKMAX REG Read W Default Description rite Hex up pg 23 16 R W CKMAX_R Red 15 8 R W CKMAX_G Green 7 0 R W CKMAX B Blue A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 477 2012 04 09 Allwinner Technology CO Ltd A10 35 5 25 Fill color of ROP output setting register Offset 0xCC Register Name MP ROPOUTFILLCOLOR REG CSC2 EN Enable control 0 Disable color space function ignore the control setting and the data flow will by pass the module 1 Enable color space converting function 35 5 27 Output control register O
84. BUFA FIFO 0 output buffer A address 32 6 6 CSI Channel 0 FIFO 0 output buffer B address register Offset Address 0X0014 Register Name CSI1 F0 BUFB REG Bit Read Default Description Write Hex 31 00 R W F0 BUFB FIFO 0 output buffer B address 32 6 7 CSI Channel 0 FIFO 1 output buffer A address register Offset Address 0X0018 Register Name CSI1 F1 BUFA REG Bit Read Default Description Write Hex uw mw fo mem S A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 390 2012 04 09 Allwinner Technology CO Ltd A10 FIFO 1 output buffer A address 32 6 8 CSI Channel 0 FIFO 1 output buffer B address register Offset Address 0X001C Register Name CSI1_F1_BUFB_REG Bit Read Default Description Write Hex 31 00 R W FI BUFB FIFO 1 output buffer B address 32 6 9 CSI Channel 0 FIFO 2 output buffer A address register Offset Address 0X0020 Register Name CSI1 F2 BUFA REG Bit Read Default Description Write Hex 31 00 R W F2_BUFA TI CRI 32 6 10 CSI Channel 0 FIFO 2 output buffer B address register Offset Address 0X0024 Register Name CSI1 F2 BUFB REG Bit Read Default Description Write Hex 31 00 R W F2_BUFB FIFO 2 output buffer B address 32 6 11 CSI Channel 0 output buffer control register Offset Address 0X0028 Register Name CSI1 BUF CTL REG Bit Read Default Description Write Hex A10 User Manual V1
85. Bit Read Write Default Hex Description 31 8 7 R W 0x0 TMR4_MODE Timer4 mode 0 Continous mode When interval value reached the timer will not disable automatically 1 Single mode When interval value reached the timer will disable automatically 6 4 R W 0x0 TMR4_CLK_PRES Select the pre scale of timer 4 clock source 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 3 2 R W Ox1 TMR4 CLK SRC Timer 4 Clock Source 00 Low speed OSC 01 OSC24M 10 External CLKINO 11 R W 0x0 TMR4_RELOAD Timer 4 Reload 0 No effect 1 Reload timer 0 Interval value R W 0x0 TMR4_EN Timer 4 Enable 0 Stop Pause 1 Start If the timer is started it will reload the interval value to internal register and the current counter will count from interval value to 0 If the current counter does not reach the zero the timer enable bit is set to 0 the current value counter will pause At least wait for 2 Tcylces the start bit can be set to 1 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 94 2012 04 09 Ou Allwinner Technology CO Ltd A10 In timer pause state the interval value register can be modified If the timer is started again and the Software hope the current value register to down count from the new interval value the
86. Byte Counter Register 149 12 3 12 Dedicated DMA Parameter Register 149 13 SDRAM Controller P 150 WS Vy e 150 14 NAND Flash Controller esssserveveenesnvvnnennennennnnnnennennennnennennennssnnennennennennnennennennnnnnennennennneenennennenenennenne 151 MESI HR 151 15 SD3 0 IEN TE 152 15 1 OVERVIEW ET 152 15 2 8D3 0 Timing Diagram eet tre tree eren e eerte ee erre tad ro nn 152 16 Two Wire LL CT 153 16 1 e 153 16 2 TWI Controller Timing Diagram sonervnrroneronenenerenerenerenesenesenesenessnessnessnessnessnessnessnesnnessnessnesnnesenee 153 16 3 TWI Controller Register Last ette ett ton eter eee tei esencia 154 16 4 TWI Controller Register Descnpon nennen nnne enen ener enen enhn enen ens 154 16 4 1 TWI Slave Address Register unosna a aa asa aa 154 16 4 2 TWIExtend Address Register 155 1643 IWlbDataRGgIsteE notet EROR ERREUR EEEERAT RR Sr OTROS Edge eate 155 1644 TWI Control erster 155 1645 FWI Status Register erem enhn teta NEESS Rede REPE ee 158 16 46 TWI Clock Register onto nee ntt ee n tr e Ee EYE Lee RE eee Re sende 159 16 47 TWI Soft Reset Register cierra ehm EDO C Ee te PER CR ede a rd dead 159 16 48 FW Enhance Feature Register ccrte riae ette e bap eee e erre 160 16 4 9 TWI Line Control Register AA 160 16 4 10 TWIDVES Control Register ceo rere n ee Er EE 161 16 5 TWI Controller Special R
87. CLK_M 2 0 R W CLK_N The 2 Wire bus is sampled by the TWI at the frequency defined by FO Fsamp F 0 Fin 2 CLK_N The TWI OSCL output frequency in master mode is F1 10 F1 F0 CLK M 1 Foscl F1 10 Fin 28CLK_N CLK M 1 10 For Example Fin 48Mhz APB clock input For 400kHz full speed 2Wire CLK_N 2 CLK_M 2 FO 48M 242 12Mhz F1 FO 10 2 1 0 4Mhz For 100Khz standard speed 2Wire CLK_N 2 CLK_M 11 FO 48M 242 12Mhz F1 F0 10 11 1 0 1Mhz 16 4 7 TWI Soft Reset Register Offset 0x18 Register Name TWI_SRST A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 159 2012 04 09 Ou Allwinner Technology CO Ltd A10 Default Value 0x0000 0000 Bit Read Write Default Description 31 1 SOFT_RST Soft Reset Write 1 to this bit to reset the TWI and clear to 0 when 0 R W 0 completing Soft Reset operation 16 4 8 TWI Enhance Feature Register Offset 0x1C Register Name TWI_EFR Default Value 0x0000_0000 Bit Read Write Default Description 31 2 0 1 R W DBN Data Byte number follow Read Command Control 0 No Data Byte to be wrote after read command 1 Only 1 byte data to be wrote after read command 2 2 bytes data can be wrote after read command 3 3 bytes data can be wrote after read comma
88. CSI is capturing video image data multiple frames The bit is set at the start of the first frame after enabling video capture When software disables video capture it clears itself after the last pixel of the current frame is captured SCAP STA Still capture in progress Indicates the CSI is capturing still image data single frame The bit is set at the start of the first frame after enabling still frame capture It clears itself after the last pixel of the first frame is captured For CCIR656 interface if the output format is frame planar YCbCr 420 mode the frame end means the field2 end the other frame end means filed end 31 6 39 CSI Channel 2 interrupt enable register Offset Address 0X0230 Register Name CSIO C2 INT EN REG Bit Read Default Description Write Hex m A S VS INT EN vsync flag The bit is set when vsync come And at this time load the buffer address for the coming frame So after this irq come change the buffer address could only effect next frame HB OF INT EN Hblank FIFO overflow A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 358 2012 04 09 Allwinner Technology CO Ltd A10 pr FIFO2 OF INT EN FIFO 2 overflow The bit is set when the FIFO 2 become overflow FIFO1 OF INT EN FIFO 1 overflow The bit is set when the FIFO 1 become overflow FIFOO OF INT EN FIFO 0 overflow The bit is set when the FIFO 0 become overflow FD INT
89. CSIO C3 BUF STA REG 0X32C CSI Channel 3 status register CSIO C3 INT EN REG 0X330 CSI Channel 3 interrupt enable A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 2012 04 09 340 Ou Allwinner Technology CO Ltd A10 register CSIO C3 INT STA REG 0X334 CSI Channel 3 interrupt status register CSIO C3 HSIZE REG 0X340 CSI Channel 3 horizontal size register CSI C3 VSIZE REG 0X344 CSI Channel 3 vertical size register CSIO C3 BUF LEN REG 0X348 CSI Channel 3 line buffer length register ISP FE EN REG 0X400 ISP Enable register ISP FE MODE REG 0X404 ISP Mode register 0X408 0X40C ISP FE OB SIZE REG 0X410 ISP OBC Image Black size register ISP FE OB VALID REG 0X414 ISP OBC Image Valid size register ISP FE OB START REG 0X418 ISP OBC Image Start register ISP FE OB CFG REG OX41C ISP OBC configuration register ISP_FE_HOB_POS_REG 0X420 ISP Horizontal OBC window start register ISP_FE_VOB_POS_REG 0X424 ISP Vertical OBC window start register ISP FE VOB PARA REG 0X428 ISP Vertical OBC parameter register ISP FE OB FIXED REG 0X42C ISP OBC fixed value register ISP FE OB OFFSET REG 0X430 ISP OBC offset register ISP FE OB CLAMP REG 0X434 ISP OBC clamp value register 0X438 ISP FE LSC CFG REG 0X43C ISP LSC configuration register ISP FE LSC ADDR REG 0X440 ISP LSC gain factor address regis
90. Digital Audio RX Channel Select register Register Name DA_RXCHSEL Offset 0x38 Default Value 0x0000_0001 Bit Read Write Default Description 31 3 RX_CHSEL RX Channel Select 0 1 ch 1 2 ch 2 3 ch 3 4 ch 2 0 R W 1 Others Reserved 22 4 16 Digital Audio RX Channel Mapping Register Register Name DA_RXCHMAP Offset 0x3C Default Value 0x0000_3210 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 233 2012 04 09 Ou Allwinner Technology CO Ltd A10 Bit Read Write Default Description 31 15 14 12 R W 3 RX_CH3_MAP RX Channel3 Mapping 000 1 sample 001 2 sample 010 3 sample 011 4 sample Others Reserved 11 10 8 R W 2 RX CH2 MAP RX Channel2 Mapping 000 1 sample 001 2 sample 010 3 sample 011 4 sample Others Reserved 6 4 R W 1 RX CHI MAP RX Channell Mapping 000 1 sample 001 2 sample 010 3 sample 011 4 sample Others Reserved 2 0 R W 0 RX CHO MAP RX Channel0 Mapping 000 1 sample 001 2 sample 010 3 sample 011 4 sample Others Reserved 22 5 Digital Audio Interface Special Requirement 22 5 1 Digital Audio Interface Pin List Port Name Width Direction M Description DA BCLK 1 IN OUT Digital Audio Serial Clock DA LRC 1 IN OUT Digital Audio Sample Rate Clock Sync
91. I tri2aciv P SDATA IN V Figure 23 4 Cold Reset timing diagram Table23 1 Cold Reset timing parameters RESET active low pulse width Tre 19 us RESET inactive to SDATA IN le A or BIT CLK active dela RESET inactive to BIT CLK JE os a startup delay A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 240 2012 04 09 N Allwinner Technology CO Ltd A10 23 5 2 Warm Reset timing diagram avri high Jeck SYNC BIT_CLK Figure 23 5Warm Reset timing diagram Table23 2 Warm Reset timing parameters ei an e Je SYNC active m pulse T syne high width SYNC inactive to BIT CLK T sync2ck 162 8 startup Kin deene O O 23 5 3 Power Down timing diagram Slot 1 Slot 2 SYNC BIT_CLK SDATA OUT sos P gt SDATA_IN WW ANN 52 pdown Note BIT CLK not to scale Fig23 6 AC link low power mode timing diagram Table23 3 AC link low power mode timing parameters End of Slot 2 to BIT CLK BIT CLK SDATA INlow A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 241 2012 04 09 N Allwinner Technology CO Ltd A10 23 5 4 AC link Clock T clk_low FE I BIT OK 7 Tok high cik period T sync low sync high sync period Fig 23 7 BIT_CLK and SYNC Timing diagram Table23 4 BIT CLK and SYNC Timing Parameters KE NUMEN fat cok fe
92. Name TCONO CTL REG Bit Read Default Description Write Hex 31 R W 0 TCONO En 0 disable 1 enable Note It executes at the beginning of the first blank line of TCONO timing 30 26 25 24 R W 0 TCONO IF 00 HV Sync DE 01 8080 I F 10 TTL I F 11 reserved 23 R W 0 TCONO RG Swap A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 402 2012 04 09 Ou Allwinner Technology CO Ltd A10 0 default 1 swap RED and BLUE data at FIFO1 22 R W TCONO Test Value O all Os l all Is 21 R W TCONO_FIFO1_Rst Write and then 0 at this bit will reset FIFO 1 Note 1 holding time must more than I DCLK 20 R W TCONO Interlace En O disable enable NOTE this flag is valid only when TCONO EN 19 9 8 4 R W TCONO State Delay STA delay NOTE valid only when TCONO EN 3 2 1 0 R W TCONO SRC SEL 00 DE CHI FIFOI enable 01 DE CH2 FIFO1 enable 10 DMA 565 input FIFO1 enable 11 Test intput FIFO1 disable Note 1 These bits are sampled only at the beginning of the first blank line of TCONO timing 2 Generally when input source is changed it would change at the beginning of the first blank line of TCONO timing 3 When FIFO1 and FIFO2 select the same source and FIFO2 is enabled it executes at the beginning of the first blank line of TV timing Also TCONO timin
93. Ou Allwinner Technology CO Ltd A10 6 4 19 APB1 Module Clock Gating Default 0x00000000 Offset 0x6C Register Name APB1_GATING_REG Bit Read Default Description Write Hex 31 24 23 R W 0x0 UART7 APB GATING Gating APB Clock for UART7 0 mask 1 pass 22 R W 0x0 UART6_APB_GATING Gating APB Clock for UART6 0 mask 1 pass 21 R W 0x0 UART5_APB_GATING Gating APB Clock for UART5 0 mask 1 pass 20 R W 0x0 UART4_APB_GATING Gating APB Clock for UART4 0 mask 1 pass 19 R W 0x0 UART3_APB_GATING Gating APB Clock for UART3 0 mask 1 pass 18 R W 0x0 UART2_APB_GATING Gating APB Clock for UART2 0 mask 1 pass 17 R W 0x0 UART1_APB_GATING Gating APB Clock for UART1 0 mask 1 pass 16 R W 0x0 UARTO APB GATING Gating APB Clock for UARTO 0 mask 1 pass 15 8 7 R W 0x0 PS21 APB GATING Gating APB Clock for PS2 1 0 mask 1 pass 6 R W 0x0 PS20_APB_GATING Gating APB Clock for PS2 0 0 mask 1 pass 3 R W 0x0 SCR APB GATING Gating APB Clock for SCR 0 mask 1 pass 4 R W 0x0 CAN APB GATING Gating APB Clock for CAN 0 mask 1 pass 3 R W 0x0 TWI2_APB_GATING Gating APB Clock for TWI2 0 mask 1 pass 1 R W 0x0 TWII APB GATING Gating APB Clock for TWI1 0 mask 1 pass 0 R W 0x0 TWIO APB GATING Gating APB Clock for TWIO 0 mask 1 pass A10 User Manual V1 20 Cop
94. Ox1 LDO EN LDO Enable 6 R W 5 4 R W 0x0 PLL5 FACTOR K PLL5 Factor K K Factor 1 The range is from 1 to 4 3 2 R W 0x0 PLL5 FACTOR MI PLL5 Factor M1 1 0 R W 0x0 PLL5 FACTOR M PLL5 Factor M M Factor 1 The range is from 1 to 4 6 4 7 PLL6 NC Default 0x21009911 Offset 0x28 Register Name PLL6 CFG REG Bit Read Default Description Write Hex 31 R W 0x0 PLL6_Enable 0 Disable 1 Enable For NC the output 24MHz N K M 6 If the NC is on the output should be equal to 10OMHz For other module the output 24MHz N K 2 Note the output 24MHz N K clock must be in the range of 240MHz 2GHz if the bypass is disabled 30 R W 0x0 PLL6_BYPASS_EN PLL6 Output Bypass Enable 0 Disable 1 Enable If the bypass is enabled the PLL6 output is 24MHz 19 18 17 16 14 13 12 8 R W Ox19 PLL6_FACTOR_N PLL6 Factor N Factor 0 N 0 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 42 2012 04 09 Ou Allwinner Technology CO Ltd A10 Factor 1 N 1 Factor 2 N 2 Factor 31 N 31 5 4 PLL6 FACTOR K PLL6 Factor K K Factor 1 The range is from I to 4 3 2 1 0 R W Ox1 PLL6 FACTOR M PLL6 Factor M M Factor 1 The range is from I to 4 6 4 8 PLL6 Tuning Default Offset 0x2C Register Name PLL6_TUN_REG Bi
95. OxBC Register Name MP_ROPIDX1CTL_REG Read W Default Description rite Hex Lon l CTL Index 1 node7 setting channel 0 and channel 1 and channel 2 mix not logic 0 by pass not NOD6 CTL Index 1 node6 setting channel 0 and channel 1 and channel 2 mix logic 0 and l or 2 xor 3 add in byte 4 add in word 32bit S multiply in byte A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 474 2012 04 09 Ou Allwinner Technology CO Ltd A10 6 multiply in word 32bit 7 channel 0 mix channel 1 then sub channel 2 in byte 8 channel 0 mix channel 1 then sub channel 2 in word 32bit Other Reserved NOD5 CTL Index 1 node5 setting channel 0 and channel 1 mix not logic 0 by pass not NOD4 CTL Index 1 node4 setting channel 0 and channel 1 mix logic 0 and l or 2 xor 3 add in byte 4 add in word 32bit S multiply in byte 6 multiply in word 32bit T channel 0 sub channel 1 in byte 8 channel 0 sub channel 1 in word 32bit Other Reserved NOD3 CTL Index 1 node3 setting channel 2 not logic O by pass not NOD2 CTL Index 1 node2 setting channel 1 not logic 0 by pass not NODI CTL Index 1 nodel setting channel 0 not logic 0 by pass not NODO CTL Index 1 node setting sorting control 0 012 1 021 2 102 3 120 4 201 5 210 Other Reserved Note t
96. PG_CFG2 Offset 0OxE0 Default Value 0x0000_0000 Bit Read Write Default Description 31 0 30 3 58 PG Configure Register 3 Register Name PG_CFG3 Offset OxE4 Default Value 0x0000_0000 Bit Read Write Default Description 31 0 30 3 59 PG Data Register Register Name PG_DAT Offset OxE8 Default Value 0x0000_0000 Bit Read Write Default Description 31 12 11 0 R W 0 PG_DAT A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 318 2012 04 09 Ou Allwinner Technology CO Ltd A10 If the port is configured as input the corresponding bit is the pin state If the port is configured as output the pin state is the same as the corresponding bit The read bit value is the value setup by software If the port is configured as functional pin the undefined value will be read 30 3 60 PG Multi Driving Register 0 Register Name PG DRVO Offset OxEC Default Value 0x0555_5555 Bit Read Write Default Description 31 20 PG_DRV PG n Multi Driving Select n 0 11 2i 1 21 00 Level 0 01 Level 1 120 11 R W Ox1 10 Level 2 11 Level 3 30 3 61 PG Multi Driving Register 1 Offset OxFO Register Name PG DRV1 Default Value 0x0000 0000 Bit Read Write Default Description 31 24 30 3 62 PG Pull Regi
97. PIO Interrupt Status Register Register Name PIO_INT_STATUS Offset 0x214 Default Value 0x0000_0000 Bit Read Write Default Description PIO_INT_STATUS External INTn Pending Bit n 0 31 0 No IRQ pending n 1 IRQ pending n 0 31 R W 0 Write 1 to clear A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 332 2012 04 09 Ou Allwinner Technology CO Ltd 30 3 88 PIO Interrupt Debounce Register A10 Offset 0x218 Register Name PIO INT DEB Default Value 0x0000 0000 Bit Read Write Default Description 31 7 DER CLK PRE SCALE Debounce Clock Pre scale n 6 4 R W 0 The selected clock source is prescaled by 2 n 3 1 PIO_INT_CLK_SELECT PIO Interrupt Clock Select 0 LOSC 32Khz 0 R W 0 1 HOSC 24Mhz A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 2012 04 09 333 Ou Allwinner Technology CO Ltd A10 31 CSIO with ISP FE 31 1 Overview CSIO is a flexible camera sensor interface which supports 8 bits raw data and 16 bits YUV422 data input and it can parse input data to memory through user format configuration CSIO has a built in ISP which can provide AWB AE Control Auto Focus Lens Shade Corrector Bad Pixel Correction and etc 31 2 Feature 31 2 1 CSI 8 bits input data Support CCIR656 protocol for NTSC and PAL 3 parallel data paths
98. Port Controller 30 1 Overview The chip has 8 ports for multi functional input out pins They are shown below RH Port A PA 18 input output port E Port B PB 24 input output port m Port C PC 25 input output port m Port D PD 28 input output port E Port E PE 12 input output port E Port F PF 6 input output port RH Port G PG 12 input output port B Port H PH 28 input output port m Port PD 22 input output port m Port SPS 84 input output port for DRAM controller For various system configurations these ports can be easily configured by software All these ports except PS can be configured as GPIO if multiplexed functions not used 32 external PIO interrupt sources are supported and interrupt mode can be configured by software 30 2 Port Register List Module Name Base Address PIO 0x01C20800 Register Name Offset Description Port n Configure Register 0 n from Pn CFGO n 0x24 0x00 0to 9 Port n Configure Register 1 n from Pn CFGI n 0x24 0x04 0 to 9 Port n Configure Register 2 n from Pn CFG2 n 0x24 0x08 0 to 9 Port n Configure Register 3 n from Pn_CFG3 n 0x24 0x0C 0 to 9 Pn_DAT n 0x24 0x10 Port n Data Register n from 0 to 9 Port n Multi Driving Register 0 n Pn_DRVO n 0x24 0x14 from 0 to 9 Port n Multi Driving Register 1 n Pn DRVI n 0x24 0x18 from 0 to 9 Pn_PULO n 0x24 0x1C Port n Pull Register 0 n from 0 to A10 User Manual V1 20 Co
99. R W 0x0 WDOG_EN Watch Dog Enable 0 No effect 1 Enable the Watch Dog 10 3 26 64 bit Counter Low Register Default 0x00000000 Offset 0xA4 Register Name CNT64_LO_REG Bit Read Default Description Write Hex 31 0 R W 0x0 CNT64_LO 64 bit Counter 31 0 10 3 27 64 bit Counter High Register Default 0x00000000 Offset 0xA8 Register Name CNT64_HI_REG Bit Read Default Description Write Hex 31 0 R W 0x0 CNT64_HI 64 bit Counter 63 32 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 100 2012 04 09 Allwinner Technology CO Ltd A10 10 3 28 64 bit Counter Control Register Default 0x00000000 Offset 0xA0 Register Name CNT64_CTRL_REG Bit Read Write Default Hex Description 31 3 2 R W 0x0 CNT64_CLK_SRC_SEL 64 bit Counter Clock Source Select 0 OSC24M 1 PLL6 6 R W 0x0 CNT64_RL_EN 64 bit Counter Read Latch Enable 0 no effect 1 to latch the 64 bit Counter to the Low Hi registers and it will change to zero after the registers are latched R W 0x0 CNT64_CLR_EN 64 bit Counter Clear Enable 0 no effect 1 to clear the 64 bit Counter Low Hi registers and it will change to zero after the registers are cleared 10 3 29 LOSC Control Default 0x00004000 Offset 0x100 Register Name LOSC_CT
100. RR Pa ERE eae Era een ovk dao Ea ena reads 297 30 3 15 PB Multi Driving Register U N 297 30 3 16 PB Multi Driving Register 1 naira 297 30 3 17 PB Pull Register Quan o eer Terese 208 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 14 2012 04 09 Ou N Allwinner Technology CO Ltd A10 30 3 18 PB Pull R gister b grenge Eed anaa aa Ea EER EES 298 30 33 19 PC Conf gure Resister LE 298 30 3 20 TEE 299 30 3 21 PC Configure Register 2 5 tr mee reete A e ob EE 301 30 3 22 PC Configure Register 3 ioeina ae EEA aE E T A EEA Eia 302 303523 PE DIGRE SSE 302 30 3 24 PC Multi Driving Register OU 303 30 3 25 PC Multi Driving Register 1 303 30 3 20 PC Pull Register E 303 30327 POPU Register Loro e epe ere eee 303 30 3 28 PD Configure Register eter eer eee RR eon eae PE Ta enata aa EES 304 30 3 29 PD Conhigure Register I Eee HH ERE EET REEF GENET ERR FERRETUR e 305 30 3 30 PD Configure Register 2 etm re Pep E re I p duds awesd rn egere ea 306 30 3 31 PD Conhtigure Register EE 307 30 3 32 PD D t TALI M ket 308 30 3 33 PD Multi Driving Register U N 309 30 3 34 PD Multi Driving Register Lice rre e EROR GRO EPR EUR Re tear ERES 309 30 3 35 PD Pull RePiSter 0e er teretes ert te er oret rr p et ERE ean 309 30 3 36 PD Pull Register 1 ere Er eter an eR e EE RE RR v e Reti ee a ERE oatescvauiencates 309 30 3 37 PE Configure Register Q D E
101. RX 100 UART1_CTS 101 Reserved 22 20 R W 0 110 Reserved 111 Reserved 19 PA12_SELECT 000 Input 001 Output 010 EMDIO 011 UART6_TX 100 UARTI_RTS 101 Reserved 18 16 R W 0 110 Reserved 111 Reserved 15 PA11 SELECT 000 Input 001 Output 010 EMDC O1 1 Reserved 100 UARTI RX 101 Reserved 14 12 R W 0 110 Reserved 111 Reserved 11 PA10 SELECT 000 Input 001 Output 010 ERXDV O1 1 Reserved 100 UARTI1 TX 101 Reserved 10 8 R W 0 110 Reserved 111 Reserved 7 PA9 SELECT 000 Input 001 Output 010 ERXERR 011 SPI3 CSI 100 Reserved 101 Reserved 6 4 R W 0 110 Reserved 111 Reserved DAN SELECT 000 Input 001 Output 010 ERXCK 011 SPD MISO 100 Reserved 101 Reserved 2 0 R W 0 110 Reserved 111 Reserved A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 290 2012 04 09 Ou Allwinner Technology CO Ltd A10 30 3 3 PA Configure Register 2 Register Name PA CFG2 Offset 0x08 Default Value 0x0000 0000 Bit Read Write Default Description 31 7 PA17 SELECT 000 Input 001 Output 010 ETXERR 011 CAN RX 100 UARTI RING 101 Reserved 6 4 R W 0 110 Reserved 111 Reserved PA16 SELECT 000 Input 001 Output 010 ECOL 011 CAN TX 100 UARTI DCD 101 Reserved 2 0 R W 0 110 Reserved 111 Reserved 30 3 4 PA Configure Register 3 Offset 0x0C Register Name PA_CFG3 Default Value 0x0000
102. Read W Default Description rite Hex aap E 28 16 R W CSC1 URCOEF the U R coefficient for CSC the value equals to coefficient 2 12 00 R W CSC URCOEF the U R coefficient for CSCO the value equals to coefficient 2 35 5 36 CSCO0 1 U R constant register Offset 0x19C Register Name MP_ICSCURCONS_REG Read W Default Description rite Hex mu p p pooo 29 16 R W 0x3211 CSC1_URCONS the U R constant for CSC1 the value equals to coefficient 2 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 483 2012 04 09 C oe CO Ltd A10 13 00 CSCO0 URCONS the U R constant for CSCO the value equals to coefficient 2 35 5 37 CSCO0 1 V B coefficient register Offset Register Name MP ICSCVBCOEF REG G Y component 0x1A0 R U component 0x1A4 B V TI 0x1A8 Read W Default Description rite Hex apr i E 28 16 R W CSC1 VBCOEF the V B coefficient for CSC the value equals to coefficient 2 12 00 R W CSCO0 VBCOEF the V B coefficient for CSCO the value equals to coefficient 2 35 5 38 CSC0 1 V B constant register Offset Ox1AC Register Name MP ICSCVBCONS REG Read W Default Description rite Hex mu p p p 29 16 R W Ox2ebl CSC1_VBCONS the V B constant for CSC1 the value equals to coefficient 2 13 00 R W Ox2ebl CSCO_VBCONS the V B constant for CSCO the value equals to coef
103. Register IR_TXFIFO Ox1C IR Transmitter FIFO Register A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 201 2012 04 09 Allwinner Technology CO Ltd A10 IR RXFIFO 0x20 IR Receiver FIFO Register IR TXINT 0x24 IR Transmitter Interrupt Control Register IR TXSTA 0x28 IR Transmitter Status Register IR RXINT Ox2C IR Receiver Interrupt Control Register IR_RXSTA 0x30 IR Receiver Status Register IR CIR 0x34 CIR Configure Register 19 4 IR Register Description 19 4 1 IR Control Register Offset 0x00 Register Name IR CTL Default Value 0x0000 0000 Bit Read Write Default Description 31 9 CGPO General Program Output GPO Control in CIR mode for TX Pin 0 Low level 1 High level 5 4 R W MD Irda Mode 00 0 576 Mbit s MIR mode 01 1 152 Mbit s MIR mode 10 4 0 Mbit s FIR mode 11 CIR mode for Remote control or wireless keyboard LOOP Loop back test 0 Normal mode 1 Loop back test When set 1 connecting the FRXD with the FTXD TXEN Transmitter Block Enable 0 Disable 1 Enable R W RXEN Receiver Block Enable 0 Disable 1 Enable 0 R W GEN A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 202 2012 04 09 Ou Allwinner Technology CO Ltd A10 Global Enable A disable on this
104. Reserved 2 0 R W 0 110 Reserved 111 Reserved 30 3 20 PC Configure Register 1 Register Name PC_CFG1 Offset 0x4C Default Value 0x0000_0000 Bit Read Write Default Description 31 PC15_SELECT 30 28 R W 0 000 Input 001 Output A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 299 2012 04 09 Ou Allwinner Technology CO Ltd A10 010 NDQ7 011 Reserved 100 Reserved 101 Reserved 110 Reserved 111 Reserved 27 PC14_SELECT 000 Input 001 Output 010 NDQ6 011 Reserved 100 Reserved 101 Reserved 26 24 R W 0 110 Reserved 111 Reserved 23 PC13_SELECT 000 Input 001 Output 010 NDQ5 011 Reserved 100 Reserved 101 Reserved 22 20 R W 0 110 Reserved 111 Reserved 19 PC12_SELECT 000 Input 001 Output 010 NDQ4 011 Reserved 100 Reserved 101 Reserved 18 16 R W 0 110 Reserved 111 Reserved 15 PC11_SELECT 000 Input 001 Output 010 NDQ3 011 SDC2_D3 100 Reserved 101 Reserved 14 12 R W 0 110 Reserved 111 Reserved 11 PC10_SELECT 000 Input 001 Output 010 NDQ2 011 SDC2_D2 100 Reserved 101 Reserved 10 8 R W 0 110 Reserved 111 Reserved 7 PC9_SELECT 000 Input 001 Output 010 NDQI 011 SDC2_D1 100 Reserved 101 Reserved 6 4 R W 0 110 Reserved 111 Reserved PC8_SELECT 000 Input 001 Output 2 0 R W 0 01
105. Reserved 417 2012 04 09 Ou Allwinner Technology CO Ltd A10 Bit Read Default Description Write Hex 31 19 18 0 R W 0 Coef_Value signed 19bit value range of 16384 16384 Offset 0x130 Register Name TCON_CEU_MUL_BR_REG Bit Read Default Description Write Hex 31 13 12 0 R W 0 Coef_Value signed 13bit value range of 16 16 Offset 0x134 Register Name TCON_CEU_MUL_BG_REG Bit Read Default Description Write Hex 31 13 12 0 R W 0 Coef_Value signed 13bit value range of 16 16 Offset 0x138 Register Name TCON CEU MUL BB REG Bit Read Default Description Write Hex 31 13 12 0 R W 0 Coef_Value signed 13bit value range of 16 16 Offset 0x13C Register Name TCON_CEU_ADD_BC_REG Bit Read Default Description Write Hex 31 19 18 0 R W 0 Coef_Value signed 19bit value range of 16384 16384 Offset 0x140 Register Name TCON_CEU_RANGE_R_ REG Bit Read Default Description Write Hex 31 24 23 16 R W 0 Coef_Range_Min unsigned 8bit value range of 0 255 15 8 7 0 R W 0 Coef_Range_Max A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 418 2012 04 09 Ou Allwinner Technology CO Ltd A10 unsigned 8bit value range of 0 255 Offset 0x144 Register Name TCON CEU R
106. Reserved 422 2012 04 09 Ou Allwinner Technology CO Ltd A10 TVE 0x01C0A000 Register Name Offset Description TVE 000 REG 0x0000 TV Encoder Enable Register TVE 004 REG 0x0004 TV Encoder Configuration Register TVE 008 REG 0x0008 TV Encoder DAC Registerl TVE 00C REG 0x000C TV Encoder Notch and DAC Delay Register TVE 010 REG 0x0010 TV Encoder chroma frequency Register TVE 014 REG 0x0014 TV Encoder Front Back Porch Register TVE 018 REG 0x0018 TV Encoder HD mode VSYNC Register TVE 01C REG 0x001C TV Encoder Line Number Register TVE 020 REG 0x0020 TV Encoder Level Register TVE 024 REG 0x0024 TV Encoder DAC Register2 TVE 030 REG 0x0030 TV Encoder Auto Detection Enable Register TVE 034 REG 0x0034 TV Encoder Auto Detection Interrupt Status Register TVE 038 REG 0x0038 TV Encoder Auto Detection Status Register TVE 03C REG 0x003C TV Encoder Auto Detection de bounce Setting Register TVE 040 REG 0x0040 TV Encoder CSC signed coefficient with 9bit fraction TVE 044 REG 0x0044 TV Encoder CSC signed coefficient2 with 9bit fraction TVE_048_REG 0x0048 TV Encoder CSC signed coefficient3 with 9bit fraction TVE_04C_REG 0x004C TV Encoder CSC unsigned coefficient4 integer TVE 100 REG 0x0100 TV Encoder Color Burst Phase Reset Configuration Register TVE 104 REG 0x0104 TV Encoder VSYNC Number Register TVE 108 REG 0x0108 TV Enco
107. SEL Clock Source Select 00 PLL3 01 PLL7 10 PLL5 11 23 18 17 16 15 4 3 0 R W 0x0 CLK DIV RATIO M Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 16 6 4 44 LCD 0 CHO Clock Default 0x00000000 Offset 0x118 Register Name LCDO0 CHO CLK REG Bit Read Default Description Write Hex 31 R W 0x0 SCLK GATING Gating Special Clock 0 Clock is OFF 1 Clock is ON This special clock 2 Clock Source 30 R W 0x0 LCDO RST LCDO Reset 0 reset valid 1 reset invalid A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 66 2012 04 09 Ou Allwinner Technology CO Ltd A10 29 26 25 24 R W 0x0 CLK_SRC_SEL Clock Source Select 00 PLL3 1X 01 PLL7 1X 10 PLL3 2X 11 PLL7 2X 23 18 17 16 15 4 3 0 6 4 45 LCD 1 CHO Clock Default 0x00000000 Offset 0x11C Register Name LCD1_CH0_CLK_REG Bit Read Default Description Write Hex 31 R W 0x0 SCLK GATING Gating Special Clock 0 Clock is OFF 1 Clock is ON This special clock 2 Clock Source 30 R W 0x0 LCD1_RST LCDI Reset 0 reset valid 1 reset invalid 29 26 25 24 R W 0x0 CLK SRC SEL Clock Source Select 00 PLL3 1X 01 PLL7 1X 10 PLL3 2X 11 PLL7 2X 23 18 17 16 15 4 3 0
108. System Control 7 1 Overview A10 embeds a high speed SRAM which has been split into five segments See detailed memory mapping in following table Area Address Size Bytes A1 0x00000000 0x00003FFF 16K A2 0x00004000 0x00007FFF 16K A3 0x00008000 0x0000B3FF 13K A4 0x0000B400 0x0000BFFF 3K C1 0x01D00000 0x01D7FFFF VE CH 0x01D80000 0x01D9FFFF ACE C3 0x01DC0000 0x01DCFFFF ISP NAND 2K D USB 0x00010000 0x00010FFF 4K B Secure RAM 0x00020000 0x0002FFFF 64K CPU I Cache 32K A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 2012 04 09 75 Allwinner Technology CO Ltd A10 CPU D Cache 32K CPU L2 Cache 256K Total K 7 2 System Control Register List Module Name Base Address SRAM 0x01C00000 Register Name Offset Description SRAM CTRL REGO 0x0000 SRAM Control Register 0 SRAM CTRL REGI 0x0004 SRAM Control Register 1 7 3 System Control Register 7 3 1 SRAM Control Register 0 Default 0x7FFFFFFF Offset 0x00 Register Name SRAM CTRL REGO Bit Read Default Description Write Hex 31 30 0 R W Ox7fffff SRAM C1 MAP ff SRAM Area C1 50K Bytes Configuration by AHB 0 map to CPU DMA 1 map to VE 7 3 2 SRAM Control Register 1 Default 0x00001300 Offset 0x04 Register Name SRAM CTRL REG1 Bit Read Default Descri
109. Technology All Rights Reserved 261 2012 04 09 Ou Allwinner Technology CO Ltd A10 1 Enable 29 R W 0x0 PREGIEN MIC1 pre amplifier Enable 0 Disable 1 Enable 28 R W 0x0 PREG2EN MIC2 pre amplifier Enable 0 Disable 1 Enable 27 R W 0x0 VMICEN VMIC pin voltage enable 0 disable 1 enable PREGI MICI pre amplifier Gain Control 00 OdB 01 35dB 10 38dB 11 41dB 26 25 R W 0x2 PREG2 MIC2 pre amplifier Gain Control 00 0dB 01 35dB 10 38dB 11 41dB 24 23 R W 0x2 ADCG ADC Input Gain Control 000 4 5dB 001 3dB 010 1 5dB 011 OdB 100 1 5dB 101 3dB 110 4 5dB 111 6dB 22 20 R W 0x3 ADCIS ADC input source select 000 left select LINEINL right select LINEINR or both select LINEINL LINEINR depending on LNRDF bit 16 001 left channel select FMINL amp right channel select FMINR 010 left and right channel both select MICI gain stage output 19 17 R W 0x2 011 left and right channel both select MIC2 gain stage output 100 left select MIC1 gain stage output amp right select MIC2 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 262 2012 04 09 Ou Allwinner Technology CO Ltd A10 gain stage output 101 left and right both select MIC1 gain stage plus MIC2 gain stage output 110 left select output MP L amp right select output MP right 111 left select LINEINL or
110. Technology CO Ltd A10 17 16 R W 0x0 PLLA OUT EXT DIV P PLLA Output external divider P The range is 1 2 4 8 15 13 R W 12 8 R W 0x10 PLLA FACTOR N PLLA Factor N Factor 0 N 0 Factor 1 N 1 Factor 2 N 2 Factor 31 N 31 7 6 5 4 R W 0x0 PLLA FACTOR K PLLA Factor K K Factor 1 The range is from 1 to 4 3 2 1 0 R W 0x0 PLLA FACTOR M PLLA Factor M M Factor 1 The range is from 1 to 4 6 4 6 PLL5 DDR Default 0x11049280 Offset 0x20 Register Name PLL5 CFG REG Bit Read Default Description Write Hex 31 R W 0x0 PLL5_Enable 0 Disable 1 Enable The PLLS output for DDR 24MHz N K M The PLL5 output for other module 24MHz N K P The PLL5 output is for the DDR Note the output 24MHz N K clock must be in the range of 240MHz 2GHz if the bypass is disabled 30 R W 0x0 PLL5_OUT_BYPASS_EN PLL5 Output Bypass Enable 0 Disable 1 Enable If the bypass is enabled the output is 24MHz 29 R W 0x0 DDR_CLK_OUT_EN DDR clock output en 17 16 R W 0x0 PLL5 OUT EXT DIV P PLL5 Output External Divider P The range is 1 2 4 8 12 8 R W Ox12 PLLS_FACTOR_N A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 41 2012 04 09 Ou Allwinner Technology CO Ltd A10 PLL5 Factor N Factor 0 N 0 Factor 1 N 1 Factor 2 N 2 Factor 3 1 N 31 7 R W
111. Technology CO Ltd A10 6 4 47 TVD Clock Default 0x00000000 eese eene enne 68 6 4 48 LCD 0 CHI Clock Default 0x00000000 sess ennemi 68 6 4 49 LCD 1 CHI Clock Default 0x00000000 eseesseeesseeeeseeeee eene enne 69 6 4 50 CSI 0 Clock Default 0x00000000 esses enne enne ennemi 70 6 4 51 CSI I Clock Default 0x00000000 eese eene enne enne 71 6 4 52 VE Clock Default 0x00000000 esses nennen enne nennen nennen rentrer enne 72 6 4 53 Audio Codec Clock Default 0x00000000 esses ener enne 72 6 4 54 AVS Clock Default 0x00000000 eese nnne 73 6 4 55 ACE Clock Default 0x00000000 eese eene nennen enne enne entente 73 6 4 56 LVDS Clock Default 0x00000000 essen enne enne enne entrent enne 74 6 4 57 HDMI Clock Default 0x00000000 ieeesssessseseseeeeee eene nennen ennemi eene 74 6 4 58 Mali400 Clock Default 0x00000000 esses enne enne 74 System Control sisscisssissciscsssssissecessissessssdssecssssssetssndssecsseissedssedssetssedseedsesdssedssnd seedsends edssed seodssndssedssed seedaseds 75 Tile e e TE 75 1 2 System Control Register EE 76 7 3 System Control Register saliske 76 7 3 1 SRAM Control Register O Default OX FFF 76 7 3 2 SRAM Control Register 1 Default 0x00001300 eene 76 TrustZone Protection Controller
112. Unit esssevevevsvevsvevnvevnnevnnevnnennnennnennnennnennnennnennnennnennnennnennnennnennnennsee 78 NEEDS 78 82 TZPC Configuration EE 78 83 TZPERE SEr Ast P EE 78 GEN E 79 8 4 1 TZPC ROSIZE Register Default 0x00000010 sees 79 8 4 2 TZPC DECPORTOStatus Register Default 0x00000000 esee 79 8 4 3 TZPC DECPORTOSet Register Default 0x00000000 eese 79 8 4 4 TZPC DECPORTOClear Register Default 0x00000000 eese 80 8 4 5 CPU Control Register Default 0x00000002 esee 80 Pulse Width Modulator 81 OTs e e TE 81 92 PWM Register EE 81 93 PWM Register DescriptiODl osi ERROR ESO GRE GERE ROUGE ROTER NERONE ORO 81 9 3 1 PWM Control Register Default 0x00000000 esee neret 81 9 3 2 PWM Channel 0 Period Register AA 83 9 3 3 PWM Channel 1 Period Register AA 84 10 Timer Controller d 85 1001 EE EE 85 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 6 2012 04 09 Ou Allwinner Technology CO Ltd A10 2012 04 09 LOD Timer Register List oh een FCR NE Pe FERRO E eee ER Fette EROR 85 10 3 Timer Programmable Register 86 10 3 1 Timer IRQ Enable Register Default 0x00000000 esee 86 10 3 2 Timer IRQ Status Register Default 0x00000000 c
113. Wide T 1 0 R W 0 Comp YUV En This bit selects if the components video output are the RGB A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 439 2012 04 09 Ou Allwinner Technology CO Ltd A10 components or the YUV components 0 The three component outputs are the RGB components 1 The three component outputs are the YUV components i e the color conversion unit is by passed 34 4 23 TV Encoder Re sync parameters Register Offset 0x130 Register Name TVE_130_REG Bit Read Default Description Write Hex 31 R W 0 Re_Sync_Field 30 R W 0 Re_Sync_Dis 0 Re Sync Enable 1 Re Sync Disable 29 27 26 16 R W 0 Re_Sync_Line_Num 15 11 10 0 R W 0 Re_Sync_Pixel_Num 34 4 24 TV Encoder Slave Parameter Register Offset 0x134 Register Name TVE_134_REG Bit Read Default Description Write Hex 31 9 8 R W 0 Slave_Thresh Horizontal line adjustment threshold selection This bit selects whether the number of lines after which the Video Encoder starts the horizontal line length adjustment is slave mode is 0 or 30 0 Number of lines is 0 1 Number of lines is 30 Default values is 0 T 1 0 R W 0 Slave_Mode Slave mode selection This bit selects whether the Video Encoder is sync slave partial slave or sync master Should be set to B 0 0 The Video Enco
114. and BP plus Register TVE 230 REG 0x0230 TV Encoder WSS Configuration Register TVE 234 REG 0x0234 TV Encoder WSS Line Register TVE 238 REG 0x0238 TV Encoder WSS Line Level Register TVE 23C REG 0x023C TV Encoder WSS Frequency Register TVE 240 REG 0x0240 TV Encoder WSS Datal Register TVE_244 REG 0x0244 TV Encoder WSS Data2 Register 34 3 TV Encoder Register Description 34 4 TV Encoder Enable Register Offset 0x000 Register Name TVE 000 REG Bit Read Default Description Write Hex 31 R W 0 Clock_Gate_Dis 0 enable 1 disable 30 Reserved 29 28 Reserved 27 23 20 19 16 R W 0 DAC3_Map 0 disable 1 TVO_DOUTO 2 TVO DOUTI 3 TVO_DOUT2 4 TVO0 DOUT3 5 TVI DOUTO 6 TV1_DOUTI 7 TV1_DOUT2 8 TV1_DOUT3 15 12 R W 0 DAC2_Map 1 TVO_DOUTO 2 TVO DOUT 3 TVO_DOUT2 4 TVO_DOUT3 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 424 2012 04 09 Ou Allwinner Technology CO Ltd A10 5 TV1_DOUTO 6 TV1 DOUTI 7 TV1 DOUT2 8 TV1 DOUT3 DAC1 map 0 disable 1 TVO_DOUTO 2 TVO DOUT 3 TVO_DOUT2 4 TVO_DOUT3 5 TV1_DOUTO 6 TV1_DOUTI 7 TV1_DOUT2 8 TV1_DOUT3 7 4 R W DACH map disable TVO_DOUTO TVO DOUTI TVO_DOUT2 TV1_DOUTO TV1 DOUT TV1_DOUT2 TV1_DOUT3 3 1 0 1 2 3 4 TVO_DOUT3 5 6 7 8 TVE_En 0 disable 1 enable Note Vi
115. been updated by the initial value the counter register should count on base of this value 23 7 13 AC97 Interface Pin list Port Name Width Direction Description AC_BIT_CLK 1 IN Digital Audio Serial Clock provided by Codec AC_SYNC 1 OUT Digital Audio Sample rate sync AC_MCLK 1 OUT AC97 Codec Input Mclk AC SDATA IN 1 IN Digital Audio serial Data Input AC SDTA OUT I OUT Digital Audio serial Data Output Note BIT CLK is provided by AC97 Codec 23 8 AC97 Clock Requirement Clock Name Description Requirement apb_clk APB bus clock s_clk AC97 serial access x1 24 576 MHz or 22 5792 MHz from CCU clock A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 253 2012 04 09 e Allwinner Technology CO Ltd A10 24 24 1 Overview Audio Codec The embedded Audio Codec is a high quality stereo audio codec with headphone amplify The audio codec is featured as following Support to automatic change amplifier On chip 24 bits DAC for play back On chip 24 bits ADC for recorder Support analog digital volume control Support 48K and 44 1K sample family Support 192K and 96K sample Support FM Line in Microphone recorder Stereo headphone amplifier that can be operated in capless headphone mode from Virtual Ground to True Ground to protect headphone The embedded Audio Codec block diagram is shown below HPC
116. between the timer disabled and enabled should be larger than 2 Tcycles Tcycles Timer clock source pre scale 10 3 18 Timer 5 Interval Value Register Offset 0x64 Register Name TMR5_INTV_VALUE_REG Bit Read Default Description Write Hex A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 96 2012 04 09 Ou Allwinner Technology CO Ltd A10 31 0 R W X TMR5 INTV VALUE Timer 5 Interval Value Note the value setting should consider the system clock and the timer clock source 10 3 19 Timer 5 Current Value Register Offset 0x68 Register Name TMR5 CUR VALUE REG Bit Read Default Description Write Hex 31 0 R W x TMRS_CUR_VALUE Timer 5 Current Value Note Timer 1 current value is a 32 bit down counter from interval value to 0 This register can be read correctly if the PCLK is faster than 2 TimerFreq TimerFreq TimerClkSource pre scale Note2 before the timer 5 is enabled the timer 5 current value register need to be written with Zero 10 3 20 AVS Counter Control Register Default 0x00000000 Offset 0x80 Register Name AVS_CNT_CTL_REG Bit Read Write Default Description 31 10 0x0 AVS_CNT1_PS Audio Video Sync Counter 1 Pause Control 0 Not pause 1 Pause Counter 1 0x0 AVS_CNTO_PS Audio Video Sync Counter 0 Pause Control 0 Not pause 1 Pause Coun
117. bit selects whether the S port Y C video output is enabled or disabled 16 R W CVBS En 0 Composite video is disabled Only Y C is enable 1 Composite video is enabled CVBS and Y C enable Note Composite Video enable Selection This bit selects whether the composite video output CVBS is enabled or disabled 15 10 R W Color_Bar_Type 0 75 7 5 75 7 5 NTSC 100 0 75 0 PAL 1 100 7 5 100 7 5 NTSC 100 0 100 0 PAL R W Color_Bar_Mode 0 The Video Encoder input is coming from the Display Engineer 1 The Video Encoder input is coming from an internal standard color bar generator Note Standard Color bar input selection This bit selects whether the Video Encoder video data input is replaced by an internal standard color bar generator or not A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 426 2012 04 09 Allwinner Technology CO Ltd A10 7 5 4 R W Mode_1080i_1250Line_Sel 0 1125 Line mode 1 1250 Line mode 3 0 R W TVMode Select 0000 480i 0001 576i 0010 480p 0011 576p O1 xx Reserved 100x Reserved 101x 720p 110x 10801 111x 1080p note changing this register value will cause some relative register setting to relative value 34 4 2 TV Encoder DAC Register1 Offset 0x008 Register Name TVE_008_REG Bit Read Default Descr
118. carrier has been detected by the modem or data set 0 ded n input is de asserted logic 1 7 R 0 1 ded n input is asserted logic 0 RI Line State of Ring Indicator This is used to indicate the current state of the modem control line ri n This bit is the complement of ri n When the Ring Indicator input ri n is asserted it is an indication that a telephone ringing signal has been 6 R 0 received by the modem or data set A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 192 2012 04 09 Ou Allwinner Technology CO Ltd A10 0 ri n input is de asserted logic 1 1 ri_n input is asserted logic 0 DSR Line State of Data Set Ready This is used to indicate the current state of the modem control line dsr_n This bit is the complement of dsr_n When the Data Set Ready input dsr_n is asserted it is an indication that the modem or data set is ready to establish communications with UART 0 dsr_n input is de asserted logic 1 1 dsr_n input is asserted logic 0 In Loopback Mode MCR 4 set to one DSR is the same as MCR 0 DTR CTS Line State of Clear To Send This is used to indicate the current state of the modem control line cts_n This bit is the complement of cts_n When the Clear to Send input cts_n is asserted it is an indication that the modem or data set is ready to exchange data with UART 0 cts_n input is de asserted logi
119. clock 31 6 42 CSI Channel 2 vertical size register Offset Address 0X0244 Register Name CSIO C2 VSIZE REG Read Default Description Write Hex m Tor 28 16 R W VER_LEN Vertical line length Valid line number of a frame ha ud 0 12 00 R W VER START Vertical line start data is valid from this line 31 6 43 CSI Channel 2 buffer length register Offset Address 0X0248 Register Name CSIO C2 BUF LEN REG Read Default Description Write Hex m or n 12 00 R W BUF LEN Buffer length of a line Unit is byte It is the max of the 3 FIFOs A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 360 2012 04 09 Ou Allwinner Technology CO Ltd A10 31 6 44 CSI Channel 3 FIFO 0 output buffer A address register Offset Address 0X0310 Register Name CSIO C3 FO BUFA REG Read Default Description Write Hex Bit 31 00 R W C3F0 BUFA FIFO 0 output buffer A address 31 6 45 CSI Channel 3 FIFO 0 output buffer B address register Offset Address 0X0314 Register Name CSIO C3 FO BUER REG Bit Read Default Description Write Hex 31 00 R W C3F0 BUFB FIFO 0 output buffer B address 31 6 46 CSI Channel 3 FIFO 1 output buffer A address register Offset Address 0X0318 Register Name CSIO C3 F1 BUFA REG Bit Read Default Description Write Hex 31 00 R W C3F1 BUFA FIFO 1 output buffer A address 31 6 47 CSI Channel 3 FIFO 1 output buffer B addres
120. coefficient RAM block 0x400 Ox7FF Palette table A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 460 2012 04 09 Ou Allwinner Technology CO Ltd A10 35 5 Registers description 35 5 1 MP control register Offset 0x0 Register Name MP_CTL_REG Read W Default Description rite Hex Gar HE R W HWERRIRQ EN Hardware error IRQ enable control O disable enable FINISHIRQ EN Mission finish IRQ enable control O disable If the bit is set the module will start 1 frame operation and stop auto MP EN Enable control O disable l enable 35 5 2 MP Status register Offset 0x4 Register Name MP_STS_REG Read W Default Description sd Po Ea o M ho HWERR FLAG TEE BUSY FLAG Module working status 5 ws ls mwmexonag A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 461 2012 04 09 Allwinner Technology CO Ltd A10 Hardware error IRQ It will be set when hardware error occur and cleared by writing 1 FINISHIRQ FLAG Mission finish IRQ Offset 0x8 Register Name MP IDMAGLBCTL REG Read W Default Description rite Hex so I Memory scan order selection 0 Top to down Left to right 1 Top to down Right to left 2 Down to top Left to right 3 Down to top Right to left Note Four input DMA channel use the same scan rule The each outpu
121. data should be written this register one by one The left channel sample 31 0 W 0 data is first and then the right channel sample 22 4 5 Digital Audio RX FIFO register Offset 0x10 Register Name DA_RXFIFO Default Value 0x0000_0000 Bit Read Write Default Description RX_DATA RX Sample Host can get one sample by reading this register The left channel sample data is first and then the right channel 31 0 R 0 sample 22 4 6 Digital Audio FIFO Control Register Register Name DA_FCTL Offset 0x14 Default Value 0x0004_00F0 Bit Read Write Default Description FIFOSRC TX FIFO source select 0 APB bus 31 R W 0 1 Analog Audio CODEC 30 26 FTX 25 R W 0 Write 1 to flush TX FIFO self clear to 0 FRX 24 R W 0 Write 1 to flush RX FIFO self clear to 0 23 19 TXTL TX FIFO Empty Trigger Level Interrupt and DMA request trigger level for TXFIFO 18 12 R W 0x40 normal condition A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 225 2012 04 09 Ou Allwinner Technology CO Ltd A10 Trigger Level TXTL 11 10 RXTL RX FIFO Trigger Level Interrupt and DMA request trigger level for RXFIFO normal condition 9 4 R W OxF Trigger Level RXTL 1 TXIM TX FIFO Input Mode Mode 0 1 0 Valid data at the MSB of TXFIFO register 1 Valid data at the LSB of TXFIFO r
122. down 11 Reserved 30 3 19 PC Configure Register 0 Register Name PC_CFG0 Offset 0x48 Default Value 0x0000_0000 Bit Read Write Default Description 31 PC7_SELECT 000 Input 001 Output 010 NRB1 011 SDC2_CLK 100 Reserved 101 Reserved 30 28 R W 0 110 Reserved 111 Reserved 27 PC6_SELECT 000 Input 001 Output 010 NRBO 011 SDC2 CMD 100 Reserved 101 Reserved 26 24 R W 0 110 Reserved 111 Reserved 23 PC5 SELECT 22 20 R W 0 000 Input 001 Output A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 2012 04 09 298 Ou Allwinner Technology CO Ltd A10 010 NRE 011 Reserved 100 Reserved 101 Reserved 110 Reserved 111 Reserved 19 PC4_SELECT 000 Input 001 Output 010 NCEO 011 Reserved 100 Reserved 101 Reserved 18 16 R W 0 110 Reserved 111 Reserved 15 PC3_SELECT 000 Input 001 Output 010 NCE1 011 Reserved 100 Reserved 101 Reserved 14 12 R W 0 110 Reserved 111 Reserved 11 PC2 SELECT 000 Input 001 Output 010 NCLE 011 SPIO_CLK 100 Reserved 101 Reserved 10 8 R W 0 110 Reserved 111 Reserved H PC1_SELECT 000 Input 001 Output 010 NALE 011 SPIO_MISO 100 Reserved 101 Reserved 6 4 R W 0 110 Reserved 111 Reserved 3 PCO_SELECT 000 Input 001 Output 010 NWE 011 SPIO_MOSI 100 Reserved 101
123. eene etre trennen enne nnns 376 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 18 2012 04 09 Ou N Allwinner Technology CO Ltd A10 31 6 88 ISP AWBE window start register rnsnonroornonrvnrnnronnnvnnvnnennsvvnvnvnnsnnenvnvnnsvnsnnsvvnsvevnesvranvnvnesene 376 31 6 89 ISP AWBE configuration register snrsnrrvrrvnnrnrnnrrvvnvnnnnrrnrnvvnnnnnnrnnrrnvernennarnrevvennennasneesvesnennne 3T 31 6 90 ISP Histogram region 0 window size register sese 3T 31 6 91 ISP Histogram region 0 window start register rrrrronnnnronrnvvnvnnnnrnvrrvnrnnnnrrnrevvnrnesnesvrevvesnennne 3T 31 6 92 ISP Histogram region 1 window size register essen 378 31 6 93 ISP Histogram region 1 window start register sse 378 31 6 94 ISP Histogram region 2 window size register sese 378 31 6 95 ISP Histogram region 2 window start register rrrrrnnnnrrnrnvrnrnnnnrnnrrnvnrnennrrnrrvvnrnernervrevvesnennne 379 31 6 96 ISP Histogram region 3 window size register esses eene 379 31 6 97 ISP Histogram region 3 window start register rsrrrnnnnrrnrnvrnvnnnnrnnrrnvnrnnnnrrnrevvnrnernervrevvennennne 379 31 6 98 ISP 3A Statistics output address register sess 380 31 6 99 ISP LUT Defect Correction configuration register ssrrnrrvrrrnnrnrnnrrrvnrnennrrnrevvnrnervarnrernesnennne 380 31 6 100 ISP LUT Defect Correction addr
124. four low power modes namely General Clock Gating STOP SUPER STANDBY and SLEEP In General Clock Gating mode developer can turn on clocks for selective internal peripherals accordingly in order to achieve optimized power consumption For instance if an UART is not required software programming can cut off the timer out of power saving consideration In STOP mode all clocks to Cortex A8 core as well as peripherals can be frozen by disabling PLLs In SUPER STANDBY mode ONLY AVCC and DRAM VCC power domains are on while all others VCC CPU VDD CORE VDD RTC VDD are off The external SDRAM has entered self refresh mode under which data can be preserved and firmware can be activated quickly In SLEEP mode Cortex A8 core has been power gated and so with internal logic except the wakeup logic RTC module In order to enter SLEEP mode an independent power source is required that supplies power to the wakeup logic A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 34 2012 04 09 Ou Allwinner Technology CO Ltd A10 6 Clock Control Module 6 1 Overview The Clock Control Module is made up of 7 PLLs a Main Oscillator an on chip RC Oscillator and a 32768Hz low power Oscillator m CPU Clock AHB Clock L B APB Clock L Special Clock It integrates two crystal oscillators A 24 MHz crystal is mandatory and provides the clock source for the PLL and the main digital block
125. framing errors or Reading the line status break interrupt status register 0100 Second Received data Receiver data available Reading the available non FIFO mode or FIFOs receiver buffer disabled or RCVR FIFO trigger register level reached FIFO mode and non FIFO mode FIFOs enabled or FIFOs disabled or the FIFO drops below the trigger level FIFO mode and FIFOs enabled 1100 Second Character No characters in or out of the Reading the timeout RCVR FIFO during the last 4 receiver buffer indication character times and there is at register least Icharacter in it during This time 0010 Third Transmit Transmitter holding register Reading the IIR holding empty Program THRE Mode register if source register empty disabled or XMIT FIFO at or of interrupt or below threshold Program THRE writing into THR Mode enabled FIFOs or THRE Mode not selected or disabled or XMIT FIFO above threshold FIFOs and THRE Mode selected and enabled 0000 Fourth Modem status Clear to send or data set ready or Reading the ring indicator or data carrier Modem status detect Note that if auto flow Register A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 184 2012 04 09 Ou Allwinner Technology CO Ltd A10 control mode is enabled a change in CTS that is DCTS set does not cause an interrupt 0111 Fifth Busy detect UART 16550 COMPATIBLE Reading the indicatio
126. is proper for PAL with square pixel 101 0 8359 when notch wide value is B 1 this selection is proper for CCIR PAL or 0 7734 when notch wide value is B 0 110 0 7813 111 0 7188 Default value is B 010 34 4 14 TV Encoder Cb Cr Level Gain Register Offset 0x10C Register Name TVE 10C REG Bit Read Default Description Write Hex 31 16 15 8 R W 0 Cr Burst Level Specify the amplitude of the Cr burst 8 bit 2 s complement integer Allowed range is 127 to 127 Default value is 0 7 0 R W 3C Cb_Burst_Level Specify the amplitude of the Cb burst 8 bit 2 s complement integer Allowed range is 127 to 127 Default value is 60 34 4 15 TV Encoder Tint and Color Burst Phase Register Offset 0x110 Register Name TVE_110_REG Bit Read Default Description Write Hex 31 24 23 16 R W 0 Tint Specify the tint adjustment of the chroma signal for CVBS and Y C outputs The adjustment is effected by setting the sub carrier phase to the value of this parameter 8 8 bit unsigned fraction Units are cycles of the color burst frequency Default value is 0 15 8 7 0 R W 0 Chroma_Phase Specify the color burst initial phase ChromaPhase 8 8 bit unsigned fraction Units are cycles of the color burst frequency Default value is X 00 The color burst is set to this phase at the first HSYNC and then reset to the same value at further HSYN
127. level 1 Level2 0x1 level 2 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 2012 04 09 131 Allwinner Technology CO Ltd A10 Offset 0x90 Register Name INTC PRIO REGS Level3 Ox1 level 3 highest priority 15 14 R W 0x0 IRQ71_PRIO IRQ 71 Priority Set priority level for IRQ bit 71 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 Ox1 level 2 Level3 Ox1 level 3 highest priority 13 12 R W 0x0 IRQ70_PRIO IRQ 70 Priority Set priority level for IRQ bit 70 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority 11 10 R W 0x0 IRQ69 PRIO IRQ 69 Priority Set priority level for IRQ bit 69 Level 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 Ox1 level 2 Level3 Ox1 level 3 highest priority 9 8 R W 0x0 IRQ68 PRIO IRQ 68 Priority Set priority level for IRQ bit 68 Level 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority 7 6 R W 0x0 IRQ67_PRIO IRQ 67 Priority Set priority level for IRQ bit 67 Level0 0x0 level 0 lowest priority Levell 0x1 level 1 Level2 Ox1 level 2 Level3 0x1 level 3 highest priority 5 4 R W 0x0 IRQ66_PRIO IRQ 66 Priority Set priority level for IRQ bit 66 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2
128. output the pin state is the same as the corresponding bit The read bit value is the value setup by software If the port is configured as functional pin the undefined value will be read 30 3 42 PE Multi Driving Register 0 Register Name PE DRVO Offset 0xA4 Default Value 0x0055 5555 Bit Read Write Default Description 31 24 PE DRV 21 1 21 PE n Multi Driving Select n 0 15 G 0 11 R W Ox1 00 Level 0 01 Level 1 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 312 2012 04 09 Ou Allwinner Technology CO Ltd A10 10 Level 2 11 Level 3 30 3 43 PE Multi Driving Register 1 Register Name PE_DRV1 Offset 0xA8 Default Value 0x0000_0000 Bit Read Write Default Description 31 0 30 3 44 PE Pull Register 0 Register Name PE_PULLO Offset OxAC Default Value 0x0000_0000 Bit Read Write Default Description 31 24 PE_PULL PE n Pull up down Select n 0 11 2i 1 2i 00 Pull up down disable 01 Pull up 120 11 R W 0x0 10 Pull down 11 Reserved 30 3 45 PE Pull Register 1 Register Name PE_PULL1 Offset 0xBO Default Value 0x0000_0000 Bit Read Write Default Description 31 0 30 3 46 PF Configure Register 0 Register Name PF_CFG0 Offset 0xB4 Default Value 0x0040_4044 Bit Read Write Default Des
129. register is valid only if the Data Ready DR bit in the Line Status Register LCR is set If in FIFO mode and FIFOs are enabled FCR 0 set to one this register accesses the head of the receive FIFO If the receive FIFO is full and this register is not read before the next data character arrives then the data already in the FIFO is preserved but any incoming data are lost and an overrun error occurs 18 4 2 UART Transmit Holding Register Offset 0x00 Register Name UART_THR Default Value 0x0000_0000 Bit Read Write Default Description 31 8 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 180 2012 04 09 Ou Allwinner Technology CO Ltd A10 7 0 THR Transmit Holding Register Data to be transmitted on the serial output port sout in UART mode or the serial infrared output sir_out_n in infrared mode Data should only be written to the THR when the THR Empty THRE bit LSR 5 is set If in FIFO mode and FIFOs are enabled FCR 0 1 and THRE is set 16 number of characters of data may be written to the THR before the FIFO is full Any attempt to write data when the FIFO is full results in the write data being lost 18 4 3 UART Divisor Latch Low Register Offset 0x00 Register Name UART_DLL Default Value 0x0000_0000 Bit Read Write Default Description 31 8 7
130. reload bit and the enable bit should be set to 1 at the same time Notel if the clock source is External CLKIN the interval value register is not used the current value register is an up counter that counting from 0 Note2 the time between the timer disabled and enabled should be larger than 2 Tcycles Tcycles Timer clock source pre scale 10 3 15 Timer 4 Interval Value Register Offset 0x54 Register Name TMR4_INTV_VALUE_REG Bit Read Default Description Write Hex 31 0 R W x TMR4_INTV_VALUE Timer 4 Interval Value Note the value setting should consider the system clock and the timer clock source 10 3 16 Timer 4 Current Value Register Offset 0x58 Register Name TMR4 CUR VALUE REG Bit Read Default Description Write Hex 31 0 R W x TMR4 CUR VALUE Timer 4 Current Value Notel Timer current value is a 32 bit down counter from interval value to 0 This register can be read correctly if the PCLK is faster than 2 TimerFreq TimerFreq TimerClkSource pre scale Note2 before the timer 4 is enabled the timer 4 current value register need to be written with Zero 10 3 17 Timer 5 Control Register Default 0x00000004 Offset 0x60 Register Name TMR5 CTRL REG Bit Read Default Description Write Hex 31 8 7 R W 0x0 TMR5 MODE Timer5 mode 0 Continous mode When interval value reached the timer will not disable automaticall
131. request interrupt service The watchdog timer generates a general reset signal The Real Time Clock RTC can be used as a calendar RTC can operate using the backup battery while the system power is off Although power is off backup battery can store the time by Second Minute Hour HH MM SS Day Month and Year YY MM DD data It has a built in leap year generator and an independent power pin RTCVDD The Alarm generates an alarm signal at a specified time in the power off mode or normal operation mode In normal operation mode both the alarm interrupt and the power management wakeup are activated In power off mode the power management wakeup signal is activated 10 2 Timer Register List Module Name Base Address Timer 0x01C20C00 Register Name Offset Description TMR IRQ EN REG 0x0000 Timer IRQ Enable TMR IRQ STA REG 0x0004 Timer Status TMRO CTRL REG 0x0010 Timer 0 Control TMRO0 INTV VALUE REG 0x0014 Timer 0 Interval Value TMRO CUR VALUE REG 0x0018 Timer 0 Current Value TMR1 CTRL REG 0x0020 Timer 1 Control TMRI1 INTV VALUE REG 0x0024 Timer 1 Interval Value TMR1 CUR VALUE REG 0x0028 Timer 1 Current Value TMR2 CTRL REG 0x0030 Timer 2 Control A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 85 2012 04 09 Ou Allwinner Technology CO Ltd A10
132. set when 3 FIFOs still overflow after the hblank co 04 R W FIFO2 OF INT EN FIFO 2 overflow The bit is set when the FIFO 2 become overflow 03 R W FIFO1 OF INT EN FIFO 1 overflow The bit is set when the FIFO 1 become overflow 02 R W FIFOO OF INT EN FIFO 0 overflow The bit is set when the FIFO 0 become overflow m pew fo mmt A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 363 2012 04 09 Ou Allwinner Technology CO Ltd A10 Frame done Indicates the CSI has finished capturing an image frame Applies to video capture mode The bit is set after each completed frame capturing data is wrote to buffer as long as video capture remains enabled CD INT EN Capture done Indicates the CSI has completed capturing the image data For still capture the bit is set when one frame data has been wrote to buffer For video capture the bit is set when the last frame has been wrote to buffer after video capture has been disabled For CCIR656 interface if the output format is frame planar YCbCr 420 mode the frame end means the field2 end the other frame end means field end 31 6 53 CSI Channel 3 interrupt status register Offset Address 0X0334 Register Name CSIO C3 INT STA REG Read Default Description Write Hex R W vsync flag R W HB_OF_PD Hblank FIFO overflow E R W FIFO2_OF_PD FIFO 2 overflow R W FIFO1_OF_PD TT re 02 R FIFOO OF PD
133. slave mode SLA6 corresponds to the first bit received from the 2 Wire bus If GCE is set to 1 the TWI will also recognize the general call address 00h For 10 bit addressing When the address received starts with 11110b the TWI recognizes this as the first part of a 10 bit address and if the next two bits match ADDR 2 1 i e SLAX9 and SLAXS of the device s extended address it sends an ACK The device does not generate an interrupt at this point If the next byte of the address matches the XADDR register SLAX7 SLAXO the TWI generates an interrupt and goes into slave mode 16 4 2 TWI Extend Address Register Register Name TWI XADDR Offset 0x04 Default Value 0x0000 0000 Bit Read Write Default Description 31 8 SLAX Extend Slave Address 7 0 R W 0 SLAX 7 0 16 4 3 TWI Data Register Register Name TWI DATA Offset 0x08 Default Value 0x0000 0000 Bit Read Write Default Description 31 8 TWI_DATA 7 0 R W 0 Data byte for transmitting or received 16 4 4 TWI Control Register Offset 0x0C Register Name TWI_CNTR A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 155 2012 04 09 Ou Allwinner Technology CO Ltd A10 Default Value 0x0000_0000 Bit Read Write Default Description 31 8 INT_EN Interrupt Enable 1 b0 The interrupt line alwa
134. subtraction value A signed number ranging from 128 to 127 31 6 78 ISP H3A Median filter threshold register Offset Address 0X470 Register Name ISP FE M FIL TH REG Read Default Description Write Hex mu o e o S 07 00 R W H3A TH H3A Median filter threshold ranges from 0 255 31 6 79 ISPAF window number register Offset Address 0X474 Register Name ISP FE AF NUM REG Read Default Description Write Hex Br or 11 08 R W AF VER NUM AF vertical window number VWN ranges from 1 8 M 03 00 R W AF HOR NUM AF horizontal window number HWN ranges from 1 8 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 373 2012 04 09 Allwinner Technology CO Ltd A10 31 6 80 ISP AF window size register Offset Address 0X478 Register Name ISP FE AF SIZE REG Bit Read Default Description Write Hex 25 16 R W AF_HEIGHT AF window height H H ranges from 0 512 08 00 R W 4 AF_WIDTH AF window width W W ranges from 0 256 The actual window width is 2 W 31 6 81 ISP AF window start register Offset Address 0X47C Register Name ISP FE AF POS REG Bit Read Default Description Write Hex 27 16 R W AF_VER_START med The start vertical position for AF window Ranges from 0 to 4095 AF HOR START The start horizontal position for AF window Ranges from 0 to 4095 31 6 82 ISPAF configuration register Offset Address 0X480 Regis
135. transmit pulse A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 203 2012 04 09 Allwinner Technology CO Ltd A10 1 0 19 4 3 IR Transmitter Address Register Register Name IR_TXADR Offset 0x08 Default Value 0x0000_0000 Bit Read Write Default Description 31 9 HAG Hardware Address Generator When this bit is set the content of the TPA bits is transmitted as a packet address When the bit is cleared the packet address is read from TX FIFO 0 Read packet address from TX FIFO 8 R W 0 1 Use TPA bits as packet address TPA Transmit Packet Address This field contains the 8 bit Transmit Packet Address If 7 0 R W 0 the HAG bit is cleared the TPA bits have no effect 19 4 4 IR Transmitter Counter Register Register Name IR TXCNT Offset 0x0C Default Value 0x0000_0000 Bit Read Write Default Description 31 11 TPL Transmit Packet Length This field contains the length of the address control and data The length are N 1 bytes 11 d0 1 bytes 11 d1 2 bytes 11 d2 3 bytes 11 d2046 2047 bytes 10 0 R W 0 11 d2047 2048 bytes A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 204 2012 04 09 Allwinner Technology CO Ltd A10 19 4 5 IR Receiver Configure Register Offset 0x10 Register Name IR_RXCTL Default Value
136. up to three times M Trustzone technology allows for secure transactions and digital right managements DRM A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 24 2012 04 09 Ou Allwinner Technology CO Ltd A10 1 1 2 GPU W support Open GL ES 2 0 open VG 1 1 W support BLT ROP2 3 4 W support 90 180 270 degree Rotation M support Mirror alpha including plane and pixel alpha color key M Scaling function with 4 4 taps and 32 phase Support format convertion 1 1 3 VPU W Video Decoding FULL HD B Support all popular video formats including VP8 AVS H 264 H 263 VC 1 MPEG 1 2 4 B Support 1920 10800 60fps in all formats BR Video Encoding W Support encoding in H 264 High Profile format B 1080p 60fps W 720p 100fps 1 1 4 Display Processing Ability Four moveable and size adjustable layers 8 tap scale filter in horizontal and 4 tap in vertical direction for scaling support Multi format image input support Alpha blending color key gamma support Hardware cursor sprite support Vertical keystone correction support Output color correction luminance hue saturation etc support motion adaptive de interlace support Video enhancement lum peaking DCTi black and white level extension support 3D format content input output format convert display including HDMI 1 1 5 Display Output Ability B Support HDMI V1 3 V1 4 W Flexible LCD interface CPU Sync RGB
137. will maintain another 12 bits counter The 12 bits counter is used for counting the cycle number of one 24Mhz clock When the 12 bits counter reaches gt N the divisor value the internal 33 bits counter register will increase 1 and the 12 bits counter will reset to zero and restart again Notes It can be configured by software at any time 10 3 24 Watch Dog Control Register Offset 0x90 Register Name WDOG_CTRL_REG Bit Read Default Description Write Hex 31 13 12 1 R W 0x333 Reserved 0 R W X WDOG RSTART Watch Dog Restart 0 No effect 1 Restart the Watch Dog 10 3 25 Watch Dog Mode Register Default 0x00000000 Offset 0x94 Register Name WDOG MODE REG Bit Read Default Description Write Hex 31 7 6 3 R W 0x0 WDOG INTV VALUE Watch Dog Interval Value Watchdog clock source is OSC24M if the OSC24M is turned off the watchdog will not work 0000 0 5sec 0001 1sec A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 99 2012 04 09 Ou Allwinner Technology CO Ltd A10 0010 2sec 0011 3sec 0100 4sec 0101 5sec 0110 6sec 0111 8sec 1000 10sec 1001 12sec 1010 14sec 1011 16sec 1100 1101 1110 1111 2 R W 0x0 WDOG_RST_EN Watch Dog Reset Enable 0 No effect on the resets 1 Enables the Watch Dog to activate the system reset 0
138. 0 X jj IIC3 lI C4 lIC5 T Figure 16 1 2 Wire Timing Diagram 16 3 TWI Controller Register List Module Name Base Address TWIO 0x01C2AC00 TWII 0x01C2B000 TWI2 0x01C2B400 Register Name Offset Description TWI ADDR 0x0000 TWI Slave address TWI XADDR 0x0004 TWI Extended slave address TWI DATA 0x0008 TWI Data byte TWI CNTR 0x000C TWI Control register TWI STAT 0x0010 TWI Status register TWI CCR 0x0014 TWI Clock control register TWI SRST 0x0018 TWI Software reset TWI EFR 0x001C TWI Enhance Feature register TWI LCR 0x0020 TWI Line Control register 16 4 TWI Controller Register Description 16 4 1 TWI Slave Address Register Register Name TWI ADDR Offset 0x00 Default Value 0x0000 0000 Bit Read Write Default Description 31 8 SLA Slave address 7 bit addressing SLA6 SLAS SLA4 SLA3 SLA2 SLA1 SLAO 7 1 R W 0 10 bit addressing A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 154 2012 04 09 eii Ou Allwinner Technology CO Ltd A10 1 1 1 1 0 SLAX 9 8 GCE General call address enable 0 Disable 0 R W 0 1 Enable Notes For 7 bit addressing SLA6 SLAO is the 7 bit address of the TWI when in slave mode When the TWI receives this address after a START condition it will generate an interrupt and enter
139. 0 31 6 106 ISP FE CbCr Output address register Offset Address 0X504 Register Name ISP FE C ADDR REG Bit Read Default Description Write Hex 31 00 R W ISP FE C ADDR The memory address for ISP FE CbCr output DRAM Address P S This register has double buffer it should be reloaded by hardware at every vsync A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 383 2012 04 09 Ou Allwinner Technology CO Ltd A10 32 CSII 32 1 Overview CSII is a high performance camera sensor interface which supports 24 bits RGB YUV444 data input and it can parse input data to memory through user format configuration It is featured as following B 8 bits input data Support CCIR656 protocol for NTSC and PAL 3 parallel data paths for image stream parsing Received data double buffer support Parsing BAYER data into planar R G B output to memory Parsing interlaced data into planar or tie based YCbCr output to memory Pass raw data direct to memory All data transmit timing can be adjusted by software support multi channel ITU R BT 656 time multiplexed format luminance statistical value support 10 bit raw data input support 24 bit RGB YUV 444 input interlace progressive mode pixel clock up to 148 5 1080p 32 2 Block diagram ZN lt n PCLK E CSI k HS tn p e FIELD S v Data 23 0 Figure32 1 A10 User Manual V1 20 Copyright O 2011 201
140. 0 NDQO 011 SDC2 DO A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 300 2012 04 09 Ou Allwinner Technology CO Ltd A10 100 Reserved 101 Reserved 110 Reserved 111 Reserved 30 3 21 PC Configure Register 2 Register Name PC_CFG2 Offset 0x50 Default Value 0x0000_0000 Bit Read Write Default Description 31 PC23_SELECT 000 Input 001 Output 010 Reserved 011 SPIO_CSO 100 Reserved 101 Reserved 30 28 R W 0 110 Reserved 111 Reserved 17 PC22_SELECT 000 Input 001 Output 010 NCE7 011 SPR MISO 100 Reserved 101 Reserved 26 24 R W 0 110 Reserved 111 Reserved 23 PC21_SELECT 000 Input 001 Output 010 NCE6 011 SPR MOSI 100 Reserved 101 Reserved 22 20 R W 0 110 Reserved 111 Reserved 19 PC20_SELECT 000 Input 001 Output 010 NCES 011 SPR CLK 100 Reserved 101 Reserved 18 16 R W 0 110 Reserved 111 Reserved 15 PC19 SELECT 000 Input 001 Output 010 NCE4 011 SPR CSO 100 Reserved 101 Reserved 14 12 R W 0 110 Reserved 111 Reserved 11 PC18 SELECT 000 Input 001 Output 10 8 R W 0 010 NCE3 011 Reserved A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 301 2012 04 09 Ou Allwinner Technology CO Ltd A
141. 0 default 1 delay next line sync Hsync in basic timing until the FIFO1 is full Note it must be used when FIFO depth is less than one line active pixels 30 28 27 16 R W 0 HT Thcycle HT 1 Tdclk Note 1 parallel HT gt HBP 1 X 1 2 2 serial 1 HT gt HBP 1 X 1 342 3 serial 2 HT gt HBP 1 X 1 3 242 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 404 2012 04 09 Ou Allwinner Technology CO Ltd A10 15 10 9 0 R W HBP horizontal back porch in delk Thbp HBP 1 Tdclk 33 4 10 TCONO basic timing register2 Offset 0x050 Register Name TCONO BASIC2 REG Bit Read Default Description Write Hex 31 28 27 16 R W 0 VT TVT VT 2 Thsync Note VT 2 gt VBP 1 Y 1 2 15 10 9 0 R W 0 VBP Tvbp VBP 1 Thsync 33 4 12 TCONO basic timing register3 Offset 0x054 Register Name TCONO BASIC3 REG Bit Read Default Description Write Hex 31 26 25 16 R W 0 HSPW Thspw HSPW 1 Tdclk Note HT gt HSPW 1 15 10 9 0 R W 0 VSPW Tvspw VSPW 1 Thsync Note VT 2 VSPW 1 33 4 13 TCONO hv panel interface register Offset 0x058 Register Name TCONO HV IF REG Bit Read Default Description Write Hex 31 R W 0 HV_Mode 0 24bit parallel mode 1 8b
142. 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority 19 18 R W 0x0 IRQ41_PRIO IRQ 41 Priority Set priority level for IRQ bit 41 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 2012 04 09 125 Ou Allwinner Technology CO Ltd A10 Offset 0x88 Register Name INTC_PRIO_REG2 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority 17 16 R W 0x0 IRQ40_PRIO IRQ 40 Priority Set priority level for IRQ bit 40 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 Ox1 level 2 Level3 Ox1 level 3 highest priority 15 14 R W 0x0 IRQ39_PRIO IRQ 39 Priority Set priority level for IRQ bit 39 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 Ox1 level 2 Level3 0x1 level 3 highest priority 13 12 R W 0x0 IRQ38 PRIO IRQ 38 Priority Set priority level for IRQ bit 38 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority 11 10 R W 0x0 IRQ37 PRIO IRQ 37 Priority Set priority level for IRQ bit 37 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 Ox1 level 2 Level3 Ox1 level 3 highest priority 9 8 R W 0x0 IRQ36_PRIO IRQ 36 Priority Set priority level for IRQ bit 36 Level0 0x0 level 0
143. 0 1 Enable RF_F34_INT_EN RXFIFO 3 4 Full Interrupt Enable 0 Disable 4 R W 0 1 Enable RF_F14_INT_EN RX FIFO 1 4 Full Interrupt Enable 0 Disable 3 R W 0 1 Enable RF_FU_INT_EN RX FIFO Full Interrupt Enable 0 Disable 2 R W 0 1 Enable RF_HALF_FU_INT_EN RX FIFO Half Full Interrupt Enable 1 R W 0 0 Disable A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 169 2012 04 09 Ou Allwinner Technology CO Ltd A10 1 Enable 0 R W RF_RDY_INT_EN RX FIFO Ready Interrupt Enable 0 Disable 1 Enable 17 4 5 SPI Interrupt Status Register Offset 0x10 Register Name SPI INT STA Default Value 0x0000 1B00 Bit Read Write Default Description 31 INT CBF Interrupt Clear Busy Flag 0 clear interrupt flag done 1 clear interrupt flag busy 30 24 23 20 ES VE ES a 19 18 MM o0 17 R W SSI SS Invalid Interrupt When SSI is 1 it indicates that SS has changed from valid state to invalid state Writing 1 to this bit clears it 16 R W TC Transfer Completed In master mode it indicates that all bursts specified by BC has been exchanged In other condition When set this bit indicates that all the data in TXFIFO has been loaded in the Shift register and the Shift register has shifted out all the bits Writing 1 to this bit clears it 0 Busy 1 Transfer Co
144. 0 29 28 27 26 25 24 23 22 21 20 19 18 17 16 B1 G1 R1 Al BO GO RO AO 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PS 0x11 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BO GO RO AO Bl Gl R1 Al 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PS 1xxx the R component is swapped with B component 16 bpp ATR5G5B5 mode PS 0x00 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 2012 04 09 490 Ou Allwinner Technology CO Ltd A10 Al R1 Gl Bl A0 RO GO BO 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PS 0x01 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 A0 RO GO BO Al R1 G1 B1 15 14 13 12 11 10 09 08 07 06 05 04 03 02 O1 00 PS 0x10 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bl Gl R1 Al BO GO RO AO 15 14 13 12 11 10 09 08 07 06 05 04 03 02 O1 00 PS 0x11 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BO GO RO AO Bl Gl RI Al 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PS 1xxx the R component is swapped with B component 16 bpp R5G6B5 mode PS 0x00 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R1 G1 B1 RO GO BO 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PS 0x01 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RO GO BO R1 Gl Bl 15 14 13 12 11 10 09
145. 0 Gating AHB Clock for SDRAM 0 mask 1 pass 13 R W 0x0 Gating AHB Clock for NAND 0 mask 1 pass 12 R W 0x0 Gating AHB Clock for NC 0 mask 1 pass 11 R W 0x0 Gating AHB Clock for SD MMC3 0 mask 1 pass 10 R W 0x0 Gating AHB Clock for SD MMC2 0 mask 1 pass 9 R W 0x0 Gating AHB Clock for SD MMC1 0 mask 1 pass 8 R W 0x0 Gating AHB Clock for SD MMCO 0 mask 1 pass 7 R W 0x0 Gating AHB Clock for BIST 0 mask 1 pass 6 R W 0x0 Gating AHB Clock for DMA 0 mask 1 pass 5 R W 0x0 Gating AHB Clock for SS 0 mask 1 pass 4 3 R W 0x0 Gating AHB Clock for USB EHCII 0 mask 1 pass 2 1 R W 0x0 Gating AHB Clock for USB EHCIO 0 mask 1 pass 0 R W 0x0 Gating AHB Clock for USBO 0 mask 1 pass 6 4 17 AHB Module Clock Gating Register 1 Default 0x00000000 Offset 0x64 Register Name AHB_GATING_REG1 Bit Read Default Description Write Hex 31 21 20 R W 0x0 Gating AHB Clock for Mali 400 0 mask 1 pass 19 18 R W 0x0 Gating AHB Clock for MP 0 mask 1 pass 17 16 15 R W 0x0 Gating AHB Clock for DE FE1 0 mask 1 pass A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 2012 04 09 48 Ou Allwinner Technology CO Ltd A10 14 R W 0x0 Gating AHB Clock for DE FEO 0 mask 1 pass 13 R W 0x0 Gating AHB Clock for DE BE1 0 mask 1 pass 12 R W 0x0 Gating AH
146. 0 TCONO LVDS REG PLRO 21 R W 0 TCONO LVDS REG PLROC 20 17 R W 0 TCONO LVDS REG EN DRVO 16 R W 0 TCONO LVDS REG EN DRV0C 15 14 11 R W 0 TCONO LVDS REG PREN DRVI 10 R W 0 TCONO LVDS REG PREN DRVIC 9 6 R W 0 TCONO0 LVDS REG PLRI1 5 R W 0 TCONO0 LVDS REG PLRI1C 4 1 R W 0 TCONO LVDS REG EN DRVI 0 R W 0 TCONO LVDS REG EN DRVIC 33 4 39 TCONI fill data control register Offset 0x300 Register Name TCON1 FILL CTL REG Bit Read Default Description Write Hex 31 R W 0 TCONI Fill En 0 bypass 1 enable 30 0 33 4 40 TCONI fill data begin register Offset 0x304 Register Name TCON1 FILL BEGO REG Bit Read Default Description Write Hex 31 24 23 0 R W 0 Fill Begin A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 420 2012 04 09 Ou Allwinner Technology CO Ltd A10 33 4 44 TCONI fill data end register Offset 0x308 Register Name TCON1 FILL ENDO REG Bit Read Default Description Write Hex 31 24 23 0 R W 0 Fill End 33 4 42 TCONI fill data value register Offset 0x30C Register Name TCON1 FILL DATAO REG Bit Read Default Description Write Hex 31 24 23 0 R W 0 Fill Value 33 4 43 TCONI fill data begin register Offset 0x310 Register Name TCON1 FILL BEG1 REG Bit Read Default Description Write Hex 31
147. 00000 eese nnns 47 6 4 16 AHB Module Clock Gating Register O Default 0x00000000 eee 47 6 4 17 AHB Module Clock Gating Register 1 Default 0x00000000 eee 48 6 4 18 APBO Module Clock Gating Default 0x00000000 eese 49 6 4 19 APBI Module Clock Gating Default 0x00000000 cessere 50 6 4 20 NAND Clock Default 0x00000000 s sesssesesesesseeeseeeee eene enne enne enne neret 51 6 4 21 SD MMC 0 Clock Default 0x00000000 cessent nnne rennen 51 6 4 22 SD MMC 1 Clock Default 0x00000000 eese eene neret 52 6 4 23 SD MMC 2 Clock Default 0x00000000 eese eene nnne nnne nnne 53 6 4 24 SD MMC 3 Clock Default 0x00000000 cesses nennen neret nhe eene 53 6 425 IS Clock Default 0x00000000 5 1 retener eee n tu eo Lebe erant ies ene s erano eb eren tura eed 54 6 4 26 SS Clock Default 0x00000000 esses nennen nennen enne nnne nnne nnn rennen nnn 55 6 4 27 SPIO Clock Default 0x00000000 essen eene nennen enne entente 55 6 4 28 SPIL Clock Default 0x00000000 essen enne enne enne nennen enne 56 6 4 29 SPI Clock Default 0x00000000 s eeeseessseseseeeeseeeeee eene nennen enne enne nne 57 6 4 30 IR 0 Clock Default 0x00000000 ressent nnne nnne nnne nen ens 57 6 4 31 IR 1 Clock Default 0x
148. 00000000 eese enne enne nenne nennen nnn 58 6 4 32 IIS Clock Default 0x00000000 cesses enne nennen enne rennen enne 59 6 4 33 AC97 Clock Default 0x00030000 AA 59 6 4 34 Keypad Clock Default 0x0000001F seen nennen nnne trennen 60 6 4 35 NC Clock Default 0x00000000 cesses eene nennen nnne nets tnnt nnne 60 6 4 36 USB Clock Default 0x00000000 cesses eene 61 6 4 37 SPI3 Clock Default 0x00000000 eese eene enne nnne rennen 61 6 4 38 DRAM CLK Default 0x00000000 cesses nennen nnne nennen nente eterne ens 62 6 4 39 DE BE 0 Clock Default 0x00000000 eese nennen nnne nnne nentes 63 6 4 40 DE BE 1 Clock Default 0x00000000 esses enne enne enn enne 64 6 4 41 DE FE 0 Clock Default 0x00000000 essen eene enne 64 6 4 42 DE FE 1 Clock Default 0x00000000 sese eene enne nnne enne 65 6 4 43 DE MP Clock Default 0x00000000 esee enne enne nnne enne 66 6 4 4 LCD 0 CHO Clock Default 0x00000000 cesses nennen nennen nennen 66 6 4 45 LCD 1 CHO Clock Default 0x00000000 eese nnne 67 6 4 46 CSIT ISP Default 0x00000000 s eesseessseseseeeeseeeee eene nnne enne nnne nnne nnne ennnn nnn 67 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 5 2012 04 09 N Allwinner
149. 0140 CPU configuration register 10 3 Timer Programmable Register 10 3 1 Timer IRQ Enable Register Default 0x00000000 Offset 0x00 Register Name TMR IRQ EN REG Bit Read Default Write Hex Description A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 86 2012 04 09 Ou Allwinner Technology CO Ltd A10 31 9 8 R W 0x0 WDOG IRQ EN Watchdog Interrupt Enable 0 No effect 1 watchdog Interval Value reached interrupt enable 7 6 R W 0x0 TMR5_IRQ_EN Timer 5 Interrupt Enable 0 No effect 1 Timer 5 Interval Value reached interrupt enable R W 0x0 TMR4_IRQ_EN Timer 4 Interrupt Enable 0 No effect 1 Timer 4 Interval Value reached interrupt enable R W 0x0 TMR3_IRQ_EN Timer 3 Interrupt Enable 0 No effect 1 Timer 3 Interval Value reached interrupt enable R W 0x0 TMR2_IRQ_EN Timer 2 Interrupt Enable 0 No effect 1 Timer 2 Interval Value reached interrupt enable R W 0x0 TMR1_IRQ_EN Timer 1 Interrupt Enable 0 No effect 1 Timer 1 Interval Value reached interrupt enable R W 0x0 TMRO IRQ EN Timer 0 Interrupt Enable 0 No effect 1 Timer 0 Interval Value reached interrupt enable 10 3 2 Timer IRQ Status Register Default 0x00000000 Offset 0x04 Register Name TMR IRQ STA REG
150. 01C2 83FF 1K UART 1 0x01C2 8400 0x01C2 87FF IK UART 2 0x01C2 8800 0x01C2 8BFF 1K UART 3 0x01C2 8C00 0x01C2 8FFF IK UART 4 0x01C2 9000 0x01C2 93FF IK UART 5 0x01C2 9400 0x01C2 97FF IK UART 6 0x01C2 9800 0x01C2 9BFF IK UART 7 0x01C2 9C00 0x01C2 9FFF IK PS2 0 0x01C2 A000 0x01C2 A3FF IK PS2 1 0x01C2 A400 0x01C2 A7FF IK TWIO 0x01C2 ACO0 0x01C2 AFFF IK TWI I 0x01C2 B000 0x01C2 B3FF IK TWI2 0x01C2 B400 0x01C2 B7FF 1K CAN 0x01C2 BC00 0x01C2 BFFF IK SCR 0x01C2 C400 0x01C2 C7FF 1K Reserved 64K Mali400 0x01C4 0000 0x01C4 FFFF 64K SRAM C 0x01D0 0000 0x01 DF FFFF Module sram DE_FEO 0x01E0 0000 0x01E1 FFFF 128K DE FEI 0x01E2 0000 0x01E3 FFFF 128K DE_BEO 0x01E6 0000 0x01E7 FFFF 128K DE BEI 0x01E4 0000 0x01E5 FFFF 128K MP 0x01E8 0000 0x01E9 FFFF 128K AVG 0x01EA 0000 0x01EB FFFF 128K A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 2012 04 09 Ou wy Allwinner Technology CO Ltd A10 Reserved 64K DDR II DDR III 0x4000 0000 0xBFFF FFFF 2G BROM OxFFFF 0000 0xFFFF 7FFF 32K A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 31 2012 04 09 Ou Allwinner Technology CO Ltd A10 4 Boot Mode 4 1 Overview With on chip 32KB ROM A10 is providing flexible boot loading options in default sequence of SD Card0 NAND FLASH SD Card2 and SPI NOR FLASH An external Boot Select Pin
151. 08 07 06 05 04 03 02 01 00 PS 1xxx the R component is swapped with B component A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 2012 04 09 491 Ou Allwinner Technology CO Ltd A10 16 bpp interleaved YUV422 mode PS xx00 xx11 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VO YI UO YO 15 14 13 12 11 10 09 08 07 06 05 04 03 02 OI PS xx01 xx10 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 YI VO YO UO 15 14 13 12 11 10 09 08 07 06 05 04 03 02 0l 16 bpp U8V8 mode PS xxxx Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 V1 Ul VO UO 15 14 13 12 11 10 0 08 07 06 05 04 03 02 OI 32 bpp ARGB or AYUV mode PS xx00 xx01 Bit ai 30 29 28 27 96 25 24 23 2 21 20 19 18 17 A R Y G U B V 15 14 13 12 11 10 09 08 07 06 05 04 03 02 OI PS xx10 xx11 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 B V G U R Y A 15 14 13 12 11 10 09 08 07 06 05 04 03 02 0l PS 1xxx the R component is swapped with B component Output data pixel sequence 32bpp A8R8G8B8 or interleaved AYUV8888 16bpp A4R4G4B4 16bpp AIR5G5B5 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 492 2012 04 09 Ou M Allwinner Technology CO Ltd A10 16bpp R5G6B5 16bpp interleaved YUV422 Planar YUV4
152. 0x0 CLK_SRC_SEL Clock Source Select 00 PLL3 01 PLL7 10 PLL5 11 23 18 17 16 15 4 3 0 R W 0x0 CLK_DIV_RATIO_M Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 16 6 4 42 DE FE 1 Clock Default 0x00000000 Offset 0x110 Register Name FE1_CLK_REG Bit Read Default Description Write Hex 31 R W 0x0 SCLK GATING Gating Special Clock 0 Clock is OFF 1 Clock is ON This special clock Clock Source Divider M 30 R W 0x0 FE1_RST DE FE1 Reset 0 reset valid 1 reset invalid 29 26 25 24 R W 0x0 CLK_SRC_SEL Clock Source Select 00 PLL3 01 PLL7 10 PLL5 11 23 18 17 16 15 4 3 0 R W 0x0 CLK_DIV_RATIO_M Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 16 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 65 2012 04 09 Ou Allwinner Technology CO Ltd A10 6 4 43 DE MP Clock Default 0x00000000 Offset 0x114 Register Name MP_CLK_REG Bit Read Default Description Write Hex 31 R W 0x0 SCLK GATING Gating Special Clock 0 Clock is OFF 1 Clock is ON This special clock Clock Source Divider M 30 R W 0x0 MP RST DE MP Reset 0 reset valid 1 reset invalid 29 26 25 24 R W 0x0 CLK SRC
153. 0x0 IRQ 1 Priority Set priority level for IRQ bit 1 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 121 2012 04 09 Ou Allwinner Technology CO Ltd A10 Offset 0x80 Register Name INTC_PRIO_REGO LevelO 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority 1 0 Programs the priority level for all sources except FIQ source source 0 The priority level can be between O lowest and 7 highest 11 4 27 Interrupt Source Priority 1 Register Default 0x00000000 Offset 0x84 Register Name INTC_PRIO_REG1 Bit Read Default Description Write Hex 31 30 R W 0x0 IRQ 31 Priority Set priority level for IRQ bit 31 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 Ox1 level 2 Level3 Ox1 level 3 highest priority 29 28 R W 0x0 IRQ 30 Priority Set priority level for IRQ bit 30 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 Ox1 level 2 Level3 0x1 level 3 highest priority 27 26 R W 0x0 IRQ 29 Priority Set priority level for IRQ bit 29 Level0 0x0 level 0 lowest priority Levell 0x1 level 1 Level2 Ox1 level 2 Level3 0x1 level 3 highest priority 25 24 R W 0x0 IRQ 28 Priority Set priority level for IRQ bit 28 Level0 0x0 level 0 lowest priority Levell 0x1 level 1 Level2 Ox1 level 2 Level3 Ox1 leve
154. 1 Level0 0x0 level 0 lowest priority Levell 0x1 level 1 Level2 Ox1 level 2 Level3 0x1 level 3 highest priority 9 8 R W 0x0 IRQ 20 Priority Set priority level for IRQ bit 20 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 123 2012 04 09 Ou Allwinner Technology CO Ltd Offset 0x84 Register Name INTC_PRIO_REG1 A10 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority 7 6 R W 0x0 IRQ 19 Priority Set priority level for IRQ bit 19 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority 5 4 R W 0x0 IRQ 18 Priority Set priority level for IRQ bit 18 Level0 0x0 level 0 lowest priority Levell 0x1 level 1 Level2 Ox1 level 2 Level3 Ox1 level 3 highest priority 3 2 R W 0x0 IRQ17_PRIO IRQ 17 Priority Set priority level for IRQ bit 17 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority 1 0 R W 0x0 IRQ16_PRIO IRQ 16 Priority Set priority level for IRQ bit 16 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 Ox1 level 2 Level3 Ox1 level 3 highest priority 11 4 28 Interrupt Source Priority 2 Register Default 0x00000000 Offse
155. 1 Reserved 27 Reserved PD6_SELECT 000 Input 001 Output 010 LCDO_D6 011 LVDSO_VPC 100 Reserved 101 Reserved 26 24 R W 0 110 Reserved 111 Reserved 23 PD5_SELECT 000 Input 001 Output 010 LCDO D5 011 LVDSO VN2 100 Reserved 101 Reserved 22 20 R W 0 110 Reserved 111 Reserved 19 PD4 SELECT 000 Input 001 Output 010 LCDO D4 011 LVDSO VP2 100 Reserved 101 Reserved 18 16 R W 0 110 Reserved 111 Reserved 15 PD3 SELECT 000 Input 001 Output 010 LCDO_D3 011 LVDSO VNI 100 Reserved 101 Reserved 14 12 R W 0 110 Reserved 111 Reserved 11 PD2 SELECT 000 Input 001 Output 010 LCDO_D2 011 LVDSO VPI 10 8 R W 0 100 Reserved 101 Reserved A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 304 2012 04 09 Ou Allwinner Technology CO Ltd A10 110 Reserved 111 Reserved 7 PD1 SELECT 000 Input 001 Output 010 LCDO DI 011 LVDSO_VNO 100 Reserved 101 Reserved 6 4 R W 0 110 Reserved 111 Reserved PDO0 SELECT 000 Input 001 Output 010 LCDO DO 011 LVDSO VPO 100 Reserved 101 Reserved 2 0 R W 0 110 Reserved 111 Reserved 30 3 29 PD Configure Register 1 Register Name PD CFG1 Offset 0x70 Default Value 0x0000 0000 Bit Read Write Default Description 31 PD15 SELECT 000 Input 001 Output 010 LCDO_D15 100 Reserved 011 LVDS1_VN2 101 Reserved
156. 1 3 phase offset 10 used DCLK2 2 3 phase offset 11 reserved oT R W 103 Inv 0 not invert 1 invert 26 R W 102 Inv 0 not invert 1 invert 25 R W IOL Inv 0 not invert 1 invert 24 R W 100 Inv 0 not invert 1 invert 23 0 R W Data Inv TCONO output port D 23 0 polarity control with independent bit A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 411 2012 04 09 Ou Allwinner Technology CO Ltd A10 control Os normal polarity Is invert the specify output Offset 0x08C Register Name TCONO IO TRI REG Bit Read Default Description Write Hex 31 28 27 R W 1 103 Output Tri En 1 disable 0 enable 26 R W 1 IO2 Output Tri En 1 disable 0 enable 25 R W 1 IO1 Output Tri En 1 disable 0 enable 24 R W 1 100 Output Tri En 1 disable 0 enable 23 0 R W OxFFFF Data Output Tri En FF TCONO output port D 23 0 output enable with independent bit control 1s disable Os enable 33 4 25 TCONI control register Offset 0x090 Register Name TCON1_CTL_REG Bit Read Default Description Write Hex 31 R W 0 TCONI1 En 0 disable 1 enable 30 21 20 R W 0 Interlace En O disable enable 19 9 8 4 R W 0 Start Delay This is for DE1 and DEZ 3 2 A10 User Manual V1 20 Copyright
157. 10 XCH Exchange Burst In master mode it is used to start to SPI burst 0 Idle 1 Initiates exchange After finishing the SPI bursts transfer specified by BC this bit is cleared to zero by SPI Controller RF_RST RXFIFO Reset Write 1 to reset the control portion of the receiver FIFO and treats the FIFO as empty It is self clearing It is not necessary to clear this bit TF RST TXFIFO Reset Write 1 to reset the control portion of the transmit FIFO and treats the FIFO as empty It is self clearing It is not necessary to clear this bit SSCTL In master mode this bit selects the output wave form for the SPI SSx signal 0 SPI SSx remains asserted between SPI bursts 1 Negate SPI SSx between SPI bursts LMTF LSB MSB Transfer First select 0 MSB first 1 LSB first DMAMC SPI DMA Mode Control 0 Normal DMA mode 1 Dedicate DMA mode R W SSPOL SPI Chip Select Signal Polarity Control 0 Active high polarity 0 Idle 1 Active low polarity 1 Idle A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 167 2012 04 09 Ou Allwinner Technology CO Ltd A10 POL SPI Clock Polarity Control 0 Active high polarity 0 Idle 3 R W 1 1 Active low polarity 1 Idle PHA SPI Clock Data Phase Control 0 Phase 0 Leading edge for sample data 2 R W 1 1 Phase 1 Leading edge for setup data MODE SPI
158. 10 100 Reserved 101 Reserved 110 Reserved 111 Reserved 7 PC17 SELECT 000 Input 001 Output 010 NCE2 O1 1 Reserved 100 Reserved 101 Reserved 6 4 R W 0 110 Reserved 111 Reserved PC16_SELECT 000 Input 001 Output 010 NWP 011 Reserved 100 Reserved 101 Reserved 2 0 R W 0 110 Reserved 111 Reserved 30 3 22 PC Configure Register 3 Register Name PC_CFG3 Offset 0x54 Default Value 0x0000_0000 Bit Read Write Default Description 31 4 3 PC24_SELECT 000 Input 001 Output 010 NDQS 011 Reserved 100 Reserved 101 Reserved 2 0 R W 0 110 Reserved 111 Reserved 30 3 23 PC Data Register Register Name PC_DAT Offset 0x58 Default Value 0x0000_0000 Bit Read Write Default Description 31 24 PC_DAT If the port is configured as input the corresponding bit is the pin state If the port is configured as output the pin state is the same as the corresponding bit The read bit value is the value setup by software If the port is configured as functional pin the undefined 23 0 R W 0 value will be read A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 2012 04 09 302 Ou Allwinner Technology CO Ltd 30 3 24 PC Multi Driving Register 0 Register Name PC DRVO Offset 0x5C Default Value 0x5555 5555 Bit Read Write Default Description PC DRV PC n Multi Driving SELECT n 0 15 21 1 21 00 Level 0 01 Level 1
159. 101 Reserved 14 12 R W 0 110 STANBYWFI 111 Reserved 11 PB2 SELECT 000 Input 001 Output 010 PWMO 011 Reserved 10 8 R W 0 100 Reserved 101 Reserved A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 293 2012 04 09 Ou Allwinner Technology CO Ltd A10 110 Reserved 111 Reserved 7 PB1_SELECT 000 Input 001 Output 010 TWIO SDA 011 Reserved 100 Reserved 101 Reserved 6 4 R W 0 110 Reserved 111 Reserved PBO SELECT 000 Input 001 Output 010 TWIO SCK 011 Reserved 100 Reserved 101 Reserved 2 0 R W 0 110 Reserved 111 Reserved 30 3 11 PB Configure Register 1 Register Name PB CFG1 Offset 0x28 Default Value 0x0000 0000 Bit Read Write Default Description 31 PB15_SELECT 000 Input 001 Output 010 SPR CLK 011 JTAG_CKO 100 Reserved 101 Reserved 30 28 R W 0 110 Reserved 111 Reserved 27 PB14_SELECT 000 Input 001 Output 010 SPR CSO 011 JTAG_MSO 100 Reserved 101 Reserved 26 24 R W 0 110 Reserved 111 Reserved 23 PB13_SELECT 000 Input 001 Output 010 SPI2_CS1 011 Reserved 100 Reserved 101 Reserved 22 20 R W 0 110 Reserved 111 Reserved 19 PB12_SELECT 000 Input 001 Output 010 I2S_DI 011 AC97_DI 18 16 R W 0 100 Reserved 101 Reserved A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Ri
160. 11 23 18 17 16 R W 0x0 CLK_DIV_RATIO_N Clock pre divide ratio n The select clock source is pre divided by 2 n The divider is 1 2 4 8 15 4 3 0 R W 0x0 CLK_DIV_RATIO_M Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 16 6 4 22 SD MMC 1 Clock Default 0x00000000 Offset 0x8C Register Name SD1_CLK_REG Bit Read Default Description Write Hex 31 R W 0x0 SCLK_GATING Gating Special Clock Max Clock 200MHz 0 Clock is OFF 1 Clock is ON This special clock Clock Source Divider N Divider M 30 26 25 24 R W 0x0 CLK_SRC_SEL Clock Source Select 00 OSC24M 01 PLL6 10 PLLS 11 23 18 17 16 R W 0x0 CLK_DIV_RATIO_N Clock pre divide ratio n The select clock source is pre divided by 2 n The divider is 1 2 4 8 15 4 3 0 R W 0x0 CLK_DIV_RATIO_M Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 52 2012 04 09 Ou Allwinner Technology CO Ltd A10 to 16 6 4 23 SD MMC 2 Clock Default 0x00000000 Offset 0x90 Register Name SD2_CLK_REG Bit Read Default Description Write Hex 31 R W 0x0 SCLK_GATING Gating Special Clock Max Clock 200MHz 0 Clock is OFF 1 Clock is ON This special clock Clo
161. 110 EINT31 111 Reserved 11 PI18 SELECT 000 Input 001 Output 010 SPI1_MOSI 011 UART2 TX 100 Reserved 101 Reserved 10 8 R W 0 110 EINT30 111 Reserved 7 PI17 SELECT 000 Input 001 Output 010 SPI1 CLK 011 UART2 CTS 100 Reserved 101 Reserved 6 4 R W 0 110 EINT29 111 Reserved PI16 SELECT 000 Input 001 Output 010 SPI1_CSO 011 UART2 RTS 100 Reserved 101 Reserved 2 0 R W 0 110 EINT28 111 Reserved 30 3 76 PI Configure Register 3 Offset 0x12C Register Name PI CFG3 Default Value 0x0000 0000 Bit Read Write Default Description 31 0 30 3 77 PI Data Register Offset 0x130 Register Name PI DAT Default Value 0x0000 0000 Bit Read Write Default Description 31 13 12 0 R W 0 PI DAT A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 2012 04 09 329 Ou Allwinner Technology CO Ltd A10 If the port is configured as input the corresponding bit is the pin state If the port is configured as output the pin state is the same as the corresponding bit The read bit value is the value setup by software If the port is configured as functional pin the undefined value will be read 30 3 78 PI Multi Driving Register 0 Register Name PI DRVO Offset 0x134 Default Value 0x0155 5555 Bit Read Write Default Description 31 26
162. 124 Register Name TVE 124 REG Bit Read Default Description Write Hex 31 12 11 0 R W SAO Active Line A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 438 2012 04 09 Ou Allwinner Technology CO Ltd A10 Specify the width of the video line in encoder clock cycles 12 bit unsigned multiple of 4 integer Allowed range is 0 to 4092 Default value is 1440 34 4 21 TV Encoder Video Chroma BW and CompGain Register Offset 0x128 Register Name TVE_128_REG Bit Read Default Description Write Hex 31 18 17 16 R W 00 Chroma_BW Chroma filter bandwidth selection This bit specifies whether the bandwidth of the chroma filter is 0 Narrow width 0 7MHz 1 Wide width 1 2MHz 2 Extra width 1 8MHz 3 Ultra width 2 5MHz Default is 0 6MHz value 0 15 2 1 0 R W 0 Comp_Ch_Gain Chroma gain selection for the composite video signal These bits specify the gain of the chroma signal for composing with the luma signal to generate the composite video signal 100 B 00 75 B 11 50 B 10 or 25 B 01 34 4 22 TV Encoder Register Offset 0x12C Register Name TVE_12C_REG Bit Read Default Description Write Hex 31 9 8 R W 0 Notch_Width Luma notch filter width selection This bit selects the luma notch filter which is a band reject filter width 0 Narrow 1
163. 15 mau 19 16 R W RO Filter right shifter rO ranges from 0 15 15 08 R W C9 Filter coeff9 A signed number ranging from 128 127 07 00 R W C8 Filter coeff8 A signed number ranging from 128 127 31 6 86 ISPAWBE window number register Offset Address 0X49C Register Name ISP FE AWBE NUM REG Bit Read Default Description Write Hex 11 08 R W 1 AWBE VER NUM AE AWB vertical window number VWN ranges from 1 8 03 00 R W 1 AWBE_HOR_NUM AE AWB horizontal window number HWN ranges from 1 8 31 6 87 ISP AWBE window size register Offset Address 0X4A0 Register Name ISP_FE_AWBE_SIZE_REG Read Default Description Write Hex mar Tor 24 16 R W AWBE_HEIGHT AE AWB window height H H ranges from 0 256 The actual window height is 2 H 08 00 R W 4 AWBE WIDTH AE AWB window width W W ranges from 0 256 The actual window width is 2 W 31 6 88 ISPAWBE window start register Offset Address 0X4A4 Register Name ISP FE AWBE POS REG A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 376 2012 04 09 Allwinner Technology CO Ltd A10 27 16 R W AWBE VER START The start vertical position for AE AWB window Ranges from 0 to 4095 11 00 R W AWBE HOR START The start horizontal position for AE AWB window Ranges from 0 to 4095 31 6 89 ISPAWBE configuration register Offset Address 0OX4A8 Register Name ISP FE AWBE CFG REG Read Default De
164. 16 or 32bpp and the work mode is palette mode only the low 8 bits input data is valid 7 4 R W IDMA ROTMIRCTL Rotation and mirroring control O normal 1 X 2 Y 3 XY A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 465 2012 04 09 Ou Allwinner Technology CO Ltd A10 4 A 5 AX 6 AY T AXY Other reserved IDMA_ALPHACTL Alpha control 0 Ignore Output alpha value pixels alpha if no pixel alpha the alpha value equal Oxff 1 Globe alpha enable Ignore pixel alpha value Output alpha value globe alpha value 2 Globe alpha mix pixel alpha Output alpha value globe alpha value pixels alpha value 3 Reserved Note the output alpha value here means the input alpha value of the ALU following the DMA controller IDMA_WORKMOD Work mode selection 0 normal mode non palette mode 1 palette mode IDMA_EN Input DMA enable control O disable input DMA channel the respective fill color value will stead of the input data enable 35 5 10 Input DMA fill color register Offset Register Name MP IDMAFILLCOLOR REG iDMA0 0x60 iDMA1 0x64 iDMA2 0x68 iDMA3 0x6C Bit Read W Default Description rite Hex 31 24 R W IDMA_FCALPHA Alpha A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 466 2012 04 09 Allwinner Technology CO Ltd A10 IDMA FCRED wt Red 15 8 R W IDMA FCGREEN Green 7 0 R W IDMA_FCBLUE B
165. 2 35 5 34 CSCO 1 EE 483 35 5 35 CSCO U R coefficient reglsler cuoi te rrt rr rre EE vn even 483 35 5 36 CSCO 1 U R constant register siaina innana nen en enne en enne nnns 483 35 5 37 CSCO T MIB coefficient register teer re te eg aeree PEE e red EUR e 484 35 5 38 CSCO 1 E e 484 39 59 39 CSC2 ee 484 35 5 40 CSC2 Y G constant register E 485 35 5 41 CSC2 UR coefficient fegister oett retten ir teer ee vedete eer et deis 485 35 5 42 CSC2 RE 485 35 5 43 Ee 486 35 5 44 CSC2 V B constant register eost etr tr teen ao ee HR hee Rhe Fh Eaa 486 35 5 45 Scaling horizontal filtering coefficient RAM block 486 35 5 46 Scaling vertical filtering coefficient RAM block 487 SRM fMi T 487 KOU n 494 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 23 2012 04 09 Ou Allwinner Technology CO Ltd A10 1 Introduction With ARM Cortex A8 core A10 will drive SoC into a brand new era of connected Smart HD which can enhance the application of connected HD SOC as well as user experiences of consumer electronics like multimedia products Due to its outstanding connected HD video performance and cost efficiency the highly integrated A10 is target at cool HD pad which can bring end users better experiences of surfing watching gaming and reading The A10 is dedicated to furthering the development of connected HD video CODEC application and
166. 2 Allwinner Technology All Rights Reserved 384 2012 04 09 Ou N Allwinner Technology CO Ltd A10 32 3 CSI data ports Bayer YCbCr YUV Interlaced Pass through FIFOO Red pixel data Y pixel data All field 1 pixel All pixel data data FIFO1 Green pixel data Cb U pixel All field 2 pixel data data FIFO2 Blue pixel data Cr V pixel data 32 4 Timing 32 4 1 CSI timing vsync n frame n 1 frame hsync 1 active data first line data t 4 lastline data Vref positive Href positive Figure32 2 vsync 5 nframe f n 1 frame e r4 m n m oe T m lines 14 5 m erte vertical size setting Figure32 3 ng n clocks m clocks gt hsyne LI t D m active data 4 C OC OC OCOGPDCOCOCOCOCO 3 ive in rising sm E tat e e E EE horizontal start clock n horizontal active clocks length m horizontal size setting and pixel clock timing Href positive Figure32 4 32 5 CSII Registers List Module Name Base Address CSI1 0x01C1D000 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 385 2012 04 09 Allwinner Technology CO Ltd A10 Register Name Offset Register name CSI1 EN REG 0X000 CSI enable register CSI1 CFG REG 0X004 CSI config
167. 2 FIFO 0 output buffer A address register CSIO C2 FO BUFB REG 0X214 CSI Channel 2 FIFO 0 output buffer B address register CSIO C2 F1 BUFA REG 0X218 CSI Channel 2 FIFO 1 output buffer A address register CSIO C2 FI BUFB REG 0X21C CSI Channel 2 FIFO 1 output buffer B address register CSIO C2 F2 BUFA REG 0X220 CSI Channel 2 FIFO 2 output buffer A address register CSIO C2 F2 BUFB REG 0X224 CSI Channel 2 FIFO 2 output buffer B address register CSIO C2 BUF CTL REG 0X228 CSI Channel 2 output buffer control register CSIO C2 BUF STA REG 0X22C CSI Channel 2 status register CSIO C2 INT EN REG 0X230 CSI Channel 2 interrupt enable register CSIO C2 INT STA REG 0X234 CSI Channel 2 interrupt status register CSIO C2 HSIZE REG 0X240 CSI Channel 2 horizontal size register CSIO C2 VSIZE REG 0X244 CSI Channel 2 vertical size register CSIO C2 BUF LEN REG 0X248 CSI Channel 2 line buffer length register CSIO C3 F0 BUFA REG 0X310 CSI Channel 3 FIFO 0 output buffer A address register CSIO C3 F0 BUFB REG 0X314 CSI Channel 3 FIFO 0 output buffer B address register CSIO C3 F1 BUFA REG 0X318 CSI Channel 3 FIFO 1 output buffer A address register CSIO C3 F1 BUFB REG 0X31C CSI Channel 3 FIFO 1 output buffer B address register CSIO C3 F2 BUFA REG 0X320 CSI Channel 3 FIFO 2 output buffer A address register CSIO C3 F2 BUER REG 0X324 CSI Channel 3 FIFO 2 output buffer B address register CSIO C3 BUF CTL REG 0X328 CSI Channel 3 output buffer control register
168. 2 FIFO 1 output buffer B address register esee 356 31 6 35 CSI Channel 2 FIFO 2 output buffer A address register esee 357 31 6 36 CSI Channel 2 FIFO 2 output buffer B address register essen 357 31 6 37 CSI Channel 2 output buffer control register 0 eee cece cece ceeeeeeesecseeeeeeaeeaeeseseeseaeeas 357 31 6 38 CSI Channel 2 status register seen en enne enne nnne 358 31 6 39 CSI Channel 2 interrupt enable register eese 358 31 6 40 CSI Channel 2 interrupt status register rusnrnrrnrrvvnvnnrnrrnrnvnrnnrnennrrnvnrververnervvnrvesnesnrevvesnesnee 359 31 6 41 CSI Channel 2 horizontal size register essere 360 31 6 42 CSI Channel 2 vertical size register 0 eee ees ceeeeeseceeceeeesecseseeceeeesesseseeeeceaeeaeseeeeeeeas 360 31 6 43 CSI Channel 2 buffer length register sees 360 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 17 2012 04 09 Ou N Allwinner Technology CO Ltd A10 31 6 44 CSI Channel 3 FIFO 0 output buffer A address register esee 361 31 6 45 CSI Channel 3 FIFO 0 output buffer B address register eese 361 31 6 46 CSI Channel 3 FIFO 1 output buffer A address register eese 361 31 6 47 CSI Channel 3 FIFO 1 output buffer B address register eese 361 31 6 48 CSI Channel 3 FIFO 2 o
169. 22 UV combined 8bpp MONO 4bpp MONO 2bpp MONO Ibpp MONO Planar YUV420 UV combined Planar YUV411 UV combined The above 13 kinds of output format is same as respective input format PS Planar YUV422 Planar YUV420 Planar YUV411 The above 3 kinds of output format is same as input 8bpp format PS A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 493 2012 04 09 Ou Allwinner Technology CO Ltd A10 36 Declaration This A10 user manual is the original work and copyrighted property of Allwinner Technology Allwinner Reproduction in whole or in part must obtain the written approval of Allwinner and give clear acknowledgement to the copyright owner The information furnished by Allwinner is believed to be accurate and reliable Allwinner reserves the right to make changes in circuit design and or specifications at any time without notice Allwinner does not assume any responsibility and liability for its use Nor for any infringements of patents or other rights of the third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Allwinner This user manual neither states nor implies warranty of any kind including fitness for any particular application A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 494 2012 04 09
170. 285 29 2 S curity ID Register Last ete aeterna Eae Rb e e Fa REND Fa nhi eR opo EE ree 285 20 3 SID Register Description ett geesde dpt e ret eegene E TENERE UR NIEEERI EPA Pete EREE 285 29 3 1 TR el ROPISGE irte eee ite tt essere t been eee 285 20 3 2 SID Root Key 1 Register ugesi eene tr tico ente turi E e eoe Eee dee uo vingene 285 20 3 3 SID Root Key 2 Register eene treten reete Us nett ret een S ke Penh Hee tore nda 286 20 3 4 SID Root Key 3 Register iei e PEERS RIO PUO KE UUYEP XX FC ES SERIE UE SURE ERE N RE e eru EEN 286 30 On d OU 287 30 1 ee E 287 30 2 Port Register Let ee eege EENS EENS AE 287 30 3 P rt Register Description aee eter ceteri d epo a d re ey tO Eee ertet eer Hed 288 3031 PA Configure Register deeg epit eph t e et HD ERE EE da 288 30 3 2 PA EE 289 30 3 3 PA EE 291 30 34 PA Configure Register TE 291 3035 PA Data Registet EE 291 30 3 6 PA Multi Driving Register OU 292 30 3 7 PA Multi Driving Register 1 eene netten nnne eii iiaei seva 292 30 3 8 PA Pull Register O in isi eem RE RE NON SU FUERO Ee P UE Ee tx ort ERR 292 30 3 0 PA PUll Register 1 scene eerte ete er ret or p P EE I E IRE RR Rr EE 292 30 3 10 PB Configure Register E 293 30 3 11 PB Configure Register 1 ute e ETE eee eere PER Ed 294 30 3 12 PB Configure Register 2 aeien aoa EEEa ET S E a TEE 295 30 3 13 PB Conf oute Register E 296 30 3 14 PB Data Register vce i e rte tenete rr inet ende rre eere
171. 3 0 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 72 2012 04 09 Ou Allwinner Technology CO Ltd A10 6 4 54 AVS Clock Default 0x00000000 Offset 0x144 Register Name AVS_CLK_REG Bit Read Default Description Write Hex 31 R W 0x0 SCLK GATING Gating Special Clock 0 Clock is OFF 1 Clock is ON This special clock OSC24M 30 26 25 24 23 18 17 16 15 4 3 0 6 4 55 ACE Clock Default 0x00000000 Offset 0x148 Register Name ACE CLK REG Bit Read Default Description Write Hex 31 R W 0x0 SCLK GATING Gating Special Clock Max Clock 200MHz 0 Clock is OFF 1 Clock is ON This special clock Clock Source Divider M 30 25 24 R W 0x0 CLK SRC SEL Clock Source Select 0 PLLA 1 PLL5 23 17 16 R W 0x0 ACE RST ACE Reset 0 reset valid 1 reset invalid 15 4 3 0 R W 0x0 CLK DIV RATIO M Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 16 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 73 2012 04 09 Ou Allwinner Technology CO Ltd A10 6 4 56 LVDS Clock Default 0x00000000 Offset 0x14C Register Name LVDS CLK REG Bit Read Default Description Write Hex 31 1 0 R W 0x0 LV
172. 30 28 R W 0 110 Reserved 111 Reserved 27 PD14 SELECT 000 Input 001 Output 010 LCDO D14 100 Reserved 011 LVDS1 VP2 101 Reserved 26 24 R W 0 110 Reserved 111 Reserved 23 PD13 SELECT 000 Input 001 Output 010 LCDO D13 100 Reserved 011 LVDS1_VN1 101 Reserved 22 20 R W 0 110 Reserved 111 Reserved 19 PD12_SELECT 000 Input 001 Output 010 LCDO_D12 011 LVDSI VPI 18 16 R W 0 100 Reserved 101 Reserved A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 2012 04 09 305 Ou Allwinner Technology CO Ltd A10 110 Reserved 111 Reserved 15 PD11 SELECT 000 Input 001 Output 010 LCDO D11 011 LVDS1 VNO 100 Reserved 101 Reserved 14 12 R W 0 110 Reserved 111 Reserved 11 PD10 SELECT 000 Input 001 Output 010 LCDO D10 011 LVDS1_VPO 100 Reserved 101 Reserved 10 8 R W 0 110 Reserved 111 Reserved 7 PD9_SELECT 000 Input 001 Output 010 LCDO D9 011 LVDSO VM3 100 Reserved 101 Reserved 6 4 R W 0 110 Reserved 111 Reserved PD8 SELECT 000 Input 001 Output 010 LCDO D8 011 LVDSO_VP3 100 Reserved 101 Reserved 2 0 R W 0 110 Reserved 111 Reserved 30 3 30 PD Configure Register 2 Register Name PD CFG2 Offset 0x74 Default Value 0x0000 0000 Bit Read Write Default 31 PD23_SELECT 000 Input
173. 4 MP Status register MP_IDMAGLBCTL_REG 0x8 Input DMA globe control register MP_IDMA_H4ADD_REG OxC Input DMA start address high 4bits register MP IDMA L32ADD REG 0x10 Ox1C Input DMA start address low 32bits register MP IDMALINEWIDTH REG 0x20 0x2C Input DMA line width register MP IDMASIZE REG 0x30 0x3C Input DMA memory block size register MP IDMACOOR REG 0x40 0x4C Input DMA memory block coordinate control register MP_IDMASET_REG 0x50 0x5C Input DMA setting register MP IDMAFILLCOLOR REG 0x60 0x6C Input DMA fill color register MP CSCOCTL REG 0x74 Color space converter 0 control register MP CSCICTL REG 0x78 Color space converter 1 control register MP SCACTL REG 0x80 Scaler control register MP SCAOUTSIZE REG 0x84 Scaling output size register MP SCAHORFCT REG 0x88 Scaler horizontal scaling factor register MP SCAVERFCT REG Ox8C Scaler vertical scaling factor register MP_SCAHORPHASE_REG 0x90 Scaler horizontal start phase setting A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 2012 04 09 459 Ou Allwinner Technology CO Ltd A10 register MP_SCAVERPHASE_REG 0x94 Scaler vertical start phase setting register MP_ROPCTL_REG OxBO ROP control register MP ROPIDXOCTL REG OxB8 ROP channel 3 index 0 control table setting register MP ROPIDX1CTL REG OxBC ROP channel 3 index 1 control table
174. 5 04 03 02 01 00 4 bpp mode PS xx00 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P07 P06 P05 P04 P03 P02 PO1 POO 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PS xx01 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P06 P07 P04 P05 P02 P03 POO PO 15 14 13 12 11 10 09 08 07 06 05 04 03 02 O1 00 PS xx10 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PO1 POO P03 P02 P05 P04 P07 P06 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PS xx11 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 POO PO P02 P03 P04 POS P06 P07 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 8 bpp mode PS xx00 xx11 Bit A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 2012 04 09 489 Ou Allwinner Technology CO Ltd A10 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P3 P2 Pl PO 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PS xx01 xx10 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PO Pl P2 P3 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 16 bpp A4R4G4B4 mode PS 0x00 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Al RI G1 B1 AO RO GO BO 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PS 0x01 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 AO RO GO BO Al RI G1 B1 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PS 0x10 Bit 31 3
175. 5 1 Overview The SD3 0 controller can be configured either as a Secure Digital Multimedia Card controller which simultaneously supports Secure Digital memory SD Memo UHS 1 Card Secure Digital T O SDIO Multimedia Cards MMC eMMC Card and Consumer Electronics Advanced Transport Architecture CE ATA The SD3 0 controller includes the following features Supports Secure Digital memory protocol commands up to SD3 0 Supports Secure Digital I O protocol commands Supports Multimedia Card protocol commands up to MMC4 3 Supports CE ATA digital protocol commands Supports eMMC boot operation and alternative boot operation Supports UHS 1card voltage switching and DDR R W operation Supports Command Completion signal and interrupt to host processor and Command Completion Signal disable feature Supports one SD Verson1 0 to 3 0 or MMC Verson3 3 to 4 3 or CE ATA device Supports hardware CRC generation and error detection Supports programmable baud rate Supports host pull up control Supports SDIO interrupts in 1 bit and 4 bit modes Supports SDIO suspend and resume operation Supports SDIO read wait Supports block size of 1 to 65535 bytes Supports descriptor based internal DMA controller Internal 16x32 bit 64 bytes total FIFO for data transfer Support 3 3 V and 1 8V IO pad 15 2 SD3 0 Timing Diagram Please refer to relative Specifications as following B Physical Layer Specification Ver3 00 Final 2009 04 16 SDIO Specifi
176. 56 and applying some condition to tailor its duty cycle This yields a 48 KHz SYNC signal whose period defines an audio frame Data is transitioned on AC link on every rising edge of BIT_CLK and subsequently sampled by the receiving device on the receiving side of AC link on each immediately following falling edge of BIT_CLK 23 4 AC Link frame Format Slot 0 1 2 3 4 5 6 7 8 9 10 11 12 SYNC l CMD CMD PCM PCM LINE 1 PCM PCM PCM SDATA_OUT ADDR DATA L FRONTIR FRONTI CENTER L SURR R SURR Controller output Desen TPOML PCMR PCMC Ene nen ne SDATA IN STATUS STATUS Sou PCM LINE PCM LINE2 HSET 10 Codec output TAG ADDR DATA LEFT RIGHT apc Mic RSRVD RSRVD RSRVD Apc apc STATUS SLOTREQ 3 12 Figure 23 3 Bi directional AC link Frame with slot assignments The AC link output slots transmitted from the Controller are defined as follows Slot Name Description 0 SDATA OUT TAG MSBs indicate which slots contain valid data LSBs convey Codec ID 1 Control CMD ADDR write port Read write command bit plus 7 bit Codec register address 2 Control DATA write port 16 bit command register write data 3 4 PCM L amp R DAC playback 16 18 or 20 bit PCM data for Left and Right channels 5 Modem Line 1 DAC 16 bit modem data for modem Line 1 output 6 7 8 9 PCM Center Surround L amp R LFE 16 18 or 20 bit PCM data for Center Surround L amp R LFE channels 10 Modem Line 2 DAC 16 bit mod
177. 59 16 Scaler vertical scaling factor register iier ertet rre a ais 470 35 5 17 Scaler horizontal start phase setting register ssrrvrrvnnrnrrnrnvvnvvnrnrnnrnnvnrnervernervvnrnesnesneevnsvennee 470 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 22 2012 04 09 Ou N Allwinner Technology CO Ltd A10 35 5 18 Scaler vertical start phase setting register essen ener 471 35 5119 TROP control EE 471 35 5 20 ROP channel 3 index 0 control table setting register sese 473 35 5 21 ROP channel 3 index 1 control table setting register seen 474 35 5 22 Alpha Color key control register mu 5 2 c itte re P EIER ERE Eia 476 35 5 23 Color key min color register cien cie ter e E eidet 477 35 5 24 Color key max color register essent ener enne nnns 477 35 5 25 Fill color of ROP output setting register 2 cece ceeeeeeeseeaeceeceeeeaesseseseaeesesseseeseaeeas 478 35 5 26 Color space converter 2 control register eee 478 35 5 27 Output RE EN 478 35 35 28 Re 480 35 5 29 Output address high 4bits register eee essere 480 35 5 30 Output address low 32Dits register tere nite rrr E rea E a a 480 35 5 31 Output line WidlliTeplsle c oiii tete tiet Ge En ert e e redeas As eei 481 35 5 32 Output alpha control regteter eren enne etre 481 35 5 33 CSCO T Y G coefficient register et reet tenete ne teer eee eee uie 48
178. 6 X 7 8 Undefined PCM Long Frame SYNC Timing Diagram 8 bits Companded Sample Example Figure 22 5 PCM Long Frame SYNC Timing Diagram PCM_SYNC POM CLK SYN PCM OUT 1 2xX3X4X5X6 7X8 9 1X 11 1 X 13X 14x 1 X 1 PCM IN BIER 2 X34 V5 X6 X7 X8 X9 KICKIN TY XT TONE PCM Short Frame SYNC Timing Diagram 16 bits sample example Figure 22 6PCM Short Frame SYNC Timing Diagram 22 3 Digital Audio Interface Register List Module Name Base Address DA 0x01C22400 Register Name Offset Description DA CTL 0x00 Digital Audio Control Register DA FATO 0x04 Digital Audio Format Register 0 DA FATI 0x08 Digital Audio Format Register 1 DA TXFIFO Ox0C Digital Audio TX FIFO Register DA_RXFIFO 0x10 Digital Audio RX FIFO Register DA_FCTL 0x14 Digital Audio FIFO Control Register A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 220 2012 04 09 Ou Allwinner Technology CO Ltd A10 DA FSTA Ox18 Digital Audio FIFO Status Register DA_INT Ox1C Digital Audio Interrupt Control Register DA ISTA 0x20 Digital Audio Interrupt Status Register DA CLKD 0x24 Digital Audio Clock Divide Register DA TXCNT 0x28 Digital Audio RX Sample Counter Register DA RXCNT Ox2C Digital Audio TX Sample Counter Register DA_TXCHSEL 0x30 Digital Audio TX Channel Select Register DA_TXCHMAP 0x34 Digital Audio T
179. 7 RFL Receive FIFO Level This is indicates the number of data entries in the 6 0 R 0 receive FIFO 18 4 16 UART Halt TX Register Register Name UART_HALT Offset 0xA4 Default Value 0x0000_0000 Bit Read Write Default Description 31 6 SIR_RX_INVERT SIR Receiver Pulse Polarity Invert 0 Not invert receiver signal 5 R W 0 1 Invert receiver signal SIR_TX_INVERT SIR Transmit Pulse Polarity Invert 0 Not invert transmit pulse 4 R W 0 1 Invert transmit pulse 3 1 HALT_TX Halt TX This register is use to halt transmissions for testing so 0 R W 0 that the transmit FIFO can be filled by the master A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 196 2012 04 09 Ou Allwinner Technology CO Ltd A10 when FIFOs are implemented and enabled 0 Halt TX disabled 1 Halt TX enabled Note If FIFOs are not enabled the setting of the halt TX register has no effect on operation 18 5 UART Special Requirement 18 5 1 UART Pin List Port Name Width Direction Description UARTO TX 1 OUT UART Serial Bit output UARTO RX 1 IN UART Serial Bit input UARTI TX 1 OUT UART Serial Bit output UARTI RX 1 IN UART Serial Bit input UARTI RTS OUT UART Request To Send This active low output signal informs Modem that the UART is ready to send data UARTI1 CIS IN UART
180. 7 R W 0x0 TMRO_MODE TimerO mode 0 Continous mode When interval value reached the timer will not disable automatically 1 Single mode When interval value reached the timer will disable automatically 6 4 R W 0x0 TMRO_CLK_PRES Select the pre scale of timer 0 clock source 000 1 001 2 010 4 011 8 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 88 2012 04 09 Ou Allwinner Technology CO Ltd A10 100 16 101 32 110 64 111 128 3 2 R W Ox1 TMRO_CLK_SRC Timer 0 Clock Source 00 Low speed OSC 01 OSC24M 10 PLL6 6 11 R W 0x0 TMRO_RELOAD Timer 0 Reload 0 No effect 1 Reload timer 0 Interval value R W 0x0 TMRO_EN Timer O Enable 0 Stop Pause 1 Start If the timer is started it will reload the interval value to internal register and the current counter will count from interval value to 0 If the current counter does not reach the zero the timer enable bit is set to 0 the current value counter will pause At least wait for 2 Tcylces the start bit can be set to 1 In timer pause state the interval value register can be modified If the timer is started again and the Software hope the current value register to down count from the new interval value the reload bit and the enable bit should be set to 1 at the same time Note the time betw
181. 8 CSI Channel 1 FIFO 0 output buffer A address register sese 351 31 6 19 CSI Channel 1 FIFO 0 output buffer B address register eese 351 31 6 20 CSI Channel 1 FIFO 1 output buffer A address register eese 351 31 6 21 CSI Channel 1 FIFO 1 output buffer B address register sese 352 31 6 22 CSI Channel 1 FIFO 2 output buffer A address register essen 352 31 6 23 CSI Channel 1 FIFO 2 output buffer B address register eee 352 31 6 24 CSI Channel 1 output buffer control register sese 352 31 6 25 CSI Channel 1 status Teglster 4 erri eer ene rie ee dv etapa ri dE een 353 31 6 26 CSI Channel 1 interrupt enable register esses 353 31 6 27 CSI Channel 1 interrupt status register srnrnrrnrrvrnvnnnnrrnrrvvnrnnrnrrnrrvernennernrevvernesnasvrervesnennne 354 31 6 28 CSI Channel 1 horizontal size register esee enne 355 31 6 29 CSI Channel 1 vertical size Teglster ace een t e re t Eege degen 355 31 6 30 CSI Channel 1 buffer length register ener 356 31 6 31 CSI Channel 2 FIFO 0 output buffer A address register esse 356 31 6 32 CSI Channel 2 FIFO 0 output buffer B address register sese 356 31 6 33 CSI Channel 2 FIFO I output buffer A address register ssnrnrrnrrvrnrnnnnrrnrrvnnrnnnnrrvrervernennne 356 31 6 34 CSI Channel
182. 8 2 UART Timing Dia gratia E 179 18 3 UART Register E 179 18 4 UART Register DescriptioD oer e etm eer PO a a a a a ranet 180 18 41 gt UART Receiver Buffer Reeister e etre rti ab en eei 180 18 4 2 UART Transmit Holding Regteter AA 180 18 4 3 UART Divisor Latch Low Register 181 18 44 UART Divisor Latch High Register iiaia 181 18 4 5 UART Interrupt Enable Register uiii terere iier bep ee e erret 182 18 4 6 UART Interrupt Identity Register eerte 183 18 4 7 UART FIFO Control Register esses ntnne tnnt nent nnne nnne nn ennt 185 18 48 UART Line Control Register ter br mer rep Dr reor erro Ep Pes rd etate 186 18 49 UART Modem Control Register siinsesse suino iin nnne auei 188 18 4 10 UART Line Status Register esnaonornronnennennnvvnsnnsnnannnsvnvnnsnnanvnsvnsvnsnnavvnsvnvsnsvnnsvnvnnsnnenvnsvnsvnsen 189 18 4 11 UART Modem Status Register AAA 192 18 4 12 UART Scratch Register etenim et ER EO LO REED REG ERO TEE ROREM Re tb r dead 194 IK e EE 195 18 4 14 UART Transmit FIFO Level Register AAA 196 18 4 15 UART Receive FIFO Level Register 196 18 4 16 UART Halt TX Register cote rn rer tete n FER te esp degt 196 18 5 UART Special Requirement ener niaii e de ak En np Fono aea engen ken adv 197 185 1 VART Pin List uei teen tret eene ie rene etit nena e erae ee ri vere eise avl 197 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 10
183. 90 32 6 7 CSI Channel 0 FIFO 1 output buffer A address register esee 390 32 6 8 CSI Channel 0 FIFO 1 output buffer B address register srrrnrrvrrvrnvnnnnrrnrrvvnrnennrrvrevnernennne 391 32 6 9 CSI Channel 0 FIFO 2 output buffer A address register esses 391 32 6 10 CSI Channel 0 FIFO 2 output buffer B address register eese 391 32 6 11 CSI Channel 0 output buffer control register sess 391 32 6 12 CSI Channel EE 392 32 6 13 CSI Channel 0 interrupt enable register esses ene 393 32 6 14 CSI Channel 0 interrupt status register oo eee eee eee ceeceeeeseesececeeeeaessecseseaeeaesaeseeseaeegs 394 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 19 2012 04 09 Ou Allwinner Technology CO Ltd A10 32 6 15 CSI Channel 0 horizontal size register eee esses enne eene 394 32 6 16 CSI Channel 0 vertical size register sese rennen 394 32 6 17 CSI Channel 0 buffer length register ener 395 35 LCD TV Timing Controller eorr eene eene Eve eeu E NEUE RE eR YE NEES 396 33 12 OVerview PE 396 33 2 EE 396 33 3 LCD TV Timing Controller Register List 396 33 4 LCD TV Timing Controller registers definition essere eene 398 3341 TCON global control register ueniet en ret rri ere rU lb eres 398 33 4 2 TCON global interrupt registerO eese nenn
184. 96 31 6 60 ISP OBC Image Valid size register Offset Address 0X414 Register Name ISP_FE_OB_VALID_REG Read Default Description Write Hex mw Tor 28 16 R W OB VALID HEIGHT The height of sensor excluding optical black area Ranges from 0 to 4096 12 00 R W 500 OB_VALID_WIDTH The width of sensor excluding optical black area Ranges from 0 to 4096 31 6 61 ISP OBC Image Start register Offset Address 0X418 Register Name ISP FE OB START REG Bit Read Default Description Write Hex A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 367 2012 04 09 OW y ee CO Ltd A10 27 16 The start vertical position of valid image Ranges from 0 to 4095 nur 7 7 11 00 R W OB_HOR_START The start horizontal position of valid image Ranges from 0 to 4095 31 6 62 ISP OBC configuration register Offset Address 0X41C Register Name ISP_FE_OB_CFG_REG Read Default Description Write Hex Gap RS 13 12 R W VER_OBC_LEN Vertical OBC length L L 0 3 The actual value is 255 09 08 R W HOR_OBC_HEIGHT Horizontal OBC height N N 0 3 The actual value is 23 The height of window for horizontal OBC SR SE 06 04 R W HOR_OBC_WIDTH Horizontal OBC width M M 0 6 The actual value is a The width of window for horizontal OBC fixed value only horizontal only vertical sum of horizontal and vertical average of horizontal and ver
185. A CFG REG Bit Read Defa Write ult H ex Description 31 R W 0x0 DMA_LOADING DMA Loading If set to 1 DMA will start and load the DMA registers to the shadow registers The bit will hold on until the DMA finished It will be cleared automatically Set 0 to the bit will stop the corresponding DMA channel and reset its state machine 30 R 0x0 DMA_BSY_STA MA Busy Status DMA idle 1 DMA busy 29 R W 0x0 MA CONT MODE EN Disable 1 Enable 28 R W 0x0 MA_DEST_SEC MA Destination Security D 0 D DMA Continuous Mode Enable 0 D D 0 secure 1 non secure 27 26 25 R W 0x0 DMA_DEST_DATA_WIDTH DMA Destination Data Width 00 8 bit 01 16 bit 10 32 bit 11 24 23 R W 0x0 DMA_DEST_BST_LEN DMA Destination Burst Length A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 145 2012 04 09 Ou Allwinner Technology CO Ltd A10 00 1 01 4 10 8 11 22 21 0x0 DMA_ADDR_MODE DMA Destination Address Mode DMA Source Address Mode 0x0 Linear Mode 0x1 IO Mode 0x2 Horizontal Page Mode 0x3 Vertical Page Mode 20 16 0x0 DDMA DEST DRQ TYPE Dedicated DMA Destination DRQ Type 0x0 SRAM memory Ox1 SDRAM memory 0x2 PATA 0x3 NAND Flash Controller NFC 0x4 USBO Ox5 0x6 Ethernet MAC Tx Ox7 0x8 SPI TX 0x9 OxA S
186. ANGE G REG Bit Read Default Description Write Hex 31 24 23 16 R W 0 Coef Range Min unsigned 8bit value range of 0 255 15 8 7 0 R W 0 Coef_Range_Max unsigned 8bit value range of 0 255 Offset 0x148 Register Name TCON_CEU_RANGE_B_REG Bit Read Default Description Write Hex 31 24 23 16 R W 0 Coef_Range_Min unsigned 8bit value range of 0 255 15 8 7 0 R W 0 Coef_Range_Max unsigned 8bit value range of 0 255 33 4 37 TCONO Ivds panel analog register0 Offset 0x220 Register Name TCONO0 LVDS ANAO0 REG Bit Read Default Description Write Hex 31 30 R W 0 TCONO LVDS CKS 29 28 R W 0 TCONO LVDS CK EN 27 26 R W 0 TCONO LVDS REG V 25 23 R W 0 TCONO LVDS REG C 22 R W 0 TCONO LVDS REG EN MB 21 19 R W 0 TCONO LVDS PD 18 17 R W 0 TCONO LVDS DEN 16 R W 0 TCONO LVDS DCHS 15 R W 0 TCONO LVDS LDO EN 14 R W 0 TCONO LVDS PWS 13 12 R W 0 TCONO LVDS TEST CK 11 0 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 419 2012 04 09 Allwinner Technology CO Ltd A10 33 4 38 TCONO Ivds panel analog register1 Offset 0x224 Register Name TCONO LVDS ANA1 REG Bit Read Default Description Write Hex 31 30 27 R W 0 TCONO LVDS REG PREN DRVO 26 R W 0 TCONO LVDS REG PREN DRV0C 25 22 R W
187. B Clock for DE BEO 0 mask 1 pass 11 R W 0x0 Gating AHB Clock for HDMI 0 mask 1 pass 10 9 R W 0x0 Gating AHB Clock for CSI1 0 mask 1 pass 8 R W 0x0 Gating AHB Clock for CSIO 0 mask 1 pass 7 6 5 R W 0x0 Gating AHB Clock for LCD1 0 mask 1 pass 4 R W 0x0 Gating AHB Clock for LCDO 0 mask 1 pass 3 R W 0x0 Gating AHB Clock for TVE 1 0 mask 1 pass 2 R W 0x0 Gating AHB Clock for TVE 0 0 mask 1 pass 1 R W 0x0 Gating AHB Clock for TVD 0 mask 1 pass 0 R W 0x0 Gating AHB Clock for VE 0 mask 1 pass 6 4 18 APB0 Module Clock Gating Default 0x00000000 Offset 0x68 Register Name APBO_GATING_REG Bit Read Default Description Write Hex 31 12 11 10 R W 0x0 KEYPAD APB GATING Gating APB Clock for Keypad 0 mask 1 pass 9 8 7 R W 0x0 IR1_APB_GATING Gating APB Clock for IR1 0 mask 1 pass 6 R W 0x0 IRO APB GATING Gating APB Clock for IRO 0 mask 1 pass 5 R W 0x0 PIO_APB_GATING Gating APB Clock for PIO 0 mask 1 pass 4 3 R W 0x0 IIS_APB_GATING Gating APB Clock for IIS 0 mask 1 pass 2 R W 0x0 ACHT APB GATING Gating APB Clock for AC97 0 mask 1 pass 1 R W 0x0 NC 0 R W 0x0 CODEC_APB_GATING Gating APB Clock for Audio CODEC 0 mask 1 pass A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 49 2012 04 09
188. BSP is applied to determine when system should jump to USB boot Normally the BSP is pulled up by an internal 50K resistor After power up boot code that is stored in embedded ROM will check automatically the state of the pin and the system will boot from USB only if the pin is on low level state 0 Since A10 will always start to fetch instructions from SD CardO it permits final product to be mass produced with SD card rather than USB which can improve the MP productivity greatly A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 32 2012 04 09 A Allwinner Technology CO Ltd A10 4 2 Boot Diagram SDCO PF port boot operation SDCO Boot Success i Yes NAND Flash boot operation CEO FC Boot Yes Success i SDC2 PC port boot operation No SDC2 Boo Success No i Yes SPIO PC port boot operation SPI Nor Flas Yes Boot Success i boot OK run other firmware USB boot operation Figure 4 1 Boot Sequence A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 33 2012 04 09 Allwinner Technology CO Ltd A10 5 System Mode 5 1 Overview Together with power management IC PMIC A10 offers a comprehensive power and clock management scheme that enables high performance and ultralow power consumption There are
189. Base Address AC 0x01C22C00 Register Name Offset Description AC DAC DPC 0x00 DAC Digital Part Control Register AC DAC FIFOC 0x04 DAC FIFO Control Register AC DAC FIFOS 0x08 DAC FIFO Status Register AC DAC TXDATA 0x0C DAC TX Data Register AC DAC ACTL 0x10 DAC Analog Control Register AC_DAC_TUNE 0x14 DAC ADC Performance Tuning Register AC_ADC_FIFOC Ox1C ADC FIFO Control Register AC ADC FIFOS 0x20 ADC FIFO Status Register AC ADC RXDATA 0x24 ADC RX Data Register AC ADC ACTL 0x28 ADC Analog Control Register AC DAC CNT 0x30 DAC TX FIFO Counter Register AC ADC CNT 0x34 ADC RX FIFO Counter Register 24 2 1 DAC Digital Part Control Register Offset 0x00 Register Name AC DAC DPC Bit Read Write Default Description EN DA DAC Digital Part Enable 31 R W 0x0 0 Disable 1 Enable 30 29 11 0 24 2 2 DAC FIFO Control Register Offset 0x4 Register Name AC DAC FIFOC Bit Read Write Default Description DAC FS Sample Rate of DAC 31 29 R W 0x0 000 48KHz 010 24KHz 100 12KHz A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 255 2012 04 09 Ou Allwinner Technology CO Ltd A10 110 192KHz 001 32KHz 011 16KHz 101 SKHz 111 96KHz 44 KHz 22 05KHZ 11 025KHz can be supported by Audio PLL Configure Bit 27 SEND LASAT Audio sample select when TX FIFO under run 26 R W 0x0 0 Sending zero 1 Sending last audio sample FIFO MOD
190. C Bit Read Default Description Write Hex 31 16 12 R W 0x0 ADC1 KEYUP IRQ EN ADC 1 Key Up IRQ Enable 0 Disable 1 Enable 11 R W 0x0 ADC1 ALRDY HOLD IRQ EN ADC 1 Already Hold Key IRQ Enable A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 267 2012 04 09 Ou Allwinner Technology CO Ltd A10 0 Disable 1 Enable 10 R W 0x0 ADC 1 Hold Key IRQ Enable 0 Disable 1 Enable 9 R W 0x0 ADC1_KEYIRQ_EN ADC 1 Key IRQ Enable 0 Disable 1 Enable 8 R W 0x0 ADC1 DATA IRQ EN ADC 1 DATA IRQ Enable 0 Disable 1 Enable 7 5 4 R W 0x0 ADCO KEYUP IRQ EN ADC 0 Key Up IRQ Enable 0 Disable 1 Enable 3 R W 0x0 ADCO ALRDY HOLD IRQ EN ADC 0 Already Hold IRQ Enable 0 Disable 1 Enable 2 R W 0x0 ADCO HOLD IRQ EN ADC 0 Hold Key IRQ Enable 0 Disable 1 Enable 1 R W 0x0 ADCO KEYDOWN EN ADC 0 Key Down Enable 0 Disable 1 Enable 0 R W 0x0 ADCO DATA IRQ EN ADC 0 Data IRQ Enable 0 Disable 1 Enable 25 3 3 LRADC Interrupt Status Register Offset 0x08 Register Name LRADC INT Bit Read Default Description Write Hex 31 8 12 0x0 ADC1_KEYUP_PENDING A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 268 2012 04 09 Ou Allwinner Technology CO Ltd A10 ADC 1 Key up pending Bit When general key pull up it the corresponding inte
191. C PRIO REGO A10 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x2 level 2 Level3 0x3 level 3 highest priority 29 28 R W 0x0 IRQ 14 Priority Set priority level for IRQ bit 14 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x2 level 2 Level3 0x3 level 3 highest priority 27 26 R W 0x0 IRQ 13 Priority Set priority level for IRQ bit 13 Level0 0x0 level 0 lowest priority Levell 0x1 level 1 Level2 0x2 level 2 Level3 0x3 level 3 highest priority 25 24 R W 0x0 IRQ 12 Priority Set priority level for IRQ bit 12 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x2 level 2 Level3 0x3 level 3 highest priority 23 22 R W 0x0 IRQ 11 Priority Set priority level for IRQ bit 11 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x2 level 2 Level3 0x3 level 3 highest priority 21 20 R W 0x0 IRQ 10 Priority Set priority level for IRQ bit 10 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x2 level 2 Level3 0x3 level 3 highest priority 19 18 R W 0x0 IRQ 9 Priority Set priority level for IRQ bit 9 Level0 0x0 level 0 lowest priority Levell 0x1 level 1 Level2 0x2 level 2 Level3 0x3 level 3 highest priority 17 16 R W 0x0 IRQ 8 Priority Set priority level for IRQ bit 8 A10 User Manual
192. C97 Codec Command Register nur t rm Pom e a RE EP leat rr D es rere 247 23 54 C97 Codec Status EE Eegeregie a t bee eren 248 23 7 5 AC9T TX FIFO Regester NENNEN EENS 248 23 76 ACIT RX FIFO Register eerte erret etr egere ret een s e Paene Heure tone enun 248 23 1 1 AC97 FIFO Control Register rne ten RED D ree PE ERE RE ere E RRR 248 23 58 AC97 FIFO Status Register oreet neri rre ir PERPE e PEE ERU CERE PER ET PERO 250 23 7 9 AC97 Interrupt Control Register 250 23 7 10 AC97 Interrupt status Register 251 23 7 11 ACI TX Counter r6BIster entgoe Eege rr ERREUR TRI FER Ov es iR Ree 252 23 10 12 KEE 253 23 7 13 AC97 Interface Pin list trente etna ee Ub Ea E aei lesende 253 23 8 AC97 Clock Requirement EE 253 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 12 Ou Allwinner Technology CO Ltd A10 24 Audio Codec ssneenervsnesnesnnnnenesnesnennnnnsnesnennenesnesnennennsnesvesnennnnesnesnennenesvesnennennenenvesnennennsnesnennenssvnsnesnevnenenneee 254 241 OMEGN 254 24 2 Audio Codec Register E 255 242 1 DAC Digital Part Control Register eese nennen enne nnne nennen 255 24 22 DAC FIFO Control Register eerte tore teet rnnt trt eee era deed Seed 255 24 2 3 DAC FIFO Status Register eset ete terree eer eed ee vedi eere eet dee 257 24 24 DACTX EE 258 24 23 DAC Analog Control Register iini eter emere rie ee ENER ELE EE Ee 258 24 2 60 ADC FIFO Status Register es
193. CLK IN 00 CLK 2 01 CLK 3 10 CLK 6 11 CLK 1 In TP mode these two bits must set 1x FS DIV ADC Sample Frequency Divider 0000 CLK IN 2 0001 CLK IN 2 0010 CLK IN 2 22 21 20 1111 CLK IN 32 T ACQ Touch panel ADC acquire time CLK_IN 16 N 1 26 3 2 TP control Register 1 Offset 0x04 Register Name TP CTRL1 Bit Read Default Description Write Hex STYLUS UP DEBOUNCE Stylus Up De bounce Time setting 0x00 0 Oxff 2N CLK IN 16 256 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 2012 04 09 274 A Allwinner Technology CO Ltd A10 11 10 9 R W 0x0 STYLUS_UP_DEBOUCE_EN Stylus Up De bounce Function Select 0 Disable 1 Enable TOUCH PAN CALI EN Touch Panel Calibration 1 start Calibration it is clear to 0 after calibration TP DUAL EN Touch Panel Double Point Enable 0 Disable 1 Enable TP MODE EN Tp Mode Function Enable 0 Disable 1 Enable 0x0 TP_ADC_SELECT Touch Panel and ADC Select 0 TP 1 ADC ADC_CHAN_SELECT Analog input channel Select In Normal mode 000 X1 channel 001 X2 Channel 010 Y1 Channel 011 Y2 Channel 1xx 4 channel robin round FIFO Access Mode based on this setting Selecting one channel FIFO will access that channel data Selecting four channels FIFO will access each channel data in successive t
194. CO Ltd A10 The OBC fixed value Ranges from 0 to 255 used only in fixed value mode 31 6 67 ISP OBC offset register Offset Address 0X430 Register Name ISP_FE_OB_OFFSET_REG Bit Read Default Description Write Hex 08 00 R W OBC_OFFSET The OBC offset value A signed number ranging from 256 to 255 31 6 68 ISP OBC clamp value register Offset Address 0X434 Register Name ISP_FE_OB_CLAMP_REG Bit Read Default Description Write Hex 23 16 OBC_VER_CLM_VAL The OBC vertical clamp value Ranges from 0 to 255 07 00 OBC_HOR_CLM_VAL The OBC horizontal clamp value Ranges from 0 to 255 31 6 69 ISP LSC configuration register Offset Address 0X43C Register Name ISP_FE_LSC_CFG_REG Bit Read Default Description Write Hex 31 24 R W 2 VER_FACTOR Gain map vertical down sampling factor N N 2 6 The actual vertical down sampling factor is 2 23 16 R W 2 HOR_FACTOR Gain map horizontal down sampling factor M M 2 6 The actual horizontal down sampling factor is 2 01 00 R W LSC_MODE The LSC gain mode A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 370 2012 04 09 Ou Allwinner Technology CO Ltd A10 00 The gain factor is in U8Q8 format 0 255 256 01 The gain factor is in U8Q7 format 0 1 127 128 10 The gain factor is in U8Q6 format 0 3 63 64 11 The gain factor is in U8Q5 format 0 7 3 1 32 31 6 70 ISP LSC gain factor address registe
195. CP15 registers 0 enable 1 disable A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 80 2012 04 09 Ou Allwinner Technology CO Ltd A10 9 Pulse Width Modulator 9 1 Overview The output of the PWM is a toggling signal whose frequency and duty cycle can be modulated by its programmable registers Each channel has a dedicated internal 16 bit up counter If the counter reaches the value stored in the channel period register it will reset At the beginning of a count period cycle the PWMOUT is set to active state and counts from 0x0000 The PWM divider divides the clock 24MHz by 1 4096 according to the pre scalar bits in the PWM control register In PWM cycle mode the output will be a square waveform and the frequency is set to the period register In PWM pulse mode the output will be either a positive pulse or a negative pulse 9 2 PWM Register List Module Name Base Address PWM 0x01C20C00 Register Name Offset Description PWM CTRL REG 0x0200 PWM Control Register PWM CH0 PERIOD 0x0204 PWM Channel 0 Period Register PWM CH1 PERIOD 0x0208 PWM Channel 1 Period Register 9 3 PWM Register Description 9 3 1 PWM Control Register Default 0x00000000 Offset 0x200 Register Name PWM CTRL REG Bit Read Default Description Write Hex 31 24 23 R W 0x0 PWM_CH1_PULSE_OUT_START PWM Channel 1 pulse out
196. Clear To End This active low signal is an input showing when Modem is ready to accept data UART1_DTR OUT UART Data Terminal Ready This active low output signal informs Modem that the UART is ready to establish a communication link UARTI DSR IN UART Data Set Ready This active low signal is an input indicating when Modem is ready to set up a link with the UARTO UARTI DCD IN UART Data Carrier Detect This active low signal is an input indicating when Modem has detected a carrier UARTI RING IN UART Ring Indicator This active low signal is an input showing when Modem has sensed a ring signal on the telephone line UART2 TX 1 OUT UART Serial Bit output UART2_RX 1 IN UART Serial Bit input UART2_RTS 1 OUT UART Request To Send This active low output signal informs Modem that the UART is ready to send data UART2_CTS 1 IN UART Clear To End This active low signal is an input showing when Modem is ready to accept data A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 197 2012 04 09 Allwinner Technology CO Ltd A10 UART3 TX 1 OUT UART Serial Bit output UART3 RX 1 IN UART Serial Bit input UART3 RTS 1 OUT UART Request To Send This active low output signal informs Modem that the UART is ready to send data UART3_CTS 1 IN UART Clear To End This active low signal is an input showing when Modem is ready to accept da
197. Cs as specified by the A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 436 2012 04 09 Ou Allwinner Technology CO Ltd A10 CPhaseRset bits of the EncConfig5 parameter see above 34 4 16 TV Encoder Burst Width Register Offset 0x114 Register Name TVE 114 REG Bit Read Default Description Write Hex 31 24 R W 58 Back_Porch Breezeway like in HD mode VSync 720p mode is 220 2080i p mode is 88 default 23 22 16 R W 16 Breezeway Must be even Specify the width of the breezeway in encoder clock cycles 5 bit unsigned integer Allowed range is 0 to 31 Default value is 22 In 10801 mode is 44 In 1080p mode is 44 In 720p mode is 40 15 14 8 R W 44 Burst_Width Specify the width of the color frequency burst in encoder clock cycles 7 bit unsigned integer Allowed range is 0 to 127 Default value is 68 In hd mode ignored 7 0 R W TE HSync_Width Specify the width of the horizontal sync pulse in encoder clock cycles Min value is 16 Max value is FrontPorch ActiveLine BackPorch Default value is 126 The sum of HSyncSize and BackPorch is restricted to be divisible by 4 In 720p mode is 40 In 1080i p mode is 44 34 4 17 TV Encoder Cb Cr Gain Register Offset 0x118 Register Name TVE_118_REG Bit Read Default Description Write Hex 31 16 15 8 R W 89 Cr_Gain Specify the Cr color g
198. DS RST LVDS reset 0 reset valid 1 reset invalid 6 4 57 HDMI Clock Default 0x00000000 Offset 0x150 Register Name HDMI CLK REG Bit Read Default Description Write Hex 31 R W 0x0 SCLK GATING Gating Special Clock 0 Clock is OFF 1 Clock is ON This special clock Clock Source Divider M 30 26 25 24 R W 0x0 CLK SRC SEL Clock Source Select 00 PLL3 1X 01 PLL7 1X 10 PLL3 2X 11 PLL7 2X 23 4 3 0 R W 0x0 CLK DIV RATIO M Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 16 6 4 58 Mali400 Clock Default 0x00000000 Offset 0x154 Register Name MALI400 CLK REG Bit Read Default Description Write Hex 31 R W 0x0 SCLK GATING Gating Special Clock Max Clock 381MHz 0 Clock is OFF A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 74 2012 04 09 Ou Allwinner Technology CO Ltd A10 1 Clock is ON This special clock Clock Source Divider M 30 R W 0x0 MALI400_RST Mali400 Reset 0 reset valid 1 reset invalid 29 26 25 24 R W 0x0 CLK_SRC_SEL Clock Source Select 00 PLL3 01 PLL4 10 PLLS 11 PLL7 23 18 17 16 15 4 3 0 R W 0x0 CLK_DIV_RATIO_M Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 16 7
199. Data 0 Register Offset 0x0c Register Name LRADC_DATA Bit Read Default Description Write Hex 31 6 5 0 R 0x0 LRADCO DATA LRADC 0 Data A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 270 2012 04 09 Ou Allwinner Technology CO Ltd A10 25 3 5 LRADC Data 1 Register Offset 0x10 Register Name LRADC_DATA Bit Read Default Description Write Hex 31 6 5 0 R 0x0 LRADC1 DATA LRADC 1 Data A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 271 2012 04 09 Ou Allwinner Technology CO Ltd A10 26 TP Controller 26 1 Overview The TP controller can be configured either as a 4 wire resistive touch screen controller or a 12 bit resolution A D converter As a 4 wire resistive touch screen controller it supports dual touch detection As an A D converter it can locate of single touch through two times of A D conversion The TP controller is featured as following 12 bit SAR type A D converter 4 wire I F Dual Touch Detection Touch pressure measurement Support program set threshold Sampling frequency 2MHz max Support both Single Ended and Ratiometric Conversion of Touch Screen Inputs TACQ up to 262ms Support Median and averaging filter which can reduce noise Pen down detection with programmable sensitivity Support X Y change function A10 Us
200. Default 0x00000000 esee 130 12 DMA Controller s esessenesssnenesnenensenensenenesneneneenensenenesnenensenenesnenesnenensenenssnenessenensenenesnenesnenensenensenenesneneneen 134 12 1 EE 134 12 2 DMA Register Last socssss sects cczesucanes HER EEA E AT A EAEE edet Pe 134 12 3 DMA Programmable Register ertet tte conte denne er ak an nn aono aea egere ie 135 12 3 1 DMA IRQ Enable Register Default 0x00000000 eese 135 12 3 2 DMA IRQ Pending Status Register Default 0x00000000 cese 137 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 8 2012 04 09 Ou Allwinner Technology CO Ltd A10 12 3 3 NDMA Auto Gating Register Default 0x00000000 oo eee eeeeeeeceeeeeeeeetaetaeeeeeeaees 140 12 3 4 Normal DMA Configuration Register Default 0x00000000 eene 141 12 3 5 Normal DMA Source Address Register Default 0x00000000 eese 144 12 3 6 Normal DMA Destination Address Register Default 0x00000000 esses 144 12 3 7 Normal DMA Byte Counter Register Default 0x00000000 rsvrrvrnvnnrnrnvrnvnnrnnrnrrvenvvnrneene 144 12 3 8 Dedicated DMA Configuration Register Default 0x00000000 csse 145 12 3 9 Dedicated DMA Source Start Address Register N 0 7 sse 148 12 3 10 Dedicated DMA Destination Start Address Register 148 12 3 11 Dedicated DMA
201. Default Value 0x0000_0000 Bit Read Write Default Description PIO_INT_CFG External INTn Mode n 8 15 0x0 Positive Edge Ox1 Negative Edge 0x2 High Level 0x3 Low Level 41 3 41 0x4 Double Edge Positive Negative i 0 7 R W 0 Others Reserved 30 3 84 PIO Interrupt Configure Register 2 Register Name PIO_INT_CFG2 Offset 0x208 Default Value 0x0000_0000 Bit Read Write Default Description PIO_INT_CFG External INTn Mode n 16 23 0x0 Positive Edge Ox1 Negative Edge 41 3 41 0x2 High Level 120 7 R W 0 0x3 Low Level A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 331 2012 04 09 Ou Allwinner Technology CO Ltd A10 0x4 Double Edge Positive Negative Others Reserved 30 3 85 PIO Interrupt Configure Register 3 Register Name PIO_INT_CFG3 Offset 0x20C Default Value 0x0000_0000 Bit Read Write Default Description PIO_INT_CFG External INTn Mode n 24 31 0x0 Positive Edge Ox1 Negative Edge 0x2 High Level 0x3 Low Level 41 3 41 0x4 Double Edge Positive Negative i 0 7 R W 0 Others Reserved 30 3 86 PIO Interrupt Control Register Register Name PIO_INT_CTL Offset 0x210 Default Value 0x0000_0000 Bit Read Write Default Description PIO_INT_CTL External INTn Enable n 0 31 n 0 Disable n 0 31 R W 0 1 Enable 30 3 87
202. Description Write Hex 31 00 R W COFO_BUFA FIFO 0 output buffer A address 31 6 6 CSI Channel_0 FIFO 0 output buffer B address register Offset Address 0X0014 Register Name CSIO C0 F0 BUFB REG Bit Read Default Description Write Hex 31 00 R W COF0 BUER FIFO 0 output buffer B address A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 346 2012 04 09 Ou Allwinner Technology CO Ltd A10 31 6 7 CSI Channel_0 FIFO 1 output buffer A address register Offset Address 0X0018 Register Name CSIO C0 F1 BUFA REG Bit Read Default Description Write Hex 31 00 R W COP BUFA FIFO 1 output buffer A address 31 6 8 CSI Channel 0 FIFO 1 output buffer B address register Offset Address 0X001C Register Name CSIO C0 F1 BUFB REG Bit Read Default Description TE E 31 00 R W COF1_BUFB ITT FIFO 1 output buffer B address 31 6 9 CSI Channel_0 FIFO 2 output buffer A address register Offset Address 0X0020 Register Name CSIO C0 F2 BUFA REG Bit Read Default Description Write Hex 31 00 R W COP BUFA FIFO 2 output buffer A address 31 6 10 CSI Channel 0 FIFO 2 output buffer B address register Offset Address 0X0024 Register Name CSIO C0 F2 BUFB REG Bit Read Default Description Write Hex 31 00 R W COF2 BUFB FIFO 2 output buffer B address 31 6 11 CSI Channel 0 output buffer control register Offset Address 0X0028 Register Name CSIO C0 BUF CTL REG A10 U
203. E When TXMODE 0 For 24 bits transmitted audio sample 00 10 FIFO 1 23 0 TXDATA 31 8 01 11 Reserved For 16 bits transmitted audio sample 00 10 FIFO 1 23 0 TXDATA 31 16 8 b0j 25 24 R W 0x0 01 11 FIFO_1 23 0 TXDATA 15 0 8 b0j When TXMODE 1 Only 16 bit sample supported 00 FIFO I 0 15 0 TXDATA 31 16 01 FIFO I 0 15 0 TXDATA 15 0 10 FIFO I 0 15 0 TXDATA 31 16 FIFO I 1 15 0 TXDATA 15 0 11 FIFO I 0 15 0 TXDATA 15 0 FIFO I 1 15 0 TXDATA 31 16 TX MODE TX FIFO Mode 23 R W 0x0 0 24x128 1 16x20x1024 DAC_DRQ_CLR_CNT When TX FIFO available room less than or equal N DRQ Request will be de asserted N is defined here 22 21 R W 0x0 00 IRQ DRQ Deasserted when WLEVEL gt TXTL 01 4 10 8 11 16 TX_TRIG_LEVEL TX FIFO Empty Trigger Level TXTL 12 0 20 8 R W OxF Interrupt and DMA request trigger level for TX FIFO normal condition IRQ DRQ Generated when WLEVEL lt TXTL A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 256 2012 04 09 Ou Allwinner Technology CO Ltd A10 Notes 1 WLEVEL represents the number of valid samples in the TX FIFO 2 Only TXTL 6 0 valid when TXMODE 0 0x0 DAC MONO EN DAC Mono Enable 0 Stereo 64 levels FIFO 1 mono 128 levels FIFO When enabled L amp R channel send same data 0x0 TX_SAMPLE_BITS Transmitting Audio Sample Resolution 0 16 bits 1 24 bits 0x0 DAC DRQ EN
204. E0_DCLK_GATING Gating DRAM Clock for DE_FE1 0 mask 1 pass 24 R W 0x0 FE1_DCLK_GATING Gating DRAM Clock for DE PPOO mask 1 pass 23 16 15 R W 0x0 DCLK_OUT_EN DRAM Clock Output Enable 0 disable 1 enable 14 7 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 62 2012 04 09 Ou Allwinner Technology CO Ltd A10 6 R W 0x0 TVE1_DCLK_GATING Gating DRAM Clock for TVE 1 0 mask 1 pass 5 R W 0x0 TVEO DCLK GATING Gating DRAM Clock for TVE 0 0 mask 1 pass 4 R W 0x0 TVD DCLK GATING Gating DRAM Clock for TVD 0 mask 1 pass 3 R W 0x0 TS DCLK GATING Gating DRAM Clock for TS 0 mask 1 pass 2 R W 0x0 CSI1_DCLK_GATING Gating DRAM Clock for CSI1 0 mask 1 pass 1 R W 0x0 CSIO DCLK GATING Gating DRAM Clock for CSIO 0 mask 1 pass 0 R W 0x0 VE_DCLK_GATING Gating DRAM Clock for VE 0 mask 1 pass 6 4 39 DE BE 0 Clock Default 0x00000000 Offset 0x104 Register Name BEO_SCLK_CFG_REG Bit Read Default Description Write Hex 31 R W 0x0 SCLK GATING Gating Special Clock 0 Clock is OFF 1 Clock is ON This special clock Clock Source Divider M 30 R W 0x0 BEO_RST 0 reset valid 1 reset invalid 29 26 25 24 R W 0x0 CLK_SRC_SEL Clock Source Select 00 PLL3 01 PLL7 10 PLL5 11 23 18 17 16 15 4 3 0 R W 0
205. EN Frame done Indicates the CSI has finished capturing an image frame Applies to video capture mode The bit is set after each completed frame capturing data is wrote to buffer as long as video capture remains enabled CD INT EN Capture done Indicates the CSI has completed capturing the image data For still capture the bit is set when one frame data has been wrote to buffer For video capture the bit is set when the last frame has been wrote to buffer after video capture has been disabled For CCIR656 interface if the output format is frame planar YCbCr 420 mode the frame end means the field2 end the other frame end means field end Offset Address 0X0234 Register Name CSIO C2 INT STA REG Bit Read Default Description Write Hex VS PD vsync flag PE HB OF PD Hblank FIFO overflow pP w jo PRTC_ERR_PD FIFO2_OF_PD FIFO 2 overflow FIFO1 OF PD A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 359 2012 04 09 am ENNIUS CO Ltd A10 FIFO 1 overflo FIFOO_OF_PD FIFO 0 overflow R W FD_PD Frame done R W CD_PD Capture done 31 6 41 CSI Channel 2 horizontal size register Offset Address 0X0240 Register Name CSIO C2 HSIZE REG Read Default Description Write Hex EE 28 16 R W HOR_LEN Horizontal pixel clock length Valid pixel clocks of a line eke a UU 12 00 R W HOR_START Horizontal pixel clock start Pixel data is valid from this
206. FFF 4K SD MMC 1 0x01C1 0000 0x01C1 OFFF 4K SD MMC 2 0x01C1 1000 0x01C1 1FFF 4K SD MMC 3 0x01C1 2000 0x01C1 2FFF 4K USB 0 0x01C1 3000 0x01C1 3FFF 4K USB 1 0x01C1 4000 0x01C1 4FFF 4K SS 0x01C1 5000 0x01C1 5FFF 4K HDMI 0x01C1 6000 0x01C1 6FFF 4K SPI 2 0x01C1 7000 0x01C1 7FFF 4K NC 0x01C1 8000 0x01C1 8FFF 4K PATA 0x01C1 9000 0x01C1 9FFF 4K ACE 0x01C1 A000 0x01C1 AFFF 4K TVE 1 0x01C1 B000 0x01C1 BFFF 4K USB 2 0x01C1 C000 0x01C1 CFFF 4K CSI I 0x01C1 D000 0x01C1 DFFF 4K TZASC 0x01C1 E000 0x01C1 EFFF 4K A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 29 2012 04 09 Ou Allwinner Technology CO Ltd SPI3 0x01C1 F000 0x01C1 FFFF 4K CCM 0x01C2 0000 0x01C2 03FF 1K INTC 0x01C2 0400 0x01C2 07FF IK PIO 0x01C2 0800 0x01C2 OBFF IK Timer 0x01C2 0C00 0x01C2 OFFF IK NC 0x01C2 1000 0x01C2 13FF IK AC97 0x01C2 1400 0x01C2 17FF IK IRO 0x01C2 1800 0x01C2 1BFF IK IR 1 0x01C2 1C00 0x01C2 1FFF IK IIS 0x01C2 2400 0x01C2 27FF IK LRADC 0 1 0x01C2 2800 0x01C2 2BFF IK AD DA 0x01C2 2C00 0x01C2 2FFF IK KEYPAD 0x01C2 3000 0x01C2 33FF 1K TZPC 0x01C2 3400 0x01C2 37FF 1K SID 0x01C2 3800 0x01C2 3BFF 1K SJTAG 0x01C2 3C00 0x01C2 3FFF IK TP 0x01C2 5000 0x01C2 53FF IK PMU 0x01C2 5400 0x01C2 57FF IK UART 0 0x01C2 8000 0x
207. FIFO O 19 4 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 249 2012 04 09 Ou Allwinner Technology CO Ltd A10 23 7 8 AC97 FIFO Status Register Offset 0x1C Register Name AC FSTA Default Value 0x0000 C000 Bit Read Write Default Description 31 6 15 R 1 TXE TX FIFO Empty 0 No room for new sample in TX FIFO 1 More than one room for new sample in TX FIFO gt 1 word 14 7 R 0x80 TXE CNT TX FIFO Empty Space Word counter 6 R 0 RXA RX FIFO Available 0 No available data in RX FIFO 1 More than one sample in RX FIFO gt 1 word 5 0 R 0 RXA_CNT RX FIFO Available Sample Word counter 23 7 9 4 C97 Interrupt Control Register Offset 0x20 Register Name AC INT Default Value 0x0000 0000 Bit Read Write Default Description 31 10 9 R W 0 CODEC_GPIO_EN Codec GPIO interrupt enable 0 Disable 1 Enable R W CREN Codec Ready interrupt enable 0 Disable 1 Enable R W TX_DRQ TX FIFO Empty DRQ Enable 0 Disable 1 Enable R W TXUI EN TX FIFO Under run Interrupt Enable 0 Disable A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 250 2012 04 09 Ou Allwinner Technology CO Ltd A10 1 Enable R W TXOL EN TX FIFO Overrun Interrupt Enable 0 Disable 1 Enable R W T
208. FIFO as empty This also de asserts the DMA TX request 2 W 0 It is self clearing It is not necessary to clear this bit RFIFOR RCVR FIFO Reset This resets the control portion of the receive FIFO and treats the FIFO as empty This also de asserts the DMA RX request 1 W 0 It is self clearing It is not necessary to clear this bit FIFOE Enable FIFOs This enables disables the transmit XMIT and receive RCVR FIFOs Whenever the value of this bit is changed both the XMIT and RCVR controller 0 W 0 portion of FIFOs is reset 18 4 8 UART Line Control Register Register Name UART LCR Offset 0x0C Default Value 0x0000 0000 Bit Read Write Default Description 31 8 DLAB Divisor Latch Access Bit It is writeable only when UART is not busy USR 0 is zero and always readable This bit is used to enable reading and writing of the Divisor Latch register DLL and DLH to set the baud rate of the UART This bit must be cleared after initial baud rate setup in order to access other registers 0 Select RX Buffer Register RBR TX Holding Register THR and Interrupt Enable Register IER 1 Select Divisor Latch LS Register DLL and 7 R W 0 Divisor Latch MS Register DLM BC Break Control Bit This is used to cause a break condition to be 6 R W 0 transmitted to the receiving device If set to one the A10 User Manual V1 20 Copyright 2011 2012 Allwinner Tech
209. FIQ The interrupt sources 1 to 63 are located at System Interrupt and user peripheral Interrupt SRC Vector FIQ Description Source External NMI 0 0x0000 YES External Non Mask Interrupt Power module battery VDD VDDIO VDD18 VDD25 brownout detect UART 0 1 0x0004 UART 0 interrupt UART 1 2 0x0008 UART I interrupt UART 2 3 0x000C UART 2 interrupt UART3 4 0x0010 UART 3 interrupt IR O 5 0x0014 IR 0 interrupt IR 1 6 0x0018 IR 1 interrupt TWIO 7 0x001C TWI 0 interrupt TWI 1 8 0x0020 TWI I interrupt TWI2 9 0x0024 TWI 2 interrupt A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 109 2012 04 09 Ou Allwinner Technology CO Ltd A10 Interrupt SRC Vector FIQ Description Source SPIO 10 0x0028 SPI 0 interrupt SPI 1 11 0x002C SPI I interrupt SPI2 12 0x0030 SPI 2 interrupt NC 13 0x0034 NC AC97 14 0x0038 AC97 interrupt TS 15 0x003C TS interrupt IIS 16 0x0040 Digital Audio Controller interrupt UART A 17 0x0044 UART 4 interrupt UART 5 18 0x0048 UART 5 interrupt UART 6 19 0x004C UART 6 interrupt UART 7 20 0x0050 UART 7 interrupt Keypad 21 0x0054 Keypad interrupt Timer 0 22 0x0058 Timer port 0 Timer 1 23 0x005C Timer port 1 Timer 24 0x0060 Timer 2 Alarm Watchdog 2 Alarm WD Timer 3 25 0x0064 Timer 3
210. Function Mode Select 0 Slave Mode 1 R W 0 1 Master Mode EN SPI Module Enable Control 0 Disable 0 R W 0 1 Enable 17 4 4 SPI Interrupt Control Register Register Name SPI INTCTL Offset 0x0C Default Value 0x0000_0000 Bit Read Write Default Description 31 18 SS_INT_EN SSI Interrupt Enable Chip Select Signal SSx from valid state to invalid state 0 Disable 17 R W 0 1 Enable TX_INT_EN Transfer Completed Interrupt Enable 0 Disable 16 R W 0 1 Enable 15 TF_UR_INT_EN TXFIFO under run Interrupt Enable 0 Disable 14 R W 0 1 Enable TF_OF_INT_EN TX FIFO Overflow Interrupt Enable 0 Disable 13 R W 0 1 Enable 12 R W 0 TF E34 INT EN A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 168 2012 04 09 Ou Allwinner Technology CO Ltd A10 TX FIFO 3 4 Empty Interrrupt Enable 0 Disable 1 Enable TF E14 INT EN TX FIFO 1 4 Empty Interrrupt Enable 0 Disable 11 R W 0 1 Enable TF_FL_INT_EN TX FIFO Full Interrupt Enable 0 Disable 10 R W 0 1 Enable TF_HALF_EMP_INT_EN TX FIFO Half Empty Interrupt Enable 0 Disable 9 R W 0 1 Enable TX_EMP_INT_EN TX FIFO Empty Interrupt Enable 0 Disable R W 0 1 Enable RF_UR_INT_EN RXFIFO under run Interrupt Enable 0 Disable 6 R W 0 1 Enable RF_OF_INT_EN RX FIFO Overflow Interrupt Enable 0 Disable 2 R W
211. G 0x0014 TCON FRM seed registerO TCON FRM PSEED G REG 0x0018 TCON FRM seed register 1 TCON FRM PSEED B REG 0x001C TCON FRM seed register2 TCON FRM LSEED R REG 0x0020 TCON FRM seed register3 TCON FRM LSEED G REG 0x0024 TCON FRM seed register4 TCON FRM LSEED B REG 0x0028 TCON FRM seed register5 TCONO FRM TABO REG 0x002C TCON FRM table register0 TCONO FRM TABI REG 0x0030 TCON FRM table register TCONO FRM TAB2 REG 0x0034 TCON FRM table register2 TCONO FRM TAB3 REG 0x0038 TCON FRM table register3 TCONO CTL REG 0x0040 TCONO control register TCONO DCLK REG 0x0044 TCONO data clock register TCONO BASICO REG 0x0048 TCONO basic timing registerO TCONO BASICI REG 0x004C TCONO basic timing register 1 TCONO BASIC2 REG 0x0050 TCONO basic timing register2 TCONO BASIC3 REG 0x0054 TCONO basic timing register3 TCONO HV IF REG 0x0058 TCONO hv panel interface register TCONO CPU IF REG 0x0060 TCONO cpu panel interface register TCONO CPU WR REG 0x0064 TCONO cpu panel write data register TCONO CPU RDO REG 0x0068 TCONO cpu panel read data register0 TCONO CPU RD1 REG 0x006C TCONO cpu panel read data register I TCONO TTLO REG 0x0070 TCONO ttl timing register0 TCONO TTL1 REG 0x0074 TCONO ttl timing register 1 TCONO TTL2 REG 0x0078 TCONO ttl timing register2 TCONO TTL3 REG 0x007C TCONO ttl timing register3 TCONO TTLA REG 0x0080 TCONO ttl timing register4 TCONO LVDS IF REG 0x0084 TCONO Ivds panel interface register TCONO IO POL REG 0x0088 TCONO IO polarity register
212. HO GATING A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 82 2012 04 09 Ou Allwinner Technology CO Ltd A10 Gating the Special Clock for PWMO 0 mask 1 pass R W 0x0 PWM CHO ACT STA PWM Channel 0 Active State 0 Low Level 1 High Level R W 0x0 PWM CHO EN PWM Channel 0 Enable 0 Disable 1 Enable 3 0 R W 0x0 PWM CHO PRESCAL PWM Channel 0 Prescalar These bits should be setting before the PWM Channel 0 clock gate on 0000 120 0001 180 0010 240 0011 360 0100 480 0101 O110 0111 1000 12k 1001 24k 1010 36k 1011 48k 1100 72k 1101 1110 1111 9 3 2 PWM Channel 0 Period Register Offset 0x204 Register Name PWM_CH0_PERIOD Bit Read Default Description Write Hex 31 24 23 16 R W X PWM CHO ENTIRE CYS Number of the entire cycles in the PWM clock 0 2 1 cycle 1 2 cycles N N 1 cycles If the register need to be modified dynamically the PCLK should be faster than the PWM CLK PWM CLK 24MHz prescale 15 8 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 83 2012 04 09 Ou Allwinner Technology CO Ltd A10 7 0 R W X PWM CHO ENTIRE ACT CYS Number of the active cycles in the PWM clock 0 0 cycle 1 1 cycles N N cycles
213. HT 1 Thdclk 15 12 11 0 R W 0 HBP horizontal back porch Thbp HBP 1 Thdclk 33 4 30 TCONI basic timing register4 Offset 0x0A4 Register Name TCON1 BASIC4 REG Bit Read Default Description Write Hex 31 29 28 16 R W 0 VT horizontal total time in HD line Tvt VT 2 Th 15 12 11 0 R W 0 VBP horizontal back porch in HD line Tvbp VBP 1 Th 33 4 34 TCONI basic timing register5 Offset 0x0A8 Register Name TCON1 BASIC5 REG Bit Read Default Description Write Hex 31 26 25 16 R W 0 HSPW horizontal Sync Pulse Width in dclk Thspw HSPW 1 Tdclk Note HT gt HSPW 1 15 10 9 0 R W 0 VSPW vertical Sync Pulse Width in lines A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 414 2012 04 09 Ou Allwinner Technology CO Ltd A10 Tvspw VSPW 1 Th Note VT 2 gt VSPW 1 33 4 32 TCONI IO polarity register Offset 0x0FO Register Name TCON1 IO POL REG Bit Read Default Description Write Hex 31 28 27 R W 0 IO3 Inv 0 not invert 1 invert 26 R W 0 102 Inv 0 not invert 1 invert 25 R W 0 IO1 Inv 0 not invert 1 invert 24 R W 0 100 Inv 0 not invert 1 invert 23 0 R W 0 Data Inv TCON1 output port D 23 0 polarity control with independent bit control Os normal polari
214. I 100 KP OUT4 101 SDC1 DO 2 0 R W 0 110 Reserved 111 CSI1 PCLK 30 3 68 PH Data Register Register Name PH DAT Offset 0x10C Default Value 0x0000_0000 Bit Read Write Default Description 31 28 PH_DAT If the port is configured as input the corresponding bit is the pin state If the port is configured as output the pin state is the same as the corresponding bit The read bit value is the value setup by software If the port is configured as 27 0 R W 0 functional pin the undefined value will be read A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 324 2012 04 09 N Allwinner Technology CO Ltd A10 30 3 69 PH Multi Driving Register 0 Register Name PH DRVO Offset 0x110 Default Value 0x5555 5555 Bit Read Write Default Description PH DRV PH n Multi Driving Select n 0 15 21 1 21 00 Level 0 01 Level 1 G 0 15 R W Ox1 10 Level 2 11 Level 3 30 3 70 PH Multi Driving Register 1 Register Name PH DRV1 Offset 0x114 Default Value 0x0055 5555 Bit Read Write Default Description 31 24 PH DRV PH n Multi Driving Select n 16 27 21 1 21 00 Level 0 01 Level 1 i20 11 R W Ox1 10 Level 2 11 Level 3 30 3 71 PH Pull Register 0 Register Name PH PULLO Offset 0x118 Default Value 0x0000 0000 Bit Read Write Default Description PH PUL
215. I Channel O interrupt status register CSIO CH HSIZE REG 0X040 CSI Channel 0 horizontal size register CSIO C0 VSIZE REG 0X044 CSI Channel 0 vertical size register CSIO C0 BUF LEN REG 0X048 CSI Channel O line buffer length register CSIO C1 FO BUFA REG 0X110 CSI Channel I FIFO 0 output buffer A address register CSIO C1 F0 BUFB REG 0X114 CSI Channel I FIFO 0 output buffer B address register CSIO C1 F1 BUFA REG OX118 CSI Channel I FIFO 1 output buffer A address register CSIO C1 F1 BUER REG OX11C CSI Channel I FIFO 1 output buffer B address register CSIO C1 F2 BUFA REG 0X120 CSI Channel I FIFO 2 output buffer A address register CSIO C1 F2 BUER REG 0X124 CSI Channel I FIFO 2 output buffer B address register CSIO C1 BUF CTL REG 0X128 CSI Channel 1 output buffer control register CSIO C1 BUF STA REG OXI12C CSI Channel 1 status register CSIO C1 INT EN REG 0X130 CSI Channel I interrupt enable register CSIO C1 INT STA REG 0X134 CSI Channel 1 interrupt status register CSIO C1 HSIZE REG 0X140 CSI Channel I horizontal size register CSIO C1 VSIZE REG 0X144 CSI Channel_1 vertical size register A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 339 2012 04 09 Allwinner Technology CO Ltd A10 CSIO C1 BUF LEN REG 0X148 CSI Channel 1 line buffer length register CSIO C2 FO BUFA REG 0X210 CSI Channel
216. INT_EN Keypad input rising edge key release interrupt enable 0 Disable 1 R W 0 1 Enable A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 281 2012 04 09 Ou Allwinner Technology CO Ltd A10 FEDGE_INT_EN Keypad input falling edge key press interrupt enable 0 Disable 1 Enable 27 3 4 Keypad Interrupt Status Register Offset 0x0C Register Name KP_INT_STA Default Value 0x0000_0000 Bit Read Write Default Description 31 2 REDGE_FLAG Keypad input rising edge key release interrupt status When it is 1 ther key released interrupt occurred The interrupt is cleared when write 1 R W FEDGE FLAG Keypad input falling edge key press interrupt status When it is 1 the corresponding pressed interrupt occurred The interrupt is cleared when write 1 27 3 5 Keypad Input Data Register 0 Offset 0x10 Register Name KP INO Default Value Oxffff ffff Bit Read Write Default Description 81 7 8i COL STAO 1 0 3 R W Oxff Keypad row input byte for column n scan n from 0 to 3 27 3 6 Keypad Input Data Register 1 Offset 0x14 Register Name KP IN1 Default Value Oxffff_ffff Bit Read Write Default Description 8i 7 81 COL STAI 120 3 R W Oxff Keypad row input byte for column n scan n from 4 to 7 27 4 Keypad Interfac
217. IRQ Pending Notes Writing 1 to the bit will clear it and its corresponding interrupt A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 269 2012 04 09 Ou Allwinner Technology CO Ltd A10 if the interrupt is enable R W 0x0 ADCO ALRDY HOLD PENDING ADC 0 Already Hold Pending Bit When hold key pull down and pull the general key down if the corresponding interrupt is enabled 0 No IRQ 1 IRQ Pending Notes Writing 1 to the bit will clear it and its corresponding interrupt if the interrupt is enable R W 0x0 ADCO HOLDKEY PENDING ADC 0 Hold Key pending Bit When Hold key pull down the status bit is set and the interrupt line is set if the corresponding interrupt is enabled 0 NO IRQ 1 IRQ Pending Notes Writing 1 to the bit will clear it and its corresponding interrupt if the interrupt is enable R W 0x0 ADCO_KEYDOWN_PENDING ADC 0 Key Down IRQ Pending Bit When General key pull down the status bit is set and the interrupt line is set if the corresponding interrupt is enabled 0 No IRQ 1 IRQ Pending Notes Writing 1 to the bit will clear it and corresponding interrupt if the interrupt is enabled R W 0x0 ADCO DATA PENDING ADC 0 Data IRQ Pending Bit 0 No IRQ 1 IRQ Pending Notes Writing 1 to the bit will clear it and its corresponding interrupt if the interrupt is enable 25 3 4 LRADC
218. IV_RATIO_M Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 56 2012 04 09 Ou Allwinner Technology CO Ltd A10 D ne S SYS 6 4 29 SPI2 Clock Default 0x00000000 Offset 0xA8 Register Name SPI CLK REG Bit Read Write Default Hex Description 31 R W 0x0 SCLK_GATING Gating Special Clock Max Clock 200MHz 0 Clock is OFF 1 Clock is ON This special clock Clock Source Divider N Divider M 30 26 25 24 R W 0x0 CLK_SRC_SEL Clock Source Select 00 OSC24M 01 PLL6 10 PLL5 11 23 18 17 16 R W 0x0 CLK_DIV_RATIO_N Clock pre divide ratio n The select clock source is pre divided by 2 n The divider is 1 2 4 8 15 4 3 0 R W 0x0 CLK_DIV_RATIO_M Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 16 6 4 30 IR 0 Clock Default 0x00000000 Offset 0xB0 Register Name IRO_CLK_REG Bit Read Default Description Write Hex 31 R W 0x0 SCLK_GATING Gating Special Clock Max Clock 100MHz 0 Clock is OFF 1 Clock is ON This special clock Clock Source Divider N Divider M 30 26 25 24 R W 0x0 CLK_SRC_SEL A10 User Manual V1 20 Copyright 2011
219. In byte accessing method if there are words in RXFIFO the top word is returned and the RXFIFO depth is decreased by 1 In half word accessing method the two SPI bursts are returned and the RXFIFO depth is decrease by 2 In word accessing method the four SPI bursts are returned and the RXFIFO depth is decreased by 4 17 4 2 SPI TX Data Register Offset 0x04 Register Name SPI TXDATA Default Value 0x0000 0000 Bit Read Write Default Description 31 0 W TDATA Transmit Data 17 4 3 SPI Control Register Offset 0x08 Register Name SPI CTL Default Value 0x0002_001C Bit Read Write Default Description 31 20 19 R W 0 SDC A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 165 2012 04 09 Ou Allwinner Technology CO Ltd A10 Master Sample Data Control Set this bit to 1 to make the internal read sample point with a delay of half cycle of SPI_CLK It is used in high speed read operation to reduce the error caused by the time delay of SPI_CLK propagating between master and slave 1 delay internal read sample point 0 normal operation do not delay internal read sample point TP_EN Transmit Pause Enable In master mode it is used to control transmit state machine 18 R W 0 f to stop smart burst sending when RX FIFO is full 1 stop transmit data when RXFIFO full 0 nor
220. L PH n Pull up down Select n 2 0 15 21 1 2i 00 Pull up down disable O1 Pull up 1 0 15 R W 0x0 10 Pull down 11 Reserved 30 3 72 PH Pull Register 1 Register Name PH_PULL1 Offset 0x11C Default Value 0x0000_0000 Bit Read Write Default Description 31 24 PH_PULL 21 1 21 PH n Pull up down Select n 2 16 27 1 0 11 R W 0x0 00 Pull up down disable 01 Pull up enable A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 325 2012 04 09 Ou Allwinner Technology CO Ltd A10 10 Pull down 11 Reserved 30 3 73 PI Configure Register 0 Register Name PI CFGO Offset 0x120 Default Value 0x0000 0000 Bit Read Write Default Description 31 PI7 SELECT 000 Input 001 Output 010 SDC3 DI 011 Reserved 100 Reserved 101 Reserved 30 28 R W 0 110 Reserved 111 Reserved 27 PI6 SELECT 000 Input 001 Output 010 SDC3 DO O11 Reserved 100 Reserved 101 Reserved 26 24 R W 0 110 Reserved 111 Reserved 23 DIS SELECT 000 Input 001 Output 010 SDC3 CLK 011 Reserved 100 Reserved 101 Reserved 22 20 R W 0 110 Reserved 111 Reserved 19 PI4 SELECT 000 Input 001 Output 010 SDC3 CMD O11 Reserved 100 Reserved 101 Reserved 18 16 R W 0 110 Reserved 111 Reserved 15 PI3_SELECT 000 Input 001 Output 010 PWMI 011 Reserved 100 Reserv
221. L5 CFG REG 0x0020 PLL5 control PLL5 TUN REG 0x0024 PLLS tuning PLL6 CFG REG 0x0028 PLL6 control PLL6 TUN REG 0x002C PLL6 tuning PLL7 CFG REG 0x0030 PLL7 control 0x0034 PLL1 TUN2 REG 0x0038 PLLI tuning2 PLL5 TUN2 REG 0x003C PLLS tuning2 Reserved OSC24M CFG REG 0x0050 OSC24M control CPU_AHB_APB0_CFG_REG 0x0054 CPU AHB and APBO divide ratio APB1_CLK_DIV_REG 0x0058 APBI clock dividor AXI GATING REG 0x005C AXI module clock gating AHB GATING REGO 0x0060 AHB module clock gating 0 AHB GATING REGI 0x0064 AHB module clock gating 1 APBO GATING REG 0x0068 APBO module clock gating APB1 GATING REG 0x006C APBI module clock gating NAND SCLK CFG REG 0x0080 0x0084 SD0 CLK REG 0x0088 SD1 CLK REG 0x008C SD2 CLK REG 0x0090 SD3 CLK REG 0x0094 TS CLK REG 0x0098 SS CLK REG 0x009C SPIO CLK REG 0x00A0 SPI1 CLK REG 0x00A4 SPD CLK REG 0x00A8 0x00AC IRO CLK REG 0x00BO IRI CLK REG 0x00B4 IIS CLK REG 0x00B8 AC97 CLK REG 0x00BC NC 0x00CO A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 2012 04 09 36 Ou Allwinner Technology CO Ltd A10 KEYPAD CLK REG 0x00C4 NC 0x00C8 USB CLK REG 0x00CC NC SPI3 CLK REG 0x00D4 DRAM CLK REG 0x0100 BEO SCLK CFG REG 0x0104 BEO SCLK CFG REG 0x0108 FEO0 CLK REG 0x010C FE1 CLK REG 0x0110 MP CLK REG 0x0114 LCDO0 CHO CLK REG 0x0118 LCD1 CH0 CLK REG 0x011C CSI ISP C
222. LINEINL LINEINR depending on LNRDF bit 16 right select MIC1 gain stage LNRDF Line in r function define 0 Line in right channel which is independent of line in left 16 R W 0x0 channel 1 negative input of line in left channel for fully differential application LNPREG 15 13 R W Ox4 Line in pre amplifier Gain Control From 12dB to 9dB 3dB step default is 0dB MICINEN Mic loutn enable 0 disable 1 enable 12 R W 0x0 11 9 5 PA_EN PA Enable O disable enable 4 R W 0x0 DDE Headphone direct drive enable DDE 0 disable 1 enable 3 R W Ox1 COMPTEN HPCOM output protection enable 2 R W Ox1 0 protection disable 1 protection enable PTDBS HPCOM protect de bounce time setting 00 2 3ms 01 4 6ms 10 8 12ms 11 16 24ms 1 0 R W 0x0 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 263 2012 04 09 Allwinner Technology CO Ltd A10 24 2 9 DAC TX Counter register Offset 0x30 Register Name AC DAC CNT Bit Read Write Default Description TX CNT TX Sample Counter The audio sample number of sending into TXFIFO When one sample is put into TXFIFO by DMA or by host IO the TX sample counter register increases by one The TX sample counter register can be set to any initial valve at any time After been updated by the initial value the counter register should c
223. LK REG 0x0120 TVD CLK REG 0x0128 LCD0 CH1 CLK REG 0x012C LCD1 CH1 CLK REG 0x0130 CSIO CLK REG 0x0134 CSI1 CLK REG 0x0138 VE CLK REG 0x013C AUDIO CODEC CLK REG 0x0140 AVS CLK REG 0x0144 ACE CLK REG 0x0148 LVDS CLK REG 0x014C HDMI CLK REG 0x0150 MALI400 CLK REG 0x0154 6 4 CCM Register Description 6 4 1 PLL1 Core Default 0x21005000 Offset 0x00 Register Name PLL1 CFG REG Bit Read Default Description Write Hex 31 R W 0x0 PLL1_Enable 0 Disable 1 Enable The PLL1 output 24MHz N K M P The PLL1 output is for the CORECLK Note the output 24MHz N K clock must be in the range of 240MHz 2GHz if the bypass is disabled Its default is 384MHz A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 37 2012 04 09 Ou Allwinner Technology CO Ltd A10 25 R W 0x0 EXG_MODE Exchange mode 19 18 17 16 R W 0x0 PLL1_OUT_EXT_DIVP PLL1 Output external divider P The range is 1 2 4 8 12 8 R W 0x10 PLL1_FACTOR_N PLLI Factor N Factor 0 N 0 Factor 1 N 1 Factor 2 N 2 Factor 31 N 31 7 6 5 4 R W 0x0 PLL1 FACTOR K PLLI Factor K K Factor I The range is from 1 to 4 R W 0x0 SIG_DELT_PAT_IN Sigma delta pattern input R W 0x0 SIG_DELT_PAT_EN Sigma delta pattern enable 1 0 R W 0x0 PLL1 FACTOR M PLLI Factor M M Fa
224. LK_REG Bit Read Default Description Write Hex 31 R W 0x0 SCLK_GATING Gating Special Clock Max Clock 200MHz 0 Clock is OFF 1 Clock is ON This special clock Clock Source Divider N Divider M 30 26 25 24 R W 0x0 CLK_SRC_SEL Clock Source Select 00 OSC24M 01 PLL6 10 PLLS 11 23 18 17 16 R W 0x0 CLK_DIV_RATIO_N Clock pre divide ratio n The select clock source is pre divided by 2 n The divider is 1 2 4 8 15 4 3 0 R W 0x0 CLK_DIV_RATIO_M Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 54 2012 04 09 Ou Allwinner Technology CO Ltd A10 to 16 6 4 26 SS Clock Default 0x00000000 Offset 0x9C Register Name SS_CLK_REG Bit Read Default Description Write Hex 31 R W 0x0 SCLK GATING Gating Special Clock Max Clock 200MHz 0 Clock is OFF 1 Clock is ON This special clock Clock Source Divider N Divider M 30 26 25 24 R W 0x0 CLK SRC SEL Clock Source Select 00 OSC24M 01 PLL6 10 PLL5 11 23 18 17 16 R W 0x0 CLK DIV RATIO N Clock pre divide ratio n The select clock source is pre divided by 2 n The divider is 1 2 4 8 15 4 3 0 R W 0x0 CLK DIV RATIO M Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 16 6 4 27 SPIO Cl
225. LL5 TUN2 REG Bit Read Default Description Write Hex 31 R W 0x0 SIG DELT DAT EN Sigma delta pattern enable 30 29 R W 0x0 SPR_FREQ_MODE Spread Frequency Mode 00 DC 0 01 DC 1 10 Triangular 11 awmode 28 20 R W 0x0 WAVE_STEP A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 44 2012 04 09 Ou Allwinner Technology CO Ltd A10 Wave step 19 18 17 R W 0x0 FREQ Frequency 00 31 5KHz 01 32KHz 10 32 5KHz 11 33KHz 16 0 R W 0x0 WAVE_BOT Wave Bottom 6 4 12 OSC24M Default 0x00138013 Offset 0x50 Register Name OSC24M CFG REG Bit Read Default Description Write Hex 31 24 R W 0x0 Reserved 23 21 17 R W Ox1 PLL IN PWR SEL PLL Input Power Select 0 2 5v 1 3 3v 16 R W Ox1 LDO EN LDO Enable 0 Disable 1 Enable 15 R W Ox1 PLL BIAS EN PLL Bias Enable 0 disable 1 enable 14 5 3 2 1 R W Ox1 OSC24M GSM OSC24M GSM 0 R W Ox1 OSC24M EN OSC24M Enable 0 Disable 1 Enable 6 4 13 CPU AHB APB0 Clock Ratio Default 0x00010010 Offset 0x54 Register Name CPU AHB APBO CFG REG Bit Read Default Description Write Hex A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 45 2012 04 09 Ou Allwinner Technology CO Ltd A10
226. Ltd A10 4 Ax e SAS Audio_PLL i l 2 giz Qt T l i M BCLK Clock Register Divide APB MCLK y 128x24 DS DS SCLK PCM CLK x24 r o SR Ai a gt bits Engine RX FIFO DS LRC PCM SYNC Y M a N VW DS SDO PCM OUT 4 64x24 bits di TX FIFO lt gt PCM PCM gt DS SDI PCM IN Codec Engine T Figure22 1 Digital Audio Interface System Block Diagram 22 2 Digital Audio Interface Timing Diagram I28 LRC Lett Cf finnel Right fannel 28 SOLK f j jj j Gs SDO SDI MSB X ff tse ff ms X ff 088 f Standard 2S Timing Diagram Figure 22 2 DS Timing Diagram I28 LRC Left d knce Right fannel I28 SCLK H Ga SDO SDI MSB LSB MSB X TSB Left justified l2S Timing Diagram Figure 22 3 I2S Left justified Timing Diagram A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 219 2012 04 09 Ou Allwinner Technology CO Ltd A10 G LRC A Left Channel A A Right Channel es so fj jj jj jj Ga SDO SDI A MSB LSB A MSB LSB Right justified 2S Timing Diagram Figure 22 4 DS Right justified Timing Diagram PCM SYNC 2 Clocks PCM CLK PCM OUT 1 2 3 4 5 6 7 8 PCM N E i X 2 3 X 4 5
227. M 30 26 25 24 R W 0x0 CLK SRC SEL Clock Source Select 0 OSC24M 1 2 LOSC clock 32KHz 3 23 18 17 16 R W 0x0 CLK RATIO N Clock pre divide ratio n The select clock source is pre divided by 2 n The divider is 1 2 4 8 15 5 4 0 R W Oxlf CLK RATIO M Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 32 6 4 35 NC Clock Default 0x00000000 Offset 0xC8 Register Name NC Bit Read Default Description Write Hex 31 R W 0x0 SCLK GATING Gating Special Clock 0 Clock is OFF 1 Clock is ON 30 25 24 R W 0x0 CLK SRC GATING A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 60 2012 04 09 Ou Allwinner Technology CO Ltd A10 Clock Source Select 0 PLL6 for NC 100MHz 1 External Clock 23 18 17 16 15 5 o LD om o o LD om 4 0 6 4 36 USB Clock Default 0x00000000 Offset 0xCC Register Name USB_CLK_REG Bit Read Default Description Write Hex 31 10 9 8 R W 0x0 SCLK GATING USBPHY Gating Special Clock for USB PHY0 1 2 0 Clock is OFF 1 Clock is ON 7 3 2 R W 0x0 USBPHY2_RST USB PHY2 Reset Control 0 Reset valid 1 Reset invalid 1 R W 0x0 USBPHY1_RST USB PHY 1 Reset Control 0 Reset valid 1 Reset invalid 0 R W 0x0 USBPHYO RST U
228. M 30 R W 0x0 CSII RST CSII Reset 0 reset valid 1 reset invalid 29 27 26 24 R W 0x0 Clock Source Select 000 OSC24M 001 PLL3 1X 010 PLL7 1X Ol1 100 101 PLL3 2X 110 PLL7 2X 111 23 18 17 16 15 5 4 0 R W 0x0 CLK DIV RATIO M A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 71 2012 04 09 Ou Allwinner Technology CO Ltd A10 Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 32 6 4 52 VE Clock Default 0x00000000 Offset 0x13C Register Name VE_CLK_REG Bit Read Default Description Write Hex 31 R W 0x0 SCLK_GATING Gating the Special clock for VE 0 mask 1 pass Its clock source is the PLL4 output This special clock Clock Source Divider N 30 19 18 16 R W 0x0 CLK_DIV_RATIO_N Clock pre divide ratio N The select clock source is pre divided by n 1 The divider is from 1 to 8 15 1 0 R W 0x0 VE_RST VE Reset 0 reset valid 1 reset invalid 6 4 53 Audio Codec Clock Default 0x00000000 Offset 0x140 Register Name AUDIO CODEC CLK REG Bit Read Default Description Write Hex 31 R W 0x0 SCLK GATING Gating Special Clock 0 Clock is OFF 1 Clock is ON This special clock 2 PLL2 output 30 26 25 24 23 18 17 16 15 4
229. Note Timer current value is a 32 bit down counter from interval value to 0 This register can be read correctly if the PCLK is faster than 2 TimerFreq TimerFreq TimerClkSource pre scale 10 3 12 Timer 3 Control Register Default 0x00000000 Offset 0x40 Register Name TMR3_CTRL_REG Bit Read Write Default Hex Description 31 5 4 R W 0x0 TMR3_MODE Timer 3 mode 0 Continous mode When interval value reached the timer will not disable automatically 1 Single mode When interval value reached the timer will disable automatically 3 2 R W 0x0 TMR3_CLK_PRES Select the pre scale of timer 3 clock source Timer3 clock source is the losc 00 16 01 32 10 64 11 R W 0x0 TMR3_EN Timer 3 Enable 0 Disable 1 Enable Note the time between the timer disabled and enabled should be larger than 2 Tcycles Tcycles Timer clock source pre scale 10 3 13 Timer 3 Interval Value Offset 0x44 Register Name TMR3_INTV_VALUE_REG Bit Read Default Description Write Hex A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 93 2012 04 09 Ou Allwinner Technology CO Ltd A10 31 0 R W X TMR3 INTV VALUE Timer 3 Interval Value 10 3 14 Timer 4 Control Register Default 0x00000004 Offset 0x50 Register Name TMR4 CTRL REG
230. O 2 output buffer B address register Offset Address 0X0124 Register Name CSIO C1 F2 BUFB REG Bit Read Default Description Write Hex 31 00 R W CIF2 BUFB TI CRI 31 6 24 CSI Channel 1 output buffer control register Offset Address 0X0128 Register Name CSIO C1 BUF CTL REG Bit Read Default Description Write Hex R W DBN Buffer selected at next storing for CSI 0 Next buffer selection is buffer A 1 Next buffer selection is buffer B DBS output buffer selected status 0 Selected output buffer A A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 352 2012 04 09 Allwinner Technology CO Ltd A10 1 Selected output buffer B DBE Double buffer mode enable 0 disable 1 enable If the double buffer mode is disabled the buffer A will be always selected by CSI module Offset Address 0X012C Register Name CSIO C1 BUF STA REG Read Default Description Write Hex LUM STATIS luminance statistical value When frame done interrupt flag come value is ready and will last until next frame done Video capture in progress Indicates the CSI is capturing video image data multiple frames The bit is set at the start of the first frame after enabling video capture When software disables video capture it clears itself after the last pixel of the current frame is captured SCAP STA Still capture in progress Indicates the CSI is capturing still image data single
231. OM FB DDE HPCOM VMICEN 200 ohm I V MIC O AAN 7 AN MICIOUTP N MIC1 2 O 94 GAIN amp MIX 12dB to 9dB 3dB step LINEINL R C G apie lineinL lineinR when LNRDF for differential application FMINL R C 4 5dB 3dB 1 5dB dB 1 5dB 3dB 4 54B 6dB E 4 5dB 3dB 1 5dB 0dB Ss 1 5dB 3dB 4 5dB dB 28 74 E 3 83 3 s STEREO WS MICILS MICIRS I MIC2LS LNOS FMOS MIC2RS PAEN PAVOL i PAMUTE MIXPAS DACMIXS HPOUTL R OG DAC 63 STEP VOLUME From 0dB to 62dB A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 2012 04 09 PREGI MICI O gt gt MICOI 32dB 35dB 38dB 41dB MICO1 MICO2 32dB 35dB 38dB 41dB me G gt MICO2 a i When ADCIS 000 ADCINL LINEINL ADCINR LINEINR or ADCINL ADCINR LINEINL LINEINR depending on LNRDF ADCINL FMINL ADCINR FMINR SYSTEM ADCINR MICOL CINR MICO2 BUS ADCINR MICO2 ADCINR MICOI MICO2 L MIXOUTL ADCINR MIXOUTR When ADCIS 111 ADCINL LINEINL or LINEINL LINEINR depending on LNRDF ADCINR MICO1 ADCG ADC MIXEN DACPAS 254 Ou Allwinner Technology CO Ltd A10 24 2 Audio Codec Register List Module Name
232. ON This special clock 1 Special Clock 1 Source 14 12 11 R W 0x0 SCLK1_SRC_SEL Special Clock 1 Source Select 0 Special Clock 2 1 Speical Clock 2 divide by 2 10 4 3 0 R W 0x0 CLK DIV RATIO M Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 16 6 4 50 CSI 0 Clock Default 0x00000000 Offset 0x134 Register Name CSIO CLK REG Bit Read Default Description Write Hex 31 R W 0x0 SCLK GATING Gating Special Clock 0 Clock is OFF 1 Clock is ON This special clock Clock Source Divider M 30 R W 0x0 CSIO RST CSIO Reset 0 reset valid 1 reset invalid 29 27 26 24 R W 0x0 CLK SRC SEL Clock Source Select 000 OSC24M A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 70 2012 04 09 Ou Allwinner Technology CO Ltd A10 001 PLL3 1X 010 PLL7 1X 011 100 101 PLL3 2X 110 PLL7 2X 111 23 18 17 16 15 5 4 0 CLK DIV RATIO M Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 32 6 4 51 CSI 1 Clock Default 0x00000000 Offset 0x138 Register Name CSI1 CLK REG Bit Read Default Description Write Hex 31 R W 0x0 SCLK GATING Gating Special Clock 0 Clock is OFF 1 Clock is ON This special clock Clock Source Divider
233. PATA interrupt VE 53 0x00D4 VE interrupt SS 54 0x00D8 Security System interrupt EMAC 55 0x00DC EMAC interrupt 56 Reserved 57 HDMI 58 0x00E8 HDMI interrupt TVE 0 1 59 Ox00EC TV encoder 0 1 interrupt ACE 60 0x00F0 ACE interrupt TVD 61 Ox00F4 TV decoder interrupt PS2 0 62 0x00F8 PS2 0 interrupt PS2 1 63 0x00FC PS2 1 interrupt USB 3 64 0x100 USB 3 wakeup connect disconnect interrupt USB 4 65 0x104 USB 4 wakeup connect disconnect interrupt PLE PERFMU 66 0x108 PLE on non secure transfers interrupt PLE on secure transfer interrupt PLE error interrupt Performance monitor interrupt Timer 4 67 0x010C Timer 4 interrupt Timer 5 68 0x0110 Timer 5 interrupt GPU GP 69 0x0114 GPU GPMMU 70 0x0118 GPU PPO 71 Ox011C GPU PPMMUO 72 0x0120 GPU PMU 73 0x0124 GPU RSVO 74 0x0128 GPU RSVI 75 0x012C GPU RSV2 76 0x0130 GPU RSV3 TI 0x0134 GPU RSV4 78 0x0138 GPU RSV5 79 0x013C GPU RSV6 80 0x0140 11 3 Interrupt Register List Module Name Base Address INTC 0x01C20400 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 2012 04 09 111 Ou Allwinner Technology CO Ltd A10 Register Name Offset Description INTC_VECTOR_REG 0x0000 Interrupt Vector INTC_BASE_ADDR_REG 0x0004 Interrupt Base Address NMI INT CTRL REG 0x000C Interrupt Control INTC IRQ PEND_REGO 0x0010 I
234. PEND Normal DMA 2 Half Transfer Interrupt Pending clear it 0 No effect 1 Pending Set I to the bit will R W 0x0 NDMA1 END IRQ PEND Normal DMA 1 End Transfer Interrupt Pending clear it 0 No effect 1 Pending Set I to the bit will R W 0x0 NDMA1 HF IRQ PEND Normal DMA 1 Half Transfer Interrupt Pending clear it 0 No effect 1 Pending Set I to the bit will R W 0x0 NDMAO_END_IRQ_ PEND Normal DMA 0 End Transfer Interrupt Pending clear it 0 No effect 1 Pending Set 1 to the bit will R W 0x0 NDMAO_HF_IRQ PEND Normal DMA 0 Half Transfer Interrupt Pending clear it 0 No effect 1 Pending Set I to the bit will 12 3 3 NDMA Auto Gating Register Default 0x00000000 Offset 0x08 Register Name NDMA AUTO GAT REG Default Value 0x0000 0000 Bit Read Default Description Write Hex A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 2012 04 09 140 Ou Allwinner Technology CO Ltd A10 31 17 l 16 R W 0x0 NDMA Auto Clock Gating bit 0 NDMA auto clock gating enable 1 NDMA auto clock gating disable If NDMA works in continous mode this bit should be set to 1 15 0 12 3 4 Normal DMA Configuration Register Default 0x00000000 Offset Register Name NDMA CTRL REG 0x100 N 0x20 N 0 1 2 3 4 5 6 7 Bi
235. PL mee FD PD Frame done CD PD Capture done 31 6 54 CSI Channel 3 horizontal size register Offset Address 0X0340 Register Name CSIO C3 HSIZE REG A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 364 2012 04 09 Ou Allwinner Technology CO Ltd A10 Read Default Description Write Hex EE Le 28 16 R W HOR LEN Horizontal pixel clock length Valid pixel clocks of a line ha uu 12 00 R W HOR_START Horizontal pixel clock start Pixel data is valid from this clock 31 6 55 CSI Channel 3 vertical size register Offset Address 0X0344 Register Name CSIO C3 VSIZE REG Read Default Description Write Hex m prr E 28 16 R W VER_LEN Vertical line length Valid line number of a frame na pp Mmm 12 00 R W VER_START Vertical line start data is valid from this line 31 6 56 CSI Channel 3 buffer length register Offset Address 0X0348 Register Name CSIO C3 BUF LEN REG Read Default Description Write Hex sf 1 12 00 R W BUF LEN Buffer length of a line Unit is byte It is the max of the 3 FIFOs 31 6 57 ISP Enable register Offset Address 0X400 Register Name ISP FE EN REG Read Default Description Write Hex Bar A R W ISP FE INIT ISP initial bit Write 1 to this bit to start and will be cleared by hardware n we wrsemw A10 User Manual V1 20 Copyright 2011 2012 Allwinner Tech
236. PORTO 0 INTC 1 RIC amp ALARM 2 3 4 5 6 I mom m I o mom I IT 7 8 3 TZPC Register List Module Name Base Address TZPC 0x01C23400 Register Name Offset Description TZPC_ROSIZE_REG 0x0000 TZPC ROSIZE register TZPC DECPORTO STA REG 0x0004 TZPC Decode Port Status TZPC DECPORTO SET REG 0x0008 TZPC Decode Port Set TZPC DECPORTO CLR REG 0x000C TZPC Decode Por Clear CPU CTRL REG 0x0020 CPU Control Register A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 78 2012 04 09 Ou Allwinner Technology CO Ltd A10 8 4 TZPC Register 8 4 1 TZPC ROSIZE Register Default 0x00000010 Offset 0x00 Register Name TZPC_ROSIZE_REG Bit Read Default Description Write Hex 31 10 9 0 R 0x10 SEC RAM SIZE Secure RAM region size in 4KB step 0x000 no secure region 0x001 4KB secure region 0x002 8KB secure region 0x003 12KB secure region 0x004 16KB secure region 0x005 20KB secure region Ox1FF 2044KB secure region 0x200 or above sets the entire RAM to secure regardless of size 8 4 2 TZPC DECPORTOStatus Register Default 0x00000000 Offset 0x04 Register Name TZPC DECPORTO STA REG Bit Read Default Description Write Hex 31 8
237. R W 0 110 Reserved 111 Reserved 11 PG2 SELECT 000 Input 001 Output 010 TS1 SYNC 011 CSI HSYNC 100 SDC1 DO 101 Reserved 10 8 R W 0 110 Reserved 111 Reserved 7 PG1 SELECT 000 Input 001 Output 010 TS1 ERR 011 CSI CK 100 SDC1 CLK 101 Reserved 6 4 R W 0 110 Reserved 111 Reserved PGO SELECT 000 Input 001 Output 010 TS1 CLK 011 CSI1 PCK 100 SDC1_CMD 101 Reserved 2 0 R W 0 110 Reserved 111 Reserved 30 3 56 PG Configure Register 1 Offset 0xDC Register Name PG CFG1 Default Value 0x0000 0000 Bit Read Write Default Description 31 7 15 PG11 SELECT 000 Input 001 Output 010 TS1_D7 011 CSI1 Di 14 12 R W 0 100 UART4 RX 101 CSIO D15 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 2012 04 09 317 Ou Allwinner Technology CO Ltd A10 110 Reserved 111 Reserved 11 PG10_SELECT 000 Input 001 Output 010 TS1_D6 011 CSI1 D6 100 UART4 TX 101 CSIO_D14 10 8 R W 0 110 Reserved 111 Reserved 7 PG9 SELECT 000 Input 001 Output 010 TS1 D5 011 CSI D5 100 UART3 CTS 101 CSIO_D13 6 4 R W 0 110 Reserved 111 Reserved PG8 SELECT 000 Input 001 Output 010 TS1_D4 011 CSI DA 100 UART3 RTS 101 CSIO_D12 2 0 R W 0 110 Reserved 111 Reserved 30 3 57 PG Configure Register 2 Register Name
238. R W C2F1 BUER FIFO 1 output buffer B address 31 6 35 CSI Channel 2 FIFO 2 output buffer A address register Offset Address 0X0220 Register Name CSIO C2 F2 BUFA REG Bit Read Default Description Write Hex 31 00 R W C2F2 BUFA FIFO 2 output buffer A address 31 6 36 CSI Channel 2 FIFO 2 output buffer B address register Offset Address 0X0224 Register Name CSIO C2 F2 BUFB REG Bit Read Default Description Write Hex 31 00 R W C2F2 BUER TI CRI 31 6 37 CSI Channel 2 output buffer control register Offset Address 0X0228 Register Name CSIO C2 BUF CTL REG Bit Read Default Description Write Hex 02 R W DBN Buffer selected at next storing for CSI 0 Next buffer selection is buffer A 1 Next buffer selection is buffer B DBS output buffer selected status 0 Selected output buffer A 1 Selected output buffer B DBE Double buffer mode enable 0 disable 1 enable If the double buffer mode is disabled the buffer A will be always selected by CSI module A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 357 2012 04 09 Allwinner Technology CO Ltd A10 31 6 38 CSI Channel 2 status register Offset Address 0X022C Register Name CSIO C2 BUF STA REG Read Default Description Write Hex LUM STATIS luminance statistical value When frame done interrupt flag come value is ready and will last until next frame done Video capture in progress Indicates the
239. RGB4444 to ARGB8888 ARGB1555 to ARGB8888 RGB565 to ARGB8888 MONO 1 2 4 8bpp to ARGB8888 MONO to ARGB mode each A R G B channel is same A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 2012 04 09 All MP output Format 448 Allwinner Technology CO Ltd A10 b7 b6 b5 b4 b3 b2 bl bo b7 b6 b5 b4 b3 ba b bo 1 bit to 8 bits 2 bit to 8 bits b3 b2 bl bo b4 b3 ba bl bo 4 bits to 8 bits 5 bits to 8 bits b5 b4 b3 b2 bl b0 ES ms Input Formatter Rule 6 bits to 8 bits Output formatter rule ARGB8888 to ARGB4444 ARGB8888 to ARGB1555 ARGB8888 to RGB565 The low significant bits cut rule Above the transform mode the low significant bits will be cut off if the round function is enabled reference the following illustration b7 b6 b5 b4 b3 b2 bl b0 Na I IIfb2 1 and Vs 0B11111 Na Vs If b2 1 and Vs OBIII11 Vs Vsl Output Formatter Round Rule illustration ARGB8888 to MONO1 2 4 8bpp In this mode the color space converter 2 should be enabled the output channel 0 Y component data will be write back Reference the Ou
240. RL_REG Bit Read Default Description Write Hex 31 16 W 0x0 Reserved 15 R W 0x0 CLK32K_AUTO_SWT_PEND CLK32K auto switch pending 0 no effect 1 auto switch pending 14 R W Ox1 CLK32K AUTO SWT EN CLK32K auto switch enable 0 Disable 1 Enable 13 10 9 R W 0x0 ALM_DDHHMMSS_ACCE ALARM DD HH MM SS access After writing the ALARM DD HH MM SS register this bit is set and it will be cleared until the real writing operation is finished 8 R W 0x0 RTC HHMMSS ACCE RTC HH MM SS access After writing the RTC HH MM SS register this bit is set and it will be cleared until the real writing operation is finished After writing the RTC YY MM DD register the Y Y MM DD register A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 101 2012 04 09 Allwinner Technology CO Ltd A10 will be refreshed for at most one second R W 0x0 RTC_YYMMDD_ACCE RTC YY MM DD access After writing the RTC YY MM DD register this bit is set and it will be cleared until the real writing operation is finished After writing the RTC YY MM DD register the YY MM DD register will be refreshed for at most one second 6 4 3 2 R W 0x0 EXT_LOSC_GSM External 32768Hz Crystal GSM 00 low 01 10 11 high R W 0x0 OSC32K_SRC_SEL OSC32KHz Clock source Select 0 Internal 32khz 1 External 32 768KHz O
241. RQ_EN Dedicated DMA 2 End Transfer Interrupt Enable 0 Disable 1 Enable 20 R W 0x0 DDMA2 HF IRQ EN Dedicated DMA 2 Half Transfer Interrupt Enable 0 Disable 1 Enable 19 R W 0x0 DDMA1 END IRQ EN Dedicated DMA 1 End Transfer Interrupt Enable 0 Disable 1 Enable 18 R W 0x0 DDMA1 HF IRQ EN Dedicated DMA 1 Half Transfer Interrupt Enable 0 Disable 1 Enable 17 R W 0x0 DDMA0_END_IRQ_EN Dedicated DMA 0 End Transfer Interrupt Enable 0 Disable 1 Enable 16 R W 0x0 DDMAO HF IRQ EN Dedicated DMA 0 Half Transfer Interrupt Enable 0 Disable 1 Enable 15 R W 0x0 NDMA7_END_IRQ_EN Normal DMA 7 End Transfer Interrupt Enable 0 Disable 1 Enable 14 R W 0x0 NDMA7 HF IRQ EN Normal DMA 7 Half Transfer Interrupt Enable 0 Disable 1 Enable 13 R W 0x0 NDMA6_END_IRQ_EN Normal DMA 6 End Transfer Interrupt Enable 0 Disable 1 Enable 12 R W 0x0 NDMA6_HF_IRQ_EN Normal DMA 6 Half Transfer Interrupt Enable 0 Disable 1 Enable 11 R W 0x0 NDMA5 END IRQ EN Normal DMA 5 End Transfer Interrupt Enable 0 Disable 1 Enable 10 R W 0x0 NDMA5 HF IRQ EN Normal DMA 5 Half Transfer Interrupt Enable 0 Disable 1 Enable R W 0x0 NDMA4 END IRQ EN A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved
242. SB PHYO Reset Control 0 Reset valid 1 Reset invalid 6 4 37 SPI3 Clock Default 0x00000000 Offset 0xD4 Register Name SPI3 CLK REG Bit Read Default Description Write Hex 31 R W 0x0 SCLK_GATING Gating Special Clock Max Clock 200MHz 0 Clock is OFF 1 Clock is ON A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 61 2012 04 09 Allwinner Technology CO Ltd A10 This special clock Clock Source Divider N Divider M 30 26 25 24 R W 0x0 CLK_SRC_SEL Clock Source Select 00 OSC24M 01 PLL6 10 PLLS 11 23 18 17 16 R W 0x0 CLK_DIV_RATIO_N Clock pre divide ratio n The select clock source is pre divided by 2 n The divider is 1 2 4 8 15 4 3 0 R W 0x0 CLK_DIV_RATIO_M Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 16 6 4 38 DRAM CLK Default 0x00000000 Offset 0x100 Register Name DRAM_CLK_REG Bit Read Default Description Write Hex 31 30 29 R W 0x0 ACE_DCLK_GATING Gating DRAM Clock for ACE 0 mask 1 pass 28 R W 0x0 DE_MP_DCLK_GATING Gating DRAM Clock for DE_MP 0 mask 1 pass 27 R W 0x0 BE1_DCLK_GATING Gating DRAM Clock for DE_BE1 0 mask 1 pass 26 R W 0x0 BE0_DCLK_GATING Gating DRAM Clock for DE_BEO 0 mask 1 pass 25 R W 0x0 F
243. SC Note Any bit of 9 7 is set the RTC HH MM SS YY MM DD and ALARM DD HH MM SS register can t be written 10 3 30 RTC YY MM DD Default 0x00000000 Offset 0x104 Register Name RTC YY MM DD REG Bit Read Default Description Write Hex 31 R W 0x0 RTC_TEST_MODE_CTRL RTC TEST Mode Control bit 30 R W 0x0 RTC_SIM_CTRL RTC Simulation Control bit 29 23 22 R W 0x0 LEAP Leap Year 0 not 1 Leap year This bit can not set by hardware It should be set or clear by software 21 16 R W X YEAR Year Range from 0 63 15 12 11 8 R W X MONTH Month Range from 1 12 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 102 2012 04 09 Allwinner Technology CO Ltd A10 7 5 4 0 R W X DAY Day Range from 1 31 10 3 31 RTC HH MM SS Offset 0x108 Register Name RTC HH MM SS REG Bit Read Default Description Write Hex 31 29 R W 0x0 WE NO Week number 000 Monday 001 Tuesday 010 Wednesday 011 Thursday 100 Friday 101 Saturday 110 Sunday 111 2821 20 16 R W D HOUR Range from 0 23 15 14 13 8 R W D MINUTE Range from 0 59 7 6 5 0 R W D SECOND Range from 0 59 10 3 32 Alarm Counter DD HH MM SS Offset 0x10C Register Name DD HH MM SS REG Bit Read Default Description Writ
244. SI D3 11 PH2 SELECT 000 Input 001 Output 10 8 R W 0 010 LCD1_D2 011 ATAA2 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 2012 04 09 320 Ou Allwinner Technology CO Ltd A10 100 UART3 RTS 101 Reserved 110 EINT2 111 CS D2 7 PH1 SELECT 000 Input 001 Output 010 LCD1 DI 011 ATAAI 100 UART3_RX 101 Reserved 6 4 R W 0 110 EINT1 111 CSI DI PHO SELECT 000 Input 001 Output 010 LCD1 DO 011 ATAAO 100 UART3 TX 101 Reserved 2 0 R W 0 110 EINTO 111 CSI1 DO 30 3 65 PH Configure Register 1 Register Name DH CFG1 Offset 0x100 Default Value 0x0000 0000 Bit Read Write Default Description 31 PH15_SELECT 000 Input 001 Output 010 LCD1_D15 011 ATADII 100 KP_INS 101 SMC_VPPPP 30 28 R W 0 110 EINT15 111 CSI1 D15 27 PH14 SELECT 000 Input 001 Output 010 LCD1 D14 011 ATAD10 100 KP IN4 101 SMC VPPEN 26 24 R W 0 110 EINT14 111 CSI D14 23 PH13 SELECT 000 Input 001 Output 010 LCD1_D13 011 ATAD9 100 PS2 SDAI 101 SMC RST 22 20 R W 0 110 EINT13 111 CSI D13 19 PH12 SELECT 000 Input 001 Output 18 16 R W 0 010 LCD1_D12 011 ATAD8 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 2012 04 09 321 Ou Allwinner Technology CO Ltd 100 PS2 SCKI A10 101 Reserved
245. Select SPI_SS and SPI Clock SPI_SCLK Support Dedicated DMA 17 2 SPI Timing Diagram The serial peripheral interface master uses the SPI SCLK signal to transfer data in and out of the shift register Data is clocked using any one of four programmable clock phase and polarity combinations During Phase 0 Polarity 0 and Phase 1 Polarity 1 operations output data changes on the falling clock edge and input data is shifted in on the rising edge During Phase 1 Polarity 0 and Phase 0 Polarity 1 operations output data changes on the rising edges of the clock and is shifted in on falling edges The POL defines the signal polarity when SPI SCLK is in idle state The SPI SCLK is high level when POL is 1 and it is low level when POL is 0 The PHA decides whether the leading edge of SPI SCLK is used for setup or sample data The leading edge is used for setup data when PHA is 1 and for sample data when PHA is 0 The four kind of modes are listed below SPI Mode POL PHA Leading Edge Trailing Edge 0 0 0 Rising Sample Falling Setup 1 0 1 Rising Setup Falling Sample 2 1 0 Falling Sample Rising Setup 3 1 1 Failing Setup Rising Sample A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 163 2012 04 09 Ou Allwinner Technology CO Ltd A10 SPI_SCLK Mode 0 SPI_SCLK Mode 2 SPI MOSI SPI MISO SPI SS Sample MOSI MISO
246. TCONO IO TRI REG 0x008C TCONO IO control register TCONI CTL REG 0x0090 TCONI control register TCONI BASICO REG 0x0094 TCONI basic timing registerO TCONI BASICI REG 0x0098 TCONI basic timing register 1 TCONI BASIC2 REG 0x009C TCONI basic timing register2 TCON1_BASIC3_REG 0x00A0 TCONI basic timing register3 TCONI BASIC4 REG 0x00A4 TCONI basic timing register4 TCONI BASIC5 REG 0x00A8 TCONI basic timing register5 TCONI IO POL REG OxOOFO TCONI IO polarity register TCONI IO TRI REG OxOOF4 TCONI IO control register TCON ECC FIFO REG 0x00F8 TCON ECC FIFO register Reserved A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 2012 04 09 397 Ou Allwinner Technology CO Ltd A10 TCON_CEU_CTL_REG 0x0100 TCON CEU control register TCON_CEU_MUL_RR_REG 0x0110 TCON CEU coefficient register TCON_CEU_MUL_RG_REG 0x0114 TCON CEU coefficient register TCON_CEU_MUL_RB_REG 0x0118 TCON CEU coefficient register2 TCON_CEU_ADD_RC_REG 0x011C TCON CEU coefficient register3 TCON CEU MUL GR REG 0x0120 TCON CEU coefficient register4 TCON CEU MUL GG REG 0x0124 TCON CEU coefficient register5 TCON CEU MUL GB REG 0x0128 TCON CEU coefficient register TCON CEU ADD GC REG 0x012C TCON CEU coefficient register7 TCON CEU MUL BR REG 0x0130 TCON CEU coefficient register8 TCON CEU MUL BG REG 0x0134 TCON CEU
247. TCON_Gamma_En 0 disable 1 enable 29 1 R W IO Map Sel 0 TCONO 1 TCONI Note this bit determined which IO INV IO TRI are valid 33 4 2 TCON global interrupt register0 Offset 0x004 Register Name TCON GINTO REG Bit Read Default Description Write Hex 31 R W 0 TCONO Vb Int En 0 disable 1 enable 30 R W 0 TCONI Vb Int En 0 disable 1 enable 29 R W 0 TCONO Line Int En 0 disable 1 enable 28 R W 0 TCONI Line Int En 0 disable 1 enable 27 16 15 R W 0 TCONO Vb Int Flag Asserted during vertical no display period every frame Write 0 to clear it 14 R W 0 TCON1_Vb_Int_Flag Asserted during vertical no display period every frame Write 0 to clear it 13 R W 0 TCONO Line Int Flag trigger when SYO match the current TCONO scan line Write 0 to clear it 12 R W 0 TCONI Line Int Flag trigger when SY1 match the current TCONI scan line Write 0 to clear it 11 0 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 399 2012 04 09 Allwinner Technology CO Ltd A10 33 4 3 TCON global interrupt register1 Offset 0x008 Register Name TCON_GINT1_REG Bit Read Default Description Write Hex 31 27 26 16 R W 0 TCONO Line Int Num scan line for TCONO line trigger including inactive lines Setting it for the specified line for trigger0 Note SYO
248. TE EE 310 30 3 38 PE Confipure Register 1 retro prp HR ERIS kannik 311 30 3 39 PE Configure Register 2 retient erem ee ret i eee e rsen ree ros p uva 312 30 3 40 PE Configure Register 3 ettet reiten rre eee Oh Pn E RVE erae Ea een aaa ao Ea iais 312 30 3 41 PE Data Register eee tenete eene ee tee ir ede ue vedette vedere de 312 30 3 42 PE Multi Driving Register iier ber Fed e edd eter ede iere ias 312 30 3 43 PE Multi Driving Register 1 nice erri erre en ree ae Eed ri a Pur EN 313 30 3 44 PE Pull Regist r EE 313 30 3 45 PE Pull Register le er EES 313 30 3 46 PF Configure Register Oleissoa oi neen n tna unasdedbvest twas ewespnanveas Fee y YR edge 313 30 3 47 PE Contigure Register EE 314 30 3 48 PF Configure E 314 30 3 49 PF Configure Register 3 eene neret tr te rente Hebe rre Rete ee eo eve eo e eaves 315 30 3 50 PF D ta Register isset em ner EROR e ree tape e PR Ce tap CERES 315 30 3 51 PE Multi Driving Register O esis iiec fett etre rrr erret lr deed 315 30 3 52 PE Multi Driving Register L saranoina da ree oaa ENEE 315 30 3 53 PF Pull Register Q i ere entr e I eee reete eee e eee aeree EE n e Debe Ee 316 30 3 54 PE Pull Register E 316 30 3 55 PG Conhigure Register NEE 316 30 3 56 PG Configure Register erret rte Rr eee OR LERRA SEE Ek Xe aep kar aero aa eno irae 317 30 3 57 PG Conhgure Register 2 endete eter red i eve dire tee deret den 318 30 3 58 PG Configure Register 3
249. TO auto Transfer Mode If it s 1 all the valid data during this frame are write to panel Note This bit is sampled by Vsync 27 R W FLUSH direct transfer mode If it s enabled FIFO1 is regardless of the HV timing pixels data keep being transferred unless the input FIFO was empty Data output rate control by DCLK 26 R W DA pin Al value in 8080 mode auto flash states 25 R W CA pin Al value in 8080 mode WR RD execute 24 R W VSYNC_Cs_Sel 0 CS 1 VSYNC 23 Wr_Flag O write operation is finishing 1 write operation is pending 22 Rd_Flag O read operation is finishing l read operation is pending 21 0 33 4 15 TCONO cpu panel write data register Offset 0x064 Register Name TCONO0 CPU WR REG Bit Read Default Description Write Hex 31 24 23 0 W 0 Data Wr data write on 8080 bus launch a write operation on 8080 bus 33 4 16 TCONO cpu panel read data register0 Offset 0x068 Register Name TCONO CPU RD0 REG Bit Read Default Description Write Hex 31 24 23 0 R Data_Rd0 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 407 2012 04 09 Ou Allwinner Technology CO Ltd A10 data read on 8080 bus launch a new read operation on 8080 bus 33 4 17 TCONO cpu panel read data register 1 Offset
250. Technology All Rights Reserved 392 2012 04 09 Allwinner Technology CO Ltd A10 32 6 13 CSI Channel 0 interrupt enable register Offset Address 0X0030 Register Name CSI1 INT EN REG Bit Read Default Description Write Hex 07 R W VS_INT_EN vsync flag The bit is set when vsync come And at this time load the buffer address for the coming frame So after this irq come change the buffer address could only effect next frame R W HB OF INT EN Hblank FIFO overflow The bit is set when 3 FIFOs still overflow after the hblank FIFO2 OF INT EN FIFO 2 overflow The bit is set when the FIFO 2 become overflow FIFO1 OF INT EN FIFO 1 overflow The bit is set when the FIFO 1 become overflow FIFOO OF INT EN FIFO 0 overflow The bit is set when the FIFO 0 become overflow CD INT EN Capture done Indicates the CSI has completed capturing the image data For still capture the bit is set when one frame data has been wrote to buffer For video capture the bit is set when the last frame has been wrote to buffer after video capture has been disabled For CCIR656 interface if the output format is frame planar YCbCr 420 mode the frame end means the field2 end the other frame end e FD INT EN Frame done Indicates the CSI has finished capturing an image frame Applies to video capture mode The bit is set after each completed frame capturing data is wrote to buffer as long as video capture remains enabled means
251. V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 2012 04 09 120 Ou Allwinner Technology CO Ltd A10 Offset 0x80 Register Name INTC_PRIO_REGO LevelO 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x2 level 2 Level3 0x3 level 3 highest priority 15 14 R W 0x0 IRQ 7 Priority Set priority level for IRQ bit 7 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x2 level 2 Level3 0x3 level 3 highest priority 13 12 R W 0x0 IRQ 6 Priority Set priority level for IRQ bit 6 Level0 0x0 level 0 lowest priority Levell 0x1 level 1 Level2 0x2 level 2 Level3 0x3 level 3 highest priority 11 10 R W 0x0 IRQ 5 Priority Set priority level for IRQ bit 5 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x2 level 2 Level3 0x3 level 3 highest priority 9 8 R W 0x0 IRQ 4 Priority Set priority level for IRQ 4 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x2 level 2 Level3 0x3 level 3 highest priority 7 6 R W 0x0 IRQ 3 Priority Set priority level for IRQ bit 3 Level0 0x0 level 0 lowest priority Levell 0x1 level 1 Level2 Ox1 level 2 Level3 Ox1 level 3 highest priority 5 4 R W 0x0 IRQ 2 Priority Set priority level for IRQ bit 2 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 Ox1 level 2 Level3 0x1 level 3 highest priority 3 2 R W
252. W Default Description rite Hex 0 Disable scaler ignore the whole scaling setting and the data flow will by pass the module 1 Enable scaling function 35 5 14 Scaling output size register Offset 0x84 Register Name MP_SCAOUTSIZE_REG Bit Read W Default Description rite Hex aap E 28 16 R W SCA OUTHEIGHT Output height The output height The value of these bits add 1 The minimum output height is 8 pixels nap ppm S 12 0 R W SCA_OUTWIDTH Output width The output width The value of these bits add 1 The minimum output width is 16 pixels A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 469 2012 04 09 Ou Allwinner Technology CO Ltd A10 35 5 15 Scaler horizontal scaling factor register Offset 0x88 Register Name MP_SCAHORFCT_REG SCA_HORINTFCT The integer part of the horizontal scaling ratio the horizontal scaling ratio input width output width 15 00 R W SCA_HORFRAFCT The fractional part of the horizontal scaling ratio the horizontal scaling ratio input width output width The input width is the memory block width of respective iDMA channel 35 5 16 Scaler vertical scaling factor register Offset 0x8C Register Name MP_SCAVERFCT_REG Bit Read W Default Description 23 16 R W SCA VERINTFCT The integer part of the vertical scaling ratio the vertical scaling ratio input height output
253. When set this bit indicates that RXFIFO has overflowed Writing 1 to this bit clears it 0 RXFIFO is available 5 R W 0 1 RXFIFO has overflowed RF34 RXFIFO 3 4 Full This bit is set when the RXFIFO is 3 4 full Writing 1 to 4 R W 0 this bit clears it A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 171 2012 04 09 Ou Allwinner Technology CO Ltd A10 0 Not 3 4 Full 1 3 4 Full RF14 RXFIFO 1 4 Full This bit is set when the RXFIFO is 1 4 full Writing 1 to this bit clears it 0 Not 1 4 Full 3 R W 0 1 1 4 Full RF RXFIFO Full This bit is set when the RXFIFO is full Writing 1 to this bit clears it 0 Not Full 2 R W 0 1 Full RHF RXFIFO Half Full This bit is set if the RXFIFO is half full 4 words in RXFIFO Writing 1 to this bit clears it 0 Less than 4 words are stored in RXFIFO 1 R W 0 1 Four or more words are available in RXFIFO RR RXFIFO Ready This bit is set any time there is one or more words stored in RXFIFO 1 words Writing 1 to this bit clears it 0 No valid data in RXFIFO 0 R W 0 1 More than 1 word in RXFIFO 17 4 6 SPI DMA Control Register Register Name SPI DMACTL Offset 0x14 Default Value 0x0000_0000 Bit Read Write Default Description 31 13 TF_EMP34_DMA TXFIFO3 4 Empty DMA Request Enable 0 Disable 12 R W 0 1 Enable TF EMP14 DMA TXFIFO 1
254. Write Default Description 31 18 17 R W 0 FTX Write 1 to flush TX FIFO self clear to 0 16 R W FRX Write 1 to flush RX FIFO self clear to 0 15 8 R W 0x30 TXTL TX FIFO empty Trigger Level Interrupt and DMA request trigger level for TX FIFO normal condition Trigger Level TXTL 7 3 R W OxOF RXTL RX FIFO Trigger Level Interrupt and DMA request trigger level for RX FIFO normal condition Trigger Level ZRXTL 1 TXIM TX FIFO Input Mode ModeoO 1 0 Valid data at the MSB of AC TXFIFO register 1 Valid data at the LSB of AC TXFIFO register Example for 18 bits transmitted audio sample Mode 0 FIFO 1 19 0 TXFIFO 31 14 2 hO Mode 1 FIFO 1 19 0 TXFIFO 17 0 2 h0 1 0 R W RXOM RX FIFO Output Mode Mode 0 1 2 3 00 Expanding 0 at LSB of AC RXFIFO register 01 Expanding received sample sign bit at MSB of AC RXFIFO register 10 Truncating received samples at high half word of AC RXFIFO register and low half word of AC FIFO register is filled by 0 11 Truncating received samples at low half word of AC RXFIFO register and high half word of AC FIFO register is expanded by its sigh bit Example for 18 bits received audio sample Mode RXFIFO 31 0 FIFO O 19 2 14 h0j Mode l RXFIFO 31 0 1 FIFO_O 19 FIFO_O 19 2 Mode 2 RXFIFO 31 0 FIFO O 19 4 16 h0 Mode 3 RXFIFO 31 0 16 FIFO_O 19
255. X Channel Mapping Register 22 4 Digital Audio Interface Register Description 22 4 1 Digital Audio Control Register Offset 0x00 Register Name DA_CTL Default Value 0x0000_0000 Bit Read Write Default Description 31 12 11 R W SDO3_EN 0 Disable 1 Enable 10 R W SDO2_EN 0 Disable 1 Enable SDO1_EN 0 Disable 1 Enable SDOO EN 0 Disable Enable ASS Audio sample select when TX FIFO under run 0 Sending zero 1 Sending last audio sample 2 R W MS Master Slave Select 0 Master 1 Slave R W PCM A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 2012 04 09 221 Ou Allwinner Technology CO Ltd A10 0 DS Interface 1 PCM Interface LOOP Loop back test 0 Normal mode 1 Loop back test When set 1 connecting the SDO with the SDI in Master mode TXEN Transmitter Block Enable 0 Disable 1 Enable RXEN Receiver Block Enable 0 Disable 1 Enable 0 R W GEN Globe Enable A disable on this bit overrides any other block or channel enables and flushes all FIFOs 0 Disable 1 Enable 22 4 2 Digital Audio Format Register 0 Offset 0x04 Register Name DA FATO Default Value 0x0000 000C Bit Read Write Default Description 31 8 LRCP Left Right Clock Parity 0 Normal 1
256. XEI EN TX FIFO Empty Interrupt Enable 0 Disable 1 Enable R W RX_DRQ RX FIFO Data Available DRQ Enable When set to 1 RX FIFO DMA Request is asserted if Data is available in RX FIFO 0 Disable 1 Enable R W RXOI EN RX FIFO Overrun Interrupt Enable 0 Disable 1 Enable R W RXAI EN RX FIFO Data Available Interrupt Enable 0 Disable 1 Enable 23 7 10 AC97 Interrupt status Register Offset 0x24 Register Name AC_ISTA Default Value 0x0000_0010 Bit Read Write Default Description 31 10 9 R W 0 CODEC_GPIO_INT Codec GPIO interrupt 0 No pending IRQ 1 Codec GPIO interrupt 8 R W 0 CR_INT Codec Ready pending Interrupt 0 No pending IRQ 1 Codec Ready Pending Interrupt Write 1 to clear this interrupt 7 6 R W 0 TXU_INT A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 251 2012 04 09 Ou Allwinner Technology CO Ltd A10 TX FIFO Under run Pending Interrupt 0 No pending IRQ 1 FIFO Under run Pending Interrupt Write 1 to clear this interrupt R W TXO_INT TX FIFO Overrun Pending Interrupt 0 No Pending IRQ 1 FIFO Overrun Pending Interrupt Write 1 to clear this interrupt R W TXE_INT TX FIFO Empty Pending Interrupt 0 No Pending IRQ 1 FIFO Empty Pending Interrupt Write 1 to clear this interrupt or automatically clear if int
257. _0000 Bit Read Write Default Description 31 0 30 3 5 PA Data Register Register Name PA_DAT Offset 0x10 Default Value 0x0000_0000 Bit Read Write Default Description 31 18 PA_DAT If the port is configured as input the corresponding bit is the pin state If the port is configured as output the pin state is the same as the corresponding bit The read bit value is the value setup by software If the port is configured as functional pin the undefined value will be 17 0 R W 0 read A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 291 2012 04 09 Ou Allwinner Technology CO Ltd A10 30 3 6 PA Multi Driving Register 0 Register Name PA DRVO Offset 0x14 Default Value 0x5555_ 5555 Bit Read Write Default Description PA_DRV PA n Multi Driving Select n 0 15 21 1 21 00 Level 0 01 Level 1 G 0 15 R W Ox1 10 Level 2 11 Level 3 30 3 7 PA Multi Driving Register 1 Register Name DA DRVI1 Offset 0x18 Default Value 0x0000 0005 Bit Read Write Default Description 31 4 PA DRV PA n Multi Driving Select n 16 17 21 1 21 00 Level 0 01 Level 1 120 1 R W Ox1 10 Level 2 11 Level 3 30 3 8 PA Pull Register 0 Register Name PA PULLO Offset 0x1C Default Value 0x0000_0000 Bit Read Write Default Description PA
258. _PULL PA n Pull up down Select n 0 15 21 1 2i 00 Pull up down disable O1 Pull up 1 0 15 R W 0x0 10 Pull down 11 Reserved 30 3 9 PA Pull Register 1 Register Name PA_PULL1 Offset 0x20 Default Value 0x0000 0000 Bit Read Write Default Description 31 4 PA PULL 21 1 21 PA n Pull up down Select n 2 16 17 120 1 R W 0x0 00 Pull up down disable 01 Pull up enable A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 292 2012 04 09 Ou Allwinner Technology CO Ltd A10 10 Pull down 11 Reserved 30 3 10 PB Configure Register 0 Register Name PB_CFG0 Offset 0x24 Default Value 0x0000 0000 Bit Read Write Default Description 31 PB7 SELECT 000 Input 001 Output 010 DS LRCK 011 AC97 SYNC 100 Reserved 101 Reserved 30 28 R W 0 110 Reserved 111 Reserved 27 PB6_SELECT 000 Input 001 Output 010 DS BCLK 011 AC97 BCLK 100 Reserved 101 Reserved 26 24 R W 0 110 Reserved 111 Reserved 23 PB5 SELECT 000 Input 001 Output 010 DS MCLK 011 AC97 MCLK 100 Reserved 101 Reserved 22 20 R W 0 110 Reserved 111 Reserved 19 PB4 SELECT 000 Input 001 Output 010 IRO RX 011 Reserved 100 Reserved 101 Reserved 18 16 R W 0 110 Reserved 111 Reserved 15 PB3 SELECT 000 Input 001 Output 010 IRO TX 011 Reserved 100 NC
259. a Aa R fb A fb 1 A a G Ga Aa G b A fb I A a B B_a A_a Bfb A fb 1 A a 35 3 8 Scaling UV channel pre scaling If the input data format is YUV422 or YUV411 or YUV420 the UV component will be pre scaling the output data will be YUV444 by the pre scaling transition So the color space convert 0 and color space convert lalways receive the YUV444 format data Pre scaling rule The following PO Pn means the U or V component of pixels YUV422 Ignore Y component UV component use linear interpolation in x direction UV component ignore y direction Input Line n PO Pl P2 SW SE Pn 3 Pn 2 Pn 1 Pn Pre Scaling Output Line n PO ir P1 CHA P2 do I rli Pn V The UV component pre scaling rule of YUV422 to YUV444 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 455 2012 04 09 e Allwinner Technology CO Ltd A10 YUV 411 Ignore Y component UV component use linear interpolation in x direction UV component ignore y direction Input Line n P Pi P2 4 PO 3 P1 1 PO 1 P1 3 P1 34P2 1 Output Line n PO A Ten 4 PI n n Pn 2 Pn 1 at r 4 Pn 1 Pn Py 2 3 Pn 1f1 Pni2 14Pn 1 5 n n 1 34Pn p T 1 Pn The UV c
260. able 1 R W 0 1 Enable ERBFI Enable Received Data Available Interrupt This is used to enable disable the generation of Received Data Available Interrupt and the Character Timeout Interrupt if in FIFO mode and FIFOs enabled These are the second highest priority interrupts 0 Disable 0 R W 0 1 Enable 18 4 6 UART Interrupt Identity Register Register Name UART_ITR Offset 0x08 Default Value 0x0000_0000 Bit Read Write Default Description 31 8 FEFLAG FIFOs Enable Flag This is used to indicate whether the FIFOs are enabled or disabled 00 Disable 7 6 R 0 11 Enable 5 4 IID Interrupt ID This indicates the highest priority pending interrupt which can be one of the following types 0000 modem status 0001 no interrupt pending 3 0 R Ox1 0010 THR empty A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 183 2012 04 09 Ou Allwinner Technology CO Ltd 0100 received data available 0110 receiver line status 0111 busy detect 1100 character timeout A10 Bit 3 indicates an interrupt can only occur when the FIFOs are enabled and used to distinguish a Character Timeout condition interrupt Interr Priority Interrupt Interrupt Source Interrupt Reset upt ID Level Type 0001 None None 0110 Highest Receiver line Overrun parity
261. ain 8 bit unsigned fraction Default value is 139 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 437 2012 04 09 Ou Allwinner Technology CO Ltd A10 7 0 Cb_Gain Specify the Cb color gain 8 bit unsigned fraction Default value is 139 34 4 18 TV Encoder Sync and VBI Level Register Offset 0x11C Register Name TVE 11C REG Bit Read Default Description Write Hex 31 26 25 16 R W 48 Sync Level Specify the sync pulse level setting 8 bit unsigned integer Allowed range is 0 to ABlankLevel 1 or VBlankLevel 1 whichever is smaller Default value is 72 15 10 9 0 R W 128 VBlank Level Specify the blank level setting for non active lines 10 bit unsigned integer Allow range 0 to 1023 Default value is hex128 dec296 34 4 19 TV Encoder White Level Register Offset 0x120 Register Name TVE 120 REG Bit Read Default Description Write Hex 31 26 25 16 R W leg HD Sync Breezeway Level Specify the breezeway level setting 10 bit unsigned integer Allowed range is 0 to 1023 Default value is 1e8 15 10 9 0 R W 320 White_Level Specify the white level setting 10 bit unsigned integer Allowed range is black_level 1 or vbi_blank_level 1 whichever is greater to 1023 Default value is 800 34 4 20 TV Encoder Video Active Line Register Offset 0x
262. al V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 104 2012 04 09 Ou Allwinner Technology CO Ltd A10 set to 1 R W 0x0 WK5_ALM_EN Week 5 Saturday Alarm Enable 0 Disable 1 Enable If this bit is set to 1 only when the Alarm Week HH MM SS register valid bits is equal to RTC HH MM SS register and the register RTC HH MM SS bit 31 29 is 5 the week 5 alarm irq pending bit will be set to 1 R W 0x0 WK4_ALM_EN Week 4 Friday Alarm Enable 0 Disable 1 Enable If this bit is set to 1 only when the Alarm Week HH MM SS register valid bits is equal to RTC HH MM SS register and the register RTC HH MM SS bit 31 29 is 4 the week 4 alarm irq pending bit will be set to 1 R W 0x0 WK3_ALM_EN Week 3 Thursday Alarm Enable 0 Disable 1 Enable If this bit is set to 1 only when the Alarm Week HH MM SS register valid bits is equal to RTC HH MM SS register and the register RTC HH MM SS bit 31 29 is 3 the week 3 alarm irq pending bit will be set to 1 R W 0x0 WK2_ALM_EN Week 2 Wednesday Alarm Enable 0 Disable 1 Enable If this bit is set to 1 only when the Alarm Week HH MM SS register valid bits is equal to RTC HH MM SS register and the register RTC HH MM SS bit 31 29 is 2 the week 2 alarm irq pending bit will be set to 1 R W 0x0 WK1_ALM_EN Week 1 Tuesday Alarm Enable
263. alue 0x0000_0000 Bit Read Write Default Description 31 16 15 PE11_SELECT 000 Input 001 Output 010 TSO_D7 011 CSIO_D7 100 Reserved 101 Reserved 14 12 R W 0 110 Reserved 111 Reserved 11 PE10 SELECT 000 Input 001 Output 010 TSO_D6 011 CSIO_D6 100 Reserved 101 Reserved 10 8 R W 0 110 Reserved 111 Reserved 7 PE9_SELECT 000 Input 001 Output 010 TSO_D5 011 CSIO D5 100 Reserved 101 Reserved 6 4 R W 0 110 Reserved 111 Reserved PE8 SELECT 000 Input 001 Output 2 0 R W 0 010 TSO_D4 011 CSIO D4 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 311 2012 04 09 Ou Allwinner Technology CO Ltd A10 100 Reserved 101 Reserved 110 Reserved 111 Reserved 30 3 39 PE Configure Register 2 Offset 0x98 Register Name PE_CFG2 Default Value 0x0000_0000 Bit Read Write Default Description 31 0 30 3 40 PE Configure Register 3 Offset 0x98 Register Name PE_CFG2 Default Value 0x0000_0000 Bit Read Write Default Description 31 0 30 3 41 PE Data Register Offset 0xA0 Register Name PE_DAT Default Value 0x0000_0000 Bit Read Write Default Description 31 12 11 0 R W PE_DAT If the port is configured as input the corresponding bit is the pin state If the port is configured as
264. and channel 2 mix not logic NOD6 CTL Index 0 node6 setting channel 0 and channel 1 and channel 2 mix logic 0 and l or 2 xor 3 add in byte 4 add in word 32bit 5 multiply in byte 6 multiply in word 32bit 7 channel 0 mix channel 1 then sub channel 2 in byte 8 channel 0 mix channel 1 then sub channel 2 in word 32bit Other Reserved NOD5 CTL Index 0 node5 setting channel 0 and channel 1 mix not logic O by pass not NOD4 CTL Index 0 node4 setting channel 0 and channel 1 mix logic 0 and l or 2 xor 3 add in byte 4 add in word 32bit 5 multiply in byte 6 multiply in word 32bit 7 channel 0 sub channel 1 in byte 8 channel 0 sub channel 1 in word 32bit Other Reserved NOD3_CTL Index 0 node3 setting channel 2 not logic A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 473 2012 04 09 Ou Allwinner Technology CO Ltd A10 NOD2_CTL Index 0 node2 setting channel 1 not logic 0 by pass not NODI CTL Index 0 nodel setting channel 0 not logic 0 by pass not NODO0 CTL Index 0 nodeO setting sorting control 0 012 1 021 2 102 3 120 4 201 5 210 Other Reserved Note the result of the add or multiply operation will select the high 8 byte operation or 32bits word operation 35 5 21 ROP channel 3 index 1 control table setting register Offset
265. anual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 231 2012 04 09 Ou Allwinner Technology CO Ltd A10 22 20 R W 5 TX_CH5_MAP TX Channel5 Mapping 000 1 sample 001 2 sample 010 3 sample 011 4 sample 100 5 sample 101 6 sample 110 7 sample 111 8 sample 19 18 16 R W 4 TX CHA MAP TX Channel4 Mapping 000 1 sample 001 2 sample 010 3 sample 011 4 sample 100 5 sample 101 6 sample 110 7 sample 111 8 sample 15 14 12 R W 3 TX_CH3_MAP TX Channel3 Mapping 000 1 sample 001 2 sample 010 3 sample 011 4 sample 100 5 sample 101 6 sample 110 7 sample 111 8 sample 11 10 8 R W 2 TX CH2 MAP TX Channel2 Mapping 000 1 sample 001 2 sample 010 3 sample 011 4 sample 100 5 sample 101 6 sample 110 7 sample 111 g sample A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 232 2012 04 09 Allwinner Technology CO Ltd A10 vi 6 4 R W 1 TX_CH1_MAP TX Channell Mapping 000 1 sample 001 2 sample 010 3 sample 011 4 sample 100 5 sample 101 6 sample 110 7 sample 111 8 sample 2 0 R W 0 TX CHO MAP TX Channel Mapping 000 1 sample 001 2 sample 010 3 sample 011 4 sample 100 5 sample 101 6 sample 110 7 sample 111 8 sample 22 4 15
266. ar YCbCr A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 349 2012 04 09 Allwinner Technology CO Ltd A10 420 mode the frame end means the field2 end the other frame end means field end 31 6 14 CSI Channel 0 interrupt status register Offset Address 0X0034 Register Name CSIO C0 INT STA REG Bit Read Default Description Write Hex VS PD 31 08 07 GE p vsync flag HB OF PD P ee muCERPD 4 FIFO2 OF PD Porno o FIFO1 OF PD Promo R W R W R W R W o R FIFOO OF PD FD PD CD PD Capture done 31 6 15 CSI Channel 0 horizontal size register Offset Address 0X0040 Register Name CSIO C0 HSIZE REG Bit Read Default Description Write Hex HOR LEN Horizontal pixel clock length Valid pixel clocks of a line HOR START Horizontal pixel clock start Pixel data is valid from this clock um a a EREEE 15 13 12 00 R 2816 R W 31 6 16 CSI Channel 0 vertical size register Offset Address 0X0044 Register Name CSIO C0 VSIZE REG A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 350 2012 04 09 Ou Allwinner Technology CO Ltd A10 Read Default Description Write Hex E EE 28 16 R W VER_LEN Vertical line length Valid line number of a frame ha ud SSCS 12 00 R W VER START Vertical line start data is valid from this line 31 6 17 CSI Channel 0 buffer length register Offset Add
267. ars the PE bit 1 R OE Overrun Error This occurs if a new data character was received before the previous data was read In the non FIFO mode the OE bit is set when a new character arrives A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 191 2012 04 09 Ou Allwinner Technology CO Ltd A10 in the receiver before the previous character was read from the RBR When this happens the data in the RBR is overwritten In the FIFO mode an overrun error occurs when the FIFO is full and a new character arrives at the receiver The data in the FIFO is retained and the data in the receive shift register is lost 0 no overrun error 1 overrun error Reading the LSR clears the OE bit DR Data Ready This is used to indicate that the receiver contains at least one character in the RBR or the receiver FIFO 0 no data ready 1 data ready This bit is cleared when the RBR is read in non FIFO mode or when the receiver FIFO is empty in FIFO 0 R 0 mode 18 4 11 UART Modem Status Register Register Name UART MSR Offset 0x18 Default Value 0x0000 0000 Bit Read Write Default Description 31 8 DCD Line State of Data Carrier Detect This is used to indicate the current state of the modem control line ded n This bit is the complement of dcd_n When the Data Carrier Detect input ded n is asserted it is an indication that the
268. as follows baud rate serial clock freq 16 divisor Note that with the Divisor Latch Registers DLL and DLH set to zero the baud clock is disabled and no serial communications occur Also once the DLH is set at least 8 clock cycles of the slowest UART clock should be allowed to pass before transmitting or 7 0 R W 0 receiving data 18 4 5 UART Interrupt Enable Register Register Name UART IER Offset 0x04 Default Value 0x0000 0000 Bit Read Write Default Description 31 8 PTIME Programmable THRE Interrupt Mode Enable This is used to enable disable the generation of THRE Interrupt 0 Disable R W 1 Enable 6 4 EDSSI Enable Modem Status Interrupt This is used to enable disable the generation of Modem Status Interrupt This is the fourth highest priority interrupt 0 Disable 3 R W 0 1 Enable ELSI 2 R W 0 Enable Receiver Line Status Interrupt A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 182 2012 04 09 Ou Allwinner Technology CO Ltd A10 This is used to enable disable the generation of Receiver Line Status Interrupt This is the highest priority interrupt 0 Disable 1 Enable ETBEI Enable Transmit Holding Register Empty Interrupt This is used to enable disable the generation of Transmitter Holding Register Empty Interrupt This is the third highest priority interrupt 0 Dis
269. ation Revision 1 0a id mud Enhanced Host Controller A high speed controller standard that is publicly Interface specified Low Resolution Analog to A module which can transfer analog signal to 15 LRADC Digital Converter digital signal 16 TP Touch Panel Controller A Human Machine Interactive Interface A data stream defined by ISO13818 1 which 17 TS Transport Stream consists of one or more programs with video and audio data A vehicle bus standard designed to allow microcontrollers and devices to communicate 18 CAN Controller area network with each other within a vehicle without a host computer An old computer bus interface for connecting Parallel Advanced Technology 19 PATA hard disk drivers optical drivers and compact Attachment flash card A computer bus interface for connecting host Serial Advanced Technology 20 SATA bus adapters to mass storage devices such as Attachment hard disk drives and optical drives The hardware block that interfaces with different image sensor interfaces and provides a 21 CSI Camera Sensor Interface standard output that can be used for subsequent image processing High Definition Multimedia A compact audio video interface for 22 HDMI Interface transmitting uncompressed digital data A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 3 2012 04 09 Ou Allwinner Technology CO Ltd A10 Table of Contents Revision HISCOLY P ENE 1 Technical
270. bit 0 No effect 1 Pending alarm counter value is reached If alarm counter irq enable is set to 1 the pending bit will be sent to the interrupt controller 10 3 37 Timer General Purpose Register 0 Offset 0x120 Register Name TMR GP DATA REGO Bit Read Default Description Write Hex 31 0 R W x TMR_GP_DATAO Data 31 0 Note timer general purpose register 0 1 2 3 value can be stored if the RTCVDD is larger than 1 0v A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 106 2012 04 09 Allwinner Technology CO Ltd A10 10 3 38 Timer General Purpose Register 1 Offset 0x124 Register Name TMR GP DATA REG Bit Read Default Description Write Hex 31 0 R W x TMR_GP_DATA1 Data 31 0 10 3 39 Timer General Purpose Register 2 Offset 0x128 Register Name TMR_GP_DATA_REG2 Bit Read Default Description Write Hex 31 0 R W x TMR_GP_DATA2 Data 31 0 10 3 40 Timer General Purpose Register 3 Offset 0x12C Register Name TMR_GP_DATA_REG3 Bit Read Default Description Write Hex 31 0 R W x TMR_GP_DATA3 Data 31 0 10 3 41 CPU Config Register Default 0x000000C0 Offset 0x13C Register Name CPU_CFG_REG Bit Read Default Description Write Hex 31 8 7 6 R 0x3 Reserve to 2 bl1 5 2 1 R W 0x0 L1 DATA CACHE INVA EN E
271. bit overrides any other block or channel enables and flushes all FIFOs 0 Disable 1 Enable 19 4 2 IR Transmitter Configure Register Register Name IR TXCTL Offset 0x04 Default Value 0x0000 0000 Bit Read Write Default Description 31 6 PCF Packet Complete by FIFO This bit determines how a packet is completed if a TX FIFO underrun event occurs Do not write software intentionally to cause underrun events However if due to erroneous conditions the value of this bit selects between two recovery modes Set the PCF based on system and upper layer IrDA protocol requirements 0 Send CRC and STO fields Send CRC16 and STO for MIR or CRC32 and STO for FIR 1 Send packet abort symbol R W 0 Send 7 b111 1111 for MIR or 8 b0000 0000 for FIR 4 SIP Transmit SIP Writing 1 to this bit produces a Serial Infrared Interaction Pulse transmission Writing a 0 to this bit is ignored This bit is always read as 0 If this bit is set while in the middle of the transfer the packet will be ignored by IRDA controller Don t Set SIP bit in the middle of transfer A SIP is defined as a 1 6us optical pulse of the transmitter followed by a 7 1us off time of the transmitter It simulates a start pulse causing the potentially interfering system to 3 R W 0 listen for at least 500 ms TPPI Transmit Pulse Polarity Invert 0 Not invert transmit pulse 2 R W 1 1 Invert
272. c 1 1 cts_n input is asserted logic 0 In Loopback Mode MCR 4 1 CTS is the same as MCR 1 RTS DDCD Delta Data Carrier Detect This is used to indicate that the modem control line ded n has changed since the last time the MSR was read 0 no change on ded n since last read of MSR 1 change on ded n since last read of MSR Reading the MSR clears the DDCD bit Note Ff the DDCD bit is not set and the ded n signal is asserted low and a reset occurs software or otherwise then the DDCD bit is set when the reset is removed if the dcd n signal remains asserted 2 R TERI Trailing Edge Ring Indicator This is used to indicate that a change on the input ri n from an active low to an inactive high state has occurred since the last time the MSR was read 0 no change on ri n since last read of MSR A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 193 2012 04 09 Ou Allwinner Technology CO Ltd A10 1 change on ri_n since last read of MSR Reading the MSR clears the TERI bit DDSR Delta Data Set Ready This is used to indicate that the modem control line dsr_n has changed since the last time the MSR was read 0 no change on dsr_n since last read of MSR 1 change on dsr_n since last read of MSR Reading the MSR clears the DDSR bit In Loopback Mode MCR 4 1 DDSR reflects changes on MCR 0 DTR Note If the DDSR bit is not s
273. cation Ver2 00 Consumer Electronics Advanced Transport Architecture CE ATA version 1 1 Multimedia Cards MMC version 4 2 JEDEC Standard JESD84 44 Embedded Multimedia Card eMMC Card Product Standard A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 152 2012 04 09 Allwinner Technology CO Ltd A10 16 Two Wire Interface 16 1 Overview This 2 Wire Controller is designed to be used as an interface between CPU host and the serial 2 Wire bus It can support all the standard 2 Wire transfer including Slave and Master The communication to the 2 Wire bus is carried out on a byte wise basis using interrupt or polled handshaking This 2 Wire Controller can be operated in standard mode 100K bps or fast mode supporting data rate up to 400K bps Multiple Masters and 10 bit addressing Mode are supported for this specified application General Call Addressing is also supported in Slave mode The 2 Wire Controller includes the following features Software programmable for Slave or Master Support Repeated START signal Support Multi master systems Support 10 bit addressing with 2 Wire bus Performs arbitration and clock synchronization Own address and General Call address detection Interrupt on address detection Supports speeds up to 400Kbits s fast mode Support operation from a wide range of input clock frequencies 16 2 TWI Controller Timing Diagram Data transferred ar
274. chnology CO Ltd A10 20 USB OTG Controller 20 1 Overview The USB OTG is dual role controller which supports both Host and device functions It can also be configured as a Host only or Device only controller full compliant with the USB 2 0 Specification It can support high speed HS 480 Mbps full speed FS 12 Mbps and low speed LS 1 5 Mbps transfers in Host mode It can support high speed HS 480 Mbps and full speed FS 12 Mbps in Device mode The USB2 0 OTG controller SIE includes the following features B Complies with USB 2 0 Specification E Support High Speed HS 480 Mbps Full Speed FS 12 Mbps and Low Speed LS 1 5 Mbps in Host mode and support High Speed HS 480 Mbps Full Speed FS 12 Mbps in Device mode W 64 Byte Endpoint 0 for Control Transfer EndpointO M Support up to 5 User Configurable Endpoints for Bulk Isochronous Control and Interrupt bi directional transfers Endpointl Endpoint2 Endpoint3 Endpoint4 Endpoint5 20 2 USB OTG Timing Diagram Please refer USB2 0 Specification and its On The Go Supplement to the USB 2 0 Specification A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 215 2012 04 09 Ou Allwinner Technology CO Ltd A10 21 USB Host Controller 21 1 Overview USB Host Controller is fully compliant with the USB 2 0 specification Enhanced Host Controller Interface EHCI Specification Revision 1 0 and the Open Hos
275. ck Source Divider N Divider M 30 26 25 24 R W 0x0 CLK SRC SEL Clock Source Select 00 OSC24M 01 PLL6 10 PLLS 11 23 18 17 16 R W 0x0 CLK_DIV_RATIO_N Clock pre divide ratio n The select clock source is pre divided by 2 n The divider is 1 2 4 8 15 4 3 0 R W 0x0 CLK_DIV_RATIO_M Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 16 6 4 24 SD MMC 3 Clock Default 0x00000000 Offset 0x94 Register Name SD3_CLK_REG Bit Read Default Description Write Hex 31 R W 0x0 SCLK_GATING Gating Special Clock Max Clock 200MHz 0 Clock is OFF 1 Clock is ON This special clock Clock Source Divider N Divider M 30 26 25 24 R W 0x0 CLK_SRC_SEL A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 53 2012 04 09 Ou Allwinner Technology CO Ltd A10 Clock Source Select 00 OSC24M 01 PLL6 10 PLL5 11 23 18 17 16 R W 0x0 CLK_DIV_RATIO_N Clock pre divide ratio n The select clock source is pre divided by 2 n The divider is 1 2 4 8 15 4 3 0 R W 0x0 CLK_DIV_RATIO_M Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 16 6 4 25 TS Clock Default 0x00000000 Offset 0x98 Register Name TS_C
276. coefficient register9 TCON CEU MUL BB REG 0x0138 TCON CEU coefficient register10 TCON CEU ADD BC REG 0x013C TCON CEU coefficient register11 TCON CEU RANGE R REG 0x0140 TCON CEU coefficient register12 TCON CEU RANGE G REG 0x0144 TCON CEU coefficient register13 TCON CEU RANGE B REG 0x0148 TCON CEU coefficient register14 TCONI FILL CTL REG 0x0300 TCONI fill data control register TCONI FILL BEGO REG 0x0304 TCONI fill data begin registerO TCONI FILL ENDO REG 0x0308 TCONI fill data end registerO TCONI FILL DATAO REG 0x030C TCONI fill data value registerO TCONI FILL BEGI REG 0x0310 TCONI fill data begin register I TCONI FILL ENDI REG 0x0314 TCONI fill data end register 1 TCONI FILL DATA1 REG 0x0318 TCONI fill data value register TCONI FILL BEG2 REG 0x031C TCONI fill data begin register2 TCONI FILL END REG 0x0320 TCONI fill data end register2 TCONI FILL DATA2 REG 0x0324 TCONI fill data value register2 TCONI GAMMA TABLE REG 0x0400 TCONI gamma table register 0x400 0x7FF 33 4 LCD TV Timing Controller registers definition 33 4 1 TCON global control register Offset 0x000 Register Name TCON GCTL REG Bit Read Default Description Write Hex 31 R W 0 TCON En 0 disable 1 enable When it s disabled the module will be reset to idle state A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 398 2012 04 09 Ou Allwinner Technology CO Ltd A10 30 R W 0
277. combined 0101 planar YUV 420 UV combined 1000 MB YUV 422 1001 MB YUV 420 When the input format is set YUV444 1100 field planar YUV 444 1101 field planar YUV 422 UV combined 1110 frame planar YUV 444 1111 frame planar YUV 422 UV combined mer a 11 10 R W FIELD SEL Field selection Applies to CCIR656 interface only 00 start capturing with field 1 O1 start capturing with field 2 10 start capturing with either field 11 reserved 09 08 R W 2 INPUT_SEQ Input data sequence only valid for Bayer mede and YUV422 mode 00 YUYV 01 YVYU 10 UYVY 11 VYUY 4 R W FPS_DS Fps down sample failed no this code 0 no down sample 1 1 2 fps only receives the first frame every 2 frames 3 R W FIELD_POL Field polarity 0 negative field 0 indicate odd field 1 indicate even 1 positive field 1 indicate odd field 0 indicate even This register is not apply to CCIR656 interface A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 388 2012 04 09 Ou Allwinner Technology CO Ltd A10 VREF_POL Vref polarity 0 negative 1 positive This register is not apply to CCIR656 interface HERF_POL Href polarity 0 negative 1 positive This register is not apply to CCIR656 interface CLK_POL Data clock type 0 active in falling edge 1 active in rising edge Offset Address 0X0008 Register Name CSI1 CAP REG Read Default Description Write Hex ee ON Video captu
278. cription 31 23 PF5_SELECT 000 Input 001 Output 010 SDCO_D2 011 Reserved 100 JTAG CK1 101 Reserved 22 20 R W Ox4 110 Reserved 111 Reserved 19 18 16 R W 0 PF4_SELECT A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 313 2012 04 09 Ou Allwinner Technology CO Ltd A10 000 Input 001 Output 010 SDCO Di 011 Reserved 100 UARTO RX 101 Reserved 110 Reserved 111 Reserved 15 PF3 SELECT 000 Input 001 Output 010 SDCO CMD O11 Reserved 100 JTAG DO 101 Reserved 14 12 R W 0x4 110 Reserved 111 Reserved 11 PF2_SELECT 000 Input 001 Output 010 SDCO_CLK 011 Reserved 100 UARTO_TX 101 Reserved 10 8 R W 0 110 Reserved 111 Reserved 7 PF1 SELECT 000 Input 001 Output 010 SDCO DO 011 Reserved 100 JTAG DII 101 Reserved 6 4 R W 0x4 110 Reserved 111 Reserved PFO_SELECT 000 Input 001 Output 010 SDCO_D1 011 Reserved 100 JTAG_MS1 101 Reserved 2 0 R W 0x4 110 Reserved 111 Reserved 30 3 47 PF Configure Register 1 Register Name PF_CFG1 Offset 0xB8 Default Value 0x0000_0000 Bit Read Write Default Description 31 0 30 3 48 PF Configure Register 2 Register Name PF_CFG2 Offset 0xBC Default Value 0x0000_0000 Bit Read Write Default Description 31 0 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology
279. ctor I The range is from 1 to 4 6 4 2 PLL2 Audio Default 0x08100010 Offset 0x08 Register Name PLL2 CFG REG Bit Read Write Default Hex Description 31 R W 0x0 PLI 2 Enable 0 Disable 1 Enable The PLL2 is for Audio PLL2 Output 24MHz N PLL2 PRE DIV PLL2 POST DIV 1X 48 N PreDiv PostDiv 2 not 50 duty 2X 48 N PreDiv 4 8X 4 50 duty 4X 48 N PreDiv 2 8X 2 50 duty 8X 48 N PreDiv not 50 duty 30 29 26 R W 0x2 PLL2 POST DIV PLL2 post dividor 3 0 0000 Ox1 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 38 2012 04 09 Ou Allwinner Technology CO Ltd A10 1111 0x10 15 14 8 R W 0x0 PLL2_Factor_N PLL2 Factor N Factor 0 N 1 Factor 1 N 1 Factor 0x7F N 0x7F 7 5 4 0 R W 0x10 PLL2 PRE DIV PLL2 pre dividor 4 0 00000 Ox1 11111 0x20 6 4 3 PLL2 Tuning Default 0x00000000 Offset 0x0C Register Name PLL2 TUN REG Bit Read Default Description Write Hex 31 R W 0x0 SIG DELT DAT EN Sigma delta pattern enable 30 29 R W 0x0 SPR_FREQ_MODE Spread Frequency Mode 00 DC 0 01 DC 1 10 Triangular 11 awmode 28 20 R W 0x0 WAVE_STEP Wave step 19 18 17 R W 0x0 FREQ Frequency 00 31 5KHz 01 32KHz 10 32 5KHz 11 33KHz 16 0 R W 0x0 WAVE_BOT Wa
280. d A10 18 UART Interface 18 1 Overview The UART is used for serial communication with a peripheral modem data carrier equipment DCE or data set Data is written from a master CPU over the APB bus to the UART and it is converted to serial form and transmitted to the destination device Serial data is also received by the UART and stored for the master CPU to read back The UART contains registers to control the character length baud rate parity generation checking and interrupt generation Although there is only one interrupt output signal from the UART there are several prioritized interrupt types that can be responsible for its assertion Each of the interrupt types can be separately enabled disabled with the control registers The UART has 16450 and 16550 modes of operation which are compatible with a range of standard software drivers In 16550 mode transmit and receive operations are both buffered by FIFOs In 16450 mode these FIFOs are disabled The UART supports word lengths from five to eight bits an optional parity bit and 1 1 or 2 stop bits and is fully programmable by an AMBA APB CPU interface A 16 bit programmable baud rate generator and an 8 bit scratch register are included together with separate transmit and receive FIFOs Eight modem control lines and a diagnostic loop back mode are provided Interrupts can be generated for a range of TX Buffer FIFO RX Buffer FIFO Modem Status and Line Status conditi
281. data full empty Others Reserved 7 5 TE TX FIFO Empty 0 TX FIFO not empty 1 TX FIFO empty by its level This bit is cleared by writing a 1 TC Transmit including the CRC and STO fields Complete 0 Transmission not completed 1 Transmission completed This bit is cleared by writing a 1 SIPE Transmitter SIP End 0 Transmission of SIP not completed 1 Transmission of SIP completed This bit is cleared by writing a 1 R W TPE Transmitter Packet End 0 Transmissions of address control and data fields not completed 1 Transmissions of address control and data fields completed This bit is cleared by writing a 1 R W TU A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 208 2012 04 09 Ou Allwinner Technology CO Ltd A10 Transmitter FIFO Under Run 0 No transmitter FIFO under run 1 Transmitter FIFO under run This bit is cleared by writing a 1 19 4 12 IR Receiver Interrupt Control Register Register Name IR_RXINT Offset 0x2C Default Value 0x0000_0000 Bit Read Write Default Description 31 12 RAL RX FIFO Available Received Byte Level for interrupt and DMA request 11 8 R W 0 TRIGGER_LEVEL RAL 1 7 6 DRQ_EN RX FIFO DMA Enable 0 Disable 1 Enable When set to 1 the Receiver FIFO DRQ is asserted if reaching RAL The DRQ is de as
282. ddress Write bit received ACK transmitted 0x70 General Call address received ACK transmitted 0x78 Arbitration lost in address as master General Call address received ACK transmitted 0x80 Data byte received after slave address received ACK transmitted 0x88 Data byte received after slave address received not ACK transmitted 0x90 Data byte received after General Call received ACK transmitted 0x98 Data byte received after General Call received not ACK transmitted OxAO0 STOP or repeated START condition received in 7 0 R OxF8 slave mode A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 158 2012 04 09 Ou Allwinner Technology CO Ltd A10 OxA8 Slave address Read bit received ACK transmitted OxBO Arbitration lost in address as master slave address Read bit received ACK transmitted OxB8 Data byte transmitted in slave mode ACK received 0xCO Data byte transmitted in slave mode ACK not received OxC8 Last byte transmitted in slave mode ACK received OxDO Second Address byte Write bit transmitted ACK received OxD8 Second Address byte Write bit transmitted ACK not received OxF8 No relevant status information INT_FLAG 0 Others Reserved 16 4 6 TWI Clock Register Offset 0x14 Register Name TWI_CCR Default Value 0x0000_0000 Bit Read Write Default Description 31 7 6 3 R W 0
283. deo Encoder enable default disable write 1 to take it out of the reset state 34 4 1TV Encoder Configuration Register Offset 0x004 Register Name TVE_004_REG Bit Read Default Description Write Hex 31 29 28 27 R W 0 DAC Src Sel 0 TV Encoder 1 LCD controller override all other TV encoder setting the DAC clock can from LCD controller 26 R W 0 DAC Control Logic Clock Sel A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 425 2012 04 09 Ou Allwinner Technology CO Ltd A10 0 Using 27M clock or 74 25M clock depend on CCU setting 1 Using 54M clock or 148 5M clock depend on CCU setting 25 R W Core_Datapath_Logic_Clock_Sel 0 Using 27M clock or 74 25M clock depend on CCU setting 1 Using 54M clock or 148 5M clock depend on CCU setting 24 R W Core_Control_Logic_Clock_Sel 0 Using 27M clock or 74 25M clock depend on CCU setting 1 Using 54M clock or 148 5M clock depend on CCU setting 23 21 20 R W Cb_Cr_Seq_For_422_Mode 0 Cb first 1 Cr first 19 R W Input Chroma Data Sampling Rate Sel 0 4 4 4 1 4 2 2 18 R W YUV RGB Output En 0 CVBS or and Y C 1 YUV or RGB Note only apply to SD interlace mode when in progressive mode output YPbPr RGB only 17 R W YC En 0 Y C is disable 1 Y C enable Note S port Video enable Selection This
284. der Notch Filter Frequency Register TVE 10C REG 0x010C TV Encoder Cb Cr Level Gain Register TVE_110_REG 0x0110 TV Encoder Tint and Color Burst Phase Register TVE 114 REG 0x0114 TV Encoder Burst Width Register TVE_118_REG 0x0118 TV Encoder Cb Cr Gain Register TVE_11C_REG 0x011C TV Encoder Sync and VBI Level Register TVE 120 REG 0x0120 TV Encoder White Level Register TVE 124 REG 0x0124 TV Encoder Video Active Line Register TVE 128 REG 0x0128 TV Encoder Video Chroma BW and CompGain Register TVE 12C REG 0x012C TV Encoder Register TVE 130 REG 0x0130 TV Encoder Re sync parameters Register TVE 134 REG 0x0134 TV Encoder Slave Parameter Register TVE 138 REG 0x0138 TV Encoder Configuration Register TVE 13C REG 0x013C TV Encoder Configuration Register TVE_200_REG 0x0200 TV Encoder MacroVision Control Register TVE 204 REG 0x0204 TV Encoder MacroVision NO N3 Register TVE 208 REG 0x0208 TV Encoder MacroVision N4 N7 Register TVE_20C_REG 0x020C TV Encoder MacroVision N8 N10 Register TVE 210 REG 0x0210 TV Encoder MacroVision N11 N12 Register A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 423 2012 04 09 Ou Allwinner Technology CO Ltd A10 TVE 214 REG 0x0214 TV Encoder MacroVision N13 N16 Register TVE 218 REG 0x0218 TV Encoder MacroVision N17 N20 Register TVE 220 REG 0x0220 TV Encoder MacroVision Plus Register TVE 220 REG 0x0224 TV Encoder Macro Vision AGC
285. der is not a full sync slave i e it is a partial sync slave or a sync master 1 Reserved A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 440 2012 04 09 Allwinner Technology CO Ltd A10 34 4 25 TV Encoder Configuration Register Offset 0x138 Register Name TVE 138 REG Bit Read Default Description Write Hex 31 9 8 R W 0 Invert_Top Field parity input signal top_field polarity selection This bit selects whether the top field is indicated by a high level of the field parity signal or by the low level The bit is applicable both when the Video Encoder is the sync master and when the Video Encoder is the sync slave 0 Top field is indicated by low level 1 Top field is indicated by high level 7 1 0 R W 0 UV_Order This bit selects if the sample order at the chroma input to the Video Encoder is Cb first i e Cb 0 Cr 0 Cb I Cr 1 or Cr first i e Cr 0 Cb 0 Cr 1 Cb 1 0 The chroma sample input order is Cb first 1 The chroma sample input order is Cr first 34 4 26 TV Encoder Configuration Register Offset 0x13C Register Name TVE 13C REG Bit Read Default Description Write Hex 31 27 26 24 R W 0 RGB Sync R G and B signals sync embedding selection These bits specify whether the sync signal is added to each of the R G and B components B 1 or not B 0 B
286. dule Name Base Address UARTO 0x01C28000 UARTI 0x01C28400 UART2 0x01C28800 UART3 0x01C28C00 UART4 0x01C29000 UARTS 0x01C29400 UART6 0x01C29800 UART7 0x01C29C00 Register Name Offset Description UART RBR 0x00 UART Receive Buffer Register UART_THR 0x00 UART Transmit Holding Register UART_DLL 0x00 UART Divisor Latch Low Register UART_DLH 0x04 UART Divisor Latch High Register UART_IER 0x04 UART Interrupt Enable Register UART IIR 0x08 UART Interrupt Identity Register A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 179 2012 04 09 Ou Allwinner Technology CO Ltd A10 UART FCR 0x08 UART FIFO Control Register UART LCR OxOC UART Line Control Register UART MCR 0x10 UART Modem Control Register UART LSR 0x14 UART Line Status Register UART MSR 0x18 UART Modem Status Register UART_SCH Ox1C UART Scratch Register UART_USR Ox7C UART Status Register UART TFL 0x80 UART Transmit FIFO Level UART RFL 0x84 UART RFL UART HALT OxA4 UART Halt TX Register 18 4 UART Register Description 18 4 1 UART Receiver Buffer Register Offset 0x00 Register Name UART RBR Default Value 0x0000 0000 Bit Read Write Default Description 31 8 7 0 R 0 RBR Receiver Buffer Register Data byte received on the serial input port sin in UART mode or the serial infrared input sir_in in infrared mode The data in this
287. e When LNRDF is 0 right select LINEINR When LNRDF is 1 right select LINEINL LINEINR LFMS Left FM to left output MP mute O mute 17 R W 0x0 1 Not mute RFMS right FM to right output MP mute 16 R W 0x0 0 mute 1 Not mute LDACLMIXS Left DAC to left output MP Mute 0 Mute 1 Not mute 15 R W 0x0 RDACRMIXS Right DAC to right output MP Mute 0 Mute 1 Not mute 14 R W 0x0 13 R W 0x0 LDACRMIXS A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 259 2012 04 09 Ou Allwinner Technology CO Ltd A10 Left DAC to right output MP Mute 0 Mute 1 Not mute MICILS MICI to output MP left channel mute 12 R W 0x0 0 mute 1 Not mute MICIRS MIC1 to output MP right channel mute 11 R W 0x0 0 mute 1 Not mute MIC2LS MIC to output MP left channel mute 0 mute 10 R W 0x0 1 Not mute MIC2RS MIC2 to output MP right channel mute 9 R W 0x0 0 mute 1 Not mute DACPAS DAC to PA Mute 0 Mute 1 Not mute 8 R W 0x0 MIXPAS Output MP to PA mute 0 Mute 1 Not mute 7 R W 0x0 PAMUTE All input source to PA mute including Output MP and Internal DAC 0 0 Mute 1 Not mute 6 R W 0x0 PAVOL 5 0 R W 0x0 PA Volume Control PAVOL Total 64 level from OdB to 62dB 1dB step mute when 000000 24 2 6 ADC FIFO Status Register Offset 0x20 R
288. e Hex 31 24 R W X DAY Range from 0 255 23 222 20 16 R W X HOUR Range from 0 23 15 14 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 103 2012 04 09 Allwinner Technology CO Ltd A10 13 8 R W D MINUTE Range from 0 59 7 6 5 0 R W D SECOND Range from 0 59 Note If the second is set to 0 it will be I second in fact 10 3 33 Alarm Week HH MM SS Offset 0x110 Register Name ALARM WK HH MM SS Bit Read Default Description Write Hex 31 21 20 16 R W X HOUR Range from 0 23 15 14 13 8 R W X MINUTE Range from 0 59 7 6 5 0 R W X SECOND Range from 0 59 10 3 34 Alarm Enable Offset 0x114 Register Name ALARM EN REG Bit Read Default Description Write Hex 31 9 8 R W 0x0 ALM CNT EN Alarm Counter Enable If this bit is set to 1 the Alarm Counter DD HH MM SS register s valid bits will down count to zero and the the alarm pending bit will be set to 1 O disable enable 7 6 R W 0x0 WK6 ALM EN Week 6 Sunday Alarm Enable 0 Disable 1 Enable If this bit is set to 1 only when the Alarm Week HH MM SS register valid bits is equal to RTC HH MM SS register and the register RTC HH MM SS bit 31 29 is 6 the week 6 alarm irq pending bit will be A10 User Manu
289. e LSR clears the BI bit In the non FIFO mode the BI indication occurs immediately and persists until the LSR is read FE Framing Error This is used to indicate the occurrence of a framing error in the receiver A framing error occurs when the receiver does not detect a valid STOP bit in the received data In the FIFO mode since the framing error is associated with a character received it is revealed when the character with the framing error is at the top of the FIFO When a framing error occurs the UART tries to resynchronize It does this by assuming that the error was due to the start bit of the next character and then continues receiving the other bit i e data and or parity and stop It should be noted that the Framing Error FE bit LSR 3 is set if a break interrupt has occurred as indicated by Break Interrupt BI bit LSR 4 0 no framing error 1 framing error Reading the LSR clears the FE bit PE Parity Error This is used to indicate the occurrence of a parity error in the receiver if the Parity Enable PEN bit LCR 3 is set In the FIFO mode since the parity error is associated with a character received it is revealed when the character with the parity error arrives at the top of the FIFO It should be noted that the Parity Error PE bit LSR 2 is set if a break interrupt has occurred as indicated by Break Interrupt BD bit LSR 4 0 no parity error 1 parity error Reading the LSR cle
290. e Pin List Port Name Width Direction Description A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 282 2012 04 09 Allwinner Technology CO Ltd A10 KP OUT 8 OUT Keypad Interface Column data KP IN 8 IN Keypad Interface Row data A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 283 2012 04 09 Ou Allwinner Technology CO Ltd A10 28 Security System 28 1 Overview The Security System SS is one encryption decryption function accelerator It supports both CPU mode and DMA mode for different application It includes the following features E Support AES DES 3DES SHA 1 MD5 ECB CBC CNT modes for AES DES 3DES 128 bits 192 bits and 256 bits key size for AES 160 bits hardware PRNG with 192 bits seed 32 words RX FIFO and 32 words TX FIFO for high speed application Support both CPU mode and DMA mode Support Interrupt A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 284 2012 04 09 Ou Allwinner Technology CO Ltd A10 29 Security ID 29 1 Overview There is one on chip EFUSE which provides 128 bit 64 bit and one 32 bit electrical fuses for security application The user can use them as root key security JTAG key and other purpose vendors configuration application It includes the following features W 128 bit electrical fuses
291. e always in a unit of 8 bit byte followed by an acknowledge bit The number of bytes that can be transmitted per transfer is unrestricted Data is transferred in serial with the MSB first Between each byte of data transfer a receiver device will hold the clock line SCL low to force the transmitter into a wait state while waiting the response from microprocessor Data transfer with acknowledge is obligatory The clock line is driven by the master all the time including the acknowledge related clock cycle except for the SCL holding between each bytes After sending each byte the transmitter releases the SDA line to allow the receiver to pull down the SDA line and send an acknowledge signal or leave it high to send a not acknowledge to the transmitter When a slave receiver doesn t acknowledge the slave address unable to receive because of no resource available the data line must be left high by the slave so that the master can then generate a STOP condition to abort the transfer Slave receiver can also indicate not to want to send more data during a transfer by leave the acknowledge signal high And the master should generate the STOP condition to abort the transfer A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 153 2012 04 09 Ou Allwinner Technology CO Ltd Below diagram provides an illustration the relation of SDA signal line and SCL signal line on the 2 Wire serial bus A1
292. e changed to alarm output if the power of I O is switched off and it s power source is RTCVDD 00 Low level sensitive 01 Negative edge trigged A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 113 2012 04 09 Ou Allwinner Technology CO Ltd A10 10 High level sensitive 11 Positive edge sensitive 11 4 5 Interrupt IRQ Pending Register 0 Default 0x00000000 Offset 0x10 Register Name INTC IRQ PEND REGO Bit Read Default Description Write Hex 31 0 R 0x0 INT IRQ SRC PENDO Interrupt Source 31 0 Pending Clear Bit 0 Corresponding interrupt is not pending 1 Corresponding interrupt is pending 11 4 6 Interrupt IRQ Pending Register 1 Default 0x00000000 Offset 0x14 Register Name INTC IRQ PEND REGI Bit Read Default Description Write Hex 31 0 R 0x0 INT IRQ SRC PENDI Interrupt Source 63 32 Pending Clear Bit 0 Corresponding interrupt is not pending 1 Corresponding interrupt is pending 11 4 7 Interrupt IRQ Pending Register 2 Default 0x00000000 Offset 0x18 Register Name INTC IRQ PEND REG2 Bit Read Default Description Write Hex 31 0 R 0x0 INT IRQ SRC PEND2 Interrupt Source 95 64 Pending Clear Bit 0 Corresponding interrupt is not pending 1 Corresponding interrupt is pending 11 4 8 Interrupt FIQ Pending Clear Register 0 Default
293. e ee EE ER TR RR REN Ede e re EEN 35 6 44 e NEE RE e e 37 6 4 1 PLLEI Core Def ult 0x21005000 Langebek Gos uda neret a en era certe 37 6 4 2 PLL2 Audio Default 0x08100010 sess eene enne enne nnne nnns 38 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 4 2012 04 09 N N Allwinner Technology CO Ltd A10 6 4 3 PLL2 Tuning Default 0x00000000 esses enne enne 39 6 4 4 PLL3 Video O Default 0x0010D063 esses enne enne 40 6 4 5 PLLA V E Default 0x21081000 eese esee eene eene nenne ener eene etnies 40 6 4 6 PLL5 DDR Default 0x11049280 ssssssssssssesseeseeeeee eene enne enne nnne nnne rennen 41 6 4 7 PLL6 NC Default Os 21O00011 enne nnnm enne nnne nnns 42 6 4 8 PLE6 Tuning Default etre etre E nte eee E cere eve E eure 43 6 4 9 PLL7 Vid o 1 Default 0x0010D0068 1i etri reete tco tne ere tn kh cna ead nno eh nena rende 43 6 4 10 PLL1 Tuning2 Default 0x00000000 cessent nennen nennen tenens 44 6 4 11 PLL5 Tuning2 Default 0x00000000 cesses nennen nennen nennen neret 44 6 4 12 OSC24M Default 0X00138013 eene enne en these nts orao eat 45 6 4 13 CPU AHB APBO Clock Ratio Default 0x00010010 seen 45 6 4 14 APBI Clock Divide Ratio Default 0x00000000 eese enne nennen 46 6 4 15 AXI Module Clock Gating Default 0x000
294. ec Channels support mono or stereo samples of 16 standard 18 optional and 20 optional bit wide One 96x20bits FIFO and one 32x20 bits FIFO for data transfer Programmable FIFO thresholds B Support Interrupt and DMA A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 237 2012 04 09 A Allwinner Technology CO Ltd A10 23 2 AC97 Block diagram 4 APB APB Wb SFR FSM amp Control KG TX FIFO LN DMA KSE Engine GE vin gt gt RX FIFO I Interrupt wk Control Figure 23 1 AC97 Interface Block Diagram Time out condition Controller off System reset or Cold reset o F Set GPIO and Release INTMSK SUBINTMSK bits SE Enable Codec Ready interrupt Codec Ready interrupt Disable Codec Ready interrupt E ee DMA operation or PIO Interrupt or Polling operation A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 238 2012 04 09 Figure 23 2 Operation flow diagram A Allwinner Technology CO Ltd A10 23 3 AC97 Interface clock tree The beginning of all audio sample packets or Audio Frames transferred over AC link is synchronized to the rising edge of the SYNC signal SYNC is driven by the Controller The Controller generates SYNC by dividing BIT_CLK by 2
295. ecurity System Tx OxB OxC OxD OxE TCONO OxF TCONI 0x10 Ox11 0x12 0x13 Ox14 0x15 0x16 0x17 Memory Stick Controller MSC 0x18 HDMI Audio 0x19 Ox1A SPIO TX Ox1B Ox1C SPR TX Ox1D A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 146 2012 04 09 Allwinner Technology CO Ltd A10 Ox1E SPI3 TX Ox1F 15 R W 0x0 BC MODE SEL BC mode select 0 normal mode the value read back is equal to the value that is written 1 remain mode the value read back is equal to the remain counter to be transfered 14 13 12 R W 0x0 DMA_SRC_SEC DMA Source Security 0 secure 1 non secure 11 10 9 R W 0x0 DMA_SRC_DATA_WIDTH DMA Source Data Width 00 8 bit 01 16 bit 10 32 bit 11 8 7 R W 0x0 DMA SRC BST LEN DMA Source Burst Length 00 1 01 4 10 8 11 6 5 R W 0x0 DMA SRC ADDR MODE DMA Source Address Mode 0x0 Linear Mode 0x1 IO Mode 0x2 Horizontal Page Mode 0x3 Vertical Page Mode 4 0 R W 0x0 DDMA SRC DRQ TYPE Dedicated DMA Source DRQ Type 0x0 SRAM memory Ox1 SDRAM memory 0x2 PATA 0x3 NAND Flash Controller NFC 0x4 USBO Ox5 Ox6 0x7 Ethernet MAC Rx Ox8 0x9 SPI RX A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 147 2012 04 09 Ou Al
296. ed 101 Reserved 14 12 R W 0 110 Reserved 111 Reserved 11 PI2 SELECT 000 Input 001 Output 010 Reserved 011 Reserved 10 8 R W 0 100 Reserved 101 Reserved A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 326 2012 04 09 Ou Allwinner Technology CO Ltd A10 110 Reserved 111 Reserved 7 PI SELECT 000 Input 001 Output 010 Reserved O1 1 Reserved 100 Reserved 101 Reserved 6 4 R W 0 110 Reserved 111 Reserved PIO SELECT 000 Input 001 Output 010 Reserved O1 1 Reserved 100 Reserved 101 Reserved 2 0 R W 0 110 Reserved 111 Reserved 30 3 74 PI Configure Register 1 Register Name PI CFG1 Offset 0x124 Default Value 0x0000 0000 Bit Read Write Default Description 31 PI15 SELECT 000 Input 001 Output 010 SPH_CS1 011 PS2 SDAI 100 TCLKIN1 101 Reserved 30 28 R W 0 110 EINT27 111 Reserved 27 PI14 SELECT 000 Input 001 Output 010 SPIO CSI 011 PS2 SCKI 100 TCLKINO 101 Reserved 26 24 R W 0 110 EINT26 111 Reserved 23 PI13 SELECT 000 Input 001 Output 010 SPIO MISO 011 UART6 RX 100 Reserved 101 Reserved 22 20 R W 0 110 EINT25 111 Reserved 19 PI12 SELECT 000 Input 001 Output 010 SPIO MOSI 011 UART6 TX 18 16 R W 0 100 Reserved 101 Reserved A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reser
297. ee ennt nennen entente nnne 260 242 2 ADC RX RE KEE 261 24 2 8 ADC Analog Control Register Liu cero t hr Por e n E REG ER P e rr E esp rette 261 242 0 DAC TEX Counter r gister n oot tras rete Gi E dr t ee tes eit ttes 264 24 2 10 ADC RX Counter register iere t eer dne tur dae eon dx SEENEdeNN 264 25 LRADC 265 29515 ODENSE LE 265 25 2 Principle of operation reiten rr dada PEU NEP E NEED swans auuvostiadsawesando vest Re eov TERR ES 265 2521 Block Ee E sabes eue foveines SEE 265 25 22 Key Function Introduction tete ettet dann con eo dera ane SER REV dog 265 23 3 LRADC Register Lists iet impen e DE E EE HER ARS 266 25 3 1 LRADG Control Register nere entera peer paene Pasa eee Pa e PSP Te E EEE Eira 266 25 3 32 LRADC Interrupt Control Regester 267 25 3 8 LRADC Interrupt Status Register s ronrronrronrronnnonnnennrenerennrennrenessnesenesenesenesenessnessnessnessnesnnee 268 25 34 LRADC Data 0 Register E 270 225 9 9 SERADE Data E 271 HORN MOIE 272 PES E 272 26 2 Typical Application Circuit oi ccscccsccsiscsacevieessccviessaccvicevsocviosvaceveosvaccviosvacsvaesvasaviesvasaveesvisaviesvasavaeaves 273 26 23 TERE Ister SN 273 26 3 1 IP Control Registet Q0 tenerent test rene eb a RENS eg ab ede Rr d ARR i aad 273 20 3 2 TP control Register 1 ette tee tete ein eee e vedete vede reet ders 274 26
298. een the timer disabled and enabled should be larger than 2 Tcycles Tcycles Timer clock source pre scale 10 3 4 Timer 0 Interval Value Register Offset 0x14 Register Name TMRO INTV VALUE REG Bit Read Default Description Write Hex 31 0 R W x TMRO_INTV_VALUE Timer 0 Interval Value Note the value setting should consider the system clock and the timer clock source 10 3 5 Timer 0 Current Value Register Offset 0x18 Register Name TMRO_CUR_VALUE_REG Bit Read Default Description Write Hex A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 89 2012 04 09 Ou Allwinner Technology CO Ltd A10 31 0 R W 0x0 TMRO_CUR_VALUE Timer 0 Current Value Note Timer 0 current value is a 32 bit down counter from interval value to 0 This register can be read correctly if the PCLK is faster than 2 TimerFreq TimerFreq TimerClkSource pre scale 10 3 6 Timer 1 Control Register Default 0x00000004 Offset 0x20 Register Name TMR1 CTRL REG Bit Read Write Default Hex Description 31 8 7 R W 0x0 TMRI MODE Timerl mode 0 Continous mode When interval value reached the timer will not disable automatically 1 Single mode When interval value reached the timer will disable automatically 6 4 R W 0x0 TMR1_CLK_PRES Select the pre scale of time
299. eginning flags STA An address Control fields Data fields A frame check sequence CRC field and A minimum of one ending flag STO A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 199 2012 04 09 Ou v Allwinner Technology CO Ltd A10 STA STA Address Control and DATA CRC16 STO MIR Packet Structure The fields in MIR packet are defined as follows STA STO The MIR use the same symbol 8 b0111 1110 for both STA and STO 8 bits Address Field 8 bits Control Field plus up to 2045 bytes in the data field 16 bits CRC field The address control data and CRC fields are not transmitted in original form They are first converted according to the MIR standards The FIR packet consists these fields Preamble field PA Beginning flag STA Address ADR Control fields Data fields A frame check sequence CRC field and A minimum of one ending flag STO PA STA Address Control and DATA CRC32 STO FIR Packet Structure The fields in FIR packet are defined as follow PA The preamble field is used by the receiver to establish phase lock The preamble field consists of exactly sixteen repeated transmissions of the following stream of symbols b 1000 0000 1010 1000 STA The STA consists of exactly one transmission of the following stream of symbols b 0000 1100 0000 1100 0110 0000 01 10 0000 STO The STO consists of exactly one transmissi
300. egion 3 window height Ranges from 0 to 4096 nuu 0 12 00 R W HIST3 WIDTH Histogram region 3 window width Ranges from 0 to 4096 31 6 97 ISP Histogram region 3 window start register Offset Address OX4D4 Register Name ISP FE HIST3 POS REG A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 379 2012 04 09 Allwinner Technology CO Ltd A10 27 16 R W HIST3 VER START Histogram region 3 window vertical start position Ranges from 0 to 4095 11 00 R W HIST3 HOR START Histogram region 3 window horizontal start position Ranges from 0 to 4095 P S When the regions are overlapped only one region is operated on The priority is Region0 gt Region1 gt Region2 gt Region3 31 6 98 ISP 3A Statistics output address register Offset Address 0X4D8 Register Name ISP FE 3A ADDR REG Bit Read Default Description Write Hex 31 00 R W STATISC 3A ADDR The output address for 3A statistic DRAM Address P S This register has double buffer it should be reloaded by hardware at every vsync 31 6 99 ISP LUT Defect Correction configuration register Offset Address OXAEA Register Name ISP FE LUT DC CFG REG Read Default Description Write Hex SSES RS Del nis 1 ES 08 00 R W DEF NUM The number of defect pixel N in LUT Ranges from 0 256 31 6 100 ISP LUT Defect Correction address register Offset Address OXAE8 Register Name ISP FE LUT DC ADDR REG Bi
301. egister essent eren nennen nnns 422 33 447 TCONL fill data end register cei rete rer ree a ro Pese ae 422 33 4 48 TCONI fill data value register eui eerte re er t ee rte thee 422 KC DRAN 422 c NEQUID M 422 34 2 TN Encoder Register L1sti ene eene age Ee 422 34 3 TV Encoder Register Description nennen trenee trennen trennen 424 34 4 TV Encoder Enable Registet nicer rer mer ee rete erai he rr rr ae deg Ee 424 34 4 TV Encoder Configuration Register ener ener 425 34 42 TV Encoder DAC Register ferret rr tr e e e res 427 34 4 3 TV Encoder Notch and DAC Delay Register 429 34 4 4 TV Encoder chroma frequency Register 431 34 4 5 TV Encoder Front Back Porch Register essent nennen 431 34 4 6 TV Encoder HD mode VSYNC Register 432 34 4 7 TV Encoder Line Number Register 432 34 4 8 TV Encoder Level Register eter tei ee eee eee erred 433 344 0 TY Encoder DAC Register cedro tege dria eter dieere ege 433 34 4 10 TV Encoder Auto Detection Enable Register 434 34 4 11 TV Encoder Auto Detection Interrupt Status Register 434 34 4 12 TV Encoder Auto Detection Status Register 435 34 4 13 TV Encoder Notch Filter Frequency Register essere 435 34 4 14 TV Encoder Cb Cr Level Gain Register AA 436 34 4 15 TV Encoder Tint and Color Burst Phase Register eese 436 34 4 16 TV Encoder Burst Width Reoteter AAA 437 34 4 17 IV Enc
302. egister Example for 20 bits transmitted audio sample Mode 0 FIFO 1 23 0 4 hO TXFIFO 31 12 2 R W 0 Mode 1 FIFO 1 23 0 4 hO TXFIFO 19 0 RXOM RX FIFO Output Mode Mode 0 1 2 3 00 Expanding 0 at LSB of DA RXFIFO register 01 Expanding received sample sign bit at MSB of DA_RXFIFO register 10 Truncating received samples at high half word of DA_RXFIFO register and low half word of DA_RXFIFO register is filled by 0 11 Truncating received samples at low half word of DA_RXFIFO register and high half word of DA RXFIFO register is expanded by its sign bit Example for 20 bits received audio sample Mode 0 RXFIFO 31 0 FIFO O 19 0 127h0j Mode 1 RXFIFO 31 0 12 FIFO_O 19 FIFO_O 19 0 Mode 2 RXFIFO 31 0 FIFO O 19 4 167h0j Mode 3 RXFIFO 31 0 16 FIFO_O 19 1 0 R W 0 FIFO_O 19 4 22 4 7 Digital Audio FIFO Status Register Register Name DA_FSTA Offset 0x18 Default Value 0x1080_0000 Bit Read Write Default Description 31 29 TXE 28 R 1 TX FIFO Empty A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 226 2012 04 09 Ou Allwinner Technology CO Ltd A10 0 No room for new sample in TX FIFO 1 More than one room for new sample in TX FIFO gt 1 word 27 24 TXE_CNT 23 16 R 0x80 TX FIFO Empty Space Word Counter 15 9 RXA RX FIFO Available 0 N
303. egister Name AC_ADC_FIFOS Bit Read Write Default Description 31 24 RXA 23 R 0x0 RX FIFO Available A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 260 2012 04 09 Ou Allwinner Technology CO Ltd A10 0 No available data in RX FIFO 1 More than one sample in RX FIFO gt 1 word 22 14 RXA_CNT 13 8 R 0x0 RX FIFO Available Sample Word Counter 7 4 RXA_INT RX FIFO Data Available Pending Interrupt 0 No Pending IRQ 3 R W 0x0 p 1 Data Available Pending IRQ Write 1 to clear this interrupt or automatic clear if interrupt condition fails 2 RXO_INT RX FIFO Overrun Pending Interrupt 1 R W 0x0 0 No Pending IRQ 1 FIFO Overrun Pending IRQ Write 1 to clear this interrupt 0 24 2 7 ADC RX DATA register Offset 0x24 Register Name AC_ADC_RXDATA Default Value 0x0000_0000 Bit Read Write Default Description RX_DATA RX Sample Host can get one sample by reading this register The left channel sample data is first and then the right channel 31 0 R 0x0 sample 24 2 8 ADC Analog Control Register Offset 0x28 Register Name AC PA ADC ACTRL Bit R W Default Description 31 R W 0x0 ADCREN ADC Right Channel Enable 0 Disable 1 Enable 30 R W 0x0 ADCLEN ADC Left Channel Enable 0 Disable A10 User Manual V1 20 Copyright O 2011 2012 Allwinner
304. em data for modem Line 2 output 11 Modem handset DAC 16 bit modem data for modem Handset output 12 Modem IO control GPIO write port for modem Control 10 11 SPDIF Out Optional AC link bandwidth for SPDIF output 6 12 Double rate audio Optional AC link bandwidth for 88 2 or 96 kHz on L C R channels Actual slots used are controlled by the DRSS bits A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 239 2012 04 09 4 Allwinner Technology CO Ltd A10 The AC link input slots transmitted from the Codec are defined as follows Slot Name Description 0 SDATA IN TAG MSBs indicate which slots contain valid data 1 STATUS ADDR read port MSBs echo register address LSBs indicate which slots request data 2 STATUS DATA read port 16 bit command register read data 3 4 PCM L amp R ADC record 16 18 or 20 bit PCM data from Left and Right inputs 5 Modem Line 1 ADC 16 bit modem data from modem Line1 input 6 Dedicated Microphone ADC 16 18 or 20 bit PCM data from optional 3rd ADC input 7 8 9 Vendor reserved Vendor specific enhanced input for docking array mic etc 10 Modem Line 2 ADC 16 bit modem data from modem Line 2 input 11 Modem handset input ADC 16 bit modem data for modem Handset input 12 Modem IO status GPIO read port for modem Status 23 5 AC97 Interface Timing Diagram 23 5 1 Cold Reset timing diagram Ta rst2clk I rom RESET J Brek He NU T X
305. en ener 399 33 4 3 TCON global interrupt register eese nnne nnne nnns 400 33 44 TCON FRM control regiStet ec iere P Re IR e rd eee Seege 400 3345 ICON ERM seed register repeto op et e eit req ERE REPRE ENS 401 33 4 0 ICON FRM table register eiie itinere trennt tete rti aaa a aian aa 402 33 4 7 TCONO control register er OTT REDE PINE CHEER EINE ENEE 402 33 48 TICONO data clock TT 403 3349 TCONO basic timing Teglster EE 404 33 4 10 TCONO basic timing register essent ener ener 404 33 4 11 TCONO basic timing E 405 3344 12 TCONDO basic timing E 405 33 4 13 TCONO hv panel interface register essere ener enne 405 33 4 14 TCONO cpu panel interface regteter ener en ener 406 33 4 15 TCONO cpu panel write data register esee 407 33 4 16 TCONO cpu panel read data register0 esses 407 33 4 17 TCONO cpu panel read data register essent 408 33 4 18 TCONO ttl panel timing register U N 408 33 4 19 TCONO tttl panel timing register 1 408 33 4 20 TCONO ttl panel timing register 2 rrr tete tete edi reads 409 33 4 21 TCONO ttl panel timing regteter A 409 33 4 22 TCONO ttl panel timing regteter ener ener nens 409 33 4 23 TCONO Ivds panel interface register sese eene 410 33 4 24 TCONO IO ee 411 32 4 25 TCONI controlresister soi tre e reet dete i ai t ee te eie ette 412 33 4 26 TCONI basic timing register
306. ennen 98 10 3 22 AVS Counter I Register Default ONOOOUOOU0 nee 98 10 3 23 AVS Counter Divisor Register Default OXOSDBOSDB eese 98 10 3 24 Watch Dog Control Register 99 10 3 25 Watch Dog Mode Register Default 0x00000000 eese 99 10 3 26 64 bit Counter Low Register Default 0x00000000 esee 100 10 3 27 64 bit Counter High Register Default 0x00000000 csset 100 10 3 28 64 bit Counter Control Register Default 0x00000000 eee 101 10 3 29 LOSC Control Default 0x00004000 cessent nennen enne 101 10 3 30 RTC YY MM DD Default 0x00000000 eese nennen nennen 102 UE RTC LEE 103 10 3 32 Alarm Counter DID HH MM S A 103 10 3 33 Alarm Week HH MM SS oornenrvnnevnnvvnsvnevnevnnsvnvvnennevnnvnnsvnsnnevnnsvnsvnevnavvnvvnsvnsvnnsnnsvnsvnsennsvnvnnsen 104 10 3 34 Alarm Enable torte ro e m e re ERR ERE Seas YER ERI test eege PERO TI Peer Re E 104 10 3 35 Alarm IRQ Enable retire teret itt es E tt tes et abe ene eed 106 10 3 36 Alarm IRQ Status Register tentent tentent Eae corna o dena oaa eda oar dun 106 10 3 37 Timer General Purpose Register U N 106 10 3 38 Timer General Purpose Register 1 eerie rantes ere Roter ERR 107 10 3 39 Timer General Purpose Register 2 eerte enirn rre nen eniti 107 10 3 40 Timer General Purpose Register 3 essere eene nennen 107 10 3 41 CPU Config Register Default
307. equirement esent neret nennen ener enen enne 161 IT PREMISE 161 16 5 2 TWI Controller Operation eerte trennt ree ener evertere ee nd nh e 162 17 SPI Inter E 163 CL CMN ee 163 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 9 2012 04 09 Allwinner Technology CO Ltd A10 2012 04 09 172 SPL Vain Diagram E 163 17 34 SPI Register List EE 164 I7 4 SPLRegister Description sessiun EROR e PE EH RE CERE GR TEE 165 ITAL ISPEROeData Register LAE 165 1742 SPITX Data Register ciinei enian o Eea RAEN nr a eee qe nd e Rel cde AR espe Ren dn 165 LL43 SPIContr l Register tone deren reete e tre er e ee de nee Ne eege 165 17 44 SPLInterrupt Control Register nire t rrt edere resin 168 17 45 RO eege EE 170 17 4 6 SPIDMA Control Register AAA 172 17 4 7 SPI Wait Clock Reglster ocecettt eter eI Pr TENERE EE ERE eue 174 1748 SPEClock Control Reglster o teni te RD ERE Per Ee ra ERE EE leat re OI Perd Ree 174 17 50 SPI Burst Counter Register i cci eter itt es rnit es t be n eei 175 17 4 10 SPI Transmit Counter Register 175 17 4 11 SPIFIFO EE 175 11 442 SPI Special Requirement 2 nae n REED REESEN 176 17 413 SPIPM Studere 176 17 4 14 SPI Module Clock Source and Frequency ernnnnrrnrnvvnnvnrnnnnrnnvnennnnennrnvvnenesnrsnenvvnevesnesnessvesveene 176 18 UART Interface 178 18 1 E 178 1
308. er Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 272 2012 04 09 Ou Allwinner Technology CO Ltd A10 26 2 Typical Application Circuit Ye X NNN WA Xe Nie Figure 26 1 Typical Application Circuit 26 3 TP Register List Module Name Base Address TP 0x01C25000 Register Name Offset Description TP_CTRLO 0x00 TP Control Register0 TP CTRLI 0x04 TP Control Register TP_CTRL2 0x08 TP Control Register2 TP CTRL3 OxOc TP Control Register3 TP INT FIFOC Ox10 TP Interrupt FIFO Control Register TP INT FIFOS 0x14 TP Interrupt FIFO Status Register TP_TPR 0x18 TP Temperature Period Register TEMP_DATA Oxlc Temperature Data Register TP_DATA 0x20 TP Data Register 26 3 1 TP Control Register 0 Offset 0x00 Register Name TP_CTRL A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 273 2012 04 09 Ou Allwinner Technology CO Ltd Bit Read Default Description Write A10 ADC CLK SELECT ADC Clock Source Select 0 HOSC 24MHZ 1 Audio PLL Hex ADC FIRST DLY 31 24 R W OxF ADC First Convert Delay setting Based on ADC First Convert Delay Mode select 23 R W Ox1 ADC FIRST DLY MODE ADC First Convert Delay Mode Select 0 CLK_IN 16 1 CLK_IN 16 256 R W 0x0 0x0 ADC CLK DIVIDER ADC Clock Divider
309. er Technology All Rights Reserved 381 2012 04 09 i ibd Allwinner Technology CO Ltd A10 PJ Dark Frame Write done interrupt enable 1 R W AWBE INT EN AWBE statistic done interrupt enable R W AF INT EN AF statistic done interrupt enable 31 6 104 ISP interrupt status register Offset Address 0X4F8 Register Name ISP_FE_INT_STA_REG Bit Read Default Description Write Hex 7 R W HIST3_INT_PD ai Histogram region 3 statistic done write 1 to clear this bit R W HIST2_INT_PD Pr Histogram region 2 statistic done write 1 to clear this bit 5 R W HIST1 INT PD Pr Histogram region statistic done write 1 to clear this bit 4 R W HISTO_INT_PD UI eee S fr rn 2 R W DF WR INT PD Dark Frame Write done write I to clear this bit 1 R W AWBE INT PD AWBE statistic done write 1 to clear this bit R W AF INT PD AF statistic done write 1 to clear this bit 31 6 105 ISP FE CbCr Output address length register Offset Address 0X500 Register Name ISP FE C LEN REG Bit Read Default Description Write Hex 12 00 R W 500 ISP_FE_C_LEN The length of ISP FE CbCr Output data in Byte while accessing DRAM ranges from 0 to 4096 This should be integer multiplier of 0X20 P S This register has double buffer it should be reloaded by hardware at every vsync A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 382 2012 04 09 Allwinner Technology CO Ltd A1
310. errupt Pending Set 1 to the bit will clear it A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 137 2012 04 09 Ou Allwinner Technology CO Ltd A10 0 No effect 1 Pending 29 R W 0x0 DDMA6_END_IRQ_PEND Dedicated DMA 6 End Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending 28 R W 0x0 DDMA6_HF_IRQ_PEND Dedicated DMA 6 Half Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending 27 R W 0x0 DDMA5 END IRQ PEND Dedicated DMA 5 End Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending 26 R W 0x0 DDMAS HF IRQ PEND Dedicated DMA 5 Half Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending 25 R W 0x0 DDMA4_END_IRQ_PEND Dedicated DMA 4 End Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending 24 R W 0x0 DDMA4_HF_IRQ_PEND Dedicated DMA 4 Half Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending 23 R W 0x0 DDMA3 END IRQ PEND Dedicated DMA 3 End Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending 22 R W 0x0 DDMA3_HF_IRQ_PEND Dedicated DMA 3 Half Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending
311. errupt condition fails R W RXO_INT RX FIFO Overrun Pending Interrupt 0 FIFO Overrun Pending Write 1 to clear this interrupt R W RXA_INT RX FIFO Available Pending Interrupt 0 No Pending IRQ 1 Data Available Pending IRQ Write 1 to clear this interrupt or automatically clear if interrupt condition fails 23 7 11 AC97 TX Counter register Offset 0x28 Register Name AC TX CNT Default Value 0x0000 0000 Bit Read Write Default Description 31 0 R W 0 TX_CNT TX Sample counter The audio sample number of writing into TX FIFO When one sample is written by DMA or by host IO the TX sample counter register increases by one The TX Counter register can be set to any initial value at any time After been updated by the initial value the counter register should count on base of this value A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 252 2012 04 09 Ou Allwinner Technology CO Ltd A10 23 7 12 AC97 RX Counter register Offset 0x2C Register Name AC_RX_CNT Default Value 0x0000_0000 Bit Read Write Default Description 31 0 R W 0 RX_CNT RX Sample counter The audio sample number of writing into RX FIFO When one sample is written by Codec the RX sample counter register increases by one The RX Counter register can be set to any initial value at any time After
312. escription Write Hex 31 25 24 0 R W 0 Pixel Seed Value Note avoid set it to 0 Offset 0x020 Register Name TCON FRM LSEED R REG Bit Read Default Description Write Hex 31 13 12 0 R W 0 Line Seed Value Note avoid set it to 0 Offset 0x024 Register Name TCON FRM LSEED G REG Bit Read Default Description Write Hex 31 13 12 0 R W 0 Line_Seed_Value Note avoid set it to 0 Offset 0x028 Register Name TCON_FRM_LSEED_B_REG Bit Read Default Description Write Hex 31 13 12 0 R W 0 Line_Seed_Value A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 401 2012 04 09 Ou Allwinner Technology CO Ltd A10 Note avoid set it to 0 33 4 6 TCON FRM table register Offset 0x02C Register Name TCONO FRM TABO REG Bit Read Default Description Write Hex 31 0 R W 0 Frm_Table_Value Offset 0x030 Register Name TCONO FRM TAB1 REG Bit Read Default Description Write Hex 31 0 R W 0 Frm_Table_Value Offset 0x034 Register Name TCONO FRM TAB2 REG Bit Read Default Description Write Hex 31 0 R W 0 Frm_Table_Value Offset 0x038 Register Name TCONO FRM TAB3 REG Bit Read Default Description Write Hex 31 0 R W 0 Frm Table Value 33 4 7 TCONO control register Offset 0x040 Register
313. ese nnne 87 10 3 3 Timer 0 Control Register Default 0x00000004 eese 88 10 3 4 Timer 0 Interval Value Register AA 89 10 3 5 Timer 0 Current Value Reester A 89 10 3 6 Timer 1 Control Register Default 0x00000004 essent 90 10 3 7 Timer Interval Value Register ree erret teretes er rre e rere dee 91 10 3 8 Timer 1 Current Value Register en enne 91 10 3 9 Timer 2 Control Register Default 0x00000004 cessere 91 10 3 10 Tim r2 Interval Value Register rer re e Er Re Om ena Res 92 10 3 11 Timer 2 Current Value Register 4e eh re eere ir e e e ke rri deg 93 10 3 12 Timer 3 Control Register Default 0x00000000 eese 93 10 3 13 Timer 3 Interval Value ertet tre ner ter n eer e eere eege 93 10 3 14 Timer 4 Control Register Default 0x00000004 essent 94 10 3 15 Timer Interval Value Register ree erret et terr Eegen 95 10 3 16 Timer 4 Current Value Register sees nene en enrenren ener nne nennt 95 10 3 17 Timer 5 Control Register Default 0x00000004 essent 95 10 3 18 Timer Interval Value Register eene ttem rep Pm teer e Pen EOE TANE 96 10 3 19 Timer 5 Current Value Register ermittelten 97 10 3 20 AVS Counter Control Register Default 0x00000000 orrrvvrvnnrnnrnrrvvnvnnrnrnnrrvvnrververnervrnrnesnene 97 10 3 21 AVS Counter 0 Register Default 0x00000000 cessere nennen n
314. ess register eese 380 31 6 101 ISP FE Y Raw Output address length register rsrrrnnnnrrnrnvrnvnnnnrnnrrvnrnennrnnrevvnrnernrsnrevvesnennne 381 31 6 102 SP FE Y Raw Output address regieter eese rennen 381 31 6 103 ISP interrupt enable register sees nennen nennen enne 381 31 6 104 ISP int rrupt status register oc niente ERR EENS E tear ERES 382 31 6 105 ISP FE CbCr Output address length register srrsrronnnnrnnrnvvnrnnnnrnnrrvnrnnnvrrnrevvnnnesnesvrevvesnennne 382 31 6 106 ISP FE CbCr Output address register essent ener 383 384 32 1 OVerview AE 384 32 2 Blockdiagram EE 384 32 3 CSI ata e CN 385 32 4 KE 385 240 Sn 385 32 5 CSI Registers Last nina retener e eem eee nr e een 385 32 6 CSU Register Descriptions o rri der eei ve e e ere e re e PR HE FEE svesdedseusiestaaves 386 32 6 1 CSI Enable R gIStet eerte tete t eer E ree a erae PE Ta enata Dua EES 386 32 6 2 CSI configuration register e rr e aa EE RR ENS Ee YER RETE FCR RETE EH Fe TER ETUR Ve 387 32 0 3 Cel capture control T69lstet o cette ore teo m E Fe I EE duds sve vanventSedeevesaeaars 389 32 6 4 CSI horizontal scale register cocer tro trt Ge n e e o ae e Ta 389 32 6 5 CSI Channel 0 FIFO 0 output buffer A address register essen 390 32 6 6 CSI Channel 0 FIFO 0 output buffer B address register eese 3
315. et and the dsr_n signal is asserted low and a reset occurs software or otherwise then the DDSR bit is set when the reset is removed if the dsr_n signal remains asserted DCTS Delta Clear to Send This is used to indicate that the modem control line cts_n has changed since the last time the MSR was read 0 no change on ctsdsr_n since last read of MSR 1 change on ctsdsr_n since last read of MSR Reading the MSR clears the DCTS bit In Loopback Mode MCR 4 1 DCTS reflects changes on MCR 1 RTS Note If the DCTS bit is not set and the cts_n signal is asserted low and a reset occurs software or otherwise then the DCTS bit is set when the reset isremoved if the cts_n signal remains asserted 18 4 12 UART Scratch Register Register Name UART_SCH Offset 0x1C Default Value 0x0000_0000 Bit Read Write Default Description 31 8 SCRATCH_REG Scratch Register This register is for programmers to use as a temporary 7 0 R W 0 storage space It has no defined purpose in the UART A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 194 2012 04 09 Allwinner Technology CO Ltd A10 18 4 13 UART Status Register Register Name UART USR Offset 0x7C Default Value 0x0000_0006 Bit Read Write Default Description 31 5 RFF Receive FIFO Full This is used to indicate that the receive FIFO is completel
316. f the output format is frame planar YCbCr 420 mode the frame end means the field2 end the other frame end means filed end 31 6 13 CSI Channel_0 interrupt enable register Offset Address 0X0030 Register Name CSI0 C0 INT EN REG Bit Read Default Description Write Hex KE M VS INT EN vsync flag The bit is set when vsync come And at this time load the buffer address for the coming frame So after this irq come change the buffer address could only effect next frame HB OF INT EN Hblank FIFO overflow The bit is set when 3 FIFOs still overflow after the hblank FIFO2 OF INT EN FIFO 2 overflow The bit is set when the FIFO 2 become overflow FIFO1 OF INT EN FIFO 1 overflow The bit is set when the FIFO 1 become overflow FIFOO OF INT EN FIFO 0 overflow The bit is set when the FIFO 0 become overflow CD INT EN Capture done Indicates the CSI has completed capturing the image data For still capture the bit is set when one frame data has been wrote to buffer For video capture the bit is set when the last frame has been wrote to buffer after video capture has been disabled ID ITE 01 R W FD_INT_EN Frame done Indicates the CSI has finished capturing an image frame Applies to video capture mode The bit is set after each completed frame capturing data is wrote to buffer as long as video capture remains enabled TT For CCIR656 interface if the output format is frame plan
317. fault Description 31 2 MS_PRIORITY CPU and DVFS BUSY set priority select 0 CPU has higher priority 2 R W 0 1 DVFS has higher priority CPU_BUSY_SET 1 R W 0 CPU Busy set DVFC_BUSY_SET 0 R W 0 DVFS Busy set Notes This register is only implemented in TWIO 16 5 TWI Controller Special Requirement 16 5 1 TWI Pin List Port Name Width Direction Description A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 161 2012 04 09 Ou Allwinner Technology CO Ltd A10 TWLSCL 1 IN OUT TWI Clock line TWI SDA 1 IN OUT TWI Serial Data line 16 5 2 TWI Controller Operation There are four operation modes on the 2 Wire bus which dictates the communications method They are Master Transmit Master Receive Slave Transmit and Slave Receive In general CPU host controls TWI by writing commands and data to it s registers The TWI interrupts the CPU host for the attention each time a byte transfer is done or a START STOP conditions is detected The CPU host can also poll the status register for current status if the interrupt mechanism is not disabled by the CPU host When the CPU host wants to start a bus transfer it initiates a bus START to enter the master mode by setting IM STA bit in the 2WIRE CNTR register to high before it must be low The TWI will assert INT line and INT FLAG to indicate a completion for the START condition and each conseq
318. ffset OxEO Register Name MP_OUTCTL_REG Read W Default Description rite Hex OUT_PS Output data pixel sequence Reference output pixel sequence table RND_EN Round enable O disabled enabled A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 478 2012 04 09 Ou Allwinner Technology CO Ltd A10 Output data format 0x0 32bpp A8R8G8B8 or interleaved AYUV8888 Ox1 16bpp A4R4G4B4 0x2 16bpp AIR5G5B5 0x3 16bpp R5G6B5 0x4 16bpp interleaved YUV422 0x5 planar YUV422 UV combined Ox6 planar YUV422 0x7 8bpp MONO Ox8 4bpp MONO 0x9 2bpp MONO Oxa 1bpp MONO Oxb planar YUV420 UV combined Oxc planar YUV420 Oxd planar YUV411 UV combined Oxe planar YUV411 Other reserved Note In all YUV output data format the CSC2 must be enabled otherwise the output data mode will be 32bpp A8R8G8B8 mode Output data mode and output data ports mapping Output data channel selection Channel 0 Channel 1 Channel 2 A8R8G8B8 or interleaved AYUV8888 ARGB or Ignore Ignore AYUV A4R4G4B4 ARGB Ignore Ignore AIRSGSB5 ARGB Ignore Ignore R5G6B5 RGB Ignore Ignore interleaved YUV422 YUV Ignore Ignore planar YUV422 UV combined Y UV Ignore planar YUV422 Y U V 8bpp MONO Ignore 4bpp MONO Ignore 2bpp MONO Ignore 1bpp MONO Ignore planar YUV420 UV combined Ignore planar YUV420 V planar YUV411 UV combined Ignore planar YUV411 V
319. ficient 2 35 5 39 CSC2 Y G coefficient register Offset Register Name MP_OCSCYGCOEF_REG G Y component 0x1C0 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 484 2012 04 09 Ou Allwinner Technology CO Ltd R U component 0x1C4 B V Seet 0x1C8 Read W Default Description rite Hex 12 00 R W CSC2_YGCOEF the Y G coefficient the value equals to coefficient 2 35 5 40 CSC2 Y G constant register Offset 0x1CC Register Name MP_OCSCYGCONS_REG Bit Read W Default Description rite Hex 13 00 R W CSC2 YGCONS the Y G constant the value equals to coefficient 2 35 5 41 CSC2 U R coefficient register Offset Register Name MP OCSCURCOEF REG G Y component 0x1D0 R U component 0x1D4 B V ee 0x1D8 Read W Default Description rite Hex mas 12 00 R W CSC2 URCOEF the U R coefficient the value equals to coefficient 2 35 5 42 CSC2 U R constant register Offset 0x1DC Register Name MP OCSCURCONS REG Read W Default Description rite Hex arr a 13 00 R W CSC2 URCONS the U R constant A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 485 2012 04 09 Allwinner Technology CO Ltd A10 the value equals to coefficient 2 35 5 43 CSC2 V B coefficient register Offset Register Name MP OCSCVBCOEF REG G Y component 0x1E0 R U compo
320. field end A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 393 2012 04 09 Ou Allwinner Technology CO Ltd A10 32 6 14 CSI Channel 0 interrupt status register Offset Address 0X0034 Register Name CSI1 INT STA REG Bit Read Default Description Write Hex 07 R W VS PD R W HB OF PD ae Hblank FIFO overflow R W FIFO2_OF_PD ir FIFO 2 overflow R W FIFO1_OF_PD i FIFO 1 overflow R W FIFOO_OF_PD Id IN FIFO 0 overflow R W FD PD DE Frame done R W CD PD Bea gf Capture done 32 6 15 CSI Channel_0 horizontal size register Offset Address 0X0040 Register Name CSI1_HSIZE_REG Offset Address 0X0044 Register Name CSI1_VSIZE_REG Bit Read Default Write Hex A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 394 2012 04 09 Allwinner Technology CO Ltd A10 VER LEN Vertical line length Valid line number of a frame na rpm R W 12 00 R W VER START Vertical line start data is valid from this line 32 6 17 CSI Channel 0 buffer length register Offset Address 0X0048 Register Name CSI1 BUF LEN REG Bit Read Default Description Write Hex Gis fr 12 00 R W 280 BUF LEN Buffer length of a line Unit is byte It is the max of the 3 FIFOs A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 395 2012 04 09 Ou Allwinner Technology CO Ltd A10 33 LCD TV Timi
321. for image stream parsing Received data double buffer support Parsing BAYER data into planar R G B output to memory Parsing interlaced data into planar or tie based YCbCr output to memory Pass raw data direct to memory All data transmit timing can be adjusted by software support multi channel ITU R BT 656 time multiplexed format luminance statistical value support 8 bit raw data input support 16 bit YUV422 data input 31 2 2 ISP FE M Digital clamp with horizontal vertical offset compensation M Lens shading correction M Color dependent gain control and black level offset control E Dark frame subtract of raw image stored B AE AF AWB statistics M Histogram statistics B DC subtract for Y channel B LUT Defect Pixel correction Double buffer for enable and output address registers A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 334 2012 04 09 Ou Allwinner Technology CO Ltd 31 3 Block diagram ISP Front End FIFO ES ed Channel 0 Control Module Timing Convert ICS Hsync CSI wi CS Vsync A10 CS Data Clock ICS Data 7 0 Data 15 0 Channel 3 Ute EN 4 Figure31 1 31 3 1 CSI data ports Bayer YCbCr YUV Interlaced Pass through FIFOO Red pixel data Y pixel data All field 1 pixel All pixel data data FIFO1 Green pixel data Cb U pixel All field 2 pixel
322. for root key 29 2 Security ID Register List Module Name Base Address SID 0x01C23800 Register Name Offset Description SID RKEYO 0x00 Root Key 31 0 SID RKEYI 0x04 Root Key 63 32 SID_RKEY2 0x08 Root Key 95 64 SID_RKEY3 OxOc Root Key 127 96 29 3 SID Register Description 29 3 1 SID Root Key 0 Register Register Name SID RKEYO Offset 0x00 Default Value 0x XXXX XXXX Bit Read Write Default Description ROOT KEY 31 0 R X Securiy root key 31 0 29 3 2 SID Root Key 1 Register Register Name SID_RKEY1 Offset 0x04 Default Value 0xXXXX_XXXX A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 285 2012 04 09 Ou Allwinner Technology CO Ltd A10 Bit Read Write Default Description ROOT KEY 31 0 R X Securiy root key 63 32 29 3 3 SID Root Key 2 Register Register Name SID RKEY2 Offset 0x08 Default Value 0x XXXX XXXX Bit Read Write Default Description ROOT KEY 31 0 R X Securiy root key 95 64 29 3 4 SID Root Key 3 Register Register Name SID RKEY3 Offset 0x0c Default Value 0x XXXX XXXX Bit Read Write Default Description ROOT KEY 31 0 R X Securiy root key 127 96 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 286 2012 04 09 A10 Allwinner Technology CO Ltd 30
323. frame The bit is set at the start of the first frame after enabling still frame capture It clears itself after the last pixel of the first frame is captured For CCIR656 interface if the output format is frame planar YCbCr 420 mode the frame end means the field2 end the other frame end means filed end 31 6 26 CSI Channel 1 interrupt enable register Offset Address 0X0130 Register Name CSIO C1 INT EN REG Bit Read Default Description Write Hex A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 353 2012 04 09 Allwinner Technology CO Ltd A10 pr VS INT EN vsync flag The bit is set when vsync come And at this time load the buffer address for the coming frame So after this irq come change the buffer address could only effect next frame HB OF INT EN Hblank FIFO overflow The bit is set when 3 FIFOs still overflow after the hblank FIFO2 OF INT EN FIFO 2 overflow The bit is set when the FIFO 2 become overflow FIFO1 OF INT EN FIFO 1 overflow The bit is set when the FIFO 1 become overflow FIFOO OF INT EN FIFO 0 overflow The bit is set when the FIFO 0 become overflow FD INT EN Frame done Indicates the CSI has finished capturing an image frame Applies to video capture mode The bit is set after each completed frame capturing data is wrote to buffer as long as video capture remains enabled CD INT EN Capture done Indicates the CSI has completed captur
324. g data 25 2 2 Key Function Introduction ADC_REF R LRADC IN apc REF m Rh 22 24 KEY DOWN IRQ z gt d as HOLD_KEY_IRQ Control Logic br ADC REF v ALREADY HOLD IRQ Le A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 265 2012 04 09 Allwinner Technology CO Ltd A10 When ADC IN Signal change from ADC REF to 2 3 ADC REF Level A the comparator24 send first interrupt to control logic When ADC IN Signal change from 2 3 ADC REF to certain level Program can set the comparator25 give second interrupt If the control Logic get the first interrupt In a certain time range program can set doesn t get second interrupt it will send hold key interrupt to the host If the control Logic get the first interrupt In a certain time range program can set get second interrupt it will send key down interrupt to the host If the control logic only get the second interrupt doesn t get the first interrupt it will send already hold interrupt to the host 25 3 LRADC Register List Module Name Base Address LRADC 0x01C22800 Register Name Offset Description LRADC CTRL 0x00 LRADC Control Register LRADC INTC 0x04 LRADC Interrupt Control Register LRADC INTS 0x08 LRADC Interrupt Status Register LRADC DATAO OxOc LRADC Data Register 0 LRADC DATAI 0x10 LRADC Data Register 1 25 3 1 LRADC C
325. g generator will reset to the beginning of the first blank line 33 4 8 TCONO data clock register Offset 0x044 Register Name TCONO DCLK REG Bit Read Default Description Write Hex 31 28 R W 0 TCONO Dclk En LCLK EN 3 0 TCONO clock enable 4 hO h4 4 h6 4 ha7 dclk_en 0 dclk1_en 0 dclk2_en 0 dclkm2_en 0 4 hl dclk en 1 dclk1_en 0 dclk2 en 0 dclkm2 en 0 4 h2 dclk en 1 dclk1_en 0 dclk2 en 0 dclkm2 en 1 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 403 2012 04 09 Ou Allwinner Technology CO Ltd A10 4 h3 dclk en 1 delkl en 1 dclk2 en 0 dclkm2_en 0 4 h5 delk en 1 delkl en 0 dclk2 en 1 dclkm2 en 0 4 n8 4 h9 4 ha 4 hb 4 hc 4 hd 4 he 4 hf delk en 1 delkl en 1 delk2 en 1 dclkm2 en 1 27 7 6 0 R W 0 TCONO Dclk Div Tdclk Tsclk DCLKDIV Note lif dclk1 amp dclk2 used DCLKDIV gt 6 2 if dclk only DCLKDIV gt 4 33 4 9 TCONO basic timing register Offset 0x048 Register Name TCONO BASICO REG Bit Read Default Description Write Hex 31 27 26 16 R W 0 TCONO X Panel width is X41 15 11 10 0 R W 0 TCONO Y Panel height is Y 1 33 4 10 TCONO basic timing register1 Offset 0x04C Register Name TCONO BASICI REG Bit Read Default Description Write Hex 31 R W 0 UF En
326. ghts Reserved 294 2012 04 09 Ou Allwinner Technology CO Ltd A10 110 Reserved 111 Reserved 15 PB11_SELECT 000 Input 001 Output 010 DS DO3 011 Reserved 100 Reserved 101 Reserved 14 12 R W 0 110 Reserved 111 Reserved 11 PB10 SELECT 000 Input 001 Output 010 DS DO2 011 Reserved 100 Reserved 101 Reserved 10 8 R W 0 110 Reserved 111 Reserved 7 PB9 SELECT 000 Input 001 Output 010 PS DO 011 Reserved 100 Reserved 101 Reserved 6 4 R W 0 110 Reserved 111 Reserved PB8 SELECT 000 Input 001 Output 010 DS DOO 011 AC97_DO 100 Reserved 101 Reserved 2 0 R W 0 110 Reserved 111 Reserved 30 3 12 PB Configure Register 2 Register Name PB CFG2 Offset 0x2C Default Value 0x0000 0000 Bit Read Write Default Description 31 PB23_SELECT 000 Input 001 Output 010 UARTO RX 011 IRI RX 100 Reserved 101 Reserved 30 28 R W 0 110 Reserved 111 Reserved 27 PB22_SELECT 000 Input 001 Output 010 UARTO TX 011 IR1 TX 26 24 R W 0 100 Reserved 101 Reserved A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 295 2012 04 09 Ou Allwinner Technology CO Ltd A10 110 Reserved 111 Reserved 23 Reserved PB21_SELECT 000 Input 001 Output 010 TWI2_SDA 011 Reserved 100 Reserved 101 Reserved
327. h Panel HM LVDS jJ H 264 JPEG Encoder NTSC PAL Y Pb Pr S TV Out Memory Subsystem SRAM ROM q C DDRJI DDRJI E NAND A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 2012 04 09 Figure 3 1 General Block Diagram 28 Ou Allwinner Technology CO Ltd A10 3 2 Memory Mapping Module Address Size Bytes SRAM Al 0x0000 0000 0x0000 3FFF 16K SRAM A2 0x0000 4000 0x0000 7FFF 16K SRAM A3 0x0000 8000 0x0000 B3FF 13K SRAM A4 0x0000 B400 0x0000 BFFF 3K SRAM Nand 2K SRAM D 0x0001 0000 0x0001 OFFF 4K SRAM B Secure 0x0002 0000 0x0002 FFFF 64K SRAM Controller 0x01C0 0000 0x01C0 OFFF 4K DRAM Controller 0x01C0 1000 0x01C0 1FFF 4K DMA 0x01C0 2000 0x01C0 2FFF 4K NFC 0x01C0 3000 0x01C0 3FFF 4K TS 0x01C0 4000 0x01C0 4FFF 4K SPIO 0x01C0 5000 0x01C0 SFFF 4K SPI I 0x01C0 6000 0x01C0 6FFF 4K MS 0x01C0 7000 0x01C0 7FFF 4K TVD 0x01CO 8000 0x01C0 8FFF 4K CSI 0 0x01CO 9000 0x01C0 9FFF 4K TVEO 0x01C0 A000 0x01CO AFFF 4K EMAC 0x01CO B000 0x01CO BFFF 4K LCD 0 0x01C0 C000 0x01CO CFFF 4K LCD 1 0x01CO D000 0x01CO DFFF 4K VE 0x01CO E000 0x01CO EFFF 4K SD MMC 0 0x01CO F000 0x01CO0 F
328. h in pixels The width The value of these bits add 1 35 5 8 Input DMA memory block coordinate control register Offset Register Name MP_IDMACOOR_REG iDMA0 0x40 iDMA 1 0x44 iDMA2 0x48 iDMA3 0x4C Bit Read W Default Description rite Hex IDMA YCOOR Y coordinate Y is the left top y coordinate of layer on output window in pixels The Y represent the two s complement IDMA XCOOR X coordinate X is left top x coordinate of the layer on output window in pixels The X represent the two s complement A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 464 2012 04 09 Allwinner Technology CO Ltd A10 35 5 9 Input DMA setting register Offset Register Name MP IDMASET REG iDMA0 0x50 iDMA1 0x54 iDMA2 0x58 iDMA3 0x5C Bit Read W Default Description rite Hex 31 24 R W IDMA_GLBALPHA Globe alpha value mer p T R W IDMA_FCMODEN Fill color mode enable control 0 disable 1 enable 15 12 R W IDMA_PS Input data pixel sequence Reference input pixel sequence table IDMA_FMT Input data format 0x0 32bpp A8R8G8B8 or interleaved AYUV8888 Ox1 16bpp A4R4G4B4 Ox2 16bpp AIRSG5B5 0x3 16bpp R5G6B5 Ox4 16bpp interleaved YUV422 0x5 16bpp U8V8 Ox6 8bpp Y8 0x7 8bpp MONO or palette 0x8 4bpp MONO or palette 0x9 2bpp MONO or palette Oxa I bpp MONO or palette Other reserved Note if the input data format is
329. hat regardless of the number of stop bits selected the receiver checks only the first stop bit 0 1 stop bit 1 1 5 stop bits when DLS LCR 1 0 is zero else 2 2 R W stop bit DLS Data Length Select 1 0 R W It is writeable only when UART is not busy USR 0 A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 187 2012 04 09 Ou Allwinner Technology CO Ltd A10 is zero and always readable This is used to select the number of data bits per character that the peripheral transmits and receives The number of bit that may be selected areas follows 00 5 bits O1 6 bits 10 7 bits 11 8 bits 18 4 9 UART Modem Control Register Register Name UART MCR Offset 0x10 Default Value 0x0000 0000 Bit Read Write Default Description 31 7 SIRE SIR Mode Enable 0 IrDA SIR Mode disabled 6 R W 0 1 IrDA SIR Mode enabled AFCE Auto Flow Control Enable When FIFOs are enabled and the Auto Flow Control Enable AFCE bit is set Auto Flow Control features are enabled 0 Auto Flow Control Mode disabled 5 R W 0 1 Auto Flow Control Mode enabled LOOP Loop Back Mode 0 Normal Mode 1 Loop Back Mode This is used to put the UART into a diagnostic mode for test purposes If operating in UART mode SIR MODE Enabled or not active MCR 6 set to zero data on the sout line is held high while serial data output is looped back to the si
330. he data frame UART Universal Asynchronous Receiver Transmitter Used for serial communication with a peripheral modem data carrier equipment DCE or data set DMA Dynamic Memory Allocation The allocation of memory storage for use in a computer program during the run time of that program DS IIS An electrical serial bus interface standard used for connecting digital audio devices together PCM Pulse Code Modulation Method used to digitally represent sampled analog signals 10 AC97 Audio Codec 97 Intel Corporation s Audio Codec standard developed by the Intel Architecture Labs in 1997 and used mainly in motherboards modems and sound cards 11 Audio Codec Audio Codec A computer program implementing an algorithm that compresses and decompresses digital audio data according to a given audio file format or streaming media audio format 12 SD Security Digital3 0 A non volatile memory card format developed by the SD Card Association for use in portable devices USB On The Go Dual role controller which supports both Host A10 U ser Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 2 2012 04 09 e Allwinner Technology CO Ltd A10 13 USB OTG and device functions and is full compliant with the On The Go Supplement to the USB 2 0 Specific
331. he result of the add or multiply operation will select the high 8 byte operation or 32bits word operation A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 475 2012 04 09 Allwinner Technology CO Ltd A10 35 5 22 Alpha Color key control register Offset 0xCO Register Name MP ALPHACKCTL REG Bit Read W Default Description rite Hex CK REDCON Red control condition 0 if R value of ck min color lt R value of layer0 lt R value of ck max color The red control condition is true else the condition is false 1 if R value of ck min color R value of layerO or R value of layerO R value of ck max color The red control condition is true else the condition is false CK GREENCON Green control condition 0 if G value of ck min color lt G value of layerO lt G value of ck max color The green control condition is true else the condition is false 1 if G value of ck min color gt G value of layerO or G value of layer0 gt G value of ck max color The green control condition is true else the condition is false CK BLUECON Blue control condition 0 if B value of ck min color lt B value of layer0 lt B value of ck max color The blue control condition is true else the condition is false Alpha Color key mode selection 0 alpha mode A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology
332. height 15 00 R W SCA_VERFRAFCT The fractional part of the vertical scaling ratio the vertical scaling ratio input height output height The input height is the memory block height of respective iDMA channel 35 5 17 Scaler horizontal start phase setting register Offset 0x90 Register Name MP SCAHORPHASE REG Bit Read W Default Description rite Hex 19 00 R W o SCA HORPHASE A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 470 2012 04 09 Ou Allwinner Technology CO Ltd A10 Start phase in horizontal complement This value equals to start phase 2 35 5 18 Scaler vertical start phase setting register Offset 0x94 Register Name MP_SCAVERPHASE_REG Bit Read W Default Description rite Hex 19 00 R W SCA_VERPHASE Start phase in vertical complement This value equals to start phase 2 35 5 19 ROP control register Offset 0xB0 Register Name MP_ROPCTL_REG Bit Read W Default Description Wd NN 15 14 R W ROP ALPHABYPASSSEL ROP output Alpha channel selection 0 channel 0 1 channel 1 2 channel 2 3 reserved Note the bit is only valid in by pass mode of Alpha channel 13 12 R W ROP_REDBYPASSSEL ROP output Red channel selection 0 channel 0 1 channel 1 2 channel 2 3 reserved Note the bit is only valid in by pass mode of Red channel 11 10 R W ROP_GREENBYPASSSEL ROP output Green channel selection 0 channe
333. ilter is operating or bypassed 15 12 11 9 R W 4 DAC3_Delay 000 The DAC3 lags DACO by 4 encoder clock cycles 001 The DAC3 lags DACO by 3 encoder clock cycles 010 The DAC3 lags DACO by 2 encoder clock cycles 011 The DAC3 lags DACO by 1 encoder clock cycle 100 There is no delay between the DACO and DAC3 signals 001 The DACO lags DAC3 by 1 encoder clock cycle 010 The DACO lags DAC3 by 2 encoder clock cycles 011 The DACO lags DAC3 by 3 encoder clock cycles DACH and DACO paths relative delays default 4 stages Relative delay between DAC3 and DACO selection These bits select the relative delay between the DACH samples and DACO samples The delay range from 4 encoder clock cycles of DAC3 lagging the DACO samples to 3 encoder clock cycles of DAC3 preceding the DACO samples 8 6 R W 4 DAC2 Delay 000 The DAC2 lags DACO by 4 encoder clock cycles 001 The DAC2 lags DACO by 3 encoder clock cycles 010 The DAC2 lags DACO by 2 encoder clock cycles 011 The DAC2 lags DACO by 1 encoder clock cycle 100 There is no delay between the DACO and DAC2 signals 001 The DACO lags DAC2 by 1 encoder clock cycle 010 The DACO lags DAC2 by 2 encoder clock cycles 011 The DACO lags DAC2 by D encoder clock cycles DAC2 and DACO paths relative delays default 4 stages Relative delay between DAC2 and DACO selection These bits select the relative delay between the DAC2 samples and DACO samples The delay range from 4 encoder c
334. ine is not greater than 20 then NumLines is restricted to be greater than 77 When PAL and FirstVideoLine is greater than 22 then NumLines is restricted to be greater than 2 FirstVideoLine 18 When PAL and FirstVideoLine is not greater than 22 then NumLines is restricted to be greater than 81 If NumLines is even then it is restricted to be divisible by 4 If NumLines is odd then it is restricted to be divisible by 4 with a remainder of 1 34 4 8 TV Encoder Level Register Offset 0x020 Register Name TVE 020 REG Bit Read Default Description Write Hex 31 26 25 16 R W OFO Blank_Level Specify the blank level setting for active lines 10 bit unsigned integer Allowed range 0 to 1023 Default value is hexFO dec240 15 10 9 0 R W lla Black_Level Specify the black level setting 10 bit unsigned integer Allowed range is 240 to 1023 Default value is 282 34 4 9 TV Encoder DAC Register2 Offset 0x024 Register Name TVE_024_REG Bit Read Default Description Write Hex 31 29 28 24 R W 0000 Internal DAC3 Amplitude Control 00000 smallest 11111 biggest 23 21 20 16 R W 0000 Internal DAC2 Amplitude Control 00000 smallest 11111 biggest 15 13 12 8 R W 0000 Internal DAC1 Amplitude Control 00000 smallest A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 433 2012 04 09
335. ing interrupt is enable the interrupt line is asserted to CPU When the duration of signal keeps one status high or low level for the specified duration ITHR 1 128 sample_clk this means that the previous CIR 15 8 R W Ox18 command has been finished NTHR Noise Threshold for CIR When the duration of signal pulse high or low level is less than NTHR the pulse is taken as noise and should be discarded by hardware 0 all samples are recorded into RX FIFO 1 If the signal is only one sample duration it is taken as noise and discarded 2 If the signal is less than lt two sample duration it is taken as noise and discarded 61 if the signal is less than lt sixty one sample 7 2 R W Oxa duration it is taken as noise and discarded A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 211 2012 04 09 Ou Allwinner Technology CO Ltd A10 1 0 SCS Sample Clock Select for CIR 0 CIR sample_clk is ir_clk 64 1 CIR sample_clk is ir_clk 128 2 CIR sample_clk is ir_clk 256 3 CIR sample_clk is ir_clk 512 FPR Force Port Resume 1 Resume detected driven on port 0 No resume K state detected driven on port Default value 0 This functionality defined for manipulating this bit depends on the value of the Suspend bit For example if the port is not suspend and software transitions this bit to a one then the effects on the bus are undefined Software
336. ing the image data For still capture the bit is set when one frame data has been wrote to buffer For video capture the bit is set when the last frame has been wrote to buffer after video capture has been disabled For CCIR656 interface if the output format is frame planar YCbCr 420 mode the frame end means the field2 end the other frame end means field end 31 6 27 CSI Channel 1 interrupt status register Offset Address 0X0134 Register Name CSIO C1 INT STA REG Bit Read Default Description Write Hex A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 354 2012 04 09 Allwinner Technology CO Ltd A10 VS PD vsync flag R W HB OF PD Hblank FIFO overflow 04 R W FIFO2 OF PD FIFO 2 overflow 03 R W FIFO1 OF PD FIFO 1 overflow 02 R W FIFOO0 OF PD FIFO 0 overflow 01 R W FD PD mm mmm R W CD PD mm Jeee o 31 6 28 CSI Channel_1 horizontal size register Offset Address 0X0140 Register Name CSIO C1 HSIZE REG Read Default Description Write Hex ms porn 28 16 R W HOR LEN Horizontal pixel clock length Valid pixel clocks of a line nuu mm 12 00 R W HOR_START Horizontal pixel clock start Pixel data is valid from this clock 31 6 29 CSI Channel 1 vertical size register Offset Address 0X0144 Register Name CSIO C1 VSIZE REG Read Default Description Write Hex m orn E 28 16 R W VER LEN Vertical line length Valid line numbe
337. inner Technology All Rights Reserved 2012 04 09 235 Allwinner Technology CO Ltd A10 22 5 3 Digital Audio Interface Clock Source andFrequency There are two clocks for Digital Audio Interface One is from APB bus and one is from Audio PLL Name Description Audio PLL 24 576Mhz or 22 528Mhz generated by Audio PLL APB CLK APB bus system clock In DS mode it is requested gt 0 25 BCLK In PCM mode it is requested gt 0 5 BCLK A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 236 2012 04 09 Ou Allwinner Technology CO Ltd A10 23 AC97 Interface 23 1 Overview The AC97 interface supports AC97 revision 2 3 AC97 Controller uses audio Controller link AC link to communicate with AC97 Codec In transmission mode Controller sends the stereo PCM data to Codec The external digital to analog converter DAC in the Codec converts the audio sample to an analog audio waveform In receiving mode Controller receives the stereo PCM data and the mono Microphone data from Codec then stores in memories AC97 Interface includes below features Compliant with AC97 2 3 component Specification Full duplex synchronous serial interface Support 2 channels TX stereo RX PCM stereo MIC mono optional Variable Sampling Rate AC97 Codec Interface support up to 48KHz Support 2 channel and 6 channel audio data output Support DRA mode Support Only one primary Cod
338. inner Technology CO Ltd A10 Over current Active 0 This port does not have an over current condition 1 This port currently has an over current condition This bit will automatically transition from a one to a zero when the over current condition is removed The default value of this bit is 0 R WC PEDC Port Enable Disable Change Default 0 1 Port enabled disabled status has changed 0 No change For the root hub this bit gets set to a one only when a port is disabled due to the appropriate conditions existing at the EOF2 point See Chapter 11 of the USB Specification for the definition of a Port Error Software clears this bit by writing a I to it This field is zero if Port Power is zero PED Port Enabled Disabled 1 Enable 0 Disable Ports can only be enabled by the host controller as a part of the reset and enable Software cannot enable a port by writing a one to this field The host controller will only set this bit to a one when the reset sequence determines that the attached device is a high speed device Ports can be disabled by either a fault condition disconnect event or other fault condition or by host software Note that the bit status does not change until the port state actually changes There may be a delay in disabling or enabling a port due to other host controller and bus events When the port is disabled downstream propagation of data is blocked on this port except for reset
339. interrupt CAN 26 0x0068 CAN Bus controller interrupt DMA 27 0x006C DMA channel interrupt PIO 28 0x0070 PIO interrupt Touch Panel 29 0x0074 Touch Panel interrupt Audio Codec 30 0x0078 Analog Aduio Codec interrupt LRADC 31 0x007C LRADC interrupt SD MMC 0 32 0x0080 SD MMC Host Controller 0 interrupt SD MMC 1 33 0x0084 SD MMC Host Controller 1 interrupt SD MMC 2 34 0x0088 SD MMC Host Controller 2 interrupt SD MMC 3 35 0x008C SD MMC Host Controller 3 interrupt 36 NAND 37 0x0094 NAND Flash Controller NFC interrupt USB 0 38 0x0098 USB 0 wakeup connect disconnect interrupt USB 1 39 0x009C USB 1 wakeup connect disconnect interrupt USB2 40 0x00A0 USB 2 wakeup connect disconnect interrupt SCR 41 0x00A4 SCR interrupt CSIO 42 0x00A8 CSI 0 interrupt CSI I 43 0x00AC CSI 1 interrupt LCD Controller 0 44 0x00BO LCD Controller 0 interrupt LCD Controller 1 45 0x00B4 LCD Controller 1 interrupt MP 46 0x00B8 MP interrupt DE FEO DE BEO 47 0x00BC DE FEO DE BEO interrupt DE FE1 DE BE1 48 0x00CO DE FEI DE BEI interrupt A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 110 2012 04 09 Ou Allwinner Technology CO Ltd A10 Interrupt SRC Vector FIQ Description Source PMU 49 0x00C4 PMU interrupt SPI3 50 0x00C8 SPD interrupt TZASC 51 0x00CC TZASC interrupt PATA 52 0x00DO
340. iption Write Hex 31 28 27 25 24 R W 1 DAC_Clock_Invert 0 not invert 1 invert 23 22 21 20 R W 10 DAC_Ref2_Connect3 00 0 25 01 0 3 10 0 35 11 0 4 Note ref2 used to detect luma 19 18 R W 10 DAC_Ref1_Connect2 00 0 6 01 0 65 10 0 7 11 0 75 Note refl used to detect chroma 17 16 R W 11 Internal DAC Mode Sel 0 150ohms terminal mode A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 427 2012 04 09 Ou Allwinner Technology CO Ltd A10 2 75 ohms terminal mode 3 37 5 ohms terminal mode 15 13 R W 0 DAC3_Src_Sel 000 Composite 001 Luma 010 Chroma 011 Reserved 100 Y Green 101 U Pb Blue 110 V Pr Red 111 Reserved 12 10 R W 0 DAC2_Src_Sel 000 Composite 001 Luma 010 Chroma 011 Reserved 100 Y Green 101 U Pb Blue 110 V Pr Red 111 Reserved 9 7 R W 0 DACI Src Sel 000 Composite 001 Luma 010 Chroma 011 Reserved 100 Y Green 101 U Pb Blue 110 V Pr Red 111 Reserved 6 4 R W 0 DACH Src Sel 000 Composite 001 Luma 010 Chroma 011 Reserved 100 Y Green 101 U Pb Blue 110 V Pr Red 111 Reserved 3 R W 0 Internal DAC3 En O disable enable 2 R W 0 Internal DAC2 En O disable A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 428 2012 04 09 Ou Allwinner Technology CO Ltd A10 enable R W Internal DAC1 En O d
341. ir656 field_reverse 0 R W 0 CSI EN Enable 0 Reset and disable the CSI module 1 Enable the CSI module 32 6 2 CSI configuration register Offset Address 0X0004 Register Name CSI1 CFG REG Bit Read Default Description Write Hex INPUT FMT Input data format 000 RAW stream 001 reserved 010 CCIR656 one channel gt 011 YUV422 100 YUV444 IR B G or Pr Pb Y others reserved OUTPUT FMT Output data format When the input format is set RAW stream 0000 pass through When the input format is set CCIR656 interface 0000 field planar YCbCr 422 0001 field planar YCbCr 420 0010 frame planar YCbCr 420 0011 frame planar YCbCr 422 0100 field planar YCbCr 422 UV combined 0101 field planar YCbCr 420 UV combined 0110 frame planar YCbCr 420 UV combined 0111 frame planar YCbCr 422 UV combined 1111 interlaced interleaved YCbCr422 In this mode capturing interlaced input and output the interlaced fields from individual ports Field 1 data will be wrote to FIFOO output buffer and field 2 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 387 2012 04 09 GZ Technology CO Ltd A10 data will be wrote to FIFO1 output buffer 1000 field MB YCbCr 422 1001 field MB YCbCr 420 1010 frame MB YCbCr 420 1011 frame MB YCbCr 422 When the input format is set YUV422 0000 planar YUV 422 0001 planar YUV 420 0100 planar YUV 422 UV
342. is calculated from the values of its adjacent pixels on the input grid To find these adjacent pixels need overlay the output grid on the input grid and align the starting pixels XOYO of the two grids To identify the adjacent input pixels for a given output pixel you divide the output pixel X pixel number along the output line and Y pixel line number within window by their corresponding scaling factors Xout Xin horizontal scaling factor where horizontal scaling factor input width output width Yout Yin vertical scaling factor where vertical scaling factor input height output height Note that the resulting Xin and Yin values will be real numbers because the output pixels will usually fall between the input pixels The fractional portion indicates the fractional distance to the next pixel To calculate the output pixel value you use the value for the nearest pixel to the left and above and combine it with the value of the other adjacent pixel s For example horizontal interpolation uses the starting pixel to the left interpolated with the next pixel to the right with the fractional value used to determine the weighting for the interpolation Quantizing The new position is forced to be at a location n 32 in H and V relative to the position of the original pixel grid TapO Tap1 Tap2 Tap3 Uwe 0 15 23 31 X Pixel Location Horizontal quantizing A10 User Manual V1 20 Copyright O 2011
343. is writable only when LINE TRGO is disabled 15 11 10 0 R W 0 TCONI1 Line Int Num scan line for TCONI line trigger including inactive lines Setting it for the specified line for trigger 1 Note SY1 is writable only when LINE TRGI is disabled 33 4 4 TCON FRM control register Offset 0x010 Register Name TCON FRM CTL REG Bit Read Default Description Write Hex 31 R W 0 TCONO_Frm_En 0 disable l enable 30 7 6 R W 0 TCONO_Frm_Mode_R 0 6bit frm output 1 Sbit frm output 5 R W 0 TCONO Frm Mode G 0 6bit frm output 1 5bit frm output 4 R W 0 TCONO Frm Mode B 0 6bit frm output 1 5bit frm output 3 2 1 0 R W 0 TCONO Frm Test 00 FRM 01 half 5 6bit half FRM 10 half 8bit half FRM 11 half 8bit half S 6bit A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 2012 04 09 400 Allwinner Technology CO Ltd A10 33 4 5 TCON FRM seed register Offset 0x014 Register Name TCON_FRM_PSEED_R_REG Bit Read Default Description Write Hex 31 25 24 0 R W 0 Pixel_Seed_Value Note avoid set it to 0 Offset 0x018 Register Name TCON FRM PSEED G REG Bit Read Default Description Write Hex 31 25 24 0 R W 0 Pixel_Seed_Value Note avoid set it to 0 Offset 0x01C Register Name TCON FRM PSEED B REG Bit Read Default D
344. isable enable R W Internal DACH En O disable l enable 34 4 3 TV Encoder Notch and DAC Delay Register Offset 0x00C Register Name TVE_00C_REG Bit Read Write Default Hex Description 31 R W 0 Chroma_Filter_Active_Valid 0 Disable 1 Enable 30 25 24 R W HD_Mode_CB_Filter_Bypass 0 Bypass Enable 1 Bypass Disable 23 R W HD_Mode_CR_Filter_Bypass 0 Bypass Enable 1 Bypass Disable 22 R W Chroma Filter 1 444 En 0 Chroma Filter 1 444 Disable 1 Chroma Filter 1 444 Enable 21 R W Chroma HD Mode Filter En 0 Chroma HD Filter Disable 1 Chroma HD Filter Enable 20 R W Chroma Filter Stage 1 Bypass 0 Chroma Filter stage 1 Enable 1 Chroma Filter stage 1 bypass 19 R W Chroma_Filter_Stage_2_ Bypass 0 Chroma Filter stage 2 Enable 1 Chroma Filter stage 2 bypass 18 R W Chroma Filter Stage 3 Bypass 0 Chroma Filter stage 3 Enable 1 Chroma Filter stage 3 bypass 17 R W Luma Filter Bypass 0 Luma Filter Enable 1 Luma Filter bypass 16 R W Notch En A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 429 2012 04 09 Ou v Allwinner Technology CO Ltd A10 0 The luma notch filter is bypassed 1 The luma notch filter is operating Luma notch filter on off selection Note This bit selects if the luma notch f
345. ise or fall plus flight time Primary Codec to Controller or Secondary SDATA combined rise or fall plus flight time Output to Input Note Combined rise or fall plus flight times are provided for worst case scenario modeling purposes BIT_CLK fL Trise ay ns E L Tfal SYNC ZN Tfal UE sync SDATA_IN A n3 Trise jir Be Tfall gin SDATA OUT hl Trise e Tfall Fig23 10 Signal rise and fall timing diagram Table23 8 Signal Rise and Fall Time Parameters BIT CLKfall me Note 1 Tfally 6 ms SYNG rise time Note 2 Triste 6 m SYNC fall time Note 2 Ui 6 ms SDATA IN rise time Note 3 Triseam J 6 ms SDATA IN fall time Note 3 Tfalla 6 f ms SDATA_OUT rise time Note 2 Triseg J 6 ms BIT CLK rise fall times with an external load of 75 pF SYNC and SDATA OUT rise fall times with a external load of 75 pF SDATA IN rise fall times with an external load of 60 pF Rise is from 10 to 90 of Vdd Vy to Voy Fall is from 90 to 10 of Vdd Von to Vo A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 244 2012 04 09 Allwinner Technology CO Ltd A10 23 6 AC97 Interface Register List Module Name Base Address AC97 0x01C21400 Register Name Offset Description AC CIL 0x00 AC97 Co
346. ister present the vector address for the interrupt currently A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 112 2012 04 09 Ou Allwinner Technology CO Ltd A10 active on the CPU IRQ input 1 0 R 0x0 Always return zero to this field 11 4 2 Interrupt Base Address Register Default 0x00000000 Offset 0x04 Register Name INTC_BASE_ADDR_REG Bit Read Default Description Write Hex 31 2 R W 0x0 BASE_ADDR This bit field holds the upper 30 bits of the base address of the vector table 1 0 R 0x0 Always write zero to this bit field 11 4 3 Interrupt Protection Register Default 0x00000000 Offset 0x08 Register Name INTC_PROT_EN Bit Read Default Description Write Hex 31 1 0 R W 0x0 INTC PROT EN Enables or disables protected register access 0 disable protection mode 1 enable protection mode If enabled only privileged mode accesss can access the interrupt controller registers If disabled both user mode and privileged mode can access the registers This register can only be accessed in privileged mode 11 4 4 NMI Interrupt Control Register Default 0x00000000 Offset 0x0C Register Name NMI_INT_CTRL_REG Bit Read Default Description Write Hex 31 2 1 0 R W 0x0 NMI SRC TYPE External NMI Interrupt Source Type External NMI pin will b
347. it 26 specify if the R signal have embedded syncs bit 25 specify if the G signal have embedded syncs and bit 24 specify if the B signal have embedded syncs When comp yuv is equal to B 1 these bits are N A and should be set to B 000 When the value is different from B 000 RGBSetup should be set to B 1 23 17 16 R W 0 RGB Setup Set up enable for RGB outputs This bit specifies if the set up implied value black level blank level specified for the CVBS signal is used also for the RGB A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 441 2012 04 09 Ou Allwinner Technology CO Ltd A10 signals 0 The set up is not used or N A i e comp yuv is equal to B 1 1 The implied set up is used for the RGB signals 15 1 R W Bypass_YClamp Y input clamping selection This bit selects whether the Video Encoder Y input is clamped to 64 to 940 or not When not clamped the expected range is 0 to 1023 The U and V inputs are always clamped to the range 64 to 960 0 The Video Encoder Y input is clamped 1 The Video Encoder Y input is not clamped 34 4 27 TV Encoder MacroVision Control Register Offset 0x200 Register Name TVE_200_REG Bit Read Default Description Write Hex 31 9 8 R W 0 Sys625 Macrovision timing parameters selection This bit selects whe
348. it serial mode 30 R W 0 Serial_Mode A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 405 2012 04 09 Ou Allwinner Technology CO Ltd A10 0 8bit 3cycle RGB serial mode RGB888 1 8bit 2cycle YUV serial mode CCIR656 29 28 27 26 R W RGB888 SMO serial RGB888 mode Output sequence at odd lines of the panel line 1 3 5 Tese 00 R gt G B 01 BOR G 10 GGBR 11 ROG 9B 25 24 R W RGB888 SM1 serial RGB888 mode Output sequence at even lines of the panel line 2 4 6 8 00 R gt G B 01 BOR G 10 GGBR 11 R gt G B 23 22 R W YUV SM serial YUV mode Output sequence 2 pixel pair of every scan line 00 YUYV 01 YVYU 10 UYVY 11 VYUY 21 20 R W YUV EAV SAV F line delay 0 F toggle right after active video line 1 delay 2 line CCIR NTSC 2 delay 3 line CCIR PAL 3 reserved 19 0 33 4 14 TCONO cpu panel interface register Offset 0x060 Register Name TCONO CPU IF REG Bit Read Default Description Write Hex 31 29 R W 0 CPU MOD 000 18bit 256K mode 001 16bit mode 010 16bit model 011 16bit mode2 100 16bit mode3 101 9bit mode A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 406 2012 04 09 Ou Allwinner Technology CO Ltd A10 110 8bit 256K mode 111 8bit 65K mode 28 R W AU
349. it the STOP condition if in master mode then transmit the START condition A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 156 2012 04 09 Ou Allwinner Technology CO Ltd A10 The M STP bit is cleared automatically writing a 0 to this bit has no effect INT_FLAG Interrupt Flag INT_FLAG is automatically set to 1 when any of 28 out of the possible 29 states is entered see STAT Register below The only state that does not set INT FLAG is state F8h If the INT EN bit is set the interrupt line goes high when IFLG is set to 1 If the TWI is operating in slave mode data transfer is suspended when INT_FLAG is set and the low period of the 2 wire bus clock line SCL is stretched until 0 is written to INT_FLAG The 2 wire clock line is then released and the 3 R W 0 interrupt line goes low A_ACK Assert Acknowledge When A_ACK is set to 1 an Acknowledge low level on SDA will be sent during the acknowledge clock pulse on the 2 Wire bus if 1 Either the whole of a matching 7 bit slave address or the first or the second byte of a matching 10 bit slave address has been received 2 The general call address has been received and the GCE bit in the ADDR register is set to 1 3 A data byte has been received in master or slave mode When A_ACK is 0 a Not Acknowledge high level on SDA will be sent when a data byte is recei
350. k Memory Block Source copy to destination Memory scan order illustration 35 3 4 Color space converter Conversion algorithm formula R Y R Y component coefficient Y Y R component coefficient R R U component coefficient U Y G component coefficient G R V component coefficient V Y B component coefficient B A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 447 2012 04 09 Ou Allwinner Technology CO Ltd A10 R constant G G Y component coefficient Y G U component coefficient U G V component coefficient V G constant B B Y component coefficient Y B U component coefficient U B V component coefficient V B constant Y constant U U R component coefficient R 4 U G component coefficient G U B component coefficient B U constant V V R component coefficient R V G component coefficient G V B component coefficient B V constant 35 3 5 Formatter In MP ALU include Color space converter ROP module Alpha Color key module scaler etc all logic operation is based 32 bits ARGB format All MP input Format Input Formatter if p MP ALU In MP ALU all logic op Output Formatter eration is based 32 bit ARGB format p Input formatter rule The high significant bits fill rule A
351. l 0 1 channel 1 2 channel 2 3 reserved A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 471 2012 04 09 Allwinner Technology CO Ltd A10 Note the bit is only valid in by pass mode of Green channel ROP BLUEBYPASSSEL ROP output Blue channel selection 0 channel 0 1 channel 1 2 channel 2 3 reserved Note the bit is only valid in by pass mode of Blue channel ROP_ALPHABYPASSEN ROP Alpha channel by pass enable control O pass through 1 by pass ROP_REDBYPASSEN ROP Red channel by pass enable control O pass through 1 by pass ROP_GREENBYPASSEN ROP Green channel by pass enable control O pass through 1 by pass ROP type selection 0 ROP3 1 ROP4 In ROP3 mode only the value of channel 3 index 0 control table setting register will be selected In ROP3 mode the channel 3 data will by pass the ROP module In ROP3 mode the channel 3 data will direct to Alpha CK module In ROP4 mode the respective input DMA channel fill color of channel 3 will transfer to Alpha CK module A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 472 2012 04 09 Allwinner Technology CO Ltd A10 35 5 20 ROP channel 3 index 0 control table setting register Offset 0xB8 Register Name MP ROPIDXOCTL REG Bit Read W Default Description rite Hex NOD7 CTL Index 0 node setting channel 0 and channel 1
352. l 3 highest priority 23 22 R W 0x0 IRQ 27 Priority Set priority level for IRQ bit 27 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 122 2012 04 09 Ou Allwinner Technology CO Ltd A10 Offset 0x84 Register Name INTC_PRIO_REG1 LevelO 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority 21 20 R W 0x0 IRQ 26 Priority Set priority level for IRQ bit 26 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority 19 18 R W 0x0 IRQ 25 Priority Set priority level for IRQ bit 25 Level0 0x0 level 0 lowest priority Levell 0x1 level 1 Level2 Ox1 level 2 Level3 Ox1 level 3 highest priority 17 16 R W 0x0 IRQ 24 Priority Set priority level for IRQ bit 24 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 Ox1 level 2 Level3 0x1 level 3 highest priority 15 14 R W 0x0 IRQ 23 Priority Set priority level for IRQ bit 23 Level 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 Ox1 level 2 Level3 Ox1 level 3 highest priority 13 12 R W 0x0 IRQ 22 Priority Set priority level for IRQ bit 22 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 Ox1 level 2 Level3 Ox1 level 3 highest priority 11 10 R W 0x0 IRQ 21 Priority Set priority level for IRQ bit 2
353. l2 0x1 level 2 Level3 Ox1 level 3 highest priority 5 4 R W 0x0 IRQ50 PRIO A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 129 2012 04 09 Ou Allwinner Technology CO Ltd A10 Offset 0x8C Register Name INTC_PRIO_REG3 IRQ 50 Priority Set priority level for IRQ bit 50 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority 3 2 R W 0x0 IRQ49_PRIO IRQ 49 Priority Set priority level for IRQ bit 49 Level0 0x0 level 0 lowest priority Levell 0x1 level 1 Level2 Ox1 level 2 Level3 Ox1 level 3 highest priority 1 0 R W 0x0 IRQ48_PRIO IRQ 48 Priority Set priority level for IRQ bit 48 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 Ox1 level 2 Level3 0x1 level 3 highest priority 11 4 30 Interrupt Source Priority 4 Register Default 0x00000000 Offset 0x90 Register Name INTC PRIO REGS Bit Read Default Description Write Hex 31 30 R W 0x0 IRQ79 PRIO IRQ 79 Priority Set priority level for IRQ bit 79 Level 0x0 level 0 lowest priority Levell 0x1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority 29 28 R W 0x0 IRQ78_PRIO IRQ 78 Priority Set priority level for IRQ bit 78 Level0 0x0 level 0 lowest priority Levell 0x1 level 1 Level2 0x1 level 2
354. lapping area R Ra Aa Rb Ab 1 A a G Ga Aa G b A b I1 A a B Ba Aa Bb Ab 1 A a In the fill color area R R_fa A_fa R fb A fb 1 A fa G G_fa A_fa Gfb A fb I A fa B B_fa A_fa B fb A fb 1 A fa Color key Matching Condition Input Color Output Color Input Color Color Key Matching MUX y g MUX Color Key Theory Block In MP the process of color key will be done in Alpha Blender Color key module 2 channels data will be processed at the same coordinate of screen If the color key function is enabled the higher priority channel will match another channel See the following Diagram Layer A Layer B Fill color area in output Matching Area The priority of layer A is higher than layer B A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 454 2012 04 09 Ou Allwinner Technology CO Ltd A10 The alpha value of layer A a The alpha value of layer B A_b The RGB value of layer A R_a G a B_a The RGB value of layer B R_b G_b B_b The alpha value of layer A fill color A fa The alpha value of layer B fill color A_fb The RGB value of layerA fill color R_fa G_fa B_fa The RGB value of layerB fill color R_fb G_fb B_fb In none matching area As same as normal alpha blending process In matching area Layer A match layer B because of the higher priority of layer A R R
355. le with AC97 version 2 3 standard Internal 24 bits Audio Codec for 2 channel headphone 2 channel microphone 2 channel FM input and Line input B 2PWM controller A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 26 2012 04 09 Allwinner Technology CO Ltd A10 1 1 9 System M 8 channel normal DMA and 8 channel dedicateed DMA M Internal 32K 64K SRAM on chip B 4 timer I RTC timer and 1 watchdog 1 1 10 Security M Security System W Support DES 3DES AES encryption and decryption B Support SHA 1 MD5 message digest W Support hardware 64 bit random generator W 128 bits EFUSE chip ID 1 1 11 Package B TFBGA441package B 0 8mm pitch 2 Pin Description Notes see details in datasheet of A10 2 1 Pin Placement Table Notes see details in datasheet of A10 2 2 Pin Detail Description Notes see details in datasheet of A10 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 27 2012 04 09 O Allwinner Technology CO Ltd A10 3 Architecture 3 1 General Block Diagram System Peripheral Multi Media d Timer 6 ch p CSI C PLL D 4 Video Decoder C PWM C DMA 16 ch C LRADC 2 k Peripheral Interface mm d SPI PIO USBOTG SD MMC Aa F Y wW IIS Audio Codec J 4 Touc
356. level 1 Level2 Ox1 level 2 Level3 Ox1 level 3 highest priority 17 16 R W 0x0 IRQ56 PRIO A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 128 2012 04 09 Ou Allwinner Technology CO Ltd A10 Offset 0x8C Register Name INTC_PRIO_REG3 IRQ 56 Priority Set priority level for IRQ bit 56 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority 15 14 R W 0x0 IRQ55_PRIO IRQ 55 Priority Set priority level for IRQ bit 55 Level0 0x0 level 0 lowest priority Levell 0x1 level 1 Level2 Ox1 level 2 Level3 Ox1 level 3 highest priority 13 12 R W 0x0 IRQ54_PRIO IRQ 54 Priority Set priority level for IRQ bit 54 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 Ox1 level 2 Level3 0x1 level 3 highest priority 11 10 R W 0x0 IRQ53_PRIO IRQ 53 Priority Set priority level for IRQ bit 53 Level0 0x0 level 0 lowest priority Levell 0x1 level 1 Level2 Ox1 level 2 Level3 Ox1 level 3 highest priority 9 8 R W 0x0 IRQ52_PRIO IRQ 52 Priority Set priority level for IRQ bit 52 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 Ox1 level 2 Level3 Ox1 level 3 highest priority 7 6 R W 0x0 IRQ51_PRIO IRQ 51 Priority Set priority level for IRQ bit 51 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Leve
357. ligned Although the increase mode of Normal DMA should be address aligned but there is no need for its byte counter always goes in multiple The Dedicated DMA can only transfer data between DRAM and modules DMA Source Address Destination Address can be modified even if DMA transfers have started 12 2 DMA Register List Module Name Base Address DMA 0x01C02000 Register Name Offset Description DMA IRQ EN REG 0x0000 DMA IRQ Enable DMA IRQ PEND STA REG 0x0004 DMA IRQ Pending Status Normal DMA Configuration NDMA CTRL REG 0x100 N 0x20 N 0 1 2 3 4 5 6 7 Normal DMA Source Address NDMA SRC ADDR REG 0x100 N 0x20 4 N 0 1 2 3 4 5 6 7 Normal DMA Destination Address NDMA DEST ADDR REG 0x100 N 0x20 8 N 0 1 2 3 4 5 6 7 Normal DMA Byte Counter NDMA BC REG 0x100 N 0x20 C N 0 1 2 3 4 5 6 7 Dedicated DMA Configuration DDMA_CFG_REG 0x300 N 0x20 N 0 1 2 3 4 5 6 7 Dedicated DMA Source Start DDMA_SRC_START_ADDR_REG 0x300 N 0x20 4 Address A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 2012 04 09 134 Ou Allwinner Technology CO Ltd A10 N 0 1 2 3 4 5 6 7 Dedicated DMA Destination Start Address DDMA DEST START ADDR REG 0x300 N 0x20 8 N 0 1 2 3 4 5 6 7 Dedicated DMA Byte Counter DDMA BC REG 0x300 N 0x20 C N 0 1 2 3 4 5 6 7 Dedicated DMA Parameter DDMA PARA REG 0x300 N 0x20 0x18 N 0 1 2 3 4
358. lock cycles of DAC2 lagging the DACO samples to 3 encoder clock cycles of DAC2 preceding the DACO samples 5 3 R W 4 DACI Delay 000 The DACI lags DACO by 4 encoder clock cycles 001 The DACI lags DACO by 3 encoder clock cycles 010 The DACI lags DACO by 2 encoder clock cycles DACI and DACO paths relative delays default 4 stages Relative delay between DAC1 and DACO selection These bits select the relative delay between the DAC1 samples and DACO samples The delay range from 4 encoder clock cycles of DACI A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 430 2012 04 09 Ou Allwinner Technology CO Ltd A10 lagging the DACO samples to 3 encoder clock cycles of DAC preceding the DACO samples 011 The DAC1 lags DACO by 1 encoder clock cycle 100 There is no delay between the DAC1 and DACO signals 001 The DACO lags DACI by 1 encoder clock cycle 010 The DACO lags DACI by 2 encoder clock cycles 011 The DACO lags DACI by D encoder clock cycles 2 0 R W YC_Delay luma and chroma paths relative delays default 4 stages Relative delay between U V and Y selection These bits select the relative delay between the U and V samples and Y samples The delay range from 4 encoder clock cycles of Y lagging the U and V samples to 3 encoder clock cycles of Y preceding the U and V samples 000 The Y lags C by 4 encoder clock cycles 001 The Y lags C by 3 e
359. low priority mixed image area is called A2 The other area is called A3 And the A0 A1 A2 is called image area the A3 is called non image area The alpha color key module is disabled Only the ROP output image area is called AO AO is called image area The other area is called A3 A3 is called non image area Note the register setting is only valid in ARGB or AYUV mode 35 5 33 CSC0 1 Y G coefficient register Offset Register Name MP ICSCYGCOEF REG G Y component 0x180 R U component 0x184 B V DE 0x188 Read W Default Description rite Hex asp E 28 16 R W Ox4a7 CSC1_YGCOEF Oxle6f the Y G coefficient for CSC1 Oxlcbf the value equals to coefficient 2 12 00 R W Ox4a7 CSCO YGCOEF Oxle6f the Y G coefficient for CSCO Oxlcbf the value equals to coefficient 2 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 482 2012 04 09 Allwinner Technology CO Ltd A10 35 5 34 CSC0 1 Y G constant register Offset 0x18C Register Name MP ICSCYGCONS REG Bit Read W Default Description rite Hex 29 16 R W 0x877 CSC1_YGCONS the Y G constant for CSCI the value equals to coefficient 2 13 00 R W 0x877 CSCO_YGCONS the Y G constant for CSCO the value equals to coefficient 2 35 5 35 CSC0 1 U R coefficient register Offset Register Name MP ICSCURCOEF REG G Y component 0x190 R U component 0x194 B V DE 0x198
360. lue 35 5 11 Color space converter 0 control register Offset 0x74 Register Name MP_CSCOCTL_REG Read W Default Description rite Hex EE ML EE CSCO0 DATAMOD Data mode control Interleaved YUV422 mode In mode 0 and mode 1 only the channel 0 data path is valid for this module the channel 1 data flow will by pass the cscO module and direct to input formatter 1 Disable color space function ignore the control setting and the data flow will by pass the module A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 467 2012 04 09 Allwinner Technology CO Ltd A10 1 Enable color space converting function 35 5 12 Color space converter 1 control register Offset 0x78 Register Name MP_CSC1CTL_REG Read W Default Description rite Hex E E E EE CSC1_DATAMOD Data mode control Interleaved YUV422 mode In mode 0 and mode 1 only the channel 3 data path is valid for this module the channel 2 data flow will by pass the csc1 module and direct to input formatter 2 Disable color space function ignore the control setting and the data flow will by pass the module Enable color space converting function A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 468 2012 04 09 Allwinner Technology CO Ltd A10 35 5 13 Scaler control register Offset 0x80 Register Name MP SCACTL REG Bit Read
361. lwinner Technology CO Ltd A10 OxA OxB Security System Rx OxC OxD OxE OxF Ox10 Ox11 0x12 0x13 0x14 0x15 0x16 0x17 Memory Stick Controller MSC 0x18 0x19 Ox1A Ox1B SPIO RX Ox1C Ox1D SPI2 RX Ox1E Ox1F SPI3 RX 12 3 9 Dedicated DMA Source Start Address Register N 0 7 Offset Register Name DDMA_SRC_START_ADDR_REG 0x300 N 0x20 0x4 N 0 1 2 3 4 5 6 7 Bit Read Default Description Write Hex 31 0 R W x DDMA_SRC_START_ADDR Dedicated DMA Source Start Address 12 3 10 Dedicated DMA Destination Start Address Register Offset Register Name DDMA_DEST_START_ADDR_REG 0x300 N 0x20 0x8 N 0 1 2 3 4 5 6 7 Bit Read Default Description Write Hex 31 0 R W x DDMA_DEST_START_ADDR Dedicated DMA Destination Start Address A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 148 2012 04 09 Allwinner Technology CO Ltd A10 12 3 11 Dedicated DMA Byte Counter Register Offset Register Name DDMA_BC_REG 0x300 N 0x20 0xC N 0 1 2 3 4 5 6 7 Bit Read Default Description Write Hex 31 25 24 0 R W x DDMA_BC Dedicated DMA Byte Counter Note If ByteCounter 0 DMA will transfer no byte The maximum value is 0x 1000000 12 3 12 Dedicated DMA Parameter Register Offset Register Na
362. lwinner Technology CO Ltd A10 11 0 R W 0x0 TP_CDAT TP Common Data A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 279 2012 04 09 Ou Allwinner Technology CO Ltd A10 27 Keypad Interface 27 1 Overview The Key Pad Interface block in A10 facilitates communication with external keypad devices The ports can provide up to 8 rows and 8 columns The events of key press or key release are delivered to the CPU by an interrupt To prevent the switching noises keypad interface comprise of internal debouncing filter The Keypad Interface includes the following features M Interrupt for key press or key release M Internal debouncing filter to prevent the switching noises 27 2 Keypad Interface Register List Module Name Base Address KP 0x01C23000 Register Name Offset Description KP_CTL 0x00 Keypad Control Register KP_TIMING 0x04 Keypad Timing Parameter Register KP_INT_CFG 0x08 Keypad Interrupt Configure Register KP INT STA 0x0C Keypad Interrupt Status Register KP_INO 0x10 Keypad Row Input Data Register 0 KP INI 0x14 Keypad Row Input Data Register 1 27 3 Keypad Interface Register Description 27 3 1 Keypad Control Register Register Name KP_CTL Offset 0x00 Default Value 0x0000_0000 Bit Read Write Default Description 31 24 23 16 R W 0 ROW_INPUT_MSK A10 User Manual V1 20 Copyright
363. lwinner Technology CO Ltd A10 MSB LSB First Select 0 MSB First 1 LSB First SEXT Sign Extend only for 16 bits slot 0 Zeros or audio gain padding at LSB position 1 Sign extension at MSB position When writing the bit is 0 the unused bits are audio gain for 13 bit linear sample and zeros padding for 8 bit companding sample When writing the bit is 1 the unused bits are both sign extension 7 6 R W SI Slot Index 00 the Ist slot 01 the 2nd slot 10 the 3rd slot 11 the 4th slot SW Slot Width 0 8 clocks width 1 16 clocks width Notes For A law or u law PCM sample if this bit is set to 1 eight zero bits are following with PCM sample SSYNC Short Sync Select 0 Long Frame Sync 1 Short Frame Sync It should be set 1 for 8 clocks width slot 3 2 R W RX_PDM PCM Data Mode 00 16 bits Linear PCM 01 8 bits Linear PCM 10 8 bits u law 11 8 bits A law 1 0 R W TX_PDM PCM Data Mode 00 16 bits Linear PCM 01 8 bits Linear PCM 10 8 bits u law 11 8 bits A law A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 224 2012 04 09 Allwinner Technology CO Ltd A10 22 4 4 Digital Audio TX FIFO Register Offset 0x0C Register Name DA_TXFIFO Default Value 0x0000_0000 Bit Read Write Default Description TX_DATA TX Sample Transmitting left right channel sample
364. mal operation ignore RXFIFO status SS LEVEL When control SS signal manually SPI CTRL REG SS CTRL 1 set this bit to 1 or 0 to 17 R W 1 e ae control the level of SS signal 1 set SS to high 0 set SS to low SS CTRL SS Output Mode Select Usually controller sends SS signal automatically with data 16 RW 0 together When this bit is set to 1 software must manually write SPI CTRL REG SS LEVEL bit 17 to 1 or 0 to control the level of SS signal 1 manual output SS 0 automatic output SS DHB Discard Hash Burst In master mode it controls whether discarding unused SPI bursts 0 Receiving all SPI bursts in BC period 1 Discard unused SPI bursts only fetching the SPI bursts during dummy burst period The bursts number is specified 15 R W 0 by WTC DDB Dummy Burst Type 0 The bit value of dummy SPI burst is zero 14 R W 0 1 The bit value of dummy SPI burst is one SS SPI Chip Select 13 12 R W 0 Select one of four external SPI Master Slave Devices A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 166 2012 04 09 Ou Allwinner Technology CO Ltd A10 00 SPI_SSO will be asserted 01 SPI_SS1 will be asserted 10 SPI_SS2 will be asserted 11 SPI_SS3 will be asserted Notes This two bits can t be configured for SPI1 Engine 11 RPSM Rapids mode select Select rapids operation for high speed read 0 normal read mode 1 rapids read mode
365. me DDMA_PARA_REG 0x300 N 0x20 0x18 N 0 1 2 3 4 5 6 7 Bit Read Default Description Write Hex 31 24 R W 0x0 DEST_DATA_BLK_SIZE Destination Data Block Size n 23 16 R W 0x0 DEST_WAIT_CYC Destination Wait Clock Cycles n 15 8 R W 0x0 SRC_DATA_BLK_ SIZE Source Data Block Size n 7 0 R W 0x0 SRC WAIT CYC Source Wait Clock Cycles n Note If the counterzN the value is N 1 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 149 2012 04 09 Ou Allwinner Technology CO Ltd A10 13 SDRAM Controller 13 1 Overview The SDRAM Controller DRAMC provides a simple flexible burst optimized interface to all in dusty standard double data rate II DDR2 ordinary SDRAM andouble data rate III DDR3 ordinary SDRAM It supports up to a 16G bits memory address space The DRAMC automatically handles memory management initialization and refresh operations It gives the host CPU a simple command interface hiding details of the required address page and burst handling procedures All memory parameters are runtime configurable including timing memory setting SDRAM type and Extended Mode Register settings The DRAMC includes the following features Support DDR2 SDRAM and DDR3 SDRAM Support Different Memory Device s Power Voltage of 1 5V and 1 8V Support DDR2 3 SDRAM of clock frequency up to DDR800 Support Memory Capacity up to 16G bits 2G Bytes
366. me IIS CLK REG Bit Read Default Description Write Hex 31 R W 0x0 SCLK_GATING Gating Special Clock Max Clock 100MHz 0 Clock is OFF 1 Clock is ON This special clock Clock Source Divider N 30 25 24 23 18 17 16 R W 0x0 CLK_DIV_RATIO_N Clock pre divide ratio n The select clock source is pre divided by 2 n The divider is 1 2 4 8 The clock source is PLL2 8x 15 4 3 0 6 4 33 AC97 Clock Default 0x00030000 Offset 0xBC Register Name AC97 CLK REG Bit Read Default Description Write Hex 31 R W 0x0 SCLK_GATING Gating Special Clock Max Clock 100MHz 0 Clock is OFF 1 Clock is ON This special clock Clock Source Divider N 30 25 24 23 18 17 16 R W 0x3 CLK DIV RATIO N Clock pre divide ratio n The select clock source is pre divided by 2 n The divider is 1 2 4 8 The clock source is PLL2 8x A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 59 2012 04 09 15 4 Ou Allwinner Technology CO Ltd A10 3 0 6 4 34 Keypad Clock Default 0x0000001F Offset 0xC4 Register Name KEYPAD_CLK_REG Bit Read Default Description Write Hex 31 R W 0x0 SCLK GATING Gating Special Clock Max Clock 100MHz 0 Clock is OFF 1 Clock is ON This special clock Clock Source Divider N Divider
367. me in dclk Toevd 2 OEVD Tdclk 33 4 31 TCONDO ttl panel timing register3 Offset 0x07C Register Name TCONO TTL3 REG Bit Read Default Description Write Hex 31 26 R W 0 STHH STH high plus time in dclk Tsthh STHH 1 Tdclk Note STH has a period of one line 25 16 R W 0 STHD HSYNC STH delay time in dclk Tsthd STHD Tdclk 15 10 R W 0 OEHH OEH high plus time in delk Tldh OEHH 1 Tdclk 9 0 R W 0 OEHD HSYNC OEH delay time in dclk Tldd OEHD Tdclk 33 4 22 TCONDO ttl panel timing register3 Offset 0x080 Register Name TCONO TTL4 REG Bit Read Default Description Write Hex 31 24 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 409 2012 04 09 Ou Allwinner Technology CO Ltd A10 23 R W 0 Output_Data_Rate 0 single data rate SDR LCD read data at the rising edge of clock 1 Double data rate DDR The first data of every line must be ready at rising edge of CKH CKH1 CKH2 Note When DATA RATE 1 HT and HBP had better be even number CKH CKHI and CKH1 CKH2 delay time is always 1 3 Tdclk 22 R W Rev_Sel REV toggle mode 0 1H time toggle mode with frame inversion 1 Frame toggle mode Note no matter in which mode make sure REV has different polarity at the beginning of every frame take VSYNC as reference 21 R W TTL_Data_Inv_En 0
368. mpleted 15 14 R W TU TXFIFO under run This bit is set when if the TXFIFO is underrun Writing 1 to this bit clears it 0 TXFIFO is not underrun 1 TXFIFO is underrun 13 R W TO TXFIFO Overflow This bit is set when if the TXFIFO is overflow Writing 1 to this bit clears it A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 170 2012 04 09 Ou Allwinner Technology CO Ltd A10 0 TXFIFO is not overflow 1 TXFIFO is overflowed TE34 TXFIFO 3 4 empty This bit is set if the TXFIFO is more than 3 4 empty 12 R W 1 Writing 1 to this bit clears it TE14 TXFIFO 1 4 empty This bit is set if the TXFIFO is more than 1 4 empty 11 R W 1 Writing 1 to this bit clears it TF TXFIFO Full This bit is set when if the TXFIFO is full Writing 1 to this bit clears it 0 TXFIFO is not Full 10 R W 0 1 TXFIFO is Full THE TXFIFO Half empty This bit is set if the TXFIFO is more than half empty Writing 1 to this bit clears it 0 TXFIFO holds more than half words 9 R W 1 1 TXFIFO holds half or fewer words TE TXFIFO Empty This bit is set if the TXFIFO is empty Writing 1 to this bit clears it 0 TXFIFO contains one or more words R W 1 1 TXFIFO is empty RU RXFIFO Underrun When set this bit indicates that RXFIFO has underrun 6 R W 0 Writing 1 to this bit clears it RO RXFIFO Overflow
369. n NO and master has tried to write UART status to the Line Control Register while the UART is busy USR 0 is set to one register 18 4 7 UART FIFO Control Register Offset 0x08 Register Name UART FCR Default Value 0x0000 0000 Bit Read Write Default Description 31 8 7 6 W RT RCVR Trigger This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt is generated In auto flow control mode it is used to determine when the rts_n signal is de asserted It also determines when the dma_rx_req_n signal is asserted in certain modes of operation 00 1 character in the FIFO 01 FIFO full 10 FIFO full 11 FIFO 2 less than full 5 4 W TFT TX Empty Trigger Writes have no effect when THRE MODE USER Disabled This is used to select the empty threshold level at which the THRE Interrupts are generated when the mode is active It also determines when the dma tx req n signal is asserted when in certain modes of operation 00 FIFO empty 01 2 characters in the FIFO 10 FIFO L full 11 FIFO Le full DMAM DMA Mode 0 Mode 0 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 185 2012 04 09 Ou Allwinner Technology CO Ltd A10 1 Mode I XFIFOR XMIT FIFO Reset This resets the control portion of the transmit FIFO and treats the
370. n line internally In this mode all the interrupts are fully functional Also in loopback mode the modem control inputs dsr_n cts_n ri_n dcd_n are disconnected and the modem control outputs dtr n rts n out n out2_n are looped back to the inputs internally If operating in infrared mode SIR MODE Enabled AND active MCR 6 set to one data on the sir out n line 4 R W 0 is held low while serial data output is inverted and A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 188 2012 04 09 Ou Allwinner Technology CO Ltd A10 looped back to the sir_in line RTS Request to Send This is used to directly control the Request to Send rts_n output The Request To Send rts_n output is used to inform the modem or data set that the UART is ready to exchange data When Auto RTS Flow Control is not enabled MCR 5 set to zero the rts n signal is set low by programming MCR 1 RTS to a high In Auto Flow Control AFCE MODE Enabled and active MCR 5 set to one and FIFOs enable FCR 0 set to one the rts n output is controlled in the same way but is also gated with the receiver FIFO threshold trigger rts n is inactive high when above the threshold The rts n signal is de asserted when MCR 1 is set low 0 rts n de asserted logic 1 1 rts n asserted logic 0 Note that in Loopback mode MCR 4 set to one the rts n output is held inac
371. n register OX4AC 0X4B0 OX4B4 ISP FE HISTO SIZE REG OX4B8 ISP Histogram region 0 window size register ISP FE HISTO POS REG OX4BC ISP Histogram region 0 window start register ISP FE HIST1 SIZE REG 0X4CO ISP Histogram region 1 window size register ISP FE HISTI POS REG OX4C4 ISP Histogram region 1 window start register ISP FE HIST2 SIZE REG 0X4C8 ISP Histogram region 2 window size register ISP FE HIST2 POS REG OX4CC ISP Histogram region 2 window start register ISP FE HIST3 SIZE REG 0X4D0 ISP Histogram region 3 window size register ISP FE HIST3 POS REG 0X4D4 ISP Histogram region 3 window start register ISP FE 3A ADDR REG 0X4D8 ISP 3A Statistics output address register OX4DC OX4E0 ISP FE LUT DC CFG REG OX4E4 ISP LUT Defect Correction configuration register ISP_FE_LUT_DC_ADDR_REG 0X4E8 ISP LUT Defect Correction address A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 2012 04 09 342 Ou Allwinner Technology CO Ltd A10 register ISP_FE_Y_LEN_REG OXAEC ISP FE Y Raw output Address length register ISP FE Y ADDR REG OXAFO0 ISP FE Y Raw output Address register ISP FE INT EN REG OX4F4 ISP interrupt enable register ISP_FE_INT_STA_REG OX4F8 ISP interrupt status register OX4FC ISP FE C LEN REG 0X500 ISP FE CbCr output Address length register ISP FE C ADDR REG 0X504 ISP FE CbCr out
372. nable L1 data cache invalidation at reset For L1 data cache the cycles are up to 512 cpu clock cycles 0 enable 1 disable 0 R W 0x0 L2 DATA CACHE INVA EN Enable L2 data cache invalidation at reset For L1 data cache the cycles are up to 1024 cpu clock cycles A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 107 2012 04 09 Ou v Allwinner Technology CO Ltd A10 0 enable 1 disable Note the bit 1 0 can be set to 0 by software A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 108 2012 04 09 Ou Allwinner Technology CO Ltd A10 11 Interrupt Controller 11 1 Overview The Interrupt Controller in A10 can handle individually maskable interrupt sources up to 95 With the 4 level programmable interrupt priority developer can define the priority for each interrupt source permitting higher priority interrupts to be serviced even if a lower priority interrupt is being treated The Interrupt Controller is featured as following Support 95 vectored nIRQ interrupt 4 programmable interrupt priority levels Fixed interrupt priority of the same level Support Hardware interrupt priority level masking Programmable interrupt priority level masking Generates IRQ and FIQ Generates Software interrupt One external NMI interrupt source 11 2 Interrupt Source The interrupt source 0 is always located at
373. ncoder clock cycles 010 The Y lags C by 2 encoder clock cycles 011 The Y lags C by 1 encoder clock cycle 100 There is no delay between the Y and C signals 101 The C lags Y by 1 encoder clock cycle 110 The C lags Y by 2 encoder clock cycles 111 The C lags Y by 3 encoder clock cycles 34 4 4 TV Encoder chroma frequency Register Offset 0x010 Register Name TVE 010 REG Bit Read Default Description Write Hex Chroma Freq Specify the ratio between the color burst frequency 32 bit unsigned fraction Default value is h21f07c1f which is compatible with NTSC 21f07c specs 31 0 R W 1f 3 5795455MHz X 21F07C1F NTSC M NTSC J 4 43361875 MHz X 2A098ACB PAL B D G H I N 3 582056 MHz X 21F69446 PAL N Argentina 3 579611 MHz X 21E6EFE3 PAL M 34 4 5 TV Encoder Front Back Porch Register Offset 0x014 Register Name TVE 014 REG Bit Read Default Description A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 431 2012 04 09 Ou Allwinner Technology CO Ltd A10 Write Hex 31 25 24 16 R W 76 Back Porch Specify the width of the back porch in encoder clock cycles Min value is burst width breeze way 17 8 bit unsigned integer Default value is 118 720p mode is 260 1080i p mode is 192 15 12 11 0 R W 20 Front Porch
374. nd 16 4 9 TWI Line Control Register Offset 0x20 Register Name TWI_LCR Default Value 0x0000_003a Bit Read Write Default Description 31 6 SCL_STATE Current state of TWI_SCL 0 low 1 high SDA STATE Current state of TWI SDA 0 low 1 high R W SCL CTL TWI SCL line state control bit When line control mode is enabled bit 2 set value of this bit decide the output level of TWI_SCL 0 output low level output high level A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 160 2012 04 09 Ou Allwinner Technology CO Ltd A10 SCL_CTL_EN TWI_SCL line state control enable When this bit is set the state of TWI_SCL is control by the value of bit 3 0 disable TWI_SCL line control mode 1 enable TWI_SCL line control mode SDA_CTL TWI_SDA line state control bit When line control mode is enabled bit 0 set value of this bit decide the output level of TWI SDA 0 output low level output high level SDA CTL EN TWI SDA line state control enable When this bit is set the state of TWI SDA is control by the value of bit 1 0 disable TWI SDA line control mode enable TWI SDA line control mode 16 4 10 TWI DVFS Control Register Register Name TWI DVFSCR Offset 0x24 Default Value 0x0000 0000 Bit Read Write De
375. nd ALE control signal lines Three kinds of mode are supported for serial read access The conventional serial access is mode 0 and mode 1 is for EDO type and mode 2 for extension EDO type NFC can monitor the status of R B signal line Block management and wear leveling management are implemented in software The NAND Flash Controller NFC includes the following features Supports all SLC MLC TLC flash and EF NAND memory available in the market Software configure seed for randomize engine Software configure method for adaptability to a variety of system and memory types Supports 8 bit Data Bus Width Supports 1024 2048 4096 8192 16384 bytes size per page Supports 1 8 3 3 V voltage supply Flash Up to 8 flash chips which are controlled by NFC_CEx Supports Conventional and EDO serial access method for serial reading Flash On the fly BCH error correction code which correcting up to 64 bits per 512 or 1024 bytes Corrected Error bits number information report ECC automatic disable function for all Oxff data NFC status information is reported by its registers and interrupt is supported One Command FIFO External DMA is supported for transferring data Two 256x32 bit RAM for Pipeline Procession Support SDR DDR and Toggle NAND Support self debug for NFC debug A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 151 2012 04 09 Ou Allwinner Technology CO Ltd A10 15 SD3 0 Controller 1
376. nding Set 1 to the bit will clear it 0 No effect 1 Pending 12 R W 0x0 NDMA6_HF_IRQ_PEND Normal DMA 6 Half Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending 11 R W 0x0 NDMA5 END IRQ PEND Normal DMA 5 End Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending 10 R W 0x0 NDMAS HF IRQ PEND Normal DMA 5 Half Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending R W 0x0 NDMA4_END_IRQ_PEND Normal DMA 4 End Transfer Interrupt Pending Set 1 to the bit will clear it 0 No effect 1 Pending R W 0x0 NDMA4 HF IRQ PEND A10 User Manual V 1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 139 2012 04 09 Ou Allwinner Technology CO Ltd A10 Normal DMA 4 Half Transfer Interrupt Pending clear it 0 No effect 1 Pending Set I to the bit will R W 0x0 NDMA3_END_IRQ_PEND Normal DMA 3 End Transfer Interrupt Pending clear it 0 No effect 1 Pending Set 1 to the bit will R W 0x0 NDMA3_HF_IRQ PEND Normal DMA 3 Half Transfer Interrupt Pending clear it 0 No effect 1 Pending Set I to the bit will R W 0x0 NDMA2 END IRQ PEND Normal DMA 2 End Transfer Interrupt Pending clear it 0 No effect 1 Pending Set I to the bit will R W 0x0 NDMA2_HF_IRQ
377. nent 0x1E4 B V aaa 0x1E8 Read W Default Description rite Hex Gnr pg 12 00 R W CSC2 VBCOEF the V B coefficient the value equals to coefficient 2 35 5 44 CSC2 V B constant register Offset Ox1EC Register Name MP OCSCVBCONS REG Read W Default Description rite Hex mu p p p S SSS 13 00 R W CSC2 VBCONS the V B constant the value equals to coefficient 2 35 5 45 Scaling horizontal filtering coefficient RAM block Offset 0x200 0x27C PE Default Description ET Horizontal tap3 coefficient i 24 The value equals to coefficient 2 15 08 Horizontal tap coefficient The value equals to coefficient 2 23 16 Horizontal tap2 coefficient The value equals to coefficient 2 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 486 2012 04 09 Allwinner Technology CO Ltd A10 Horizontal tapO coefficient The value equals to coefficient 2 35 5 46 Scaling vertical filtering coefficient RAM block Offset 0x280 0x2FC Bit Read W Default Description rite Hex 31 24 R W Vertical tap3 coefficient The value equals to coefficient 2 23 116 R W Vertical tap2 coefficient The value equals to coefficient 2 15 08 R W Vertical tap1 coefficient The value equals to coefficient 2 07 00 R W Vertical tapO coefficient The value equals to coefficient 2 35 5 17 Palette table Offset 0x400 0x7FF Bit Read W Default Descripti
378. ner Technology CO Ltd A10 RA Receiver Address The value of this bit can be changed when the RXEN 7 0 R W 0 bit is cleared 19 4 7 IR Receiver Counter Register Register Name IR RXCNT Offset 0x18 Default Value 0x0000 0000 Bit Read Write Default Description 31 12 RPL Receiver Packet Length This field contains the length of the address control and data The length are N 1 bytes 0 no bytes received N N bytes received It can automatically clear by Irda Controller when new 11 0 R 0 packet is found 19 4 8 IR Transmitter FIFO Register Register Name IR_TXFIFO Offset 0x1C Default Value 0x0000_0000 Bit Read Write Default Description 31 8 TX_DATA 7 0 W 0 Transmitter Byte FIFO 19 4 9 IR Receiver FIFO Register Register Name IR_RXFIFO Offset 0x20 Default Value 0x0000_0000 Bit Read Write Default Description 31 8 RX_DATA 7 0 R 0 Receiver Byte FIFO A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 206 2012 04 09 Allwinner Technology CO Ltd A10 19 4 10 IR Transmitter Interrupt Control Register Offset 0x24 Register Name IR TXINT Default Value 0x0000 0000 Bit Read Write Default Description 31 12 11 8 TEL TX FIFO Empty Level for interrupt and DMA request TRIGGER_LEVEL TEL 1 7 6
379. ng Controller 33 1 Overview TCON in A10 is of high flexibility in timing configuration as well as LCD module compatibility 33 2 Block Diagram MAX 700MHz gt CONTROL LOGIC 2 RGB 2YU DATA DMA OUTO Async FIFO1 Se P v F w FORMATTER i 444 HV TIMING OUT2 par 3 CPU TIMING Channel To FIFO Flag BASIC p amp TIMING ES DE M gt crock 9 gt GENERATOR E gt EINING U GEN x LVDS TIMING OUT CEU Gamma i TV TIMING TV L A o GENERATOR Channel LCD Timing Controller Block Diagram Figure33 1 Block Diagram 33 3 LCD TV Timing Controller Register List Module Name Base Address TCON 0x01C0CO000 Register Name Offset Description TCON GCTL REG 0x0000 TCON global control register TCON GINTO REG 0x0004 TCON global interrupt register0 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 396 2012 04 09 Ou Allwinner Technology CO Ltd A10 TCON_GINT1_REG 0x0008 TCON global interrupt register1 TCON_FRM_CTL_REG 0x0010 TCON FRM control register TCON FRM PSEED R RE
380. ng S P os Mis ns I 17301 p BIT CLK high pulse width note 2 Tak sa 36 407 45 ns EE GT RE TAN ep me EE Sce ee 712 71 7 38 SYNC ow pulse width Tow 95 us Note 1 47 5 75 pF external load as per Table 54 Note 2 Worst case duty cycle restricted to 45 55 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 242 2012 04 09 N Allwinner Technology CO Ltd A10 23 5 5 Data transmission timing diagram TAG Phase DATA Phase 16 bits 12 Slots x 20 Bits 240 Bits he 12 288MHz BITCLK CLKS SYNC FSX ba 1 cycle delay from SYNC SDATAOUT DX vali SN ee det 0 Xo Xo X19 0 X19 0 Y 19 0 19 0 SDATAIN DR Ae TAZAJIAGA S AS AS AAA AS ALTA KKK KIKKI X Slot 1 Slot 2 Slot 3 Slot 12 End of previous Transmission of TAG Transmission of Audio Frame Phase data begins DATA Phase data here begins here Fig24 8 Data transmission timing diagram tco BIT_CLK Vin SDATA_OUT SDATA_IN SYNC Fig 24 9 Data Output and Input Timing Diagram Table23 5 AC link Output Valid Delay Timing Parameters Parameter Output Valid Delay from rising edge of BIT CLK Table23 7 AC link Combined Rise or Fall plus Flight Timing Parameters A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 243 2012 04 09 GZ Technology CO Ltd A10 Parameter BIT_CLK combined r
381. nner Technology All Rights Reserved 115 2012 04 09 Allwinner Technology CO Ltd A10 11 4 12 Interrupt Select Register 1 Default 0x00000000 Offset 0x34 Register Name INTC IRQ TYPE SEL Bit Read Default Description Write Hex 31 0 R W 0x0 INT IRQ TYPE SELI Interrupt Source 63 32 irq type select 0 IRQ 1 FIQ 11 4 13 Interrupt Select Register 2 Default 0x00000000 Offset 0x38 Register Name INTC IRQ TYPE SEL2 Bit Read Default Description Write Hex 31 0 R W 0x0 INT IRQ TYPE SEL2 Interrupt Source 95 64 irq type select 0 IRQ 1 FIQ 11 4 14 Interrupt Enable Register 0 Default 0x00000000 Offset 0x40 Register Name INTC EN REGO Bit Read Default Description Write Hex 31 0 R W 0x0 INT_ENO Interrupt Source 31 0 Enable Bits 0 Corresponding interrupt is disabled 1 Corresponding interrupt is enabled 11 4 15 Interrupt Enable Register 1 Default 0x00000000 Offset 0x44 Register Name INTC_EN_REG1 Bit Read Default Description Write Hex 31 0 R W 0x0 Interrupt Source 63 32 Enable Bits 0 Corresponding interrupt is disabled 1 Corresponding interrupt is enabled A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 116 2012 04 09 Allwinner Technology CO Ltd A10
382. nology All Rights Reserved 186 2012 04 09 Ou Allwinner Technology CO Ltd A10 serial output is forced to the spacing logic 0 state When not in Loopback Mode as determined by MCRJ4 the sout line is forced low until the Break bit is cleared If SIR MODE Enabled and active MCR 6 set to one the sir out n line is continuously pulsed When in Loopback Mode the break condition is internally looped back to the receiver and the sir out n line is forced low 5 EPS Even Parity Select It is writeable only when UART is not busy USR 0 is zero and always writable readable This is used to select between even and odd parity when parity is enabled PEN set to one 0 Odd Parity 4 R W 1 Even Parity PEN Parity Enable It is writeable only when UART is not busy USR 0 is zero and always readable This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively 0 parity disabled 3 R W 1 parity enabled STOP Number of stop bits It is writeable only when UART is not busy USR 0 is zero and always readable This is used to select the number of stop bits per character that the peripheral transmits and receives If set to zero one stop bit is transmitted in the serial data If set to one and the data bits are set to 5 LCR 1 0 set to zero one and a half stop bits is transmitted Otherwise two stop bits are transmitted Note t
383. nology All Rights Reserved 307 2012 04 09 Ou Allwinner Technology CO Ltd A10 Bit Read Write Default Description 31 16 15 PD27_SELECT 000 Input 001 Output 010 LCDO_ VSYNC 011 SMC_SDA 100 Reserved 101 Reserved 14 12 R W 0 110 Reserved 111 Reserved 11 Reserved PD26_SELECT 000 Input 001 Output 010 LCDO_ HSYNC 011 SMC_SCK 100 Reserved 101 Reserved 10 8 R W 0 110 Reserved 111 Reserved 7 PD25_SELECT 000 Input 001 Output 010 LCDO_ DE 011 SMC_RST 100 Reserved 101 Reserved 6 4 R W 0 110 Reserved 111 Reserved 3 PD24_SELECT 000 Input 001 Output 010 LCDO_CLK 011 SMC_VCCEN 100 Reserved 101 Reserved 2 0 R W 0 110 Reserved 111 Reserved 30 3 32 PD Data Register Register Name PD_DAT Offset 0x7C Default Value 0x0000_0000 Bit Read Write Default Description 31 28 PD_DAT If the port is configured as input the corresponding bit is the pin state If the port is configured as output the pin state is the same as the corresponding bit The read bit value is the value setup by software If the port is configured as functional pin the undefined value will 27 0 R W 0 be read A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 308 2012 04 09 Ou Allwinner Technology CO Ltd 30 3 33 PD Multi Driving Register 0 Register Name
384. nology All Rights Reserved 365 2012 04 09 Ou Allwinner Technology CO Ltd A10 fT LUT Defect correction Enable 12 R W HIST3_EN EE Histogram region 3 Enable 11 R W HIST2 EN pope Histogram region 2 Enable 10 R W HISTI EN UL Histogram region 1 Enable R W HISTO EN pom d Histogram region 0 Enable R W HIST EN LEN RN 07 R W AWBE_EN WENN CRI R W AF EN E ee 05 R W H3A_EN NENNEN CRI 04 R W LUMA_DC_SUB_EN WE 03 R W GAIN_OFFSET_EN m T mmn ooo 02 R W LSC EN Z UI meme 01 R W OBC_HOR_LMT_EN ES EI R W OBC_EN Optical Black Clamp Enable 0 Disable 1 Enable P S This register has double buffer it should be reloaded by hardware at every vsync 31 6 58 ISP Mode register Offset Address 0X404 Register Name ISP_FE_MODE_REG Read Default Description Write Hex sf 1 09 08 BAYER SEQ Bayer Raw Pattern Sequence 00 RG GB 01 GR BG 10 BG GR A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 366 2012 04 09 Allwinner Technology CO Ltd A10 LT mm gt R W INPUT FMT ISP FE input format 0 Bayer Raw 1 YUV422 31 6 59 ISP OBC Image Black size register Offset Address 0X410 Register Name ISP_FE_OB_SIZE_REG Read Default Description Write Hex BEER RE 28 16 R W OB_HEIGHT The height of sensor including optical black area Ranges from 0 to 4096 12 00 R W 500 OB_WIDTH The width of sensor including optical black area Ranges from 0 to 40
385. nterrupt IRQ Pending 0 Status INTC IRQ PEND REGI 0x0014 Interrupt IRQ Pending 1 Status INTC IRQ PEND REGO 0x0018 Interrupt IRQ Pending 2 Status INTC FIQ PEND REGO 0x0020 Interrupt FIQ Pending 0 Status INTC FIQ PEND REGI1 0x0024 Interrupt FIQ Pending 1 Status INTC FIQ PEND REG2 0x0028 Interrupt FIQ Pending 2 Status INTC IRQ TYPE SELO 0x0030 Interrupt Select 0 INTC IRQ TYPE SEL1 0x0034 Interrupt Select 1 INTC IRQ TYPE SEL2 0x0038 Interrupt Select 2 INTC EN REGO 0x0040 Interrupt Enable 0 INTC EN REGI 0x0044 Interrupt Enable 1 INTC EN REG2 0x0048 Interrupt Enable 2 INTC MASK REGO 0x0050 Interrupt Mask 0 INTC MASK REGI 0x0054 Interrupt Mask 1 INTC MASK REG2 0x0058 Interrupt Mask 2 INTC RESP REGO 0x0060 Interrupt Response 0 INTC RESP REGI 0x0064 Interrupt Response 1 INTC RESP REG2 0x0068 Interrupt Response 2 INTC FF REGO 0x0070 Interrupt Fast Forcing 0 INTC_FF_REG1 0x0074 Interrupt Fast Forcing 1 INTC_FF_REG2 0x0078 Interrupt Fast Forcing 2 INTC PRIO REGO 0x0080 Interrupt Source Priority 0 INTC PRIO REG 0x0084 Interrupt Source Priority 1 INTC_PRIO_REG2 0x0088 Interrupt Source Priority 2 INTC_PRIO_REG3 0x008C Interrupt Source Priority 3 INTC PRIO REG4 0x0090 Interrupt Source Priority 4 11 4 Interrupt Programmable Register 11 4 1 Interrupt Vector Register Default 0x00000000 Offset 0x00 Register Name INTC VECTOR REG Bit Read Default Description Write Hex 31 2 R 0x0 VECTOR ADDR This reg
386. ntrol Register AC FAT 0x04 AC97 Format Register AC CMD 0x08 AC97 Command Register AC CS OxOC AC97 Codec Status Register AC TX FIFO 0x10 AC97 TX FIFO Register AC RX FIFO 0x14 AC97 RX FIFO Register AC_FCTL 0x18 AC97 FIFO Control Register AC_FSTA Ox1C AC97 FIFO Status Register AC_INT 0x20 AC97 Interrupt Control Register AC_ISTA 0x24 AC97 Interrupt Status Register AC TX CNT 0x28 AC97 TX Counter register AC RX CNT O0x2C AC97 RX Counter register 23 7 AC97 Interface Register Description 23 7 1 AC97 Control Register Offset 0x00 Register Name AC CTL Default Value 0x0000 0000 Bit Read Write Default Description 31 19 18 R 0 CS_RF CODEC Status Register FLAG 0 Empty 1 Full 17 R 0 CMD_RF CMD Register FLAG 0 Empty 1 Full 16 R 0 RX_STATUS A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 245 2012 04 09 Ou Allwinner Technology CO Ltd A10 RX Transfer Status 0 PCM IN 1 MIC IN 15 10 RX_MODE RX MODE 0 PCM IN 1 MIC IN Note this bit indicate which mode will be selected when PCM IN and MIC IN slots are available simultaneity ASS Audio sample select with TX FIFO under run 0 sending 0 invalid frame 1 sending the last audio valid frame TXEN 0 Disable 1 Enable RXEN 0 Disable 1 Enable AC link EN 0 Disable 1 Enable SYNC signal transfer to Codec GEN Globe Enable
387. o available data in RX FIFO 8 R 0 1 More than one sample in RX FIFO gt 1 word 7 RXA_CNT 6 0 R 0 RX FIFO Available Sample Word Counter 22 4 8 Digital Audio DMA amp Interrupt Control Register Offset 0x1C Register Name DA_INT Default Value 0x0000_0000 Bit Read Write Default Description 31 8 TX_DRQ TX FIFO Empty DRQ Enable 0 Disable 1 Enable TXUI EN TX FIFO Under run Interrupt Enable 0 Disable 1 Enable TXOL EN TX FIFO Overrun Interrupt Enable 0 Disable 1 Enable When set to 1 an interrupt happens when writing new audio data if TX FIFO is full TXEI EN TX FIFO Empty Interrupt Enable 0 Disable 1 Enable 3 R W RX DRQ RX FIFO Data Available DRQ Enable 0 Disable A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 227 2012 04 09 Ou Allwinner Technology CO Ltd A10 1 Enable When set to 1 RXFIFO DMA Request line is asserted if Data is available in RX FIFO RXUI EN RX FIFO Under run Interrupt Enable 0 Disable 1 Enable RXOI EN RX FIFO Overrun Interrupt Enable 0 Disable 1 Enable 0 R W RXAI EN RX FIFO Data Available Interrupt Enable 0 Disable 1 Enable 22 4 9 Digital Audio Interrupt Status Register Offset 0x20 Register Name DA ISTA Default Value 0x0000 0010 Bit Read Write Default De
388. o image data stream 0 Disable video capture If video capture is in progress the CSI stops capturing image data at the end of the current frame and all of the current frame data is wrote to output FIFO 1 Enable video capture The CSI starts capturing image data at the start of the next frame SCAP ON Still capture control Capture a single still image frame A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 345 2012 04 09 Ou Allwinner Technology CO Ltd A10 0 Disable still capture 1 Enable still capture The CSI module starts capturing image data at the start of the next frame The CSI module captures only one frame of image data This bit is self clearing and always reads as a 0 31 6 4 CSI horizontal scale register Offset Address 0X000C Register Name CSIO SCALE REG Read Default Description Write Hex KJE 27 24 R W VER MASK Vertical line mask Every 4 line is a mask group Bit 24 mask the first line bit 25 mask the second line and so on Mask bit 0 means discarding this line data 15 00 R W FFFF HOR_MASK Horizontal datastream mask Every 16 byte is a mask group Bit 0 mask the firest byte bit 1 mask the second byte and so on Mask bit 0 means discarding this byte from the datastream 31 6 5 CSI Channel_0 FIFO 0 output buffer A address register Offset Address 0X0010 Register Name CSI0 C0 FO BUFA REG Bit Read Default
389. ock Default 0x00000000 Offset 0xA0 Register Name SPIO CLK REG Bit Read Default Description Write Hex 31 R W 0x0 SCLK_GATING Gating Special Clock Max Clock 200MHz 0 Clock is OFF 1 Clock is ON This special clock Clock Source Divider N Divider M 30 26 25 24 R W 0x0 CLK_SRC_SEL A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 55 2012 04 09 Ou Allwinner Technology CO Ltd A10 Clock Source Select 00 OSC24M 01 PLL6 10 PLL5 11 23 18 17 16 R W 0x0 CLK_DIV_RATIO_N Clock pre divide ratio n The select clock source is pre divided by 2 n The divider is 1 2 4 8 15 4 3 0 R W 0x0 CLK_DIV_RATIO_M Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 16 6 4 28 SPI1 Clock Default 0x00000000 Offset 0xA4 Register Name SPI1_CLK_REG Bit Read Default Description Write Hex 31 R W 0x0 SCLK_GATING Gating Special Clock Max Clock 200MHz 0 Clock is OFF 1 Clock is ON This special clock Clock Source Divider N Divider M 30 26 25 24 R W 0x0 CLK_SRC_SEL Clock Source Select 00 OSC24M 01 PLL6 10 PLLS 11 23 18 17 16 R W 0x0 CLK_DIV_RATIO_N Clock pre divide ratio n The select clock source is pre divided by 2 n The divider is 1 2 4 8 15 4 3 0 R W 0x0 CLK_D
390. odec D A 10100 10101 SRAM range 10110 SDRAM 10111 11000 SPIO TX 11001 SPIL TX 11010 SPI2 TX 11011 SPI3 TX others reserved 15 R W 0x0 BC_MODE_SEL BC mode select 0 normal mode the value read back is equal to the value that is written 1 remain mode the value read back is equal to the remain A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 142 2012 04 09 Ou Allwinner Technology CO Ltd A10 counter to be transfered 14 11 10 9 R W 0x0 NDMA_SRC_DATA_WIDTH Normal DMA Source Data Width 00 8 bit 01 16 bit 10 32 bit 11 8 7 R W 0x0 DMA_SRC_BST_LEN DMA Source Burst Length 00 1 01 4 10 8 11 R W 0x0 DMA_SRC_SEC DMA Source Security 0 secure 1 non secure R W 0x0 NDMA_SRC_ADDR_TYPE Normal DMA Source Address Type 0 Increment 1 No Change 4 0 R W 0x0 NDMA_SRC_DRQ_TYPE Normal DMA Source DRQ Type 00000 IRO RX 00001 IR1 RX 00010 00011 IIS RX 00100 00101 AC97 RX 00110 00111 01000 UARTO RX 01001 UARTI RX 01010 UART2 RX 01011 UART3 RX 01100 UART4 RX 01101 UART5 RX 01110 UART6 RX 01111 UART7 RX 10000 HDMI DDC RX 10001 10010 10011 Audio Codec A D A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reser
391. oder Cb Cr Gain Reeister iere rte aree tee ER Ce tertie 437 34 4 18 TV Encoder Sync and VBI Level Register 438 34 4 19 TV Encoder White Level Register AAA 438 34 4 20 TV Encoder Video Active Line Register essent nennen 438 34 4 21 TV Encoder Video Chroma BW and CompGain Register esee 439 34 4 22 IV Encoder R PISIeE ctor anti e erem NG TSG 439 34 4 23 TV Encoder Re sync parameters Register essere 440 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 21 2012 04 09 Ou Allwinner Technology CO Ltd A10 34 4 24 TV Encoder Slave Parameter Register aei 440 34 4 25 TV Encoder Configuration Register eese eene teens 441 34 4 26 TV Encoder Configuration Register essere enne 441 34 4 27 TV Encoder MacroVision Control Register A 442 34 4 28 TV Encoder MacroVision NO N3 Register 442 34 4 29 TV Encoder MacroVision N4 N7 Register 443 34 4 30 TV Encoder MacroVision N8 N10 Register AAA 443 34 4 31 TV Encoder MacroVision N11 N12 Register AAA 443 34 4 32 TV Encoder MacroVision N13 N16 Register AAA 443 34 4 33 TV Encoder MacroVision N17 N20 Register AA 444 35 Mixer Processor MP E 445 DL ee ER 445 35 3 Block Draam iie ene en deti eere esteso dee I edes redet ee tnn 446 35 9 MP Description EE 446 3531 Data EE 446 35 3 2 Rotation and mirroring Control 446 35 3 3 Meinory EE 447 35 994 Colo
392. omponent ignore y direction The input UV component odd line will be thrown away A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 2012 04 09 450 e Allwinner Technology CO Ltd A10 Input Line 2n Po Pl P2 Pn 6 Pn 5 Pn 4 Pn 3 Pn 2 Pn 1 Pn j p vv f Pn 7 Pn 6 Pn 3 Pn2 jo RTT H PO P1 P2 P3 P4 P5 P6 P7 m n Output Line n j Pn 5 Pn 4 Pn 1 Pn n B 1 The UV component output formatter rule of YUV444 to YUV420 35 3 6 ROP AHB BUS Input from formatter or scaling module Logic table index Output to Alpha CK module ROP Diagram ROP node There are many nodes in ROP module each node can realize some independent function according control table register Reference the ROP diagram following is the respective node diagram A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 451 2012 04 09 Ou v Allwinner Technology CO Ltd A10 Nodel node6 node7 node2 9 node3 node4 ROP node define 35 3 7 Alpha Color key Alpha blending Alpha blending is a convex combination of two colors allowing for transparency effects in computer graphics The value of alpha in the color code ranges from 0 0 to 1 0 where 0 0 represents a fully trans
393. omponent pre scaling rule of YUV411 to YUV444 YUV420 gnore Y component UV component use linear interpolation in x direction UV component ignore y direction The output UV component odd line always copy last even line Input Line n PO PI P2 PR eden Output Line 2n po CRP pi ORO po VT sn Pn 2 PAPO pa REP pn pn Output Line 2n 1 po CRP pr PEP po D enen Pn 2 PrP py Tra pp pn Same The UV component pre scaling rule of YUV420 to YUV444 If the source data format is YUV420 the number 2n and number 2n 1 of output line is same because of using nearest neighbor interpolation in y direction Scaler kernel algorithm Re sampling is used for generating the output pixels Up sampling is the process of inserting new data samples between original data samples to increase the sampling rate Down sampling is the process of reducing the sampling rate by removing or throwing away original data samples A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 456 2012 04 09 Ou Allwinner Technology CO Ltd A10 In order to generate the output pixels first need relate the output grid to the input grid Scaling is a pixel transformation in which an array of output pixels is generated from an array of input pixels The value of each pixel on the output pixel grid
394. on 31 PE7 SELECT 000 Input 001 Output 010 TSO_D3 011 CSIO D3 100 Reserved 101 Reserved 30 28 R W 0 110 Reserved 111 Reserved 27 PE6_SELECT 000 Input 001 Output 010 TSO_D2 011 CSIO_D2 100 Reserved 101 Reserved 26 24 R W 0 110 Reserved 111 Reserved 23 PES_SELECT 000 Input 001 Output 010 TSO_D1 011 CSIO_D1 100 SMC_VPPEN 101 Reserved 22 20 R W 0 110 Reserved 111 Reserved 19 PE4 SELECT 000 Input 001 Output 010 TS0 DO 011 CSIO DO 100 Reserved 101 Reserved 18 16 R W 0 110 Reserved 111 Reserved 15 PE3 SELECT 000 Input 001 Output 010 TS0 DVLD 011 CSIO_VSYNC 100 Reserved 101 Reserved 14 12 R W 0 110 Reserved 111 Reserved 11 PE2 SELECT 000 Input 001 Output 010 TS0 SYNC 011 CSIO HSYNC 10 8 R W 0 100 Reserved 101 Reserved A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 310 2012 04 09 Ou Allwinner Technology CO Ltd A10 110 Reserved 111 Reserved 7 PE1 SELECT 000 Input 001 Output 010 TS0 ERR 011 CSIO_CK 100 Reserved 101 Reserved 6 4 R W 0 110 Reserved 111 Reserved PEO SELECT 000 Input 001 Output 010 TSO_CLK 011 CSIO_PCK 100 Reserved 101 Reserved 2 0 R W 0 110 Reserved 111 Reserved 30 3 38 PE Configure Register 1 Register Name PE_CFG1 Offset 0x94 Default V
395. on rite H 31 24 Alpha value 1508 rav mo ww oor meve Input data pixel sequence table ex os uw i W UDF Note x means no care 1 bpp mode PS xx00 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 487 2012 04 09 Ou Allwinner Technology CO Ltd A10 P3 P3 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 Pl Pl Pl Pl 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 Pl P Pl Pi Pl Pl PO PO PO PO PO PO PO PO PO PO 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 O00 PS xx01 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P2 P2 P2 P2 P2 P2 P3 P3 Pl Pl Pl Pl P2 P2 P2 P2 4 5 6 7 8 9 0 1 6 7 8 9 0 1 2 3 PO PO PI P1 Pl Pl Pl Pl PO PO PO PO PO PO PO PO 8 9 0 1 2 3 4 5 0 1 2 3 4 5 6 7 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PS xx10 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PO PO PO PO PO PO PO PO PI Pl Pl Pl Pl Pl PO PO 7 6 5 4 3 2 1 0 5 4 3 2 1 0 9 8 P2 P2 P2 P2 P1 Pl Pl
396. on Status Register Offset 0x038 Register Name TVE 038 REG Bit Read Write Default Hex Description 31 26 25 24 R W 0 DAC3_Status 00 Unconnected 01 Connected 11 Short to ground 10 Reserved 23 18 17 16 R W DAC2_Status 00 Unconnected 01 Connected 11 Short to ground 10 Reserved 15 10 9 8 R W DACI Status 00 Unconnected 01 Connected 11 Short to ground 10 Reserved 7 2 1 0 R W DACH Status 00 Unconnected 01 Connected 11 Short to ground 10 Reserved 34 4 13 TV Encoder Notch Filter Frequency Register Offset 0x108 Register Name TVE_108_REG Bit Read Default Description Write Hex 31 3 2 0 R W 2 Notch Freq Luma notch filter center frequency selection These bits select the luma notch filter which is a band reject filter center frequency In two of the selections the filter width affects also the selection of the center frequency A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 435 2012 04 09 Ou Allwinner Technology CO Ltd A10 000 1 1875 001 1 1406 010 1 0938 when notch wide value is B 1 this selection is proper for CCIR NTSC or 1 0000 when notch wide value is B 0 011 0 9922 This selection is proper for NTSC with square pixels 100 0 9531 This selection
397. on of a stream of symbols b 0000 1100 0000 1100 0000 0110 0000 0110 ACD The payload data is encoded as 4 PPM The encoded symbols reside in the ACD field and can be up to 2048 bytes long CRC32 The CRC field consists of the 4 PPM encoded data resulting from the IEEE 802 CRC32 algorithm for cyclic redundancy check as applied to the payload data contained in the packet For MIR data rates the NZR modulation scheme is used A 0 is represented by a light pulse The optical pulse duration is nominally 1 4 of a bit duration The LED is off when a 1 is transmitted Data Bit Data Symbol Address Control and Data 0 1000 0000 MIR Modulation Scheme For 4 Mbit s FIR the modulation scheme is 4 PPM In this modulation a pair of bits is one data symbol A data symbol is divided into four chips only one of which contains an optical pulse The nominal pulse duration is 125 ns A 1 is represented by a light pulse Data Symbol 4 PPM Data Symbol A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 200 2012 04 09 Allwinner Technology CO Ltd A10 00 1000 01 0100 10 0010 11 0001 FIR Modulation Scheme For 0 576Mbit s MIR the serial clock is 12 times of 0 576Mhz witch it is 6 912Mhz For 1 152Mbit s MIR the serial clock is 12 times of 0 576Mhz witch it is 13 824Mhz For 4Mbit s FIR the serial clock is 24Mhz
398. ons For integration in systems where Infrared SIR serial data format is required the UART can be configured to have a software programmable IrDA SIR Mode If this mode is not selected only the UART RS232 standard serial data format is available The UART includes the following features Compatible with industry standard 16550 UARTs 64 Bytes Transmit and receive data FIFOs DMA controller interface Software Hardware Flow Control Programmable Transmit Holding Register Empty interrupt Support IrDa 1 0 SIR Interrupt support for FIFOs Status Change A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 178 2012 04 09 Allwinner Technology CO Ltd A10 18 2 UART Timing Diagram One Character Bit Time TX RX Serial Data S Data bits 5 8 P 1 1 5 2 Figure 18 1 UART Serial Data Format Data Bits Bit Time SIN SOUT S Stop gt 3 1 6 Bit Time gt 3 16 Bit Time SIR OUT 3 6 Bit Time SIR IN Figure 18 2 Serial IrDA Data Format 18 3 UART Register List There are 8 UART controllers UARTI has full modem control signals including RTS CTS DTR DSR DCD and RING signal UART2 3 has two data flow control singals including RTS and CTS Other UART controller has only two data signals including DIN and DOUT All UART controllers can be configured as Serial IrDA Mo
399. ontrol Register Offset 0x00 Register Name LRADC CTRL Bit Read Default Description Write Hex 31 24 R W Ox1 FIRST CONCERT DLY ADC First Convert Delay setting ADC conversion is delayed by n samples 23 22 R W 0x0 ADC CHAN SELECT ADC channel select 00 ADCO channel 01 ADCI channel lx ADCO amp ADCI channel 21 20 19 16 R W 0x0 CONTINUE TIME SELECT Continue Mode time select one of 8 N 1 sample as a valuable sample data 15 14 13 12 R W 0x0 KEY MODE SELECT A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 266 2012 04 09 Ou Allwinner Technology CO Ltd A10 Key Mode Select 00 Normal Mode 01 Single Mode 10 Continue Mode R W Ox1 LEVELA B CNT Level A to Level B time threshold select judge ADC convert value in level A to level B in n 1 samples R W Ox1 LRADC HOLD EN LRADC Sample hold Enable 0 Disable 1 Enable 5 4 R W 0x2 LEVELB_VOL Level B Corresponding Data Value setting the real voltage value 00 0x3C 1 9v 01 0x39 1 8v 10 0x36 1 7v 11 0x33 1 6v 3 2 R W 0x2 LRADC_SAMPLE_RATE LRADC Sample Rate 00 250 Hz 01 125 Hz 10 62 5 Hz 11 32 25 Hz R W 0x0 LRADC_EN LRADC enable 0 Disable 1 Enable 25 3 2 LRADC Interrupt Control Register Offset 0x04 Register Name LRADC_INT
400. ount on base of this initial value 31 0 R W 0x0 Notes It is used for Audio Video Synchronization 24 2 10 ADC RX Counter register Offset 0x34 Register Name AC_ADC_CNT Bit Read Write Default Description RX_CNT RX Sample Counter The audio sample number of writing into RXFIFO When one sample is written by Digital Audio Engine the RX sample counter register increases by one The RX sample counter register can be set to any initial valve at any time After been updated by the initial value the counter register should count on base of this initial value 31 0 R W 0x0 Notes It is used for Audio Video Synchronization A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 264 2012 04 09 Ou Allwinner Technology CO Ltd A10 25 LRADC 25 1 Overview LRADC is 6 bits resolution for key application The LRADC can work up to maximum conversion rate of 250Hz The LRADC is featured as following Support APB 32 bits bus width Support Interrupt Support Hold Key and General Key Support Single Key and continue key mode 6 bits Resolution Voltage input range between 0 to 2V Sample Rate up to 250Hz 25 2 Principle of operation 25 2 1 Block Diagram The LRADC converted data can by accessed by interrupt and polling method If software can t access the last converted data instantly the new converted data would update the old one at new samplin
401. parent color and 1 0 represents a fully opaque color In the MP If setting the alpha register value ARV OB xxxxxxxx 8 bit value In the alpha color key ALU the ARV will be transform another value for actual calculation The value represent with ARV If ARV 20 Then ARV 2 0 If ARV 0 Then ARV ARV I Then the alpha value A ARV 256 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 452 2012 04 09 O Allwinner Technology CO Ltd A10 Layer A Layer B A Fill Color Area Overlapping Area In the above diagram layer A and layer B are from ROP module or input DMA channel 3 The priority of layer A is higher than layer B The alpha value of layer A A_a The alpha value of layer B A_b The RGB value of layer A R_a G_a B_a The RGB value of layer B R_b G_b B_b The alpha value of layer A fill color A_fa The alpha value of layer B fill color A_fb The RGB value of layerA fill color R_fa G_fa B_fa The RGB value of layerB fill color R_fb G_fb B_fb In the only layer A area R R_a A_a R_fb A_fb 1 A_a G Ga Aa G_fb A_fb 1 A_a B B_a A_a B_fb A_fb 1 A_a In the only layer B area R Rb Ab R a A fa 1 A b G G b A b Gfa A fa 1 A b B B_b A_b Bfa A fa 1 A b A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 453 2012 04 09 Ou N Allwinner Technology CO Ltd A10 In the over
402. pin Phase 0 Figure 17 1 SPI Phase 0 Timing Diagram SPI_SCLK Mode 1 SPI_SCLK Mode 3 SPI MOSI SPI MISO SPI SS Sample MOSI MISO pin Phase 1 Figure 17 2 SPI Phase 1 Timing Diagram 17 3 SPI Register List Module Name Base Address SPIO 0x01C05000 SPII 0x01C06000 SPD 0x01C17000 SPI3 0x01C1F000 Register Name Offset Description SPI_RXDATA 0x00 SPI RX Data register SPI TXDATA 0x04 SPI TX Data register SPI CTL 0x08 SPI Control register SPLINTCTL Ox0C SPI Interrupt Control register SPI ST 0x10 SPI Status register A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 164 2012 04 09 Ou Allwinner Technology CO Ltd A10 SPI DMACTL 0x14 SPI DMA Control register SPI_WAIT 0x18 SPI Wait Clock Counter register SPI_CCTL Ox1C SPI Clock Rate Control register SPI BC 0x20 SPI Burst Counter register SPI TC 0x24 SPI Transmit Counter Register SPI FIFO STA 0x28 SPI FIFO Status register 17 4 SPI Register Description 17 4 1 SPI RX Data Register Offset 0x00 Register Name SPI RXDATA Default Value 0x0000 0000 Bit Read Write Default Description 31 0 R RDATA Receive Data In 8 bits SPI bus width this register can be accessed in byte half word or word unit by AHB
403. ption Write Hex 31 R W 0x0 BIST NDMA CTRL SEL Bist and Normal DMA control select 0 N DMA 1 Bist 30 20 19 Reserved 18 Reserved 17 Reserved 16 Reserved A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 76 2012 04 09 Ou Allwinner Technology CO Ltd 15 13 A10 12 R W 0x1 SRAM_C3_MAP SRAM C3 map config 0 map to CPU BIST 1 map to ISP 11 10 9 8 R W 0x3 SRAM C2 MAP SRAM C2 map config map to CPU BIST map to AE map to CE map to ACE IIS N ra 7 6 5 4 R W 0x0 SRAM A3 A4 MAP 00 map to CPU DMA 01 map to EMAC SRAM Area A3 A4 Configuration by AHB 10 11 3 1 0 R W 0x0 SRAMD_MAP SRAM D Area Config 0 map to CPU DMA 1 map to USBO A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 2012 04 09 77 Ou Allwinner Technology CO Ltd A10 8 TrustZone Protection Controller Unit 8 1 Overview The TZPC provides a software interface to the protection bits in a secure system in a TrustZone design It provides system flexibility that enables to configure different areas of memory as secure or non secure 8 2 TZPC Configuration The following table shows the configurable region Register Bit TZPCO TZPC1 TZPC2 Module Name Module Module Name Name TZPCDEC
404. put Address register 31 6 CSIO Register Description 31 6 1 CSI Enable Register Offset 0x0000 Register Name CSIO EN REG Bit Read Default Hex Description Write 31 10 9 R W 0 PCLK_CNT Pclk count per frame 8 R W 0 LUMA_EN Luma enable Ta R W 0 NON16 ADD Non 16 add 0x00 3 R W 10 RD FIFO EN Read fifo 3 fifo enable fifo address 01c09800 01c09ffc 2 R W 0 FIELD_REV Ccir656 field_reverse 0 R W 0 CSI EN Enable 0 Reset and disable the CSI module 1 Enable the CSI module 31 6 2 CSI configuration register Offset Address 0X0004 Register Name CSIO CFG REG A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 343 2012 04 09 Ou Allwinner Technology CO Ltd A10 Read Default Description Write Hex INPUT_FMT Input data format 000 RAW stream 001 reserved 010 CCIR656 one channel 011 YUV422 100 YUV422 16bit data bus 101 two channel CCIR656 110 reserved 111 four channel CCIR656 OUTPUT FMT Output data format When the input format is set RAW stream 0000 pass through When the input format is set CCIR656 interface 0000 field planar YCbCr 422 0001 field planar YCbCr 420 0010 frame planar YCbCr 420 0011 frame planar YCbCr 422 0100 field planar YCbCr 422 UV combined 0101 field planar YCbCr 420 UV combined 0110 frame planar YCbCr 420 UV combined 0111 frame planar YCbCr 422 UV combined 1111 interlaced interleaved YCbC
405. put start 0 no effect 1 output 1 pulse A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 81 2012 04 09 Ou Allwinner Technology CO Ltd A10 The pulse width should be according to the period 1 register 15 0 and the pulse state should be according to the active state After the pulse is finished the bit will be cleared automatically 22 R W 0x0 PWM_CH1_MODE PWM Channel 1 mode 0 cycle mode 1 pulse mode 21 R W 0x0 PWM_CH1_CLK_GATING Gating the Special Clock for PWM1 0 mask 1 pass 20 R W 0x0 PWM_CH1_ACT_STATE PWM Channel 1 Active State 0 Low Level 1 High Level 19 R W 0x0 PWM CHI EN PWM Channel 1 Enable 0 Disable 1 Enable 18 15 R W 0x0 PWM_CH1_PRESCAL PWM Channel 1 Prescalar These bits should be setting before the PWM Channel 1 clock gate on 0000 120 0001 180 0010 240 0011 360 0100 480 0101 0110 0111 1000 12k 1001 24k 1010 36k 1011 48k 1100 72k 1101 1110 1111 14 9 8 R W 0x0 PWM CHO PUL START PWM Channel 0 pulse output start 0 no effect 1 output 1 pulse The pulse width should be according to the period 0 register 15 0 and the pulse state should be according to the active state After the pulse is finished the bit will be cleared automatically 7 R W 0x0 PWM_CHANNELO_MODE 0 cycle mode 1 pulse mode 6 R W 0x0 SCLK C
406. pyright 2011 2012 Allwinner Technology All Rights Reserved 174 2012 04 09 Ou Allwinner Technology CO Ltd A10 17 4 9 SPI Burst Counter Register Register Name SPI_BC Offset 0x20 Default Value 0x0000_0000 Bit Read Write Default Description 31 24 BC Burst Counter In master mode this field specifies the total burst number when SMC is 1 0 0 burst 1 1 burst 23 0 R W 0 N N bursts 17 4 10 SPI Transmit Counter Register Register Name SPI_TC Offset 0x24 Default Value 0x0000_0000 Bit Read Write Default Description 31 24 WTC Write Transmit Counter In master mode this field specifies the burst number that should be sent to TXFIFO before automatically sending dummy burst when SMC is 1 For saving bus bandwidth 23 0 R W 0 the dummy burst all zero bits or all one bits is sent by SPI Controller automatically 0 0 burst 1 I burst N N bursts 17 4 11 SPI FIFO Status Register Register Name SPI FIFO STA Offset 0x28 Default Value 0x0000 0000 Bit Read Write Default Description 31 25 TF CNT 22 16 R 0x0 TXFIFO Counter A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 175 2012 04 09 Ou Allwinner Technology CO Ltd A10 These bits indicate the number of words in TXFIFO 0 0 byte in TXFIFO 1 1 byte in TXFIFO 63 63 bytes in TXFIFO
407. pyright O 2011 2012 Allwinner Technology All Rights Reserved 2012 04 09 287 Ou Allwinner Technology CO Ltd A10 9 Port n Pull Register 1 n from 0 to Pn PULI n 0x24 0x20 9 PIO INT CFGO 0x200 PIO Interrrupt Configure Register 0 PIO INT CFGI 0x204 PIO Interrrupt Configure Register 1 PIO INT CFG2 0x208 PIO Interrrupt Configure Register 2 PIO INT CFG3 0x20C PIO Interrrupt Configure Register 3 PIO INT CTL 0x210 PIO Interrupt Control Register PIO INT STA 0x214 PIO Interrupt Status Register PIO INT DEB 0x218 PIO Interrupt Debounce Register SDRAM Pad Multi Driving SDR PAD DRV 0x220 Register SDR PAD PUL 0x224 SDRAM Pad Pull Register 30 3 Port Register Description 30 3 1 PA Configure Register 0 2012 04 09 Register Name PA CFGO Offset 0x00 Default Value 0x0000 0000 Bit Read Write Default Description 31 PA7_SELECT 000 Input 001 Output 010 ETXDO 011 SPI3 MOSI 100 Reserved 101 Reserved 30 28 R W 0 110 Reserved 111 Reserved 27 Reserved PA6 SELECT 000 Input 001 Output 010 ETXD1 011 SPI3_CLK 100 Reserved 101 Reserved 26 24 R W 0 110 Reserved 111 Reserved 23 PA5 SELECT 000 Input 001 Output 010 ETXD2 011 SPI3 CSO 100 Reserved 101 Reserved 22 20 R W 0 110 Reserved 111 Reserved 19 18 16 R W 0 PA4 SELECT A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reser
408. r Offset Address 0X440 Register Name ISP FE LSC ADDR REG Bit Read Default Description Write Hex 31 00 R W LSC ADDR PP NK 31 6 71 ISP LSC gain factor address length register Offset Address 0X444 Register Name ISP_FE_LSC_LEN_REG Bit Read Default Description me me MM 12 00 R W LSC LEN The length for LSC gain factor table in byte while accessing DRAM ranges from 0 to 4096 This should be integer multiplier of 0X20 31 6 72 ISP Offset register Offset Address 0X44C Register Name ISP_FE_OFFSET_REG Bit Read Default Description Write Hex 08 00 R W OFFSET_VAL The offset value A signed number ranges from 256 to 255 31 6 73 ISP Gain Factor register Offset Address 0X450 Register Name ISP_FE_GAIN_REG Bit Read Default Description Write Hex A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 371 2012 04 09 Ou Allwinner Technology CO Ltd A10 d Gain factor for even pixel even line in U8Q5 format 23 16 R W 20 GAIN2 Gain factor for odd pixel even line in U8Q5 format 15 08 R W 20 GAINI Gain factor for even pixel odd line in U8Q5 format 07 00 R W 20 GAINO Gain factor for odd pixel odd line in U8Q5 format 31 6 74 ISP Dark Frame Enable register Offset Address 0X45C Register Name ISP FE DF EN REG Read Default Description Write Hex mor n R W DF SUB EN Dark Frame Subtraction Enable This bit has double buffer it
409. r 1 clock source 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 3 2 R W Ox1 TMR1 CLK SRC Timer 1 Clock Source 00 Low speed OSC 01 OSC24M 10 PLL6 6 11 R W 0x0 TMR1_RELOAD Timer 1 Reload 0 No effect 1 Reload timer 1 Interval value R W 0x0 TMR1_EN Timer 1 Enable 0 Stop Pause 1 Start If the timer is started it will reload the interval value to internal register and the current counter will count from interval value to 0 If the current counter does not reach the zero the timer enable bit is set A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 90 2012 04 09 Ou Allwinner Technology CO Ltd A10 to 0 the current value counter will pause At least wait for 2 Tcylces the start bit can be set to 1 In timer pause state the interval value register can be modified If the timer is started again and the Software hope the current value register to down count from the new interval value the reload bit and the enable bit should be set to 1 at the same time Note the time between the timer disabled and enabled should be larger than 2 Tcycles Tcycles Timer clock source pre scale 10 3 7 Timer 1 Interval Value Register Offset 0x24 Register Name TMR1 INTV VALUE REG Bit Read Default Description Write Hex 31 0 R W x TMR1_INTV_VALUE
410. r of a frame na 7 3 LLL 12 00 R W VER START Vertical line start data is valid from this line A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 355 2012 04 09 Ou Allwinner Technology CO Ltd A10 31 6 30 CSI Channel 1 buffer length register Offset Address 0X0148 Register Name CSIO C1 BUF LEN REG Bit Read Default Description Write Hex 12 00 R W 280 BUF_LEN Buffer length of a line Unit is byte It is the max of the 3 FIFOs 31 6 31 CSI Channel 2 FIFO 0 output buffer A address register Offset Address 0X0210 Register Name CSI0 C2 FO BUFA REG Bit Read Default Description me m ooo oo mmm 31 00 R W C2F0 BUFA PITT CRM 31 6 32 CSI Channel 2 FIFO 0 output buffer B address register Offset Address 0X0214 Register Name CSIO C2 FO BUER REG Bit Read Default Description TS oo oo rmm 31 00 R W C2F0 BUER PPT eene 31 6 33 CSI Channel 2 FIFO 1 output buffer A address register Offset Address 0X0218 Register Name CSIO C2 F1 BUFA REG Bit Read Default Description Write Hex 31 00 R W C2F1_BUFA FIFO 1 output buffer A address 31 6 34 CSI Channel 2 FIFO 1 output buffer B address register Offset Address 0X021C Register Name CSIO C2 F1 BUFB REG Bit Read Default Description Write Hex A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 356 2012 04 09 Allwinner Technology CO Ltd A10 31 00
411. r422 In this mode capturing interlaced input and output the interlaced fields from individual ports Field 1 data will be wrote to FIFOO output buffer and field 2 data will be wrote to FIFO1 output buffer 1000 field tiled based YCbCr 422 1001 field tiled based YCbCr 420 1010 frame tiled based YCbCr 420 1011 frame tiled based YCbCr 422 When the input format is set YUV422 0000 planar YUV 422 0001 planar YUV 420 0100 planar YUV 422 UV combined 0101 planar YUV 420 UV combined 1000 tiled based YUV 422 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 344 2012 04 09 Allwinner Technology CO Ltd A10 1001 tiled based YUV 420 HET ANNE 11 10 R W FIELD_SEL Field selection Applies to CCIR656 interface only 00 start capturing with field 1 O1 start capturing with field 2 10 start capturing with either field 11 reserved 09 08 INPUT_SEQ DS data sequence only valid for YUV422 mode VREF_ MM Vref polarity 0 negative 1 positive This register is not apply to CCIR656 interface HERE POL Href polarity 0 negative 1 positive This register is not apply to CCIR656 interface CLK POL Data clock type 0 active in falling edge 1 active in rising edge 31 6 3 CSI capture control register Offset Address 0X0008 Register Name CSIO CAP REG Bit Read Default Description Write Hex mr porn VCAP ON Video capture control Capture the vide
412. re control Capture the video image data stream 0 Disable video capture If video capture is in progress the CSI stops capturing image data at the end of the current frame and all of the current frame data is wrote to output FIFO 1 Enable video capture The CSI starts capturing image data at the start of the next frame SCAP_ON Still capture control Capture a single still image frame 0 Disable still capture 1 Enable still capture The CSI module starts capturing image data at the start of the next frame The CSI module captures only one frame of image data This bit is self clearing and always reads as a 0 32 6 4 CSI horizontal scale register Offset Address 0X000C Register Name CSIO SCALE REG A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 389 2012 04 09 Allwinner Technology CO Ltd A10 27 24 R W F VER MASK Vertical line mask Every 4 line is a mask group Bit 24 mask the first line bit 25 mask the second line and so on Mask bit 0 means discarding this line data 15 00 R W FFFF HOR MASK Horizontal datastream mask Every 16 byte is a mask group Bit 0 mask the firest byte bit I mask the second byte and so on Mask bit 0 means discarding this byte from the datastream 32 6 5 CSI Channel 0 FIFO 0 output buffer A address register Offset Address 0X0010 Register Name CSI1 F0 BUFA REG Bit Read Default Description Write Hex 31 00 R W F0
413. ress 0X0048 Register Name CSIO C0 BUF LEN REG Read Default Description Write Hex a or n 12 00 R W BUF LEN Buffer length of a line Unit is byte It is the max of the 3 FIFOs 31 6 18 CSI Channel 1 FIFO 0 output buffer A address register Offset Address 0X0110 Register Name CSIO C1 F0 BUFA REG Bit Read Default Description Write Hex 31 00 R W CIF0 BUFA FIFO 0 output buffer A address 31 6 19 CSI Channel 1 FIFO 0 output buffer B address register Offset Address 0X0114 Register Name CSIO C1 F0 BUFB REG Bit Read Default Description Write Hex 31 00 R W CIF0 BUER FIFO 0 output buffer B address 31 6 20 CSI Channel 1 FIFO 1 output buffer A address register Offset Address 0X0118 Register Name CSIO C1 F1 BUFA REG Bit Read Default Description Write Hex A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 351 2012 04 09 Allwinner Technology CO Ltd A10 31 00 R W C1F1 BUFA FIFO 1 output buffer A address 31 6 21 CSI Channel 1 FIFO 1 output buffer B address register Offset Address 0X011C Register Name CSIO C1 F1 BUFB REG Bit Read Default Description Write Hex 31 00 R W C1F1 BUER FIFO 1 output buffer B address 31 6 22 CSI Channel 1 FIFO 2 output buffer A address register Offset Address 0X0120 Register Name CSIO C1 F2 BUFA REG Bit Read Default Description Write Hex 31 00 R W CIF2 BUFA TI RENI 31 6 23 CSI Channel 1 FIF
414. rom 0 to 4096 31 6 93 ISP Histogram region 1 window start register Offset Address 0X4C4 Register Name ISP_FE_HIST1_POS_REG Read Default Description Write Hex Pu 1 2 1 o o 27 16 R W HIST1_VER_START Histogram region 1 window vertical start position Ranges from 0 to 4095 11 00 R W HIST1_HOR_START Histogram region 1 window horizontal start position Ranges from 0 to 4095 31 6 94 ISP Histogram region 2 window size register Offset Address OXAC8 Register Name ISP FE HIST2 SIZE REG A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 378 2012 04 09 Ou Allwinner Technology CO Ltd A10 Read Default Description Write Hex EE OE E LL 28 16 R W HIST2 HEIGHT Histogram region 2 window height Ranges from 0 to 4096 DEE 12 00 R W HIST2_WIDTH Histogram region 2 window width Ranges from 0 to 4096 31 6 95 ISP Histogram region 2 window start register Offset Address OXACC Register Name ISP FE HIST2 POS REG Read Default Description Write Hex Gas pg 27 16 R W HIST2 VER START Histogram region 2 window vertical start position Ranges from 0 to 4095 11 00 R W HIST2_HOR_START Histogram region 2 window horizontal start position Ranges from 0 to 4095 31 6 96 ISP Histogram region 3 window size register Offset Address 0X4D0 Register Name ISP FE HIST3 SIZE REG Read Default Description Write Hex Pa o S 28 16 R W HIST3_HEIGHT Histogram r
415. rrupt is enabled 0 No IRQ 1 IRQ Pending Notes Writing 1 to the bit will clear it and its corresponding interrupt if the interrupt is enable 11 R W 0x0 ADC1_ALRDY_HOLD_PENDING ADC 1 Already Hold Pending Bit When hold key pull down and pull the general key down if the corresponding interrupt is enabled 0 No IRQ 1 IRQ Pending Notes Writing 1 to the bit will clear it and its corresponding interrupt if the interrupt is enable 10 R W 0x0 ADC1_HOLDKEY_PENDING ADC 1 Hold Key pending Bit When Hold key pull down the status bit is set and the interrupt line is set if the corresponding interrupt is enabled 0 NO IRQ 1 IRQ Pending Notes Writing 1 to the bit will clear it and its corresponding interrupt if the interrupt is enable 9 R W 0x0 ADC1_KEYDOWN_IRQ_PENDING ADC 1 Key Down IRQ Pending Bit When General key pull down the status bit is set and the interrupt line is set if the corresponding interrupt is enabled 0 No IRQ 1 IRQ Pending Notes Writing 1 to the bit will clear it and its corresponding interrupt if the interrupt is enable 8 R W 0x0 ADC1 DATA IRQ PENDING ADC 1 Data IRQ Pending Bit 0 No IRQ 1 IRQ Pending Notes Writing 1 to the bit will clear it and its corresponding interrupt if the interrupt is enable 7 5 4 R W 0x0 ADCO KEYUP PENDING ADC 0 Key up pending Bit When general key pull up it the corresponding interrupt is enabled 0 No IRQ 1
416. s The 32768Hz oscillator is used only to provide a low power accurate reference for the RTC In order to provide the high performance low power consumption and easy user interface the chip has the following clock domain CLK Module Speed Range Description Domain OSC24M Most Clock 24MHz Root clock for most of the chip Generator RC osc Timer Key 32KHz Source for the RTC Timer 32K768Hz Timer Key 32768Hz Low power source for the RTC Timer CPU32_clk CPU32 2K 1200M Divided from CPU32_clk or OSC24M AHB clk AHB Devices 8K 276M Divided from CPU32_clk APB clk Peripheral 0 5K 138M Divided from AHB_clk SDRAM clk SDRAM 0 400MHz Sourced from the PLL USB clk USB 480MHz Sourced from the PLL Audio clk A D D A 24 576MHz Sourced from the PLL 22 5792MHz 6 2 Clock Tree Diagram Notes See details in the datasheet of A10 6 3 CCM Register List Module Name Base Address CCM 0x01C20000 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 35 2012 04 09 Ou Allwinner Technology CO Ltd A10 Register Name Offset Description PLL1_CFG_REG 0x0000 PLLI1 control PLL1 TUN REG 0x0004 PLLI tuning PLL2 CFG REG 0x0008 PLL2 control PLL2 TUN REG 0x000C PLL2 tuning PLL3 CFG REG 0x0010 PLL3 control PLL4 CFG REG 0x0018 PLL4 control PL
417. s Reserved 217 2012 04 09 Ou Allwinner Technology CO Ltd A10 22 Digital Audio Interface 22 1 Overview The Digital Audio Interface can be configured as I2S interface or PCM interface by software When configured as I2S interface it can support the industry standard format for I2S left justified or right justified When configured as PCM it can be used to transmit digital audio over digital communication channels It supports linear 13 16 bits linear 8 bit u law or A law compressed sample formats at 8K samples sec and can receive and transmit on any selection of the first four slots following PCM_SYNC It includes the following features m PDS or PCM configured by software Full duplex synchronous serial interface Configurable Master Slave Mode operation Support Audio data resolutions of 16 20 24 DS Audio data sample rate from 8Khz to 192Khz DS Data format for standard I2S Left Justified and Right Justified DS support 8 channel output and 2 channel input PCM supports linear sample 8 bits or 16 bits 8 bits u law and A law compressed sample One 128x24 bits FIFO for data transmit one 64x24 bits FIFO for data receive Programmable FIFO thresholds Support Interrupt and DMA Two 32 bits Counters for AV sync application The Digital Audio Interface block diagram is shown below A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 218 2012 04 09 Allwinner Technology CO
418. s register Offset Address 0X031C Register Name CSIO C3 F1 BUFB REG Bit Read Default Description Write Hex 31 00 R W C3F1 BUFB FIFO 1 output buffer B address 31 6 48 CSI Channel 3 FIFO 2 output buffer A address register Offset Address 0X0320 Register Name CSIO C3 F2 BUFA REG Bit Read Default Description Write Hex 31 00 R W C3F2 BUFA FIFO 2 output buffer A address A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 361 2012 04 09 Ou Allwinner Technology CO Ltd A10 31 6 49 CSI Channel 3 FIFO 2 output buffer B address register Offset Address 0X0324 Register Name CSIO C3 F2 BUFB REG Read Default Description Write Hex Bit 31 00 R W C3F2 BUFB FIFO 2 output buffer B address 31 6 50 CSI Channel 3 output buffer control register Offset Address 0X0328 Register Name CSIO C3 BUF CTL REG Bit Read Default Description Write Hex 02 R W DBN Buffer selected at next storing for CSI 0 Next buffer selection is buffer A 1 Next buffer selection is buffer B DBS output buffer selected status 0 Selected output buffer A 1 Selected output buffer B DBE Double buffer mode enable 0 disable 1 enable If the double buffer mode is disabled the buffer A will be always selected by CSI module 31 6 51 CSI Channel_3 status register Offset Address 0X032C Register Name CSI0 C3 BUF STA REG Bit Read Default Description Write Hex 31 08 LUM_STATIS
419. scription 31 7 TXU INT TX FIFO Under run Pending Interrupt 0 No Pending Interrupt 1 FIFO Under run Pending Interrupt TXO INT TX FIFO Overrun Pending Interrupt 0 No Pending Interrupt 1 FIFO Overrun Pending Interrupt Write 1 to clear this interrupt TXE INT TX FIFO Empty Pending Interrupt 0 No Pending IRQ 1 FIFO Empty Pending Interrupt Write 1 to clear this interrupt or automatic clear if interrupt condition fails 2 R W RXU INT RX FIFO Under run Pending Interrupt 0 No Pending Interrupt 1 FIFO Under run Pending Interrupt A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 228 2012 04 09 Ou Allwinner Technology CO Ltd A10 Write 1 to clear this interrupt RXO_INT RX FIFO Overrun Pending Interrupt 0 No Pending IRQ 1 FIFO Overrun Pending IRQ 1 R W 0 Write 1 to clear this interrupt RXA_INT RX FIFO Data Available Pending Interrupt 0 No Pending IRQ 1 Data Available Pending IRQ Write 1 to clear this interrupt or automatic clear if 0 R W 0 interrupt condition fails 22 4 10 Digital Audio Clock Divide Register Register Name DA_CLKD Offset 0x24 Default Value 0x0000_0000 Bit Read Write Default Description 31 8 MCLKO_EN 0 Disable MCLK Output 1 Enable MCLK Output Notes Whether in Slave or Master mode when this bit
420. scription Write Hex KJE 28 24 R W AWBE_INC AE AWB line increment number INC Ranges from 0 to 16 mf 9 19 16 R W AWBE RS AE AWB right shifter before accumulation Ranges from 0 to 15 nw ps 00 07 00 R W AWBE LMT AE AWB saturation limit ranges from 0 to 255 31 6 90 ISP Histogram region 0 window size register Offset Address 0X4B8 Register Name ISP FE HISTO SIZE REG Read Default Description Write Hex Gap RS 28 16 R W HISTO_HEIGHT Histogram region 0 window height Ranges from 0 to 4096 7 12 00 R W HISTO WIDTH Histogram region 0 window width Ranges from 0 to 4096 31 6 91 ISP Histogram region 0 window start register Offset Address OX4BC Register Name ISP FE HISTO POS REG A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 377 2012 04 09 Ou Allwinner Technology CO Ltd A10 Read Default Description Write Hex 27 16 R W HISTO_VER_START Histogram region 0 window vertical start position Ranges from 0 to 4095 11 00 R W HISTO_HOR_START Histogram region 0 window horizontal start position Ranges from 0 to 4095 31 6 92 ISP Histogram region 1 window size register Offset Address 0X4C0 Register Name ISP_FE_HIST1_SIZE_REG Read Default Description Write Hex Gap RS 28 16 R W HIST1_HEIGHT Histogram region 1 window height Ranges from 0 to 4096 mf 0 9 12 00 R W HISTI WIDTH Histogram region 1 window width Ranges f
421. ser Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 347 2012 04 09 Ou Allwinner Technology CO Ltd A10 Description Buffer selected at next storing for CSI 0 Next buffer selection is buffer A 1 Next buffer selection is buffer B DBS output buffer selected status 0 Selected output buffer A 1 Selected output buffer B DBE Double buffer mode enable 0 disable 1 enable If the double buffer mode is disabled the buffer A will be always selected by CSI module Offset Address 0X002C Register Name CSIO C0 BUF STA REG Read Default Description Write Hex LUM_STATIS luminance statistical value When frame done interrupt flag come value is ready and will last until next frame done Video capture in progress Indicates the CSI is capturing video image data multiple frames The bit is set at the start of the first frame after enabling video capture When software disables video capture it clears itself after the last pixel of the current frame is captured SCAP_STA Still capture in progress Indicates the CSI is capturing still image data single frame The bit is set at the start of the first frame after enabling still frame capture It clears itself after the last pixel of the first frame is captured A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 348 2012 04 09 Ou Allwinner Technology CO Ltd A10 For CCIR656 interface i
422. serted when condition 2 R W 0 fails RAI EN RX FIFO Available Interrupt Enable 0 Disable 1 Enable When set to 1 the Receiver FIFO IRQ is asserted if reaching RAL The IRQ is de asserted when condition 4 R W 0 fails CRCI EN Receiver CRC Error Interrupt Enable 0 Disable 3 R W 0 1 Enable RISI EN Receiver Illegal Symbol Interrupt Enable 0 Disable 2 R W 0 1 Enable RPEI EN Receiver Packet End Interrupt Enable 0 Disable 1 R W 0 1 Enable A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 209 2012 04 09 Ou Allwinner Technology CO Ltd A10 ROI_EN Receiver FIFO Overrun Interrupt Enable 0 Disable 0 R W 0 1 Enable 19 4 13 IR Receiver Status Register Register Name IR_RXSTA Offset 0x30 Default Value 0x0000_0000 Bit Read Write Default Description 31 13 RAC RX FIFO Available Counter 0 No available data in RX FIFO 1 1 byte available data in RX FIFO 2 2 byte available data in RX FIFO 12 8 R 0 16 16 byte available data in RX FIFO 7 5 RA RX FIFO Available 0 RX FIFO not available according its level 1 RX FIFO available according its level 4 R W 0 This bit is cleared by writing a 1 CRC Receiver CRC Error Flag 0 No CRC failure 1 CRC failure 3 R W 0 This bit is cleared by writing a 1 RIS Receiver Illegal Symbol Flag 0 No illegal symbols in addre
423. sets this bit to a 1 drive resume signaling The Host Controller sets this bit to a 1 if a J to K transition is detected while the port is in the Suspend state When this bit transitions to a one because a J to K transition is detected the Port Change Detect bit in the USBSTS register is also set to a one If software sets this bit to a one the host controller must not set the Port Change Detect bit Note that when the EHCI controller owns the port the resume sequence follows the defined sequence documented in the USB Specification Revision 2 0 The resume signaling Full speed K is driven on the port as long as this remains a one Software must appropriately time the Resume and set this bit to a zero when the appropriate amount of time has elapsed Writing a zero from one causes the port to return high speed mode forcing the bus below the port into a high speed idle This bit will remain a one until the port has switched to high speed idle The host controller must complete this transition within 2 milliseconds of software setting this bit to a zero This field is zero if Port Power is zero R WC OCC Over current Change Default 0 This bit gets set to a one when there is a change to Over current Active Software clears this bit by writing a one to this bit position R OCA A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 212 2012 04 09 Ou Allw
424. should be reloaded by hardware at every vsync saf EE EE R W DF_WR_EN Dark Frame Write Enable This bit has double buffer it should be reloaded by hardware at every vsync The Dark Frame Write and Subtraction can not be enabled at the same time When in e the dark frame write should be started first After the writing has been done the subtraction should be enabled by the software 31 6 75 ISP Dark Frame buffer address register Offset Address 0X460 Register Name ISP_FE_DF_ADDR_REG Bit Read Default Description Write Hex 31 00 R W DF_ADDR Dark Frame Write and Subtraction Buffer Address DRAM Address P S This register has double buffer it should be reloaded by hardware at every vsync 31 6 76 ISP Dark Frame buffer address length register Offset Address 0X464 Register Name ISP_FE_DF_LEN_REG A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 372 2012 04 09 Ou Allwinner Technology CO Ltd A10 Read Default Description Write Hex 12 00 R W 500 DF_LEN The length of dark frame data in Byte while accessing DRAM ranges from 0 to 4096 This should be integer multiplier of 0X20 P S This register has double buffer it should be reloaded by hardware at every vsync 31 6 77 ISP luma DC subtraction value register Offset Address OX46C Register Name ISP FE DC SUB REG Read Default Description Write Hex us 7 qr 07 00 R W LUMA DC SUB VAL Luma DC
425. ss control data or CRC field 1 Illegal symbol in address control data or CRC field 2 R W 0 This bit is cleared by writing a 1 RPE Receiver Packet End Flag 0 STO was not detected In CIR mode one CIR symbol is receiving or not detected 1 STO field or packet abort symbol 7 b0000 000 and 8 b0000 0000 for MIR and FIR is detected In CIR 1 R W 0 mode one CIR symbol is received A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 210 2012 04 09 Ou Allwinner Technology CO Ltd A10 This bit is cleared by writing a 1 R W ROI Receiver FIFO Overrun 0 Receiver FIFO not overrun 1 Receiver FIFO overrun This bit is cleared by writing a 1 19 4 14 CIR Configure Register Register Name IR_CIR Offset 0x34 Default Value 0x0000_1828 Bit Read Write Default Description 31 16 ITHR Idle Threshold for CIR The Receiver uses it to decide whether the CIR command has been received If there is no CIR signal on the air the receiver is staying in IDLE status One active pulse will bring the receiver from IDLE status to Receiving status After the CIR is end the inputting signal will keep the specified level high or low level for a long time The receiver can use this idle signal duration to decide that it has received the CIR command The corresponding flag is asserted If the correspond
426. ster 0 Register Name PG_PULLO Offset 0xF4 Default Value 0x0000 0000 Bit Read Write Default Description 31 24 PG PULL PG n Pull up down Select n 2 0 11 2i 1 2i 00 Pull up down disable 01 Pull up 120 11 R W 0x0 10 Pull down 11 Reserved 30 3 63 PG Pull Register 1 Offset OxF8 Register Name PG_PULL1 Default Value 0x0000_0000 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 319 2012 04 09 Ou Allwinner Technology CO Ltd A10 Bit Read Write Default Description 31 0 30 3 64 PH Configure Register 0 Register Name PH CFGO Offset OxFC Default Value 0x0000 0000 Bit Read Write Default Description 31 PH7 SELECT 000 Input 001 Output 010 LCD1 D7 011 ATAD3 100 UARTS_RX 101 MS_CLK 30 28 R W 0 110 EINT7 111 CSI D7 27 PH6 SELECT 000 Input 001 Output 010 LCD1_D6 011 ATAD2 100 UARTS TX 101 MS BS 26 24 R W 0 110 EINT6 111 CSI1 D6 23 PH5 SELECT 000 Input 001 Output 010 LCD1 D5 011 ATADI 100 UART4 RX 101 Reserved 22 20 R W 0 110 EINTS 111 CSI D5 19 PH4 SELECT 000 Input 001 Output 010 LCD1_D4 011 ATADO 100 UART4 TX 101 Reserved 18 16 R W 0 110 EINT4 111 CSI D4 15 PH3 SELECT 000 Input 001 Output 010 LCD1_D3 011 ATAIRQ 100 UART3 CTS 101 Reserved 14 12 R W 0 110 EINT3 111 C
427. ster can be set by software The LSB bit of the 33 bits counter register should be zero when the initial value is updated It will count from the initial value The initial value can be updated at any time It can also be paused by setting AVS CNTI PS to 1 When it is paused the counter won t increase 10 3 23 AVS Counter Divisor Register Default 0x05DBO5DB Offset 0x8C Register Name AVS CNT DIV REG Bit Read Default Description Write 31 28 AVS CNTI D Divisor N for AVS Counter AVS CNI CLK 24MHz Divisor_N1 Divisor N1 Bit 27 16 1 27 16 R W Ox5DB The number N is from 1 to 0x7ff The zero value is reserved A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 98 2012 04 09 Allwinner Technology CO Ltd A10 The internal 33 bits counter engine will maintain another 12 bits counter The 12 bits counter is used for counting the cycle number of one 24Mhz clock When the 12 bits counter reaches gt N the divisor value the internal 33 bits counter register will increase I and the 12 bits counter will reset to zero and restart again Notes It can be configured by software at any time 15 12 11 0 R W Ox5DB AVS CNTO D Divisor N for AVS CounterO AVS CNO CLK 24MHz Divisor NO Divisor NO Bit 11 0 1 The number N is from 1 to 0x7ff The zero value is reserved The internal 33 bits counter engine
428. t 0x88 Register Name INTC PRIO REG2 Bit Read Default Description Write Hex 31 30 R W 0x0 IRQ47 PRIO IRQ 47 Priority Set priority level for IRQ bit 47 A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 2012 04 09 124 Ou Allwinner Technology CO Ltd Offset 0x88 Register Name INTC_PRIO_REG2 A10 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority 29 28 R W 0x0 IRQ46_PRIO IRQ 46 Priority Set priority level for IRQ bit 46 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 Ox1 level 2 Level3 Ox1 level 3 highest priority 27 26 R W 0x0 IRQ45_PRIO IRQ 45 Priority Set priority level for IRQ bit 45 Level0 0x0 level 0 lowest priority Levell 0x1 level 1 Level2 Ox1 level 2 Level3 Ox1 level 3 highest priority 25 24 R W 0x0 TRQ44_RPIO IRQ 44 Priority Set priority level for IRQ bit 44 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority 23 22 R W 0x0 IRQ43_PRIO IRQ 43 Priority Set priority level for IRQ bit 43 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 Ox1 level 2 Level3 Ox1 level 3 highest priority 21 20 R W 0x0 IRQ42_PRIO IRQ 42 Priority Set priority level for IRQ bit 42 Level0 0x0 level
429. t Controller Interface OHCI Specification Release 1 0a The controller supports high speed 480 Mbps transfers 40 times faster than USB 1 1 full speed mode using an EHCI Host Controller as well as full and low speeds through one or more integrated OHCI Host Controllers The USB host controller includes the following features M Including an internal DMA Controller for data transfer with memory B Complies with Enhanced Host Controller Interface EHCI Specification Version 1 0 and the Open Host Controller Interface OHCI Specification Version 1 0a E Support High Speed HS 480 Mbps Device only Full Speed FS 12Mbps and Low Speed LS 1 5Mbps Device W Support only I USB Root Port shared between EHCI and OHCI The USB host controller System Level block diagram is shown below USB HCI AN EHCI nm o Nr 5 ea d ea o T AHB N EN 4 Us lt N Slave g SE Puy BE SR B E 2 a un Ze OHCI m 8 E DRAM Memory A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 216 2012 04 09 Allwinner Technology CO Ltd A10 21 2 USB Host Timing Diagram Please refer USB2 0 Specification Enhanced Host Controller Interface EHCI Specification Version 1 0 and the Open Host Controller Interface OHCI Specification Release 1 0a A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Right
430. t DMA channel should match the same memory scan order rule with the input DMA channel 35 5 4 Input DMA start address high 4bits register Offset 0xC Register Name MP IDMA H4ADD REG Read W Default Description rite Hex Ear p L A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 462 2012 04 09 Allwinner Technology CO Ltd A10 19 16 R W IDMA2 H4ADD iDMA2 High 4bits address in bits Ee IDMA1_H4ADD iDMAI High 4bits address in bits 35 5 5 Input DMA start address low 32bits register Offset Register Name MP IDMA L32ADD REG iDMA0 0x10 iDMA1 0x14 iDMA2 0x18 iDMA3 0x1C Read W Default Description rite Hex R W IDMA_L32ADD iDMA Low 32bits address in bits 35 5 6 Input DMA line width register Offset Register Name MP_IDMALINEWIDTH_REG iDMA0 0x20 iDMA1 0x24 iDMA2 0x28 iDMA3 0x2C Read W Default Description rite Hex R W IDMA LINEWIDTH iDMA Line width in bits A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 463 2012 04 09 Allwinner Technology CO Ltd A10 35 5 7 Input DMA memory block size register Offset Register Name MP IDMASIZE REG iDMA0 0x30 iDMA1 0x34 iDMA2 0x38 iDMA3 0x3C Read W Default Description rite Hex Eus p E 28 16 R W IDMA HEIGHT Memory block height in pixels m The height The value of these bits add 1 IDMA_WIDTH Memory block widt
431. t Read Default Description Write Hex 31 R W 0x0 DMA LOADING DMA Loading If set to 1 DMA will start and load the DMA registers to the shadow registers The bit will hold on until the DMA finished It will be cleared automatically Set 0 to the bit will reset the corresponding DMA channel 30 R W 0x0 DMA_CONTI_MODE EN DMA Continuous Mode Enable 0 Disable 1 Enable 29 27 R W 0x0 DMA WAIT STATE DMA Wait State 0 wait for 0 DMA clock to request 7 wait for 2 DMA clock to request 26 25 R W 0x0 NDMA_DEST_DATA_WIDTH Normal DMA Destination Data Width 00 8 bit 01 16 bit 10 32 bit 11 24 23 R W 0x0 DMA_DEST_BST_LEN DMA Destination Burst Length 00 1 01 4 10 8 11 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 141 2012 04 09 22 R W 0x0 GW Allwinner Technology CO Ltd A10 DMA_DEST_SEC DMA Destination Security 0 secure 1 non secure 21 R W 0x0 NDMA_DEST_ADDR_TYPE Normal DMA Destination Address Type 0 Increment 1 No Change 20 16 R W 0x0 NDMA_DEST_DRQ_TYPE Normal DMA Destination DRQ Type 00000 IRO TX 00001 IR1 TX 00010 NC 00011 IIS TX 00100 00101 AC97 TX 00110 00111 01000 UARTO TX 01001 UARTI TX 01010 UART2 TX 01011 UART3 TX 01100 UART4 TX 01101 UART5 TX 01110 UART6 TX 01111 UART7 TX 10000 HDMI DDC TX 10001 10010 10011 Audio C
432. t Read Default Description Write Hex 31 0 6 4 9 PLL7 Video 1 Default 0x0010D063 Offset 0x30 Register Name PLL7_CFG_REG Bit Read Default Description Write Hex 31 R W 0x0 PLL7_Enable 0 Disable 1 Enable In the integer mode The PLL7 output 3MHz M In the fractional mode the PLL7 output is select by bit 14 The PLL7 output range is 27MHz 381MHz 30 29 27 23 21 15 R W Ox1 PLL7 MODE SEL PLL7 mode select 0 fractional mode 1 integer mode 14 R W Ox1 PLL7 FRAC SET PLLT fractional setting 0 270MHz 1 297MHz 13 7 6 0 R W 0x63 PLL7_FACTOR_M A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 43 2012 04 09 Ou Allwinner Technology CO Ltd A10 PLL7 Factor M The range is from 9 to 127 6 4 10 PLL1 Tuning2 Default 0x00000000 Offset 0x38 Register Name PLL1 TUN2 REG Bit Read Default Description Write Hex 31 R W 0x0 SIG DELT DAT EN Sigma delta pattern enable 30 29 R W 0x0 SPR_FREQ_MODE Spread Frequency Mode 00 DC 0 01 DC 1 10 Triangular 11 awmode 28 20 R W 0x0 WAVE_STEP Wave step 19 18 17 R W 0x0 FREQ Frequency 00 31 5KHz 01 32KHz 10 32 5KHz 11 33KHz 16 0 R W 0x0 WAVE BOT Wave Bottom 6 4 11 PLL5 Tuning2 Default 0x00000000 Offset 0x3C Register Name P
433. t Read Default Description Write Hex A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 380 2012 04 09 Ou Allwinner Technology CO Ltd A10 31 00 R W DEF_LUT_ADDR The memory address for LUT DRAM Address 31 6 101 ISP FE Y Raw Output address length register Offset Address OXAEC Register Name ISP FE Y LEN REG Bit Read Description ISP FE Y LEN The length of ISP FE Y Raw Output data in Byte while accessing DRAM ranges from 0 to 4096 This should be integer multiplier of 0X20 P S This register has double buffer it should be reloaded by hardware at every vsync 31 6 102 SP FE Y Raw Output address register Offset Address 0X4F0 Register Name ISP FE Y ADDR REG Bit Read Default Description Write Hex R ISP FE Y ADDR The memory address for ISP FE Y Raw output DRAM Address P S This register has double buffer it should be reloaded by hardware at every vsync gu 31 6 103 ISP interrupt enable register Offset Address 0X4F4 Register Name ISP FE INT EN REG Bit Read Default Description Write Hex HIST3 INT EN 31 8 Histogram region 3 statistic done interrupt enable HIST2_INT_EN Histogram region 2 statistic done interrupt enable HIST1_INT_EN Histogram region statistic done interrupt enable HISTO_INT_EN Histogram region 0 statistic done interrupt enable n prwumm A10 User Manual V1 20 Copyright 2011 2012 Allwinn
434. t Space EE 447 EK GE Ee EE 448 3536 ROP acsi eaa teet eite ee eeu iv tede dee ved rv deerit deas 451 35 3 Alpha Or 452 EN 455 33 4 Register EE 459 E e E OT 461 35 5 1 MP eonprolmeister cc sscestesccecacusosnestosecenaewsodteasebesecsavacducodvantesacweesseoltanseestesedveoutascsestesndves 461 35 5 2 MP Status register sess aee ete eren ree EVE Heu ii Ee ee ere aeneo aee 461 35 5 3 Input DMA globe control register esent nennen nnne 462 35 5 4 Input DMA start address high 4bits reotster sees 462 35 5 5 Input DMA start address low 32bits register srervnsvnnnrarvrrernnrververvrrervervarvrresnerverversrsesvervene 463 35 5 6 Input DMA line width register ENEE 463 35 5 7 Input DMA memory block size register nennen 464 35 5 8 Input DMA memory block coordinate control register sesssseee 464 35 5 9 Input DMA setting register eerte rrr bre eee E SEENEN e aon aano Ri ia i 465 35 5 10 Input DMA fill color register rsrrrnnnnrnnrnvrrrnnnnnnnrrvvnrnnnnrrnrrvvervesnernrenvernennesneevvennesvasnrevvesnennne 466 35 5 11 Color space converter 0 control register enne ener 467 35 5 12 Color space converter 1 control register essent siaii 468 35 5 13 Scaler control register feed EES FR HER en tabat Edge 469 35 5 14 Scaling output size register ed ENEE 469 35 5 15 Scaler horizontal scaling factor register usrnonrrnrrvvrvnnnnrrnrnnvnrnnrnrrnennvnrnnrnerneervnrnesnesnsevnsvesnee 470 35
435. t tete retener eee e vedo vere reet dee 370 31 6 68 ISP OBC clamp value register ber red ie ai 370 31 6 69 ISP LSC configuration register eerte tot ntn hn inita phe iei NE S haha 370 31 6 70 ISP LSC gain factor address register eese nennen 371 31 6 71 ISP LSC gain factor address length register esee 371 31 0 72 ISP Offset register iari Ido nb S ege RED EXER aE ege denke 371 31 6 735 ISP Gam Bee 371 31 6 74 ISP Dark Frame Enable register eese en rnnt 372 31 6 75 ISP Dark Frame buffer address register essere 372 31 6 76 ISP Dark Frame buffer address length register sese 372 31 6 77 ISP luma DC subtraction value register eese 373 31 6 78 ISP H3A Median filter threshold register essen enne 373 31 6 79 ISP AF window number register essent nente trementes 373 31 6 80 ISPAF window size feglSter onion HH EEG ERTERH RETE EEN Eege ER 374 31 6 81 ISPAF window SEET eegene rer ERE ee REOR UA MEER 374 31 6 82 ISP AF configuration register eee ene erennen sieran 374 31 6 83 ISP AF filter parameter 0 regteter nennen eene enne nnennennenns 375 31 6 84 ISP AF filter parameter 1 register iiid rr pe e d cep rd ES tab rea edda 375 31 6 85 ISP AF filter parameter 2 register ie enin ertet eere EE hei rr EE Ee 375 31 6 86 ISP AWBE window number register essent e eene entren 376 31 6 87 ISP AWBE window size register teen
436. ta UART4_TX 1 OUT UART Serial Bit output UART4_RX 1 IN UART Serial Bit input UARTS TX 1 OUT UART Serial Bit output UART5 RX 1 IN UART Serial Bit input UART6_TX 1 OUT UART Serial Bit output UART6_RX 1 IN UART Serial Bit input UART7_TX 1 OUT UART Serial Bit output UART7_RX 1 IN UART Serial Bit input A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 198 2012 04 09 Ou Allwinner Technology CO Ltd A10 19 IR Interface 19 1 Overview Infrared Interface IR supports CIR MIR and FIR modes The IR includes the following features Compliant with IrDA 1 1 for MIR and FIR Full physical layer implementation Support 0 576 Mbit sec and 1 152 Mbit sec Medium Infrared MIR physical layer protocol Support 4 Mbit sec FIR physical layer protocol defined by IrDA version 1 4 Support CIR for remote control or wireless keyboard Hardware CRC16 for MIR and CRC32 for FIR Dual 16x8 bits FIFO for data transfer Programmable FIFO thresholds Support Interrupt and DMA The IR block diagram is shown below PLL_FIR Interrupt amp DMA Modulator CRC Encoder Register Encoder N Decoder CRC Encoder 16x8 bits TX FIFO 16x8 bits RX FIFO Searcher Demodulator Figure 19 1 IR Block Diagram The MIR packet consists these fields Two b
437. ter ISP FE LSC LEN REG 0X444 ISP LSC gain factor address length register 0X448 ISP FE OFFSET REG OX44C ISP Offset register ISP_FE_GAIN_REG 0X450 ISP Gain Factor register 0X454 0X458 ISP FE DF EN REG 0X45C ISP Dark Frame Enable register ISP_FE_DF_ADDR_REG 0X460 ISP Dark Frame buffer address register ISP_FE_DF_LEN_REG 0X464 ISP Dark Frame buffer address length register 0X468 Reserved ISP FE DC SUB REG 0X46C ISP luma DC subtraction value register A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 2012 04 09 341 Allwinner Technology CO Ltd A10 ISP FE M FIL TH REG 0X470 ISP H3A Median filter threshold register ISP_FE_AF_NUM_REG 0X474 ISP AF window number register ISP_FE_AF_SIZE_REG 0X478 ISP AF window size register ISP FE AF POS REG 0X47C ISP AF window start register ISP FE AF CFG REG 0X480 ISP AF configuration register ISP FE AF PARAO REG 0X484 ISP AF filter parameter 0 register ISP FE AF PARA1 REG 0X488 ISP AF filter parameter 1 register ISP FE AF PARA2 REG 0X48C ISP AF filter parameter 2 register 0X490 0X494 0X498 ISP FE AWBE NUM REG 0X49C ISP AWBE window number register ISP FE AWBE SIZE REG 0X4A0 ISP AWBE window size register ISP FE AWBE POS REG OX4A4 ISP AWBE window start register ISP FE AWBE CFG REG OX4A8 ISP AWBE configuratio
438. ter 0 0x0 AVS_CNT1_EN Audio Video Sync Counter 1 Enable Disable The counter source is OSC24M 0 Disable 1 Enable 0x0 ANS CNTO EN Audio Video Sync Counter 1 Enable Disable The counter source is OSC24M 0 Disable 1 Enable A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 97 2012 04 09 Allwinner Technology CO Ltd A10 10 3 21 AVS Counter 0 Register Default 0x00000000 Offset 0x84 Register Name AVS CNTO REG Bit Read Write Default Description 31 0 R W 0x0 AVS_CNTO Counter 0 for Audio Video Sync Application The high 32 bits of the internal 33 bits counter register The initial value of the internal 33 bits counter register can be set by software The LSB bit of the 33 bits counter register should be zero when the initial value is updated It will count from the initial value The initial value can be updated at any time It can also be paused by setting AVS CNTO PS to 1 When it is paused the counter won t increase 10 3 22 AVS Counter 1 Register Default 0x00000000 Offset 0x88 Register Name AVS CNT1 REG Bit Read Write Default Description 31 0 R W 0x0 AVS CNTI Counter 1 for Audio Video Sync Application The high 32 bits of the internal 33 bits counter register The initial value of the internal 33 bits counter regi
439. ter Name ISP FE AF CFG REG Bit Read Default Description Write Hex EE M a 12 08 R W AF INC AF line increment number INC EEE from 0 to 16 Las AF source mode 0 FV 1 Pixel A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 374 2012 04 09 Ou Allwinner Technology CO Ltd A10 AF_ACC_MODE AF accumulating mode 0 sum mode The accumulation is the sum of every FV or pixel 1 peak mode The accumulation is the sum of the maximum FV or pixel in every line 31 6 83 ISP AF filter parameter 0 register Bit Read Default Description pre NEN 31 24 R W C3 PN rs s t neon 812 23 16 R W C2 PPT rei s te ton ee 15 08 R W C1 TU P re 0 07 00 R W CO PP ee 31 6 84 ISP AF filter parameter 1 register Offset Address 0X488 Register Name ISP FE AF PARA1 REG Bit Read Default Description Write Hex 31 24 R W C7 Filter coeff7 A signed number ranging from 128 127 23 16 R W C6 Filter coeff6 A signed number ranging from 128 127 15 08 R W C5 PPT PEN 07 00 R W C4 PT eee 31 6 85 ISP AF filter parameter 2 register Offset Address 0X48C Register Name ISP FE AF PARA2 REG Read Default Description Write Hex ma 70 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 375 2012 04 09 ON an Allwinner CO Ltd 27 24 Filter right shifter rl ranges from 0
440. ther the timing parameters used by the Macrovision function are like those specified for PAL or those specified for NTSC 0 Macrovision timing parameters are like those of NTSC 1 Macrovision timing parameters are like those of PAL 7 1 0 R W 1 MV disable 34 4 28 TV Encoder MacroVision NO N3 Register Offset 0x204 Register Name TVE_204_REG Bit Read Default Description Write Hex 31 30 29 24 R W 0 MacroVision N3 23 22 16 R W 0 MacroVision N2 15 14 13 8 R W 0 MacroVision N1 7 0 R W 0 MacroVision NO A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 442 2012 04 09 Allwinner Technology CO Ltd A10 34 4 29 TV Encoder MacroVision N4 N7 Register Offset 0x208 Register Name TVE 208 REG Bit Read Default Description Write Hex 31 26 25 24 R W 0 MacroVision N7 23 19 18 16 R W 0 MacroVision N6 15 11 10 8 R W 0 MacroVision N5 7 6 0 R W 0 MacroVision N4 34 4 30 TV Encoder Macro Vision N8 N10 Register Offset 0x20C Register Name TVE_20C_REG Bit Read Default Description Write Hex 31 22 21 16 R W 0 MacroVision N10 15 14 13 8 R W 0 MacroVision NO 7 6 5 0 R W 0 MacroVision NS 34 4 31 TV Encoder MacroVision N11 N12 Register Offset 0
441. tical Others reserved 31 6 63 ISP Horizontal OBC window start register Offset Address 0X420 Register Name ISP_FE_HOB_POS_REG A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 368 2012 04 09 Allwinner Technology CO Ltd A10 27 16 R W HOR OBC VER START The start vertical position for Horizontal OBC window Ranges from 0 to 4095 11 00 R W HOR OBC HOR START The start horizontal position for Horizontal OBC window Ranges from 0 to 4095 31 6 64 ISP Vertical OBC window start register Offset Address 0X424 Register Name ISP_FE_VOB_POS_REG Read Default Description Write Hex ur RS 11 00 R W VER_OBC_HOR_START The start horizontal position for Vertical OBC window Ranges from 0 to 4095 31 6 65 ISP Vertical OBC parameter register Offset Address 0X428 Register Name ISP_FE_VOB_PARA_REG Read Default Description Write Hex malo LS 23 16 R W VER OBC K Coefficient k for vertical OBC Ranges from 0 to 255 VE g 0 07 00 R W VER_OBC_RESET_VAL The reset value of previous line at the every beginning of OB Vertical valid Ranges from 0 to 255 31 6 66 ISP OBC fixed value register Offset Address 0X42C Register Name ISP_FE_OB_FIXED_REG Read Default Description Write Hex ma E me ew Jon A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 369 2012 04 09 Ou Allwinner Technology
442. tion RX CNT RX Sample Counter The audio sample number of writing into RXFIFO When one sample is written by Digital Audio Engine the RX sample counter register increases by one The RX sample counter register can be set to any initial valve at any time After been updated by the initial value the counter register should count on base of this initial value 22 4 13 Digital Audio TX Channel Select register Offset 0x30 Register Name DA TXCHSEL A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 230 2012 04 09 Ou Allwinner Technology CO Ltd A10 Default Value 0x0000_0001 Bit Read Write Default Description 31 3 TX_CHSEL TX Channel Select 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch T ch 8 ch cb Mec SD ce 2 0 R W 1 22 4 14 Digital Audio TX Channel Mapping Register Register Name DA TXCHMAP Offset 0x34 Default Value 0x7654 3210 Bit Read Write Default Description 31 30 28 R W 7 TX CH7 MAP TX Channel7 Mapping 000 1 sample 001 2 sample 010 3 sample 011 4 sample 100 5 sample 101 6 sample 110 7 sample 111 8 sample 27 26 24 R W 6 TX_CH6_MAP TX Channel6 Mapping 000 1 sample 001 2 sample 010 3 sample 011 4 sample 100 5 sample 101 6 sample 110 7 sample 111 8 sample 23 A10 User M
443. tion B Buffer block size Up to 8192 8192 pixels W Support Memory scan order option B Support Clipping E ROP2 Line Rectangle Point Block fill BH ROP3 BitBLT PatBLT StretchBLT BH ROP4 MaskBLT W Rotation 90 180 270 degree M Support Mirror m Alpha blending Plane amp Pixel alpha support Output alpha configurable support M Support Color key B Scaling 4 4 taps 32 phase W Support Color space convert A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 445 2012 04 09 Ou Allwinner Technology CO Ltd A10 35 2 Block Diagram AHB BUS 22 e Scaler 55 SL gt A DMA Controller Output Fmt Data Channel Sorter Figure35 1 MP General Diagram 35 3 MP Description 35 3 1 Data Mode There are 4 input data channel and 3 output data channel in MP the data mixing application will be realized through the input and output data mode of configuration 35 3 2 Rotation and mirroring control Each input DMA channel can be realized rotation and mirror operation function total 8 operation according 8 control code refer to the following diagram A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 446 2012 04 09 Ou Allwinner Technology CO Ltd A10 Control code Normal A X Y Control code AXY AY XY AX 35 3 3 Memory scan order Memory Block Memory Block Memory Bloc
444. tive high while the value of this location is internally looped back to an input 0 R W DTR Data Terminal Ready This is used to directly control the Data Terminal Ready dtr n output The value written to this location is inverted and driven out on dtr n 0 dtr n de asserted logic 1 1 dtr n asserted logic 0 The Data Terminal Ready output is used to inform the modem or data set that the UART is ready to establish communications Note that in Loopback mode MCR 4 set to one the dtr n output is held inactive high while the value of this location is internally looped back to an input 18 4 10 UART Line Status Register Offset 0x14 Register Name UART LSR Default Value 0x0000 0060 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 189 2012 04 09 Ou Allwinner Technology CO Ltd A10 Bit Read Write Default Description 31 8 FIFOERR RX Data Error in FIFO When FIFOs are disabled this bit is always 0 When FIFOs are enabled this bit is set to 1 when there is at least one PE FE or BI in the RX FIFO It is cleared by a read from the LSR register provided there are no subsequent errors in the FIFO TEMT Transmitter Empty If the FIFOs are disabled this bit is set to 1 whenever the TX Holding Register and the TX Shift Register are empty If the FIFOs are enabled this bit is set whene
445. tput data mode and output data ports mapping of Output control register YUV444 to YUV422 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 449 2012 04 09 e Allwinner Technology CO Ltd A10 Enable CSC2 gnore Y component UV component use linear interpolation in x direction UV component ignore y direction Pn 3 Pn 2 Pn 1 Pn ET SEEREN EN r T Input Line n PO Pl P2 PB P4 P5 P6 P7 temen Pn 7 Pn 6 Pn 5 Pn 4 Pn 3 Pn2 Pn 1 Pn AQ 1 I Pn 7 Pn 6 Pn 3 Pn 2 1 Output Line n p bs T lensen pute n B The UV component output formatter rule of YUV444 to YUV422 YUV444 to YUV411 Enable CSC2 gnore Y component UV component use linear interpolation in x direction UV component ignore y direction Input Line n PO PI P2 Pn 6 Pn 5 Pn 4 Pn 3 Pn 2 Pn 1 Pn I Pn 11 Pn 10 Pn 9 Pn 8 4 Ie IS REE A A eR ORE RE 2 Geh P RSC P11 Output Line n Hate PI dE D T d Pn 15 Pn 14 Pn 13 Pn 12 Pn 74Pn 6 Pn 5 Pn 4 14 The UV component output formatter rule of YUV444 to YUV411 YUV444 to YUV420 Enable CSC2 Ignore Y component UV component use linear interpolation in x direction UV c
446. ty 1s invert the specify output 33 4 33 TCONI IO control register Offset 0x0F4 Register Name TCON1 IO TRI REG Bit Read Default Description Write Hex 31 28 27 R W 1 103_Output_Tri_En 1 disable 0 enable 26 R W 1 102_Output_Tri_En 1 disable 0 enable 25 R W 1 101_Output_Tri_En 1 disable 0 enable 24 R W 1 IOO Output Tri En A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 415 2012 04 09 Ou Allwinner Technology CO Ltd 1 disable 0 enable 23 0 R W OxFFFF Data_Output_Tri_En control 1s disable Os enable 33 4 34 TCON ECC FIFO register Offset 0x0F8 Register Name TCON_ECC_FIFO_REG Bit Read Default Description Write Hex 31 R W ECC_FIFO_BIST_EN 0 disable 1 enable 30 R W ECC_FIFO_ERR_FLAG 29 24 23 16 R W ECC_FIFO_ERR_BITS 15 8 7 0 R W ECC_FIFO_SETTING 33 4 35 TCON CEU control register Offset 0x100 Register Name TCON_CEU_CTL_REG Bit Read Default Description Write Hex 31 R W 0 CEU_en 0 bypass 1 enable 30 0 33 4 36 TCON CEU coefficent register Offset 0x110 Register Name TCON_CEU_MUL_RR_REG Bit Read Default Description Write Hex 31 13 12 0 R W 0 Coef_Value signed 13bit value range of 16 16 A10 User Manual V1 20 Copyright
447. ty Levell 0x1 level 1 Level2 0x1 level 2 Level3 0x1 level 3 highest priority 29 28 R W 0x0 IRQ62_PRIO A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 127 2012 04 09 Ou Allwinner Technology CO Ltd A10 Offset 0x8C Register Name INTC_PRIO_REG3 IRQ 62 Priority Set priority level for IRQ bit 62 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 0x1 level 2 Level3 Ox1 level 3 highest priority 27 26 R W 0x0 IRQ61 PRIO IRQ 61 Priority Set priority level for IRQ bit 61 Level 0x0 level 0 lowest priority Levell 0x1 level 1 Level2 Ox1 level 2 Level3 0x1 level 3 highest priority 25 24 R W 0x0 IRQ60_PRIO IRQ 60 Priority Set priority level for IRQ bit 60 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 Ox1 level 2 Level3 Ox1 level 3 highest priority 23 22 R W 0x0 IRQ59_PRIO IRQ 59 Priority Set priority level for IRQ bit 59 Level0 0x0 level 0 lowest priority Levell 0x1 level 1 Level2 Ox1 level 2 Level3 Ox1 level 3 highest priority 21 20 R W 0x0 IRQ58_PRIO IRQ 58 Priority Set priority level for IRQ bit 58 Level0 0x0 level 0 lowest priority Levell Ox1 level 1 Level2 Ox1 level 2 Level3 Ox1 level 3 highest priority 19 18 R W 0x0 IRQ57_PRIO IRQ 57 Priority Set priority level for IRQ bit 57 Level0 0x0 level 0 lowest priority Levell Ox1
448. uent byte transfer At each interrupt the micro processor needs to check the 2WIRE STAT register for current status transfer has to be concluded with STOP condition by setting M STP bit high In Slave Mode the TWI also constantly samples the bus and look for its own slave address during addressing cycles Once a match is found it is addressed and interrupt the CPU host with the corresponding status Upon request the CPU host should read the status read write 2WIRE DATA data register and set the 2 WIRE CNTR control register After each byte transfer a slave device always halt the operation of remote master by holding the next low pulse on SCL line until the microprocessor responds to the status of previous byte transfer or START condition A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 162 2012 04 09 Ou Allwinner Technology CO Ltd A10 17 SPI Interface 17 1 Overview The SPI is the Serial Peripheral Interface which allows rapid data communication with less software interrupts The SPI module contains one 64x8 receiver buffer RXFIFO and one 64x8 transmit buffer TXFIFO It can work at two modes Master mode and Slave mode It includes the following features Full duplex synchronous serial interface Configurable Master Slave SPIO has four chip selects and SPI1 has only one chip select 8x64 FIFO for both transmit and receive data Configurable Polarity and phase of the Chip
449. uration register CSI1 CAP REG 0X008 CSI capture control register CSIL SCALE REG 0X00C CSI scale register CSI1 F0 BUFA REG 0X010 CSI FIFO 0 output buffer A address register CSI1 F0 BUFB REG 0X014 CSI FIFO 0 output buffer B address register CSI1 F1 BUFA REG 0X018 CSI FIFO 1 output buffer A address register CSI1 F1 BUFB REG 0X01C CSI FIFO 1 output buffer B address register CSI1 F2 BUFA REG 0X020 CSI FIFO 2 output buffer A address register CSI1 F2 BUFB REG 0X024 CSI FIFO 2 output buffer B address register CSI1 BUF CTL REG 0X028 CSI output buffer control register CSI1 BUF STA REG 0X02C CSI status register CSI1 INT EN REG 0X030 CSI interrupt enable register CSI1 INT STA REG 0X034 CSI interrupt status register CSI1 HSIZE REG 0X040 CSI horizontal size register CSI1 VSIZE REG 0X044 CSI vertical size register CSI1 BUF LEN REG 0X048 CSI line buffer length register 32 6 CSII Register Description 32 6 1 CSI Enable Register Offset 0x0000 Register Name CSI1 EN REG Bit Read Default Hex Description Write 31 10 9 R W 0 PCLK CNT Pclk count per frame 8 R W 0 LUMA EN Luma enable 7 5 R W 0 NON16_ADD A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 386 2012 04 09 Ou Allwinner Technology CO Ltd A10 Non 16 add 0x00 3 R W 0 RD_FIFO_EN Read fifo 3 fifo enable fifo address 01c09800 01c09ffc 2 R W 0 FIELD_REV Cc
450. urn first is X1 data 26 3 3 TP control Register 2 Offset 0x08 Register Name TP_CNT2 Bit Read Default Description Write Hex 31 28 R W 0x8 TP SENSITIVE ADJUST Internal Pull up Resistor Control 0000 least sensitive 0011 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 275 2012 04 09 Ou Allwinner Technology CO Ltd A10 1111 most sensitive Note Used to adjust sensitivity of pen down detection 27 26 R W 0x0 TP_MODE_SELECT TP Mode Select 00 FIFO store X Y data with Z filter 01 FIFO store X Y AX AY data with Z filter 10 FIFO store X Y X2 Y2 data with Z filter 11 Reserved 25 24 R W 0x0 PRE_MEA_EN TP Pressure Measurement Enable Control 0 Disable 1 Enable 23 0 R W OxFFF PRE_MEA_THRE_CNT TP Pressure Measurement threshold Control Notes 0x000000 least sensitive OxFFFFFF most sensitive Note used to adjust sensitivity of touch 26 4 Median filter Control Register Offset 0x0c Register Name TP CTRL3 Bit Read Write Default Hex Description 31 3 2 R W 0x0 FILTER_EN Filter Enable 0 Disable 1 Enable 1 0 R W 0x1 FILTER_TYPE Filter Type 00 4 2 01 5 3 10 8 4 11 16 8 26 4 1 TP Interrupt amp FIFO Control Register Offset 0x10 Register Name TP INT
451. utput buffer A address register eese 361 31 6 49 CSI Channel 3 FIFO 2 output buffer B address register essen 362 31 6 50 CSI Channel 3 output buffer control register esee 362 31 6 51 CSI Channel 3 status register IEN rer rte eee eee dre rre dvale 362 31 6 52 CSI Channel 3 interrupt enable register essere nennen 363 31 6 53 CSI Channel 3 interrupt status register rosessi eniron edora eaea EE ES ENESTE EEEE SE Ni eai 364 31 6 54 CSI Channel 3 horizontal size register sees eene entere 364 31 6 55 CSI Channel 3 vertical size register essent eene 365 31 6 56 CSI Channel 3 buffer length register eese eene a a 365 Set ISP EIDE reser 365 31 6 58 ISP Mode EE 366 31 6 59 ISP OBC Image Black size register essent eene nennen ener 367 31 6 60 ISP OBC Image Valid size register essen ener enne 367 31 6 61 ISP OBG Image Start register idee terrere or tre NEE EE ed 367 31 6 62 ISP OBC configuration register ssssesseeseeseseeeeeee rennen ener en eene enne enne 368 31 6 63 ISP Horizontal OBC window start register essent 368 31 6 64 ISP Vertical OBC window start register eere en eere 369 31 6 65 ISP Vertical OBC parameter register eene nennen 369 31 6 66 ISP OBC fixed value register soisissa iseken inoan aAa Sna nennen 369 31 6 67 ISP OBC offset TGglstet eti
452. value is the value setup by software If the port is configured as functional pin the undefined value will 23 0 R W 0 be read 30 3 15 PB Multi Driving Register 0 Register Name PB DRVO Offset 0x38 Default Value 0x5555 5555 Bit Read Write Default Description PB DRV PB n Multi Driving Select n 0 15 21 1 21 00 Level 0 01 Level 1 G 0 15 R W Ox1 10 Level 2 11 Level 3 30 3 16 PB Multi Driving Register 1 Register Name PB DRV1 Offset 0x3C Default Value 0x0000_5555 Bit Read Write Default Description 31 16 PB_DRV PB n Multi Driving Select n 16 23 21 1 21 00 Level 0 01 Level 1 120 7 R W Ox1 10 Level 2 11 Level 3 A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 297 2012 04 09 Ou Allwinner Technology CO Ltd A10 30 3 17 PB Pull Register 0 Register Name PB PULLO Offset 0x40 Default Value 0x0000 0000 Bit Read Write Default Description PB PULL PB n Pull up down Select n 0 15 2i 1 2i 00 Pull up down disable 01 Pull up i20 15 R W 0x0 10 Pull down 11 Reserved 30 3 18 PB Pull Register 1 Register Name PB_PULL1 Offset 0x44 Default Value 0x0000_0000 Bit Read Write Default Description 31 16 PB_PULL PB n Pull up down Select n 16 23 2i 1 2i 00 Pull up down disable 01 Pull up enable i 0 7 R W 0x0 10 Pull
453. ve Bottom A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 39 2012 04 09 Ou Allwinner Technology CO Ltd A10 6 4 4 PLL3 Video 0 Default 0x0010D063 Offset 0x10 Register Name PLL3_CFG_REG Bit Read Default Description Write Hex 31 R W 0x0 PLL3_Enable 0 Disable 1 Enable In the integer mode The PLL3 output 3MHz M In the fractional mode the PLL3 output is select by bit 14 The PLL3 output range is 27MHz 381MHz 30 29 27 23 21 15 R W Ox1 PLL3 MODE SEL PLL3 mode select 0 fractional mode 1 integer mode 14 R W Ox1 PLL3 FUNC SET PLL3 fractional setting 0 270MHz 1 297MHz 13 7 6 0 R W 0x63 PLL3_FACTOR_M PLL3 Factor M The range is from 9 to 127 6 4 5 PLL4 VE Default 0x21081000 Offset 0x18 Register Name PLL4 CFG REG Bit Read Default Description Write Hex 31 R W 0x0 PLL4_Enable 0 Disable 1 Enable The PLL4 output 24MHz N K M P The PLL4 output is for the VE Note the output 24MHz N K clock must be in the range of 240MHz 2GHz if the bypass is disabled 30 R W 0x0 PLLA OUT BYPASS EN PLLA Output Bypass Enable 0 Disable 1 Enable If the bypass is enabled the PLL4 output is 24MHz 18 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 40 2012 04 09 Ou Allwinner
454. ved 143 2012 04 09 Ou Allwinner Technology CO Ltd A10 10100 10101 SRAM range 10110 SDRAM 10111 TP A D 11000 SPIO RX 11001 SPI RX 11010 SPR RX 11011 SPI3 RX others reserved 12 3 5 Normal DMA Source Address Register Default 0x00000000 Offset Register Name NDMA SRC ADDR REG 0x100 N 0x20 0x4 N 0 1 2 3 4 5 6 7 Bit Read Default Description Write Hex 31 0 R W 0x0 NDMA SRC ADDR Normal DMA Source Address 12 3 6 Normal DMA Destination Address Register Default 0x00000000 Offset Register Name NDMA DEST ADDR REG 0x100 N 0x20 0x8 N 0 1 2 3 4 5 6 7 Bit Read Default Description Write Hex 31 0 R W 0x0 NDMA DEST ADDR Normal DMA Destination Address 12 3 7 Normal DMA Byte Counter Register Default 0x00000000 Offset Register Name NDMA BC REG 0x100 N 0x20 0xC N 0 1 2 3 4 5 6 7 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 144 2012 04 09 Ou Allwinner Technology CO Ltd A10 Bit Read Default Description Write Hex 31 24 23 0 R W 0x0 NDMA BC Normal DMA Byte Counter Note If ByteCounter 0 DMA will transfer no byte The maximum value is 128k 12 3 8 Dedicated DMA Configuration Register Default 0x00000000 Offset 0x300 N 0x20 N 0 1 2 3 4 5 6 7 Register Name DDM
455. ved 288 Ou Allwinner Technology CO Ltd A10 000 Input 001 Output 010 ETXD3 011 SPH_CS1 100 Reserved 101 Reserved 110 Reserved 111 Reserved 15 PA3_SELECT 000 Input 001 Output 010 ERXDO 011 SPI1 MISO 100 UART2 RX 101 Reserved 14 12 R W 0 110 Reserved 111 Reserved 11 PA2 SELECT 000 Input 001 Output 010 ERXDI 011 SPI1 MOSI 100 UART2 TX 101 Reserved 10 8 R W 0 110 Reserved 111 Reserved 7 DAT SELECT 000 Input 001 Output 010 ERXD2 011 SPI1 CLK 100 UART2 CTS 101 Reserved 6 4 R W 0 110 Reserved 111 Reserved Reserved PAO SELECT 000 Input 001 Output 010 ERXD3 011 SPI1_CSO 100 UART2 RTS 101 Reserved 2 0 R W 0 110 Reserved 111 Reserved 30 3 2 PA Configure Register 1 Register Name PA_CFG1 Offset 0x04 Default Value 0x0000_0000 Bit Read Write Default Description 31 PA15 SELECT 000 Input 001 Output 010 ECRS 011 UART7 RX 100 UARTI DSR 101 Reserved 30 28 R W 0 110 Reserved 111 Reserved 27 26 24 R W 0 PA14_SELECT A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 289 2012 04 09 Ou Allwinner Technology CO Ltd A10 000 Input 001 Output 010 ETXCK 011 UART7_TX 100 UART1_DTR 101 Reserved 110 Reserved 111 Reserved 23 PA13 SELECT 000 Input 001 Output 010 ETXEN 011 UART6
456. ved 327 2012 04 09 Ou Allwinner Technology CO Ltd A10 110 EINT24 111 Reserved 15 PI11 SELECT 000 Input 001 Output 010 SPIO_CLK 011 UARTS RX 100 Reserved 101 Reserved 14 12 R W 0 110 EINT23 111 Reserved 11 PI10 SELECT 000 Input 001 Output 010 SPIO_CSO 011 UART5 TX 100 Reserved 101 Reserved 10 8 R W 0 110 EINT22 111 Reserved 7 PI9 SELECT 000 Input 001 Output 010 SDC3 Di 011 Reserved 100 Reserved 101 Reserved 6 4 R W 0 110 Reserved 111 Reserved 3 PI8 SELECT 000 Input 001 Output 010 SDC3 D2 011 Reserved 100 Reserved 101 Reserved 2 0 R W 0 110 Reserved 111 Reserved 30 3 75 PI Configure Register 2 Register Name PI CFG2 Offset 0x128 Default Value 0x0000 0000 Bit Read Write Default Description 31 24 23 PI21 SELECT 000 Input 001 Output 010 PS2 SDAO 011 UART7 RX 100 HSDA 101 Reserved 22 20 R W 0 110 Reserved 111 Reserved 19 PI20 SELECT 000 Input 001 Output 18 16 R W 0 010 PS2 SCKO 011 UART7 TX A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 328 2012 04 09 Ou Allwinner Technology CO Ltd A10 100 HSCL 101 Reserved 110 Reserved 111 Reserved 15 PI19_SELECT 000 Input 001 Output 010 SPI1_MISO 011 UART2 RX 100 Reserved 101 Reserved 14 12 R W 0
457. ved in master or slave mode If A_ACK is cleared to 0 in slave transmitter mode the byte in the DATA register is assumed to be the last byte After this byte has been transmitted the TWI will enter state C8h then return to the idle state status code F8h when INT_FLAG is cleared 2 R W 0 The TWI will not respond as a slave unless A_ACK is set 1 0 R W 0 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 157 2012 04 09 Allwinner Technology CO Ltd A10 16 4 5 TWI Status Register Register Name TWI STAT Offset 0x10 Default Value 0x0000_00F8 Bit Read Write Default Description 31 8 STA Status Information Byte Code Status 0x00 Bus error 0x08 START condition transmitted 0x10 Repeated START condition transmitted 0x18 Address Write bit transmitted ACK received 0x20 Address Write bit transmitted ACK not received 0x28 Data byte transmitted in master mode ACK received 0x30 Data byte transmitted in master mode ACK not received 0x38 Arbitration lost in address or data byte 0x40 Address Read bit transmitted ACK received 0x48 Address Read bit transmitted ACK not received 0x50 Data byte received in master mode ACK transmitted 0x58 Data byte received in master mode not ACK transmitted 0x60 Slave address Write bit received ACK transmitted 0x68 Arbitration lost in address as master slave a
458. ver the TX FIFO and the TX Shift Register are empty In both cases this bit is cleared when a byte is written to the TX data channel THRE TX Holding Register Empty If the FIFOs are disabled this bit is set to 1 whenever the TX Holding Register is empty and ready to accept new data and it is cleared when the CPU writes to the TX Holding Register If the FIFOs are enabled this bit is set to 1 whenever the TX FIFO is empty and it is cleared when at least one byte is written to the TX FIFO R BI Break Interrupt This is used to indicate the detection of a break sequence on the serial input data If in UART mode SIR MODE Disabled it is set whenever the serial input sin is held in a logic 0 state for longer than the sum of start time data bits parity stop bits If in infrared mode SIR MODE Enabled it is set whenever the serial input sir_in is continuously pulsed to logic 0 for longer than the sum of start time data bits parity stop bits A break condition on serial input causes one and only one character consisting of all zeros to be received by the UART In the FIFO mode the character associated with the break condition is carried through the FIFO and is revealed when the character is at the top of the FIFO A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 190 2012 04 09 Ou Allwinner Technology CO Ltd A10 Reading th
459. x0 CLK_DIV_RATIO_M Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 16 A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 63 2012 04 09 Allwinner Technology CO Ltd A10 6 4 40 DE BE 1 Clock Default 0x00000000 Offset 0x108 Register Name BE1 CLK REG Bit Read Default Description Write Hex 31 R W 0x0 SCLK GATING Gating Special Clock 0 Clock is OFF 1 Clock is ON This special clock 2 Clock Source Divider M 30 R W 0x0 BEI RST DE BEI Reset 0 reset valid 1 reset invalid 29 26 25 24 R W 0x0 CLK SRC SEL Clock Source Select 00 PLL3 01 PLL7 10 PLL5 11 23 18 17 16 15 4 3 0 R W 0x0 CLK DIV RATIO M Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 16 6 4 41 DE FE 0 Clock Default 0x00000000 Offset 0x10C Register Name FE0 CLK REG Bit Read Default Description Write Hex 31 R W 0x0 SCLK_GATING Gating Special Clock 0 Clock is OFF 1 Clock is ON This special clock Clock Source Divider M 30 R W 0x0 FE0_RST DE FEO Reset 0 reset valid 1 reset invalid A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 64 2012 04 09 Ou Allwinner Technology CO Ltd A10 29 26 25 24 R W
460. x210 Register Name TVE 210 REG Bit Read Default Description Write Hex 31 30 16 R W 0 MacroVision N12 15 14 0 R W 0 MacroVision N11 34 4 32 TV Encoder MacroVision N13 N16 Register Offset 0x214 Register Name TVE 214 REG A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 443 2012 04 09 Ou Allwinner Technology CO Ltd A10 Bit Read Default Description Write Hex 31 25 24 R W 0 MacroVision N16 23 16 R W 0 MacroVision N15 15 8 R W 0 MacroVision N14 7 0 R W 0 MacroVision N13 34 4 33 TV Encoder MacroVision N17 N20 Register Offset 0x218 Register Name TVE_218_REG Bit Read Default Description Write Hex 31 27 26 24 R W 0 MacroVision N7 23 20 19 16 R W 0 MacroVision N6 15 12 11 8 R W 0 MacroVision N5 T 4 3 0 R W 0 MacroVision N4 A10 User Manual V1 20 Copyright O 2011 2012 Allwinner Technology All Rights Reserved 444 2012 04 09 Ou Allwinner Technology CO Ltd A10 35 Mixer Processor MP 35 1 Overview MP is a 2D graphics engine of high performance and 2D image can be widely customized due to its high flexibility in configuration B Support Color format ARGB 8888 4444 1555 RGB565 MONO 1 2 4 8 bpp Palette 1 2 4 8 bpp input only 22 420 M Any format convert func
461. y 1 Single mode When interval value reached the timer will disable A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 95 2012 04 09 Ou Allwinner Technology CO Ltd A10 automatically 6 4 R W 0x0 TMR5 CLK PRES Select the pre scale of timer 5 clock source 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 3 2 R W Ox1 TMR5 CLK SRC Timer 5 Clock Source 00 Low speed OSC 01 OSC24M 10 External CLKIN1 11 1 R W 0x0 TMR5_RELOAD Timer 5 Reload 0 No effect 1 Reload timer 0 Interval value 0 R W 0x0 TMR5_EN Timer 5 Enable 0 Stop Pause 1 Start If the timer is started it will reload the interval value to internal register and the current counter will count from interval value to 0 If the current counter does not reach the zero the timer enable bit is set to 0 the current value counter will pause At least wait for 2 Tcylces the start bit can be set to 1 In timer pause state the interval value register can be modified If the timer is started again and the Software hope the current value register to down count from the new interval value the reload bit and the enable bit should be set to 1 at the same time Note 1 if the clock source is External CLKIN the interval value register is not used the current value register is an up counter that counting from 0 2 the time
462. y full 0 Receive FIFO not full 1 Receive FIFO Full This bit is cleared when the RX FIFO is no longer 4 R 0 full RENE Receive FIFO Not Empty This is used to indicate that the receive FIFO contains one or more entries 0 Receive FIFO is empty 1 Receive FIFO is not empty 3 R 0 This bit is cleared when the RX FIFO is empty TFE Transmit FIFO Empty This is used to indicate that the transmit FIFO is completely empty 0 Transmit FIFO is not empty 1 Transmit FIFO is empty This bit is cleared when the TX FIFO is no longer 2 R 1 empty TFNF Transmit FIFO Not Full This is used to indicate that the transmit FIFO in not full 0 Transmit FIFO is full 1 Transmit FIFO is not full 1 R 1 This bit is cleared when the TX FIFO is full BUSY UART Busy Bit 0 Idle or inactive 0 R 0 1 Busy A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 195 2012 04 09 N Allwinner Technology CO Ltd A10 18 4 14 UART Transmit FIFO Level Register Register Name UART TFL Offset 0x80 Default Value 0x0000 0000 Bit Read Write Default Description 31 7 TFL Transmit FIFO Level This is indicates the number of data entries in the 6 0 R 0 transmit FIFO 18 4 15 UART Receive FIFO Level Register Register Name UART_RFL Offset 0x84 Default Value 0x0000_0000 Bit Read Write Default Description 31
463. yright O 2011 2012 Allwinner Technology All Rights Reserved 50 2012 04 09 Allwinner Technology CO Ltd A10 6 4 20 NAND Clock Default 0x00000000 Offset 0x80 Register Name NAND SCLK CFG REG Bit Read Default Description Write Hex 31 R W 0x0 SCLK_GATING Gating Special Clock Max Clock 200MHz 0 Clock is OFF 1 Clock is ON This special clock Clock Source Divider N Divider M 30 26 25 24 R W 0x0 CLK_SRC_SEL Clock Source Select 00 OSC24M 01 PLL6 10 PLLS 11 23 18 17 16 R W 0x0 CLK_DIV_RATIO_N Clock pre divide ratio n The select clock source is pre divided by 2 n The divider is 1 2 4 8 15 4 3 0 R W 0x0 CLK_DIV_RATIO_M Clock divide ratio m The pre divided clock is divided by m 1 The divider is from 1 to 16 Note In application the module clock frequency always switches off 6 4 21 SD MMC 0 Clock Default 0x00000000 Offset 0x88 Register Name SD0_CLK_REG Bit Read Default Description Write Hex 31 R W 0x0 SCLK GATING Gating Special Clock Max Clock 200MHz 0 Clock is OFF 1 Clock is ON This special clock Clock Source Divider N Divider M 30 26 25 24 R W 0x0 CLK SRC SEL A10 User Manual V1 20 Copyright 2011 2012 Allwinner Technology All Rights Reserved 51 2012 04 09 Ou Allwinner Technology CO Ltd A10 Clock Source Select 00 OSC24M 01 PLL6 10 PLL5
464. ys low 1 b1 The interrupt line will go high when INT FLAG is set BUS EN 2 Wire Bus Enable 1 b0 The 2 Wire bus inputs ISDA ISCL are ignored and the 2 Wire Controller will not respond to any address on the bus 1 bl The TWI will respond to calls to its slave address and to the general call address if the GCE bit in the ADDR register is set Notes In master operation mode this bit should be set to q M_STA Master Mode Start When M STA is set to 1 TWI Controller enters master mode and will transmit a START condition on the bus when the bus is free If the M STA bit is set to 1 when the 2 Wire Controller is already in master mode and one or more bytes have been transmitted then a repeated START condition will be sent If the M_STA bit is set to 1 when the TWI is being accessed in slave mode the TWI will complete the data transfer in slave mode then enter master mode when the bus has been released The M_STA bit is cleared automatically after a START condition has been sent writing a 0 to this bit has no effect R W M_STP Master Mode Stop If M_STP is set to 1 in master mode a STOP condition is transmitted on the 2 Wire bus If the M_STP bit is set to 1 in slave mode the TWI will behave as if a STOP condition has been received but no STOP condition will be transmitted on the 2 Wire bus If both M_STA and M_STP bits are set the TWI will first transm

A10 User manual V1.20 20120409

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