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Lightning DSPC-8681E Quad-TMS320C6678 DSP PCI

1. 13 TABLE 3 CLOCK DOMAINS T 16 TABLE 4 PCI E PORT MAPPING ON 8624 20 TABLES PCI E SWITCH LED T 25 TABLES FPGA LED 26 TABLE7 1 ASSIGNMENT T 28 TABLE8 CN2 DSP EMULATOR PIN ASSIGNMENTS 30 TABLE9 CN3 PIN ASSIGNMENT u 31 TABLE10 CN4 PIN ASSIGNMEN 32 TABLE11 CN5 PIN ASSIGNMEN 33 TABLE12 CN6 PIN ASSIGNMENT sssesesesesesesssesessssesesescsessssscsssesesscscesscsescssscsesssssesenes 34 TABLE13 1 PIN ASSIGNMEN TT 34 14 560V2_PWR1 PIN 5 37 TABLE15 THE SW1 SETTING TABII 37 Page 6 of 39 Trusted ePlatform Services ADNANTECH Advantech Confidential 1 General 1 1 General Introduction This document is the H W user manual of DSPC 8681E the PCI E x8 Half Length add on card with quad TMS320C6678 DSPs DSPC 8681E is composed of four TMS320C6678 DSPs one PCI E GEN2 switch P
2. CDCLVD1208 SerDes_CLK TI gt m CDCLVD1208 1 0V E MCM_CLK Regulator 3 3V Regulator 2 5V Regulator PLX 8624 CDCE62005 91 guaa9rx guaa9rx 91 2 91 9 IDT ICS9DB801 14444444 leg PCIE CLK Figure12 LAN interconnection 2 13 HyperLink interface Another high speed interlink named HyperLink is implemented on DSPC 8681E to connect each two DSPs DSP 1 and DSP 2 DSP 3 as pair and its interface can provide 50 5 12 5GT s per lane for data transactions This HyperLink interface on the TMS320C6678 is used to exchange data between two DSPs with low latency for the specific process accelerations on DSPC 8681E PCIE card There are four lane SerDes interface designed to operate up to 12 5Gbps per lane The links of the HyperLink bus on DSPC 8681E are connected of the DSPHO and the DSP 1 as well as the DSP 2 and DSP 3 Below figure describes the Hyperlink connection on DSPC 8681E Page 22 of 39 Trusted ePlatform Services ADNANTECH Advantech Confidential Broadcom BCM5461S Xilinx XC3S200AN Drs e e 104 Drs e e Regulator 15V Regulator 0 75 Regulator 1 8V Regulator 1 0V
3. Figure1 DSPC 8681E System Block Diagram Page 9 of 39 Trusted ePlatform Services ADNANTECH Advantech Confidential 1 4 DSPC 8681E PCI E card Placement Below figure shows main components on DSPC 8681E It s only for reference if user needs to learn specific DSP or want to find a key chip on the card during developing Tras TI 5320 6678 2 DSPC 8681E PCI E card Placement Page 10 of 39 Trusted ePlatform Services ADNANTECH Advantech Confidential 2 Hardware Specification 2 1 Power Feed The power source of DSPC 8681E is provided by two power rails 12V and 3 3V from host via PCI Ex 8 golden fingers 2 2 Power Distribution The major power on DSPC 8681E is illustrated as below Figure Figure8 shows the power rails and the chips requirements on the DSPC 8681E User could refer to DSPC 8681E schematics for more details regarding the power supplies on DSPC 8681E SmartRe flex UCD9244 YT237 gt 10 20 00888 VT235 n 1 5 VV_GP 0 1 4010 8A Figure3 Power Distribution Block Diagram 23 Power Budget Page 11 of 39 Trusted ePlatform Services ADNANTECH Advantech Confidential The estimated operational power budget of DSPC 8681E is about 52 751W This value is estimated based on the assumption of the power dissipations and utilizations of the key components For detailed num
4. 18 FIGURE9 TI TMS320C6678 BLOCK DIAGRAMN 19 FIGURE10 SERIAL RAPIDIO RING 20 FIGURE11 PCIE INTERCONNECTION 21 FIGURE12 LAN INTERCONNECTION 22 FIGURE13 HYPERLINK CONNECTION 23 FIGURE14 FPGA CONNECTION 24 FIGURE15 TOP SIDE LED LOCATION 24 FIGURE16 BOTTOM SIDE LED LOCATION 25 FIGURE17 CONNECTOR OVERVIEMW 27 FIGURE18 THE FPGA JTAG FOR FIRMWARE UPDATE 28 FIGURE19 2 TI 60 PIN EMULATION CONNECTOR 29 FIGURE20 CONNECTION THE XDS560V2 STM EMULATOR 29 FIGURE21 60 PIN HEADER ORIENTATION 29 FIGURE22 THE CONNECTION WITH TI XDS560V2 STM EMULATOR 30 FIGURE
5. 91 g uqa9rx 91 y dd 91x 9 9 9 PCle x8 Figure10 Serial RapidlO Ring Advantech Confidential Broadcom BCM5461S CDCLVD1208 DDR3 CLK TI CDCLVD1208 Core_CLK TI E CDCLVD1208 PASS CLK TI CDCLVD1208 SerDes_CLK H TI CDCLVD1208 CLK TI CDCE62005 IDT ICS9DB801 PCIE CLK GbE DSPC 8681E adopts a star topology to link host platform with two lane PCIE interface via a PCI E GEN2 switch PEX8624 One PCI E Gen2 port is designed with two Lanes Supports Up To 5G baud Per Lane connected to each DSP With PEX8624 it can support up to six PCI Express GEN ports with 24 lanes of integrated on chip SerDes and provide an aggregated bandwidth of up to 240 GT s Below table describes the port mapping of PEX8624 on DSPC 8681E while below figure describes the PCle interconnection on DSPC 8681E Port Function Connects to Host computer Root Complex by PCI E X8 Connects to DSPO through PCI E X2 interface Connects to DSP1 through PCI E X2 interface Connects to DSP2 through PCI E X2 interface OO Connects to DSP3 through PCI E X2 interface Table 4 PCI E port mapping on PEX8624 Page 20 of 39 Trusted ePlatform Services ADNANTECH Advantech Confidential Broadcom GbE BCM5461S Xilinx XC3S200AN exaagLx exaagix exaagix ex
6. 100 00MHz IDT_ICS9DB803DFLFT U31 DSP1 U2 DSP2_PCIE_REF_CLKP DSP2_PCIE_REF_CLKN 100 00MHz IDT_ICS9DB803DFLFT U31 DSP2 U3 DSP3_PCIE_REF_CLKP DSP3_PCIE_REF_CLKN 100 00MHz IDT_ICS9DB803DFLFT U31 DSP3 U4 DSPO_MCM_CLKP DSPO_MCM_CLKN 250 00MHz CDCLIVD110ARHBR U16 DSPO U1 DSP1_MCM_CLKP DSP1_MCM_CLKN 250 00MHz TI CDCLVD110ARHBR U16 DSP1 02 DSP2 MCM CLKP DSP2 250 00MHz TI_CDCLVD110ARHBR U16 Page 15 of 39 DSP2 U3 Trusted ePlatform Services AD ANTECH Advantech Confidential Signal Frequency Source Device DSP3 TI CDCLVD110ARHBR DSP3 CLKN U 54616 XTALO BCM54616SCOKFBG 54616 XTALI 25 00MHz Crystal 058 XILINX XC35200AN U21 PCIE e PCI E Gold Finger ICS9DB803DFLFT PCIE REF CLK GF1 U31 DSP3 U4 MAIN_48MHZ_CLK_R 48 00MHz Oscillator Table 3 Clock Domains X TAL Shannon DSP 0 3 25Mhz 250Mhz Diff DSPn CLKP N MCM CLKP N 62005 5 5 CLK Gen TI CDCLVD110A 1 10 LVDS Clock Buffer DSPn SRIOSGMII CLKP N sgro scMI CLKP N Control 62005_CLK_SSP_CSO 166 67Mhz Diff 62005_CLK_SSP_CLK Control 62005 CLK SSP MOSI 62005 55 5 100Mhz Diff TI CDCLVD110A DSPn DDR CLKP N 1 10 LVDS DDR_CLKP N EN3 Clock Buffer Control CORE
7. Page 14 of 39 Trusted ePlatform Services ADNANTECH Advantech Confidential The platform clock distribution scheme is illustrated as the below Figure Figure11 DSPC 8681E Carrier Clock Feeding Diagram Signal Frequency Source Device DSPO DDR CLKP DSPO DDR CLKN 166 67MHz CDCLIVD110ARHBR U18 DSPO U1 DSP1 DDR CLKP DSP1 DDR CLKN 166 67MHz CDCLVD110ARHBR U18 DSP1 U2 DSP2_DDR_CLKP DSP2_DDR_CLKN 166 67MHz TI_CDCLVD110ARHBR U18 DSP2 U3 DSP3_DDR_CLKP DSP3_DDR_CLKN 166 67MHz TI CDCLVD110ARHBR U18 DSP3 U4 DSPO CORE CLKP DSPO CORE CLKN 100 00MHz CDCLVD110ARHBR U13 DSPO U1 DSP1_CORE_CLKP DSP1_CORE_CLKN 100 00MHz TI_CDCLVD110ARHBR U13 DSP1 U2 DSP2_CORE_CLKP DSP2_CORE_CLKN 100 00MHz TI CDCLVD110ARHBR U13 DSP2 U3 DSP3 CORE CLKP DSP3 CORE CLKN 100 00MHz CDCLVD110ARHBR U13 DSP3 04 DSPO SRIOSGMII CLKP DSPO SRIOSGMII CLKN 250 00MHz CDCLVD110ARHBR U16 DSPO U1 DSP1_SRIOSGMII_CLKP DSP1_SRIOSGMII_CLKN 250 00MHz TI_CDCLVD110ARHBR U16 DSP1 U2 DSP2_SRIOSGMII_CLKP DSP2_SRIOSGMII_CLKN 250 00MHz TI CDCLVD110ARHBR U16 DSP2 U3 DSP3 SRIOSGMII CLKP DSP3_SRIOSGMII_CLKN 250 00MHz TI CDCLVD110ARHBR U16 DSP3 U4 DSPO PCIE CLKP DSPO PCIE CLKN 100 00MHz IDT_ICS9DB803DFLFT U31 DSPO U1 DSP1_PCIE_REF_CLKP DSP1_PCIE_REF_CLKN
8. POWER DISTRIBUTION 5 2500 606 11 22 RPOWER BUDGET kaspa tu aan a 11 24 POWER SEQUENGE wayaqata 13 2 5 PLATFORM CLOCK R R 14 2 6 BLOCK DIAGRAM a e 17 2 7 RESET SEQUENCE 18 2 8 DSP TI TMS320C6678 BLOCK DIAGRAM 19 2 9 MEMORY DDR3 E 19 2 IO SRIO INITRA CQ huu a 19 2 11 EE 20 LMPI3ITT dune 21 2 13 PIYPERLINKCINTERFPACE 1 uu RR 22 2 14 5200 naa veseussasaas sasbdedanpevesndasataaesesssvadsancepdecuasasaasssasdadasoevesseass 23 sai 24 3e 4950 u 27 3 1 CONNECTOR OVERVIEW EE 27 3 2 XILINX XC3S200AN JTAG INTERFACE a a 28 3 3 60 PINS DSP EMULATOR a r 29 3 4 5320 6678 BOUNDARY SCAN CONNECTOR 31
9. VCCAUX and VCCO supplies to the FPGA be applied in any order The rising time of VCCINT VCCAUX and VCCO is 0 2ms to 100ms When power on 5ms lt t lt 200 5 There is no specific power up nor power down sequence between VDD10 VDD10A and VDD25 VDD25A It does not have any specific power sequencing requirements 3 3V first then 2 5V and then 1 2V is recommended CVDD VCC1PO gt DVDD1P8 gt VCC1P5 XC3S200AN 1 2V VCCINT 3 3V 1 8 XC3S200AN SHANNON DSP 0 3 1 0V core 1 0V Fix 13V 0 75V SHANNON PEX8624 1 0V VDD10 V DD10A 8624 2 BVILVDD25 DD2SA BCM54616S YS DDBIASvppXTALvpp 546165 1 2V DV DD AVDD PLLVDD Figure 5 Power Distribution on DSPC 8681E Card 2 5 Platform Clock The DSPC 8681E clocks are generated by the clock synthesizers crystals and oscillators Introductions for each clock are described as below CDCE62005 It s a Low Jitter clock generator with 25 0MHz crystal It s programmed to provide 166 66MHZ 250MHZ and 100MHz with LVDS level for the DSP reference clocks ICS9D803D It s a PCI E GEN2 clock buffer and provides five reference clocks to the PCI E switch by HCSL and to the DSP PCI E clocks by LVDS level CDCLVD110A It s a 1 10 LVDS clock buffer There are three clock buffers whic fan out 166 66MHZ 250MHZ and 100MHz to each DSP for the reference clocks of core DDR3 HyperLink and SRIO SGMII interfaces
10. CLKP N TI CDCLVD110A DSPn CORE CLKP N 1 10 LVDS Clock Buffer Control DSP0_PCIE REF CLKP N 3 3 5 MAN PCIE REF CLKP N OSC 48Mhz E gt XC3S200AN DSP2_PCIE_REF_CLKP N FPGA DSP3_PCIE_REF_CLKP N ICS9DB803DFLFT PEX8624_REF_CLKP N 100Mhz Diff 25Mhz 3 546165 DSPC 8681E Clock Feeding Diagram PCIE_REF_CLK_P N Page 16 of 39 Trusted ePlatform Services AD ANTECH Advantech Confidential 2 6 Reset Block Diagram DSPC 8681E reset mechanism is shown in Figure 12 DSPC 8681E Reset Block Diagram with below description of the reset sequence on DSPC 8681E The FPGA on the card will do the power on sequence and make all power rails on the card be ready The FPGA waits for the PWROK on PCI E golden finger PCIE_GF_RST asserted After PCI E PWROK asserted as well as all the power on the card valid the FPGA will de assert SYS_RESETz of PEX8624 the PCI E switch PHY_RESETz of BCM54616s the PHY chip and DSP 0 3 RESET on four DSP chips To wait for 5mS the FPGA de assert the DSP_POR to four DSPs To wait for 5mS the FPAG de assert the DSP RESETFULLz to four DSPs During 5 RESETFULLz de asserted the DSP straps the boot configurations on its own GPIO pins driven by the FPAG 1ms later after DSP RESETFULLz de asserted the FPGA will set the GPIO pins on the FPGA side at input after that the reset sequence on DSPC 86
11. Regulator 3 3V Regulator o PLX PEX8624 25V Regulator 9 Drz e e 124 rz e e 24 9 prz e e 124 1 2V Regulator PCle x8 PCle_CLK Figure13 Hyperlink connection 2 14 XC3S200AN For FPGA design Xilinx XC3S200AN is implemented on DSPC 8681E for the power control DSP boot configurations programming clock generators and clock buffers and reset events for DPS farm With the programmed FPGA on DSPC 8681E below functions are provided DSP boot mode setting Power sequences control Enabling Disabling the device power to meet the power sequence requirement Reset methodology control Asserting De asserting RESET signals to each chip respectively Configure the clock generator Other control functions Below figure describes the FPGA connection on DSPC 8681E Page 23 of 39 Trusted ePlatform Services AD ANTECH Advantech Confidential Broadcom GbE 54615 Xilinx XC3S200AN UCD9244 EF TI 07242 91 g guqaqa9x Haderx 91 9 9 5 g guaqa9rx CDCLVD1208 DDR3 CLK 1 0V Regulator TI CDCLVD1208 Regulator 0 75V CDCLVD1208 Regulator PASS_CLK 1 8V Regulator Ti CDCLVD1208 SerDes_CLK TI CDCLVD1208 1 0V MCM CLK Regulator E R
12. edge of board Towards cable entry DSP Figure21 60 pin Header Orientation Page 29 of 39 Trusted ePlatform Services ADNANTECH Advantech Confidential Figure22 The connection with TI XDS560v2 STM Emulator Col Row B 1 GND GND GND NC 2 GND TMS EMU18 GND 3 GND EMU17 TRST GND 4 GND TDI EMU16 GND 5 GND EMU14 EMU15 GND 6 GND EMU12 EMU13 GND 7 GND TDO EMU11 GND 8 Reserve TVD TCLKRTN GND 9 GND EMU9 EMU10 GND 10 GND EMU7 EMU8 GND 11 GND 5 EMU6 GND 12 GND TCLK EMU4 GND 13 GND EMU2 EMU3 GND 14 GND EMU0 EMU1 GND 15 TGRST GND GND GND Table8 CN2 DSP Emulator Pin Assignments Page 30 of 39 Trusted ePlatform Services ADNANTECH Advantech Confidential 3 4 TMS320C6678 Boundary Scan Connector In this paragraph we introduce the boundary scan connector from the TMS320C6678 DSP CN3 TMS320C6678 boundary scan connector 600 CONN40 0 TMS JTAG SW CTRL 80 18 CONN40_TDO 60 CONN40 TDI 60 CONN40_TRSTN Figure23 CN3 the Boundary Scan for the DSP farm i 1 TCK 2 PLUG DETn 3 TMS 4 NC 5 TDO 6 GND 7 TDI 8 GND 9 TRSTn 10 GND Table9 CN3 Pin Assignment Page 31 of 39 Trusted ePlatform Services ADNANTECH Advantech Confidential 3 5 8624 BCM54616S boundary scan connector In this paragraph we introduce the bo
13. others reserved for future use The default setting of the switch SW1 DSPC 8681E is 0x0011b bit 4 1 ON ON OFF OFF for little endian data format and EEPROM boot from 0x51h Page 37 of 39 Trusted ePlatform Services ADNANTECH Advantech Confidential Mechanical Drawing 5 PM 98 16 7 101 80 35 10 4 4 y P SSSSSS SIS 85 40 8 094 4095 9289295080805950 Page 38 of 39 JS D Q a Figure31 DSPC 8681E TOP side Figure32 DSPC 8681E Front Side Trusted ePlatform Services ADNANTECH Advantech Confidential Figure 33 DSPC 8861E Bottom Side Page 39 of 39
14. 23 CN3 THE BOUNDARY SCAN FOR THE DSP FARM 31 FIGURE24 4 BOUNDARY SCAN FOR 8624 AND 546165 32 FIGURE25 5 RJ45 LAN PORT 33 FIGURE26 CN6 FAN CONNECTOR 34 Page 4 of 39 Trusted ePlatform Services AD ANTECH Advantech Confidential FIGURE27 COMI UART PIN OUI 34 FIGURE28 560V2_PWR1 CONNECTOR 36 FIGURE29 THE SW1 ON DSPC 8681E PCIE CARD 36 FIGURESO THE SW1 SCHEIVIATIG 36 FIGURE31 DSPC 8681E TOP SIDE 38 FIGURE32 DSPC 8681E FRONT SIDE 38 FIGURE33 DSPC 8861E BOTTOM SIDE 39 Page 5 of 39 Trusted ePlatform Services ADNANTECH Advantech Confidential Table TABLE 1 DSPC 8681E POWER BUDGEIT aa 12 TABLE 2 SYSTEM POWER SEQUENCE PARAMETFER
15. 3 5 PEX8624 AND 546165 BOUNDARY SCAN CONNECTOR 1 ns 32 3 6 RI45 CONNECTOR sis qi 33 2 7 h 33 2 8 UART CONNECTOR Sasa 34 JUMPER AND SWITCH SETTING 36 MECHANICAL DRAWING 38 Page 3 of 39 Trusted ePlatform Services ADNANTECH Advantech Confidential Figure FIGURE1 DSPC 8681E SYSTEM BLOCK DIAGRAM 9 FIGURE2 DSPC 8681E PCI E CARD PLACEMEN T 10 FIGURE3 POWER DISTRIBUTION BLOCK DIAGRAMA 11 FIGURE4 DSPC 8681E OVERALL POWER SEQUENCE 13 FIGURE 5 POWER DISTRIBUTION ON DSPC 8681E PCIE CARD 14 FIGURE6 DSPC 8681E CARRIER CLOCK FEEDING DIAGRAM 16 FIGURE7 DSPC 8681E RESET BLOCK DIAGRAM 17 FIGURE8 THE DSP RESET SEQUENCE ON DSPC 86818
16. 81E is completed then PCIE GF DSP_RESETFULLZ DSP 0 3 _RESET PEX8624 SYS_RESET XC3S200AN Shannon DSPO DSP3 546165 Figure7 DSPC 8681E Reset Block Diagram Page 17 of 39 Trusted ePlatform Services ADNANTECH Advantech Confidential 2 7 Reset Sequence Below figure is provided by TMS320C6678 data manual which describes the reset timings related to DSP power rails CVDD CVDD1 DVDD15 and DVDD18 reference clocks core clock and DDR3 clock and three reset events RESETz PORz and RESETFULLz User can refer to TMS320C6678 Data Manual on TI webpage for the details Power Stabilization Phase Device Initialization Phase POR le t7 RESETFULL 1 14 68 Bits gt lt gt t4b tio tt 141 CVDD1 l 14 I DVDD18 D gt DVDD15 le 15 1 J00C 2000C 20C 20000 Figure8 DSP Reset Sequence DSPC 8681E Page 18 of 39 Trusted ePlatform Services ADNANTECH Advantech Confidential 2 8 DSP TI TMS320C6678 Block Diagram The DSPC 8681E PCI E add on card a
17. B BB Piala s B BBH33BEE EEEEEEEEI 29 SW1 DSPC 8681E Card Below figure shows the sliding switch circuit and notes the bit number for use VOC3VG_FPGA T R233 R690 Reve 8670 Figure30 SW1 Schematic The settings of Jumper and switch for DSPC 8681E are described as below table Page 36 of 39 Trusted ePlatform Services ADNANTECH Advantech Confidential Configuration Bit2 Bitl Description ON Endian 0 Endian Settin 8 OFF Little Endian 1 Boot1 000 ON ON ON Boot for development Boot2 001 ON ON OFF 2 Boot from 0x51h SEEPROM Boot3 010 ON OFF ON PCle Boot TBD Other states TBD Table14 The SW1 setting table The data format configuration setting is as below SW1 bit1 Endian 0 Big Endian 1 Little Endian default The Boot interface of the DSP the setting is as below SW1 bit 4 2 000 None boot GPIO 13 1 on the DSPs 0 0 0000 0000 0000b This mode is for the purpose of the development SW1 bit 4 2 001 2 boot GPIO 13 1 on the DSPs 0x0 0100 0000 0101b booting DSP from Ox51h of EEPROM and branch to the PCIE bus for the second boot default SW1 bit 4 2 010 PCIE Boot GPIO 13 1 on the DSPs Ox 0 0001 1000 0000 0100b booting DSP from PCIE interface SW1 bit 4 2
18. D D2 indicates the error event of PEX8624 LED D3 indicates the interrupt event of PEX8624 LED SYSPG 01 indicates that all power rails are stable Four pieces of 1M bits I2C EEPROM are attached to four DSPs respectively The EEPROM is contained of the DSP boot code and the initializations for the first boot while the card power on and then branch to PCI E interface for the second boot by the HOST computer One piece of 128kbit SPI EEPROM is attached to PCI E switch PEX8624 for specific port configurations No content is stored in the EEPROM Power Requirement 12V and 3 3V from PCI E golden finger Page 8 of 39 Trusted ePlatform Services ADNANTECH Advantech Confidential OS Verification Booting image TBD Application Program TBD Environments Operating temperatures 5 C to 45 C Storage temperatures 20 C to 70 C Relative humidity 5 to 95 Non condensing Certification CE FCCClass A UL CCC Compliant with RoHS 1 3 DSPC 8681E Block Diagrams The internal connections on DSPC 8681E PCI E card are described and shown as below figures The whole system interface block diagram for the Lightning broad is shown as Figure6 Each TMS320C6678 DSP contains several interfaces such as DDR HyperLink Serial RapidlO PCle and SGMII for Ethernet connection 1 TMS320C6678 2 DSP Bus 1 lan 3 1256 4 lan 12 56 3 4Gb x16 64bits 1 333MHz Non ECC
19. EX8624 and one RJ45 LAN port 1 2 Product Specifications Below information describes the components designed on DSPC8681E PCI E card DSP TI TMS320C6678 Multi core Fixed and Floating Point Digital Signal Processor DSP Memory 1024MB memory size on each DSP composed of 64 bit data width with four 2G bits DDR3 1333 x16 memory chips FPGA XILINX XC3S200AN Handle the DSPs interrupt events booting configurations power sequences and reset sequences and programming clock generator of CDCE62005 and the LVDS clock buffers PCl express Switch PEX8624 24 lanes PCI E GEN2 Upstream port PCI E x8 to HOST Downstream port PCI E x2 4 port to four DSPs Ethernet PHY BCM54616S Support 10 100 1000 Mb s with 1000BASE T interface I O Expansion Standard PCI E x8 golden finger I O connector CN1 XILINX XC3S200AN interface CN2 TI 60 pins DSP emulator connector CN3 The DSP boundary scan connector Page 7 of 39 Trusted ePlatform Services AD ANTECH Advantech Confidential Indicator CN4 8624 and BCM54616S boundary scan connector 5 RJ45 connector for LAN CN6 FAN connector for the heatsink COM1 3 pins UART connector 560V2_PWR1 XDS560v2 Mezzanine Power Connector Four LEDs Debug LED1 to Debug LED4 are used for the FPGA XC3S200AN debugging Five LEDs P5 D1toP5 D5 indicate available PCI E ports LE
20. GA_D4 Debug LED_3 Table6 FPGA LED Some LEDs are built in RJ 45 connector for RJ 45 behavior The right side LED blinks with green color when activity occurs normally The left side LED presents green color when 1000 BASE T link is established The left side LED present orange color when 100 BASE TX link is established If left side LED is dark it means 10 BASE T link is established or no link is established Page 26 of 39 Trusted ePlatform Services ADNANTECH Advantech Confidential 3 Connector 3 1 Connector Overview This section describes the pin definition of the connectors on the DSPC 8681E PCIE card User can have a detail on the pin signals for further use For more details please refer to the related documents from the website of the manufacturer 1 XC3S200AN for the FPGA debugging and new firmware updating CN2 TI 60 pin DSP emulator connector for software development CN3 The DSP boundary scan connector for facility test only 4 PEX8624 and 546165 boundary scan connector for the purpose of the facility test CN5 RJ45 connector Giga Ethernet port connected to DSP 0 for networking applications CN6 FAN connector for the FAN attached on the heat sink COM 1 3 pin UART connector connected to DSP 0 for the software development 560V2 1 XDS560v2 Mezzanine Power Connector TMS320C6678 boundary scan F
21. Trusted ePlatform Services ADNANTECH sve Advantech Confidential ee Lightning DSPC 8681E Quad TMS320C6678 DSP PCI E HL Card H W Manual Page 1 of 39 Trusted ePlatform Services ADNANTECH Advantech Confidential Author Status Version 0 3 Document ID Location History Version Date Handled by Comments 0 1 2012 01 06 Initial draft 0 2 2012 02 16 0 3 2012 06 21 Approved by Date Approve Version Summary Version Changes 0 1 Initial draft 0 2 Page 2 of 39 Trusted ePlatform Services AD ANTECH Advantech Confidential Content Bi GENERAL A 7 1 1 su ni 7 1 2 PRODUCT SPECIFICATIONS cccccccccccecccecccccecccccuscusceueceuseaueecuceuacecueeeueseueeeuesacueeuceesueceucetecseuaceaueuaeeuaees 7 1 3 DSPC 8681E BLOCK 5 1 o Eaa E a 9 1 4 DSPC 8681E PCI E CARD 1 4 10 2 HARDWARE SPECIFICATION 11 2 1 POWER 11 2 2
22. aagix exaagix Regulator 1 8 Regulator 1 0V Regulator 3 3V Regulator CDCE62005 PLX zi PEX8624 Regulator 9 9 eyaagix Eyaag x 1 2V Regulator PCle x8 Figure11 PCle interconnection 2 12 Ethernet MAC There are two Gigabit Ethernet MACs in DSP TMS320C6678 and are connected by SGMII SERDES interface Therefore the route of LAN packets is forwarded orderly by LAN port DSP 0 DSP 1 DSP 2 and DSP 3 On DSPC 8681E a daisy chain for LAN connections in implemented whereas the LAN port is connected to DSPHO via a PHY 546165 to provide 1000BASE T Gigabit Ethernet feature With Ethernet PHY 546165 it supports Ethernet 10 100 1000M bit s with SGMII interface and integrates triple speed Ethernet transceiver MAC to magnetic including 1000BASE T IEEE 802 3ab 100BASE TX IEEE802 3u and 10BASE T IEEE 802 3 Below figure describes the LAN connection on DSPC 8681E Page 21 of 39 Trusted ePlatform Services ADNANTECH Advantech Confidential GbE Broadcom 54615 TI UCD7242 Xilinx TI XC3S200AN UCD9244 4 TI 64 64 CDCLVD1208 0 07242 DDR3_CLK guqa9rx guqaq9rx 91 91 Regulator TI CpCLVD1208 Core_CLK Regulator Regulator B PASS_CLK 1 8V Regulator
23. ber it is summarized in the following table Table1 DSPC 8681E Power Budget VCC12load 6 882 A VCC3 3 load 2 435 A Total power consumption for EE Design 90 62W Total power consumption for Thermal Design 52 75W Power budget table please refer to below lc wp CVDD 121 5104 3 ys TECNO ETON Ta a mem zem ww aus x ma T oT on wp ics mace ose ws ee ose x me 76 o a m x pes e am ous 1 oos 8 o ms om sw lt BU 8S8 faa en Dem o ie as a ae AJAPLSM2HACTRG LDO ao foro a FPGA 0362004 120 02 1 0250 0750 x 328 ESENE EEES ES ma Table 1 DSPC 8681E Power Budget Page 12 of 39 Trusted ePlatform Services AD ANTECH Advantech Confidential 2 4 Power Sequence DSPC 8681E consists of many devices on it including DSP PCle switch PHY am
24. dopts TI 8 core DSP TMS320C6678 and its core frequency is 1000MHz Memory Subsystem 64 Bit DDR3 EMIF Debug ace gt Boot Rom E C66x CorePac Power gt Management 32KB L1 32KB L1 P Cache D Cache 512KB L2 Cache 8 Cores up to 1 25 GHz HyperLink Multicore Navigator Queue Packet Manager DMA Security Accelerator Packet Network Coprocessor PCle x2 Figure9 TMS320C6678 Block Diagram 2 9 Memory DDR3 Four DDR3 memory devices are populated for each DSP on the DSPC 8681E PCI E add on card The RAM speed is 1333MHz while each DSP connects to four 2G bit 128M x 16 DDR3 devices via DDR interface 2 10 SRIO interface For SRIO connection DSPC 8681E adopts a ring topology to chain four DSPs by one lane SRIO interface One SRIO lane is connected to previous DSP while another lane is connected to next DSP on DSPC 8681E e g the DSP 3 connects the DSPHO with x1 SRIO port and connect the DSP 2 with another x1 SRIO port Page 19 of 39 Trusted ePlatform Services ADNANTECH 1 0V Regulator 1 5V Regulator Regulator 1 8V Regulator 1 0V Regulator 3 3V Regulator 2 5 Regulator 1 2V Regulator 2 11 PCI E interface 9 Xilinx XC3S200AN 91 9 9 9 9 8624 9
25. egulator PLX CDCE62005 PEX8624 IDT ICS9DB801 1 2V PCIE_CLK Regulator PCle x8 2 5V Regulator 91 5 94x 91x 91x 94x 94x 94x 5 91 Figure14 FPGA connection 2 15 LEDs The locations of the LED indicators on the DSPC 8681E are shown by below figures User can find the indicators easily for specific purpose The detail descriptions are listed by following sections Figure15 TOP Side LED Location Page 24 of 39 Trusted ePlatform Services ADNANTECH Advantech Confidential Figure16 BOTTOM Side LED Location There are many LEDs near PEX8624 these LEDs indicates whether the PCle ports are available or not Details are shown below Table5 LED Function P5_D5 Port 0 good P5_D1 Port 9 good P5_D2 Port 8 good P5_D3 Port 6 good P5_D4 Port 5 good D2 PEX8624 error D3 PEX8624 interrupt Table5 PCI E switch LED Some LEDs are near XC3S200AN Four LEDs are used for code debugging and one LED indicates that all power rails are good Details are shown as below Table6 Page 25 of 39 Trusted ePlatform Services ADNANTECH Advantech Confidential LED Port SYSPG_D1 All power rails are good FPGA_D1 Debug LED_0 FPGA_D2 Debug LED_1 FPGA_D3 Debug LED_2 FP
26. graph we introduce the FAN connector CN6 FAN connector 3 8 UART connector FAN CNN CNB WB 2 0mm 1257 1252 10 O 1uF 164 T 189 Figure26 CN6 connector 1 GND 2 VCC 3 VCC Table12 CN6 Pin Assignment In this paragraph we introduce the 3 pin UART connector COM1 3 pins UART connector PH_3x1V_2 1 5 3 2 1 54mm RS232 RX RS232 TX Figure27 UART pin out Table13 1 Pin Assignment 1 RX 2 TX 3 GND 3 9 XDS560v2 Mezzanine Power Connector Page 34 of 39 AV Advantech Confidential Trusted ePlatform Services ADNANTECH In this paragraph we introduce the XDS560v2 Mezzanine Power Connector Advantech Confidential 560V2_PWR1 8 pin power connector for the XDS560v2 mezzanine emulator board 54 XDS560 EN Figure28 560V2_PWR1 Connector 1 VCC5 2 VCC5 3 XDS560 EN 4 GND 5 3VSB 6 3VSB 7 GND 8 GND Table14 560V2 PWRI1 Pin Assignment Page 35 of 39 Trusted ePlatform Services ADNANTECH Advantech Confidential 4 Jumper and Switch setting There is one 4 bit sliding switch SW1 on the board to set the Endian boot devices and variety of BRA size for the DSP farm by the FPGA Below figure shows the position of the 4 bit sliding switch CELII SW1 DELCE
27. igure17 Connector Overview Page 27 of 39 Trusted ePlatform Services ADNANTECH Advantech Confidential 3 2 XILINX XC3S200AN JTAG interface In this paragraph we introduce the connector for Xilinx XC3S200AN JTAG interface CN1 XILINX XC3S200AN JTAG interface FPGA JTAG 56 FPGA JTAG_TDO 66 FPGA JTAG_TDI 56 gt FPGA JTAG TMS 56 gt Figure18 the FPGA JTAG for firmware update 1 VCC 2 GND 3 TCK 4 5 TDO TDI 6 TMS Table7 CN1 Pin Assignment Page 28 of 39 Trusted ePlatform Services ADNANTECH Advantech Confidential 3 3 60 pins DSP emulator connector In this paragraph we introduce the 60 pin DSP emulator connector used for XDS562V2 CN2 60 pins DSP emulator connector 18 80 Go TRORSTZI 0970018 o sm isv LEV o _ 725 3540 awo lt T gt Figure19 2 60 Emulation Connector Tail Header Emulator Tails J2 Header to 4 60 Adapter 60 to Target Emulator TI 60 pin Connector DSP a Target Board Figure20 Connection the XDS560v2 STM Emulator Towards
28. p FPGA etc Hence the power sequence is designed to meet all devices power on requirements And the timing parameters are shown in below table Table2 System Power Sequence Parameter while the power sequence is shown in below figure Figure9 DSPC 8681E overall power sequence PEX8624 546165 VCC12 N a 5VSB 33V stacy power FPGA 3458 1V2SB FPGA VCC1V8_FPGA BCM54616S EN C6678 CVDD 05 Sms lt t lt 200ms 707 9 L L _ PEX8624 C 678 Sms lt t lt 200ms 1 1 gt 4 0700178 EN 6678 pyppire T 4 Sms lt t lt 200ms DSP_IPSV_EN j 6678 yccips POWER GOOD Figure4 DSPC 8681E overall power sequence Sym Parameter Timing Note TO EN is ramped up after UCD9244 5ms t 200ms T1 VCC1P8_EN is ramped up after VCC1PO_EN 5ms lt t lt 200ms T2 VCC1P5V_EN is ramped up after VCC1P8_EN 5ms lt t lt 200ms T3 POWER_GOOD is asserted after the last power rail VCC1P5V t gt 100ms Table 2 System Power Sequence Parameter Page 13 of 39 Trusted ePlatform Services AD ANTECH Advantech Confidential For the power sequence on each main component are designed based on the specifications of each chipset and shown in below figure Figure 5 Power distribution on DSPC 8681E PCle card VCCINT
29. undary scan connector for PEX8648 and BCM54616S CN4 PEX8624 and BCM54616S boundary scan connector 58 59 CHAIN1 JTAG i aes F 59 54616 JTAG TOO IN gt l J 58 CHAIN1_JTAG_TDI SOUT 5859 CHAIN JTAG TRSTN lt OUT E Figure24 Boundary Scan for PEX8624 and BCM54616s 1 TCK 2 PLUG DETn 3 TMS 4 NC 5 TDO 6 GND 7 TDI 8 GND 9 TRSTn 10 GND Table10 CN4 Pin Assignment Page 32 of 39 Trusted ePlatform Services ADNANTECH Advantech Confidential 3 6 RJ45 LAN connector In this paragraph we introduce the 5 connector CN5 5 connector 55 54616 LAN ACT 54616 LAN ACT R872 220 5 54616 LAN ACT 55 54616 LAN LINK 54616 LAN LINK R876 220 5 54616 LAN LINK R 54616 TROOP 54616 54616 TRDIP 54616 TRDIN NL220 100 5461 45 5 54616 TRD2P 54616 TRD2N 54616 TRD3P 54616 TRD3N 65 545156 LAN sPEED TH 5 525 5 LAN SPEED R796 220 5 54616 LAN SPEED R 55 54816 LAN SPEED2 54616 LAN SPEED2 R790 220 5 54516 LAN SPEED R PIS wintFMR amp LED 100MHz i F VCC 12 LED_LINK VCC 13 LED_SPEED1 14 LED_SPEED2 1 2 3 4 TRD1N 11 LED_ACK 5 6 Table11 CN5 Pin Assignment 3 7 FAN connector Page 33 of 39 Trusted ePlatform Services ADNANTECH In this para

Lightning DSPC-8681E Quad-TMS320C6678 DSP PCI

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