IOS-320 User`s Manual
Contents
1. CH0 19 Bi HN NN CH20 39 Auto Zero input is enabled by the mode bits overriding all channel selection bits Bits 7 amp 6 Control the programmable gain setting as described in the following table Setting 007 006 E snum Bit 5 Not used if read will return data written to the bit position Bit 4 The SEL HIGH bit acts as the MSB for analog input channel selection As such its action is grouped with that of bits 3 0 see following Bits 3 0 Control the selection of analog input channels per the following table Note that the SEL HIGH bit and MODE bits are also shown to completely define the channel selection When MODE 1 amp MODE 0 are both 0 differential channels 0 19 and calibration voltages 0 3 may be selected when MODE 1 is 0 nm t X 1 be selected when MODE 1 is 1 and MODE 0150 single ended channels 20 39 may be selected when both MODE 1 amp MODE 0 are 1 the Auto Zero input is selected regardless of any other bit levels Ea Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com SERIES 5 3201 SERVER MODULE ADC Convert Command Write Base 10H The ADC Convert Command is a write only register will not respond to reads that is used to trigger a conversion The data written to this location should be all ones to reduce digital noise although the write action alone is sufficient to trigger the conversion2. 40 to 125 C Non Isolated Logic and field commons have a direct electrical connection Radiated Field Immunity RFI Complies with EN61000 4 3 10V m 80 to 1000MHz AM amp 900MHz keyed and European Norm EN50082 1 with error less then 0 25 of FS Conducted RF Immunity CRFI Complies with EN61000 4 6 3V rms 150KHz to 80MHz and European Norm EN50082 1 with error less then 0 25 of FS Electromagnetic Interference Immunity EMI No digital upset under the 12 BIT HIGH DENSITY ANALOG INPUT BOARD Radiated Emissions Meets or exceeds European Norm EN50081 1 for class B equipment Shielded cable with connections in shielded enclosure are required to meet compliance ANALOG INPUTS Input Channels Field Access 40 Single ended or 20 Differential Ended Input Signal Voltage Non isolated Input Ranges DIP switch selectable Bipolar 5 to 5 Volts See Note 2 Bipolar 10 to 10 Volts See Notes 2 amp 3 Unipolar 0 to 10 Volts See Notes 2 amp 3 Programmable Gains x2 x4 x8 Input Overvoltage Protection 32 Volts with power applied 35V to 55 Volts unpowered Input Resistance 1000 MO Typical Input Bias Current 1nA Typical Common Mode Rejection Ra
3. 3 Default Hardware Jumper Configuration 3 Analog Input Range Hardware Jumper Configuration 4 Control Register 4 Analog Input Data 4 GONNECTORS INS 4 IOS Field Connector 2 4 Analog Input Noise and Grounding Considerations 5 External Trigger 5 3 0 PROGRAMMING 5 5 I O SPACE ADDRESS MAP oe ieu nins 6 Contool Registo isses debated 6 ADC Convert 7 Read ADC Dala ui eR MERE 7 PROGRAMMING CONSIDERATIONS 8 Using the Separate ADC Convert amp Read Command 8 Using External Conversion Triggers 8 USE OF CALIBRATION SIGNALS 8 Uncalibrated 8 Calibrated 9 4 0 THEORY OF 11 ANALOG INPUTS 11 05592 TT 11 5 0 SERVICE AND 12 SERVICE AND REPAIR ASSISTANCE 12 PRELIMINARY SERVIC
4. Table 2 4 Bipolar Straight Binary Analog Data Format Bipolar Straight Binary Data Analog Input Voltage Volts Hex 4 9976 FFFO 4 9951 FFEO 0 0024 8010 0 0000 8000 0 0024 7FFO 4 9976 0010 5 0000 0000 For Table 2 4 it is assumed that the analog input range bipolar is 5 to 5 Volts i e with a programmable gain of 1 The straight binary 12 bit data is left justified within the 16 bit word The 4 Least Significant Bits LSB s are zero and should be ignored in calculations made with the data returned from the IOS module Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com SERIES 5 3201 SERVER MODULE CONNECTORS IOS Field I O Connector P2 P2 provides the field I O interface connector for mating IOS modules to the carrier board The field and logic side connectors are keyed to avoid incorrect assembly P2 pin assignments are unique to each IOS model see Table 2 5 and correspond to the pin numbers of the front panel field I O interface connector on the carrier board In Table 2 5 channel designations are abbreviated to save space For example single ended channel 0 is abbreviated as the input for differential channel 0 is abbreviated as DCHOO Both of these labels are attached to pin 1 but only one applies according to whether the input is single ended or differential i e if your inputs are applied differentially follow the
5. 4 Read ADC Data if the conversion is still in progress the read command will generate wait states until it can deliver the data The Read ADC Data command will reset the CTRIG bit in the control register to prepare for the next external trigger 5 Repeat steps 3 4 for acquisition of the same input Otherwise repeat steps 1 4 as required USE OF CALIBRATION SIGNALS Reference signals for analog input calibration have been provided to improve the accuracy over the uncalibrated state The use of software calibration allows the elimination of hardware calibration potentiometers traditionally used in precision analog front ends A comparison of the uncalibrated and software calibrated performance is shown to illustrate the importance of the software calibration Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com SERIES 5 3201 SERVER MODULE Uncalibrated Performance The uncalibrated performance is affected by two primary error sources These are the Programmable Gain Amplifier PGA and the Analog to Digital Converter ADC The 12 BIT HIGH DENSITY ANALOG INPUT BOARD The calibration voltages are used with the auto zero signal to find two points that determine the straight line characteristic of the analog front end for a particular range The recommended calibration voltage selection for each range is summarized in the following table untrimmed PGA and ADC have the followin
6. Ideal Zero Table 3 5 Ideal Voltage Span and Zero For Input Ranges Input Range Volts 2 5 to 42 5 EON Poe 10 0000 mu M 2 5 to 42 5 0 to 5 Volts Volts 5 to 45 10 0000 5 0000 1 25 to 1 25 Eme FEE NE 10 to 10 10 to 10 20 0000 10 0000 5 to 5 1 25 to 1 25 0 to 10 0 to 2 5 0 to 1 25 The calibration parameters Countc qj and Counte qj o for each active input range should be determined at startup and updated periodically e g once an hour or more often if ambient temperatures change to obtain the best accuracy Note that several readings e g 16 of the calibration parameters should be taken via the ADC and averaged to reduce the measurement uncertainty 12 BIT HIGH DENSITY ANALOG INPUT BOARD Calibration Programming Example 1 Assume that the input range is 10 to 10 volts Channel 0 is connected differentially and corrected input channel data is desired From Tables 3 4 amp 3 5 several calibration parameters can be determined Gain 1 From Table 3 4 Voltc AL HI 4 9000 volts CALO From Table 3 4 Voltc AI Oo 0 0000 volts Auto Zero From Table 3 4 Ideal Volt Span 20 0000 volts From Table 3 5 Ideal Zero 10 0000 volts From Table 3 5 The calibration parameters Countc qj and Counte qj o remain to be determined before uncorrected input channel data can be taken and corrected T 2 13 14 15 10
7. 3 0 PROGRAMMING INFORMATION ID SPACE Read Only 32 even byte addresses Each IOS module contains an identification ID PROM that resides in the ID space This area of memory contains 32 bytes of information at most Both fixed and variable information may be present within the ID PROM Fixed information includes the IOS identifier model number and manufacturer s identification codes Variable information includes unique information required for the module The 05 320 ID information does not contain any variable e g unique calibration information ID space bytes are addressed using only the even addresses in a 64 byte block The 05 320 ID space contents are shown in Table 3 1 Note that the base address for the IOS module ID space see your carrier board instructions must be added to the addresses shown to properly access ID space Execution of an ID space read requires O wait states Table 3 1 05 320 ID Space Identification ID Hex Offset Numeric Field Description From ID Base Value Address Hex 4 L 06 8 08 AcromagIDCode 0C 00 NotUsed Revision OE 00 Reseved 10 00 NotUsd O 12 00 j Bytes 18t03bE 00 NotUsed Notes Table 3 2 1 The lOS model number is represented by a two digit code within the ID space the IOS 320 model is represented by 32 Hex SPACE ADDRESS MAP This board is addressa
8. Control Register Base OOH to setup the differential input channel 0 acquisition mode and PGA gain 1 by writing 0000H Note that not used bits are set to zero Delay to allow for input settling Execute ADC Convert Command Base 10H Execute Read ADC Data Command Base 20H Note that the 12 bit data is left justified within the 16 bit word This data represents the uncorrected Count Actual term in equation 1 Since all parameters on the right hand side of equation 1 are known Calculate the calibrated value Corrected Count This is the desired corrected value for input channel 0 Repeat steps 12 15 to re measure channel zero s data as desired Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com SERIES 5 3201 SERVER MODULE Calibration Programming Example 2 Assume that the input range is 0 to 1 25 volts Channel 39 is connected single ended and corrected input channel data is desired From Tables 3 4 and 3 5 several calibration parameters can be determined Gain 8 From Table 3 4 Voltc AI HI 1 2250 volts CAL2 From Table 3 4 Voltc A O 0 6125 volts CAL3 From Table 3 4 Ideal Volt Span 10 0000 volts From Table 3 5 Ideal Zero 0 0000 volts From Table 3 5 The calibration parameters Countc qj and Countca o remain to be determined before uncorrected input channel data can be taken and corrected 1 To prepare to measure
9. FINGOW 5 OCE SO 591995 GYVOd LNdNI DOIVNV ALISN3CO HDIH 18 SERIES 105 320 I O SERVER MODULE 12 BIT HIGH DENSITY ANALOG INPUT BOARD LOGIC FIELD 1 9 INTERFACE NOTES CA SHIELDED CABLE IS RECOMMENDED FOR LOWEST NOISE SHIELD IS CONNECTED TO GROUND REFERENCE CALIBRATK N SERIAL LINK ADORESS DATA BLIS CONTROL LINES EXTERHAL TRIGGER INPUT DIGITAL COMMON 15V SUPPLIES Ji amp J2 12 SUPPLIES SUPPLY SELECTION 105 320 BLOCK DIAGRAM A SINGLE ENDED VOLTAGE INPUT CONNECTION DIAGRAM E C CN SCHOO ms SCHO1 x i CH39 SCH39 MN CQ ES39 SENSE ANALOG COMMON EARTH GROUND Y Y T POWER SUPPLY SEE NOTE 2 SHIELD 4 l TYPICAL DIGITAL i 4 T m P2272 SEE NOTE 1 i B DIFFERENTIAL VOLTAGE INPUT CONNECTION DIAGRAM P2 m ESO DCH 4 DCH ew l o 5 i ES1 DCH 1 i L _ DCH 1 m i dg ES19 M DCH19 i E DCH19 i B ANALOG COMMON EARTH GROUND T ae 2 SHIELD bi POWER SUPPLY SEE NOTE 2 i 4 reme TYPICAL SEE NOTE 1 V COMMON
10. Further Acromag has automated test equipment that thoroughly checks the performance of each board When a board is first produced and when any repair is made it is tested placed in a burn in room at elevated temperature and retested before shipment Please refer to Acromag s Service Policy Bulletin or contact Acromag for complete details on how to obtain parts and repair PRELIMINARY SERVICE PROCEDURE Before beginning repair be sure that all of the procedures in Section 2 Preparation For Use have been followed Also refer to the documentation of your carrier board to verify that it is correctly configured Verify that there are no blown fuses Replacement of the carrier and or IOS with one that is known to work correctly is a good technique to isolate a faulty board CAUTION POWER MUST BE TURNED OFF BEFORE REMOVING OR INSERTING BOARDS WHERE TO GET HELP If you continue to have problems your next step should be to visit the Acromag worldwide web site at http www acromag com Our web site contains the most up to date product and software information Go to the Support tab to access e Application Notes Frequently Asked Questions FAQ s Product Knowledge Base Tutorials Software Updates Drivers An email question can also be submitted from within the Knowledge Base or directly from the Contact Us tab Acromag s application engineers can also be contacted directly for technical assistance via telephone or FAX throug
11. 2 amp 3 12 Volt Internal P1 15 Volt External P2 Internal and external supplies should not be mixed e g do not use 12 Volts with 15 Volts WARNING J3 IS USED FOR FACTORY CALIBRATION ONLY TREAT THESE PINS AS DO NOT CONNECTS CONNECTING THSE PINS MAY DAMAGE THE BOARD Control Register Configuration The control register is software configurable There are no hardware jumpers associated with it Control register bits are defined as logic low at reset and must be programmed to the desired gain acquisition mode and channel configuration before starting ADC analog input acquisition refer to Section 3 for details Analog Input Data Format The analog input data will appear as Straight Binary for all input ranges The following tables indicate the relationship between data format bipolar vs unipolar and the ideal analog input voltage to the module siea 12 BIT HIGH DENSITY ANALOG INPUT BOARD Table 2 3 Unipolar Straight Binary Analog Data Format Analog Input Voltage Volts Unipolar Straight Binary Data Hex 9 9976 FFFO 9 9951 FFEO 0 0024 0010 0 0000 0000 For Table 2 3 it is assumed that the analog input range unipolar is O to 10 Volts i e with a programmable gain of 1 The 12 bit straight binary data is left justified within the 16 bit word The 4 Least Significant Bits LSB s are zero and should be ignored in calculations made with the data returned from the IOS module
12. Signal 25 C Volts 0 0000 0 0002 s CAL2 12250 3004 0 6125 30002 Worst case temperature drift is the sum of the 15 ppm 9C drift of the calibration voltage reference plus the 5 ppm 9C drift of the resistors in the voltage divider 27622 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com SERIES 5 3201 SERVER MODULE The following equation 1 is used to correct the actual ADC data i e the uncorrected bit count read from the ADC making use of the calibration voltages and range constants 4096 m Corrected Count Ideal Volt Span Volt Gain Ideal Zero CALLO Count Actu al Count 1 m CALLO where m represents the actual slope of the transfer characteristic as defined in equation 2 M Voltc Ar gp VoltcAr 2 Count T Count c ALLO Gain The Programmable Gain Amplifier Setting Used See Table 3 4 Voltc AL HI High Calibration Voltage See Table 3 4 VoltcALLO Low Calibration Voltage See Table 3 4 Countcal HI Actual ADC Data Read With High Calibration Voltage Applied Actual ADC Data Read With Low Calibration Voltage Applied Ideal ADC Voltage Span See Table 3 5 Count_ Actual Actual Uncorrected ADC Data For Input Being Measured Ideal ADC Input For Zero See Table 3 5 CountcalLo Ideal Volt Span
13. To prepare to measure Countc qj o write to the Control Register Q Base 00H to setup the auto zero acquisition mode and PGA gain 1 by writing O300H Note that not used and don t care bits are set to zero Delay to allow for input settling Execute ADC Convert Command Base 10H Execute Read ADC Data Command Base 20H Note that the 12 bit data is left justified within the 16 bit word Repeat steps 3 and 4 several times e g 16 and take the average of the ADC results Save this number as CountcalLo To prepare to measure qj pj write to the Control Register Base to setup the CALO acquisition mode and PGA gain 1 by writing 0014H Note that not used bits are set to zero Delay to allow for input settling Execute ADC Convert Command Base 10H Execute Read ADC Data Command Base 20H Note that the 12 bit data is left justified within the 16 bit word Repeat steps 8 and 9 several times e g 16 and take the average of the ADC results Save this number as Countc al Calculate m actual_slope from equation 2 since all parameters are known It is now possible to correct input channel data from any input channel using the same input range i e 10 to 10 volts with a PGA gain 1 Repeat steps 1 11 periodically to re measure the calibration parameters Countc qj and Countc al as required To prepare to measure channel 0 differentially write to the
14. immediately after initiating the previous conversion will allow the input to adequately settle before the next conversion is started The overlapping of these tasks with the ADC conversion cycle is what gives rise to pipelined operation and maximum system throughput Using External Conversion Triggers External hardware triggers are generated by the user via an external TTL compatible input through the field connector see Section 2 make sure that all pertinent voltage and pulse width constraints are met The conversion is initiated on the falling edge of the external trigger signal This type of conversion triggering is useful for synchronizing the ADC conversion of analog inputs e g several OS 320 s to external events Precise time intervals between conversions can be achieved with an external timing device Note that external triggers that occur during an A D conversion cycle will be ignored Programming Example External Conversion Trigger NOTE For this example it is assumed that the external trigger input is being used to trigger conversions 1 Write to the control register to setup the acquisition mode gain and channel selections 2 Delay to allow for input settling 3 Poll Bit 15 CTRIG in the control register to determine when an ADC conversion has been triggered this assumes some prior knowledge in the application program that a hardware external trigger will occur for a particular channel s conversion
15. Countc aj o write to the Control 12 BIT HIGH DENSITY ANALOG INPUT BOARD Error checking should be performed on the Corrected Count value to make sure that calculated values below 0 or above 4095 are restricted to those end points Note that the software calibration cannot recover signals near the end points of each range which are clipped off due to the uncalibrated hardware e g PGA ADC The maximum corrected i e calibrated error is summarized in Table 3 6 as the worst case accuracy possible for each range It is the sum of error components due to ADC quantization of the low and high calibration signals PGA and ADC linearity error and the absolute errors of the recommended calibration voltages at 25 C Typical accuracies are significantly better Table 3 6 Maximum Overall Calibrated Error 25 C Input Range Volts Max Error LSB ADC Range Volts Span Register Base to setup the CAL3 acquisition mode and PGA gain 8 by writing 00D7H Note that not used bits are set to zero 2 Delay to allow for input settling Execute ADC Convert Command Base 10H 4 Execute Read ADC Data Command Base 20H Note that the 12 bit data is left justified within the 16 bit word 5 Repeat steps 3 and 4 several times e g 16 and take the average of the ADC results Save this number as CountcA 0 6 To prepare to measure Countc A write to the Control 2 5 to 42 5 1 25 to 1 25 062
16. Note that a write to this register during an A D conversion will have no effect Execution of this command requires 1 wait state D15 D00 FFFF NOTE FFFF means that all bits are programmed as ones Read ADC Data Read Base 20H Use the Read ADC Data command to read the results of the last ADC conversion This command should be used following the ADC Convert command or an external trigger input Bit 15 CTRIG in the Control Register can be used to determine if a conversion has been triggered either by software command or external trigger input Bit 14 Data Ready in the Control Register can be used to determine if a conversion has been completed If the Read ADC Data command is executed while the ADC conversion is taking place then the IOS 320 will institute wait states until the data is available up to 4 5 uS before providing the ADC data and completing the cycle Execution of the read command requires 2 wait states if the ADC conversion completed prior to initiating the read command The execution of this command will reset the CTRIG and Data Ready bits in the Control Register The 12 bits of data are left justified within the 16 bit word The four LSB s will always read as 0 Data format is Straight Binary A Reset will set all bits of this register to 0 MSB LSB D15 gt D4 DO3 DO ADC DATA 0000 PROGRAMMING CONSIDERATIONS FOR ACQUIRING ANALOG INPUTS The 05 320 provides two different methods of analo
17. v AT ONE END ONLY PROVIDE SHIELDING WITHOUT GROUND LOOPS REFERENCE CHANNELS TO ANALOG COMMON IF THEY WOULD OTHERWISE BE FLOATING CHANNELS ALREADY HAVING A GROUND REFERENCE MUST NOT BE CONNECTED TO ANALOG COMMON TO AVOID GROUND LOOPS EXTERNAL SUPPLIES CAN BE USED BY JUMPERING IT IS RECOMMENDED THAT THE SUPPLY COMMONS BE CONNECTED TO ANALOG COMMON 16 Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com
18. 5 8 0 128 Surge Immunity Not required for signal I O per European Norm 50082 1 Settling Time 20V step 5 2uS to 0 01 of FSR Electric Fast Transient A D Conversion Time 4 5uS Maximum Immunity EFT sese Complies with EN61000 4 4 AD THgderSusee ie External and Software Level 2 0 5KV at field I O Maximum Conversion Rate 200KHz Maximum terminals and European Norm Recommended Conversion Rate 100KHz Maximum EN50082 1 Input 0 2 LSB rms Typical Temperature Coefficient See specification of calibration voltages Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com SERIES 5 3201 SERVER MODULE Programmable Calibration Voltages follow Ideal Calib Value Signal Volts Maximum Tolerance 25 C Volts Temperature Drift ppm C Auto 0 0000 0 0002 ww 4 Zero CAL2 1220 0 0008 CALS 0 6125 30002 Worst case temperature drift is the sum of the 15 ppm C drift of the calibration voltage reference plus the 5 ppm 9C drift of the resistors in the voltage divider Notes 2 3 Range assumes the programmable gain is equal to one Additional ranges are created with other gains Divide the listed range by the programmable gain to determine the actual input range
19. 5 to 0 625 25 p m E4951 25 0061 I 29 0071 j 18 004 JL 9546 0951 25 0 061 22 0055 99 10 to 10 Register Base to setup the CAL2 acquisition mode and PGA gain 8 by writing OOD6H Note that not used bits are set to zero 7 Delay to allow for input settling 8 Execute ADC Convert Command Base 10H 9 Execute Read ADC Data Command Base 20H Note that the 12 bit data is left justified within the 16 bit word Repeat steps 8 and 9 several times e g 16 and take the average of the ADC results Save this number as Countc al 11 Calculate m actual_slope from equation 2 since all parameters are known It is now possible to correct input channel data from any input channel using the same input range i e 0 to 1 25 volts with a PGA gain 8 Repeat steps 1 11 periodically to re measure the calibration parameters Countc qj and Countc al as required TO prepare to measure channel 39 single ended write to the Control Register Base OOH to setup the single ended input channel 39 acquisition mode and PGA gain 8 by writing O2D3H Note that not used bits are set to zero Delay to allow for input settling Execute ADC Convert Command Base 10H Execute Read ADC Data Command Base 20H Note that the 12 bit data is left justified within the 16 bit word This data represents the uncorrected Count Actual term in equa
20. Acroma THE LEADER IN INDUSTRIAL 1 gi 105 320 12 Bit High Density Analog Input Module USER S MANUAL ACROMAG INCORPORATED Tel 248 295 0310 30765 South Wixom Road Fax 248 624 9234 P O BOX 437 Wixom MI 48393 7037 U S A solutions acromag com Copyright 2009 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 837 C11C007 SERIES 5 3201 SERVER MODULE The information contained in this manual is subject to change without notice Acromag Inc makes no warranty of any kind with regard to this material including but not limited to the implied warranties of merchantability and fitness for a particular purpose Further Acromag Inc assumes no responsibility for any errors that may appear in this manual and makes no commitment to update or keep current the information contained in this manual No part of this manual may be copied or reproduced in any form without the prior written consent of Acromag Inc Table of Contents Page 1 0 GENERAL 2 KEY ANALOG INPUT 2 I O SERVER MODULE INTERFACE FEATURES 3 I O SERVER MODULE 3 2 0 PREPARATION FOR 0 3 UNPACKING AND 3 BOARD
21. DIP switch controls the input voltage span and the selection of unipolar or bipolar input ranges The configuration of the DIP switch for the different ranges is shown in table 2 1 A switch selected as ON would be positioned to the side of the DIP labeled ON The DIP switch location is shown in the Jumper Locations drawing on page 14 The selection of internal or external analog power supplies is accomplished via hardware jumpers J1 and J2 J1 J2 controls the selection of either the internal 12 12 Volt supply sourced from P1 connector or the external 15 15 Volt supply sourced from the P2 connector The configuration of the jumpers for the different supplies is shown in the table 2 2 IN means that the pins are shorted together with a shorting clip OUT means the clip has been removed For a detailed drawing refer to the Jumper Locations drawing on page 14 Table 2 1 Analog Input Range Selections DIP Switch Settings Desired ADC Input Range VDC Switch Settings OFF Switch Settings ON Required Input Span Volts Required Input Type 13 49 2 5 6 7 8 10 to 10 2 5 6 9 1 3 4 7 8 010 10 1 3 4 7 2 5 6 8 9 Assuming a gain of 1 These ranges can only be achieved with 15V external power supplies The input ranges will be clipped if 12V supplies are used typically to 9 V maximum inputs Table 2 2 Power Supply Selections Pins of J1 and J2 Power Supply J1 J2 J1 J2 Selection 1 amp 2
22. E PROCEDURE 12 WHAERE TOGET HELP ir 12 6 0 SPECIFICATIONS 12 GENERAL 12 ENVIRONMENTAL 5 dote nce 12 ANALOG INPUTS coco is decet Pase toas setae o oso 13 DRAWINGS Page IOS 320 JUMPER LOCATIONS 14 IOS 320 BLOCK DIAGRAM 15 ANALOG INPUT CONNECTION DIAGRAM 15 12 BIT HIGH DENSITY ANALOG INPUT BOARD IMPORTANT SAFETY CONSIDERATIONS It is very important for the user to consider the possible adverse effects of power wiring component sensor or software failures in designing any type of control or monitoring system This is especially important where economic property loss or human life is involved It is important that the user employ satisfactory overall system design It is agreed between the Buyer and Acromag that this is the Buyer s responsibility 1 0 GENERAL INFORMATION The I O Server Module IOS 320 is a 12 bit high density single size IOS analog input board with the capability to monitor 20 differential or 40 single ended analog input channels The IOS 320 utilizes state of the art Surface Mounted Technology SMT to achieve its high channel density It offers a variety of features which make it an ideal choice for many industrial and scientific applications as described below Important Note The following IOS model are accessories to the IOS Server Mo
23. ELECTROSTATIC ELECTROMAGNETIC l MAGNETIC OR RADIOACTIVE FIELDS board utilizes static sensitive components and should only be handled at a static safe workstation BOARD CONFIGURATION The board may be configured differently depending on the application All allowable jumper settings are discussed in the following sections Jumper locations are shown in the drawing in the end of this manaul Power should be removed from the board when configuring hardware jumpers installing IOS modulesIP s cables termination panels and field wiring Refer to the Analog Input Connection Diagram on page 15 and IOS documentation for IOS configuration and assembly instructions Default Hardware Jumper Configuration A board shipped from the factory is configured as follows e Analog input range is configured for a 10V bipolar input span i e an ADC input range of 5 to 5 Volts e Internal 12 Volt power supplies are used sourced from P1 connector e X Programmable software control register bits set at logic low during power up reset The control register should be programmed to the desired gain mode and channel configuration before starting ADC analog input acquisition Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com SERIES 5 3201 SERVER MODULE Analog Input Range Hardware Jumper Configuration The ADC input range is programmed via hardware DIP switch The
24. Input signal ranges may actually fall short of reaching the specified endpoints due to hardware limitations For example if an input may reach zero volts or less a bipolar input range should be selected These ranges can only be achieved with 15 Volt external power supplies The input ranges will be clipped if 12 Volt supplies are used typically to 9 Volt maximum inputs 14 12 BIT HIGH DENSITY ANALOG INPUT BOARD Follow the input connection recommendations of Section 2 because input noise and non ideal grounds can degrade overall system accuracy For critical applications multiple input samples can be averaged to improve performance Accuracy is specified for the software conversion command Use of the external hardware trigger input with software polling may degrade accuracy Accuracy versus temperature depends on the temperature coefficient of the calibration voltage Access Times 8MHz Clock ID PROM Read 0 wait states 250ns cycle Control Register Read wait states 250ns cycle Control Register Write 1 wait state 375ns cycle Conversion Request Write 1 wait states 375ns cycle Read ADC Data Note 5 2 wait states 500ns cycle Note 5 The 2 wait states specified assume that the previous conversion has been completed and that data is available to be read If a conversion is in progress the command will institute wait states until the data can be de
25. a time Execution of a Control Register read write requires O 1 wait states At reset all bits are set to 0 The function of each bit is described as follows High Byte LSB D08 CTRIG Data Not Not Not Not MODE MODE Ready used used used used 1 0 Low Byte MSB LSB D07 DOO GSEL GSEL Not SEL CH3 CH2 CH1 CHO 1 0 used HIGH Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com SERIES 5 3201 SERVER MODULE 12 BIT HIGH DENSITY ANALOG INPUT BOARD Bit 15 When read the CTRIG bit indicates whether an ADC conversion has been triggered either by software command or external trigger input If the bit reads high the conversion could be taking place or has been completed CTRIG is cleared by reading the ADC data Writing to this bit position will have no effect Bit 14 The Data Ready bit indicates if an ADC convert command has completed and valid data resides in the ADC Data Register If the bit reads high then valid data awaits in the ADC data register from the previous conversion Data Ready is cleared by reading the ADC data register Writing to this bit position will have no effect Bits 13 10 Not used if read will return data written to those bit positions Bits 9 amp 8 Control the input acquisition mode as described in the following table e DNE Acquisition Mode 009 Bit 008 Po 19 amp CALO 3 emm
26. ble in the Server Module space to control the acquisition of analog inputs from the field The I O space may be as large as 64 16 bit words 128 bytes but the IOS 320 only uses a portion of this space The I O space address map for the 05 320 is shown in Table 3 2 Note the base address for the IOS module space see your carrier board instructions must be added to the addresses shown to properly access the space All accesses are performed on 16 bit word basis DO D15 12 BIT HIGH DENSITY ANALOG INPUT BOARD Table 3 2 105 320 Space Address Memory Map Base High Byte Add D15 D08 Hex R W Control Register eo ENIM O m N Y 10 Y 03 OF T1 13 4 1F v Repeated Read ADC Data 2F 31 4 41 4 4F 51 NO oim N m N Im BIEN BIEN I o Notes Table 3 1 1 Registers appear in multiple locations in the memory map because of simplified address decoding these locations can be ignored 2 The IOS will respond to addresses that are Not Used with an active IOS module acknowledge ACK The board will return O for all address reads that are not used or reserved A O oye ITI NJ m Control Register Read Write Base 00H The IOS 320 Control Register reflects and controls analog input channel data acquisition functions This register must be written read one word D16 at
27. dels 05 7200 IOS 7200 WIN IOS 7400 and IOS 7400 WIN which are cULus Listed This equipment is suitable for use in Class 1 Division 2 Groups A B C and D or non hazardous locations only Operating Temperature Range 105 320 40 to 85 C KEY ANALOG INPUT FEATURES e High Channel Count Monitors up to 20 differential or 40 single ended analog inputs acquisition mode and channels are selected via a programmable control register Up to four units may be mounted on a carrier board providing up to 80 differential inputs or 160 single ended inputs in a single system slot e 12 bit Accuracy Contains an enhanced 12 bit successive approximation Analog to Digital Converter ADC with a 4 5uS conversion time e High Speed The recommended maximum system throughput rate is 100KHz e Multiple Input Range A Hardware DIP switch allows for selectable ranges for both bipolar and unipolar voltage inputs 5 to 5V 10 to 10V and to 10V e Programmable Gain Gains of 1 2 4 and 8 are programmable via the control register e Software Hardware Trigger Input acquisition can be triggered via software or by an external hardware input for synchronization to external events e Precision References On board high precision voltage references provide the means for accurate and reliable software calibration of the module e Conduction Cooled Module I O modules employ advanced thermal technologies A thermal pad and module cov
28. differential channel labeling for each channel s and input leads Table 2 5 105 320 Field I O Pin Connections P2 Pin Description odd Pin Description lua SCH22 DCHO2 6 SCH23 DCHO3 8 SCHO44DCHO4 9 ndicates an Active Low Signal Analog Input Noise and Grounding Considerations Differential inputs require two leads and per channel and provide rejection of common mode voltages This allows the desired signal to be accurately measured However the signal being measured cannot be floating it must be referenced to analog common on the IOS module and be within the normal input voltage range Differential inputs are the best choice when the input channels are sourced from different locations having slightly xb 12 BIT HIGH DENSITY ANALOG INPUT BOARD different ground references See page 14 for analog input connections for differential and single ended inputs Single ended inputs only require a single lead per channel with a shared sense reference lead for all channels and can be used when a large number of input channels come from the same location e g printed circuit board The channel density doubles when using single ended inputs and this a powerful incentive for their use However caution must be exercised since the single sense lead references all channels to the same common which will induce noise and offset if they are different IOS 320 is non isolated since the
29. er wicks heat away from the module and transfers the energy to a heat spreading friction plate Heat moves to the enclosure walls where it is dissipated by the external cooling fins Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com SERIES 5 3201 SERVER MODULE SERVER MODULE INTERFACE FEATURES e High density Single size industry standard IOS module footprint Four units mounted on a carrier board provide up to 80 differential or 160 single ended channels e Local ID Each IOS module has its own 8 bit ID PROM which is accessed via data transfers in the ID Read space e 16 bit I O Control register Read Write and A D Conversion Read are performed through 16 bit data transfer cycles SERVER MODULE SOFTWARE IOS MODULE Win32 DRIVER SOFTWARE Acromag provides a software product sold separately to facilitate the development of Windows Embedded Standard applications interfacing with I O Server Modules installed on Acromag Industrial I O Server systems This software Model IOSSW DEV WIN consists of a low level driver and Windows 32 Dynamic Link Libraries DLLS that are compatible with a number of programming environments including Visual C Visual Basic NET Borland C Builder and others The DLL functions provide a high level interface to the IOS carrier and modules eliminating the need to perform low level reads writes of registers and the writing of interrupt ha
30. g input acquisition to give the user maximum flexibility for each application The following sections describe the features of each and how to best use them Using the Separate ADC Convert and Read Commands Use of the separate convert and read commands is a straightforward and accurate way to acquire data This method is useful for most applications Programming Example Separate ADC Convert amp Read NOTE For this example it is assumed that the external trigger input is NOT being used to trigger conversions 1 Write to the control register to configure the acquisition mode gain and channel selections 2 Delay to allow for input settling 3 Execute the ADC Convert command 12 BIT HIGH DENSITY ANALOG INPUT BOARD 4 Write to the control register to configure the acquisition mode gain and channel selections for the next acquisition if they are different This may be done while the conversion is in progress because the ADC is in the hold mode 5 The ADC conversion takes several microseconds This time can be put to use for other purposes e g calibration of ADC channel data 6 Read ADC Data if the conversion is still in progress the read command will generate wait states until it can deliver the data 7 Repeat steps 3 6 as required to acquire additional analog input samples Note that the input settling delay does not have to be inserted since writing to the control register to configure for the next acquisition
31. g performance Table 3 4 Recommended Calib Voltages For Input Ranges Rec Low Rec High Calib Calib Voltage Voltage Voltc AL Volts Lr aai BM cio _ Lr AE ps PGA206AU 9259 Linearity Error is 0 005 Maximum i e 1 4 LSB Offset Error RTI is 1mv Typical 2 5mV Maximum Gain Error is 0 01 typical 0 1 maximum for all gains ADC ADS8508 25 C Linearity Error is 0 5 LSB Maximum Unipolar Zero Error is 5 mV Maximum Bipolar Zero Error is 1 mV Maximum Full Scale Calibration Error is 0 5 of span Maximum Table 3 3 Maximum Overall Uncalibrated Error at 25 C Max Offset Error LSB 2 5 to 42 5 1 25 to 1 25 2 4500 CAL1 0 625 to l 0 625 1 0 6125 CAL3 LI D aa 1 2 Note that the worst case non linearity error is 0 75 LSB the sum of the 1 2 LSB non linearity of the ADC and the 1 4 LSB non linearity of the PGA Calibrated Performance Very accurate calibration of the IOS 320 can be accomplished by using calibration voltages present on the board The four voltages and the analog ground reference are used to determine the endpoints of a straight line which defines the analog input characteristic The calibration voltages are precisely adjusted at the factory to provide optimum performance as detailed in the following table Maximum Temperature Drift ppm 9C Maximum Calibration Tolerance
32. h the numbers listed below When needed complete repair services are also available Phone 248 295 0310 Fax 248 624 9234 Email solutions acromag com Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com SERIES 5 3201 SERVER MODULE 6 0 SPECIFICATIONS GENERAL SPECIFICATIONS Physical Configuration Single I O Server Module LOO 4 030 in 102 36 mm MGE 1 930 in 49 02 mm Board Thickness 0 062 in 1 59 mm HeIODEb tout incon ette 0 500 in 12 7 mm Connectors P1 IOS Logic Interface 50 pin female receptacle header AMP 173279 8 or equivalent P2 Field l O 50 pin female receptacle header AMP 173279 8 or equivalent Power 5 Volts 59 90mA Typical 210mA Maximum 12 Volts 45 from P1 or 15mA Typical 25mA Maximum 15 Volts 45 from P2 See Note 1 12 Volts 5 from P1 or 13mA Typical 25mA Maximum 15 Volts 45 from P2 See Note 1 Note 1 The 12 volt power supplies are normally supplied through 1 logic interface connector Optionally jumper selectable on the IOS the user may connect external 15 volt supplies through the field I O interface connector P2 ENVIRONMENTAL Operating Temperature 40 to 85 C Relative Humidity 5 95 non condensing Storage Temperature
33. livered This could take up to 4 5uS 32 wait states maximum Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com uoo BeuloJoe MWWW diu uoo Beuiojoegsuonnjos ieu3 pEZ6 7Z9 8rzZ xe4 01 lt 0 662 9 2 1 oul 6euioJoy SwiTCH SWITCH ON POSITION SWITCH SHOWN WITH DEFAULT SWITCH SETTINGS POSITIONS 1 3 4 AND 3 ON JO FOR FACTORY USE ONLY GO NOT CONNECT 4 21 COMPONENT SIDE VIEW ANALOG INPUT RANGE SELECTION E Switch Settings POWER SUPPLY SELECTI SELECTIONS NS PINS OF J1 J1 AND 202 POWER SUPPLY O SELECTION 1 a2 2 12 VOLT INTERNAL Jes C 3 L L 3 15 VOLT EXTERNAL N ee aus 22a 18T0 1804 20 Bipot T T INTERNAL AND EXTERNAL SUPPLIES SHOULD HOT BE MIXED E G DO NOT USE 12 VOLTS WITH 15 VOLTS eo 108 18 Wier 1347 25555 x THE BOARD 15 SHIPPED WITH THE DEFAULT JUMPER SETTING FOR amp 12 VOLT SUPPLIES AS SHOWN IN THE DIAGRAM ASSUMING A GAIN OF 1 s THE BOARD 15 SHIPPED WITH THE DEFAULT CHP SWITCH SETTING FOR THE 5 TO 5 VOLT ADC INPUT RAMGE AS SHOWH THE ABOVE DIAGRAM aaa THESE RANGES CAN ONLY ACHIEVED WITH 15 VOLT EXTERNAL POWER SUPPLES THE INPUT RANGES WILL BE CUPPED IF 12 vOLT SUPPLIES ARE USED TICALLY TO 78 5 VOLT MAXIMUM INPUTS 105 320 JUMPER LOCATIONS
34. nd differential channels cannot be mixed i e they must all be single ended or differentially wired A Programmable Gain Instrumentation Amplifier PGA takes as input the selected channel s and inputs or and sense and outputs a single ended voltage proportional to it The gain can be 1 2 4 or 8 and is selected through the control register Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com SERIES 105 320 I O SERVER MODULE The output of the PGA feeds the Analog to Digital Converter ADC The A D Converter is a state of the art 12 bit successive approximation converter with a built in Sample and Hold S H circuit The S H goes into the hold mode when a conversion is initiated This maintains the selected channel s voltage constant until the A D Converter has accurately digitized the input Then it returns to the sample mode to acquire the next channel Once a conversion has been started the control register can be updated for the next channel This allows the input to settle for the next channel while the previous channel is converting which gives rise to the pipelined mode of operation and maximum system throughput A miniature DIP switch on the board control the range selection for the A D Converter 5 to 5 10 to 10 or 0 to 10 Volts as detailed in Section 2 DIP switch selection should be made prior to powering the unit Thus all channels will use the same A D Co
35. ndlers IOS MODULE LINUX SOFTWARE Acromag provides a software product sold separately consisting of Linux software This software Model IOSSW API LNX is composed of Linux libraries designed to support applications accessing Server Modules installed on Acromag Industrial I O Server systems The software is implemented as a library of C functions which link with existing user code 2 0 PREPARATION FOR USE UNPACKING AND INSPECTION Upon receipt of this product inspect the shipping carton for evidence of mishandling during transit If the shipping carton is badly damaged or water stained request that the carrier s agent be present when the carton is opened If the carrier s agent is absent when the carton is opened and the contents of the carton are damaged keep the carton and packing material for the agent s inspection For repairs to a product damaged in shipment refer to the Acromag Service Policy to obtain return instructions lt is suggested that salvageable shipping cartons and packing material be saved for future use in the event the product must be shipped 12 BIT HIGH DENSITY ANALOG INPUT BOARD This board is physically protected with packing material and electrically protected with an anti static bag during shipment lt is recommended that the board be visually inspected for evidence of mishandling prior to CAUTION SENSITIVE ELECTRONIC DEVICES applying power DO NOT SHIP OR STORE NEAR STRONG
36. nverter range However the analog input range can vary on an individual channel basis depending on the programmable gain selection The logic interface provides 12 Volt supplies to the analog circuitry The 10 to 10 and 0 to 10 Volt A D Converter ranges will be clipped if these supplies are used typically to 9 Volt maximum inputs The user has the option of providing 15 Volt external supplies to fully utilize input ranges to 10 Volts These supplies are selected via hardware jumpers J1 and J2 as detailed in Section 2 Note that jumper selection should be made prior to powering the unit Further internal and external supplies should not be mixed e g do not use 12 Volts with 15 Volts The board contains four precision voltage references and a ground autozero reference for use in calibration These provide considerable flexibility in obtaining accurate calibration for any desired ADC range and gain combination when compared to fixed hardware potentiometers for offset and gain calibration of the ADC and PGA The calibration signals are selected multiplexed into the PGA like any other input channel 12 BIT HIGH DENSITY ANALOG INPUT BOARD 5 0 SERVICE AND REPAIR SERVICE AND REPAIR ASSISTANCE Surface Mounted Technology SMT boards are generally difficult to repair It is highly recommended that a non functioning board be returned to Acromag for repair The board can be damaged unless special SMT repair and service tools are used
37. re is electrical continuity between the logic and field grounds As such the field I O connections are not isolated from the carrier board and backplane Care should be taken in designing installations without isolation to avoid noise pickup and ground loops caused by multiple ground connections This is particularly important for analog inputs when a high level of accuracy resolution is needed 12 bits or more Contact your Acromag representative for information on our many isolated signal conditioning products that could be used to interface to the IOS 320 input module External Trigger Input The external trigger signal on P2 is an active low input which may be used for synchronizing the ADC conversion of analog inputs from several IOS modules to external events The external trigger must be a 5 Volt logic TTL compatible debounced signal referenced to analog common Note that the IOS 320 provides 125ns of debounce on the external trigger input The conversion is triggered on the falling edge of a normally high signal The trigger pulse must be low for a minimum of 25005 to guarantee acquisition The external trigger may remain low for an indefinite period of time However it must return to a high state for a minimum of 250nS prior to a subsequent trigger See Section 3 for programming information Acromag Inc Tel 248 295 0310 Fax 248 624 9234 Email solutions acromag com http www acromag com SERIES 5 3201 SERVER MODULE
38. tio 80dB Typical 60Hz CH to CH Rejection Ratio 80dB Typical 60Hz A D Resolution 12 bits Data Format left justified Straight Binary No Missing Codes No Missing Codes 12 bit ADC A D Integral Linearity Error 1 2 LSB Maximum System Accuracy See Note 4 The maximum corrected i e calibrated error is summarized in the following table as the worst case accuracy possible for each range It is the sum of error components due to ADC quantization of the low and high calibration signals PGA and ADC linearity error and the absolute errors of the recommended calibration voltages at 25 C Typical accuracies are significantly better Maximum Overall Calibrated Error 25 C Input Range PGA ADC Range Max Error Volts Gain Volts LSB Span 250025 2 21 0 051 switching solenoids 71251 4125 4 2510061 commutator motors and drill 06251040026 8 _ 29 007 motors influence of EMI from Electrostatic Discharge Immunity ESD Complies with EN61000 4 2 Level 3 8KV enclosure port air discharge and Level 2 4KV 510055 2 1 8 0 04 2510425 4 2 2 1 0 051 1 2510 41 25 8 0 to 10 2 5 0 061 3 2 0 078 NEAL EMI enclosure port contact discharge and European Norm owes 4 31 076 _ 50082 1 L 015512
39. tion 1 Since all parameters on the right hand side of equation 1 are known Calculate the calibrated value Corrected Count This is the desired corrected value for input channel 39 Repeat steps 12 15 to re measure channel 39 s data as desired 13 14 15 s E se mE dq 8 1 0 076 0 to 1 25 a 4 0 THEORY OF OPERATION This section describes the functionality of the IOS 320 circuitry Refer to the IOS 320 block diagram on page 15 as you study the following paragraphs ANALOG INPUTS The field I O interface via the carrier board is through connector P2 Field analog inputs are non isolated This means that the field analog return and logic common have a direct electrical connection Care must be taken to avoid ground loops and excessive common mode voltage see Section 2 for connection recommendations These can cause measurement error and with extreme abuse circuit damage Analog inputs and calibration voltages are selected via CMOS analog multiplexers MUX s A software programmable control register contains gain acquisition mode e g single ended or differential and channel selection information to control the multiplexers Up to 40 single ended inputs can be monitored where each channel s input is individually selected along with a single sense lead for all channels Up to 20 differential inputs can be monitored where each channel s and inputs are individually selected Single ended a
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