SH67P847 - SinoWealth！
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1. Pin DATA Register GND 0 DATA READ DATA IN ree READ t 5 67 847 In SH67P847 each output port contains a latch which can hold the output data Writing the port data register under the output mode can directly transfer data to the corresponding pad All input ports do not have latches so the external input data should be held externally until the input data is read from outside or reading the port data register PDR is read under the input mode When digital 1 port is selected as an output the reading of the associated port bit actually represents the value of the output data latch not the voltage on the pad When a digital I O port is selected as an input the reading of the associated port bit represents the status on the corresponding pad m PORTA 0 2 can be shared with ADC input channel ANO 2 m PORTA 0 can be shared with the reference voltage input VREF W 0 can be shared with ADC input channel AN3 m PORTB 1 can be shared with PWM channel Port Interrupt The PORTA 3 is used as external port interrupt sources Since PORTA 3 is bit programmable I O only when the PORTA 3 is select as normal input the voltage transition from to GND applying to the digital input port can generate a port interrupt Port Interrupts can be used to wake up the CPU from the HALT or the STOP mode IEP 2 Falling PORTA 3 Dx2. SINO WEALTH SH67P847 OTP 1K 4 bit micro controller with 10 bit SAR ADC Features m SH6610C Based Single Chip 4 bit Micro Controller With 10 bit SAR ADC WOTP ROM 1K X 16bits W RAM 124 X 4bits 28 System Control Registers 96 Data Memory W Operation Voltage fosc 16MHz Vpp 3 3V 5 5V m6 CMOS Bi Directional I O Pins E 4 L evel Stack Including Interrupts E One 8 bit Auto Re Loaded Timer m Warm Up Timer Powerful Interrupt Sources A D Interrupt TimerO Interrupt External Interrupts PORTA 3 Falling Edge General Description E Oscillator Internal RC Oscillator 16MHz E Instruction Cycle Time 16 fosc W Two Low Power Operation Modes HALT And STOP E Reset Built in Power on Reset POR Built in Low Voltage Reset LVR Code Option Built in Watchdog Timer WDT Code Option W 4 Channels 10 bit Resolution Analog Digital Converter ADC W 1 Channels 9 bit PWM Output m Type Code Protection W8 pin SOP package available SH67P847 is a single chip 4 bit micro controller This device integrates a SH6610C CPU core RAM ROM timer ADC high speed PWM output watch dog timer low voltage reset The SH67P847 is suitable for charger application Pin Configuration PORTB 1 PWM 11 2 GND 13 PORTA O VREF ANO SDA 14 1 8419 5 PORTA 2 AN2 SCK VDD PORTA 1 AN1 V2 0 5 67 847 Block Diagram Reset Circuit Oscill
3. 2 PC1 PCO The program counter is loaded with data corresponding to each instruction The unconditional jump instruction JMP can be set at 1 bit page register for higher than 2K The program counter cans only 4K program ROM address Refer to the ROM description 1 2 ALU and CY The ALU performs arithmetic and logic operations The ALU provides the following functions Binary addition subtraction ADC SBC ADD SUB ADI SBI Decimal adjustments for addition subtraction DAA DAS Logic operations AND EOR OR ANDIM EORIM ORIM Decisions BAO BA1 2 BAZ BNZ BC BNC Logic Shift SHR The Carry Flag CY holds the ALU overflow that the arithmetic operation generates During an interrupt service or CALL instruction the carry flag is pushed into the stack and recovered from the stack by the RTNI instruction It is unaffected by the RTNW instruction 1 3 Accumulator AC The accumulator is a 4 bit register holding the results of the arithmetic logic unit In conjunction with the ALU data is transferred between the accumulator and system register or data memory can be performed 2 RAM SH67P847 1 4 Table Branch Register TBR Table Data can be stored in program memory and can be referenced by using Table Branch TJMP and Return Constant RTNW instructions The TBR and AC are placed by an offset address in program ROM TJMP instruction branch into address PC11 PC8 X 23 TBR AC T
4. Write PP 7 PP 0 0DH Write PD 7 PD 0 07H PWM output 1 I r 4 9 9 Duty cycle Duty cycle Duty cycle 06H X tewm 06H X tewm 07H X tewm lt Period cycle OFH X tewm Period cycle X PWM Output Period or Duty Cycle Changing Example 101 02 03 04 05 06 07 08 09 0B 0C 0D 0E 01 02 03 04 05 06 07 08 09 0A 0BOCOD O1 02 03 04 05 06 07 08 PWM clock tPwM 0 06 PD 7 PDO 06H 0 1 PWM output Dutycyde Duty cycle Duty cycle 6 X 6 1 2 X tewm 6 1 2 X tewm Period cycle X tPwM Period cycle X tPwM PWM Fine Tune Example 16 5 67 847 11 Low Voltage Reset LVR The LVR function is to monitor the supply voltage and generate an internal reset in the device It is typically used in AC line applications or large battery where large loads may be switched in and cause the device voltage to temporarily fall below the specified operating minimum The LVR function is selected by Code option The LVR circuit has the following functions when LVR function is enabled Generates a system reset when VDD lt Cancels the system reset when VDD gt VLVR Here is the Power voltage VLvR is LVR detect Voltage
5. AC Mx Decimal adjust for sub 20 CY SH67P847 2 Transfer Instruction Function AC Mx Mx AC AC Mx lt Instruction Code Flag Change 00111 Obbb xxxx 00111 1bbb xxx xxxx Mnemonic LDA X B STA LDI Xil 01111 iiii 3 Control Instruction Function lt ifAC 0 Mnemonic Instruction Code Flag Change BAZ X BNZ BC 10010 PC lt X PC lt X if AC 0 if CY 21 10000 XXXX 10011 2 1 PC lt 3 1 ST 1 PC X Not include PC ST TBR lt hhhh lt IIII CY PC ST if CY 1 0 1 10001 10101 10110 10111 10100 11000 H L 11010 0001 hhh ill 11010 1000 000 0000 11011 0000 000 0000 11011 1000 000 0000 PC lt X Include p PC lt PC11 PC8 TBR AC 1110 XXXX 11110 1111 111 1111 11111 1111 111 1111 No Operation Where Program Counter Immediate Data Accumulator Logical Exclusive OR Complement of Accumulator
6. 12 Watchdog Timer WDT The watchdog timer is a down count counter and its clock source is an independent built in RC oscillator so that it will always run even in the STOP mode The watchdog timer automatically generates a device reset when it overflows It can be enabled or disabled permanently by using the code option The watchdog timer control bits 1E Bit2 are used to select different overflow frequency The watchdog timer overflow flag 1E Bit3 will be automatically set to 1 by hardware when the watchdog timer overflows By reading writing the system register 1E the watchdog timer should re count before the overflow happens System Register 1E Watchdog Timer WDT Remarks Bit2 0 Watchdog timer control register Bit3 Watchdog timer overflow flag register gt Z Watchdog timer out period 4096ms Watchdog timer out period 1024ms Watchdog timer out period 256ms Watchdog timer out period 128ms Watchdog timer out period 64ms Watchdog timer out period 16ms Watchdog timer out period 4ms Watchdog timer out period 1ms 2 o iloio o gt gt gt No watchdog timer overflow reset Watchdog timer overflow WDT reset happens Note Watchdog timer overflow period is valid for 5V 13 HALT and STOP Mode After the execution of HALT instructi
7. All output pins unload including all digital input unfloating CPU off execute STOP instruction WDT off ADC disable LVR off WDT Current 20 fosc 16MHz fsvs 1MHz 5 0V All output pins unload including all digital input unfloating CPU off execute STOP instruction WDT on ADC disable LVR off GND Input Low Voltage 0 3 Ports except PORTA 3 GND 0 2 XVDD PORTA 3 0 7 X VDD Input High Voltage VDD Ports except PORTA 3 0 8 X VDD VDD PORTA 3 Input Leakage Current 1 Input pad VIN or GND 5 0V Output Leakage Current 1 PORTA 3 5 0V Vour VDD Output High Voltage Ports 5mA 5 0 Output Low Voltage GND 0 6 Ports loL 5mA VDD 5 0 Pull High Resistor Pull high resistor VDD 5 0V Data in Typ column is at 5 0V 25 C unless otherwise specified Maximum value of the supply current to is 25mA Maximum value of the output current from GND is 25 22 5 67 847 AC Electrical Characteristics 3 3V 5 5V GND OV TA 25 C fosc 16MHz fsvs 1MHZz unless otherwise specified Parameter Symbol in Condition WDT Period twDT 5 0V z Internal RC Oscillator 5 0V TA 5 C 45 C including chip to chip variation 3 3V 5 5V 25
8. Disable ADC module Enable ADC module ADC channel ANO ADC channel AN1 ADC channel AN2 ADC channel AN3 Internal reference voltage VREF VDD lt 1 41 1 External reference voltage System Register 08 ADC Port Configuration Control Register Address Remarks Bit3 0 ADC port configuration control register Select PORTA 0 as normal I O Select PORTA 0 as ADC port ANO Select PORTA 1 as normal Select PORTA 1 as ADC port AN1 Select PORTA 2 as normal Select PORTA 2 as ADC port AN2 Select PORTB 0 as normal I O Select PORTB 0 as ADC port AN3 13 5 67 847 5 ADC conversion time control register Bit2 1 ADC clock period control register Bit3 ADC status flag register A D Conversion Time 15 tAD A D Conversion Time 114 tAD ADC clock period tap tsys tsys tosc 16 clock period tAD 2tsvs tsvs tosc 16 ADC clock period tap 4tsvs tsvs tosc 16 ADC clock period tAD 8tsvs tsvs tosc 16 A D conversion is completed or in processing Set 1 to start A D conversion keep GO DONE 1 when A D conversion is in processing xx ALO System Register 0A 0C ADC Data Register Remarks ADC data low nibble ADC dat
9. Edge Detector Port Interrupt PACR 3 Port interrupt function block diagram 10 7 1 TimerO SH67P847 has one 8 bit timer The timer counter has the following features 8 bit up counting timer counter Automatic re load counter 8 level prescaler Interrupt on overflow from FF to 00 The following is a simplified timer block diagram 4tosc 8 BIT COUNTER System clock Prescaler 2 TM 1 0 The timers provide the following functions Programmable interval timer function Read counter value 7 1 1 Timer0 Configuration and Operation The TimerO consist of an 8 bit write only timer load register TLOL TLOH and an 8 bit read only timer counter TCOL TCOH Each of them has both low order digits and high order digits Writing data into the timer load register TLOL TLOH can initialize the timer counter 7 1 2 Timer0 Mode Register SH67P847 The low order digit should be written first and then the high order digit The timer counter is automatically loaded with the contents of the load register when the high order digit is written or counter counts overflow from FF to 00 Timer Load Register The register H controls the physical READ and WRITE operations Please follow these steps Write Operation Low nibble first High nibble to update the counter Read Operation High nibble first Low nibble followed Load Reg L Load Reg H 6 1
10. 4 0 is used as LED driver I O 5 PORTB 1 is used as control 6 For good EFT performance a 10000pF ceramic capacity should be connected between PORTA 3 and GND FROM ADAPTER 12Vdc RT NTC 24 SH67P847 Ordering Information SH67P847M 8L SOP 25 5 67 847 Package Information SOP 8L Outline Dimensions unit inches mm Se See Detail F ating Plane 5 mme _ o ese Notes 1 The maximum value of dimension D includes end flash 2 Dimension E does not include resin fins 26 SH67P847 Data Sheet Revision History Modify INL Parameter Jun 2009 0 27
11. 8 bit timer counter Latch Reg L The TimerO can be programmed in several different prescalers by setting the TimerO Mode register TOM The clock source pre scale by the 8 level counter first then generate the output plus to timer counter The Timer Mode registers TOM are 3 bit registers used for the timer control as shown in Table 1 Table 1 Timer0 Mode Register 02 Prescaler Divide Ratio Clock Source System clock System clock System clock System clock System clock System clock System clock 11 System clock SH67P847 8 Interrupt Three interrupt sources are available on SH67P847 ADC interrupt TimerO interrupt PORTA interrupt Falling edge Interrupt Control Bits and Interrupt Service The interrupt control flags are mapped on 00 and 01 of the system register They can be accessed or tested by the program Those flags are clear to 0 at initialization by the chip reset System Register Address Remarks 00 Interrupt enable flags register 01 Interrupt request flags register When IEx is set to 1 and the interrupt request is generated IRQx is 1 the interrupt will be activated and vector address will be generated from the priority PLA corresponding to the interrupt sources When an interrupt occurs the PC and CY flag will be saved into stack memory and jump to interrupt service vector address After
12. AC Mx AC CY CY SBCM X B 00010 1bbb xxx xxxx AC Mx Mx AC CY CY SUB X B 00011 Obbb xxx xxxx AC Mx AC 41 CY SUBM X B 00011 1bbb xxx xxxx AC Mx Mx 1 CY EOR X B 00100 Obbb xxx xxxx AC lt Mx 6 AC EORM X B 00100 1bbb xxx xxxx AC Mx Mx 6 AC OR X B 00101 Obbb xxx xxxx AC Mx AC ORM X B 00101 1bbb xxx xxxx AC Mx Mx AC AND X B 00110 Obbb xxx xxxx AC Mx amp AC ANDM X B 00110 1bbb xxx xxxx AC Mx lt MX amp AC SHR 1 2 Immediate Type Mnemonic 11110 0000 000 0000 Instruction Code 0 gt AC 3 01 CY AC shift right one bit Function Flag Change ADI 01000 Mx ADIM Xil 01001 AC Mx lt Mx I CY SBI Xil 01010 iiii lt Mx 1 CY SBIM Xl 01011 iiii xxxx AC Mx lt Mx 1 CY EORIM Xl 01100 iiii Xxxx AC Mx lt Mx ORIM 1 01101 iiii AC Mx lt ANDIM 1 3 Decimal Adjustment Mnemonic 01110 iiii Instruction Code AC Mx lt Mx amp I Function Flag Change DAA X 11001 0110 xxx xxxx AC Mx Decimal adjust for add CY DAS X 11001 1010 xxx xxxx
13. F 3 3V F 5V F 5V Instruction Cycle Time tcy fosc 16MHz fsys 1MHz Frequency Variation RC fosc Frequency Stability RC AF F ADC Converter Electrical Characteristics 3 3V 5 5V GND OV TA 25 C fosc 16MHz fsvs 1MHz unless otherwise specified Parameter in Condition Resolution it GND VAIN VREF Reference Voltage ADC Input Voltage ADC Input Resistor VIN 7 5 0V VREF Input Resistor VIN 7 5 0V Differential Nonlinear Error VREF 5 0V Integral Nonlinear Error VREF VDD 5 0V GND x VAIN x 4 5V Full Scale Error VREF VDD 5 0V Offset Error VREF 5 0V ADC Clock Period fosc 16MHz fsvs 1MHz ADC Conversion Time Set ADCS 0 ADC Conversion Time Set ADCS 1 Low Voltage Reset Electrical Characteristics GND OV 25 C fosc 16MHz fsvs 1MHz unless otherwise specified Parameter Symbol Min Typ Condition LVR Voltage VLVR1 3 3 3 7 V LVR enable Timing Waveform System Clock Timing Waveform System Clock lt tcv y 23 SH67P847 Application Circuits For Reference Only Application 1 Battery Charger 1 Operating Voltage 5 0V 2 Oscillator Internal RC 3 PORTA 2 0 are used as ADC channel for sampling battery voltage charge current and battery temperature
14. Logical OR Carry Flag Logical AND Data Memory RAM Bank ROM Page RAM Bank Stack 21 Table Branch Register Electrical Characteristics Absolute Maximum Ratings Ste senna od Lem 0 3V to 7 0V DC Supply Voltage GND 0 3V to VDD 0 3V Input Output Voltage Operating Ambient Temperature 40 C to 85 Storage Temperature 55 C to 125 SH67P847 Comments Stresses exceed those listed under Absolute Maximum Ratings may cause permanent damage to this device These are stress ratings only Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended Exposure to the absolute maximum rating conditions for extended periods may affect device reliability DC Electrical Characteristics 3 3 5 5V GND OV TA 25 unless otherwise specified Parameter Condition Operating Voltage fosc 16MHz fsvs 1MHz Operating Current fosc 16MHz fsvs 1MHz 5 0V All output pins unload execute NOP instruction WDT off ADC disable LVR off Stand by Current HALT fosc 16MHz fsvs 1MHz 5 0V All output pins unload including all digital input unfloating CPU off execute HALT instruction WDT off ADC disable LVR off Stand by Current STOP fosc 16MHz fsvs 1MHz 5 0V
15. WM outputs high when the PWMS bit is set to 0 If PP 7 PP 0 x PD 7 PD 0 PWM outputs GND level when the PWMS bit is set to 1 15 5 67 847 Programming Notes a Select the PWM module system clock b Set the PWM period cycle by writing proper value to the PWM period control register PWMP First set the low nibble then the high nibble c Set the PWM duty cycle by writing proper value to the PWM duty control register PWMD First set the fine tune nibble then the low nibble then the high nibble d Select the PWM output mode of the duty cycle by writing the PWMS bit in the PWM control register e To output the desired PWM waveform enable the PWM module by writing 1 to the PWM EN bit in the PWM control register PWMC f If the PWM period cycle or duty cycle is needed to be changed the writing flow should be followed as described in step b or step c Then the revised data are loaded into the re load counter and the PWM module starts counting at next period i 01 02 03 04 05 70 7E 7F 80 FO 101 02 03 04 NS luuuuu uum um PWM output oL P nce PWM output duty cycle 7FH X tewm see PWM output period cycle FOH X tewm PP 7 PP 0 FOH PD 7 PD 0 PWM Output Example 1 01 02 03 04 05 06 07 08 09 OD OE OF 101 02 03 04 05 06 07 08 09 00101 02 03 04 05 06 07 08 PWM clock tPwM
16. a medium nibble ADC data high nibble CH1 CHO N E PORTA O Vner Select VREF 00 01 Dx PORTA 1 AN1 Input voltage 10 Dx PORTA 2 AN2 E owe Hi Dx PORTB O AN3 ADC Block Diagram Notes Select A D clock period taD make sure that 1us lt lt 33 4us When the A D conversion is complete an ADC interrupt occurs if the ADC interrupt is enabled The analog input channels must have their corresponding PXCR X A B bits selected as inputs If select I O port as analog input the I O functions and pull high resistor are disabled Bit GO DONE is automatically cleared by hardware when the A D conversion is complete Clearing the GO DONE bit during a conversion will abort the current conversion The A D result register will NOT be updated with the partially completed A D conversion sample 16 tosc wait is required before the next acquisition is started ADC could keep on working in HALT mode and would stop automatic while executing STOP instruction ADC could wake up the device from HALT mode if the ADC interrupt is enabled 14 5 67 847 10 Pulse Width Modulation PWM The SH67P847 consists of one 9 bit PWM module The PWM module can provide the pulse width modulation waveform with the period and the duty being controlled individually The PWMC is used to control the PWM module operation wit
17. ata memory 020 07F 5 67 847 2 2 Configuration of System Register TOM 2 TOM Bit2 0 TimerO Mode register me mz mi mo ems SES mae Bita Lm IRQAD Interrupt request flags register Rw PoRTe oaa regse 0 ADC module operate control register VREFS Bit2 1 ADC channel control register Bit3 ADC reference voltage control register ACR3 Bit3 0 ADC port configuration register ADC conversion time control register GO DONE Bit1 0 ADC clock period control register Bit3 ADC status flag register A2 data low nibble register A6 4 data medium nibble register A8 AT ADC data high nibble register Reserved TBR 1 TBR O Table Branch register INX 1 INX O Pseudo index register DPL 1 DPL O Data pointer for INX low nibble register DPM 1 0 Data pointer for INX middle nibble register DPH 1 DPH O Data pointer for INX high nibble register PACR 1 PACR O PORTA input output control register PBCR 1 PBCR O PORTB input output control register PWM output control register TCK1 TCKO PWM_EN Bit2 1 PWM clock source control register Bit3 PWM output mode control register PP 2 PP 1 0 PWM period low nibble register PP 6 5 PPA PWM period high nibble register PWM duty fine tune regist
18. ator Watchdog Timer RAM 28 X 4 Bits PORTA O ANO VREF System Register PORTA 1 AN1 PORTA 2 AN2 PORTA 3 VPP OTP ROM 4 Bit PORTB 1 PWM 1024 X 16 Bits Bit RAM 96 X 4 Bits ADC Data Memory n VDD Power Circuit GND SH67P847 Pin Name Description PORTB 1 Bit programmable PWM PWM output pin PORTA 3 Bit programmable 1 Open drain type Vector Interrupt Active falling edge GND Ground pin PORTA O Bit programmable ANO ADC input pin VREF ADC VREF input pin PORTA 1 Bit programmable AN1 ADC input pin Power supply pin PORTA 2 Bit programmable AN2 ADC input pin 0 Bit programmable input pin Which Input Output P Power 2 High impedance OTP Programming Pin Description OTP Program Mode 2 ve PORTA 3 Programming high voltage power supply 11V ow rf o wm sc Which Input Output P Power 2 High impedance Functional Description 1 CPU The CPU contains the following functional blocks Program Counter PC Arithmetic Logic Unit ALU Carry Flag CY Accumulator Table Branch Register Data Pointer INX DPH DPM and DPL and Stacks 1 1 PC The PC is used for ROM addressing consisting of 12 bit Page Register PC11 and Ripple Carry Counter PC10 PC9 PC8 PC7 PC6 PC5 4
19. efore programming the OTP chip Of course it s accessible bonding OTP chip only first and then programming code and finally assembling other components Since the programming timing of Programming Interface is very sensitive therefore four jumpers are needed VDD VPP SDA SCK to separate the programming pins from the application circuit as shown in the following diagram Application PCB OTP Chip VPP 5 Writer SDA GND Circuit To Application The recommended steps are the followings 1 The jumpers are open to separate the programming pins from the application circuit before programming the chip 2 Connect the programming interface with OTP writer and begin programming 3 Disconnect OTP writer and shorten these jumpers when programming is completed For more detail information please refer to the OTP writer user manual 19 Instruction Set SH67P847 All instructions are one cycle and one word instructions The characteristic is memory oriented operation 1 Arithmetic and Logical Instruction 1 1 Accumulator Type Mnemonic Instruction Code Function Flag Change ADC X B 00000 Obbb xxx xxxx AC Mx AC CY CY ADCM 00000 1bbb xxx xxxx AC Mx Mx AC CY CY ADD X B 00001 Obbb xxx xxxx AC Mx AC CY ADDM X B 00001 1bbb xxx xxxx AC lt Mx AC CY SBC X B 00010 Obbb xxx xxxx
20. er PD 2 PD 1 PD 0 PWM duty low nibble register PD 6 PD 5 PD 4 PWM duty high nibble register PPACR 2 PPACR 1 PPACR O PORTA pull high control register PPBCR 1 PPBCR O PORTB pull high control register Reserved WDT 1 WDT O Bit2 0 Watchdog timer control register Bit3 WDT overflow flag register Reserved SH67P847 3 ROM The ROM can address 1024 X 16 bits of program area from 000 to 3FF 3 1 Vector Address Area 000 to 004 The program is sequentially executed There is an area address 000 through 004 that is reserved for a special interrupt service routine such as starting vector address Address Instruction Remarks Jump to RESET service routine Jump to ADC interrupt service routine Jump to TIMERO interrupt service routine Jump to Port interrupt service routine JMP instruction can be replaced by any instruction SH67P847 4 Initial State 4 1 System Register State Address Bit 3 Power on Reset Voltage Reset WDT Reset 00 IEAD 00 0 00 0 01 IRQAD 00 0 00 0 02 000 uuu 03 TOL 3 XXXX XXXX 04 TOH 3 XXXX 05 0000 06 00 507 VREFS 508 509 GO DONE Ouuu 0A A2 A1 0B A6 AS A3 0 9 AT u
21. h proper clocks The PWMP is used to control the period cycle of the PWM module output And the PWMD is used to control the duty in the waveform of the PWM module output System Register 15 PWM Control Register PIWMC Remarks PWM output enable control register Bit2 1 PWM clock control register Bit3 PWM output mode of duty cycle control register Shared with 1 port Power on initial Shared with PWM PWM clock tosc Power on initial PWM clock 2 tosc PWM clock 4 tosc PWM clock 8 tosc PWM output normal mode of duty cycle high active Power on initial lt x gt PWM output negative mode of duty cycle low active The PWM output pin is shared with PORTB 1 System Register 16 17 PWM Period Control Register PIWMP Remarks PWM period low nibble register PWM period high nibble register PWM output period cycle PP 7 PP 0 X PWM clock When 7 PP 0 00H PWM will output GND if the PWMS bit is set to 0 When 7 0 PWM will output high level if the PWMS bit is set to 1 System Register 18 1A PWM Duty Control Register PWMD Remarks PWM duty fine tune nibble register PWM duty low nibble register PWM duty high nibble register Average PWM output duty cycle PD 7 0 X PWM clock If PP 7 PP 0 x PD 7 PD 0 P
22. he address is determined by RTNW to return look up value into TBR AC ROM code bit7 bit4 is placed into TBR and bit3 bitO into AC 1 5 Data Pointer The Data Pointer can indirectly address data memory Pointer address is located in register DPH 3 bit DPM 3 bit and DPL 4 bit The addressing range can have 3FFH locations Pseudo index address INX is used to read or write Data memory then RAM address Bit9 0 which comes from DPH DPM and DPL 1 6 Stack The stack is a group of registers used to save the contents of CY amp PC 11 0 sequentially with each subroutine call or interrupt The MSB is saved for CY and it is organized into 13 bits X 4 levels The stack is operated on a first in last out basis and returned sequentially to the PC with the return instructions RTNI RTNW Note The stack nesting includes both subroutine calls and interrupts requests The maximum allowed for subroutine calls and interrupts are 4 levels If the number of calls and interrupt requests exceeds 4 then the bottom of stack will be shifted out that program execution may enter an abnormal state Built in RAM contains general purpose data memory and system register Because of its static nature the RAM can keep data after the CPU entering STOP or HALT 2 1 RAM Addressing Data memory and system register can be accessed in one instruction by direct addressing The following is the memory allocation map System register 000 01F D
23. he port pull high control register 1B 1C independently E When the port is selected as an input port write 1 to the relevant bit in the port pull high control register 1B 1C could turn on the pull high resistor and write 0 could turn off the pull high resistor E When the port is selected as an output port the pull high resistor will be turned off automatically regardless the value of the corresponding bit in the port pull high control register 1B 1C m When is selected as the digital input direction it can active port interrupt by falling edge if port interrupt is enable System Register 05 06 Port Data Register Address Remarks 05 PORTA data register 06 PORTB data register System Register 13 14 Port Control Register Address Remarks 13 PORTA input output control register 14 PORTB input output control register PA B CR n n 0 1 2 3 0 Set I O as an input direction Power on initial 1 Set I O as an output direction System Register 1B 1C Port Pull high Control Register PPBCR 1 0 R W PORTB pull high control register PPA B CR n n 0 1 2 0 Disable internal pull high resistor Power on initial 1 Enable internal pull high resistor Equivalent Circuit for a Single I O Pin Pull high Register o y d Pull high Control 4 T Register 4
24. on SH67P847 will enter the HALT mode In the HALT mode CPU will stop operating But peripheral circuit Timer ADC will keep status After the execution of STOP instruction SH67P847 will enter the STOP mode The whole chip including oscillator will stop operating In the HALT mode SH67P847 can be waked up if any interrupt occurs In the STOP mode SH67P847 can be waked up if port interrupt occurs When CPU is awaked from the HALT STOP by any interrupt source it will execute the relevant interrupt serve subroutine at first Then the instruction next to HALT STOP is executed 17 SH67P847 14 Warm up Timer The device has a built in warm up timer to eliminate unstable state of initial oscillation when oscillator starts oscillating in the following conditions 14 1 Power on Reset In RC oscillator mode fosc 16MHz the warm up counter prescaler divide ratio is 1 215 32768 14 2 Wake up from Stop Mode In RC oscillator mode fosc 16MHz the warm up counter prescaler divide ratio is 1 28 256 15 Code Option 15 1 Watchdog Timer OP WDT 0 Disable Default 1 5 Enable 15 2 Low Voltage Reset OP LVR 0 Disable Default 1 5 Enable 18 SH67P847 In System Programming Notes for OTP The In System Programming technology is valid for OTP chip The Programming Interface of the OTP chip must be set on user s application PCB and users can assemble all components including the OTP chip in the application PCB b
25. the interrupt occurs all interrupt enable flags IEx are clear to 0 automatically so when IRQx is 1 and IEx is set to 1 again the interrupt will be activated and vector address will be generated from the priority PLA corresponding to the interrupt sources 1 2 3 4 5 Inst cycle Instruction Instruction Instruction Execution Execution Execution 1 12 Interrupt Generated Interrupt Accepted Start at vector address Interrupt Nesting During the CPU interrupt service the user can enable any interrupt enable flag before returning from the interrupt The servicing sequence diagram shows the next interrupt and the next nesting interrupt occurrences If the interrupt request is ready and the instruction of execution N is IE enabled then the interrupt will start immediately after the next two instruction executions However if instruction 11 or instruction 12 disables the interrupt request or enable flag then the interrupt service will be terminated ADC Interrupt Bit3 IEAD of system register 00 is the ADC interrupt enable flag When the ADC conversion is complete it will generate an interrupt request IRQAD 1 if the ADC interrupt is enabled IEAD 1 an ADC interrupt service routine will start The ADC interrupt can be used to wake the CPU from HALT mode Interrupt Servicing Sequence Diagram Interrupt The input clock of TimerO is based on system clock as TimerO source The
26. timer overflow from FF to 00 will generate internal interrupt request IRQTO 1 If the interrupt enable flag is enabled IETO 1 a timer interrupt service routine will start Timer interrupt can also be used to wake the CPU from HALT mode Port Falling Edge Interrupt Only the digital input port can generate a port interrupt The analog input can not generate an interrupt The PORTA 3 input pin transitions form to GND would generate an interrupt request 1 Port Interrupt can be used to wake the CPU from the HALT or STOP mode SH67P847 9 Analog Digital Converter ADC The 4 channels and the 10 bit resolution ADC converter are implemented in this micro controller The ADC control registers can be used to define the A D channel number select analog channel reference voltage and conversion clock start A D conversion and set the end of A D conversion flag The A D conversion result register byte is read only The approach for A D conversion Set analog channel and select reference voltage When using the external reference voltage keep in mind that any analog input voltage must not exceed VREF Operating ADC module and select the converted analog channel Set A D conversion clock source GO DONE 1 start A D conversion Systems Register 07 Address Remarks ADC module control register 07 Bit2 1 ADC channel control register Bit3 ADC reference voltage control register
27. uu 0D 0E TBR 2 TBR 1 TBR O 0F INX 2 INX 1 INX O 10 DPL 2 DPL 1 DPL O 11 DPM 2 DPM 1 12 2 1 13 2 1 PACR O 14 PBCR 1 0 515 TCK1 TCKO PWM EN 16 2 17 6 5 518 19 PD 2 PD 1 0 1 6 PD 5 PD 4 1B PPACR 2 PPACR 1 0 1C PPBCR 1 PPBCR O 1D 1E WDT 1 WDT O 1F Legend x unknown unchanged unimplemented read as 0 4 2 Others Initial States Others After any Reset Program Counter PC 000 CY Undefined Accumulator AC Undefined Undefined Data Memory 5 67 847 5 System Clock Oscillator The oscillator generates the basic clock pulses that provide the system clock to supply CPU and on chip peripherals System clock fsvs fosc 16 5 1 Instruction Cycle Time 1 1us for 16MHz oscillator SH67P847 6 I O Ports The MCU provides 6 bi directional ports The PORT data is put in register 05 06 The PORT control register 13 14 controls the PORT as input or output Each 1 port excluding PORTA 3 contains a pull high resistor which is controlled by the value of the corresponding bit in t
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