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S7G2 MCU (High-performance MCU)

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1. Test Item Symbol 1 2 Max Unit conditions 3 SCL input cycle time tse 6 12 240 ns Figure 2 53 Fast mode ee _ 4 SCL input high pulse width 3 6 120 ns SCL input low pulse width tsciL 3 6 120 ns SCL SDA input rise time tsr 120 ns SCL SDA input fall time tsf 120 ns SCL SDA input spike pulse removal tsp 0 1 4 ticeye ns SDA input bus free time when tBur 3 6 120 ns wakeup function is disabled SDA input bus free time when tBuF 3 6 4 ns wakeup function is enabled 120 Start condition input hold time when 15 120 ns wakeup function is disabled START condition input hold time 1 5 tpeye ns when wakeup function is enabled 120 Restart condition input setup time 120 ns Stop condition input setup time tstos 120 ns Data input setup time tspas tiiceye 30 ns Data input hold time tspaH 0 ns SCL SDA capacitive load Cp 550 pF Note internal reference clock IIC cycle cycle Note 1 The value in parentheses apply when ICMR3 NF 1 0 is set to 11b while the digital filter is enabled with ICFER NFE set to 1 Note 2 Cb indicates the total capacity of the bus line Note 3 Renesas recommends using pins that have a letter appe
2. Figure 1 6 Pin assignment for LGA 145 pin Upper perspective view R01DS0262bEU0080 Rev 0 80 134 NE SAS Page 21 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 1 Overview 107 P101 1067 P102 105 P103 104 P104 103 P105 102L P106 101 _ P107 75 P110 TDI 74 P109 TDO SWO 737 P108 TMS SWDIO P800 P300 TCK SWCLK P801 P301 vcc P302 vss P303 P500 vcc P501 vss P502 P304 P503 P305 P504 P306 P505 P307 P506 P308 2 P309 vec P310 vss P311 P015 P312 P014 P200 VREFL P201 MD VREFH R7FS7G2xxxA01CFB RES AVCCO VCC DCDC AVSSO VREFLO VREFHO vss P009 008 VCC P007 VSS P006 P313 P005 P202 P004 P203 P003 P204 P002 P205 P001 P206 P000 P207 VSS VCC USB vec USB DP P512 USB DM P511 VSS USB VBATT 14 xcouT 17 P213 XTAL Q 19 P212 EXTAL 7 20 Figure 1 7 Pin assignment for LOFP 144 Top view 01050262 00080 Rev 0 80 134 NE SAS Page 22 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 1 Overview 5317 P110 TDI 52 P109 TDO SWO 510 P108 TMS SWDIO P500 P300 TCK SWCLK P501 P301 P502 P302 P503 P303 P504 VCL2 VSS vec P304 VSS P305 P015 P306 P014 P307 VREFL P200 VREFH P201 MD R7FS7G2xxxA01CFP ne 550
3. S7 Series 2 Electrical Characteristics 2 9 POR and LVD Characteristics Table 2 46 Power on reset circuit and voltage detection circuit characteristics Item Symbol Min Typ Max Unit Test conditions Voltage detection Power on reset Module stop function 2 5 2 6 2 7 V Figure 2 90 level POR disabled Module stop function 2 0 2 35 2 7 enabled 2 Voltage detection circuit LVDO 4 2 84 2 94 3 04 Figure 2 91 2 2 77 2 87 2 97 Vdeto 3 2 70 2 80 2 90 Voltage detection circuit LVD1 1 2 89 2 99 3 09 Figure 2 92 2 2 82 2 92 3 02 3 2 75 2 85 2 95 Voltage detection circuit LVD2 1 2 89 2 99 3 09 Figure 2 93 2 2 82 2 92 3 02 Vdet2 2 75 2 85 2 95 Internal reset time Power on reset time tpor 4 6 ms Figure 2 90 LVDO reset time ti vpo 0 70 Figure 2 91 LVD1 reset time ti vp1 0 57 Figure 2 92 LVD2 reset time ti vp2 0 57 Figure 2 93 Minimum VCC down time tvorrF 200 us Figure 2 90 Figure 2 91 Response delay 200 us Figure 2 90 to Figure 2 93 LVD operation stabilization time after LVD is enabled Ta E A 10 us Figure 2 92 Hysteresis width LVD1 and LVD2 Vive 80 T my Note 1 Note 2 Note 3 Internal reset signal low is valid Figure 2 90 Power on reset timing taet laet The minimum down time indicates the t
4. 5 tym gt lt Software Standby mode Snooze Normal mode Software Standby mode Duration of normal mode Figure 2 11 Software Standby mode cancellation timing and duration 01050262 0080 Rev 0 80 2tENESAS Page 46 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics 1T dl 5 IRQ Deep Software Standby X4 low is valid Internal reset low is valid Deep Software Standby mode tossy 1 A Reset exception handling start Figure 2 12 Deep Software Standby mode cancellation timing 2 3 5 NMI and IRQ Noise Filter Table 2 17 NMI and IRQ noise filter Item Symbol Min Typ Max Unit Test conditions NMI pulse width tuii 200 ns NMI digital filter disabled 1 2 lt 200 ns X 2 1 1 X 2 gt 200 ns 200 NMI digital filter enabled 3 lt 200 ns 3 5 2 X 3 gt 200 ns IRQ pulse width 200 ns IRQ digital filter disabled 2 lt 200 ns 2 1 1 2 gt 200 ns 200 IRQ digital filter enabled 3 lt 200 ns 3 573 3 gt 20
5. Lr RUN LILI Lu trovs ET DV tbh tubs Figure 2 66 reception timing in normal operation ET_RX_DV ET ERXD 3 0 Preamble 2 67 reception timing when error occurs Figure 2 68 WOL output timing for MII 01050262 00080 Rev 0 80 ESAS Page 83 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change 2 Electrical Characteristics S7 Series 2 3 17 PDC Timing Table 2 32 PDC timing Conditions Middle drive output is selected with the port drive capability bit in the PmnPFS register Output load conditions Voy VCC x 0 5 VCC x 0 5 C 30 pF Item PDC Test Symbol Min Max Unit conditions PIXCLK input cycle time 37 ns Figure 2 69 PIXCLK input high pulse width tPixH 10 ns PIXCLK input low pulse width tPixL 10 ns PIXCLK rising time tPixr 5 ns PIXCLK falling time 5 ns PCKO output cycle time PCKcyc 2 ns Figure 2 70 PCKO output high pulse width 2 ns PCKO output low pulse width tPcKcyc 2 3 ns PCKO rising time tPckr 5 ns PCKO falling time ns VSYNV HSYNC input setup time tevNcs 10
6. 25 Unit mm 1p Index area NOTE NOTE 3 1 DIMENSIONS 1 AND 2 DO NOT INCLUDE MOLD FLASH 2 DIMENSION 3 DOES NOT INCLUDE TRIM OFFSET 3 PIN 1 VISUAL INDEX FEATURE MAY VARY BUT MUST BE LOCATED WITHIN THE HATCHED AREA 4 CHAMFERS AT CORNERS ARE OPTIONAL SIZE MAY VARY Reference Dimensions in millimeters Symbol Min Nom D 13 9 14 0 14 1 E 13 9 14 0 14 1 A2 1 4 15 8 16 0 16 2 15 8 16 0 16 2 m 1 7 0 05 0 15 0 15 0 27 0 09 0 20 0 8 Detail F 2015 Renesas Electronics Corporation All rights reserved Figure 1 6 LQFP 100 pin RO1DS0262EU0080 Rev 0 80 ESAS Page 111 of 111 Oct 12 2015 Revision History Renesas Synergy MCU 5702 Data Sheet Description Date Summary 0 80 Oct 12 2015 First Edition issued All trademarks and registered trademarks are the property of their respective owners Revision History 1 General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products 1 Precaution against Electrostatic Discharge ESD A strong electrical fie
7. 101 111 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics 2 14 Flash Memory Characteristics 2 14 1 Code Flash Memory Characteristics Table 2 52 Code flash memory characteristics Conditions Program Erase 4 to 60 MHz Read FCLK s 60 MHz 4 MHz 20 MHz lt lt 60 MHz Item Symbol Min Typ Max Min Typ Max Unit Programming time 256 byte 256 0 9 13 2 0 4 6 ms Npec lt 100 times 8 KB fane 29 176 13 80 ms 32 KB tp32K 116 704 52 320 ms Programming time 256 byte 1 256 1 1 15 8 0 5 7 2 ms times 8 35 212 16 96 ms 32 KB 2 140 848 64 384 ms Erasure time 8 KB 71 216 39 120 ms Mpeg 100 umes 32 KB 254 864 2 141 480 ms Erasure time 8 KB tesk 85 260 47 144 ms Mages 100 times 32 KB TEK 304 1040 169 576 ms Reprogramming erasure 1 1000 2 1000 2 Times Suspend delay during programming tspp 264 120 us First suspend delay during erasure in tsesp1 216 120 us suspend priority mode Second suspend delay during erasure in tsgsp2 1 7 1 7 ms suspend priority mode Suspend delay during erasure in erasure tsggp 1 7 1 7 ms priority mode Forced stop command tep 32 20 us Data hol
8. 2 SSIRX LCD D0 B DATA 9A 01050262 00080 Rev 0 80 Oct 12 2015 Page 27 of 111 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 1 Overview Pin number Extbus Timers Communication interfaces Analog HMI 9 28 5 o 8 22 2 SM E 5 g e R vo 99 z gt ERER 5 A lt Tj o NI I o N a 5 T n o x o E lt 515 5 2 a 5233 o 8 8 882525210 z 3 3 895 2 2 2 a a 2 9 i lt o 9 5509 09 9 Ole Nie 5 ajaa o 6 80 58 JAT SSITX LCD D0 B DATA 8A Di 97 02 81 VCC 02 4 68 D 2 VSS F4 02 99 83 59 P608 0 0 LCD BCO amp 1 DATA 7A G4 01 100 2 84 60 P609 51 CKE LCD DATA 6A 101 85 61 P610 50 LCD DATA E2 2 02 1 86 611 SDCS F2 103 2 87 P612 08 008 4 104 F1 88 P613 099 009 F1 F2 105 89 P614 010 0010 G8 F1 106 615 LCD DATA 10 B 67 61 107 08 LCD
9. 5 MOSCWTCR 05h tuAINOSCWT MOSCWTCR Xh tMAINOSCWT MOSCWTCR 05h Note 4 When the frequency of the external clock is 24 MHz The Main Clock Oscillator Wait Control Register MOSCWTCR is set to OOh For other settings MOSCWTCR is set to Xh the recovery time can be determined with the following equation MOSCWTCR Xh MOSCWTCR 00h tyaAINOSCWT MOSCWTCR Xh tMAINOSCWT MOSCWTCR 00h Note 5 When the frequency of PLL is 240 MHz The Main Clock Oscillator Wait Control Register MOSCWTCR is set to 00 For other settings MOSCWTCR is set to Xh the recovery time can be determined with the following RO1DS0262EU0080 Rev 0 80 ESAS Page 44 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics Note 6 Note 7 Note 8 Note 9 Note 10 Note 11 equation tspymc MOSCWTCR Xh tspymc MOSCWTCR 00h tMAINOSCWT MOSCWTCR Xh tMAINOSCWT MOSCWTCR 00h The frequency of HOCO is 20 MHz The frequency of MOCO is 8 MHz The sub clock oscillator or LOCO itself continues oscillating in Software Standby mode during Subosc speed mode When the SNZCR RXDREQEN bit is set to 0 86 us is added as power supply return time This defines the duration of normal mode after transition from Snooze to normal mode The following cases are
10. 8 000 0 027 x AVCCO 0 09 x AVCCO V AIN13 10 000 0 025 x AVCCO 0 08 x AVCCO V AIN14 13 333 0 023 x AVCCO 0 06 x AVCCO V Gain error 2 000 1 0 1 0 Gerr1 2 500 1 0 1 0 Gerr2 2 667 1 0 1 0 Gerr3 2 857 1 0 1 0 Gerr4 3 077 1 0 1 0 Gerr5 3 333 1 5 1 5 Gerr6 3 636 1 5 1 5 4 000 1 5 1 5 Gerr8 4 444 2 0 2 0 Gerr9 5 000 2 0 2 0 Gerr10 5 714 2 0 2 0 Gerr11 6 667 2 0 2 0 Gerr12 8 000 2 0 2 0 Gerr13 10 000 2 0 2 0 Gerr14 13 333 2 0 2 0 Offset error Voff 8 8 mV 01050262 00080 Rev 0 80 2tENESAS Page 100 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics Table 2 51 PGA characteristics in differential mode Item Symbol Min Typ Max Unit PGAVSS input voltage range PGAVSS 0 3 0 3 V Differential input voltage range 1 500 AIN PGAVSS 0 5 0 5 V Input voltage range 2 333 0 4 0 4 V Input voltage range 4 000 0 2 0 2 V Input voltage range 5 667 0 15 0 15 V Gain error 1 500 2 5 2 5 2 333 2 2 4 000 1 1 5 667 1 1 01050262 00080 0 80 2 1
11. DRW JPEG Codec PDC Analogs TSN ACMPHS 6 RO1DS0262EU0080 Rev 0 80 Oct 12 2015 ztENESAS Page 9 of 111 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 1 Overview 1 3 Part Numbering R7FS7G27H2A01CBD 1 Package type Figure 1 2 Part numbering scheme BD BGA 224 pins BG BGA 176 pins FC LQFP 176 pins FB LQFP 144 pins FP LQFP 100 pins LK LGA 145 pins Quality ID Software ID Operating temperature 2 40 C to 85 3 40 105 Code flash memory size G 3 MB 4 MB Feature set T Superset Group name 2 S7G2 Core ARM Cortex M4 Series name T High performance Renesas Synergy family Flash memory Renesas microcontroller unit Renesas 01050262 00080 Rev 0 80 Oct 12 2015 134 NE SAS Page 10 of 111 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 1 Overview 1 4 Function Comparison Table 1 15 Functional comparison Parts number RTFS7GITGPADICBD R7FS7GZ7GAAOiCBG RZFS7GZ GGADICFC RIFSTGATGPADICLK R7FS7GZ7GOADICFB ATFS7GZ7GSAUICEP Pin count 224 176 176 145 144 100 Package BGA BGA LQ
12. ICFER FMPE 1 VoL 0 4 loL 20 0 mA ICFER FMPE 1 ETHERC Vou VCC 0 5 1 0 mA VoL 0 4 lo 1 0 mA Ports P205 P206 P407 to P415 VoH VCC 10 20 mA P602 P708 to P713 P813 Fale to VCC 3 3V PA15 01 total 24 pins 24 pins VoL 1 0 loL 20 mA VCC 3 3V Other output pins 0 5 lop 1 0 mA VoL 0 5 lo 1 0 mA Input leakage current RES 5 0 Vin 0V Vin 5 5 V Ports P000 to P007 P200 1 0 Vin 0 V Vin VCC Three state leakage 5V tolerant ports I rsil 5 0 Vin 0 current off state Vin 55V Other ports except for ports PO00 1 0 Vin O V to P007 P200 Vin VCC Input pull up MOS current Ports PO to PB except for ports lp 300 10 VCC 2 7 to 3 6 V P000 to P007 Vin 0 V Input capacitance USB_DP USB_DM USBHS_DP Cin 16 Vin 0 V USBHS DM and ports P003 f 1 MHz P007 P014 P015 P400 P415 25 401 511 512 Other input pins 8 Note 1 SCLO B SDAO B SCL1 A SDA1 A SCL1 B SDA 1 B SCL2 SDA2 Note 2 SCLO A SDAO A Note 3 This is the value when high driving ability is selected with the port drive capability bit in the PmnPFS register Even when high driving ability is selected lop and shift to middle driving ability during Deep Software Standby mode 01050262 00080 Rev 0 80 Oct 12 2015 2tENESAS Page 35 of 111 Under developmen
13. PDcyc Figure 2 29 Dual edge 2 5 GTIOCxY_Z output skew Middle drive buffer 2 4 ns Figure 2 30 0 107 Y AorB Z AorB High drive buffer 4 GTIOCxY 27 output skew Middle drive buffer 4 x28to 13 Y AorB Z2 Aor B High drive buffer 4 GTIOCxY Z output skew Middle drive buffer 6 x20to 13 Y AorB Z2 Aor B High drive buffer 6 OPS output skew tetosk 5 ns Figure 2 31 GTOUUP_x GTOULO_x GTOVUP_x 2 GTOVLO_x GTOWUP_x GTOWLO_x x AorB GPT PWM GTIOCxY_Z output skew tursk 2 0 ns Figure 2 32 delay x 0 to 3 Y AorB Z A generation circuit AGT AGTIO AGTEE input cycle tacyc 100 ns Figure 2 33 AGTIO AGTEE input high level width low level width tackwH 40 ns tackwL AGTOA output cycle tacvc2 62 5 ns ADC12 12 bit A D converter trigger input pulse width ttrew 1 5 Figure 2 34 KINT Key interrupt input low level width 250 ns Figure 2 35 Note 1 tp PCLKB cycle PCLKD cycle Note 2 This skew applies when the same driver is used If the of the middle and high drivers is mixed operation is not guaranteed Note 3 The load is 30 pF Note 4 Constraints on AGTIO input 2 tpeyc PCLKB cycle lt Port Figure 2 27 ports input timing R01DS0262bEU0080 Rev 0 80 ESAS Page 60 of 111 Oct 12 2015 Under development Preliminary document Specifi
14. The 2D Drawing Engine DRW provides very flexible functions that can support almost any object geometry rather than being bound to only a few specific geometries such as lines triangles or circles The edges of every object can be independently blurred or antialiased Rasterization is executed on the bounding box of the object from left to right and top to bottom and performs one pixel per clock The DRW can also raster bottom to top to optimize the performance in certain cases In addition certain optimization methods are available to avoid rasterization of many empty pixels of the bounding box The distances to the edges of the object are calculated by a set of edge equations for every pixel of the bounding box These edge equations can be combined to describe the entire object If a pixel is inside the object it is selected for rendering If it is outside it is discarded If it is on the edge an alpha value can be chosen proportional to the distance of the pixel to the nearest edge for antialiasing Every pixel that is selected for rendering can be textured The resulting aRGB quadruple can be modified by a general raster operation approach independently for each of the four channels The aRGB quadruples can then be blended with one of the multiple blend modes of the DRW The DRW provides two inputs texture read and framebuffer read and one output framebuffer write The internal color format is always aRGB 8888 The color formats fr
15. 12 Bit D A Converter DAC12 in User s Manual Temperature Sensor TSN High Speed Analog Comparator ACMPHS RO1DS0262EU0080 Rev 0 80 Oct 12 2015 The on chip temperature sensor can be used to determine and monitor the die temperature for reliable operation of the device The sensor outputs a voltage directly proportional to the die temperature and the relationship between the die temperature and the output voltage is linear The output voltage is provided to the ADC for conversion and can be further used by the end application See section 48 Temperature Sensor TSN in User s Manual Analog comparators can be used to compare a test voltage with a reference voltage and to provide a digital output based on the result of conversion Both the test voltage and the reference voltage can be provided to the comparator from internal sources such as D A converter output and internal reference voltage and an external source with or without an internal PGA Such flexibility is useful in applications that require go no go comparisons to be performed between analog signals without necessarily requiring A D conversion See section 49 High Speed Analog Comparator ACMPHS in User s Manual ztENESAS Page 6 of 111 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 1 Overview Table 1 11 Human machine interfaces Feature Key Interrupt Function KINT Fu
16. 16 35 o etecting j 5 unit power consumption function enabled gt 2 Increase When a low speed on chip 9 9 5 when the oscillator LOCO is in use RTC and AGT are When a crystal oscillator 10 1 0 E operating for low clock loads is in use 8 When crystal oscillator 3 0 3 0 8 for standard clock loads is a in use RTC operating while When a crystal 0 9 0 9 lt 2 0 V VCC is off with the oscillator for low clock VCC 0V battery backup loads is in use function only the n 1 6 1 6 E 3 3 V and sub clock 0 oscillator operate When a crystal 17 17 2 0 V oscillator for standard VCC 0V clock loads is in use 33 33 Vann 8 8 V VCC 0V Analog During 12 bit A D conversion Alcc 0 8 1 1 0 8 1 1 mA Supply During 12 bit A D conversion with S H amp 23 33 23 33 ma current PGA 1ch 1 3 1 3 mA ACMPHS 1unit 100 150 100 150 AVCC22 7V Temperature sensor 0 1 0 2 0 1 0 2 mA During D A conversion Without AMP output 0 1 0 2 0 1 0 2 mA it With output 05 05 08 Waiting for A D D A conversion all units 0 9 1 6 0 9 1 6 mA AID D A converter in Standby mode all units 2 6 2 6 Reference During 12 bit A D conversion unit 0 70 120 70 120 pA Supr Waiting for 12 bit A D conversion unit 0 i 00
17. Caution Permissible output current lot Maximum of all output max ZIOL max mA To protect the reliability of the MCU the output current values should not exceed the values in this table The average output current indicates the average value of current measured during 100 us Note 1 This is the value when low driving ability is selected with the port drive capability bit in the PmnPFS register The selected driving ability is retained in Deep Software Standby mode Note 2 This is the value when middle driving ability is selected with the port drive capability bit in the PmnPFS register The selected driving ability is retained in Deep Software Standby mode Note 3 This is the value when high driving ability is selected with the port drive capability bit in the PmnPFS register When the following ports are configured for high driving ability they shift to middle driving ability during Deep Software Standby mode ports 203 to P207 407 to P415 602 P708 to P713 813 PA12 to PA15 01 Note 4 Except for ports 000 to 007 P200 which are input ports 2 2 4 Voi and Other Characteristics Table 2 6 VoL and other characteristics Item Symbol Min Typ Max Unit Test conditions Output voltage VoL 0 4 V loj 3 0 mA VoL x 0 6 loL 6 0 mA IIC 2 VoL 0 4 loL 15 0 mA
18. ET ERXDS3 to ET ERXDO RX ER ETO COL Input Input collision detection signals ET1 COL ETO WOL Output Receive Magic packets ET1 WOL ETO MDC Output Output reference clock signals for information transfer via ET MDIO ET1 MDC ETO MDIO VO Input or output bidirectional signals for exchange of management data with ET1_MDIO PHY LSI SDHI SDOCLK SD1CLK Output SD clock output pin SDOCMD SD1CMD I O Command output response input signal pin SDODATO to y o SD data bus pins MMC data bus pins SDODATT SD1DATO to SD1DAT7 SDOCD SD1CD Input SD card detection pin SDOWP SD1WP Input SD write protect signal 01050262 00080 Rev 0 80 Oct 12 2015 ztENESAS Page 15 of 111 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 1 Overview Function Signal yo Description Analog power AVCCO Input Analog voltage supply pin for the analog Connect this pin to VCC supply AVSSO Input Analog ground pin Connect this pin to VSS VREFHO Input Analog reference voltage supply pin for the A D converter Connect this pin to VCC when not using the A D converter VREFLO Input Analog reference ground pin for the A D converter Connect this pin to VSS when not using the A D converter VREFH Input Reference voltage input pin for the 12 bit A D converter unit 1 and D A converter Thi
19. P FBGA176 13x13 0 80 PRBG0176GA A 0 59 D w S A z aul yi 8 5 lt 262526947 VUVEM 4250 0505 5 lt 20 pia R 000000000909000 Reference Dimension in Millimeters Symbol ur 7 n em D 180 0000 0000 E 130 600 6 OOO09 m 045 020 X 19 d A 035 040 0 45 nao b 0 45 0 50 0 55 12 3 4 5 6 7 8 9 10 11 12 13 14 15 x 0 08 ob S y 040 yi 020 Sp ER SE CHEER Zp 0 9 ZE 0 9 Figure 1 2 BGA 176 pin R01DS0262EU0080 Rev 0 80 24 NE S AS Page
20. ns Figure 2 71 VSYNV HSYNC input hold time tevNcH 5 ns PIXD input setup time 10 ns PIXD input hold time tPixpH 5 ns Note 1 tpgcyc PCLKB cycle PIXCLK input tpixcyc Figure 2 69 PCKO pin output PDC input clock timing teckeye Figure 2 70 Figure 2 71 PDC output clock timing PIXCLK VSYNC HSYNC PIXD7 to PIXDO PDC AC timing 01050262 00080 Rev 0 80 Oct 12 2015 Page 84 of 111 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics 2 3 18 Graphics LCD Controller Timing Table 2 33 Graphics LCD controller timing Conditions LCD CLK High drive output is selected with the port drive capability bit in the PmnPFS register LCD DATA Middle drive output is selected with the port drive capability bit in the PmnPFS register Test Item Symbol Min Typ Max Unit conditions 2 LCD_EXTCLK input clock frequency tEcyc 60 1 MHz Figure 2 72 LCD EXTCLK input clock low pulse width tw 0 45 0 55 tEcyc LCD EXTCLK input clock high pulse width twn 0 45 0 55 LCD CLK output clock frequency 60 1 2 Figure 2 73 LCD CLK output clock low pulse width tio 0 4 0 6 li Figure 2 73 LCD output clock high pulse width ti ou 0 4 0 6 4 Figure 2 73 LCD data output delay timing top 3 5 2 4 2 ns Figure 2 74 LCD data output
21. 12 bit A D Converter ADC12 The Secure Digital Host Interface SDHI and MultiMediaCard MMC interface provide the functionality required to connect a variety of external memory cards with the MCU The SDHI supports both 1 bit and 4 bit buses for connecting different memory cards that support SD SDHC and SDXC formats When developing host devices that are compliant with the SD Specifications you must comply with the SD Host Ancillary Product License Agreement SD HALA The MNC interface supports 1 bit 4 bit and 8 bit MMC buses that provide eMMC 4 51 JEDEC Standard JESD 84 B451 device access This interface also provides backward compatibility and supports for high speed SDR transfer modes See section 43 SD MMC Host Interface SDHI in User s Manual Functional description This MCU incorporates up to two units of a 12 bit successive approximation A D converter In Unit O up to 13 analog input channels are selectable In Unit 1 up to 12 analog input channels a temperature sensor output and an internal reference voltage are selectable for conversion The A D conversion accuracy is selectable from 12 bit conversion 10 bit conversion and 8 bit conversion making it possible to optimize the tradeoff between speed and resolution in generating a digital value See section 46 12 Bit A D Converter ADC12 in User s Manual 12 bit D A Converter DAC12 This MCU includes a 12 bit D A converter with an output amplifier See section 47
22. 3 VCC_DCDC VREFLO VLO VREFHO VLO P008 VSS P007 VCL1 P006 P205 P005 P206 P004 P207 P003 USB P002 USB DP P001 USB DM P000 VSS USB XCOUT 1 P213 XTAL 13 P212 EXTAL 14 Figure 1 8 Pin assignment for LOFP 100 pin Top view 01050262 1 0080 Rev 0 80 ztENESAS Page 23 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 1 Overview 1 7 Pin Lists Pin number Extbus Timers Communication interfaces Analog HMI 9 28 5 o9 8 gt 2 N g e R vo 99 a gt ERER 5 Bl N E O didi I 9 e e 5 n o x o E lt 2 5 2 a 95 gl 6 658 6 E E 2825858 z 2 25 8 amp 8 85 2 2 a 21 9 i lt o 9 5509 09 9 Nie 5 lt lt o 1 1 400 SCK4 SCK7 SCLO AUDI ETT T ADTR IRQO C6A_ B X CL G1 A K K B P15 815 2 2 2 401 GTIO CTXO CTS4 TXD7 SDAO ETO _ IRQ5 RGA C6B_ B B A MDC MDC DS B A SMOS 17 SSDA 7A 4 14 3 M13 3 3 P402 RTCIC CRXO RXD7 ETO _ IRQ4 O0 B 0 B MDIO MDIO DS SMIS O1B O7 A SSCL 7A N15 12 4 KM 4 4 403 GTIO RTCIC CTS7 5515 ET1_ P
23. DATA 9B Ge PA11 LCD_ DATA 18_ G5 TCLK 12 64 108 09 LCD DATA 8B Hz E PA13 0 TDAT 14 A1 H5 62 109 PA10 LCD DATA 7B G2 15 GTIO A2 C9A B G1 TDAT P813 GTIO A3 H3 63 10 61 90 62 vcc H2 H3 11 62 97 63 55 HY 412 Ht 92 64 J1 07 GTIO C10A B 42 06 GTIO C108 B 3 05 GTIO CTS7 11 _ B B 4 GTIO SCK7 C11B_ B B 45 RXD7 IRQ9 _ SMIS O7 B SSCL 7B H6 02 TXD7 IRQ10 B SMOS I7 B SSDA 7B H2 1 LCD DATA 6B 00 LCD_ DATA 5B K5 4 115 607 LCD DATA 4B 116 P606 LCD_ DATA 3B 2 117 H2 93 P605 011 0011 2 03 118 64 94 P604 012 0912 119 H3 95 P603 013 0013 L1 Ki 120 96 65 P602 SDCL LCD K K DATA 4A 12 121 2 97 66 P601 WR LCD WRO DATA RO1DS0262EU0080 0 80 RENESAS Page 28 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 1 Overview Pin
24. Electrical Characteristics SDRAM command SDCLK A15 to 0 Column address D15 to DO Note Address pins are for output of the precharge setting command Precharge sel for the SDRAM Figure 2 20 SDRAM single read timing 01050262 00080 Rev 0 80 ESAS Page 53 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics SDRAM command ACT WR PRA gt 14 gt 4 gt sek NA AZF ANNY WY ANZ VY VAN 2 tap2 2 2 lt gt lt gt A15 to 0 Column address tap2 tap tap DQMn twop2 twpH2 4 Note Address pins for output of the precharge setting command Precharge sel for the SDRAM Figure 2 21 SDRAM single write timing RO1DS0262EU0080 Rev 0 80 ESAS Page 54 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics A15 to D15 to DO Note Address pins are for output of the precharge setting command Precharge sel for the SDRAM Figure 2 22 SDRAM multiple read timing 01050262 00080 Rev 0 80 ESAS Page 55 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tenta
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26. Renesas Electronics product for which the product is not intended by Renesas Electronics 6 You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges 7 Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or systems manufactured by you 8 Please contact a Re
27. TXD4 CTS9 SCL1 SSLB 55 ETO 5000 TSCA 1 1 4 _ OVRC A joa 81 WOL 105 SMOS A DS A SSDA 4A Dii 13 52 Cio 44 CACR 204 GTIW GTIO USB SCK4 5 9 SCLO RSPC SSISC ETO 5000 TSO EF_A OVRC A K1A RX_D 4 B URB v A DS B12 011 53 9 45 203 19 GTIO CTXO CTS2 TXD9 MOSI ETO_ 5000 TSCA 2 5 _ A A B_A COL 5 105 SMOS I9 AI SSDA 9A A12 812 54 59 6 P202 1 GTIO CRXO SCK2 RXD9 MISO ETO SDOD IRQ3 LCD BC1 C5B_ A ERXD 6 DS TCON A SMIS 2 3B O9 Al SSCL 9A E10 12 55 8 7 P313 20 _ 5000 LCD ERXD TCON 3 2B F9 jen se P314 A21 LCD TCON 1B Bit 57 315 22 LCD TCON 0B a 58 P900 A23 LCD CLK B BM 59 T 901 LCD DATA 15 B AM P902 LCD DATA 23 B C10 510 60 09 48 T VSS D10 09 61 08 49 VCC po 903 GTIO SDOC 7 _ D B co P904 GTIO C7B_ B A10 410 62 8 50 VCL1 B10 810 63 88 51 34 vss A9 9 64 7 52 35 89 65 87 53 36 A8 8 66 54 37 DCDC H8 B E a E P913 F8 69 67 7 55 38 RES amp 68 86 56 39 MD 201 B8 69 cs 57 40 200 NMI B7 P912 GTIO C8A_ B 911 GTIO
28. Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 1 Overview Function Signal y o Description QSPI QSPCLK Output QSPI clock output pin QSSL Output QSPI slave output pin QIOO to QIO3 Data0 to Data3 CAN CRXO0 CRX1 Input Receive data CTXO CTX1 Output Transmit data USBFS VCC USB Input Power supply pins VSS USB Input Ground pins USB DP VO D pin of the USB on chip transceiver This pin should be connected to the D pin of the USB bus USB_DM D pin the USB on chip transceiver This pin should be connected to the D pin of the USB bus USB VBUS Input USB cable connection monitor pin This pin should be connected to VBUS of the USB bus The VBUS pin status connected or disconnected can be detected when the USB module is operating as a function controller USB EXICEN Output Low power control signal for external power supply OTG chip USB VBUSEN Output VBUS 5 V supply enable signal for external power supply chip USB OVRCURA Input External overcurrent detection signals should be connected to these pins USB OVRCURB VBUS comparator signals should be connected to these pins when the OTG power supply chip is connected USB ID Input MicroAB connector ID input signal should be connected to this pin during operation in OTG mode USBHS VCC USBHS Input Power supply pin VSS1 USB
29. error reset SRAM DED error reset Bus master MPU error reset e Bus slave MPU error reset e Stack pointer error reset Software reset See section 6 Resets in User s Manual Low Voltage Detection LVD The Low Voltage Detection LVD monitors the voltage level input to the VCC pin and the detection level can be selected using a software program See section 8 Low Voltage Detection LVD in User s Manual Clock e Main clock oscillator MOSC e Sub clock oscillator SOSC e High speed on chip oscillator HOCO e Middle speed on chip oscillator MOCO e Low speed on chip oscillator LOCO e PLL frequency synthesizer e Independent Watchdog Timer on chip oscillator Clock out support See section 9 Clock Generation Circuit in User s Manual Clock Frequency Accuracy Measurement Circuit CAC The Clock Frequency Accuracy Measurement Circuit CAC is used to check the system clock frequency with a reference clock signal by counting the number of pulses of the system clock to be measured The reference clock can be provided externally through a CACREF pin or internally from various on chip oscillators Event signals can be generated when the clock does not match or measurement ends This feature is particularly useful in implementing a fail safe mechanism for home and industrial automation applications See section 10 Clock Frequency Accuracy Measurement Circuit CAC in User s Manual Low Po
30. function is enabled 300 START condition input hold time tiiccye 300 ns when wakeup function is disabled START condition input hold time 15 1 5 ns when wakeup function is enabled 300 Repeated START condition input tstas 300 ns setup time STOP condition input setup time tstos 300 ns Data input setup time tspas 50 ns Data input hold time tepAH 0 ns SCL SDA capacitive load Cp 400 pF 01050262 00080 Rev 0 80 24 NE S AS Page 75 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics Note tiiceyc internal reference clock cycle PCLKB cycle Note 1 The value in parentheses apply when ICMR3 NF 1 0 is set to 11b while the digital filter is enabled with ICFER NFE set to 1 Note 2 Only supported for SCLO A SDAO A SCL2 and SDA2 Note Renesas recommends using pins that have a letter appended to their names for instance or B to indicate group membership For the IIC interface the AC portion of the electrical characteristics is measured for each group Note 4 This is only 2 channel A and B and 0 A Others are not specified Table 2 28 timing 2 Conditions Setting of the SCLO A SDAO A pins is not required with the port drive capability bit in the PmnPFS register
31. responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics products 11 This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics 12 Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products or if you have any other inquiries Note 1 Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics 34 NE SAS SALES OFFICES Renesas Electronics Corporation http Wwww renesas com Refer to http www renesas com for the latest and detailed information Renesas Electronics America Inc 2801 Scott Boulevard Santa Clara CA 95050 2549 U S A Tel 1 408 588 6000 Fax 1 408 588 6130 Renesas Electronics Canada Limited 9251 Yonge Street Suite 8309 Richmond Hill Ontario Canada L4C 9T3 Tel 1 905 237 2004 Renesas Electronics Europe Limited Dukes Meadow Millboard Road Bourne End Buckinghamshire SL8 5FH U K Tel 44 1628 585 100 Fax 44 1628 585 900 Renesas Electronics Europe GmbH Arcadiastrasse 10 40472 D sseldorf Germany Tel 49 211 6503 0 Fax 49 211 6503 1327 Renesas
32. rising time 0 8 to 2 0 V tpr 2 Figure 2 75 LCD data output falling time 2 0 to 0 8 V tpr 2 Note 1 Parallel RGB888 666 565 Maximum 54 MHz Serial RGB888 Maximum 60 MHz 4x speed Note 2 Renesas recommends using pins that have a letter appended to their names for instance A or B to indicate group membership For the Graphics LCDC interface the AC portion of the electrical characteristics is measured for each group When group A and B combinations are used the LCD data output delay times are minimum 5 0 ns and maximum 5 5 ns 1 2 Vcc LCD EXTCLK poyc tEcyc Figure 2 72 LCD_EXTCLK clock input timing LCD_CLK Figure 2 73 LCD_CLK clock output timing R01DS0262EU0080 Rev 0 80 Oct 12 2015 2 1 85 of 111 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics LCD CLK Output on falling edge LCD DATA23 to LCD DATAO LCD TCONG to LCD TCONO Output on rising edge Figure 2 74 Display output timing Figure 2 75 LCD output rise and fall times 01050262 00080 Rev 0 80 ESAS Page 86 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics 2 4 USB Characteristics 2 4 1 USBHS Timin
33. speed only for the host controller transfer as defined in the Universal Serial Bus Specification 2 0 The module has an internal USB transceiver and supports all of the transfer types defined in the Universal Serial Bus Specification 2 0 The USB has buffer memory for data transfer providing a maximum of 10 pipes PIPE1 to 9 be assigned any endpoint number based on the peripheral devices used for communication or based on the user system See section 32 USB 2 0 Full Speed Module USBFS in User s Manual RO1DS0262EU0080 Rev 0 80 134 NE SAS Page 5 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 1 Overview Table 1 9 Communication interfaces Feature Functional description USB 2 0 High Speed Module USBHS This MCU incorporates a USB 2 0 High Speed module USBHS The USBHS is a USB controller that is equipped to operate as a host controller or a device controller As a host controller the USBHS supports high speed transfer full speed transfer and low speed transfer as defined in the Universal Serial Bus Specification 2 0 As a device controller the USBHS supports high speed transfer and full speed transfer as defined in the Universal Serial Bus Specification 2 0 The USBHS has an internal USB transceiver and supports all of the transfer types defined in the Universal Serial Bus Specification 2 0 The USBHS has FIFO bu
34. using pins that have a letter appended to their names for instance A or B to indicate group membership For the SSI interface the AC portion of the electrical characteristics is measured for each group SSISCKn Figure 2 54 SSI clock input output timing RO1DS0262EU0080 Rev 0 80 ESAS Page 77 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics SSISCKn input or output SSIWSn SSIDATAn input tsr SSIWSn 55 output Figure 2 55 SSI data transmit receive timing SSICR SCKP 0 SSISCKn input or output SSIWSn SSIDATAn input tsr SSIWSn SSIDATAn output Figure 2 56 SSI data transmit receive timing SSICR SCKP 1 SSIWSn input SSIDATAn output lprRw MSB bit output delay from SSIWSn change time for Slave transmitter when DEL 1 SDTA 0 or DEL 1 SDTA 1 SWL 2 0 DWL 2 0 Figure 2 57 SSI data output delay from SSIWSn change time RO1DS0262EU0080 Rev 0 80 ESAS Page 78 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics 2 3 15 SD MMC Host Interface Timing Table 2 30 SD MMC host interface signal timing Conditions High drive output is selected with the port drive capability bit in the PmnPF
35. valid uses of the main clock oscillator The crystal resonator is connected to main clock oscillator The external clock is input to main clock oscillator The following cases are excluded The main clock resonator is not connected to the system clock source Used when transitioning from Software Standby to normal mode The same value as set in MOSCWTCR MSTS 3 0 Duration of normal mode must be maintained longer than the main clock oscillator wait time MOSCWTCR Main Clock Oscillator Wait Control Register tcycmosc Main clock oscillator frequency cycle RO1DS0262EU0080 Rev 0 80 ESAS Page 45 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics Oscillator system clock Oscillator not the system clock Software Standby mode tsayec tsaysc When stabilization of the system clock oscillator is slower Oscillator system clock tspyoscwt tspysea Oscillator not the system clock tssyoscwt EH Software Standby mode gt tsBvex 5 tspysc tsevLo When stabilization of an oscillator other than the system clock is slower Main clock oscillator system clock Ml
36. 0 Note 55 11 A output is not supported at these specifications internal reference clock cycle tpeyc PCLK cycle Note 1 Cb indicates the total capacity of the bus line RO1DS0262EU0080 Rev 0 80 ESAS Page 67 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics SSDAO to SSDA9 SSCLO to SSDL9 Test conditions Vin VCC x 0 7 V VCC 0 3 Vor 0 6 V 6 ICFER FMPE 0 Vor 0 4 V 15 mA ICFER FMPE 1 Note 1 5 P and Sr indicate the following S Start condition P Stop condition Sr Restart condition Figure 2 43 SCI simple IIC mode timing 01050262 00080 Rev 0 80 ESAS Page 68 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics 2 3 11 SPI Timing Table 2 25 SPI timing Conditions Middle drive output is selected with the port drive capability bit in the PmnPFS register Test Item Symbol Min Max Unit conditions SPI RSPCK clock cycle Master sPcyc 2 PCLKA 60 MHz and und
37. 0 A RGA A KROO SMIS LK A O0 A SSCL 0A P2 2 109 P800 014 0014 R2 R1 2 10 P801 015 0015 5010 4 808 P809 PS E 5 P810 R3 2 135 f P802 SD1D LCD 5 DATA 2B P4 82 136 803 5010 LCD 6 DATA 1B 3 137 P804 5010 LCD DATA 0B 15 P811 CTXO 16 P812 CRXO 26 7 138 VCC 18 4 139 112 VSS R4 R3 40 k4 113 76 P500 GriU erio USB QSPC SD1C 01 IVREF A0 11 _ VBUS LK 0 N4 4 41 4 14 7 501 GTIV_ GTIO USB_ TXD5 QSSL SD1C AN116 IVREF IRQ11 C11B_ OVRC Al MD 1 A URA_ SMOS B 15_ SSDA 54 42 4 15 78 502 GTIW GTIO USB_ RXD5 SD1D 01 IVCM IRQ12 C12A OVRC _ ATO 7 URB SMIS B O5 AI SSCL P5 143 ks 116 79 503 GTET 08 56 5 5 QIO1 SD1D 117 12 AT1 B NB R5 5 44 15 17 80 504 USB 1 SCK6 CTS5 QIO2 5010 ANO1 RGD C13A DB B 2 8 Ms 6 145 6 18 505 GTIO RXD6 5010 118 IRQ14 C13B B SMIS O6 B SSCL 6 B 6 65 146 6 19 506 TXD6 SD1C 01 IRQ15 _ D 9 SMOS l6 B SSDA 6 B 47 507 CTS5 SD1W AN119 B P R01DS0262EU0080 Rev 0 80 RENESAS Page 29 of 111 Oct 12 2015 Under de
38. 0 ns Note 200 ns minimum Software Standby mode Note 1 tpcyc indicates the PCLKB cycle Note 2 indicates the cycle of the NMI digital filter sampling clock Note 3 indicates the cycle of the IRQi digital filter sampling clock Figure 2 13 NMI interrupt input timing Figure 2 14 IRQ interrupt input timing RO1DS0262EU0080 Rev 0 80 ESAS Page 47 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics 2 3 6 Bus Timing Table 2 18 Bus timing Condition 1 When using the CS area controller CSC BCLK EBCLK 8 to 60 MHz VCC AVCCO VCC USB VBATT 2 7 to 3 6 V VREFH VREFHO 2 7 V to AVCCO VCC_USBHS AVCC USBHS 3 0 to 3 6 V Output load conditions VOH x 0 5 VOL VCC x 0 5 C 30 pF EBCLK High drive output is selected with the port drive capability bit in the PmnPFS register Others Middle drive output is selected with the port drive capability bit in the PmnPFS register Condition 2 When using the SDRAM area controller SDRAMC BCLK SDCLK 8 to 120 MHz VCC AVCCO VCC USB VBATT 3 0 to 3 6 V VREFH VREFHO 3 0 V to AVCCO VCC_USBHS AVCC USBHS 3 0 to 3 6 V Output load conditions VOH x 0 5 VOL VCC x 0 5 C 15 pF High drive output is selected with the port drive capability bit in the PmnPFS register Conditi
39. 00 to 002 VREFHO 0 25 V Absolute accuracy 2 5 5 5 LSB DNL differential nonlinearity error 1 0 2 0 LSB INL integral nonlinearity error 1 5 3 0 LSB Holding characteristics of sample and hold 20 us circuits Dynamic range 0 25 VREFH V 0 0 25 Channel dedicated Conversion time 1 Permissible signal 0 88 0 667 2 us Sampling in 40 states sample and hold operation at Source impedance circuits not in use PCLKC 60 MHz 1kQ ANO000 to 002 Offset error F 1 0 2 5 LSB Full scale error 1 0 22 5 LSB Absolute accuracy 2 0 4 5 LSB DNL differential nonlinearity error 0 5 1 5 LSB INL integral nonlinearity error 1 0 2 5 LSB High precision Conversion 1 Permissible signal 0 48 0 267 us Sampling in 16 states channel operation at source impedance 003 to 006 PCLKC 60 1 Offset error 1 0 2 5 LSB Full scale error 1 0 2 5 15 Absolute accuracy 2 0 4 5 LSB DNL differential nonlinearity error 0 5 1 5 LSB INL integral nonlinearity error 1 0 2 5 LSB Normal precision Conversion time 1 Permissible signal 0 88 0 667 2 us Sampling in 40 states channel Operation at Source impedance ANO16 to ANO21 PCLKC 60 MHz 1 Offset error x1 0 15 5 LSB Full scale error x1 0 45 5 LSB Absolute accuracy 2 0 7 5 LSB DNL differential nonlinearity error 0 5 4 5 LSB INL integral non
40. 015 P100 to P115 VO General purpose input output pins P200 Input General purpose ilnput pin P200 to P207 P212 I O General purpose input output pins P213 P300 to P315 VO General purpose input output pins P400 to P415 VO General purpose input output pins P500 to P515 VO General purpose input output pins P600 to P615 VO General purpose input output pins P700 to P713 VO General purpose input output pins P800 to P813 VO General purpose input output pins P900 to P915 VO General purpose input output pins PAOO to PA15 VO General purpose input output pins PBOO to PBO7 General purpose input output pins GLCDC LCD DATA23 to Output Data output pin for panel LCD DATAO LCD TCONS to Output Output pins for panel timing adjustment LCD TCONO LCD CLK Output Panel clock output pin LCD EXTCLK Input Panel clock source input pin 01050262 00080 Rev 0 80 Oct 12 2015 134 NE SAS Page 16 of 111 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 1 Overview Function Signal 1 0 Description PDC PIXCLK Input Image transfer clock pin VSYNC Input Vertical synchronization signal pin HSYNC Input Horizontal synchronization signal pin PIXDO to PIXD7 Input 8 bit image data pins PCKO Output Output pin for dot clock R01DS0262EU0080 0 80 lt 17 111 12 2015 Under development Preli
41. 08 GTIO USB 1 RXD3 ETO RMIIO 05 TS4 IRQ7 WLO C10B DA _ CRS CRS S ID B LA SMIS DV SSCL RO1DS0262EU0080 Rev 0 80 234 NE S AS Page 25 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 1 Overview Pin number Extbus Timers Communication interfaces Analog HMI 9 28 5 o 8 22 2 NES E 5 g e R o 99 z gt ERER 5 A N o I o N ja 5 N n S x lt I rir a gt 8 a 5 83 5 533 o 8 8 amp 885525210 z 8 895 2 2 2 2 9 i lt o 9 5509 09 9 5 ajaaa o A15 A15 4 13 36 25 P407 RTCO 058 CTS4 SDAO SSLB ETO ADTR TS3 UT VBUS A B EXOU EXOU T B B13 c13 45 1 37 26 55 USB B14 Bi4 46 A12 38 27 USB_ DM 14 A14 a 12 39 28 USB DP A13 48 404 29 USB C13 c12 49 41 30 207 17 SSLB TS2 2A 012 50 10 42 31 206 WAIT amp GTIU USB RXD4 SDA1 5518 SSIDAJETO_L ETO_L 5000 TS1 00 VBUS A LA MA 1 A INKST INKST 2 DS EN A SMIS A A 04 AI SSCL 4A C12 E12 51 A10 43 32 205 16 GriV USB
42. 107 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series Appendix 1 Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS Typ P LFQFP176 24x24 0 50 176 176P6Q A FP 176E FP 176EV 1 8g NOTE 1 DIMENSIONS 1 AND 2 DO NOT INCLUDE MOLD FLASH 2 DIMENSION 3 DOES NOT INCLUDE TRIM OFFSET section Reference Dimension Millimeters Symbol Min Nom Max 23 9 24 0 24 1 23 9 24 0 24 1 A 1 4 Hp 25 8 26 0 26 2 He 25 8 26 0 26 2 A 0 05 0 1 0 15 bp 0 15 0 20 0 25 lt b 018 T 0 09 0 145 0 20 a L i Cy 0 125 0 8 8 05 x 0 08 Detail F y 010 Zp 1 25 Ze 1 25 L 0 35 0 5 0 65 L 1 0 Figure 1 3 LQFP 176 pin RO1DS0262EU0080 Rev 0 80 tENESAS Page 108 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative an
43. 2 P306 11 SCK6 LCD ES DATA 18 A D4 5 81 D6 65 43 P305 10 410 TXD6 IRQ8 LCD _ DATA SMOS 17 A l6 SSDA 82 4 66 44 P304 19 AQ GTIO RXD6 IRQ9 LCD _ SMIS 16 A O6 Al SSCL 6A 5 83 67 145 55 5 05 84 68 46 vcc E6 915 LCD_ DATA 20_B E5 914 LCD_ DATA 19 85 05 69 7 P303 48 GTIO LCD C7B_ DATA A 15 A A2 86 2 70 48 P302 411 A7 GTOU GTIO TXD2 SSLB IRQ5 LCD UP A C4A _ _ 3B DATA A SMOS 14 A I2 A SSDA 2 2 87 j 19 P301 486 A6 GTOU GTIO RXD2 SSLB IRQ6 LCD LO A C4B _ 2B DATA A SMIS 13 A O2 Al SSCL 2A F5 88 82 72 50 P300 GTIO SSLB SWCL COA_ 1B K A B2 c3 88 1 73 51 TMS 108 GTIO 59 SSLB SWDI B 0 04 74 52 109 GTOV GTIO CTXi TXD9 MOSI UT B UP A C1A_ _ _ BB TDO A SMOS swo lo B SSDA 9B C2 03 91 Bi 75 53 110 GTIO CRX1 CTS2 RXD9 MISO VCOU IRQ3 LO A C1B A B B B_B SMIS O9 B SSCL 9B 04 92 c2 76 54 111 5 5 GTIO SCK2 5 9 RSPC IRQ4 LCD _ B KB B DATA A 12A 82 93 03 77 55 112 44 4 GTIO TXD2 SSISC LCD C3B_ _ K0 B DATA A SMOS 11A 12 B SSDA 2B Bt 4 ct 78 56 P113 RXD2 SSIW LCD_ _ 50_ SMIS 10 A O2 B SSCL 2B E4 c2 95 E4 79 57 P114 A2
44. 3 DC characteristics Conditions Products with operating temperature T4 40 to 105 Item Test conditions Permissible junction temperature High speed mode Low speed mode Subosc speed mode Note sure that Tj T4 x total power consumption W where total power consumption VCC Voy x VoL x x VCC 2 2 2 2 4 syma Min unt Input voltage EXTAL exemalcock vcc o3 v 2 function pin input WAIT SPI m 202 S VCC x02 DO to 015 Vin VCC x 0 7 VCC 0 3 0 3 VCC x 0 3 ETHERC Vin 2 3 VCC 0 3 0 3 VCC x 0 2 SMBus 2 1 VCC 0 3 0 3 0 8 SMBus 2 2 1 5 8 0 3 0 8 Schmitt trigger Peripheral except for 0 7 0 3 V input voltage function pin SMBus ViL 203 VCC x03 AVI VCC x 0 05 except for 0 7 5 8 SMBus 2 Vir 0 3 VCC x 0 3 AVT VCC x 0 05 5V tolerant ports 3 VCC x 0 8 5 8 0 3 VCC x 0 2 AVT VCC x 0 05 RTCICO RTCIC1 Vpatt 0 8 VgarT 0 3 hen power D3 0 2 supply is selected AVT 0 05 3 Other input pins 4 Vin VCC x 0 8 VCC 0 3 0 3 VCC x 0 2 AVT VCC x 0 05 P
45. 6 162 K7 133 93 P007 PGAV 55100 10 10 163 19 134 94 006 10 IVCM IRQ11 2 P2 DS R11 R10 164 K8 135 95 P005 AN10 IVCM IRQ10 1 P2 DS M11 P11 165 K9 136 96 P004 AN10 IVCM IRQ9 0 P2 DS L10 M5 166 K10 137 97 P003 PGAV SS000 N12 R11 167 M10 138 98 P002 ANOO IVCM IRQ8 2 P2 DS P11 N11 168 N10 139 99 P001 ANOO IVCM IRQ7 1 P2 DS R12 812 169 L10 140 100 P000 ANOO IVCM IRQ6 0 P2 DS L11 M10 170 N11 141 VSS L12 M11 171 2 142 VCC M12 12 172 806 LCD EXTC LK B R13 JR13 173 P805 LCD DATA 17 B 12 P807 P13 12 174 513 LCD ETXD DATA 3 16 B K9 515 R14 14 175 M11 143 P512 GTIO CTX1 TXD4 5 12 IRQ14 VSYN COA B B ETXD SMOS 2 B SSDA 4B P14 5 5 P514 GTET RGB 15 13 176 M12 144 511 GTIO CRX1 RXD4 SDA2 T IRQ15 PCKO _ _ _ 5 5 O4 SSCL 4B Note Several pin names have the added suffix of A B and C When assigning the SPI and SSI functionality select the functional pins with the same suffix The other pins can be selected regardless of the suffix R01DS0262bEU0080 Rev 0 80 RENESAS Page 30 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics 2 Electrical Characteristics Unless otherwise specified the electrical characteristics of th
46. 7 04 l 007 04 current 12 bit A D converter in standby mode unit 0 0 07 02 0 07 0 2 VREFHO R01DS0262bEU0080 Rev 0 80 24 NE S AS Page 36 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics Table 2 7 Operating and standby current LDO mode DCDC mode Item Symbol Min Typ Max Min Typ Max Unit Test conditions Reference During 12 bit A D conversion unit 1 AlREFH 70 120 70 120 supply During D A conversion Without AMP output 02404 024 04 ma it current Per unit With AMP ouput 01 02 l 01 02 Waiting for 12 bit A D unit1 D A all units 0 07 0 4 0 07 0 4 12 bit A D converter standby mode unit 1 0 07 0 2 0 07 0 2 05 Low speed USB lccusBis 3 5 6 5 3 5 6 5 mA VCC USB ti 25 USBHS 105 135 10 5 13 5 VCC USBHS AVCC USBHS PHYSET HSEB 0 USBHS 2 8 3 6 28 36 mA VCC USBHS AVCC USBHS PHYSET HSEB 1 Full speed USB lccusBrs 4 0 10 0 4 0 10 0 mA USB USBHS 14 22 14 22 mA VCC USBHS AVCC USBHS PHYSET HSEB 0 USBHS 6 5 13 0 6 5 13 0 mA VCC USBHS AVCC_USBHS PHYSET HSEB 1 High speed USBHS lccusBHs 50 65 50 65 mA VCC US
47. 9 PA10 108 1 09 107 8 106 P615 105 P614 104 P613 103 P612 102 P611 101 P610 100 P609 P800 133 P300 TCK SWCLK P801 134 P301 P802 135 P302 P803 136 P303 P804 137 VCC VSS P304 P500 140 P305 P306 P502 142 P307 P503 P308 P504 144 P309 P505 145 P310 P506 146 P311 P507 147 P312 VCL2 148 P905 P906 P907 P015 151 908 P014 152 P200 vene R7FS7G2xxxA01CFC ag AVCCO 155 VCC_DCDC AVSSO 156 VLO VREFLO 157 VLO VREFHO 158 VSS P010 71159 VCL1 P009 160 VCC P008 161 VSS P007 162 P901 P006 163 P900 P005 164 P315 P004 165 P314 P003 166 P313 P002 167 P202 P001 168 P203 P000 169 P204 P205 P206 P806 172 P207 P805 173 VCC USB P513 174 USB DP P512 175 USB DM P511 176 VSS USB VBATT 18 XCOUT 21 P213 XTAL 23 P212 EXTAL 24 AVCC USBHS 26 USBHS RREF 27 AVSS USBHS 28 PVSS USBHS 29 VSS2 USBHS USBHS DM 31 USBHS DP 132 VSS1 USBHS VCC USBHS 34 Figure 1 5 Pin assignment for LOFP 176 pin Top view R01DS0262EU0080 Rev 0 80 134 NE SAS Page 20 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 1 Overview R7FS7G2xxxA01CLK P212 EXTAL VREFLO VREFHO P201 MD P109 TDO SWO 00 SWCLK 108 5 SWDIO P110 TDI
48. A e 12 Bit D A Converter DAC12 x 2 Up to 24 pins high current 20 mA e High Speed Analog Comparator ACMPHS x 6 m Operating Voltage Programmable Gain Amplifier PGA x 6 e 2 7 to 3 6 V T turi sor TSN emperature sensor PSN m Operating Temperature and Packages m Timers 40 to 85 General PWM Timer 32 Bit Enhanced High Resolution 224 pin BGA 13 mm x 13 mm 0 8 mm pitch GPT32EH x 4 176 pin BGA 13 mm x 13 mm 0 8 mm pitch e General PWM Timer 32 Bit Enhanced GPT32E x 4 145 pin LGA 7 mm x 7 mm 0 5 mm pitch e General PWM Timer 32 Bit GPT32 x 6 e Ta 40 C to 105 C e Asynchronous General purpose Timer AGT x 2 176 pin LQFP 24 mm x 24 mm 0 5 mm pitch e Watchdog Timer WDT 144 pin LQFP 20 mm x 20 mm 0 5 mm pitch Safety 100 pin LQFP 14 mm x 14 mm 0 5 mm pitch SRAM parity error check e Flash area protection e ADC self diagnosis function Clock Frequency Accuracy Measurement Circuit CAC Cyclic Redundancy Check CRC calculator Data Operation Circuit DOC Port Output Enable for GPT POEG e Independent Watchdog Timer IWDT GPIO readback level detection e Register write protection Main oscillator stop detection e Illegal memory access R01DS0262EU0080 Rev 0 80 21 NE S AS Page 1 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 1 Overview 1 Overvie
49. BHS AVCC USBHS Standby mode USBHS IcCUSBSBY 05 30 0 5 3 0 VCC USBHS direct power down AVCC USBHS Note 1 Supply current values are with all output pins unloaded and all input pull up MOS transistors in the off state Note 2 Measured with clocks supplied to the peripheral functions This does not include the BGO operation Note 3 This does not include the BGO operation Note 4 Supply of the clock signal to peripherals is stopped in this state This does not include the BGO operation Note 5 When is used 2 2 6 VCC Rise and Fall Gradient and Ripple Frequency Table 2 8 Rise and fall gradient characteristics VCC rising gradient SrVCC 0 0084 ms V VCC falling gradient SfVCC 0 0084 ms V Note 1 This applies when VBATT is used Table 2 9 Rising and falling gradient and ripple frequency characteristics The ripple voltage must meet the allowable ripple frequency frycc within the range between the VCC upper limit 3 6 V and lower limit 2 7 V When the VCC change exceeds VCC 10 the allowable voltage change rising and falling gradient dt dVCC must be met Item Symbol Min Typ Max Unit Test conditions Allowable ripple frequency fr vec 10 kHz Figure 2 2 0 2 1 MHz Figure 2 2 Vr vec lt VCC x 0 08 10 MHz Figure 2 2 Vr vec x 0 06 Allowable voltage change rising dt dVCC 1 0 ms V When VCC chan
50. C8B_ B 08 910 LCD_ DATA 2 909 LCD_ DATA 21_B E7 08 70 T P908 57 LCD DATA 14 B F7 07 71 P907 56 LCD DATA 13 B 01050262 00080 Rev 0 80 Oct 12 2015 134 NE SAS Page 26 of 111 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 1 Overview Pin number Extbus Timers Communication interfaces Analog HMI 9 28 5 o 8 22 2 SM E 5 g e R 99 a gt ERER 5 E O I r 9 aja 5 9 N n S x lt rira 5 8 a 5 3 5 o 8 8 S E 882525210 z gegga 3 895 2 2 2 a 21 9 lt o 9 5509 0 9 Nie 5 ajaa o F6 72 P906 55 LCD DATA 12 B A6 7 P905 54 LCD DATA 1B Be 77 4 ce 58 P312 53 CAS 06 75 5 59 P311 CS24 RAS LCD DATA 23 A A4 E VSS 4 5 VCC c6 6 6 07 je P310 15 15 LCD DATA 22 A c5 86 7 61 P309 14 414 LCD DATA 21A 7 78 cs 62 P308 A13 LCD DATA 20 A 06 9 4 63 4 P307 12 12 56 LCD ES DATA 19 A D5 4 80 84 64 4
51. D_EN RMII_TXD1 RMII TXDO RMII CRS DV RMII RXD1 RMII_RXDO RMII RX ER Figure 2 59 REF50CK and RMII signal timing REF50CK Preamble RMII_TXDO Figure 2 60 transmission timing u Ts CRS DV RXD1 RXDO Figure 2 61 RMII reception timing in normal operation RO1DS0262EU0080 Rev 0 80 2tENESAS Page 81 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics REFSOCK anni RMIL DV _ J RXD1 mero RXDO ER 2 62 RMII reception timing when error occurs REFSOCK WOL 2 63 WOL output timing for RMII ET TX CLK ET TX EN ET ETXD 3 0 ET TX ER ET CRS Figure 2 64 MII transmission timing in normal operation ET TX CLK _ ET ETXD 3 0 X Preamble 2 65 transmission timing when a conflict occurs RO1DS0262EU0080 0 80 24 NE SAS Page 82 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics
52. EFHO 0 25 V Absolute accuracy 12 5 5 5 LSB DNL differential nonlinearity error 1 0 2 0 LSB INL integral nonlinearity error 1 5 3 0 LSB Holding characteristics of sample and hold 20 us circuits Dynamic range 0 25 VREFH V 0 0 25 Channel dedicated Conversion time Permissible signal 0 88 us Sampling in 40 states sample and hold Operation at Source impedance 0 667 2 circuits not use PCLKC 60 MHz 1kQ AN100 to AN102 1 0 2 5 LSB Full scale error 1 0 2 5 LSB Absolute accuracy 2 0 4 5 LSB DNL differential nonlinearity error 0 5 1 5 LSB INL integral nonlinearity error 1 0 2 5 LSB High precision Conversion time Permissible signal 0 48 us Sampling in 16 states channel Operation at source impedance 0 267 AN103 to AN106 PCLKC 60 MHz 1 kQ Offset error 1 0 42 5 LSB Full scale error 1 0 2 5 LSB Absolute accuracy 2 0 4 5 LSB DNL differential nonlinearity error 0 5 1 5 LSB INL integral nonlinearity error 1 0 2 5 LSB Normal precision Conversion time 1 Permissible signal 0 88 us Sampling in 40 states channel Operation at Source impedance 0 667 2 AN116 to AN120 PCLKC 60 MHz 1 Offset error 1 0 45 5 LSB Full scale error 1 0 5 5 LSB Absolute accuracy 2 0 7 5 LSB DNL differential nonlinearity error 0 5 34 5 LSB INL integral nonlinearity error 1 0 5 5 LSB Note The
53. Erase 4 to 60 MHz Read lt 60 MHz 4 MHz 20 MHz lt s 60 MHz Item Symbol Min Typ Max Min Typ Max Unit Forced stop command 32 20 us Data hold time 3 20 20 Year Note 1 The reprogram erase cycle is the number of erasure for each block When the reprogram erase cycle is n times n 125 000 erasing can be performed n times for each block For instance when 4 byte programming is performed 16 times for different addresses in 64 byte blocks and then the entire block is erased the reprogram erase cycle is counted as one However programming the same address for several times as one erasure is not enabled overwriting is prohibited Note 2 This is the minimum number of times to guarantee all the characteristics after reprogramming The guaranteed range is from 1 to the minimum value Note 3 This indicates the characteristics when reprogramming is performed within the specified range including the minimum value 2 15 Boundary Scan Table 2 54 Boundary scan characteristics Item Symbol Min Typ Max Unit Conditions TCK clock cycle time trCKcyc 100 ns Figure 2 97 TCK clock high pulse width trckH 45 ns TCK clock low pulse width trckL 45 ns TCK clock rise time trckr 5 ns TCK clock fall time 5 ns TMS setup time truss 20 ns Figure 2 98 TMS hold time 20 ns TDI setup time trpi
54. F15 31 05 S DM 14 F14 32 T USBH S DP F12 12 33 VSS1 USB HS F13 213 34 VCC_ USBH 8 E15 E15 35 VSS G10 G10 22 713 GTIO 1_ 1517 2 _ EXOU EXOU B FW Fit 23 712 GTIO TS16 C2B_ B E12 E13 24 P711 CTS1 ETO T TS15 B X_CL K F10 E12 25 P710 SCK1 ETO 1514 B X_ER E13 10 26 709 TXD1 ETO TS13 010 B ETXD SMOS 2 M B SSDA 1B D15 D13 27 16 708 RXD1 SSLA _ 1512 EF B B 3B ETXD SMIS 3 O1 B SSCL 1B E14 E14 6 28 17 415 SSLA T RMIIO TS11 2B X EN TXD EN EM 015 37 012 29 18 414 SSLA ETO RMIIO SDOW TS10 1B RX E TXD P R 1 D12 E13 388 10 30 19 413 GTOU CTSO SSLA ETO RMIIO SDOC 159 UP B B ETXD TXD LK 1 0 D13 014 39 ct3 20 P412 GTOU SCKO RSPC ETO 5 SDOC TS8 LO B KA B ETXD MD 0 Di4 ci5 44 32 21 P411 GTOV TXDO CTS3 MOSI ETO 0 5000 TS7 IRQ4 A1 UP C9A Bi A AB ERXD RXD ATO A SMOS 1 0 10 B SSDA 0B C15 14 41 12 33 22 P410 AGTO GTOV GTIO RXDO SCK3 MISO ETO RMIIO 5000 756 IRQS B1 C9B_ B A AB ERXD RXD AT1 A SMIS 0 1 O0 B SSCL 0B B15 42 B13 34 23 P409 GTIO USB TXD3 ETO 0 05 TS5 IRQ6 WUP C10A EXICE _ _RX_ 5 B LA SMOS LK CEN SSDA B15 013 43 040 35 24 4
55. FP LGA LQFP LQFP Code flash memory 4 3 MB 3 MB Data flash memory 64 KB SRAM 640 KB Parity 608 KB DED 32 Standby SRAM 8KB System CPU clock 240 MHz Backup registers 512 bytes Interrupt control Yes Event link ELC Yes DMA DTC Yes DMAC 8 BUS External bus 16 bit bus 8 bit bus SDRAM Yes No Timers GPT32EH 4 4 4 4 4 4 GPT32E 4 4 4 4 4 3 GPT32 6 6 6 6 6 6 AGT 2 2 2 2 2 2 RTC Yes WDT IWDT Yes Communication SCI 10 3 2 SPI 2 SSI 2 1 QSPI 1 Dual SPI 1 SDHI 2 CAN 2 USBFS Yes USBHS Yes No ETHERC 2 RMMI 2 RMMI 2 RMMI 2 MMI 1 RMMI 1 Analog ADC12 25 21 21 19 19 16 DAC12 2 ACMPHS 6 TSN Yes HMI CTSU 18 12 12 18 12 KINT 8 Graphics GLCDC RGB888 RGB565 DRW Yes JPEG Yes PDC Yes No Data processing CRC Yes DOC Yes SRC Yes Security SCE7 01050262 00080 Rev 0 80 ztENESAS Page 11 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 1 Overview 1 5 Pin Functions Function Signal Description Power supply VCC Input Power supply pin Connect it to the system power supply Connect this pin to VSS via 0 1 pF capacitor The capacitor should be placed close to the pin VCC DCDC Input Switching regulator power supply pin VLO VO Switching regulator pin VCLO to VCL2 Input Connect this pin to VSS via the 4 7 smooth
56. HS Input Ground pin VSS2 USBHS Input Ground pin AVCC USBHS Input Analog power supply pin for the USBHS AVSS USBHS Input Analog ground for the USBHS Must be shorted to the PVSS USBHS pin PVSS USBHS Input PLL circuit ground pin for the USBHS Must be shorted to the AVSS USBHS pin USBHS RREF VO USBHS reference current source pin This pin should be connected to the AVSS_USBHS pin through a resistor of 2 2 kQ 1 USBHS_DP USB bus D data USBHS DM USB bus D data USBHS EXCEN Output This pin should be connected to the OTG power supply IC USBHS ID Input This pin should be connected to the OTG power supply IC USBHS VBUSEN Output VBUS power enable pin for USB USBHS OVRCURA Input Overcurrent pin for USB USBHS OVRCURB USBHS VBUS Input USB cable connection monitor input pin 01050262 00080 Rev 0 80 Oct 12 2015 134 NE SAS Page 14 of 111 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 1 Overview Function Signal yo Description ETHERC REF50CkO Input 50 MHz reference clocks These pins input reference signals for REF50CK1 transmission reception timings in RMII mode CRS DV Input Indicate that there are carrier detection signals and valid receive data on RMII1 CRS DV RXD1 and RXDO in mode RMIIO TXDO Out
57. ITA Package Code RENESAS Code Previous Code MASS Typ P LFBGA224 13x13 0 80 PLBG0224GA A 224FHE 0 4g m D b 3 E Ai _ 2D Ti hk r f R 0020000099 a 1 N L J H e 0 o e e e o 6 e e o e e o e amp a D gt q B 0000000000000 Reference Dimension in Millimeters t 1 Symbol Min Max x4 1234567 8 9 101112131415 Index mark s D 13 0 Laser mark Index mark 180 v 045 0 20 A 14 0 3 0 35 04 08 b 0 4 0 45 0 5 x 0 08 y 0 10 Zo 0 9 Ze 0 9 Figure 1 1 BGA 224 pin RO1DS0262EU0080 Rev 0 80 2tENESAS Page 106 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series Appendix 1 Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS Typ
58. IXD7 O0 C C3A 1 A MDC MDC AGTI B K10 13 5 112 5 5 404 SSIW 1_ PIXD6 2 SO MDIO MDIO B M13 15 6 113 6 6 405 GTIO SSITX T RMII1 PIXD5 1 _ 00 A X EN B EN J9 N14 7 7 7 P406 GTIO SSIRX ET1 RMI PIXD4 C1B_ 00 A RX E B R 1 M14 15 8 10 8 700 GTIO PIXD3 C5A_ ETXD _TXD B 1 0 15 14 9 k12 9 P701 GTIO 5 PIXD2 C5B_ ETXD 0CK1 B 0 112 fho 10 702 GTIO RMIIt PIXD1 C6A_ ERXD _RXD B 1 0 48 15 1 Jt n P703 GTIO RMIH PIXDO C6B_ ERXD _RXD B 0 1 12 2 704 RMIH HSYN RXC RX 113 2 705 RMI PIXCL CRS CRS K Dv 014 14 706 RXD3 USBH IRQ7 OV SMIS RCUR O3 B B SSCL 3B 115 15 15 P707 TXD3 USBH IRQ8 Ov SMOS RCUR I3 B A SSDA 3B 42 16 00 SCK3 USBH B S VB USEN f 02 CTS8 1_ B RX_D v 12 PB03 SCK8 B COL 10 04 TXD8 1_ IRQ12 B ERXD SMOS 2 l8 B SSDA 8B 17 1 CTS3 USBH B S VB US 912 05 RXD8 1_ IRQ13 B ERXD SMIS 3 O6 B SSCL 6B Hit 06 1_ WOL WOL Gn f 07 L ET1 L INKST A A 14 Ki 4 H8 2 14 8 VBAT T 15 Ki5 9 13 15 19 VCL
59. K clock low pulse width tePCKWL 0 4 0 6 SCK clock rise and fall time tspckr 20 ns Data input setup time tsu 33 3 ns Figure 2 39 to Data input hold time tH 33 3 ns Figure sata SS input setup time ti EAD 1 sPcyc SS input hold time ti AG 1 Data output delay top 33 3 ns Data output hold time tou 10 ns Data rise and fall time tpr tor 16 6 ns SS input rise and fall time 1551 tssLf 16 6 ns Slave access time tsa 4 lt 60 MHz Figure 2 42 8 gt 60 2 Slave output release time 5 PCLKA lt 60 MHz tpcyc 10 PCLKA 60 MHz Note SMISO1 A is not supported in these specifications tsPckwH SCKn master select output tspcKwH SCKn slave select input n 0 to 9 Vou 0 7 x VCC Voa 0 3 VCC Vin 0 7 VCC V 0 3 x VCC Figure 2 38 SCI simple SPI mode clock timing 01050262 00080 Rev 0 80 ESAS Page 65 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics SMOSIn LSB OUT MSB OUT output n 0 to 9 Figure 2 39 SCI simple SPI mode timing master CKPH 1 SMISOn input tor tor SMOSIn MSB OUT LSB OUT MSB OUT output n 0 to 9 Figure 2 40 SCI simple SPI mode timing master CKPH 0 SMISOn MSB OUT ou
60. O 115 45 20 16 10 04 21 12 17 11 XCOU T 22 F12 18 12 VSS 01050262 00080 Rev 0 80 12 2015 134 NE SAS Page 24 of 111 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 1 Overview Pin number Extbus Timers Communication interfaces Analog HMI 9 28 5 o 8 22 2 SM E 5 g e R 99 z gt ERER 5 A o allio I o N ja 5 N n A S x o lt I rir a gt 8 a 5 3 5 882525210 g 3 3 895 2 2 2 2 a 21 2 20 9 lt o 9 58509 0 9 Q9 z 5 ajaaa o Hi4 14 23 612 19 13 213 TXD1 IRQ2 RGC_ G1 A SMOS A _ SSDA 1A 15 15 24 G13 20 14 EXTA 212 RXD1 IRQ3 L RGD _ SMIS O1A SSCL 1A H12 H12 25 21 15 H13 H13 26 USB HS 613 27 USBH S RR EF G14 614 28 55 USB HS G15 615 29 PVSS USB HS G12 612 30 VSS2 USB HS 15
61. Preliminary H N ESAS Specifications in this document are tentative and subject to change 5762 MCU High performance MCU 32 bit ARM Cortex M4 microcontroller eading performance 240 2 ortex M4 microcontroller up to 4 MB code flash memory 640 Graphics LCD Controller 2D Drawing Engine Capacitive Touch Sensing Unit Ethernet Controller with IEEE 1588 PTP USB 2 0 High Speed USB 2 0 Full Speed SDHI Quad SPI security and safety features and advanced analog Features ARM Cortex M4 Core with Floating Point Unit FPU System and Power Management ARMV7E M architecture with DSP instruction set Low power modes Maximum operating frequency 240 MHz e Switching regulator Supports 4 GB address space e Realtime Clock RTC with calendar and VBATT support On chip Debugging System JTAG SWD and ETM Event Link Controller ELC Boundary scan and ARM Memory Protection Unit MPU DMA Controller DMAC x 8 Memory Controller Up to 4 MB code flash memory 80 MHz zero wait states Power on reset 64 KB data flash memory up to 100 000 erase write cycles e Low voltage detector with voltage settings e Up to 640 KB SRAM Flash Cache FCACHE m Security and Encryption e Memory protection units AESI28 192 256 Memory mirror function 3DES ARC4 128 bit unique ID SHAI SHA224 SHA256 Connectivity 4 Ethernet MAC Controller ETHERC x 2 e True Random Number Ge
62. S register Clock duty ratio is 5096 Item Symbol Min Max Unit SDCLK clock cycle Tspcvc 20 ns SDCLK clock high level pulse width TspwH 6 5 ns SDCLK clock low level pulse width TspwL 6 5 ns SDCLK clock rising time 3 ns SDCLK clock falling time TspHL 3 ns SDCMD SDDAT output data delay TspopLv 6 5 ns SDCMD SDDAT input data setup Tspis ns SDCMD SDDAT input data hold 2 ns SDCLK output TspoDLy min gt Test conditions Figure 2 58 SDCMD SDDAT output SDCMD SDDAT input Figure 2 58 SD MMC host interface signal timing R01DS0262EU0080 Rev 0 80 Oct 12 2015 2 1 Page 79 of 111 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics 2 3 16 ETHERC Timing Table 2 31 ETHERC timing Conditions ETHERC Middle drive output is selected with the port drive capability bit in the PmnPFS register for the following pins ETO MDC ETO_MDIO 1 MDC and ET1_MDIO For other pins high drive output is selected with the port drive capability bit in the PmnPFS register ETHERC MII Middle drive output is selected with the port drive capability bit in the PmnPFS register Test Item Symbol Min Max Unit conditions ETHERC REFSOCK cyc
63. Serial Communication Interface SCI is configurable to five asynchronous and SCI synchronous serial interfaces asynchronous interfaces UART and Asynchronous Communications Interface Adapter ACIA e 8 bit clock synchronous interface e simple master only e simple SPI smart card interface The smart card interface complies with the ISO IEC 7816 3 standard for electronic signals and transmission protocol Each SCI has FIFO buffers to enable continuous and full duplex communication and the data transfer speed can be configured independently using an on chip baud rate generator See section 34 Serial Communications Interface in User s Manual 12C Bus Interface 1 This MCU has a three channel 2 bus interface The module conforms with and provides a subset of the NXP bus Inter Integrated Circuit bus interface functions See section 36 I2C Bus Interface IIC in User s Manual Serial Peripheral Interface SPI This MCU includes two independent channels of the Serial Peripheral Interface SPI The SPI channels are capable of high speed full duplex synchronous serial communications with multiple processors and peripheral devices See section 38 Serial Peripheral Interface SPI in User s Manual Serial Sound Interface SSI The Serial Sound Interface SSI peripheral provides functionality to interface with digital audio devices for transmitting PCM audio data over a serial bus with
64. ace space is in progress WR Output Strobe signal which indicates that writing to the external bus interface space is in progress in 1 write strobe mode WRO to WR1 Output Strobe signals which indicate that either group of data bus pins D7 to DO D15 to D8 is valid in writing to the external bus interface space in byte strobe mode BCO to BC1 Output Strobe signals which indicate that either group of data bus pins D7 to DO D15 to D8 is valid in access to the external bus interface space in 1 write strobe mode WAIT Input Input pin for wait request signals in access to the external space 50 to CS7 Output Select signals for CS areas AO to A23 Output Address bus DO to D15 Data bus SDRAM interface CKE Output SDRAM clock enable signal SDCS Output SDRAM chip select signal RAS Output SDRAM low address strobe signal CAS Output SDRAM column address strobe signal WE Output SDRAM write enable signal DQMO Output SDRAM data mask enable signal for D7 to DO DQM1 Output SDRAM data mask enable signal for D15 to D8 to A15 Output Address bus DQO to DQ15 Data bus RO1DS0262EU0080 Rev 0 80 134 NE SAS Page 12 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 1 Overview Function Signal yo Descriptio
65. age Dimensions JEITA Package Code RENESAS Code Previous Code MASS Typ P LFQFP144 20x20 0 50 PLQP0144KA A 144 6 FP 144L FP 144LV 1 29 1 DIMENSIONS 1 AND 2 DO NOT INCLUDE MOLD FLASH 2 DIMENSION 3 DOES NOT INCLUDE TRIM OFFSET bp bi e c Reference Dimension in Millimeters symbol Min Nom Max Terminal cross section 19 9 20 0 20 1 19 9 20 0 20 1 A2 1 4 Hp 21 8 22 0 22 2 21 8 22 0 22 2 A 17 A1 0 05 0 1 0 15 4 bp 0 17 0 22 0 27 Index mark l bi 10 20 i 17 0 09 0 145 0 20 lt L 0 125 5 Asl a 0 8 amp 0 5 e yIs e Teka Detail F x 0 08 y gt 10 10 Zp 1 25 Ze 1 25 L 035 05 0 65 L4 1 0 Figure 1 5 LQFP 144 RO1DS0262EU0080 Rev 0 80 2tENESAS Page 110 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series Appendix 1 Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS Typ g P LFQFP100 14x14 0 50 PLQP0100KB B 0 6
66. al resonator or by an external oscillator while program execution is in progress wait until the target clock signal is stable 6 Voltage application waveform at input pin Waveform distortion due to input noise or a reflected wave may cause malfunction If the input of the CMOS device stays in the area between VIL Max and VIH Min due to noise for example the device may malfunction Take care to prevent chattering noise from entering the device when the input level is fixed and also in the transition period when the input level passes through the area between VIL Max and VIH Min 7 Prohibition of access to reserved addresses Access to reserved addresses is prohibited The reserved addresses are provided for possible future expansion of functions Do not access these addresses as the correct operation of the LSI is not guaranteed 8 Differences between products Before changing from one product to another for example to a product with a different part number confirm that the change will not lead to problems The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms of internal memory capacity layout pattern and other factors which can affect the ranges of electrical characteristics such as characteristic values operating margins immunity to noise and amount of radiated noise When changing to a product with a different part number imp
67. ata delay Clock trxp 25 ns Figure 2 37 synchronous Receive data setup time Clock tRxs 15 ns synchronous Receive data hold time Clock trxH 5 ns synchronous Note 1 tpgyc PCLKA cycle SCKn n 0 to 9 Figure 2 36 SCK clock input output timing Figure 2 37 SCI input output timing in clock synchronous mode RO1DS0262EU0080 Rev 0 80 2tENESAS Page 64 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics Table 2 23 SCI timing 2 Conditions High drive output is selected with the port drive capability bit in the PmnPFS register for the following pins SCKO to SCK9 except for SCK4 B SCK7 For the SCK4 B SCK7 A pins middle drive output is selected with the port drive capability bit in the PmnPFS register For the SMISO1 A pins low drive output is selected with the port drive capability bit in the PmnPFS register For other pins middle drive output is selected with the port drive capability bit in the PmnPFS register Test Item Symbol Min Max Unit conditions Simple SCK clock cycle output tsPcyc 4 PCLKA lt 60 MHz 65536 pcyc Figure 2 38 SPI master 8 PCLKA gt 60 MHz SCK clock cycle input slave 6 PCLKA lt 60 MHz 65536 12 PCLKA 60 MHz SCK clock high pulse width tspcxwu 0 4 0 6 sPcyc SC
68. cations in this document are tentative and subject to change S7 Series 2 Electrical Characteristics POEG input trigger Figure 2 28 POEG input trigger timing Input capture Figure 2 29 GPT32 input capture timing xg e X xg Output delay GPT32 output tetisk Figure 2 30 GPT32 output delay skew PX eee a x Output delay GPT32 output tetosk Figure 2 31 GPT32 output delay skew for OPS RO1DS0262EU0080 Rev 0 80 2tENESAS Page 61 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics f VI V VI VI Output delay GPT32 output PWM delay generation circuit Figure 2 32 GPT32 PWM delay generation circuit output delay skew tackwL tackwH AGTIO AGTEE input tacyc2 AGTIO AGTO AGTOA AGTOB output Figure 2 33 AGT I O timing ADTRGO ADTRG1 Figure 2 34 ADC 12 trigger input timing KROO to KRO7 Figure 2 35 Key interrupt input timing RO1DS0262EU0080 Rev 0 80 ESAS Page 62 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics 2 3 8 PWM Delay Generation Circuit Timing Table 2 20 PWM delay generation circuit timing Resolution PCLKD 120 MHz DNL 1 2 0 LSB Note 1 T
69. cs Conditions VCC AVCCO VREFH USB 2 7 to 3 6 V VREFHO 2 7 V to AVCCO VBATT 2 0 to 3 6 V Item Symbol Min Typ Max Unit Test conditions Voltage level for switching to battery backup VDETBATT 2 50 2 60 2 70 V Figure 2 94 Lower limit VBATT voltage for power supply VBATTSW 2 70 V Pues Switching due to VCC voltage drop VCC off period for starting power supply switching tVOFFBATT 200 Hus Note VCC off period for starting power supply switching indicates the period in which VCC is below the minimum value of the voltage level for switching to battery backup VpgrgaATT tvorrBATT V VCC DETBATT gt lt gt lt ha VCC supply supply VCC supply Figure 2 94 Battery backup function characteristics RO1DS0262EU0080 Rev 0 80 ESAS Page 98 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics VCC supply i i 2 0 2 5 2 7 3 Figure 2 95 VBATT supply range 2 11 CTSU Characteristics Table 2 48 CTSU characteristics Item Symbol Min Typ Max Unit Test conditions External capacitance connected to TSCAP pin Ctscap 9 10 11 nF TS pin capacitive load Chase 50 pF Permissible output high current 40 mA When the mutual capacitance method is applied 2 12 Comparator Character
70. cs is measured for each group Note 3 N is set to an integer from 1 to 8 by the SPCKD register Note 4 N is set to an integer from 1 to 8 by the SSLND register 01050262 00080 Rev 0 80 Oct 12 2015 34 NE SAS Page 69 of 111 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics tePckwi tspckr SPI RSPCKA master select output tspckwH RSPCKA slave select input 0 7 x VCC 0 3 VCC Vin 0 7 x VCC 0 3 x Figure 2 44 SPI clock timing SPI SSLAO to SSLA3 output RSPCKA 0 output RSPCKA CPOL 1 output tssir tssur top LSB OUT MSB OUT Figure 2 45 SPI timing master CPHA 0 RO1DS0262EU0080 Rev 0 80 ESAS Page 70 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics SPI SSLAO to 5 output RSPCKA CPOL 0 output RSPCKA CPOL 1 output Figure 2 46 SPI SSLAO to SSLA3 output 1551 15517 RSPCKA CPOL 0 output RSPCKA CPOL 1 output MSBIN MSB OUT LSB OUT IDLE MSB OUT Figure 2 47 SPI timing master CPHA 1 bit rate PCLKA division is set to 1 2 RO1DS0262EU0080 0 80 2 1 Page 71 of 111 Oct 12 2015 U
71. ct to change S7 Series 2 Electrical Characteristics Note 1 Programming or erasing the Flash memory is disable in Subosc speed mode Note 2 See section 9 Clock Generation Circuit in User s Manual for the relationship of frequencies between the ICLK PCLKA PCLKB PCLKC PCLKD FCLK and BCLK Note 3 The 12 bit A D converter cannot be used 2 3 2 Clock Timing Table 2 13 Clock timing except for sub clock Item Symbol Min Typ Max Unit Test conditions EBCLK pin output cycle time 16 6 ns Figure 2 3 EBCLK pin output high pulse width tcu 3 3 ns EBCLK pin output low pulse width 3 3 ns EBCLK pin output rising time 5 0 ns EBCLK pin output falling time tcr 5 0 ns SDCLK pin output cycle time tsDeyc 8 33 ns SDCLK pin output high pulse width 1 0 ns SDCLK pin output low pulse width teL 1 0 ns SDCLK pin output rising time tor 3 0 ns SDCLK pin output falling time tcr 3 0 ns EXTAL external clock input cycle time tExcyc 41 66 ns Figure 2 4 EXTAL external clock input high pulse width texH 15 83 ns EXTAL external clock input low pulse width text 15 83 ns EXTAL external clock rising time texr 5 0 ns EXTAL external clock falling time tgxr 5 0 ns Main clock frequency 8 24 2 Main clock oscillation stabilization wait time MAINOSCWT 1 m
72. d data asynchronous mode clock synchronous mode CTSO to CTS 9 Input Input pins for controlling the start of transmission and reception asynchronous mode clock synchronous mode RTSO to RTS9 Output Output pins for controlling the start of transmission and reception SSCLO to SSCL9 Input output pins for the clock simple SSDAO to SSDA9 y o Input output pins for the data simple SCKO to SCK9 Input output pins for the clock simple SPI SMISOO to SMISO9 I O Input output pins for slave transmission of data simple SPI SMOSIO to SMOSI9 I O Input output pins for master transmission of data simple SPI 550 to 559 Input Chip select input pins simple SPI SCLO to SCL2 Input output pins for clock SDAO to SDA2 Input output pins for data SSI SSISCKO SSI serial bit clock pin SSISCK1 SSIWSO VO Word select pins SSIWS1 SSITXDO Output Serial data output pins SSIRXDO Input Serial data input pins SSIDATA1 VO Serial data input output pins AUDIO_CLK Input External clock pin for audio input oversampling clock SPI RSPCKA RSPCKB I O Clock input output pin MOSIA MOSIB VO Inputs or outputs data output from the master MISOA MISOB Inputs or outputs data output from the slave SSLAO SSLBO Input or output for slave selection SSLA1 to SSLA3 Output Output pin for slave selection SSLB1 to SSLB3 RO1DS0262EU0080 Rev 0 80 ztENESAS Page 13 of 111 Oct 12 2015
73. d subject to change S7 Series Appendix 1 Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS Typ P TFLGA145 7x7 0 50 PTLG0145KA A 145F0G 0 1g 9b ex 015 D 5 ox 5 AB _ _ e N 0008009000000 0ooooooooe L 9999999999909 kK 1 0000 e000 5 000044 F 0000000000000 0000000000000 a 00000000000007 n m d um Bou Ug 1 at dod 42 48 i Reference Dimension in Millimeters Ay Min Nom Index mark fs D LE 7 0 lt Laser mark 70 v 045 w 0 20 A 1 05 e 05 b 0 21 0 25 0 29 b 0 29 0 34 0 39 x 0 08 y 0 08 25 05 2 05 Figure 1 4 LGA 145 pin RO1DS0262EU0080 Rev 0 80 tENESAS Page 109 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series Appendix 1 Pack
74. d time 3 20 20 Years FCU reset time tFCUR 35 35 Hus Note 1 The reprogram erase cycle is the number of erasures for each block When the reprogram erase cycle is n times n 1 000 erasing can be performed n times for each block For instance when 256 byte programming is performed 32 times for different addresses in 8 KB blocks and then the entire block is erased the reprogram erase cycle is counted as one However programming the same address for several times as one erasure is not enabled overwriting is prohibited Note 2 This is the minimum number of times to guarantee all the characteristics after reprogramming The guaranteed range is from 1 to the minimum value Note 3 This indicates the characteristics when reprogramming is performed within the specified range including the minimum value RO1DS0262EU0080 0 80 2tENESAS Page 102 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics Suspension during programming FCU command Program Suspend FSTATRO FRDY Not Ready Programming pulse J 1 000000 Suspension during erasure in suspend priority mode FCU command X Erase X X Suspend X Resume X X Suspend tsesp1 tsesp2 FSTATRO FRDY Not Ready Not Ready Erasure pulse Erasing Erasin
75. dth of analog input voltage 1 LSB width which can meet the expectation of outputting an equal code based on the theoretical A D conversion characteristics is used as an analog input voltage For example if 12 bit resolution is used and the reference voltage VREFHO 3 072 V then 1 LSB width becomes 0 75 mV and 0 0 75 and 1 5 mV are used as the analog input voltages If analog input voltage is 6 mV an absolute accuracy of 4 5 LSB means that the actual A D conversion result is in the range of 003h to 00Dh though an output code of 008h can be expected from the theoretical A D conversion characteristics Integral nonlinearity error INL Integral nonlinearity error is the maximum deviation between the ideal line when the measured offset and full scale errors are zeroed and the actual output code Differential nonlinearity error DNL Differential nonlinearity error is the difference between 1 LSB width based on the ideal A D conversion characteristics and the width of the actual output code Offset error Offset error is the difference between the transition point of the ideal first output code and the actual first output code Full scale error Full scale error is the difference between the transition point of the ideal last output code and the actual last output code 01050262 00080 Rev 0 80 Oct 12 2015 ztENESAS Page 94 of 111 Under development Preliminary document Specifications in this doc
76. e MCU are defined under the following conditions AVCCO USB VBATT 2 7 to 3 6 V 2 7 lt VREFHO VREFH x AVCCO USBHS AVCC USBHS 3 0 to 3 6 V VSS AVSS0 VREFLO VREFL VSS USB VSS1_USBHS VSS2 USBHS PVSS USBHS AVSS USBHS 0 V Ta Figure 2 1 shows the timing conditions For example P100 VCC x 0 7 Vo VCC x 0 3 Vin VCC x 0 7 Vy VCC 0 3 Load capacitance 30pF Figure 2 1 Input or output timing measurement conditions RO1DS0262EU0080 Rev 0 80 34 N SAS Page 31 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics 2 1 Absolute Maximum Ratings Table 2 1 Absolute maximum ratings Item Symbol Value Unit Power supply voltage VCC VCC_USB 2 0 3 to 4 6 V VBATT power supply voltage VBATT 0 3 to 4 6 V Input voltage except for 5V tolerant 1 Vin 0 3 to VCC 0 3 V Input voltage 5V tolerant 1 Vin 0 3 to 5 8 V Reference power supply voltage VREFH VREFHO 0 3 to VCC 0 3 V Analog power supply voltage AVCCO 2 0 3 to 4 6 V USBHS power supply voltage VCC USBHS 0 3 to 4 6 V USBHS analog power supply voltage AVCC USBHS 0 3 to 4 6 V Switching regulator power supply voltage VCC DCDC 0 3 to 4 6 V Analog input voltage VAN 0 3 to AVCCO 0 3 V Operating tempera
77. ect to change S7 Series 2 Electrical Characteristics Table 2 36 USBHS high speed characteristics USBHS DP and USBHS DM pin characteristics Conditions USBHS RREF 2 2 196 USBMCLK 20 24 MHz characteristics Disconnect detect sensitivity 525 625 mV Figure 2 81 Common mode voltage VuscM 50 500 mV Output Idle state Vusol 10 0 10 mV characteristics Output high level voltage Viso 360 440 mV Output low level voltage VHsoL 10 0 10 mV Chirp J output voltage difference VCHIRPJ 700 1100 mV Chirp K output voltage difference 900 500 Rise time 500 Figure 2 82 characteristics Fall time fase 500 ps Output resistance ZHSDRV 40 5 49 5 Q USBHS_DP USBHS_DM Figure 2 80 USBHS_DP and USBHS_DM squelch detect sensitivity in high speed mode USBHS_DP USBHS_DM Figure 2 81 USBHS_DP and USBHS_DM disconnect detect sensitivity in high speed mode USBHS_DP USBHS_DM Figure 2 82 USBHS_DP and USBHS_DM output timing in high speed mode Observation USBHS_DP point USBHS DM Figure 2 83 Test circuit in high speed mode 01050262 00080 Rev 0 80 ESAS Page 89 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics Table 2 37 USBHS high speed characteri
78. ed mode when system clock tsnz 68 9 us from Software source is HOCO 20 MHz 2 mode to High speed mode when system clock tsnz 14 9 us n9029 source is MOCO 8 Normal mode System clock source is main clock oscillator 1 toyemose Figure 2 11 duration 10 System clock source is PLL with main clock oscillator Note 1 The recovery time is determined by the system clock source When multiple oscillators are active the recovery time can be determined with the following equation Total recovery time recovery time for an oscillator as the system clock source the longest oscillation stabilization time by any oscillators requiring longer stabilization times than the system clock source 2cyc of LOCO when LOCO is operating 3cyc of SOSC when Subosc is oscillating and MSTPCO CAC module stop bit is set to 0 Note 2 When the frequency of the crystal is 24 MHz The Main Clock Oscillator Wait Control Register MOSCWTCR is set to 05h For other settings MOSCWTCR is set to Xh the recovery time can be determined with the following equation MOSCWTCR Xh teBYMC MOSCWTCR 05h tMAINOSCWT MOSCWTCR Xh gt tMAINOSCWT MOSCWTCR 05h Note 3 When the frequency of PLL is 240 MHz The Main Clock Oscillator Wait Control Register MOSCWTCR is set to 05h For other settings MOSCWTCR is set to Xh the recovery time can be determined with the following equation MOSCWTCR Xh
79. er 4096 Figure 2 44 4 PCLKA more than 60 MHz C 30 pF Slave 6 4096 RSPCK clock high Master tePckwH tsPcyc tePCkR tsPckr 12 3 ns pulse width Slave x tpoyc RSPCK clock low pulse Master tspcKWL tsPcyc tspcKR tsPckr 12 3 ns width Slave 3 tpoyc RSPCK clock rise and Master tspckp 5 ns fall time Slave _ 1 us Data input setup time Master tsu 4 ns Figure 2 45 to Figure 2 50 Master 4 C 30 pF Slave 5 Data input hold time Master tur 0 ns Slave ty 20 SSL setup time Master ti EAD N tspeyc 10 3 Nx ns 100 3 Slave 6 x tpoyc ns SSL hold time Master N tspoyc 10 4 Nx ns tsPcyc 100 4 Slave 6 x tpoyc ns Data output delay Master top 6 3 ns Figure 2 45 to Figure 2 50 Slave 20 C 30pF Data output hold time Master toH 0 ns Slave 0 Successive Master trp tspcyc 2 8x ns transmission delay 2x tPcyc Slave 6 tpoyc MOSI and MISO rise Output tor 5 ns and fall time Input 1 us SSL rise and fall time Output tssi 5 ns Input tssLf 1 us Slave access time tsa 2 ns Figure 2 49 and 28 Figure 2 50 Slave output release time 2 X tpoyc 28 Note 1 PCLKA cycle Note 2 Renesas recommends using pins that have a letter appended to their names for instance A B to indicate group membership For the SPI interface the AC portion of the electrical characteristi
80. eries 2 Electrical Characteristics PLLCR PLLSTP PLL circuit output OSCSF PLLSF PLL clock Figure 2 7 PLL clock oscillation start timing Note Only operate the PLL is operated after main clock oscillation has stabilized SOSCCR SOSTP Y 5 4 Sub clock oscillator output Jm FN TS tsuBoscwr Sub clock 1291 Figure 2 8 Sub clock oscillation start timing RO1DS0262EU0080 Rev 0 80 34 N SAS Page 42 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics 2 3 3 Reset Timing Table 2 15 Reset timing Test Item Symbol Min Typ Max Unit conditions RES pulse width Power on LDO mode 1 ms Figure 2 9 DCDC mode 1 5 ms Deep Software Standby mode tRESWD 0 6 ms Figure 2 10 Software Standby mode Subosc speed tRESwS 0 3 ms mode All other tresw 200 5 Wait time after RES cancellation tRESWT B 33 4 us Figure 2 9 Internal reset cancellation time tresw2 390 us IWDT reset WDT reset software reset SRAM parity error reset SRAM ECC error reset bus master MPU error reset bus slave MPU error reset stack pointer error reset Internal reset signal low is valid Figure 2 9 Power on reset timing RES Internal reset signal low is valid 1 9 treswt treswo t
81. ffer for data transfer providing a maximum of 10 pipes Any endpoint number can be assigned to pipes 1 to 9 based on the peripheral devices or user system for communication See section 33 USB 2 0 High Speed Module USBHS in User s Manual Ethernet MAC with IEEE 1588 PTP ETHERC This MCU has a two channel Ethernet MAC Controller ETHERC compliant with the Ethernet or IEEE802 3 Media Access Control MAC layer protocol Each ETHERC channel has one channel of the MAC layer interface connecting the MCU to the physical layer LSI PHY LSI that allows transmission and reception of frames compliant with the Ethernet IEEE802 3 standard The ETHERC is connected to the Ethernet DMA Controller EDMAC so data can be transferred without using the CPU This MCU has an on chip Precision Time Protocol PTP module for the Ethernet PTP Controller EPTPC The module applies the PTP defined in the IEEE 1588 2008 version 2 0 standard to handle timing and synchronization between devices The EPTPC is composed of synchronization frame processing units SYNFPO and SYNFP1 e a packet relation controller unit PRC TC a Statistical Time Correction Algorithm unit STCA Use the EPTPC in combination with the on chip Ethernet MAC Controller ETHERC and the DMA controller for the Ethernet Controller PTPEDMAC See section 29 Ethernet Controller ETHERC in User s Manual SD MMC Host Interface SDHI Table 1 10 Analog Feature
82. g Suspension during erasure in erasure priority mode FCU command Suspend FSTATRO FRDY Not Ready Forced Stop FACI command Forced Stop FSTATR FRDY Not Ready Figure 2 96 Flash memory programming and erasure suspension and forced stop timing 2 14 2 Data Flash Memory Characteristics Table 2 53 Data flash memory characteristics Conditions Program Erase 4 to 60 MHz Read FCLK s 60 MHz 4 MHz 20 MHz lt s 60 MHz Item Symbol Min Typ Max Min Typ Max Unit Programming time 4 byte tpp4 0 36 3 8 0 16 1 7 ms Erasure time 64 byte tpEe4 3 1 18 1 7 10 ms Blank check time 4 byte tppc4 84 30 us Reprogramming erasure cycle 1 125000 2 125000 2 Suspend delay during programming tospp 264 120 us First suspend delay during erasure in tpsEsp1 216 120 us suspend priority mode Second suspend delay during erasure in tpsesp2 300 300 us suspend priority mode Suspend delay during erasing in erasure tpsegp 300 300 us priority mode 01050262 1 0080 Rev 0 80 ztENESAS Page 103 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics Table 2 53 Data flash memory characteristics Conditions Program
83. g Table 2 34 USBHS low speed characteristics for host only USBHS DP and USBHS DM pin characteristics Conditions USBHS RREF 2 2 1 USBMCLK 20 24 MHz UCLK 48 MHz Item Symbol Min Typ Max Unit Test conditions Input Input high level voltage 2 0 V characteristics Input low level voltage 0 8 V Differential input sensitivity Vpi 0 2 V USBHS DP USBHS DM Differential common mode Vom 0 8 2 5 V range Output Output high level voltage 2 8 3 6 V 200 pA characteristics tout low level voltage VoL 00 0 3 V 2 5 Cross over voltage Vers 1 3 2 0 V Figure 2 76 Rise time tR 75 300 ns l Fall time tLe 75 300 ns Rise fall time ratio tLe 80 125 tLe Pull up USBHS_DP and USBHS DM Rpa 14 25 24 80 KQ Pull down pull down resistors host characteristics USBHS_DP Vors USBHS_DM Figure 2 76 USBHS_DP and USBHS_DM output timing in low speed mode Observation USBHS_DP J point 200 pF to 7777 USBHS DM 200 pF to 600 pF Figure 2 77 Test circuit in low speed mode RO1DS0262EU0080 Rev 0 80 ESAS Page 87 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics Table 2 35 USBHS full speed characteristics USBHS DP and USBHS DM pin charac
84. ge exceeds VCC 10 and falling gradient RO1DS0262EU0080 Rev 0 80 ESAS Page 37 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics 2 2 Ripple waveform RO1DS0262EU0080 Rev 0 80 ESAS Page 38 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics 2 3 AC Characteristics 2 3 1 Frequency Table 2 10 Operation frequency value in high speed mode Item Symbol Min Typ Max Unit Operation frequency System clock ICL f 240 Peripheral module clock PCLKA 2 120 Peripheral module clock PCLKB 2 60 Peripheral module clock PCLKC 2 3 60 Peripheral module clock PCLKD 2 120 Flash IF clock FCLK 2 1 E 60 External bus clock BCLK 2 2 120 EBCLK pin output 60 SDCLK pin output VCC 23 0 V 120 Note 1 FCLK must run at a frequency of at least 4 MHz when programming or erasing the flash memory Note 2 See section 9 Clock Generation Circuit in User s Manual for the relationship of frequencies between the PCLKA PCLKB PCLKC PCLKD FCLK and BCLK Note 3 When the 12 bit A D converter is used the frequency must be set to at leas
85. his value normalizes the differences shared with each line 1 LSB resolution 2 3 9 CAC Timing Table 2 21 CAC timing Test conditions Item tpgoyc 2 tppcyc gt tcac 4 9 tppoyc CACREF input pulse width Note 1 tpgcyc PCLKB cycle Note 2 tcaci count clock source cycle 5 x 65x tpBcyc 01050262 00080 Rev 0 80 ESAS Page 63 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics 2 3 10 SCI Timing Table 2 22 SCI timing 1 Conditions High drive output is selected with the port drive capability bit in the PmnPFS register for the following pins SCKO to SCK9 except for SCK4 B SCK7 A SCK4 B For other pins middle drive output is selected with the port drive capability bit in the PmnPFS register Test Item Symbol Min Max Unit conditions SCI Input clock cycle Asynchronous tscyc 4 Figure 2 36 6 synchronous Input clock pulse width tsckw 0 4 0 6 tscyc Input clock rise time tsckr 5 ns Input clock fall time 5 ns Output clock cycle Asynchronous tscyc 6 tPoyc Clock 4 synchronous Output clock pulse width tsckw 0 4 0 6 tscyc Output clock rise time tsckr 5 ns Output clock fall time tsckt 5 ns Transmit d
86. ime when is below the minimum value of voltage detection levels for POR and LVD The low power function is disabled and DEEPCUT 1 0 00b or 01b The low power function is enabled and DEEPCUT 1 0 11b 01050262 00080 Rev 0 80 Oct 12 2015 2tENESAS Page 96 of 111 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics Internal reset signal low is valid laet Figure 2 91 Voltage detection circuit timing LVCMPCR LVD1E LVD1 Comparator output LVD1CRO CMPE LVD1SR MON Internal reset signal Active low When LVD1CRO RN 0 lt gt oer laet When LVD1CRO RN 1 Figure 2 92 Voltage detection circuit timing Vget1 RO1DS0262EU0080 Rev 0 80 ESAS Page 97 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics LVCMPCR LVD2E LVD2 Comparator output LVD2CRO CMPE LVD2SR MON Internal reset signal Active low When LVD2CRO RN 0 or laet taet li vp2 When LVD2CRO RN 1 tivp2 Figure 2 93 Voltage detection circuit timing Vget2 2 10 Characteristics Table 2 47 Battery backup function characteristi
87. inary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics CSRWAIT 2 CSROFF 2 Byte strobe mode A23 to AO 1 write strobe mode A23 to 1 BC1 BCO Common to both byte strobe mode and 1 write strobe mode CS7 to CSO RD Read D15 to DO Read Figure 2 15 External bus timing normal read cycle bus clock synchronized RO1DS0262EU0080 Rev 0 80 2tENESAS Page 49 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics CSWWAIT 2 CSWOFF 2 Byte strobe mode A23 to 0 1 write strobe mode A23 to A1 BC1 to BCO Common to both byte strobe mode and 1 write strobe mode CS7 to CSO WR1 WRO WR Write D15 to DO Write Note Always specify WDON and WDOFF as at least one EBCLK cycle Figure 2 16 External bus timing normal write cycle bus clock synchronized RO1DS0262EU0080 Rev 0 80 ESAS Page 50 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics CSRWAIT 2 CSPRWAIT 2 CSPRWAIT 2 CSPRWAIT 2 CSROFF 2 Byte strobe mode A23 to AO 1 write strobe mode A23 to Al BCt Com
88. ing capacitor used to stabilize VCL_F Input the internal power supply Place the capacitor close to the pin VSS Input Ground pin Connect it to the system power supply 0 V VBATT Input Backup power pin Clock XTAL Output Pins for a crystal resonator An external clock signal can be input through the EXTAL Input EXTAL pin XCIN Input Input output pins for the sub clock oscillator Connect a crystal resonator XCOUT Output between XCOUT and XCIN EBCLK Output Outputs the external bus clock for external devices SDCLK Output Outputs the SDRAM dedicated clock CLKOUT Output Clock output pin Operating mode MD Input Pins for setting the operating mode The signal levels on these pins must not control be changed during operation mode transition at the time of release from the reset state System control RES Input Reset signal input pin This MCU enters the reset state when this signal goes low CAC CACREF Input Measurement reference clock Input pin On chip emulator TMS VO On chip emulator or boundary scan pins TDI Input TCK Input TDO Output TRCLK Output This pin outputs the clock for synchronization with the trace data TRDATAO to Output These pins indicate that output from the TRDATAO to TRDATAS pins is valid TRDATA3 SWDIO VO Serial wire debug data input output pin SWCLK Input Serial wire clock pin SWO Output Serial wire trace output pin External bus RD Output Strobe signal which indicates that reading from the external bus interface interf
89. istics Table 2 49 ACMPHS characteristics Item Symbol Min Typ Max Unit Test conditions Reference voltage range VREF 0 AVCCO V Input voltage range 0 AVCCO V Output delay 1 Td 50 100 ns VI VREF 100 mV Note 1 This value is internal propagation delay 01050262 00080 Rev 0 80 ESAS Page 99 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics 2 13 PGA Characteristics Table 2 50 PGA characteristics in single mode Item Symbol Min Typ Max Unit PGAVSS input voltage range PGAVSS 0 0 V AINO 2 000 0 050 x AVCCO 0 45 x AVCCO V AIN1 2 500 0 047 x AVCCO 0 360 x AVCCO V AIN2 2 667 0 046 x AVCCO 0 337 x AVCCO V AIN3 2 857 0 046 x AVCCO 0 32 x AVCCO V 4 3 077 0 045 0 292 5 3 333 0 044 0 265 V 6 3 636 0 042 0 247 V 7 4 000 0 040 0 212 V 8 4 444 0 036 0 191 V 9 5 000 0 033 x AVCCO 0 17 x AVCCO V AIN10 5 714 0 031 x AVCCO 0 148 x AVCCO V AIN11 6 667 0 029 x AVCCO 0 127 x AVCCO V AIN12
90. ld when exposed to a CMOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop the generation of static electricity as much as possible and quickly dissipate it when it occurs Environmental control must be adequate When it is dry a humidifier should be used This is recommended to avoid using insulators that can easily build up static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work benches and floors must be grounded The operator must also be grounded using a wrist strap Semiconductor devices must not be touched with bare hands Similar precautions must be taken for printed circuit boards with mounted semiconductor devices 2 Processing at power on The state of the product is undefined at the time when power is supplied The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the time when power is supplied In a finished product where the reset signal is applied to the external reset pin the states of pins are not guaranteed from the time when power is supplied until the reset process is completed In a similar way the states of pins in a product that is reset by an on chip power on reset function are not guaranteed from the time when power is supplied until the power reaches the le
91. le time 20 ns Figure 2 59 to RMII REF50CK frequency typical 50 MHz 5 B 50 100 MHz gure 2 62 REF50CK duty 35 65 REF50CK rise fall time Teck 0 4 3 5 ns RMII_xxxx 1 output delay 2 5 12 0 ns xxxx setup time Tsui 3 ns RMII_xxxx 2 hold time 1 ns xxxx 2 rise fall time T T 0 5 4 ns ET_WOL output delay twoLd 1 23 5 ns Figure 2 63 ETHERC ET TX CLK cycle time 40 ns TX EN output delay 1 20 ns 2 64 ET ETXDO to ETXD3 output delay 1 20 ns ET CRS setup time tcRss 10 ns ET CRS hold time 10 ns ET COL setup time 10 ns Figure 2 65 ET COL hold time 10 ns ET RX CLK cycle time trRoyc 40 ns RX DV setup time trovs 10 ns Figure 2 66 ET_RX_DV hold time trovh 10 ns ET ERXDO to ET_ERXD3 setup time MRDs 10 ns ET ERXDO to ET_ERXD3 hold time tMRDh 10 ns ET RX ER setup time tRERs 10 ns Figure 2 67 ET_RX_ER hold time tRESh 10 ns WOL output delay twoLd 1 23 5 ns Figure 2 68 Note 1 RMII TXD EN RMII TXD1 RMII TXDO Note 2 RMII CRS DV RMII RXD1 RMII RXDO RX ER 01050262 00080 Rev 0 80 ESAS Page 80 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics REFSOCK 90 oxxx 5096 signal level 10 L Note RMII_TX
92. lement a system evaluation test for the given product Notice 1 Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information 2 Renesas Electronics has used reasonable care in preparing the information included in this document but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein 3 Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is granted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others 4 You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Renesas Electronics assumes no responsibility fo
93. linearity error 1 0 5 5 LSB Note These specification values apply when there is no access to the external bus during A D conversion If access proceeds during A D conversion values might not fall within the indicated ranges Note 1 The conversion time includes the sampling time and the comparison time The number of sampling states is indicated for the test conditions Note 2 Values in parentheses indicate the sampling time 01050262 00080 Rev 0 80 Oct 12 2015 234 N SAS Page 92 of 111 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics Table 2 41 conversion characteristics for unit 1 Conditions PCLKC 1 to 60 MHz Item Min Typ Max Unit Test conditions Frequency 1 60 MHz Analog input capacitance 30 pF Quantization error 0 5 LSB Resolution 12 Bit Channel dedicated Conversion time Permissible signal 1 06 us Sampling of channel sample and hold operation at Source impedance 0 4 0 25 2 dedicated sample and hold circuits in use PCLKC 60 MHz 1 circuits in 24 states AN100 to AN102 e Sampling 15 states Offset error 1 5 3 5 LSB AN100 to AN102 0 25 V Full scale error x1 5 3 5 LSB AN100 to AN102 VR
94. mage load address in code flash memory to the application image link address in the unused memory 23 bit space memory mirror space addresses The user application code is developed and linked to run from this MMF destination address The user application code does not need to know the load location where it is stored in code flash memory See section 5 Memory Mirror Function MMF in User s Manual SRAM This MCU has an on chip high speed SRAM with either parity bit or Double bit Error Detection DED The first 32 KB of the SRAMO is subject to DED Parity check is performed for other areas See section 52 SRAM in User s Manual Standby SRAM This MCU provides an on chip SRAM that can retain data in Deep Software Standby mode See section 53 Standby SRAM in User s Manual RO1DS0262EU0080 0 80 134 NE SAS Page 2 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 1 Overview Table 1 3 System Feature Operating mode Functional description Two operating modes Single chip mode SCI USB boot mode See section 3 Operating Modes in User s Manual Reset This MCU has 14 types of resets RES pin reset Power on reset e Voltage monitor reset 0 e Voltage monitor reset 1 e Voltage monitor reset 2 e Independent watchdog timer reset e Watchdog timer reset e Deep software standby reset SRAM parity
95. minary document S7 Series Specifications in this document are tentative and subject to change 1 Overview 1 6 Pin Assignments Figure 1 3 to Figure 1 8 show the pin assignments Figure 1 3 R7FS7G2xxxA01CBD P212 JEXTAL 902 901 VCL1 vss VLO VLO vcc_ DCDC P200 P911 P912 P905 P312 VSS vcc P300 TCK SWCLK VREFHO VREFH 108 5 SWDIO 109 00 SWO Pin assignment for BGA 224 pin Upper perspective view P110 TDI 01050262 00080 Rev 0 80 Oct 12 2015 134 NE SAS Page 18 of 111 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 1 Overview R7FS7G2xxxA01CBG P212 JEXTAL VREFLO VREFHO P300 TCK SWCLK P110 TDI Figure 1 4 Pin assignment for BGA 176 pin Upper perspective view RO1DS0262EU0080 Rev 0 80 ztENESAS Page 19 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 1 Overview 91 P110 TDI 90 P109 TDO SWO 89 P108 TMS SWDIO 132 P100 1310 P101 130 1 P102 129 P103 128 P104 127 P105 1267 P106 125 P107 122 P600 1217 P601 1207 P602 119L P603 P604 1177 P605 116 606 1157 P607 1147 PAOO 113 PAO1 1127 VCL_F 10
96. modules as event signals to connect them to different modules enabling direct interaction between the modules without CPU intervention See section 19 Event Link Controller ELC in User s Manual Table 1 6 Direct memory access Feature Functional description Data Transfer Controller DTC This MCU incorporates a Data Transfer Controller DTC that performs data transfers when activated by an interrupt request See section 18 Data Transfer Controller DTC in User s Manual DMA Controller DMAC This MCU incorporates an 8 channel DMA Controller DMAC module that can transfer data without the CPU When a DMA transfer request is generated the DMAC transfers data stored at the transfer source address to the transfer destination address See section 17 DMA Controller DMAC in User s Manual Table 1 7 External bus interface Feature Functional description External bus CS area EXBIU Connected to the external devices external memory interface SDRAM area EXBIU Connected to the SDRAM external memory interface QSPI area EXBIUT2 Connected to the QSPI external device interface Table 1 8 Timers Feature Functional description General PWM Timer GPT The General PWM Timer GPT is a 32 bit timer with 14 channels PWM waveforms can be generated by controlling the up counter down counter or the up and down counter In addition PWM waveforms for controlling brushless DC motors can be generated The GPT can al
97. mon to both byte strobe mode and 1 write strobe mode cs7 tocso RD Read D15 to DO Read Figure 2 17 External bus timing page read cycle bus clock synchronized CSWWAIT 2 CSPWWAIT 2 CSPWWAIT 2 CSWOFF 2 WDOFF 1 WDOFR IE WDON 1 Byte strobe mode A23 to AO 1 write strobe mode A23 to A1 BC1 BCO Common to both byte strobe mode and 1 write strobe mode CS7 toCSOR twro WR1 WRO WR Write q twop twop D15 to DO Write ES Note 1 Always specify WDON and WDOFF as at least one EBCLK cycle Figure 2 18 External bus timing page write cycle bus clock synchronized RO1DS0262EU0080 Rev 0 80 2tENESAS Page 51 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics CSRWAIT 3 CSWWAIT 3 Tena A23 to CS7 to CSO RD read WR write External wait Figure 2 19 External bus timing external wait control RO1DS0262EU0080 Rev 0 80 2tENESAS Page 52 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2
98. n Interrupt NMI Input Non maskable interrupt request pin IRQO to IRQ15 Input Maskable interrupt request pins GPT GTETRGA Input External trigger input pin GTETRGB GTETRGD GTIOCOA to Input capture output compare or PWM output GTIOC13A GTIOCOB to GTIOC13B GTIU Input Hall sensor input pin U GTIV Input Hall sensor input pin V GTIW Input Hall sensor input pin W GTOUUP Output Three phase PWM output for BLDC motor control positive U phase GTOULO Output Three phase PWM output for BLDC motor control negative U phase GTOVUP Output Three phase PWM output for BLDC motor control positive V phase GTOVLO Output Three phase PWM output for BLDC motor control negative V phase GTOWUP Output Three phase PWM output for BLDC motor control positive W phase GTOWLO Output Three phase PWM output for BLDC motor control negative W phase AGT AGTEEO AGTEE1 Input External event input enable AGTIOO AGTIO1 External event input and pulse output AGTO1 Output Pulse output AGTOAO AGTOA1 Output Output compare match A output AGTOBO 1 Output Output compare match B output RTC RTCOUT Output Output pin for 1 Hz 64 Hz clock RTCICO to RTCIC2 Input Time capture event input pins SCI SCKO to SCK9 Input output pins for the clock clock synchronous mode RXDO to RXD9 Input Input pins for received data asynchronous mode clock synchronous mode TXDO to TXD9 Output Output pins for transmitte
99. nal description e Security algorithm Symmetric algorithm AES 3DES 4 Asymmetric algorithm RSA DSA DLP e Other support features TRNG True Random Number Generator Hash value generation SHA1 SHA224 SHA256 GHASH Unique ID 128 bit RO1DS0262EU0080 Rev 0 80 Oct 12 2015 ztENESAS Page 8 of 111 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 1 Overview 1 2 Block Diagram Figure 1 1 shows the block diagram of this MCU superset Individual devices within the group may have a subset of the features Memories Interrupt Control ARM Cortex M4 System 4 MB Code Flash ICU FPU POR LVD Clocks 64 KB Data Flash 640 KB SRAM 8 Standby SRAM MOSC SOSC Reset External H M L OCO CSC System Timer Mode Control PLL USBPLL Power Control Test and Register Write Protecion Battery Backup Timers Communication Interfaces Human Machine Interfaces GPT32EH x 4 GPT32E 4 GPT32x6 AGT x 2 RTC WDT IWDT Event Link Security SCE7 Figure 1 1 Graphics SCI x 10 QSPI USBHS IrDA 1 2 with IEEE 1588 IC x 3 SDHI x 2 SPI x 2 CAN x 2 SSI x 2 USBFS Data Processing CRC SRC DOC Block diagram ADC12 with PGA x 2 DAC12 GLCDC
100. nctional description A key interrupt KINT can be generated by setting the Key Return Mode register KRM and inputting a rising falling edge to the key interrupt input pins See section 21 Key Interrupt Function KINT in User s Manual The Capacitive Touch Sensing Unit CTSU Table 1 12 Graphics Feature Graphics LCD Controller GLCDC The Capacitive Touch Sensing Unit CTSU measures the electrostatic capacitance of the touch sensor Changes in the electrostatic capacitance are determined by software which enables the CTSU to detect whether a finger is in contact with the touch sensor The electrode surface of the touch sensor is usually enclosed with an electrical conductor so that a finger does not come into direct contact with the electrode See section 50 Capacitive Touch Sensing Unit CTSU in User s Manual Functional description The GLCDC provides multiple functions and supports various types of data formats and panels Key GLCDC features include GPX bus master function for accessing graphics data e Superimposition of three planes single color background plane graphic 1 plane and graphic 2 plane e Supports various types of 32 bit or 16 bit per pixel graphics data and 8 bit 4 bit or 1 bit LUT data format Digital interface signal output supporting the video image size of WVGA or greater See section 57 Graphics LCD Controller GLCDC in User s Manual 2D Drawing Engine DRW JPEG Codec JPEG
101. nded to their names for instance A or B to indicate group membership For the IIC interface the AC portion of the electrical characteristics is measured for each group 01050262 00080 Rev 0 80 24 NE S AS Page 76 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics SDAO to SDA3 tsros SCLO to SCL3 Test conditions Vin VCC x 0 7 Va VCC 0 3 Vor 0 6 V o 6 mA ICFER FMPE 0 Vor 0 4 V oL 15 mA ICFER FMPE 1 Note 1 S P and Sr indicate the following S Start condition P Stop condition Sr Restart condition Figure 2 53 bus interface input output timing 2 3 14 SSI Timing Table 2 29 SSI timing Conditions Middle drive output is selected with the port drive capability bit in the PmnPFS register Test Item Symbol Min Max Unit conditions SS AUDIO ClKimutfreqlency tyo 5 h Output clock period to 150 64000 ns Figure 2 54 Input clock period ti 150 64000 ns Clock high pulse width tuc 60 ns Clock low pulse width tic 60 ns Clock rise time tre 25 ns Data delay tprR 5 25 ns Figure 2 55 Set up time tsp 25 ns Pie aap Hold time 25 ns SSIDATA output delay from WS change time TprRw 25 ns Figure 2 57 Note 1 Renesas recommends
102. nder development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics SPI SSLAO to SSLA3 outpu 155 tssur MSB OUT Figure 2 48 RSPI timing master CPHA 1 bit rate PCLK division ratio is set to 1 2 SPI SSLAO input RSPCKA CPOL 0 input RSPCKA CPOL 1 input MSB OUT tsu MSB IN Figure 2 49 SPI timing slave CPHA 0 RO1DS0262EU0080 0 80 ESAS Page 72 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics SPI SSLAO input RSPCKA CPOL 0 input RSPCKA CPOL 1 input MISOA LSB OUT MSB OUT output Figure 2 50 SPI timing slave CPHA 1 2 3 12 QSPI Timing Table 2 26 QSPI timing Conditions High drive output is selected with the port drive capability bit in the PmnPFS register Item Symbol Min Max Test conditions QSPI QSPCK clock cycle tascyc 2 48 pcyc Figure 2 51 QSPCK clock high level pulse width taswH tascyc 0 4 ns QSPCK clock low level pulse width toswL tascyc 0 4 ns Data input setup time tsu 11 ns Figure 2 52 Data input hold time 0 ns QSSL setup time EAD N 0 5 x N 0 5 x ns tascyc 5 2 tascyc 100 2 QSSL hold time ti AG N 0 5 x 0 5 x ns tascyc 5 3 tascyc 100 3 Da
103. nerator TRNG Ethernet DMA Controller EDMAC Ethernet PTP Controller EPTPC m Human Machine Interface HMI USB 2 0 High Speed Module USBHS Graphics LCD Controller GLCDC On chip transceiver JPEG Codec USB battery charge 1 2 version supported 2D Drawing Engine DRW USB 2 0 Full Speed Module USBFS Capacitive Touch Sensing Unit CTSU On chip transceiver Parallel Data Capture Unit PDC Serial Communications Interface SCI with FIFO x 10 Multiple Clock Sources Serial Peripheral Interface SPI x 2 Main clock oscillator MOSC 8 to 24 MHz e 2C bus interface x 3 Sub clock oscillator SOSC 32 768 kHz CAN module CAN x 2 E e High speed on chip oscillator HOCO 16 18 20 MHz Serial Sound Interface SSI x 2 e Middle speed on chip oscillator MOCO 8 MHz e SD MMC Host Interface SDHI x 2 E Low speed on chip oscillator LOCO 32 768 kHz Quad Serial Peripheral Interface QSPI interface Independent watchdog timer OCO 15 kHz e Sampling Rate Converter SRC Clock trim function for HOCO MOCO LOCO Clock out support External memory bus 8 bit and 16 bit address width m General Purpose Ports SDRAM support Up to 172 input output pins Analog Up to 9 CMOS input 12 Bit A D Converter ADC12 with 3 sample and hold circuit Ups input output Up to 22 5 V tolerant input output cach x2 Up to 24 pins high t 20 m
104. nesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations 9 Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction When exporting the Renesas Electronics products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations 10 It is the responsibility of the buyer or distributor of Renesas Electronics products who distributes disposes of or otherwise places the product with a third party to notify such third party in advance of the contents and conditions set forth in this document Renesas Electronics assumes no
105. ntative and subject to change S7 Series 2 Electrical Characteristics SDRAM command Ts RFA RFA SDCLK 15 to AO tcsp2 High D15 to DO Note Address pins are for output of the precharge setting command Precharge sel for the SDRAM Figure 2 26 SDRAM self refresh timing 01050262 00080 Rev 0 80 ESAS Page 59 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics 2 3 7 I O Ports POEG GPT32 KINT and ADC12 Trigger Timing Table 2 19 ports POEG GPT32 KINT and ADC12 trigger timing GPT32 Conditions Middle drive output is selected with the port drive capability bit in the PmnPFS register for the following pins GTIOC6A A GTIOC6B GTIOC3A GTIOC3B B GTIOCOA B GTIOCOB B GTIOC9A B GTIOC9B High drive output is selected with the port drive capability bit in the PmnPFS register for all other pins AGT Conditions Middle drive output is selected with the port drive capability bit in the PmnPFS register Test Item Symbol Min Max Unit conditions Ports Input data pulse width tprw 1 5 Figure 2 27 POEG input trigger pulse width 3 Figure 2 28 GPT32 Input capture pulse width Single edge teticw 1 5
106. nual RO1DS0262EU0080 Rev 0 80 Oct 12 2015 ztENESAS Page 3 of 111 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 1 Overview Table 1 3 System Feature Functional description Independent Watchdog Timer IWDT The Independent Watchdog Timer IWDT consists of a 14 bit down counter that must be serviced periodically to prevent counter underflow The IWDT provides functionality to reset the MCU or to generate a non maskable interrupt interrupt for a timer underflow Because the timer operates with an independent dedicated clock source it is particularly useful in returning the MCU to a known state as a fail safe mechanism when the system runs out of control The watchdog timer can be triggered automatically on a reset underflow or refresh error or by a refresh of the count value in the registers See section 28 Independent Watchdog Timer IWDT in User s Manual Table 1 4 Interrupt control Feature Functional description Interrupt Controller Unit ICU The Interrupt Controller Unit ICU controls which event signals are linked to the NVIC DTC module and DMAC module The ICU also controls NMI interrupts See section 14 Interrupt Controller Unit ICU in User s Manual Table 1 5 Event link Feature Event Link Controller ELC Functional description The Event Link Controller ELC uses the interrupt requests generated by various peripheral
107. number Extbus Timers Communication interfaces Analog HMI 9 28 5 o 8 22 2 SM E 5 51 e R 99 z gt ERER 5 A lt o lt 5 N n S x lt rira 5 8 a 5 S 5 523 o 8 8 S E E 882525210 z 3 3 895 2 2 2 a 21 1 20 Q lt o 9 58509 09 9 Ole 5 ajaa o 1 122 4 8 67 P600 RD LCD DATA 2 2 4 2 k2 99 VCC Mi 24 VSS 2 25 3 101 68 P107 07 007 GTIO CTS8 KRO7 LCD_ C8A_ LA DATA A 1A 4 1 126 102 69 P106 06 006 GTIO SCK8 SSLA 06 LCD_ C8B_ LA 127 103 70 P105 095 005 TXD8 SSLA IRQO LCD _ _ 2A KRO05 TCON SMOS l8 SSDA 8A 2 128 3 104 71 P104 94 004 RXD8 SSLA IRQ1 LCD RGB AI 1A KR04 TCON B SMIS 2A O8 Al SSCL BA 129 1 105 72 P103 03 003 GTIO 50 SSLA KRO3 LCD WUP C2A LA OA TCON A A 1A 130 M 106 73 P102 02 092 AGTO GTO SCKO RSPC ADTR KR02 LCD_ 0 WLO C2B LA TCON A A A 0A 131 2 107 74 P101 01 GTET CTS1 SDA1 MOSI IRQ1 LCD RGB A A KRO1 CLK A SMOS A I0 A SSDA 0A Ri 7 132 108 75 P100 00 000 GTET RXDO SCK1 SCL1 MISO IRQ2 LCD O
108. of 111 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics Table 2 14 Clock timing for sub clock Sub clock frequency fsuB 32 768 Sub clock oscillation stabilization wait time tsUBOSCWT 1 2 S Note 1 When setting up a sub clock ask the oscillator manufacturer for an oscillation evaluation Use the results as the recommended oscillation stabilization time Note 2 After changing the setting in the SOSCCR SOSTP bit to start the sub clock oscillator operation only start using the sub clock after the sub clock oscillation stabilization time has elapsed with an adequate margin Two times the value shown is recommended tspoyc tcu EBCLK pin output SDCLK pin output Figure 2 3 EBCLK and SDCLK output timing EXTAL external clock input VCC x 0 5 Figure 2 4 EXTAL external clock input timing MOSCCR MOSTP twainosc Main clock oscillator output tMmainoscwT Main clock Figure 2 5 Main clock oscillation start timing LOCOCR LCSTP Y On chip oscillator output UM tiocowr LOCO clock Figure 2 6 LOCO clock oscillation start timing RO1DS0262EU0080 0 80 2tENESAS Page 41 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 S
109. om the inputs are converted to the internal format on read and a conversion back is done on write See section 55 2D Drawing Engine DRW in User s Manual The JPEG Code JPEG incorporates a JPEG codec that conforms to the JPEG baseline compression and decompression standard This provides high speed compression of image data and high speed decoding of JPEG data See section 56 JPEG Codec in User s Manual Parallel Data Capture Unit PDC This MCU includes a single Parallel Data Capture unit PDC The PDC has the function of communicating with external I O devices including image sensors and transferring parallel data such as an image output from the external device through the or DMAC to the on chip SRAM and external address spaces the CS and SDRAM areas See section 44 Parallel Data Capture Unit PDC in User s Manual RO1DS0262EU0080 Rev 0 80 Oct 12 2015 134 NE SAS Page 7 of 111 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 1 Overview Table 1 13 Data processing Feature CRC Calculator CRC Functional description The Cyclic Redundancy Check CRC generates CRC codes to detect errors in the data The bit order of CRC calculation results can be switched for LSB first or MSB first communication Additionally various CRC generation polynomials are available The snoop function allows monitoring reads from and writes to
110. on 3 When using the SDRAM area controller SDRAMC and CS area controller CSC simultaneously BCLK SDCLK 8 to 60 MHz VCC AVCCO VCC USB VBATT 3 0 to 3 6 V VREFH VREFHO 3 0 V to AVCCO USBHS AVCC USBHS 3 0 to 3 6 V Output load conditions VOH x 0 5 VOL VCC x 0 5 C 15 pF High drive output is selected with the port drive capability bit in the PmnPFS register Item Symbol Min Max Unit Test conditions Address delay tAD 12 5 ns Figure 2 15 to Byte control delay tBcp 12 5 ns Figure 2 16 CS delay tcsp 12 5 ns RD delay trsp 12 5 ns Read data setup time 205 12 5 ns Read data hold time 0 ns WR delay twRD gt 12 5 ns Write data delay twpp 12 5 ns Write data hold time twpH 0 ns WAIT setup time twts 12 5 ns Figure 2 19 WAIT hold time twrH 0 ns Address delay 2 SDRAM tap2 0 8 6 8 ns Figure 2 20 to CS delay 2 SDRAM tesh 0 8 6 8 ns Figure 2 26 DQM delay SDRAM 0 8 6 8 ns CKE delay SDRAM 0 8 6 8 ns Read data setup time 2 SDRAM 2032 2 9 ns Read data hold time 2 SDRAM 1 2 1 5 ns Write data delay 2 SDRAM twpp2 6 8 ns Write data hold time 2 SDRAM twpu2 0 8 ns WE delay SDRAM twED 0 8 6 8 ns RAS delay SDRAM 0 8 6 8 ns CAS delay SDRAM tcasp 0 8 6 8 ns 01050262 00080 Rev 0 80 ESAS Page 48 of 111 Oct 12 2015 Under development Prelim
111. orts 5V tolerant 5 x 0 8 5 8 ViL 0 3 VCC x 0 2 Other input 6 Vin VCC x 0 8 0 3 0 3 VCC x 0 2 Note 1 SCLO B SCL1 B SDA1 Note 2 SCLO A SDAO A SDAO B SCL1 A SDA1 A SCL2 SDA2 01050262 00080 Rev 0 80 ESAS Page 33 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics Note 3 RES and peripheral function pins associated with P205 P206 P400 P401 P407 to P415 P511 P512 P708 to P713 01 Note 4 All input pins except for the peripheral function pins already described in the table Note 5 P205 P206 P400 P401 P407 to P415 P511 P512 P708 to P713 01 total 22pins Note 6 All input pins except for the ports already described in the table 2 23 lou lo Table 2 5 lor Item Symbol Min Typ Max Unit Permissible output current Ports P008 to P011 P212 2 0 2 0 mA Ports 014 015 213 P400 lou 4 0 mA P401 P511 P512 4 0 402 404 Low drive 1 2 0 mA lo 2 0 mA Middle drive 2 4 0 a 4 0 mA Po
112. own down resistance in host characteristics controller mode Figure 2 84 USB_DP and USB_DM output timing in low speed mode Observation J point 200 pF to T 600 pF I 200 pF to 12 600 pF Figure 2 85 Test circuit in low speed mode 01050262 00080 Rev 0 80 ESAS Page 90 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics Table 2 39 USBFS full speed characteristics USB DP and USB DM pin characteristics Conditions VCC AVCCO USB VBATT 3 0 to 3 6 V 2 7 lt VREFHO VREFH lt AVCCO USBHS USBHS 3 0 to 3 6 V USBA RREF 22 1 USBMCLK 20 24 MHz UCLK 48 MHz Item Symbol Min Typ Max Unit Test conditions Input Input high level voltage 2 0 V Input low level voltage ViL 0 8 V Differential input sensitivity Vpi 0 2 V USB DP USB DM Differential common mode VcM 0 8 2 5 V range Output Output high level voltage 2 8 3 6 V 200 pA characteristics lO tout low level voltage VoL 0 0 i 0 3 V lg22mA Cross over voltage Vers 1 3 x 2 0 V Figure 2 86 Rise time tLe 4 20 ns Fall time tLe 4 20 ns Rise fall time ratio tLe tr 90 111 11 96 teR ter Output resistance 28 44 Q USBFS Rs 27 Q included Pull up and
113. pull DM pull up resistance in Rpu 0 900 1 575 kQ During idle state down EM 1 425 3 090 During transmission characteristics reception USB DP and USB DM pull Rog 14 25 24 80 kQ down resistance in host controller mode USB_DP Vers USB_DM Figure 2 86 USB_DP and USB_DM output timing in full speed mode Observation Z point 50 7 Figure 2 87 Test circuit in full speed mode R01DS0262EU0080 Rev 0 80 2 1 91 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 5 Normal precision channel ADC12 Characteristics 2 Electrical Characteristics Table 2 40 conversion characteristics for unit 0 Conditions PCLKC 1 to 60 MHz Item Min Typ Max Unit Test conditions Frequency 1 60 MHz Analog input capacitance 30 pF Quantization error 0 5 LSB Resolution 12 Bit Channel dedicated Conversion time Permissible signal 1 06 us e Sampling of channel sample and hold operation at Source impedance 0 4 0 25 2 dedicated sample and hold circuits in use PCLKC 60 MHz 1 circuits in 24 states 000 to 002 Sampling in 15 states Offset error 1 5 3 5 15 ANO00 to 002 0 25 V Full scale error 1 5 3 5 LSB 0
114. put 2 bit transmit data in RMII mode RMIIO_TXD1 RMII1_TXDO RMII1_TXD1 RMIIO_RXDO Input 2 bit receive data in RMII mode RMIIO_RXD1 RMII1_RXDO RMII1_RXD1 RMIIO_TXD_EN Output Output pins for data transmit enable signals RMII mode RMII1_TXD_EN RMIIO_RX_ER Input Indicate an error has occurred during reception of data in RMII mode RMII1_RX_ER ETO_CRS ET1_CRS Input Carrier detection data reception enable pins ETO_RX_DV Input Indicate that there are valid receive data on ET_ERXD3 to ET_ERXDO ET1_RX_DV ETO_EXOUT Input General purpose external output pins ET1_EXOUT ETO_LINKSTA Output Input link status from the PHY LSI ET1_LINKSTA ETO ETXDO to output 4 bits of MII transmit data ETO_ETXD3 ET1 ETXDO to ET1 ETXDS ETO ERXDO to Input 4 bits of MII receive data ETO_ERXD3 ET1 ERXDO to ET1_ERXD3 ETO_TX_EN Output Transmit enable pins Function as signals indicating that transmit data is ET1_TX_EN ready on ET_ETXD3 to ET_ETXDO ETO_TX_ER Output Transmit error pins Function as signals notifying the PHY_LSI of an error ET1_TX_ER during transmission ETO_RX_ER Input Receive error pins Function as signals to recognize an error during ET1_RX_ER reception ETO TX CLK Input Transmit clock pins These pins input reference signals for output timings ET1 TX CLK from TX EN ETXD3 to ETXDO ET TX ER ETO RX CLK Input Receive clock pins These pins input reference signals for input timings to ET1 RX CLK RX DV
115. put low pulse width tscLL 3 6 300 ns SCL SDA input rise time tsr 1000 ns SCL SDA input fall time ter 300 ns SCL SDA input spike pulse removal tsp 0 1 4 ns time SDA input bus free time when tgur 3 6 300 ns wakeup function is disabled SDA input bus free time when tBur 3 6 thiccyc 4 ns wakeup function is enabled 300 START condition input hold time 15 tiiccye 300 ns when wakeup function is disabled START condition input hold time 15 1 5 ns when wakeup function is enabled 300 Repeated START condition input 1000 ns setup time STOP condition input setup time tsros 1000 ns Data input setup time tspas 50 ns Data input hold time tspaH 0 ns SCL SDA capacitive load Cp 400 pF SCL input cycle time 6 12 thiccye 600 ns Figure 2 53 Fast imode SCL input high pulse width 3 6 ticcye 300 ns SCL input low pulse width tsciL 3 6 300 ns SCL SDA input rise time tsr 20 x external pullup 300 ns voltage 5 5V 2 SCL SDA input fall time ter 20 x external pullup 300 ns voltage 5 5V 2 SCL SDA input spike pulse removal tsp 0 1 4 tliceye ns time SDA input bus free time when tgur 3 6 300 ns wakeup function is disabled SDA input bus free time when tBur 3 6 4 ns wakeup
116. r any losses incurred by you or third parties arising from such alteration modification copy or otherwise misappropriation of Renesas Electronics product 5 Renesas Electronics products are classified according to the following two quality grades Standard and High Quality The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots etc High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems and safety equipment etc Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury artificial life support devices or systems surgical implantations etc or may cause serious property damages nuclear reactor control systems military equipment etc You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application for which it is not intended Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any
117. resws tresw Figure 2 10 Reset input timing 01050262 00080 Rev 0 80 Oct 12 2015 2tENESAS Page 43 of 111 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics 2 3 4 Wakeup and Duration Table 2 16 Timing of recovery from low power modes and duration Test Item Symbol Min Typ Max Unit conditions Recovery time Crystal System clock source is main tsgymc 2 8 9 ms Figure 2 11 from Software resonator clock oscillator 2 The division Standby mode connected 9 ratio of all System clock source is PLL tspypc 3 2 ms to main oscillators with main clock oscillator 3 clock are 1 oscillator External System clock source is main tspyex 2809 ys clock input clock oscillator 4 fo main System clock source is PLL tsBvPE 700 9 us clock 45 with main clock oscillator oscillator System clock source is sub clock tspysc 1 379 ms oscillator 8 System clock source is LOCO 8 tsByLo 1 4 9 ms System clock source is HOCO clock tsByHo 300 us oscillator 6 System clock source is MOCO clock tsBYMO 300 9 us oscillator Recovery time from Deep Software Standby mode tpspv 1 0 ms Figure 2 12 Wait time after cancellation of Deep Software Standby mode tpsgvwr 31 32 Recovery time High spe
118. rts P205 P206 P407 to P415 Low drive 1 lou 2 0 mA P602 P708 to P713 P813 PA12 to PA15 01 total 24 pins loL 2 0 mA Middle drive 2 4 0 lo 4 0 High drive 3 20 E 20 Other output pin 4 Low drive 1 2 0 2 0 Middle drive 2 4 0 lo 4 0 High drive 3 16 16 Permissible output current Ports P008 to P011 P212 loH 4 0 Max value per pin lor 4 0 mA Ports P014 P015 P213 P400 8 0 401 511 512 lo 8 0 402 404 Low 1 4 0 mA D 4 0 mA Middle drive 2 8 0 8 0 mA Ports P205 P206 P407 to P415 Low drive 4 0 602 708 713 813 12 to PA15 PBO1 loL d 5 40 mA total 24 pins Middle drive 2 lou 8 0 mA E 8 0 mA High drive 3 40 2 40 Other output pin 4 Low 1 loH 4 0 lo 4 0 Middle drive 2 8 0 8 0 mA High drive 3 32 mA 32 mA RO1DS0262EU0080 Rev 0 80 tENESAS Page 34 of 111 Oct 12 2015 Under development Preliminary document S7 Series Specifications in this document are tentative and subject to change 2 Electrical Characteristics Table 2 5 max value total pins
119. s 20 ns TDI hold time 20 ns TDO data delay trpop 40 ns Boundary scan circuit startup time 1 TgssrUP treswpe Figure 2 99 Note 1 Boundary scan does not function until the power on reset becomes negative trokcyc Figure 2 97 Boundary scan TCK timing RO1DS0262EU0080 0 80 2tENESAS Page 104 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics Figure 2 98 Boundary scan input output timing i tesstup Boundary scan treswp execute Figure 2 99 Boundary scan circuit start up timing RO1DS0262EU0080 0 80 2tENESAS Page 105 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series Appendix 1 Package Dimensions Appendix 1 Package Dimensions Information on the latest version of the package dimensions or mountings is displayed in Packages on the Renesas Electronics Corporation website JE
120. s Figure 2 5 crystal 1 LOCO clock oscillation frequency fLoco 29 4912 32 768 36 0448 kHz LOCO clock oscillation stabilization wait time tLocowT 60 4 us Figure 2 6 ILOCO clock oscillation frequency 13 5 15 16 5 kHz MOCO clock oscillation frequency Fuoco 7 2 8 8 8 MHz MOCO clock oscillation stabilization wait time 15 0 us HOCO clock oscillator oscillation frequency fuoco16 15 61 16 16 39 MHz 20 lt lt 105 C fuoco18 17 56 18 18 44 fuoco2o 19 52 20 20 48 oco 15 52 16 16 48 40 lt Ta lt 20 C fHoco18 17 46 18 18 54 fHocozo 19 40 20 20 60 HOCO clock oscillation stabilization wait time 2 tHocowT 64 7 us PLL clock frequency 120 240 2 PLL clock oscillation stabilization wait time 174 9 us Figure 2 7 Note 1 When setting up the main clock ask the oscillator manufacturer for an oscillation evaluation and use the results as the recommended oscillation stabilization time Set the MOSCWTCR register to a value equal to or greater than the recommended stabilization time After changing the setting of the MOSCCR MOSTP bit so that the main clock oscillator operates read the OSCSF MOSCSF flag to confirm that it is 1 then start using the main clock Note 2 This is the time from release from reset state until the oscillation frequency of the HOCO fHOCO reaches the range for guaranteed operation 01050262 00080 Rev 0 80 Oct 12 2015 2tENESAS Page 40
121. s is used as the analog power supply for the respective modules and temperature sensor Connect this pin to VCC if the 12 bit A D converter unit 1 D A converter or temperature sensor is not in use VREFL Input Reference ground pin for the 12 bit A D converter and D A converter This is used as the analog ground for the respective modules and temperature sensor Set this pin to the same potential as the VSS pin ADC12 000 to ANOO6 Input Input pins for the analog signals to be processed by the A D converter ANO016 to ANO21 AN100 to AN106 Input AN116 to AN120 ADTRGO Input Input pins for the external trigger signals that start the A D conversion ADTRG1 Input 55000 Input Differential input pins PGAVSS100 DAC12 DAO DA1 Output Output pins for the analog signals to be processed by the D A converter ACMPHS VCOUT Output Comparator output pin IVREFO 016 Input Reference voltage input pin for Comparator IVREF1 AN116 IVREF3 DAO IVCMPO 017 Input Analog voltage input pins for Comparator IVCMP1 DA1 2 ANOOO0 to 002 AN100 to AN102 CTSU TSO to TS17 Input Capacitive touch detection pins touch pins TSCAP Secondary power supply for the touch driver KINT KROO to KRO7 Input A key interrupt KINT can be generated by inputting a falling edge to the key interrupt input pins ports P000 to P007 Input General purpose input pin P008 to P011 P014 I O General purpose input output pins P
122. se specification values apply when there is no access to the external bus during A D conversion If access proceeds during A D conversion values might not fall within the indicated ranges Note 1 The conversion time is the sum of the sampling time and the comparison time The number of sampling states is indicated for the test conditions Note 2 Values in parentheses indicate the sampling time 01050262 00080 Rev 0 80 Oct 12 2015 2tENESAS Page 93 of 111 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics Table 2 42 AID internal reference voltage characteristics Item Test conditions internal reference voltage Integral nonlinearity error INL converter output code characteristic Ideal A D conversion characteristic Di gene Up Actual A D conversion m ddl ifferential nonlinearity error DNL 1 LSB width for ideal A D conversion characteristic 1 LSB width for ideal A D conversion characteristic Absolute accuracy Analog input voltage Figure 2 88 Absolute accuracy VREFHO full scale Illustration of 12 bit A D converter characteristic terms Absolute accuracy is the difference between output code based on the theoretical A D conversion characteristics and the actual A D conversion result When measuring absolute accuracy the voltage at the midpoint of the wi
123. so be used as a general purpose timer See section 23 General PWM Timer GPT in User s Manual Asynchronous General Purpose The Asynchronous General Purpose Timer AGT is a 16 bit timer that can be used for pulse Timer AGT output external pulse width or period measurement and counting external events This 16 bit timer consists of a reload register and a down counter The reload register and the down counter are allocated to the same address and can be accessed with the AGT register See section 25 Asynchronous General Purpose Timer AGT in User s Manual RO1DS0262EU0080 0 80 134 NE SAS Page 4 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 1 Overview Table 1 8 Timers Feature Functional description Realtime Clock RTC The Realtime Clock RTC has two counting modes calendar count mode and binary count mode that are used by switching the register settings For calendar count mode the RTC has a 100 year calendar from 2000 to 2099 and automatically adjusts dates for leap years For binary count mode the RTC counts seconds and retains the information as a serial value Binary count mode can be used for calendars other than the Gregorian Western calendar See section 26 Realtime Clock RTC in User s Manual Table 1 9 Communication interfaces Feature Functional description Serial Communications Interface The
124. specific addresses This function is useful in applications that require CRC code to be generated automatically in certain events such as monitoring writes to the serial transmit buffer and reads from the serial receive buffer See section 40 Cyclic Redundancy Check CRC Calculator in User s Manual Data Operation Circuit DOC Sampling Rate Converter SRC Table 1 14 Security Feature Secure Crypto Engine 7 SCE7 The Data Operation Circuit DOC is used to compare add and subtract 16 bit data See section 51 Data Operation Circuit DOC in User s Manual The Sampling Rate Converter SRC is used to convert the sampling rate of data produced by various audio decoders such as the WMA MP3 and AAC Both 16 bit stereo and monaural data are supported The sampling rate of the input signal can be one of the following in KHz 8 e 11 025 12 e 16 e 22 05 24 e 32 44 1 48 2 sampling rate of the output signal can be one of the following in KHz 8 16 e 32 44 1 48 2 There independent FIFOs for the input and output In a typical application controller can be used to transfer PCM audio data from SRAM for example to the SRC Sample converted audio data from the SRC can then be transferred using the DMA controller to the SSI from where it can be transmitted to an external audio codec See section 42 Sampling Rate Converter SRC in User s Manual Functio
125. stics USBHS DP and USBHS DM pin characteristics Conditions USBHS RREF 2 2 196 USBMCLK 20 24 MHz Item Symbol Min Max Unit Test conditions Battery Charging D sink current IpP siNK 25 175 Specification D sink current 25 175 UA DCD source current sRC 7 13 Data detection voltage VpAT REF 0 25 0 4 V D source voltage VpP sRC 0 5 0 7 V Output current 250 pA D source voltage sRC 0 5 0 7 V Output current 250 uA 2 4 2 USBFS Timing Table 2 38 USBFS low speed characteristics for host only USB DP and USB DM pin characteristics Conditions VCC AVCCO USB VBATT 3 0 to 3 6V 2 7 lt VREFHO VREFH lt AVCCO VCC_USBHS AVCC USBHS 3 0 to 3 6 V USBA RREF 2 2 1 USBMCLK 20 24 MHz UCLK 48 MHz Item Symbol Min Typ Max Unit Test conditions Input Input high level voltage 2 0 V characteristics Input low level voltage Vi 0 8 V Differential input sensitivity Vpi 0 2 V USB DP USB DM Differential common mode VcM 0 8 2 5 V range Output Output high level voltage 2 8 3 6 V 200 pA characteristics tout low level voltage Var 0 0 0 3 V lg22mA Cross over voltage Vers 1 3 2 0 V Figure 2 84 Rise time tLe 75 300 ns Fall time 75 300 ns Rise fall time ratio ttr 80 125 tir tle Pull up and pull USB_DP and USB_DM pull Rog 14 25 24 80 kQ d
126. t 1 MHz Table 2 11 Operation frequency value in low speed mode Item Symbol Min Typ Max Unit Operation frequency System clock ICLK 2 f 1 MHz Peripheral module clock PCLKA 2 1 Peripheral module clock PCLKB 1 Peripheral module clock PCLKC 2 3 3 1 Peripheral module clock PCLKD 2 1 FlashlF clock FCLK 1 2 1 External bus clock BCLK 1 EBCLK pin output 1 Note 1 Programming or erasing the flash memory is disabled in low speed mode Note 2 See section 9 Clock Generation Circuit in User s Manual for the relationship of frequencies between the ICLK PCLKA PCLKB PCLKC PCLKD FCLK and BCLK Note 3 When the 12 bit A D converter is used the frequency must be set to at least 1 MHz Table 2 12 Operation frequency value in Subosc speed mode Item Symbol Min Typ Max Unit Operation frequency System clock ICLK 2 f 29 4 36 1 kHz Peripheral module clock PCLKA 2 36 1 Peripheral module clock PCLKB 36 1 Peripheral module clock PCLKC 2 3 36 1 Peripheral module clock PCLKD 2 36 1 Flash IF clock FCLK 1 2 29 4 36 1 External bus clock BCLK 2 36 1 EBCLK pin output 36 1 R01DS0262bEU0080 Rev 0 80 ESAS Page 39 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subje
127. t Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics 2 2 5 Operating and Standby Current Table 2 7 Operating and standby current LDO mode DCDC mode Item Symbol Min Typ Min Typ Max Unit Test conditions Supply Maximum 2 loc 330 140 ICLK 240 MHz current 1 34 120 2 CoreMark 45 24 60 MHz Normal All peripheral clocks 75 38 PCLKC 60 MHz 3 mode 3 enabled code executing PCLKD 120 MHz E from flash 60 MHz o 120 MHz 9 peripheral clocks 32 18 FH disabled code executing from flash 2 T Sleep mode 4 25 150 15 75 Increase Data flash P E 7 7 during BGO operation Code flash P E 10 10 Low speed mode 4 4 4 3 ICLK 1 MHz Subosc speed mode 4 3 2 32 768 kHz Software Standby mode 24 110 1 2 55 Power supplied to standby RAM and USB 37 255 37 255 resume detecting unit Power not Power on reset circuit low 25 50 25 50 supplied to power consumption function RAM and disabled USB d dial Power on reset circuit low 16 35
128. ta output delay top 4 ns Data output hold time tou 3 3 ns Successive transmission delay trp 1 16 ns Note 1 PCLKA cycle Note 2 Nis set 0 or 1 by SFMSLD Note 3 N is set 0 or 1 by SFMSHD QSPCLK output Figure 2 51 QSPI clock timing RO1DS0262EU0080 Rev 0 80 ESAS Page 73 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics QSPCLK output LSB IN MSB OUT LSB OUT Figure 2 52 Transmit receive timing RO1DS0262EU0080 Rev 0 80 ESAS Page 74 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change 2 Electrical Characteristics S7 Series 2 3 13 IIC Timing Table 2 27 IC timing 1 Conditions Middle drive output is selected with the port drive capability bit in the PmnPFS register for the following pins SDAO B SCLO B SDA1 A SCL1 A SDA1 B SCL1 B The following pins do not required setting SCLO A SDAO A SCL2 SDA2 Test Item Symbol Min 1 2 Max Unit conditions SCL input cycle time tse 6 12 ticcye 1300 ns Figure 2 53 Standard mode SCL input high pulse width 3 6 300 ns ICFER FMPE 0 SCL in
129. teristics Conditions USBHS RREF 2 2 196 USBMCLK 20 24 MHz UCLK 48 MHz Item Symbol Min Typ Max Unit Test conditions Input Input high level voltage 2 0 V characteristics Input low level voltage Vu 0 8 V Differential input sensitivity 0 2 V USBHS_DP USBHS_DM Differential common mode Vom 0 8 2 5 V range Output Output high level voltage 2 8 3 6 V 200 pA characteristics stout low level voltage Voi 0 0 0 3 2 Cross over voltage Vers 1 3 2 0 V Figure 2 78 Rise time tLe 4 20 ns Fall time 4 20 ns Rise fall time ratio tir 90 111 11 ter Output resistance Zpnv 40 5 49 5 Q Rs Not used PHYSET REPSEL 1 0 01b and PHYSET HSEB 0 DC USBHS DM pull up resistor Ry 0 900 1 575 During idle state device 1 425 3 090 During transmission and reception USBHS DP USBHS DM 14 25 24 80 kQ pull down resistor host USBHS_DP USBHS_DM Figure 2 78 USBHS_DP and USBHS_DM output timing in full speed mode Observation USBHS_DP J pon 50 pF 7777 USBHS DM 7777 Figure 2 79 Test circuit in full speed mode 01050262 00080 Rev 0 80 ESAS Page 88 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subj
130. the MCU The SSI supports an audio clock frequency of up to 50 MHz and can be operated as a slave or master receiver transmitter transceiver to suit various applications The SSI includes 8 stage FIFO buffers in the receiver and transmitter and supports interrupts and DMA driven data reception and transmission See section 41 Serial Sound Interface SSI in User s Manual Quad Serial Peripheral Interface The QSPI is a memory controller for connecting a serial ROM nonvolatile memory such as a QSPI serial flash memory serial EEPROM or serial FeRAM that has an SPI compatible interface See section 39 Quad Serial Peripheral Interface QSPI in User s Manual CAN Module CAN The Controller Area Network CAN module provides functionality to receive and transmit data using a message based protocol between multiple slaves and masters in electromagnetically noisy applications The CAN module complies with the ISO 11898 1 CAN 2 0A CAN 2 0B standard and supports up to 32 mailboxes which can be configured for transmission or reception in normal mailbox and FIFO modes Both standard 11 bit and extended 29 bit messaging formats are supported See section 37 Controller Area Network CAN Module in User s Manual USB 2 0 Full Speed Module USBFS This MCU incorporates a USB 2 0 Full Speed module USBFS The USBFS is a USB controller that is equipped to operate as a host controller or device controller The module supports full speed and low
131. tive and subject to change S7 Series 2 Electrical Characteristics WR WR WR WR X e X D co A1 5 to 0 column address c 1 ii ii dL com D15 to DO Note Address pins are for output of the precharge setting command Precharge sel for the SDRAM Figure 2 23 SDRAM multiple write timing 01050262 00080 Rev 0 80 ESAS Page 56 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics SDRAM command SDCLK A15 to D15 to DO Note Address pins are for output of the precharge setting command Precharge sel for the SDRAM Figure 2 24 SDRAM multiple read line stride timing RO1DS0262EU0080 Rev 0 80 ESAS Page 57 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics SDRAM command SDCLK A15 to High Hi Z D15 to DO Note Address pins are for output of the precharge setting command Precharge sel for the SDRAM Figure 2 25 SDRAM mode register set timing 01050262 00080 Rev 0 80 ESAS Page 58 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are te
132. tput tsu SMOSIn MSB IN input n 0 to 9 Figure 2 41 simple SPI mode timing slave CKPH 1 01050262 00080 Rev 0 80 ESAS Page 66 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics SSn input SCKn CKPOL 1 input 5 CKPOL 0 to SMISOn LSB OUT Last data MSB OUT K output MSB OUT SMOSIn input n 2 0 to 9 Figure 2 42 simple SPI mode timing slave 0 Table 2 24 SCI timing 3 Conditions For the SSCL1 A pins low drive output is selected with the port drive capability bit in the PmnPFS register For other pins middle drive output is selected with the port drive capability bit in the PmnPFS register Simple SSDA input rise time tsr 1000 ns Figure 2 43 Standard mode SSDA input fall time sr 300 ns SSDA input spike pulse removal time tsp 0 4 X ns Data input setup time tspas 250 ns Data input hold time 0 ns SSCL SSDA capacitive load C 400 pF Simple IIC SSCL SSDA input rise time tsr 300 ns Figure 2 43 Fastimeds SSCL SSDA input fall time sr a 300 ns SSCL SSDA input spike pulse removal tsp 0 4 X tiiccyc ns time Data input setup time tspas 100 ns Data input hold time tspaH 0 ns SSCL SSDA capacitive load 40
133. ture 3 4 40 to 105 Storage temperature Tstg 55 to 125 Caution Permanent damage to the MCU may result if absolute maximum ratings are exceeded Note 1 Ports P205 P206 P400 P401 P407 to P415 P511 P512 P708 to P713 and 01 are 5V tolerant Note 2 Connect AVCCO and USB to VCC Note 3 See section 2 2 1 Tj Ta Definition Note 4 Contact Renesas Electronics sales office for information on derating operation when T4 85 to 105 Derating is the systematic reduction of load for improved reliability Table 2 2 Recommended operating conditions Item Symbol Value Min Typ Max Unit Power supply voltages VCC When USB SDRAM is not used 2 7 3 6 V When USB SDRAM is used 3 0 3 6 V VSS 0 V USB power supply voltages VCC USB VCC V VCC USBHS VSS USB 0 V AVSS USBHS PVSS USBHS VSS1 USBHS VSS2 USBHS Switching regulator power VCC DCDC When switching regulator is VCC V supply voltage used When switching regulator is not 0 V used VBATT power supply voltage VBATT 2 0 3 6 V Analog power supply voltages AVCCO VCC V AVSSO 0 V R01DS0262bEU0080 Rev 0 80 ESAS Page 32 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change S7 Series 2 Electrical Characteristics 2 2 DC Characteristics 2 2 1 Tj Ta Definition Table 2
134. ument are tentative and subject to change S7 Series 2 Electrical Characteristics 2 6 DAC12 Characteristics Table 2 43 D A conversion characteristics Item Min Typ Max Unit Test conditions Resolution 12 Bit Without output amplifier Absolute accuracy 24 LSB Resistive load 2 MO DNL 1 0 2 0 LSB Resistive load 2 MQ Output impedance 7 5 kQ Conversion time 3 0 us Capacitive load 20 pF With output amplifier INL 2 0 4 0 LSB DNL 1 0 2 0 LSB Conversion time 4 0 us Resistive load 5 kQ Capacitive load 50 pF Output voltage range 0 2 VREFH 0 2 V 2 7 TSN Characteristics Table 2 44 TSN characteristics Item Symbol Min Typ Max Unit Test conditions Relative accuracy 1 0 Temperature slope 4 1 mV C Output voltage at 25 1 24 V Temperature sensor start time tsTaRT 30 Hus Sampling time 4 15 us 2 8 OSC Stop Detect Characteristics Table 2 45 Oscillation stop detection circuit characteristics Test conditions Figure 2 89 Item Detection time Main clock OSTDSR OSTDF MOCO clock ICLK Figure 2 89 Oscillation stop detection timing RO1DS0262EU0080 Rev 0 80 2tENESAS Page 95 of 111 Oct 12 2015 Under development Preliminary document Specifications in this document are tentative and subject to change
135. vel at which resetting is specified 3 Input of signal during power off state Do not input signals or an I O pull up power supply while the device is powered off The current injection that results from input of such a signal or I O pull up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements Follow the guideline for input signal during power off state as described in your product documentation 4 Handling of unused pins Handle unused pins in accordance with the directions given under handling of unused pins in the manual The input pins of CMOS products are generally in the high impedance state In operation with an unused pin in the open circuit state extra electromagnetic noise is induced in the vicinity of the LSI an associated shoot through current flows internally and malfunctions occur due to the false recognition of the pin state as an input signal become possible 5 Clock signals After applying a reset only release the reset line after the operating clock signal becomes stable When switching the clock signal during program execution wait until the target clock signal is stabilized When the clock signal is generated with an external resonator or from an external oscillator during a reset ensure that the reset line is only released after full stabilization of the clock signal Additionally when switching to a clock signal produced with an extern
136. velopment Preliminary document Specifications in this document are tentative and subject to change S7 Series 1 Overview Pin number Extbus Timers Communication interfaces Analog HMI 59 28 5 o 8 22 2 5 g e R 51 99 z ERER 5 A N lt Tj o allio I o N v 5 N n S x lt I rir a gt 8 a 2258585 658 5 E 892555206 2 25 3 amp 888 2 3 2 a 2 2 Q i lt 6 Go 585609209 9 6 oss 5 ajaa E o M7 P508 SCK5 02 B 0 P6 P509 TXD5 AN12 B 0 SMOS I5 B SSDA 5B N7 P510 RXD5 ANO2 B 1 SMIS O5 B SSCL 5B R6 R6 148 4 120 81 2 P7 M7 149 N5 121 82 VCC R7 N7 150 5 122 83 VSS M8 P7 151 M6 123 84 015 00 DA1 IRQ13 6 IVCM 10 P1 6 M9 R7 152 N6 124 85 P014 00 DA0 5 IVREF AN10 3 5 N8 P8 153 M7 125 86 VREF L R8 R8 154 N7 126 87 VREF H P8 N8 155 17 127 88 0 N9 N9 156 L8 128 89 AVSS 0 9 9 157 M8 129 90 VREF 10 R9 158 130 97 VREF HO N10 P011 AN10 IRQ15 4 DS M10 M8 159 P010 AN10 IRQ14 3 DS R10 9 160 M9 131 009 00 IRQ13 4 DS N11 P10 161 N9 132 92 P008 00 IRQ12 3 DS L9 M
137. w The 5762 MCU comprises multiple series of software and pin compatible ARM based 32 bit MCUS that share common set of Renesas peripherals to facilitate design scalability and efficient platform based product development This MCU provides a high performance ARM Cortex M4 core running up to 240 MHz with the following features e Up to 4 MB code flash memory 640 KB SRAM Graphics LCD Controller GLCDC e 2D Drawing Engine DRW Capacitive Touch Sensing Unit CTSU e Ethernet MAC Controller ETHERC with IEEE 1588 USBFS USBHS SD MMC host interface Quad Serial Peripheral Interface QSPI e Security and safety features Analog peripherals 1 1 Function Outline Table 1 1 ARM core Feature Functional description ARM Cortex M4 e Maximum operating frequency up to 240 MHz ARM Cortex M4 core Revision 0 1 01 10 ARMv7E M architecture profile Single Precision Floating Point Unit compliant with the ANSI IEEE Std 754 2008 e ARM Memory Protection Unit MPU ARMv7 Protected Memory System Architecture 8 protect regions SysTick timer Driven by LOCO clock Table 1 2 Memory Feature Functional description Code flash memory Maximum 4 MB of code flash memory See section 54 Flash Memory in User s Manual Data flash memory 64 KB of data flash memory See section 54 Flash Memory in User s Manual Memory Mirror Function MMF The MMF can be configured to mirror the desired application i
138. wer Mode This MCU has several functions for reducing power consumption such as setting clock dividers controlling EBCLK output controlling SDCLK output stopping modules selecting power control mode in normal operation and transitioning to low power modes See section 11 Low Power Mode in User s Manual Battery Backup Function This MCU has a battery backup function that can be partly powered by a battery The battery powered area includes RTC SOSC backup memory switch between VCC and VBATT See section 12 Battery Backup Function in User s Manual Register Write Protection The Register Write Protection function protects important registers from being overwritten due to software errors See section 13 Register Write Protection in User s Manual Memory Protection Unit MPU This MCU incorporates two memory protection units and provides a CPU stack pointer monitor function See section 16 Memory Protection Unit MPU in User s Manual Watchdog Timer WDT The Watchdog Timer WDT is a 14 bit down counter It can be used to reset the MCU when the counter underflows because the system has run out of control and is unable to refresh the WDT In addition a non maskable interrupt or interrupt can be generated by an underflow The refresh permitted period can be set to refresh the counter and used as the condition to detect when the system runs out of control See section 27 Watchdog Timer WDT in User s Ma

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