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FORCE GATE ARRAY FGA

1. INTERRUPT CONTROL REGISTER STATUS REGISTER CHANNEL Mnemonic Address Mnemonic Address Mailbox 0 ICRMBOXO SFFDO0000 Mailbox 1 ICRMBOX1 SFFD00004 Mailbox 2 ICRMBOX2 SFFD00008 Mailbox 3 ICRMBOX3 SFFDOOOOC Mailbox 4 ICRMBOX4 SFFD00010 Mailbox 5 ICRMBOX5 SFFD00014 Mailbox 6 ICRMBOX6 FFD00018 5 Mailbox 7 ICRMBOX7 SFFDOOO1C Timer CRTIMO SFFD00220 STIMO SFFDO04A0 FMB1 Refused CRFMBIREF SFFD00244 SFMB1REF SFFDOO4BC FMBO Refused ICRFMBOREF SFFD00240 ISFMBOREF SFFDO004B8 FMB1 Message CRFMB1MES SFFDOO24C ISFMB1MES SFFDO04E4 FMBO Message ICRFMBOMES SFFD00248 TSFMBOMES SFFDO04E0 ABORT ICRABORT SFFD00280 ISABORT SFFDO04C8 ACFAIL ICRACFAIL SFFD00284 ISACFAIL SFFDOO4CC SYSFAIL ICRSYSFAIL SFFD00288 ISSYSFAIL SFFD004D0 DMA Error ICRDMAERR SFFD00234 ISDMAERR SFFDO004B4 DMA Normal ICRDMANORM SFFD00230 ISDMANORM SFFDO04BO0 PARITY Error ICRPARITY SFFD00258 SPARITY SFFDO04CO0 LOCALO ICRLOCALO SFFDO028C ISLOCALO SFFD00480 LOCAL1 ICRLOCAL1 SFFD00290 ISLOCAL1 SFFD00484 LOCAL2 ICRLOCAL2 SFFD00294 ISLOCAL2 SFFD00488 LOCAL3 TCRLOCAL3 SFFD00298 ISLOCAL3 SFFDO048C LOCAL4 ICRLOCAL4 SFFD0029C ISLOCAL4 SFFD00490 LOCAL5 ICRLOCAL5 SFFDO02A0 ISLOCAL5 SFFD00494 LOCAL6 ICRLOCAL6 SFFDOO02A4 ISLOCAL6 SFFD00498 LOCAL7 ICRLOCAL7 SFFDO02A8 ISLOCAL7 SFFDOO049C VIRQ7 ICRVME7 SFFD0021C VIROQ6 ICRVME 6 SF
2. 3 DMA REGISTERS 3 1 DMA Controller Register Organization The following outlines the organization of the DMA controller registers 31 24 ICRDMANORM Interrupt Control Normal Termination ICRDMAERR Interrupt Control Error Termination DMASRCATT Source Attribute Register DMADSTATT Destination Attribute Register DMAGENERAL General Control Register ISDMANORM Interrupt Status Register Normal Termination ISDMAERR Interrupt Status Register Error Termination DMARUNCTL Run Control Register DMAMODE Mode Status Register 3l 0 DMASRCADR Source Address DMADSTADR Destination Address DMATRFECNT Transfer Count THE 32 BIT DMA CONTROLLER 3 2 DMA Controller Register Address Assignment The following chart outlines the address assignment of the DMA controller registers DMA Control Register Mnemonic Address R W Default Interrupt Control Norm ICRDMANOR SFFD00230 R W S00 Interrupt Control Error ICRDMAERR SFFD00234 R W S00 Source Attribute DMASRCATT SFFD00320 R W 00 Destination Attribute DMADSTATT SFFD00324 R W S00 General Control DMAGENERAL SFFD00328 R W 00 Interrupt Status Normal ISDMANORM SFFDOO4BO R W 80 Interrupt Status Error ISDMAERR SFFDO04B4 R W 80 Run Control DMARUNCTL SFFDO04C4 R W 00
3. OMWAAIANDDADADADUWIUNUNOBWWDN DN THE CPU AND VME INTERFACE TABLE OF CONTENTS cont d VMEbus ARB TRATION 2 Oued 24 962 Automatic Re ALTER On eh a Internal External Arbiter select Dig Da 2 vocal ees CTE VMEbus REQ 2 6 1 2 6 2 UEST a SS VMEbus request on power Fa detection FAIR request option VMEbus REL 2 el 221 2 Coe eee 2 7 4 Ze bad Oi Oi 2 kek Register CTLE EASE OSes Map oe oS Bie A ee Release On Request ROR 2 7 elsd Register CTL7 Release on Bus Clear RBCLR Dep To Big Register CTL7 Release Voluntary RV Release on ACFAIL RACFAIL Release Every Cycle REC 2A ERS Register CTL12 VME SLAVE INTERFACE Sak 3 2 FEATURES VME Access B22 wil Bie we 352453 3 2 4 Shared Mem EA VME Access Se Aad 3 4 2 to ERE ogai MAI N MEMORY MAIN memory from the VMEbus side VME Page Decoding AS N Register VMEPAGE VME Interval Decoding T ich R EA A Registers for Bottom and Top page selection Be eh mk Enab Le Address Modifier Decoding 3 2 4 1 Register ENAMCODE ory Structure Support RMW Cycles from VME to the MAIN Memory Guy Register CTL115 to FGA 002 functions VME page selection a NE 3 4 1 Register MYVMEPAGE Address Modifier Code selection 3645 24 11 Register CTL5
4. BITs 76543210 Byte XXXXXXXX Reset Value 00 BIT 7 4 DSTASSACK 7 4 AUXACK pin is asserted after x cycles of 32mhz clock SO 1 clockcycle Sl 2 clockcycles 2 3 clockcycles 3 4 clockcycles 4 5 clockcycles 5 6 clockcycles 6 7 clockcycles 7 8 clockcycles 8 9 clockcycles 9 10 clockcycles SA 11 clockcycles SB 12 clockcycles SC on AUXREQ pin asserted SD on AUXREQ pin asserted AUXRDY pin must be released SE after data has been read into the fifo SF on AUXRDY pin asserted BIT 3 0 DSTRDY 3 0 READY after SO 1 clockcycle Sl 2 clockcycles 2 3 clockcycles 3 4 clockcycles S4 5 clockcycles 5 6 clockcycles 6 7 clockcycles 7 8 clockcycles 8 9 clockcycles 9 10 clockcycles SA 11 clockcycles SB 12 clockcycles SC AUXREQ pin asserted SD AUXREQ pin asserted AUXRDY pin must be released SE data has been read into the fifo SF AUXRDY pin asserted AUXSRCTERM REGISTER FORMAT BITs 76543210 Byte XXXXXXXX Reset Value 00 BIT 7 4 BIT 3 0 SRCRELACK 7 4 SRCNEWCYC 3 0 SFFD00348 AUXACK pin is released x cycles of 32mhz clock after READY es es es es es es es es es es es pin is asserted ter data has been read clock e es es
5. 6 FMB REGISTERS 6 1 FMB Register Organization The following outlines the organization of the FMB registers 31 24 FMBCTL FMB Control Register FMBAREA FMB Area Register ICRFMBOMES Interrupt Control FMBO Message ICRFMBOREF Interrupt Control FBMO Refused ICRFMBIMES Interrupt Control FMB1 Message ICRFMB1REF Interrupt Control FMB1 Refused ISFMBOMES Interrupt Status FMBO Message ISFMBOREF Interrupt Status FMBO Refused ISFMB1MES Interrupt Status FMB1 Message ISFMB1REF Interrupt Status FMB1 Refused 31 0 FMBCHO Channel Message Readout Register FMBCH1 Channel Message Readout Register FORCE MESSAGE BROADCAST FMB 6 2 FMB Register Address Assignment The following chart details the address assignment of the FMB register FMB Register Mnemonic Address R W Default FMB Control Register FMBCTL SFFD00338 R W 00 FMB Area Register FMBAREA SFFD0033C R W 00 Ints Ge FMBO Message ICRFMBOMES SFFD00248 R W 00 Int Ct1l FMBO Refused ICRFMBOREF SFFD00240 R W 00 Int ctl FMB1 Message ICRFMB1MES SFFDO024C R W 00 Int ctl FMB1 Refused ICRFMB1REF SFFD00244 R W S00 Int Status FMBO Message ISFMBOMES SFFDO04E0 R W 80 Int Status FMBO Refu
6. Autoclear IRQ Enable IRQ Level Extended interrupt control register backs If this bit is cleared an interrupt acknowledge cycle that answers the interrupt will clear the edge triggered interrupt automatically Autoclear option is enabled Autoclear option is disabled The bit enables or disables the interrupt chan the interrupt nel If the bit is 0 G request is not recognized by This bit field the interrupt channel Interrupt channel is enabled Interrupt channel is disabled request level defines the interrupt If no interrupt level is selected the interrupt channel is disabled No level selected Level Level Level Level Level Level Level HYHDOBRWNE INTERRUPT MANAGEMENT 2 5 3 The which access to the status register bit returns interrupt pending A logical one is read when no pending Interrupt Status Register Interrupt Status Registers contain a single bit position reflects whether or not an interrupt is pending A zero if there is an read interrupt is The status bit is readable at bit 7 of the interrupt status register The status register is always readable and does not effect devic operation Format of the Interrupt Status Register
7. 7 6 5 4 3 2 1 0 CNTSRC CNTDST reserved bits DMAENA 7 CNTSRC This bit selects the count mode for the source address register 1 The source address register does not count 0 The source address register counts up 6 CNTDST This bit selects the count mode for the destination address register 1 The destination address register does not count 0 The destination address register counts up Back Reserved This bitfield is reserved for future use The bits have to be written with WOM 0 DMAENA This bit is a general enable bit for the DMA Controller function 1 The DMA Controller is enabled 0 The DMA Controller is under reset THE 32 BIT DMA CONTROLLER 3 3 4 The operating state and to function the with start has completed the task Run Control Register DMARUNCTL top the DMARUNCTL Register is used for the evaluation of start and st The OPSTATE bit is read onl DMA Controller is running or idle any data has no effect DMA operation and to stop the the DMA Controller ly and indicates whether Writing the OPSTATE bit The START STOP bit is DMA controller before it The START STOP bit always returns zero DMA used to when the register is read 7 6 5 4 3 2 0 START OPSTATE
8. status register location SFAILINPIN bit 7 4 1 1 Register SFAILINPIN Register Mnemonic Address R W Default Sysfail Input Status SFAILINPIN SFFDOO4DC R W 00 Format of SFAILINPIN 7 6 5 4 2 1 0 SFPIN STATE 7 SFPINSTATE The bit reflects the level of the SFAILI input 1 input is high 1 O input is low 0 MISCELLANEOUS 4 2 SYSFAIL Output The gate array supplies the SFAILO output for th the VMEbus The status and allows a VME master in a multiprocessor syst which board t be perf correct address modifier code Please refer to t signal SYSFAIL e generation of of the SFAILO signal can be read from the VME side em to determine drove the SYSFAIL signal The access from VME has ormed in the short I O decoding range with the and CPU INT for details The SFAILO signal status is displayed when th is accessed gate array the gate ar The generat Data bit 6 ret he section VME ERFACE chapter VME access to FGA 002 functions on the decoding selection SXXFD The status is supplied by the DVME and appears on D06 of the VMEbus address location 6 signal of the ray is high turns a logical 0 if the sysfail signal is driven low by the gate array and a logical 1 if the sysfail output of ion of the SYSFAIL signal is inhibited if the LOCS
9. I No VME access 0 Parity error during VME access 6 DMA This bit indicates if the parity error occurred during a DMA access to the shared main memory 1 No DMA access 0 Parity error during DMA access 5 RMC This bit indicates if the parity error occurred during a Read Modify Write operation 1 No RMC operation 0 Parity error during a RMC operation 4 2 FC 2 0 This bitfield reflects the state of the function code signals FC2 FCO according to the address space encoding for 68020 30 processors 1 0 S Z 1 0 This bitfield reflects the state of the transfer size signals SZ1 and SZO0O 00 4 byte transfer size O1 1 byte transfer size 10 2 byte transfer size 1 3 byte transfer size 6 7 REGISTER FORMAT SHORT DESCRIPTION This page was intentionally left blank The following nota register format sho Register bits writt bits CAUTION Register bits programmed by PREFACE written in small the boot software tions are used for the register bits in the rt description ten in capital letters are user programmable letters will be The user is not allowed by any means to change these bits don t care e Read only bit Write only bit Read Write bit Readable bit Readable bit Readable bit g bit is not existent write cycle sets it to 1 write cycle causes special data transfer read cycle sets i
10. Write access causes special data transfer xx Write access clears the timer interrupt C Register Description T Timer Preload Register TIMOPRELOAD The Timer Preload Register TIMOPRELOAD contains the preset value which can be loaded into the counter circuit The defaul value of this register after reset is 00 The TIMOPRELOA register can be read at any time but must not be altered if the timer is running ct Od 7 6 5 4 3 2 1 0 Timer Counter preload value 7 0 The Timer Preload register contains the 8 bit value that is loaded into the counter if the Autopreload option in the TIMOCTL register is selected and the counter reaches the value zero Also if a write access to the TIMOCOUNT register is performed the counter is loaded with the value stored in the Timer Preload Register THE TIMER Timer Control Register TIMOCTL 2 In the Control Regis define the op Bits 3 0 sele MOCTL regist TI the Timer Control Register TI clock source of the timer can be selected ter is grouped into two major rating mode of the timer and the sysfail option ct the source clock applied ter is cleared to 00 after any reset operation MOCTL the operating mode and The Timer fields Bits 7 4 to the timer The 6 4 3 Zero Stop Auto pr
11. Register Mnemonic Address R W Default Timer Int Control Reg ICRTIMO SFFD00220 R W 00 Timer Int Status Reg STIMO FFD004A0 R W 80 A write access clears the timer interrupt The timer interrupt is controlled by the timer interrupt control register providing selection of the in level and enables disables th terrrupt request timer interrupt channel ct ct The timer interrupt is recognized if the enable bit is 1 and an in in interrup enable b interrup terrup terrupt request level greater than zero is programmed request level is sel will not request servic ected from condition to the CPU it may be set to 1 and the timer may hav be If the 0 the timer although the ntered th THE TIMER The timer interrupt is actually initiated when the counter decrements from 01 A write access to t the timer interrupt status bit in the Timer Interrupt Status Register ISTIMO The timer interrupt is pending if the the interrupt status bit is low The timer interrupt status bit is bit 7 of the interrupt status register The bit is always readable to 00 This is indicated by the interrupt he Timer Interrupt Status Register clears If the timer sysfail option is enabled this will also negate the sysfail signal The data writt
12. IRQ Level This bit field defines the interrupt request level 220 Interrupt Level 000 Interrupt disabled 001 Level 1 010 Level 2 011 Level 3 100 Level 4 101 Level 5 110 Level 6 Level 7 FORCE MESSAGE BROADCAST FMB 6 3 7 Interrupt Status Register Channel0 Message ISFMBOMES The ISFMBOMES status register contains the IRQ status bit assigned to the channelO message interrupt The status bit displays zero on a pending message interrupt request for FMB channel 0 The interrupt condition is negated when the FMB FIFO is empty ct ct 7 6 5 4 3 2 1 0 IRQ Status 7 IRQ Status The IRQ Status register bit shows if an interrupt is pending 1 is returned if no interrupt is pending 0 is returned if an interrupt is pending 6 3 8 Interrupt Status Register Channel0 Refused ISFMBOREF The ISFMBOREF status register contains the IRQ Status flag assigned to the channelO refused interrupt request A write access to the ISFMBOREF register clears the Refused interrupt 7 6 5 4 3 2 1 0 IRQ Status 7 7 IRQ Status The IRQ Status register bit shows if an interrupt is pending Writing the status register with any data clears the interrupt pa is returned if no interrupt 0 is returned
13. SFFD00280 SFFD00284 SFFD00288 SFFDO028C SFFD00290 SFFD00294 SFFD00298 SFFDO029C SFFDOO02A0 SFFDOO2A4 SFFDO02A8 ten 0 sensitive sensitive e high e low enabled disabled not used must be writ IRQ Input is edge 0 IRQ Input is level IRQ Input is activ 0 IRQ Input is activ 1 Autoclear disabled 0 Autoclear enabled Interrupt channel 0 Interrupt channel Interrupt Request Level Code 000 No level selected 001 Level 1 010 Level 2 011 Level 3 100 Level 4 101 Level 5 110 Level 6 1 Level 7 VMEPAGE REG ISTER FORMAT BITs 76543210 Byte XXXX Reset Value 00 BIT 3 0 P 31 28 SFFD00200 Decoding page for the local Main Memory from VME Side SPxxxxxxx The page is decoded when the VME Address lines A31 A28 match the value of the corresponding bits P31 P28 CTL1 REGISTER FORMAT SFFD00238 BITs 76543210 Byte XXXxX Reset Value 00 BIT 3 SUP USR 1 Access to FGA 002 registers only in Supervisor mode 0 Access to FGA 002 registers in Supervisor amp User mode BIT 2 ARBITER 1 Internal Arbiter selected 0 External Arbiter selected BIT 1 0 CSCO 00 CSCOPROC asynchronous 01 CSCOPROC O Waitstate 1 CSCOPROC 1 Waitstate CSCOPROC 2 Waitstate O ll CTL2 REGISTER FORMAT SFFD0023C
14. INTERRUPT MANAGEMENT 2 4 1 The interrup Register vectors suppl 3 CTS A two bit field of this regist the common most significant bits of the internal lied by the FGA 002 gate array used as vector bit 7 The bits 1 an Interrupt Vector Page Programming t vector page is to be programmed in d 0 of the CTL3 register ar the Control ter defines interrupt Register bit 3 is register bit 2 as vector bit 6 used to control other internal functions Therefore the register bits 1 and O must retain their value when the contents of the vector bits are altered Register Mnemonic Address R W Default Control Register 3 CTL3 FFD00250 R W 00 2 4 2 Register CTL3 7 6 5 4 3 2 T 0 VECTOR VECTOR 5 5 BIT 7 BIT 6 VSBENA OPT16 Denotes nonexistent bits 3 2 VECTORBIT 7 6 The two bit field defines th uppermost rupt veci by the responds to an internal vector number gate bits of the inter tor which is supplied array when it TACK cycles with INTERRUPT MANAGEMENT 2 5 2 5 1 The following chart displays the register m Interrupt Registers Register Map of INTERRUPT CONTROL and STATUS REGISTER control and status register ap for the interrupt
15. BITs 76543210 Byte XXXX Reset Value 00 BIT 3 PTYOUT 1 Parity output enabled O Parity output disabled BIT 2 VMERESCALL 1 VME Reset call enabled 0 VME Reset call disabled BIT 1 CSDPR 1 CSDPR Pin active in Read Write cycles 0 CSDPR Pin active only in Read cycles BIT 0 STBCTL 1 All byte strobe outputs asserted during read cycle 0 No byte strobe output asserted during read cycle CTL3 REGISTER FORMAT SFFD00250 BITs Byte Reset Value BIT 3 2 BIT 1 BIT 0 76543210 XXXX 00 VECTORBIT 7 6 Bit 7 and Bit 6 of the interrupt vector number VSBENA 1 VSB bus decoding enabled O VSB bus decoding disabled OPT16 1 VME data transfer capability is limited to 16 Bit cycle types 0 Data transfer capability is according to the VME areas CTL4 REGISTER FORMAT BITs 76543210 Byte XXXX Reset Value 00 BIT 3 1 TACKDSACK BIT 0 BOOTE LAG 001 010 100 000 H Normal BOOT IACKDSACK IACKDSACK IACKDSACK IACKDSACK 1 Wal 2 Wal 3 Wal 4 Wai SFFD00254 CS cate CS Cates CS Cates CS Cates Decoding activ Decoding activ AUXPINCTL REGISTER FORMAT SFFD00260 BITs 76543210 Byte XXXX Reset Value 00 BIT 3 AUTOREQUEST 1 AUTOREQUEST enabled Q AUTOREQUEST
16. CPU INTERFACE oil FEATURES ROP Teme ee tet nS 2 ADDRESS DECODING STRUCTURE 3 MAI N MEMORY s 8 BA tere aah Dae ee See eh ste Gas Si id Sale N ora The MAIN MEMORY Decoding Registers L 53 2 The MAIN MEMORY ENABLE Bit Le Sel el Register CTL11 peor The MAIN MEMORY SIZE s TSL Register CTL11 TS BZ Register CTL10 3 4 The MAIN MEMORY BASE ADDRESS Taranui Register MAINUU eS A2 Register MAINUM re e The MAIN MEMORY DSACK STERM eens S eee Register CTL11 ites e ee Register CTL16 4 VSB BUS SELECT a aes 1 4 1 Register CTL3 5 SECONDARY Bus D32 6 SECONDARY Bus D16 7 SYSTEM EPROM Decoding Area Se eee Gos oe fala Ded Register CTL14 whe SYSTEM EPROM DSACK Control Appelt Register CTL9 1 8 LOCAL I O AREA ae Re eat es oe LB LOCAL I O Page A FF8X XXXX 1 2Bin 2 LOCAL I O Page B FF9X XXXX TOR LOCAL I O Page C FFAX XXXX 1 8 4 LOCAL I O Page D FFBX XXXX Is a BOOT SRAM FFCX XXXX E e h 1 8 6 THE GATE ARRAY ITSELF FFDX XXXX E EBen BOOT EPROM FFEX XXXX 1 8 8 LOCAL I O Page E FFFX XXXX 1 9 ACCESS TO FGA 002 REGISTERS 1 9 1 Supervisor User Access Qe thes Register CTL1 e JIZ DSACK Control EAS Ro eee Register CTL6 1 10 BOOT DECODING FEATURES VME MASTER INTERFACE De FEATURES 2 2 Description 243 Addressing Capability eo Bo ay d PER Address Modifier Signal Generation 2 4 Data Transfer Capability A 2 4 1 D16 Master Option CE is Register CTL3 2 4 2 Support for Unaligned RMW areles PE Register CTL16
17. During the processor s IACK cycle the gate array does not intervene but merely asserts the corresponding LIACK pin as soon as possible Upon IACK the gate array responds to the CPU with vector The corresponding LIACKx be asserted and the interrupting device has to supply the interrupt vector The vector is read on the local I O bus and presented on the CPU data bus The access time to the interrupting device on the local I O bus is 1 us an external signal will on the local to supply the int bus The access the local I O bus is 500ns 2 2 3 VMEbus Vector Response VMEbus external vector response Upon IACK the gate array responds to the CPU with an external vector will be asserted and the interrupting device has terrupt vector The vector is read I O bus and presented on the CPU data time to the interrupting device on The corresponding LIACKx pin interrupts are handled by the gate array with an interrupter on data pins If a VMEbus interrupt is serviced by the processor the FGA 002 gate array awaits vector da DVME 0 1 ta delivered by the VMEbus DVME7 The vector will be read in and transmitted to the CPU data pins DCPU24 1 DCPU31 INTERRUPT MANAGEMENT INTERRUPT CHANNEL VECTOR NUMBER IROI IRQ6 TRQ5 IRQ4 IRQ3 IRQ2 TROQ1 Ssssssc external from VME exter
18. RMW Read Modify Write THE VME INTERFACE Table 2 4 Supported Data Transfer Types for D32 D16 and DO8 MASTER capability Transfer Type D31 24 D2 3 21 6 DIS 08 DO7 00 Byte Byte Byte 2 x Byte Word Byte 0 1 x x Byte 2 3 X x RMW Byte Byte 0 x Byte 1 X Byte 2 x Byte 3 x RMW Word Byte 0 1 x x Byte 2 3 x x RMW Long Byte 0 3 R x x x Unaligned Byte 0 2 X X xX Byte 1 2 Byte 1 3 X X xX x x RMW Read Modify Write THE VME INTERFACE 2 4 1 D16 Master Option As described above each VMEbus area has specific data transfer capabilities assigned to it which provide an optimum interfacing to slaves with 32 bit size However in a VMEbu 16 bit and 8 bit data bus s system with 16 bit data bus the 32 bit transfer capability may be undesirable since 32 bit operands cannot be a VME system with transferred 16 bit databus limitation for the VME areas to the A register bit selects whether executed with the 16 8 bit data format or according to the capabilities of the decoded VME areas In order to allow the use of all decoded VME address ranges in the gate array provides a D16 D08 MASTER capability the transfer cycles are When the D16 MASTER option is enabled only 16 and 8 bit transfer types will be executed by the VMEbus master in
19. Decoding scheme for accesses to the local WWNNFOOWO CA UI OWOWMDAWAATAHDGUNIAH DW WW DN Oe BW THE CPU AND VME INTERFACE Figure 1 1 LIST OF FIGURES Masking scheme for the base address register bits Tabl Tabl Tabl Tabl Tabl Tabl Tabl Tabl THE CPU AND VME INTERFACE LIST OF TABLES The 32bit Address Decoding Map MAIN MEMORY control overview eae A Address assignment of the local MAIN MEMORY control registers MAIN MEMORY S ZE Address ranges of the VMEbus areas with addressing capability and data transfer bility Axx Dxx So A ak SSS os orted Address Modifier Codes for CPU ss to the VMEbus areas capa Supp acce Supp and Supp and orted Data D08 MASTER orted Data DO8 MASTER Transfer Types for D16 MASTER capability SO Rig th tied Transfer Types for D32 D16 capability a a THE CPU AND VME INTERFACE This page was intentionally left blank THE CPU INTERFACE CPU INTERFACE zL FEATURES programmable main memory decoding programmable main memory size programmable DSACK STERM timing for main memory access programmable DSACK timing for user eprom access Supervisor User mode select for gate array register access programmable DSACK timing for gate array register access LOCAL I O decoding pages with selectable timing parameters THE CPU INTERFACE
20. address lines A31 A28 in this order They define the highest nibble of the 32 bit VMEbus access address 3 2 2 1 Register VMEPAGE Register Mnemonic Address R W Default VME PAGE register VMEPAGE SFFD00200 R W 00 Format of VMEPAGE 7 6 5 4 3 2 1 0 P31 P30 P29 P28 3 0 P 31 28 This bitfield selects the page in can be which the local main accessed from the VME side ram THE VME INTERFACE 3 2 3 VME Interval Decoding The following registers define the decoding interval for VME accesses to the local MAIN memory 3 2 3 1 Registers for Bottom and Top page selection Register Mnemonic Address R W Default Bottom Page Register U BOTTOMPAGEU FFD002D0 R W 00 Bottom Page Register L BOTTOMPAGEL SFFD002D4 R W S00 Top Page Register U TOPPAGEU SFFDO02D8 R W 00 Top Page Register L TOPPAGEL FFD002DC R W 00 The interval decoding of the access range is accomplished by two page decoders One page decoder selects the BOTTOM page and the other the TOP page of the address interval Between these pages all VME addresses are valid Each page decoder compares 16 address lines A27 A11 of the VMEbus with the contents of two 8 bit registers The bottom page decoder compares the address lines A27 A20 with the BOTTOMPAGEU register and the address lines A19 A12 with the BOTTOMPAGEL register Likewise
21. 2 3 The FMB Decoding Definition 2 3 1 FMB Area Decoding The FMB area decoding is performed with the VMEbus address lines A31 A24 They select the FMB area from the 4 Gbyte total address space There must not be any slave responding in the defined FMB area other than according to the FMB protocol 2 3 2 FMB Channel Decoding The address line A23 selects one of two FMB channels Channel 0O is addressed with A23 0 low channel 1 is addressed with A23 1 high FORCE MESSAGE BROADCAST FMB 2 3 3 FMB Board Decoding The FMB board decoding is performed by the address lines A22 to A2 The VMEbus specifies a maximum of 21 slots in a VMEbus rack where boards can be installed Each address line is assigned to one slot in the VMEbus rack Address lines A22 through A2 address slots 21 through 1 respectively A logical one 1 on these address lines means that the FMB slave in the corresponding slot is addressed A logical zero on the address line means that the board is not addressed Any combination is allowed For example if the address lines A2 A3 and A15 are high the boards installed in slot 1 slot 2 and slot 14 are addressed Naturally an FMB slave needs to have a register or other logic built in where the respective slot number is available for the decoding logic The following table shows the assignment of the address lines to the slot numbers VMEbus Slot Addre
22. 7 6 5 4 3 2 1 0 IRQ Status a ES oe a oe 7 IRQ Status The IRQ Status register bit reflects whether there is an interrupt request pending or not 1 is returned if no interrupt is pending 0 is returned if an interrupt request is pending THE 32 BIT DMA CONTROLLER THE 32 BIT DMA CONTROLLER This page was intentionally left blank THE 32 BIT DMA CONTROLLER TABLE OF CONTENTS I FEATURES 2 GENERAL DESCRIPTION 3 DMA REGISTERS Tg 3 1 DMA Controller Register Organization 3 2 DMA Controller Register Address Assignment 3 3 DMA Controller Register Description P 8 63 l Source Attribute Register DMASRCATT S poe Destination Attribute Register DMADSTATT 303433 General Control Register DMAGENERAL 3 3 4 Run Control Register DMARUNCTL 3 30 Mode Status Register DMAMODE Suono Source Address Register DMASRCADR 3 357 Destination Address Register DMADSTADR 3 353 8 Transfer Count Register DMATRFCNT 3 6349 Interrupt Control Register Normal Termina tion ICRDMANOR al NEM dick Seale cela Gen Fale We el Ve 3 3 10 Interrupt Control Register Error Termina tion ICRDMAERR a A OSes SN Ser Sk OLS te 3 3 11 Interrupt Status Register Normal Termina tion ISDMANORM eta tebe Jar eet T 3 3 12 Interrupt Status Register Error Termina tion ISDMAERR LIST OF TABLES Ta
23. STOP 7 OPSTATE The bit reflects the operating state of the DMA Controller 1 The DMA Controller is running 0 The DMA Controller is in the idle state 0 START STOP Writing this bit will start or stop the DMA Controller operation Writing this bit 1 starts the DMA operation 0 stops the DMA operation THE 32 BIT DMA CONTROLLER 3 3 5 Mode Status Register DMAMODE The DMAMODE status indicates if the or in the destination mode register contains a status bit which DMA Controller is operating in the source mode 7 6 5 4 2 2 T 0 MODE z 7 MODE The bit indicates the operating mode of the DMA Controller 1 The DMA Controller is operating in the source mode 0 The DMA Controller is operating in the destination mode 3 3 6 Source Address Register DMASRCADR The 32 bit wide Source Address Register DMASRCADR is to be initialized wi used to genera th the source addressing sequence and holds actual source address after termination of the transfer the start address for the source port It is the 31 24 23 16 15 8 7 Source Address 3 3 7 Destination Address Register DMADSTADR The 32 bit wide is used to gen holds the actual transfer destination address after termination of Destination Address Register DMADSTADR is t
24. areas and several areas for a VMEbus access decoding outputs are supplied Local MAIN memory decoding signal CSDPR System eprom decoding signal Local I O area decoding signal CSPROM CSLIO Secondary or VSBbus decoding signal CSVSB Co processor decoding The local main memory map is software programmabl capacity is selectable from 64 Kby The areas which decode accesses designed to serve the needs of mult CSCOPR te to 256 MByte to the VMEbus ti processor applications STERM INHIN BRCPU BGCPU BGACK PL2 IPLO RESCPU HALT BERRC CKCPU NHOUT secondary bus The following e The memory are specially INTRODUCTION 2 The VMEbus Interface The FGA 002 gate array is connected to the VMEbus via the receiver transmitter circuits The control signals for the transceiver circuitry is also provided by the gate array Control of bus mastership addressing in slave mode as well as a Single level bus arbiter and the bus mastership request releas logic are also included in the FGAOO2 The following VMEbus signals are applied to the gate array VMEbus FGA 002 signals signals Addressing signals A31 A01 AVME31 01 LWORD LWDVME Address Modifier signals AM5 AMO AM5 0 Data signals D31 D00 DVME31 00 Asynchronous bus control AS DS1 DSO ASVME
25. 0 200 002 0000 00000 16 4 2 1 DMA Source Descriptor 2 2 2 2 e 16 4 2 2 DMA Destination Descriptor 2 0 00 00 0000 00 eee 16 4 2 3 DMA Operation Sequence Control 2 0 000 000 ee 17 424 DMA Run Control 2 2 0 2 2 a 17 4 3 Timer Dependent Functions 2 aaa 17 4 3 1 Timer Initialization 2 0 aaa a 17 4 3 2 Timer Run Control 2 aaa a 17 4 4 IRQ Control Functions 0 0200 0 00 2 18 44 1 VMEbus IRQ Control 02 0 200002000000 00 00 ee 18 442 EMB IRQ Control 0 020020 0000000 00 ee 18 4 4 3 Extended Local IRQ Control 2 0 200200 0 000000 0000000 19 444 Local IRQ Control 2 0 0 200 00 00000 a 19 4 4 5 Mailbox IRQ Control 0 2 02 00002000 0000000 0 ee 20 446 Other IRQ Control 0 0 00 20 0 00000 000000000 2 20 4 5 Miscellaneous oaa aaa 21 4 5 1 Receive 4 bytes FMB Message and Jump to this Address 00202 21 FORCE COMPUTERS 4 5 2 4 5 3 4 5 4 4 5 5 4 5 6 4 5 7 4 5 8 4 5 9 Set DPR Address Parameters 2 2 a a Convert Number to Hex String aaa a Convert Hex ASCII to Binary Number 2 0 0 0 0 0 0 0 Broadcast Message via FMB 2 ee Perform VME Reset Call 2 0 0 200200 000000000000 00 0004 Initiate Mailbox IRQ 0 2 0 0 0000 00 ee Program Flash EPROMs 2 000 0000 00000 2 ee Read EAGLE Module Base Addresses 2 2 0 200200 0 0020004 5 Software Structure 5 1 Layout 5
26. The options are to be enabled in the CTL16 register where each option is assigned a register bit It is not allowed to enable both options at the same time After reset the options are disabled A parity error triggers the parity error interrupt if any option is enabled In addition the access address of the cycle will be latched inside the gate array when the interrupt is triggered The error address remains latched until the parity interrupt is cleared The interrupt is cleared by a write access to the interrupt status register of the parity error interrupt 6 2 1 Register CTL16 Register Mnemonic Address R W Default Control Register 16 CThL1L6 SFFDO0035C R W 00 Format of CTL16 7 6 5 4 3 2 1 0 URMW VMET IMEOUT PEB PEA MAIN STERM 4 PEB The bit selects the parity error option B 1 Option B enabled O Option B disabled 3 PEA The bit selects the parity error option A ab Option A enabled O Option A disabled MISCELLANEOUS 6 2 2 PARITY ERROR OPTION A If parity option A is selected a parity error will initiate the following response from the gate array Ts The local processor accesses the main memory A parity error detected during a CPU access to the main memory will trigger the parity error interrupt indicating a malfunction in memory The access address and th
27. 1 2 ADDRESS DECODING STRUCTURE The Gate Array decoding logic involves a 4 GByte address space to control the access to the local MAIN MEMORY the VMEbus the VSB bus the secondary bus and the Local I O Area The decoding logic contains hard wired decoding logic and software programmable decoding logic Software programmable decoding is realized for the local MAIN MEMORY The size and the base address can be selected For the remaining areas hard wired decoding is included The address range 0000 0000 SFAFF FFFF is shared by the local MAIN MEMORY the Extended VMEbus address range and the VSB bus selection The address range S FBOO 0000 SFFFF FFFF contains five 16MByte pages four pages for additional VMEbus and secondary bus decoding and one page for the SYSTEM EPROM and the LOCAL I O Area The LOCAL I O decoding area is provided to select devices which are connected to the Gate Array s Local I O bus such as the BOOT SRAM the BOOT EPROM and diverse I O devices The following table shows the 32bit decoding map for the 4GByte address space of the CPU THE CPU INTERFACE Table 1 1 The 32bit Address Decoding Map 0000 0000 MAIN MEMORY A32 D32 VSB Bus A32 D32 D16 D8 VMEbus Extended Address Range A32 D32 D16 FAFF FFFF FBXX XXXX FBOO 0000 VMEbus Standard Address Range A24 D32 ETE E
28. interrupt ICRFMBOMES 7 6 3 IRQ Enable IRQ Level 6 3 4 The control register FMBO Refused channel 0 refused interrupt is used to configure which is assigned to Interrupt Control Register Channel0 Refused ICRFMBOREF ICRFMBOREF interrupt channel the the Format of ICRFMBOREF 7 6 4 3 2 1 0 IRQ Enable IRQ Level FORCE MESSAGE BROADCAST FMB 6 3 5 Interrupt Control Register Channel 1 Message ICRFMB1MES The ICRFMBIMES control register is used to configure the interrupt channel FMB1 Message handling the message interrupt of Channel 1 Format of ICRFMBIMES 7 6 5 4 3 2 1 0 IRQ Enable IRQ Level 6 3 6 Interrupt Control Register Channel 1 Refused ICRFMB1REF The ICRFMBIREF control register is used to configure the interrupt channel FMB1 Refused which is assigned to the channel 1 refused interrupt Format of ICRFMBIREF 7 6 5 4 3 2 1 0 IRQ F Enable IRQ Level Bit function of the FMB interrupt control registers 3 IRQ Enable The bit enables or disables the interrupt channel O Interrupt channel is disabled 1 Interrupt channel is enabled FORCE MESSAGE BROADCAST FMB
29. AUXFIFREX REG STER FORMAT BITs 76543210 Byte XXXX Reset Value 00 BIT 3 0 AUXFIFREX 3 0 EI DYPPNPPYPPDPYNPPDPDY P U U XFI FO Read Tim XF IFO Read Tim XFI FO Read Tim XF IFO Read Tim XFI FO Read Tim XF IFO Read Tim XFI FO Read Tim XF TEO Read Tim XFI FO Read Tim XF IFO Read Tim XFI FO Read Tim XF TEO Read Tim XFI FO Read Tim XF IFO Read Tim XFI FO Read Tim XF TEO Read Tim in in in in in in in in in in in in in in in in SFF BQAQQONYNQNQNQYNOQQNQQQNQY rWO OAD PWNEF OO OB WNEF O D0026C CTL6 REGISTER FORMAT SFFD00270 BITs 76543210 Byte XXXX Reset Value 00 BIT 3 0 MYREGDSACK Access to FGA 002 Registers from local side 0001 with Waitstate 0010 with Waitstates 0100 with Waitstates 1000 with Waitstates 0000 with Waitstates BwWNHE O CTL7 REGISTER FORMAT BITs 76543210 Byte XXXX Reset Value 00 BIT 3 RBCLR BIT 2 0 RORINHIBIT SFFD00274 Release On Busclear option VMEbus will be released on asserted BCLR 1 no N 0 yes O as as quest inhibit time O O O O W E a Ee M e oO s
30. bat triggers the timer sysfail signal is negated terrupt is cleared tion is enables disables If this option is LO output pin of the FGA 002 ted the sysfail low when the interrupt The when the timer enabled Timer Sysfail generation is disabled Start Stop Clock select This bit controls the timer start and stop operation Writin enables counting the bit is cleared to S S tops timer operation of the source Th tarts timer operation 03 g this bit with 1 e timer stops if This bitfield provides selection clock for timer operation 3 0 source clock period 0000 1 microsecond 0001 2 microseconds 0010 4 microseconds 0011 8 microseconds 0100 16 microseconds 0101 32 microseconds 0110 64 microseconds 0 128 microseconds 1000 256 microseconds 100 512 microseconds 1010 2 milliseconds 10 8 milliseconds 1100 32 milliseconds 0 125 milliseconds 10 500 milliseconds 2 seconds THE TIMER 3 Timer Count Register TIMOCOUNT The Timer Count Register T of the timer counter load the counter with the val Register The written data will be timer Count Register when th Register is ignored is running initialized to the value FF MOCOUNT contains the current value A write access to this re
31. BITs 76543210 Byte XXXXXXXX Reset Value 00 BIT 7 0 Tasses Decoding Page for access to FGA 002 functions from VME side SYYxx The decoding is valid when the VME Address lines A15 A8 match the value of the corresponding bits 15 0 8 TIMOPRELOAD REGI BITs 76543210 Byte XXXXXXXX Reset Value 00 BIT 7 0 IMOPRELOAD STER FORMAT SFE Preload Register for Timer0O D00300 TIMOCTL REG ISTER FORMAT BITs 76543210 Byte XXXXXXXX Reset Value 00 BIT 7 ZEROSTOP BIT 6 AUTOPRELOAD BIT 5 SYSFAIL BIT 4 STARTSTOP BIT 3 0 CLOCKSELECT OF starts T stops T SYSFAIL generat SYSFAIL generat MER IMER SFFD00310 Roll over zero and continue Stops counting on zero Auto Preload enabled Auto Preload disabled tion enabled tion disabled Clock period select for timer0O 0 27 1 us 2 u 4 u 8 u 16 u ANNANAANAANANNAUUNANNAUNANN w N Sog ie ie ee N n DMASRCATT REG BITs 76543210 Byte XXXXXXXX Reset Value 00 BIT 7 0 DMASRCATT STER FORMAT DMA Source Attribute SFE D00320 DMADSTATT REGISTER FORMAT SFFD00324 BITs 76543210 Byte XXXXXXXX Reset Value 00 BIT 7 0 DMADSTATT DMA Destination Attribute DMAGENERAL REGISTER FORMAT BITs 76543210 Byte XXXXXXXX Reset Value 00 BIT 7 C
32. RSKEYRES REGISTER FORMAT SFFDO0O4F4 BITs 76543210 Byte RoS S gt Power Up Value 80 BIT 7 Read Only Location Reset Status of the KEY Reset 1 RESET KEY input was not activ 0 Reset was initiated by the RESET KEY input RSCPUCALL REGISTER FORMAT SFFDOO4F8 BITs 76543210 Byte Rea Se Power Up Value 80 BIT 7 Read Only Location Reset Status for the CPU Reset call 1 CPU Reset call was not activ 0 Reset was initiated by the CPU Reset call RSLOCSW REGISTER FORMAT SFFDOO4FC BITs 76543210 Byte RSS SS Power Up Value 80 BIT 7 Read Only Location Reset Status for the LOCAL SWITCH reset 1 LOCAL SWITCH reset was not activ O Reset was initiated by the LOCSW input DMASRCADR REGISTER FORMAT SFFD00500 BITs 31 0 Long XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Reset Value 00000000 BIT 31 0 DMASRCADR 31 0 DMA Source Address Register DMADSTADR REG STER FORMAT SFFD00504 BITs Long 31 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0 Reset Value BIT 31 0 DMA DSTA 00000000 DR 31 DMA Destination Address Register DMATRFCNT REGISTER FORMAT SFFD00508 BITs Long 31 XXXXXXXX XXXXXXXX XXXXXXXK XXXXXXXX 0 Reset Value BIT 31 0 SFFFFFFFF DMATRFCNT 31 0 DMA Byte Transfer Count Register TIMOCOUNT REG
33. Write Access Clears the Parity interrupt DMARUNCTL REGISTER FORMAT BITs 76543210 Byte Resa W Reset Value 00 BIT 7 OPSTATE BIT 0 START STOP SFFD004C4 Read Access 1 0 DMA operation state bit DMA is running DMA is idle Write Access writing the bit Ts 0 59773 starts DMA controller stops DMA controller ISABORT REG ISTER FORMAT BITs 76543210 Byte i Reset Value 80 BIT 7 ISABORT SFFDO04C8 Read Access Interrupt Status readback ABORT interrupt cleared 0 ABORT interrupt pending Write Access Clears the edge triggered ABORT interrupt ISACFAIL REGISTER FORMAT BITs 76543210 Byte SoS aS Reset Value 80 BIT 7 ISACFAI SFFDOO4CC Read Access Interrupt Status readback ACFAIL interrupt cleared O ACFAIL interrupt pending Write Access Clears the edge triggered ACFAIL interrupt ISSYSFAIL REGISTER FORMAT SFFDO04D0 BITs 76543210 Byte SS gt SS Reset Value 80 BIT 7 ISSYSFAIL Read Access Interrupt Status readback 1 SYSFAIL interrupt cleared 0 SYSFAIL interrupt pending Write Access Clears the edge triggered SYSFAIL interrupt ABORTPIN REGISTER FORMAT SFFDO004I BITs 76543210 Byte Rea SSS BIT 7 Read Only Location ABORT input pin level readback 1 ABORT input
34. 3 CPU clock cycles delay 2 CPU clock cycles delay 1 CPU clock cycles delay Fastest Timing CPU clock synchronized AS to VME Timing ASV Pin valid after 00 01 1 5 CPU clock cycles CPU clock cycle 10 41 0 5 CPU clock cycle Fastest Timing CTL15 REGISTER FORMAT BITs 76543210 Byte XXxxXXXX Reset Value 00 BIT 7 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 VSBSECTIMEOUT BURSTTRANS BURSTCYCLE CINHOFFBRD CINH16 CINHLIO SHAREDRMW SFFD00358 VSB SECONDARY Bus Error Timeout 00 64000 us 01 1000 us 10 16 us 11 disabled 1 Two transfers per burst 0 Four transfers per burst I l waitstate burst cycles O O waitstate burst cycles Cache Inhibit generation for access to offboard addresses 1 disabled 0 enabled Cache Inhibit generation for access to the address range FCXX XXXX 16Bit VME Data bus FEXX XXXX 16Bit Secondary Data 1 disabled 0 enabled Cache Inhibit generation for access to the Local I O area FF8X XXXX FFFX XXXX 1 disabled 0 enabled RMW cycle from VME to the Shared main memory is 1 supported The local bus will be released later for the CPU 0 not supported Fast release of the local bus for the CPU is provided CTL16 REGISTER FORMAT BITs 76543210 Byte XXXXXXXX Reset
35. BIT 5 4 XSD BIT 3 2 XUP BIT 1 0 XUD SFFDO002B4 MAIN MEMORY Access from VME with Extended Supervisor Program Address Modifier Code SOE 00 disabled 01 disabled 10 enabled for READ cycles 11 enabled for R W cycles MAIN MEMORY Access from VME with Extended Supervisor Modifier Code 0D Data Address 00 disabled 01 disabled 10 enabled for READ Cycles 11 enabled for R W Cycles MAIN MEMORY Access from VME with Extended User Program Address Modifier Code 0A 00 disabled 01 disabled 10 enabled for READ Cycles 11 enabled for R W Cycles MAIN MEMORY Access from VME with Extended User Data Address Modifier Code 09 00 disabled 01 disabled 10 enabled for READ Cycles 11 enabled for R W Cycles CTL10 REGISTER FORMAT SFFDO02CO BITs 76543210 Byte XXXXXXXX Reset Value 00 BIT 7 0 MS 23 16 MAIN Memory Size selection The register bits have to be programmed according to the following table 00000000 256 MByte 00000000 128 MByte 00000000 64 MByte 00000000 32 MByte 00000000 16 MByte 10000000 8 MByte 11000000 4 MByte 100000 2 MByte 0000 1 MByte 000 512 KByte 00 256 KByte 10 128 KByte 1 64 KByte CTL11 RE
36. Release on ACFAIL Release Every Cycle 2 7 1 Release On Request ROR The Release On Request func The gate array releases th tion ROR demands the actual bus master to release the mastership if another requester has a request for bus control pending bus on the request of another master provided that a predetermined interval has elapsed The interval starts when the board becomes master and the length of the interval is selectable in the CTL7 register by This guarantees the master a e VMEbus Once the interval has the RORINHIBIT bitfield minimum occupation time on th elapsed and a bus request is pending then the bus released after completion of the current bus cycle The ROR function cannot be disabled will be THE VME INTERFACE 2 7 1 1 Register CTL7 Register Mnemonic Address R W Default Control 7 Register CPE SFFD00274 R W 00 Format of CTL 7 7 6 5 4 3 2 1 0 RBCLR RORINHIBIT 2 0 RORINHIBIT Release On Request inhibit time 000 0 5 us 001 iL us 010 2 us 011 4 us 100 8 us 101 16 us 110 32 us 64 us THE VME INTERFACE 2 7 2 The gate array releases th option asserte 3 to en Release on Bus Clear RBCLR is enabled and the BCLR d on the BCLRI able this release function VMEbus mastershi
37. by a fixed interrupt vector The timer also can be used as a system watchdog timer to generate sysfail information for the VMEbus The generation of an interrupt or a sysfail may be enabled disabled independently The clock source of the Timer Counter can be selected from one of 16 internally generated clocks with frequencies from 0 5Hz to 1MHz The Timer Counter is realised as an 8 bit synchronous down counter which can be loaded from an 8 bit preload register The Timer Counter function and clock selection are fully controlled by the 8 bit Timer Control Register THE TIMER This page was intentionally left blank THE TIMER III TIMER REGISTERS A Register Organization 31 24 TIMOPRELOAD Timer Preload Register TIMOCTL Timer Control Register TIMOCOUNT Timer Count Register CRTIMO Timer Interrupt Control Register STIMO Timer Interrupt Status Register THE TIMER B Register Address Assignment The following chart details the register address assignment Register Mnemonic Address R W Default Timer Preload Register TIMOPRELOAD SFFD00300 R W 00 Timer Control Register TIMOCTL SFFD00310 R W 00 Timer Count Register TIMOCOUNT SFFDOOCOO R W SFF Timer Int Control Reg ICRTIMO SFFD00220 R W 00 Timer Int Status Reg STIMO FFD004A0 R W 80
38. es es es es es es es es es pin is assert ted pin is assert ter data has been read 0 1 clockcycl Sl 2 clockcycl 2 3 e lockcycl 3 4 clockcycl 4 5 clockcycl 5 6 clockcycl 6 7 clockcycl 7 8 clockcycl 8 9 clockcycl 9 10 clockcycl SA 11 clockcycl B 12 clockcycl C after AUXRDY D not allowed SE aft into the fifo SF on valid READY NEWCYCLE starts x cycles of 32mhz after READY 0 1 clockcycl 1 2 clockcycl 2 3 clockcycl 3 4 clockcycl 4 5 clockcycl 5 6 clockcycl 6 7 clockcycl 7 8 clockcycl 8 9 clockcycl 9 10 clockcycl SA 11 elockeyel SB 12 clockcycl SC after AUXRDY SD after AUXACK SE aft into the fifo SF on valid READY 38 ted AUXDSTTERM REGISTER FORMAT BITs 76543210 Byte XXXXXXXX Reset Value 00 BIT 7 4 BIT 3 0 DSTRELACK 7 4 DSTNEWCYC 3 0 SFFD0034C AUXACK pin is released x cycles of 32mhz clock after READY es es es es es es es es es es es pin is asserted ter data has been read clock e es es es es es es es es es es es pin is assert ted pin is assert ter data has been read 0 1 clockcycl Sl 2 clockcycl 2 3 e lockcycl 3 4 clockcycl 4 5 clockcycl 5 6 clockcycl 6 7 clockcycl 7 8 clockcycl 8 9 clockc
39. retry try jn times to send IRQ 4 5 8 Program Flash EPROMs This routine is used to program Flash EPROMs It must be called in Supervisor Mode typedef struct char flashbase char rambase unsigned long length int width unsigned long vall unsigned long val2 long firstbad FLASHPARM int fga_util unsigned long flashprg FLASHPARM flashdata flashprg 34 flashdata pointer to struct FLASHPARM The structure must be filled with flashbase The base address of the Flash EPROM which is to program rambase The start address of the data which is to program length It specifies the length of the Flash EPROM If a 0 is given the length and width is calculated automatically width It selects the data width of the Flash EPROMs Three values are possible 1 Byte width 8 bit 2 Word width 16 bit 4 Long width 32 bit NOTE The Flash EPROM s must be programmed completely Therefore programming only parts of a Flash EPROM is not possible 4 5 9 Read EAGLE Module Base Addresses This function returns the base addresses for I O EPROM and RAM of every EAGLE module 23 FORCE COMPUTERS typedef struct _module_initparms unsigned long modulel_iobase unsigned long module1_idprom unsigned long modulei_apmem unsigned long module2_iobase unsigned long module2_idprom unsigned long module2_apmem MODULE_INITPARMS int fga_util unsigned long readModuleParms MODULE_INITPARMS parmsptr readModule
40. the top page decoder compares the VME address lines A27 A20 and A19 A12 with the registers TOPPAGEU and TOPPAGEL respectively Each register set bottom or top specifies the base address of its respective 4 KByte page The register contents of the top page do not define th nd address of an interval but specify the base address of its top page The address interval selected by these registers ranges from the base address of the bottom page to the end address of the top page THE VME INTERFACE Format of BOTTOMPAGEU Y 6 5 4 3 2 1 0 B27 B26 B25 B24 B23 B22 B21 B20 7 0 B 27 20 These bits are compared with the VMEbus address lines A27 A20 and select the upper portion of the bottom page address Format of BOTTOMPAGEL 7 6 5 4 3 2 0 B19 B18 B17 B16 B15 B14 B13 B12 7 0 B 19 12 These bits are compared with the VMEbus address lines A19 A12 and select the lower portion of the bottom page address Format of TOPPAGEU 7 6 5 4 3 2 a 0 T27 T26 T25 T24 T23 T22 T21 T20 7 0 T 27 20 These bits are compared with the VMEbus address lines A27 A20 and select the upper portion of the top page address Format of TOPPAGEL 7 6 5 4 3 2 0 T19 T18 T17 T16 T15 T14 T13 T12 7 0 B 27 20 These bits are compared with the VMEbus address lines A27
41. 0 0 0 0 0 0 0 0 16 MByte 1 0 0 0 0 0 0 0 0 8 MByte 1 0 0 0 0 0 0 0 4 MByte 1 0 0 0 0 0 0 2 MByte 0 0 0 0 0 1 MByte 0 0 0 0 512 KByte 0 0 0 256 KByte 0 0 128 KByte 1 0 64 KByte 1 THE CPU INTERFACE T 3 4 The MAIN MEMORY BASE ADDRESS The base address for the local main memory has to be defined within the address range 0000 0000 A set of two selection SFAFF FFFF registers is provided for the base address MAINUU register MAINUM register The following terms are used to designate the address bytes of a 32 bit address value Address bits Address byte A31 A24 Upper Upper Byte A23 A16 Upper Middle Byte A15 A08 Lower Middle Byte AO7 A00 Lower Lower Byte The local base address of assigning the value of the upper upper address byte to the MAINUU register and the MAINUM register Th th the main memory can be selected by A31 A24 the upper middle byte A23 A16 to e base address decoding is performed by a comparison of the e BASEUU pattern stored in the bits B31 B16 To determine which values have to be writ address registers the programmed main memory size also has to be taken into account When the memory size the base address register bits B27 B16 will be masked by is selected to be greater than 64 Kby the CPU address lines A31 A16 with th
42. 1 PARITY GENERATION CHECK 6 1 Registers CTL2 6 1 2 Register CTL2 6 2 PARITY ERROR EVALUATION 6 2 1 Register CTL16 C2 eZ PARITY ERROR OPTION A 6 22 3 PARITY ERROR OPTION B 0 OY A W PARITY ERROR ADDRESS READOUT Register PTYATT oo MISCELLANEOUS I BUS ERROR GENERATION The BUS ERROR Logic of the gate array supports bus error generation for the VMEbus as well as for the local processor The BERRVO output provides the active low error termination signal for the VMEbus On the BERRVI input the gate array detects when a bus error condition occurred on the VMEbus The BERRC signal is generated as an active low bus error signal for the local processor This signal is also generated for the gate array internal DMA controller 1 1 BUS ERROR GENERATION TO VME The gate array drives the signal BERRVO low for a VMEbus error termination in the following cases a Bus error during an FMB cycle D Bus error due to a parity error detection Ex Bus error due to a VMEbus timeout 1 1 1 FMB bus error If the gate array is addressed in a FORCE Message Broadcast cycle and the message cannot be stored because of a full FMB fifo the BERRVO signal will be asserted Please refer to the FMB section of this manual for more details 1 1 2 Bus error on parity error detection The gate array drives the VME bus error signal BERRVO if the internal parity logic detects an error during a
43. 2 Structure 2 5 3 Starting Firmware 2 A Incompatibilities to Previous Versions List of Figures 1 2 EPROM Usage 2 a Flow Chart 2 0 0 0 List of Tables 1 Slot Numbers VMEbus address 2 0 a 25 25 FGA 002A Boot Software Version 4 1 Overview This Boot Software is needed to set up various board specific details to get the board running Its goal is to relieve the customer s software of initializing the hardware The Boot Software is the very first code executed from the processor after reset It exits to the firmware of the board The Boot Software is devided into 2 parts Initialization and Debugger Initialization is done every time the Boot Software is executed while the debugger is only executed if requested 2 Initialization The initialization is started directly after a processor reset Most of the initialization values are fetched from the battary backed up SRAM If the SRAM content is corrupted default values will be copied to the SRAM prior to initialization 2 1 Changing the SRAM default The SRAM values control the setting of the FGA 002A They do not control the FC68165 initialization values 2 ways are possible to change the SRAM defaults e Using the SETUP command of the Debugger This is the best way for changing default values Some bits of FGA 002A registers should not be altered i e timings to ensure proper functionality of the board The SETUP command takes care of th
44. A20 and select the lower portion of the top page address THE VME INTERFACE 3 2 4 Enable Address Modifier Decoding The address modifier code which the VME master has to broadcast for a valid access to the main memory is selectable in the ENAMCODE register After reset no access to the main memory from VME side is possible since the register is cleared and all address modifier code selections are disabled Additionally the decoding area can be protected from write accesses by VMEbus masters THE VME INTERFACE 3 2 4 1 Register ENAMCODE Register Mnemonic Address R W Default Enable AM code Register ENAMCODE SFFDO02B4 R W 00 Format of ENAMCODE 7 6 4 3 2 1 0 XSP XSD XUP XUD 7 6 XSP Extended Supervisor Program Access AM code 00 disabled 01 disabled 10 enabled for READ Access 11 enabled for R W Access 5 4 XSD Extended Supervisor Data Access AM code 00 disabled 01 disabled 10 enabled for READ Access 11 enabled for R W Access 3 2 XUP Extended User Program Access AM code 00 disabled 01 disabled 10 enabled for READ Access 11 enabled for R W Access 1 0 XUD Extended User Data Access AM code 00 disabled 01 disabled 10 enabled for READ Access 11 enabled for R W Access THE VME INTERFACE 3 3 S
45. CELLS SFFD00358 R W 00 Format of CTL15 7 6 5 4 3 2 1 0 VSBSEC BURST BURST CINH CINH16 CINH SHARED TIMEOUT TRANS CYCLE OFF BRD LIO RMW 7 6 VSBSECTIMEOUT The bitfield selects the bus error timeout for accesses to the VSB bus or to the SECONDARY bus decoding area 00 64000 us 01 1000 us 10 16 us 11 disabled MISCELLANEOUS 1 2 3 Bus error on parity error detection The gate array drives the bus error signal BERRC for the lo processor and the DMA when a parity error is detected on access to the main memory For this bus error the parity er option A must be enabled More information can be found in chapter PARITY Support 1 2 4 VMEbus timeout bus error The gate array provides a timeout counter for accesses of local processor or the DMA controller to the VMEbus The counter is started if any VME data strobe output of gate array DSO or DS1 is asserted cal an ror the the the If the VMEbus timeout counter has counted out becaus th addressed device was not responding the gate array generates an active low BERRVO bus error signal which is driven as BERR signal to the VMEbus In order to inform the processor or the DMA controller of an unsuccessful VME cycle the VME bus error signal is monitored on the BERRVI input of th
46. LOCAL I O page which is not supported by the LOCAL I O interface A valid decoding of the LOCAL I O Area is indicated by a low level on the output pin CSLIO of the gate array The various pages of the LOCAL I O Area have to be decoded with external hardware using the processor address lines A22 A20 and the signal CSLIO generated by the gate array In order to decode the BOOT EPROM area during the boot up procedure the address signal A23 needs to be included as well Please refer to the chapter BOOT DECODING FEATURES for more details The LOCAL I O interface is implemented with a byte wide data bus and consists of the following signals Signal Name Function CSLIO LOCAL I O Area Select RDLIO Read Strobe WRLIO Write Strobe DLIO 0 7 Data Lines THE CPU INTERFACE The LOCAL I O Pages ar defined as follows Address Range Definition FF8X XXXX LOCAL I O Page A FF9X XXXX LOCAL I O Page B FFAX XXXX LOCAL I O Page C FFBX XXXX LOCAL I O Page D FFCX XXXX BOOT SRAM FFDX XXXX GATE ARRAY Registers FFEX XXXX BOOT EPROM FFFX XXXX LOCAL I O Page E The LOCAL I O pages A whose access protocol provided for the LOCAL connected to the LOCAL D can be used to select onboard devices meets one of the timing parameters I O pages A D The devices must be I O interface Acce
47. Level vity clear Enable IRQ Level Select INTERRUPT MANAGEMENT Edge Level Activity Extended interrupt control register bit The bit selects whether input is level or edge the bit is set to 1 input is selected sensitive An active interrupt input pin interrupt I interrupt cT CT the interr sensitive the interr to be e edge at triggers If the bit is 0 input is level sensitive As bit 6 is cleared to zero af reset level sensitivity is selected by default Interrupt input is edge Interrupt input is leve Extended Interrupt Cont Bat This bit configures the interr input to be active hi low An active low inp sensitiv l sensitiv rol Regist gh or act Up ct Hct upi dge the the the CCE e e er upt ive ut means that the interrupt will be triggered by a high to low edge fo sensitive input or a low level on th for a leve sensitive input An active high inpu interrupt input pin r an means that the interrupt will triggered by a low to high edge or high level on the interrupt pin After reset the bit is cleared an the input activity is a ctive low Interrupt input is active high Interrupt input is active low inpu dge b to OoctrHo Q INTERRUPT MANAGEMENT
48. MAILBOX 7 Mailbox 7 SFFDOOOI1C THE TIMER This page was intentionally left blank THE TIMER TABLE OF CONTENTS FEATURES GENERAL DESCRIPTION TIMER REGISTERS 3 1 Register Organization 3 2 Register Address Assignment 3 3 Register Description Timer Preload Register TIMOPRELOA Timer Control Register TIMOCTL Timer Count Register TIMOCOUNT Timer Interrupt WWW W W WWW W W Obs WN Control Register CRI Timer Interrupt OPERATION DESCRIPTION 4 1 Timer Counter 4 1 1 Timer Registers 4 2 Timer Interrupt 4 2 1 Timer Interrupt 4 3 SYSFAIL Generation ST Status Register Registers MO MO N WWW WW WW W W NDNOUWNNNEF EF THE TIMER This page was intentionally left blank THE TIMER FEATURES 8 bit Synchronous Counter 16 selectable clocks with frequencies from 1MHz to 0 5 Hz Autopreload and Zerostop operating modes Watchdog Timer operation SYSFAIL and or interrupt generation Vectored interrupt Interrupt levels selectable by software THE TIMER This page was intentionally left blank THE TIMER II GENERAL DESCRIPTION The FGA 002 Gate Array includes an 8 bit Timer Counter It can be programmed to generate periodical interrupts or a single interrupt after a programmed time period The interrupt level is software programmable and is supported
49. MEMORY ENABLE Bit Bit 7 of the CTL11 register selects if the local sided MAIN MEMORY decoding is enabled or disabled After reset the register is cleared to 0 which disables the decoding During the initialization of the MEMORY SIZE and the MEMORY BASE address the bit should be cleared to disable the decoding logic 1 321 Register CTL11 7 6 5 4 3 2 HE 0 MAIN ENA MAIN DSACK S27 S26 S25 S24 7 MAIN ENA This bit is used to enable disable the local sided MAIN MEMORY decoding area 1 enabled 0 disabled THE CPU INTERFACE 1 3 3 The MAIN MEMORY SIZE The SIZE of the local MAIN MEMORY is programmed in the CTL10 and CTL11 registers The bits S27 S16 select the SIZE in ranges of 64 KByte up to 256 MByte 1 3 3 1 Register CTL11 7 6 5 4 3 2 1 0 MAIN ENA MAIN DSACK S27 S26 25 S24 1 3 3 2 Register CTL10 a 6 5 4 3 2 1 0 23 22 S21 S20 s19 s18 S17 s16 The following table summarizes the selectable memory sizes Other combinations are not allowed Table 1 4 MAIN MEMORY SIZE CTLELL CTL10 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 MEMORY SIZE 256 MByte 0 0 0 0 0 0 0 0 0 0 0 0 128 MByte 1 0 0 0 0 0 0 0 0 0 0 0 64 MByte 1 1 0 0 0 0 0 0 0 0 0 0 32 MByte 1 0
50. Mode Status DMAMODE SFFDOO4EC R W 80 Source Address DMASRCADR SFFD00500 R W 00000000 Destination Address DMADSTADR SFFD00504 R W 00000000 Transfer Count DMATRECNT SFFD00508 R W SFFFFFFFF Register is to be accessed only with Long Operand Size THE 32 BIT DMA CONTROLLER 3 3 DMA Controller Register Description 3 3 1 Source Attribute Register DMASRCATT The DMASRCATT register is to be programmed with the attribute code for the source operation port The code has to define the source operating port with the appropriate bus width If the port is selected to be the local bus the least significant three bits have to hold the function code according to the address space type of 68020 68030 processor If the VMEbus port is selected as source the lower six bits must be programmed with the proper Address Modifier code for the access to the VMEbus 7 6 5 4 3 2 il 0 Attribute code for the source port 7 0 Attribute code for the operation on the source port Please refer to table 3 1 3 3 2 Destination Attribute Register DMADSTATT The DMADSTATT register is to be programmed with the attribute code for the destination operation port The code has to define the destination operating port with the appropriate bus width If the port is select
51. Register CTL8 Register Mnemonic Address R W Default Control 8 Register CTL8 SFFD00278 R W 00 Format of CTL8 7 6 5 4 3 2 1 0 BSYSBIT SSYSBIT FAIR ROACF 1 FAIR FAIR request option bit 1 FAIR request option disabled O FAIR request option enabled 2 15 THE VME INTERFACE 2 7 VMEbus RELEASE The gate array provides va the local processor or the released in different ways minimize arbitration overhead in multi mast Depending on which device has become the current bus master DMA controller the bus rious bus release funct The DMA Controller only rel discretion irrespective of implemented additionally ases the VMEbus only at ions to ter VMEbus systems will be its own the release functions which are Every time the DMA controller switches from the source mode to the destination mode it releases for its task The bus occupation time between two swit transfer This is dependent is approximately the time the a block of 32 bytes on the appropriate bus DMA controller needs to the bus which it had occupied tchovers on the access time of the devices and the alignment of the source and destination address When the local processor has been granted the mastership for the VMEbus the following release options can come into effect Release on Request Release on BUSCLEAR Release Voluntary RV
52. SHAREDRMW The bit selects if read modify write cycles from VME to the shared RAM will be supported by the gate array 1 supports RMW cycles 0 no support for RMW cycles THE VME INTERFACE 3 4 VME Access to FGA 002 functions The gate array provides several functions which are available from the VMEbus side The following functions and status reports provided by the gate array are accessible MAILBOX Locations RESET Call function STATUS report of the SYSFAIL output signal and the processor HALT signal line The gate array is accessible by all VMEbus masters which have short addressing capability A16 Additionally the bus master has to present an address modifier code for the Short I O decoding range Before a VMEbus master can perform a valid access to the gate array two registers have to be initialized by the local processor One register defines the VME page and another selects the code for the Address Modifier signals which the VME master has to broadcast for a valid access to the gate array If no selection for the address modifier code is made an access to these gate array functions from VME side is not possible The VME page of the gate array is a 256 byte page which is decoded by the VME address signals A15 A8 within the short addressing range of the VMEbus Within the VME page the functions are assigned fixed offsets The VME page is programm
53. Status 7 IRQ Status The IRQ Status register bit displays if a timer interrupt request is pending 1 is returned if no interrupt is pending O is returned if the interrupt is pending THE TIMER IV OPERATION DESCRIPTION A Timer Counter 1 Timer Registers The timer function includes the following registers Register Mnemonic Address R W Default Timer Preload Register TIMOPRELOAD SFFD00300 R W 00 Timer Control Register TIMOCTL SFFD00310 R W S00 Timer Count Register TIMOCOUNT SFFDOOCOO R W SFF Write access causes special data transfer The Timer Counter may be clocked by 16 different internally generated clocks The timer source clock is selected by the lower 4 bits of the TIMOCTL register After reset the Timer Control Register is cleared and therefore the timer will be clocked by the 1 MHz clock The counter circuitry is cleared to the value 00 only after the powerup reset while the preload and control register ar cleared by any reset Timer run control is performed by the START STOP bit in the timer control register Writing this bit with 1 will enable timer operation in the selected operating mode This bit also allows the timer to be stopped during operation and to be restarted again The maximum resolution of a start stop period is the period of the source clock This also implies that the coun
54. The interrupt is performed by simultaneously sending each board a message byte Any VME master with 32 bit addressing capability can accomplish an FMB broadcast cycle The implementation of the FMB concept in the FGA 002 is realized with two individual message channels each able to perform two interrupt requests While the 8 byte FIFO of channel 0 allows several messages to be sent in succession channel 1 with its one byte FIFO can be used for prioritized messages In the current version of the FGA 002 gate array 8 bit wide messages can be received 6 THE MAILBOXES The FGA 002 includes 8 mailboxes The dual ported mailboxes are accessible by the local processor as well as by VME masters The mailboxes provide a means to synchronize multiple cpu boards by sending them an interrupt The mailboxes also can be used as semaphores for the allocation of system resources used by several masters in common Ls The Timer There is an 8 bit timer included in the FGA 002 gate array The timer can be used as a periodical timer or as a watchdog timer generating a sysfail signal to the VMEbus The timer generates an interrupt request with a software programmable level The clock source for the timer is software selectable from one of 16 internally generated clocks INTRODUCTION 8 History of Manual Revisions Revision 1 Complete Rework of Manual Revision 2 The following Section
55. Timing DTACK output Table 2 3 Parameter min ns max ns 6 420 510 7 540 a 8 0 a Timing Parameters for an Accepted Cycle FORCE MESSAGE BROADCAST FMB FEATURES OF THE FGA 002 FMB INTERFACE Full compatibility with the VMEbus Specification Rev C 2 FMB Channels for high and low prioritized messages 8 bit wide message data FIFO depth of 8 Bytes on FMB Channel 0 FIFO depth of 1 Byte on FMB Channel 1 Software selectable FMB address decoding 2 vectored interrupts for each FMB channel Programmable interrupt levels Software selectable address modifier decoding No special hardware requirements for the message broadcasting master FORCE MESSAGE BROADCAST FMB This page was intentionally left blank FORCE MESSAGE BROADCAST FMB 4 GENERAL DESCRIPTION The FGA 002 Gate Array has implemented the FMB structure with byte wide message data The message is to be sent by the broadcasting master on the D7 DO data lines of the VMEbus With the FGA 002 Gate Array any FMB data cycle Byte Word or Long data format is allowed The message data will always be fetched from the VME Data Bus on the D7 DO signal lines The FMB Slave interface on the FGA 002 gate array includes two channels The channels are selected by the VMEbus address line A23 A low state logical 0 on A23 selects channel 0 while the high state logical 1 selects chann
56. VME access to the local main memory The generation of the VME bus error signal due to a parity error detection assumes that the gate array is programmed to support the shared memory structure and that one of the parity error options Option A or B is enabled For more information please refer to chapter Parity Support MISCELLANEOUS 1 1 3 VME timeout bus error A timeout bus error is generated to the VMEbus to terminate a cycle which addresses a nonpresent location or a device which does not respond The BERRVO signal is driven if the device does not respond within a defined time The timeout is monitored by the gate array s internal VMEbus timeout counter which is restarted on CPU accesses and DMA controller accesses to the VMEbus Please refer to chapter VME bus access timeout later in this section 1 2 BUS ERROR GENERATION FOR THE CPU AND DMA CONTROLLER The gate array indicates a bus error to the processor or to the DMA controller in the following cases ue to an ONBOARD access timeout ue to a VSB SECONDARY bus access timeout ue to a PARITY error detection ue to a VMEbus access timeout ue to an UNALIGNED RMW cycle to VME ue to a LONG timeout Bus error Bus error Bus error Bus error Bus error Bus error Mwoa W a2a00 0 0 1 2 1 Onboard timeout Bus error A timeout counter is provided inside the gate array for local processor accesses to the MAIN memory d
57. Value 00 BIT 7 URMW BIT 6 5 VMETIMEOUT BIT 4 PEB BIT 3 PEA BIT 2 0 MAINSTERM SFFD0035C 1 Unaligned Read Modify Write cycle will be executed as standard Read and Write cycles 0 Unaligned Read Modify Write cycle generates bus error to the CPU VME Bus Error Timeout 00 64000 us 01 1000 us 10 64 us 1 16 us Parity Error Option B Parity Error triggers Parity Interrupt 1 enabled 0 disabled Parity Error Option A Parity Error and triggers 1 enabled disabled generates Bus Error Parity Interrupt MAIN Memory STERM timing no STERM generation 000 001 010 100 43 0 waits 1 waits 2 waits tate STERM tate STERM tate STERM PTYLL REGISTER FORMAT SFFD00400 BITs 76543210 Byte RRRRRRRR Reset Value 00 BIT 7 0 Readonly Register for the parity error address evaluation LL Byte of the latched parity error address SxxxxxxLL A7 A0 PTYLM REGISTER FORMAT SFFD00404 BITs 76543210 Byte RRRRRRRR Reset Value S04 BIT 7 0 Readonly Register for the parity error address evaluation LM Byte of the latched parity error address xxxxLMxx A15 A8 PTYUM REGISTER FORMAT BITs Byte Reset Value BIT 7 0 Readonly Register for the parit error address evaluat UM Byte error A23 A16 tched parit SxxUM
58. an interrupt request is triggered when the gate array internal parity checkers detect a parity error A pending interrupt is displayed in the parity error status register Bit 7 returns zero if the interrupt request is asserted The interrupt is cleared through a write cycle to the status register location 2 1 1 5 MAILBOXES A mailbox interrupt request is active when a read access to the mailbox location in the FGA 002 gate array is performed The mailbox interrupt is pending until a write access to the same mailbox location will clear the interrupt The read write accesses can be performed not only from VME side but also from the local processor For details please refer to the section entitled THE MATLBOXES INTERRUPT MANAGEMENT 2 1 2 External Interrupt Sources The FGA 002 gate array contains 18 interrupt request inputs to provide for external interrupt sources The inputs are assigned to the interrupt channels as shown in the following table Interrupt Source Interrupt Channel LOCAL INTERRUPTS LIRQO input pin LOCALO LIRQI input pin LOCALI LIRQ2 input pin LOCAL2 LIRQ3 input pin LOCAL3 LIRQ4 input pin LOCAL4 LIRQ5 input pin LOCALS LIRQ6 input pin LOCAL6 LIRQ7 input pin LOCAL7 UTILITY INTERRUPTS ABOKEY input pin ABORT ACFAIL input pin ACFAIL SFAILI input pin SYSFA
59. bit enables or disables the FMB Channel 0 for FMB cycles 1 Enabled 0 Disabled FORCE MESSAGE BROADCAST FMB 4 0 SLOTCODE The bit field is used to store the slot code which corresponds to the VMEbus slot number where the board is installed 4 0 Slot Number 01 1 02 2 03 2 04 4 05 5 S06 6 07 7 S08 8 S09 9 SOA 10 SOB 11 SOC 12 SOD 13 SOE 14 SOF 15 10 16 11 17 12 18 13 19 S14 20 15 21 6 3 2 FMB Area Register FMBAREA The FMBARFA register defines the address space of the FMB Area The area is selected from the 4 GByte total address space by a comparison of the VMEbus address signals A31 A24 with the register bits F31 F24 The area is addressed when the address signals match the register bit pattern FORCE MESSAGE BROADCAST FMB Format of FMBAREA 7 6 5 4 3 2 1 0 F31 F30 F29 F28 F27 F26 F25 F24 7 0 F31 F24 The bits define the FMB decoding area The register bits correspond to the VME address lines as follows Register Bit F31 F30 ae ae aa Te aif n F Address line A31 A30 A29 A28 A27 A26 A25 A24 6 3 3 Interrupt Control Register Channel0 Message ICRFMBOMES The ICRFMBOMES control register is used to configure the interrupt channel FMBO Message handling the channel 0 messag Format of
60. blank INTERRUPT MANAGEMENT TABLE OF CONTENTS GENERAL DESCRIPTION OPERATION DESCRIPTION 2 1 NN A W INTERRUPT REQUEST Interrupt Sources PAN Internal In EEES DMA CONTROLLER PEE A TIMER Be a a Mek Ge fe ely tet ee 2el Las FORCE MESSAGE BROADCAST FMB oA 2 ls 4 PARITY ERROR Ziadie 5 MATLBOXES X Del S72 External Interrupt Sources 2 die oc LOCAL INTERRUPTS Qh G22 UTILITY INTERRUPTS 2 Shee Zig Bs VME INTERRUPTS INTERRUPT ACKNOWLEDGE Bea EE pe od TA ORN Internal Vector Response ome a 2 2 2 Local I O Vector Response or Internal Vector Response Local TACK control register NARTA LOCALIACK GO dees an Sous is AE AE VMEbus Vector Response 2 2 4 EMPTY Vector Response Interrupt Priority Structure Interrupt Vector Page 2 4 1 Interrupt Vect 2 4 2 Register CTL3 Interrupt Registers 260 3 Register Map of 1 STATUS REGISTER or Page Programming INTERRUPT CONTROL and 202 The Interrupt Control Register 2 3 Dd Interrupt Status Register 1 2 1 2 1 2 2 2 3 2 3 2 3 2 4 2 4 2 5 2 6 2 6 2 2 8 2 8 2 10 2 12 2 12 2 13 2 14 2 15 2 18 2 18 2 19 2 19 2 20 2 24 INTERRUPT MANAGEMENT This page was intentionally left blank INTERRUPT MANAGEMENT I GENERAL DESCRIPTION The FGA 002 Gate Array provides high end support for interrupt functionali
61. board releases th In addition the gate which can be u ACFAIL handler board whic the VME input is detected low A board which is defined as 1 will not BUSCLEAR However it will LE sed to define a certain board ina sys dler bit designates a board ei VMEbus mastership ACFAIL Handler Option L input of the gate array is used for power fail L pin low generates an interrupt to the CPU array provides the ACFAIL handler option tem as the ther as the acfail privileged in gaining the bus or as a non privileged board which immediately if the powerfail h is bus the ACFAIL handler HANDLER bit t release the VMEbus mastership due to a request of another master or the assertion of busclear if the acfail inp the internal release the bus mastership after each transfer burst s Rel On ut is detected low DMA controller operates on the VMEbus as for the local processor finished the current The gate array will If the ACFAI L handler option is disabled and the power fail input is asser the VMEbus mastership HANDLER bit 0 the gate array releases ted mastership again for After reset The following table sh of an active acfail signal the ACFA the HANDLER bit immediately after the processor has cycle be prevented from requesting the VMEbus the local CPU or the DMA co
62. disable IRQ 1 to enable IRQ locirqx linum lflag llevel edge active clear llevel interrupt request level code edge 1 for edge sensitive IRQ 0 for level sensitive IRQ active 1 for active high 0 for active low clear 1 for disable autoclear 0 for enable autoclear handler address of the irq handling routine 4 4 4 Local IRQ Control Sets up local IRQ controls This routine also initializes the 680XX IRQ handler in the vector page It is a short form of the above described locirqx function NOTE May only be called in the SUPERVISOR mode int fga_util unsigned long locirgq unsigned long linum unsigned long lflag unsigned long llevel char handler 19 FORCE COMPUTERS locirq 11 linum 0 abort 1 acfail 2 sysfail 3 locald 4 locall 5 local 6 local3 7 local4 8 locald 9 local6 10 local Iflag 0 to disable IRQ 1 to enable IRQ llevel interrupt request level code handler address of the irq handling routine 4 4 5 Mailbox IRQ Control Sets up mailbox IRQ controls This routine also initializes the 680XX IRQ handler in the vector page NOTE May only be called in the SUPERVISOR mode int fga_util unsigned long mbxirq unsigned long minum unsigned long mflag unsigned long mlevel char handler mbxirq 13 minum Mailbox IRQ 0 7 mflag 0 to disable IRQ 1 to enable IRQ mlevel interrupt request level code handler address of the irq handling routi
63. i e combinated outputs on the WRITExXxDPR signals 0O Timing controlled WRITExxDPR signals 1 Asynchronous i e combinated output on the CPUDPRSEL signal O Timing controlled CPUDPRSEL signal 1 Word DSACK generated for the system EPROM area i e 16 bit wide EPROM is used 0 Long DSACK generated for the System EPROM area i e 32 bit wide EPROM is used 1 Fast VME Access disabled 0 Fast VME Access enabled New VME Address on DTACK AS to VME Timing ASV signal valid after 00 2 CPU clock cycles 01 1 5 CPU clock cycles 10 CPU clock cycles 11 0 5 CPU clock cycles LIOTIMING REG BITs 76543210 Byte XXXXXXXX Reset Value 00 BIT 7 6 LIOTIM 7 BIT 5 4 LIOTIM 5 BIT 3 2 LIOTIM 3 BIT 1 0 LIOTIM 1 STER FORMAT Access timing for the page 00 01 10 D SFFB Access Access Access Access X XXXX time 2 us time 1 us Access timing for the page 00 01 10 C SFFA Access Access Access Access X XXXX time 2 us time 1 us Access timing for the page 00 01 10 B SFF9 Access Access Access Access X XXXX time 2 us time 1 us Access timing for the page 00 01 10 A SFF8 Access Access Access Access X XXXX time 2 us time 1 us time 500ns time 250ns time 500ns time 250ns time 500ns time 250ns time 500ns tim
64. is 1 0 ABORT input is 0 D4 ACFAILPIN REGISTER FORMAT SFFD004D8 BITs 76543210 Byte Ree ao BIT 7 Read Only Location ACFAIL input pin level readback 1 ACFAIL input is high 0 ACFAIL input is low SFAILINPIN REGISTER FORMAT SFFDO04DC BITs 76543210 Byte Ree ao BIT 7 Read Only Location SYSFAIL input pin level readback 1 SYSFAIL input is high 0 SYSFAIL input is low ISFMBOMES REGISTER FORMAT SFFDO04E0 BITs 76543210 Byte SSS a gt Reset Value 80 BIT 7 ISFMBOMES Interrupt Status readback 1 FMBO message interrupt not pending 0 FMBO message interrupt pending ISFMB1IMES REGISTER FORMAT SFFDO04E4 BITs 76543210 Byte SSS a gt Reset Value 80 BIT 7 ISFMBIMES Interrupt Status readback 1 FMBI message interrupt not pending O FMB1 message interrupt pending DMASRCDST REGISTER FORMAT BITs 76543210 Byte R gt Reset Value 80 BIT 7 DMASRCDST SFFDOO4EC Read Only Location Mode readback of the DMA controller DMA operates in source mode DMA operates in destination mode RSVMECALL REGISTER FORMAT SFFDOO4F0 BITs 76543210 Byte RoS S gt Power Up Value 80 BIT 7 Read Only Location Reset Status of VME Reset call 1 VME Reset call was not activ O Reset was initiated by a VME Reset call
65. is active Therefore external decoding logic has to provide the decoding signal for the BOOT EPROM which is then asserted in the following cases see The decoding area of the BOOT EPROM is addressed FFEX XXXX 2 The output pin CSLIO is asserted and one of the CPU address lines A31 A23 is ina low state The boot information has to lead the program flow to the normal address range of the BOOT EPROM decoding area Then the first action should be to write a 1 to the BOOTFLAG bit Thereafter the decoding logic operates as described above For the processor the boot EPROM and boot SRAM are byte wid memory locations with a byte DSACK generated by the gate array THE CPU INTERFACE This page was intentionally left blank THE VME INTERFACE VME MASTER INTERFACE sL FEATURES Extended 432 Standard A24 and Short A16 addressing capability D32 Master D16 Master and D08 Master capability Unaligned cycles and Read Modify Write cycles supported Support for Unaligned Read Modify Write cycles Internal single level VMEbus arbiter module Automatic re arbitration Special ACFAIL handler option Fair VMEbus request option Various bus release options Release Voluntary RV Release On Request ROR Release On BUSCLEAR RBCLR Release On ACFAIL RACFAIL THE VME INTERFACE 2 2 Description The VMEbus interface of the gate array supports
66. is reset only with the VMEbus reset signal SYSRES which is monitored at the RESVI input pin MISCELLANEOUS 2 2 VMEbus RESET The gate array contains a VME reset generator which generates a VMEbus compatible reset signal The VME reset signal is driven on the RESVO output pin of the gate array Th reset generator is triggered by the following reset sources Power up input Reset key input CPU reset call Processor opcode reset if enabled 2 3 PROCESSOR RESET The processor is reset by the signal RESCPU generated by the gate array as an active low signal The processor will be reset if one of the following reset sources are active Power up input Reset key input Local switch input CPU reset call VME reset call SYSRESET from VME input MISCELLANEOUS 2 4 RESET SOURCES 2 4 1 Power up Input A power up reset is triggered when the PWUP input pin of the gate array is asserted low The input has to be driven by external logic when power is applied to the gate array The PWUP pin is typically driven by a voltage sensor which asserts the pin to low during the power up phase The gate array will be initialized completely Al 1 functions inside the gate array including the VME arbiter and the registers SPECIAL and SPECIALENA are reset The power up reset input triggers the VMEbus reset generator generating a VMEbus compatible reset s
67. message interrupt and a refused interrupt is available The message interrupt request is generated if one or more messages are received As long as the FIFO has a message stored the message interrupt is pending The message interrupt will be negated after the FIFO has been emptied The state of the FMB message interrupt is readable at the register ISFMBOMES for channel 0 and register ISFMBIMES for channel 1 A second interrupt source which is available for each FMB channel is the FMB refused interrupt request This interrupt becomes active if an FMB cycle is attempted and the addressed slave cannot accept the message because its FIFO is full The interrupt could be used by the slave CPU to count unsuccessful message cycles The FMB refused interrupt is cleared by writing the corresponding interrupt status register with any data The FMB interrupt channels can be configured to interrupt the cpu at any level If both message interrupts of are programmed to the same level higher interrupt priority is given to messages sent to FMB Channel 1 since the FMB1 message interrupt is ahead of the FMBO message interrupt in the daisy chain FORCE MESSAGE BROADCAST FMB This page was intentionally left blank FORCE MESSAGE BROADCAST FMB
68. source to destination the bus will be released and requested again for new mastership This guarantees that the DMA does not block any of the buses and The DMA controller does not have dynamical bus sizing in the sense of the 68020 68030 The program has to define the port of operation and is not subject to the decoding logic It is not possible to initiate a which crosses a port boundary in contiguous memory DMA transfer for a datablock A port boundary being the boundary between local memory and VMEbus memory and or secondary bus memory For example if a contiguous memory block contains local memory ranging from 0000 SIFFF and VME memory ranging from 2000 SFFFF it is not possible to transfer the block located at memory 1000 3000 to the desti task Such a transfer has to 3000 a valid transfer acknowledge DSACKO and DSACK1 are not distinguished nation address ina single be split into two tasks transferring the block of the local memory 1000 1FFF he other task for the transfer of the VMEbus block 2000 DMA one and and any assertion is When the DMA controller has finished its task successfully it generates the Normal termination interrupt command the Error termination interrupt is generated If the DMA operation is stopped due to a bus error or a stop THE 32 BIT DMA CONTROLLER
69. the present gate array and those not used are reserved for future extensions INTERRUPT MANAGEMENT The following groups of interrupt sources are supported aims Internal Interrupt Sources DMA CONTROLLER TIMER FORCE MESSAGE BROADCAST FMB PARITY ERROR 8 MAILBOXES 2s External Interrupt Sources Onboard interrupts LOCAL O 7 inpu ABORT Key inpu ACFAIL input SYSFAIL input S VMEbus interrupts 7 VMEbus interrupt inputs INTERRUPT MANAGEMENT 2 DESCRIPTION OF OPERATION 2 1 INTERRUPT REQUEST The FGA 002 Gate Array requests service from the interrupt channel recognizes the interrupt of ane source A pending interrupt from an interrupt source will processor when the xternal or internal be recognized when the IRQ enable bit in the interrupt control register is set to 1 An interrupt level greater than 0 has to be programmed in order that the gate array sends the interrupt request to the processor The gate array supports seven interrupt levels for service requests to the local CPU Each interrupt can be converted interrupt levels by programming the lower three bi to any of the seven ts of the interrupt control register which stores the interrupt request level code INTERRUPT MANAGEMENT 2 1 1 Internal Interrupt Sources The following table shows the FGA 002 Gate Array internal inter
70. the processor is and does not initialize bus arbiter will be initialized if the reset option bit is programmed to enable a VMEbus system In this case the bus arbiter is reset by the VMEbus signal SYSRESET which is monitored on the RESVI input of the gate array The reset option bit is available in the CTL9 register After reset the bit is cleared to 0 2 4 4 1 Register CTL9 Register Mnemonic Address R W Default Control 9 Register CTL9Y SFFDO0O27C R W 00 Format of CTL9 7 6 5 4 3 2 1 0 RESET 5 gt OPTION SEPROMDSACK 3 RESETOPTION The bit controls the generation of a VMEbus system reset when th processor executes the RESET opcode a enables generation of a VMEbus system reset 0 disables generation of a VMEbus system reset MISCELLANEOUS 2 4 5 CPU Reset Call A CPU reset call is triggered when the local processor addresses the gate array location SFFDOOEOO either in a read or a write cycle Data written to this location will be ignored The CPU reset call has the sam ffect as the key reset Accessing this location will reset th ntire gate array except the SPECIAL and SPECIALENA registers The VMEbus reset generator of the gate array will be triggered and drives the RESVO output low for a system reset Also the RESCPU output will go low to initialize the processor 2
71. to accept message data then it first checks whether or not another FMB slave has asserted BERR to abort the FMB transmission If BERR is sensed asserted in the time window as defined in Figure 2 2 then the cycle will not be executed and neither the DTACK output nor the BERR output will be asserted to the VMEbus Figure 2 2 Refused Cycle Timing Due to the Decision of Another Slave DSA input BERR input 4 lt gt 5 lt gt Table 2 2 Timing Parameters for a Refused Cycle Due to the Decision of Another Slave Parameter min ns max ns 4 170 5 350 S FORCE MESSAGE BROADCAST FMB 2 4 3 If a slave recognizes and is ready to accept the BERR input signal Accepted Message Cycle Timing that it is addressed as an FMB slave message data If BERR then it first observes is not asserted in the specified time widow t hen th and DTACK will the following table The minimum time befor several slaves respond to continuous releasing DTACK the message data will be fetched be asserted according to the timing given in guarantees that if same FMB cycle then a DTACK assertion will take place The master will be prevented from starting a new data cycle too early by the slaves holding Figure 2 3 DSA input DTACK asserted for a defined time Accepted Cycle
72. to the LOCAL when th ternal or external vector trol register is the access I O bus in an interrupt acknowledge cycle xternal response mode is needed The register is grouped into four bit fields where each field stores a 2 bit code of the LOCAL 4 7 interrupts to control the vec tor response mode of one Register Mnemonic Address R W Default Local IACK Control Reg LOCALIACK SFFD00334 R W 00 Format of LOCALIACK 7 6 4 3 2 dl O LOCAL7 LOCAL6 LOCALS LOCAL4 7 6 LOCAL7 This bit field controls the vector response mode of the gate array for the LOCAL 7 interrupt 5 4 LOCAL6 This bit field controls the vector response mode of the gate array for the LOCAL 6 interrupt channel 3 2 LOCAL5 This bit field controls the vector response mode of the gate array for the LOCAL 5 interrupt 1 0 LOCAL4 This bit field controls the vector response mode of the gate array for the LOCAL 4 interrupt INTERRUPT MANAGEMENT The 2 bit code stored in the LOCALIACK register for the control of the vector response mode of the LOCAL 4 7 interrupts has the following selections 00 10 The gate array answers with an internal vector The vector of the corresponding LOCAL interrupt is driven on the CPU data bus signals DCPU31 DCPU24 The corresponding LIACKx pin will be asserted
73. with 32 bit data bus FBFE FFFF FBFF XXXX VMEbus Short Address Range A16 D32 with 32 bit data bus FCXX XXXX FCOO 0000 VMEbus Standard Address Range A24 D16 A ye with 16 bit data bus FCFE FFFF FCFF XXXX VMEbus Short Address Range A16 D16 with 16 bit data bus FDXX XXXX FDOO 0000 SECONDARY bus Address Range A24 D32 S ES with 32 bit data bus FDFF FFFF FEXX XXXX FEOO 0000 SECONDARY bus Address Range A24 D16 Eurei Venen with 16 bit data bus FEFF FFFF THE CPU INTERFACE Table 1 1 cont d FFXX XXXX FFOO 0000 SYSTEM EPROM Area A23 D32 FF7F FFFF LOCAL I O Area A23 D08 FF80 0000 FF8X XXXX LOCAL I O Page A A20 D08 Der cris ee FF9X XXXX LOCAL I O Page B A20 D08 FFAX XXXX LOCAL I O Page C A20 D08 FFBX XXXX LOCAL I O Page D A20 D08 FFCX XXXX BOOT SRAM A20 D08 FFDX XXXX GATE ARRAY Registers A20 D08 or oy cans R FFEX XXXX BOOT EPROM A20 D08 PREP EEEE FFFX XXXX LOCAL I O Page E A20 D08 1 3 MAIN MEMORY 1 3 1 The MAIN MEMORY Decoding Registers The local MAIN MEMORY decoding is realized as software programmable decoding logic The decoding logic includes registers for the selection of the memory size and the local base address The registers can be programmed by the local cpu A set of two registers has to be programmed for the memory size as for the base address selection as well The local sided MA a single bit in th During the registers
74. 0 URMW VMETIMEOUT PEB PEA MAIN STERM 2550 MAINSTERM This bit field is used to select the STERM timing for an access to the local MAIN MEMORY 000 No STERM Generation 001 0 Waitstate STERM 010 1 Waitstate STERM 100 2 Waitstate STERM 1 10 THE CPU INTERFACE 1 4 VSB BUS SELECT An access to the VSB bus is indicated by the VSB select signal CSVSB This signal is low when the VSBbus is decoded A register bit in the CTL3 register nables the VSB bus selection If the bit VSBENA is set all accesses to the decoded VMEbus Extended Address Range will lead to a VSB bus access The VSB bus access will be refused and redirected to a VMEbus access when the gate array input pin NOVSB is asserted low 1 4 1 Register CTL3 Register Mnemonic Address R W Default Control 3 Register CTL3 SFFD00250 R W 00 Format of CTL3 Fi 6 5 4 3 2 1 0 VECTOR BIT 7 BIT 6 VSBENA OPT16 7 VSBENA This bit is used to control the VSB bus decoding 1 VSB bus decoding enabled O VSB bus decoding disabled 1 5 SECONDARY Bus D32 The address range FD00 0000 SFDFF FFFF is decoded for accesses to a Secondary bus with 32 bit data bus width A valid decoding of this area is indicated by the output signal CSVSB 1 6 SECONDARY Bus D16 The address range SFEOO 0000 SFFEF FFFF is decoded for accesses to a Seco
75. 2 Internal External Arbiter select the arbiter will negate its bus grant signal automatically and start a new arbitration cycle The FGA 002 gate array is equipped with an arbiter module which supports arbitration of the VME data transfer bus The internal arbiter function can be enabled disabled by a register bit inside the gate arr ARBI The bit named ay TER is contained in the CTL1 register and selects the internal arbiter function if it is set to 1 After reset the arbiter module is disabled and the bus mastership has to be controlled by an external arbiter 254251 Register CTL1 Register Mnemonic Address R W Default Control 1 Register CTL1 SFFD00238 R W 00 Format of CTL1 7 6 5 4 3 2 1 0 SUP USR ARBITER CSCO 2 ARBITER The bit selects the internal or external arbiter for VMEbus control 1 Internal arbiter is selected 0 External arbiter is selected 2 13 THE VME INTERFACE 2 6 VMEbus REQUEST The VMEbus will b requested by the gate array if the processor accesses a VME decoded address area or the DMA controller is programmed to transfer data on the VMEbus 2 6 1 VMEbus request on power fail detection The gate array provides a special bus request handling in case of a power fail detection on its ACFAIL input pin The handling depends on the state of the HANDLER
76. 21 80000000 80000000 84000000 88000000 8C000000 90000000 94000000 98000000 9C000000 A0000000 44000000 A8000000 AC000000 B0000000 B4000000 B8000000 BC000000 C0000000 C4000000 C8000000 CC000000 D0000000 FCFF8000 FCFF8000 FCFF8400 FCFF8800 FCFF8C00 FCFF9000 FCFF9400 FCFF9800 FCFF9C00 FCFFA000 FCFFA400 FCFFA800 FCFFACOO FCFFBO0O FCFFB400 FCFFB800 FCFFBCOO FCFFC000 FCFFC400 FCFFC800 FCFFCCOO FCFFDOOO Table 1 Slot Numbers VMEbus address FGA 002A Boot Software Version 4 2 1 2 FGA 002A registers Some FGA 002A registers can be altered However a few bits of FGA 002A registers should not be altered i e timings to ensure proper functionality of the board The debugger command SETUP takes care of that and does not allow to change these values 2 1 3 FC68165 registers The FC68165 has no base address after reset It must be programmed with one The first FC68165 in the chain is programmed to be at base address F EC00000 Every EAGLE module must have connected at chip select 0 of the FC68165 an Identification EPROM ID EPROM If this ID EPROM contains valid data the base address initialization will be continued according to this stored information In the ID EPROM is located how much FC68165 are on this EAGLE module Now every new FC68165 will be programmed that its base address is 200 higher than the previous one After the initiali
77. 4 6 VME Reset Call A reset call from VMEbus side resets the gate array without affecting the registers SPECIAL and SPECIALENA In addition the RESCPU output will be asserted to reset the local CPU and peripheral devices The reset call can be placed in the short decoding page of the gate array when the location SXXFF is addressed in a read or write cycle Please refer to the section VME AND CPU INTERFACE how to select the VME decoding page for accesses from the VMEbus to gate array functions The execution of the VME reset call has to be enabled by the bit VMERESCALL in the CTL2 register Writing this bit with 1 nables the VME reset call function If this bit is cleared the gate array does not respond to the reset call access from VME neither with DTACK nor by generating a bus error to the VMEbus MISCELLANEOUS 2 4 6 1 Register CTL2 Register Mnemonic Address R W Default Control 2 Register CTL2 SFFD0023C R W 00 Format of CTL2 7 6 4 3 1 0 VMERES a PTYOUT CALL CSDPR STBCTL 2 VMERESCALL The bit enables disables the VMEbus Reset Call function of the gate array 1 enables VMEbus reset call function O disables VMEbus reset call function 2 4 7 SYSRESET Signal From VME The RESVI input pin of the gate array is connected to the VMEbus signal SYSRESET Asserting th
78. 7 in the Interrupt status registers ISDMANORM and ISDMAERR is zero The interrupts can be cleared by writing the corresponding status register with any data 2 1 1 2 TIMER The timer triggers its interrupt request when the counter decrements from 01 to 00 A pending interrupt request is displayed as a low in bit 7 of the timer interrupt status register Writing the timer interrupt status register clears the interrupt The written data will be ignored After reset the timer interrupt is cleared 2 1 1 3 FORCE MESSAGE BROADCAST FMB The gate array contains two FMB message channels to receive messages from the VMEbus Each FMB message channel can genera and the refused interrupt request the message interrupt request cr CT The message interrupt request is pending as long as there are messages contained in the message fifo After the last message has been read by the local CPU the message interrupt request disappears An active message interrupt request is displayed in the interrupt status register bit 7 The bit is low if the interrupt is asserted INTERRUPT MANAGEMENT The refused interrupt request is edge triggered and can be cleared by a write cycle to the corresponding interrupt status register The status register displays 1 at bit 7 if the refused interrupt is pending 2 1 1 4 PARITY ERROR If one of the parity error options is enabled
79. CPU31 tor to be presented at the After being read in the upt acknowledge cycle with DCPU29 To complete the 8 bit vector information provided by the CTL3 register and are driven on the DCPU30 pins the two Interrupt Vector Page are DCPU31 INTERRUPT MANAGEMENT The gate array supports interrupt acknowledge cycles with the internal vector number when th following interrupt channels are decoded INTERRUPT CHANNEL VECTOR NUMBER Mailbox 0 00 Mailbox 1 S01 Mailbox 2 02 Mailbox 3 03 Mailbox 4 04 Mailbox 5 05 Mailbox 6 06 Mailbox 7 07 Timer 20 FMB1 Refused 24 FMBO Refused 25 FMB1 Message 26 FMBO Message 27 ABORT 28 ACFAIL 29 SYSFAIL S2A DMA Error 2B DMA Normal S2C PARITY Error S2D LOCALO 30 LOCAL1 31 LOCAL2 32 LOCAL3 33 Empty Interrupt S3F INTERRUPT MANAGEMENT 2 2 2 Local I O Vector Response or Internal Vector Response The LOCAL4 LOCAL7 interrupts are supported by three different modes of response to an interrupt acknowledge cycle of the processor The modes are 1 Response with Internal Vector Number 2 Response with External Interrupt Vector 3 No response The modes are selected in the control register LOCALIACK The register also controls the timing of the access on the LOCAL I O bus which fetches the vector from the interrupting device The contents of
80. DS1 DS0 WRITE DTACK RWVME DTACK BERR DTACK BERRV Bus arbitration signals BRx BRVMEO BRVME BGxIN BGVME I BGxXOUT BGVMEO BBSY BBSYO BBSY BCLR BCLRI Interrupt signals IRO Fyell VIRO Terl Utility signals SYSRESET RESVO RESVI ACFAIL ACFAIL SYSFAIL SFAILO SFAIL There is a decoding range defined for accesses from the VMEbus to the local main memory The FGA 002 gate array decodes all address and address modifier signals The address range for the main memory is software programmable with the lowest boundary at 4 KByte Several Address Modifier Codes are selectable for a valid memory decoding It is selectable if the decoding is valid for Read only or Read and Write cycles This allows on board memory to be protected from being overwritten by VMEbus accesses The gate array includes slot 1 functions such as the Single Level Arbiter and the SYSRESET generator Several release options for the VMEbus are provided Timing and enable of the bus release options are software selectable The following bus release functions can be selected Release on request ROR Release on Bus Clear RBCLR Release voluntary RV Release on ACFAIL RACFAIL INTRODUCTION Bs The Interrupt Management The FGA002 includes several internal interrupt sources which are fully under software control Additionally 11 interrupt inputs are provided for utility interrupts and those from local I O d
81. FD00218 VIRO5 ICRVME 5 SFFD00214 VIRQ4 ICRVME 4 SFFD00210 VIRQ3 ICRVME3 SFFDO020C E VIRQ2 ICRVME2 SFFD00208 VIRQ1 ICRVME1 SFFD00204 INTERRUPT MANAGEMENT 2 5 2 The Interrupt Control Register There are two different types of interrupt control registers implemented in the FGA 002 gate array 1 Standard Interrupt control registers 2 Extended interrupt control registers Both types of the interrupt channels of the corresponding interrupt source Interrupt Control registers are used to configure They provide selection of the interrupt level generation and enable disable control Extended Interrupt Control Registers have additional bits to select characteristics of the corresponding interrupt input Extended interrupt control registers are used to control the ABORT ACFAIL and SYSFAIL interrupts All other interrupt channels of i the LOCAL interrupts as well as the gate array are configured by standard interrupt control registers The followin to the corresponding interrupts in detail INTERRUPT CONTROL REGISTERS STANDARD EXTENDED Mailbox 0 LOCALO Mailbox 1 LOCAL1 Mailbox 2 LOCAL2 Mailbox 3 LOCAL3 Mailbox 4 LOCAL4 Mailbox 5 LOCALS Mailbox 6 LOCAL6 Mailbox 7 LOCAL7 Timer ABORT FMB1 Refuse ACFAIL FMBO Refused SYSFAIL FMB1 Message FMBO Message DMA Error DMA Normal
82. GISTER FORMAT SFFDO02C4 BITs 76543210 Byte XXXXXXXX Reset Value 00 BIT 7 MATINENA MAIN Memory Decoding from CPU side 1 enabled 0 disabled BIT 6 4 MATNDSACK MAIN Memory DSACK timing 000 no DSACK Generation 001 O Waitstate DSACK 010 1 Waitstate DSACK 100 2 Waitstate DSACK BIT 3 0 MS 27 24 MAIN Memory Size selection The bitfield has to be programmed according to the following table 0000 256 MByte 1000 128 MByte 1100 64 MByte 110 32 MByte 1 16 MByte 8 MByte 4 MByte 2 MByte 1 MByte 512 KByte 256 KByte 128 KByte 64 KByte MAINUM REGISTER FORMAT BITs 76543210 Byte XXXXXXXX Reset Value 00 BIT 7 0 B 23 16 SFFD002C8 Upper Middle address byte of the MAIN MEMORY Base address SxxBBxxxx The decoding is valid when the VME Address lines A23 A16 match the value of the corresponding bits B23 B16 MAINUU REGISTER FORMAT BITs 76543210 Byte XXXXXXXX Reset Value 00 BIT 7 0 B 31 24 SFFDO02CC Upper Upper address byte of the MAIN MEMORY Base address SBBXxxXxXxXX The decoding is valid when the VME Address lines A31 A24 match the value of the corresponding bits B31 B24 BOTTOMPAGEU REGISTER FORMAT SFFD002D0 BITs 76543210 Byte XXXXXXXX Reset Value 00 BIT 7 0 B 27 20
83. IL VME INTERRUPTS VIRQ7 input pin VIRQ7 VIRQ6 input pin VIRQ6 VIRQ5 input pin VIRQ5 VIRQ4 input pin VIRQ4 VIRQ3 input pin VIRQ3 VIRQ2 input pin VIRQ2 VIRQ1 input pin VIRQ1 INTERRUPT MANAGEMENT 2 1 2 1 LOCAL INTERRUPTS The LOCAL 0 7 interrupt inputs may be configured to be high or low tive and edge or level sensitive The configuration is to be lected in the corresponding Extended Interrupt Control Register ac se Edge sensitive configured LOCAL interrupt inputs trigger an interrupt the active edge of the input signal Active low on in in puts trigger the interrupt on the high puts on the low to high edge to low edge and ac tive high A pending interrupt request of a LOCAL interrupt input is readable on th Re st Th is Th ei or ac en Th th 2 Th respective status register location ading bit 7 of the interrupt status register returns the active ate of the interrupt request e bit is low if the interrupt is pending and high when no interrupt pending independent of the selected input activity e interrupt of edge sensitive configured inputs can be cleared ther with a write access to the interrupt status register location automatically when the processor executes the interrupt knowledge cycle For this mode the autoclear option has to be abled in the extended interrupt control register e clear operation of the inter
84. ISTER FORMAT SFFDOOCO0O0 BITs 76543210 Byte ET a Er Reset Value SFF BIT 7 0 TIMOCOUNT Read Access Counter State of TIMERO Write Access Loads the contents of the TIMOPRELOAD register into the TIMERO SOFTRESCALL SFFDOOEOO A read or write access to this location will reset the FGA 002 Gate Array The registers SPECIAL and SPECIALENA registers will not be reset MBOXx REGISTER FORMAT MBOXO SFFD80000 MBOX1 SFFD80004 MBOX2 SFFD80008 MBOX3 SFFD8000C MBOX4 SFFD80010 MBOXS SF FD80014 MBOX6 SFFD80018 MBOX7 SFFD8001C BITs 76543210 Byte Ons S aoe Reset Value 00 BIT 7 MBOXx Read Access 1 is returned if the Mailbox is already occupied The mailbox interrupt is pending 0 is returned if a released Mailbox could be occupied successfully The mailbox interrupt will be triggered Write Access Releases the Mailbox and clears the Mailbox interrupt FMBCHO REGISTER FORMAT SFFDC0000 BITs 31 7 0 Long RRRRRRRR BIT 7 0 FMBCHO Read Only Location Local Readout for the Message received in the Force Message Broadcast Channel 0 FMBCH1 REGISTER FORMAT SFFDC0004 BITs Sil 7 0 Long RRRRRRRR BIT 7 0 FMBCH1 7 0 Read Only Location Local Readout for the Message received in the Force Message Broadcast Channel 1 FGA 002A Boot Software User s Manual Revision 2 July 1992 FORCE C
85. L 7 SFATLO cleared on cleared on signal any reset powerup reset level 0 0 1 X X don t care 4 2 1 1 Register CTL8 Register Mnemonic Address R W Default Control 8 Register CTL8 SFFD00278 R W 00 Format of CTL8 7 6 5 4 3 2 0 x z x e BSYSBIT SSYSBIT FAIR HANDLER 3 BSYSBIT Depending on the contents of the SPECIAL 7 register bit the bit determines the level of the SFAILO signal The bit is cleared when the gate array is reset 1 SFAILO signal is tristated 0 SFAILO signal is driven low 4 3 MISCELLANEOUS 4 2 1 2 Register SPECIAL Register Mnemonic Address R W Default Special Register SPECIAL SFFD00420 R W 00 Format of SPECIAL A 6 5 4 3 2 1 0 SPECIAL 7 7 SPECIAL 7 This bit cleared enables the BSYSBIT When set this bit overrides the BSYSBIT bit and negates the SFAILO signal 1 Negates the SFAILO signal 0 Enables the function of the BSYSBIT in the CTL8 register MISCELLANEOUS 4 2 2 Softsysfail Bit SSYSBIT An additional source for the generation of the SYSFAIL signal by the gate array is the bit named SSYSBIT contained in the CTL8 register By default the register is cleared and the SSYSBIT will not originate a sysfail signal When the bit is set the SFAILO signal will be driven low 4 2 2 1 Register CTL8 Register Mnemonic Address R W Default C
86. LI 0031 1 00 FGA 002A register ICRLOCAL2 0032 1 00 FGA 002A register ICRLOCAL3 0033 1 00 FGA 002A register ICRLOCAL4 0034 1 00 FGA 002A register ICRLOCALS 0035 1 00 FGA 002A register ICRLOCALG6 0036 1 00 FGA 002A register ICRLOCAL7 0037 1 33 FGA 002A register VMEDPRENA 0038 1 00 FGA 002A register MAINUM 0039 1 00 FGA 002A register MAINUU 003F 1 61 FGA 002A register FMBCTL 0040 1 FA FGA 002A register FMBPAGE 0800 1 Reset condition Every bit of this byte represents a reset condition bit 0 power on reset bit 1 VME reset call bit 2 local key reset bit 3 soft reset call bit 4 reset key bit 5 VME system reset bit 6 reserved bit 7 reserved 0810 2 CPU type binary coded 0812 2 Memory size 0 256 kByte FORCE COMPUTERS Offset Byte Default Description 1 512 kByte 2 1 MByte 3 2 MByte 4 4 MByte 5 8 MByte 6 16 MByte 7 32 MByte 0814 2 Processor speed binary coded 0820 1 Rotary Switch 0825 1 Number of FC68165 0826 4 Address of first FC68165 1F00 256 Free All not listed offsets are internally used reserved for future use FGA 002A Boot Software Version 4 3 Debugger The FGA 002A Boot Software normally is fully transparent This means that it executes silently How ever sometimes it is necessary to change initialization values and as everybody agree this should be possible in a conveni
87. Lm RSE FORCE GATE ARRAY FGA 002 User s Manual Edition No 6 November 1996 P N 201559 FORCE COMPUTERS Inc GmbH All Rights Reserved This document shall not be duplicated nor its contents used for any purpose unless express permission has been granted Copyright by FORCE COMPUTERS Introduction CPU and VME Interface Interrupt Management INDEX The 32 Bit DMA Controller Force Message Broadcast FMB The Mailboxes The Timer Miscellaneous Register Format Short Boot Software Description User Notes Product Error Report As to Title Page s separate File Title man CAUTION The FGA 002 gate array contains registers which are used to configure the gate array for special external hardware requirements These registers are reserved and will be setup by the boot software according to the hardware environment in which the gate array is implemented These registers must not be changed by the user Some of these hardware configuration registers also contain user selectable bits Programming the contents of thes registers has to be done carefully without changing the bits initialized by the boot software Registers not described must not be programmed Unqualified changes of register bits may have unpredictable consequences for the gate array and external hardware It is expressly forbidden to change register bits except those defined for t
88. NIT Description Initialize FC68165s 11 FORCE COMPUTERS FC68165INIT initializes the FC68165s according to the content of the ID EPROMs This includes the timings for every device connected to the FC68165 3 2 9 HELP Syntax HELP Description Display help text The HELP command displays a help text which shows all available commands 3 2 10 INIT Syntax INIT Description Initialize board INIT initialize the complete board according to the SRAM contents INIT includes the command FC68165INIT Therefore FC68165INIT need not be run seperately 3 2 11 M Syntax M lt address gt B WIL amp N EIF Description Memory Modify The Memory Modify command is used to inspect and change memory locations Several options are allowed on the command line to specify the size of the memory and the access type The following options are allowed memory is byte sized 8 bits memory is word sized 16 bits This is the default memory is long word sized 32 bits memory is byte sized and on odd addresses only memory is byte sized and on even addresses only memory is write only the current contents is not displayed F set the function code lines of the processor to the value directly followed the F These function codes are only driven for the memory access Shor w The O and E options are overriding the B W L options All memory accesses check that the write access was successful by performing a read after the writ
89. NTSRCENA BIT 6 CNTDSTENA BIT 5 2 BIT 1 FORCEZERO BIT 0 DMAENABLE l count 0 a count 0 up reserved must be written 0 the DMA Forces disgorge any data ETEO Example source port for a where it the be programmed count 1k started and then to find out whe finished forcezerocount so the bytes output The transfer count SFFD00328 Source Address does not Source Address counts up Destination Address does not Destination Address counts source FIFO to still in If the AUX is with the The transfer n the tran Then DMA transfe is not known how man bytes are to be transferred the t register woul maximu th th i th QaQ3IK KOO m S the SW must poll sfer i S e bit should be set in the FIFO terminated normally T DMA Controller is enabled DMA Controller is under reset ar e DMA transfer is then CTL12 REGISTER FORMAT BITs 76543210 Byte XXXXXXXX Reset Value 00 BIT 7 RECENA BIT 6 STERMDRV BIT 5 ASYNCWRDPR BIT 4 ASYNCCPUDPR BIT 3 USEREPROM16 BIT 2 DMAFASTVME BIT 1 0 ASDMATOVME 1 0 SFFD0032C 1 Release Every Cycle enabled O Release Every Cycle disabled Enable STERM and CBACK O Disable STERM and CBACK Asynchronous
90. OMPUTERS Inc GmbH All Rights Reserved This document shall not be duplicated nor its contents used for any purpose unless express permission has been granted Copyright by FORCE COMPUTERS FGA 002A Boot Software Version 4 FORCE COMPUTERS GmbH FGA 002A Boot Software Version 4 Contents 1 Overview 3 2 Initialization 3 2 1 Changing the SRAM default 2 0 00000 00 00 00 0000 0000 00000 3 2 1 1 Slotnumber 2 0 20 00 a 3 2 1 2 FGA O02A registers 2 aaa a 5 2 1 3 FC68165 registers 2 a 5 2 2 SRAM Layout 20 20 2 0 200200000 2 ee 5 3 Debugger 9 3 1 How to start 2 0 0 0 9 3 2 Commands 2 2 2 2 0 0002 9 BIA E 9 3 2 2 BF aaa a 9 3 23 BM 0 020 0000 2 10 324 Bs 0 0 00 000 00 2 a 10 3 2 5 BT 0 200 0 00 00 a 10 3 26 BV 2 a 11 3 2 7 EXIT eaaa 11 3 2 8 FC68165INIT 2 2 20 a 11 3 2 9 HELP 0 0 0 000000 a 12 3 2 10 INIT 2 a 12 3 2 11 M 2 a 12 3 2 12 MD 2 13 3 2 18 PROG 2 2 2 a 13 3 2 14 SELFTEST 200200 a 14 3 2 15 SETUP 0202000020020 00 00 2 14 3 2 16 USER 2 0 0 000020 00 02 14 4 System Calls 15 4 1 AUX Dependent Functions 0 0 20 200 00 00 2 ee 15 4 1 1 AUX Pin Control 2 0 0 00 0 00 e 15 4 1 2 AUX Source Cycle Control 2 0 0 00200 000000002 ee 15 4 1 3 AUX Destination Cycle Control 2 0 00 0000200000 0000008 16 4 2 DMA Channel Dependent Functions
91. OX6 SFFDO0018 R W 00 Int Ctl Mailbox7 ICRMBOX7 SFFDOOOIC R W 00 351 THE MAILBOXES 3 3 3 3 1 The Format of Register Description Interrupt Control Register _ICRMBOX 0 7 ICRMBOX 0 7 ICRMBOX 0 7 control registers are used to configure the interrupt channels for interrupts initiated by mailboxes 0 7 7 6 5 4 3 1 IRQ 3 x z Enable IRQ Leve 3 IRQ Enable The bit enables or disables the interrupt channel 1 Interrupt channel is enabled O Interrupt channel is disabled 2 0 IRQ Level This bit field defines the interrupt request level 2230 0 Interrupt Level 000 Interrupt disabled 001 Level 1 010 Level 2 011 Level 3 100 Level 4 101 Level 5 110 Level 6 1 Level 7 THE MAILBOXES 4 DESCRIPTION OF OPERATION 4 1 Mailbox Operation The Mailboxes of the FGA 002 gate array are readable and writable address locations Each Mailbox is capable of storing a Single bit of data The special feature of a Mailbox is that data will be stored not only in a write cycle but also when accessing the Mailbox location with a read cycle A read access to this location will internally be executed as a read and write operation There is no difference in the function of the Mailboxes whether they are accessed from the VME side or from th
92. PARITY Error VMEbus IRQ7 VMEbus IRQ6 VMEbus IRQ5 VMEbus IRQ4 VMEbus IRQ3 VMEbus IRQ2 VMEbus IRQ1 g chart shows the assignment of control registers INTERRUPT MANAGEMENT The standard interrupt control registers contain four register bits while th xtended interrupt control registers contain seven control bits Unused register bits have to be programmed to zero Both register types have in common the control function of the lower four register bits These bits configure th channel The bits 2 0 store th which level servic disables th interrupt level code and determine on Bits 6 4 of the extended interrupt control registers configure the interrupt inpu select the sources and autoclear opt disables the autoclear option while bit of the interrupt input to be high low aci if the IRQ input is edge or level sensitive Bit 4 is requested from the CPU Bit 3 enables or interrupt channel t provided for external interrupt enables 5 selects the activity Bit 6 determines All interrupt control registers of the FGA 002 Gate Array are initialized to 00 after reset Format of Standard Interrupt Control Register IRQ Enable Interrrupt Level Select Format of Extended Interrupt Control Register 7 6 5 4 3 1 0 Edge Acti Auto IRQ
93. Parms 35 parmsptr pointer to the a structure MODULE INITPARMS The structure is filled with 2 sets of initialization values The first is for module 1 while the second is for module 2 Each set consists of 3 entries the ID EPROM base an I O base address and an application memory address 24 FGA 002A Boot Software Version 4 5 Software Structure 5 1 Layout FFE00000 SP FFE00004 PC FFE00008 Utility Pointer FFE0000C Pointer to Address for a User Program FFEO0010 Firmware Start Address FFEO0014 Boot Code User Program FFEOFFFF Figure 1 EPROM Usage The user program pointer points to the end of the boot software At this point any program can be put The boot software jumps to this code after initializing the board The code must be finished with a RTS instruction Per default only a RTS instruction is included 5 2 Structure Start Simulate PDOS Environment Store Reset Condition Turn boot decoding off Get CPU type Calculate processor speed Get Rotary Switch Initialize serial communication Preinitialize FC68165s Abort Switch pressed Yes Rotary Switch lower than 22 Yes Set new slot number Stop No Start debugger Final initialization of the FC68165s Initialize FGA 002A Initialize DRAM Start User Program End Figure 2 Flow Chart 25 FORCE COMPUTERS 5 3 Starting Firmware Afte
94. S ERROR GENERATION 1 1 BUS ERROR GENERATION TO VME al FMB bus error 3 52 Bus error on par bey error detection ce VME timeout bus error 1 2 BUS ERROR GENERATION FOR THE CPU AND DMA CONTROLLER a ee a ee E hes 2 sch Onboard timeout Bus error pe e VSB SECONDARY timeout bus error wl Ze Register CTLI5 Taara Bus error on parity error detection 2 4 VMEbus timeout bus error 2 4 Register CTL16 2st Unaligned RMW cycle to VME 2 6 LONG timeout 2 RESET FUNCTION 2 1 GATE ARRAY RESET 2 2 VMEbus RESET 2 2 3 PROCESSOR RESET 2 4 RESET SOURCES er 2 4 1 Power up Input 2 4 2 Reset Key Input 2 4 3 Local Switch Reset 2 4 4 Processor Opcode Reset 2 4 4 1 Register CTL9 2 4 5 CPU Reset Cal 2 4 6 VME Reset Cal oo ig x 2 4 6 Register CTL2 2 4 7 SYSRESET Signal From VME 2 5 RESET SOURCE READOUT LOCATIONS 3 ACFAIL Handler Option 3 1 Register CTL8 4 SYSFAIL 2 43 4 1 SYSFAIL Input rA alan 4 ra 4 1 1 Register SFAILINPIN 4 2 SYSFAIL Output hs ie ete te a 4 2 1 Bootsysfail Bit BSYSBIT Aad ded Register CTL8 4 2 1 2 Register SPECIAL 4 2 2 Softsysfail Bit SSYSBIT 4 2 2 1 Register CTL8 Beis Watchdog Sysfail Pali i iia aa HAUDHDUUOAPBPWWWWNHNE ET NNMNNNNNNNNNNNNDN NY MISCELLANEOUS TABLE OF CONTENTS cont d LOCAL SWITCH Input PARITY SUPPORT 6
95. Selection for the decoding interval of the local MAIN memory from VMEbus side Upper portion of the Bottom Page base address SxBBxxxxx For a valid decoding the VME Address lines A27 A20 must match the value of the corresponding bits B27 B20 BOTTOMPAGEL REGISTER FORMAT SFFD002D4 BITs 76543210 Byte XXXXXXXX Reset Value 00 BIT 7 0 B 19 12 Selection for the decoding interval of the local MAIN memory from VMEbus side Lower portion of the Bottom Page base address SxxxBBxxx For a valid decoding the VME Address lines A19 A12 must match the value of the corresponding bits B19 B12 TOPPAGEU REGISTER FORMAT SFFD002D8 BITs 76543210 Byte XXXXXXXX Reset Value 00 BIT 7 0 EL27 22 20 Selection for the decoding interval of the local MAIN memory from VMEbus side Upper portion of the Top Page base address SxTTXxxxx For a valid decoding the VME Address lines A27 A20 must match the value of the corresponding bits T27 T20 TOPPAGEL REGISTER FORMAT SFFDO02DC BITs 76543210 Byte XXXXXXXX Reset Value 00 BIT 7 0 TPs 22 Selection for the decoding interval of the local MAIN memory from VMEbus side Lower portion of the Top Page base address SxxxTTxxx For a valid decoding the VME Address lines A19 A12 must match the value of the corresponding bits T19 T12 MYVMEPAGE REGISTER FORMAT SFFDOO2FC
96. T FMB REGISTERS FMB FMB Regis Regis OV OV OV 1 2 3 FMB 6 6 6 6 Regis 31 BZ 3 63 3 4 Ger Organization ter Address Assignment ter FMB Con Interru Message Interru Refused Interru Message Imcerru Refused Interru Message Interru Refused Interru Message Interru Refused Message FMBCHO Message FMBCH1 Description trol Register FMBCTL FMB Area Register FMBAREA pt Control Register Chan ICRFMBOMES ioe bok pt Control Register Chan ICRFMBOREF sT ar 5 pt Control Register Chan ICRFMB1MES te ey SB pt Control Register Chan ICRFMB1IREF Be tetas pt Status Register Chann ISFMBOMES ae 4 ea pt Status Register Chann ISFMBOREF Bo ees ate ge pt Status Register Chan ISFMB1MES lt lt E aT Bes pt Status Register Chann ISFMB1REF OMe Cec an Ye Readout Register Channel Readout Register Channel nel ell bh NN ee al NMNNMNNMNNNNNN Lb NOR BWNHNDN ND FORCE MESSAGE BROADCAST FMB Figure 2 1 Figure 2 2 Figure 2 3 LIST OF FIGURES Refused Cyc Refused Cyc le Timing le Timing Another Slave Accepted Cycle Timing Timing Paramet Own Decision Timing Paramet the Decision Timing Paramet Due Due to Own to the LIST OF TABLES ters for a Refused ters for a Refused of Another S
97. This feature is available if the gate array is configured for the shared memory structure defined in the SPECIAL register and any option for parity error support by the gate array enabled is THE VME INTERFACE 3 3 1 RMW Cycles from VME to the MAIN Memory When the gate array is initialized to support the Shared memory structur selected in the SPECIAL register bit 5 read modify write cycles from VME can be performed only if the SHAREDRMW bit enables this type of access In this mode the local bus is kept for the VME master until the RMW operation is finished With the SHAREDRMW option disabled a correct RMW operation cannot be guaranteed since the local bus will always be released for the processor between two consecutive accesses from VME to the main memory Note If this option is enabled not only read modify write cycles from VME to the shared main memory but also standard cycles cause the gate array to keep the local bus mastership for the VME master until the VME address strobe is negated to finish the cycle This will reduce performance of the local processor 3 3 1 1 Register CTL15 Register Mnemonic Address R W Default Control 15 Register CELLS SFFD00358 R W 00 Format of CTL15 7 6 5 4 3 2 1 0 VSBSEC BURST BURST CINH CINH16 CINH SHARED TIMEOUT TRANS CYCLE OFFBRD LIO RMW 0
98. To terminate access cycles to the MAI termination termination modes indicate to the processor a long word port size The timing of these signals is controlled by the CTL11 and the CTL16 registers or the DSACKx initialization of the MAI signal can IN MEMORY the decoding should be disabled by this bit N MEMORY the STERM signal be selected IN MEMORY decoding can be enabled disabled by e register CTL11 decoding Both THE CPU INTERFACE The first registers and the corresponding bits the local of the following tables gives an overview of the which are used to select sided decoding area and the cycle termination mode for MAIN MEMORY accesses The second table shows the address assignment for these registers Table 1 2 MAIN MEMORY control overview REGISTER CTLLL CTL10 MATNUU MATNUM CTL16 Bits Bits Bits Bits Bits SIZE 3210 76543210 BASE 76543210 76543210 ENABLE 7 DSACK 654 STERM 210 Table 1 3 Address assignment of the local MAIN MEMORY control registers Register Mnemonic Address R W Default Control Register 10 CTL10 FFD002C0 R W 00 Control Register 1 CTL111 FFD002C4 R W S00 Base Address Reg UM MAINUM SFFDO002C8 R W 00 Base Address Reg UU MAINUU SFFDO02CC R W 00 Control Register 16 CTL16 FFD0035C R W 00 THE CPU INTERFACE 1 3 2 The MAIN
99. W input provided for the connection of the local switch is asserted lo The active following s a Boot b Soft s WATC W low SFAILO signal may be driven ources sysfail bit BSYSBIT sysfail bit SSYSBIT HDOG SYSFAIL of the timer 4 2 1 Bootsysfail Bit BSYSBIT by any of the The bootsysfail bit is included in the control register CTL8 as bit 3 The bit is readable and can be modified by writing the control register Any reset operation which r array will When the bi clear the bit to 0 t is cleared it will drive the SFAI esets the gate LO signal low The bootsysfail bit is qualified to drive the SFAILO signal low if the SPEC this AL 7 bit contained in the SPECIAL r gister enables MISCELLANEOUS The SPEC with this default value by the BSYSBIT everytime Writing the SPECIAL 7 function AL 7 device reset bit with the sysfail signal will the gate array is reset 1 overrides the This inhibits the generation of sysfail after every register bit is cleared after power up reset and be generated BSYSBIT The following table displays the function of the sysfail bit and the SPECIAL 7 bit BSYSBI SPECIA
100. XXXX PTYUU REGISTER FORMAT BITs 76543210 Byte RRRRRRRR Reset Value SFF BIT 7 0 SFFDO040C Readonly Register for the parity error address evaluation UU Byte of the latched parity error address A31 A24 47 SUUXXXXXX PTYATT REGISTER FORMAT l BITs Byte 76543210 RRRRRRRR Reset Value BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 0 Dependent on access conditions SFFD00410 Readonly Register of parity error att N U a Se FC2 FC1 FCO State of nact v nact v inactiv tributes Local RAM accessed from VME Local RAM accessed by DMA RAM Access was RMC operation pin sta tus information pin sta tus information pin sta SZ1 and SZO 0 01 10 0 transfer size pins tus information 4 byte transfer size 1 byte transfer size 2 byte transfer size 3 byte transfer size IDENT REGISTER FORMAT BITs 76543210 Byte CEE REEL BIT 7 4 BIT 3 0 SFE Readonly Register location FGA 002 revision number FGA 002 ident number DOO41C SPECIAL REGISTER FORMAT SFFD00420 BITs 76543210 Byte XXXX Reset Value after power up 00 BIT 7 SPECIAL 7 1 Overrides the BSYSBIT and releases the SFAILO sig
101. able in the register MYVMEPAGE The Address Modifier Code selection is to be made in the CTL5 register The bitfield MYAMCODE selects the valid VME Address Modifier Code or disables the page decoding The function of the mailboxes together with their access addresses is described in the section MAILBOXES A description of the RESET call together with its location can be found in the section MISCELLANEOUS THE VME INTERFACE For the status readout of is provided the SFAILO output signal and the HALT signal the address location SXXFD The status of the SFAI data bit 6 and the HALT signal at data bit 5 is driven by the 68020 processor to processing Therefore th when the 68020 processor is implement 68030 processor does not have a HALT HALT signal can onl ted as the local CPU output signal LO signal indicate has to be taken on the other data bits 3 4 1 The register MYVMEPAGE SUU This register holds the VMEbus address lines of a short address VME page selection is displayed at The HALT signal that it stopped ly be evaluated the No care is used to select the VME page in which the gate array can be accessed from VME side A valid decoding page can be selected by writing the upper byte SUUXX the bits Y15 Y08 A15 A08 into the 8 bit register which are compared with The decoding is va
102. anagement provides a software controllable method of prioritization for the interrupts using programmable interrupt levels Seven different interrupt levels are supported by the interrupt management Highest priority is given to level 7 and lowest priority to level 1 ct ct Each level is coded so that the interrupt priority level Signals IPL2 IPLO of the 68020 68030 processor can be directly connected to the FGA 002 Gate Array If the interrupt request level is programmed to zero no interrupt will be sent to the processor This is similar to the interrupt being disabled by clearing the enable bit in th corresponding interrupt control register 0 A second kind of prioritization is hardware defined inside the gate array and is designated as the interrupt daisy chain The interrupt daisy chain structure defines the order in which n g interrupts on the same level will be serviced The daisy chai operates such that interrupt priority decreases with ascendin vector numbers The main priority is always determined by the interrupt level This means that prioritization according to the interrupt daisy chain is only given for interrupt sources which are programmed on the same interrupt level Therefore an interrupt source programmed to interrupt level 6 always has priority over a level 5 interrupt although its channel may be after the other c
103. at and does not allow to change these values Additionally the SETUP command is interactive and therefore easy to use e Direct You can directly change the SRAM content with the debugger You have to execute the INIT command after you have finished your changes to validate the new values 2 1 1 Slot number The VMEbus has no real slot numbering Because of that this number is only a logical number In fact it defines the VMEbus base address of the board according to Table 1 2 ways are possible to set the slot number e Using the SETUP command of the Debugger This is the easiest way if you have a terminal Simply invoke the SETUP command and change the slot number Afterwards execute an INIT command and all is done e Changing the Rotary Switches Change the rotary switches to the slot number you want to adjust Press the Abort Switch together with the Reset Switch as you do if you start the debugger The new slot number will be set and the system is halted until you press the Reset Switch again without the Abort Switch Slot number 0 selected with the rotary switches has a special meaning If the board is able to enable the VMEbus arbiter via software a setting of slot number 0 is in fact setting slot number 1 with arbiter enabled All other slot numbers disable the VMEbus arbiter automatically FORCE COMPUTERS Slot VMEbus address Short I O address 10 11 12 13 14 15 16 17 18 19 20
104. ate array 1 Parity generation is enabled 0 Parity generation is disabled 6 1 MISCELLANEOUS the func tion of the parity appropriate purpose parity data the signals wil be driven in write cycles evaluated only in a read cycle The generation of the parity data outside the gate array may sometimes be advantageous to gain speed The option is selectable in If the bit is set write cy cles is always checked by the gate array whether the parity signal Ss wi Depending on whether parity is being generated or only checked I O pins can be configured for the If the gate array is used to generate The parity but the result is ll be driven or not the CTL2 register bit 2 the parity signals wi MP TYOUT x 1l be driven during 6 1 2 Register CTL2 Register Mnemonic Address R W Default Control 2 Register CTL2 FFD0023C R W 00 Format of CTL2 7 6 5 4 3 2 1 0 VMERES PTYOUT CALL CSDPR STBCTL 3 PTYOUT The bit selects parity generation and check or only parity check by the gate array iL Parity is generated and checked 0 Parity is only checked MISCELLANEOUS 6 2 PARITY ERROR EVALUATION The gate array offers two options to evaluate a parity error which is detected by the internal parity checkers in a read access to the local main memory
105. bit VMEbus 16 bit VMEbus 8 bit AUX Bus 8 bit The DMA controller reads data from the source port into a 32 byte deep gate array internal F until the FIFO the internal FI LO OF empty is full until th Source and e transfer is completed FO as long as it is requested Data is then transferred from FO to the destination port until the FIFO is Then the FIFO is filled again and the process continues destination addressing is the full 32 bit address space and the count register has 32 bits The DMA controller can transfer any number of bytes from any unaligned start address to any unaligned destination address The DMA controller uses the internal FIFO to minimize the number of transfer cycles If unaligned transfers are necessary they only occur at the beginning and or end of the transfer THE 32 BIT DMA CONTROLLER The DMA controller generates 68020 68030 compatible cycles to the local CPU bus and VMEbus compatible cycles to the VMEbus The DMA controller operates only on the source or destination port at the same tim Both CPU and VME arbitration structures have been designed so The DMA controller can be selected for the source destination individually to count up or not to count Counting down is not possible that if the source and destination port are identical upon switchover from
106. blank THE MAILBOXES FEATURES 8 Mailboxes Mailboxes accessible from CPU side and VME side Interrupt capability for each mailbox Programmable interrupt level 8 Individual interrupt vectors THE MAILBOXES This page was intentionally left blank THE MAILBOXES 2 GENERAL DESCRIPTION The FGA 002 Gate Array includes eight dual ported mailboxes The mailboxes are specified as address locations which are able to trigger interrupts if an access to them is performed The mailboxes can be accessed from the local and VME side Each mailbox is assigned to an interrupt channel and is thus able to interrupt to the local CPU The interrupts can be triggered from the local side as well as from the VME side The accessibility of mailbox locations from the local side allows the local CPU to generate interrupt requests to itself The mailboxes provide a means to synchronize multiple CPU boards in a VMEbus environment by interrupts In using the mailbox interrupt capability interrupts can be sent by each board to any other board individually Additionally this method of interrupt generation reduces VMEbus load as the local CPUs will fetch the vector from the FGA 002 Gate Array and not from The select the VME bus Interrupt level for each mailbox interrupt is software table and an individual interrupt vector for each mailbox interrupt is prov
107. ble 3 1 Attribute Code for the Source Destination Port bh N wW w aR l r ah I r l al WWWW WW WW W W MAYA YNADWOWWWNEE THE 32 BIT DMA CONTROLLER This page was intentionally left blank THE 32 BIT DMA CONTROLLER T FEATURES The FGA 002 Gate Array contains a high speed 32 bit DMA Controller Module providing the following features 32 bit Addressing Range 32 bit Count Register Multiport Data Transfer Capability CPU bus gt CPU bus m gt VME bus gt AUX bus VME bus gt VME bus m gt CPU bus gt AUX bus AUX bus gt CPU bus gt VME bus 32 Byte deep internal FIFO 32 bit Data Port on Local and VME side Up to 25 Mbyte second transfer rate 2 vectored interrupts Internal registers allow complete software control by the local CPU THE 32 BIT DMA CONTROLLER This page was intentionally left blank THE 32 BIT DMA CONTROLLER 2 GENERAL DESCRIPTION The FGA 002 Gate Array includes a multi interface 32 bit Controller Module DMA The DMA Controller can be programmed and started from the local CPU side The source and destination ports can be selected as follows Port Device Data Bus Width CPU Bus MAIN MEMORY 32 bit CPU Bus Secondary Bus 322 bast CPU Bus Secondary Bus 16 bit CPU Bus Secondary Bus 8 bit VMEbus 32
108. ccess AM Code ODh 09h d ed d ed FMBAREA REGISTER FORMAT BITs 76543210 Byte XXXXXXXX Reset Value 00 BIT 7 0 F 31 24 SFFD0033C FMB Area decoding SFFFFxxxx The decoding is valid when the VME Address lines A31 A24 match the value of the corresponding bits F31 F24 39 AUXSRCSTART REGISTER FORMAT SFFD00340 BITs 76543210 Byte XXXXXXXX Reset Value 00 BIT 7 4 SRCASSACK 7 4 AUXACK pin is asserted after x cycles of 32mhz clock SO 1 clockcycle Sl 2 clockcycles 2 3 clockcycles 3 4 clockcycles 4 5 clockcycles 5 6 clockcycles 6 7 clockcycles 7 8 clockcycles 8 9 clockcycles 9 10 clockcycles SA 11 clockcycles SB 12 clockcycles SC on AUXREQ pin asserted SD on AUXREQ pin asserted AUXRDY pin must be released SE after data has been read into the fifo SF on AUXRDY pin asserted BIT 3 0 SRCRDY 3 0 READY after SO 1 clockcycle Sl 2 clockcycles 2 3 clockcycles 3 4 clockcycles S4 5 clockcycles 5 6 clockcycles 6 7 clockcycles 7 8 clockcycles 8 9 clockcycles 9 10 clockcycles SA 11 clockcycles SB 12 clockcycles SC AUXREQ pin asserted SD AUXREQ pin asserted AUXRDY pin must be released SE data has been read into the fifo SF AUXRDY pin asserted AUXDSTSTART REGISTER FORMAT SFFD00344
109. d is used to run several memory tests in the specified block of memory The first two command line parameters are begin and end address of the memory block to be tested These parameters are required to run the memory tests The third parameter count is an optional loop count If count is omitted all tests are executed twice The first test begins at begin while the second one begins at begin 1 So normaly the memory tests are started on a aligned memory address as well as on a unaligend address A count of zero will force an endless test If the fourth parameter trigger address is entered a TST B trigger address instruction is executed directly after any error is detected This feature may be used to trigger a logic analyzer on error The Block Test command executes the following memory tests BYTE PATTER TEST Fill the memory block with a byte pattern read it back and compare This procedure is done twice first started at begin and increment the address second started at end 1 and decrement the address 10 FGA 002A Boot Software Version 4 BYTE SHIFT TEST This test is performed only for some bytes of the memory block First a ZERO is shifted over the byte read back and compared seconed a ONE is shifted WORD PATTER TEST Fill the memory block with a word pattern read it back and compare WORD SHIFT TEST This test is performed only for some words of the memory block First a ZERO is shifted over the word read back and c
110. data bit 15 THE MAILBOXES 4 3 1 Access Addresses The following chart displays the mailbox access addresses from VMEbus side Mailbox VME Address MAILBOX 0 SXX00 MAILBOX 1 SXX04 MAILBOX 2 SXX08 MAILBOX 3 SXXOC MAILBOX 4 SXX10 MAILBOX 5 SXX14 MAILBOX 6 SXX18 MAILBOX 7 SXX1C 4 4 Mailbox Interrupts The active state of a Mailbox with regard to the interrupt request generation is when its contents is a logical 1 one This is equal to the condition when a Mailb interrupt request will go active and is mailbox is released by a write access The eight Mailboxes are assigned to the Mailbox 0 7 interrupt control registers where the in interrupt enable disable can be selected ox is occupied So if a read access to a Mailbox is performed the Mailbox pending until the Interrupt channels The Mailbox interrupt channels are controlled by a set of j terrupt level and The following chart shows the assignment of the Mailboxes to the interrupt channels and the corresponding interrupt control registers THE MAILBOXES Mailbox Interrupt Channel Interrupt Control Register MAILBOX 0 Mailbox 0 SFFDO0000 MAILBOX 1 Mailbox 1 SFFDO00004 MAILBOX 2 Mailbox 2 SFFDO00008 MATLBOX 3 Mailbox 3 SFFDOOOOC MAILBOX 4 Mailbox 4 SFFD00010 MATLBOX 5 Mailbox 5 SFFD00014 MATLBOX 6 Mailbox 6 SFFDO00018
111. disabled BIT 2 AUXREQHILO 1 AUXREQ signal active high 0 AUXREQ signal active low BIT 1 AUXRDYHILO 1 AUXRDY signal active high 0 AUXRDY signal active low BIT 0 AUXACKHILO 1 AUXACK signal active high 0 AUXACK signal active low CTL5 REGISTER FORMAT BITs 76543210 Byte XXXxX Reset Value 00 BIT 3 2 MYAMCODE BIT 1 AUXOPTB BIT 0 AUXOPTA SFFD00264 VME Access to FGA 002 for to SYSFAI MA L amp HALT status report ILBOX Locations RESETCALL function no access possible 0 01 10 0 SHORT NON PRIVILEGED AM Code SHORT SUPERVISORY AM Code AUXOPT AUXOPT AUXOPT AUXOPT both SHORT IONB IONB AM Codes allowed enabled disabled IONA IONA enabled disabled AUXFIFWEX REGISTER FORMAT SFFD00268 BITs 76543210 Byte XXXX Reset Value 00 BIT 3 0 AUXFIFWEX 3 0 0 AUXFIFO Write Timing 0 1 AUXFIFO Write Timing 1 2 AUXFIFO Write Timing 2 3 AUXFIFO Write Timing 3 4 AUXFIFO Write Timing 4 5 AUXFIFO Write Timing 5 6 AUXFIFO Write Timing 6 7 AUXFIFO Write Timing 7 8 AUXFIFO Write Timing 8 9 AUXFIFO Write Timing 9 SA AUXFIFO Write Timing 10 SB AUXFIFO Write Timing 11 C AUXFIFO Write Timing 12 D AUXFIFO Write Timing 13 SE AUXFIFO Write Timing 14 SF AUXFIFO Write Timing 15
112. e 250ns SFFD00330 Local I O Local I 0 Local I 0 Local I O LOCALIACK REGISTER FORMAT BITs 76543210 Byte XXXXXXXX Reset Value 00 BIT 7 6 LOCAL7 BIT 5 4 LOCAL6 BIT 3 2 LOCALS BIT 1 0 LOCAL4 IACK IACK IACK IACK 00 01 11 con con con con The is D31 The trol for LOCAL7 trol for LOCAL6 trol for LOCALS trol for LOCAL4 SFFD00334 vector number corresponding channel is presented Vector interrupt interrupt interrupt interrupt of the interrupt placed on CPU data bus D24 corresponding signal will be asserted No handling on Local and CPU bus corresponding signal will be asserted The Vector read on Local CPU bus and presented Acc ess time 1 us on Vector read on Local CPU bus and presented on Access time 500 ns LIACKx I O bus LIACKx I O bus I O bus FMBCTL REG SFFD00338 STER FORMAT BITs 76543210 Byte XXXXXXXX Reset Value 00 BIT 7 USERMODE BIT 6 ENACH1 BIT 5 ENACHO BIT 4 0 SLOTCODE 34 Access Access Chann nabl Channel disab l Channel 0 enabl Channel 0 disabl Slot code Slot number Slot number 21 to FMB only with Extended Supervisory Data Access AM Code ODh to FMB with Extended Supervisory User Data A
113. e RESVI the single level pin low will reset th VMEbus arbiter gat array including The special registers will not be affected by this reset MISCELLANEOUS 2 5 RESET SOURCE READOUT LOCATIONS The gate array allows the local CPU to determine which reset source had triggered the last reset Each reset source has an associated status register If bit 7 of the status register is low then that particular source was active The following table shows the address locations of the status registers provided to identify the active reset source Reset Source Address VME Reset call SFFDO04FO LOCAL Switch Reset SFFDO04F4 CPU Reset Call SFFDO04F8 Reset KEY SFFDOO4FC Additionally the power up reset can be identified by reading bit 7 of the SPECIALENA register This bit will be set to 1 by the boot software and is cleared only if a power up reset was active If none of the above reset sources are active then the reset will have been caused by a VMEbus SYSRESET Power Up reset SFFD00424 SPECIALENA Register Bit 7 VMEbus SYSRESET If no other reset source can be identified MISCELLANEOUS This page was intentionally left blank MISCELLANEOUS The ACFAI detection Asserting the ACFA if it is enabled The ACFA handler mastership on IL han
114. e attributes of the access will be latched in five gate array registers see Parity Error Address Readout In addition the parity error causes the gate array to drive the CPU bus error signal BERRC low The bus error signal is generated according to the late bus error timing specified for 68020 30 processors 2 The main memory is accessed from the VMEbus If a parity error is detected during an access of a VMEbus master to the shared main memory the cycle will be terminated with a bus error signal which is driven by the gate array on the BERRVO output to the VMEbus The parity interrupt will be generated The memory access address can be determined by the local CPU since it is latched inside the gate array MISCELLANEOUS 6 2 3 PARITY ERROR OPTION B If parity option B is selected a parity error will initiate the following response from the gate array ules The local processor accesses the main memory A parity error detected during a CPU access to the main memory will trigger the parity error interrupt indicating a malfunction in memory The access address and the attributes of the access will be latched in five gate array registers see Parity Error Address Readout 2 The main memory is accessed from the VMEbus Same response as option A MISCELLANEOUS 6 3 PARITY ERROR ADDRESS READOUT The gate array provides five register locations for parity error evalua
115. e gate array The BERRC signal is driven low when the BERR signal detected low during a VMEbus cycle of the CPU or the controller One of four possible timeouts can be programmed in regis CTL16 16 64 1000 or 64000 microseconds The 64 microsecond timeout is the default selection after reset is DMA Cer 000 MISCELLANEOUS 1 2 4 1 Register CTL16 Register Mnemonic Address R W Default Control Register 16 CTL16 SFFD0035C R W 00 Format of CTL16 7 6 5 4 3 2 1 O URMW VMETIMEOUT PEB PEA MAIN STERM 6 5 VMETIMEOUT The bitfield selects the bus error timeout for accesses to the VME bus 00 64000 us 01 1000 us 10 64 us 11 16 us 1 2 5 Unaligned RMW cycle to VME When the processor executes a read modify write operation to an unaligned address location on the VMEbus the gate array drives the bus error signal BERRC low No cycle on the VMEbus will be started in this case This is the default handling after reset However the gate array can support the execution of unaligned read modify write cycles on the VMEbus by programming bit 7 of the register CTL16 If this bit is set to 1 the unaligned bus error will not be generated Please refer to the chapter Support for unaligned RMW cycles in the section VME and CPU interface 1 2 6 LONG timeout The Long Timeout Count
116. e local side 4 1 1 Write cycles to a Mailbox A write cycle to a Mailbox location causes the Mailbox to store a logical 0 zero The data written to the location is irrelevant 4 1 2 Read cycles to a Mailbox A read cycle to a Mailbox location returns the value which is actually stored in the Mailbox The following conditions may occur If the previous cycle was a write to the Mailbox the read access will return a logical 0 If the previous cycle was a read cycle a logical 1 will be returned This is so because not only a write access but also a read access changes the contents of a Mailbox A read access appears as a Standard read cycle to the master but internally a read and write operation will be executed in the same cycle The access is performed in such a way that after the data which is actually stored in the Mailbox has been latched a logical 1 one is written into the Mailbox This means that after a read cycle has been performed the contents of a Mailbox is always a logical 1 The states of a Mailbox can be described in terms of released and occupied After reset the Mailbox locations are initialized to the released state This state is characterized such that a read access will return 0 zero Only the first read access to a free Mailbox reflects this condition since the read operation causes the Mailbox to be occupied Subsequent read acce
117. e register bits B31 B16 and the BASEUM register The main memory addressed when the CPU address signals mat of is tch the register bit ten into the base te SIZE bits 27 S516 In this case the masked base address bits can be ignored and need not be initia A base address register bit is masked corresponding sS A masked base address register bit will ZE register bit base address decoding The masking scheme is demonstrated in figure 1 1 lized if 0 is stored in the L not be compared for the THE CPU INTERFACE Figure 1 1 Masking scheme for the base address register bits CPU Address signals A31 A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 S27 S26 S25 S 24 S23 S22 S21 S20 S19 S18 S17 S16 SIZE selection bits O means that the bit Bxx will not be compared B31 B30 B29 B28 B27 B 26 B25 B24 B23 B22 B21 B20 B19 B18 B17 B16 MAI Base address register bits NUU MAINUM Base address register bits 1 3 4 1 Register MAINUU 7 6 5 4 3 2 1 0 B31 B30 B29 B28 B27 B26 B25 B24 7 0 B31 B24 These bits are used to define the the Upper Upper byte of the main memory base address The bits will be compa
118. e unless N is specified If the data written and the data read do not match the command is terminated and an error message is displayed The Memory Modify command supports a number of sub commands which can be entered instead of a new memory value These sub commands do not change the access option specified on the command line The following sub commands are supported 12 FGA 002A Boot Software Version 4 lt cr gt open next location open same location again open previous location again lt count gt go back lt count gt bytes open next location lt count gt go forward lt count gt bytes lt address gt open new absolute address lt esc gt exit to the command interpreter exit to the command interpreter 3 2 12 MD Syntax MD lt address gt lt count gt Description Memory display The MD command displays the memory contents of the specified address The data is displayed in hex and ASCII representation 16 bytes on every line If the hex value cannot be displayed in ASCII representation a full stop is displayed instead If no count is specified on the command line the display memory command displays 16 lines representing 296 bytes of data and prompts the user to display more or to return to the command interpreter If a carriage return is entered the next 256 bytes are displayed Any other character returns control back to the command interpreter If a count is specifi
119. ecoding area the USER Eprom area or the LOCAL I O area The timeout counter for onboard accesses starts counting when the gate array samples a low on the ASCPU input signal In addition the decoding logic of the gate array has to decode the respective decoding area Accesses by the DMA controller to the MAIN memory will also start the timeout counter for onboard accesses The Local Bus Error counter of the gate array will terminate the current cycle after 16 microseconds driving the BERRC output signal low This action will not take place if the cycle is terminated regularly 1 2 MISCELLANEOUS 1 2 2 VSB SECONDARY timeout bus error If the gate array decodes an access to the VSB bus or to the SECONDARY bus address ranges the VSB SECONDARY bus timeout counter is started The current cycle will be terminated with a bus error by the VSB SECONDARY bus timeout counter after the bus error time has elapsed The gate array finishes the cycle by asserting its BERRC output low The VSB SECONDARY timeout counter is not only started if the processor executes cycles to the secondary or the VSB bus but also if the DMA controller accesses these areas Using bits 6 and 7 in the CTL15 register the bus error timeout can be set to 16 1000 or 64000 microseconds or can be disabled 1 2 2 1 Register CTL15 Register Mnemonic Address R W Default Control 15 Register
120. ed on the command line the value is interpreted as the number of bytes to be displayed 3 2 13 PROG Syntax PROG lt source gt lt dest gt lt length gt lt width gt Description Program Flash EPROMs This command is used to program Flash EPROMs The first parameter is the start address of the data which is to program into the Flash EPROM The second parameter represents the base address of the Flash EPROM The third parameter specifies the length of the Flash EPROM Of 0 is entered the length and width is automatically calculated The optional fourth parameter selects the data width of the Flash EPROMs Three values are possible 4 Byte width 8 bit 72 Word width 16 bit 4 Long width 32 bit Please note that a Flash EPROM must be programmed completely Therefore programming only parts 13 FORCE COMPUTERS of a Flash EPROM is not possible 3 2 14 SELFTEST Syntax SELFTEST Description Start Selftest The selftest tests the FGA 002A and the FC68165 for proper functionality First of all the access to these chips is tested Afterwards special parts of them will be tested including interrupt generation Please note that a few tests can only be executed if the FGA 002A FC68165 is initialized If you need these tests ensure that the INIT command has been executed prior to the SELFTEST command 3 2 15 SETUP Syntax SETUP Description Change initialization values The SETUP command is used to c
121. ed to be the local bus the least significant three bits have to hold the function code according to the address space type of 68020 68030 processor If the VMEbus port is selected as destination the lower six bits must hold the proper Address Modifier code for the access to the VMEbus 7 6 5 4 3 2 1 0 Attribute code for the destination port 7 0 Attribute code for the operation on the destination port Please refer to table 3 1 3 3 THE 32 BIT DMA CONTROLLER Table 3 1 Attribute Code for the Source Destination Port Attribute Code Bit Port Device Data Bus TP Ao Sb Ae 23 2 Ae O With 0 0 0 FC CPU Bus MAIN MEMORY 32 bit QO 10 SF T CPU Bus Secondary Bus 32 bit T a A CPU Bus Secondary Bus 16 bit Oe Pee FE gt CPU Bus Secondary Bus 8 bit X xX xX Forbidden O 0 AM Code VMEbus 32 bit 1 0 AM Code VMEbus IG Ie O AM Code VMEbus 8 bit 0o 0 1 0 0 0 AUX Bus 8 bit FC Function Code according to address space type encoding of the 68020 68030 processor AM Code Address Modifier Code defined in the VMEbus specification THE 32 BIT DMA CONTROLLER 3 3 3 General Control Register DMAGENERAL The DMAGENERAL Register is used to enable the DMA Controller function and selects the count mode for the source and destination addresses
122. el FMB channel 0 can receive data through a dual ported FIFO In the current version of the gate array the FIFO contains eight entries of 1 byte each Transfer bursts of some bytes are possible but the reaction delay of different slaves to the same message can vary significantly Data received for FMB channel 1 is stored in a latch of one entry only 1 byte No new message will be accepted until the register contents are fetched by the local CPU This structure means that variations in reaction delay are limited or at least more predictable The received messages are available for the local CPU by reading the registers FMBCHO and FMBCH1 A read access to an empty FMB FIFO will lead to a bus error termination of the cycle With the FGA 002 gate array the FMB area decoding is software selectable by the FMBAREA register The FMB area is reserved only for message broadcast cycles There must not be any slave responding in the defined FMB Area other than according to the FMB protocol The code for the VME slot in which the board is installed is programmable in the control register FMBCTL This register controls further functions for the FMB channels like enable disable control and Supervisor User access control FORCE MESSAGE BROADCAST FMB This page was intentionally left blank FORCE MESSAGE BROADCAST FMB 5 FMB INTERRUPT For each FMB channel a
123. eload Sys fail tart top nn source clock select pi Zerostop Autopreload This bit selects stops when continues counting whether reaching the counter Zzero count Or down The value the counter will decrement to next depends on the register setting which is of bit 6 of this the Autopreload bit The counter continues counting down The counter stops o This bit selects wh n zero count ether the counter rolls over from 00 to the value SFF and continues preset by the con preload register aft count ignored if the coun stop on zero count The Autopreload opt When S00 the value register will counter on following the zero that transfer the decrementing from t be the The Au After will topreload opt the counter roll over to the counter has passed from S01 stored in the Preload counting down or is tents of the timer ter reaching the zero The Autopre load option may be ter is programmed to ion is enabled to transferred to the first clock edge count clock After counter continues he new value ion is disabled has reached zero it the value SFF and continue counting down 3 3 THE TIMER Sysfail This generation by the timer enabled the SFAI te array will be asser gal timer int Timer Sysfail generat
124. en to The timer interrupt the status register will be ignored is acknowledged with a single vector The least significant five bits of the timer interrupt vector are fixed and defin after reset the default value for the vector as 20 For further information please refer to the section Interrupt Management in the FGA 002 Gate Array description Ca SYSFAIL Generation The timer can be configured to operate as a system watchdog timer generating a sysfail signal to the VMEbus The timer generates the sysfail signal if the sysfail enable bit in the timer control register TIMOCTL is set to 1 and the timer decrements from 01 to 00 This will also trigger the timer interrupt The IRQ enable bit in the interrupt control register CRTIMO determines if the timer interrupt is recognized by the interrupt logic to request service from the CPU The sysfail signal can be released by a clear operation of the timer interrupt The clear operation is performed by a write access to the ISTIMO register location The sysfail signal i s also released when the sysfail enable bit is cleared to 0 The sysfail signal will be driven on the SFAILO output of the gate array The SFAI LO signal is an active low signal MISCELLANEOUS This page was intentionally left blank MISCELLANEOUS TABLE OF CONTENTS I BU
125. ent way For this reason this debugger is designed You can change the initialization values initialize the board and test if you still can access all of the peripherals 3 1 How to start If during the startup of the FGA 002A Boot Software the Abort Switch is pressed the debugger is started This means every time a reset is generated while the Abort Switch is pressed the debugger begin to run You must have a terminal connected to the console port The terminal is to set for 8 bit 9600 baud no parity and 1 stop bit The debugger starts with printing an information page This page shows most of the important board parameters Afterwards the debugger prompts for a command All possible commands are described in the following sections Every input line has to be finished with a carriage return The command line and every interactive input can be edited with the following control characters ESC Cancel current line and exit CTRL C Cancel current line and exit CTRL I Toggle between insert and replace mode First the line editor is in insert mode CTRL L Move right one character CTRL E Move to end of line CTRL H Move one character left CTRL B Move to begin of line CTRL D Delete character under cursor RUBOUT Delete one character to the left CTRL Delete character under cursor to the end of line CTRL 0 Delete whole line 3 2 Commands 3 2 1 Syntax Description Display a help text The com
126. er addressed slave refuses to store the message in its register Otherwise all addressed slaves fetch the message data and terminate the cycle The master that wanted to transfer the message can react to the bus error exception by trying the message passing cycle repeatedly A successful FMB cycle is terminated by DTACK assertion It is possible that several boards assert DTACK at the same time FORCE MESSAGE BROADCAST FMB 2 2 The FMB Data Format Definition The FORCE Message broadcast definition allows message data to be sent in a Byte Word or Long data format The message is transferred on the data lines DOO D31 of the VMEbus backplane The VMEbus signal lines Al and LWORD should be used according to the VMEbus addressing conventions for data transfer In the same way DS1 and DSO have to be driven according to the VMEbus specification The following FMB message transfers are defined DATA FORMAT Al LWORD DS1 DSO Data Lines Byte Message 1 1 1 0 DO7 DO Word Message 1 1 0 0 DES isa DO Long Message 0 0 0 0 D3 Lasa DO Note To ensure that slave boards with Byte Word or Long data formats can be used together in a system it is necessary that each FMB Slave board accepts any data format without generating a bus error to the VMEbus This guarantees that data sent on the D7 D0 signal lines will be accepted by every slave as message data
127. er is started anytime the gate array detects that the ASCPU input is asserted If the current cycle is not terminated regularly 3 seconds after it was started the Long Timeout Counter will generate a bus error to the processor or the DMA controller by asserting I MISCELLANEOUS the BERRC output pin of the gate array MISCELLANEOUS This page was intentionally left blank MISCELLANEOUS 2 RESET FUNCTION The gate array supports the initialization of the VMEbus and the CPU by generating reset signals for the VMEbus and for the local processor Software and hardware triggerable reset sources are provided The reset signal for the VMEbus is driven on the RESVO outpu while the RESCPU I O pin of the gate array drives the CPU rese signal 2 1 GATE ARRAY RESET The gate array itself is reset by several sources The reset sources are Power up input Reset key input Local switch input CPU reset call VME reset call SYSRESET from VME input Q After the power up reset has been active all functions an registers inside the gate array will be initialized the SPECIAL register and the SPECIALENA register included All other reset sources initialize the gate array functions and registers with the exception of the special registers The special registers are only reset by the power up reset The gate array internal VMEbus arbiter
128. essages sent to FMB channel 0 The register can only be read The message data is presented on the data bits 7 0 31 24 23 16 15 8 7 MESSAGE 7 0 MESSAGE These bits contain the message data from FMB channel 0 6 3 12 Message Readout Register Channel 1 FMBCH1 The FMBCHO register is used to read the messages sent to FMB channel 1 The register can only be read The message data is presented on the data bits 7 0 31 24 23 16 15 8 7 MESSAGE 7 0 MESSAGE These bits contain the message data from FMB channel 1 THE MAILBOXES THE MAILBOXES This page was intentionally left blank THE MAILBOXES TABLE OF CONTENTS I FEATURES 2 GENERAL DESCRIPTION 3 arenes INTERRUPT REGISTERS 33 Register Organization 5 2A Register Addressing Assignments 3 3 Register Description Bethe You eatg ts 3 3 1 Interrupt Control Register ICRMBOX 0 7 4 DESCRIPTION OF OPERATION 4 1 Mailbox Operation u eS ye ag 4 1 1 Write cycles to a Mailbox 4 1 2 Read cycles to a Mailbox 4 2 Mailbox Access from Local Side 4 2 1 Mailbox Register Organization 4 2 2 Mailbox Register Format MBOX 0 7 4 3 Mailbox Access from VMEbus Side 4 3 1 Access Addresses 4 4 Mailbox Interrupts LIST OF TABLES Table 4 1 Mailbox Register Addressing Assignment RHE ADAH AAA A A THE MAILBOXES This page was intentionally left
129. evices The 7 interrupts from the VMEbus may also be connected The interrupt of each source can be mapped to any level for service request from the local CPU Except for the VMEbus interrupts the gate array supplies an individual interrupt vector for each interrupt source Four local interrupt request channels support fetching the interrupt vector from the interrupting device through the local I O interface local cpu bus FO to minimize nd destination 4 The DMA Controller The 32 bit high speed DMA controller operates to the the VMEbus and to the auxilary bus The DMA controller uses an internal 32 byte deep FI the number of transfer cycles If the source a addresses are aligned the data is transferred in bursts of 32 bytes The DMA controller uses the local bus or the VMEbus continuously only for the time of a transfer burst This guarantees realtime capability of the system since neither the VME maste cpu The is blocked in its operation DMA controller executes 68020 30 compatible cycles on the local r nor the loca side and uses the VME interface for VMEbus compatible transfer cycles INTRODUCTION O s FORCE MESSAGE BROADCAST FMB The FORCE Message Broadcast Concept is realized inside the FGA 002 gate array The FMB concept allows up to 20 CPU boards on the VMEbus to be synchronized using interrupts
130. gister will lue stored in the Timer Preload It is permitted to perform read write accesses to the Timer The Timer Count after reset 7 6 5 4 3 dD 0 Timer Count Value 4 Timer Interrupt Control Register ICRTIMO Timer Interrupt Control is performed by the Timer Interrupt Control Register ICRTIMO which enables disables the interrupt and selects the interrupt level 7 6 5 4 3 1 0 IRQ 5 5 Enable IRQ Level 3 IRQ Enable The bit enables or disables the timer interrupt channel 1 Interrupt channel is enabled 0 Interrupt channel is disabled 2 0 IRQ Level This bit field defines the interrupt request level 000 Interrupt disabled 001 Level 1 010 Level 2 01 Level 3 100 Level 4 101 Level 5 110 Level 6 Level 7 3 5 THE TIMER The Timer ST In terrupt timer interrupt Th Timer Interrupt Status Register ISTIMO Status Register IST MO displays a pending is bit is always readable and indicates 0 if the timer int terrupt this register wil has been triggered A write access to the MO register clears the timer interrupt The data written to ll be ignored Format of ISTIMO 7 6 5 4 3 2 1 0 IRQ
131. h requester who has sampled the bus request line high is now allowed to request control of the VMEbus After the request line has been asserted again the participants of the current round are defined The mastership will be given to the reguesters in the order of priority starting at the most prioritized location in the daisy chain which is closest to the bus arbiter On gaining the mastership the new master releases his bus request line whilst the other requesters leave theirs asserted When the master has finished with the bus BBSY goes inactive the next arbitration round begins without him since the FAIR request option prevents him from asserting his bus request line until BRx has been released by all other requesters This guarantees that low prioritized masters can obtain the bus The gate array samples the VMEbus requests at the BRVMEI input pin and recognizes it negated when it is high for a minimum of 20 nanoseconds In order that all participants are able to sample the high state of the request signal line the gate array asserts its request output not earlier than 50 nanoseconds after it has detected the BRx signal high The FAIR request option bit is contained in the CTL8 register The FAIR request option is enabled after reset 2 6 2 1
132. hange the initialization values of the FGA 002A As mentioned above some bits of FGA 002A registers should not be altered to be sure that the board keeps running The SETUP command takes care of that and does not allow to change these values The SETUP command displays the content of the SRAM value and let you EDIT this value You can step backward if you enter a single 3 2 16 USER Syntax USER Description Start user program The command USER starts the user defined subroutine Please refer to section 5 14 FGA 002A Boot Software Version 4 4 System Calls The FGA 002A Boot Software provides some calls to control the FGA 002A and some useful tools The following code is a C code example how to access these system calls define BOOTUTIL_BASE Oxffe00008 define FLASHPRG_CALL 34 typedef int FLASH_PTR int FlashProgram source_address eprom_base_address length width char source_address char eprom_base_address long length short width FLASHPARM flashdata FLASH_PTR fga_util FLASH_PTR long BOOTUTIL_BASE flashdata flashbase eprom_base_address flashdata rambase source_address flashdata length length flashdata width width return fga_util long FLASHPRG_CALL amp flashdata Any return value except 0 indicates an error 4 1 AUX Dependent Functions 4 1 1 AUX Pin Control Set the activity levels of the REQUEST ACKNOWLEDGE and READY signals Enable disable auto re
133. hannel in the daisy chain The order of the interrupt daisy chain is given in Table 2 1 Interrupt Vector Number Assignment INTERRUPT MANAGEMENT 2 4 Interrupt Vector Page The 8 bit interrupt vector information which is presented by the gate array when it responds to IACK cycles with an internal vector is set together from the lower 6 bit field for the vector number and the upper 2 bit field for the vector page The lower six bits are provided by the prioritization logic and determine the vector number of the corresponding interrupt channel The upper two bits are programmable in the CTL3 register and are common for all vector numbers of the gate array For details please refer to Interrupt Vector Page Programming later in this description The interrupt vector table of the FGA 002 Gate Array consists of a contiguous block of 64 vector numbers Unused vector number ntries ar reserved for future extensions NOTE The zero vector page the two most significant bits of the interrupt vector are 0 is a reserved area for system vectors of 68020 68030 processors Since all bits of the CTL3 register are set to zero after reset the default gate array vector page is the zero page Therefor th bootup software has to initialize this register to select one of the remaining vector pages The vector page binary 11XXXXXX generating the interrupt vectors SCO SFF is
134. hared Memory Structure Support When the gate array is initialized to support the shared memory structure selected in the SPECIAL register bit 5 an access from VME to the local MAIN memory causes the gat array request control of the local bus from the processor to Depending on the selection for RMW cycle support CTLI15 register SHAREDRMW bit the gate array either performs a fast execution of the memory access cycle or the memory cycle is terminated only on completion of the VMEbus cycle In the fast execution mode the gate array first finishes memory cycle and then completes the VME cycle A memory read cycle is terminated by the gate array after the the data has been latched A memory write cycle is finished aft the data is stored in the memory The local bus is released immediately after the cycle terminated If the gate array is programmed to support RMW cycles from Cer is the VMEbus SHAREDRMW bit 1 the slow access mode to the memory is selected In this mode the local memory cycle is not terminated unt the VME cycle is finished by a negated VME address strobe as is the case in the fast access mode til In this mode the local bus will be occupied about twice as long The gate array terminates a VMEbus access to the local main memory with VMEbus error if a parity error is decoded by the gate array
135. he CPU and the VMEbus are either directly connected or connected via buffers to the gate array allowing easy implementation and usage The gate array registers are programmed by the local CPU FEATURES Programmable decoding for CPU and VME access to the local main memory Interrupt management for internal and external interrupt sources 32 bit multi port DMA Controller FORCE Message Broadcast slave interface with 2 message channels 8 interrupt capable MAILBOXES 8 bit TIMER with 16 selectable internal source clocks IIL Ss INTRODUCTION The CPU Interface 1 Connected signals The FGA 002 is directly connected to signal lines of the 68020 30 microprocessor The following signals are connected 32 address signals 32 data signals Function code signals Transfer size Asynchronous bus control PROCESSOR Signals A31 A00 D31 D00 FC2 FCO SIZO SIZ AS ECS R W RMC DSACKO DSACK1 FGA 002 Signals ACPU31 0 DCPU31 0 FC2 FCO SIZE 0 1 ASCPU ECS RWCPU RMC DSACKO DSACK1 STERM CIIN CIOUT Synchronous bus control signal Bus arbitration control signal Interrupt control signals Bus exception control signals Processor clock 1 2 Decoding signals The FGA 002 gate array decodes local address areas BR BG BGACK PL2 IPLO RESET HALT BERR CLK
136. he VMEbus SYSFAIL and HALT Status report to VME THE VME INTERFACE 3 2 VME Access to the local MAIN MEMORY The gate array supports accesses from the VMEbus to the local MAIN memory by providing address decoding and Address Modifier decoding both software selectable Accesses from the VME bus to the local main memory are decoded in the 32 bit address space of the VMEbus The 4 Gbyte total address space is decoded into 16 pages each of 256 Mbyte The page can be defined by the VMEPAGE register whose register bits are compared with the VME address lines A31 A28 The VMEPAGE is then further decoded into intervals This is performed by two address comparators one decoding a bottom page and the other decoding a top page The bottom page decoder accomplishes a higher or equal comparison and the top page decoder a lower or equal comparison of the applied E e VME address The VME address is valid when both comparisons are valid The address interval in which a VMEbus access is decoded ranges from the lowest bottom page to the highest top addressable page The address comparators evaluate the VME address lines A27 A12 for the interval decoding The remaining address lines A11 A00 are not decoded which allows the interval size to be selected in steps of 4KByte An interval contains the address range that starts with the base address of the bottom page and finishes with the end address of the
137. he user User selectable registers and register bits are given in the Register Format Short Description in section 7 of this manual They are designated with capital letters in the register format scheme NOTE Throughout the description the terms active and inactive asserted and negated or set and cleared are used to designate a signal or a register bit as true or false independent of whether the signal is active in the logic 1 state or the logic 0 state The default contents given for the register is the value after th gate array has been reset and not the value which is programmed by the boot software If no reference is made concerning the gate array support for dual ported memory structure shared memory structure the described gate array functions are common to both structures INTRODUCTION INTRODUCTION The FGA 002 gate array is a high speed CMOS device manufactured in 1 2 micron technology and containing 24 000 gates in a 281 pin PGA package It provides interfaces to the 68020 30 microprocessor as well as a VMEbus compatible interfac The auxilary interface of the gate array is a high speed data channel used by the internal 32 bit DMA controller The interfac allows data transfer rates of up to 6 MByte second The timing of the local I O interface is programmable and provides easy interfacing of local I O devices All control address and data lines of t
138. hich may be used for additional addressing purposes such as the selection of address spaces or privilege levels The Gate Array supports the generation of address modifier signals and drives the AM code on the pins AM5 0 The AM code signals 5 3 determine if the address broadcast by the master is to be used as an Extended 32 bit Standard 24 bit or Short 16 bit address The AM code signals 2 0 specify the privilege level of the address space supervisor or non privileged the use of the memory area program or data and the type of transfer standard or block transfer When the gate array internal DMA Controller accesses the VMEbus the address modifier signals are supplied by the lower five bits of the DMA attribute registers DMASRCATT and DMADSTATT This allows all AM codes which are defined in the VMEbus specification to be generated for DMA transfers The attribute register bits have to be programmed with the correct AM code for the intended transfer When the local CPU is master on the VMEbus the AM signals are generated by the gate array and the processor The AM signals 5 3 are directly generated by the gate array s decoding logic Depending on the selected VMEbus area the AM signals 5 3 indicate the code for Extended Standard or Short address decoding The AM signals 2 0 are generated by the processor by driving the function code i
139. ided by the gate array For p rocessor to processor communication the mailboxes also can be used as semaphores The allocation of a mailbox is done only by a standard read cycle instead of a read modify write operation to a global or a dual ported memory location THE MAILBOXES This page was intentionally left blank THE MAILBOXES ce MAILBOX INTERRUPT REGISTERS Register Organization outline of the mailbox The following is an organizational interrupt control registers 31 24 ICRMBOXO Interrupt Control Register Mailbox ICRMBOX1 Interrupt Control Register Mailbox ICRMBOX2 Interrupt Control Register Mailbox ICRMBOX3 Interrupt Control Register Mailbox ICRMBOX4 Interrupt Control Register Mailbox ICRMBOX5 Interrupt Control Register Mailbox ICRMBOX6 Interrupt Control Register Mailbox ICRMBOX7 Interrupt Control Register Mailbox 3 2 Register Addressing Assignments Mailbox Interrupt Reg Mnemonic Address R W Default Int Ctl Mailbox0 ICRMBOX0 SFFDO0000 R W 00 Int Ctl Mailbox ICRMBOX1 SFFDO0004 R W 00 Int Ctl Mailbox2 ICRMBOX2 SFFDO0008 R W 00 Int Ctl Mailbox3 ICRMBOX3 SFFDOOOOC R W 00 Int Ctl Mailbox4 ICRMBOX4 SFFDO0010 R W 00 Int Ctl Mailbox5 ICRMBOX5 SFFD00014 R W 00 Int Ctl Mailbox6 ICRMB
140. if an interrupt is pending is pending FORCE MESSAGE BROADCAST FMB 6 3 9 Interrupt Status Register Channel 1 Message ISFMB1MES The ISFMBIMES status register contains the IRQ Status flag assigned to the channel 1 message interrupt request The status bit displays zero on a pending message interrupt request of FMB channel 1 The interrupt condition is negated when the FMB FIFO is empty 7 6 5 4 3 2 1 0 IRQ Status 7 IRQ Status The IRQ Status register bit shows if an interrupt is pending be is returned if no interrupt 0 is returned if an interrupt is pending is pending ct ct 6 3 10 Interrupt Status Register Channel 1 Refused ISFMB1REF The ISFMBIREF status register contains the IRQ Status flag assigned to the channel 1 refused interrupt request A write access to the ISFMBOREF register clears the Refused interrupt 7 6 5 4 3 2 1 0 IRQ Status zs 7 IRQ Status The IRQ Status register bit shows if an interrupt is pending Writing the status register with any data clears the interrupt 1 is returned if no interrupt is pending 0 is returned if an interrupt is pending FORCE MESSAGE BROADCAST FMB 6 3 11 Message Readout Register Channel 0 FMBCHO The FMBCHO register is used to read the m
141. ignal on the RESVO output pin Also the RESCPU output signal will be driven low resetting the processor and peripheral devices as long as the VMEbus reset generator drives the RESVO reset signal 2 4 2 Reset Key Input The RESKEY input pin of the gate array is provi connection of a panel reset key The reset is active when the pin is asserted low Th key reset initializes the gate array functi initializing the special registers The VMEbus reset generator is triggered and the RESCPU output ded for the ons without will be asserted low resetting the local processor 2 4 3 Local Switch Reset array will be reset CPU The VMEbus reset generator is not triggered More details can be found in the chapter LOCAL SWI section If the LOCSW input of the gate array is asserted low the gate In addition this reset source drives the reset signal for the TCH of this MISCELLANEOUS 2 4 4 Processor Opcode Reset The processor will reset external devices which are connected to its reset signal when it executes a reset opcode A reset option bit inside th reset signal of the processor will VMEbus reset generator for a system reset The execution of the reset independent of the reset option bit any gate array registers However the single level reset gate array determines if the opcode also trigger the internal by
142. ill be executed as standard read and write cycles on the VMEbus This allows RMW cycles to be performed also with unaligned data cycle types The correct execution of the RMW operation on the VMEbus is ensured since the control of the VMEbus is continuously kept for the CPU during the whole RMW operation 2 4 2 1 Register CTL16 Register Mnemonic Address R W Default Control Register 16 CTL16 SFFD0035C R W 00 Format of CTL16 7 6 5 4 3 2 il 0 URMW VMET IMEOUT PEB PEA MAIN STERM 7 URMW Unaligned Read Modify Write option bit 1 Unaligned RMW operation to VME is supported Cycle will be executed as individual and Write cycles 0 Unaligned RMW operation to VME is supported Cycle is terminated with bus error to the processor 2 11 THE VME INTERFACE 2 5 VMEbus ARBITRATION The FGA 002 gate array is equipped with an arbiter module to control the allocation of the VME data transfer bus DTB to VMEbus masters The arbiter module provides mastership arbitration on a single level and its function can be enabled or disabled When the processor or the onchip DMA controller intend to access the VMEbus the gate array requests mastership over the VME data transfer bus DTB by asserting its bus request output BRVMEO This signal is evaluated by the internal arbiter together with the requests of other bus participa
143. ister bit displays if an interrupt request is pending n is returned if no interrupt 0 is returned if the interrupt is pending is pending 3 3 12 Interrupt Status Register Error Termination ISDMAERR The ISDMAERR status register contains the IRQ Status bit for the Error termination interrupt The bit indicates zero if an interrupt request is pending A write access to the status register location clears the error termination interrupt The written data will be ignored 7 6 5 4 3 2 1 0 IRQ Status me me z 7 IRQ Status The IRQ Status register bit displays if an interrupt request is pending T is returned if no interrupt 0 is returned if the interrupt is pending is pending FORCE MESSAGE BROADCAST FMB FORCE MESSAGE BROADCAST FMB This page was intentionally left blank FORCE MESSAGE BROADCAST FMB TABLE OF CONTENTS THE CONCEPT OF FMB ree DEFINITION Des Introduction Se Saw et x Ms 2 The FMB Data Format Definition 2 3 The FMB Decoding Definition 2o FMB Area Decoding 22 32 FMB Channel Decoding 2253 35 FMB Board Decoding 2 4 The Timing of FMB Cycles n 2 Ao Own Refused Messag cycle 2 4 2 Foreign Refused Message Cycle Timing 2 4 3 Accepted Message Cycle Timing FEATURES OF THE FGA 002 FMB INTERFACE GENERAL DESCRIPTION FMB INTERRUP
144. itialized Additionally asserting the LOCSW input will prevent the gate array from generating a SYSFAIL signal at its SFAILO output MISCELLANEOUS This page was intentionally left blank MISCELLANEOUS 6 PARITY SUPPORT 6 1 PARITY GENERATION CHECK The gate array provides parity generators for even byte parity generation and checking The parity generation check function can be used only if the gate array is programmed to support the shared memory structure defined in the SPECIAL register bit 5 Each data byte of the processor bus has an associated parity I O pin The following table shows the assignment of the byte parity I O signals to the CPU data bytes Parity Signal Data Bits PTYUU 31 24 PTYUM 23 16 PTYLM 15 08 PTYLL 07 00 During read cycles the parity is always checked During write cycles if the gate array is used to generate parity the parity I O signals will be driven by the gate array It is possible to disable parity generation by the gate array It may sometimes be advantageous to generate parity with external hardware to gain a speed improvement The PTYOUT bit in the CTL2 register determines whether the gate array generates parity or not If the bit is set the parity signals will be driven during write cycles 6 1 1 Registers CTL2 3 PTYOUT This bit enables parity generation by the g
145. lave Basie a ters for an Accepted Cycle Cycle Due to Decision Decision of Cycle Due to FORCE MESSAGE BROADCAST FMB This page was intentionally left blank FORCE MESSAGE BROADCAST FMB 1 THE CONCEPT OF FMB Consider the situation where a master wants to transfer data to several slaves at the same tim Normally the master which transfers the data would have to address each slave in turn and runs the risk of losing the bus mastership if a higher priority master requests it before it has transferred the data to all slaves Likewise the master could receive an interrupt which would also disturb the transfer disabling the interrupts for such a length of time is not a good solution To solve this problem FORCE COMPUTERS defined the FORCE Message Broadcast FMB as a means of transferring data to several boards up to 20 simultaneously FORCE MESSAGE BROADCAST FMB This page was intentionally left blank FORCE MESSAGE BROADCAST FMB 2 FMB DEFINITION 2 1 Introduction The FMB concept defines a slave interface which makes it possible to transfer data simultaneously to one or more possibly all boards in a VMEbus system All operations of the FMB slave are compatible with the existing VMEbus Specification Rev C Any VME Master with 32 bit addressing capability can accomplish an FMB broadcast cycle That is a write cycle to one or more slaves on the VMEb
146. ler in the vector page NOTE May only be called in the SUPERVISOR mode int fga_util unsigned long vmeirq unsigned long inum unsigned long vflag unsigned long vlevel unsigned long vector char handler vmeirq 9 inum 0 reserved VMEbus IRQ 1 7 vflag 0 to disable IRQ 1 to enable IRQ vlevel interrupt request level code vector the 680xx vector number handler the irq handling routine address 4 4 2 FMB IRQ Control Sets up FORCE FMB IRQ controls The routine also initializes the 680XX IRQ handler in the vector page NOTE May only be called in the SUPERVISOR mode int fga_util unsigned long fmbirq unsigned long finum unsigned long fflag unsigned long flevel char handler fmbirqg 10 finum 0 FMBO error 1 FMB1 error 2 FMBO normal 3 FMB1 normal flag 0 to disable IRQ 1 to enable IRQ flevel interrupt request level code handler address of the irq handling routine 18 FGA 002A Boot Software Version 4 4 4 3 Extended Local IRQ Control Sets up local IRQ controls This routine also initializes the 680XX IRQ handler in the vector page NOTE May only be called in the SUPERVISOR mode int fga_util unsigned unsigned unsigned unsigned unsigned unsigned unsigned char handler locirqx 12 linum 0 abort 1 acfail 2 sysfail 3 locald 4 locall 5 local2 6 local3 7 local4 8 locald 9 local6 10 local7 long long long long long long long Iflag 0 to
147. lid when the register bit pattern matches the corresponding VME address signals 3 4 1 1 Register MYVMEPAGE Register Mnemonic Address R W Default FGA 002 VME Page MYVMEPAGE SFFDOO2FC R W 00 Format of MYVMEPAGE 7 6 5 4 3 2 1 0 YS Y14 La Y12 Y11 Y10 YO9 YO8 7 0 Y15 Y08 These bits select the VME page for accesses from the VMEbus array functions with the VME address signal to the gate The bits are compared ls Al15 A08 THE VME INTERFACE 3 4 2 Address Modifier Code selection The Control Register 5 address modifier code for a valid access to the gate array CTL5 provides two bits which has to be broadcast by to select the bus master the If the bits are zero which is the case after reset no VME access to the gate array is possible 3 4 2 1 Register CTL5 Register Mnemonic Address R W Default Control 5 Register CTL5 SFFD00264 R W 00 Format of CTL5 7 6 5 4 3 2 dh 0 MYAMCODE AUXOPTB AUXOPTA 3 2 MYAMCODE This bitfield selects the AM Code for VME accesses to the gate array 00 VME page decoding disabled O01 Short Non Privileged AM code 29 10 Short Supervisory AM code 2D 1 Both Short AM Codes allowed INTERRUPT MANAGEMENT INTERRUPT MANAGEMENT This page was intentionally left
148. ll ypu aie f NDANNANnNDANANAAUnNMNH DW Q S fo ll ll NWHE BHOOD dOABNEF O CTL8 REGISTER FORMAT BITs 76543210 Byte XXXX Reset Value 00 BIT 3 BSYSBIT BIT 2 SSYSBIT BIT 1 FAIR BIT 0 HANDLER SFFD 00278 BIT This bit is LE pie Pook the SPECIAL register SFFD00420 is the SFAILO pin SYSFLTOVME Pin 1 to 1 SYSFLTOVME Pin to 1 the SFAILO pin FAIR request op BOOT SYSFAIL overridden set to l 1 Releases 0 Asserts SOFT SYSFAIL BIT 1 Asserts 0 Releases 1 Disables 0 Enables tion FAIR request op Power fail Handler Active ACFAIL Handler Inactive tion CTL9 REGISTER FORMAT SFFDO0O27C BITs 76543210 Byte XXXX Reset Value 00 BIT 3 RESETOPTION 1 Processor RESET Opcode will initiate a VMEbus system reset O Processor RESET Opcode will not initiate a VMEbus system reset BIT 2 0 SEPROMDSACK SYSTEM EPROM DSACK 000 No DSACK Generation 001 O Waitstate 010 1 Waitstate 011 2 Waitstates 100 3 Waitstates 1 4 Waitstates 110 5 Waitstates 11 6 Waitstates O Oo C ENAMCODE REGISTER FORMAT BITs 76543210 Byte XXXXXXXX Reset Value 00 BIT 7 6 XSP
149. mand displays a help text which shows all available commands 3 2 2 BF Syntax BF lt begin gt lt end gt lt value gt B W ILIP Description Fill memory This command fills the specified memory area with a constant The type of the constant is defined by the fourth parameter and may be a byte word long word or a pattern A pattern is an ASCII string FORCE COMPUTERS which is to be put in quotation marks The maximum length is only restricted by the length of the input line If no option is specified a default of word is assumed 3 2 3 BM Syntax BM lt begin gt lt end gt lt destination gt Description Move memory block The BM command copies a specified memory area 3 2 4 BS Syntax BS lt begin gt lt end gt lt value gt B WILIP Description Block search This command searches for a constant in the specified memory area The type of the constant is defined by the fourth parameter and may be a byte word long word or a pattern A pattern is an ASCII string which is to be put in quotation marks The maximum length is only restricted by the length of the input line If no fourth parameter is specified a default of word is assumed The data which has to be searched for may be preceeeded by a to look only for locations not containing the value or pattern 3 2 5 BT Syntax BT lt begin gt lt end gt lt count gt lt trigger address gt Description Block test The Block Test comman
150. nal from VME external from VME external from VME external from VME external from VME external from VME 2 4 EMPTY Vector Response The gate array responds to the IACK cycle of the presenting an interrup channel vector which logic or the external device t vector This is normally the int is decoded by the gate array int vector supplied by the interrupt In order to guarantee that the interrupt channel which CPU by terrup terrup ting is addressed by the processor in the IACK cycle is decoded successfully by the gate array the interrupt source must hold the request stable in the asserted state Care has been taken with the design of the gate array interrupt circuitry to prevent the a timeout bus error if a decoding fault occurs TACK cycle from being terminated with However if an interrupt source could not be decoded in an IACK cycle the gate array always supplies the EMPTY interrupt vector to the processor The EMPTY interrupt vector is assigned to the EMPTY interrupt ch Th th Ln annel and carries the vector number S 3F e EMPTY interrupt channel is a virtual channel which means at there is no interrupt source to trigger this interrupt terrupt status register Accordingly it does not own an interrupt control register or an INTERRUPT MANAGEMENT 2 3 Interrupt Priority Structure The FGA 002 Gate Array interrupt m
151. nal to high level 0 The BSYSBIT contained in the CTL8 register determins the level of the SFAILO signal BIT 6 SPECIAL 6 Only for test purposes This bit must remain cleared to 0 BIT 5 SPECIAL 5 1 Shared RAM functions enabled 0 Shared RAM functions disabled BIT 4 SPECIAL 4 1 Dual Port RAM functions enabled 0 Dual Port RAM functions disabled SPECIALENA REGISTER FORMAT SFFD00424 BITs 76543210 Byte Kase Reset Value after power up 00 BIT 7 SPECIALENA 1 Enables the SPECIAL register 0 Disables the SPECIAL register ISLOCALx REGI STER FORMAT BITs 76543210 Byte ae an Reset Value 80 BIT 7 ISLOCALxX ISLOCALO ISLOCAL1 ISLOCAL2 ISLOCAL3 ISLOCAL4 ISLOCALS5 ISLOCAL6 ISLOCAL7 Read Access LOCALX Interrupt Stat interrupt 0 LOCALx interrupt Write Access Clears the edge triggered LOCALx interrupt 52 SFF SFF SFF SFF SFF SFF SFF SFF OW JOJO IOU OU O sO tus readback cleared pending OJlO sO sO sO sO sO O ISTIMO REGISTER FORMAT BITs Byte 76543210 Reset Value BIT 7 ST MO SFFD0O04A0 Read Access Interrupt Status readback 1 TIMERO interrupt cleared 0 TIMERO interrupt pending Write Access Clears the TimerO interrupt ISDMANORM REGISTER FORMAT BITs 76543210 Byte SS gt SS Rese
152. ndary bus with 16 bit data bus width A valid decoding of this area is indicated by the output signal CSVSB 1 11 THE CPU INTERFACE 1 7 The SYSTEM EPROM area is decoded in SFFO00000 SYSTEM EPROM Decoding Area 0 the address range SFF7FFFF The Gate Array pin CSPROM is low when this area is decoded area are allowed By default However accesses as well hardware configurations The enable bit SEPROMWRITE only read accesses a control bit can be programmed to enable This feature may be useful to this write L in special board EPROM area is contained in the register CTL14 for write accesses to the SYSTEM 1 7 0 1 Register CTL14 Register Mnemonic Address R W Default Control 14 Register CTL14 FFD00354 R W 00 Format of CTL14 7 6 5 4 2 1 0 SEPROM WRITE BSCUT VMEDTACKEVAL DSVMEWRITE ASTOVME 7 SEPROMWRITE This bit selects if the SYSTEM EPROM area is also decoded for write cycles 1 read and write cycles possible O only read cycles possible THE CPU INTERFACE T 7 1 SYSTEM EPROM DSACK Control Access cycles to the SYSTEM EPROM area will be terminated by a Long Word The timing of the register This regist has to insert befor th After reset r selects the number of waitst cycle will be terminat the CTL9 register is cleared generation for SYSTEM EPROM acces
153. ne 4 4 6 Other IRQ Control Sets up miscellaneous IRQ controls This routine also initializes the 680XX IRQ handler in the vector page NOTE May only be called in the SUPERVISOR mode int fga_util unsigned long othirq unsigned long onum unsigned long oflag unsigned long olevel char handler othirg 14 20 FGA 002A Boot Software Version 4 onum 0 timer 1 3 reserved 4 DMA normal 5 DMA error oflag 0 to disable IRQ 1 to enable IRQ olevel interrupt request level code handler address of the irq handling routine 4 5 Miscellaneous 4 5 1 Receive 4 bytes FMB Message and Jump to this Address This routine is useful when downloading software to the DPR and starting afterwards int fga_util unsigned long getmsg getmsg 17 4 5 2 Set DPR Address Parameters This routine sets the address and range parameters for the onboard dual ported gated memory int fga_util unsigned long setdpr unsigned long locdprbas unsigned long vmedprbas unsigned long vmedprtop setdpr 18 locdprbas local DPR base address vmedprbas VMEbus DPR base address vmedprtop VMEbus DPR top address 4 5 3 Convert Number to Hex String Converts a binary number byte word or long to a hex ASCII string int fga_util unsigned long hexas unsigned long mode unsigned long number char string hexas 19 mode 1 byte 2 word 4 long 10 should be added to precede with blanks 21 FORCE COMPUTERS number binary n
154. nputs FC2 0 of the gate array The CPU uses the FC2 0 signals to select the address space for every bus cycle it is executing According to the address space encodings which are defined for 680x0 processors the AM codes outlined in table 2 2 may be generated when the CPU accesses the specified ranges for VMEbus areas THE VME INTERFACE Table 2 2 Supported Address Modifier Codes for CPU access the VMEbus areas Range Area Addressing AM Capability Code 543210 0000 0000 SPA 001110 Extended A32 SDA 00110 NPA 001010 FAFF FFFF NDA 00100 FBOO 0000 SPA 10 Standard A24 SDA 101 NPA 1010 FBFE FFFF NDA 101 FBFF XXXX Short A16 SDA 10110 NDA 10100 FCOO 0000 SPA 0 Standard A24 SDA 01 NPA 010 FCFE FFFF NDA 1001 FCFF XXXX Short A16 SDA 10110 NDA 10100 SPA Supervisor Program Access SDA Supervisor Data Access NPA Non Privileged Program Access NDA Non Privileged Data Access t THE VME INTERFACE 2 Th in 4 Data Transfer Capability e basic data transfer capabilities of the VMEbus master terfac ar defined as D32 MASTER D16 MASTER and D08 MASTER Th an Th in e D32 MASTER capability includes the D16 and D08 capability d the D16 MASTER capability includes the D08 capability e master interface of the gate array provides fo
155. ntroller IL handler option is disabled ows the board operation on the detection depending on the configuration of MISCELLANEOUS The board is The board is not ACFAIL Handler the ACFAIL Handler HANDLER bit HANDLER bit 0 VMEbus The VMEbus will Bus cannot be Request be granted on the requested request VMEbus Bus will not be Bus will be Release released except by released the DMA controller immediately 3 1 Register CTL8 Register Mnemonic Address R W Default Control 8 Register CTL8 SFFD00278 R W 00 Format of CTL8 7 6 5 4 3 2 0 BSYSBIT SSYSBIT FAIR HANDLER 0 HANDLER The ACFAIL handler bit is used to select the handler option 1 The board is ACFAIL handler 0 The board is not ACFAIL handler MISCELLANEOUS 4 SYSFAIL 4 1 SYSFAIL Input The gate array provides the SFA the VMEbus signal SYSFAI monitor The level of it is enabled If this input is asserted low interrupt if INTERRUPT MANAGEMENT for the the SFA I L ELA input refer to the which is used to the gate array will generate an please interrupt section initialization input can be read back locally at the
156. nts coming in on the BRVMEI input pin The mastership will be given to the requester which is detected earlier If the bus is granted to an external requester the BGVMEO pin of the gate array will be asserted Otherwise the BBSYO output signal will be driven to 0 reflecting that the bus is allocated for processor or DMA controller operation If the internal arbiter module is disabled the gate array will occupy the VMEbus when it has asserted the BRVMEO pin to signal its mastership request and detects a falling edge on the BGVMEI input signal The mastership is taken over by the gate array in driving the BBSYO output to 0 When the gate array receives the BGVMEI signal asserted while it has no bus request pending the BGVMEI signal is passed on to the BGVMEO output permitting further requesters to take control of the VMEbus The internal arbiter module can be reset only with the VMEbus signal SYSRES THE VME INTERFACE 2 5 1 Automatic Re Arbitration The internal single level arbiter prevents a hangup of the VMEbus in the case where a master has requested control of the VMEbus and does not respond to the busgrant by driving the BBSY signal line low The bus will be re arbitrated if the arbitration cycle is not terminated within 32 microseconds by the assertion of the VMEbus signal BBSY After this time BGVMEO 2 5
157. o be initialized with the start address of the destination port I rate the destination addressing sequence It and the 31 24 23 t6115 8 7 Destination Address THE 32 BIT DMA CONTROLLER 3 3 8 Transfer Count Register DMATRFCNT The 32 bit wide Transfer Count Register DMATRFCNT is used to define the number of bytes to be transferred in a DMA task The contents of the Transfer Count Register after reset or after a successful completion of the If a transfer cycle is terminated by a bus error or the DMA was the register holds the remaining ler was not able to transfer forced to stop the operation number of bytes the DMA Control DMA job are SFFFFFFFF 31 24 23 161 15 Byte Transfer Count 3 3 9 Interrupt Control Register Normal Termination ICRDMANOR The ICRDMANOR control register interrupt channel DMA Normal is for interrupt Please refer to the section more details used to configure the the normal termination INTERRUPT MANAGEMENT for 7 6 5 4 3 2 1 0 IRQ a a Enable IRQ Level 3 IRQ Enable The bit enables or disables the interrupt channel 1 Interrupt channel is enabled O Interrupt channel is disabled 2 0 IRQ Level This bit field defines the interrupt request level 000 N
158. o level selected 001 Level 1 010 Level 2 01 Level 3 100 Level 4 101 Level 5 110 Level 6 1 Level 7 3 8 THE 32 BIT DMA CONTROLLER Interrupt Control Register Error Termination ICRDMAERR 3 3 10 The ICRDMAERR control register is interrupt channel DMA Error which termination interrupt MANAGEMENT for more details used to Please refer to the section configure is assigned to the error INTERRUPT the 6 5 4 3 2 0 IRQ Enable IRQ Level 3 IRQ Enable The bit enables or disables the interrupt channel 1 Interrupt channel is enabled 0 Interrupt channel is disabled 2 0 IRQ Level This bit field defines the interrupt request level 00 Interrupt disabled 001 Level 1 O1 Level 2 011 Level 3 10 Level 4 101 Level 5 11 Level 6 Level 7 THE 32 BIT DMA CONTROLLER 3 3 11 Interrupt Status Register Normal Termination ISDMANORM The ISDMANORM status register contains the IRQ Status bit for the Normal termination interrupt The bit indicates zero if the interrupt request is pending A write access to the status register location clears the normal termination interrupt The written data will be ignored 7 6 5 4 3 2 1 0 IRQ Status a i a a oi 7 IRQ Status The IRQ Status reg
159. ol 6 Register CTL6 SFFD00270 R W 00 Format of CTL6 z MYDSACK 3 0 MYDSACK This bit field selects the number of wait states for access cycles to the gate array registers 0000 4 Waitstate DSACK 0001 0 Waitstate DSACK 0010 1 Waitstate DSACK 0100 2 Waitstate DSACK 1000 3 Waitstate DSACK THE CPU INTERFACE 1 10 BOOT DECODING FEATURES After the gate array has been reset the normal address decoding structure will be disabled and a special area decoding BOOT decoding is active This BOOT decoding comes into effect when the BOOTFLAG is zero The decoding is used to support the boot procedure for the processor The BOOTFLAG is a readable writable register bit which is cleared to 0 after every boot reset The BOOTFLAG is bit 0 of the CTL4 Register in the Gate Array As long as the BOOTFLAG 0 the decoding structure is changed in such way that the LOCAL I O Area will be selected in the whole 32 bit address space When the BOOT decoding is active the LOCAL I O Interface has the timing parameters of the BOOT EPROM page The BOOT EPROM and the Gate Array itself are always accessible at their correct address according to the LOCAL I O Page decoding address map In order to boot the 680X0 processors from the address 0 the BOOT EPROM must to be the only device selected when th BOOTFLAG
160. ompared seconed a ONE is shifted LONG PATTER TEST Fill the memory block with a byte pattern read it back and compare LONG SHIFT TEST This test is performed only for some long words of the memory block First a ZERO is shifted over the long word read back and compared seconed a ONE is shifted OPCODE TEST A test subroutine is copied into the memory block and executed Note this test is executed only if no error occurred before and only if the begin is word aligned RMW TEST A read modify write test is executed using TAS and CAS instructions There are two possibilities to execute the PATTERN TESTS e Fill the whole memory area to be tested with a pattern then read it back and compare e Test each byte word or long separately This means write a pattern to a memory location read it back and compare Before starting the memory tests this question has to be answered The DEFAULT is the first possibility fill the whole memory area with a pattern then read it back and compare The Block Test may be quit earlier after each loop by entering ESCAPE 3 2 6 BV Syntax BV lt begin gt lt end gt lt destination gt Description Block verify This command compares two blocks of memory If the specified blocks are not equal the different values and the memory address is displayed 3 2 7 EXIT Syntax EXIT Description Exit Debugger EXIT exits the debugger and starts the firmware 3 2 8 FC68165INIT Syntax FC68165I
161. on 0000 4 FB40 Ident 0004 4 Checksum 0005 1 20 FGA 002A register SPECIAL 000B 1 0C FGA 002A register CTL5 000E 1 40 FGA 002A register CTL15 0010 1 00 FGA 002A register ICRMBOXO 0011 1 00 FGA 002A register ICRMBOX1 0012 1 00 FGA 002A register ICRMBOX2 0013 1 00 FGA 002A register ICRMBOX3 0014 1 00 FGA 002A register ICRMBOX4 0015 1 00 FGA 002A register ICRMBOX5 0016 1 00 FGA 002A register ICRMBOX6 0017 1 00 FGA 002A register ICRMBOX7 0019 1 01 FGA 002A register ICRVME1 0014 1 02 FGA 002A register ICRVME2 001B 1 03 FGA 002A register ICRVME3 001C 1 04 FGA 002A register ICRVME4 001D 1 05 FGA 002A register ICRVME5 001E 1 06 FGA 002A register ICRVME6 001F 1 07 FGA 002A register ICORVME7 0020 1 00 FGA 002A register ICRTIMO 0021 1 00 FGA 002A register ICRDMANORM 0022 1 00 FGA 002A register ICRDMAERR 0023 1 00 FGA 002A register ICRFMBOREF 0024 1 00 FGA 002A register ICRFMBIREF 0025 1 00 FGA 002A register ICRFMBOMES 0026 1 00 FGA 002A register ICRFMBIMES 0027 1 0C FGA 002A register CTL3 FGA 002A Boot Software Version 4 Offset Byte Default Description 0028 1 00 FGA 002A register ICRPARITY 0029 1 00 FGA 002A register CTL7 002A 1 00 FGA 002A register CTL8 002C 1 00 FGA 002A register ICRABORT 002D 1 00 FGA 002A register ICRACFAIL 002E 1 00 FGA 002A register ICRSYSFAIL 002F 1 00 FGA 002A register ICRLOCALO 0030 1 00 FGA 002A register ICRLOCA
162. ontrol 8 Register CTL8 SFFD00278 R W 00 Format of CTL8 7 6 5 4 3 2 1 0 z BSYSBIT SSYSBIT FAIR HANDLER 2 SSYSBIT The bit asserts or releases the SFAILO output signal p SFAILO signal is asserted low 0 SFAILO signal is negated high 4 2 3 Watchdog Sysfail The watchdog sysfail can be generated by the gate array timer when the sysfail control bit in the timer control register enables this function The sysfail output signal SFAILO will be driven if the timer interrupt has been triggered The sysfail signal is released when the timer interrupt is cleared A write access to the timer interrupt status register STIMO clears the interrupt and negates the sysfail signal The written data is ignored MISCELLANEOUS This page was intentionally left blank MISCELLANEOUS 5 LOCAL SWITCH Input A low level applied to the LOCSW input of the gate array will disable the operation of the local processor by generating a processor reset signal The main memory and the gate array will not be accessible from the VMEbus side since the gate array is also reset and therefore the software selectable decoding areas are disabled VMEbus operation is not affected by the local switch function since neither a VME reset is generated by the gate array nor will the single level arbiter be in
163. option bit in the register CTL8 which is used to define a certain board in a system as the ACFAIL handler board If the ACFAIL handler option is disabled HANDLER bit 0 the gate array will be prevented from requesting the VMEbus if an active power fail signal is pending More details can be found in the section MISCELLANEOUS where the ACFAIL Handler option is described completely 2 6 2 FAIR request option The VMEbus specifies four bus request levels To support several requesters on an individual level a bus grant daisy chain is assigned to each request level On a specific level the priority of bus allocation is determined by the position of each requester within the bus grant daisy chain In system configurations where requesters are arbitrated on a single level low prioritized masters might have problems with getting mastership on the VMEbus This difficulty can be solved when a special protocol for requests to the VMEbus is practiced but this requires that the protocol is respected by all requesters on the VMEbus The gate array supports this protocol by offering the FAIR request option THE VME INTERFACE When the FAIR request option is enabled the gate array will not request VMEbus mastership until the bus request line BRx of the VMEbus is released by all requesters This is the beginning of a new arbitration round Eac
164. p line if the RBCLR signal is recognized input pin The CTL7 register provides bit The bus will be released immediately after the processor has finishe d the current cycle An active read modify write cycle on the VMEbus will not be interru The Release On BUSCLEAR function is enabled after reset pted 2 7 2 1 Register CTL7 Register Mnemonic Address R W Default Control 7 Register CTE FFD00274 R W 00 Format of CTL7 7 6 5 4 2 1 0 RBCLR RORINH I 3 RBCLR Release On Busclear option bit T disables RBCLR function 0 enables RBCLR function THE VME INTERFACE 2 7 3 Release Voluntary RV If the local processor is bus master on the VMEbus the release on request counter inhibits the gate array from releasing the bus for the specified time See ROR function After this time has passed the gate array may release the bus voluntary if the local cpu does not perform accesses to the VMEbus within a 100 microsecond time period After each new access to VME this 100 us time period has to pass until the bus will be released voluntary 2 7 4 Release on ACFAIL RACFAIL The gate array releases the VMEbus mastership on the detect ion of a power failure immediately after the processor has finished its current bus cycle The power fail signal is sampled on the ACFAIL input pin and is normall
165. quest int fga_util unsigned long auxpin unsigned long areq unsigned long rdy unsigned long ack unsigned long req auxpin 0 areq 0 1 disable enable autorequest rdy 0 1 active level ack 0 1 active level req 0 1 active level 4 1 2 AUX Source Cycle Control This routine is used to initialize the AUX port to serve as the DMA source int fga_util unsigned long auxsrc unsigned long wtim unsigned long sstrt unsigned long sterm 15 FORCE COMPUTERS auxsrc 1 rtim AUX fifo write timing FGA 002 register AUXSRCWEX sstrt AUX source cycle start FGA 002 register AUXSRCSTART sterm AUX source cycle termination FGA 002 register AUXSRCTERM 4 1 3 AUX Destination Cycle Control This function is used to initialize the AUX port to serve as the DMA destination int fga_util unsigned long auxdst unsigned long rtim unsigned long dstrt unsigned long dterm auxdst 2 wtim AUX fifo read timing FGA 002 register AUXDSTREX dstrt AUX destination cycle start FGA 002 register AUXDSTSTART dterm AUX destination cycle termination FGA 002 register AUXDSTTERM 4 2 DMA Channel Dependent Functions 4 2 1 DMA Source Descriptor Set up DMA source descriptor with source attribute and source address int fga_util unsigned long dmasrc unsigned long sattr unsigned long saddr dmasrc 3 sattr DMA source attribute FGA 002 register DMASRCATT saddr DMA source address FGA 002 register DMASRCADDR 4 2 2 DMA De
166. quests are level sensitive inputs The interrupt is active when the input signal is asserted low The VMEbus interrupt channels have no associated interrupt status registers As in the case for all other interrupt sources the gate array can map the VMEbus interrupts to any interrupt level for the CPU INTERRUPT MANAGEMENT INTERRUPT ACKNOWLEDGE The FGA 002 gate array decodes interrupt acknowledge cycles from the processor and responds to the cycle by presenting an interrupt vector on the data pins DCPU31 DCPU24 The vector which is presented to the may be supplied by the gate array internal interrupt logic processor or by the External Vect external interrupter for the local interrupts LOCAL4 LOCAL7 The vector which is supplied by an transmitted by the gate array from the LOCAL the CPU data bus tor response is supported for the VMEbus interrupts and external interrupter is I O bus or the VMEbus to VMEbus interrupts are supported as external vector responses The gate array requires the interrupt vec data pins vector is DVMEO DVME7 of the gate array presented to the CPU data pins 2 2 1 Internal Vector Response When the gate array responds to an interr an Internal Vector it places the vector number of the acknowledged interrupt DCPU24 uppermost channel on the CPU data pins vector bits determining the DCPU24 D
167. r Format MBOX 0 7 The following chart outlines the mailbox register format for MBOX O 7 7 6 5 4 3 2 i 0 DATA 7 DATA The bit reflects the contents of the Mailbox 1 is returned if the Mailbox is already occupied 0 is returned if a released Mailbox could be occupied successfully 4 3 Mailbox Access from VMEbus Side From VME side the Mailboxes are accessible within the decoding page for VME accesses to the FGA 002 Gate array This area is software programmable in the register MYVMEPAGE Address SFFD002FC which defines the decoding page for all VME accesses to the FGA 002 Gate Array Accesses from VMEbus side can be performed in the short address range with the SHORT USER and or SHORT SUPERVISOR Address Modifier Code The Address Modifier code selection can be made in the register CTL5 Address SFFD00264 by the bits 3 and 2 Please refer to the VME Slave Interface chapter of section 1 CPU AND VME INTERFACE for more information about accesses to the FGA 002 gate array from VME side In read accesses to the Mailboxes from VME the data is driven from the DVME15 signal of the gate array to the data line D15 on the VMEbus If the Mailbox locations are accessed with a Byte or Word operand the data appears at the position of the most Significant bit of the operand Otherwise with long operands the data appears at
168. r execution of the FGA 002A Boot Software the firmware is started Registers D0 D7 A0 A6 and the VBR are cleared The default start address of the firmware can be changed in the Boot EPROM Therefore the address at offset 10 is to patch Inserting a 0 the default makes the FGA 002A Boot Software jump to the default firmware start Any other address inserted leads to fetch the data from this address The firmware acts as if the FGA 002A Boot Software is not present Therefore at the beginning the stack pointer and the program counter must be located 26 FGA 002A Boot Software Version 4 A Incompatibilities to Previous Versions It is no longer possible to set Fair VMEbus Arbitration via the rotary switches It is no longer possible to set the VMEbus width via the rotary switches Setting the ACFAIL handler via the rotary switches is no longer possible The SRAM location named Ident has changed from FGA2 to FB40 Because of this the SRAM content is always invalid on the very first start of this FGA 002A Boot Software even if the SRAM content was valid for the previous boot software version 3 The following utility calls are no longer supported chk sum cpu_info putmsg putchar dinit getchar getline set ram ch sram version dmapage dmajob There is no longer a fixed address for the user program Please refer to section 5 for details 27
169. r the simultaneous transfer of 32 bit 16 bit and 8 bit operands addition 24 bit data can be transferred if an unaligned transfer cycle makes this necessary The support of all defined un Th wh aligned transfer types results in a reduction of bus cycles e data transfer capability is defined by the VMEbus areas ich are addressed for the transfer cycles Together with the addressing capabilities of the areas a comprehensive f exibility is provided Th in in In e various VME areas and their capabilities allow easy terfacing of peripheral boards with different data bus sizes a single VMEbus system addition to the data transfer capabilities specified in table 2 3 a general limitation for all VMEbus areas to the D16 MASTER capability can be chosen This option is selected by a register bit and is described in the chapter D16 MASTER Option Tables 2 3 and 2 4 summarize the supported data transfer types of the VMEbus interface with either the D16 D08 MASTER capability or the D32 D16 D08 capability THE VME INTERFACE Table 2 3 Supported Data Transfer Types for D16 MASTER and DO8 MASTER capability Transfer Type D31 24 D23 16 D15 08 DO7 00 Byte Byte Byte Byte 2 x Byte Word Byte 0 1 x x Byte 2 3 x x RMW Byte Byte Byte Byte 2 x Byte RMW Word Byte 0 1 x x Byte 2 3 x x
170. red with the CPU address signals A31 A24 1 3 4 2 Register MAINUM 7 6 5 4 3 2 1 0 B23 B22 B21 B20 B19 B18 B17 B16 Eee B23 B16 These bits are used to select the Upper Middle byte of the main memory base address The bits will be compared with the CPU address Signals A23 A16 1 9 THE CPU INTERFACE 1 3 5 The MAIN MEMORY DSACK STERM Access cycles to the MAI IN MEMORY area are terminated either with the DSACKx signals for a long word port or with the synchronous STERM output signal generated by the gate array The timing of the signals can be selected by the registers CTL11 for the The timing is given as DSACK signal and CTL16 for the STERM signal a number of waitstates which the processor has to insert b Three timing opt STERM signal fore the cycle will be terminated tions are offered for the DSACK signals and the After reset the registers are cleared to zero and no termination mode is selected 1 23 53 Register CTL11 7 6 5 4 3 2 T 0 MAIN ENA MAIN DSACK S27 S26 S25 S24 6 4 MAINDSACK This bit field is used to select the DSACK timing for an access to the local MAIN MEMORY 000 No DSACK Generation 001 O Waitstate DSACK 010 1 Waitstate DSACK 100 2 Waitstate DSACK 1 3 5 2 Register CTL16 7 6 5 4 3 2 1
171. reserved for the BOOT EPROM device A byte DSACK signal is generated for this page Please refer to the chapter BOOT Decoding Features for more details 1 8 8 LOCAL I O Page E FFFX XXXX This page is usable as a special decoding area and for devices whose timing does not meet the protocols provided for the timed LOCAL I O pages Since the interface does nothing if this page is addressed the device has to be directly connected to the CPU data bus An access to this address range is indicated by a low CSLIO signal The FGA 002 Gate Array does not generate a DSACK for this page 1 9 ACCESS TO FGA 002 REGISTERS The FGA 002 Gate Array Registers can only be accessed via the cpu interface of the gate array The address range which decodes the gate array registers is located within the LOCAL I O Area from FFD00000 to SFFDFFFFF The 8 bit registers can be accessed with byte word or longword operand sizes 32 bit registers must be accessed with longword operands THE CPU INTERFACE 1 9 1 The 680X0 processor famil Supervisor operation privilege leve the access to In which privilege vel Supervisor User Access register CTL1 level ly defines two privileged privilege and Bit 3 of the register CTL1 selects type or Supervisor and User access type to be valid in After reset ith Eve hy the processor ha
172. rupt sources and their assigned interrupt channels Interrupt Source Interrupt Channel DMA CONTROLLER Normal Termination Interrupt DMA Normal Error Termination Interrupt DMA Error TIMER Timer Interrupt Timer FORCE MESSAGE BROADCAST ChannelO Message Interrupt FMBO Message Channell Message Interrupt FMB1 Message ChannelO Refused Interrupt FMBO Refused Channell Refused Interrupt FMB1 Refused PARITY ERROR Parity Error Interrupt PARITY Error MATLBOXES Mailbox 0 Interrupt Mailbox 0 Mailbox 1 Interrupt Mailbox 1 Mailbox 2 Interrupt Mailbox 2 Mailbox 3 Interrupt Mailbox 3 Mailbox 4 Interrupt Mailbox 4 Mailbox 5 Interrupt Mailbox 5 Mailbox 6 Interrupt Mailbox 6 Mailbox 7 Interrupt Mailbox 7 INTERRUPT MANAGEMENT 2 1 1 1 DMA CONTROLLER Two interrupts are assigned to the DMA controller Normal termination interrupt Error termination interrupt erri The DMA controller generates a normal termination interrupt request if its task is successfully terminated An error termination interrupt occurs if the DMA operation is aborted by a stop command The stop command is issued if bit 0 in the DMARUNCTL register is written with 0 Also the DMA operation is forced to stop when a bus error condition occurs The active interrupt state is when bit
173. rupt request with a write e interrupt status register can be accomplished with any data 1 2 2 UTILITY INTERRUPTS e utility interrupt inputs for ABORT ACFAIL and SYSFAI access to L can be sensitive configured like the local interrupt inputs as edge level tion has to be programmed in an th Wh st in Th wh d high low active inputs The configurat e corresponding extended interrupt cont trol register en a utility interrupt input is configured edge sensitive the atus of a pending interrupt can be read at the location of the terrupt status register bit 7 e status bit indicates low if the interrupt is pending and high en no interrupt is pending INTERRUPT MANAGEMENT Edge sensitive utility interrupts can be cleared by a write access data is ignored to the respective status register location or automatically in the acknowledge cycle if the autoclear option is nabled s xtended interrupt control register The active state of level sensitive ABORT ACFAIL and SYSFAIL interrupt inputs can be identified by reading back the instantaneous level of the respective input pin The level is read back at bit 7 of the following registers locations Register Address ABORTPIN SFFDO04D4 ACFAILPIN SFFDO04D8 SFATLINPIN SFFDOO4DC 2 1 2 3 VME INTERRUPTS The inputs provided for VMEbus interrupt re
174. s Chapters have been edited as indicated below Section 1 INTRODUCTION Chapter 1 1 Connected signals Under PROCESSOR Signals AS DS has been changed to AS ECS STERM has been changed to STERM CIIN CINOUT Under FGA 002 Signals ASCPU DSCPU has been changed to ASCPU ECS STERM has been changed to STERM INHIN INHOUT Section 1 INTRODUCTION Chapter 2 The VMEbus Interface Under FGA 002 Signals VIRQ 7 0 is now VIRQ Aa le Revision 3 Section 10 The FGA 002 Gate Array Boot Software has been updated to comply with the FGA 002 boot software Version 3 1 Revision 4 Section 3 Interrupt Management Page 2 23 O and 1 were switched by Autoclear Section 4 The 32 Bit DMA Controller Page 3 4 O and 1 were switched by bits 3 amp 4 of the attribute code Section 9 Register Format Short Description Page 8 Bits 0 1 and 2 were switched Page 30 Bit 1 was added Page 31 Bits 3 4 5 6 and 7 were added Revision 5 Section 2 The VME Interface Page 2 5 Table 2 2 corrected for Standard A24 NDA CPU AND VME INTERFACE This page was intentionally left blank THE CPU AND VME INTERFACE TABLE OF CONTENTS
175. s to perform a legal the gate array is defined by bit 3 of the control the CTL1 register bits are cleared to 0 This selects both the User and the Supervisor privilege levels as being valid access types levels of the User Supervisor access If the bit is cleared the gate array can be accessed not only the Supervisor access mode but also in the User access mode The Supervisor privilege level is selected if the bit is set to 1 9 1 1 Register CTL1 Register Mnemonic Address R W Default Control 1 Register CTL1 SFFD00238 R W 00 Format of CTL1 7 6 5 4 3 2 I 0 SUP z USR ARBITER CSCO 3 SUP USR The bit selects the access mode to the FGA 002 registers 1 Access only in Supervisor mode O Access in Supervisor and User mode THE CPU INTERFACE 1 9 2 DSACK Control The gate array terminates an access to its registers by asserting the DSACKO and DSACK1 output pins to 0 indicating a Long Word port size to the processor The timing of the DSACKx signals is software selectable by the register CTL6 This register is used to select the number of waitstates the processor has to insert before the cycle is complete After reset the CTL6 register is cleared to 0 and the gate array will terminate bus cycles with 4 waitstates 1 9 2 1 Register CTL6 Register Mnemonic Address R W Default Contr
176. sed ISFMBOREF SFFD004B8 R W 80 Int Status FMB1 Message ISFMB1MES SFFDO04E4 R W 80 Int Status FMB1 Refused ISFMB1REF SFFDOO4BC R W 80 MessageReadout Channel0 FMBCHO SFFDCOO000 R MessageReadout Channell FMBCH1 SFFDCO0004 R 6 3 FMB Register Description 6 3 1 FMB Control Register FMBCTL The FMBCTL register is a general control register for both channels the FMBO channel and FMB1 channel The bit field 4 0 is used to store the slot which corresponds to the slot board is installed in the VMEbus system Bits 5 and 6 enables disables the FMB channels 0 and 1 for 7 selects if the FMB cycle is to be number wher FMB cycles performed with the th Bit Address Modifier Code for Extended Supervisory data access 0D or also with the AM Code for Extended Non Privileged Data Access 09 FORCE MESSAGE BROADCAST FMB Format of FMBCTL 7 6 4 3 2 il USER MODE ENACH ENACHO SLOT CODE 7 USERMODE This bit selects the Address Modifier code which the master has to send to address the FMB slave in an FMB cycle 1 FMB slave is accessible with Extended User Supervisor Data Access AM Code 0D 09 0 FMB slave is accessible only with Extended Supervisory Data Access AM Code SOD 6 ENACH1 This bit enables or disables the FMB Channel 1 for FMB cycles 1 Enabled 0 Disabled 5 ENACHO This
177. ses is disabled by defa DSACK signal generated by the Gate Array DSACK signals can be selected in the CTL9 ed to 0 and the ates the processor DSACK Wilt 1 7 1 1 Register CTL9 Register Mnemonic Address R W Default Control 9 Register CTL9Y SFFDOO27C R W 00 Format of CTL9 4 6 5 4 3 2 1 0 RESET OPTION SEPROMDSACK 2 0 SEPROMDSACK This bit field selects the number of waitstates for data cycles to the SYSTEM EPROM decoding area 000 No DSACK Generation 001 0 Waitstate DSACK 010 1 Waitstate DSACK 011 2 Waitstate DSACK 100 3 Waitstate DSACK 10 4 Waitstate DSACK 110 5 Waitstate DSACK 1 6 Waitstate DSACK THE CPU INTERFACE 1 8 LOCAL I O AREA The Gate Array decodes the LOCAL I O Area in the following address range SFF80 0000 SFFFF FFFF The LOCAL I O Area is split into eight pages Six pages can be used to decode onboard devices connected to the Gate Array s byte wide LOCAL I O bus When these pages are accessed the Data transfer to the onboard devices is performed via the LOCAL I O interface of the gate array which executes an individual timing protocol selectable in the register LIOTIMING for the LOCAL I O pages A D One page selects the Gate Array itself and another one a special
178. ss Line Number A2 1 A3 2 A4 3 A5 4 A6 5 A7 6 A8 7 AQ 8 A10 9 A11 10 A12 1 A13 2 A14 3 A15 4 A16 15 A17 16 A18 17 A19 18 A20 19 A21 20 A22 21 FORCE MESSAGE BROADCAST FMB 2 4 The Timing of FMB Cycles 2 4 1 Own Refused Message Cycle If a slave recognises that a message cannot accept of the in Figure 2 1 to abort must stay asserted for th contigu accept the message tha Figure 2 1 DSA input VMEbus as soon as possible Also BERR output t it is addressed as an FMB slave but then the board asserts the BERR signal according to so that all the other FMB slaves a possible fetch of the message data specified time to ous BERR assertion occurs if more than one FMB slave cannot the BERR the timing given have enough time The BERR output make sure that a assertion timing guarantees t all other FMB slaves have enough time to abort the cycle and thus prevent the master from starting a new data cycle as long as the slaves are not ready Refused Cycle Timing Due to Own Decision Table 2 1 Decision Parameter min ns 1 50 2 540 3 0 140 max ns Timing Parameters for a Refused Cycle Due to Own FORCE MESSAGE BROADCAST FMB 2 4 2 Foreign Refused Message Cycle Timing If a slave recognises that it is addressed as an FMB slave and it is ready
179. sses to these pages are terminated with a byte DSACK to the processor 1 8 1 LOCAL I O Page A FF8X XXXX This page selects the LOCAL I O Interface with an access time for R W cycles defin register d by the bits 1 0 of the LIOTIMING 1 8 2 LOCAL I O Page B FF9X XXXX This page selects the LOCAL I O Interface with an access time for R W cycles defin register d by the bits 3 2 of the LIOTIMING 1 8 3 LOCAL I O Page C FFAX XXXX This page selects the LOCAL I O Interface with an access time for R W cycles defin register d by the bits 5 4 of the LIOTIMING 1 8 4 LOCAL I O Page D FFBX XXXX This page selects the LOCAL I O Interface with an access time for R W cycles defin register d by the bits 7 6 of the LIOTIMING 1 15 THE CPU INTERFACE 1 8 5 BOOT SRAM FFCX XXXX This LOCAL I O page is decoded for the BOOT SRAM device A DSACK signal code for an 8 bit port is generated to terminate accesses to this page 1 8 6 THE GATE ARRAY ITSELF FFDX XXXX This page selects the Gate Array itself Cycle termination is performed with long DSACK Accesses to the gate array registers are indicated by a low CSLIO signal For more details please refer to the chapter Access to FGA 002 Registers in this section 1 8 7 BOOT EPROM FFEX XXXX This page is
180. sses will always return a 1 until the 4 1 THE MAILBOXES Mail box is released again performed by a write cycle to the Mailbox location A Mailbox interrupt will go active when a mailbox More detail occu Mail pied lo The release of a mailbox can be cation is box Interrupts 4 2 Mailbox Access from Local Side ls are described later in the chapter From the local side the Mailboxes are accessible at fixed The contents of the Mailboxes ar The contents of a Mailbox is readable in bit 7 of the MBOX registers and is presented on the data pin DCPU31 addr ond OF HE ess locations ata line Silt he gate array presented The following table shows the access address from local side assigned to the Mailboxes Table 4 1 Mailbox Register Addressing Assignment Mailbox Mnemonic Local Address R W Default MAILBOX 0 MBOX0 SFFD80000 R W 00 MAILBOX 1 MBOX1 SFFD80004 R W 00 MAILBOX 2 MBOX2 SFFD80008 R W 00 MAILBOX 3 MBOX3 SFFD8000C R W 00 MAILBOX 4 MBOX4 SFFD80010 R W 00 MAILBOX 5 MBOX5 SFFD80014 R W 00 MAILBOX 6 MBOX6 SFFD80018 R W 00 MAILBOX 7 MBOX7 SFFD8001C R W 00 4 2 1 Mailbox Register Organization The following displays the mailbox register organization 31 24 MBOX 0 7 Mailbox Registers MBOX 0 7 THE MAILBOXES 4 2 2 Mailbox Registe
181. stination Descriptor Set up DMA destination descriptor with destination attribute and destination address int fga_util unsigned long dmadst unsigned long dattr unsigned long daddr dmadst 4 16 FGA 002A Boot Software Version 4 dattr DMA destination attribute FGA 002 register DMADSTATT daddr DMA destination address FGA 002 register DMADSTADDR 4 2 3 DMA Operation Sequence Control Set up the DMA general sequence control int fga_util unsigned long dmactl unsigned long genctl unsigned long tcount dmactl 5 genctl DMA general control FGA 002 register DMAGENERAL tcount DMA byte transfer counter FGA 002 register DMATRECNT 4 2 4 DMA Run Control Start or stop the DMA channel int fga_util unsigned long dmarun unsigned long flag dmarun 6 flag 0 to stop the DMA 1 to start the DMA 4 3 Timer Dependent Functions 4 3 1 Timer Initialization Set up TIMER preload and control register int fga_util unsigned long timinit unsigned long preload unsigned long tctrl timinit 7 preload Timer Preload Value FGA 002 Register TIMOPRELOAD tetrl Timer Control FGA 002 Register TIMOCTL 4 3 2 Timer Run Control Start or stop the timer int fga_util unsigned long timrun unsigned long flag 17 FORCE COMPUTERS timrun 8 flag 0 to stop the timer 1 to start the timer 4 4 IRQ Control Functions 4 4 1 VMEbus IRQ Control Sets up VMEbus IRQ controls This routine also initializes the 680XX IRQ hand
182. t Value 80 BIT 7 ISDMANORM SFFDO04B0 Read Access Interrupt Status readback DMA normal termination interrupt cleared 0 DMA normal termination interrupt pending Write Access Clears the DMA normal termination interrupt ISDMAERR REGISTER FORMAT SFFD004B4 BITs 76543210 Byte SS gt SS Reset Value 80 BIT 7 TSDMAERR Read Access Interrupt Status readback 1 DMA error termination interrupt cleared O DMA error termination interrupt pending Write Access Clears the DMA error termination interrupt SFFDO04B8 ISFMBOREF REGISTER FORMAT BITs 76543210 Byte SoS aS Reset Value 80 BIT 7 ISFMBOREF Read Access Interrupt Status readback FMBO Refused interrupt cleared O FMBO Refused interrupt pending Write Access Clears the FMBO Refused interrupt ISFMB1REF REGISTER FORMAT BITs 76543210 Byte SoS aS Reset Value 80 BIT 7 ISFMB1REF SFFDOO4BC Read Access Interrupt Status readback FMB1 Refused interrupt cleared 0 FMB1 Refused interrupt pending Write Access Clears the FMB1 Refused interrupt ISPARITY REGISTER FORMAT SFFD004CO BITs 76543210 Byte SSS a gt Reset Value 80 BIT 7 SPARITY Read Access Interrupt Status readback PARITY error interrupt cleared O PARITY error interrupt pending
183. t t write cycle clears it t to 0 STANDARD INTERRUPT CONTROL REGI BITs 76543210 Byte XXXX Reset Value 00 BIT 3 IRQENABLE BIT 2 0 ITROLEVEL STER FORMAT _ICRMBOXO ICRMBOX1 ICRMBOX2 ICRMBOX3 ICRMBOX4 ICRMBOX5 ICRMBOX6 ICRMBOX7 ICRVME1 ICRVME2 ICRVME3 ICRVME4 ICRVME5 ICRVME6 ICRVME7 ICRTIMO ICRDMANORM ICRDMAERR ICRFMBOREF ICRFMB1REF ICRFMBOMES ICRFMB1MES ICRPARITY Interrupt SFF SFF SFF SFF SFF SFF SFF SFF SFF SFF SFF SFF SFF SFF SFF SFF SFF SFF SFF SFF SFF SFF SFF OII IL OU OI OU TO JOJO JOJO JO sO yO JOJO JU TO OU JO JO yO JO 000 DIDIO OCJOJOJOIOI O OJO oO NIN N OJojJoj e gt j Q Joo 00 N ED channel is enabled channel is disabled 0 Interrupt 000 No level selected 001 Level 010 Level 011 Level 100 Level 101 Level 110 Level 11 Level YANO BWNE Interrupt Request Level Code EXTENDED INTERRUPT CONTROL REG BITs 76543210 Byte XXXXXXXX Reset Value 00 BIT 7 BIT 6 EDGE LEVEL BIT 5 ACTIVITY BIT 4 AUTOCLEAR BIT 3 TROENABLE BIT 2 TROLEVEL STER FORMAT ICRABORT ICRACFAIL ICRSYSFAIL ICRLOCALO ICRLOCAL1 ICRLOCAL2 ICRLOCAL3 ICRLOCAL4 ICRLOCAL5 ICRLOCAL6 ICRLOCAL7
184. ter may not be clocked if the start stop period is shorter than the selected source clock period Of course toggling the start stop bit does not clock the counter The timer operating modes are controlled by the AUTOPRELOAD and the ZEROSTOP bits The ZEROSTOP bit determines if the counter terminates when it has reached the zerocount or continues counting If the bit is set to 1 the timer continues counting and the further action is determined by the contents of the AUTOPRELOAD bit 4 1 THE TIMER When the AUTOPRELA decrement decrement 1 to 00 e value SFF Otherwise the coun very D bit is set the timer will be loaded by value stored in the TIMOPRELOAD register ts from SO ting to th time the coun ter wraps aro the ter und The synchronous 8 bit Timer Counter is loaded with the contents of the timer preload registi timer count register The dat ignored The counter state IMOCOUNT T is readable ter on every write access to the ta written to this location will be Since the contents of the counter are latched data is always valid The following chart outlines th Timer Interrupt Timer Interrupt Registers timer is running in the timer count register the It is permitted to perform read write accesses to the Timer Count Register when th timer interrupt registers
185. terface The selection is to be made in register CTL3 by the bit named the bit selects no limitation and the data transfer capabilities of the areas are available as predefined OPT16 After reset THE VME INTERFACE 2 4 1 1 Register CTL3 Register Mnemonic Address R W Default Control 3 Register CTE SFFD00250 R W 00 Format of CTL3 7 6 5 4 3 2 il 0 VECTOR BIT 7 BIT 6 VSBENA OPT16 0 OPT16 This bit selects if the VMEbus master interface supports only D16 D08 data transfer capability 1 VME data transfer capability is limited to 16 8 Bit cycle types O VME data transfer capability is according to the VME areas THE VME INTERFACE 2 4 2 Support for Unaligned RMW cycles The VMEbus specification allows Read Modify Write cycles to be executed only if they are aligned This is guaranteed by the gate array which supports VMEbus compatible RMW cycles according to the data transfer types outlined in table 2 4 If a RMW operation by the cpu were to generate unaligned transfer types on the VMEbus the cycle would be terminated by a bus error signal to the cpu The gate array would not initiate a cycle to the VMEbus This is the default setting of the gate array after reset However unaligned RMW cycle support can be selected by the URMW option bit in the CTL16 register When this bit is set all RMW cycles w
186. the transfer of 8 16 or 32 bit data operands All basic transfer types as well as read modify write and unaligned transfers are provided Although unaligned read modify write cycles are not defined in the VMEbus specification the gate array is able to accomplish this operation by using VMEbus compatible cycles The register bit URMW of the CTL16 register enables this option The specified ranges have the addressing capabilities of Short A16 Standard A24 and Extended A32 addressing Together with the appropriate Address Modifier generation all peripheral VMEbus boards can be addressed To provide high data throughput on the VMEbus the gate array has implemented th D32 D16 and D08 MASTER data transfer capabilities They are specified for each decoding area Assigned to the various VMEbus decoding areas the available capabilities allow the use of slave boards with different data bus sizes in a single VMEbus system Additionally these features allow for a maximum data transfer rate and may avoid additional overhead in the software 2 3 Addressing Capability The decoding logic of the gate array identifies accesses to the address ranges outlined in table 2 1 as VMEbus areas Each VMEbus area has a specific addressing and data transfer capability assigned to it The addressing capability of the various areas is supported by an address modifier code which will be generated in addition
187. this register have to be programmed according to the external hardware configuration INTERRUPT CHANNEL VECTOR NUMBER LOCAL4 34 or from Local I O bus LOCALS 35 or from Local I O bus LOCAL6 36 or from Local I O bus LOCAL7 37 or from Local I O bus When internal vector response is selected the associated vector number of the acknowledged interrupt channel is presented to the processor For external vector response the gate array fetches the interrupt vector on the Local I O bus and transmits it to the CPU data bus In this case th xternal device connected to the Local I O data bus of the gate array has to provide the interrupt vector The third selection is that the gate array does not respond to the IACK cycle of the processor This mode supports interrupting devices which are directly connected to the CPU data bus External interrupters connected to the LOCAL4 LOCAL7 interrupt channels are supported by the gate array s four acknowledge outputs LIACK 4 7 respectively A LIACKx output will be asserted low when the processor acknowledges the corresponding LOCALx interrupt INTERRUPT MANAGEMENT ee ew eek Local IACK control register LOCALIACK The 8 bit control register LOCALIACK is assigned to the LOCAL 4 7 interrupts and selects the int response mode for these interrupts Also selectable by the LOCALIACK con time
188. tion The address on which the parity error occurred will be latched in four 8 bit registers named PTYUU PTYUM PTYLM and PTYLL The cycle attribute register PTYATR stores information about the access conditions such as the transfer size the access type and who has accessed the memory The address of the accessed memory location is latched when th parity interrupt is triggered A write access to the parity interrupt status register clears the interrupt and releases th latches Reading the parity error address registers when no error is latched will return the following data PTYUU SFF PTYUM SDO PTYLM 04 PTYLL 00 The default value of the parity attribute register cannot be given since it depends on the access conditions Error Parity error address Attributes 31 24 PAMETE ters 16 LD is ee 08 OF caw OD PTYATT PTYUU PTYUM PTYLM PTYLL SFFD00410 SFFDO040C SFFD00408 SFFD00404 SFFD00400 MISCELLANEOUS 6 4 Register PTYATT Register Mnemonic Address R W Default Parity Attribute Reg PTYATT SFFD00410 R Format of PTYATT 7 6 5 4 3 2 1 0 VME DMA RMC FC2 PEL FCO SZL SZO 7 VME This bit indicates if the parity error occurred during a VMEbus access to the shared main memory
189. to the VMEbus address THE VME INTERFACE The local main memory is mapped somewhere in the Extended VMEbus area If the CPU addresses local main memory the gate array s decoding logic recognizes this and selects local memory If the address is not local memory then the gat array s decoding logic assumes it to be a VME address and initiates a VME cycle In other words the whole of the Extended addressing range 0000 0000 SFAFF FFFF is available as a VME address with the exception of the local memory range The following table shows the address ranges of the various VMEbus areas with their addressing and data capabilities Table 2 1 Address ranges of the VMEbus areas with addressing capability and data transfer Capabilit Axx Dxx Range Area Address Data Capability Mnemonic 0000 0000 Extended Address 32 bit A32 D32 Data 32 16 8 bit D16 D8 FAFF FFFF FBXX XXXX FBOO 0000 Standard Address 24 bit A24 D32 seein yee gies Data 32 16 8 bit D16 FBFE FFFF D8 FBFF XXXX Short Address 16 bit A16 D32 Data 32 16 8 bit D16 D8 FCXX XXXX FC00 0000 Standard Address 24 bit A24 D16 giget resite Data 16 8 bit D8 FCFE FFFF FCFF XXXX Short Address 16 bit Alo D16 Data 16 8 bit D8 2 3 THE VME INTERFACE 2 3 1 Address Modifier Signal Generation The VMEbus specification defines five address modifier lines w
190. top page Accesses from the VMEbus to the local MAIN memory have to be executed with a valid Address Modifier Code Four AM codes can be selected in the ENAMCODE register Selecting one of the Address Modifier codes enables the decoding range Additionally the gate array provides write protection for the decoding interval The access qualification is available for each selected AM code separately THE VME INTERFACE 3 2 1 Decoding scheme for accesses to the local MAIN memory from the VMEbus side VME Page Decoding VME Address line A31 A30 A29 A28 P31 P30 P29 P28 VMEPAGE Register Bits Address Interval Decoding VME Address line A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 T2 T26 T25 T24 T23 T22 T21 TZ0 TT9 TIS TIT TL6 TLS Tha TL3 T12 TOPPAGEU TOPPAGEL B27 B26 B25 B24 B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 BOTTOMPAGEU BOTTOMPAGEL THE VME INTERFACE 3 2 2 The access page to the local MAI 256 MByt page array The four register bits P31 P28 are compared wit VME Page Decoding N memory from VMEbus side is a specified by the VMEPAGE register of the gate th the VME
191. ty It manages interrupt sources within the gate array as well as external sources connected to the gate array The FGA 002 Gate Array is an efficient interface for various interrupt sources to the local CPU and supports up to 18 external interrupters Interrupt inputs provided for external interrupt sources exclusive of the VMEbus interrupt inputs offer maximum flexibility as they may be configured to be level edge sensitive or low high active The control of these features is performed by two bits contained in the extended interrupt control registers The Interrupt Auto Clear bit in the extended interrupt control register determines whether the interrupt of an edge sensitive input is cleared automatically during the interrupt acknowledge cycle or has to be cleared by the interrupt service routine Each interrupt source is bound to an individual interrupt channel which has its own assigned vector number The interrupt channels are configured by the Interrupt Control Registers where a 3 bit code for the level and a bit for enable disable control are stored Each interrupt channel may be programmed to interrupt the processor at any level The vector table of the gate array is a group of 64 vectors The two most significant bits of the 8 bit vector are programmable via register bits The rest of the bits are assigned by gate array hardware Not all of the 64 vectors are used in
192. umber string buffer for converted number 4 5 4 Convert Hex ASCII to Binary Number Convert the given hex ASCII string to a binary number int fga_util unsigned long ashex char ascii unsigned long binary unsigned long digits ashex 25 ascii hex ascii digit string binary result storage digits number of hex digits max is 8 4 5 5 Broadcast Message via FMB This routine sends out via FMB a message to the given logical slot address es NOTE May only be called in the SUPERVISOR mode int fga_util unsigned long broadc unsigned long fmbch unsigned long msg char slot unsigned long retry broade 29 fmbch FMB channel 0 or 1 msg message to send slot destination slot number list must be NULL terminated retry broadcast retry count on error 4 5 6 Perform VME Reset Call This routine performs a VME reset call on the specified board NOTE If the logical slot number is its own then the own board is reset int fga_util unsigned long rstcall unsigned long slot rstcall 30 slot destination slot number 22 FGA 002A Boot Software Version 4 4 5 7 Initiate Mailbox IRQ This function is used to generate one of the mailbox IRQs on the specified board NOTE If the logical slot number is its own then an own mailbox IRQ is generated int fga_util unsigned long mailbx unsigned long box unsigned long slot unsigned long retry mailbx 31 slot destination slot number box mailbox channel 0 7
193. us The slaves need to have a special FMB protocol handling The master needs absolutely no special FMB hardware From the master s point of view the Message Broadcast cycle is a write cycle to the Extended Address Space A32 with the Address Modifier code 09 or SOD for Extended User Supervisory Data Access The FMB definition includes two channels where a message can be sent to The slave has to stor th messages in dual ported registers or fifos In order that the register fifo is emptied from messages as soon as possible each FMB channel must be connected to the CPU interrupt logics The channel has to request service when there is message data stored in its register fifo If the FMB channel FIFO or buffer is full then no new FMB transfer to that channel is possible The concept that all boards addressed should react the same way requires that if one board cannot accept the message then any other board should be prevented from fetching the message Therefore the board that is incapable of fetching the message has to send out a signal that the cycle is to be aborted This action is performed via the BERR signal of the VMEbus In an FMB cycle each addressed slave monitors the BERR signal line This line is driven low immediately by a slave if it is not able to read in the message If the BERR signal is asserted within a specified time window each oth
194. used by FORCE bootup software and reserved for future interrupt enhancement The following table shows the interrupt channels and the assigned vector numbers INTERRUPT MANAGEMENT Table 2 1 Interrupt Vector Number Assignment INTERRUPT CHANNEL VECTOR NUMBER DAISY CHAIN Mailbox 0 S00 highest Mailbox 1 01 priority Mailbox 2 02 Mailbox 3 03 Mailbox 4 S04 Mailbox 5 05 Mailbox 6 06 Mailbox 7 07 f reserved S08 descending priority reserved S1F Timer 20 ies reserved 21 reserved 22 reserved 23 FMB1 Refused 24 FMBO Refused 25 FMB1 Message 26 FMBO Message 27 ABORT 28 ACFAIL 29 SYSFAIL S2A DMA Error 2B DMA Normal S2C PARITY Error S2D reserved S2E reserved S2F LOCALO 30 LOCAL 31 LOCAL2 32 LOCAL3 33 LOCAL4 34 or external LOCAL5 35 or external LOCAL6 36 or external LOCAL7 37 or external reserved 38 reserved 39 reserved S3A reserved 3B reserved 3C reserved 3D reserved 3E INTERRUPT MANAGEMENT Table 2 1 Interrupt Vector Number Assignment cont d INTERRUPT CHANNEL VECTOR NUMBER DAISY CHAT VIRQ7 external from VME descending VIRQ6 external from VME priority VIRQ5 external from VME VIRQ4 external from VME VIRQ3 external from VME VIRQ2 external from VME VIROQ1 external from VME lowest Empty Interrupt 3F priority
195. y attached to the ACFAIL signal of the VMEbus The RACFAIL function will be performed if the gate array is initialized not to support the ACFAIL Handler option After reset the RACFAIL option is enabled The ACFAIL Handler option is described in the section MISCELLANEOUS THE VME INTERFACE 2 7 5 Release Every Cycle If the REC option is enabled the gate array releases the bus mastership immediately after the processor has finished the current cycle irrespective of the state of the BCLR pin An active read modify write cycle on the VMEbus will not be interrupted The Release Every Cycle option is disabled after reset 2 7 5 1 Register CTL12 Register Mnemonic Address R W Default Control 12 Register CTL12 SFFD0032C R W 00 Format of CTL7 7 6 5 4 3 2 1 0 DMA RECENA FASTVME ASDMATOVME 7 RECENA Release Every Cycle option bit 1 enables REC function 0 disables REC function THE VME INTERFACE VME SLAVE INTERFACE L FEATURES Programmable DPR SHARED memory address interval decoding 4 AM Codes selectable for accesses to the DPR SHARED memory Support for RMW cycle to the SHARED memory Programmable VME decoding page for the gate array 2 AM Codes selectable for VME access to gate array functions Reset Call function from t
196. ycl 9 10 clockcycl SA 11 clockcycl B 12 clockcycl C after AUXRDY D not allowed SE aft into the fifo SF on valid READY NEWCYCLE starts x cycles of 32mhz after READY 0 1 clockcycl 1 2 clockcycl 2 3 clockcycl 3 4 lockeycl S4 5 elockeyel 5 6 clockcycl 6 7 clockcycl 7 8 clockcycl 8 9 clockcycl 9 10 clockcycl SA 11 clockcycl SB 12 clockcycl SC after AUXRDY SD after AUXACK SE aft into the fifo SF on valid READY 39 ted CTL13 REGISTER FORMAT SFFD00350 BITs 76543210 Byte REEP ROE Reset Value 00 BIT 7 0 BRIDGE This register is for test purposes only All bits are cleared to 0 after reset Changing the contents of the register will have unpredictable consequences CTL14 REGISTER FORMAT BITs 76543210 Byte XXXXXXXX Reset Value 00 BIT 7 BIT 6 BIT 5 4 BIT 3 2 BIT 1 0 SEPROMWRITE BSCUT VME DTACKEVAL DSVMEWRITE ASTOVME 00 01 10 11 U 00 01 10 SFFD00354 Write Access to SYSTEM EPROM enabled Write Access to SYSTEM EPROM disabled Write Byte Strobes will not be cut Write Byte Strobes will be cut Sync DSACK delayed with 2 cpu clock cycles Sync DSACK delayed with 1 cpu clock cyle Synchronous DSACK DSACK Asynchronous DS LDS Timing for Write Cycles
197. zation of the last FC68165 of this module the same procedure starts for a second module The base address of the first FC68165 of the second EAGLE module is programmed to be at address FEEQ0000 If the ID EPROM contains no or invalid data the address of further FC68165s are programmed sequentially The offset is always 200 Every I O dependent setting timing address offset can be set in the ID EPROM of the first FC68165 of a module Please refer to the EAGLE module specification Board Manual for the correct contents of the ID EPROM Examples e The first EAGLE module contains two FC68165 and a valid ID EPROM No second EAGLE module is installed The base addresses of the FC68165 are FEC00000 FECO0200 e The first EAGLE module contains one FC68165 and a valid ID EPROM The second EAGLE module contains two FC68165 and a valid ID EPROM The base addresses of the FC68165 are FEC00000 first module FEE00000 second module FEE00200 second module e The first EAGLE module contains two FC68165 and an invalid ID EPROM The second EAGLE module contains one FC68165 and a valid ID EPROM The base addresses of the FC68165 are FEC00000 first module FEC00200 first module FEC00400 second module Please note that the FC68165 is programmed to be only accessible in supervisor mode 2 2 SRAM Layout First of all the structure of the SRAM FORCE COMPUTERS Offset Byte Default Descripti

FORCE GATE ARRAY FGA

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