ODMB user`s manual
Contents
1. ODMEB user s manual Optical DAQ MotherBoard for the ME1 1 stations of the CMS muon endcap detector Firmware tag 3 0C ODMB V2 O MB V3 and ODMB V4 compatible Manuel Franco Sevilla Frank Golf Guido Magazzu Tom Danielson Adam Dishaw Jack UC Santa Barbara 5th October 2015 Bradmiiller Feld Table of Contents Front panel General Firmware version VME access through the board discrete emergency logic Jumpers and test points Device 1 DCFEB JTAG Example Read DCFEB UserCode Device 2 ODMB JTAG Example Read ODMB UserCode Device 3 ODMB DCFEB control Bit specification DCFEB pulses command W 3200 Information accessible via command R 3YZC Device 4 Configuration registers Delay diagrams Device 5 Test FIFOs Device 6 BPI Interface PROM Device 7 ODMB monitoring Translation into temperatures current and voltages Device 8 Low voltage monitoring Device 9 System tests Firmware block diagram ODMB headers trailers DMB user s manual oOo OON Op an PB WWW PN h l O N N d O a A Q Front panel 1 2V FPGA 3 3V ICs 3 3V ORX1 3 6V PPIB 1 0V FPGA 2 5V FPGA 3 3V ORX 3 3V VME Firmware tag 3 0C EDA 02415 DMB user s manual Push buttons HRST Reloads firmware in PROM onto FPGA SRST Resets registers FIFOs in FW LEDs 1 12 bl2. 22 s sti6 MO o T17 M1 2 ST18 Mp Ries LI En c34 SNM i aA G Set M2 to P2V5 for slave mode 1C35 R122 Firmware tag 3 0C ODMB user s manual Device 1 DOFEB JIAG Y refers to the number of bits to be shifted Instruction Description R 1014 Read TDO register w 1018 Resets JTAG protocol to IDLE state data sent with this command is disregarded Shift Instruction register w 1020 Select DCFEB one bit per DCFEB R 1024 Read which DCFEB is selected Example Read DCFEB UserCode DCFEB registers are set and read via JTAG The following procedure reads the 32 bit USERID of DCFEB 3 W 1020 4 Select DCFEB 3 one bit per DCFEB W 191c 3C8 Set instruction register to 3C8 read UserCode W 1F04 0 Shift 16 lower bits R 1014 0 Read last 16 shifted bits DBDB W 1F08 0 Shift 16 upper bits R 1014 0 Read last 16 shifted bits XYZK Firmware tag 3 0C 5 ODMB user s manual Device 2 ODMB JIAG Y refers to the number of bits to be shifted Instruction Description P R 2014 Read TDO register w 2018 Resets JTAG protocol to IDLE state data sent with this command is disregarded Shift Instruction register W 2020 Change polarity of V6_JTAG_SEL Example Read ODMB UserCode Read FPGA UserCode W 291C 3C8 Set instruction register to 3C8 read UserCode W 2F04 0 Shift 16 lower bits R 2014 0 Read last 16 shifted bits DBDB W 2F08 0 Shift 16 upper bits R
3. ALCT Instruction Description R 5000 Read one word of selected DCFEB FIFO R 500C Read numbers of words stored in selected DCFEB FIFO W R 5010 Select DCFEB FIFO W 5020 Reset DCFEB FIFOs 7 bits one per FIFO which are auto reset R 5200 Read one word of FIFO Read numbers of words stored in FIFO Notes 1 All these FIFOs except PC DDU TX can hold a maximum of 2 000 18 bit words 36 kb 1 PC and DDU TX are 4 times larger 2 The OTMB ALCT and 7 DCFEB FIFOs store the data as it arrives in parallel to the standard data path e They can hold a maximum of 3 OTMB 4 ALCT and 2 DCFEB data packets 3 The DDU TX FIFO stores DDU packets just before being transmitted e They include the DDU header 4 words starting with 9 4 starting with A ALCT data TMB data DCFEB data and trailer 4 words starting with F 4 starting with E 4 The PC TX FIFO stores DDU packets wrapped in ethernet frames just before being transmitted e They include the ethernet header 4 words and trailer 4 words and fillers e They need to be at least 32 words long 5 The DDU and PC RX FIFOs can be used for loopback tests Firmware tag 3 0C 10 ODMB user s manual Device 6 BPI Interface PROM Important Instruction 6000 takes 1 second during which Device 4 and 6 write commands are ignored Instruction Description w 6000 Write configuration registers to PROM w 6004 Set configuration registers to retrieved values from PROM W 6020 Reset BPI i
4. BPI_PORT Device 6 VMECONFREGS Device 4 VMEMON Device 3 ODMB_CTRL MBC CALIBTRG Calibration TRGCNTRL Trigger control le COMMAND VME protocol DATA FIFOs E CAFIFO Event manager l CONTROL DDU packets E PCFIFO PC packets Firmware tag 3 0C 15 DMB user s manual ODMB headers trailers Structure of ODMB header Four 0x9000 words and four 0xA000 words DMB_LI1A 11 0 DMB_L1A 23 12 1b 100 i ALCT_DAV 1 TMB_DAV 1 Fmt_Vers 1 0 CLCT DAV Mismatch 1 CFEB_CLCT_SENT 7 1 o id Omg DMB_BXN 11 0 ALCT_DAV 1 TMB_DAV 1 Fmt_Vers 1 0 CLCT DAV Mismatch 1 CFEB_DAV 7 1 2b 100 En DMB_CRATE 8 DMB_ID 4 ALCT_DAV 1 TMB_DAV 1 CFEB_MOVLP 5 1 DMB_BXN 4 0 DMB CFEB Sync 3 0 Fmt_Vers 1 0 CLCT DAV Mismatch 1 DMB_L1A 4 0 Structure of ODMB trailer Four 0xF000 words and four 0xE000 words a ALCT_End_Timeout 1 DMB_BXN 4 0 DMB_L1A 5 0 unu EN CFEB_MOVLP 5 1 CFEB_End_Timeout 7 1 CFEB_FULL 3 1 TMB_Start_Timeout 1 DMB_L1PIPE 8 id 1111 RI ALCT_Start_Timeout 1 CFEB_Start_Timeout 7 1 CFEB_FULL 7 4 2 110 ALCT_FULL 1 TMB_FULL 1 ALCT_HALF 1 TMB_HALF 1 TMB_End_Timeout 1 CFEB_HALF 7 1 2 1110 HER Duplicate Header 2b DMB Crate amp ID 2 TOREN DMB_CRC_LowParity 1 DMB_CRC 10 0 2d IO RN DMB_CRC HighParity 1 DMB_CRC 21 11 Firmware tag 3 0C 16
5. bit errors in the PC RX Production tests gt gt YZ 5A Read last CCB_CMD 5 0 EVTRST BXRST strobed YZ 5B Read last CCB_DATA 7 0 strobed YZ 5C Read toggled CCB_CAL 2 0 CCB_BXO CCB_BXRST CCB_L1ARST CCB_L1A CCB_CLKEN CCB_EVTRST CCB_CMD_STROBE CCB_DATA_STROBE YZ 5D Read toggled CCB_RSV signals Firmware tag 3 0C 8 DMB user s manual Device 4 Configuration registers W R 4000 LCT_L1A_DLY 5 0 gt Set to LCT L1A gap 100 W R 4004 OTMB_DLY 5 0 gt Set to L1A OTMBDAV gap read with R 338C ALCT_DLY 5 0 gt Set to L1A ALCTDAV gap read with R 339C INJ_DLY 4 0 Delay 12 5 INJ_DLY ns EXT_DLY 4 0 Delay 12 5 EXT_DLY ns CALLCT_DLY 3 0 Delay 25 CALLCT_DLY ns ee re Delay diagrams 1 LCT_L1A_DLY OTMB_DLY and ALCT_DLY matcht LCT OTMBDAV and ALCTDAV to L1A respectively Pipeline depth 120 100 LCT_L1A_DLY 125 3 1 us Muon LCT OTMBDAV ALCTDAV LIA _ MATCH ALCT_DLY 31 u digitation f OTMB DLY 2 2 EXT_DLY INJ_DLY set the distance between the CCB signals and the pulses CALLCT_DLY sets the distance between the pulses and the L1A L1A_MATCHes t EXT_DLY A CALLCT DA t INJ_DLY i Set Ua e a CCB CALO EXT PLS LIAL MATCH CCB CALI INJ PLS LIA MATCH Firmware tag 3 0C 9 ODMB user s manual Device 5 Test FIFOs Z refers to FIFO 1 gt PC TX 2 gt PC RX 3 gt DDU TX 4 gt DDU RX 5 OTMB 6 gt
6. 2014 0 Read last 16 shifted bits XYZK Firmware tag 3 0C 6 ODMB user s manual DEMOS er OMA Gre Gente Instruction Description W R 3000 O gt nominal mode 1 gt calibration mode ODMB generates L1A with every pulse ed eee W R 3020 TP_SEL register selects which signals are sent to TP31 TP35 TP41 TP45 a eet fee W 3200 Sends pulses to DCFEBs see below W R 3300 Data multiplexer O gt real data 1 gt dummy data W R 3304 Trigger multiplexer O gt external triggers 1 internal triggers W R 3308 LVMB multiplexer O gt real LVMB 1 gt dummy LVMB W R 3400 O gt normal 1 gt pedestal L1A MATCHes sent to DCFEBs for each L1A W R 3404 O gt normal 1 gt OTMB data requested for each L1A requires special OTMB FW W R 3408 Bit O gt kills L1A Bits 1 7 gt kills L1A_MATCHes W R 340C MASK_PLS 0 gt normal 1 gt no EXTPLS INJPLS for non pulsed pedestals from CCB Read ODMB_DATA corresponding to selection YZ see below Firmware tag 3 0C 7 DMB user s manual Bit specification DCFEB pulses command W 3200 DCFEB_PULSE 0 Sends INJPLS signal to all DCFEBs DCFEB_PULSE 1 Sends EXTPLS signal to all DCFEBs DCFEB_PULSE 2 Sends test L1A and L1A_MATCH to non killed DCFEBs DCFEB_PULSE 3 Sends LCT request to OTMB DCFEB_PULSE 4 Sends external trigger request to OTMB DCFEB_PULSE 5 Sends BCO to all DCFEBs Information accessible via command R 3YZC Trigger an
7. DCFEBs ALCT are actually powered on W 8020 Select ADC to be read O to 6 R 8024 Read which ADC is to be read Notes The ODMB has an internal 8 bit register that selects with DCFEBs ALCT to turn on when a LOAD signal is issued Command W 8010 XX both changes the register to XX and issues the LOAD signal R 8014 reads the internal register while R 8018 reads the actual state of the boards on the crate The mapping of the 8 bits to DCFEBS ALCT is non trivial and different for forward and backward chambers Table 1 Control Byte Format BIT 7 BITO MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB START SEL2 SEL1 SELO RNG BIP Poi PDO PD1 PDO MODE 0 0 Normal operation always on internal clock mode 0 1 Normal operation always on external clock INPUT RANGE RNG BIP mode g Standby power down mode STBYPD clock Oto 5V Full power down mode FULLPD clock mode 5V unaffected 10V 0 0 mode unaffected O to 10V 1 0 0 1 1 1 Firmware tag 3 0C 13 DMB user s manual Device 9 System tests Instruction Description er Ee a 9200 Geis tonie Esen Te O en Firmware tag 3 0C 14 DMB user s manual Firmware block diagram The firmware can be downloaded from http github com odmb odmb_ucsb_v2 ODMB_UCSB_V2 Top of the design FPGA Control gt Data ODMB_VME MBV Te LVDBMON Device 8 SYSTEM_MON Device 7
8. ct DR Scan W FFFC 1 To Select IR Scan W FEFFC 0 To Capture IR W FFFC 0 To Shift IR W FEFFC 0 Shifting IR Read UserCode IR 3C8 W FFFC 0 Shifting IR W FFFC 0 Shifting IR W FFFC 2 Shifting IR W FFFC 0 Shifting IR W FFFC 0 Shifting IR W FFFC 2 Shifting IR W FFFC 2 Shifting IR W FFFC 2 Shifting IR W FFFC 3 Shifting IR and to Exitl IR W FFFC 1 To Update IR W FFFC 0 To Run_Test Idle W FFFC 1 To Select DR Scan W FFFC 0 To Capture DR W FFFC 0 Shifting DR R FFFC 0 Shifting DR Read bit 0 of UserCode Since the Usercode register is 32 bits the last two commands should be repeated 31 more times Firmware tag 3 0C 3 Jumpers and test points ODMB user s manual Place the jumpers marked in red in the diagram master mode The signals sent to the test points marked are TP13 MATCH 1 TP31 Defined by TP_SEL TP32 TP15 ATCH 2 TP33 TP17 ATCH 3 TP35 TP19 MATCH 4 TP37 TP21 ATCH 5 TP39 TP23 MATCH 6 TP41 TP25 MATCH 7 TP43 TP27 DDU_ DATA VALID TP45 TP29 ALCTDAV TP47 TP49 OPLL FOSISg e 2 E OPLL FOSO H oz OPLL EXT OOO a Lo OPLL FOS3 TDC aL D2 incwos e0200 Je oPet Fose a BE au S OD a En i si 73 DRE CD ak we b wa ST15 rz C LJ ros Ci wos C Cm Add ST15 ae C us sl XILINX for slave mode s C Cee zc re C Ero R97 LT C ros VI RTEX 6 ms is E XC6VLX130T R99 wo oc LW FFG1156 mor J ale R102 Lus 2 gl z Coru DEEDE SH16
9. d packet counters gt gt gt gt gt gt YZ SF Least significant 16 bits of L1A COUNTER YZ 5F Least significant 16 bits of L1A COUNTER only reset by hard resets no RESYNCs YZ 71 77 Number of LCTs for given DCFEB YZ 78 Number of OTMBDAVs available OTMB packets YZ 79 Number of ALCTDAVs available ALCT packets YZ 21 29 Number of L1A_MATCHes for given DCFEB OTMB ALCT YZ 41 49 Number of packets received for given DCFEB TMB or ALCT YZ 4A Number of packets sent to the DDU YZ 4B Number of packets sent to the PC YZ 51 59 Number of packets shipped to DDU and PC for given DCFEB TMB or ALCT YZ 61 67 Number of data packets received with good CRC for given DCFEB Timing gt gt gt YZ 31 37 Gap in number of bunch crossings between the last LCT and L1A for given DCFEB YZ 38 Gap in number of bunch crossings between the last L1A and OTMBDAV YZ 39 Gap in number of bunch crossings between the last L1A and ALCTDAV Monitoring of QPLL RX TX gt gt gt gt YZ 4F Read number of times the QPLL lock has been lost YZ A1 A7 Number of bad CRCs for given DCFEB YZ B1 B7 Number of times there are fiber errors for given DCFEB includes errors on IDLE YZ A8 Times the PLL for the DDU TX lost its lock YZ A9 Times the DDU RX has an error YZ AA Number of bit errors in the DDU RX YZ AB Times the PC RX has an error YZ AC Number of
10. ink at different speeds for 3s PB1 Sends L1A and L1A_MATCH to all DCFEBs Turns on LED 12 LEDs set in firmware 1 4 Hz signal from clock for data gt DDU 3 2 Hz signal from clock for data gt PC 5 1 Hz signal from internal ODMB clock 7 Data taking ON normal OFF pedestal 9 Triggers ON external OFF internal 11 Data ON real OFF simulated 2 Bit O of L1A COUNTER 4 Bit 1 of L1A_ COUNTER 6 Bit 2 of L1A_ COUNTER 8 Bit 3 of L1A_ COUNTER 10 Bit 4 of L1A COUNTER 12 Briefly ON when a VME command is received Also ON when PB1 is pressed LEDs set in hardware DDU Signal Detected on DDU RX PC Signal Detected on PC RX ETD DTACK enable for discrete logic active low EJD JTAG enable for discrete logic active low DON DONE signal from FPGA ON when pro grammed INIT INIT_B signal from FPGA active low LOCK OPLL is locked ERR Error with QPLL Bottom 12 Voltage monitoring DMB user s manual Genera Firmware version For a given firmware tag VXY ZK Usercode is XYZKdbdb Firmware version read via R 4200 is XYZK VME access through the board discrete emergency logic The FPGA may be accessed via JTAG through the discrete logic as follows The VME address is OxFFFC The bit O of the data sent is TMS The bit 1 of the data sent is TDI For example to read the Usercode starting from JTAG idle five TMS 1 amp one TMS 0 the commands are W FEFFC 1 To Sele
11. nterface state machines W 6024 Disable parsing commands in command FIFO while filling FIFO with commands no data w 6028 Enable parsing commands in the command FIFO no data W 602C Write one word to command FIFO R 6030 Read one word from read back FIFO R 6034 Read number of words in read back FIFO R 6038 Read BPI Interface Status Register Read Timer 16 LSBs Read Timer 16 MSBs Firmware tag 3 0C 11 ODMB user s manual Device 7 ODMB monitoring Reads output of the ADC inside the FPGA Instruction Description Translation into temperatures current and voltages The output of the 7YZO commands is a 12 bit number that we call Ryz The measurement is Roo x 503 975 4096 10 mA e The FPGA temperature is Ta pga 273 15 C Rie x 5000 e The PPIB current is Tpprp 4096 e The temperature of the thermistors THERM1 THERM2 is given by BN ele pes fols olfsel o s ej e The voltage levels are Vy7 a x Vyz Nom V where Vyz Nom is the nominal voltage level for that register That is V10 Nom 3 3V V13 Nom 3 6V V11 Nom V17 Nom DV V14 Nom 2 5V and V46 Nom 1V Firmware tag 3 0C 12 DMB user s manual Device 8 Low voltage monitoring Instruction Description W 8000 Send control byte to ADC R 8004 Read ADC W 8010 Select DCFEBs ALCT to be powered on 8 bits ALCT 7 DCFEBs R 8014 Read selected DCFEBs ALCT to be powered on see notes R 8018 Read which
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