IOS-470 User`s Manual
Contents
1. BOARD CONFIGURATION CONNECTORS sees IOS Field Connector P2 I O Noise and Grounding Considerations 3 0 PROGRAMMING INFORMATION ADDRESS 5 Standard Default Mode Memory Map Enhanced Mode Memory Map REGISTER DEFINITIONS THE EFFECT OF RESET Basic I O Operation Enhanced Operating Event Sense Inputs eeseesese Change Of State Detection Debounce Control Interrupt Generation Programming 8 4 0 THEORY OF 1 IOS 470 1 5 0 SERVICE AND 1 SERVICE AND REPAIR ASSISTANCE 1 PRELIMINARY SERVICE PROCEDURE 6 0 5 1 GENERAL SPECIFICATIONS ENVIRONMENTAL DIGITAL INPUTS DIGITAL 5 1 DRAWINGS IOS 470 BLOCK DIAGRAM 1 5 470 PULLUP RESISTOR LOCATIONS 12. Turn Off Time 4 7K pull ups Debounce Debounce Register Setting Count 00 32 01 512 10 8000 11 64000 16 4us 64us 1ms or 8ms with an error of 250ns 48 open drain CMOS outputs For DC voltage applications only observe proper polarity 0 1VDC Typical 0 4VDC Maximum at 12mA Supply 0 2V at 10uA 0 to 15mA DC for x0 5V 4 7KQ pull ups are installed in sockets on the board Even with these pull ups removed weak integrated 47 5KQ nominal pull ups are always present See the IOS for resistor locations 125nS Typical 2uS Typical SERIES 5 470 SERVER MODULE 48 CHANNEL DIGITAL I O MODULE WITH INTERRUPTS 9y 05 4 69 BLOCK DIAGRAM LOGIC 1 0 INTERFACE FIELD Qn P2 a 492 Ohm 3 3V Resistors VOLTAGE FPGA SIMPLIFIED x 3 3V 5V n TRANSLATION BUFFER 1 T 1 DEVICE 5V 5V 3 3V FIELD PROGRAMMABLE GATE ARRAY VBias CONTROL BUS 5v to 3 3V CONTROL BUS 47K 475K DEBOUCE CHANGE OF f 3 3V to 5V ooo i STATE INTERRUPT J J T CONTROL REGISTERS ACKNOWLEDGE VOLTAGE ACKNOWLEDGE b 4 TRANSLATION DEVICES T lot ug o S 1 0 CONTROL INTERRUPT LINE I
3. Surface Mounted Technology SMT boards are generally difficult to repair It is highly recommended that a non functioning board be returned to Acromag for repair The board can be damaged unless special SMT repair and service tools are used Further Acromag has automated test equipment that thoroughly checks the performance of each board When a board is first produced and when any repair is made it is tested placed in a burn in room at elevated temperature and retested before shipment Please refer to Acromag s Service Policy Bulletin or contact Acromag for complete details on how to obtain parts and repair PRELIMINARY SERVICE PROCEDURE Before beginning repair be sure that all of the procedures in Section 2 Preparation For Use have been followed Also refer to the documentation of your carrier board to verify that it is correctly configured Verify that there are no blown fuses Replacement of the carrier and or IOS with one that is known to work correctly is a good technique to isolate a faulty board CAUTION POWER MUST BE TURNED OFF BEFORE REMOVING OR INSERTING BOARDS WHERE TO GET HELP If you continue to have problems your next step should be to visit the Acromag worldwide web site at http www acromag com Our web site contains the most up to date product and software information Go to the Support tab to access e Application Notes e Frequently Asked Questions FAQ s e Product Knowledge Base e Tutorial
4. Page ARRWWWW C5 Co TO TO IMPORTANT SAFETY CONSIDERATIONS It is very important for the user to consider the possible adverse effects of power wiring component sensor or software failures in designing any type of control or monitoring system This is especially important where economic property loss or human life is involved It is important that the user employ satisfactory overall system design It is agreed between the Buyer and Acromag that this is the Buyer s responsibility 1 0 GENERAL INFORMATION The SERVER MODULE IOS Series IOS 470 module provides 48 channels of general purpose digital inputs and outputs Four units may be mounted on a carrier board to provide up to 192 points per system slot Inputs and outputs of this module are CMOS and TTL compatible Each of the I O lines can be used as either an input an output or an output with readback capability Each I O line has built in event sense circuitry with programmable polarity and interrupt support The inputs may also operate as independent event sense inputs without interrupts Outputs are open drain and may sink up to 15mA each A 4 7K pull up is provided for each drain and is installed in sockets on the board SIP resistors for easy removal or replacement Inputs include hysteresis and programmable debounce Interrupt event and debounce functionality applies to all 48 channels of this model The IOS 470 utilizes state of the art Surface Mounte
5. This model provides control for generation of interrupts on positive or negative events for all 48 channels Interrupts are only generated in the Enhanced Mode for event channels when enabled via the Event Sense Status Register Writing 0 to the corresponding event sense bit in the Event Sense Status Register will clear the event sense flip flop Successive interrupts will only occur if the event channel has been reset by writing a 1 to the corresponding event sense bit in the Event Sense Status Register after writing 0 to clear the event sense flip flop Interrupts may be reflected internally and reported by polling the module or optionally reported to the carrier by enabling control of the Interrupt Request line Intreq0 Control of this line is initiated via bit 0 of the Interrupt Enable Register IER After pulling the IntReq0 line low and in response to an Interrupt Select cycle the module will provide its 8 bit interrupt vector The interrupt vector is written to the Interrupt Vector Register The IOS module will thus execute a read of the Interrupt Vector Register in response to an interrupt select cycle The IntReq0 line will be released as soon as the conditions generating the interrupt have been cleared or return to normal and the event sense flip flop has been cleared by writing 0 to the corresponding bit position of the Event Sense Status Register or until the Interrupt Enable Register bit is cleared Zero wait states are requir
6. drive INTREQO or not This bit defaults to O interrupt request disabled and event interrupts are only flagged internally That is you would have to poll the Event Status Register to determine if an interrupt had occurred or not and the INTREQO line would not be driven If bit O of this register is set to 1 then interrupts will drive the INTREQO line and permit Interrupt Select Cycles INTSEL to occur This bit is cleared following a system reset but not a software reset see below Writing a 1 to the bit 1 position of this register will cause a software reset to occur be sure to preserve the current state of bit 0 when conducting a software reset This bit is not stored and merely acts as a trigger for software reset generation this bit will always readback as 0 The effect of a software reset is similar to a carrier reset except that it is not driven by the carrier and it only resets the digital ASIC chip that provides the field interface functions Likewise the Interrupt Vector Register or the Interrupt Enable Bit of this register is not cleared in response to a software reset these are not stored in the ASIC It is useful for use with some carriers which do not implement the bus reset control Bits 2 7 of this register are not used and will always read high 1 s Interrupt Vector Register Read Write This 8 bit read write register is used to store the interrupt vector Interrupts are driven by events in the Enhanced Mode
7. driving this port Enhanced Mode Write Mask Register Port 7 0 PortOWriteMask PortOWrieMask 6 BankSelectBitO BankStatusBitO _ Bits 6 amp 7 of this register are used to select monitor the bank of registers to be addressed In Enhanced Mode three banks banks 0 2 of eight registers may be addressed Bank 0 is similar to the Standard Mode bank of registers Bank 1 allows the 48 event inputs to be monitored and controlled Bank 2 registers control the debounce circuitry of the event inputs Bits 7 and 6 select the bank as follows SERIES 5 470 SERVER MODULE 48 CHANNEL DIGITAL I O MODULE WITH INTERRUPTS Enhanced Mode Bank Select Bit 7 Bit6 BANK OF REGISTERS 00 Bank 0 Read Write Bank 1 Event Status Clear 10 Bank 2 Event Debounce Control Clock and Duration INVALID DO NOT WRITE On power up reset the device is put into the Standard Mode and this register defaults to the unmasked state allowing writes to the output ports and bank 0 Default BANK 1 REGISTERS Event Sense Status amp Clear Registers For 0 47 Enhanced Mode Bank 1 Ports 0 5 Read Write Each I O line of each port includes an event sense input Reading each port will return the status of each I O port sense line Writing 0 for a bit position of each port will clear the event on the corresponding line When writing ports 0 5 of Enhanced Mode bank 1 each data bit written wi
8. 3 1B 5 470 R W Space Address Hex Memory Map Base MSB LSB Base Addr D15 D08 D07 DOO Addr nonren To megiseriootor oo Not Driven Register l O0 I O7 motive iORegsteruoe O s o2 Not Driven Register l O8 I O15 motive wOWegsterOisTOzs Not Driven I O Register 1 016 1 023 VO Register voza ios1 06 I Not Driven Register l O24 I O31 Register Port 1 I O Points 8 15 READ Port 2 Event Sense Status Reg Port 2 I O Points 16 23 WRITE Port 2 Event Sense Clear Register Port 2 I O Points 16 23 READ Port 3 Event Sense Status Reg Port 3 I O Points 24 31 WRITE Port 3 Event Sense Clear Register Port 3 I O Points 24 31 READ Port 4 Event Sense Status Reg Port 4 I O Points 32 39 WRITE Port 4 Event Sense Clear Register Port 4 I O Points 32 39 READ Port 5 Event Sense Status Reg Port 5 I O Points 40 47 WRITE Port 5 Event Sense Clear Register Port 5 I O Points 40 47 READ WRITE Port 6 Not Driven NOT USED oc READ Port 7 Not Driven READ MASK REGISTER Not Driven WRITE MASK REGISTER Also Bank Select Register Event Sense Status Reg Port 0 I O Points 0 7 WRITE Port 0 Not Driven Port 0 I O Points 0 7 READ Port 1 Not Driven Event Sense Status Reg Event Sense Clear 07 Not Driven 07 Not Driven READ WRITE Port 4 Not Driven I O Register I O32 I O39 READ WRITE
9. In response to an interrupt select cycle the IOS module will execute a read of this register This register is cleared following a system reset but not a software reset Note that interrupts will not be reported to the carrier board unless control of Interrupt Request Line 0 has been enabled via the Interrupt Enable register IOS Identification PROM Read Only 32 Even Byte Addresses Each IOS module contains an identification ID PROM that resides in the ID space per the IOS module specification This area of memory contains 32 bytes of information at most Both fixed and variable information may be present within the ID PROM Fixed information includes the IOS identifier model number and manufacturer s identification codes Variable information includes unique information required for the module The IOS 470 ID PROM does not contain any variable e g unique calibration information ID PROM bytes are addressed using only the odd addresses in a 64 byte block on the Big Endian VMEbus Even addresses are used on the Little Endian PC bus The 8 470 ID PROM contents are shown in Table 3 2 Note that the base address for the IOS module ID space see your carrier board instructions must be added to the addresses shown to properly access the ID PROM Execution of an ID PROM Read requires 0 wait states SERIES 5 470 SERVER MODULE 48 CHANNEL DIGITAL I O MODULE WITH INTERRUPTS Table 9 2 5 470 ID Space Identif
10. Register amp Enhanced Mode Select Register Standard Mode Port 7 Read Write This register is used to mask the ability to write data to the six ports Writing a 1 to bits 0 5 of the Mask Register will mask ports 0 5 from write control respectively A read of this register will return the status of the mask A Mask Register is used to disable writes to I O ports designated as input ports Thus when a port group of 8 I O lines is used for input writes to this port must be blocked masked to prevent contention between the output circuitry open drain and any external devices driving this port Standard Mode Write Mask Register Port 7 0 PortOWriteMask PorOWrteMask 6 NOTUSED X Bits 6 amp 7 of this register are not used On power up reset this register defaults to the unmasked clear state allowing writes to the output ports This register is also used to select the Enhanced Mode of operation To switch to Enhanced Mode four unique bytes must be written to port 7 in consecutive order without doing any reads or writes to any other port and with interrupts disabled The data pattern to be written is 07H ODH 06H and 12H in order and this must be written immediately after reset or power up ENHANCED MODE BANK 0 REGISTERS Port I O Registers Enhanced Mode Bank 0 Ports 0 5 Read Write Six I O Registers are provided to control monitor 48 possible I O points Data is read from or wri
11. groups of 4 I O lines or half ports The Enhanced Mode is entered by writing four unique bytes to the Port 7 register in consecutive order without doing any reads or writes to any other port and with interrupts disabled The data pattern to be written is 07H ODH 06H and 12H and this must be written immediately after reset or power up In Enhanced Mode there are three groups or banks of eight registers or ports The first group bank 0 provides register functionality similar to Standard Mode The second group bank 1 provides monitor and control of the event sense inputs The third group bank 2 is used to configure the debounce circuitry for each input while in the Enhanced Mode Event Sense Inputs The IOS 470 has event sense logic built in for all 48 digital lines 1 000 through 1 047 Event sensing may be configured to generate an interrupt to the carrier or merely reflect the interrupt internally Event sensing is enabled in Enhanced Mode only Inputs can be set to detect positive or negative events on a nibble by nibble group of 4 I O lines basis The event sensing is enabled on an individual channel basis You can combine event SERIES 5 470 SERVER MODULE 48 CHANNEL DIGITAL I O MODULE WITH INTERRUPTS sensing with the built in debounce control circuitry to obtain glitch free edge detection of incoming signals To program events determine which I O lines are to have events enabled and which
12. multiple ground connections This device is capable of switching many channels at high total currents Additionally the nature of the IOS interface is inherently inductive I O channels have special circuitry to help protect the device from ESD over voltage and switching transients within limitations However when switching inductive loads it is important that careful consideration be given to the use of snubber devices to shunt the reverse emf that develops when the current through an inductor is interrupted Filtering and bypassing at the load may also be necessary Additionally proper grounding with thick conductors is essential Interface cabling and ground wiring should be kept as short as possible For outputs of this device the 4 7KQ pull up resistors provide only limited digital drive capability Likewise outputs are intended to sink only 15mA or less As such the use of an interposing device may be required for controlling or isolating the load or to provide additional system protection The output pull up resistor SIP s are installed in sockets on the board allowing their values to be adjusted for greater drive capability if required see IOS 470 Pullup Resistors Locations The signal ground connection at the I O ports is common to the IOS interface ground which is typically common to safety chassis ground when mounted on a carrier board and inserted in a backplane As such be careful not to attach I O ground to safety g
13. of C functions which link with existing user code 2 0 PREPARATION FOR USE UNPACKING AND INSPECTION Upon receipt of this product inspect the shipping carton for evidence of mishandling during transit If the shipping carton is badly damaged or water stained request that the carrier s agent be present when the carton is opened If the carrier s agent is absent when the carton is opened and the contents of the carton are damaged keep the carton and packing material for the agent s inspection For repairs to a product damaged in shipment refer to the Acromag Service Policy to obtain return instructions It is suggested that salvageable shipping cartons and packing material be saved for future use in the event the product must be shipped NW This board is physically protected with packing material and electrically protected with an anti static bag during shipment However it is recommended that the board be visually inspected for evidence of mishandling prior to applying power CAUTION SENSITIVE ELECTRONIC DEVICES DO NOT SHIP OR STORE NEAR STRONG ELECTROSTATIC ELECTROMAGNETIC MAGNETIC OR RADIOACTIVE FIELDS The board utilizes static sensitive Components and should only be handled at a static safe workstation BOARD CONFIGURATION Power should be removed from the board when installing IOS modules cables termination panels and field wiring Refer to your IOS module documentation for configuration and assembly i
14. only be read by reading the corresponding port address while in bank 1 of the Enhanced Mode Remember the event sense status is a flag that is raised when a specific positive or negative transition has occurred for a given I O point while the state refers to its current level SERIES 5 470 SERVER MODULE 48 CHANNEL DIGITAL I O MODULE WITH INTERRUPTS 4 0 THEORY OF OPERATION This section provides a description of the basic functionality of the circuitry used on the board Refer to the IOS 470 Block Diagram as you review this material 5 470 OPERATION The 5 470 is built around a Field Programmable Gate Array FPGA IC The device provides the control interface necessary to operate the module the IOS identification space all registers and provides I O interface and configuration functions The FPGA monitors and controls the functions of the 48 digital used by this model It also provides debounce control and event sensing functions Electronic protection array circuitry is also installed on board for increased ESD and overvoltage protection of each I O line I O lines are pulled up to 5V via 4 7KQ SIP resistors installed in Sockets on the board However weak internal pull ups of 47 5 nominal are always present on these lines with the SIP resistors removed 14 SERIES IOS 470 I O SERVER MODULE 48 CHANNEL DIGITAL I O MODULE WITH INTERRUPTS 5 0 SERVICE AND REPAIR SERVICE AND REPAIR ASSISTANCE
15. to high transitions 1 004 07 will be used to detect negative events high to low transitions 1 000 and 1 004 will be tied to the first input signal 1 001 1 005 to the second 1 002 l O06 to the third and 1 003 amp 1 007 to the fourth Any change of state detected on these input signals will cause an interrupt to be generated SERIES 5 470 SERVER MODULE 48 CHANNEL DIGITAL I O MODULE WITH INTERRUPTS 1 After power up or reset the module is placed in the Standard Operating Mode To switch to Enhanced Mode execute four consecutive write cycles to port 7 with the following data 07H first followed by ODH followed by 06H then 12H At this point you are in Enhanced Mode bank 0 Port 7 would be used to access register banks 1 amp 2 2 Write 80H to the port 7 address to select register bank 2 where debounce will be configured for our port 0 input channels At this point you are in Enhanced Mode Bank 2 where access to the debounce configuration registers is obtained 3 For our example we want use the 8MHz system clock to generate our debounce time By default the debounce clock is taken from 047 pin 41 of P2 Select the 8MHz system clock as the debounce clock by writing 01H to the port 3 address of this bank Debounce Clock Select Register 4 The default debounce duration is 4us with the 8MHz clock selected in step 3 Write 01H to the port 1 address of this bank to select a 64us debounce time D
16. Acromag ld THE LEADER IN INDUSTRIAL I O IOS IOS 470 48 Channel Digital I O Module with Interrupts USER S MANUAL ACROMAG INCORPORATED Tel 248 295 0310 30765 South Wixom Road Fax 248 624 9234 P O BOX 437 Wixom MI 48393 7037 U S A solutions acromag com Copyright 2009 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 838 B11C007 SERIES 5 470 SERVER MODULE 48 CHANNEL DIGITAL I O MODULE WITH INTERRUPTS The information contained in this manual is subject to change without notice Acromag Inc makes no warranty of any kind with regard to this material including but not limited to the implied warranties of merchantability and fitness for a particular purpose Further Acromag Inc assumes no responsibility for any errors that may appear in this manual and makes no commitment to update or keep current the information contained in this manual No part of this manual may be copied or reproduced in any form without the prior written consent of Acromag Inc Table of Contents 1 0 GENERAL KEY IOS 470 FEATURES sese I O SERVER MODULE INTERFACE FEATURES SERVER MODULE 5 2 0 PREPARATION FOR USE sssss UNPACKING AND CARD CAGE
17. EAD WRITE Port 3 Not Driven Register 1 024 1 031 READ WRITE Port 4 Not Driven Register l O32 1 O39 READ WRITE Port 5 Not Driven Register l O40 I O47 READ WRITE Port 6 Not Driven NOT USED oc READ WRITE Port 7 WRITE MASK REGISTER Also Enhanced Mode Not Driven Select Register 11 10 4 NOT USED V 7F 7E 1 The upper 8 bits of these registers are not driven and pull ups on the carrier data bus will cause these bits to read high 1 s 2 The IOS will return 0 for all addresses that are Not Used Enhanced Mode Memory Maps The following table shows the memory maps used for the Enhanced Mode of operation Enhanced Mode includes the same functionality of Standard Mode but allows each I O port s event sense input and debounce logic to be enabled Thus the Enhanced Mode allows input event triggered interrupts to occur In Enhanced Mode a memory map is given for each of 3 memory banks The first memory bank bank 0 has the same functionality as the Standard Mode Additionally its port 7 register is used to select which bank to access similar to Standard Mode where port 7 was used to select the Enhanced Mode Bank 1 provides read write access to the 48 event sense inputs Bank 2 provides access to the registers used to control the debounce circuitry applied to the event sense inputs SERIES 5 470 SERVER MODULE 48 CHANNEL DIGITAL I O MODULE WITH INTERRUPTS Table
18. ISTORS AS SHOWN THESE SIP RESISTORS ARE INSTALLED IN SOCKETS AND MAY SIP_RESISTOR IDENTIFICATION BE MODIFIED AS REQUIRED SIP VALUE FUNCTION PORT 2 ZERO OHM RESISTOR R7 TIES P2 PIN 49 TO 5V THROUGH FUSE F1 R1 A R1 H 4 7K OHM 007 000 PULLUP PORT O ALTERNATELY R7 CAN BE REMOVED AND R8 CAN BE INSERTED TO TIE P2 PIN 49 R2 A R2 H 4 7K OHM 1 015 1 0 8 PULLUP PORT 1 TO GROUND R7 AND R8 ARE 0805 OHM RESISTORS ACROMAG PART 1400 214 R3 A R3 H 4 7K OHM 17023 1 016 PULLUP PORT 2 MODEL IS SHIPPED WITH ONLY R7 INSTALLED 5V TO P2 PIN 49 R4 A R4 H 4 7K OHM 1 031 1 024 PULLUP PORT 3 3 FUSE F1 TIES P2 PIN 49 TO 5V THROUGH OHM RESISTOR R7 F1 IS A 2 AMP R5 A R5 H 4 7K OHM 1 039 17 032 PULLUP PORT 4 LITTELFUSE NO 466003NR OR EQUIVALENT ACROMAG PART 1430 005 R6 A R6 H 4 7K OHM 1 047 17 040 PULLUP PORT 5 um zu
19. NTERRUPT LINE REGISTERS 0 wo R M gt 1 j i DATA BUS DO D7 _DATA BUS D2 D7 p 45V 45 33V REGISTER T l VBias p ADDRESS BUS ADDRESS BUS 4 7K l 7 5K 25K INTERRUPT pet y 1 047 N ne T IN 4775 VECTOR REGISTER 5 pt OUT 47 ID SPACE 3 3V NOTE INDIVIDUAL 1 0 LINES 5V r INCLUDE ADDITIONAL ESD amp SUBEN SUPPLY C OVER VOLTAGE PROTECTION CONFIGURATION REGULATOR HME 5 CIRCUITRY NOT SHOWN DEVICE 3 3V FILTERING M 4 7K RESISTORS ARE SOCKETED i SUPPLY k l oL GND N PIN 5 085 470 PULLUP RESISTOR LOCATION DRAWING FOR REMOVAL AND REPLACEMENT WHERE REQUIRED NOTE THAT OHM RESISTOR R7 TIES P2 PIN 49 TO 5V HOWEVER IT MAY BE REMOVED AND 0 OHM RESISTOR R8 INSERTED TO TIE P2 PIN 49 TO SIGNAL COMMON ee eee ee COM P2 O 0 R3 B 56 O RESISTOR SIPS ARE MOUNTED IOS 470 PARTIAL VIEW krez ill IN SOCKETS AND CAN BE 1 REMOVED IF REQUIRED RESISTOR SIPS ARE DIVIDED AS SHOWN 1 8 COMMON PIN RESISTOR SIPS ARE GROUPS OF EIGHT olla RESISTORS WITH A COMMON PIN 9 PINS 3 8 PIN 1 POSITION IS IDENTIFIED BY A DOT alie sifp THE COMMON PINS OF elilE THE RESISTOR SIPS ARE JUF CONNECTED TO 5 i 8 c R1 9 UJH O R4 fg O DETAIL A MODULE IS SHIPPED WITH ALL NOTES CONCERNING PULLUP RESISTORS R1 R6 ZERO OHM RESISTORS R7 RB AND FUSE F1 SIP RESISTORS INSTALLED 1 ALL I O POINTS INCLUDE OPEN DRAIN OUTPUT CIRCUITRY WITH 4 7K OHM PULLUP RESISTORS TO 5V IN THE FORM OF SIP RES
20. OS technology As such output levels are CMOS compatible even while sinking high current see Specifications Section SERIES 5 470 SERVER MODULE 48 CHANNEL DIGITAL I O MODULE WITH INTERRUPTS e Output Readback Function Readback buffers are provided that allow the output port registers to be read back e High Output Sink Capability All outputs may sink up to 15mA with a voltage drop lt 0 5V e Outputs are Glitch Free Unlike some competitive units the outputs of this device do not glitch momentarily turn on upon power up or power down for steady and safe control e Open Drain Outputs Include Pull ups All outputs include 4 7K pull ups to 5V in the form of resistor SIP s installed in sockets on the board for convenient removal or replacement 9 Overvoltage Protection Individual I O channels include over voltage clamps for increased ESD amp transient protection e High Impedance Inputs High impedance inputs minimize input current and loading of the input source e No Configuration Jumpers or Switches All configuration is performed through software commands with no internal jumpers to configure or switches to set e Industry Compatible P2 Pinouts the field side P2 pinout configuration of this module is common to similar models and directly compatible with industry accepted digital I O cards screw termination panels and electromechanical amp solid state relay boards consult factory fo
21. Port 5 Not Driven Register l O40 I O47 Also Current Bank Status WRITE Port 7 ENHANCED MODE REGISTER BANK 1 DEFINITION READ Port 0 Not Driven Event Sense Clear Register Port 1 I O Points 8 15 WRITE Port 1 Mia PERI Table 3 1B continued Base MSB LSB Base Addr D15 D08 D07 D00 Addr ENHANCED MODE REGISTER BANK 1 DEFINITIONS READ Port 6 Event Status for Ports 0 5 and Interrupt Status Reg WRITE Port 6 Event Polarity Control Register for Port 0 3 READ Port 7 Event Polarity Control for Ports 4 amp 5 and Current Bank Status Reg WRITE Port 7 Event Polarity Control for ee Not Driven Ports 4 amp 5 and Bank Select Register ENHANCED MODE REGISTER BANK 2 DEFINITION NOT USED READ WRITE Interrupt Enable Register enables INTREQO amp Software Reset Generator NOT USED for Ports 0 5 READ WRITE Port 1 NL m Not Driven Debounce Clock Select 8MHz or 1 047 31 30 4 NOT USED 4 7F 7E Notes Table 3 1 READ WRITE Port 0 Debounce Control Register me BED Debounce Duration Reg 0 m for Ports 0 3 READ WRITE Port 2 Debounce Duration Reg 1 for Ports 4 amp 5 WRITE ONLY Port 3 09 Port 4 5 6 08 oD READ WRITE Port 7 BID Bank Status Select ag Register INDEPENDENT FIXED FUNCTION REGISTERS BM 1F 1E READ WRITE 1 The upper 8 bits of these registers are not driven and pull up
22. annels would use the Port 7 address Note that this port address has a dual function depending on whether a read or write is being executed As such if the current polarity configuration for the other ports must be preserved then it must be remembered since it cannot be read back 13 8 10 11 12 13 To enable event sensing for the port 0 I O points write FFH to the Event Sense Status Register for port 0 I O points at the port 0 address in this bank Note that writing a 1 to a bit position enables the event sense detector while writing a 0 clears the event sensed without enabling further event sensing Write OOH to the port 7 address to select register bank 0 where the port 0 input channels may be write masked Note that the port 7 address bank selection only operates from bits 6 amp 7 of this register while bits 0 3 are used to select the event polarity for port 4 5 I O channels Keep this in mind when switching banks so as not to inadvertently change the polarity configuration of port 4 amp 5 input channels in the process of switching register banks Likewise this register has a dual function depending on whether a read or write is executed As such the polarity settings cannot be read back and must be remembered if they are to be preserved for successive writes At this point you are in Enhanced Mode Bank 0 where access to the write mask register is obtained For our example port 0 I O points a
23. ard Default Mode Memory Map The following table shows the memory map for the Standard Mode of operation This is the Default mode reached after power up or system reset Standard Mode provides simple monitor and control of 48 digital I O lines In Standard Mode each I O line is configured as either an input or an output with readback capability but not both Data is read from or written to one of eight groups ports as designated by the address and read and write signals A Mask Register is used to disable writes to I O ports designated as input ports That is when a port group of 8 I O lines is used as an input port writes to this port must be blocked masked to prevent contention between the output circuitry and any external device driving this line To switch to Enhanced Mode four unique bytes must be written to port 7 in consecutive order without doing any reads or writes to any other port and with interrupts disabled This is usually done immediately after power up or reset The data pattern to be written is 07H ODH 06H and 12H and this must be written after reset or power up Table 3 1A 5 470 R W Space Address Hex Memory Map Base MSB LSB Base Addr D15 D08 D07 DOO Addr STANDARD MODE DEFAULT REGISTER DEFINITION READ WRITE Port 0 Not Driven Register 0 7 READ WRITE Port 1 Not Driven Register l O8 I O15 READ WRITE Port 2 Not Driven Register 1 016 23 07 R
24. ct Register then the debounce times are selected as shown below to within 250nS Alternately the debounce clock may be input on 1 047 and other values configured see Debounce Clock Select Register but this reduces the effective number of input channels to 47 Debounce Duration Register 0 Duration 8MHz 3 Port 1 Debounce Value Bit 1 4 Port 2 Debounce Value Bit 0 5 Port 2 Debounce Value Bit 1 SERIES 5 470 SERVER MODULE 48 CHANNEL DIGITAL I O MODULE WITH INTERRUPTS Debounce Duration Register 1 DEBOUNCE CONTROL Port 4 Debounce Value Bit 0 Port 4 Debounce Value Bit 1 Port 5 Debounce Value Bit 0 Port 5 Debounce Value Bit 1 4 5 6 7 NOT USED Note that with an 8MHz clock a debounce value of 00 sets a nominal value of 4us 01 sets 64us 10 sets 1ms and 11 sets 8ms The default value is 00 setting a 4us debounce period for an 8MHz debounce clock When using 1 047 as the debounce clock the effective debounce can be calculated by taking the clock period in seconds and multiplying it by the appropriate constant shown in the table below The debounce will have an error of 2 clock periods Debounce Duration Debounce Selection Count Constant o 35 8000 64000 Debounce Clock Select Register Enhanced Mode Bank 2 Port 3 Write Only This register selects the source clock for the event sense input debounce circuitry If bit 0 of this register is 0 default value t
25. d Technology SMT to achieve its wide functionality and is an ideal choice for a wide range of industrial I O applications that require a high density highly reliable high performance interface at a low cost Important Note The following IOS model are accessories to the IOS Server Models IOS 7200 IOS 7200 WIN IOS 7400 and IOS 7400 WIN which are cULus Listed This equipment is suitable for use in Class Division 2 Groups A B C and D or non hazardous locations only MODEL OPERATING TEMPERATURE RANGE 5 470 40 to 8550 KEY 5 470 FEATURES e High Channel Count Provides programmable monitor and control of 48 I O points Four units mounted on a carrier board provide 192 I O points in a single VMEbus or PCI bus System slot e Programmable Polarity Event Interrupts all 48 channels Interrupts are software programmable for positive low to high or negative high to low input level transitions on all 48 channels Using two channels per input signal change of state transitions may also be configured for up to 24 inputs e Programmable Debounce all 48 channels The event sense input circuitry includes programmable debounce times for all 48 channels Debounce time is the duration of time that must pass before the input transition is recognized as valid This helps prevent false events and increases noise immunity e CMOS TTL Compatible Input threshold is at TTL levels and includes hysteresis I O circuitry uses CM
26. ebounce Duration Register 0 An incoming signal must be stable for the entire debounce time before it will be recognized as a valid input transition Note that Debounce Duration Register 1 port address 2 would be used to configure debounce durations for I O points of ports 4 amp 5 5 Enable the debounce circuitry for port 0 inputs by setting bit 0 of the Debounce Control Register Write 01 to the Port 0 address of this bank Debounce Control Register If the module had been configured earlier you would first read this register to check the existing settings of debounce enable for the other ports of this module with the intent of preserving their configuration by adjusting the value written above 6 Write 40H to the port 7 address to select register bank 1 where the event polarity requirements of our application will be configured At this point you are in Enhanced Mode Bank 1 where access to the event polarity status registers is obtained 7 For change of state detection both positive and negative polarities must be sensed As such two channels are required to detect a change of state on a single input signal For our example 9 will be used to detect positive events low to high transitions 004 07 will be used to detect negative events high to low transitions Write 01H to the port 6 address to set I O00 I O03 to positive edge detection and l O04 07 to negative edge detection Port 4 and 5 I O ch
27. ed to complete an interrupt select cycle Note that the state of the inputs on off can be determined by reading the corresponding port address while in bank 0 of the Enhanced Mode However the event sense status can only be read by reading the corresponding port address while in bank 1 of the Enhanced Mode Remember the event sense status is a flag that is raised when a specific positive or negative transition has occurred for a given I O point while the state refers to its current level Note that the Interrupt Enable Register and Interrupt Vector Register are cleared following a power up or bus initiated software reset but not a software reset initiated via writing a one to bit 1 of the Interrupt Enable Register Keep this in mind when you wish to preserve the information in these two registers following a reset PROGRAMMING EXAMPLE The following example outlines the steps necessary to configure the IOS 470 for Enhanced Mode operation to setup event generated interrupts configure debounce and read and write inputs It is assumed that the module has been reset and no prior non default configuration exists For this example we will configure port 0 I O points as a four channel change of state detector For change of state detection both positive and negative polarities must be sensed and thus two channels are required to detect a change of state on a single input signal 1 000 1 003 will be used to detect positive events low
28. errupt asserted event sensed Note that the interrupt status flag may optionally drive the Interrupt Request Line of the carrier board see Interrupt Enable Register Event Interrupt Status Register For Ports 0 5 0 Porto Interrupt Status O0 VO7 1 PorttintemuptStatus O8 VO15 2 Port2 Interrupt Status O16 O23 3 Port 3 Interrupt Status O24 O31 4 Port 4 Interrupt Status O32 O39 5 Port Interrupt Status O40 l O47 6 NOTUSED Event Polarity Control Register For Ports 0 3 Enhanced Mode Bank 1 Port 6 Write Only A write to this register controls the polarity of the input sense event for nibbles of ports 0 3 channels 0 31 four channels at a time A 0 written to a bit in this register will cause the corresponding event sense input lines to flag negative events high to low transitions A 1 will cause positive events to be sensed low to high transitions The polarity of the event sense logic must be set prior to enabling the event input logic Note that no events will be detected until enabled via the Event Sense Status amp Clear Register Further interrupts will not be reported to the carrier board unless control of Interrupt Request Line 0 has been configured via the Interrupt Enable Register Event Polarity Control Register WRITE 0 NEGATIVE WRITE 1 POSITIVE Negative Events on Positive Events on vos Pono ton mou vos 1 Negative Events
29. f incoming signals Memory is organized and addressed in separate banks of eight registers or ports eight ports to a bank The Standard Mode of operation addresses the first group of 8 registers or ports ports 0 5 for reading writing 0 47 Port 6 which is not used and Port 7 which is the Mask Register If the Enhanced Mode is selected then 3 additional banks of 8 registers are accessed to cover the additional functionality in this mode The first bank of the Enhanced Mode bank 0 is similar in operation to the Standard Mode The second bank bank 1 provides event sense and interrupt control The third bank is used to configure the debounce circuitry to be applied to input channels in the Enhanced Mode Two additional registers are provided to enable the interrupt request line generate a software reset and store the interrupt vector The I O space may be as large as 64 16 bit words 128 bytes using address lines A1 A6 but the IOS 470 uses only a portion of this space The I O space address map for the IOS 470 is shown in Table 3 1 Note the base address for the IOS module I O space see your carrier board instructions must be added to the addresses shown to properly access the I O space All accesses are performed on an 8 bit byte basis DO D7 Note that some functions share the same register address For these items the address lines are used along with the read and write signals to determine the function required Stand
30. f the IER Register will cause this type of software reset to occur Reset in this manner has been provided for use with some ISA carriers which do not implement the bus reset control or when the interrupt vector and interrupt enable information must be preserved following reset Basic I O Operation Note that the I O lines of this module are assembled in groups of eight Each group of eight I O lines is referred to as a port Ports 0 5 control and monitor I O lines 0 47 Additionally ports are grouped eight to a bank There are four banks of ports used for controlling this module Standard Mode plus Enhanced Mode Banks 0 1 and 2 plus 2 additional registers for enabling the interrupt request line generating a software reset and storing the interrupt vector 11 In both the Standard and Enhanced operating modes each group of eight parallel input lines port are gated to the data bus DO D7 lines These input signals are inverted when an output is ON set to 1 the transistor sinks current and drives the output low this is readback as a 1 Inputs include hysteresis Further each input port is connected such that the current status of a given output port can be read back via the corresponding input port Individual ports may also be masked from writes to the port when the port is intended for input only and this helps prevent contention errors Each port I O line includes an integrated 47 5KQ nominal pull up re
31. hen the debounce source clock is taken from 1 047 pin 41 of P2 thus reducing the effective number of inputs to 47 If bit 0 is set to 1 then the 8MHz IOS bus clock is used recommended Bits 1 7 of this register are not used and will always read as zero WARNING IF USING 1 047 AS THE DEBOUNCE CLOCK DO NOT SET THE I O AS AN ACTIVE OUTPUT VIA THE PORT I O REGISTERS SETTING 1 047 AS AN ACTIVE OUTPUT MAY CAUSE A BUS CONFLICT Bank Select Write amp Status Read Register 2 Enhanced Mode Bank 2 Port 7 Read and Write Bits 0 5 of this register are not used Bits 6 amp 7 of this register are used to indicate read or select write the bank of registers to be addressed In Enhanced Mode three banks banks 0 1 amp 2 of eight registers may be addressed Bank 0 is similar to the Standard Mode bank of registers Bank 1 allows the 48 event inputs to be monitored and controlled Bank 2 registers control the debounce circuitry of inputs Bits 7 and 6 select indicate the bank as follows Bank Select Write amp Status Read Register Bit 7 Bit6 BANK OF REGISTERS 00 BankO Read Write Bank 1 Event Status Clear Bank 2 Debounce Control Clock amp Duration INVALID DO NOT WRITE INDEPENDENT FIXED FUNCTION CONTROL REGISTERS Interrupt Enable amp Software Reset Register Read Write Bit 0 of this register specifies if the internal event sense interrupts are to be reported to the carrier or not i e whether they
32. hree banks banks 0 2 of eight registers may be addressed Bank 0 is similar to the Standard Mode bank of registers Bank 1 allows the 48 event inputs to be monitored and controlled Bank 2 registers control the debounce circuitry of the event inputs Bits 7 and 6 select the bank as follows Bank Selected Status Register Read Bit 7 Bit6 BANK OF REGISTERS 00 Bank 0 Read Write Bank 1 Event Status Clear 10 Bank 2 Event Debounce Control Clock and Duration INVALID DO NOT WRITE BANK 2 REGISTERS Debounce Control Register Enhanced Mode Bank 2 Port 0 Read Write This register is used to control whether each individual port is to be passed through the debounce logic before being recognized by the circuitry A 0 disables the debounce logic and a 1 enables the debounce logic Debounce is applied to both inputs and event sense inputs and only in Enhanced Mode Debounce Control Register CONTROL Poto OCO7 Debounce Duration Register 0 Enhanced Mode Bank 2 Port 1 Read Write Debounce Duration Register 1 Enhanced Mode Bank 2 Port 2 Read Write These registers control the duration required by each input signal before it is recognized by each individual input in the Enhanced Mode both inputs and event inputs Register 0 controls debounce for ports 0 3 Register 1 controls debounce for ports 4 amp 5 If the debounce clock selected is the 8MHz IOS clock see Debounce Clock Sele
33. ication ID PROM Hex Offset From ID PROM Base Address Numeric Value Hex as ae ae 06 43 A3 AcromagID Code 08 IOS Model Code Not Used Revision Field Description EET 0 Reseved 0 NotUsed 12 00 NotUsed ID PROM Bytes Notes Table 3 2 1 The IOS model number is represented by a two digit code within the ID PROM the IOS 470 model is represented by 08 Hex THE EFFECT OF RESET Power up or bus initiated software reset will set the outputs to the false high state and place the module in the Standard Operating Mode thus disabling debounce and event detection Pull ups on the I O lines ensure a false high input signal for inputs left floating i e reads as 0 A reset will also clear the mask register and enable writes to the I O ports Further all I O event inputs are reset set to negative events and are disabled following reset The Interrupt Enable Register IER and Interrupt Vector Register IVR are also cleared except for IER generated software resets Another form of software reset IER register initiated acts similar to a carrier or power up reset except that it is not driven by the carrier and only resets the digital ASIC chip installed on the module As such the Interrupt Vector Register and Interrupt Enable Register are not cleared for a software reset initiated in this manner writing a 1 to the bit 1 position o
34. ies with EN61000 4 3 10V m 80 to 1000MHz AM amp 900MHz keyed and European Norm EN50082 1 with no digital upsets Complies with EN61000 4 6 3V rms 150KHz to 80MHz and European Norm EN50082 1 with no digital upsets No digital upset under the influence of EMI from switching solenoids commutator motors and drill motors Complies with EN61000 4 2 Level 3 8KV enclosure port air discharge and Level 2 4KV enclosure port contact discharge and European Norm EN50082 1 Not required for signal I O per European Norm EN50082 1 Immunity EFT Complies with EN61000 4 4 Radiated Emissions DIGITAL INPUTS Level 2 0 5KV at field I O terminals and European Norm EN50082 1 Meets or exceeds European Norm EN50081 1 for class B equipment Shielded cable with I O connections in shielded enclosure are required to meet compliance Input Channel Configuration 48 buffered inputs For DC voltage applications only observe proper polarity Input Debounce Each input includes debounce circuitry with variable debounce times Debounce times are programmable and derived from a clock signal present on 1 047 or the 8MHz system clock in combination with the debounce duration register value Note that if the debounce clock is delivered on 1 047 then this effectively reduces the number of inputs to SERIES 5 470 SERVER MODULE 48 CHANNEL DIGITAL I O MODULE WITH INTERRUPTS 47 As
35. nstructions Model IOS 470 digital I O boards have no hardware jumpers or switches to configure However 4 7KQ pull up resistor SIP s are installed in sockets on the board and these may be easily changed or removed where required see IOS 470 Pullup Resistor Locations SERIES 5 470 SERVER MODULE 48 CHANNEL DIGITAL I O MODULE WITH INTERRUPTS CONNECTORS IOS Field I O Connector P2 P2 provides the field I O interface connections for mating IOS modules to the carrier board P2 is a 50 pin female receptacle header which mates to the male connector of the carrier board AMP 173280 3 or equivalent This provides excellent connection integrity and utilizes gold plating in the mating area The field and logic side connectors are keyed to avoid incorrect assembly P2 pin assignments are unique to each IOS model see Table 2 1 and normally correspond to the pin numbers of the field I O interface connector on the carrier board you should verify this for your carrier board Table 2 1 5 470 Field I O Pin Connections P2 Pin Description Number Pin Description Number vooo 8 P P o vo2 6 10 R R T T 0 3 P P T T 1 4 09 P P T T 2 5 5V OUT Note COMMON 1 By default pin 49 of P2 is connected to the 5V supply of the IOS module but may be optionally connected to common or opened by repositioning surface mount resistor R72 see page 16 f
36. ombine debounce with event sensing to obtain glitch free edge detection of incoming signals for all 48 channels That is the debounce circuitry will automatically filter out glitches or transients that can occur on received signals for error free edge detection and increased noise immunity With debounce an incoming signal must be stable for the entire debounce time before it is recognized by the I O or event sense logic Debounce is applied to both inputs and event sense inputs and only in Enhanced Mode The debounce circuitry can be configured to use the 8MHz carrier clock or a clock signal present on 1 047 to determine the debounce times see the Debounce Clock Select register If the debounce clock is taken from 1 047 then the effective number of inputs is reduced to 47 If the IOS 470 is configured to use the 8MHz carrier clock recommended a debounce value of 4us 64us 1ms or 8ms may be selected see the Debounce Duration Register As such an incoming signal must be stable for the debounce time before it is recognized by the I O pin or event sense logic A slower clock may be used to provide even longer debounce times this clock would have to be provided on 1 047 Upon initialization of the debounce circuitry be sure to delay at least the programmed debounce time before reading any of the input ports or event signals to ensure that the input data is valid prior to being used by the software 12 Interrupt Generation
37. on Positive Events on Poko Vos trougn vor Pao vO rouen vor Negative Events on Positive Events on Port Yos tronar von pon 17os rouen von Ka Negative Events on Positive Events on Port 1 1 012 through Port 1 1 012 through 1 015 1 015 Negative Events on Positive Events on Port 2 1 016 through Port 2 1 016 through 1 019 1 019 Negative Events on Positive Events on Port 2 1 020 through Port 2 1 020 through 1 023 1 023 Negative Events on Positive Events on Port 3 1 024 through Port 3 1 024 through 1 027 1 027 Negative Events on Positive Events on Port 3 1 028 through Port 3 1 028 through 1 031 1 031 SERIES 5 470 SERVER MODULE 48 CHANNEL DIGITAL I O MODULE WITH INTERRUPTS Event Polarity Control For Ports 4 amp 5 amp Bank Select Register Enhanced Mode Bank 1 Port 7 Read Write A write to this register controls the polarity of the input sense event for nibbles of ports 4 amp 5 channels 32 47 four channels at a time A written to a bit in this register will cause the corresponding event sense input lines to flag negative events high to low transitions A 1 will cause positive events to be sensed low to high transitions The polarity of the event sense logic must be set prior to enabling the event input logic Note that no events will be detected until enabled via the Event Sense Status amp Clear Register Further interrupts will not be reported to the carrier board unless con
38. or location The 5V connection is in series with fuse F1 2A Littelfuse 245002 or equivalent Note that the I O points of this module are assembled in groups of eight Each group of eight I O lines is referred to as a port Registers at port addresses 0 5 control and monitor I O lines 00 47 Individual I O ports may be masked from writes to the port when the port is used for input This helps prevent contention errors Further event polarities may be defined as positive low to high or negative high to low for individual nibbles groups of 4 I O lines or half ports Outputs of this device are open drain and operate using low level true active low logic The pinouts of P2 are arranged to be compatible with similar industry models and are directly compatible with industry accepted I O panels termination panels and relay racks Consult the factory for information on compatible products Noise and Grounding Considerations The IOS 470 is non isolated between the logic and field I O grounds since output common is electrically connected to the IOS module ground Consequently the field I O connections are not isolated from the carrier board and backplane Special care has been taken in the design of this module to help minimize the negative effects of ground bounce impedance drops and Switching transients However care should be taken in designing installations without isolation to avoid noise pickup and ground loops caused by
39. polarity is to be detected high to low level transitions negative or low to high level transitions positive Set each half port nibble to the desired polarity and then enable each of the event inputs to be detected Optionally load the interrupt vector register and enable the interrupt request line Note that all I O event inputs are reset set to negative events and disabled after a power up or software reset has occurred Note that no events will be detected until enabled via the Event Sense Status amp Clear Register Further interrupts will not be reported to the carrier board unless control of Interrupt Request Line 0 has been configured via the Interrupt Enable Register Change Of State Detection Change of State signal detection requires that both a high to low and low to high signal transition be detected On the IOS 470 if change of state detection for an input signal is desired two channels connected to the same input signal would be required one sensing positive transitions one sensing negative transitions Since channel polarity is programmable on a nibble basis group of four the first nibble of a port could be configured for low to high transitions the second nibble for high to low transitions As such up to 24 change of state detectors may be configured Debounce Control Debounce control is built into the on board digital FPGA employed by the IOS 470 and is enabled in the Enhanced Mode only You can c
40. r recommendations SERVER MODULE INTERFACE FEATURES e High density Single size IOS module footprint Four units mounted on a carrier board provide up to 128 isolated input points in a single system slot e LocalID Each IOS module has its own 8 bit ID which is accessed via data transfers in the ID Read space e 8 bitl O Port register Read Write is performed through 8 bit data transfer cycles SERVER MODULE SOFTWARE IOS MODULE Win32 DRIVER SOFTWARE Acromag provides a software product sold separately to facilitate the development of Windows Embedded Standard applications interfacing with I O Server Modules installed on Acromag Industrial I O Server systems This software Model IOSSW DEV WIN consists of a low level driver and Windows 32 Dynamic Link Libraries DLLS that are compatible with a number of programming environments including Visual C Visual Basic NET Borland C Builder and others The DLL functions provide a high level interface to the IOS carrier and modules eliminating the need to perform low level reads writes of registers and the writing of interrupt handlers IOS MODULE LINUX SOFTWARE Acromag provides a software product sold separately consisting of Linux amp software This software Model IOSSW API LNX is composed of Linux libraries designed to support applications accessing I O Server Modules installed on Acromag Industrial I O Server systems The software is implemented as a library
41. re to be used for inputs only and writes to this port should be masked to prevent the possibility of data contention between the built in output circuitry and the devices driving these inputs Write 01H to the port 7 address to mask writes to port 0 Read 01H from the port 7 address to verify bank 0 access bits 6 amp 7 are 0 and port 0 write masking bit 0 is 1 OPTIONAL Write your interrupt vector to the Interrupt Vector Register Address Note that this register operates independent of the current bank since it does not reside at any of the bank addresses OPTIONAL Write 01H to the Interrupt Enable Register IER address location to enable IOS control of the IOS Interrupt Request 0 line IntReqO When a change of state is detected IntReqO will be pulled low if the event sense detection circuitry has been enabled and IER bit 0 1 In response the host will execute an Interrupt Select cycle and the contents of the Interrupt Vector Register will be provided To enable further interrupts to occur for an event that has already occurred for an I O point the Event Sense Status Register must be written with a 1 to reenable event sensing for subsequent events but only after first writing 0 to the corresponding bit position to clear the event sense flip flop Note that the state of the inputs on off can be determined by reading the corresponding port address while in bank 0 of the Enhanced Mode However the event sense status can
42. round via any device connected to these ports or a ground loop will be produced and this may adversely affect operation 3 0 PROGRAMMING INFORMATION ADDRESS MAPS This board is addressable in the Industrial Pack space to control the input output configuration control and status monitoring or 48 digital I O channels Each of the I O points can be configured as either an input an output or an output with readback capability Interrupt event and debounce capability applies to all 48 channels This board operates in two modes Standard Mode and Enhanced Mode Standard Mode provides simple monitor and control of 48 digital I O lines In Standard Mode each I O line is configured as either an input an output or an output with readback capability Data is read from or written to one of eight groups ports as designated by the address and read and write signals A Mask Register is used to disable writes to I O ports designated as inputs to prevent possible contention between an external input signal and the output mosfet Enhanced Mode includes the same functionality of Standard Mode but adds SERIES 5 470 SERVER MODULE 48 CHANNEL DIGITAL I O MODULE WITH INTERRUPTS access to 48 additional event sense inputs connected to each I O point of ports 0 5 Thus the Enhanced Mode allows event triggered interrupts to be generated Selectable hardware debounce may also be applied in Enhanced Mode for noise free edge detection o
43. s e Software Updates Drivers An email question can also be submitted from within the Knowledge Base or directly from the Contact Us tab Acromag s application engineers can also be contacted directly for technical assistance via telephone or FAX through the numbers listed below When needed complete repair services are also available Phone 248 295 0310 Fax 248 624 9234 Email solutions acromag com 6 0 SPECIFICATIONS GENERAL SPECIFICATIONS Physical Configuration Single O SERVER MODULE neces 4 030 in 102 36 mm Willis 1 930 in 49 02 mm Board Thickness 0 062 in 1 59 mm Height ntes 0 500 in 12 7 mm Power 5 Volts 596 85mA Typical all outputs active 35mA Typical all outputs 12 Volts 596 from P1 ENVIRONMENTAL inactive 160mA Maximum OmA Maximum Not Used Operating Temperature 40 to 85 C Relative Humidity 5 95 non condensing Storage Temperature Non Isolated Radiated Field Immunity RFI Conducted RF Immunity CRFI Electromagnetic Interference Immunity Electrostatic Discharge Immunity ESD Surge Immunity Electric Fast Transient 55 C to 15050 Logic and field commons have a direct electrical connection Compl
44. s on the carrier data bus will cause these bits to read high 1 s 2 The IOS will return 0 for all addresses that are Not Used All Reads and Writes are 0 wait state The Interrupt Vector Register also decodes at base address 6FH due to simplified address decoding BO SERIES 5 470 SERVER MODULE 48 CHANNEL DIGITAL I O MODULE WITH INTERRUPTS REGISTER DEFINITIONS STANDARD MODE REGISTERS Port I O Registers Standard Mode Ports 0 5 Read Write Six I O Registers are provided to control monitor 48 possible points Data is read from or written to one of six groups Ports 0 5 of eight I O lines as designated by the address and read and write signals Each port assigns the least significant data line DO to the least significant I O line of the port grouping e g 1 000 for port 0 Thus a write to this register controls the state of the open drain output low level true A read of this register returns the status ON OFF of the point A Mask Register is used to disable writes to I O ports designated as input ports That is when a port group of 8 I O lines is used as an input port writes to this port must be blocked masked to prevent contention between the output circuitry and any external device driving this input line Outputs are open drain mosfets with pull ups installed Thus on power up or reset the port registers are reset to 0 forcing the outputs to be set high OFF Write Mask
45. sistor to 5V Additional 4 7KQ pull up resistor SIP s are also installed in sockets on the board For inputs the pull ups provide a low false 0 input indication if the input is left floating Each line is in the form of an open drain signal Thus data written to any port used as an input must be masked or always false zero to avoid contention errors between the output circuitry and an input signal from an external device All 48 lines are placed into the false high output state following power up or a system reset The 4 7KQ pull up resistor SIP s installed in sockets on the board provide only limited digital high drive capability for the output signals You may need to adjust these pull up values for your application refer to IOS 470 Pullup Resistor Locations for SIP resistor location Enhanced Operating Mode In the Enhanced Mode of operation each port signal has an associated event sense input and debounce logic circuit The event sense inputs are used to sense high to low level or low to high level transitions on digital input lines at CMOS thresholds Interrupts may also be triggered by events The optional debounce logic can act as a filter to glitches or transients present on the received signals Individual ports may be masked from writes to the port when the port is used for input This helps prevent contention errors Further event polarities may be defined as positive or negative for individual nibbles in
46. such use of the 8MHz System clock is recommended Interrupts eeesesssse 48 channels of interrupts may be configured for high to low low to high and change of state two inputs required event types Input Voltage Range Ground 0 25V to 5 Volt supply 0 25V Input Low Voltage Range 0 8V Maximum to 0 25V below Common Ground Input High Voltage Range 2 2V Minimum to Supply 0 25V Maximum Input transition rise of fall time 3mS V Maximum Input Response Time 250nS Typical Input Threshold 1 5V Typical Input Output Capacitance 20pF Maximum 10pF Typical Input Leakage Current 10uA Typical Debounce Times The Input debounce is implemented using a counter The debounce time can be calculated by taking the clock period in seconds and multiplying it by the debounce count given in the table on the left Note that all debounce times including the internal 8MHz clock have a tolerance of 2 clock periods The default 8MHz has debounce times of DIGITAL OUTPUTS Output Channel Configuration Output Low Voltage Output High Voltage Output ON Current Range 330 Maximum 25 C Output Ras ON Resistance Output Pullups Turn On
47. th logic 0 clears the corresponding event sense flip flop Each data bit of ports 0 5 must be written with a 1 to re enable or initially enable the corresponding event sense input after it is cleared Reading ports 0 5 of Enhanced Mode bank 1 returns the current event sense flip flop status Port 0 Event Sense Status Register Ports 1 5 Similar READ PORT WRITE 0 WRITE 1 Port 0 1 00 Event Clear 0 Event Re enable Status Sense Flip Flop 1 00 Event Sense Port 0 1 01 Event Clear 1 Event Status Sense Flip Flop Re enable 1 01 Port 0 1 02 Event Clear 1 02 Event Status Sense Flip Flop Event Sense Port 0 1 03 Event Clear 1 03 Event Status Sense Flip Flop Re enable 1 02 Port 0 1 04 Event Clear 1 04 Event Status Sense Flip Flop Event Sense 5 Port 0 1 05 Event Clear l O5 Event Status Sense Flip Flop Re enable 1 03 Port 0 1 06 Event Clear l O6 Event Status Sense Flip Flop Event Sense 7 Port 0 7 Event Clear 7 Event Status Sense Flip Flop Re enable 1 04 Event Sense Re enable 1 05 Event Sense Re enable 1 06 Event Sense Re enable 1 07 Event Sense Event Interrupt Status Register For Ports 0 5 Enhanced Mode Bank 1 Port 6 Read Only Reading this register will return the event interrupt status of I O ports 0 5 bits 0 5 and the interrupt status flag bit 7 Bit 7 of this register indicates an event sense was detected on any of the 6 event sense ports 1 int
48. trol of Interrupt Request Line 0 has been configured via the Interrupt Enable Register Event Polarity Control Register WRITE 0 NEGATIVE Negative Events on Port 4 1 032 through 1 035 Negative Events on Port 4 1 036 through 1 039 2 Negative Events on I Port 5 1 040 through 1 043 3 Negative Events on Port 5 1 044 through Port 5 1 044 through 1 047 1 047 6 fBankSelctBtO WRITE 1 POSITIVE Positive Events on Port 4 1 032 through 1 035 Positive Events on Port 4 1 036 through 1 039 Positive Events on Port 5 1 040 through 1 043 Positive Events on Bank Select Bit 1 Bits 6 amp 7 of this register are used to select monitor the bank of registers to be addressed In Enhanced Mode three banks banks 0 2 of eight registers may be addressed Bank 0 is similar to the Standard Mode bank of registers Bank 1 allows the 48 event inputs to be monitored and controlled Bank 2 registers control the debounce circuitry of the event inputs Bits 7 and 6 select the bank as follows Bank Select Register Write Bit 7 Bit6 BANK OF REGISTERS 00 Bank 0 Read Write Bank 1 Event Status Clear 10 Bank 2 Event Debounce Control Clock and Duration INVALID DO NOT WRITE Bank Select Status Register 1 Enhanced Mode Bank 1 Port 7 Read Only Bits 0 5 of this register are not used Bits 6 amp 7 of this register are used to indicate the bank of registers to be addressed In Enhanced Mode t
49. tten to one of six groups Ports 0 5 of eight I O lines as designated by the address and read and write signals Each port assigns the least significant data line DO to the least significant I O line of the port grouping e g 1 000 for port 0 A write to this register controls the state of the open drain output low level true A read of this register returns the status ON OFF of the point A Mask Register is used to disable writes to I O ports designated as input ports That is when a port group of 8 I O lines is used as an input port writes to this port must be blocked masked to prevent contention between the output circuitry and any external devices driving this port Outputs are open drain mosfets with pull ups installed Thus on power up or reset the port registers are reset to 0 forcing the outputs to be set high OFF Write Mask Register And Bank Select Register 0 Enhanced Mode Bank 0 Port 7 Read Write This register is used to mask the ability to write data to the six ports in Enhanced Mode Writing a 1 to bits 0 5 of the Mask Register will mask ports 0 5 from write control respectively A read of this register will return the status of the mask A Mask Register is used to disable writes to I O ports designated as input ports Thus when a port group of 8 I O lines is used for input writes to this port must be blocked masked to prevent contention between the output circuitry and any external devices
Download Pdf Manuals
Related Search