6 ML605 Development Board with 4-‐DSP FMC
Contents
1. A Errors I Findin Files Results 5 Console f Warnings Ln 150 Coll VHDL Open an existing project Figure 6 Opening the project from ISE gt Open Project Organize v New folder Fr Favorites EE Desktop Downloads Recent Places 53 Libraries Es Documents 2 Music Pictures B Videos had B Comnuter a gt Computer OS C fmc150 ISE 14 4 Name d xInx auto 0 xdb J xst E ads62p49_init_mem E amc7823 init mem sse cdce72010 init mem ext LE cdce72010 init mem int Date modified 5 18 2013 1 49 PM 5 17 2013 1 39 PM 5 17 2013 1 44 PM 5 17 2013 1 44 PM 5 17 2013 1 44 PM 5 17 2013 1 44 PM 5 17 2013 1 44 PM Type File folder File folder Xilinx ISE Project Xilinx ISE Project Xilinx ISE Project Xilinx ISE Project Xilinx ISE Project 6 KB 5 KB 5 KB 5KB 5 KB E ILA ADC cali ila_baseband_out 5 18 2013 1 53 PM Xilinx ISE Project 5 17 2013 1 44 PM 5 17 2013 1 44 PM 5 10 2013 11 04 PM Xilinx ISE Project Xilinx ISE Project Xilinx ISE Project 44 KB 6 KB 5 KB 5 KB File name fmc150_ISE_14_4 ia Figure 7 Open the project from the location of the unzipped contents of the project provided with this tutorial 12 4 Select the top file ML605_fmc150 and in the process window directly below the Design Hierarchy double click Generate Programming File As shown in Figure 8 This will synthesize the design produci2. SAN DIEGO STATE UNIVERSITY Virtex 6 ML605 Development Board with 4 DSP FMC 150 ADC DAC Department of Electrical and Computer Engineering Real Time DSP and FPGA lab Colin Fera Matthew Luscher Ashkan Ashrafi inis inii pee 8688 Seehtet ere Oana NE E 74 A 3 5 sks v n systams com Figure 1 ML605 and FMC 150 PUREE OUNCE OND Emm 2 Project Specific Custonmizatlons iet eaa rai Rest E CA s Sa ate skis Rs cR s ARa 3 Requirements co a ma Ea cdc ee dE RUD eee 4 Software ReguirFerients 55 oe dco a dan 5 Hardware Requiremliernts 5 5 itio poeti ete es ta re ort xe co etsi s Tta Soci IE e ERE eR CoU LEL Iu cS DESA Ro sc vuU EE 5 Limitations and Specifications iid tiii n ect be ee ee eee 5 SG CUD aucuns unc ern EISE DELL C ERE CUDAB EcDUA IS ES ED IR CUR HARTE EFC UE FEN UR CLR A 6 Eti rig e n 7 Connecting the MLG05 and FMCG T5003 sut ex D ret b a aic dei ree 7 Connecting the Waveform Function Generator essent nnn tennis 10 Block DI3EBESUYns c acinis n sii ihiisim aim er EE eh ficere iE iu d i tue co tud adit I iU 11 tis irc 12 Running the DESID cuui oui vem ede et iciatis iem esaet i im rue mecs dr ite ed 14 VGPifiCatiOn of Seti Py et 15 Implementation a Digital FIR Filter using Xilinx ISE eese 19 FOC OSS sires Y 19 IrstontidtrOBigsscm pie cei
3. gt 6 250000e 02 6 250000e 02 Input 16 15 gt 1 1 Filter Internals Full Precision Output 36 34 gt 2 2 auto determined Product 31 34 gt 6 250000e 02 6 250000e 02 auto determined Accumulator s36 34 gt 2 2 auto determined Round Mode No rounding Overflow Mode No overflow Numerator fe6b fd99 fca3 fb8b fa57 f90c f7b4 f659 f507 f3ce f2bc f1e2 f151 f11b f14e f1fc f333 f4fe f766 fa72 fe24 027c 0774 0d02 1319 19a7 2096 27cf 2f34 36a8 3e0a 34 453a 4c16 527e 5853 5d78 61d4 654f 67d9 6965 69e9 6965 67d9 654f 61d4 5d78 5853 527e 4c16 453a 3e0a 36a8 2f34 27cf 2096 19a7 1319 0d02 0774 027c fe24 fa72 f766 f4fe 333 fifc f14e f11b f151 fle2 f2bc f3ce f507 f659 f7b4 f90c fab7 fb8b fca3 fd99 fe6b 35 References 1 No author provided 2010 Xilinx Vertex 6 DSP Development Kit with High Speed Analog Available https www em AVNET com Support 20And 20Downloads virtex6dsp_rtl_referen ce_design_tutorial_13_1 zip 2 No author provided 2010 FMC150 User Manual Available https www em AVNET com Support9620And9620Downloads FMC150 user manual pdf 36
4. Bits 0 Range 0 0 Datapath Options L Number of Paths 1 Range 1 16 E Input Data Type Signed v Input Data Width 14 Range 2 48 Ge aoa we e X Input Data Fractional Bits 0 Range 0 14 Normalized Frequency x PI rad sample Output Rounding Mode Symmetric Rounding to Zero z t Output Width 16 Range 1 31 Set to Display 1 Range 1 1 Output Fractional Bits 0 pur Analysis Allow Rounding Approximation Passband Stop band 7 Registered Output M Range 0 0 220 5 0 5 11 0 Min 26 226911 dB Max 102 390973 dB 22 907857 dB Ripple 128 617884 dB E IN P Symbol J Freq Response 5 Implementation Details Dotashoct Page 2 of uiis onorate Cancel Help Figure 19 FIR Compiler Widow 13 At this point since no other options need to be changed from the default values click generate This will generate the IP core the process takes about 1 2 minutes 14 The filter IP core you created should be visible under the Verilog module sample pass inst this indicates that the filter is being instantiated under that module as shown below sample pass inst sample pass sample pass v q firl lowpass lowpass xco icon_inst icon icon xco This concludes this part of the tutorial 24 Instantiation This code below is the actual sample_pass_inst where the filter in this tutorial is being instantiated Note the multiplexers that control how data is routed between inputs and
5. DDC Out ILA Trigger Setup Waveform TM _ Using 0 5 5 Ecc WL Async Input Port Sync Input Port ADC Ch A iDelay at output of iodela Scope Pro ADC Ch B iDelay at output of iodelz ADC CLK iDelay at output of iodela Register Data FPGA RD from FMG CH 47 SPI bus BUSY Async Output Port Sync Output Port Register Address AD h AiDela P wv Reading file C fmc150 ISE 14 4Wml605 fmc150 bit Figure 11 After the FGPA is programmed the lost most pane should populate with relevant information regarding the detected programmed devices 16 12 Select UNIT 0 from the left most pane and double click VIO Console As shown in Figure Select ADC channel A iDelay from the VIO console type 25 and hit enter Jf you intend to use Chanel B of the ADC then it should set to the same value Note The connection between the ADC and DAC within the FPGA is not registered making setup and hold times more critical The setup and hold times cannot be maintained within the FPGA at the sampling frequency used in this tutorial The iDelay Incremental Delay adds a sub clock period delay to the clock at critical points allowing the setup and hold times to be maintained Without this you will essentially see noise being output by the DAC r el ChipScope Pro Analyzer ml605 fmc150 File View JTAG Chain Device VIO Window Help JTAG
6. lowpass hex In the above command h is the filter itself simple lowpass is the name of the file to be exported hex is the data format The coefficients are listed under numerator Numerator fe6b fd99 fca3 32 MATLAB Code The following script Sets parameters for a simple digital low pass filter Generates the low pass filter Displays the filters response graphically Retrieves hex coefficients which can be directly used in a COE file fp 5e6 freq at beging of pass band 5MHz fst 9e6 freq at end of stop band 9MHz n 80 filter order 80 fs 245e6 Y sampling frequency 245MHz Instruct MATLAB to design the filter specified above f fdesign lowpass N Fp Fst 80 fp fst fs Generate a direct form low pass filter using above specifications h design f firls Wpass 1 WStop 100 FilterStructure dffir set filter to fixed type set h Arithmetic fixed use the filter visualization tool to hfvt fvtool h retrieve filter coefficients as hex list fcfwrite h simple_lowpass hex 33 MATLAB Filter Coefficients Generated by MATLAB R 7 12 and the Signal Processing Toolbox 6 15 Generated on 19 May 2013 16 44 36 Coefficient Format Hexadecimal Discrete Time FIR Filter real eee ee Filter Structure Direct Form FIR Filter Length 81 Stable Yes Linear Phase Yes Type 1 Arithmetic fixed Numerator 16 19
7. oscilloscope 14 Verification of Setup 1 With the Xilinx project navigator open from the last step of Preparing the Software double click on Analyze Design Using ChipScope A window should popup as shown in Figure 9 2 Inthe upper left of the ChipScope Pro window click the icon This icon opens the JTAG search chain and searches for Xilinx cores 3 Two devices should be detected displayed in the most pane of the ChipScope window DEV 0 and DEV 1 4 Right click DEV 1 and select Configure As shown in Figure 9 ie 4 Project ml605 fmc150 JTAG Chain DEV 0 MyDevice0 System ACE CF I Rename Signals DEV 1 UNI 9 Data Port ADC ChA Show IDCODE LN ADC Ch B Show USERCODE Trigger Ports 4 1 Show Configuration Status Show JTAG Instruction Register q hipScope Pro a w Reading project file C imc150_ISE_14_4 mI605_fmc150 cpj Figure 9 This window will appear only after a bit file has been generated and the reader clicked on Analysis Design using Chipscope This figure shows what you should expect to see in the left pane after step two from above 15 yn After clicking on Configure Click Select New File and locate ml605_fmc150 bit 6 Select open then select OK This is the bit file that was generated in Preparing the Software This will program the FPGA using the selected bit file Note if the board is power cycled the board must be
8. outputs and also between the inputs and the filter The dipswitches that control the multiplexers are numbered one through eight and are shown in Figure 25 module sample pass input clk fs clk gfs input 13 0 din a din b output 15 0 dout a dout b input 7 0 gpio dip sw J wires used in IO Muxes wire 13 0 dinf wire 15 0 doutf 1O Muxes select how inputs are passed to outputs assign dout a gpio_dip_sw 1 0 1 doutf gpio dip sw 1 0 2 din b 2 b00 din_a 2 b00 assign dout b gpio dip sw 3 2 1 doutf gpio dip sw 3 2 2 din 3 2 b00 din b 2 b00y combinational assignment of the either input A or B to the filter assign dinf gpio dip sw 5 din a din b the actual instantiation of the filter lowpass fir1 din dinf dout doutf clk clk gfs endmodule Figure 20 Dipswitches 25 Verification At this point it is assumed that all previous tutorial sections have been completed 1 e Setup o Preparing the Hardware o Preparing the Waveform Signal Generator o Preparing the Software e Design a Simple Digital Filter using MATLAB e Implement a Digital FIR Filter using ISE Ensure your setup identical to Diagram 1 in the Preparing the Hardware section 2 Activate channels one two and three on the oscilloscope and verify that a sine wave at 3 4 the previously set frequency is displayed on all three channels As shown in figure 22 Note the
9. purple signal is the signal being passed through the filter Its appearance should look very similar because the frequency of the signal from the function generator has not been tuned to the cutoff frequency of the filter Ink Saver or NL Save File Utilities Figure 21 Expected signals displayed on the oscilloscope Record the peak amplitude of the filtered sine wave to verify the cutoff frequency when you increase the frequency of the signal later in the instructions Increase the frequency of the function generator until the amplitude of the filtered signal drops to 707 Vpeak of the reference signal This is the 3DB point at which signal power has fallen by half its original voltage denoting the start of the filter s cutoff frequency Compare this point to the 3DB frequency shown in the MATLAB plot they should similar but not exact 26 6 Continue to increase the frequency of the function generator beyond the filter cutoff The amplitude of the filtered signal should fall gradually to zero as the frequency is increased towards the stop frequency As shown in Figure 23 and Figure 24 Ink Saver or NL Save File Utilities Ink Saver Off NL Save File Utilities Figure 23 Function generator output at 9Mhz This concludes this part of the tutorial ZT Appendix The appendix of the tutorial provides the reader with additional tutorials and documentation 28
10. reprogrammed See Figure 10 7 The FPGA is now programmed and you should expect to see the ChipScope Pro left most pane populate As shown in Figure 11 mn ystem ACE CF COEVI JT ChipScope Pro Analyzer ml605 fmc1 E4 Open Configuration File Lookin fmc150 ISE 14 4 eH J _bbx Js tmp rie di _cg P xinx_auto_0_xdb Recentitems _ngo Ji xst J _xmsgs Bi mi605_fmc150 bit Jo ads62p49 init mem Ww Js ads62p49 init mem ste Desktop J mc7823 init mem ste u J cdce72010 init mem ext ste E D cdce72010 init mem int ste J dac3283 init mem ste My J demo tb i ipcore dir 7 Ji iseconfig J MMCM Computer J mmcm_adac JJ testbench a File name ml605 fmc150 bit Network JTAG Configuration File mi605 fmc150 bit Directory CMmc150 ISE 14 4 Partial Reconfiguration Bitstream C Clean previous project setting Select New File C Import Design level CDC File NOTE This operation cannot be undone Design evel CDC File C Auto create Buses Files oftype bitfiles bit File N Figure 10 Select the generated bit file generated in Preparing the Software r el ChipScope Pro Analyzer ml605 fmc150 t 4 U File View JTAG Chain Device Window Help Project ml605 fmc150 BE JTAG Chain DEV 0 MyDevice0 System ACE CF DEV 1 MyDevice1 XC6VLX240T System Monitor Console UNIT 0 MyVIOO VIO UNIT 11ILA
11. to Display 1 Select format Frequency Specification Y m Filter Analysis Input Sampling Frequency 245 76 Range 0 000001 550 0 MHz Passband Stop band j xol coe E Range 0 0 05 0 5 E10 Clock Frequency 491 52 Range 245 76 550 0 MHz i Min 26 226911 dB Input Sample Period 1 Range 1 10000000 Clock cycles Max 102 390973 dB 22 907857 dB Ripple 128 617884 dB e IPSymbol 4 Freq Response Implementation Details lt Back Pagelof4 Next gt Generate Cancel Help Figure 18 Defining the filter 23 9 Click next to move on to page 2 of the FIR compiler menu 10 Change the input data width to 14 Note the FMC 150 has a 14Bit ADC 11 Change output rounding mode to any choice other than full precision in this case we have chosen symmetric rounding to zero 12 Change the output width to 16 all other choices can be left at the default values as shown below lt a FIR Compile Documents View Freq Response Bx ig iC PE logi o FIR Compiler xilinx com ip fir compiler 5 0 M Frequency Response Magnitude Filter Architecture Systolic Multiply Accumulate Coefficient Options Use Reloadable Coefficients Coefficient Structure Inferred x W Coefficient Type Signed Quantization Integer Coefficients Y Coefficient Width 16 Range 2 49 i E Best Precision Fraction Length E Coefficient Fractional
12. E rrr ere nearer ren rere n E NUM eee eer 25 AY 18 672 08 0 cen crn ete fern nr nearer retro er eee eee 26 wgibcste D M 28 Running the ML605 Reference Design In ISE13 1 eese nnn 29 Designing a Digital LPF in MATLEAB iiiusucaeriisi en anre a 30 Proces nean react ales dp LUND eU M cS to e EDU ay 30 MATLAB COd RC ome 33 MATLAB Fer COSITICIGEHUS uditeiesit a t rae doe bc todo a or uen deat 34 AM ICE E eed 36 Introduction The purpose of this tutorial is to help familiarize readers with the use of the AVNET Xilinx Virtex 6 based ML605 development kit and in particular the accompanying 4 DSP FMC 150 analog to digital converter ADC and digital to analog converter DAC for real time digital signal processing DSP applications This tutorial assumes familiarity with hardware description languages HDL s and basic concepts of digital signal processing By following this tutorial and using the accompanying VHDL Verilog code the reader should be able to Configure the DAC to pass data through from the ADC e Implement a basic Low pass filter with the aid of MATLAB Located in the appendix Portions of this tutorial have been taken from various AVNET and Xilinx tutorials and documentation accompanying the board Document names as well as links are provided in the references section at the end of
13. L605 and FMC 150 1 Insert the FMC 150 into LPC FMC connector J63 on the ML605 board as shown in Figure 1 Figure 2 Inserting the FMC 150 board into the ML605 board Apply slight pressure to ensure proper connection 2 Connect ADC input B and DAC outputs C and D to MMCX to BNC cables as shown below Inserting these cables requires slight force you should heard and feel the connection Click into place See Figure 2 Figure 3 Connecting the signal cables to the FMC 150 When inserted properly the reader should feel and hear the cables click into place Inputs A and External Clock are not used in this tutorial 3 Connect a mini B USB cable to the USB female J22 on the ML605 labeled JTAG As shown in Figure 4 Connect the other end to your computer 4 Set the dipswitches on the lower right corner ML605 board adjacent to the USB to all OFF a Y ty L ag 4 WLCth Figure 4 Connect a mini B USB cable to the ML605 board and connect the other end to the PC with ISE currently running Connecting the Waveform Function Generator 1 Attach the BNC splitter to output of the function generator This enables the function generator s output to be observed in parallel with the output of the FMC 150 DAC 2 Connect one of the outputs from the function generator to an input of the oscilloscope Channel one of the scope is connected to the output of the function generator as shown in Figure 6 3 Connec
14. Process In this part of the tutorial you will generate a simple digital low pass filter using MATLAB The filter will have quantized 16bit coefficients such that it can be readily implemented on the FPGA The MATLAB script used to generate this filter is appendix A of this document The following enumerated steps are provided the reader with a better understanding of the creation 1 First you must decide upon the specifications of your filter For this particular filter we will specify order sampling frequency pass band and stop band frequencies e A high filter order is recommended here will use order 80 This ensures that the filter cutoff is relatively sharp Pass band is the frequency at which the signal begins to roll off here we chose 5MHz e Stop band is the frequency at which the signal will be totally attenuated here we chose 9MHz e Sampling frequency is the frequency of sampling on the ADC The code provided with this tutorial sets the sampling frequency at 245 11MHz 2 Savethe filter specifications as variables in MATLAB fp 5e6 freq at beging of pass band 5MHz fst 9e6 freq at end of stop band 9MHz n 80 filter order 80 fs 245e6 sampling frequency 245MHz 3 Save the filter specifications ina MATLAB data structure f fdesign lowpass N Fp Fst 80 fp fst fs f Response Lowpass Specification N Fp Fst Description Filter Order Passband Frequency Stopband Frequency Normalize
15. Running the ML605 Reference Design In ISE13 1 The purpose of this section is to provide notes regarding the process of running of the ML605 reference design tutorials provided by AVNET You can obtain the ML605 reference design tutorial of your choice from http www xilinx com products boards and kits EK V6 ML605 G htm Notes e The reference designs do not work in any version of ISE newer than 13 1 Onlythe tutorial instructions themselves are different The project code included with this tutorial is a minimization of the actual code from AVNET e Even if using ISE 13 1 some IP cores cannot be opened because they are not fully supported e You can obtain code versions of the tutorial for ISE back to 12 2 from the link above The IP cores in these versions can be opened modified Thetutorial is unusable until the ADC CH A and B iDelay s are set as demonstrated in the main tutorial These should be set as soon as the ML605 board has been programed using ChipScope The recommended value is approximately 25 While running the tutorial o The DAC outputs a constant 12MHz sinusoid This acts as a function generator to drive the ADC which is then viewed in ChipScope o Dipswitch 3 can be switched to bypass the digital up converter and digital down converter such that the ADC input is passed directly out of the DAC output e The sampling frequency used by the tutorial is 66 44MHz 29 Designing a Digital LPF in MATLAB
16. Scan Rate 250 ms lw Project ml605 fmc150 JTAG Chain DEV 0 MyDevice0 System ACE CF DEV 1 MyDevice1 XC6VLX240T System Monitor Console UNIT 0 MyVIOO VIO VIO Console UNIT 11ILA DDC Out ILA Trigger Setup Waveform Listing Signals DEV 1 UNIT 0 Async Input Port Sync Input Port ADC Ch A iDelay at output of iodel ADC Ch B iDelay at output of iodela ADC CLK iDelay at output of iodela Register Data FPGA RD from FM CH 47 SPI bus BUSY Async Output Port Sync Output Port Register Address AD h AiDelav a w Reading file C imc150_ISE_14_4 mI605_fmc150_bit U D LE M M M _ p S8 vio Console DEV 1 MyDevice1 XC6VLX240T UNIT 0 MyVIOO VIO 2222222 P Bus Signal 9 ADC Ch A iDelay at output of iodelayel 9 ADC Ch B iDelay at output of iodelayel 9 ADC CLK iDelay at output of iodelayel 9 Register Data FPGA RD from FMC150 SPI bus BUSY 9 ADC Ch A iDelay 9 ADC Ch B iDelay 9 ADC CLK iDelay 9 Register Address 9 Register Data FPGA WR to FMC150 00 0000 00000000 Figure 12 VIO Console within ChipScope Pro window 10 Check the dipswitches and ensure the four green LED s numbed 5 8 are illuminated As shown in Figure 13 The green LEDs indicate the clocks on the FMC 150 and FPGA are phase locked this is critical The LEDs are indicative of the proper func
17. d licensed 1 Unzip the software provided with this tutorial fmc150_ISE_14_4 zip to a suitable location Experience has shown that locations with spaces in the path may cause issues 2 Launch ISE Design Suite 14 4 3 From the File Menu select Open Project and locate the ISE project file fmc150_ISE_14_4 as shown in Figure X B File Edit View Project Source Window Layout Help New Project 8X ooc 2229 iA B Open Project eBn8x HA Simulation p ML605 fmc150 syn Process Tools clk to fpga p in clk to fpga n in ext trigger p in ext trigger n In std logic a std logic Open Example Project Browser Copy Project std logic Close Project ose Fro Serial Peripheral Interface SPI spi sclk out std logic spi sdata out std logic ADC specific signals adc n en out adc sdo in adc reset out std logic std logic std logic Ctrl S Save As Ep Save All CDCE specific signals cdce n en out cdce sdo E 3H std logic std logic Print Preview Print Ctrl P Recent Files gt Q cdce n reset cdce n pd out out std_logic std_logic a 2 x8 lt 2 lw ref en out pll status in std logic std logic Recent Projects b TA FS RI c 5 70 Exit CE SW 8S ven VT Fes US Wheres JE Ac suis calbvatonvhd 1 E nies mcisoota
18. d select New Source 4 Click IP CORE Generator and Architecture Wizard type the name lowpass under the filename field and select next 20 a New Source Wizard Select Source Type Select source type file name and its location C ISE COMPE475 Final Project COMPE475_PL_HU ipcore_dir Figure 16 New source gt IP Z1 5 When prompted select yes to overwrite the existing core named lowpass 6 Expand the view to Digital Signal Processing then Filters and highlight FIR Compiler version 5 0 as shown in Figure 19 and click next and then finish a du umm vetu us use HEELS i New Source Wizard Select IP Create Coregen or Architecture Wizard IP Core Version AXM AXM Stream AXM Lite Status 79 Automotive amp Industrial AXI Infrastructure BaselP H b Basic Elements H E Communication amp Networking Debug amp Verification Digital Signal Processing PF Building Blocks C n Filters CIC Compiler i xilinx com CIC Compiler i xilinx com i DUC DDC Compiler i xilinx com i FIR Compiler FIR Compiler i xilinx com FIR Compiler i xilinx com Trig Functions Waveform Synthesis Embedded Processing FPGA Features and Design Math Functions Memories amp Storage Elements Standard Bus Interfaces Video amp Image Processing E t f Transforms H ed E UU esc Search IP Catalog 7 All IP versions Only IP compatible with ch
19. dFrequency false Fs 245000000 FilterOrder 80 Fpass 5000000 Fstop 9000000 4 Generate the low pass filter h design f firls Wpass 1 WStop 100 FilterStructure dffir 30 5 Change the data format for the filter that was just created to fixed set filter to fixed type set h Arithmetic fixed 6 Review the specifications of the filter that was just created hz FilterStructure Direct Form FIR Arithmetic fixed Numerator 1x81 double PersistentMemory false CoeffWordLength 16 CoeffAutoScale true Signed true InputWordLength 16 InputFracLength 15 FilterInternals FullPrecision 31 7 Use the filter visualization tool to view the frequency response of the filter See Figures 15 and Figure 16 hfvt fvtool h Magnitude Response dB R 10 amp 30 2 LU B PO w 40 60 80 100 120 E Frequency MHz Figure 24 Magnitude Response Phase Response E 0 1 4 E 8 E E m 3 B 9 r x g 10 8A 6 91 ERXCERRR UENIRE TIER 61 598 9 03 IN D4 da 862444994 N 054 FERE T VE 6 60 80 bist bale 0864 1299 73 T6300 VE EP AAT AE OVE 0000608 ade fe s je e 20 40 50m 80 100 120 A Frequency MHz Figure 25 Phase Response 8 Export the filter coefficients as 16bit hex such that they can be readily use in a Xilinx COE file to initialize block memory in an FIR core fcfwrite h simple
20. e2pulse vhd pulse2pulse instO pulse2pulse syn pulse2pulse vhd ry C IOB Properties Module Level Utilization O Timing Constraints CO Pinout Report O Clock Report Q3 Static Timing B Errors and Warnings Parser Messages Synthesis Messages E Translation Messages H B fin 80 IS n iB S O O pulse2pulse_instl pulse2pulse syn pulse2pulse vhd E Map Messages amc7823 init mem inst amc7823 init mem amc7823 init mem xco E Place and Route Messages Dass inst sample pass sample pass v Timing Messages d lowpass lowpass xco Bitgen Messages icon_inst icon icon xco E New Source All Implementation Messages ila dac inst ila dac ila_dac xc S Add Source amp e Nw Reports ml605 fmc150 ucf Synthesis Report G Add Copy of Source O Translation Report O Map Report C Place and Route Report O Post PAR Static Timing Report C Power Report Design Properties Enable Message Filtering SmartGuide Optional Design Summary Contents 7 Show Clock Report Source Libraries B gt Implement Top Module 7 Show Failing Constraints P D work 3 7 Show Warnings Expand All Collapse All M Find Design Properties Source Properties CORE Generator Manual Compile Order Manage Cores i Set as Top Module Figure 15 Removing the original LPF 3 Right click anywhere in the design hierarchy window an
21. ependencies to a different version of ISE MATLAB Optional for design of LPF as mentioned in the Appendix Also MATLAB requires the DSP toolbox Note Xilinx ISE must be a fully licensed product The free web pack will not work Hardware Requirements e AVNET Xilinx ML605 Development Kit e 4 DSP FMC 150 ADC DAC e Waveform Signal Generator e Oscilloscope 2 3 channel e MMCX to BNC Coax Cable Qty 3 e BNC to BNC Coax Cable e BNC Splitter Limitations and Specifications A key limitation of the FMX 150 is the ADC DAC is AC coupled effectively creating a high pass filter and imposes bandwidth limitations on the hardware In addition the DAC has an 82MHz 5 order Chebyshev low pass filter on its output Listed below summarizes the useful reliable operational bandwidths as well as some key limitations outlined in the FMC 150 user manual ADC e Bandwidth 400KHz 250MHz e Input voltage range 2Vp p note the gain is adjustable so achieve a 1Vp p range DAC e Bandwidth 3MHz 82MHz e Output voltage range 1Vp p 4 DSP the manufacturer of the FMC 150 offers a service to convert the FMC 150 ADC DAC to DC coupling In addition they can alter the low pass filter on the DAC The unit would have to be sent in for the modifications at a cost Setup The following instructions will guide the reader through the setup of the aforementioned required hardware and software for this tutorial Hardware Connecting the M
22. n character ends every command and can also be used to denote comments Any characters following the semicolon up until the next line return is ignored The file should be saved in ASCI format with file extension coe radix 16 Denotes that the filter data is hex other options are 2 or 10 for binary or decimal respectively The following is the coefficient vector one coefficient should appear on each line the lines are terminated with a comma until the last line that is terminated with a semicolon The file can have any number of coefficients between 1 and over 200 depending on which IP core version and options are selected The number of coefficients dictates the order of the filter COEFDATA fff1 ffe5 fff1 2 Right click on the IP Core called lowpass and select remove and then ok In the next part of this tutorial we will recreate this IP core 19 X File Edit View Project Source Process Tools Window Layout Help DaaBlL XSGxloe Si ABRrAlATBanslisry Design enaex P i dj View T Implementation ffl Simulation l Hierarchy z qq dac3283_init_mem_inst dac3283_init_mem dac3283_init_mem xco S h amc7823 ctrl inst amc7823_ctrl amc7823 ctrl syn amc7823 ctrl vhd ge 1 fmc150 stellar cmd inst fmc150 stellar cmd arch fmc150 stellar crr ha p2p0 pulse2pulse syn pulse2pulse vhd p2p1 pulse2pulse syn pulse2pulse vhd p2p2 pulse2pulse syn pulse2pulse vhd p2p3 pulse2pulse syn puls
23. ng a bit file This step takes approximately three minutes to complete X Ele Edit View Project Source Process Jools Window in Design Overview E Summary 8 IOB Properties Module Level Utilization 8 Timing Constraints 8 Pinout Report E Clock Report on Static Timing GI Errors and Warnings 8 Parser Messages E Synthesis Messages 8 Translation Messages E Map Messages Design Summary Reports B Place and Route Peons E Design Utilities _ E g User Constraints Timing Constraints E RA Synthesize XST E Show Columns E fmc150 ISE 14 4 B 3 xc vix240t 1ff1156 B D 4 ML605 fmc150 ML605 fmc150 syn q vio_inst VIO VIO xco b daf Q o o a Br CIA Implement Design Po Met Generate Programming File b Constraint Configure Target Device Analyze Design Using ChipScope E Worst Case Slack Best Case Achievable Errors fj Find in Files Results E Console fV Warnings A Figure 8 Select the top module from the Design pane and double click Generate Programming File to generate a bit file and synthesize the design 13 Running the Design In this part of the tutorial you will program the FPGA with the bit file created in the Preparing the Software section You will then configure ADC channel s for optimal performance Finally you will pass a sine wave into the ADC from the function generator where it will be output by the DAC and viewed on the
24. osen part Figure 17 Selecting a IP core 22 7 Click the vector drop down and change this to COE file then click the browse button and select the COE file created in step 1 The COE file will be imported and the coefficients file field will show a path If this area is highlighted in red then there may be an issue with the format of this file 8 Fill in the input sampling frequency and clock frequency in this case they are 245 76 and 491 52 respectively The first page of the fir compiler menu should look as shown below MO EET ET AUC i e ARP een BEES spe pew 72 Documents View Freq Response Bx TT MEM 2 togi FE log C m FIR Compiler xilinx com ip fir_compiler 5 0 n i Frequency Response Magnitude Component Name lowpass Filter Coefficients Select Source COE File al Coefficient Vector 6 0 4 3 5 6 6 13 7 44 64 44 7 13 6 6 5 3 4 0 6 L Coefficients File C Users Administrator Desktop filter coe Browse Show a i T Number of Coefficient Sets 1 Range 1 256 Rej g Number of Coefficients per set 81 EI S Filter Specification E Filter Type Single Rate Y Rate Change Type Integer Interpolation Rate Value 1 Range 1 1 Decimation Rate Value 1 Range 1 1 Ll Zero Pack Factor 1 Range 1 1 o o2 o4 os os i 12 Number of Channels 1 Range 1 64 Normalized Frequency x PI rad sample Hardware Oversampling Specification Set
25. t the other output of the function generator to the ADC on the FMC 150 board using the MMCX to BNC Coax Cable on port A Or port B but note which port the function generator is connected to because it will referenced later in this tutorial for specific configuration of the port 4 Turn on the function generator and oscilloscope and set the function generator to output a 1Vy sine wave at 5MHz 5 Setthe oscilloscope to display the waveform to verify proper connection Using the Auto Set feature on the oscilloscope should provide you with a decent viewable window of the signal from the function generator See Figure 4 6 Connect DAC channels C and D to the oscilloscope on channels 2 and 3 of the oscilloscope respectively 7 Ensure the waveform is as expected on the oscilloscope and turn the power to the board on As shown in Figure 5 Figure 5 1 Connection to the oscilloscope with attached BNC splitter on the output of the function generator 2 Connection of the function generator to the input of the ADC on port A of the FMC 150 board connection of the MMCX to the FMC 150 board not shown here please see Figure Z Refer to the documentation provided with the oscilloscope and function generator as needed 10 Block Diagram Signal Generator Oscilloscope ML605 FMC 150 JTAG Diagram 1 Block diagram of how to setup should look 11 Software Before beginning this section ensure that ISE 14 4 is installed an
26. this document Project Specific Customizations e Project based on AVNET RTL Reference Design Tutorial Available through their website for ISE 13 1 e Sampling rate changed to the maximum supported by the internal clock of the FMC 150 at 245 11MHz e The Digital Up Converter DUC Digital Down Converter DDC and Direct Digital Synthesizer DDS IP Cores and supporting code were removed as they were not needed for the purposes of this tutorial however if you wish to follow the aforementioned tutorial of which this project is based on the DUC DDC and DDS are an integral part of their AVNET tutorial and must be implemented in the project provided with this tutorial e An order 80 digital low pass filter is implemented in addition to this tutorial as a reference to verify the functional behavior this tutorial See Appendix The project file originating in ISE 13 1 was moved to ISE 14 4p by the means of instantiating the minimum required IP cores for the demonstration purposes of this tutorial which suggests not all the IP cores in this project are a necessity for proper functional behavior i e the aforementioned LPF Requirements This section reviews the minimum hardware and software requirements needed to successfully complete the tutorial Software Requirements SE 14 4p Latest version available when this documents was created See Code Customizations section for pseudo instructions on moving the ISE project and d
27. tional behavior of the connection between the ML605 and FMC 150 Figure 13 LEDs 5 8 must be illuminated and indicate the clocks on the FMC 150 and ML605 are phase locked 17 11 Activate channels one and two on the oscilloscope if not done so already and verify that a sine wave at the previously set frequency of 5MHz is displayed on both channels As shown in Figure 14 SAY E REC Save Image Ink Saver Off I Destination USB Save File Utilities zi E P M Figure 14 The yellow signal shown in this figure is the output of the function generator and the blue signal is the signal from the DAC of the FMC 150 board Note Using the BNC splitter with transmission lines at differing lengths is far from ideal The sine waves displayed will not be identical but will be similar As shown in Figure 14 The output from the DAC will be out of phase with respect to the function generator s output and have different amplitudes which should be within about 3096 of the function generator s measured reference signal but the frequency and form should be very similar This completes this portion of the tutorial 18 Implementation a Digital FIR Filter using Xilinx ISE Process 1 First create the COE file this file initializes the block memory with the filter coefficients To change the filter coefficients this file will need to be reimported each time The format of the file is as follows The semicolo
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