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8XC196MC, 8XC196MD, 8XC196MH Microcontroller User`s Manual

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1. Address High Odd Byte Low Even Byte Address High Odd Byte Low Even Byte 1FDEH Reserved Reserved 1 7 2 TIMER2 L 1FDCH Reserved Reserved 1F7CH Reserved T2CONTROL 1FDAH Reserved Reserved HF7AH TIMER TIMER1 L 1FD8H Reserved Reserved 1F78H Reserved T1CONTROL 1FD6H P7 PIN P2 PIN 1F76H Reserved Reserved 1FD4H P7 REG P2 REG 1F74H Reserved Reserved 1FD2H P7 DIR P2 DIR 1F72H T1 RELOAD H T1RELOAD L 1FDOH P7 MODE P2 MODE 1F70H Reserved Reserved Waveform Generator SFRs 1F6EH COMP5 TIME 5 TIME L Address High Odd Byte Low Even Byte 1F6CH Reserved COMP5 CON 1FCEH Reserved WG PROTECT 1F6AH COMP4 TIME 4 TIME L 1FCCH WG CONTROL H WG CONTROL L 1F68H Reserved COMP4 CON 1FCAH WG COUNTER H COUNTER L 1F66H COMP3 TIME H COMP3 TIME L 1FC8H WG RELOAD WG RELOAD L 1F64H Reserved CON 1FC6H WG_COMP3 H WG COMP3 L 1F62H COMP2 TIME H COMP2 TIME L 1FC4H COMP2 WG 2 L 1F60H Reserved COMP2 CON 1FC2H WG_COMP1 H WG COMP L 1F5EH COMP1 TIME H COMP1 TIME L 1FCOH WG OUTPUT H WG OUTPUT L 1F5CH Reserved COMP1 CON Periph Int Freq Gen and PWM SFRs 1F5AH COMPO TIME H COMPO TIME L Address High Odd Byte Low Even Byte 1F58H Rese
2. Hex Code Instruction Mnemonic 97 XORB Indexed 98 CMPB Direct 99 CMPB Immediate 9A CMPB Indirect 9B CMPB Indexed 9C DIVUB Direct 9D DIVUB Immediate 9E DIVUB Indirect 9F DIVUB Indexed LD Direct Al LD Immediate A2 LD Indirect LD Indexed A4 ADDC Direct 5 ADDC Immediate A6 ADDC Indirect A7 ADDC Indexed 8 SUBC Direct AQ SUBC Immediate AA SUBC Indirect AB SUBC Indexed AC LDBZE Direct AD LDBZE Immediate AE LDBZE Indirect AF LDBZE Indexed BO LDB Direct B1 LDB Immediate B2 LDB Indirect B3 LDB Indexed B4 ADDCB Direct B5 ADDCB Immediate B6 ADDCB Indirect B7 ADDCB Indexed B8 SUBCB Direct B9 SUBCB Immediate BA SUBCB Indirect BB SUBCB Indexed BC LDBSE Direct BD LDBSE Immediate BE LDBSE Indirect BF LDBSE Indexed A 44 lel INSTRUCTION SET REFERENCE Table A 7 Instruction Opcodes Continued Hex Code Instruction Mnemonic CO ST Direct C1 BMOV C2 ST Indirect C3 ST Indexed C4 STB Direct C5 CMPL C6 STB Indirect C7 STB Indexed C8 PUSH Direct C9 PUSH Immediate CA PUSH Indirect CB PUSH Indexed CD BMOVI CE POP Indirect CF POP Indexed DO JNST D1 JNH D2 JGT D3 JNC D4 JNVT D5 JNV D6 JGE D7 JNE D8 JST D9 JH DA JLE DB JC DC JVT DD JV DE JLT DF JE EO DJNZ E1 DJNZW E2 TIJMP E
3. 15 8 8XC196MC EXTINT PI COMP3 EPA3 7 0 COMP2 EPA2 1 EPA1 COMPO EPAO AD OVRTM 15 8 8XC196MD EXTINT PI EPA5 COMP4 EPA4 COMP3 EPA3 7 0 2 EPA2 COMP1 EPA1 COMPO EPAO AD OVRTM 15 8 8XC196MH EXTINT WG SPI Ri RIO TH TIO 7 0 2 1 EPA1 COMPO EPAO AD OVRTM Bit 5 Number Function 15 Reserved This bit is undefined 14 07 A bit is set by hardware to request an end of PTS interrupt for the corresponding interrupt through its standard interrupt vector The PTS interrupt vector locations are as follows Bit Mnemonic EXTINT MD WG 5 MD SPI COMP4 MD MH EPA4 MD RIO MH COMP3 MC MD TH MH EPA3 MC MD t PTS service is not useful for multiplexed interrupts because the PTS cannot readily determine the source of these interrupts PTS Vector 205CH 205AH 205AH 2058H 2058H 2056H 2056H 2054H 2054H 2052H 2052H 2050H Bit Mnemonic TIO MH 2 MC MD COMP3 MH EPA2 MC MD 2 MH 1 1 EPAO AD OVRTM PTS Vector 2050H 204EH 204EH 204CH 204CH 204AH 2048H 2046H 2044H 2042H 2040H t On the 8XC196MC device bits 10 12 are reserved These bits are undefined 5 26 Figure 5 14 PTS Service PTSSRV Register intel STANDARD AND PTS INTERRUP
4. 5 23 5 13 PTS Control Blocks aks erren ree eet ei ee eves 5 25 5 14 PTS Service PTSSRV 5 26 5 15 PTS Mode Selection Bits PTSCON Bits 7 5 5 27 5 16 PTS Control Block Single Transfer Mode 9 28 5 17 PTS Control Block Block Transfer Mode 5 31 5 18 PTS Control Block A D Scan Mode DTO 5 19 PTS Control Block 1 Serial 5 38 5 20 PTS Control Block 2 Serial 5 41 5 21 Synchronous SIO Transmit Mode 5 43 5 22 Synchronous SIO Transmit Mode End of PTS Interrupt Routine Flowchart 5 46 5 23 Synchronous SIO Receive eem 5 47 5 24 Synchronous SIO Receive Mode End of PTS Interrupt Routine Flowchart 5 50 5 25 Asynchronous SIO Transmit Timing is 2255 51 5 26 Asynchronous SIO Transmit End of PTS Interrupt Routine Flowchart 5 54 5 27 Asynchronous SIO Receive 5 55 5 28 Asynchronous SIO Receive Mode End of PTS Interrupt Routine Flowchart 5 58 6 1 Standard Input only Port Structure sese 9 6 2 Bidirectional Port Structure Ms Wi UR 6 3 Address
5. TBASE INDEX 11100010 INDEX MASK NOTE TIJMP multiplies OFFSET by two to provide for word alignment of the jump table TRAP SOFTWARE TRAP This instruction causes an interrupt call that is vectored through location 2010H The operation of this instruction is not affected by the state of the interrupt enable flag 1 in the PSW Interrupt calls cannot occur immediately following this instruction SP lt SP 2 SP PC PC lt 2010H PSW Flag Settings 11110111 NOTE This instruction is not supported by assemblers The TRAP instruction is intended for use by development tools These tools may not support user application of this instruction A 39 8XC196MC MD MH USER S MANUAL Table A 6 Instruction Set Continued intel Mnemonic Operation Instruction Format XCH EXCHANGE WORD Exchanges the value of DEST SRC the source word operand with that of the XCH wreg waop destination word operand i 00000100 wreg direct DEST lt gt SRC 00001011 waop wreg indexed PSW Flag Settings Z N C V VT ST XCHB EXCHANGE BYTE Exchanges the value of DEST SRC the source byte operand with
6. 7 0 Unused 0 0 0 0 0 0 0 0 7 0 SAMPTIME Sample Time Value 15 8 DATA H Data Register high byte 7 0 DATA L Data Register low byte 7 0 PTSCON1 Synch 0 0 0 0 0 0 TRC 0 7 0 PTSCON1 Asynch 0 RPAR PEN 0 0 0 FE TPAR 7 0 PORTMASK Port Mask Register 15 0 PORTREG H Port Address Pointer high byte 7 0 PORTREG L Port Address Pointer low byte Register Location Function SAMPTIME PTSCB2 6 Sample Time Value This register controls the time between samples during asynchronous receive mode when majority sampling is selected Use the following formula to calulate the value to load into the SAMPTIME register Sample_time TEAU ATAL 9 where Sample_time is an integer 1 31 that is loaded into the SAMPTIME register Tsam is the desired time between samples us is the input frequency XTAL1 in MHz Figure 5 20 PTS Control Block 2 Serial 1 0 Mode 5 41 8XC196MC MD MH USER S MANUAL intel PTS Serial I O Mode Control Block 2 Continued 8XC196MC MD Register Location Function DATA PTSCB2 4 Data Register This 16 bit register holds the data to be transmitted or the data that has been received During transmit mode the least significant bit bit 0 is transmitted first Data shifts to the right with each successive transmission During receive mode the first bit is loaded into the most significant bit bit 15 Data shifts to the right
7. Indirect Indexed Mnemonic Direct Immed Normal Autoinc Short Long Reg Mem Reg Mem Reg Mem Reg Mem ADD 2 ops 4 5 6 8 7 9 6 8 7 9 ADD 3 ops 5 6 7 10 8 11 7 10 8 11 ADDB 2 ops 4 4 6 8 7 9 6 8 7 9 ADDB 3 ops 5 5 7 10 8 11 7 10 8 11 ADDC 4 5 6 8 7 9 6 8 7 9 ADDCB 4 4 6 8 7 9 6 8 7 9 CLR 3 CLRB 3 CMP 4 5 6 8 7 9 6 8 9 CMPB 4 4 6 8 7 9 6 8 9 CMPL 7 DEC 3 DECB 3 EXT 4 EXTB 4 INC 3 INCB 3 SUB 2 ops 4 5 6 8 7 9 6 8 7 9 SUB 3 ops 5 6 7 10 8 11 7 10 8 11 SUBB 2 ops 4 4 6 8 7 9 6 8 7 9 SUBB 3 ops 5 5 7 10 8 11 7 10 8 11 SUBC 4 5 6 8 7 9 6 8 7 9 SUBCB 4 4 6 8 7 9 6 8 7 9 NOTE column entitled Reg lists the instruction execution times for accesses to the register file or peripheral SFRs The column entitled Mem lists the instruction execution times for accesses to all memory mapped registers I O or memory See Table 4 1 on page 4 2 for address information A 52 intel INSTRUCTION SET REFERENCE Table A 9 Instruction Execution Times in State Times Continued Arithmetic Group II Indirect Indexed Mnemonic Direct Immed Normal Autoinc Short Long Reg Mem Reg Mem Reg Mem Reg Mem DIV 26 27 28 31 29 32 29 32 30 33 DIVB 18 18 20 23 21 24 21 24 22 25 DIVU 24 25 26 29 27 30 27 30 28 31 DIVUB
8. 16 16 Slave Programming Mode Memory Map emm 16 17 Timing Mnemlonics e ne c hee ety 16 24 8XC196MC MD Auto Programming Memory 16 27 8XC196MH Auto Programming Memory 16 27 PCCB and UPROM Programming Values sss 16 32 Opcode Map Left Opcode Map Right emm eene enne Processor Status Word PSW Flags Effect of PSW Flags or Specified Conditions on Conditional Jump Instructions 5 PSW Flag Setting A 5 Operand Variables eese ennemi ACG InstrUction Set Et A 7 Iristr ctlon OpcodeS ionian ema ee A 41 Instruction Lengths and Hexadecimal A 47 Instruction Execution Times in State 00000 0000 52 Signal Name Changes nia eec tr eret EE ED e DUE ud a ev dad B 1 8XC196MC Signals Arranged by Functional 2 8XC196MD Signals Arranged by Functional Categories 6 8XC196MH Signals Arranged by Functional BY Description of Columns of Table 6 B 13 Signal Descripti
9. 15 8 OPO 7 M6 M5 4 M3 2 M1 0 7 0 D7 D6 D5 D4 D3 D2 D1 DO Bit Bit Function 7 0 D7 0 Data In general purpose output mode these bits hold the values to be driven out on the pins Write the desired values to these bits bits 7 0 correspond to pins P6 7 0 Figure 6 5 Port 6 Output Configuration WG_OUTPUT Register Continued 6 19 intel 7 Serial I O SIO Port intel CHAPTER 7 SERIAL I O SIO PORT A serial input output SIO port provides a means for the system to communicate with external devices The 8XC196MH device has a two channel serial I O port that shares pins with ports 1 and 2 The 8KC196MC and 8XC196MD devices do not have serial I O ports This chapter de scribes the SIO port and explains how to configure it Chapter 6 I O Ports explains how to con figure the port pins for their special functions Refer to Appendix B for details about the signals discussed in this chapter 7 1 SERIAL I O SIO PORT FUNCTIONAL OVERVIEW The serial I O port Figure 7 1 is an asynchronous synchronous port that includes a universal asynchronous receiver and transmitter UART The UART has two synchronous modes modes 0 and 4 and three asynchronous modes modes 1 2 and 3 for both transmission and reception Internal Data Bus a SBUFx_RX Receive Shift Register A RXDx SBUFx_TX Transmit Shift Register LJ TXDx
10. 9 12 9 4 1 Configuring the Outputs entente 9 12 9 4 2 Controlling the Protection Circuitry and EXTINT Interrupt Generation 9 15 9 4 3 Specifying the Carrier Period and Duty 9 16 9 4 4 Specifying the Operating Mode and Dead Time and Starting the Counter 9 17 9 5 DETERMINING THE WAVEFORM GENERATOR S 9 19 9 6 ENABLING THE WAVEFORM GENERATOR INTERRUPTS eee 9 19 9 7 DESIGN trennen inns 9 20 9 7 1 Dead Time and Duty Cycle SM A40 9 7 2 EXTINT Interrupts and Protection Circuitry descr ERR 9 21 9 8 PROGRAMMING 9 21 CHAPTER 10 PULSE WIDTH MODULATOR 10 1 PWM FUNCTIONAL essent nennen enne nnne nnns 10 1 10 2 PWM SIGNALS AND sse 10 2 10 3 PWM OPERATION reiecit rito od er e nce LEE 10 3 10 4 PROGRAMMING THE FREQUENCY AND 10 4 10 5 PROGRAMMING THE DUTY seem 10 6 10 5 1 Sample Calc lations Re estesa cocina ester vii 8XC196MC MD MH USER S MANUAL intel 10 5
11. 15 81 15 6 1 Explanation of AC Symbols 15 33 15 6 2 Timing Definitions seen eee ener nens 15 33 CHAPTER 16 PROGRAMMING THE NONVOLATILE MEMORY 16 1 PROGRAMMING 16 1 16 2 MEMORY 16 2 16 3 SECURITY 1 42 1 4 4 1 bnnc 16 9 16 3 1 Controlling Access to Internal 16 3 16 3 1 1 Controlling Access to the OTPROM During Normal Operation 16 4 16 3 1 2 Controlling Access to the OTPROM During Programming Modes 16 4 16 3 2 Controlling Fetches from External Memory seme 16 6 16 4 PROGRAMMING PULSE WIDTH eene 16 8 165 MODIFIED QUICK PULSE sese eem emere nennen 16 9 166 PROGRAMMING MODE 5 16 11 16 7 ENTERING PROGRAMMING MODES eee emere 16 13 16 7 1 Selecting the Programming Mode seem 16 13 16 7 2 Power up and Power down Sequences sese 16 14 16 7 2 1 Power up Sequence 10 14 16 7 2 2 Power down Sequence essem emend 14 168 SLAVE PROGRAMMING eee eere errem 16 15 16 8 1 Reading the Signature Word and Programming Voltages 16 15
12. Bit Bit Number Mnemonic Function 7 5 SAM2 0 A D Sample Time These bits specify the sample time Use the following formula to compute the sample time RE xF 2 SAM SAM 8 where SAM 1107 Tsam the sample time in usec from the data sheet 1 the input frequency XTAL1 in MHz 4 0 CONV4 0 A D Convert Time These bits specify the conversion time for each bit Use the following formula to compute the conversion time T xF 3 CONV XTAL1 erro where CONV 21031 the conversion time in usec from the data sheet the input frequency on XTAL1 in MHz the number of bits to be converted 8 or 10 XTAL1 intel REGISTERS CCRO CCRO no direct accesst The chip configuration 0 CCRO register controls powerdown mode bus control signals and internal memory protection Three of its bits combine with two bits of CCR1 to control wait states and bus width 7 0 LOC1 LOCO IRC1 IRCO ALE WR BWO PD Bit Bit Number Mnemonic Function 7 6 LOC1 0 Lock Bits These two bits control read and write access to the OTPROM during normal operation Refer to Controlling Access to the OTPROM During Normal Operation on page 16 4 for details LOC1 LOCO 0 0 read and write protect 0 1 read protect only 1 0 write protect only 1 1 no protection 5 4 IRC1 0 Internal Ready Control These two bits a
13. Call Indexed Pacman Direct Immediate Indirect Note 1 Length Opcode Length Opcode Length Opcode Length Opcode LCALL 3 EF RET 1 FO SCALL Note 2 2 28 2F TRAP 1 F7 Conditional Jump Direct Immediate Indirect Note d Mnemonic Length Opcode Length Opcode Length Opcode ae Opcode DJNZ 3 EO DJNZW 3 E1 JBC 3 30 37 JBS 3 38 3 JC 2 DB JE 2 DF JGE 2 D6 JGT 2 D2 JH 2 09 2 DA JLT 2 DE JNC 2 03 2 D7 JNH 2 D1 JNST 2 00 JNV 2 D5 JNVT 2 D4 JST 2 D8 JV 2 DD JVT 2 DC NOTES 1 For indexed instructions the first column lists instruction lengths as S L where S is the short indexed instruction length and L is the long indexed instruction length 2 For the SCALL and SJMP instructions the three least significant bits of the opcode are concatenated with the eight bits to form an 11 bit two s complement offset A 50 intel INSTRUCTION SET REFERENCE Table A 8 Instruction Lengths and Hexadecimal Opcodes Continued Shift Direct Immediate Indirect Indexe
14. 7 0 8XC196MH Data Received Bit 3 Number Function 7 0 Data Received This register contains the last byte of data received from the serial port C 47 8XC196MC MD MH USER S MANUAL SBUFx_TX intel SBUFx TX x 0 1 8XC196MH Address 1F82H 1F8AH Reset State 00H The serial port transmit buffer x SBUFx TX register contains data that is ready for transmission In modes 1 2 and 3 writing to SBUFx TX starts a transmission In mode 0 writing to SBUFx TX starts a transmission only if the receiver is disabled SPx 0 7 0 8XC196MH Data to Transmit Bit Number Function 7 0 Data to Transmit This register contains a byte of data to be transmitted by the serial port C 48 intel REGISTERS SP SP Address 18H Reset State XXXXH The system s stack pointer SP can point anywhere in internal or external memory it must be word aligned and must always be initialized before use The stack pointer is decremented before a PUSH and incremented after a POP so the stack pointer should be initialized to two bytes in 64 Kbyte mode or four bytes in 1 Mbyte mode above the highest stack location If stack operations are not being performed locations 18H and 19H may be used as standard registers 15 0 Stack Pointer Bit Number Function 15 0 Stack Pointer This register makes up the system s stack pointer
15. 15 33 8XC196MC MD MH USER S MANUAL intel Table 15 9 Microcontroller Meets These Specifications Symbol Definition Tavel Address Setup to ALE ADV Low Length of time address is valid before ALE ADV falls Useful when using an external latch to demultiplex the address from the address data bus Teja CLKOUT High CLKOUT Low CLKOUT pulse width Useful when using CLKOUT to clock external devices Tore CLKOUT Cycle Time The period of the CLKOUT signal equal to 2T y 4 CLKOUT Low to ALE ADV High Tinia ALE Cycle Time Minimum time between two ALE rising edges ALE High to ALE Low ALE pulse width Useful when using an external latch to demultiplex the address from the address data bus Tiny AD15 0 Hold after ALE ADV Low Length of time address is valid after ALE ADV falls Useful when using an external latch to demultiplex the address from the address data bus ALE ADV Low to CLKOUT High Tun ALE ADV Low to RD Low Length of time after ALE ADV falls before the microcontroller asserts RD Maximum time a memory system has to decode the address before the microcontroller asserts RD ALE ADV Low to WR Low Length of time after ALE ADV falls before the microcontroller asserts WR Maximum time a memory system has to decode the address before the microcontroller asserts WR Output Data Valid to WR High Leng
16. Figure 5 19 PTS Control Block 1 Serial I O Mode Continued 5 39 8XC196MC MD MH USER S MANUAL intel PTS Serial I O Mode Control Block 1 Continued 8XC196MC MD Register Location Function PTSCOUNT PTSCB1 0 Consecutive PTS Cycles Defines the number of bits to be transmitted or received including parity and stop bits but not the start bit For asynchronous modes program a number that is between 1 16 For synchronous modes program a number that is twice the number of bits to be transmitted or received 2 32 PTSCOUNT is decremented at the end of each PTS cycle When it reaches zero hardware clears the corresponding PTSSEL bit and sets the PTSSRV bit which requests the end of PTS interrupt 5 40 Figure 5 19 PTS Control Block 1 Serial I O Mode Continued intel STANDARD AND PTS INTERRUPTS PTS Serial I O Mode Control Block 2 8XC196MC MD The PTS control block 2 contains pointers to both the port register PORTREG and the data register DATA It also contains a 16 bit value that is used to calculate the sample time for asynchronous receptions when majority sampling is selected a control register PTSCON1 and a 16 bit value that is used to select the port signal that functions as the TXD or signal PORTMASK
17. eee 15 27 Comparison of ALE and ADV Bus eem 15 27 e bit System with Flash 15 28 16 bit System with nennen nennen nemen nens 15 29 Timings of Address Valid with Write Strobe Mode 15 30 intel CONTENTS Figure 15 21 15 22 16 1 16 2 16 3 16 4 16 5 16 6 16 7 16 8 16 9 16 10 16 11 16 12 16 13 16 14 16 15 B 1 B 3 B 4 B 6 B 7 FIGURES Page 16 bit System with 5 31 System BUS Timing teer p rendent er oe Pri ie diced 15 32 Unerasable PROM USFR Register emen 16 7 Programming Pulse Width PPW 16 8 Modified Quick pulse 16 10 Pin Functions in Programming 16 11 Slave Programming Circuit enne eene 16 16 Chip Configuration Registers 5 sse eene 16 18 Address Command Decoding Routine eee 16 20 Program Wordi ROUN Rr Pret Gea ene dete taped 16 21 Program Word Waveforms siiiu de 16 22 Dump Word Routine 3 sus eoa sed a pod ed dde et ins 16 23 Dump Word Waveforms ilienea a r cine ener 16724 Auto Programming Circuit 16 26 Auto Programming Routine i J 10529 PCC
18. ADDB AL BL CL MULB AX BL INCB CL AX lt CX AL lt BL CL AX lt AX X BL CL CL 1 3 2 2 Immediate Addressing Immediate addressing mode accepts one immediate value as an operand in the instruction You specify an immediate value by preceding it with a number symbol An instruction can contain only one immediate value the remaining operands must be direct references The following in structions use immediate addressing ADD AX 340 PUSH 1234H AX lt AX 340 SP lt SP 2 MEM_WORD SP lt 1234H i DIVB 10 AL lt AX 10 lt MOD 10 3 2 3 Indirect Addressing The indirect addressing mode accesses an operand by obtaining its address from a WORD regis ter in the lower register file You specify the register containing the indirect address by enclosing it in square brackets The indirect address can refer to any location within the address space including the register file The register that contains the indirect address must be word aligned and the indirect address must conform to the rules for the operand type An instruction can contain only one indirect reference any remaining operands must be direct references The following in structions use indirect addressing LD AX BX lt MEM WORD BX 3 6 intel PROGRAMMING CONSIDERATIONS ADDB AL BL CX AL BL BYTE CX POP AX MEM WORD AX lt MEM WORD SP
19. dre e 0 im X Biz X LSB MSB A3120 01 Figure 5 21 Synchronous SIO Transmit Mode Timing 5 43 8XC196MC MD MH USER S MANUAL intel If the SCK signal is generated by the EPA channel the first PTS cycle must be started manually Initialize the TXD port pin and the SCK signal to the system required logic level before starting a transmission Add the contents of the timer register to the Baud value Figure 5 19 on page 5 38 and store the result into the EPA time register This sets up the timing for the first interrupt and causes the first bit transmission to occur at the proper baud rate The following example uses EPAO to control the baud rate and output the SCK signal and P2 2 to output the data TXD It sets up a synchronous serial I O PTS routine that transmits 16 bytes with eight data bits at 9600 baud This example uses several user defined registers T COUNT defines the number of bytes to transfer and TXDDONE is a flag that is set when all bytes are transferred 1 Disable the interrupts and the PTS Use the DI instruction to disable all standard interrupts and the DPTS instruction to disable the PTS 2 Set up the stack pointer 3 Reset all interrupt mask registers Clear INT MASK INT MASKland PI MASK 4 Initialize P2 0 to function as the EPAO output SCK and P2 2 to function as TXD Clear P2 DIR selects output Set P2 MODE O
20. register Figure 9 9 on page 9 15 select the type of ex ternal event that will generate an interrupt request a falling or rising edge or a low or high level 5 6 intel STANDARD AND PTS INTERRUPTS When the level sensitive event is selected the external interrupt signal must remain asserted for at least 24 24 to be recognized as a valid interrupt When the signal is asserted the level sampler samples the level of the signal three times during a 24 period When a valid level occurs the level sampler generates a a single output pulse The output pulse generates the EXTINT interrupt request The level sensitive mode is useful in noisy environments where a noise spike might cause an unintentional interrupt request When an edge triggered event is selected the input must remain asserted for at least two 2 Fy 7 11 to be recognized as a valid interrupt When a valid transition occurs the transition de tector generates a single output pulse The output pulse generates the EXTINT interrupt request ES IT EXTINT Interrupt Request DP EO Bit Register Falling pesa Transition Detector Level Sampler OD EXTINT FxrAL1 A CPU Read EO A2661 01 Figure 5 2 Waveform Generator Protection Circuitry 5 3 3 Multiplexed Interrupt Sources The PI MD OVRTM Mx and SPI MH interrupts have multiple sources see Table 5 3 on page 5 5
21. 1 0 TXDO P2 0 2 0 P1 1 RXDO P2 1 EPA1 PALE P2 1 SCLK0 BCLK0 PALE 1 2 TXD1 P2 2 EPA2 PROG P2 2 EPA1 PROG P1 3 RXD1 P2 3 EPA3 P2 3 COMP3 P2 4 2 4 COMP0 AINC P2 5 COMP1 PACT P2 5 COMP1 PACT P2 6 COMP2 CPVER P2 6 COMP2 CPVER P2 7 COMP3 P2 7 SCLK1 BCLK1 Port 5 Port 7 8XC196Mx 8XC196MD Pin 5 0 ALE ADV 7 0 4 P5 1 INST P7 1 EPA5 P5 2 WR WRL P7 2 COMP4 P5 3 RD P7 3 COMP5 P5 4 ONCE P7 4 5 5 BHE WRH P7 5 5 6 READY P7 6 P5 7 BUSWIDTH P7 7 FREQOUT C 32 intel REGISTERS Address Table C 9 Reset State 0 5 8 196 MH 0 5 7 8XC196MD Each bit of the port x pin input Px_PIN register reflects the current state of the corresponding pin regardless of the pin configuration 7 0 x 1 MC 4 PIN2 PINO 7 0 1 PINS PIN2 PIN1 PINO 7 0 x 1 7 MD PIN7 PIN6 5 4 PIN2 PINO 7 0 x 0 2 5 PIN7 PIN6 PIN5 PIN4 PINS PIN2 PINO Bit Number Bit Function Mnemonic 7 01 PIN7 0 Port x Pin y Input Value This bit contains the current state of Px y The bits shown as dashes are reserved their values are undefined Table C 9 Px_PIN Addresses
22. While a threshold detection mode is selected for an analog input no other conversion be started If another value is loaded into AD COMMAND the threshold detection mode is disabled and the new command is executed tt Itis the act of writing to the GO bit rather than its value that starts a conversion Even if the GO bit has the desired value you must set it again to start a conversion immediately or clear it again to arm it for an EPA initiated conversion Figure 12 5 A D Command AD COMMAND Register 12 4 5 Enabling the A D Interrupt The A D converter can set the A D interrupt pending bit when it completes a conversion or when the input voltage crosses the threshold value in the selected direction To enable the interrupt set the corresponding mask bit in the interrupt mask register see Table 12 2 on page 12 2 and exe cute the EI instruction to globally enable servicing of interrupts The A D interrupt can cause the PTS to begin a new conversion See Chapter 5 Standard and PTS Interrupts for details about interrupts and a description of using the PTS in A D scan mode 12 8 intel ANALOG TO DIGITAL A D CONVERTER 12 5 DETERMINING A D STATUS AND CONVERSION RESULTS You can read the AD_RESULT register Figure 12 6 to determine the status of the A D convert er The AD_RESULT register is cleared when a new conversion is started therefore to prevent losing data you must read both bytes b
23. 1FACH Reserved AD_COMMAND 1F4EH COMP3_TIME H COMP3_TIME L 1FAAH AD_RESULT H AD_RESULT L 1F4CH Reserved COMP3_CON Reset Control SFR Address High Odd Byte Low Even Byte 11 6 EPA1 TIME EPA1_TIME L 1FA8H Reserved Reserved 1F44H Reserved EPA1_CON 1 42 EPAO TIME H EPAO TIME L 1 Reserved GEN CON 1F40H Reserved EPAO CON Must be addressed as a word 4 8 ntel MEMORY PARTITIONS 4 1 6 Register File The register file Figure 4 1 is divided into an upper register file and a lower register file The upper register file consists of general purpose register RAM The lower register file contains gen eral purpose register RAM along with the stack pointer SP and the CPU special function regis ters SFRs Table 4 1 on page 4 2 lists the register file memory addresses The RALU accesses the lower reg ister file directly without the use of the memory controller It also accesses a windowed location directly see Windowing on page 4 12 The upper register file and the peripheral SFRs can be windowed Registers in the lower register file and registers being windowed can be accessed with register direct addressing NOTE The register file must not contain code An attempt to execute an instruction from a location in the register file causes the memory controller to fetch the instruction from external memory Address 02FFH MH
24. P5 2 WR WRL 1 P5 7 BUSWIDTH amp 2 015 4 7 PBUS 15 F13 014 P4 6 PBUS 14 944 P6 7 PWM1 P2 6 COMP2 CPVER P2 5 COMP1 PACT P2 4 COMPO 7 3 COMP5 P7 2 COMP4 CLKOUT 97 P2 7 COMP3 P2 3 AD11 P4 3 PBUS 11 9 S8XC196MD P2 2 EPA2 PROG AD10 P4 2 PBUS 10 Ej P7 1 AD9 P4 1 PBUS 9 P7 0 4 P4 0 PBUS 8 P2 1 EPA1 PALE 07 P3 7 PBUS 7 P2 0 PVER AD6 P3 6 PBUS 6 amp P7 7 FREQOUT AD5 P3 5 PBUS 5 amp View of component as P0 0 ACHO AD4 P3 4 5 4 mounted on PC board P0 1 ACH1 P3 3 PBUS 3 Ej 17 4 P0 2 ACH2 P0 3 ACH3 P0 4 ACH4 PMODE O P0 5 5 PMODE 1 VREF 2 P3 2 PBUS 2 J AD1 P3 1 PBUS 1 r3 ADO P3 0 PBUS 0 F3 20 1 7 9 21 RESET amp 22 ANGND NMI 23 P0 6 ACH6 PMODE 2 EA O 24 3 P0 7 ACH7 PMODE 3 10 N NNO CO CO CO CO tH Hr 3k C 00 8090 BNOTRATT IT gt gt 2 03 gt 95008025599 99 4 lt Se SS 69 4 e2 a 2522286 lt lt bo Qn aa A3105 01 Figure B 5 8XC196MD 80 lead Shrink EIAJ QFP Package intel SIGNAL DESCRIPTIONS Table B 4 8XC196MH Signals Arranged by Fun
25. in dicating that programming has begun PACT is also active during reset although no program ming is in progress PVER is initially asserted and remains asserted unless an error is detected in which case it is deasserted The routine then reads the contents of the external EPROM beginning at 4000H 2000H for the 8 196 It skips any word that contains FFFFH unprogrammed state When it reads word that contains any value other than FFFFH the routine calls the modified quick pulse algo rithm which writes that value to the OTPROM using the appropriate number of pulses for the device then verifies the result The routine repeats this activity until the entire OTPROM is pro grammed then deasserts PACT and enters an endless loop 16 9 4 Auto Programming Procedure If a glitch or reset occurs while programming the security key and lock bits an unknown security key might accidentally be written rendering the device inaccessible for further programming To minimize this possibility follow this recommended programming procedure NOTE All addresses are given for the circuit shown in Figure 16 12 on page 16 26 If you choose a different circuit you must adjust the addresses accordingly 1 Using a blank EPROM device follow these steps to skip programming of CCBO and program the rest of the OTPROM array including the security key Place the programming pulse width PPW in external EPROM locations 14H 15H f
26. FIGURES Page A D Result AD RESULT Register Write 12 6 A D Time AD TIME nennen nennen nnne 12 7 A D Command AD COMMAND Register emen 12 8 A D Result AD RESULT Register Read 12 9 Idealized A D Sampling 12 10 Suggested A D Input Circuit seem mmmeemmim2 2 Ideal A D Conversion eem em 12 15 Actual and Ideal A D Conversion 12 16 Terminal based A D Conversion 00 0 12 18 Minimum Hardware 13 3 Power and Return 13 4 On chip Oscillator GIECUIE curri ee rette ente doni ended dere 13 5 External Crystal eem d 3 8 External Clock 13 7 External Clock Drive 13 7 Reset Timing 13 8 General Configuration Register GEN 13 9 Internal Reset eene nennen Minimum Reset nennen nnns 13 11 Example of a System Reset Circuit eese 13 11 Cl
27. aeu ge PAR Start timer 1 with a 1 microsecond clock period load the carrier frequency into FREQ GEN and enable the interrupts AAA ARI UK ldb temp 11000010b init EPA timerl stb temp ticontrol 0 21 uS ticks ldb freq load carrier freq 8 7 8XC196MC MD MH USER S MANUAL intel stb ei y Kcd uA pue oie Now send buffer ou OK SES KE SK AR sk Ie Sese eee e This section issue for use with an os ck ck ck ck ck ck ck ock KKK KKK KKK KK 1 1 orb djnzw andb 1 y Sd a Ka SED Ip eO e Initialize the buf 1 Td 1 RS RO AAR AAR Set the compare mo to start sending t send is complete 1 wait jbs ljmp IESE AR AK IK AK COMPARE3 INTERRUPT This routine execu The flag registe ILLI cseg at 0 120 pusha jbs jbs jbs jbs sjmp get_byte andb 1 1 temp freq_gen 0 into freq gen enable interrupts t as serial data bytes 1 millisecond pulse on P2 0 cilloscope monitor ok ck ck ck ck ck ck ck ock ck ock ck ck KKK KKK KKK 7EH temp 0400 p2_reg
28. 15 5 OP1 OPO SYNC PE7 PE6 PH3 2 PH2 2 PH1 2 7 0 P7 P6 PH3 1 PH3 0 PH2 1 PH2 0 PH1 1 PH1 0 Bit Bit Number Mnemonic Function 15 OP1 Output Polarity Selects the output polarity for negative phase outputs WG1 WG2 and WG3 0 active low outputs 1 active high outputs 14 OPO Output Polarity Selects the output polarity for positive phase outputs WG1 WG2 and WG3 0 active low outputs 1 active high outputs 13 SYNC Synchronize Selects whether updating the WG_OUTPUT register is synchronized with another event or occurs immediately after you change it 0 update WG_OUTPUT immediately 1 synchronize WG_OUTPUT update with an event To ensure that the outputs are in the desired states when the waveform generator starts you should initially clear this bit then set it later if you want subsequent WG_OUTPUT updates to be synchronized with an event Table 9 4 on page C 8 lists the events that update WG_OUTPUT in each mode 12 PE7 P6 7 PWM1 Function Selects the port function or the PWM output function of P6 7 PWM1 0 P6 7 1 PWM1 11 PE6 P6 6 PWMO Function Selects the port function or the PWM output function of P6 6 PWMO 0 P6 6 1 PWMO C 63 8XC196MC MD MH USER S MANUAL WG_OUTPUT Waveform Generator intel WG_OUTPUT Waveform Generator Continued Address 1FCOH Reset State 0000H The waveform generator output configuration WG OUTPUT regist
29. 5 35 5 6 5 2 A D Scan Mode Example 1 5 35 5 6 5 3 Scan Mode Example 2 essere enne 5 37 8XC196MC MD MH USER S MANUAL 5 6 6 Serial VO MOES a prr Doi eee Porti ise no 5 97 5 6 6 1 Synchronous SIO Transmit Mode Example 5 43 5 6 6 2 Synchronous SIO Receive Mode Example esee DAT 5 6 6 3 Asynchronous SIO Transmit Mode Example 5 50 5 6 6 4 Asynchronous SIO Receive Mode Example 5 55 CHAPTER 6 1 0 PORTS 6 1 PORTS OVERVIEW FE ECT HE TD anal 6 1 6 2 INPUT ONLY PORTS 1 MC MD ONLY AND 0 0 6 2 6 2 1 Standard Input only Port Operation 6 3 6 2 2 Standard Input only Port Considerations Bit 6 4 6 3 BIDIRECTIONAL PORTS 1 MH ONLY 2 5 7 MD ins 6 4 6 3 1 Bidirectional Port Operation peer nette eb 6 6 6 3 2 Bidirectional Port Pin Configurations seem O79 6 3 3 Bidirectional Port Pin Configuration Example 2 6 11 6 3 4 Bidirectional Port Considerations 6 12 6 4 BIDIRECTIONAL PORTS AND 4 ADDRESS DATA BUS eee 6 14 6 4 1 Bidirectional Ports and 4 Address Data Bus Operation 6 15 6 4 2 Using Ports 3
30. eem eee eene 14 6 14 4 3 1 Driving the Vop ssi 14 6 14 4 8 2 Generating a Hardware Reset 14 6 14 4 3 3 Asserting the External Interrupt Signal 14 7 14 4 3 4 Selecting Ry and GC cect en a cp 14 8 14 5 ONGE MODE eH ne eene deg idee 14 10 14 6 RESERVED TEST 14 11 15 INTERFACING WITH EXTERNAL MEMORY 15 1 EXTERNAL MEMORY INTERFACE SIGNALS AND REGISTERS 15 1 15 2 CHIP CONFIGURATION REGISTERS AND CHIP CONFIGURATION BYTES 15 5 15 3 BUS WIDTH AND MULTIPLEXING seen ene 19710 15 3 1 Timing Requirements for 15 13 15 3 2 16 bit Bus Timings netter teri spen 14d 15 32 23 8 bit Bus Timings uote rrt 15 16 8XC196MC MD MH USER S MANUAL intel 15 4 WAIT STATES READY 15 17 15 5 BUS CONTROL 5 2 0 2 2 0 1 daii ntn tb nnne n teni eterni 15 21 15 5 1 Standard Bus control Mode sse 15 22 15 5 2 Write Strobe Mode ceteri era 15 25 15 5 3 Address Valid Strobe Mode see em eene nens 15 27 15 5 4 Address Valid with Write Strobe 15 30 15 6 SYSTEM BUS AC TIMING
31. WG RELOAD Changed P WG_COUNTER N WG RELOAD WG COUNTER Value 1 Carrier Period A2636 01 Reset Write to WG_RELOAD Figure 9 4 Center aligned Modes Counter Operation In mode 0 the WG_COMPx and WG_OUTPUT registers are updated only once during the car rier period when the counter reaches the reload value In mode 1 these registers are updated twice during the carrier period first when the counter is set to 1 then again when it reaches the reload value 8XC196MC MD MH USER S MANUAL intel WG COMPx WG COUNTER WG_COUNTER WG COMPx bc qr WG Interrupt P6 0 WG1 Note Carrier period and duty cycle both change since WG_COMPx is not changed P6 1 WG1 Mode 0 OPO OP1 1 PH1 0 PH1 1 PH1 2 1 Additional interrupt in mode 1 only A2641 01 Figure 9 5 Center aligned Modes Output Operation 9 3 5 2 Edge Aligned Modes In the edge aligned modes the counter begins at 1 and counts up to the WG_RELOAD value When you write to the WG_RELOAD register WG_COUNTER is loaded with 0001H When you set the enable bit in the control register the counter begins counting up and continues count ing until it reaches the WG_RELOAD value or in mode 3 only until an EPA event occurs At this point WG_COUNTER is reloaded with 0001H and WG_RELOAD is updated so a new re load value takes effect for the next cycle The counter resumes co
32. 5 intel PI_MASK Continued Address Reset State 1FBCH AAH The peripheral interrupt mask PI_MASk register enables or disables masks interrupt requests associated with the peripheral interrupt the serial port interrupt SPI and the overflow underflow timer interrupt OVRTM 7 0 8XC196MC WG OVRTM2 OVRTM1 7 0 8XC196MD COMP5 WG OVRTM2 OVRTM1 7 0 8XC196MH SP1 SPO OVRTM2 OVRTM1 Kanta VET Function 0 OVRTM1 Timer 1 Overflow Underflow Setting this bit enables the timer 1 overflow underflow interrupt The timer 1 and timer 2 overflow underflow interrupts are associated with the overflow underflow timer interrupt OVRTM Setting INT 5 0 enables OVRTM C 36 intel REGISTERS PEND PI PEND Address 1FBEH E Reset State AAH When hardware detects a pending peripheral or timer interrupt it sets the corresponding bit in the interrupt pending INT PEND or INT PEND1 registers and the peripheral interrupt pending PEND register When the vector is taken the hardware clears the INT PEND INT PEND1 pending bit Reading this register clears all the Pl PEND bits Software can generate an interrupt by setting a PEND bit 7 0 8XC196MC WG OVRTM2 OVRTM1 7 0 8XC196MD 5 WG OVRTM2 OVRTM1 7 0 8XC196MH SP1 SPO OVR
33. Bit Number Bit Mnemonic Function ALE WR Address Valid Strobe and Write Strobe These bits define which bus control signals will be generated during external read and write cycles ALE WR 0 0 address valid with write strobe mode ADV RD WRL WRH 0 1 address valid strobe mode ADV RD WR BHE 1 0 write strobe mode ALE RD WRL WRH 1 1 standard bus control mode ALE RD WR BHE BWO Buswidth Control This bit along with the BW1 bit CCR1 2 selects the bus width BW1 BWO 0 0 illegal 0 1 16 bit only 1 0 8 bit only 1 1 BUSWIDTH pin controlled PD Powerdown Enable Controls whether the IDLPD 2 instruction causes the microcontroller to enter powerdown mode If your design uses powerdown mode set this bit when you program the CCBs If it does not clearing this bit when you program the CCBs will prevent accidental entry into powerdown mode 0 disable powerdown mode 1 enable powerdown mode The CCRs are loaded with the contents of the chip configuration bytes CCBs after reset unless the microcontroller is entering programming modes see Entering Programming Modes on page 16 13 in which case the programming chip configuration bytes PCCBs are used The CCBs reside in nonvolatile memory at addresses 2018H CCBO and 201AH 1 15 8 Figure 15 1 Chip Configuration 0 CCRO Register Continued intel INTERFACING WITH EXTERNAL M
34. C 24 intel The interrupt mask INT_MASk register enables or disables masks individual interrupt requests The El and DI instructions enable and disable servicing of all maskable interrupts INT_MASK is the low byte of the processor status word PSW PUSHF or PUSHA saves the contents of this register onto the stack and then clears this register Interrupt calls cannot occur immediately following this instruction POPF or POPA restores it REGISTERS INT_MASK INT_MASK Address 0008H Reset State 00H The standard interrupt vector locations are as follows Bit Mnemonic Interrupt COMP2 MC MD EPA Compare only Channel 2 COMPS MH EPA Compare only Channel 3 EPA2 MC MD EPA Capture Compare Channel 2 2 MH EPA Compare Channel 2 COMP1 EPA Compare Channel 1 EPA1 EPA Capture Compare Channel 1 COMPO EPA Compare Channel 0 EPAO EPA Capture Compare Channel 0 AD A D Conversion Complete OVRTMt Overflow Underflow Timer Both timer 1 and timer 2 can generate the multiplexed overflow underflow interrupt Write to PI MASK to enable the interrupt sources read to determine which source caused the interrupt Standard Vector 200EH 200EH 200CH 200EH 200AH 2008H 2006H 2004H 2002H 2000H 7 0 MC MD 2 EPA2 1 EPA1 COMPO EPAO AD OVRTM 7 0 MH COMP2 1 EPA1 COMPO EPAO AD OVRTM Bit Number Function 7
35. forces the output to re main low Figure 10 2 shows typical PWM output waveforms NOTE The PWMx CONTROL register value and corresponding duty cycle result in Figure 10 2 are true only when the PWM PERIOD register value is FFH Duty PWM Control Cycle Register Value Output Waveform 0 00H 0 10 19H JI 90 E6H o T Il U 99 6 FFH T T A0119 02 Figure 10 2 PWM Output Waveforms 10 4 PROGRAMMING THE FREQUENCY AND PERIOD The input frequency on XTALI Fs44 and the contents of the PWM_PERIOD register deter mine the PWM output frequency and period Table 10 3 shows the PWM output frequencies for common values of Fy44 with a variety of PWM_PERIOD values Use the fol lowing formulas to calculate the PWM period value for the desired output frequency and write the corresponding value to the PWM_PERIOD register 512x PWM_PERIOD 1 Towa inus SSS XTAL Frat in 51 PWM_PERIOD 1 10 4 intel PULSE WIDTH MODULATOR where PWM PERIOD 8 bit value to load into the PWM PERIOD register FyraLt input frequency on XTAL1 pin in MHz output period on the PWM output pins us Fowm output frequency on the PWM output pins in MHz Table 10 3 PWM Output Frequencies XTAL1 Frequency Fyz 1 PWM_PERIOD 8 MHz 10 MHz 16 MHz 00H 15 6 kHz 19 5 kHz 31 2 kHz OFH 976 6 Hz 122
36. End Of PTS Interrupt Save Critical Data N Disable EPA Channel Clear Interrupt Request Bit t Error Start Bi N Initialize EPA Channel N Set Time To kirsi Save Received Data RXDDONE 3 Bit Sample R_COUNT R_COUNT 1 Enable PTS Service for EPA Channel Set up next data reception Clear DATA register Reload PTSCOUNT and PTSCON1 registers RXDDONE 1 Select PTS service for EPA channel Re initialize the EPA channel Load Critical Data A3277 01 Figure 5 28 Asynchronous SIO Receive Mode End of PTS Interrupt Routine Flowchart 5 58 intel I O Ports intel CHAPTER 6 PORTS I O ports provide a mechanism to transfer information between the device and the surrounding system circuitry They can read system status monitor system operation output device status configure system options generate control signals provide serial communication and so on Their usefulness in an application is limited only by the number of I O pins available and the imagination of the engineer 6 1 I O PORTS OVERVIEW Standard I O port registers are located in the SFR address space and they can be windowed Mem ory mapped I O port registers are located in memory mapped address space Memory mapped registers must be accessed with indirect or indexed addressing they cannot be windowed All ports can provide low speed input output pins or serve alter
37. JPR ARIA AK IK AR ke Koo OS KARR now initialize the WFG X Re D Cr set up interrupts ldb temp 00010000b n stb temp PI_MASK 0 unmask WG interrupt ldb temp 00100000b ldb int maskl temp 9 22 intel WAVEFORM GENERATOR load WFG registers call wgout initialize WG OUTPUT register call loadregs initialize reload amp compare regs call protect initialize protection call wgcon initialize WG CONTROL enable interrupts amp loop here ei sjmp J PEAR Ge KK Sk AR ek eek ALARA ERK RAR RK form WG OUTPUT value from variable data PAPO eae Ano e de edente aseo a a a wgout 1 temp op1 opl and temp 00018 mask shl temp 15 move bit to correct location id temp1 get 0 templ 0001h mask shl templ 414 move bit to correct location or temp1 temp combine ld temp sync get sync bit and temp 00018 mask shl temp 13 move to correct location or temp1 temp combine 1 temp pe7 get pe7 bit and temp 40001h mask shl temp 12 move to correct location or temp1 temp combine ld temp bit and temp 00018 mask shl temp 11 move to correct location or temp1 temp combine ld temp ph3 get ph3 bits and temp 0004h mask for ph3 2 shl temp 86 move or temp1 temp combine ld temp ph2 get ph2 bits and temp 0004h mask for ph2 2 shl temp 76 mo
38. its code widths are all exactly one LSB These qualities result in a digitization without zero offset full scale or linearity errors in other words a perfect conversion 12 15 8XC196MC MD MH USER S MANUAL intel 1nd1no ZERO OFFSET 1 2 1 2 3 4 5 6 6 1 2 7 8 INPUT VOLTAGE LSBs A0084 01 Figure 12 10 Actual and Ideal A D Conversion Characteristics The actual characteristic of a hypothetical 3 bit converter is not perfect When the ideal charac teristic is overlaid with the actual characteristic the actual converter is seen to exhibit errors in the locations of the first and final code transitions and in code widths as shown in Figure 12 10 The deviation of the first code transition from ideal is called zero offset error and the deviation of the final code transition from ideal is full scale error The deviation of a code width from ideal causes two types of errors differential nonlinearity and nonlinearity Differential nonlinearity is a measure of local code width error whereas nonlinearity is a measure of overall code transition error 12 16 intel ANALOG TO DIGITAL A D CONVERTER Differential nonlinearity is the degree to which actual code widths differ from the ideal one LSB width It provides a measure of how much the input voltage may have changed in order to produce a one count change in the conversion result In the 10 bit converter the code widths are ideall
39. t On the 8XC196MC device bits 10 12 are reserved For compatibility with future devices write zeros C 42 intel REGISTERS PTSSRV PTSSRV Address 0006H Reset State 0000H The PTS service PTSSRV register is used by the hardware to indicate that the final PTS interrupt has been serviced by the PTS routine When PTSCOUNT reaches zero hardware clears the corre sponding PTSSEL bit and sets the PTSSRV bit which requests the end of PTS interrupt When the end of PTS interrupt is called hardware clears the PTSSRV bit The PTSSEL bit must be set manually to re enable the PTS channel 15 8 8XC196MC EXTINT PI COMP3 EPA3 7 0 COMP2 EPA2 COMP1 EPA1 COMPO EPAO AD OVRTM 15 8 8XC196MD EXTINT PI EPA5 COMP4 EPA4 COMP3 EPA3 7 0 COMP2 EPA2 1 EPA1 COMPO EPAO AD OVRTM 15 8 8XC196MH EXTINT WG SPI Ri RIO TH TIO 7 0 2 1 EPA1 COMPO EPAO AD OVRTM Bit Number Function 15 Reserved This bit is undefined 14 07 A bit is set by hardware to request an end of PTS interrupt for the corresponding interrupt through its standard interrupt vector The PTS interrupt vector locations are as follows Bit Mnemonic EXTINT PI MC MD WG MH 5 MD SPI COMP4 MD MH EPA4 MD RIO MH COMP3 MC MD TH MH EPA3 MC MD PTS service is not useful for multiplex
40. 3 1 6 DOUBLE WORD Operands A DOUBLE WORD is an unsigned 32 bit variable that can take on values from 0 through 4 294 967 295 232 1 The architecture directly supports DOUBLE WORD operands only as the operand in shift operations as the dividend in 32 by 16 divide operations and as the product of 16 by 16 multiply operations For these operations a DOUBLE WORD variable must reside in the lower register file and must be aligned at an address that is evenly divisible by four The address of a DOUBLE WORD is that of its least significant byte the even byte address The least significant word of the DOUBLE WORD is always in the lower address even when the data is in the stack This means that the most significant word must be pushed into the stack first DOUBLE WORD operations that are not directly supported can be easily implemented with two WORD operations For example the following sequences of 16 bit operations perform a 32 bit addition and a 32 bit subtraction respectively ADD 2 operand addition ADDC REG2 2 operand subtraction SUBC 2 8XC196MC MD MH USER S MANUAL intel 3 1 7 LONG INTEGER Operands A LONG INTEGER is a 32 bit signed variable that can take on values from 2 147 483 648 231 through 2 147 483 647 2311 The architecture directly supports LONG INTEGER operands only as the operand in shift operations as the dividend in 32 b
41. 7 CE Counter Enable This bit enables or disables the timer From reset the timers are disabled and not free running 0 disables timer 1 enables timer 6 UD Up Down This bit determines the timer counting direction in selected modes see mode bits M2 0 0 count down 1 count up 5 3 M2 0 EPA Clock Direction Mode Bits These bits determine the timer clocking source and direction control source M2 Mi 0 Clock Source Direction Source 0 0 0 1 4 UD bit T1CONTROL 6 X 0 1 T1CLK pint UD bit T1CONTROL 6 0 1 0 1 4 T1DIR pin 0 1 1 T1CLK pint T1DIR pin 1 1 1 quadrature clocking using T1CLK and T1DIR T If an external clock is selected the timer counts on both the rising and falling edges of the clock 2 0 P2 0 EPA Clock Prescaler Bits These bits determine the clock prescaler value P2 P1 PO Prescaler Divisor Resolution 0 0 0 divide by 1 disabled 250 ns 0 0 1 divide by 2 500 ns 0 1 0 divide by 4 1 us 0 1 1 divide by 8 2 us 1 0 0 divide by 16 4us 1 0 1 divide by 32 8 us 1 1 0 divide by 64 16 us 1 1 1 enable TT RELOAD T At 16 MHz Use the formula on page 11 6 to calculate the resolution at other frequencies Figure 11 8 Timer 1 Control T1CONTROL Register 11 16 intel EVENT PROCESSOR ARRAY EPA T2CONTROL Address 1F7CH Reset State 00H The timer 2 control T2CONTROL register determines the clock source counting direction and count rate for
42. C 49 8XC196MC MD MH USER S MANUAL intel SPx BAUD SPx BAUD Address 1F84H 1F8CH x 0 1 8XC196MH Reset State 0000H The serial port baud rate x SPx BAUD register selects the serial port x baud rate and clock source The most significant bit selects the clock source The lower 15 bits represent BAUD VALUE an unsigned integer that determines the baud rate The maximum BAUD VALUE is 32 767 7FFFH In asynchronous modes 1 2 and 3 the minimum BAUD VALUE is 0000H when using XTAL1 and 0001H when using BCLKx In synchronous mode 0 the minimum BAUD VALUE is 0001H for transmissions and 0002H for receptions In synchronous mode 4 the minimum BAUD VALUE is 0001H for both transmissions and receptions 15 8 8XC196MH CLKSRC BV14 BV13 BV12 BV11 BV10 BV9 BV8 7 0 BV7 BV6 BV5 BV4 BV3 2 BV1 BVO Bit Bit Function Number Mnemonic 15 CLKSRC Serial Port Clock Source This bit determines whether the serial port is clocked from an internal or an external source 0 signal on the T1CLK pin external source 1 input frequency on the XTAL1 pin internal source 14 0 BV14 0 These bits constitute the BAUD_VALUE Use the following equations to determine the BAUD_VALUE for a given baud rate Synchronous mode 0 1 FxrAL1 BCLKx BAUD VALUE Baud Ratex Baud Rate Asynchronous modes 1 2 and 3 FxrAL1 BCLKx BAUD VALUE Baud Rate 16 Baud Rate x 8 Synchronous
43. DATA H unused BAUD L AOH 9600 baud at 16 MHz DATA L nnH 8 data bits EPAREG 1FH 0 TIME PTSCON1 21H enable odd parity EPAREG L 42H EPAQ_ TIME PORTMASK 01H P2 0 TXD PTSCON 60H ASIO transmit mode PORTREG H 1FH P2 REG PTSCOUNT 0AH 8 data bits 1 parity amp 1 stop PORTREG L D4H P2 REG bit Load the number of bytes to transmit into the user defined transmit count register Start the operation of the EPAO channel by writing the time of the first interrupt to EPAO TIME To set up the correct value add the baud value 1A0H to the current TIMERI value and store the result in EPAO TIME The baud value determines the time to the first PTS interrupt When the interrupt occurs the PTS transmits the first data bit 7 Enable EPAO interrupt Set INT MASK A 8 T COUNT and clear the user defined transfer done flag TXDDONE LD T COUNT 16 CLRB TXDDONE 9 Select PTS service for EPAO Set PTSSEL 2 10 Set up the transmission start bit Clear P2 0 11 Set up EPAO as a compare only channel Set CON 6 Figure 11 10 on page 11 19 12 The baud value of 1 selects a baud rate of 9600 13 Enable the PTS and conventional interrupts 5 52 Use the EI instruction to enable all standard interrupts and the EPTS instruction to enable the PTS intel STANDARD AND PTS INTERRUPTS 14 Th
44. Output Data Hold after WR High Length of time output data is valid on the bus after the microcontroller deasserts WR WR Low to WR High WRi pulse width XTAL1 High to CLKOUT High or Low Tyrani The period of the frequency on the XTAL1 input Fyz4 4 All AC timings are referenced to Tyrant The CLKOUT pin is available only on the 8XC196MC MD microcontrollers 15 35 intel 16 Programming the Nonvolatile Memory intel CHAPTER 16 PROGRAMMING THE NONVOLATILE MEMORY The 87C196MC and 87C196MD contain 16 Kbytes of one time programmable read only mem ory OTPROM the 87C196MH contains 32 Kbytes OTPROM is similar to EPROM but it comes in an unwindowed package and cannot be erased You can either program the OTPROM yourself or have the factory program it as a quick tum ROM product this option may not be available for all devices This chapter provides procedures and guidelines to help you program the device The information is organized as follows overview of programming methods OTPROM memory map page 16 2 security features page 16 3 programming pulse width page 16 8 modified quick pulse algorithm page 16 9 programming mode pins page 16 11 entering programming modes page 16 13 slave programming page 16 15 auto programming page 16 25 PCCB and UPROM programming 8XC196MH only page 16 30 run time programming page 16 32 16
45. Programming Considerations for a discussion of addressing modes Windowing can provide for fast context switching of interrupt tasks and faster program execution See Windowing on page 4 12 PTS control blocks and the stack are most efficient when located in the upper register file 4 1 6 2 Stack Pointer SP Memory locations 0018H and 0019H contain the stack pointer SP The SP contains the address of the stack The SP must point to a word even address that is two bytes greater than the desired starting address Before the CPU executes a subroutine call or interrupt service routine it decre ments the SP by two and copies PUSHes the address of the next instruction from the program counter onto the stack It then loads the address of the subroutine or interrupt service routine into the program counter When it executes the return from subroutine RET instruction at the end of the subroutine or interrupt service routine the CPU loads POPs the contents of the top of the stack that is the return address into the program counter and increments the SP by two Subroutines may be nested That is each subroutine may call other subroutines The CPU pushes the contents of the program counter onto the stack each time it executes a subroutine call The stack grows downward as entries are added The only limit to the nesting depth is the amount of available memory As the CPU returns from each nested subroutine it pops the address off
46. 1 in MHz SERT PH2 State Time in us XTAL1 Because the microcontroller can operate at many frequencies this manual defines time require ments such as instruction execution times in terms of state times rather than specific measure ments Datasheets list AC characteristics in terms of clock periods 2 5 INTERNAL PERIPHERALS The internal peripheral modules provide special functions for a variety of applications This sec tion provides a brief description of the peripherals subsequent chapters describe them in detail 2 8 intel ARCHITECTURAL OVERVIEW 2 5 4 W O Ports The 8 196 microcontrollers have seven I O ports ports 0 6 The 8XC196MD has an addi tional port port 7 Individual port pins are multiplexed to serve as standard I O or to carry special function signals associated with an on chip peripheral or an off chip component If a particular special function signal is not used in an application the associated pin can be individually con figured to serve as a standard I O pin Ports 3 and 4 are exceptions they are controlled at the port level not at the pin level When the bus controller needs to use the address data bus it takes con trol of the ports When the address data bus is idle you can use the ports for I O Port 0 is an input only port that is also the analog input for the A D converter On the 8XC196MH port 0 provides two pins for the EPA
47. REGISTERS WG_OUTPUT Waveform Generator Table C 11 Output Configuration Output Values Output Polarities PHx 2 PHx 1 PHx 0 WGx WGx WGx WGx 1 0 0 Low Low Always Low Always Low 1 0 1 Low WG_EVEN Always Low 1 1 0 WG ODD Low Always Low 1 1 1 WG ODD WG EVEN quse ET NOTE This table assumes active high outputs 1 1 C 65 8XC196MC MD MH USER S MANUAL intel WG PROTECT WG PROTECT Address 1FCEH Reset State MC MD FOH Reset State MH EOH The waveform protection WG register enables and disables the outputs and the protection circuitry It also selects either level sensitive or edge triggered EXTINT interrupts and selects which level or edge will generate an EXTINT interrupt request 7 0 8XC196MC MD ES IT DP EO 7 0 8XC196MH PT ES IT DP EO Bit Bit Number Mnemonic Function 7 5 Reserved for compatibility with future devices write zeros to these bits et PT Protection Type This bit selects the method used for disabling the outputs 0 inactive states 1 weak pull ups 3 2 ES Enable Sampling and Interrupt Type IT The ES bit selects whether the protection circuitry samples the EXTINT signal level or detects a signal transition edge while the IT bit controls which value of the edge or level triggers an interrupt request The possible com
48. SP lt SP 2 3 2 3 1 Indirect Addressing with Autoincrement You can choose to automatically increment the indirect address after the current access You spec ify autoincrementing by adding a plus sign to the end of the indirect reference In this case the instruction automatically increments the indirect address by one if the destination is an 8 bit register or by two if it is a 16 bit register When your code is assembled the assembler automat ically sets the least significant bit of the indirect address register The following instructions use indirect addressing with autoincrement LD AX BX lt MEM_WORD BX BX lt BX 2 AL lt BL ADDB 1 CX CX amp 1 PUSH SSP i 2 MEM_WORD SP lt MEM WORD AX lt AX 2 3 2 3 2 Indirect Addressing with the Stack Pointer You can also use indirect addressing to access the top of the stack by using the stack pointer as the WORD register in an indirect reference The following instruction uses indirect addressing with the stack pointer PUSH SP duplicate top of stack SP lt 5 2 3 2 4 Indexed Addressing Indexed addressing calculates an address by adding an offset to a base address There are three variations of indexed addressing short indexed long indexed and zero indexed Both short and long indexed addressing are used to access a specific element within
49. This register contains one bit that globally enables or disables servicing of all maskable interrupts and another that enables or disables the PTS These bits are set or cleared by executing the enable interrupts El disable interrupts DI enable PTS EPTS and disable PTS DPTS instructions PTSSEL 0004H 0005H PTS Select Register This register selects either a PTS routine or a standard interrupt Service routine for each of the maskable interrupt requests PTSSRV 0006H 0007H PTS Service Register The bits in this register are set by hardware to request an end of PTS interrupt 5 3 INTERRUPT SOURCES AND PRIORITIES Table 5 3 lists the interrupts sources their default priorities 30 is highest and 0 is lowest and their vector addresses The unimplemented opcode and software trap interrupts are not priori tized they go directly to the interrupt controller for servicing The priority encoder determines the priority of all other pending interrupt requests NMI has the highest priority of all prioritized interrupts PTS interrupts have the next highest priority and standard interrupts have the lowest The priority encoder selects the highest priority pending request and the interrupt controller se lects the corresponding vector location in special purpose memory This vector contains the start ing base address of the corresponding PTS control block PTSCB or interrupt service routine PTSCBs m
50. 12 P2 5 COMP1 PACT 14 P4 6 PBUS 14 E 13 P2 4 COMPO Voc NC AD13 P4 5 PBUS 13 E 15 NC CLKOUT o 16 2 7 COMP3 AD12 P4 4 PBUS 12 E 17 2 3 AD11 P4 3 PBUS 11 18 P2 2 EPA2 PROG AD10 P4 2 PBUS 10 E 19 NC AD9 PBUS 9 2 20 N8XC196MC NG AD8 P4 0 PBUS 8 21 NC o 23 NC AD7 P3 7 PBUS 7 24 View of component as P0 0 ACHO P2 1 EPA1 PALE NC E322 P2 0 PVER AD6 P3 6 PBUS 6 25 mounted on PC board P0 1 ACH1 AD5 P3 5 PBUS 5 26 P0 2 ACH2 AD4 P3 4 PBUS 4 E 27 P0 3 ACH3 AD3 P3 3 PBUS 3 28 P0 4 PMODE O AD2 P3 2 PBUS 2 29 P0 5 ACH5 PMODE 1 AD1 P3 1 PBUS 1 30 VREF ADO P3 0 PBUS 0 31 ANGND NC r1 32 P0 6 ACH6 PMODE 2 xt LO KO O CO xt 10 00 AM CO CO CO CO s b b FP Wb xb MB MB Mb LO 10 LI L LI LI LI LI LI LI LI LI LI LE LI LIE LE LE LE LI LI LI LI 25955 uzi 2 22059298950200 2r5o0Hl a 9 lt lt 0 OOo SSS for ofere Y oo T lt lt an 5 tt A3101 02 Figure B 2 8XC196MC 84 lead PLCC Package intel SIGNAL DESCRIPTIONS 80 F P5 5 BHE WRH 79 P5 3 RD amp 78 B Vpp 77 P5 0 ALE ADV 76 Vss 73 5 4 ONCE 72 71 F Vss 70 EB
51. Control Logic TI Interrupts RI SPx STATUS SPx BAUD MSB A2774 01 Figure 7 1 SIO Block Diagram The serial port receives data into the receive buffer SBUFx RX and transmits data from the port through the transmit buffer SBUFx_RX The transmit and receive buffers are separate registers permitting simultaneous reads and writes to both These buffers support continuous transmissions and allow reception of a second byte before the first byte has been read 8XC196MC MD MH USER S MANUAL intel An independent 15 bit baud rate generator controls the baud rate of the serial port Either XTAL1 or BCLKx can provide the clock signal for modes 0 3 In mode 4 the internal shift clock is output on SCLK or an external shift clock is input on SCLKx in which case the baud rate generator is not used The baud rate register SPx BAUD selects the clock source and the baud rate The serial port control register SPx CON register controls whether SCLKx outputs the internal shift clock or inputs an external shift clock 7 2 SERIAL I O PORT SIGNALS AND REGISTERS Table 7 1 describes the SIO signals and Table 7 2 describes the control and status registers Table 7 1 Serial Port Signals Serial Port Serial Port Port ee Pin Signal Signal Description Type P1 0 TXDO Transmit Serial Data 1 2 TXD1 In modes 1 2 3 and 4 TXDx transmits serial port output data In mode 0 it is the serial clock outpu
52. NOTE Memory mapped SFRs must be accessed using indirect or indexed addressing modes they cannot be accessed through a window Reading a memory mapped SFR through a window returns FFH all ones and writing to a memory mapped SFR through a window has no effect intel 4 2 1 Selecting a Window MEMORY PARTITIONS The window selection register Figure 4 3 selects a window to be mapped into the top of the low er register file Table 4 9 provides a quick reference of WSR values for windowing the peripheral SFRs Table 4 10 on page 4 14 lists the WSR values for windowing the upper register file WSR Address 0014H Reset State 00H The window selection register WSR maps sections of RAM into the top of the lower register file in 32 64 or 128 byte increments PUSHA saves this register on the stack and POPA restores it 7 0 W6 W4 W3 W2 W1 WO Bit Bit Number Mnemonic Funeton 7 Reserved for compatibility with future devices write zero to this bit 6 0 W6 0 Window Selection These bits specify the window size and number See Table 4 9 on page 4 13 or Table 4 10 on page 4 14 See Table 4 9 for peripheral SFR windows or Table 4 10 for upper register file windows Figure 4 3 Window Selection WSR Register Table 4 9 Selecting a Window of Peripheral SFRs WSR Value for WSR Value for WSR Value for Peripherals 32 byte Window 64 b
53. Reserved for compatibility with future devices write zeros to these bits 6 MC Reserved for compatibility with future devices write zero to this bit COMP5 EPA Compare Channel 5 Setting this bit enables the EPA compare channel 5 interrupt The EPA compare channel 5 and the waveform generator interrupts are associated with the peripheral interrupt Pl Setting INT_MASK1 5 enables PI SP1 MH Serial Port 1 Error Setting this bit enables the serial port 1 error interrupt The serial port 1 and serial port 0 error interrupts are associated with the serial port interrupt Setting INT_MASK1 4 enables SPI 4 WG MC MD Waveform Generator Setting this bit enables the waveform generator interrupt The waveform generator and the EPA compare channel 5 interrupts are associated with the peripheral interrupt Pl Setting INT_MASK1 5 enables PI SPO MH Serial Port 0 Error Setting this bit enables the serial port 0 error interrupt The serial port 0 and serial port 1 error interrupts are associated with the serial port interrupt Setting INT_MASK1 4 enables SPI 2 OVRTM2 Timer 2 Overflow Underflow Setting this bit enables the timer 2 overflow underflow interrupt The timer 2 and timer 1 overflow underflow interrupts are associated with the overflow underflow timer interrupt OVRTM Setting INT MASK 0 enables OVRTM C 35 8XC196MC MD MH USER S MANUAL
54. When hardware detects a pending peripheral or timer interrupt it sets the corresponding bit in the interrupt pending INT PEND or INT PEND1 registers and the peripheral interrupt pending PEND register When the vector is taken the hardware clears the INT PEND INT PEND1 pending bit Reading this register clears all the PEND bits Software can generate an interrupt by setting a PEND bit 7 0 8XC196MC WG OVRTM2 OVRTM1 7 0 8XC196MD 5 WG OVRTM2 OVRTM1 7 0 8XC196MH SP1 SPO OVRTM2 OVRTM1 am TOUR Function 7 5 3 1 Reserved These bits are undefined 6 MC Reserved This bit is undefined 5 MD EPA Compare Channel 5 When set this bit indicates a pending EPA compare channel 5 interrupt The EPA compare channel 5 and the waveform generator interrupts are associated with the peripheral interrupt PI Setting INT_MASK1 5 enables PI Setting Pl MASK 6 enables COMP5 SP1 MH Serial Port 1 Error When set this bit indicates a pending serial port 1 error interrupt The serial port 1 and 0 error interrupts are associated with the serial port interrupt SPI Setting INT_MASK1 4 enables SPI Setting PI_MASK 6 enables SP1 4 WG MC MD Waveform Generator When set this bit indicates a pending waveform generator interrupt The waveform generator and the EPA compare channel 5 interrupts are associated with the p
55. intel We Value Your Opinion Dear Intel Customer We have updated the information that was provided in the 1992 version of the 8XC196MC User s Manual added information about the 8XC196MD and 8XC196MH and corrected known errata We hope these changes make it easier for you to use our products Your feedback will help us to provide the information you need We ll use your responses to guide us in developing other man uals and new versions of this one Does the manual contain the information that you need If not what s missing What do you like the most about this manual What do you like the least about this manual How would you rate the overall quality 1 awful 2 average 3 better than average _ Name Title Company Address City State or Country Zip Code or Postal Code Phone Fax Intel products used Type of application Please fax this form to 602 554 7436 or mail it to Marcia Bethel Glenn Dotson Robin Manelis and Sue Ranta Technical Information Developers Intel Corporation Mail Stop CH6 224 5000 W Chandler Blvd Chandler AZ 85226 intel 8XC196MC 8XC196MD 8XC196MH Microcontroller User s Manual October 1995 Information in this document is provided solely to enable use of Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel s
56. unsigned arithmetic and stores the word result into the destination operand The sticky bit flag is undefined after the instruction is executed DEST lt SRC1 x SRC2 010111 baop breg wreg PSW Flag Settings Z N C V VT ST A 26 intel INSTRUCTION SET REFERENCE Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format NEG NEGATE INTEGER Negates the value of the integer operand NEG wreg DEST lt DEST 00000011 wreg PSW Flag Settings Z N C V VI ST V v 7 v Tt NEGB NEGATE SHORT INTEGER Negates the value of the short integer operand NEGB breg DEST lt DEST 00010011 breg PSW Flag Settings Z N C V VI ST tia NOP NO OPERATION Does nothing Control passes to the next sequential instruction NOP PSW Flag Settings 11111101 Z N C V VI ST NORML NORMALIZE LONG INTEGER Normalizes SRC DEST the source leftmost long integer operand NORML breg That is it shifts the operand to the left until its most significant bit is 1 or until it has performed 31 shifts If the most significant bit is still 0 after 31 shifts the instruction stops the process and sets the zero flag The instruction stores the actual number of shifts performed in the destination rightmost
57. x 0 1 8XC196MH x 0 3 8XC196MC x 0 5 8XC196MD Address Reset State Table C 4 The EPA control EPAx CON registers control the functions of their assigned capture compare channels 7 0 x 0 2 4 TB CE M1 0 RE WGR ROT ON RT 7 0 x 1 3 5 TB CE M1 0 RE AD ROT ON RT Bit Bit Number Mnemonic Function 0 ON RT Overwrite New Reset Timer The ON RT bit functions as overwrite new in capture mode and reset timer in compare mode In Capture Mode ON An overrun error is generated when an input capture occurs while the event time register EPAx_TIME and its buffer are both full When an overrun occurs the ON bit determines whether old data is overwritten or new data is ignored 0 ignores new data 1 overwrites old data in the buffer In Compare Mode RT 0 disables the reset function 1 resets the ROT selected timer Table C 4 EPAx_CON Addresses and Reset Values Register Address Reset Value EPAO CON 8XC196M x 1F40H 00H EPA1 CON 8XC196M x 1F44H 00H EPA2 CON 8XC196MC MD 1F48H 00H CON 8XC196MC MD 1F4CH 00H 4 CON 8XC196MD 1F50H 00H 5 CON 8XC196MD 1F54H 00H C 20 intel REGISTERS EPAx TIME EPAx TIME Address Table C 5 x 0 1 8XC196MH Reset State x 0 3 8XC196MC 0 5 8XC196MD The EPA time EPAx_TIME registers are the event time registers for t
58. 0 0 0 0 0 0 RETURN FROM SUBROUTINE Pops the PC off the top of the stack RET PC lt SP 11110000 SP lt SP 2 PSW Flag Settings A 30 intel INSTRUCTION SET REFERENCE Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format RST RESET SYSTEM Initializes the PSW to zero the PC to 2080H and the pins and SFRs to RST their reset values Executing this instruction causes the RESET pin to be pulled low for 11111111 16 state times SFR lt Reset Status Pin lt Reset Status PSW lt 0 PC 2080H PSW Flag Settings 5 0 0 0 0 0 0 SCALL SHORT CALL Pushes the contents of the program counter the return address onto the stack then adds to the program counter the offset between the end of this instruction 00101 disp low and the target label effecting the call The offset must be in the range of 1024 to NOTE The displacement disp is sign 41023 extended to 16 bits SP lt SP 2 SP lt PC PC lt PC 11 bit disp PSW Flag Settings SETC SET CARRY FLAG Sets the carry flag C lt 1 SETC 11111001 PSW Flag Settings 7 VT ST 1 A 31 8XC196MC MD MH USER S MANUAL Table A 6 Instruction Set Continued tel Mnemonic Operation Instru
59. 011011aa waop Ireg MUL 8 operands MULTIPLY INTEGERS Multiplies the two Source integer operands using signed arithmetic and stores the 32 bit result into the destination long integer operand The sticky bit flag is undefined after the instruction is executed DEST lt SRC1 x SRC2 PSW Flag Settings 7 VT ST DEST SRC1 SRC2 MUL lreg wreg waop 11111110 010011aa wreg Ireg MULB 2 operands MULTIPLY SHORT INTEGERS Multiplies the source and destination short integer operands using signed arithmetic and stores the 16 bit result into the destination integer operand The sticky bit flag is undefined after the instruction is executed DEST lt DEST x SRC PSW Flag Settings ST DEST SRC wreg baop 11111110 011111 wreg MULB 8 operands MULTIPLY SHORT INTEGERS Multiplies the two source short integer operands using signed arithmetic and stores the 16 bit result into the destination integer operand The sticky bit flag is undefined after the instruction is executed DEST lt SRC1 x SRC2 PSW Flag Settings ST DEST SRC1 SRC2 MULB wreg breg baop 11111110 010111aa baop breg wreg A 25 8XC196MC MD MH USER S MANUAL intel Table A 6 Instruction S
60. 11 5 4 Programming the Compare only Channels 11 22 11 6 ENABLING THE EPA INTERRUPTS icii nnee rre nennen enn 11 23 11 7 DETERMINING EVENT 6 5 11 24 12 ANALOG TO DIGITAL A D CONVERTER 12 1 A D CONVERTER FUNCTIONAL 12 1 12 2 A D CONVERTER SIGNALS AND REGISTERS seen 12 2 12 3 A D CONVERTER 12 3 12 4 PROGRAMMING THE A D 12 4 12 4 1 Programming the A D Test Register ZO 12 4 2 Programming the A D Result Register for Threshold Detection Only 2 8 12 4 8 Programming the A D Time Register mmn 12 6 12 4 4 Programming the A D Command Register esse 12 7 12 4 5 Enabling the A D emm meme 12 8 12 5 DETERMINING A D STATUS AND CONVERSION 12 9 12 6 DESIGN 0 12 10 12 6 1 Designing External Interface 12 10 12 6 1 1 Minimizing the Effect of High Input Source Resistance 12 11 12 6 1 2 Suggested A D Input Circuit 2 a P Pa 12 6 1 3 Analog Ground and Reference Voltages 12 12 viii intel CONTENTS 12 6 1 4 Using Mixed Analog and Digital Inputs 12 13 12 6 2 Understanding A D
61. 16 8 2 Slave Programming Circuit and Memory 16 16 16 8 3 Operating 2 16 17 16 8 4 Slave Programming Routines 16 19 16 8 5 Timing 16 24 169 AUTO PROGRAMMING 16 25 16 9 1 Auto Programming Circuit and Memory 16 25 16 9 2 Operating Environment 16 27 16 9 3 Auto Programming Routine essen em ene 16 27 16 9 4 Auto Programming Procedure sse em eene 16 29 16 9 5 ROM dump 16 30 16 10 PCCB AND UPROM PROGRAMMING 8XC196MH ONLY 16 30 16 11 RUN TIME 16 32 intel CONTENTS APPENDIX A INSTRUCTION SET REFERENCE APPENDIX B SIGNAL DESCRIPTIONS 1 SIGNAL NAME 1 2 FUNCTIONAL GROUPINGS OF SIGNALS seen Bod 3 SIGNAL 2 P deii Dated s 12 B4 DEFAUET CONDITIONG Bee APPENDIX REGISTERS GLOSSARY INDEX xi 8XC196MC MD MH USER S MANUAL intel FIGURES Figure Page 2 1 8XC196Mx Block Diagana arniran et p
62. 3 operands source word operands and stores the result AND into the destination operand The result has ones in only the bit positions in which both 010000aa waop Swreg Dwreg operands had a 1 and zeros in all other bit positions DEST lt SRC1 AND SRC2 Dwreg Swreg waop PSW Flag Settings 0 0 LOGICAL AND BYTES ANDs the source DEST SRC 2 operands and destination byte operands and stores the ANDB breg baop result into the destination operand The result has ones in only the bit positions in which 011100aa baop breg both operands had a 1 and zeros in all other bit positions DEST lt DEST AND SRC PSW Flag Settings 0 0 8 intel INSTRUCTION SET REFERENCE Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format ANDB 3 operands LOGICAL AND BYTES ANDs the two source byte operands and stores the result into the destination operand The result has ones in only the bit positions in which both operands had a 1 and zeros in all other bit positions DEST lt SRC1 AND SRC2 PSW Flag Settings Z N C V VT ST 0 DEST SRC1 SRC2 ANDB Sbreg baop 010100aa baop Sbreg Dbreg BMOV BLOCK MOVE
63. 8XC196MC NMI EXTINT COMP3 EPA3 7 0 8XC196MD NMI EXTINT 5 4 4 7 0 8 196 SPI RIO TIO Bit c Number Function 7 07 Setting a bit enables the corresponding interrupt The standard interrupt vector locations are as follows Bit Mnemonic Interrupt Standard Vector NMI Nonmaskable Interrupt 203EH EXTINT EXTINT pin 203CH MC MD Multiplexed Peripheral Interrupt 203AH WG MH Waveform Generator 203AH 5 MD EPA Capture Compare Channel 5 2038H SPI Serial Port 2038H COMP4 MD EPA Compare Channel 4 2036H MH SIO 1 Receive 2036H EPA4 MD EPA Capture Compare Channel 4 2034H RIO MH SIO 0 Receive 2034H MC MD EPA Compare Channel 3 2032H MH SIO 1 Transmit 2032H EPA3 MC MD EPA Capture Compare Channel 3 2030H TIO MH SIO 0 Transmit 2030H On the 8XC196MC device bits 4 3 are reserved These bits are undefined C 28 intel REGISTERS ONES_REG ONES_REG The two byte ones register ONES_REG is always equal to FFFFH ones for comparison operations Address 02H Reset State FFFFH It is useful as a fixed source of all 15 0 One Bit Number Function 15 0 One These bits are always equal to FFFFH C 29 8XC196MC MD MH USER S MANUAL intel Px_DIR Px_DIR Address Table C 6 X 2 5 8XC196MC Reset St
64. 9 Channels Transition From Detector P6 0 WG1 Phase 10 Bit Counter Output CPs Tri Comparator Bah es CNT 0 Circuitry Edges WFG gt WFG A2640 01 Figure 9 2 Dead time Generator Circuitry 9 3 3 Control and Protection Circuitry The control circuitry contains the control WG_CONTROL and output WG_OUTPUT regis ters The control register enables or disables the counter specifies the count direction controls the operating mode and specifies the dead time for all three phases The output register config ures the pins specifies the output polarity active high or active low and controls whether the outputs are updated immediately or are synchronized with an event 8XC196MC MD MH USER S MANUAL intel The protection circuitry Figure 9 3 monitors the EXTINT pin When it detects a valid event on the input it simultaneously disables the outputs and generates an EXTINT interrupt request Soft ware can also disable the outputs by clearing the enable outputs EO bit in the protection WG_PROTECT register For the 8 196 and 8XC196MD disabled outputs go to their inactive states based on the programmed polarity The protection circuitry of the 8XC196MH operates in the same way as that of the 8 196 and 8XC196MD but it allows you to choose the method used to disable the outputs It can either place outputs in their inactive states as the other devices do or it c
65. C 69 P6_MODE C 69 P6_PIN C 69 INDEX P6_REG C 69 P7 7 0 B 19 PACT B 19 PALE 16 8 16 10 16 11 B 19 Parameters passing to subroutines 3 10 Parity 7 7 7 8 7 9 PBUS 16 12 PBUS15 0 B 19 PC program counter 2 4 master 2 6 slave 2 6 Peripheral Interrupt mask register 5 17 C 35 Peripheral interrupt pending register 5 23 C 37 Peripherals internal 2 8 Phase compare register 9 17 C 59 Pin out diagrams B 3 B 4 B 5 B 7 B 8 B 11 B 12 PLM 96 conventions 3 9 3 10 3 11 interrupt procedures 3 11 PMODE 16 11 16 13 and programming modes 16 14 PMODE3 0 B 19 POP instruction A 3 A 29 A 45 A 49 A 54 POPA instruction A 2 A 29 A 46 A 49 A 54 POPF instruction A 2 A 29 A 46 A 49 A 54 Port 0 6 2 B 17 considerations 6 4 12 13 13 5 idle powerdown reset status 25 input only pins 6 2 overview 6 1 structure 6 3 Port 1 6 2 B 17 considerations 6 4 6 12 idle powerdown reset status B 23 B 25 input buffer 6 7 input only pins 6 2 logic tables 6 9 operation 6 4 overview 6 1 SFRs 6 6 14 3 Port 2 14 2 B 18 considerations 6 12 idle powerdown reset status B 23 B 25 operation 6 4 overview 6 1 P2 7 considerations 6 12 P2 7 reset status 6 7 Index 7 8XC196MC MD MH USER S MANUAL SFRs 6 6 14 3 Port 3 B 18 addressing 6 14 idle powerdown reset status B 23 B 25 operation 6 15 6 16 overview 6 1 pin configuration 6 14 structure 6 15 Port 4 B 18
66. Continued Mnemonic Address Description PO PIN 1FA8H MC MD Port 0 Pin State 1FDAH MH Read PO PIN to determine the current values of the port 0 pins Reading the port induces noise into the A D converter decreasing the accuracy of any conversion in progress We strongly recommend that you not read the port while an A D conversion is in progress To reduce noise the PO PIN register is clocked only when the port is read P1 PIN MC MD 1FA9H MC MD Port 1 Pin State Read P1 PIN to determine the current values of the port 1 pins Reading the port induces noise into the A D converter decreasing the accuracy of any conversion in progress We strongly recommend that you not read the port while an A D conversion is in progress To reduce noise the P1 PIN register is clocked only when the port is read 12 3 A D CONVERTER OPERATION An A D conversion converts an analog input voltage to a digital value stores the result in the AD RESULT register and sets the A D interrupt pending bit An 8 bit conversion provides 20 mV resolution while a 10 bit conversion provides 5 mV resolution An 8 bit conversion takes less time than a 10 bit conversion because it has two fewer bits to resolve and the comparator re quires less settling time for 20 mV resolution than for 5 mV resolution You can convert either the voltage on an analog input channel or a test voltage Converting the test inputs allows you to calculate t
67. DEST DEST 2 Temp Temp 1 end while PSW Flag Settings Z N C V VT ST 0 0 SHR wreg count 00001000 count wreg or SHR wreg breg 00001000 breg wreg NOTES This instruction clears the sticky bit flag at the beginning of the instruction If at any time during the shift a 1 is shifted into the carry flag and another shift cycle occurs the instruc tion sets the sticky bit flag In this operation DEST 2 rep resents unsigned division A 33 8XC196MC MD MH USER S MANUAL Table A 6 Instruction Set Continued tel destination byte operand to the right as many times as specified by the count operand The count may be specified either as an immediate value in the range of 0 to 15 OFH inclusive or as the content of any register 10H OFFH with a value in the range of 0 to 31 inclusive If the original high order bit value was 0 zeros are shifted in If the value was 1 ones are shifted in The last bit shifted out is saved in the carry flag Temp lt COUNT do while Temp 0 C Low order bit of DEST DEST lt DEST 2 Temp lt Temp 1 end while PSW Flag Settings Z N C V VT ST 0 Mnemonic Operation Instruction Format SHRA ARITHMETIC RIGHT SHIFT WORD Shifts the de
68. If Disable Reset Out 1 pin is 3 f EA 0 Port Port 4 If EA 1 Port and Port 4 ODIO 4 If EA 1 pin is WK1 If EA 0 P5 0 P5 3 and P5 5 are configured as outputs and function as ADV RD or BHE respectively READY function not selected and three wait states inserted to allow fetch of CCB 13 14 15 24 BUSWIDTH function is selected If XTAL1 1 pin is LoZO If XTAL1 0 pin is 1071 If P5 MODE O 0 port is as programmed If P5 MODE 0 1 and CCR 3 1 ALE mode is 1070 If P5 MODE 0 1 and CCR 3 0 ADV mode pin is LoZ1 If P5 MODE 1 0 port is as programmed If PS5_MODE 1 1 is 1070 If P5 MODE y 0 port is as programmed If P5 MODE y 1 pin is 1071 If P5 MODE y 0 port is as programmed If P5 MODE y 1 pin is If Px MODE y 0 port is as programmed If Px_MODE y 1 pin is as specified by the associated peripheral If output port pin is as programmed If special function pin is as specified by the associated periph eral The values in this column are valid until your software writes to Px MODE Shaded rows indicate those signals that are available only on the 8XC196MD intel SIGNAL DESCRIPTIONS Table B 9 8XC196MH Default Signal Conditions Alternate During Port
69. In mode 0 writing to SBUFx TX starts a transmission only if the receiver is disabled SPx CON 3 0 SPO BAUD 1F84H 1F85H Serial Port x Baud Rate SP1 BAUD 1F8CH 1F8DH This register selects the serial port baud rate and clock source The most significant bit selects the clock source The lower 15 bits represent the BAUD VALUE an unsigned integer that determines the baud rate 5 0 CON 1F83H Serial Port x Control SP1 CON 1F8BH This register selects the communications mode and enables or disables the receiver parity checking and ninth bit data transmis sions The TB8 bit is cleared after each transmission For mode 4 this register also selects the direction input or output of the SCLKx signal SPO STATUS 1F81H Serial Port x Status SP1 STATUS 1F89H This register contains the serial port status bits It has status bits for receive overrun errors OE transmit buffer empty TXE framing errors FE transmit interrupt receive interrupt RI and received parity error RPE or received bit 8 RB8 Reading SPx STATUS clears all bits except TXE writing a byte to SBUFx TX clears the TXE bit 7 3 SERIAL PORT MODES The serial port has both synchronous and asynchronous operating modes for transmission and re ception This section describes the operation of each mode 7 4 intel SERIAL 1 0 SIO PORT 7 3 1 Synchronous Modes Modes 0 and 4 The 8XC196MH serial port has two synchronous modes mode
70. Moves a block of word data from one location in memory to another The Source and destination addresses are calculated using the indirect with autoin crement addressing mode A long register PTRS addresses the source and destination pointers which are stored in adjacent word registers The source pointer SRCPTR is the low word and the destination pointer DSTPTR is the high word of PTRS A word register CNTREG specifies the number of transfers The blocks of word data can be located anywhere in register RAM but should not overlap COUNT lt CNTREG LOOP SRCPTR PTRS DSTPTR lt PTRS 2 DSTPTR lt SRCPTR PTRS lt SRCPTR 2 PTRS 2 lt DSTPTR 2 COUNT lt COUNT 1 if COUNT 0 then go to LOOP end if PSW Flag Settings Z N C v VvT ST PTRS CNTREG BMOV wreg 11000001 wreg Ireg NOTE The pointers are autoincre mented during this instruction However CNTREG is not decre mented Therefore it is easy to unintentionally create a long uninterruptible operation with the BMOV instruction Use the BMOVI instruction for an interrupt ible operation A 9 8XC196MC MD MH USER S MANUAL intel Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format BMOVI INTERRUPTIBLE BLOCK MOVE Moves a PTRS CNTREG block of word data fr
71. Note 10 Note 10 P5 5 BHE WRH WK1 WK1 Note 4 Note 10 Note 10 P5 6 READY WK1 Note 5 Note 11 Note 11 P5 7 BUSWIDTH WK1 Note 6 Note 11 Note 11 P6 0 WG1 WK1 WK1 Note 13 Note 13 P6 1 wai WK1 WK1 Note 13 Note 13 P6 2 WG2 WK1 WK1 Note 13 Note 13 8XC196MC MD MH USER S MANUAL intel Table B 8 8XC196MC and MD Default Signal Conditions Continued Upon RESET Alternate During Inactive Idle Powerdown Functions RESET Active Note 14 P6 3 WG2 WK1 WK1 Note 13 Note 13 P6 4 WG3 WK1 WK1 Note 13 Note 13 P6 5 WG3 WK1 WK1 Note 13 Note 13 P6 6 PWMO WKO Note 13 Note 13 P6 7 PWM1 WKO Note 13 Note 13 P7 1 0 Note 15 EPA5 4 WK1 Note 1 Note 12 Note 12 P7 3 2 Note 15 COMP5 4 WK1 Note 12 Note 12 P7 6 4 Note 15 WK1 Note 12 Note 12 P7 7 Note 15 FREQOUT WK1 Note 12 Note 12 CLKOUT CLKOUT active CLKOUT 1070 1020 1 active LoZ0 1 EA HiZ HiZ HiZ EXTINT HiZ HiZ HiZ NMI WKO WKO WKO RESET LoZ0 HiZ HiZ HiZ Note 2 HiZ LoZ1 LoZ1 XTAL1 Osc input HiZ Osc input HiZ Osc input HiZ Osc input HiZ XTAL2 Osc output Osc output Osc output Note 7 1020 1 1020 1 1020 1 NOTES 1 These pins also control test mode entry 2 If Disable Reset Out 0 pin is LoZO
72. On the 8XC196MC and 8XC196MD port 1 is also an input only port that provides analog inputs for the A D converter On the 8XC196MH port 1 is a bidi rectional port that shares pins with the serial I O port Port 2 is a standard bidirectional I O port that provides pins for the EPA and timers Port 7 which is unique to the 8KC196MD is a standard bidirectional I O port that provides additional pins for the EPA and also provides pins for the frequency generator Ports 3 4 and 5 are memory mapped bidirectional I O ports Ports 3 and 4 serve as the external address data bus while port 5 provides bus control signals Port 6 is a standard output only port that provides pins for the pulse width modulator and waveform generator Chapter 6 I O Ports describes the I O ports in more detail 2 5 2 Serial I O SIO Port The 8XC196MH microcontroller has a two channel serial I O port that shares pins with ports 1 and 2 The 8KC196MC and 8XC196MD have no serial I O ports but have PTS modes that allow asynchronous or synchronous serial communication See Chapter 5 Standard and PTS Inter rupts for more information The serial I O SIO port is an asynchronous synchronous port that includes a universal asynchronous receiver and transmitter UART The UART has two synchro nous modes modes 0 and 4 and three asynchronous modes modes 1 2 and 3 for both trans mission and reception The asynchronous modes are full duplex meaning that they ca
73. PBUS 15 2 1 AD12 P4 4 PBUS AD11 P4 3 PBUS AD10 P4 2 PBUS 10 AD9 P4 1 PBUS 9 AD8 P4 0 PBUS 8 AD7 P3 7 PBUS 7 AD6 P3 6 PBUS 6 AD5 P3 5 PBUS 5 P3 4 PBUS 4 P3 3 PBUS 3 2 2 PBUS 2 AD1 P3 1 PBUS 1 ADO P3 0 PBUS O NMI 6 5 WG3 P6 4 WG3 P6 3 WG2 Oak WD U8XC196MC View of component as mounted on PC board P5 6 READY P5 4 ONCE EXTINT Vss XTAL1 XTAL2 P6 6 PWMO P6 7 PWM1 P2 6 COMP2 2 5 1 PACT 2 4 COMPO AINC 2 3 P2 2 EPA2 PROG 2 1 1 PALE 2 0 P0 0 ACHO P0 1 ACH1 P0 2 ACH2 P0 3 ACH3 P0 4 PMODE 0 P0 5 ACH5 PMODE 1 VREF ANGND P0 6 ACH6 PMODE 2 P0 7 ACH7 PMODE 3 P1 0 8 P1 1 ACH9 P1 2 10 P1 3 ACH11 T1DIR P6 0 WG1 P6 1 WG1 P6 2 WG2 A3103 02 Figure B 1 8XC196MC 64 lead Shrink DIP SDIP Package 8XC196MC MD MH USER S MANUAL 1 P5 7 BUSWIDTH 10 5 2 WR WRL 8 E P5 5 WRH 7E 5 3 RD 5 H P5 0 ALE ADV 2 5 6 READY e1 P5 4 ONCE 84 EXTINT 83 Vss 82 B XTAL1 81 2 80 A NC 79 78 77 b P6 6 PWMO 76 P6 7 PWM1 75 P2 6 COMP2 CPVER AD15 P4 7 PBUS 15
74. PTSCON PTSCB 1 PTS Control Bits 2 0 PTS Mode M2 1 0 1 0 0 single transfer mode BW Byte Word Transfer 0 word transfer 1 byte transfer SU Update PTSSRC 0 reload original PTS source address after each byte or word transfer 1 retain current PTS source address after each byte or word transfer 011 Update PTSDST 0 reload original PTS destination address after each byte or word transfer 1 retain current PTS destination address after each byte or word transfer Slt PTSSRC Autoincrement 0 do not increment the contents of PTSSRC after each byte or word transfer 1 increment the contents of PTSSRC after each byte or word transfer DIt PTSDST Autoincrement 0 do not increment the contents of PTSDST after each byte or word transfer 1 increment the contents of PTSDST after each byte or word transfer PTSCOUNT PTSCB 0 Consecutive Word or Byte Transfers Defines the number of words or bytes that will be transferred during the single transfer routine Each word or byte transfer is one PTS cycle Maximum value is 255 t The DU DI bits and SU SI bits are paired in single transfer mode Each pair must be set or cleared together However the two pairs DU DI and SU SI need not be equal Figure 5 16 PTS Control Block Single Transfer Mode Continued The PTSCB in Table 5 5 defines nine PTS cycles Each cycle moves a single word from locati
75. SHLB breg breg 00011001 breg breg A 32 intel INSTRUCTION SET REFERENCE Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format SHLL SHIFT DOUBLE WORD LEFT Shifts the destination double word operand to the left as many times as specified by the count operand The count may be specified either as an immediate value in the range of 0 to 15 OFH inclusive or as the content of any register 10H OFFH with a value in the range of 0 to 31 1FH inclusive The right bits of the result are filled with zeros The last bit shifted out is saved in the carry flag Temp lt COUNT do while Temp 0 C lt High order bit of DEST DEST lt DEST x 2 Temp lt Temp 1 end while PSW Flag Settings 2 V VT ST SHLL Ireg count 00001101 count Ireg or SHLL lreg breg 00001101 breg SHR LOGICAL RIGHT SHIFT WORD Shifts the destination word operand to the right as many times as specified by the count operand The count may be specified either as an immediate value in the range of 0 to 15 OFH inclusive or as the content of any register 10H OFFH with a value in the range of 0 to 31 inclusive The left bits of the result are filled with zeros The last bit shifted out is saved in the carry flag Temp lt COUNT do while Temp 0 C lt Low order bit of DEST
76. Stores the value of the SRC DEST source leftmost word operand into the ST wreg waop destination rightmost operand 110000aa mon wreg DEST lt SRC PARTEM PSW Flag Settings Z N C V VT ST STB STORE BYTE Stores the value of the source SRC DEST leftmost byte operand into the destination breg baop rightmost operand i 110001 baop bre DEST lt SRC breg PSW Flag Settings SUB SUBTRACT WORDS Subtracts the source DEST SRC 2 operands word operand from the destination word SUB wreg waop operand stores the result in the destination operand and sets the carry flag as the complement of borrow DEST lt DEST SRC PSW Flag Settings 2 V 5 011010 SUB 3 operands SUBTRACT WORDS Subtracts the first source word operand from the second stores the result in the destination operand and sets the carry flag as the complement of borrow DEST lt SRC1 SRC2 PSW Flag Settings 2 V VT ST DEST SRC1 SRC2 SUB Dwreg Swreg waop 010010aa waop Swreg Dwreg A 37 8XC196MC MD MH USER S MANUAL intel Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format SUBB SUBTRACT BYTES Subtracts the source DEST SRC 2 operands byte operand from the
77. Table 16 2 describes the options You can program the CCBs using any of the programming methods Table 16 2 Memory Protection for Normal Operating Mode Read Protect Write Protect LOC1 0 7 LOCO CCRO 6 Protection Status No protection Run time programming is permitted and the entire OTPROM array can be read Write protection only Run time programming is disabled but the entire OTPROM array can be read 1 1 Read protection Run time programming is disabled If program 0 1 execution is external only the interrupt vectors and CCBs can be read The security key is write protected Read and write protection Run time programming is disabled If 0 0 program execution is external only the interrupt vectors and CCBs can be read Clearing 6 enables write protection With write protection enabled a write attempt causes the bus controller to cycle through the write sequence but it does not enable or write data to the OTPROM This protects the entire OTPROM array from inadvertent or unauthorized pro gramming Clearing CCBO 7 enables read protection and also write protects the security key to protect it from being overwritten With read protection enabled the bus controller will not read from pro tected areas of OTPROM An attempt to load the slave program counter with an external address causes the device to reset itself Because the slave program counter can be as much as fou
78. addressing 6 14 idle powerdown reset status B 23 25 operation 6 15 6 16 overview 6 1 pin configuration 6 14 structure 6 15 Port 5 B 18 considerations 6 12 idle powerdown reset status B 23 B 25 operation 6 4 6 12 overview 6 1 pin configuration 6 12 SFRs 6 6 14 3 Port 6 B 18 configuration 6 17 idle powerdown reset status B 23 B 25 operation 6 17 output configuration register 6 18 C 62 overview 6 1 Port 7 B 19 idle powerdown reset status B 24 operation 6 4 overview 6 1 SFRs 6 6 14 3 Port x data output register C 34 Port x I O direction register C 30 Port x mode register C 31 Port x pin input register C 33 Port serial See SIO port Ports general purpose I O 2 9 unused inputs 13 2 Power and ground pins minimum hardware connections 13 5 Power consumption reducing 2 11 14 5 Power up sequence programming modes 16 14 Powerdown mode 2 11 14 5 14 10 circuitry external 14 8 14 10 disabling 14 5 Index 8 enabling 14 5 entering 14 6 exiting 14 6 with EXTINT 14 7 14 10 with RESET 14 6 with 14 6 pin status B 23 reset status B 25 Powerdown sequence programming modes 16 14 Prefetch queue 2 6 Priority encoder 5 4 Processor status word See PSW Product information ordering 1 6 PROG 16 10 16 12 B 20 Program counter See PC Program memory 4 2 Program word routine 16 22 Programming frequency generator frequency 8 3 output 8 3 Programming mod
79. and the BUSWIDTH signal has no effect CCRO 1 CCR1 2 BUSWIDTH 0 1 X fixed 8 bit data bus 0 X fixed 16 bit data bus 1 high 16 bit data bus 1 1 1 1 low 8 bit data bus CLKOUT MC MD Clock Output Output of the internal clock generator The CLKOUT frequency is 1 2 the oscillator input frequency 4 CLKOUT has 50 duty cycle 15 2 intel INTERFACING WITH EXTERNAL MEMORY Table 15 1 External Memory Interface Signals Continued Signal Name Port Pin Type Description EA External Access This input determines whether memory accesses to special purpose and program memory partitions are directed to internal or external memory See Table 4 1 on page 4 2 for address ranges of special purpose and program memory partitions These accesses are directed to internal memory if EA is held high and to external memory if EA is held low For an access to any other memory location the value of EA is irrelevant EA also controls entry into the programming modes If EA is at Vpp voltage typically 12 5 V on the rising edge of RESET the micro controller enters a programming mode NOTE Systems with EA tied inactive have idle time between external bus cycles When the address data bus is idle you can use ports 3 and 4 for I O Systems with EA tied active cannot use ports and 4 as standard 1 0 when EA is active these ports will function only as the address da
80. and write the desired pin values to the low byte If you are using port 6 for waveform generator or PWM outputs please refer to Chapter 9 Waveform Generator or Chapter 10 Pulse width Modulator for a description of the WG OUTPUT register functions 15 8 OP1 OPO M7 M6 M5 4 M3 2 M1 0 7 0 D7 D6 D5 D4 D3 D2 D1 DO mber 15 14 1 0 Output Polarity These bits select the output polarity of the port 6 pins 0 active low outputs 1 active high outputs 13 Reserved for compatibility with future devices write zero to this bit 12 8 M7 0 Mode These bits select either the peripheral function or general purpose output function of the port 6 pins Clear these bits for general purpose output 6 18 Figure 6 5 Port 6 Output Configuration WG OUTPUT Register a intel PORTS WG OUTPUT Port 6 Continued Address 1FCOH Reset State 0000H The port 6 output configuration _ OUTPUT register controls port 6 functions If you are using port 6 for general purpose outputs write COH for active high outputs or OOH for active low outputs to the high byte of WG OUTPUT and write the desired pin values to the low byte If you are using port 6 for waveform generator or PWM outputs please refer to Chapter 9 Waveform Generator or Chapter 10 Pulse width Modulator for a description of the WG OUTPUT register functions
81. areas including general and product specific subjects 4 Type the number that corresponds to the subject of interest and press Enter to list the latest files 5 the file numbers to select the files you wish to download for example 1 6 for files 1 and 6 or 3 7 for files 3 4 5 6 and 7 and press Enter The BBS displays the approx imate time required to download the files you have selected and gives you the option to download them 1 4 2 2 How to Find ApBUILDER Software and Hypertext Documents on the BBS The latest ApBUILDER files and hypertext manuals and datasheets are available first from the BBS To access the files complete these steps 1 TypeF from the BBS Main menu The BBS displays the Intel Apps Files menu 2 Type L and press Enter The BBS displays the list of areas and prompts for the area number 3 Type 25 and press Enter to select ApBUILDER Hypertext The BBS displays several options one for ApBUILDER software and the others for hypertext documents for specific product families 4 1 and press Enter to list the latest ApBUILDER files or type 2 and press Enter to list the hypertext manuals and datasheets for MCS 96 microcontrollers 5 the file numbers to select the files you wish to download for example 1 6 for files 1 and 6 or 3 7 for files 3 4 5 6 and 7 and press Enter The BBS displays the approx imate time required to download the selected files a
82. go above 4 5 volts until is at least 4 5 volts The maximum voltage must not be exceeded EA must reach programming voltage before does so The PMODE pins P0 7 4 must be in their desired states before RESET rises All voltages must be within the ranges specified in the datasheet and the oscillator must be stable before RESET rises The power supplies to EA and RESET pins must be well regulated and free of glitches and spikes Vs pins must be well grounded 16 7 2 1 Power up Sequence 1 Ow OM Hold RESET low while stabilizes Allow and EA to float during this time After and the oscillator stabilize continue to hold RESET low and apply V voltage to EA After EA stabilizes apply voltage 12 5V to the V pin Set the PMODE value to select a programming algorithm Bring the RESET pin high Complete the selected programming algorithm 16 7 2 2 Power down Sequence 1 Assert the RESET signal and hold it low throughout the powerdown sequence Remove the voltage from the V pin and allow the pin to float Remove the voltage from the EA pin and allow the pin to float Turn off the supply and allow time for it to reach 0 volts 16 14 intel PROGRAMMING THE NONVOLATILE MEMORY 16 8 SLAVE PROGRAMMING MODE Slave programming mode allows you to program and verify the entire OTPROM array including
83. intel deassert differential nonlinearity doping double word DOUBLE WORD EPA EPROM ESD feedthrough FET frequency generator GLOSSARY The act of making a signal inactive disabled The polarity high or low is defined by the signal name Active low signals are designated by a pound symbol suffix active high signals have no suffix To deassert RD is to drive it high to deassert ALE is to drive it low The difference between the actual code width and the ideal one LSB code width of the terminal based characteristic of an A D converter It provides a measure of how much the input voltage may have changed in order to produce a one count change in the conversion result Differential nonlinearity is a measure of local code width error nonlinearity is a measure of overall code transition error The process of introducing a periodic table Group III or Group V element into a Group IV element e g silicon A Group impurity e g indium or gallium results in a p type material A Group V impurity e g arsenic or antimony results in an n type material Any 32 bit unit of data An unsigned 32 bit variable with values from 0 through 2321 Event processor array An integrated peripheral that provides high speed input output capability Erasable programmable read only memory Electrostatic discharge The attenuation from an input voltage on the selected channel to the A D output after the sample
84. operand COUNT lt 0 do while MSB DEST 0 AND COUNT 31 DEST lt DEST x 2 COUNT lt COUNT 1 end_while PSW Flag Settings 0 00001111 breg Ireg A 27 8XC196MC MD MH USER S MANUAL intel Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format NOT COMPLEMENT WORD Complements the value of the word operand replaces each 1 NOT with a 0 and each 0 with a 1 DEST lt NOT DEST wreg 00000010 wreg PSW Flag Settings 0 0 NOTB COMPLEMENT BYTE Complements the value of the byte operand replaces each 1 NOTB breg with a 0 and each 0 with a 1 00010010 breg DEST lt NOT DEST PSW Flag Settings 0 0 OR LOGICAL OR WORDS ORs the source word DEST SRC operand with the destination word operand OR wreg waop and replaces the original destination operand with the result The result has a 1 in each bit 100000aa waop wreg position in which either the source or destination operand had a 1 DEST lt DEST OR SRC PSW Flag Settings 0 0 ORB LOGICAL OR BYTES ORs the source byte DEST SRC operand with the destination byte operand ORB breg baop
85. programming you can use the ROM dump mode to write the entire OTPROM array to an external memory device to verify its contents Customers typically use this low cost method to program a small number of microcontrollers after development and testing are complete can also program individual OTPROM locations without entering a programming mode With this method called run time programming your software controls the number and duration of programming pulses Customers typically use this mode to download small sections of code to the microcontroller during software development and testing 16 2 OTPROM MEMORY The The tion OTPROM contains customer specified special purpose and program memory Table 16 1 128 byte special purpose memory partition is used for interrupt vectors the chip configura bytes CCBs and the security key Several locations are reserved for testing or for use in future products Write the value 20H or FFH indicated in Table 16 1 to each reserved location The remainder of the OTPROM is available for code storage intel PROGRAMMING THE NONVOLATILE MEMORY Table 16 1 87C196Mx OTPROM Memory Map Address Range ee Hex Description 9FFF MH 2080 Program memory 5FFF MC MD 2080 Program memory Reserved each location must contain 205E 205D 2040 PTS vectors 203F 2030 Upper interrupt vectors 202F 2020 Security ke
86. scheme and timing for standard and peripheral transaction server PTS interrupts It also ex plains interrupt programming and control Chapter 6 I O Ports describes the input output ports and explains how to configure the ports for input output or special functions Chapter 7 Serial I O SIO Port describes the 8XC196MH s asynchronous synchronous serial I O SIO port and explains how to program it Chapter 8 Frequency Generator describes the 8XC196MD s frequency generator and ex plains how to configure it For additional information and application examples consult AP 483 Application Examples Using the SXC196MC MD Microcontroller order number 272282 8XC196MC MD MH USER S MANUAL intel Chapter 9 Waveform Generator describes the waveform generator and explains how to configure it For additional information and application examples consult AP 483 Application Examples Using the SXC196MC MD Microcontroller order number 272282 Chapter 10 Pulse width Modulator provides a functional overview of the pulse width modulator PWM modules describes how to program them and provides sample circuitry for converting the PWM outputs to analog signals Chapter 11 Event Processor Array EPA describes the event processor array a tim er counter based high speed input output unit It describes the timer counters and explains how to program the EPA and how to use the EPA to produce pulse
87. status and order number of each document that has been added revised or deleted dur ing the past eight weeks The daily update catalogs are numbered with the subject catalog number followed by a zero For example for the complete microcontroller and flash catalog request doc ument number 2 for the daily update to the microcontroller and flash catalog request document number 20 The following catalogs and information are available at the time of publication 1 Solutions OEM subscription form ntel GUIDE TO THIS MANUAL Microcontroller and flash catalog Development tools catalog Systems catalog Multimedia catalog Multibus and iRMX software catalog and BBS file listings Microprocessor PCI and peripheral catalog Quality and reliability and change notification catalog Dr n SL S OO iAL Intel Architecture Labs technology catalog 1 4 2 Bulletin Board System BBS The bulletin board system BBS lets you download files to your computer The application BBS has the latest ApBUILDER software hypertext manuals and datasheets software drivers firm ware upgrades application notes and utilities and quality and reliability data 916 356 3600 U S Canada Japan Asia Pacific up to 19200 baud 916 356 7209 U S Canada Japan Asia Pacific 2400 baud only 44 0 1793 496340 Europe The toll free BBS available in the U S and Canada offers lists of documents available from FaxBack a master list of files a
88. 1 intel REGISTERS CCR1 CCR1 no direct access The chip configuration 1 CCR1 register enables the watchdog timer and selects the bus timing mode Two of its bits combine with three bits of CCRO to control wait states and bus width 7 0 1 1 0 1 WDE BW1 IRC2 0 Bit Bit Function 7 6 1 To guarantee proper operation write ones to these bits 5 0 To guarantee proper operation write zero to this bit 4 1 To guarantee proper operation write one to this bit 3 WDE Watchdog Timer Enable Selects whether the watchdog timer is always enabled or enabled the first time it is cleared 0 always enabled 1 enabled first time it is cleared 2 BW1 Buswidth Control This bit along with the BWO bit CCRO 1 selects the bus width BW1 BWO 0 illegal 1 16 bit only 0 8 bit only 1 BUSWIDTH pin controlled The CCRs loaded with the contents of the chip configuration bytes CCBs after reset unless the microcontroller is entering programming modes see Entering Programming Modes page 16 13 in which case the programming chip configuration bytes PCCBs are used The CCBs reside in nonvolatile memory at addresses 2018H CCBO and 201 CCB1 8XC196MC MD MH USER S MANUAL CCR1 intel 7 CCR1 Continued no direct access The chip configuration 1 CCR1 register enables the watchdog
89. 1 PROGRAMMING METHODS You can program the OTPROM by configuring a circuit that allows the device to enter a program ming mode In programming modes the device executes an algorithm that resides in the internal test ROM Slave programming mode allows you to use an EPROM programmer as a master to program several microcontrollers the slaves The code and data to be programmed into the nonvolatile memory typically resides on a diskette The EPROM programmer transfers the code and data from the diskette to its memory then manipulates the slave s pins to define the addresses to be programmed and the contents to be written to those addresses Using this 16 1 8XC You 196MC MD MH USER S MANUAL intel mode you can program and verify single or multiple words in the OTPROM This mode allows you to read the signature word and programming voltages and to program the PCCBs and unerasable PROM UPROM bits Programming vendors and Intel distributors typically use this mode to program a large number of microcontrollers with a customer s code and data Auto programming mode enables the microcontroller to act as a master to program itself with code and data that reside in an external memory device Using this mode you can program the entire OTPROM array except the UPROM bits and PCCBs For the 8XC196MH PCCB and UPROM modes allow you to program those locations For the 8XC196MC and 8XC196MD only slave mode allows you to program them After
90. 1 error interrupts are associated with the serial port interrupt SPI Setting INT MASK1 4 enables SPI 2 OVRTM2 Timer 2 Overflow Underflow Setting this bit enables the timer 2 overflow underflow interrupt The timer 2 and timer 1 overflow underflow interrupts are associated with the overflow underflow timer interrupt OVRTM Setting INT MASK 0 enables OVRTM Figure 5 9 Peripheral Interrupt Mask PI MASK Register 5 17 8XC196MC MD MH USER S MANUAL intel PI MASK Continued Address Reset State 1FBCH AAH The peripheral interrupt mask MASK register enables or disables masks interrupt requests associated with the peripheral interrupt the serial port interrupt SPI and the overflow underflow timer interrupt OVRTM 7 0 8XC196MC WG OVRTM2 OVRTM1 7 0 8XC196MD 5 WG OVRTM2 OVRTM1 7 0 8XC196MH SP1 SPO OVRTM2 OVRTM1 BR Bit Function Number Mnemonic 0 OVRTM1 Timer 1 Overflow Underflow Setting this bit enables the timer 1 overflow underflow interrupt The timer 1 and timer 2 overflow underflow interrupts are associated with the overflow underflow timer interrupt OVRTM Setting INT MASK 0 enables OVRTM Figure 5 9 Peripheral Interrupt Mask MASK Register Continued 5 5 1 Modifying Interrupt Priorities Your software can mod
91. 1 on page 4 2 for address information 5 5 PROGRAMMING THE INTERRUPTS The PTS select register PTSSEL selects either PTS service or a standard software interrupt ser vice routine for each of the maskable interrupt requests see Figure 5 6 The bits in the interrupt mask registers INT MASK and INT MASKI enable or disable mask individual interrupts see Figures 5 7 and 5 8 For the multiplexed interrupt sources bits in the PI MASK register Figure 5 9 on page 5 17 enable or disable mask the individual interrupt sources With the ex ception of the nonmaskable interrupt NMI bit INT MASKI 7 setting a bit enables the corre sponding interrupt source and clearing a bit disables the source To disable any interrupt clear its mask bit To enable an interrupt for standard interrupt service set its mask bit and clear its PTS select bit To enable an interrupt for PTS service set both the mask bit and the PTS select bit 5 12 intel STANDARD AND PTS INTERRUPTS When you assign an interrupt to the PTS you must set up a PTS control block PTSCB for each interrupt source see Initializing the PTS Control Blocks on page 5 24 and use the EPTS in struction to globally enable the PTS When you assign an interrupt to a standard software service routine use the EI enable interrupts instruction to globally enable interrupt servicing NOTE The DI disable interrupts instruction does not disable PTS service However it does disabl
92. 11 A 18 A 19 A 20 A 21 A 31 Cascading timers 11 7 CCB fetch and BHE 6 13 and 5 5 6 13 and 5 6 6 13 and READY 6 13 CCBs 4 3 13 8 security lock bits 16 29 16 30 CCBs See also chip configuration bytes CCRO 14 2 CCRs 13 8 14 5 security lock bits 16 17 CCRs See also chip configuration registers Chip configuration and bus contention 15 11 and reset 15 6 bytes 15 5 chip configuration register 0 15 7 C 11 chip configuration register 1 15 9 C 13 registers 15 5 Clear defined 1 3 CLKOUT 14 1 B 15 and internal timing 2 7 and interrupts 5 6 and RESET 13 8 idle powerdown reset status B 24 reset status 6 7 intel Clock external 13 7 generator 2 7 13 7 13 8 internal and idle mode 14 4 14 5 phases internal 2 8 CLR instruction A 2 A 10 A 41 A 47 A 52 CLRB instruction A 2 A 11 A 41 A 47 A 52 CLRC instruction A 3 A 11 A 46 A 51 A 57 CLRVT instruction A 3 A 11 A 46 A 51 A 57 CMP instruction A 3 A 11 A 43 A 47 A 52 CMPB instruction A 3 A 11 A 44 A 47 A 52 CMPL instruction 2 A 12 A 45 47 52 Code execution 2 5 2 6 COMPO TIME C 68 CON C 68 TIME C 68 COMPS 0 11 3 B 15 CompuServe forums 1 10 Conditional jump instructions A 5 Configuring external memory pins 15 5 CPU 2 4 CPVER 16 12 B 15 Customer service 1 8 D D A converter 10 10 Data instructions A 49 A 55 Data types 3 1 3 4 addressing restrictions
93. 11 4 11 5 11 6 12 1 12 2 13 1 13 2 13 3 14 1 14 2 15 1 15 2 15 3 15 4 15 5 15 6 15 7 15 8 15 9 TABLES Page Control Register Values for Each 6 11 Port Configuration 6 11 Port Pin States After Reset and After Example Code Execultion 6 12 Ports 3 and 4 Pins iie Re 6 14 Ports and 4 Control and Status 6 14 Logic Table for Ports and 4 as Open drain l O 6 16 Standard Output only Port eme eene enne 6 17 Output only Port Control Register 244 00 eene enne 6 17 SerialPort Sigrials aay ae 7 2 Serial Port Control and Status 7 2 BAUD Values When Using XTAL1 at 16 2 7 14 Frequency Generator Signal 9 2 Frequency Generator Control and Status Registers o Waveform Generator 9 3 Waveform Generator Control and Status 9 3 Operation in Center aligned and Edge aligned 9 8 Register Updates oi eite dete reri perdi A ae 9 8 Output ContiGuration i e Rec Ser R
94. 12 17 8XC196MC MD MH USER S MANUAL intel 7 IDEAL FULL SCALE CODE TRANSITION 6 4 IDEAL STRAIGHT LINE TRANSFER FUNCTION ACTUAL FULL SCALE CODE TRANSITION di DIFFERENTIAL NON LINEARITY TERMINAL BASED POSITIVE CHARACTERISTIC corrected for zero offset IDEAL and full scale error 5 4 CODE WIDTH ACTUAL S CHARACTERISTIC 79 8 34 m o DIFFERENTIAL NON LINEARITY NEGATIVE IDEAL CODE WIDTH 1 2 1 2 3 4 5 6 61 2 7 8 INPUT VOLTAGE LSBs 0085 01 Figure 12 11 Terminal based A D Conversion Characteristic 12 18 intel 13 Minimum Hardware Considerations intel CHAPTER 13 MINIMUM HARDWARE CONSIDERATIONS The 8XC196MC MD and MH have several basic requirements for operation within a system This chapter describes options for providing the basic requirements and discusses other hardware considerations 13 1 MINIMUM CONNECTIONS Table 13 1 lists the signals that are required for the device to function and Figure 13 1 shows the connections for a minimum configuration Table 13 1 Minimum Required Signals Signal Name ANGND GND Analog Ground ANGND must be connected for A D converter and port 0 operation also port 1 on the 8XC196MC and MD ANGND and Vss should be nominally at the same potential RESET Reset A level sensitive reset input to and open drain system reset output from the micro controller Either a falling edge on RESET or a
95. 3 1 converting between 3 4 defined 3 1 iC 96 3 1 PLM 96 3 1 signed and unsigned 3 1 3 4 values permitted 3 1 Datasheets online 1 10 ordering 1 7 Deassert defined 1 3 DEC instruction A 2 A 12 A 41 A 47 A 52 DECB instruction 2 A 12 41 A 47 A 52 DED bit 16 6 16 7 16 30 DEI bit 16 6 16 7 16 17 Design considerations waveform generator 9 19 9 20 Device minimum hardware configuration 13 1 INDEX pin reset status B 23 B 25 programming 16 1 16 33 reset 13 8 13 9 13 10 13 11 13 12 DI instruction A 3 A 12 A 46 A 51 A 57 Digital to analog converter 10 10 DIR bit 7 2 7 6 Direct addressing 3 6 3 9 DIV instruction A 13 A 46 A 48 A 53 DIVB instruction A 13 A 46 A 48 A 53 DIVU instruction A 3 A 13 A 43 A 48 A 53 DIVUB instruction A 3 A 14 A 44 A 48 A 53 DJNZ instruction A 2 A 5 A 14 A 45 A 50 A 56 DJNZW instruction A 2 A 5 A 14 A 45 A 50 A 56 Documents related 1 5 1 8 DOUBLE WORD defined 3 3 DPTS instruction A 3 A 15 A 45 A 51 A 57 Dump word routine 16 24 E EA 16 13 B 15 and 5 0 6 13 and 5 3 6 13 and programming modes 16 14 idle powerdown reset status B 24 B 25 EE opcode and unimplemented opcode interrupt A 3 A 46 EI instruction 5 13 A 3 A 15 46 A 51 57 EPA 2 10 11 1 11 24 and PTS 11 12 block diagram 11 2 capture data overruns 11 21 capture compare channels programming 11 18 choosing capture or compare mode
96. 3 6 3 2 2 Immediate Addressing essen OO 3 2 3 Indirect Addressilig 3 6 3 2 3 1 Indirect Addressing with Autoincrement 3 7 3 2 8 2 Indirect Addressing with the Stack Pointer 2 3 7 3 2 4 Indexed Addressing eo deer sh dt Rede ed ede 3 7 3 2 4 1 Short indexed 3 7 3 2 4 2 Long indexed Addressing 3 8 3 2 4 3 Zero indexed Addressing sese nnne 3 8 3 3 ASSEMBLY LANGUAGE ADDRESSING MODE SELECTIONS ees 3 9 3 8 1 Direct Addressing rere dro eei dese eee 3 9 3 3 2 Indexed Addressing eco a neta 3 9 3 4 SOFTWARE STANDARDS AND emen 3 9 3 4 1 Using Registers cete ee ati peciit ced 3 4 2 Addressing 32 bit Operands esee 0710 3 4 3 Linking aes ee pe pt e e nag n ites ovens 3 10 3 5 SOFTWARE PROTECTION FEATURES AND GUIDELINES 3 11 CHAPTER 4 MEMORY PARTITIONS 4 1 MEMORY PARTITIONS nee eh REEL Ye eo RE e EE ea eoe ara 4 1 4 1 1 External Devices Memory or sse eme emen 4 1 4 1 2 Program and Special purpose Memory 1 sese emm 4 1 4 1 3 Program Memory rds dep au
97. 4 ONCE EXTINT Ves XTAL1 XTAL2 P6 6 PWMO P2 7 SCLK1 BCLK1 P2 6 COMP2 CPVER P2 5 COMP1 PACT P2 4 COMPO AINC P2 3 COMP3 2 2 EPA1 PROG P2 1 SCLKO BCLKO PALE 2 0 PVER P0 0 ACHO 1 ACH1 2 2 P0 3 P0 4 PMODE O P0 5 ACH5 PMODE 1 VREF ANGND P0 6 ACH6 T1CLK PMODE 2 7 ACH7 T1DIR PMODE 3 P1 0 TXDO P1 1 RXDO P1 2 TXD1 1 3 RXD1 P6 0 WG1 P6 1 WG1 P6 2 WG2 A2572 02 Figure B 6 8XC196MH 64 lead Shrink DIP SDIP Package intel SIGNAL DESCRIPTIONS 1 P5 7 BUSWIDTH 10 B P5 2 WR WRL 8 E31 P5 5 BHE WRH 7 P5 3 RD 5 5 0 ALE ADV 2 P5 6 READY 1 P5 4 ONCE 84 EXTINT 83 Vss 82 EB XTAL1 81 EP XTAL2 80 79b NC 78 77 b P6 6 PWMO 76 F P6 7 PWM1 75 8 P2 6 COMP2 CPVER 2 5 COMP1 PACT P2 4 COMPO AINC 015 4 7 PBUS 15 12 014 P4 6 PBUS 14 13 Voc NC 013 P4 5 PBUS 13 NC NC P2 7 SCLK1 BCLK1 AD12 P4 4 PBUS 12 P2 3 COMP3 AD11 P4 3 PBUS 11 E 18 P2 2 EPA1 PROG AD10 P4 2 PBUS 10 E 19 NC 9 P4 1 PBUS 9 20 N8XC196MH NC P4 0 PBUS 8 2 21 P2 1 SCLKO BCLKO PALE NC 5 22 P2 0 PVER NC amp 23 NC 07 P3 7 PBUS 7 24 View of component as 0 0 ACHO AD6 P3 6 PBUS 6 25 mounted
98. 5 3 Flow Diagram for the OVRTM Interrupt 5 8 intel STANDARD AND PTS INTERRUPTS 5 3 4 End of PTS Interrupts When the PTSCOUNT register decrements to zero at the end of a single transfer block transfer A D scan or serial I O routine hardware clears the corresponding bit in the PTSSEL register Figure 5 6 on page 5 14 which disables PTS service for that interrupt It also sets the corre sponding PTSSRV bit requesting an end of PTS interrupt An end of PTS interrupt has the same priority as a corresponding standard interrupt The interrupt controller processes it with an inter rupt service routine that is stored in the memory location pointed to by the standard interrupt vec tor For example the PTS services the EPAO interrupt if PTSSEL 2 is set The interrupt vectors through 2044H but the corresponding end of PTS interrupt vectors through 2004H the standard EPAO interrupt vector When the end of PTS interrupt vectors to the interrupt service routine hardware clears the PTSSRV bit The end of PTS interrupt service routine should reinitialize the PTSCB if required and set the appropriate PTSSEL bit to re enable PTS interrupt service 5 4 INTERRUPT LATENCY Interrupt latency is the total delay between the time that the interrupt request is generated not acknowledged and the time that the device begins executing either the standard interrupt service routine or the PTS interrupt service routine A delay occurs between the time that t
99. 8 jump taken JE 4 jump not taken 8 jump taken JGE 4 jump not taken 8 jump taken JGT 4 jump not taken 8 jump taken JH 4 jump not taken 8 jump taken JLE 4 jump not taken 8 jump taken JLT 4 jump not taken 8 jump taken JNC 4 jump not taken 8 jump taken JNE 4 jump not taken 8 jump taken JNH 4 jump not taken 8 jump taken JNST 4 jump not taken 8 jump taken JNV 4 jump not taken 8 jump taken JNVT 4 jump not taken 8 jump taken JST 4 jump not taken 8 jump taken JV 4 jump not taken 8 jump taken JVT 4 jump not taken 8 jump taken NOTE The column entitled Reg peripheral SFRs The column entitled Mem lists the instruction execution times for accesses to the register file or lists the instruction execution times for accesses to all memory mapped registers I O or memory See Table 4 1 on page 4 2 for address information A 56 intel INSTRUCTION SET REFERENCE Table A 9 Instruction Execution Times in State Times Continued Shift Mnemonic Direct NORML 8 1 per shift 9 for 0 shift SHL 6 1 per shift 7 for 0 shift SHLB 6 1 per shift 7 for 0 shift SHLL 7 1 per shift 8 for 0 shift SHR 6 1 per shift 7 for 0 shift SHRA 6 1 per shift 7 for 0 shift SHRAB 6 1 per shift 7 for 0 shift SHRAL 7 1 per shift 8 for 0 shift SHRB 6 1
100. 9 Slave Programming Mode Memory Map Description Address Comments OTPROM MH 2000 9FFFH OTPROM Cells MC MD 2000 5FFFH DED 0758H UPROM Cell 0718H UPROM Cell PCCB 0218H Test EPROM Programming voltages see Table 16 8 on page 16 16 0072H 0073H Read Only Signature word 0070H Read Only These bits program the UPROM cells Once these bits are programmed they cannot be erased and dynamic failure analysis of the device is impossible 16 8 3 Operating Environment The chip configuration registers CCRs define the system environment Since the programming environment is not necessarily the same as the application environment the device provides a means for specifying different configurations Specify your application environment in the chip configuration bytes CCBs located in the OTPROM Specify your programming environment in the programming chip configuration bytes PCCBs located in the test ROM Figure 16 6 shows an abbreviated description of the CCRs with the default PCCB environment settings The reset sequence loads the CCRs from the CCBs for normal operation and from the PCCBs when entering programming modes You can program the CCBs using any of the pro gramming methods but only slave mode allows you to program the PCCBs Chapter 15 Inter facing with External Memory describes the system configuration options and Controlling Access to Internal Memory on page 16 3 des
101. 9 3 WAVEFORM GENERATOR OPERATION This section describes the major components of the waveform generator the timebase generator the phase driver channels and the control and protection circuitry It also explains how the buff ered registers are updated and describes the similarities and differences between the center aligned and edge aligned operating modes Finally it describes the two types of interrupt requests that the waveform generator can generate and explains how to enable the interrupts 9 3 1 Timebase Generator The timebase generator establishes the carrier period of the PWM outputs You specify this period by writing a value to the reload register RELOAD This value is loaded into the counter register WG_COUNTER when the system is initialized and periodically depending on the op erating mode thereafter You can read the counter register to determine the current counter value and you can write to the reload register to change the reload value at any time The 16 bit timebase counter is clocked every state time The control register CONTROL enables and disables the counter controls the counting mode and reflects the count direction When the counter is enabled it continuously counts between 0001H and the reload value Writing 0000H to the reload register or clearing the enable bit in the control register stops the counter 9 4 intel WAVEFORM GENERATOR 9 3 2 Phase Driver Channels The phase driver channels
102. A 34 intel INSTRUCTION SET REFERENCE Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format SHRAL ARITHMETIC RIGHT SHIFT DOUBLE WORD Shifts the destination double word SHRAL count to the right as many times as specified by the count operand The count 00001110 count Ireg may be specified either as an immediate or value in the range of 0 to 15 OFH inclusive SHRAL breg or as the content of any register 10H with a value in the range of 0 to 31 00001110 breg Ireg inclusive If the original high order bit value was 0 zeros shifted in If the NOTES This instruction clears the value was 1 ones are shifted in sticky bit flag at the beginning Temp lt COUNT of the instruction If at any time do while Temp 0 during the shift a 1 is shifted lt Low order bit of DEST into the carry flag and another DEST lt DEST 2 shift cycle occurs the instruc Temp lt Temp 1 tion sets the sticky bit flag end_while In this operation DEST 2 rep PSW Flag Settings resents signed division Z N C V VI ST 0 v SHRB LOGICAL RIGHT SHIFT BYTE Shifts the destination byte operand to the right as many SHRB breg count times as specified by the count operand The count may be specified either as an immediate value in the range of 0 to 15 OFH
103. A 47 A 52 SUBCB instruction 3 A 38 A 44 A 47 A 52 Index 12 Subroutines linking 3 10 nested 4 10 Symbols signal status B 23 System bus timing 15 32 T TICLK 11 2 B 21 TICONTROL C 70 TIDIR 11 2 B 21 TIRELOAD C 70 T2CONTROL C 70 Technical support 1 11 Terminology 1 3 TIJMP instruction A 2 A 39 A 45 A 49 A 55 Timer 1 control register 11 16 C 53 Timer 1 reload register C 54 Timer 2 control register 11 17 C 55 Timer x register C 56 Timer watchdog See watchdog timer Timer counters 2 10 and PWM 11 13 11 14 cascading 11 7 count rate 11 6 programming 11 15 quadrature clocking 11 7 resolution 11 6 signals 11 2 See also EPA 70 2 C 70 Timing dump word routine 16 24 instruction execution 52 53 internal 2 7 2 8 interrupt latency 5 9 5 12 5 30 program word routine 16 22 PTS cycles 5 12 SIO port mode 0 7 6 7 7 SIO port mode 1 7 8 SIO port mode 2 7 9 SIO port mode 3 7 9 slave programming routines 16 22 16 24 Timing definitions BUSWIDTH 15 13 READY 15 20 intel Timing diagrams 16 bit data bus 15 15 8 bit data bus 15 17 BUSWIDTH 15 12 READY 15 19 system bus timing 15 32 Timing requirements BUSWIDTH 15 13 READY 15 18 TRAP instruction 5 6 A 2 A 39 A 46 A 50 A 55 A 56 TRAP interrupt 5 4 TXD B 21 and SIO port mode 0 7 5 U UART 2 9 7 1 Unerasable PROM register 16 7 C 57 Unimplemented opcode interru
104. AND REMOVING POWER When power is first applied to the device RESET must remain continuously low for at least one state time after the power supply is within tolerance and the oscillator clock has stabilized oth erwise operation might be unpredictable Similarly when powering down a system RESET should be brought low before is removed otherwise an inadvertent write to an external lo cation might occur Carefully evaluate the possible effect of power up and power down sequenc es on a system 13 3 NOISE PROTECTION TIPS The fast rise and fall times of high speed CMOS logic often produce noise spikes on the power supply lines and outputs To minimize noise it is important to follow good design and board lay out techniques We recommend liberal use of decoupling capacitors and transient absorbers Add 0 01 uF bypass capacitors between and each Vg pin and a 1 0 uF capacitor between and ANGND to reduce noise Figure 13 2 Place the capacitors as close to the device as possible Use the shortest possible path to connect V lines to ground and each other VREF 8XC196 Device Analog 5 7 7 Ground Digital Plane Ground Plane 5V Return Power Source 1 Use 0 01 bypass capacitors for maximum decoupling A0272 02 Figure 13 2 Power and Return Connections 13 4 intel MINIMUM HARDWARE CONSIDERATIONS If the A D converter will be used connect V to a separate reference supply
105. ANGND pin relative to V may cause the analog circuitry to latch up This is an additional reason to follow careful ground ing practice The analog reference voltage Vg is the positive supply to which all A D conversions are com pared It is also the supply to port 0 and port 1 for the MC and MD if the A D converter is not being used If high accuracy is not required can be tied to If accuracy is important must be very stable way to accomplish this is through the use of a precision power sup ply ora separate voltage regulator usually an IC These devices must be referenced to ANGND not to to ensure that tracks ANGND and not Veg 12 6 1 4 Using Mixed Analog and Digital Inputs Port 0 and port 1 for the MC and MD may be used for both analog and digital input signals at the same time However reading the port may inject some noise into the analog circuitry For this reason make certain that an analog conversion is not in progress when the port is read Refer to Chapter 6 I O Ports for information about using the port as digital inputs 12 6 2 Understanding A D Conversion Errors The conversion result is the ratio of the input voltage to the reference voltage Viy ANGND Viy ANGND RESULT 8 bit 255 ANGND RESULT 10 bit 1023 x y cr ANGND This ratio produces a stair stepped transfer function when the output code is plotted versus input voltage The resulting digital co
106. Action Taken When a Valid Edge Occurs z amp EPAx_TIME 0 empty Edge is captured and event time is loaded into the capture buffer and EPAx_TIME register 0 full New data is ignored no capture EPA interrupt or transfer occurs 1 empty Edge is captured and event time is loaded into the capture buffer and EPAx_TIME register 1 full Old data is overwritten in the capture buffer An input capture event does not set the interrupt pending bit until the captured time value actually moves from the capture buffer into the EPAx_TIME register If the buffer contains data and the PTS is used to service the interrupts then two PTS interrupts occur almost back to back that is with one instruction executed between the interrupts 11 4 1 1 EPA Overruns Overruns occur when an EPA input transitions at a rate that cannot be handled by the EPA inter rupt service routine If no overrun handling strategy is in place and if the following three condi tions exist a situation may occur where both the capture buffer and the EPAx_TIME register contain data and no EPA interrupt is generated an input signal with a frequency high enough to cause overruns is present on an enabled EPA pin and the overwrite bit is set EPAx_CON 0 1 old data is overwritten on overrun and the EPAx_TIME register is read at the exact instant that the EPA recognizes the captured edge as valid The input frequency at which this occurs depends on the
107. Address 1FB8H 8XC196MD Reset State 00H The frequency FREQ_GEN register holds a programmed value that specifies the output frequency This value is reloaded into the down counter each time the counter reaches 0 7 0 8XC196MD Output Frequency Bit _ Number Function 7 0 Output Frequency Use the following formula to calculate the FREQ value for the desired output frequency and write this value to the frequency register F 16 x FREQ_OUT where FREQ 8 bit value to load into FREQ GEN register FxTAL1 input frequency on XTAL1 pin in MHz FREQ OUT Output frequency on FREQOUT pin in MHz C 23 8XC196MC MD MH USER S MANUAL intel GEN CON GEN CON Address 1FAOH 8XC196MH Reset State 00H The GEN register controls whether an internal reset asserts the external RESET signal and indicates the source of the most recent reset 7 0 8XC196MH RSTS DRO Bit Bit Number Mnemonic Function 7 RSTS Reset source read only status bit 0 external reset RESET pin asserted 1 internal reset watchdog overflow illegal IDLPD key or RST instruction 6 1 Reserved for compatibility with future devices write zeros to these bits DRO Disable RESET out 0 an internal reset asserts the RESET 1 an internal reset has no effect on the RESET pin the RESET pin is pulled high inactive
108. An individual source will generate the interrupt only if software enables both the in terrupt source and multiplexed interrupt To enable the multiplexed interrupt set the appropriate bit in the interrupt mask register Figures 5 7 and 5 8 To enable an interrupt source set the ap propriate bit in the PI register Figure 5 9 on page 5 17 Figure 5 3 shows the flow for the timer interrupt NOTE Although the PI interrupt on the 8 196 has a single source the waveform generator software must still enable both the source interrupt WG in the PI PEND register and the PI interrupt in the INT MASK register 8XC196MC MD MH USER S MANUAL intel The interrupt service routine should read the PI PEND Figure 5 12 on page 5 23 register to de termine the source of the interrupt Before executing the return instruction the interrupt service routine should check to see if any of the other interrupt sources are pending Generally PTS in terrupt service is not useful for multiplexed interrupts because the PTS cannot readily determine the interrupt source Timer x Overflows Set OVRTMx bit in Pl PEND Is OVRTMx bit set in PI MASK OVRTM bit is not set in INT PEND Set OVRTM bit INT PEND Is OVRTM bit set in INT MASK OVRTM interrupt is not generated Generate OVRTM interrupt Read PEND to see which timer overflowed A3254 01 Figure
109. BEE rseg at 30h rism dsb 13 reserved for RISM rseg at 40h 8 6 intel FREQUENCY GENERATOR temp dsw 1 templ dsw 1 temp2 dsw 1 buf_start dsw 1 buf_cnt dsb 1 bit cnt dsb 1 flag dsb 1 bit 0 zero being sent bit 1 one being sent bit 5 get next bit bit 6 get next byte bit 7 buffer send in progress xmit buf dsb buf size block of data to send shift reg dsb 3L age te aeg cac Rae MAIN PROGRAM UR OR ALAA RA AAR RAL Define the program location and set up the interrupts and stack OK AACA cseg at 0e000h RISM user space start di set up interrupts dpts int pendl 410000000b orb int mask1 400000010b unmask compare3 ld sp 02005 up stack SECO ue dete Initialize pin P7 7 FREQOUT for I O and set the pin low ldb wsr 7EH move SFR s into window p7 reg 01111111 P7 7 low p7 dir w 401111111b P7 7 comp output p7 mode 011111110 7 7 I O ldb wsr zero reg LUCES RR AA This section fills the data buffer with a fill character An application would typically place a block of data here ld temp xmit_buf initialize buffer data ldb templ fill_char ldb temp2 buf_size fill stb templ temp djnz temp2 fill
110. CCRO 2 0 selects WRH B 14 intel SIGNAL DESCRIPTIONS Table B 6 Signal Descriptions Continued Name Type Description BUSWIDTH Bus Width Two chip configuration register bits CCRO 1 and CCR1 2 along with the BUSWIDTH pin control the data bus width When both CCR bits are set the BUSWIDTH signal selects the external data bus width When only one CCR bit is set the bus width is fixed at either 16 or 8 bits and the BUSWIDTH signal has no effect CCRO 1 CCR1 2 BUSWIDTH 0 1 X fixed 8 bit data bus 1 0 X fixed 16 bit data bus 1 1 high 16 bit data bus 1 1 low 8 bit data bus BUSWIDTH is multiplexed with P5 7 CLKOUT Clock Output MC MD Output of the internal clock generator The CLKOUT frequency is 1 2 the oscillator input frequency Fy7 1 CLKOUT has a 50 duty cycle CLKOUT is not implemented on the 8XC196MH COMPS 0 MC Event Processor Array EPA Compare Pins MH These signals are the output of the EPA compare only channels These pins COMP5 0 are multiplexed with other signals and may be configured as standard I O MD 5 0 are multiplexed as follows COMP0 P2 4 AINC COMP 1 P2 5 PACT COMP2 P2 6 CPVER COMP3 P2 7 MC MD COMP3 P2 3 COMP4 P7 2 and COMP5 P7 3 COMP4 and 5 are not implemented on the 8 196 and MH CPVER Cumulative Program Verification During slave programming a high signal indicates that all locations programmed correctly while a low si
111. Continued Signal ee Name Type Description XTAL1 Input Crystal Resonator or External Clock Input Input to the on chip oscillator and the internal clock generators The internal clock generators provide the peripheral clocks CPU clock and CLKOUT signal MC MD only When using an external clock or crystal instead of the on chip oscillator connect the clock input to XTAL1 The external clock signal must meet the speci fication for XTAL1 see datasheet XTAL2 Inverted Output for the Crystal Resonator Output of the on chip oscillator inverter Leave XTAL2 floating when the design uses an external clock source instead of the on chip oscillator 13 1 1 Unused Inputs For predictable performance it is important to tie unused inputs to or Otherwise they can float to a mid voltage level and draw excessive current Unused interrupt inputs may generate spurious interrupts if left unconnected 13 1 2 I O Port Pin Connections Tie unused input only port inputs to as shown in Figure 13 1 Chapter 6 I O Ports contains information about initializing and configuring the ports Table 13 2 lists the sections with page numbers that contain the information for each port Table 13 2 I O Port Configuration Guide Port Where to Find Configuration Information Port 0 Standard Input only Port Considerations on page 6 4 Port 1 Standard Input only Port Considerations on
112. Conversion Errors 12 13 CHAPTER 13 MINIMUM HARDWARE CONSIDERATIONS 131 MINIMUM 13 1 131 1 Unused Inputs n eene reet dene 13 2 13 1 2 gt l O Port Pin Connections een tie 13 2 13 2 APPLYING AND REMOVING 19 4 13 8 NOISE PROTECTION TIPS eene 13 4 13 4 THE ON CHIP OSCILLATOR CIRCUITRY essem een 13 5 13 5 USING AN EXTERNAL CLOCK SOURGE eee emen 19 7 13 6 RESETTING THE 13 8 13 6 1 Generating an External 13 10 13 6 2 Issuing the Reset RST Instruction 19 12 13 6 3 Issuing an Illegal IDLPD Key Operand 13 12 13 6 4 Generating Wait States emmemmeeeld 12 13 6 5 Enabling the Watchdog 13 12 CHAPTER 14 SPECIAL OPERATING MODES 141 SPECIAL OPERATING MODE SIGNALS AND 14 1 14 2 REDUCING POWER 14 3 1439 IDBE MODE nter Bie ape ER ee eet 14 4 14 8 POWERDOWN MODE 14 5 14 4 1 Enabling and Disabling Powerdown Mode seem 14 5 14 4 2 Entering Powerdown Mode 2 14 6 14 4 8 Exiting Powerdown Mode
113. Data Bus Ports 3 and 4 Structure EE 6 4 Output only ni ere rere 6 18 6 5 Port 6 Output Configuration WG_OUTPUT 6 18 7 1 SIO Block Diagram erii tdt 7 1 7 2 Typical Shift Register Circuit for 0 7 5 7 3 Mode 0 Timing 7 6 7 4 Serial Port Frames for 1 7 8 xii intel CONTENTS Figure 7 5 7 7 7 8 8 2 8 3 8 4 8 5 9 1 9 2 9 3 9 5 9 6 9 8 9 9 9 10 9 11 9 12 9 13 9 14 10 1 10 2 10 3 10 4 10 5 10 6 10 7 10 8 11 1 11 2 11 3 11 4 11 5 11 6 11 7 11 8 11 9 11 10 11 11 12 1 12 2 FIGURES Page Serial Port Frames in Mode 2 eme 79 Serial Port Control SPx CON 7 10 Serial Port x Baud Rate SPx BAUD 7 12 Serial Port Status SPx STATUS Register 7 15 Frequency Generator Block Diagram essem 8 1 Frequency FREQ GEN 8 3 Frequency Generator Count FREQ CNT 8 4 Infrared Remote Control Application Block 8 5
114. Data Encoding Example rhet tee te dae ew tee re lh Waveform Generator Block Diagram eee Dead time Generator Protection Circuit oor cp cente rtt e e ie Ent Sh aban d eee Pe Dre deed Center aligned Modes Counter Center aligned Modes Output Edge aligned Modes Counter Operation Edge aligned Modes Output Operation WG Output Configuration OUTPUT Register Waveform Generator Protection WG PROTECT 9 15 Waveform Generator Reload WG RELOAD 9 16 Phase Compare COMP x 9 17 Waveform Generator Control WG CONTROL Register sees 9 18 Waveform Generator Counter WG_COUNTER Register 0 19 Effect of Dead Time on Duty 9 20 PWM Block Diagram pce eerte teen e ERA EE Re RH e En 10 2 PWM Ou tp t Waveforms ed rm hne hed teed ane A 10 4 PWM Period PERIOD Register seem 10 6 PWM Control PWMx CONTROL 10 7 PWM Count PWM COUNT Register emm eme 10 8 Waveform Generator Output Configuration WG OUTPUT Reg
115. Each bit of Px_DIR controls the direction of the corresponding pin P7_DIR MD 1FD3H 0 complementary output output only 1 input or open drain output input output or bidirectional Open drain outputs require external pull ups P1_MODE MH 1F99H Port x Mode P2_MODE 1FDOH Each bit of Px_MODE controls whether the corresponding pin Oe functions as standard I O port pin or as special function signal P7 MODE MD 1FD1H Anou VO port pi pecial function signal 0 standard I O port pin 1 special function signal P1_PIN MH 1F9FH Port x Input EE DIN EET Each bit of Px PIN reflects the current state of the corresponding in regardless of the pin configuration 7 MD 1FD7H dc peice iod P1 REG MH 1F9DH Port x Data Output E MEG eed For an input set the corresponding Px REG bit P7 REG MD 1FD5H For an output write the data to be driven out by each pin to the corresponding bit of Px REG When a is configured as standard Px_MODE y 0 the result of a CPU write to REG is immediately visible on the pin When a pin is configured as a special function signal Px MODE y 1 the associated on chip peripheral or off chip component controls the pin The CPU can still write to Px REG but the pin is unaffected until it is switched back to its standard function This feature allows software to configure a pin as standard clear MODE y initialize over
116. Figure 6 1 Standard Input only Port Structure 6 3 8XC196MC MD MH USER S MANUAL intel 6 2 2 Standard Input only Port Considerations Port 0 and 1 pins are unique in that they may individually be used as digital inputs and analog inputs at the same time However reading the port induces noise into the A D converter decreas ing the accuracy of any conversion in progress We strongly recommend that you not read the port while an A D conversion is in progress To reduce noise the PO PIN or P1 PIN register is clocked only when the port is read These port pins are powered by the analog reference voltage and analog ground ANGND pins If the port pins are to function as either analog or digital inputs the and ANGND pins must provide power If the voltage applied to the analog input exceeds ANGND by more than 0 5 volts current will be driven through Q1 or Q2 into the reference circuitry decreasing the accuracy of all analog conversions The port pin is sampled one state time before the read buffer is enabled Sampling occurs during phase 1 while CLKOUT is low and resolves the value of the pin before it is presented to the internal bus To ensure that the value is recognized it must be valid 45 ns before the rising edge of CLKOUT and must remain valid until CLKOUT falls If the pin value changes during the sam ple time the new value may or may not be recorded As a digital input a pin acts as a high impe
117. GEN_CON The following events will reset the device see Figure 13 9 anexternal device pulls the RESET pin low the CPU issues the reset RST instruction the CPU issues an idle powerdown IDLPD instruction with an illegal key operand the watchdog timer WDT overflows The following paragraphs describe each of these reset methods in more detail 13 9 8XC196MC MD MH USER S MANUAL intel Internal External Reset State Internal Machine Reset Signal RESET 0 MH Only RST Instruction WDT Overflow IDLPD Invalid Key See the datasheet for minimum and maximum values A3086 01 Figure 13 9 Internal Reset Circuitry 13 6 1 Generating an External Reset To reset the device hold the RESET pin low for at least one state time after the power supply is within tolerance and the oscillator has stabilized When RESET is first asserted the device turns on a pull down transistor Q1 for 16 state times This enables the RESET signal to function as the system reset The simplest way to reset the device is to insert a capacitor between the RESET pin and shown in Figure 13 10 The device has an internal pull up resistor shown in Figure 13 9 RESET should remain asserted for at least one state time after XTAL1 have stabilized and met the operating conditions specified in the datasheet A capacitor of 4 7 uF or greater should prov
118. General purpose Register RAM 0200H 01FFH MC MD Address 0100H 00 02FFH Upper General purpose i i Register RAM Register File 9 OOFFH Lower Stack Pointer 0018H 0017 ook Register File CPU SFRs 0000H A3066 02 Figure 4 1 Register File Memory Map 4 9 8XC196MC MD MH USER S MANUAL intel Table 4 7 Register File Memory Addresses Device and Hex Address Range Description Addressing Modes MC MD MH 01FF 02FF f i 0100 0100 Upper register file register RAM Indirect indexed or windowed direct OOFF OOFF 001A 001A Lower register file register RAM Direct indirect or indexed 0019 0019 2 TOn 0018 0018 Lower register stack pointer Direct indirect or indexed 0017 0017 Ania 0000 0000 Lower register CPU SFRs Direct indirect or indexed 4 1 6 1 General purpose Register RAM The lower register file contains general purpose register RAM The stack pointer locations can also be used as general purpose register RAM when stack operations are not being performed The RALU can access this memory directly using register direct addressing The upper register file also contains general purpose register RAM The RALU normally uses indirect or indexed addressing to access the RAM in the upper register file Windowing enables the RALU to use register direct addressing to access this memory See Chapter 3
119. Ground These pins supply ground for the digital circuitry Connect each Vas pin to ground through the lowest possible impedance path B 21 8XC196MC MD MH USER S MANUAL intel Table B 6 Signal Descriptions Continued Name Type Description WG3 1 Waveform Generator Phase 1 3 Positive Outputs 3 phase output signals used in motion control applications WG1 is multiplexed with P6 1 WG2 is multiplexed with P6 3 is multiplexed with P6 5 WG3 1 Waveform Generator Phase 1 3 Negative Outputs Complimentary 3 phase output signals used in motion control applications WG1 is multiplexed with P6 0 WG2 is multiplexed with P6 2 WG3 is multiplexed with P6 4 WR Write This active low output indicates that an external write is occurring This signal is asserted only during external memory writes WRi is multiplexed with P5 2 WRL The chip configuration register 0 CCRO determines whether this pin functions as WR or WRL CCRO 2 1 selects WR CCRO 2 0 selects WRL WRH Write High During 16 bit bus cycles this active low output signal is asserted for high byte writes and word writes to external memory During 8 bit bus cycles WRH is asserted for all write operations WRH is multiplexed with P5 5 and BHE The chip configuration register 0 CCRO determines whether this pin functions as BHE or WRH CCRO 2 1 selects BHE CCRO 2 0
120. INTEGER defined 3 4 Lookup tables software protection 3 11 Manual contents summary 1 1 Manuals online 1 10 Measurements defined 1 5 Memory bus 2 6 Memory controller 2 4 2 6 Memory map 4 1 4 2 Memory mapping auto programming mode 16 27 Memory partitions 4 1 4 19 chip configuration bytes 4 4 chip configuration registers 4 4 interrupt and PTS vectors 4 3 OTPROM 16 2 program memory 4 2 16 2 register file 4 9 register RAM 4 10 reserved memory 4 3 security key 4 4 SFRs 4 4 special purpose memory 4 2 4 3 16 2 Memory protection 16 3 16 7 CCR security lock bits 16 17 UPROM security bits 16 7 Memory space See memory partitions Microcode engine 2 4 Miller effect 13 7 Mode 0 SIO 7 5 Mode 1 SIO 7 7 Mode 2 SIO 7 9 Mode 3 SIO 7 9 Index 6 intel Mode 4 SIO 7 6 Modified quick pulse algorithm 16 9 MUL instruction A 25 A 46 A 48 A 53 MULB instruction A 25 A 46 A 48 A 53 Multiprocessor communications SIO port 7 8 7 9 MULU instruction A 3 A 26 A 42 A 43 A 46 A 48 A 53 MULUB instruction A 3 A 26 A 42 A 43 A 48 A 53 N Naming conventions 1 3 1 4 NEG instruction A 2 A 27 A 41 A 48 A 53 Negative N flag A 4 A 5 A 18 A 19 A 20 NEGB instruction A 2 A 27 A 41 A 48 A 53 NMI 5 3 5 4 5 6 B 16 hardware considerations 5 6 idle powerdown reset status B 24 B 25 Noise reducing 6 3 6 4 6 7 12 12 12 13 13 4 13 5 13 6 NOP i
121. O mode Figure 5 19 PTS Control Block 1 Serial 1 0 Mode 5 38 intel STANDARD AND PTS INTERRUPTS PTS Serial I O Mode Control Block 1 Continued 8XC196MC MD Register Location Function BAUD PTSCB1 4 Baud Value This register contains the 16 bit value that the PTS uses to generate the desired baud rate Use the following formula to calculate the value to load into the BAUD register Baud value CRM OU M Multiplier Baud_rate x EPA_prescale where Baud_value is a 16 bit integer that is loaded into the BAUD register is the input frequency XTAL1 in MHz Multiplier is the number 4 in asynchronous modes and the number 8 in synchronous modes Baud_rate is the desired baud rate in bits per second EPA prescale is the EPA timer prescale number 1 64 EPAREG PTSCB1 2 EPA Time Register Address This register contains the 16 bit address of the EPAx_TIME or COMPx_TIME register PTSCON PTSCB1 2 PTS Control Bits M2 0 PTS Mode M2 Mi MO 0 0 1 SIO Receive Mode 0 1 1 SIO Transmit Mode SA1 0 Asynchronous Synchronous Mode Select SA1 SAO 0 0 enables the asynchronous serial modes 1 1 enables the synchronous serial I O modes Always write the same value to both bits MAJ Majority Sampling 0 disable majority sampling in asynchronous receive mode always clear in all other modes 1 enable majority sampling in asynchronous receive mode
122. OF INTERRUPT S snien poii e a e E ea 5 1 5 2 INTERRUPT SIGNALS AND 5 3 5 3 INTERRUPT SOURCES AND 5 4 5 3 1 Special IMtSrrupts 5 6 5 3 1 1 Unimplemented Opcode 5 6 5 3 1 2 Software Trap i eese tene E 5 6 KIES tede aden ete edna 5 6 5 8 2 External Interrupt PIN 5 6 5 8 3 Multiplexed Interrupt Sources sss emere 5 7 5 8 4 End of PTS Interrupts enden eee eite 5 9 5 4 INTERRUPT LATENCY 5 4 1 Situations that ligesse interrupt Latency 5 9 5 4 2 Calculating Latency eb 5 10 5 4 2 1 Standard Interrupt 5 10 5 4 2 2 PTS Interrupt Latency 2 5 11 5 5 PROGRAMMING THE 1 eee eem 6 12 5 5 1 Modifying Interrupt Priorities 5 18 5 5 2 Determining the Source of an Interrupt pM ET ena 5 6 INITIALIZING THE PTS CONTROL BLOCKS pene dl e E oO OS 5 24 5 6 1 Specifying the PTS Counts iii e e p Hte 5 25 5 6 2 Selecting the PTS Mode eese eene DOL 5 6 3 Single Transfer Mode 5 27 5 6 4 Block Transfer Mode 2 5 30 5 6 5 A D scan se nnne tae eit eere ire 5 32 5 6 5 1 Scan Mode Cycles 2
123. P7 7 FREQOUT in general purpose mode In special function mode the frequency generator controls the pin 8 2 intel FREQUENCY GENERATOR 8 2 PROGRAMMING THE FREQUENCY GENERATOR This section explains how to configure the frequency generator and determine its status 8 2 1 Configuring the Output The frequency generator s output is multiplexed with P7 7 so you must configure it as a special function output signal To do so follow this sequence 1 Clear bit 7 of P7 DIR 2 Setbit 7 of P7 MODE 3 Clear bit 7 of P7 REG Refer to Chapter 6 I O Ports for additional information about configuring port pins 8 2 2 Programming the Frequency Program the frequency register Figure 8 2 to control the frequency of the output FREQ GEN Address 1FB8H 8XC196MD Reset State 00H The frequency FREQ_GEN register holds a programmed value that specifies the output frequency This value is reloaded into the down counter each time the counter reaches 0 7 0 8XC196MD Output Frequency Bit _ Number Function 7 0 Output Frequency Use the following formula to calculate the FREQ value for the desired output frequency and write this value to the frequency register F FREQ E 16 x FREQ_OUT where FREQ 8 bit value to load into FREQ GEN register FxrAL1 input frequency on XTAL1 pin in MHz FREQ OUT Output frequency on FREQOUT pin in MHz Figure 8 2 Frequency
124. PWM p7 dsw 1 P6 7 I O value p6 dsw 1 P6 7 I O value phi dsw 7P6 0 1 contig 2 dsw PPOI2 3 contig 9 21 8XC196MC MD MH USER S MANUAL intel ph3 dsw 6 4 5 config eo dsw 1 0 disable output l enable output dp dsw 1 0 enable protection 1 disable dsw 1 0 falling edge trig l rising edge es dsw 1 0 edge 1 1 ec dsw 1 0 stop l start dead dsw 10 dead time reload dsw compl dsw comp2 dsw comp3 dsw temp dsw templ dsw temp2 dsw first initialize the values for these variables FIA oA OER VAS RRR EAS cseg at 0e000h board RAM di dpts ld sp 200h ld mode 0000h mode0 ld 0001h enable ld dead 0010h 71 6 us ld 0 0001 active high ld 1 0001 active high ld sync 0001h synchronized WG OUTPUT load ld 7 00000 P6 7 in I O mode ld 00000h 6 6 in I O mode ld p7 00000h P6 7 0 1 000008 7P6 6 0 ld phi 0007h wfg both outputs ld ph2 0007h wfg both outputs ld ph3 0007h wfg both outputs ld 0001h enable outputs ld dp 4 0001h disable protection ld it 0001h rising high edge trigger ld es 0001h 24 state trigger ld reload 1000h 71 024 ms modeO ld compl 0100h 64 us ld comp2 0200h 128 us ld comp3 0400h 256 us
125. Reg Mem Reg Mem Reg Mem Reg Mem POP 8 10 12 11 13 11 13 12 14 POPA 12 POPF 7 PUSH 6 7 9 12 10 13 10 13 11 14 PUSHA 12 PUSHF 6 Stack Memory Indirect Indexed Mnemonic Direct Immed Normal Autoinc Short Long Reg Mem Reg Mem Reg Mem Reg Mem POP 11 13 15 14 16 14 16 15 17 POPA 18 POPF 10 PUSH 8 9 11 14 12 15 12 15 13 16 PUSHA 18 PUSHF 8 NOTE Thecolumn entitled Reg lists the instruction execution times for accesses to the register file or peripheral SFRs The column entitled Mem lists the instruction execution times for accesses to all memory mapped registers I O or memory See Table 4 1 on page 4 2 for address information A 54 intel INSTRUCTION SET REFERENCE Table A 9 Instruction Execution Times in State Times Continued Data Mnemonic Indirect BMOV register register 6 8 per word memory register 6 11 per word memory memory 6 14 per word BMOVI register register 7 8per word 14 per interrupt memory register 7 11 word 14 per interrupt memory memory 7 14 per word 14 per interrupt Indirect Indexed Mnemonic Direct Immed Normal Autoinc Short Long Reg Mem Reg Mem Reg Mem Reg Mem LD 4 5 5 8 6 8 6 9 7 10 LDB 4 4 5 8 6 8 6 9 7 10 LDBSE 4 4 5 8 6 8 6 9 7 10 LDBZE 4 4 5 8 6 8 6 9 7 10
126. SFRs write zeros to them or leave them in their default state When read reserved bits and reserved SFRs return undefined values NOTE Using any SFR as a base or index register for indirect or indexed operations can cause unpredictable results because external events can change the contents of SFRs Also because some SFRs are cleared when read consider the implications of using an SFR as an operand in a read modify write instruction e g XORB ntel MEMORY PARTITIONS 4 1 5 1 Memory mapped SFRs Locations 1FE0 1FFFH contain memory mapped SFRs see Table 4 3 Locations in this range that are omitted from the table are reserved The memory mapped SFRs must be accessed with indirect or indexed addressing modes and they cannot be windowed If you read a location in this range through a window the SFR appears to contain FFH all ones If you write a location in this range through a window the write operation has no effect on the SFR The memory mapped SFRs are accessed through the memory controller so instructions that op erate on these SFRs execute as they would from external memory with zero wait states Table 4 3 Memory mapped SFRs Ports 3 4 5 UPROM SFRs Hex Address High Odd Byte Low Even Byte 1FFE P4_PIN P3_PIN 1FFC P4_REG P3_REG 1FF6 P5_PIN USFR 1FF4 P5 REG Reserved 1FF2 P5 DIR Reserved 1FFO P5 MODE Reserved 4 1 5 2 Peripheral SFRs Locations IF00 1FDFH p
127. ST 4 5 8 6 9 6 9 7 10 STB 4 5 8 6 8 6 9 7 10 XCH 5 8 13 9 14 XCHB 5 8 13 9 14 Jump Indirect Indexed Mnemonic Direct Immed Normal Autoinc Short Long BR 7 7 LJMP 7 SJMP 7 TIJMP register register _ 15 E 25 memory register 18 memory memory 21 Call Register Indirect Indexed Mnemonic Direct Immed Normal Autoinc Short Long LCALL 11 RET 11 SCALL 11 TRAP 16 a NOTE The column entitled Reg lists the instruction execution times for accesses to the register file or peripheral SFRs The column entitled Mem lists the instruction execution times for accesses to all memory mapped registers I O or memory See Table 4 1 on page 4 2 for address information A 55 8XC196MC MD MH USER S MANUAL intel Table A 9 Instruction Execution Times in State Times Continued Call Memory Indirect Indexed Mnemonic Direct Immed Normal Autoinc Short Long LCALL 13 RET pe 14 SCALL __ 13 18 Conditional Jump Mnemonic Short Indexed DJNZ 5 jump not taken 9 jump taken DJNZW 6 jump not taken 10 jump taken JBC 5 jump not taken 9 jump taken JBS 5 jump not taken 9 jump taken JC 4 jump not taken
128. Terms and Conditions of Sale for such products Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein Intel retains the right to make changes to these specifications at any time without notice Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order MDS is an ordering code only and is not used as a product name or trademark of Intel Corporation Intel Corporation and Intel s FASTPATH are not affiliated with Kinetics a division of Excelan Inc or its FASTPATH trademark or products Other brands and names are the property of their respective owners Additional copies of this document or other Intel literature may be obtained from Intel Corporation Literature Sales P O Box 7641 Mt Prospect IL 60056 7641 or call 1 800 879 4683 INTEL CORPORATION 1996 intel CONTENTS CHAPTER 1 GUIDE TO THIS MANUAL 1 1 MANUAL 1 1 1 2 NOTATIONAL CONVENTIONS AND TERMINOLOGY eem e 1 3 1 3 RELATED 5 enne 1 5 1 4 ELECTRONIC SUPPORT 5 5 1 8 1 4 1 FaxBack Service enit saves ER HENDRER 1 8 1 4 2 Bulletin Board System BBS eene 1
129. The maximum output frequency depends upon the total interrupt latency and the interrupt service execution times used by your system As additional EPA channels and the other functions of the microcontroller are used the maximum PWM frequency decreases because the total interrupt la tency and interrupt service execution time increases To determine the maximum low speed PWM frequency in your system calculate your system s worst case interrupt latency and worst case interrupt service execution time and then add them together The worst case interrupt la tency is the total latency of all the interrupts both normal and PTS used in your system The worst case interrupt service execution time is the total execution time of all interrupt service rou tines and PTS routines Assume a system with a single EPA channel a single enabled interrupt and the following inter rupt service routine interrupt is generated EPA0 x ISR PUSHA LD EPAx CON fstoggle command ADD EPAx TIME TIMERx next duty ptr Load next event time POPA RET The worst case interrupt latency for a single interrupt system is 56 state times for external stack usage and 54 state times for internal stack usage see Standard Interrupt Latency on page 5 10 To determine the execution time for an interrupt service routine add up the execution time of the instructions Table A 9 The total execution time for the ISR that services the EPA interrupts is 79 state
130. Value low byte 7 0 PTSCON M2 M1 MO o o 1 0 7 0 PTSCOUNT Consecutive A D Conversions Register Location Function PTSPTR2 PTSCB 4 Pointer 2 Value This register contains the address of the A D result register AD RESULT PTSPTR1 PTSCB 2 Pointer 1 Value This register contains the address of the table of A D conversion commands and results PTSCON PTSCB 1 PTS Control Bits M2 0 PTS Mode These bits select the PTS mode M2 1 0 1 1 0 A D Scan Mode UPDT Update 0 reload original PTSPTR1 value after each A D scan 1 retain current PTSPTR1 value after each A D scan Figure 5 18 PTS Control Block A D Scan Mode 5 33 8XC196MC MD MH USER S MANUAL intel PTS A D Scan Mode Control Block Continued PTSCOUNT PTSCB 0 Consecutive A D Conversions Defines the number of A D conversions that will be completed during the A D scan routine Each cycle consists of the PTS transferring the A D conversion results into the command data table and then loading a new command into the AD COMMAND register Maximum number is 255 Figure 5 18 PTS Control Block A D Scan Mode Continued To use the A D scan mode you must first set up a command data table in memory Table 5 7 The command data table contains A D commands that are interleaved with blank memory loca tions The PTS stores the conversion results in these blank l
131. XTAL1 69 XTAL2 68 E1NC 75 P5 1 INST 67 FA NC 74 Ea P5 6 READY 65 P6 6 66 FNC P5 2 WR WRL 1 P5 7 BUSWIDTH amp 2 015 4 7 PBUS 15 F13 014 P4 6 PBUS 14 944 P6 7 PWM1 P2 6 COMP2 2 5 1 2 4 Voc NC 13 P4 5 PBUS 13 NC CLKOUT 97 P2 7 AD12 P4 4 PBUS 12 H 8 2 3 AD11 P4 3 PBUS 11 9 S8XC196MC P2 2 EPA2 PROG AD10 P4 2 5 10 AD9 P4 1 PBUS 9 08 P4 0 PBUS 8 AD7 P3 7 PBUS 7 NC NC P2 1 EPA1 PALE P2 0 PVER AD6 P3 6 PBUS 6 amp NC AD5 P3 5 PBUS 5 amp View of component as P0 0 ACHO AD4 P3 4 5 4 mounted on PC board P0 1 ACH1 P3 3 PBUS 3 17 4 P0 2 ACH2 2 2 PBUS 2 AD1 P3 1 PBUS 1 P0 3 ACH3 P0 4 ACH4 PMODE O ADO P3 0 PBUS 0 amp 20 P0 5 ACH5 PMODE 1 NC 921 VREF RESET r1 22 ANGND 23 P0 6 ACH6 PMODE 2 EA O 24 3 P0 7 ACH7 PMODE 3 CN CO sx 10 CO NN 9 DT LI LI LI LI Li LI LI Li MHA 3t T 225050 84055 gt gt gt sOs gt O0SZ90905 955 lO 0 Se Se AIO TUUS dif 23052 328 a Oo lt lt Qn aa A3104 01 Figure B 3 8XC196MC 80 lead Shrink EIAJ QFP Packag
132. a reset on the external pin see Resetting the Device on page 13 8 After a device reset the first instruction fetch is from FF2080H RXD1 0 MH only Receive Serial Data 0 1 In modes 1 2 and 3 RXDO and 1 receive serial port input data In mode 0 they function as either inputs or open drain outputs for data RXDO is multiplexed with P1 1 RXD1 is multiplexed with P1 3 B 20 intel SIGNAL DESCRIPTIONS Table B 6 Signal Descriptions Continued Name Type Description SCLK1 0 Shift Clock 0 and 1 MH only In SIO mode 4 SCLKx are bidirectional shift clock signals that synchronize the serial data transfer The DIR bit in the SP_CON register controls the direction of SCLKx DIR 1 allows an external shift clock to be input SCLKx DIR 0 causes SCLKx to output the internal shift clock SCLKO is multiplexed with P2 1 BCLKO and PALE SCLK1 is multiplexed with 2 7 and Timer 1 External Clock External clock for timer 1 Timer 1 increments or decrements on both rising and falling edges of T1CLK Also used in conjunction with T1DIR for quadrature counting mode and External clock for the serial I O baud rate generator input program selectable On the 8XC196MC and MD T1CLK is multiplexed with P1 2 and ACH10 On the 8XC196MH T1CLK is multiplexed with P0 6 ACH6 and PMODE 2 T1DIR Timer 1 External Dir
133. an instruction sequence that loads the contents of the interrupt pending register into a tempo rary register modifies the contents of the temporary register and then writes the contents of the temporary register back into the interrupt pending register If the interrupt occurs during one of the last four states of the second instruction it will not be acknowledged until after the completion of the third instruction Because the third instruction overwrites the contents of the interrupt pend ing register the jump to the interrupt vector will not occur The PI MD SPI MH and OVRTM Mx interrupts have multiple sources Read PI PEND Figure 5 12 on page 5 23 to determine which source generated the interrupt request Reading PEND clears all the bits PEND is a read only register 5 20 intel STANDARD AND PTS INTERRUPTS INT_PEND Address 0009H Reset State 00H When hardware detects an interrupt request it sets the corresponding bit in the interrupt pending INT PEND or INT PEND1 registers When the vector is taken the hardware clears the pending bit Software can generate an interrupt by setting the corresponding interrupt pending bit 7 0 MC MD 2 EPA2 1 EPA1 COMPO EPAO AD OVRTM 7 0 MH COMP2 1 1 0 OVRTM Bit Number Function 7 0 Any set bit indicates that the corresponding interrupt is pend
134. and Reset Values Register Address Reset Value POPIN when pin is not driven E MD EP FFH when pin is not driven P2 PIN 8XC196Mx 1FD6H FFH when pin is not driven P3 PIN 8XC196Mx 1FFEH FFH when pin is not driven P4 PIN 8XC196Mx 1FFFH FFH when pin is not driven P5 PIN 8XC196MC MD 1FF7H FFH P5 PIN 8XC196MH 1FF7H FFH when pin is not driven P7 PIN 8XC196MD 1FD7H XXH C 33 8XC196MC MD MH USER S MANUAL intel Px REG Px REG Address Table C 10 2 5 8XC196MC Reset State 2 5 7 8XC196MD 1 5 8 196 For an input set the corresponding port x data output Px_REG register bit For an output write the data to be driven out by each pin to the corresponding bit of Px REG When pin is configured as standard I O Px_MODE y 0 the result of a CPU write to Px_REG is immediately visible on the pin When a pin is configured as a special function signal Px_MODE y 1 the associated on chip peripheral or off chip component controls the pin The CPU can still write to Px_REG but the pin is unaffected until it is switched back to its standard I O function This feature allows software to configure pin as standard clear Px_MODE y initialize or overwrite the pin value then configure the as a special function signal set Px_MODE y In this way initialization fault recovery exception handling etc can be done without changing the operation
135. and replaces the original destination operand with the result The result has a 1 in each bit 100100aa baop breg position in which either the source or destination operand had a 1 DEST lt DEST OR SRC PSW Flag Settings 0 0 A 28 intel INSTRUCTION SET REFERENCE Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format POP POP WORD Pops the word on top of the stack and places it at the destination operand DEST lt SP SP lt SP 2 PSW Flag Settings waop 110011 aa waop POPA POP ALL This instruction is used instead of POPF to support the eight additional interrupts It pops two words off the stack and places the first word into the INT_MASK1 WSR register pair and the second word into the PSW INT_MASK register pair This instruction increments the SP by 4 Interrupt calls cannot occur immediately following this instruction INT_MASK1 WSR lt SP SP lt SP 2 PSW INT_MASK lt SP SP lt SP 2 PSW Flag Settings Z N C V VT ST 11110101 POPF POP FLAGS Pops the word on top of the stack and places it into the PSW Interrupt calls cannot occur immediately following this instruction PSW INT_MASK lt SP SP lt
136. are as follows Bit Mnemonic PTS Vector Bit Mnemonic PTS Vector EXTINT 205CH TIO MH 2050H PI MC 11 205AH COMP2 MC MD 204EH WG MH 205AH COMP3 MH 204EH 5 MD 2058H EPA2 MC MD 204CH SPI 2058H COMP2 MH 204CH COMP4 MD 2056H COMP1 204AH MH 2056H EPA1 2048H EPA4 MD 2054H COMPO 2046H RIO MH 2054H EPAO 2044H COMP3 MC MD 2052H AD 2042H TH MH 2052H OVRTM t 2040H EPA3 MC MD 2050H PTS service is not useful for multiplexed interrupts because the PTS cannot readily determine the source of these interrupts to these bits t On the 8XC196MC device bits 10 12 are reserved For compatibility with future devices write zeros 5 14 Figure 5 6 PTS Select PTSSEL Register intel STANDARD AND PTS INTERRUPTS INT_MASK The interrupt mask INT MASK register enables or disables masks individual interrupt requests The El and DI instructions enable and disable servicing of all maskable interrupts INT_MASK is the low byte of the processor status word PSW PUSHF or PUSHA saves the contents of this register onto the stack and then clears this register Interrupt calls cannot occur immediately following this instruction POPF or POPA restores it Address Reset State 0008H 00H 7 0 MC MD 2 EPA2 1 EPA1 COMPO EPAO AD OVRTM 7 0 MH COMP2 1 EPA1 COMPO EPAO AD OVRTM Bit Num
137. as an input 1 output O bidirectional I O power PWR or ground GND Note that all inputs except RESET are sampled inputs RESET is a level sensitive input During powerdown mode the powerdown circuitry uses EXTINT as a level sensitive input Description Briefly describes the function of the pin for the specific signal listed in the Name column Also lists any alternate fuctions that are multiplexed with the signal Table B 6 Signal Descriptions Name Type Description ACH12 0 MC ACH13 0 MD 7 0 MH Analog Channels These pins are analog inputs to the A D converter These pins may individually be used as analog inputs ACH or digital inputs PO y While it is possible for the pins to function simultaneously as analog and digital inputs this is not recommended because reading port 0 while a conversion is in process can produce unreliable conversion results The ANGND and Vr pins must be connected for the A D converter and port 0 to function ACH7 0 are multiplexed as follows 0 0 ACH1 P0 1 ACH2 P0 2 ACH3 P0 3 ACH4 P0 4 PMODE 0 ACH5 P0 5 PMODE 1 ACH6 P0 6 PMODE 2 ACH7 P0 7 PMODE 3 ACH8 P1 0 ACH9 P1 1 ACH10 P1 2 T1CLK ACH11 P1 3 T1DIR and 12 1 4 and ACH13 P1 5 ACH13 is not implemented on the 8XC196MC and ACH13 8 are not implemented on the 8XC196MH AD15 0 Address Data Lines These pins provide a multiplexed address and data bus Du
138. both a transmit interrupt and a receive interrupt RIx Each channel can also generate a serial port receive error interrupt SPx To enable an interrupt set the corresponding mask bit in the interrupt mask register or peripheral interrupt mask register see Table 7 2 on page 7 2 and execute the EI instruction to globally enable servicing of interrupts See Chapter 5 Standard and PTS Interrupts for more information about interrupts intel SERIAL 1 0 SIO PORT 7 4 5 Determining Serial Port Status You can read the SPx_STATUS register Figure 7 8 to determine the status of the serial port Reading SPx_STATUS clears all bits except TXE For this reason we recommend that you copy the contents of the SPx_STATUS register into a shadow register and then execute bit test instruc tions such as JBC and JBS on the shadow register Otherwise executing a bit test instruction clears the flags so any subsequent bit test instructions will return false values You can also read the interrupt pending register or peripheral interrupt pending register see Table 7 2 on page 7 2 to determine the status of the serial port interrupts SPx_STATUS Address 1F81H 1F89H x 0 1 8XC196MH Reset State 00H The serial port status SPx STATUS register contains bits that indicate the status of serial port x 7 0 8XC196MH RPE RB8 TI FE Bit Bit Function Number Mnemonic 7 RPE RB8 Rece
139. bus until the CCBs are loaded AD15 8 weakly drive address during the CCB fetches For 16 bit systems write 20H to the high byte of CCBO and CCB1 2019H and 201 in order to prevent bus contention A3088 02 Figure 13 7 Reset Timing Sequence 13 8 intel MINIMUM HARDWARE CONSIDERATIONS The 8XC196MH provides the option of an internal only reset or an internal reset that is also re flected externally by the RESET pin The GEN CON register controls whether an internal re set asserts the external RESET signal and indicates the source of the most recent reset Figure 13 8 describes the general configuration register GEN CON GEN CON Address 1FAOH 8XC196MH Reset State 00H The GEN CON register controls whether an internal reset asserts the external RESET signal and indicates the source of the most recent reset 7 0 8XC196MH RSTS DRO Bit Bit i Function Number Mnemonic unctio 7 RSTS Reset source read only status bit 0 external reset RESET pin asserted 1 internal reset watchdog overflow illegal IDLPD key or RST instruction 6 1 Reserved for compatibility with future devices write zeros to these bits DRO Disable RESET out 0 an internal reset asserts the RESET pin 1 internal reset has no effect on the RESET pin the RESET pin is pulled high inactive Figure 13 8 General Configuration Register
140. controller is locked into an 8 bit bus mode In comparing 8 bit bus system to a 16 bit bus system expect some performance degradation In a 16 bit bus system a word fetch is done with a single word fetch However in an 8 bit bus system a word fetch takes an additional bus cycle because it must be done with two byte fetches If BWO is set and BW1 is clear the bus controller is locked into a 16 bit bus mode If both BWO and BWI are set the BUSWIDTH signal controls the bus width The bus is 16 bits wide when BUSWIDTH is high and 8 bits wide when BUSWIDTH is low The BUSWIDTH signal is sam pled after the address is on the bus as shown in Figures 15 4 and 15 5 15 11 8XC196MC MD MH USER S MANUAL intel TxrAL1 i oq rex qos CLKOUT ALE gt lt BUSWIDTH K vaia X lt Tavev The CLKOUT pin is available only on the 8XC196MC MD A3162 01 Figure 15 4 BUSWIDTH Timing Diagram 8XC196MC MD TxrAL1 XTAL1 ALE BUSWIDTH AD15 0 99900979 A3169 01 Figure 15 5 BUSWIDTH Timing Diagram 8XC196MH 15 12 intel INTERFACING WITH EXTERNAL MEMORY Table 15 4 BUSWIDTH Signal Timing Definitions Symbol Definition Tavev Address Valid to BUSWIDTH Setup Maximum time the external device has to assert or deassert BUSWIDTH after the microcon troller outputs the address Terex BUSWIDTH Hold after CLKOUT Low Minimum time the l
141. data frame used in this mode It con sists of a start bit 0 nine data bits LSB first and a stop bit 1 During transmissions setting the TB8 bit in the SPx CON register before writing to SBUFx TX sets the ninth transmission bit The hardware clears the TB8 bit after every transmission so it must be set if desired before each write to SBUFx TX During receptions the RI flag and RIx interrupt pending bit are set only if the TB8 bit is set This provides an easy way to have selective reception on a data link See tiprocessor Communications on page 7 9 Parity cannot be enabled in this mode 7 8 intel SERIAL 1 0 SIO PORT St X 02 X BAX DSK DEX OTK Sup 8 Bits of Data ji Programmable 9th Bit k 11 bit Frame gt 0111 01 Figure 7 5 Serial Port Frames in Mode 2 and 3 7 3 2 3 Mode 3 Mode 3 is the asynchronous ninth bit mode The data frame for this mode is identical to that of mode 2 Mode 3 differs from mode 2 during transmissions in that parity can be enabled in which case the ninth bit becomes the parity bit When parity is disabled data bits 0 7 are written to the serial port transmit buffer and the ninth data bit is written to SPx_CON 4 TB8 In mode 3 a reception always sets the RIx interrupt pending bit regardless of the state of the ninth bit If parity is disabled the SPx STATUS register bit 7 RB8 contains the ninth data bit If parity is enabled
142. dis abled RBS is the ninth data bit received in modes 2 and 3 intel Frequency Generator intel CHAPTER 8 FREQUENCY GENERATOR The 8XC196MD has a peripheral not found on other 8XC196Mx devices the frequency gen erator This peripheral produces a waveform with a fixed duty cycle 5096 and a programmable frequency ranging from 4 kHz to 1 MHz with 16 MHz input clock One application for the frequency generator is to drive an infrared LED to transmit remote control data and control sig nals This chapter describes the frequency generator and explains how to configure it For detailed de scriptions of the signals discussed in this chapter refer to Appendix B Signal Descriptions For additional information and application examples consult AP 483 Application Examples Using the 8XC196MC MD Microcontroller order number 272282 8 1 FUNCTIONAL OVERVIEW The frequency generator Figure 8 1 has a frequency register a count register and an output sig nal The output signal shares pin P7 7 so you must configure the pin for its frequency generator output function Port 7 Control Down Counter 2702 01 Figure 8 1 Frequency Generator Block Diagram 8XC196MC MD MH USER S MANUAL intel The frequency register FREQ controls the output frequency The frequency generator loads the FREQ_GEN value into the counter The counter counts down until it reaches zero at which ti
143. each PWM channel is a variable duty cycle pulse Several types of motors require a PWM waveform for most efficient operation When filtered the PWM wave form produces a DC level that can change in 256 steps by varying the duty cycle The number of steps per PWM period is also programmable 8 bits See Chapter 10 Pulse width Modulator for more information 2 5 5 Frequency Generator The 8XC196MD has a peripheral not found on other 8XC196Mx microcontrollers the fre quency generator This peripheral produces a waveform with a fixed duty cycle 5096 and a pro grammable frequency ranging from 4 kHz to 1 MHz with a 16 MHz input clock See Chapter 8 Frequency Generator for details 2 5 6 Waveform Generator A waveform generator simplifies the task of generating synchronized pulse width modulated PWM outputs This waveform generator is optimized for motion control applications such as driving 3 phase AC induction motors 3 phase DC brushless motors or 4 phase stepping motors The waveform generator can produce three independent pairs of complementary PWM outputs which share a common carrier period dead time and operating mode Once it is initialized the waveform generator operates without CPU intervention unless you need to change a duty cycle See Chapter 9 Waveform Generator for more information intel ARCHITECTURAL OVERVIEW 2 5 7 Analog to digital Converter The analog to digital A D converter converts an an
144. following formula to calculate the appropriate DT VALUE T xF DT VALUE DEAD 5 XTAL1 where dead time in us FxraL1 input frequency XTAL1 pin in MHz 9 18 Figure 9 12 Waveform Generator Control WG CONTROL Register intel WAVEFORM GENERATOR 9 5 DETERMINING THE WAVEFORM GENERATOR S STATUS Read CONTROL Figure 9 12 on page 9 18 to determine the current dead time value counter status count direction and operating mode Read WG_COUNTER Figure 9 13 to de termine the current counter value WG COUNTER Address 1FCAH E Reset State MC MD XXXXH Reset State MH 0000H You can read the waveform generator counter WG register to determine the current counter value 15 0 Counter Value Bit Number Function 15 0 Counter Value This register reflects the current counter value Figure 9 13 Waveform Generator Counter WG COUNTER Register 9 6 ENABLING THE WAVEFORM GENERATOR INTERRUPTS The waveform generator can generate two types of interrupt requests The WG interrupt request is triggered by the counter while the EXTINT interrupt is triggered by an external event Mode 0 generates a WG interrupt request once per period when the counter reaches the WG_RELOAD value Mode 1 generates a WG interrupt request twice per period first when the counter reaches and again when it reaches the WG_RELOAD value The edge aligned modes gen
145. for the low order half of the destination operand Chapter 3 Programming Considerations defines the operands and possible values for each Instruction Quotient Stored in V Flag Set if Quotient is DIVB Short integer lt 128 or gt 127 lt 81H or gt 7FH DIV Integer lt 32768 or gt 32767 lt 8001H or gt 7FFFH DIVUB Byte 255 FFH DIVU Word 65535 FFFFH VT The overflow trap flag is set when the overflow flag is set but it is cleared only by the CLRVT JVT and JNVT instructions This allows testing for a possible overflow at the end of a sequence of related arithmetic operations which is generally more efficient than testing the overflow flag after each operation The zero flag is set to indicate that the result of an operation was zero For multiple precision calculations the zero flag cannot be set by the instructions that use the carry bit from the previous calculation e g ADDC SUBC However these instructions can clear the zero flag This ensures that the zero flag will reflect the result of the entire operation not just the last calculation For example if the result of adding together the lower words of two double words is zero the zero flag would be set When the upper words are added together using the ADDC instruction the flag remains set if the result is zero and is cleared if the result is not zero A 4 intel INSTRUCTION SET REFERENCE Table A 3 shows the effect o
146. function The difference becomes apparent only when the bus is idle Because ADV is high during these periods external memory will be disabled thus saving power 1 1 ave 1 1 ADV 1 1 1 1 1 1 1 1 1 ALE RD WR Bus Idle Next Bus Cycle A3093 02 Figure 15 17 Comparison of ALE and ADV Bus Cycles 15 27 8XC196MC MD MH USER S MANUAL intel Figure 15 18 and Figure 15 19 show sample circuits that use the address valid strobe mode Fig ure 15 18 shows a simple 8 bit system with a single flash It is configured for the address valid strobe mode This system configuration uses the ADV signal as both the flash chip select signal and the address latch signal 32Kx8 8XC196 Flash 28F256 7 0 7 0 A3094 01 Figure 15 18 8 bit System with Flash 15 28 intel INTERFACING WITH EXTERNAL MEMORY Figure 15 19 shows a 16 bit system with two EPROMs This system configuration uses the ADV signal as both the EPROM chip select signal and the address latch signal Voc BUSWIDTH AD15 8 ADV 8XC196 AD7 0 A3095 01 Figure 15 19 16 bit System with EPROM 15 29 8XC196MC MD MH USER S MANUAL intel 15 5 4 Address Valid with Write Strobe Mode When the address valid with write strobe mode is selected the microcontroller generates the ADV RD WRL and WRH bus control signals This mode is used for a simple s
147. inclusive or as the content of any register 10H OFFH with a value in the range of 0 to 31 1FH inclusive The left bits of the result are filled with zeros The last bit shifted out is saved in the carry flag Temp lt COUNT do while Temp 0 lt Low order bit of DEST DEST DEST 2 Temp lt Temp 1 end_while PSW Flag Settings 0 0 00011000 count breg or SHRB breg breg 00011000 breg breg NOTES This instruction clears the sticky bit flag at the beginning of the instruction If at any time during the shift a 1 is shifted into the carry flag and another shift cycle occurs the instruc tion sets the sticky bit flag In this operation DEST 2 rep resents unsigned division A 35 8XC196MC MD MH USER S MANUAL Table A 6 Instruction Set Continued tel Control passes to the next sequential instruction This is actually a two byte NOP in which the second byte can be any value and is simply ignored PSW Flag Settings Mnemonic Operation Instruction Format SHRL LOGICAL RIGHT SHIFT DOUBLE WORD Shifts the destination double word operand to SHRL Ireg count the right as many times as specified by the count operand The count may be specified 00001100 c
148. is configured at reset you should still write data into Pl MODE After reset your software must configure the device to match the external system This is accomplished by writing appropriate config uration data into P2 MODE Writing to P2 MODE not only configures the pins but also turns off the transistor that weakly holds the pins high Q4 in Figure 6 2 on page 6 8 For this reason even if port 2 is to be used as it is configured at reset you should still write data into 2 MODE A value written to P2 REG 7 is held in a buffer until P2 7 is cleared at which time the value is loaded into P2 REG 7 A value read from P2_REG 7 is the value currently in the register not the value in the buffer Therefore any change to P2_REG 7 can be read only after P2 MODE 7 is cleared After reset the device configures port 5 to match the external system The following paragraphs describe the states of the port 5 pins after reset and until your software writes to the P5 MODE register Writing to P5 MODE not only configures the pins but also turns off the transistor that weakly holds the pins high Q4 in Figure 6 2 on page 6 8 For this reason even if port 5 is to be used as it is configured at reset you should still write data into 5 MODE intel P5 0 ALE P5 1 INST P5 2 WR WRL P5 3 RD P5 4 P5 5 BHE WRH P5 6 READY P5 7 BUS WIDTH PORTS If EA is high on reset internal access the pin is weakly held
149. is the start reception interrupt interrupt service routine contains the following steps Reconfigure the EPA channel to compare mode Set EPAO_CON 6 selects compare mode Initialize the first PTS cycle time by writing the time of the first interrupt to TIME To set up the correct value multiply the baud value 1 by 1 5 add the product to the current TIMERI value and store the result in EPAO TIME The baud value determines the time to the first PTS interrupt When the interrupt occurs the PTS transmits the first data bit The baud value of 1A0H selects a baud rate of 9600 In this example the value added to the current value is 270H Select PTS service for EPAO Set PTSSEL 2 The PTS routine begins sampling the data every 1 5 bit times When PTSCOUNT decrements to zero the PTS calls the end of PTS interrupt Figure 5 28 The interrupt service routine should check to see if a framing or parity error occurred Figure 5 19 on page 5 38 clear the DATA registers to prepare for the next reception reload the PTSCOUNT and PTSCONI registers and reconfigure the EPA channel to select capture on falling edge mode Note that PTS service is not enabled for the EPA channel at this time because the next interrupt must be a conventional interrupt To determine when all bytes have been transmitted create a loop routine to check the status of the RXDDONE flag 5 57 8XC196MC MD MH USER S MANUAL intel
150. length of the interrupt service routine as well as other factors Unless the interrupt service routine includes a check for overruns this situ ation will remain the same until the device is reset or the EPAx_TIME register is read The act of reading EPAx_TIME allows the buffered time value to be moved into EPAx_TIME This clears the buffer and allows another event to be captured Remember that the act of the transferring the buffer contents to the EPAx_TIME register is what actually sets the EPAx interrupt pending bit and generates the interrupt 11 12 intel EVENT PROCESSOR ARRAY EPA 11 4 1 2 Preventing EPA Overruns Any one of the following methods can be used to prevent or recover from an EPA overrun situa tion e Clear 0 When the overwrite bit EPAx 0 is zero the EPA does not consider the captured edge until the EPAx TIME register is read and the data in the capture buffer is transferred to EPAx TIME This prevents overruns by ignoring new input capture events when both the capture buffer and EPAx TIME contain valid capture times Check for pending EPAx interrupts before exiting an EPAx ISR Another method for avoiding this situation is to check for pending EPA interrupts before exiting the EPA interrupt service routine This is an easy way to detect overruns and addi tional interrupts It can also save loop time by eliminating the latency necessary to service the pending interrupt However this method
151. list the signals for the 8 196 8XC196MD and 8XC196MH re spectively grouped by function A diagram of each package that is currently available shows the pin location of each signal NOTE The datasheets are revised more frequently than this manual As new packages are supported the pin out diagrams will be added to the datasheets first If your package type is not shown in this appendix refer to the latest datasheet to find the pin locations 8XC196MC MD MH USER S MANUAL intel Table B 2 8XC196MC Signals Arranged by Functional Categories Address amp Data Programming Control Input Output Input Output Cont d AD15 0 AINC P0 7 0 ACH7 0 P6 5 WG3 CPVER P1 0 ACH8 P6 6 PWMO Bus Control amp Status PACT P1 1 ACH9 P6 7 PWM1 ALE ADV PALE P1 2 ACH10 T1CLK BHE WRH PBUS 15 0 P1 3 ACH11 T1DIR BUSWIDTH PMODE 3 0 P1 4 ACH12 INST PROG P2 3 0 EPA3 0 READY PVER P2 6 4 COMP2 0 RD P2 7 COMP3 WR WRL Processor Control P3 7 0 CLKOUT P4 7 0 Power amp Ground EA P5 1 ANGND EXTINT P5 7 0 Voc NMI P6 0 WG1 Vop ONCE P6 1 WG1 VREE RESET P6 2 WG2 Vss XTAL1 P6 3 WG2 XTAL2 P6 4 WG3 NOTE The shaded signals are not available in the 64 pin package B 2 SIGNAL DESCRIPTIONS Vss P5 0 ALE ADV P5 3 RD 5 5 BHE WRH P5 2 WR WRL P5 7 BUSWIDTH 14 P4 6 PBUS 14 AD13 P4 5 PBUS 13 015 P4 7
152. map Auto programming is specified for a crystal frequency of 6 to 8 MHz At 8 MHz usea 27 C 512 EPROM with tACC 250 ns and tOE 100 ns or faster specifications Tie the BUSWIDTH pin low to configure an 8 bit data bus Connect P1 3 0 8XC196MH only as shown to generate the high order bits of the external EPROM address Connect 0 7 4 to and to select auto programming 1100B and PVER are status outputs buff ered by the 74HC 14s They drive LEDs that indicate programming active PACT and program ming verification PVER Connect all unused inputs to ground and leave unused outputs floating READY and NMI are active connect them as indicated NOTE All external EPROM addresses specified in this section are given for the circuit in Figure 16 12 If you choose a different circuit you must adjust the addresses accordingly 16 25 8XC196MC MD MH USER S MANUAL intel 100 kQ XTAL2 RESET lt lt Reset 5 0V e T 74HC14 1 0pF READY P5 6 EE Voc VREF a P0 7 3 PMODE 3 c P0 6 PMODE 2 OEK CE P0 5 0 4 Voc PMODE O ANGND 270kQ ALE P5 0 LE po lt of 2 AD7 0 Ao 74HC14 5 ON Programming W vs 270kQ x P2 0 PVER 9 lt lt 2 74HC14 ON Error 87C196Mx A3111 01 Figure 16 12 Auto Programming Circuit 16 26 intel PROGRAMMING THE NONVOL
153. method only when using an external clock input because the internal CPU and peripheral clocks will be enabled but the internal oscillator will not 14 4 3 2 Generating a Hardware Reset The device will exit powerdown if RESET is asserted If the design uses an external clock input signal rather than the on chip oscillator RESET must remain low for at least 16 state times If the design uses the on chip oscillator then RESET must be held low until the oscillator has sta bilized 14 6 intel SPECIAL OPERATING MODES 14 4 3 3 Asserting the External Interrupt Signal The final way to exit powerdown mode is to assert the external interrupt signal EXTINT for at least 50 ns Although EXTINT is normally a sampled input the powerdown circuitry uses it as a level sensitive input The interrupt need not be enabled to bring the device out of powerdown but the pin must be configured as a special function input see Bidirectional Port Pin Configura tions on page 6 9 Figure 14 2 shows the power up and power down sequence when using an external interrupt to exit powerdown When an external interrupt brings the device out of powerdown mode the corresponding pending bit is set in the interrupt pending register If the interrupt is enabled the device executes the in terrupt service routine then fetches and executes the instruction following the IDLPD 2 instruc tion If the interrupt is disabled masked the device fetches and executes t
154. modes work Assembly Language Addressing Mode Selections on page 3 9 describes how the assembly language handles direct and indexed addressing modes The examples in this section assume that temporary registers are defined as shown in this segment of assembly code and described in Table 3 3 Oseg at ich AL DSB BL DSB Che DSB DL DSB AX DSW BX DSW CX DSW DSW THISVAR DSW 8XC196MC MD MH USER S MANUAL intel Table 3 3 Definition of Temporary Registers Temporary Register Description AX word aligned 16 bit register AH is the high byte of AX and AL is the low byte BX word aligned 16 bit register BH is the high byte of BX and BL is the low byte CX word aligned 16 bit register CH is the high byte of CX and CL is the low byte DX word aligned 16 bit register DH is the high byte of DX and DL is the low byte 3 2 1 Direct Addressing Direct addressing directly accesses a location in the 256 byte lower register file without involv ing the memory controller Windowing allows you to remap other sections of memory into the lower register file for direct access see Chapter 4 Memory Partitions for details You specify the registers as operands within the instruction The register addresses must conform to the align ment rules for the operand type Depending on the instruction up to three registers can take part in a calculation The following instructions use direct addressing ADD
155. number of bytes to receive and RXDDONE is a flag that is set when all bytes are received 1 Disable the interrupts and the PTS Use the DI instruction to disable all standard interrupts and the DPTS instruction to disable the PTS 2 Set upthe stack pointer 3 Reset all interrupt mask registers Clear INT MASK INT_MASK land PI MASK 4 Initialize P2 0 to function as the EPAO input SCK and P2 3 to function as RXD Set P2 DIR bits 0 and 3 selects input Set P2 MODE selects special function Clear P2_MODE 3 selects LSIO function Set 2 REG bits 0 and 3 initializes and RXD input to 1 5 Initialize the PTSCB as shown in Table 5 14 Table 5 14 SSIO Receive Mode PTSCBs PTSCB1 PTSCB2 PTSVEC H pointer to PTSCB2 Unused PTSVEC L pointer to PTSCB2 SAMPTIME unused BAUD H unused DATA H unused BAUD L unused DATA L clear register to receive data EPAREG 1FH EPAO TIME PTSCON1 00H receive data on even PTS cycles EPAREG L 42H EPAO_TIME PORTMASK 08H P2 3 RXD PTSCON 32H SSIO receive mode PORTREG H 1FH P2_REG PTSCOUNT 10H 8 data bits x 2 PORTREG L D4H P2_REG 6 Enable EPAO interrupt Set INT MASK 2 7 Load the number of bytes to transmit into the user defined transmit count register 5 48 COUNT and clear the user defined reception done flag RXDDONE LD R COUNT 16 CLRB R
156. of the associated peripheral 7 0 1 MH 2x m 2 PIN1 7 0 2 5 Mx 6 5 4 2 PIN1 7 0 xz 7 MD PIN7 PIN6 PIN5 PIN4 2 PIN1 Bit Number E Function 7 0f PIN7 0 Port x Pin y Output To use Px y for output write the desired output data to this bit To use for input set this bit The bits shown as dashes are reserved for compatibility with future devices write zeros to these bits Table C 10 Px REG Addresses and Reset Values Register Address Reset Value P1 REG 8XC196MH 1F9DH FFH P2 REG 8 196 1FD4H FFH P3 REG 8XC196M x 1FFCH FFH P4 REG 8XC196Mx 1FFDH FFH P5 REG 8XC196MC MD 1FF5H FFH when pin is not driven P5 REG 8XC196MH 1FF5H FFH P7 REG 8XC196MD 1FD5H FFH C 34 intel REGISTERS MASK PI MASK Address 1FBCH Reset State AAH The peripheral interrupt mask register enables or disables masks interrupt requests associated with the peripheral interrupt the serial port interrupt SPI and the overflow underflow timer interrupt OVRTM 7 0 8XC196MC WG OVRTM2 OVRTM1 7 0 8XC196MD 5 WG OVRTM2 OVRTM1 7 0 8XC196MH SP1 SPO OVRTM2 OVRTM1 Function 7 5 3 1
157. on an address that is evenly divisible by 2 The value must be in the range of 00 FEH lreg A 32 bit register in the lower register file Must be aligned on an address that is evenly divisible by 4 The value must be in the range of 00 FCH preg A pointer register Must be aligned on an address that is evenly divisible by 4 The value must be in the range of 00 FCH Sbreg A byte register in the lower register file that serves as the source of the instruction operation Slregt A 32 bit register in the lower register file that serves as the source of the instruction operation Must be aligned on an address that is evenly divisible by 4 The value must be in the range of 00 FCH Swreg A word register in the lower register file that serves as the source of the instruction operation Must be aligned on an address that is evenly divisible by 2 The value must be in the range of 00 waop A word operand that is addressed by any addressing mode w2_reg A double word register in the lower register file Must be aligned on an address that is evenly divisible by 4 The value must be in the range of 00 FCH Although w2 reg is similar to reg there is a distinction w2 reg consists of two halves each containing a 16 bit address reg is indivisible and contains a 32 bit number wreg A word register in the lower register file When it could be unclear whether this variable refers to a source or a destination register it is prefixed with an S or a D M
158. output code versus input voltage the characteristic of the A D converter intel transfer function errors UART rejection wait state watchdog timer waveform generator WDT word WORD zero extension zero offset error GLOSSARY Errors inherent in an analog to digital conversion process quantizing error zero offset error full scale error differential nonlinearity and nonlinearity Errors that are hardware dependent rather than being inherent in the process itself include feedthrough repeatability channel to channel matching off isolation and rejection errors Universal asynchronous receiver and transmitter A part of the serial I O port The property of an A D converter that causes it to ignore reject changes in so that the actual characteristic is unaffected by those changes The effectiveness of Voc rejection is measured by the ratio of the change in to the change in the actual characteristic Time spent waiting for an operation to take place Wait states are added to external bus cycles to allow a slow memory device to respond to a request from the microcontroller An internal timer that resets the device if software fails to respond before the timer overflows One of the 8XC196Mx peripherals that can be used to produce pulse width modulated PWM outputs The waveform generator is optimized for controlling 3 phase AC induction motors brushless DC motors and ot
159. per shift 7 for 0 shift SHRL 7 1 per shift 8 for 0 shift Special Indirect Indexed Mnemonic Direct Immed Normal Autoinc Short Long CLRC 2 CLRVT 2 DI 2 EI 2 IDLPD Valid key 12 Invalid key 28 2 RST 4 uz SETC 2 SKIP 3 PTS Indirect Indexed Mnemonic Direct Immed Normal Autoinc Short Long DPTS 2 2 NOTE Thecolumn entitled Reg lists the instruction execution times for accesses to the register file or peripheral SFRs The column entitled Mem lists the instruction execution times for accesses to all memory mapped registers I O or memory See Table 4 1 on page 4 2 for address information A 57 intel B Signal Descriptions APPENDIX B SIGNAL DESCRIPTIONS This appendix provides reference information for the pin functions of the 8XC196MC 8XC196MD and 8XC196MH B 1 SIGNAL NAME CHANGES The names of some 8XC196MC and 8XC196MD signals have been changed for consistency with other MCS 96 microcontrollers Table B 1 lists the old and new names Table B 1 Signal Name Changes Name in 8XC196MC User s Manual New Name AGND ANGND CAPCOMPx EPAx COMPAREx COMPx 2 FUNCTIONAL GROUPINGS OF SIGNALS Tables B 2 B 3 and B 4
160. receive interrupt RD flag 7 16 selecting baud rate 7 12 7 14 SFRs 7 2 signals 7 2 status 7 15 7 16 transmit interrupt TI flag 7 16 See also mode 0 mode 1 mode 2 mode 3 port 2 Index 11 8XC196MC MD MH USER S MANUAL SJMP instruction A 2 A 36 A 41 A 47 A 49 A 55 SKIP instruction A 2 A 36 A 41 A 51 A 57 Slave programming mode 16 15 16 24 address command decoder routine 16 19 16 20 algorithm 16 19 16 24 circuit 16 16 dump word routine 16 19 16 23 entering 16 19 program word routine 16 19 16 21 security key programming 16 15 timings 16 22 16 24 Software addressing modes 3 9 conventions 3 9 3 11 device reset 13 12 interrupt service routines 5 19 linking subroutines 3 10 protection 3 11 trap interrupt 5 4 5 6 5 9 SP_STATUS 7 15 SPE bit 7 3 Special instructions A 51 A 57 Special operating modes SFRs 14 2 Special purpose memory 4 2 SPx bit 7 4 SPx_BAUD C 70 SPx_CON C 70 SPx_STATUS C 70 ST instruction A 2 A 37 A 45 A 49 A 55 Stack instructions A 49 A 54 Stack pointer 4 10 C 49 and subroutine call 4 10 initializing 4 11 Standard bus control mode decoding WRL and WRH 15 22 example system 15 23 signals 15 22 State time defined 2 8 STB instruction A 2 A 37 A 45 A 49 A 55 Sticky bit ST flag 3 4 A 4 A 5 A 21 A 22 SUB instruction A 3 A 37 A 42 A 47 A 52 SUBB instruction A 3 A 38 A 42 A 43 A 47 A 52 SUBC instruction A 3 A 38 A 44
161. required Five 100 us pulses required 8 MHz PPW VALUE 62 5 x 8 504 01F4H PPW VALUE 25 x 8 200 00C8H 16 MHz PPW VALUE 62 5 x 16 1000 PPW VALUE 25 x 16 400 0190 16 5 MODIFIED QUICK PULSE ALGORITHM Both the slave and auto programming routines use the modified quick pulse algorithm Figure 16 3 The modified quick pulse algorithm sends programming pulses to each OTPROM word location After the required number of programming pulses a verification routine compares the contents of the programmed location to the input data A verification error deasserts the PVER signal but does not stop the programming routine This process repeats until each OTPROM word has been programmed and verified Intel guarantees lifetime data retention for a device pro grammed with the modified quick pulse algorithm NOTE The 87C196MC MD devices use two pulses the 87C196MH uses five 16 9 8XC196MC MD MH USER S MANUAL From Auto or Slave Programming Start PPW Timer Write Data to OTPROM Enable Interrupts Enter Idle Mode Wait for PPW Timer Interrupt Required Writes Done Yes Compare Programmed Locations and Set Flags A0190 03 Figure 16 3 Modified Quick pulse Algorithm Auto programming repeats the pulse twice for the 87C196MC MD or five times for the 87 196 using the pulse width you specify in the external EPROM Slave mode
162. sese emen 15 4 Register Settings for Configuring External Memory Interface Signals 15 5 BUSWIDTH Signal Timing Definitions eee 15 13 READY Signal Timing Definitions mm mIIe9 20 5 1 enne enne enne esent nenne 15 21 AC Timing Symbol Definitions esses eem 15 33 External Memory Systems Must Meet These Specifications 15 33 Microcontroller Meets These 15 34 xvii 8XC196MC MD MH USER S MANUAL intel Table 16 1 16 2 16 3 16 4 16 5 16 6 16 7 16 8 16 9 16 10 16 11 16 12 16 13 A 1 A 1 A 3 A 4 A 6 A 7 A 9 B 1 B 3 B 4 B 6 B 7 B 8 B 9 2 C 3 C 5 C 6 C 8 C 9 C 10 11 12 xviii TABLES Page 87C196Mx OTPROM Memory 16 3 Memory Protection for Normal Operating 16 4 Memory Protection Options for Programming Modes 16 5 UPROM Programming Values and Locations for Slave 16 7 Example PPW VALUE 2 16 9 Pin Descriptions ete cereo iesu PMO pE Vall6 5 nec ate ha e b RERO IE RUPEE 16 13 Device Signature Word and Programming
163. sth na ta 5 30 Block Transfer Mode PTSCB 5 30 A D Scan Mode Command Data Table sse een 5 34 Command Data Table Example 1 15 36 A D Scan Mode PTSCB Example 1 esee emen 5 36 Command Data Table Example 2 eene eee OL A D Scan Mode PTSCB Example 2 emn 5 37 SSIO Transmit Mode 5 8 45 SSIO Receive Mode 5 5 48 ASIO Transmit Mode 5558 ASIO Receive Mode 5 56 Device ae Der 6 1 Standard Input only Port eem enne 6 2 Input only Port 6 3 Bidirectional Port Pins aciei tret Poder esie unde EEEa 6 5 Bidirectional Port Control and Status Registers 1 6 6 Logic Table for Bidirectional Ports in 6 9 Logic Table for Bidirectional Ports in Special function Mode 6 9 intel CONTENTS Table 6 8 6 10 6 11 6 12 6 13 6 14 6 15 7 1 7 2 7 3 8 1 9 1 9 2 9 4 9 5 10 1 10 2 10 3 10 4 11 1 11 2 11 3
164. that of the XCHB breg destination byte operand SAVON 00010100 baop breg direct DEST lt gt SRC 00011011 baop breg indexed PSW Flag Settings Z N C V ST XOR LOGICAL EXCLUSIVE OR WORDS XORs DEST SRC the source word operand with the destination yor wreg waop word operand and stores the result in the destination operand The result has ones in 100001 waop wreg the bit positions in which either operand but not both had a 1 and zeros in all other bit positions DEST lt DEST XOR SRC PSW Flag Settings Z N C V VT ST 0 0 XORB LOGICAL EXCLUSIVE OR BYTES XORs DEST SRC the source byte operand with the destination breg baop byte operand and stores the result in the destination operand The result has ones 100101 breg the bit positions in which either operand but not both had a 1 and zeros in all other bit positions DEST lt DEST XOR SRC PSW Flag Settings Z N C V VT ST 0 0 40 intel INSTRUCTION SET REFERENCE Table A 7 lists the instruction opcodes in hexadecimal order along with the corresponding in struction mnemonics Table A 7 Instruction Opcodes Hex Code Instruction Mnemonic 00 SKIP 01 CLR 02 NOT 03 NEG 04 XCH Direct 05 DEC 06 EXT 07 INC
165. that you use the conventions adopted by the C programming language for procedure linkage These standards are usable for both the assembly language and C programming environments and they offer compat ibility between these environments 3 4 4 Using Registers The 256 byte lower register file contains the CPU special function registers and the stack pointer The remainder of the lower register file and all of the upper register file is available for your use Peripheral special function registers SFRs and memory mapped SFRs reside in higher memory The peripheral SFRs can be windowed into the lower register file for direct access Memory mapped SFRs cannot be windowed you must use indirect or indexed addressing to access them All SFRs can be operated on as BYTEs or WORDs unless otherwise specified See Special function Registers SFRs on page 4 4 and Register File on page 4 9 for more information 8XC196MC MD MH USER S MANUAL intel To use these registers effectively you must have some overall strategy for allocating them The C programming language adopts a simple effective strategy It allocates the eight bytes beginning at address ICH as temporary storage and treats the remaining area in the register file as a segment of memory that is allocated as required NOTE Using any SFR as a base or index register for indirect or indexed operations can cause unpredictable results because external events can change the contents o
166. the top of the stack and the next return address moves to the top of the stack 4 10 intel MEMORY PARTITIONS Your program must load a word aligned even address into the stack pointer Select an address that is two bytes greater than the desired starting address because the CPU automatically decre ments the stack pointer before it pushes the first byte of the return address onto the stack Remem ber that the stack grows downward so allow sufficient room for the maximum number of stack entries The stack must be located in either the internal register file or external RAM The stack can be used most efficiently when it is located in the register file The following example initializes the top of the upper register file 8 196 MD as the stack For the 8XC196MH the immediate value would be 300H LD SP 200H Load stack pointer The following example shows how to allow the linker locator to determine where the stack fits in the memory map that you specify LD SP STACK 4 1 6 3 CPU Special function Registers SFRs Locations 0000 0017 in the lower register file are the CPU SFRs Table 4 8 Appendix de scribes the CPU SFRs Table 4 8 CPU SFRs Address High Odd Byte Low Even Byte 0016H Reserved Reserved 0014H Reserved WSR 0012H INT_MASK1 INT_PEND1 0010H Reserved Reserved 000 Reserved Reserved 000 Reserved Reserved 000 Reserved WAT
167. the A D conver sion complete interrupt is generated the A D scan mode routine begins The PTS reads the com mand in location 3000H and stores it in a temporary location Then it increments PTSPTR 1 twice and stores the value of the AD_RESULT register in location 3002H The final step is to copy the conversion command from the temporary location to the AD COMMAND register The CPU could process or move the conversion results data from the table before the next conversion com pletes and a new PTS cycle begins When the next cycle begins PTSPTR1 again points to 3000H and the repeats the events of the first cycle The value of the RESULT register is written to location 3002H and the command at location 3000H is re executed 5 6 6 Serial I O Modes The 8XC196MH has a two channel serial I O port The 8XC196MC and MD have no serial I O ports but the serial I O modes of the PTS provide a software serial I O channel for both synchro nous and asynchronous transfers and receptions There are four basic modes of operation syn chronous transmit synchronous receive asynchronous transmit and asynchronous receive A standard I O port signal is configured to function as either the transmit data TXD or receive data RXD signal and an EPA channel sets the baud rate You may configure any port 2 signal MC and MD or P7 3 0 MD as TXD or RXD In the synchronous modes an EPA channel can either generate the serial clock SCK signal or input an external c
168. the device must either enter idle mode or execute code from external memory An access to OTPROM would abort the current programming cycle Each programming cycle begins when a word is written to the OTPROM and ends when the next OTPROM access occurs Each word requires a total of five programming cycles each of which must be approximately 100 us in duration Figure 16 15 is a run time programming example It performs five programming cycles for each word After each programming cycle the code causes the device to enter idle mode 16 32 intel PROGRAMMING THE NONVOLATILE MEMORY The calling routine must pass two parameters to this routine the data to be programmed in DATA TEMP and the address in ADDR TEMP PROGRAM PUSHA LD WSR 7BH LD COUNT 5 ANDB INT_PEND CLEAR_EPAO ENABLE_EPAO _ EPAO_TIMER LD TEMPO TIMER1 ADD EPAO_TIME TEMPO PGM_PULSE ST DATA_TEMP ADDR_TEMP IDLPD 1 DJNZ COUNT LOOP POPA RET EPAO_ISR RET 1 PSW WSR INT_MASK INT MASK1 select 32 byte window with _ set up for 5 programming cycles clear EPAO pending bit enable EPAO interrupt set up EPAO as software timer load TIMER1 value into TEMPO load EPAO TIME with TIMER1 PULSE enable unmasked interrupt EPAO Store passed data at passed address enter idle mode decrement COUNT and loop if not 0 to complete 5 progra
169. the receive shift register to shift in whatever data is present on the RXDx pin This data is treated as the least significant bit LSB of the reception The reception then continues in the normal synchronous manner but the data received is shifted left by one bit because of the false LSB The seventh data bit transmitted is received as the most significant bit MSB and the transmitted MSB is never shifted into the receive shift register Using XTALI at 16 MHz the maximum baud rates are 2 76 Mbaud SPx BAUD 8002H or 0002H for mode 0 and 1 0 Mbaud for modes 1 2 and 3 Table 7 3 shows the SPx BAUD values for common baud rates when using 16 MHz XTALI clock input Because of rounding the BAUD VALUE formula is not exact and the resulting baud rate is slightly different than desired Table 7 3 shows the percentage of error when using the sample SPx BAUD values In most cases a serial link will work with up to a 5 0 difference in the receiving and transmitting baud rates Table 7 3 SPx BAUD Values When Using XTAL1 at 16 MHz SPx BAUD Register Value Error Baud Rate Mode 0 Mode 1 2 3 Mode 0 4 Mode 1 2 3 9600 8340H 8067H 0 04 0 16 4800 8682H 80CFH 0 02 0 16 2400 8D04H 81A0H 0 01 0 08 1200 8340H 0 0 04 300 E82BH 8D04H 0 0 01 Bit 15 is always set when XTAL 1 is selected as the clock source for the baud rate generator 7 4 44 Enabling the Serial Port Interrupts Each serial port channel has
170. then bit 7 RB8 is the received parity error RPE flag 7 3 2 4 Mode 2 and 3 Timings Operation in modes 2 and 3 is similar to mode 1 operation The only difference is that the data consists of 9 bits so 11 bit packages are transmitted and received During a reception the RI flag and the RIx interrupt pending bit are set just after the end of the stop bit During a transmission the TI flag and the TIx interrupt pending bit are set at the beginning of the stop bit The ninth bit can be used for parity or multiprocessor communications 7 3 2 5 Multiprocessor Communications Modes 2 and 3 are provided for multiprocessor communications In mode 2 the serial port sets the RIx interrupt pending bit only when the ninth data bit is set In mode 3 the serial port sets the RIx interrupt pending bit regardless of the value of the ninth bit The ninth bit is always set in address frames and always cleared in data frames One way to use these modes for multiprocessor communication is to set the master processor to mode 3 and the slave processors to mode 2 When the master processor wants to transmit a block of data to one of several slaves it sends out an address frame that identifies the target slave Be cause the ninth bit is set an address frame interrupts all slaves Each slave examines the address byte to check whether it is being addressed The addressed slave switches to mode 3 to receive the data frames while the slaves that are not addressed r
171. timer and selects the bus timing mode Two of its bits combine with three bits of CCRO to control wait states and bus width WDE BW1 IRC2 0 Bit Number Bit Mnemonic Function IRC2 Ready Control This bit along with IRCO CCRO 4 IRC1 CCRO 5 and the READY pin determine the number of wait states that can be inserted into the bus cycle While READY is held low wait states are inserted into the bus cycle until the programmed number of wait states is reached If READY is pulled high before the programmed number of wait states is reached no additional wait states will be inserted into the bus cycle IRC2 IRCO zero wait states illegal illegal one wait state two wait states three wait states infinite If you choose the infinite wait states option you must keep P5 6 configured as the READY signal Also be sure to add external hardware to count wait states and pull READY high within a specified time Otherwise a defective external device could tie up the address data bus indefinitely gt 0 0 Reserved for compatibility with future devices write zero to this bit The CCRs are loaded with the contents of the chip configuration bytes CCBs after reset unless the microcontroller is entering programming modes see Entering Programming Modes on page 16 13 in which case the programming chip configur
172. times for external stack usage or 71 state times for internal stack usage Therefore a single capture compare channel can be updated every 125 state times assuming internal stack usage 54 71 Each PWM period requires two updates one setting and one clearing so the execution time for a PWM period equals 250 state times When the input frequency on XTAL 1 is 16 MHz the PWM period is 31 25 us and the maximum PWM frequency is 32 kHz 11 4 2 2 Generating the Highest speed PWM Output You can generate a highest speed pulse width modulated output with a pair of EPA channels and a dedicated timer counter The first channel toggles the output when the timer value matches EPAx TIME and at some later time the second channel toggles the output again and resets the timer counter This restarts the cycle No interrupts are required resulting in the highest possible speed Software must calculate and load the appropriate EPAx TIME values and load them at the correct time in the cycle in order to change the frequency or duty cycle 11 14 intel EVENT PROCESSOR ARRAY EPA With this method the resolution of the EPA selected by the TxCONTROL registers see Figure 11 8 on page 11 16 and Figure 11 9 on page 11 17 determines the maximum PWM output fre quency Resolution is the minimum time required between consecutive captures or compares When the input frequency on XTALI is 16 MHz a 250 ns resolution results in a maximum PWM of 4 MHz 11 5 P
173. to PTSCB2 SAMPTIME 01H BAUD H 01H DATA H 00H clear register to receive data BAUD L AOH DATA L clear register to receive data EPAREG H 1FH EPAO_TIME PTSCON1 60H enable odd parity L 42H EPAO_ TIME PORTMASK 01H P2 0 RXD PTSCON 21H SSIO receive mode majority PORTREG H 1FH P2_PIN sampling PTSCOUNT OAH receive 8 data bits 1 parity bit PORTREG L D6H P2 PIn 10 5 56 Enable EPAO interrupt Set INT_MASK 2 Load the number of bytes to transmit into the user defined transmit count register COUNT and clear the user defined reception done flag RXDDONE LD R COUNT 16 CLRB RXDDONE Select PTS service for EPAO Set PTSSEL 2 Set up EPAO to capture on falling edges Set EPAO_CON 4 Figure 11 10 on page 11 19 11 12 1 tal STANDARD AND PTS INTERRUPTS Enable the PTS and conventional interrupts Use the EI instruction to enable all standard interrupts and the EPTS instruction to enable the PTS Toggle the RXD input to start the reception The EPA will generate a conventional interrupt This interrupt service routine should be the same as the end of PTS rountine The service routine can determine if this is a start reception interrupt or a end of PTS interrupt by reading the register If the register is set to capture mode then this
174. to be driven out by each pin to the corresponding bit of Px_REG When a pin is configured as standard I O Px_MODE y 0 the result of a CPU write to Px_REG is immediately visible on the pin When a pin is configured as a special function signal Px_MODE y 1 the associated on chip peripheral or off chip component controls the pin The CPU can still write to Px_REG but the pin is unaffected until it is switched back to its standard function This feature allows software to configure a as standard I O clear Px_MODE y initialize or overwrite the pin value then configure the pin as a special function signal set Px MODE y In this way initialization fault recovery exception handling etc can be done without changing the operation of the associated peripheral 14 2 REDUCING POWER CONSUMPTION Both power saving modes conserve power by disabling portions of the internal clock circuitry Figure 14 1 The following paragraphs describe both modes in detail 14 8 8XC196MC MD MH USER S MANUAL intel Disable Clock Input Powerdown FXTALI Divide by two Circuit Disable Clocks Powerdown XTAL2 Peripheral Clocks PH1 PH2 Jerkour CPU Clocks PH1 PH2 Clock Disable Generators Oscillator Powerdown Disable Clocks Idle Powerdown NOTE The CLKOUT pin is unique to the 8XC196MC and MD A3115 02 Figure 14 1 Clock Control During Power saving Mod
175. to output valid data after RD is asserted py When INST is asserted it indicates that the read operation is an instruc tion fetch For 16 bit write cycles the bus controller drives WR low then puts data onto the bus The rising edge of WR signifies that data is valid At this time the external system must latch the data 15 14 INTERFACING WITH EXTERNAL MEMORY CLKOUT Pe o OS Nom Valid gt BUSWIDTH AD15 0 read Address Out RD INST AD15 0 Address Out Data Out write WR CLKOUT pin is available only on the 8XC196MC MD Figure 15 6 Timings for 16 bit Buses A3163 01 15 15 8XC196MC MD MH USER S MANUAL intel 15 3 3 8 bit Bus Timings When the microcontroller is configured to operate in the 8 bit bus mode lines AD7 0 form a mul tiplexed lower address and data bus Lines AD15 8 are not multiplexed the upper address is latched and remains valid throughout the bus cycle Figure 15 7 shows an idealized timing dia gram for the external read and write cycles One cycle is required for an 8 bit read or write A 16 bit access requires two cycles The first cycle accesses the lower byte and the second cycle ac cesses the upper byte Except for requiring an extra cycle to write the bytes separately the timings are the same as on the 16 bit bus The ALE signal is used to demultiplex the lower address by strobing a transparent latch such as a 74AC3
176. to the sample capacitor of an A D converter Any member of the set consisting of the positive and negative whole numbers and zero A 16 bit signed variable with values from ea through 4205 1 The module responsible for handling interrupts that are to be serviced by interrupt service routines that you provide Also called the programmable interrupt controller PIC The total delay between the time that an interrupt is generated not acknowledged and the time that the device begins executing the interrupt service routine or PTS routine A software routine that you provide to service a standard interrupt See also PTS routine A location in special purpose memory that holds the starting address of an interrupt service routine See interrupt service routine See differential nonlinearity and nonlinearity A 32 bit signed variable with values from 2931 through 231 1 intel LSB maskable interrupts monotonic MSB n channel FET n type material no missing codes nonlinearity GLOSSARY 1 Least significant bit of a byte or least significant byte of a word 2 In an A D converter the reference voltage divided by 2 where n is the number of bits to be converted For a 10 bit converter with a reference voltage of 5 12 volts one LSB is equal to 5 0 millivolts 5 12 210 interrupts except unimplemented opcode software trap and NMI Maskable interrupts can be disabled masked by the individual
177. usual 16 bit addressing The lower register file locations that are covered by the window are always accessible by indirect or indexed operations To re enable direct access to the entire lower register file clear the WSR To enable direct access to a particular location in the lower register file you can select a smaller window that does not cover that location When windowing is enabled a register direct instruction that uses an address within the lower register file actually accesses the window in the upper register file an indirect indexed or zero register instruction that uses an address within either the lower register file or the upper register file accesses the actual location in memory The following sample code illustrates the difference between register direct and indexed address ing when using windowing PUSHA LDB WSR 12H pushes the contents of WSR onto the stack select window 12H a 128 byte block The next instruction uses register direct addr mem word 40H mem word 40H mem word 380H The next two instructions use indirect addr mem word 40H mem word 40H mem word 80H 0 mem word 40H mem word 40H mem word 380H 0 reloads the previous contents into WSR ADD 40H 80H ADD 40H 80H 0 ADD 40H 380H 0 POPA 0 4 44 44 04 4 19 intel Standard and PTS Interrupts intel CHAPTER 5 STANDARD AND PTS INTERRUPTS This chapter describes the interrupt control circuitry pr
178. value in immediate addressing mode Chapter 3 Programming Considerations describes the operand types and addressing modes 8XC196MC MD MH USER S MANUAL Table A 1 Opcode Map Left Half intel Opcode x0 x1 x2 x3 x4 x5 x6 x7 ox SKIP CLR NOT NEG XCH DEC EXT INC di Ay CLRB NOTB NEGB XCHB DECB EXTB INCB di SJMP 2x JBC bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 AND ADD di im in ix di im in ix 5x ANDB ADDB di im in ix di im in ix 6x AND 2 ADD 2 di im in ix di im in ix 7 ANDB 2 ADDB 2 di im in ix di im in ix OR XOR 8x di im in ix di im in ix ORB XORB 9x 2 in ix di im in ix LD ADDC Ax di im in ix di im in ix LDB ADDCB Bx di im in ix di im in ix Cx ST BMOV STB CMPL STB di in ix di in ix Dx JNST JNH JGT JNC JNVT JNV JGE JNE BR Ex DJNZ DJNZW in LJMP i F i RET PUSHF POPF PUSHA POPA IDLPD TRAP NOTE The first digit of the opcode is listed vertically and the second digit is listed horizontally The A 2 related instruction mnemonic is shown at the intersection of the two digits Shading indicates reserved opcodes If the CPU attempts to execute an unimplemented opcode an interrupt occurs For more information see Unimplemented Opcode on page 5 6 INSTRUCTION
179. variables that are used in Table A 6 to represent the instruction operands Table A 5 Operand Variables Variable Description aa A 2 bit field within an opcode that selects the basic addressing mode used This field is present only in those opcodes that allow addressing mode options The field is encoded as follows 00 register direct 01 immediate 10 indirect 11 indexed baop A byte operand that is addressed by any addressing mode bbb A 3 bit field within an opcode that selects a specific bit within a register bitno A 3 bit field within an opcode that selects one of the eight bits in a byte breg A byte register in the internal register file When it could be unclear whether this variable refers to a source or a destination register it is prefixed with an S or a D The value must be in the range of 00 FFH cadd An address in the program code Dbreg A byte register in the lower register file that serves as the destination of the instruction operation disp Displacement The distance between the end of an instruction and the target label Dlregt A 32 bit register in the lower register file that serves as the destination of the instruction operation Must be aligned on an address that is evenly divisible by 4 The value must be in the range of 00 FCH Dwreg A word register in the lower register file that serves as the destination of the instruction operation Must be aligned
180. width modulated PWM outputs Chapter 12 Analog to digital A D Converter provides an overview of the analog to digital A D converter and describes how to program the converter read the conversion results and interface with external circuitry Chapter 13 Minimum Hardware Considerations describes options for providing the ba sic requirements for device operation within a system discusses other hardware considerations and describes device reset options Chapter 14 Special Operating Modes provides an overview of the idle powerdown and on circuit emulation ONCE modes and describes how to enter and exit each mode Chapter 15 Interfacing with External Memory lists the external memory signals and de scribes the registers that control the external memory interface It discusses the bus width and memory configurations the bus hold protocol write control modes and internal wait states and ready control Finally it provides timing information for the system bus Chapter 16 Programming the Nonvolatile Memory provides recommended circuits the corresponding memory maps and flow diagrams It also provides procedures for auto program ming Appendix A Instruction Set Reference provides reference information for the instruction set It describes each instruction defines the processor status word PSW flags shows the rela tionships between instructions and PSW flags and lists hexadecimal op
181. with code Figure 5 16 shows the PTS control block for single transfer mode 5 27 8XC196MC MD MH USER S MANUAL intel PTS Single Transfer Mode Control Block In single transfer mode the PTS control block contains a source and destination address PTSSRC and PTSDST a control register PTSCON and a transfer count PTSCOUNT 7 0 Unused 0 0 0 0 0 0 0 0 7 0 Unused 0 0 0 0 0 0 0 0 15 8 PTSDST H PTS Destination Address high byte 7 0 PTSDST L PTS Destination Address low byte 15 8 PTSSRC H PTS Source Address high byte 7 0 PTSSRC L PTS Source Address low byte 7 0 PTSCON M2 M1 Mo Bw 50 DU 5 DI 7 0 PTSCOUNT Consecutive Byte or Word Transfers Register Location Function PTSDST PTSCB 4 PTS Destination Address Write the destination memory location to this register A valid address is any unreserved memory location however it must point to an even address if word transfers are selected PTSSRC PTSCB 2 PTS Source Address Write the source memory location to this register A valid address is any unreserved memory location however it must point to an even address if word transfers are selected 5 28 Figure 5 16 PTS Control Block Single Transfer Mode intel STANDARD AND PTS INTERRUPTS PTS Single Transfer Mode Control Block Continued Register Location Function
182. with their windowed direct addresses 4 16 intel 4 2 2 5 MEMORY PARTITIONS Using the Linker Locator to Set Up a Window In this example the linker locator is used to set up a window The linker locator locates the win dow in the upper register file and determines the value to load in the WSR for access to that win dow Please consult the manual provided with the linker locator for details modl modl module main public functionl extrn WSR wsr equ 14h byte sp equ 18h word oseg varl dsw 1 var2 dsw 1 var3 dsw 1 cseg functionl push wsr ldb wsr WSR add varl var2 var3 ldb wsr sp add sp 2 ret end Main module for linker Must declare WSR as external Allocate variables in an overlayable segment Prolog code for wsr Prolog code for wsr Use the variables as registers Epilog code for wsr Epilog code for wsr mod2 public function2 extrn WSR wsr equ 14h byte sp equ 18h word oseg varl dsw 1 var2 dsw 1 var3 dsw 1 cseg function2 push wsr Prolog code for wsr 4 17 8XC196MC MD MH USER S MANUAL ldb wsr WSR Prolog code for wsr add varl var2 var3 ldb wsr sp Epilog code for wsr add sp 2 Epilog code for wsr ret end The following is an example of a linker invocati
183. 0 0 X 0 X 0 Generate interrupt only software timer X 1 0 1 X X X X Clear output pin X 1 1 0 X X X X Set output pin X 1 1 1 X X X X Toggle output pin X 1 X X X X 0 1 Reset reference timer X 1 X X X X 1 1 Reset opposite timer X 1 X X X 1 X X Start A D conversion EPA1 3 5 or reload waveform generator 2 4 NOTES 1 bitis not used 2 X bit may be used but has no effect on the described operation These bits cause other operations to occur 11 18 intel EVENT PROCESSOR ARRAY EPA EPAx CON Address See Table 11 3 on page 11 3 x 0 1 8XC196MH Reset State 00H X 0 3 8XC196MC x 0 5 8XC196MD The EPA control EPAx CON registers control the functions of their assigned capture compare channels 7 0 x 0 2 4 TB CE M1 0 RE WGR ROT ON RT 7 0 x 1 3 5 TB CE M1 0 RE AD ROT ON RT Bit Bit Function Number Mnemonic 7 TB Time Base Select Specifies the reference timer 0 timer 1 is the reference timer and timer 2 is the opposite timer 1 timer 2 is the reference timer and timer 1 is the opposite timer A compare event reloading the waveform generator starting an A D conversion clearing setting or toggling an output pin and or resetting either timer occurs when the reference timer matches the time programmed in the event time register When a capture event falling edge rising edge or an edge change on the EPAx pin occurs the referenc
184. 0 selects special function Clear P2 MODE selects LSIO function Set P2 REG bits 0 and 2 initializes and SCK outputs to 1 5 Initialize and enable the timer Select up counting internal clock and prescaler disabled Set TICONTROL bits 6 and 7 Figure 11 8 on page 11 16 6 Initialize the PTSCB as shown in Table 5 13 5 44 intel STANDARD AND PTS INTERRUPTS Table 5 13 SSIO Transmit Mode PTSCBs PTSCB1 PTSCB2 PTSVEC H pointer to PTSCB2 Unused PTSVEC L pointer to PTSCB2 SAMPTIME unused BAUD H 00H 9600 baud at 16 MHz DATA H unused BAUD L DOH 9600 baud at 16 MHz DATA L nnH 8 data bits EPAREG H 1FH EPAO TIME PTSCON1 02H transmit data on odd PTS cycles EPAREG L 42H EPAO TIME PORTMASK 04H P2 2 TXD PTSCON 72H SSIO transmit mode PORTREG H 1FH P2 REG PTSCOUNT 10H 8 data bits x 2 PORTREG L D4H P2 REG 7 Enable EPAO interrupt Set INT MASK 2 8 Load the number of bytes to transmit into the user defined transmit count register T COUNT and clear the user defined transfer done flag TXDDONE LD T COUNT 16 TXDDONE 9 Select PIS service for EPAO Set PTSSEL 2 10 Set up EPAO as a compare only channel Set EPAO_CON 6 Figure 11 10 on page 11 19 11 Start the operation of the EPAO channel by writing the time of the first interrupt to EPAO_TIME To set up the corre
185. 0 5 7 C 1 8XC196MC MD MH USER S MANUAL Table C 2 Register Name Address and Reset Status tel Binary Reset Value Register Name AD_COMMAND A D Command 1FAC 1000 0000 AD_RESULT MC MD 1111 1111 1100 0000 AD_RESULT MH Tort 1100 0000 AD_TEST MC MD 1100 0000 AD_TEST MH A D Test 1FAE 1000 AD_TIME A D Time 1FAF 1111 1111 CCRO Chip Configuration 0 ttt XXXX XXXX CCR1 Chip Configuration 1 ttt XXXX XXXX COMPO CON EPA Compare 0 Control 1F58 0000 0000 COMP1 CON EPA Compare 1 Control 1F5C 0000 0000 COMP2 CON EPA Compare 2 Control 1F60 0000 0000 CON MC MD 1F64 COMP3 CON MH EPA Compare 3 Control 0000 0000 COMP4_CON MD EPA Compare 4 Control 1F68 0000 0000 5_ MD EPA Compare 5 Control 1F6C 0000 0000 COMPO TIME EPA Compare 0 Time 1F5A XXXX XXXX COMP1 TIME EPA Compare 1 Time 1F5E XXXX XXXX XXXX COMP2 TIME EPA Compare 2 Time 1F62 XXXX XXXX XXXX XXXX COMPS TIME MC MD 1F66 COMP3 TIME MH EPA Compare 3 Time COMP4_TIME MD EPA Compare 4 Time 1F6A COMP5_TIME MD EPA Compare 5 Time 1F6E XXXX XXXX XXXX _ EPA Capture Comp 0 Control 1F40 0000 0000 EPA1_CON EPA Capture Comp 1 Control 1F44 0000 0000 EPA2
186. 0 7 12 1 8XC196MD 84 16 488 64 12 0 9 14 1 8XC196MD 80 16 488 64 12 0 9 14 1 NOTES 1 Nonvolatile memory is optional The second character of the device name indicates the presence and type of nonvolatile memory 80C196Mx 83C196Mx ROM 87C196Mx OTPROM 2 Register RAM amounts include the 24 bytes allocated to core SFRs and the stack pointer 3 The 8XC196MC and 8XC196MD have no serial I O ports but have PTS modes that allow asynchro nous or synchronous serial communication 4 The number of PWM channels includes the outputs from the PWM peripheral and the waveform gen erator For the 8XC196MD it also includes the output from the frequency generator 2 3 FUNCTIONAL OVERVIEW Figure 2 1 shows the major blocks within the microcontroller The core of the microcontroller Figure 2 2 consists of the central processing unit CPU and memory controller The CPU con tains the register file and the register arithmetic logic unit RALU A 16 bit internal bus connects the CPU to both the memory controller and the interrupt controller An extension of this bus con nects the CPU to the internal peripheral modules In addition an 8 bit internal bus transfers in struction bytes from the memory controller to the instruction register in the RALU 2 2 intel ARCHITECTURAL OVERVIEW Optional Interrupt Core p Clock and PTS Power Mgmt Note The frequency generator is uniqu
187. 0 7 Hz 1953 1 Hz 1FH 488 3 Hz 610 3 Hz 976 6 Hz 2FH 325 5 Hz 406 9 Hz 651 0 Hz 3FH 244 1 Hz 395 2 Hz 488 3 Hz 4FH 195 3 Hz 244 1 Hz 390 6 Hz 5FH 162 8 Hz 203 4 Hz 325 5 Hz 6FH 139 5 Hz 174 4 Hz 279 0 Hz 7FH 122 1 Hz 152 6 Hz 244 1 Hz 8FH 108 5 Hz 135 6 Hz 217 0 Hz 97 7 Hz 122 1 Hz 195 3 Hz 88 8 Hz 111 0 Hz 177 6 Hz 81 4 Hz 101 7 Hz 162 8 Hz 75 1 Hz 93 9 Hz 150 2 Hz 69 7 Hz 87 2 Hz 139 5 Hz EFH 65 1 Hz 81 4 Hz 130 2 Hz FFH 61 0 Hz 76 0 Hz 122 0 Hz 10 5 8XC196MC MD MH USER S MANUAL intel PWM PERIOD The PWM period PWM PERIOD register controls the period of the PWM outputs It contains a value that determines the number of state counts necessary for incrementing the PWM counter The value of PWM PERIOD is loaded into the PWM period count register whenever the count equals zero Address 1FB4H Reset State 00H 7 0 PWM Period Bit Number Function 7 0 PWM Period This register controls the period of the PWM outputs The value of PWM_PERIOD is loaded into the PWM period count register whenever the count equals zero Figure 10 3 PWM Period PWM_PERIOD Register 10 5 PROGRAMMING THE DUTY CYCLE The values written to the PWMx_CONTROL and PWM_PERIOD registers control the width of the high pulse effectively controlling the duty cycle The 8 bit value written to the control regis ter is loaded into a buffer and this value is used during th
188. 0 Setting a bit enables the corresponding interrupt C 25 8XC196MC MD MH USER S MANUAL INT_MASK1 intel INT_MASK1 Address Reset State 0013H 00H The interrupt mask 1 INT MASK1 register enables or disables masks individual interrupt requests The EI and DI instructions enable and disable servicing of all maskable interrupts INT MASK1 can be read from or written to as a byte register PUSHA saves this register on the stack and POPA The waveform generator and the EPA compare only channel 5 can generate this interrupt Write to to enable the interrupt sources read PEND to determine which source caused the interrupt SIO 0 and SIO 1 can generate this interrupt Write to to enable the interrupt sources read PI_PEND to determine which source caused the interrupt restores it 7 0 8XC196MC NMI EXTINT COMP3 EPA3 7 0 8XC196MD NMI EXTINT 5 4 4 7 0 8 196 SPI Ri RIO TH TIO Bit 7 Number Function 7 07 Setting a bit enables the corresponding interrupt The standard interrupt vector locations are as follows Bit Mnemonic Interrupt Standard Vector NMI Nonmaskable Interrupt 203EH EXTINT EXTINT pin 203CH MC MD Multiplexed Peripheral Interrupt 203AH WG Waveform Generator 203AH 5 MD
189. 0 and mode 4 Mode 0 is the syn chronous mode available on all the 8XC196 devices that have serial ports Mode 4 is an enhanced full duplex synchronous mode 7 3 1 1 Mode 0 The most common use of mode 0 is to expand the I O capability of the device with shift registers see Figure 7 2 In this mode the TXDx pin outputs a set of eight clock pulses while the RXDx pin either transmits or receives data Data is transferred eight bits at a time with the least signif icant bit first Figure 7 3 shows a diagram of the relative timing of these signals Note that only mode 0 uses RXDx as an open drain output Shift LOAD Clock Inhibit Shift Register 74HC165 Inputs Microcontroller Outputs Serial In A Shift Register 74HC164 Enable A0264 03 Figure 7 2 Typical Shift Register Circuit for Mode 0 In mode 0 RXDx must be enabled for receptions and disabled for transmissions See Program ming the Control Register on page 7 10 When RXDx is enabled either a rising edge on the RXDx input or clearing the receive interrupt RI flag in SPx STATUS starts a reception When RXDx is disabled writing to SBUFx TX starts a transmission Disabling RXDx stops a reception in progress and inhibits further receptions To avoid a partial or undesired complete reception disable RXDx before clearing the RI flag in SPx STATUS This can be handled in an interrupt environment by using software flags or in straig
190. 0 then PC lt 8 bit disp end if PSW Flag Settings Z N C V VT ST DJNZW DECREMENT AND JUMP IF NOT ZERO WORD Decrements the value of the word DJNZW wreg operand by 1 If the result is 0 control passes to the next sequential instruction If the result 11100001 wreg disp is not 0 the instruction adds to the program counter the offset between the end of this NOTE The displacement disp is sign instruction and the target label effecting the extended to 16 bits jump The offset must be in the range of 1 28 to 127 COUNT COUNT 1 if COUNT 0 then PC lt PC 8 bit disp end if PSW Flag Settings intel INSTRUCTION SET REFERENCE Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format DPTS DISABLE PERIPHERAL TRANSACTION SERVER PTS Disables the peripheral transaction server PTS PTS Disable PSW 2 lt 0 PSW Flag Settings DPTS 11101100 ENABLE INTERRUPTS Enables interrupts following the execution of the next statement Interrupt calls cannot occur immediately following this instruction Interrupt Enable PSW 1 lt 1 PSW Flag Settings El 11111011 EPTS ENABLE PERIPHERAL TRANSACTION SERVER PTS E
191. 08 SHR 09 SHL 0A SHRA 0B XCH Indexed 0C SHRL 00 SHLL SHRAL OF NORML 10 Reserved 11 CLRB 12 NOTB 13 NEGB 14 XCHB Direct 15 DECB 16 EXTB 17 INCB 18 SHRB 19 SHLB 1A SHRAB 1B XCHB Indexed 1C 1F Reserved 20 27 SJMP 28 2F SCALL 30 37 JBC 38 3 JBS 40 AND Direct 3 ops 41 AND Immediate 3 ops 42 AND Indirect 3 ops 43 AND Indexed 3 ops 44 ADD Direct 3 ops 41 8XC196MC MD MH USER S MANUAL Table A 7 Instruction Opcodes Continued lel Hex Code Instruction Mnemonic 45 ADD Immediate 3 ops 46 ADD Indirect 3 ops 47 ADD Indexed 3 ops 48 SUB Direct 3 ops 49 SUB Immediate 3 ops 4A SUB Indirect 3 ops 4B SUB Indexed 3 ops 4C MULU Direct 3 ops 4D MULU Immediate 3 ops 4E MULU Indirect 3 ops 4F MULU Indexed 3 ops 50 ANDB Direct 3 ops 51 ANDB Immediate 3 ops 52 ANDB Indirect 3 ops 53 ANDB Indexed 3 ops 54 ADDB Direct 3 ops 55 ADDB Immediate 3 ops 56 ADDB Indirect 3 ops 57 ADDB Indexed 3 ops 58 SUBB Direct 3 ops 59 SUBB Immediate 3 ops 5A SUBB Indirect 3 ops 5B SUBB Indexed 3 ops 5C MULUB Direct 3 ops 5D MULUB Immediate 3 ops 5E MULUB Indirect 3 ops 5F MULUB Indexed 3 ops 60 AND Direct 2 ops 61 AND Immediate 2 ops 62 AND Indirect 2 ops 63 AND Indexed 2 ops 64 ADD Direct 2 ops 65 ADD Immediate 2 o
192. 11 19 clock prescaler 11 16 11 17 compare channels programming 11 18 compare modules programming 11 18 controlling the clock source and direction 11 16 11 17 determining event status 11 24 enabling a timer counter 11 16 11 17 enabling the compare function 11 22 overruns 11 12 11 13 Index 3 8XC196MC MD MH USER S MANUAL re enabling the compare event 11 20 11 22 reloading the waveform generator 11 20 11 23 C 16 resetting the timer in compare mode 11 21 resetting the timers 11 21 11 23 selecting the capture compare event 11 19 selecting the compare event 11 22 selecting the time base 11 19 11 22 selecting up or down counting 11 16 11 17 signals 11 2 starting an A D conversion 11 20 11 23 C 16 See also port 1 port 6 PWM timer counters EPA compare control x register 11 22 C 15 EPA compare x time register C 17 EPA control x register 11 19 C 18 EPA time registers C 21 0 68 0 69 1 C 68 1 69 EPA2 69 EPA2 TIME 69 EPA3 CON C 69 EPA3 TIME C 69 EPA4 CON C 69 4 TIME C 69 5 0 11 2 B 16 5 CON 69 EPAS5 TIME C 69 EPTS instruction 5 13 A 15 A 45 A 51 A 57 ESD protection 6 3 6 7 13 5 Event processor array See EPA EXT instruction A 2 A 15 A 41 A 47 A 52 EXTB instruction 2 A 16 A 41 A 47 A 52 EXTINT 5 3 14 7 B 16 and idle mode 14 5 and powerdown mode 14 6 14 7
193. 16 16 18 21 19 22 19 22 20 23 MUL 2 ops 16 17 18 21 19 22 19 22 20 23 MUL 3 ops 16 17 18 21 19 22 19 22 20 23 MULB 2 ops 12 12 14 17 15 18 15 18 16 19 MULB 3 ops 12 12 14 17 15 18 15 18 16 19 MULU 2 ops 14 15 16 19 17 19 17 20 18 21 MULU 3 ops 14 15 16 19 17 19 17 20 18 21 MULUB 2 ops 10 10 12 15 13 15 12 16 14 17 MULUB 3 ops 10 10 12 15 13 15 12 16 14 17 Logical Indirect Indexed Mnemonic Direct Immed Normal Autoinc Short Long Reg Mem Reg Mem Reg Mem Reg Mem AND 2 ops 4 5 6 8 7 9 6 8 7 9 AND 3 ops 5 6 7 10 8 11 7 10 8 11 ANDB 2 ops 4 4 6 8 7 9 6 8 7 9 ANDB 3 ops 5 5 7 10 8 11 7 10 8 11 NEG 3 NEGB 3 NOT 3 NOTB 3 OR 4 5 6 8 7 9 6 8 7 9 ORB 4 4 6 8 7 9 6 8 7 9 XOR 4 5 6 8 7 9 6 8 7 9 XORB 4 4 6 8 9 6 8 7 9 NOTE Thecolumn entitled Reg lists the instruction execution times for accesses to the register file or peripheral SFRs The column entitled Mem lists the instruction execution times for accesses to all memory mapped registers I O or memory See Table 4 1 on page 4 2 for address information A 53 8XC196MC MD MH USER S MANUAL Table A 9 Instruction Execution Times in State Times Continued intel Stack Register Indirect Indexed Mnemonic Direct Immed Normal Autoinc Short Long
194. 16 7 reads the PBUS and transfers control to the program word or dump word routine based on the value of P3 0 A one on P3 0 selects the program word command and the remaining bits specify the address For example a PBUS value of 3501H programs a word of data at location 3500H A zero on P3 0 selects the dump word com mand and the remaining bits specify the address For example a PBUS value of 3500H places the word at location 3500H on the PBUS The program word routine Figure 16 8 checks the CCB security lock bits If either security lock bit CCB0 6 or CCBO 7 has been programmed you must provide a matching security key to gain access to the device Using the program word command write eight consecutive words to the de vice starting at location 2020H and continuing to 202FH The routine stores these eight words in an internal register and compares their value with the internal key If the keys match the routine allows you to program individual or sequential OTPROM locations otherwise the device enters an endless loop The dump word routine Figure 16 10 also checks the CCB security lock bits but it has no pro vision for security key verification If the lock bits are unprogrammed the routine fetches a word of data from the OTPROM and writes that data to the PBUS If either lock bit is programmed the routine performs a write cycle without first getting data from the OTPROM 16 19 8XC196MC MD MH USER S MANUAL intel PMODE 0
195. 1FH 00B4H t Must be addressed as a word C 69 8XC196MC MD MH USER S MANUAL WSR intel Table C 12 WSR Settings and Direct Addresses for Windowable SFRs Continued 32 byte Windows 64 byte Windows 128 byte Windows 00 0 0 00 0 0080 0 egister Mnemonic Location WSR Direct WSR Direct WSR Direct Address Address Address PWMO CONTROL 1FBOH 7DH OOFOH 3EH OOFOH 1FH 00B0OH PWM1 CONTROL 1FB2H 7DH 00 2 00 2 1FH 00B2H SBUFO RX MH 1F80H 7CH 00EO0H 3EH 00COH 1FH 0080H SBUF1 RX MH 1F88H 7CH 00 8 00C8H 1FH 0088H SBUFO TX MH 1F82H 7CH 00 2 00C2H 1FH 0082H SBUF1 TX MH 1F8AH 7CH 00 00 1 008 SPO BAUD 1F84H 7CH 00 4 00C4H 1FH 0084H SP1 BAUD 1F8CH 7CH 00 00CCH 1FH 008CH 5 0 CON MH 1F83H 7CH 00 00C3H 1FH 0083H SP1_CON MH 1F8BH 7CH 00 00CBH 1FH 008BH STATUS 1F81H 7CH 00 00C1H 1FH 0081H SP1_STATUS MH 1F89H 7CH OOE9H 3EH 00C9H 1FH 0089H T1CONTROL 1F78H 7BH 00 8 3DH 00F8H 1EH 00F8H T1RELOAD 1F72H 7BH 00 2 3DH 00 2 1EH 00F2H T2CONTROL 1F7CH 7BH OOFCH 3DH 00 1EH 00FCH TIMER1 1F7AH 7BH 00 3DH 00 1EH OOFAH TIMER2 1F7EH 7BH 00 3DH 00 1EH 00 WG_COMP1 1FC2H 7EH 00
196. 2 00C2H 1FH 00C2H WG_COMP2 1FC4H 7EH 00 4 00C4H 1FH 00C4H WG_COMP3 1FC6H 7EH 00 6 00C6H 1FH 00C6H WG CONTROL 1FCCH 7EH 00 00CCH 1FH 00CCH WG COUNTER 1FCAH 7EH OOEAH 3FH 00 1 00 WG_OUTPUT 1FCOH 7EH OOEOH 3FH 00COH 1FH 00COH WG PROTECT 1FCEH 7EH 00 00 1 00 WG_RELOAD 1FC8H 7EH 00 8 00C8H 1FH 00C8H Must be addressed as a word C 70 intel REGISTERS ZERO_REG ZERO REG Address 00H Reset State 0000H The two byte zero register ZERO REG is always equal to zero constant zero for comparisons and calculations It is useful as a fixed source of the 15 0 Zero Bit 2 Number Function 15 0 Zero This register is always equal to zero C 71 intel Glossary intel GLOSSARY This glossary defines acronyms abbreviations and terms that have special meaning in this man ual Chapter 1 discusses notational conventions and general terminology absolute error accumulator actual characteristic A D converter ALU assert attenuation bit BIT break before make byte BYTE The maximum difference between corresponding actual and ideal code transitions Absolute error accounts for all deviations of an actual A D converter from an ideal converter A register or storage location that forms the result of an arithmetic or logical operation A graph of output code v
197. 2 PSW Flag Settings 2 V VT ST DEST SRC1 SRC2 ADDB Dbreg Sbreg baop 010101aa baop Sbreg Dbreg ADDC ADD WORDS WITH CARRY Adds the source and destination word operands and the carry flag 0 or 1 and stores the sum into the destination operand DEST lt DEST SRC PSW Flag Settings 7 V ST DEST SRC ADDC wreg waop 101001aa waop wreg A 7 8XC196MC MD MH USER S MANUAL intel Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format ADDCB ADD BYTES WITH CARRY Adds the source DEST SRC and destination byte operands and the carry breg baop flag 0 or 1 and stores the sum into the destination operand 101101 baop breg DEST lt DEST SRC PSW Flag Settings Z N C V VT ST AND LOGICAL AND WORDS ANDs the source DEST SRC 2 operands and destination word operands and stores AND wreg waop the result into the destination operand The result has ones in only the bit positions in 011000aa waop wreg which both operands had a 1 and zeros in all other bit positions DEST lt DEST AND SRC PSW Flag Settings Z N C V VT ST 0 0 LOGICAL AND WORDS ANDs the two DEST SRC1 SRC2
198. 2 1 PH2 0 PH1 1 PH1 0 Humbet UM Function 10 PH3 2 Phase 3 Function Selects either the port function or the waveform generator output function for pins P6 4 WG3 and P6 5 WG3 0 P6 4 P6 5 1 WG3 WG3 9 PH2 2 Phase 2 Function Selects either the port function or the waveform generator output function for pins P6 2 WG2 and P6 3 WG2 0 P6 2 P6 3 1 WG2 WG2 8 PH1 2 Phase 1 Function Selects either the port function or the waveform generator output function for pins P6 0 WG1 and P6 1 WG1 0 P6 0 P6 1 1 WG12 WG1 7 P7 P6 7 PWM1 Value Write the desired P6 7 PWM1 value to this bit 6 P6 P6 6 PWMO Value Write the desired P6 6 PWMO value to this bit 5 4 1 0 P6 4 WG3 P6 5 WG3 Value Write the desired output values to these bits See Table 9 5 on page 9 12 3 2 PH2 1 0 P6 2 WG2 P6 3 WG2 Values Write the desired output values to these bits See Table 9 5 on page 9 12 1 0 PH1 1 0 P6 0 WG1 P6 1 WG1 Values Write the desired output values to these bits See Table 9 5 on page 9 12 Figure 9 8 WG Output Configuration WG OUTPUT Register Continued intel WAVEFORM GENERATOR 9 4 2 Controlling the Protection Circuitry and EXTINT Interrupt Generation The protection register Figure 9 9 controls the protection circuitry and EXTINT interrupt re quests WG_PROTECT Address 1FCEH Reset State MC MD FOH Reset State MH EOH The waveform protection register enables and disa
199. 2 Reading the Current Value of the Down counter sss 10 7 10 5 3 Enabling the PWM Outputs cete t eade 10 8 10 5 4 Generating Analog Outputs 10 10 CHAPTER 11 EVENT PROCESSOR ARRAY EPA 11 1 FUNCTIONAL 11 1 11 2 EPA AND TIMER COUNTER SIGNALS AND 11 2 11 8 TIMER COUNTER FUNCTIONAL 11 5 11 3 1 Cascade Mode Timer 2 Only seemed 11 3 2 Quadrature Clocking Modes 11 7 11 4 EPA CHANNEL FUNCTIONAL 11 9 11 4 1 Operating in Capture Mode sese emere ener 11 10 11 4 17 EPA OverrUns eee err Rr pe EU ER b cea ERE ERE dees 11 12 11 4 1 2 Preventing EPA Overruns sese 11 13 11 4 2 Operating in Compare 2 11 13 11 4 2 1 Generating a Low speed PWM Output seem 11 13 11 4 2 2 Generating the Highest speed PWM Output 11 14 11 5 PROGRAMMING THE EPA AND 11 15 11 5 1 Configuring the EPA and Timer Counter Signals 11 15 11 5 2 Programming the Timers 11 5 3 Programming the Capture Compare Channels
200. 3 BR Indirect 4 Reserved EC DPTS ED EPTS EE Reserved Note 1 EF LCALL A 45 8XC196MC MD MH USER S MANUAL Table A 7 Instruction Opcodes Continued Hex Code Instruction Mnemonic FO RET F2 PUSHF F3 POPF F4 PUSHA F5 POPA F6 IDLPD F7 TRAP CLRC F9 SETC FA DI FB EI FC CLRVT FD NOP FE DIV DIVB MUL MULB Note 2 FF RST NOTES 1 2 A 46 This opcode is reserved but it does not generate an unimplemented opcode interrupt Signed multiplication and division are two byte instructions For each signed instruction the first byte is FE and the second is the opcode of the corresponding unsigned instruction For example the opcode for MULU 3 operands direct is 4C so the opcode for MUL 3 oper ands direct is FE 4C intel INSTRUCTION SET REFERENCE Table A 8 lists instructions along with their lengths and opcodes for each applicable addressing mode A dash in any column indicates not applicable Table A 8 Instruction Lengths and Hexadecimal Opcodes Arithmetic Group 1 Direct Immediate Indirect cea Mnemonic Length Opcode Length Opcode Length Opcode pid Opcode ADD 2 ops 3 64 4 65 3 66 4 5 67 ADD 3 ops 4 44 5 45 4 46 5 6 47 ADD
201. 31 8XC196MC MD MH USER S MANUAL intel Table 16 13 PCCB and UPROM Programming Values Pins PCCB Programming UPROM Programming PMODE3 0 09H P4 7 0 FFH FFH P3 7 0 Data to be programmed in PCCB Value to program UPROM bits See CCR descriptions in Appendix C 04H to program DED only 08H to program DEI only OCH to program both DED and Assert PALE to begin programming The algorithm sends five programming pulses that write the port 3 data to the OTPROM then it compares the input data with the programmed data If the programming verifies the PVER signal lights the LED to indicate successful programming Oth erwise you can pulse PALE to repeat programming Complete the procedure by following the power down sequence page 16 14 NOTE The PCCB and UPROM programming modes are available only for the 8XC196MH device The pulse width is 200 pts at 8 MHz or 266 us at 6 MHz 16 11 RUN TIME PROGRAMMING You can program an OTPROM location during normal code execution To make the OTPROM array accessible apply voltage to EA while you reset the device Apply V pp voltage to the Vpp pin during the entire programming process Then simply write to the location to be pro grammed NOTE Programming either security lock bit in CCBO disables run time programming For details see Controlling Access to the OTPROM During Normal Operation on page 16 4 Immediately after writing to the OTPROM
202. 4 2048 19 0 INTO3 2006H 03 503 2046 18 EPA Capture Compare 0 02 2004 02 502 2044H 17 A D Conversion Complete AD_DONE INTO1 2002H 01 PTSO1 2042H 16 Timer 1 or 2 Overflow OVRTM INTOO 2000H 00 PTSOO 2040H 15 PTS service is not useful for multiplexed interrupts because the PTS cannot readily determine the source of these interrupts 5 5 8XC196MC MD MH USER S MANUAL intel 5 3 1 Special Interrupts This microcontroller has three special interrupt sources that are always enabled unimplemented opcode software trap and NMI These interrupts are not affected by the EI enable interrupts and DI disable interrupts instructions and they cannot be masked All of these interrupts are serviced by the interrupt controller they cannot be assigned to the PTS Of these three only NMI goes through the transition detector and priority encoder The other two special interrupts go di rectly to the interrupt controller for servicing Be aware that these interrupts are often assigned to special functions in development tools 5 3 1 1 Unimplemented Opcode If the CPU attempts to execute an unimplemented opcode an indirect vector through location 2012H occurs This prevents random software execution during hardware and software failures The interrupt vector should contain the starting address of an error routine that will not further corrupt an already erroneous situation T
203. 4 FE 7 4 FE 7D 4 FE 7E 5 6 FE 7F MULB 3 ops 5 FE 5 5 FE 5D 5 FE 5E 6 7 FE 5F MULU 2 ops 3 6C 4 6D 3 6E 4 5 6F MULU 3 ops 4 4 5 4 4 4E 5 6 4F MULUB 2 ops 3 7C 3 7D 3 7E 4 5 7F MULUB 3 ops 4 5C 4 5D 4 5E 5 6 5F Logical Direct Immediate Indirect Nee Mnemonic Length Opcode Length Opcode Length Opcode nh Opcode AND 2 ops 3 60 4 61 3 62 4 5 63 AND 3 ops 4 40 5 41 4 42 5 6 43 ANDB 2 ops 3 70 3 71 3 72 4 5 73 ANDB 3 ops 4 50 4 51 4 52 5 6 53 NEG 2 03 NEGB 2 13 NOT 2 02 NOTB 2 12 OR 3 80 4 81 3 82 4 5 83 ORB 3 90 3 91 3 92 4 5 93 XOR 3 84 4 85 3 86 4 5 87 XORB 3 94 3 95 3 96 4 5 97 NOTES 1 For indexed instructions the first column lists instruction lengths as S L where S is the short indexed instruction length and L is the long indexed instruction length 2 For the SCALL and SJMP instructions the three least significant bits of the opcode are concatenated with the eight bits to form an 11 bit two s complement offset A 48 intel INSTRUCTION SET REFERENCE Table A 8 Instruction Lengths and Hexadecimal Opcodes Continued Stack gt Indexed Direct Immediate Indirect Note 1 Mnemonic Length Length Opcode Length Opcode Length Opcode S L Opcode POP 2 CC 2 CE 3 4 CF POPA 1
204. 50 01 Figure 11 3 Quadrature Mode Interface Table 11 4 Quadrature Mode Truth Table TE i State TORAS Count Direction T 0 Increment Increment 0 2 Increment 1 T Increment 2 0 Decrement T 1 Decrement 0 al Decrement 1 Decrement intel EVENT PROCESSOR ARRAY EPA ckxour LI LILILILILILILILILILI I e all CLKOUT is available on the 8XC196MC and 8XC196MD only A1549 01 Figure 11 4 Quadrature Mode Timing and Count 11 4 EPA CHANNEL FUNCTIONAL OVERVIEW The EPA has both programmable capture compare and compare only channels Each cap ture compare channel can perform the following tasks The compare only channels have the same functionality except that they cannot capture an external event capture the current timer value when a specified transition occurs on the EPA pin start A D conversion or reload the waveform generator when an event is captured or the timer value matches the programmed value in the event time register clear set or toggle the EPA pin when the timer value matches the programmed value in the event time register generate an interrupt when a capture or compare event occurs reset its own base timer in compare mode reset the opposite timer in both compare and capture mode 8XC196MC MD MH USER S MANUAL intel Each EPA channel has a control register EPAx CON capture com
205. 5H Yes Read Data From PBUS Deassert CPVER No PVER Assert PVER a 20 1 Check Address Dump Word Routine Yes Program Word Routine Figure 16 7 Address Command Decoding Routine A0193 02 16 20 intel PROGRAMMING THE NONVOLATILE MEMORY Lock Bits Enabled Read Data Verify from PBUS Security Key Execute Modified Quick Pulse Algorithm then Return Loop Forever Programming No Deassert Verifies PVER P2 0 0 Assert PVER P2 0 1 Read Data from PBUS To Address Command Decoder Increment Address by 2 Deassert CPVER Assert PVER A0194 03 Figure 16 8 Program Word Routine 16 21 8XC196MC MD MH USER S MANUAL intel Figure 16 9 shows the timings of the program word command with a repeated programming pulse and auto increment Asserting PALE latches the command and address on the PBUS Asserting PROG latches the data on the PBUS and starts the programming sequence The PROG signal controls the programming pulse width Slave programming mode does not use the PPW regis ter After the rising edge of PROG the routine verifies the contents of the location that was just programmed and asserts PVER to indicate successful programming AINC is optional and can automatically increment the address for the next location If you do not use AINC you must send a new program word command to acc
206. 6 9 16 11 B 20 PWM 10 1 and cascading timer counters 11 7 block diagram 10 2 D A converter 10 10 duty cycle 10 4 enabling outputs 10 8 generating analog outputs 10 10 highest speed 11 14 low speed 11 7 11 13 overview 10 1 programming duty cycle 10 4 typical waveforms 10 4 with dedicated timer counter 11 14 PWM control x register 10 7 C 46 PWM count register 10 8 C 44 PWM period register 10 6 C 45 PWM1 0 B 20 INDEX Q Quadrature clocking 11 7 Quick reference guides ordering 1 8 R RALU 2 4 2 6 RD B 20 considerations 6 13 idle powerdown reset status B 23 B 25 Read cycles 16 bit data bus 15 14 8 bit data bus 15 16 READY 15 17 15 21 16 25 and wait states 15 18 considerations 6 13 idle powerdown reset status B 23 B 25 timing definitions 15 20 timing diagram 15 19 timing requirements 15 18 REAL variables 3 4 Register bits naming conventions 1 4 reserved 1 4 Register file 2 4 4 9 and windowing 4 9 4 12 See also windows Register RAM 4 10 and idle mode 14 4 and powerdown mode 14 5 Register direct addressing 4 10 and register RAM 4 10 and windows 4 12 4 19 Registers AD_COMMAND 12 8 C 6 AD_RESULT read 12 9 C 7 AD_RESULT write 12 6 C 8 AD_TEST 12 5 C 9 AD_TIME 12 7 C 10 addresses and reset values C 2 allocating 3 10 CCRO 15 7 C 11 15 9 C 13 COMPx_CON 11 22 C 15 COMPx_TIME C 17 EPAx_CON 11 19 C 18 EPAx_TIME C 21 external memo
207. 6MC MD MH USER S MANUAL intel 8 Bits of Data or 7 Bits of Data with Parity Bit 10 bit Frame gt A0245 02 Figure 7 4 Serial Port Frames for Mode 1 The transmit and receive functions are controlled by separate shift clocks The transmit shift clock starts when the baud rate generator is initialized The receive shift clock is reset when a start bit high to low transition is received Therefore the transmit clock may not be synchronized with the receive clock although both will be at the same frequency The transmit interrupt TI and receive interrupt RI flags in SPx_STATUS are set to indicate completed operations During a reception both the RI flag and the RIx interrupt pending bit are set just before the end of the stop bit During a transmission both the TI flag and the TIx interrupt pending bit are set at the beginning of the stop bit The next byte cannot be sent until the stop bit is sent Use caution when connecting more than two devices with the serial port in half duplex i e with one wire for transmit and receive The receiving processor must wait for one bit time after the RI flag is set before starting to transmit Otherwise the transmission could corrupt the stop bit causing a problem for other devices listening on the link 7 3 2 2 Mode 2 Mode 2 is the asynchronous ninth bit recognition mode This mode is commonly used with mode 3 for multiprocessor communications Figure 7 5 shows the
208. 73 For 8 bit bus read cycles after ALE falls the bus controller floats the bus and drives the RD signal low The external memory then must put its data on the bus That data must be valid at the rising edge of the RD signal To read a data word the bus controller performs two consecutive reads reading the low byte first followed by the high byte For 8 bit bus write cycles after ALE falls the bus controller outputs data on AD7 0 and then drives WR low The external memory must latch the data by the time WR goes high That data will be valid on the bus until slightly after WR goes high To write a data word the bus controller performs two consecutive writes writing the low byte first followed by the high byte 15 16 intel INTERFACING WITH EXTERNAL MEMORY XTAL1 ALE BUSWIDTH LNS Nef ON UP NN Nee H NHN AD15 8 Address Out Address Out AD7 0 Address Address RD INST AD7 0 Address Address Lio UN The CLKOUT pin is available only on the 8XC196MC MD A3164 01 Figure 15 7 Timings for 8 bit Buses 15 4 WAIT STATES READY CONTROL An external device can use the READY input to lengthen an external bus cycle When an external address is placed on the bus the external device can pull the READY signal low to indicate it is not ready In response the microcontroller inserts wait states to lengthen the bus cycle unti
209. 9 1 4 2 1 How to Find MCS 96 Microcontroller Files on the BBS 1 10 1 4 2 2 How to Find ApBUILDER Software and Hypertext Documents on the BBS 1 10 1 4 3 CompusServe FOrUutms 1 10 1 4 4 World Wide 1 11 1 5 TECHNICAL SUPPORT trant tette tg ret ERR ERR KR RI 1 11 1 6 PRODUCT 1 11 2 ARCHITECTURAL OVERVIEW 2 1 TYPICAL ener rrt etienne drei e tnra 2 1 2 2 MICROCONTROLLER 5 emen 251 2 3 FUNCTIONAL 2 2 2 3 1 6158 code 2 4 2 3 2 Register bee 2 4 2 3 3 Register Arithmetic logic Unit seem mm O74 2 3 3 1 Gode Execution 2 5 2 3 9 2 Jnstruction Format eter rete terni emp rie D 2 3 4 Memory Interface 2 6 2 3 5 Interrupt Service IRE DU Ho HEIDE eee ah es ri ERE 2 6 2 4 INTERNAL 2 7 2 5 INTERNAL 25 2 8 2 5 1 VO POf S 5 ane dagen ue ete rere 79 2 5 2 0 510 Port ne Re ER DI PNE 2 9 2 5 3 Event Processor Array EPA and Timer Counters sese 2 10 2 5 4 Pul
210. 9 16 C 67 WSR 4 12 C 68 ZERO REG C 71 Reserved bits defined 1 4 Reset 13 9 and CCB fetches 4 4 circuit diagram 13 11 general configuration register 13 9 C 24 pin status B 23 B 25 status CLKOUT P2 7 6 7 with illegal IDLPD operand 13 12 with RESET pin 13 10 with RST instruction 13 9 13 12 with watchdog timer 13 12 RESET 13 1 14 2 B 20 and CCB fetch 13 8 and CLKOUT 13 8 and device reset 13 8 13 9 13 10 and ONCE mode 14 11 and powerdown mode 14 6 and programming modes 16 13 16 14 idle powerdown reset status B 24 B 25 Resonator ceramic 13 6 RET instruction A 2 A 30 A 46 A 50 A 55 A 56 ROM dump mode 16 30 security key verification 16 30 intel RST instruction 3 11 13 9 13 12 A 3 A 31 A 46 A 51 A 57 Run time programming 16 32 16 33 code example 16 33 RXD B 20 and SIO port mode 0 7 5 7 7 and SIO port modes 1 2 and 3 7 7 5 Sampled input B 13 SBUFx_RX C 70 SBUFx_TX C 70 SCALL instruction A 3 A 31 A 41 A 47 A 50 A 55 A 56 SCLKx 7 2 Security key verification 16 30 Serial I O modes See PTS Serial I O port See SIO port Serial port control x register 7 10 C 51 Serial port receive buffer x register C 47 Serial port status x register 7 15 C 52 Serial port transmit buffer x register C 48 Serial port x baud rate register 7 12 C 50 Set defined 1 3 SETC instruction A 3 A 31 A 46 A 51 A 57 SFRs and idle mode 14 4 and powerdown mode 14 5
211. 9 S8XC196MH P2 2 EPA1 PROG P4 2 AD10 PBUS 10 amp NC P4 1 PBUS 9 amp NC P4 0 AD8 PBUS 8 P2 1 SCLKO BCLKO PALE P3 7 AD7 PBUS 7 E P2 0 PVER P3 6 AD6 PBUS 6 amp 5 AD5 PBUS 5 View of component as P0 0 ACHO P3 4 AD4 PBUS 4 C mounted on PC board 1 ACH1 P3 3 AD3 PBUS 3 17 48 P0 2 ACH2 P3 2 PBUS 2 P0 3 P3 1 AD1 PBUS 1 E P3 0 ADO PBUS 0 20 P0 4 ACH4 0 0 5 ACH5 PMODE 1 NC 21 VREF RESET 22 ANGND NMI E 23 P0 6 ACH6 T1CLK PMODE 2 r 24 P0 7 ACH7 T1DIR PMODE 3 10 CO P e QN CO CO CO CO CO 29 8859 B85 255992988 gt 25 zOoz aor EIS Lo apo pecia ao A2574 02 Figure B 8 8XC196MH 80 lead Shrink EIAJ QFP Package B 3 SIGNAL DESCRIPTIONS Table B 5 defines the columns used in Table B 6 which describes the signals intel SIGNAL DESCRIPTIONS Table B 5 Description of Columns of Table B 6 Column Heading Description Name Lists the signals arranged alphabetically Many pins have two functions so there are more entries in this column than there are pins Every signal is listed in this column Type Identifies the pin function listed in the Name column
212. A channel Load Critical Data A3275 01 Figure 5 24 Synchronous SIO Receive Mode End of PTS Interrupt Routine Flowchart 5 6 6 3 Asynchronous SIO Transmit Mode Example In asynchronous serial I O ASIO transmit mode an EPA channel controls the transmission baud rate by generating an interrupt whenever a match occurs between the EPA event time register and a timer register The PTS shifts a data bit out onto a port pin that is configured to function as the Transmit Data signal TXD when the selected EPA channel generates a compare interrupt Fig ure 5 25 In ASIO transmit mode the PTS automatically transmits up to 16 bits data 1 optional parity 1 stop bit The maximum number of data bits is 14 with parity or 15 without 5 50 intel STANDARD AND PTS INTERRUPTS End of PTS Conventional 10 PTS Serviced Interrupts interrupt Interrupts Software Clears TXD LSB MSB TXD Stop Start Port pin 1 Bit Time Y optional Parity Bit A3119 01 Figure 5 25 Asynchronous SIO Transmit Timing The first PTS cycle must be started manually by generating a start bit and then setting up the tim ing for the first EPA interrupt Initialize the TXD port pin to one before starting a transmission Write a zero to the TXD port pin to start the transmission The PTS uses this as the start bit Add the contents of the timer register to the Baud value Figure 5 19 on page 5 38 and sto
213. ALU uses the upper and lower word registers together for the 32 bit instructions and as temporary registers for many instructions These registers have their own shift logic and are used for operations that require logical shifts including normalize multiply and divide operations The six bit loop counter counts repetitive shifts The second operand register stores the second operand for two operand instructions including the multiplier during multiply operations and the divisor during divide operations During subtraction operations the output of this register is com plemented before it is moved into the ALU The RALU speeds up calculations by storing constants e g 0 1 and 2 in the constants register so that they are readily available when complementing incrementing or decrementing bytes or words In addition the constants register generates single bit masks based on the bit select reg ister for bit test instructions 2 3 3 1 Code Execution The RALU performs most calculations for the microcontroller but it does not use an accumula tor Instead it operates directly on the lower register file which essentially provides 256 accumu lators Because data does not flow through a single accumulator the microcontroller s code executes faster and more efficiently 2 3 3 2 Instruction Format MCS 96 microcontrollers combine a large set of general purpose registers with a three operand instruction format This format allows a single i
214. AMPLE This example was designed to run on an 8XC196MC demo board but it can easily be modified for an evaluation board The program allows you to test the waveform generator s registers and observe their effects on the output waveforms All variables are defined as words and are masked to the appropriate length before they are written to the registers This method is not compact but it is easy to code and debug When running the program under the reduced instruction set mon itor RISM software you can use the following command to change any variable and immedi ately see the result on the outputs WORD variable_name This program and the other programs included in AP 483 Application Examples Using the 6XC196MC MD Microcontroller order number 272282 are available from the Intel BBS file name AP_483 EXE See Bulletin Board System BBS on page 1 9 for information about ac cessing the BBS Sdebug Program to test WFG peripheral nolist include 19 Slist This program allows modifying the WFG input parameters on the fly on the MC demo board This allows you to see what is really going on First set up the variables that you want to control rseg at 40h mode dsw mode 0 3 0 dsw P6 0 2 4 polarity 0O low 1 high opl dsw 6 1 3 5 polarity 0 1ow 1 high sync dsw 0 load now 1 synchronized 7 dsw P6 7 0 1 1 PWM dsw P6 6 0 i o 1
215. ATILE MEMORY Table 16 11 8XC196MC MD Auto Programming Memory intial lt i aes ee 8XC196MC ML Figure 16 12 Description 8XC196MD A15 0 4014H N A 14H Programming pulse width PPW LSB 4015H N A 15H Programming pulse width PPW MSB 4020 402FH 2020 202FH 0020 002FH Security key for verification 4000 7FFFH 2000 4000 7FFFH Code data and reserved locations Table 16 12 8XC196MH Auto Programming Memory Map Address Internal ji nn nm Output from OTPROM Figure 16 12 Description 8XC196MH Address P1 3 0 A11 0 105EH N A 105EH Programming pulse width PPW LSB 105FH N A 105FH Programming pulse width PPW MSB 0020 002 2020 202 0020 002FH Security key for verification 2000 9FFFH 2000 9FFFH 2000 9FFFH Code data and reserved locations 16 9 2 Operating Environment In the auto programming mode the PCCBs are loaded into the chip configuration registers Since the device gets programming data through the external bus the memory device in the program ming system must correspond to the default configuration Figure 16 6 on page 16 18 Auto pro gramming requires an 8 bit bus configuration so the circuit must tie the BUSWIDTH pin low The PCCB defaults allow you to use any standard EPROM that satisfies the AC specifications listed in the device datasheet The auto programming mode also loads CCBO into an internal RAM loc
216. Any attempt to load an external address initiates a reset 2 DED Disable External Data Fetch Setting this bit prevents the bus controller from executing external data reads and writes Any attempt to access data through the bus controller initiates a reset 1 0 Reserved for compatibility with future devices write zero to these bits Figure 16 1 Unerasable PROM USFR Register You can verify a UPROM bit to make sure it programmed but you cannot erase it For this reason Intel cannot test the bits before shipment However Intel does test the features that the UPROM bits enable so the only undetectable defects are unlikely defects within the UPROM cells them selves Table 16 4 UPROM Programming Values and Locations for Slave Mode To set this bit Write this value To this location DEI 08H 0718H DED 04H 0758H 16 7 8XC196MC MD MH USER S MANUAL intel 16 4 PROGRAMMING PULSE WIDTH The programming pulse width is controlled in different ways depending on the programming mode In slave programming mode the pulse width is controlled by the PALE signal In auto programming mode it is loaded from the external EPROM into the PPW register In the UPROM 8XC196MH only and PCCB programming modes the pulse width is controlled by the test ROM routine For run time programming your software controls the pulse width To determine the correct PPW VALUE for the frequency of the device u
217. B 2 ops 3 74 3 75 3 76 4 5 77 ADDB 3 ops 4 54 4 55 4 56 5 6 57 ADDC 3 A4 4 A5 3 A6 4 5 A7 ADDCB 3 B4 3 B5 3 B6 4 5 B7 CLR 2 01 CLRB 2 11 CMP 3 88 4 89 3 8A 4 5 8B CMPB 3 98 3 99 3 9A 4 5 9B CMPL 3 C5 DEC 2 05 DECB 2 15 EXT 2 06 EXTB 2 16 INC 2 07 INCB 2 17 SUB 2 ops 3 68 4 69 3 6A 4 5 6B SUB 3 ops 4 48 5 49 4 4A 5 6 4B SUBB 2 ops 3 78 3 79 3 7A 4 5 7B SUBB 3 ops 4 58 4 59 4 5A 5 6 5B SUBC 3 8 4 9 3 AA 4 5 AB SUBCB 3 B8 3 9 3 BA 4 5 BB NOTES 1 For indexed instructions the first column lists instruction lengths as S L where is the short indexed instruction length and L is the long indexed instruction length 2 For the SCALL and SJMP instructions the three least significant bits of the opcode are concatenated with the eight bits to form an 11 bit two s complement offset A 47 8XC196MC MD MH USER S MANUAL intel Table A 8 Instruction Lengths and Hexadecimal Opcodes Continued Arithmetic Group Il Direct Immediate Indirect Neto Mnemonic Length Opcode Length Opcode Length Opcode pa Opcode DIV 4 FE 8C 5 FE8D 4 FE 8E 5 6 FE 8F DIVB 4 FE 9C 4 FE 9D 4 FE 9E 5 6 FE 9F DIVU 3 8C 4 8D 3 8E 4 5 8F DIVUB 3 9C 3 9D 3 9E 4 5 9F MUL 2 ops 4 FE eC 5 FE 6D 4 FE 6E 5 6 FE 6F MUL 3 ops 5 FE 4C 6 FE4D 5 FE 4E 6 7 FE 4F MULB 2 ops
218. B and UPROM Programming Circuit EE 16 31 Run time Programming Code Example seen 16 33 8XC196MC 64 lead Shrink DIP SDIP B 3 8XC196MC 84 lead PLCC enne eene B 4 8XC196MC 80 lead Shrink EIAJ QFP B 5 8XC196MD 84 lead PLCC Package B 7 8XC196MD 80 lead Shrink EIAJ QFP B 8 8XC196MH 64 lead Shrink DIP SDIP 55 10 8XC196MH 84 lead PLCC Package poe 8XC196MH 80 lead Shrink EIAJ QFP Package 12 XV 8XC196MC MD MH USER S MANUAL intel 5 10 5 11 5 13 5 14 5 15 5 16 6 1 6 3 6 4 6 6 6 7 xvi TABLES Page Handbooks and Product 1 6 Application Notes Application Briefs and Article Reprints 1 6 MCS 96 Microcontroller Datasheets 1 7 MCS 96 Microcontroller Datasheets Automotive 1 7 MCS 96 Microcontroller Quick References 1 8 Features of the 8 196 Product 2 2 State Times at Various eee 2 8 Ope
219. C196MD EPA5 0 COMP5 0 8XC196MH EPA1 0 COMP3 0 8XC196MC MD MH USER S MANUAL intel Timer counter Unit TIMER1 TIMER2 Capture Compare EPAO Channel 0 Capture Compare EPAx Channel Compare only Channel EPAO Interrupt EPAx Interrupt COMPO Interrupt COMPO i COMPYy Interrupt Compare Channe COMPy Notes For the 8XC196MC x amp y 3 For the 8XC196MD x amp 5 For the 8XC196MH 1 amp 3 A2846 01 Figure 11 1 EPA Block Diagram 11 2 EPA AND TIMER COUNTER SIGNALS AND REGISTERS Table 11 2 describes the EPA and timer counter input and output signals Each signal is multi plexed with a port pin as shown in the first column Table 11 3 briefly describes the registers for the EPA capture compare channels EPA compare only channels and timer counters Table 11 2 EPA and Timer Counter Signals Port Pin EPA EPA Signals Signal Description 8XC196MC 8XC196MD 8XC196MH Type 1 2 1 2 P0 6 External clock source for timer 1 P1 3 P1 3 7 T1DIR External direction control for timer 1 P2 0 P2 0 P2 0 VO High speed input output for the P2 1 P2 1 P2 2 EPA1 capture compare channels P2 2 P2 2 EPA2 P2 3 P2 3 EPAS3 P7 0 EPA4 P7 1 EPA5 intel EVENT PROCESSOR ARRAY EPA Table 11 2 EPA and Timer Counter Signals Continu
220. CCBs are used The CCBs reside in nonvolatile memory at addresses 2018H CCBO and 201AH CCB1 Figure 15 2 Chip Configuration 1 CCR1 Register 15 3 BUS WIDTH AND MULTIPLEXING The external bus can operate as either a 16 bit multiplexed address data bus or as a multiplexed 16 bit address 8 bit data bus Figure 15 3 15 10 intel INTERFACING WITH EXTERNAL MEMORY Bus Control Bus Control 8 bit Address 16 bit Multiplexed High Address Data AD15 0 mm Ports 4 and 3 8 bit Multiplexed Address Data Port 3 8XC196 8XC196 16 bit Bus 8 bit Bus A3068 01 Figure 15 3 Multiplexing and Bus Width Options After reset but before the CCB fetch the microcontroller is configured for 8 bit bus mode re gardless of the BUS WIDTH input The upper address lines AD15 8 are weakly driven through out the CCBO and bus cycles To prevent bus contention neither pull ups nor pull downs should be used on AD15 8 Also the upper bytes of the CCB words locations 2019H and 201BH should be loaded with 20H If the external memory outputs 20H on its high byte there will be no bus contention After CCBs are loaded into the CCRs the values of and BW1 define the data bus width as either a fixed 8 bit a fixed 16 bit or a dynamic 16 bit 8 bit bus width controlled by the BUSWIDTH signal BWO and BW1 bits are defined in Figures 15 1 and 15 2 If BWO is clear and BW is set the bus
221. CHDOG 0008H INT_PEND INT_MASK 0006 PTSSRV H PTSSRV L 0004 PTSSEL PTSSEL L 0002H ONES REG H ONES REG L 0000H ZERO_REG H ZERO_REG L NOTE Using any SFR as a base or index register for indirect or indexed operations can cause unpredictable results because external events can change the contents of SFRs Also because some SFRs are cleared when read consider the implications of using an SFR as an operand in a read modify write instruction e g XORB 8XC196MC MD MH USER S MANUAL 4 2 WINDOWING intel Windowing expands the amount of memory that is accessible with register direct addressing Register direct addressing can access the lower register file with short fast executing instruc tions With windowing register direct addressing can also access the upper register file and pe ripheral SFRs Windowing maps a segment of higher memory the upper register file or peripheral SFRs into the lower register file The window selection register WSR selects a 32 64 or 128 byte seg ment of higher memory to be windowed into the top of the lower register file space Figure 4 2 illustrates a 128 byte window 128 byte Window WSR 13H WSR Window in Lower Register File 8XC196MC MD 02FFH 1 0180H 0080H 0000H 128 byte Window WSR 13H WSR Window in Lower Register File 8XC196MH A3062 01 Figure 4 2 Windowing
222. COMPx value x WG RELOAD Figure 9 10 Waveform Generator Reload WG RELOAD Register 9 16 intel WAVEFORM GENERATOR WG COMPx Address 1FC2H 1FC4H 1FC6H x 1 3 Reset State 0000H The phase compare WG_COMP register controls the duty cycle of each phase Write a value to each phase compare register to specify the length of time that the associated outputs will remain asserted Changing the WG_RELOAD value changes both the carrier period and the duty cycle because the outputs remain asserted for a constant length of time while the counter takes longer to cycle To change the carrier period without changing the duty cycle you must proportionally change both WG_RELOAD and WG_COMP x at the same time immediately after the interrupt 15 0 Compare Bit Number Function 15 0 Compare These bits determine the length of time that the associated outputs are asserted Use the following formulas to calculate output assertion time and duty cycle multiplier x WG_COMPx OUTPUT FyrAL1 Hee WG RELOAD where Toureur total time output is asserted in us FxraLi input frequency on XTAL1 pin in MHz multiplier 4 for center aligned modes 2 for edge aligned modes WG RELOAD 16 bit WG RELOAD value gt WG_COMPx WG COMPx 16 bit WG_COMPx value x WG RELOAD Figure 9 11 Phase Compare WG_COMPx Register 9 4 4 Specifying the Operating Mode and Dead Time a
223. CPU 4 11 memory mapped 4 5 peripheral 4 4 4 5 and windowing 4 12 reserved 3 10 4 4 4 11 with indirect or indexed operations 3 10 4 4 4 11 with read modify write instructions 4 4 Shift instructions A 51 A 57 SHL instruction A 3 A 32 A 41 A 51 A 57 SHLB instruction A 3 32 41 A 51 57 SHLL instruction A 3 A 33 A 41 A 51 SHORT INTEGER defined 3 2 SHR instruction A 3 A 33 A 41 A 51 A 57 SHRA instruction A 3 A 34 A 41 A 51 A 57 SHRAB instruction A 3 A 34 A 41 A 51 A 57 SHRAL instruction A 3 A 35 A 41 A 51 A 57 SHRB instruction A 3 A 35 A 41 A 51 A 57 INDEX SHRL instruction A 3 A 36 A 41 A 51 A 57 Signals configuring for external memory interfacing 15 5 default conditions 23 B 25 descriptions 13 22 external memory 15 1 AD15 0 15 1 ADV 15 1 ALE 15 2 BHE 15 2 BUSWIDTH 15 2 CLKOUT 15 2 EA 15 3 INST 15 3 RD 15 3 READY 15 3 WR 15 3 WRH 15 4 WRL 15 4 functional listings B 2 B 6 B 9 name changes B 1 naming conventions 1 4 Single transfer mode See PTS SIO port 2 9 7 1 9 bit data See mode 2 mode 3 block diagram 7 1 calculating baud rate 7 13 7 14 enabling interrupts 7 14 enabling parity 7 10 framing error 7 16 half duplex considerations 7 8 interrupts 7 7 7 9 7 16 mode 0 7 5 7 6 mode 1 7 7 mode 2 7 7 7 8 mode 3 7 7 7 9 multiprocessor communications 7 8 7 9 overrun error 7 16 programming 7 10
224. CPU and the peripherals to provide flexibil ity in power management Reducing Power Consumption on page 14 3 describes the power management modes The 8XC196MC 8XC196MD microcontrollers output the CLKOUT signal on the CLKOUT pin Because of the complex logic in the clock circuitry the signal on the CLKOUT pin is a delayed version of the internal CLKOUT signal This delay varies with tem perature and voltage The 8XC196MH microcontroller has no CLKOUT pin If your 8 196 design requires system clock we recommend that you use an external oscillator and add external logic to generate the system clock signal 8XC196MC MD MH USER S MANUAL intel XTAL1 7 me TX TALL lt 1 gt lt lt 1 State Time X9 amp 1 State Time gt PH1 Sieg Ue CLKOUT M Phase 1 Phase 2 1 Phase2 0114 04 Figure 2 4 Internal Clock Phases The combined period of phase and phase 2 of the internal CLKOUT signal defines the basic time unit known as a state time or state Table 2 2 lists state time durations at various frequencies Table 2 2 State Times at Various Frequencies FyraLi Frequency Input to the State Time Divide by two Circuit 8 MHz 250 ns 12 MHz 167 ns 16 MHz 125 ns The following formulas calculate the frequency of PH1 and PH2 the duration of a state time and the duration of a clock period Ty4 1 F 2 7
225. Cs luis Leakage A0243 02 Figure 12 7 Idealized A D Sampling Circuitry During the sample window the external input circuit must be able to charge the sample capacitor C through the series combination of the input source resistance R source the input series re sistance R and the comparator feedback resistance Ry The total effective series resistance is calculated using the following formula where A is the gain of the comparator circuit Re Rgource R4 ME 12 10 intel ANALOG TO DIGITAL A D CONVERTER Typically the Ry Ay 1 term is the major contributor to the total resistance and the factor that determines the minimum sample time specified in the datasheet 12 6 1 1 Minimizing the Effect of High Input Source Resistance Under some conditions the input source resistance Rsourcg can be great enough to affect the measurement You can minimize this effect by increasing the sample time or by connecting an external capacitor from the input pin to ANGND The external signal will charge Cy to the source voltage level When the channel is sampled acts as a low impedance source to charge the sample capacitor A small portion of the charge in Cy is transferred to Cg re sulting in a drop of the sampled voltage The voltage drop is calculated using the following for mula Cs Sampled Voltage Drop 100 Cext Cs If Ci is 0 005 or greater the
226. EA signal must be tied low EA is latched at reset Table 4 2 Special purpose Memory Addresses Hex Address Description 207F 205E Reserved each byte must contain FFH 205D 2040 PTS vectors 203F z 2030 Upper interrupt vectors 202F 2020 Security key 201F Reserved must contain 20H 201E Reserved must contain FFH 201D Reserved must contain 20H 201C Reserved must contain FFH 201B Reserved must contain 20H 201A CCB1 2019 Reserved must contain 20H 2018 CCBO 2017 2014 Reserved each byte must contain FFH 2013 2000 Lower interrupt vectors 4 1 4 1 Reserved Memory Locations Several memory locations are reserved for testing or for use in future products Do not read or write these locations except to initialize them The function or contents of these locations may change in future revisions software that uses reserved locations may not function properly Al ways initialize reserved locations to the values listed in Table 4 2 4 1 4 2 Interrupt and PTS Vectors The upper and lower interrupt vectors contain the addresses of the interrupt service routines The peripheral transaction server PTS vectors contain the addresses of the PTS control blocks See Chapter 5 Standard and PTS Interrupts for more information on interrupt and PTS vectors 4 3 8XC196MC MD MH USER S MANUAL intel 4 1 4 3 Security Key The security key prevents unauthorized programm
227. EMORY CCR1 no direct accesst The chip configuration 1 CCR1 register enables the watchdog timer and selects the bus timing mode Two of its bits combine with three bits of CCRO to control wait states and bus width 7 0 1 1 0 1 WDE BW1 IRC2 0 Number Funetion 7 6 1 To guarantee proper operation write ones to these bits 5 0 To guarantee proper operation write zero to this bit 4 1 To guarantee proper operation write one to this bit 3 WDE Watchdog Timer Enable Selects whether the watchdog timer is always enabled or enabled the first time it is cleared 0 always enabled 1 enabled first time it is cleared 2 BW1 Buswidth Control This bit along with the BWO bit CCRO 1 selects the bus width BW1 BWO 0 illegal 1 16 bit only 0 8 bit only 1 BUSWIDTH pin controlled CCRs are loaded with the contents of the chip configuration bytes CCBs after reset unless the microcontroller is entering programming modes see Entering Programming Modes page 16 13 in which case the programming chip configuration bytes PCCBs are used The CCBs reside in nonvolatile memory at addresses 2018H CCBO and 201 CCB1 Figure 15 2 Chip Configuration 1 CCR1 Register 15 9 8XC196MC MD MH USER S MANUAL intel 7 CCR1 Continued The chip configuration 1 CCR1 register enables the watchdog timer and selects the bus
228. EPA Capture Compare Channel 5 2038H SPI MH it Serial Port 2038H COMP4 MD EPA Compare Channel 4 2036H MH SIO 1 Receive 2036H EPA4 MD EPA Capture Compare Channel 4 2034H RIO MH SIO 0 Receive 2034H MC EPA Compare Channel 3 2032H MH SIO 1 Transmit 2032H EPA3 MC MD EPA Capture Compare Channel 3 2030H TIO MH SIO 0 Transmit 2030H these bits On the 8 196 device bits 4 3 are reserved For compatibility with future devices write zeros to C 26 intel When hardware detects an interrupt request it sets the corresponding bit in the interrupt pending INT_PEND or INT_PEND1 registers When the vector is taken the hardware clears the pending bit Software can generate an interrupt by setting the corresponding interrupt pending bit REGISTERS INT_PEND INT_PEND Address 0009H E Reset State 00H when processing transfers to the corresponding interrupt vector The standard interrupt vector locations are as follows Bit Mnemonic 2 MC MD COMP3 MH EPA2 MC MD 2 MH 1 EPA1 COMPO EPAO AD OVRTM t Timer 1 and timer 2 can generate the multiplexed overflow underflow interrupt Write to to enable the interrupt sources read PI_PEND to determine which source caused the interrupt Interrupt EPA Compare Channel 2 EPA Compare Channel 3 EPA Capture Compare Channe
229. EPAx Capture Compare Time EPALLHME 1TF46H 1F46H 1F46H n capture mode these registers contain the EPA2_TIME ESAE captured timer value In compare mode these EPA3_TIME 1F4EH 1F4EH ES registers contain the time at which an event is to EPA4 TIME m 1F52H occur capture mode these registers are EPAS_TIME P 1FS6H e buffered to allow two captures before an overrun occurs However they are not buffered in compare mode INT MASK 0008H 0008H 0008H Interrupt Mask The bits in this 8 bit register enable and disable mask the interrupts associated with the corre sponding bits in the INT PEND register INT MASK1 0013H 0013H 0013H Interrupt Mask 1 The bits in this 8 bit register enable and disable mask the interrupts associated with the corre sponding bits in the INT PEND1 register 8XC196MC MD MH USER S MANUAL Table 11 3 EPA Control and Status Registers Continued Mnemonic Address MH Description INT_PEND 0009H 0009H 0009H Interrupt Pending Any set bit in this 8 bit register indicates a pending interrupt request INT_PEND1 0012H 0012H 0012H Interrupt Pending 1 Any set bit in this 8 bit register indicates a pending interrupt request P2 DIR P7_DIR 1FD2H 1FD2H 1FD3H 1FD2H Port x Direction Each bit of Px_DIR controls the direction of the corresponding pin Clearing a bit configures a pin as a complementary ou
230. F5 POPF 1 F3 PUSH 2 C8 3 C9 2 CA 3 4 CB PUSHA 1 F4 PUSHF 1 F2 Data 2 Indexed Direct Immediate Indirect Note 1 Mnemonic Length Length Opcode Length Opcode Length Opcode S L Opcode BMOV 3 C1 BMOVI 3 CD LD 3 AO 4 Al 3 A2 4 5 A3 LDB 3 BO 3 B1 3 B2 4 5 B3 LDBSE 3 BC 3 BD 3 BE 4 5 BF LDBZE 3 AC 3 AD 3 AE 4 5 AF ST 3 CO 3 C2 4 5 C3 STB 3 C4 3 C6 4 5 C7 XCH 3 04 4 5 0B XCHB 3 14 4 5 1B Jump Indexed Direct Immediate Indirect Note 1 Mnemonic Length Length Opcode Length Opcode Length Opcode S L Opcode BR 2 E3 LJMP 3 7 SJMP Note 2 2 20 27 TIJMP 4 E2 4 E2 4 E2 NOTES 1 For indexed instructions the first column lists instruction lengths as S L where is the short indexed instruction length and L is the long indexed instruction length 2 For the SCALL and SJMP instructions the three least significant bits of the opcode are concatenated with the eight bits to form an 11 bit two s complement offset A 49 8XC196MC MD MH USER S MANUAL intel Table A 8 Instruction Lengths and Hexadecimal Opcodes Continued
231. FREQ GEN Register 8 3 8XC196MC MD MH USER S MANUAL intel 8 2 3 Determining the Current Value of the Down counter You can read the FREQ CNT register Figure 8 3 to determine the current value of the down counter FREQ CNT Address 1FBAH 8XC196MD Reset State 00H Read the frequency generator count FREQ register to determine the current value of the down counter 7 0 8XC196MD Count Bit Number Function 7 0 Count This register contains the current down counter value Figure 8 3 Frequency Generator Count FREQ_CNT Register 8 3 APPLICATION EXAMPLE One application for the frequency generator is to drive an infrared LED to transmit remote control data and control signals Figure 8 4 In this example the frequency generator is configured with a 40 kHz frequency and is switched on and off by writing to bit 7 of the P7_MODE register In formation is transmitted serially Zero is represented by a one millisecond carrier burst followed by a one millisecond pause one is represented by a two millisecond carrier burst followed by a two millisecond pause Figure 8 5 A photodiode receives the light pulses and a high pass filter rejects low frequency ambient light and allows the 40 kHz carrier to pass through This carrier is amplified and detected to reproduce the original pulse sequence intel FREQUENCY GENERATOR 8XC196 Device i Output Signal Filter and put sl
232. Function 15 6 ADRLT9 0 A D Result These bits contain the A D conversion result Reserved This bit is undefined STATUS A D Status Indicates the status of the A D converter Up to 8 state times are required to set this bit following a start command When testing this bit wait at least the 8 state times 0 A D is idle 1 A D conversion is in progress 3 0 0 A D Channel Number These bits indicate the A D channel number that was used for the conversion C 7 8XC196MC MD MH USER S MANUAL intel AD RESULT Write AD RESULT Write Address 1FAAH Reset State MC MD FFCOH Reset State MH 7FCOH The high byte of the A D result AD RESULT register can be written to set the reference voltage for the A D threshold detection modes 15 8 REFV7 REFV6 REFV5 REFV4 REFV3 REFV2 REFV1 REFVO 7 0 Bit Bit Function Number Mnemonic 15 8 REFV7 0 Reference Voltage These bits specify the threshold value This selects a reference voltage that is compared with an analog input pin When the voltage on the analog input pin crosses over detect high or under detect low the threshold value the A D conversion complete interrupt pending bit is set Use the following formula to determine the value to write to this register for a given threshold voltage desired threshold voltage x 256 reference voltage Vker ANGND 7 0 Reserv
233. G OUTPUT register update reload amp compare regs update protection options update WG CONTROL 9 25 intel 10 Pulse width Modulator intel CHAPTER 10 PULSE WIDTH MODULATOR The pulse width modulator PWM module has two output pins each of which can output a PWM signal with a fixed programmable frequency and a variable duty cycle These outputs can be used to drive motors that require an unfiltered PWM waveform for optimal efficiency or they can be filtered to produce a smooth analog signal This chapter provides a functional overview of the pulse width modulator module describes how to program it and provides sample circuitry for converting the PWM outputs to analog signals For detailed descriptions of the signals and registers discussed in this chapter please refer to Ap pendix B Signal Descriptions and Appendix C Registers 10 1 PWM FUNCTIONAL OVERVIEW The PWM module has two channels each of which consists of a control register PWMx CONTROL a buffer a comparator an RS flip flop and an output pin Two other com ponents an eight bit counter _ COUNT and a period register PWM PERIOD shared across the PWM module s two channels completing the circuitry see Figure 10 1 10 1 8XC196MC MD MH USER S MANUAL intel Load Buffer RS Flip flopx Port 6 Control Internal Clock Signal PWMx Output Down Counter P6 x PWMx PWM_PER
234. GEN_CON General Configuration 1FAO 0000 0000 INT_MASK Interrupt Mask 0008 0000 0000 INT_MASK1 Interrupt Mask 1 0013 0000 0000 INT_PEND Interrupt Pending 0009 0000 0000 INT_PEND1 Interrupt Pending 1 0012 0000 0000 ONES_REG Ones Register 0002 1111 1111 1111 1111 P1_DIR MH Port 1 I O Direction 1F9B 1111 1111 P2_DIR Port 2 I O Direction 1FD2 1111 1111 P5_DIR Port 5 I O Direction 1FF3 1111 1111 P7_DIR MD Port 7 I O Direction 1FD3 1111 1111 P1_MODE MH Port 1 Mode 1F99 0000 0000 P2_MODE Port 2 Mode 1FDO 0000 0000 P5 MODE Port 5 Mode 1FF1 tt P7_MODE MD Port 7 Mode 1FD1 0000 0000 PO_PIN MC MD 1FA8 PIN MH Port 0 Pin Input EDA T P1 PIN MC MD 1FA9 P1 PIN MH Port 1 Pin Input 1F9F T P2 PIN Port 2 Pin Input 1FD6 T P3 PIN Port 3 Pin Input 1FFE 1 P4_PIN Port 4 Pin Input 1FFF t P5_PIN Port 5 Pin Input 1FF7 1111 1111 Reset value is FFH when pin is not driven t Reset value is 80H if the EA pin is high if EA is low The CCRs are loaded with the contents of the chip configuration bytes CCBs after a device reset unless the device is entering programming modes see Entering Programming Modes on page 16 13 in which case the programming chip configuration bytes PCCBs are used The CCBs reside in internal nonvolatile memory at addresses 2018H CCBO and 201AH CCB1 C 3 8XC196MC MD MH USER S MANUAL intel Table C 2 Register Name Address and Reset Status Continued Binary
235. Generator Type Description in 2 Signal P6 0 WG1 Waveform generator phase 1 negative output P6 1 WG1 Waveform generator phase 1 positive output P6 2 WG2 Waveform generator phase 2 negative output P6 3 WG2 Waveform generator phase 2 positive output P6 4 WG3 Waveform generator phase 3 negative output P6 5 WG3 Waveform generator phase 3 positive output EXTINT Input to the waveform generator s protection circuitry Table 9 2 Waveform Generator Control and Status Registers Mnemonic Address Description INT_MASK1 0013H Interrupt Mask 1 The EXTINT bit enables or disables the EXTINT interrupt 8XC196MH The WG bit enables or disables the waveform generator interrupt 8XC196MC MD The PI bit enables or disables the multiplexed peripheral interrupt The corresponding bit in the register enables or disables the individual sources of the peripheral interrupt INT_PEND1 0014H Interrupt Pending 1 Any set bit indicates a pending interrupt request PI MASK 1FBCH Peripheral Interrupt Mask MC MD 8XC196MC MD The WG bit enables or disables the waveform generator interrupt as one of the possible sources of the multiplexed peripheral interrupt The PI bitin INT MASK1 must be set to enable the multiplexed peripheral interrupt PI PEND 1FBEH Peripheral Interrupt Pending MC MD Any set bit indicates a pending interrupt request WG_COMP1 1FC2H Waveform Generator Compare Buffers WG_COMP2 1FC4H Each phas
236. H 00C2H EPA1_TIME 1F46H 7AH 00 6 3DH 00C6H 1EH 00C6H EPA2 TIME MC MD 1F4AH 7AH 00 3DH 00 1EH 00 EPA3_TIME MD 1F4EH 7AH 00 3DH 00 1EH 00 EPA4 TIME MD 1F52H 7AH 00 2 3DH 00D2H 1EH 00D2H 5 TIME MD 1F56H 7AH 00 6 3DH 00D6H 1EH 00D6H FREQ ONT MD 1FBAH 7DH 00 00 1 00 FREQ_GEN MD 1FB8H 7DH 00 00 8 1 00B8H GEN CON MH 1FAOH 7DH 00 00 1 00A0H P1 DIR MH 1F9AH 7CH OOFAH 3EH 00DAH 1FH 009AH P2 DIR 1FD2H 7EH 00 2 0002 00D2H P7_DIR MD 1FD3H 7EH 0OF3H 3FH 00D3H 1FH 00D3H P1_MODE MH 1F98H 7CH 00 8 00D8H 1FH 0098H P2_MODE 1FDOH 7EH OOFOH 3FH 00DOH 1FH 00DOH P7 MODE MD 1FD1H 7EH 00 00D1H 1FH 00D1H PO_PIN MC MD 1FA8H 7DH 00 8 00E8H 1FH 00A8H PO PIN MH 1FDAH 7EH 00DAH 1FH 00DAH P1 PIN MC 1FA8H 7DH 00 8 00E8H 1FH 00A8H 1 PIN MH 1F9EH 7CH 00 00 1 009 P2 PIN 1FD6H 7EH 00 6 00D6H 1FH 00D6H P7 PIN MD 1FD7H 7EH 00F7H 3FH 00D7H 1FH 00D7H P1_REG 1F9CH 7CH 00 00DCH 1FH 009CH P2 REG 1FD4H 7EH 00F4H 3FH 00D4H 1FH 00D4H P7_REG MD 1FD5H 7EH 00 5 00D5H 1FH 00D5H PI MASK 1FBCH 7DH 00 00 1 00 PEND 1FBEH 7DH 00 00 1 00 PWM_COUNT 1FB6H 7DH 00 6 OOF6H 1FH 00 6 PWM_PERIOD 1FB4H 7DH 00F4H 3EH 00F4H
237. HER UNSIGNED Tests both the zero flag and the carry flag If either the JH cadd carry flag is clear or the zero flag is set i control passes to the next sequential 11011001 disp instruction If the carry flag is set and the zero flag is clear this instruction adds to the NOTE The displacement disp is sign program counter the offset between the end extended to 16 bits of this instruction and the target label effecting the jump The offset must be in range of 128 to 127 if C 1 AND Z 0 then PC lt PC 8 bit disp PSW Flag Settings Z N C V VT ST JLE JUMP IF SIGNED LESS THAN OR EQUAL Tests both the negative flag and the zero flag JLE cadd If both flags are clear control passes to the next soguer instruction If either flag is set 11011010 disp this instruction adds to the program counter the offset between the end of this instruction NOTE The displacement disp is sign and the target label effecting the jump The extended to 16 bits offset must be in the range of 128 to 127 if N 1 ORZ 1 then PC lt PC 8 bit disp PSW Flag Settings Z N C V VT ST 8XC196MC MD MH USER S MANUAL intel Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format JLT JUMP IF SIGNED LESS THAN Tests the negative flag If the flag is clear control JLT cadd passes to the next s
238. I O Port SFRs 1FD2H Reserved P2_DIR Address High Odd Byte Low Even Byte 1FDOH Reserved P2_MODE 1F8EH Reserved Reserved Waveform Generator SFRs 1F8CH SP1_BAUD H SP1_BAUD L Address High Odd Byte Low Even Byte 1F8AH SP1_CON SBUF1_TX 1FCEH Reserved WG_PROTECT 1F88H SP1_STATUS SBUF1_RX 1FCCH WG_CONTROL H WG_CONTROL L 1F86H Reserved Reserved 1FCAH WG_COUNTER H WG_COUNTER L 1F84H SPO_BAUD H SPO BAUD L 1FC8H WG RELOAD H WG RELOAD L 1F82H SPO CON SBUFO TX 1FC6H WG COMPS H WG COMP3 L 1F80H SPO STATUS SBUFO RX 1FC4H WG_COMP2 H WG 2 L EPA and Timer SFRs 1FC2H WG_COMP1 H WG COMP L Address High Odd Byte Low Even Byte 1FCOH WG OUTPUT H WG OUTPUT L HF7EH 2 TIMER2 L Peripheral Interrupt and PWM SFRs 1F7CH Reserved T2CONTROL Address High Odd Byte Low Even Byte HF7AH TIMER1 H TIMER1 L 1FBEH Reserved PEND 1F78H Reserved T1CONTROL 1FBCH Reserved PI MASK 1FBAH Reserved Reserved 1F72H T1RELOAD H T1RELOAD L 1FB8H Reserved Reserved 1FB6H Reserved PWM_COUNT 1F62H COMP2_TIME H COMP2_TIME L 1FB4H Reserved PWM_PERIOD 1F60H Reserved COMP2_CON 1FB2H Reserved PWM1_CONTROL 1F5EH COMP1_TIME H COMP1_TIME L 1FBOH Reserved PWMO CONTROL 1F5CH Reserved COMP1 CON A D SFRs 1F5AH COMPO TIME H COMPO TIME L Address High Odd Byte Low Even Byte 1F58H Reserved COMPO CON 1FAEH AD TIME AD TEST
239. IOD Load Shared Circuitry A2761 02 Figure 10 1 PWM Block Diagram 10 2 PWM SIGNALS AND REGISTERS Table 10 1 describes the PWM s signals and Table 10 2 briefly describes the control and status registers Table 10 1 PWM Signals PWM PWM Signal Signal Type Description P6 6 PWMO Pulse width modulator 0 output with high drive capability P6 7 PWM1 Pulse width modulator 1 output with high drive capability 10 2 intel PULSE WIDTH MODULATOR Table 10 2 PWM Control and Status Registers Mnemonic Address Description PWMO CONTROL PWM1 CONTROL 1FBOH 1FB2H PWM Duty Cycle This register controls the PWM duty cycle A zero loaded into this register will cause the PWM to output a low continuously 0 duty cycle An FFH in this register will cause the PWM to have its maximum duty cycle 99 6 duty cycle PWM_PERIOD 1FB4H PWM Period This register holds a programmed value that determines the output period of the PWM outputs The value is reloaded into the counter each time the count resets to FFH PWM_COUNT 1FB6H PWM Counter This read only register contains the current value of the decremented counter WG_OUTPUT 1FCOH Waveform Generator Output Bits 11 and 12 PE6 and PE7 determine whether the corresponding pin functions as a standard port pin or as a PWM output Bits 6 and 7 P6 and P7 defin
240. Idle mode 2 11 13 13 14 4 14 5 entering 14 5 pin status B 23 B 25 timeout control 11 7 IDLPD instruction A 2 A 16 A 46 A 51 A 57 IDLPD 1 14 5 IDLPD 2 14 6 illegal operand 13 9 13 12 Immediate addressing 3 6 INC instruction A 2 A 16 A 41 A 47 A 52 INCB instruction A 2 A 17 A 41 A 47 A 52 Indexed addressing 3 9 and register RAM 4 10 and windows 4 19 Indirect addressing 3 6 and register RAM 4 10 with autoincrement 3 7 Input pins level sensitive B 13 sampled B 13 unused 13 2 INST B 16 Instruction set 3 1 and PSW flags A 5 code execution 2 5 2 6 conventions 1 3 execution times A 52 A 53 lengths A 47 A 52 opcode map 2 3 opcodes 41 46 overview 3 1 3 4 protected instructions 5 9 reference 1 3 See also RISM INT_MASK 14 2 INTEGER defined 3 3 Interfacing with external memory configuring port pins 15 5 registers 15 4 signals 15 1 Interrupt mask 1 register 5 16 C 26 Interrupt mask register 5 15 C 25 Interrupt pending 1 register 5 22 C 28 INDEX Interrupt pending register 5 21 C 27 Interrupts 5 1 5 58 controller 2 6 5 1 end of PTS 5 25 inhibiting 5 9 latency 5 9 5 11 calculating 5 10 priorities 5 4 5 5 modifying 5 18 5 19 procedures PLM 96 3 11 processing 5 2 programming 5 12 5 19 selecting PTS or standard service 5 12 service routine processing 5 19 sources 5 5 unused inputs 13 2 vectors 5 1 5 5 vectors memory location
241. Input A D converter P1 6 MD P1 7 MD intel PORTS Table 6 3 Input only Port Registers Mnemonic Address Description PO_PIN 1FA8H MD Each bit of PO PIN reflects the current state of the corresponding 1FDAH port 0 pin P1_PIN MC MD 1FA9H MC MD Each bit of P1_PIN reflects the current state of the corresponding port 1 pin 6 2 1 Standard Input only Port Operation Figure 6 1 is a schematic of an input only port pin Transistors 1 and Q2 serve as electrostatic discharge ESD protection devices they are referenced to and ANGND Transistor is an additional ESD protection device it is referenced to V digital ground Resistor limits current flow through Q3 to acceptable levels At this point the input signal is sent to the analog multiplexer and to the digital level translation buffer The level translation buffer converts the in put signals to work with the and lt digital voltage levels used by the CPU core This buffer is Schmitt triggered for improved noise immunity The signals are latched in the PO PIN or PIN register and are output onto the internal bus when PO PIN or P1 PIN is read Internal Bus Vcc VREF VREF To Analog MUX PORT 0 Data Register Level Q1 Translation Buffer Buffer 150 to 200 Ohms Input Pin Read Port PH1 Clock Vss Vss Vss ANGND ANGND A0236 01
242. LU or the prefetch queue queue requests always have priority This queue is transparent to the RALU and your software NOTE When using a logic analyzer to debug code remember that instructions are preloaded into the prefetch queue and are not necessarily executed immediately after they are fetched When the bus controller receives a request from the queue it fetches the code from the address contained in the slave PC The slave PC increases execution speed because the next instruction byte is available immediately and the processor need not wait for the master PC to send the ad dress to the memory controller If a jump interrupt call or return changes the address sequence the master PC loads the new address into the slave PC then the CPU flushes the queue and con tinues processing 2 3 5 Interrupt Service The microcontroller s flexible interrupt handling system has two main components the program mable interrupt controller and the peripheral transaction server PTS The programmable inter rupt controller has a hardware priority scheme that can be modified by your software Interrupts that go through the interrupt controller are serviced by interrupt service routines that you provide The peripheral transaction server PTS a microcoded hardware interrupt processor provides high speed low overhead interrupt handling You can configure most interrupts except NMI trap and unimplemented opcode to be serviced by the PTS instead of
243. ME COMPx TIME Address Table C 3 x 0 3 8XC196MC MH Reset State x 0 5 8XC196MD The EPA compare x time COMPx TIME registers are the event time registers for the EPA compare channels they are functionally identically to the EPAx TIME registers The EPA triggers a compare event when the reference timer matches the value in COMPx TIME 15 0 EPA Event Time Value Bit Number 15 0 EPA Event Time Value Write the desired compare event time to this register Function Table C 3 COMPx TIME Addresses and Reset Values Register Address Reset Value COMPO TIME 8XC196Mx 1F5AH XXXXH COMP1 TIME 8XC196Mx 1F5EH XXXXH COMP2 TIME 8XC196Mx 1F62H XXXXH COMP3 TIME 8XC196MC MD 1F66H XXXXH COMP3 TIME 8XC196MH 1F4EH XXXXH 4 TIME 8XC196MD 1F6AH XXXXH COMPS5 TIME 8XC196MD 1F6EH XXXXH 8XC196MC MD MH USER S MANUAL intel EPAx CON EPAx CON x 0 1 8XC196MH x 0 3 8XC196MC x 0 5 8XC196MD Address Table C 4 Reset State The EPA control EPAx CON registers control the functions of their assigned capture compare channels 7 0 x 0 2 4 TB CE M1 MO RE WGR ROT ON RT 7 0 x 1 3 5 TB CE M1 MO RE AD ROT ON RT Bit Bit Number Mnemonic Function 7 TB Time Base Select Specifies the reference timer 0 timer 1 is the reference timer and timer 2 is the opposite timer 1 timer 2 is the referenc
244. Mode Before entering powerdown complete the following tasks Complete all serial port transmissions or receptions Otherwise when the device exits powerdown the serial port activity will continue where it left off and incorrect data may be transmitted or received Complete all analog conversions If powerdown occurs during the conversion the result will be incorrect If the watchdog timer WDT is enabled clear the WATCHDOG register just before issuing the powerdown instruction This ensures that the device can exit powerdown cleanly Otherwise the WDT could reset the device before the oscillator stabilizes The WDT cannot reset the device during powerdown because the clock is stopped Putall other peripherals into an inactive state After completing these tasks execute the IDLPD 7 2 instruction to enter powerdown mode NOTE To prevent an accidental return to full power hold the external interrupt pin EXTINT low while the device is in powerdown mode 14 4 3 Exiting Powerdown Mode The device will exit powerdown mode when any of the following events occurs e an external device drives the V pin low for at least 50 ns ahardware reset is generated atransition occurs on the external interrupt pin 14 4 3 1 Driving the Vpp Pin Low If the design uses an external clock input signal rather than the on chip oscillator the fastest way to exit powerdown mode is to drive the V pin low for at least 50 ns Use this
245. NVERTER FUNCTIONAL OVERVIEW The A D converter Figure 12 1 can convert an analog input voltage to an 8 or 10 bit digital result and set the A D interrupt pending bit when it stores the result It can also monitor an input and set the A D interrupt pending bit when the input voltage crosses over or under the pro grammed threshold voltage Analog Inputs t Analog Mux Sample and Hold EPA or PTS Command Control Successive Logic Approximation A D Converter Status AD RESULT t Multiplexed with port inputs AD COMMAND AD TIME AD TEST A2652 02 Figure 12 1 A D Converter Block Diagram 12 1 8XC196MC MD MH USER S MANUAL intel 12 2 A D CONVERTER SIGNALS AND REGISTERS Table 12 1 lists the A D signals and Table 12 2 describes the control and status registers Al though the analog inputs are multiplexed with I O port pins no configuration is necessary Table 12 1 A D Converter Pins Port Pin A D Signal A D Signal Type Description P1 4 0 P1 5 0 ACH12 8 MC ACH13 8 MD Analog inputs See the Voltage on Analog Input Pin specification in the datasheet P0 7 0 ACH7 0 MD Analog inputs See the Voltage on Analog Input Pin specification in the datasheet ANGND GND Reference Ground Must be connected for A D converter and port operation Vngr PWR Reference Voltage Must be connected for A D c
246. OMP1_CON 1F5CH 7AH 00 3DH 00DCH 1EH 00DCH COMP2 CON 1F60H 7BH OOEOH 3DH 00 1EH 00 1F64H 7BH 00 4 3DH 00 4 1EH 00 4 4_ 1F68H 7BH OOE8H 3DH 00 8 1EH 00 8 5 MD 1F6CH 7BH 00 3DH 00 1EH 00 1F5AH 7AH 00 3DH 00DAH 1EH 00DAH 1 TIME 1F5EH 7AH 00 3DH 00DEH 1EH 00DEH 2 TIME 1F62H 7BH 00 2 3DH 00 2 1EH 00 2 1F66H 7BH OOE6H 3DH 00 6 1EH 00 6 4 TIME MD 1F6AH 7BH 00 3DH 00 00 COMP5 MD 1F6EH 7BH 00 00 1EH 00 EPAO 1F40H 7AH OOEOH 3DH 00COH 1EH 00COH EPA1 1F44H 7AH 00 4 3DH 00C4H 1EH 00C4H Must be addressed as a word C 68 intel REGISTERS WSR Table C 12 WSR Settings and Direct Addresses for Windowable SFRs Continued 32 byte Windows 64 byte Windows 128 byte Windows 00 0 00 0 0 0080 00FFH Register Mnemonic WSR Direct WSR Direct WSR Direct Address Address Address EPA2_CON MC MD 1F48H 7AH 00 8 3DH 00C8H 1EH 00C8H EPA3 MC MD 1F4CH 7AH 00 3DH 00CCH 1EH 00CCH EPA4 CON MD 1F50H 7AH OOFOH 3DH 00DOH 1EH 00DOH EPA5 CON MD 1F54H 7AH 00F4H 3DH 00D4H 1EH 00D4H EPAO TIME 1F42H 7AH 00 2 3DH 00C2H 1E
247. OVRTM Setting INT 5 0 enables OVRTM Setting 5 2 enables OVRTM2 C 37 8XC196MC MD MH USER S MANUAL PEND intel PI PEND Continued Address Reset State 1FBEH AAH When hardware detects a pending peripheral or timer interrupt it sets the corresponding bit in the interrupt pending INT PEND or INT PEND1 registers and the peripheral interrupt pending PEND register When the vector is taken the hardware clears the INT PEND INT PEND1 pending bit Reading this register clears all the PEND b setting a PEND bit its Software can generate an interrupt by 7 0 8XC196MC WG OVRTM2 OVRTM1 7 0 8XC196MD COMP5 WG OVRTM2 OVRTM1 7 0 8XC196MH SP1 SPO OVRTM2 OVRTM1 Function 0 OVRTM1 Timer 1 Overflow Underflow When set this bit indicates a pending timer 1 overflow underflow interrupt The timer 1 and timer 2 overflow underflow interrupts are associated with the overflow underflow timer interrupt OVRTM Setting INT 5 0 enables OVRTM Setting MASK 0 enables OVRTM1 C 38 intel REGIST ERS PPW PPW no direct access The programming pulse width PPW register is loaded from the external EPROM locations 14H and 15H for the 8XC196MC and MD locations 4014H and 4015H for the 8 196 in auto programming m
248. P1 PACT S 14 o 13 P2 4 COMPO AINC Vcc P7 3 COMP5 9 13 54 15 7 2 COMP4 2 7 2 3 2 2 EPA2 PROG 7 1 5 1264 17 5 116 18 5 10 E 19 US 9 2 20 N8XC196MD P7 0 EPA4 US 8 E 21 P2 1 PALE NC E 22 P2 0 PVER NC E 23 P7 7 FREQOUT US 7 24 View of component as P0 0 ACHO US 6 25 mounted on PC board P0 1 ACH1 US 5 9 26 P0 2 ACH2 US 4 6 27 0 3 ACH3 US 3 2 28 P0 4 PMODE O US 2 129 P0 5 ACH5 PMODE 1 US 1 2 30 VREF ADO P3 0 PBI US 0 rJ 31 L3 ANGND P1 7 132 20 6 ACH6 PMODE 2 CO LO KO xr LO NMQ C CO CO CO CO CO x x xb xb xb Mb LO 00 10 ESOS LOS IXON uz u i zoz OozoOGorrool 55 099 5 lt lt 55 x me PHL LL TSS OSS G grooxLr t rot eter tprraag I lt Q 5 Ss an ee N a A3102 02 Figure B 4 8XC196MD 84 lead PLCC Package 8XC196MC MD MH USER S MANUAL intel 80 Fa P5 5 BHE2 WRH 79 El P5 3 RD 78 B Vpp 77 P5 0 ALE ADV 76 Vss 73 P5 4 ONCE 72 EXTINT 71 B Vss 70 B XTAL1 69 XTAL2 68 6 67 P7 5 74 Ea P5 6 READY 66 P7 4 75 P5 1 INST 65 F P6 6 PWMO
249. PTSVEC1 L SAMPTIME PTSDST H PTSDST H PTSPTR2 H BAUD H DATA H PTSDST L PTSDST L PTSPTR2 L BAUD L DATA L PTSSRC H PTSSRC H PTSPTR1 H EPAREG H PTSCON1 PTSSRC L PTSSRC L PTSPTR1 L EPAREG L PORTMASK PTSCON PTSCON PTSCON PTSCON PORTREG PTSVECT PTSCOUNT PTSCOUNT PTSCOUNT PTSCOUNT PORTREG L 8XC196MC and MD only 5 6 1 Specifying the PTS Count Figure 5 13 PTS Control Blocks The first location of the PTSCB contains an 8 bit value called PISCOUNT This value defines the number of interrupts that will be serviced by the PTS routine The PTS decrements PTSCOUNT after each PTS cycle When PTSCOUNT reaches zero hardware clears the corre sponding PTSSEL bit and sets the PTSSRV bit Figure 5 6 which requests an end of PTS inter rupt The end of PTS interrupt service routine should reinitialize the PTSCB if required and set the appropriate PTSSEL bit to re enable PTS interrupt service 5 25 8XC196MC MD MH USER S MANUAL intel PTSSRV Address Reset State 0006H 0000H The PTS service PTSSRV register is used by the hardware to indicate that the final PTS interrupt has been serviced by the PTS routine When PTSCOUNT reaches zero hardware clears the corre sponding PTSSEL bit and sets the PTSSRV bit which requests the end of PTS interrupt When the end of PTS interrupt is called hardware clears the PTSSRV bit The PTSSEL bit must be set manually to re enable the PTS channel
250. ROGRAMMING THE EPA AND TIMER COUNTERS This section discusses configuring the port pins for the EPA and the timer counters describes how to program the timers the capture compare channels and the compare only channels and explains how to enable the EPA interrupts 11 5 1 Configuring the EPA and Timer Counter Signals Before you can use the EPA you must configure the appropriate port signals to serve as the spe cial function signals for the EPA and optionally for the timer counter clock source and direction control signals See Bidirectional Ports 1 MH Only 2 5 and 7 MD Only on page 6 4 for information about configuring the ports Table 11 2 on page 11 2 lists the signals associated with the EPA and the timer counters Signals that are not being used for an EPA channel or timer counter can be configured as standard I O 11 5 2 Programming the Timers The control registers for the timers are TICONTROL Figure 11 8 T2CONTROL Figure 11 9 Write to these registers to configure the timers Write to the TIMER and TIMER regis ters see Table 11 3 on page 11 3 for addresses to load a specific timer value 11 15 8XC196MC MD MH USER S MANUAL intel T1CONTROL Address 1F78H Reset State 00H The timer 1 control T1 CONTROL register determines the clock source counting direction and count rate for timer 1 7 0 CE UD M2 M1 MO P2 P1 PO Bit Bit Function Number Mnemonic
251. ROL H WG_CONTROL L 1F66H COMP3_TIME COMP3_TIME L 1FCAH WG_COUNTER H WG_COUNTER L 1F64H Reserved COMP3_CON 1FC8H WG_RELOAD WG_RELOAD L 1F62H COMP2_TIME COMP2_TIME L 1FC6H WG_COMP3 H WG COMPS L 1F60H Reserved COMP2 CON 1FC4H WG_COMP2 H WG 2 L 1F5EH COMP1 TIME H COMP1 TIME L 1FC2H WG_COMP1 WG COMP L 1F5CH Reserved COMP1 CON 1FCOH WG OUTPUT H WG OUTPUT L 1F5AH COMPO TIME H COMPO TIME L Peripheral Interrupt and PWM SFRs 1F58H Reserved COMPO CON Address High Odd Byte Low Even Byte 1F56H Reserved Reserved 1FBEH Reserved PEND 1FBCH Reserved PI MASK 1F4EH TIME EPA3 TIME L 1 Reserved 1FB6H Reserved PWM_COUNT 1F4AH EPA2_TIME H EPA2_TIME L 1FB4H Reserved PWM_PERIOD 1F48H Reserved EPA2_CON 1FB2H Reserved PWM1_CONTROL 1F46H EPA1_TIME H EPA1_TIME L 1FBOH Reserved PWMO CONTROL 1F44H Reserved EPA1 CON A D SFRs 1F42H EPAO TIME H EPAO TIME L Address High Odd Byte Low Even Byte 1F40H Reserved EPAO CON 1FAEH AD TIME AD TEST 1FACH Reserved AD COMMAND 1FAAH AD RESULT H AD RESULT L 1FA8H P1 PIN PO PIN 1FA6H Reserved Reserved 1F80H Reserved Reserved Must be addressed as a word 4 6 intel MEMORY PARTITIONS Table 4 5 Peripheral SFRs 8XC196MD Ports 2 and 7 SFRs EPA and Timer SFRs
252. Reset Value aac RegisterName D P7_PIN MD Port 7 Pin Input 1FD7 XXXX XXXX P1_REG Port 1 Data Output 1F9D 1111 1111 P2_REG Port 2 Data Output 1FD4 1111 1111 P3_REG Port 3 Data Output 1FFC 1111 1111 P4_REG Port 4 Data Output 1FFD 1111 1111 Port 5 Data Output 1FF5 5_ MH 1111 1111 P7 REG MD Port 7 Data Output 1FD5 1111 1111 PI MASK Peripheral Interrupt Mask 1FBC 1010 1010 PI PEND Peripheral Interrupt Pending 1FBE 1010 1010 PPW Programming Pulse Width no direct PSW Processor Status Word access PTSSEL PTS Select 0004 0000 0000 0000 0000 PTSSRV PTS Service 0006 0000 0000 0000 0000 PWM_COUNT PWM Count 1FB6 0000 0000 PWM_PERIOD PWM Period 1FB4 0000 0000 PWMO CONTROL PWM 0 Control 1FBO 0000 0000 PWM1 CONTROL PWM 1 Control 1FB2 0000 0000 SBUFO RX MH Serial Port Receive Buffer 1F80 0000 0000 SBUF1_RX MH Serial Port Receive Buffer 1F88 0000 0000 SBUFO TX MH Serial Port Transmit Buffer 1F82 0000 0000 SBUF1 TX MH Serial Port Transmit Buffer 1F8A 0000 0000 SP Stack Pointer 0018 XXXX SPO BAUD Serial Port 0 Baud Rate 1284 0000 0000 0000 0000 SP1_BAUD MH Serial Port 1 Baud Rate 1F8C 0000 0000 0000 0000 SPO CON Serial Port Control 1F83 0000 0000 SP1 CON MH Serial Port Control 1F8B 0000 0000 SPO STATUS MH Serial Port Status 1F81 0000 0000 SP1 STATUS MH S
253. SET REFERENCE Table A 1 Opcode Map Right Half Opcode x8 x9 xB xC xD xE xF ox SHR SHL SHRA XCH SHRL SHLL SHRAL NORML ix ds SHRB SHLB SHRAB XCHB ix 2x SCALL ay JBS bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 4x SUB MULU Note 2 di im in ix di im in ix 5x SUBB MULUB Note 2 di im in ix di im in ix 6x SUB 2 MULU 2op Note 2 di im in ix di im in ix 7 SUBB 2 MULUB 2op Note 2 di im in ix di im in ix 8x CMP DIVU Note 2 di im in ix di im in ix 9x CMPB DIVUB Note 2 di im in ix di im in ix SUBC LDBZE Ax 1 di im in ix di im in ix SUBCB LDBSE Bx di im in ix di im in ix Cx PUSH POP BMOVI POP di im in ix di in ix Dx JST JH JLE JC JVT JV JLT JE Ex DPTS Note 1 LCALL CLRC SETC DI EI CLRVT NOP signed RST Fx MUL DIV Note 2 NOTES 1 This opcode is reserved but it does not generate an unimplemented opcode interrupt 2 Signed multiplication and division are two byte instructions The first byte is FE and the second is the opcode of the corresponding unsigned instruction A 3 8XC196MC MD MH USER S MANUAL intel Table A 2 Processor Status Word PSW Flags Mnemonic Description C The carry flag is set to indicate an arithmetic carry from the MSB of the ALU or the state of the last bit shifted out of an operand If a
254. SP 2 PSW Flag Settings Z N C V VT ST POPF 11110011 PUSH PUSH WORD Pushes the word operand onto the stack SP lt SP 2 SP lt DEST PSW Flag Settings Z N C V VT ST PUSH waop 110010aa waop A 29 8XC196MC MD MH USER S MANUAL Table A 6 Instruction Set Continued tel Z N C V VI ST Mnemonic Operation Instruction Format PUSHA PUSH ALL This instruction is used instead of to support the eight additional PUSHA interrupts It pushes two words PSW INT_MASK and INT MASK1 WSR 11110100 onto the stack This instruction clears the PSW INT_MASK and INT 5 registers and decrements the SP by 4 Interrupt calls cannot occur immediately following this instruction SP lt SP 2 SP lt PSW INT MASK PSW INT MASK lt 0 SP lt SP 2 SP lt INT MASK1 WSR INT MASK1 lt 0 PSW Flag Settings 5 0 0 0 0 0 0 PUSHF PUSH FLAGS Pushes the PSW onto the top of the stack then clears it Clearing the PSW pUsHF disables interrupt servicing Interrupt calls cannot occur immediately following this 11110010 instruction SP lt SP 2 SP lt PSW INT MASK PSW INT MASK lt 0 PSW Flag Settings 5
255. SW Flag Settings Z N C V VT ST 1 0 0 0s 00000001 wreg intel INSTRUCTION SET REFERENCE Table A 6 Instruction Set Continued operand The flags are altered but the operands remain unaffected If a borrow occurs the carry flag is cleared otherwise it is set DEST SRC PSW Flag Settings 2 V VT ST Operation Instruction Format CLRB CLEAR BYTE Clears the value of the DEST operand CLRB breg DEST lt 0 00010001 breg PSW Flag Settings 1 0 0 0 CLRC CLEAR CARRY FLAG Clears the carry flag 0 CLRC 11111000 PSW Flag Settings 0 CLRVT CLEAR OVERFLOW TRAP FLAG Clears the overflow trap flag CLRVT VT lt 0 11111100 PSW Flag Settings ST 0 COMPARE WORDS the source DEST SRC word operand from the destination word CMP wreg waop operand The flags are altered but the operands remain unaffected If a borrow 100010 waop wreg occurs the carry flag is cleared otherwise it is set DEST SRC PSW Flag Settings COMPARE BYTES Subtracts the source DEST SRC byte operand from the destination byte CMPB breg 100110aa bao
256. SYNC Synchronize Selects whether updating the WG_OUTPUT register is synchronized with another event or occurs immediately after you change it 0 update WG_OUTPUT immediately 1 synchronize WG_OUTPUT update with an event To ensure that the outputs are in the desired states when the waveform generator starts you should initially clear this bit then set it later if you want subsequent WG_OUTPUT updates to be synchronized with an event Table 9 4 on page 9 8 lists the events that update WG_OUTPUT in each mode 12 PE7 P6 7 PWM1 Function Selects the port function or the PWM output function of P6 7 PWM1 0 P6 7 1 PWM1 11 PE6 P6 6 PWMO Function Selects the port function or the PWM output function of P6 6 PWMO 0 P6 6 1 PWMO Figure 9 8 WG Output Configuration WG_OUTPUT Register 9 13 8XC196MC MD MH USER S MANUAL intel WG_OUTPUT Waveform Generator Continued Address 1FCOH Reset State 0000H The waveform generator output configuration WG OUTPUT register controls the configuration of the waveform generator and PWM module pins Both the waveform generator and the PWM module share pins with port 6 Having these control bits in a single register enables you to configure all port 6 pins with a single write to OUTPUT 15 8 OP1 OPO SYNC PE7 PE6 PH3 2 PH2 2 PH1 2 7 0 P7 PH3 1 PH3 0 PH
257. Signals Functions PENES inactive Idle Powerdown ctive Note 12 P0 5 0 ACH5 0 HiZ HiZ HiZ P0 6 ACH6 T1CLK HiZ HiZ HiZ P0 7 ACH7 T1DIR HiZ HiZ HiZ P1 0 TXDO WK1 WK1 Note 10 Note 10 P1 1 RXDO WK1 WK1 Note 10 Note 10 P1 2 TXD1 WK1 WK1 Note 10 Note 10 P1 3 RXD1 WK1 WK1 Note 10 Note 10 P2 0 EPAO WK1 Note 1 WK1 Note 10 Note 10 P2 1 BCLKO SCLKO WK1 WK1 Note 10 Note 10 P2 2 EPA1 WK1 WK1 Note 10 Note 10 P2 3 COMP3 WK1 WK1 Note 10 Note 10 P2 5 4 COMP 1 0 WK1 WK1 Note 10 Note 10 P2 6 COMP2 MD1 Note 1 MD1 Note 10 Note 10 P2 7 BCLK1 SCLK1 WK1 WK1 Note 10 Note 10 P3 7 0 AD7 0 WK1 HiZ Note 10 Note 3 P4 7 0 AD15 8 WK1 HiZ Note 3 Note 3 P5 0 ADV ALE WK1 Note 1 Note 6 Note 6 Note 6 P5 1 INST WK1 WK1 Note 7 Note 7 P5 2 WR WRL WK1 Note 1 WK1 Note 8 Note 8 P5 3 RD WK1 Note 1 Note 4 Note 8 Note 8 P5 4 ONCE MD1 Note 1 MD1 Note 8 Note 8 P5 5 BHE WRH WK1 Note 5 Note 10 Note 10 P5 6 READY WK1 WK1 Note 9 Note 9 P5 7 BUSWIDTH WK1 WK1 Note 9 Note 9 P6 0 WG1 WK1 WK1 Note 11 Note 11 P6 1 WG1 WK1 WK1 Note 11 Note 11 P6 2 WG2 WK1 WK1 Note 11 Note 11 P6 3 WG2 WK1 WK1 Note 11 Note 11 P6 4 WG3 WK1 WK1 Note 11 Note 11 P6 5 WG3 WK1 WK1 Note 11 Note 11 P6 6 PWMO WKO WK1 Note 11 Note 11 P6 7 PWM1 WKO WK1 Note 11 Note 11 EA HiZ HiZ HiZ EXTINT HiZ HiZ HiZ WKO WKO WKO RESET LoZ0 HiZ HiZ H
258. T RT 7 TB Time Base Select Specifies the reference timer 0 timer 1 is the reference timer and timer 2 is the opposite timer 1 timer 2 is the reference timer and timer 1 is the opposite timer A compare event start of an A D conversion clearing setting or toggling an output pin and or resetting either timer occurs when the reference timer matches the time programmed in the event time register 6 CE Compare Enable This bit enables the compare function 0 compare function disabled 1 compare function enabled 5 4 M1 0 EPA Mode Select Specifies the type of compare event M1 MO 0 0 no output 0 1 clear output pin 1 0 set output pin 1 1 toggle output pin 3 RE Re enable Allows a compare event to continue to execute each time the event time register matches the reference timer rather than only upon the first time match 0 compare function will drive the output only once 1 compare function always enabled Figure 11 11 EPA Compare Control COMPx_CON Registers 11 22 intel EVENT PROCESSOR ARRAY EPA COMPx CON Continued Address See Table 11 3 on x 0 3 8 196 MH page 11 3 X 0 5 8XC196MD Reset State 00H The EPA compare control registers determine the function of the EPA compare channels 7 0 x 0 2 4 TB CE M1 MO RE WGR ROT RT 7 0 x21 3 5 TB CE M1 MO RE AD ROT RT 2 WGR A D C
259. TM2 OVRTM1 Function 7 5 3 1 Reserved These bits are undefined 6 MC Reserved This bit is undefined 5 EPA Compare Channel 5 When set this bit indicates a pending EPA compare channel 5 interrupt The EPA compare channel 5 and the waveform generator interrupts are associated with the peripheral interrupt Pl Setting INT_MASK1 5 enables Setting Pl MASK 6 enables COMP5 SP1 MH Serial Port 1 Error When set this bit indicates a pending serial port 1 error interrupt The serial port 1 and 0 error interrupts are associated with the serial port interrupt SPI Setting INT_MASK1 4 enables SPI Setting PILMASK 6 enables SP1 4 WG MC MD Waveform Generator When set this bit indicates a pending waveform generator interrupt The waveform generator and the EPA compare channel 5 interrupts are associated with the peripheral interrupt Pl Setting INT_MASK1 5 enables Setting Pl MASK 5 enables WG SPO MH Serial Port 0 Error When set this bit indicates a pending serial port 0 error interrupt The serial port 0 and 1 error interrupts are associated with the serial port interrupt SPI Setting INT_MASK1 4 enables SPI Setting PILMASK 4 enables SPO 2 OVRTM2 Timer 2 Overflow Underflow When set this bit indicates a pending timer 2 overflow underflow interrupt The timer 2 and timer 1 overflow underflow interrupts are associated with the overflow underflow timer interrupt
260. TS 5 6 2 Selecting the PTS Mode The second byte of each PTSCB is always an 8 bit value called PISCON Bits 5 7 select the PTS mode Figure 5 15 The function of bits 0 4 differ for each PTS mode Refer to the sections that describe each mode in detail to see the function of these bits Table 5 4 on page 5 12 lists the cycle execution times for each PTS mode PTSCON Address PTSPCB 1 The PTS control PTSCON register selects the PTS mode and sets up control functions for that mode 7 0 M2 M1 MO T t t t t Bit Bit i Number Mnemonic Function 7 5 M2 0 PTS Mode These bits select the PTS mode 2 1 0 0 0 0 block transfer 0 0 1 serial receive MC MD only 0 1 0 reserved 0 1 1 serial transmit MC MD only 1 0 0 single transfer 1 0 1 reserved 1 1 0 A D scan 1 1 1 reserved t The function of this bit depends upon which mode is selected See the PTS control block description in each PTS mode section Figure 5 15 PTS Mode Selection Bits PTSCON Bits 7 5 5 6 3 Single Transfer Mode In single transfer mode an interrupt causes the PTS to transfer a single byte or word selected by the BW bit in from one memory location to another This mode is typically used with the EPA to move captured time values from the event time register to internal RAM for further processing See AP 483 Application Examples Using the SXC196M C MD Microcontroller for application examples
261. This bit selects even or odd parity 0 even parity 1 odd parity 4 TB8 Transmit Ninth Data Bit This is the ninth data bit that will be transmitted in mode 2 or 3 This bit is cleared after each transmission so it must be set before SBUFx_TX is written When parity is enabled SPx_CON 2 1 this bit takes on the even parity value Figure 7 6 Serial Port Control SPx_CON Register 7 10 intel SERIAL 1 0 SIO PORT SPx_CON Continued Address 1F83H 1F8BH x 0 1 8XC196MH Reset State 00H The serial port control SPx CON register selects the communications mode and enables or disables the receiver parity checking and nine bit data transmission 7 0 8XC196MH M2 DIR PAR TB8 1 0 Bit Bit Function Number Mnemonic 3 REN Receive Enable Setting this bit enables receptions When this bit is set a falling edge on the RXDx pin starts a reception in mode 1 2 or 3 In mode 0 this bit must be clear for transmission to begin and must be set for reception to begin Clearing this bit stops a reception in progress and inhibits further receptions To avoid a partial or undesired reception clear this bit before clearing the RI flag in SPx_STATUS This can be handled in an interrupt environment by using software flags or in straight line code by using the interrupt pending register to signal the completion of a reception 2 PEN Parity Enable In m
262. U ER ete 9 12 ES Er 10 2 PWM Control and Status em enne 10 3 PWM Output Frequencies nnns 10 5 PWM Output Alternate 10 8 erret Get t PO eher 11 1 EPA and Timer Counter 11 2 EPA Control and Status Registers Quadrature Mode Truth mener nnne 11 8 Action Taken When a Valid Edge Occurs emm 11 12 Example EPA Control Register Settings for Channels 1 3 or 5 11 18 A D Gonverter PINS 12 2 A D Control and Status 12 2 Minimum Required 5 13 1 VO Port Configuration 13 2 Selecting the Watchdog Reset Interval 8 196 13 13 Operating Mode Control Signals senem een 14 1 Operating Mode Control and Status Registers sse 14 2 External Memory Interface 15 1 External Memory Interface Registers
263. VRTM Setting 5 2 enables OVRTM2 0 OVRTM1 Timer 1 Overflow Underflow When set this bit indicates a pending timer 1 overflow underflow interrupt The timer 1 and timer 2 overflow underflow interrupts are associated with the overflow underflow timer interrupt OVRTM Setting 0 enables OVRTM Setting MASK 0 enables OVRTM1 Figure 5 12 Peripheral Interrupt Pending PEND Register Continued 5 6 INITIALIZING THE PTS CONTROL BLOCKS Each PTS interrupt requires a block of data in register RAM called the PTS control block PTSCB The PTSCB identifies which PTS microcode routine will be invoked and sets up the specific parameters for the routine You must set up the PTSCB for each interrupt source before enabling the corresponding PTS interrupts 5 24 intel The address of the first lowest PTSCB byte is stored in the PTS vector table in special purpose memory see Special purpose Memory on page 4 3 Figure 5 13 shows the PTSCB for each PTS mode Unused PTSCB bytes can be used as extra RAM STANDARD AND PTS INTERRUPTS NOTE The PTSCB must be located in the internal register file The location of the first byte of the PTSCB must be aligned on a quad word boundary an address evenly divisible by 8 Transfer pte SIO 17 SIO 27 Unused Unused Unused PTSVEC1 H Unused Unused PTSBLOCK Unused
264. WG_OUT 12 1 10 8 intel PULSE WIDTH MODULATOR WG_OUTPUT Waveform Generator Address Reset State 1FCOH 0000H The waveform generator output configuration WG_OUTPUT register controls the configuration of the waveform generator and PWM module pins Both the waveform generator and the PWM module share pins with port 6 Having these control bits in a single register enables you to configure all port 6 pins with a single write to WG_OUTPUT 15 8 OP1 OPO SYNC PE7 PE6 PH3 2 PH2 2 PH1 2 7 0 P7 P6 1 0 2 1 2 0 PH1 1 PH1 0 Function 15 1 Output Polarity 14 OPO Output Polarity 13 SYNC Synchronize 12 PE7 P6 7 PWM1 Function Selects either the port function or the PWM output function of P6 7 PWM1 1 PWM1 0 P6 7 11 PE6 P6 6 PWMO Function Selects either the port function or the PWM output function of P6 6 PWMO 1 PWMO 0 P6 6 10 PH3 2 Phase 3 Function PH2 2 Phase 2 Function PH1 2 Phase 1 Function P7 P6 7 PWM1 Value Write the desired P6 7 PWM1 value to this bit 6 P6 P6 6 PWMO Value Write the desired P6 6 PWMO value to this bit 5 4 PH3 1 0 P6 4 WG3 P6 5 WG3 Value 3 2 PH2 1 0 P6 2 WG2 P6 3 WG2 Values 1 0 PH1 1 0 P6 0 WG1 P6 1 WG1 Values Figure 10 6 Waveform Generator Output Configuration WG OUTPUT Register 10 9 8XC196MC MD MH USER S MANUAL intel 10 5 4 Gene
265. XC196MC MD MH USER S MANUAL intel TxTAL1 XTAL1 p 2 22 ALE TLLYX max TLLYx min READY F Tni RH 2TxrALI RD Mee Ini py 2 1 gt gt Tavov 2 gt Mead Address Out Datan read Address Out Data In lt lt 2TxrAL1 4 WR H Tni pv 2TxTAL1 gt I TovwH 2TxraL1 ion Address Out lt Data Out Address A3167 01 Figure 15 9 READY Timing Diagram One Wait State 8 196 Table 15 5 READY Signal Timing Definitions Symbol Definition Tavyv Address Valid to READY Setup Maximum time the external device has to deassert READY after the microcontroller outputs the address to guarantee that at least one wait state will occur READY Hold after CLKOUT Low Minimum time the level of the READY signal must be valid after CLKOUT falls ALE Cycle Time Minimum time between ALE pulses This specification applies to the 8XC196MC MD microcontrollers only tt This specification applies to the 8XC196MH microcontroller only 15 20 intel INTERFACING WITH EXTERNAL MEMORY Table 15 5 READY Signal Timing Definitions Continued Symbol Definition Tu vt READY Hold after ALE Low Minimum time the level of the READY signal must be valid after ALE falls If the maximum v
266. XDDONE intel STANDARD AND PTS INTERRUPTS 10 12 Select PTS service for EPAO Set PTSSEL 2 Set up EPAO to capture on both rising and falling edges Set EPAO CON bits 4 and 5 Figure 11 10 on page 11 19 Enable the PTS and conventional interrupts Use the EI instruction to enable all standard interrupts and the EPTS instruction to enable the PTS Toggle the SCK input to start the reception Data is shifted into the most significant leftmost bit first and shifts right with each successive bit received The EPA generates an interrupt each time that the SCK input toggles The PTS receives the next bit of data on the pin configured as RXD on even PTS cycles When PTSCOUNT decrements to zero the PTS calls the end of PTS interrupt Figure 5 24 The interrupt service routine should disable the EPA channel clear the DATA register reload the PISCOUNT and PTSCONI registers reload EPAO CON and select PTS service for EPAO If the EPA were generating the SCK signal the end of PTS interrupt service routine would also have to reload the EPAO TIME register To determine when all bytes have been transmitted create a loop routine to check the status of the RXDDONE flag 5 49 8XC196MC MD MH USER S MANUAL intel Disable EPA Channel Set up next data reception Clear DATA register Y Reload PTSCOUNT and 1 registers RXDDONE 1 Select PTS service for EPA channel Re initialize the EP
267. _CON MC MD EPA Capture Comp 2 Control 1F48 0000 0000 EPA3_CON MC MD EPA Capture Comp 3 Control 1F4C 0000 0000 EPA4_CON MD EPA Capture Comp 4 Control 1F50 0000 0000 EPA5 CON MD EPA Capture Comp 5 Control 1F54 0000 0000 EPAO TIME EPA Capture Comp 0 Time 1F42 XXXX XXXX XXXX XXXX Reset value is when pin is not driven t Reset value is 80H if the EA pin is high if EA is low ttt The CCRs are loaded with the contents of the chip configuration bytes CCBs after a device reset unless the device is entering programming modes see Entering Programming Modes on page 16 13 in which case the programming chip configuration bytes PCCBs are used The CCBs reside in internal nonvolatile memory at addresses 2018H CCBO and 201AH CCB1 2 intel REGISTERS Table C 2 Register Name Address and Reset Status Continued Binary Reset Value RegisterName EPA1_TIME EPA Capture Comp 1 Time 1F46 XXXX XXXX XXXX 2 MD EPA Capture Comp 2 Time 1F4A XXXX XXXX XXXX EPA3_TIME MC MD EPA Capture Comp 3 Time 1F4E XXXX XXXX XXXX XXXX EPA4_TIME MD EPA Capture Comp 4 Time 1F52 XXXX XXXX XXXX XXXX EPA5 TIME MD EPA Capture Comp 5 Time 1F56 XXXX XXXX 0000 0000 FREQ_CNT MD Frequency Gen Count 1FBA 0000 0000 FREQ_GEN MD Frequency 1FB8 0000 0000
268. _w 11111110b strobe p2 0 to sync p2_dir_w 11111110b scope p2_mode_w 11111110b p2_reg_w 00000001b set pin high temp 5 j pause p2_reg_w 11111110b set pin low WSr zero reg fers and flag register that the interrupt routine needs KKKKKKKKKKKKKKKKKKKKKK buf_start xmit_buf pointer reg buf_cnt buf_size number to send flag 11000000b set buffer send in progress get next byte flags kk ck ck KKK KKK KK KKK KK KK dule s interrupt pending bit he buffer Loop until the buffer then start main program over ck ck ck ck ck ck ck ck KKK KKK KKK KK KK int pend1 400000010b force interrupt flag 7 wait loop here until done start then start over ROUTINE tes each time the EPA compare channel times out identifies the reason for the interrupt request KEK ck ck ck ck ck ck ck ock KKK KK KK KKK KKK comp3 Int vector demo board Save cpu status flag l one pause jump if one being sent flag 0 zero pause jump if zero being sent flag 5 get bit get next bit flag 6 get byte get next byte all done if nothing set done flag 10111111b clear get byte flag shift reg buf_start get byte to send into temp bit_cnt 8 of bits to send per char intel dec_buf_cnt get bit send zero send one zero pa
269. a more accurate worst case value if you use the BMOV instruction in your calculation instead of NORML See Appendix A for instruction execution times For standard interrupts only the response time to get the vector and force the call 11 state times for an internal stack or 13 for an external stack assuming a zero wait state bus 5 4 2 1 Standard Interrupt Latency The worst case delay for a standard interrupt is 56 state times 4 39 11 2 if the stack is in external memory Figure 5 4 This delay time does not include the time needed to execute the first instruction in the interrupt service routine or to execute the instruction following a protected instruction 5 10 intel STANDARD AND PTS INTERRUPTS 4 3 2 1 39 11 2 12 Ending NORML End Call is lf Stack uf lf Stack SS Forced External PUSHA External Routi EXTINT nterrupt Routine Pending Set Cleared Interrupt Response 56 State Times Time A0136 02 Figure 5 4 Standard Interrupt Response Time 5 4 2 2 PTS Interrupt Latency The maximum delay for a PTS interrupt is 43 state times 4 39 as shown in Figure 5 5 This delay time does not include the added delay if a protected instruction is being executed or if a PTS request is already in progress See Table 5 4 for execution times for PTS cycles 4 3 2 1ke 39 gt Ending End Vecto
270. a loop routine to check the status of the TXDDONE flag End Of PTS Interrupt Save Critical Data Disable EPA Channel Clear Interrupt Request Bit T COUNT T COUNT 1 Set up next data transfer Load next data byte into DATA register Reload PTSCOUNT PTSCONI registers Select PTS service for EPA channel 1 Re initialize the EPA channel Re initialize the EPA timer to initiate first bit transfer Load Critical Data A3274 01 Figure 5 22 Synchronous SIO Transmit Mode End of PTS Interrupt Routine Flowchart 5 46 intel STANDARD AND PTS INTERRUPTS 5 6 6 2 Synchronous SIO Receive Mode Example In synchronous serial I O SSIO receive mode an EPA channel controls the reception baud rate by generating or capturing a serial clock signal SCK To generate the SCK signal configure the EPA channel in compare mode and set the output pin toggle option Whenever a match occurs between the EPA event time register and a timer register the EPA channel toggles SCK and gen erates an interrupt If an external source will provide the SCK signal configure the EPA channel in capture mode with capture on either edge set In this case the EPA channel generates an inter rupt whenever the SCK input toggles On every other EPA interrupt the PTS inputs a data bit from a port pin that is configured to function as the Receive Data signal RXD PTSCONI Fig ure 5 19 on page 5 38 controls whe
271. a structure Short indexed addressing can access up to 255 byte locations long indexed addressing can access up to 65 535 byte locations and zero indexed addressing can access a single location An instruction can con tain only one indexed reference any remaining operands must be direct references 3 2 4 1 Short indexed Addressing In a short indexed instruction you specify the offset as an 8 bit constant and the base address as an indirect address register a WORD The following instructions use short indexed addressing LD AX 12H BX lt MEM_WORD BX 12H MULB AX BL 3 lt BL 3 3 7 8XC196MC MD MH USER S MANUAL intel The instruction LD AX 12H B X loads AX with the contents of the memory location that resides at address BX 12H That is the instruction adds the constant 12H the offset to the contents of BX the base address then loads AX with the contents of the resulting address For example if BX contains 1000H then AX is loaded with the contents of location 1012H Short indexed ad dressing is typically used to access elements in a structure where BX contains the base address of the structure and the constant 12H in this example is the offset of a specific element in a struc ture You can also use the stack pointer in a short indexed instruction to access a particular location within the stack as shown in the following instruction LD AX 2 SP 3 2 4 2 Long i
272. after development and testing are complete Run time programming allows you to program individual nonvolatile memory locations during normal code execution under complete software control Customers typically use this mode to download a small amount of information to the microcontroller after the rest of the array has been programmed For example you might use run time programming to download a unique identification number to a security device ROM dump mode allows you to dump the contents of the microcontroller s nonvolatile memory to a tester or to a memory device such as flash memory or RAM Chapter 16 Programming the Nonvolatile Memory provides recommended circuits the corre sponding memory maps and flow diagrams It also provides procedures for auto programming intel Programming Considerations intel CHAPTER 3 PROGRAMMING CONSIDERATIONS This section provides an overview of the instruction set of the MCS9 96 microcontrollers and of fers guidelines for program development For detailed information about specific instructions see Appendix A 3 1 OVERVIEW OF THE INSTRUCTION SET The instruction set supports a variety of operand types likely to be useful in control applications see Table 3 1 NOTE The operand type variables are shown in all capitals to avoid confusion For example a BYTE is an unsigned 8 bit variable in an instruction while a byte is any 8 bit unit of data either signed or
273. alog input voltage to a digital equivalent Resolution is either 8 or 10 bits sample and convert times are programmable Conversions can be performed on the analog ground and reference voltage and the results can be used to calculate gain and zero offset errors The internal zero offset compensation circuit enables automatic zero offset adjustment The A D also has a threshold detection mode which can be used to generate an interrupt when a programmable threshold voltage is crossed in either direction The A D scan mode of the PTS facilitates automated A D conversions and result storage See Chapter 12 alog to digital A D Converter for more information 2 5 8 Watchdog Timer The watchdog timer is a 16 bit internal timer that resets the microcontroller if the software fails to operate properly See Chapter 13 Minimum Hardware Considerations for more informa tion 2 6 SPECIAL OPERATING MODES In addition to the normal execution mode the microcontroller operates in several special purpose modes Idle and powerdown modes conserve power when the microcontroller is inactive On circuit emulation ONCE mode electrically isolates the microcontroller from the system and several other modes provide programming options for nonvolatile memory See Chapter 14 Special Operating Modes for more information about idle powerdown and ONCE modes and see Chapter 16 Programming the Nonvolatile Memory for details about programming op
274. alue is exceeded additional wait states will occur Tu wt ALE Low to READY Setup Maximum time the external device has to deassert READY after ALE falls Data Valid to WR High Time between data being valid on the bus and the microcontroller deasserting WR RD Low Input Data Valid Am time the memory system has to output valid data after the microcontroller asserts RD Low to RD High RD pulse width WR Low to WR High WR pulse width Tyrani All AC timings are referenced to Tyr This specification applies to the 8XC196MC MD microcontrollers only This specification applies to the 8XC196MH microcontroller only 15 5 BUS CONTROL MODES The ALE and WR bits CCRO 3 and CCRO 2 define which bus control signals will be generated during external read and write cycles Table 15 6 lists the four bus control modes and shows the CCRO 3 and CCRO 2 settings for each Table 15 6 Bus control Modes Bus control Mode Bus control Signals TR Standard Bus control Mode ALE RD WR BHE 1 1 Write Strobe Mode ALE RD WRL WRH 1 0 Address Valid Strobe Mode ADV RD WR BHE 0 1 Address Valid with Write Strobe Mode ADV RD WRL WRH 0 15 21 8XC196MC MD MH USER S MANUAL intel 15 5 1 Standard Bus control Mode In the standard bus control mode the microcontroller generates the standard bus control signals ALE RD WR a
275. an apply weak pull ups to them The protection type PT bit in the protection register controls the method ES IT EXTINT Interrupt Request DP EO Bit Register Falling pens Transition Detector Level Sampler OD EXTINT FxrAL1 A CPU Read EO CPU Bus A2661 01 Figure 9 3 Protection Circuitry 9 3 4 Register Buffering and Synchronization The WG_RELOAD WG_COMPx and WG_OUTPUT registers are buffered you read and write the buffers rather than the registers The waveform generator updates the registers synchronously to prevent erroneous or nonsymmetrical duty cycles When you write to the WG_COMPx buffers while the counter is stopped either when the counter register is zero or when the enable counter bit in the control register is clear the registers are updated one half state time later intel WAVEFORM GENERATOR The WG RELOAD register is updated when the counter value reaches the reload value The WG COUNTER register is loaded with the updated RELOAD value so a new reload value takes effect for the next cycle In mode 3 and mode 4 for the 8XC196MH RELOAD register can be updated when an EPA event occurs This requires you to enable an EPA channel s peripheral function See Chapter 11 Event Processor Array EPA for details The WG OUTPUT register contains a synchronization bit that controls whether changes to the output signals are reflected imm
276. ance of an undesired WDT reset The section of code that resets the WDT should monitor the other code sections for proper operation This can be done by checking variables to make sure they are within reasonable values Simply using a software timer to reset the WDT every 10 milliseconds will provide protection only for cata strophic failures intel Memory Partitions intel CHAPTER 4 MEMORY PARTITIONS This chapter describes the address space its major partitions and a windowing technique for ac cessing the upper register file and peripheral SFRs with register direct instructions 4 4 MEMORY PARTITIONS Table 4 1 15 a memory map of the 8XC196Mx devices The remainder of this section describes the partitions 4 1 1 External Devices Memory or I O Several partitions are assigned to external devices see Table 4 1 Data can be stored in any part of this memory Chapter 15 Interfacing with External Memory describes the external memory interface and shows examples of external memory configurations These partitions can also be used to interface with external peripherals connected to the address data bus 4 1 2 Program and Special purpose Memory Internal nonvolatile memory is an optional component of the 8 196 devices Various devic es are available with masked ROM EPROM QROM or OTPROM Please consult the datasheets in the Embedded Microcontrollers databook for details If present the nonvolatile memory occupies
277. and A aS bre 6 16 6 4 8 Design Considerations for Ports and 4 6 16 6 5 STANDARD OUTPUT ONLY PORT 6 sse 8 16 6 5 1 Output only Port Operation 6 17 6 5 2 Configuring Output only Port PINS 6 17 CHAPTER 7 SERIAL I O SIO PORT 7 1 SERIAL I O SIO PORT FUNCTIONAL OVERVIEW 7 2 SERIAL I O PORT SIGNALS AND 7 2 7 3 SERIAL PORT MODES EP 7 3 1 Synchronous Modes Modes 0 and 4 et 7 341 eis cfs dee ee nene te dala idee dene 7 5 7 3 1 25 Mode4 i4 dei eere he eg irte cade evi deae eid 7 6 7 3 2 Asynchronous Modes Modes 1 2 and 3 7 3 2 1 Mode eene tee ur pepe e ez rtm cadi ee decedere 7 7 1 0 2 2 niece eh ea ad A aa 7 8 7 3 2 3 9 5 1e E deret eee t EE E EON Eve ras 7 9 7 3 2 4 2 and Timings 7 9 7 3 2 5 Multiprocessor Communications 7 9 7 4 PROGRAMMING THE SERIAL nennen nennen ens 7 10 7 4 1 Configuring the Serial Port Pins 7 10 7 4 2 Programming the Control Register EE 7 10 7 4 3 Programming the Baud Rate and Clock 74 7 4 4 Enabling the Seria
278. apacitor is disconnected from the selected channel All input pins with the exception of RESET are sampled inputs The input pin is sampled one state time before the read buffer is enabled Sampling occurs during while CLKOUT is low and resolves the value high or low of the pin before it is presented to the internal bus If the pin value changes during the sample time the new value may or may not be recorded during the read RESET is level sensitive input EXTINT 15 normally a sampled input however the powerdown circuitry uses EXTINT as a level sensitive input during powerdown mode Successive approximation register A component of the A D converter The 1 value of a bit or the act of giving it a 1 value See also clear Special function register An 8 bit signed variable with values from 227 through 27 1 A method for converting data to a larger format by filling the upper bit positions with the value of the sign This conversion preserves the positive or negative value of signed integers Current flowing into a device to ground Always a positive value Current flowing out of a device from Always a negative value Stack pointer Glossary 9 8XC196MC MD MH USER S MANUAL special interrupt special purpose memory standard interrupt state time or state successive approximation temperature coefficient temperature drift terminal based characteristic tra
279. aracters in a pair indicate a signal and its condition respectively Symbols represent the time between the two sig nal condition points For example T 4 is the time between signal L ALE ADV condition L Low and signal R RD condition L Low Table 15 7 defines the signal and condition codes Table 15 7 AC Timing Symbol Definitions Signals Conditions A Address Q Output Data H High B BHE R RD L Low Ct CLKOUT WR WRH WRL V Valid D Input Data X XTAL1 X No Longer Valid G BUSWIDTH Y READY Z Floating L ALE ADV The CLKOUT pin is available only on the 8XC196MC MD microcontrollers 15 6 2 AC Timing Definitions Tables 15 8 and 15 9 define the AC timing specifications that the memory system must meet and those that the microcontroller will provide Table 15 8 External Memory Systems Must Meet These Specifications Symbol Definition Address Valid Input Data Valid Maximum time the memory system has to output valid data after the microcontroller outputs a valid address Tnupz RD High to Input Data Float Time after the microcontroller deasserts RD until the memory system must float the bus If this timing is not met bus contention will occur RD Low to Input Data Valid Maximum time the memory system has to output valid data after the microcontroller asserts RD The CLKOUT pin is available only on the 8XC196MC MD microcontrollers
280. asserted only during external memory writes t The chip configuration register 0 CCRO determines whether this pin functions as WR or WRL CCRO 2 1 selects WR CCRO 2 0 selects WRL 15 3 8XC196MC MD MH USER S MANUAL intel Table 15 1 External Memory Interface Signals Continued Signal Name PortPin Type Description WRH P5 5 Write Hight During 16 bit bus cycles this active low output signal is asserted for high byte writes and word writes to external memory During 8 bit bus cycles WRH is asserted for all write operations t The chip configuration register 0 CCRO determines whether this pin functions as BHE or WRH CCRO 2 1 selects BHE CCRO 2 0 selects WRH WRL 5 2 Write Low During 16 bit bus cycles this active low output signal is asserted for low byte writes and word writes to external memory During 8 bit bus cycles WRL is asserted for all write operations t The chip configuration register 0 CCRO determines whether this pin functions as WR or WRL CCRO0 2 1 selects WR 2 0 selects WRL Table 15 2 External Memory Interface Registers Register eir Address Description CCRO 2018H Chip Configuration 0 Controls powerdown mode bus control signals and internal memory protection Three of its bits combine with two bits of CCR1 to control wait states and bus width CCR1 201AH Chip Configuration 1 Enables the
281. ate 2 5 7 8XC196MD x 1 2 5 XC196MH Each pin of port x can operate in any of the standard I O modes of operation complementary output open drain output or high impedance input The port x I O direction DIR register determines the direction for each port x pin The register settings for an open drain output or a high impedance input are identical An open drain output configuration requires an external pull up A high impedance input configuration requires that the corresponding bit in Px REG be set 7 0 1 MH 2 PINO 7 0 2 5 Mx PIN7 6 5 PIN4 2 PINO 7 0 7 MD PIN7 PIN6 5 PIN4 2 PINO Function 7 01 PIN7 0 Port x Pin y Direction This bit selects the Px y direction 0 complementary output output only 1 input or open drain output input output or bidirectional open drain outputs require external pull ups The bits shown as dashes are reserved for compatibility with future devices write ones to these bits C 30 Table C 6 Px_DIR Addresses and Reset Values Register Address Reset Value P1_DIR 8 196 1F9BH FFH P2_DIR 8XC196Mx 1FD2H FFH P5_DIR 8XC196Mx 1FF3H FFH P7_DIR 8XC196MD 1FD3H FFH intel REGISTERS Px MODE Px MODE 2 5 8XC196MC
282. ation and checks the lock bits If either lock bit is programmed the auto programming routine compares the internal secu rity key to the external security key location If the verification fails the device enters an endless internal loop If the security keys match the routine continues The auto programming routine uses the modified quick pulse algorithm and the pulse width value programmed into the external EPROM 16 9 3 Auto Programming Routine Figure 16 13 illustrates the auto programming routine This routine checks the security lock bits in CCBO if either bit is programmed it compares the internal security key to the external security key locations If the security keys match the routine continues otherwise the device enters an endless loop 16 27 8XC196MC MD MH USER S MANUAL intel PMODE 0CH Lock Bits Enabled Verify Security Key Loop Forever Load PPW Assert PACT Get External Data Data OFFFFH Execute Modified Quick Pulse Algorithm then Return Error Programming 2 Clear PVER Increment Address Pointer Top of Deassert PACT OTPROM Loop Forever A0191 03 Figure 16 13 Auto Programming Routine 16 28 intel PROGRAMMING THE NONVOLATILE MEMORY If the security key verification is successful the routine loads the programming pulse width PPW value from the external EPROM into the internal PPW register It then asserts
283. ation bytes PCCBs are used The CCBs reside in nonvolatile memory at addresses 2018H CCBO and 201AH CCB1 intel REGISTERS COMPx_CON COMPx_CON 0 3 8XC196MC MH 0 5 8XC196MD Address Table C 3 Reset State The EPA compare control COMPx_CON registers determine the function of the EPA compare channels 7 0 x 0 2 4 TB CE M1 MO RE WGR ROT RT 7 0 x 1 3 5 TB CE M1 MO RE AD ROT RT 7 TB Time Base Select Specifies the reference timer 0 timer 1 is the reference timer and timer 2 is the opposite timer 1 timer 2 is the reference timer and timer 1 is the opposite timer A compare event start of an A D conversion clearing setting or toggling an output pin and or resetting either timer occurs when the reference timer matches the time programmed in the event time register 6 CE Compare Enable This bit enables the compare function 0 compare function disabled 1 compare function enabled 5 4 M1 0 EPA Mode Select Specifies the type of compare event M1 MO 0 0 no output 0 1 clear output pin 1 0 set output pin 1 1 toggle output pin 3 RE Re enable Allows a compare event to continue to execute each time the event time register COMPx TIME matches the reference timer rather than only upon the first time match 0 compare function will drive the output only once 1 compare function always enabled 8XC196MC MD MH USER S MANUAL in
284. ation registers Registers that specify the environment in which the device will be operating The chip configuration registers are loaded with the contents of the CCBs after a device reset unless the device is entering programming modes in which case the PCCBs are used The difference between corresponding code transitions of actual characteristics taken from different A D converter channels under the same temperature voltage and frequency conditions This error is caused by differences in DC input leakage and on channel resistance from one multiplexer channel to another A graph of output code versus input voltage the transfer function of an A D converter The 0 value of a bit or the act of giving it a 0 value See also set 1 A set of instructions that perform specific function a program 2 The digital value output by the A D converter The voltage corresponding to the midpoint between two adjacent code transitions on the A D converter The point at which the A D converter s output code changes from Q to Q 1 The input voltage corre sponding to a code transition is defined as the voltage that is equally likely to produce either of two adjacent codes The voltage change corresponding to the difference between two adjacent code transitions Code width deviations cause differential nonlinearity and nonlin earity errors See off isolation Leakage current from an analog input pin to ground
285. back up to about 3 5 V The pull up becomes ineffective and the external resistor R takes over and pulls the volt age up to see recovery time in Figure 14 4 The time constant follows an exponential charg ing curve 1 MQ and C 1 uF the recovery time will be one second 14 4 3 4 Selecting R and C The values of R and C are not critical Select components that produce a sufficient discharge time to permit the internal oscillator circuitry to stabilize Because many factors can influence the discharge time requirement you should always fully characterize your design under worst case conditions to verify proper operation 14 8 SPECIAL OPERATING MODES 200 uA C4 Discharge Vpp Volts 2 R4 x C4 Recovery Time Constant Pullup On Code Execution Resumes A0151 01 Figure 14 4 Typical Voltage on the Pin While Exiting Powerdown Select a resistor that will not interfere with the discharge current In most cases values between 200 kQ and 1 MQ should perform satisfactorily 14 9 8XC196MC MD MH USER S MANUAL intel When selecting the capacitor determine the worst case discharge time needed for the oscillator to stabilize then use this formula to calculate an appropriate value for C DIS C E t where C is the capacitor value in farads Tpis is the worst case discharge time in seconds is the discharge current in amperes Ve is the t
286. ber Function 7 0 Setting a bit enables the corresponding interrupt The standard interrupt vector locations are as follows Bit Mnemonic 2 MC MD COMP3 EPA2 MC MD 2 1 EPA1 COMPO EPAO AD OVRTM Both timer 1 and timer 2 can generate the multiplexed overflow underflow interrupt Write to PI MASK to enable the interrupt sources read PEND to determine which source caused the interrupt Interrupt EPA Compare only Channel 2 EPA Compare only Channel 3 EPA Capture Compare Channel 2 EPA Compare Channel 2 EPA Compare Channel 1 EPA Capture Compare Channel 1 EPA Compare Channel 0 EPA Capture Compare Channel 0 A D Conversion Complete Overflow Underflow Timer Standard Vector 200EH 200EH 200CH 200EH 200AH 2008H 2006H 2004H 2002H 2000H Figure 5 7 Interrupt Mask INT MASK Register 5 15 8XC196MC MD MH USER S MANUAL ntel INT_MASK1 Address Reset State 0013H 00H The interrupt mask 1 INT MASK1 register enables or disables masks individual interrupt requests The El and DI instructions enable and disable servicing of all maskable interrupts INT MASK1 can be read from or written to as a byte register PUSHA saves this register on the stack and POPA tt The waveform generator and the EPA compare only channel 5 can generate this interrupt Write to to enable
287. binations are as follows ES IT Event 0 0 falling edge 0 1 rising edge 1 0 low level 1 1 high level 1 DP Disable Protection This bit enables and disables the protection circuitry 0 enable protection 1 disable protection 0 EO Enable Outputs This bit enables and disables the outputs 0 disable outputs 1 enable outputs On the 8XC196MC MD devices this bit is reserved For compatibility with future devices always write as zero C 66 intel REGISTERS WG RELOAD WG RELOAD Address 1FC8H Reset State 0000H The waveform generator reload WG_RELOAD register and the phase compare registers WG_COMPx control the carrier period and duty cycle Write a value to the reload register to establish the carrier period Changing the WG_RELOAD value changes both the carrier period and the duty cycle because the outputs remain asserted for a constant length of time while the counter takes longer to cycle To change the carrier period without changing the duty cycle you must proportionally change both WG_RELOAD and WG COMPx at the same time immediately after the interrupt This register determines the carrier period Use the following formulas to calculate carrier period and duty cycle multiplier x WG RELOAD T CARRIER FyTAL1 RELOAD 7 where ToARRIER carrier period in us Fani input frequency on XTAL1 pin in MHz multiplier 4forcenter aligned modes 2 for edge aligned
288. bles the outputs and the protection circuitry It also selects either level sensitive or edge triggered EXTINT interrupts and selects which level or edge will generate an EXTINT interrupt request 7 0 8XC196MC MD ES IT DP EO 7 0 8XC196MH PT ES IT DP EO Bit Bit Number Mnemonic Function 7 5 Reserved for compatibility with future devices write zeros to these bits 61 Protection This bit selects the method used for disabling the outputs 0 inactive states 1 weak pull ups 3 2 ES Enable Sampling and Interrupt Type IT The ES bit selects whether the protection circuitry samples the EXTINT signal level or detects a signal transition edge while the IT bit controls which value of the edge or level triggers an interrupt request The possible combinations are as follows ES IT Event 0 0 falling edge 0 1 rising edge 1 0 low level 1 1 high level 1 DP Disable Protection This bit enables and disables the protection circuitry 0 enable protection 1 disable protection 0 EO Enable Outputs This bit enables and disables the outputs 0 disable outputs 1 enable outputs On the 8XC196MC MD devices this bit is reserved For compatibility with future devices always write as zero Figure 9 9 Waveform Generator Protection WG PROTECT Register 9 15 8XC196MC MD MH USER S MANUAL intel 9 4 3 Specifying the Carrier Period and Duty C
289. by a string of hexadecimal digits followed by the character H Decimal and binary numbers are represented by their customary notations That is 255 is a decimal number and 1111 1111 is a binary number In some cases the letter B is appended to binary numbers for clarity Bit locations are indexed by 7 0 or 15 0 where bit O is the least significant bit and bit 7 or 15 is the most significant bit An individual bit is represented by the register name followed by a period and the bit number For example WSR 7 is bit 7 of the window selection register In some discussions bit names are used Register mnemonics are shown in upper case For example TIMER2 is the timer 2 register timer 2 is the timer A register name containing a lowercase italic character represents more than one register For example the x in Px REG indicates that the register name refers to any of the port data registers Certain bits are described as reserved bits In illustrations reserved bits are indicated with a dash These bits are not used in this device but they may be used in future implementations To help ensure that a current software design is compatible with future imple mentations reserved bits should be cleared given a value of 0 or left in their default states unless otherwise noted Do not rely on the values of reserved bits consider them undefined Signal names are shown in upper case When several signals share a common name a
290. c is translated and scaled to eliminate zero offset and full scale error as shown in Figure 12 11 The terminal based characteristic is similar to the actual characteristic that would result if zero offset and full scale error were externally trimmed away In practice this is done by using input circuits that include gain and offset trimming In addition could also be closely regulated and trimmed within the specified range to affect full scale error Other factors that affect a real A D converter system include temperature drift failure to com pletely reject unwanted signals multiplexer channel dissimilarities and random noise Fortunate ly these effects are small Temperature drift is the rate at which typical specifications change with a change in temperature These changes are reflected in the temperature coefficients Unwanted signals come from three main sources noise input signal changes on the channel being converted after the sample window has closed and signals applied to channels not selected by the multiplexer The effects of these unwanted signals are specified as Vcc rejection off isolation and feedthrough respectively Finally multiplexer on channel resistances differ slightly from one channel to the next which causes channel to channel matching errors and repeatability errors Differences in DC leakage current from one channel to another and random noise in general con tribute to repeatability errors
291. cannot be used with the peripheral transaction server PTS 11 4 2 Operating in Compare Mode When the selected timer value matches the event time value the action specified in the control register occurs i e the pin is set cleared or toggled an A D conversion is initiated or the wave form generator is reloaded If the re enable bit EPAx CON 3 is set the action reoccurs on ev ery timer match If the re enable bit is cleared the action does not reoccur until a new value is written to the event time register See Programming the Capture Compare Channels on page 11 18 and Programming the Compare only Channels on page 11 22 for configuration informa tion In compare mode you can use the EPA to produce a pulse width modulated PWM output The following sections describe two possible methods 11 4 2 1 Generating a Low speed PWM Output You can generate a low speed pulse width modulated output with a single EPA channel and a standard interrupt service routine Configure the EPA channel as follows compare mode toggle output and the compare function re enabled Select standard interrupt service enable the EPA interrupt and globally enable interrupts with the EI instruction When the assigned timer counter value matches the value in the event time register the EPA toggles the output pin and generates an interrupt The interrupt service routine loads a new value into EPAx TIME 11 13 8XC196MC MD MH USER S MANUAL intel
292. ce and direction control source M2 1 0 ClockSource Direction Source 0 0 0 FyraL1 4 UD bit T1CONTROL 6 X 0 1 UD bit T1CONTROL 6 0 1 0 1 4 T1DIR pin 0 1 1 T1CLK T1DIR pin 1 1 1 quadrature clocking using T1CLK and T1DIR If an external clock is selected the timer counts on both the rising and falling edges of the clock 2 0 P2 0 EPA Clock Prescaler Bits These bits determine the clock prescaler value 2 PO Prescaler Divisor Resolution 0 0 0 divide by 1 disabled 250 ns 0 0 1 divide by 2 500 ns 0 1 0 divide by 4 1 us 0 1 1 divide by 8 2 us 1 0 0 divide by 16 4us 1 0 1 divide by 32 8 us 1 1 0 divide by 64 16 us 1 1 1 enable T1 RELOAD At 16 MHz Use the formula on page 11 6 to calculate the resolution at other frequencies C 53 8XC196MC MD MH USER S MANUAL intel TIRELOAD T1RELOAD Address 1F72H Reset State XXXXH The timer 1 reload T1 RELOAD register contains a reinitialization value for timer 1 The value of T1RELOAD is loaded into TIMER1 when timer 1 overflows or underflows and both quadrature clocking and the reload function are enabled i e T1 CONTROL 5 0 1 15 0 Timer 1 Reload Value Bit Number Function 15 0 Timer 1 Reload Value Write the timer 1 reinitialization value to this register 54 intel REGISTERS T2CONTROL T2CONTROL Address 1F7CH Reset State 00H The t
293. ce integer word operand using signed arithmetic It stores the quotient into the low order word of the destination i e the word with the lower address and the remainder into the high order word The following two statements are performed concurrently low word DEST lt DEST SRC high word DEST lt DEST MOD SRC PSW Flag Settings Z N C V VT ST a DEST SRC DIV lreg waop 11111110 100011aa waop Ireg DIVB DIVIDE SHORT INTEGERS Divides the contents of the destination integer operand by the contents of the source short integer operand using signed arithmetic It stores the quotient into the low order byte of the destination i e the word with the lower address and the remainder into the high order byte The following two statements are performed concurrently low byte DEST lt DEST SRC high byte DEST lt DEST MOD SRC PSW Flag Settings p DEST SRC DIVB wreg baop 11111110 100111aa baop wreg DIVU DIVIDE WORDS UNSIGNED Divides the contents of the destination double word operand by the contents of the source word operand using unsigned arithmetic It stores the quotient into the low order word i e the word with the lower address of the destination operand and the remainder into the high order word The following two statements are
294. circuit then use ROM dump mode to write the entire OTPROM array to an external memory device and verify its contents See ROM dump Mode for details 16 9 5 ROM dump Mode The ROM dump mode provides an easy way to verify the contents of the OTPROM array after auto programming Use the same circuit as for auto programming but change the connections of the PMODE P0 7 4 pins To select ROM dump mode PMODE 6H connect P0 6 and P0 5 to and connect P0 7 and 0 4 to ground The same bank switching mechanism is used and the memory map is the same as that for auto programming The example circuit Figure 16 12 on page 16 26 does not show the necessary WR and connections to allow writing to the EPROM And although the example uses an EPROM you could also use a RAM device Alter natively you could dump the OTPROM contents to any 16 bit parallel port NOTE If you have programmed the DED bit USFR 2 ROM dump mode is disabled See Controlling Fetches from External Memory on page 16 6 To enter ROM dump mode follow the power up sequence on page 16 14 The ROM dump mode checks the security key regardless of the CCR security lock bits If you have programmed a se curity key a matching key must reside in the external memory otherwise the device enters an endless loop If the security key verifies ROM dump mode fetches the PPW then writes the en tire OTPROM array to external memory PACT remains low while the dump is in pr
295. cne e ta ec 2 3 2 2 Block Diagram of the Core seen 2 9 2 3 CIOGK GI CUILDy i ceto erede ete ere ED Sng e rene 2 7 2 4 Internal Clock Phases essen een enne nennen 2 8 4 1 Register File Memory 4 9 4 2 WindoWlfig aoe cae ena 4 12 4 3 Window Selection WSR 4 13 5 1 Flow Diagram for PTS and Standard 5 2 5 2 Waveform Generator Protection 5 7 5 3 Flow Diagram for the OVRTM 5 8 5 4 Standard Interrupt Response Time 9 11 5 5 PTS Interrupt Response Time iioii 5 11 5 6 PTS Select PTSSEL DOTA 5 7 Interrupt Mask INT MASK 5 15 5 8 Interrupt Mask 1 INT_MASK1 eem 5 16 5 9 Peripheral Interrupt Mask 5 17 5 10 Interrupt Pending INT 8 21 5 11 Interrupt Pending 1 INT_PEND1 5 22 5 12 Peripheral Interrupt Pending PEND Register
296. codes instruction lengths and execution times For additional information about the instruction set see Chapter 3 Programming Considerations Appendix B Signal Descriptions provides reference information for the device pins in cluding descriptions of the pin functions reset status of the I O and control pins and package pin assignments intel GUIDE TO THIS MANUAL Appendix C Registers provides a compilation of all device special function registers SFRs arranged alphabetically by register mnemonic It also includes tables that list the win dowed direct addresses for all SFRs in each possible window Glossary defines terms with special meaning used throughout this manual Index lists key topics with page number references 1 2 NOTATIONAL CONVENTIONS AND TERMINOLOGY The following notations and terminology are used throughout this manual The Glossary defines other terms with special meanings assert and deassert clear and set instructions italics The pound symbol has either of two meanings depending on the context When used with a signal name the symbol means that the signal is active low When used in an instruction the symbol prefixes an immediate value in immediate addressing mode The terms assert and deassert refer to the act of making a signal active enabled and inactive disabled respectively The active polarity low or high is defined by the signal name Active
297. component controls the pin The CPU can still write to P5 REG but the pin is unaffected until it is switched back to its standard I O function This feature allows software to configure a pin as standard I O clear P5 y initialize or overwrite the pin value then configure the pin as a special function signal set P5 MODE y In this way initialization fault recovery exception handling etc can be done without changing the operation of the associated peripheral Table 15 3 Register Settings for Configuring External Memory Interface Signals Port Pin Name t Signal Type Port Register Settings P5 0 ALE ADV P5_DIR 110X 0000 P5 1 INST 5_ 111 1111 5 2 WR WRL P5_REG 11 XXXXB 5 RD 5 5 BHE WRH 5 6 READY 5 7 BUSWIDTH Kx t The chip configuration register 0 CCRO which is loaded at reset from the chip configuration byte 0 CCBO 2018H during normal operation determines whether P5 2 functions as BHE or WRH and whether P5 5 functions WR WRL 2 1 selects BHE and WR CCRO 2 1 selects WRH and WRL 15 2 CHIP CONFIGURATION REGISTERS AND CHIP CONFIGURATION BYTES Two chip configuration registers CCRs have bits that set parameters for chip operation and ex ternal bus cycles The CCRs cannot be accessed by code They are loaded from the chip config uration bytes CCBs which reside in nonvolat
298. cribes the memory protection options 16 17 8XC196MC MD MH USER S MANUAL intel CCR1 CCRO no direct access The chip configuration registers CCRs control wait states powerdown mode and internal memory protection These registers are loaded from the PCCBs during programming modes and from the CCBs for normal operation 7 0 1 1 0 1 WDE BW1 IRC2 0 7 0 LOC1 LOCO IRC1 IRCO ALE WR BWO PD Bit Mnemonic Function WDE Watchdog Timer Enable PCCB default is initially disabled enabled the first time WDT is cleared BW1 Buswidth Control PCCB default selects BUSWIDTH pin control IRC2 Internal Ready Control PCCB default selects READY pin control LOC1 0 Security Bits PCCB default selects no protection IRC1 0 Internal Ready Control PCCB default selects READY pin control ALE Select Address Valid Strobe Mode PCCB default selects ALE WR Select Write Strobe Mode PCCB default selects WR and BHE BWO Buswidth Control PCCB default selects BUSWIDTH pin control PD Powerdown Enable PCCB default enables powerdown Figure 16 6 Chip Configuration Registers CCRs 16 18 intel PROGRAMMING THE NONVOLATILE MEMORY 16 8 4 Slave Programming Routines The slave programming mode algorithm consists of three routines the address command decod ing routine the program word routine and the dump word routine The address command decoding routine Figure
299. ct value add the baud_value ODOH to the current TIMERI value and store the result in EPAO TIME The baud value determines the time to the first PTS interrupt and the first transition on SCK The PTS transmits the first data bit on first transition of SCK in this example The baud value of ODOH selects a baud rate of 9600 12 Enable the PTS and conventional interrupts Use the EI instruction to enable all standard interrupts and the EPTS instruction to enable the PTS 13 The transmission will begin Data is shifted out with the least significant rightmost bit first Each time a timer match occurs between EPAO TIME and TIMERI the EPAO channel generates an interrupt and toggles the SCK signal The PTS outputs the next bit of data on the pin configured as TXD on odd PTS cycles When PTSCOUNT decrements to zero the PTS calls the end of PTS interrupt Figure 5 22 The interrupt service routine should disable the EPA channel because the final PTS cycle loads the next SCK toggle 5 45 8XC196MC MD MH USER S MANUAL intel 14 time into the event time register If this toggle occurs the clock polarity will change because of the odd number of toggles and erroneous data may be output The interrupt service routine should also load the next data byte reload the PPSCOUNT and PTSCONI registers select PTS service for EPAO reload both the EPAO CONTROL EPAO TIME registers To determine when all bytes have been transmitted create
300. ction Format SHL SHIFT WORD LEFT Shifts the destination word operand to the left as many times as specified by the count operand The count may be specified either as an immediate value in the range of 0 to 15 OFH inclusive or as the content of any register 10H OFFH with a value in the range of 0 to 31 1FH inclusive The right bits of the result are filled with zeros The last bit shifted out is saved in the carry flag Temp lt COUNT do while Temp 0 C lt High order bit of DEST DEST lt DEST x 2 Temp lt Temp 1 end while PSW Flag Settings 2 V VT ST SHL wreg count 00001001 count wreg or SHL wreg breg 00001001 breg wreg SHLB SHIFT BYTE LEFT Shifts the destination byte operand to the left as many times as specified by the count operand The count may be specified either as an immediate value in the range of 0 to 15 OFH inclusive or as the content of any register 10H OFFH with a value in the range of 0 to 31 1FH inclusive The right bits of the result are filled with zeros The last bit shifted out is saved in the carry flag Temp lt COUNT do while Temp 0 lt High order bit of DEST DEST lt DEST x 2 Temp lt Temp 1 end while PSW Flag Settings 2 V 5 SHLB breg count 00011001 count breg or
301. ction register 9 15 C 66 WDE bit 13 12 WG3 1 B 22 WG3 1 B 22 Window selection register See WSR Windowing 4 12 4 19 examples 4 16 4 19 See also windows Windows 4 12 4 19 addressing 4 16 and addressing modes 4 19 and memory mapped SFRs 4 15 base address 4 14 4 15 locations that cannot be windowed 4 15 offset address 4 14 selecting 4 13 setting up with linker loader 4 17 Index 13 8XC196MC MD MH USER S MANUAL WSR values and direct addresses 4 15 WORD defined 3 2 World Wide Web 1 11 WR B 22 idle powerdown reset status B 23 B 25 WRH B 22 Write cycles 16 bit data bus 15 14 8 bit data bus 15 16 Write strobe mode example system 15 26 signals 15 25 WRL B 22 WSR 4 13 C 68 X X defined 1 5 x defined 1 3 XCH instruction A 2 A 3 A 40 A 41 A 49 A 55 XCHB instruction A 2 A 3 A 40 A 41 A 49 A 55 XOR instruction A 2 A 40 A 43 A 48 A 53 XORB instruction A 2 A 40 A 43 A 44 A 48 A 53 XTALI 13 2 B 22 and Miller effect 13 7 and programming modes 16 13 and SIO baud rate 7 14 hardware connections 13 6 13 7 XTAL2 13 2 B 22 hardware connections 13 6 13 7 Y y defined 1 3 Z Zero Z flag A 4 A 5 A 18 A 19 A 20 A 21 Zero register C 71 Index 14
302. ction that immediately follows the command that invoked the power saving mode In idle mode asserting any enabled interrupt causes the device to resume normal operation NMI Nonmaskable Interrupt In normal operating mode a rising edge on NMI generates a nonmaskable interrupt NMI has the highest priority of all prioritized interrupts Assert NMI for greater than one state time to guarantee that it is recognized Table 5 2 Interrupt and PTS Control and Status Registers Mnemonic Address Description INT MASK 0008H Interrupt Mask Registers INT MASK1 0013H These registers enable disable each maskable interrupt that is each interrupt except unimplemented opcode software trap and NMI INT PEND 0009H Interrupt Pending Registers INT PEND1 0012H The bits in this register are set by hardware to indicate that an interrupt is pending PI MASK 1FBCH Peripheral Interrupt Mask The bits in this register enable and disable mask the timer 1 and 2 overflow underflow interrupt requests the waveform generator interrupt request MC MD the EPA compare only channel 5 interrupt request MD and the serial port error interrupts MH 5 3 8XC196MC MD MH USER S MANUAL intel Table 5 2 Interrupt and PTS Control and Status Registers Continued Mnemonic Address Description PI PEND 1FBEH Peripheral Interrupt Pending Any bit set indicates a pending interrupt request PSW No direct access Processor Status Word
303. ctional Categories Address amp Data Programming Control Input Output Input Output Cont d AD15 0 AINC P0 5 0 ACH5 0 P5 0 CPVER P0 6 ACH6 T1CLK P5 1 Bus Control amp Status PACT P0 7 ACH7 T1 DIR P5 7 2 ALE ADV PALE P1 0 TXDO P6 0 WG1 BHE WRH PBUS 15 0 P1 1 RXDO P6 1 WG1 BUSWIDTH PMODE 3 0 P1 2 TXD1 P6 2 WG2 INST PROG P1 3 RXD1 P6 3 WG2 READY PVER P2 0 EPAO P6 4 WG3 RD P2 1 SCLKO BCLKO P6 5 WG3 WR WRL Processor Control P2 2 EPA1 P6 6 PWMO EA P2 3 COMP3 P6 7 PWM1 Power amp Ground EXTINT P2 4 COMPO ANGND NMI 2 5 1 Voc ONCE P2 6 COMP2 Vop RESET P2 7 SCLK1 BCLK1 VREE XTAL1 P3 7 0 Vss XTAL2 P4 7 0 NOTE The shaded signals are not available in the 64 pin package B 9 8XC196MC MD MH USER S MANUAL Vss P5 0 ALE ADV 5 3 RD 5 5 BHE WRH P5 2 WR WRL 5 7 BUSWIDTH 14 P4 6 PBUS 14 AD13 P4 5 PBUS 13 15 P4 7 PBUS 15 c 2 1 012 P4 4 PBUS AD11 P4 3 PBUS AD10 P4 2 PBUS 10 AD9 P4 1 PBUS 9 08 P4 0 PBUS 8 AD7 P3 7 PBUS 7 AD6 P3 6 PBUS 6 AD5 P3 5 PBUS 5 AD4 P3 4 PBUS 4 AD3 P3 3 PBUS 3 2 P3 2 PBUS 2 AD1 P3 1 PBUS 1 ADO P3 0 PBUS 0 RESET NMI P6 5 WG3 P6 4 WG3 P6 3 WG2 Oar U8XC196MH View of component as mounted on PC board P5 6 READY P5
304. cts either the general purpose input output function or the peripheral function for each pin of port 2 Set P2_MODE 1 and P2_MODE 7 to configure SCLKOZ BCLKO P2 1 and SCLK1 BCLK1 P2 7 for the SIO port P2 PIN 1FD6H Port 2 Pin State Two bits of this register contain the values of the SCLKOZ BCLKO P2 1 and SCLK1 BCLK1 P2 7 pins Read P2 PIN to determine the current value of the pins P2 REG 1FD4H Port 2 Output Data This register holds data to be driven out on the pins of port 2 Set P2 REG 1 and P2 REG 7 for the SCLKO BCLKO P2 1 and SCLK1 BCLK1 P2 7 pins 7 3 8XC196MC MD MH USER S MANUAL intel Table 7 2 Serial Port Control and Status Registers Continued Mnemonic Address Description PI MASK 1FBCH Peripheral Interrupt Mask This register enables and disables multiplexed peripheral interrupts Setting an SPx bit enables a serial port receive error interrupt clearing the bit disables masks the interrupt PEND 1FBEH Peripheral Interrupt Pending This register indicates pending multiplexed peripheral interrupts When set an SPx bit indicates a pending serial port receive error interrupt SBUFO RX 1F80H Serial Port x Receive Buffer SBUF1 RX 1F88H This register contains data received from the serial port SBUFO TX 1F82H Serial Port x Transmit Buffer SBUF1 TX 1F8AH This register contains data that is ready for transmission In modes 1 2 and 3 writing to SBUFx TX starts a transmission
305. curity key Auto and slave programming permitted with matching 1 9 Yes security key 0 X 0 X X All programming unconditionally disabled If you want to prohibit all programming clear both PCCBO lock bits If these bits are cleared they prevent the device from entering any programming mode If you want to prevent programming but allow ROM dumps leave the PCCBO read protection bit 7 unprogrammed and clear the PCCBO write protection bit PCCBO 6 To protect against unauthorized reads program an internal security key The ROM dump mode compares the internal security key location with an externally supplied security key regardless of the CCBO lock bits If the security keys match the routine continues otherwise the device enters an endless internal loop If you want to allow slave and auto programming as well as ROM dumps leave both PCCBO lock bits unprogrammed To protect against unauthorized programming clear the CCBO lock bits and program an internal security key After the device enters either slave or auto programming mode the corresponding test ROM routine reads the CCBO lock bits If either CCBO lock bit is enabled the routine compares the internal security key location with an externally supplied security key If the security keys match the routine continues otherwise the device enters an endless internal loop 16 5 8XC196MC MD MH USER S MANUAL intel You can program the internal security key i
306. d Mnemonic Length Opcode Length Opcode Length Opcode Length Opcode NORML 3 OF SHL 3 09 SHLB 3 19 SHLL 3 oD SHR 3 08 SHRA 3 0A SHRAB 3 1A SHRAL 3 SHRB 3 18 SHRL 3 0 Special Direct Immediate Indirect Indexed Mnemonic Length Opcode Length Opcode Length Opcode Length Opcode CLRC 1 F8 CLRVT 1 FC DI 1 FA El 1 FB IDLPD 1 F6 NOP 1 FD RST 1 FF SETC 1 F9 SKIP 2 00 PTS Direct Immediate Indirect Indexed Mnemonic Length Opcode Length Opcode Length Opcode Length Opcode DPTS 1 EC EPTS 1 ED NOTES 1 For indexed instructions the first column lists instruction lengths as S L where S is the short indexed instruction length and L is the long indexed instruction length 2 For the SCALL and SJMP instructions the three least significant bits of the opcode are concatenated with the eight bits to form an 11 bit two s complement offset A 51 8XC196MC MD MH USER S MANUAL lel Table A 9 lists instructions alphabetically within groups along with their execution times ex pressed in state times Table A 9 Instruction Execution Times in State Times Arithmetic Group 1
307. d circuit con figurations Consult the manufacturer s datasheet for the requirements 13 6 intel MINIMUM HARDWARE CONSIDERATIONS 13 5 USING AN EXTERNAL CLOCK SOURCE To use an external clock source apply a clock signal to XTAL1 and let XTAL2 float Figure 13 5 To ensure proper operation the external clock source must meet the minimum high and low times and Ty and the maximum rise and fall transition times Ty 44 and Figure 13 6 The longer the rise and fall times the higher the probability that external noise will affect the clock generator circuitry and cause unreliable operation See the datasheet for required XTALI voltage drive levels and actual specifications Clock Input ucs 96 Clock Driver Microcontroller No Connection 1 Required if TTL driver is used Not needed if CMOS driver is used A0274 03 Figure 13 5 External Clock Connections Txuxc 0 7 0 5 V 0 7 Vec 0 5 V Tux 0 3 Veg 0 5 V 0 3 Vo 0 5 V T XLXL A2119 02 Figure 13 6 External Clock Drive Waveforms At power on the interaction between the internal amplifier and its feedback capacitance i e the Miller effect may cause a load of up to 100 pF at the pin if the signal at XTAL1 is weak such as might be the case during start up of the external oscillator This situation will g
308. dance Note 4 NOTES 1 2 3 4 X Don t care If Px REG is cleared Q2 is on if REG is set Q2 is off Px PIN contains the current value on the pin During reset and until the first write to Px MODE Q4 is on Table 6 7 Logic Table for Bidirectional Ports in Special function Mode Open drain Configuration Complementary Output Output Input Px MODE 1 1 1 1 Px DIR 0 0 1 1 SFDIR 0 0 1 1 SFDATA 0 1 0 1 Note 2 1 Px REG X X X 1 Q1 off on off off Q2 on off on off Note 2 off Px PIN 0 1 X Note 3 high impedance Note 4 NOTES 1 X Don t care 2 If Px_REG is cleared Q2 is on if REG is set Q2 is off 3 PIN contains the current value on the pin 4 During reset and until the first write to MODE Q4 is on 6 3 2 Bidirectional Port Pin Configurations Each bidirectional port pin can be individually configured to operate either as an I O pin or as a pin for a special function signal In the special function configuration the signal is controlled by an on chip peripheral or an off chip component In either configuration two modes are possible complementary output output only high impedance input or open drain output input output or bidirectional 6 9 8XC196MC MD MH USER S MANUAL intel To prevent the CMOS inputs from floating the bidirectional port pins are weakly pulled high dur ing and after reset until your software writ
309. dance input However as an analog input a pin must provide current for a short time to charge the internal sample capacitor when a conversion begins This means that if a conversion is taking place on a port pin its input characteristics change mo mentarily 6 3 BIDIRECTIONAL PORTS 1 MH ONLY 2 5 AND 7 MD ONLY Although the bidirectional ports are very similar in both circuitry and configuration port 5 differs from the others in some ways Port 5 a memory mapped port uses a standard CMOS input buffer because of the high speeds required for system control functions The remaining bidirectional ports use Schmitt triggered input buffers for improved noise immunity NOTE Ports 3 and 4 are significantly different from the other bidirectional ports See Bidirectional Ports 3 and 4 Address Data Bus on page 6 14 for details on the structure and operation of these ports Table 6 4 lists the bidirectional port pins with their special function signals and associated periph erals Table 6 4 Bidirectional Port Pins Port Pin Special function Special function Associated Signal s Signal Type Peripheral P1 0 MH TXDO SIO P1 1 MH RXDO SIO P1 2 MH TXD1 SIO P1 3 MH RXD1 SIO P2 0 EPAO yo EPA EPA1 MC MD yo EPA P2 1 SCLKO MH y o SIO BCLKO MH SIO poo EPA2 MC MD yo EPA EPA1 MH yo EPA
310. des can be taken as simple ratiometric information or they pro vide information about absolute voltages or relative voltage changes on the inputs The more demanding the application the more important it is to fully understand the converter s operation For simple applications knowing the absolute error of the converter is sufficient However closing a servo loop with analog inputs requires a detailed understanding of an A D converter s operation and errors 12 13 8XC196MC MD MH USER S MANUAL intel In many applications it is less critical to record the absolute accuracy of an input than it is to de tect that a change has occurred This approach is acceptable as long as the converter is monotonic and has no missing codes That is increasing input voltages produce adjacent unique output codes that are also increasing Decreasing input voltages produce adjacent unique output codes that are also decreasing In other words there exists a unique input voltage range for each 10 bit output code that produces that code only with a repeatability of typically 0 25 LSBs 1 5 mV The inherent errors in an analog to digital conversion process are quantizing error zero offset er ror full scale error differential nonlinearity and nonlinearity All of these are transfer function errors related to the A D converter In addition temperature coefficients rejection sample hold feedthrough multiplexer off isolation channel to channe
311. destination byte SUBB breg operand stores the result in the destination operand and sets the carry flag as the 011110aa baop breg complement of borrow DEST lt DEST SRC PSW Flag Settings 2 V VT ST Vi iviv 7111 SUBB SUBTRACT BYTES Subtracts the first DEST SRC1 SRC2 3 operands source byte operand from the second stores SUBB Dbreg Sbreg baop the result in the destination operand and sets the carry flag as the complement of borrow 010110aa Sbreg Dbreg DEST lt SRC1 SRC2 PSW Flag Settings 2 V VT ST SUBC SUBTRACT WORDS WITH BORROW DEST SRC Subtracts the source word operand from the SUBC wreg waop destination word operand If the carry flag was clear SUBC subtracts 1 from the result 101010aa wreg It stores the result in the destination operand and sets the carry flag as the complement of borrow DEST lt DEST SRC 1 0 PSW Flag Settings Z N C V VT ST SUBCB SUBTRACT BYTES WITH BORROW DEST SRC Subtracts the source byte operand from the SUBCB breg baop destination byte operand If the carry flag was clear SUBCB subtracts 1 from the result 101110aa baop breg stores the result in the destination operand and sets the carry flag as the complement of borro
312. determine the duty cycle of the outputs You specify the duty cycle by writing a value to each phase s compare register WG_COMPx In all operating modes the out puts are initially asserted and they remain asserted until the counter value WG_COUNTER matches the phase s compare register WG_COMPx value At this point the outputs are deas serted and remain deasserted until another event occurs The event that causes the outputs to be asserted again depends on the operating mode See Operating Modes on page 9 7 The dead time generator circuitry Figure 9 2 prevents an output and its complement from being asserted at the same time It uses two internal signals WFG and DT to generate the nonoverlap ping outputs The edge detection circuitry generates the WFG signal while a 10 bit dead time counter generates the DT signal When a valid edge is detected the dead time counter is loaded with the 10 bit dead time value from the control register and DT is driven low The counter dec rements once every state time until it reaches zero at which point the counter stops and DT is driven high The WFG signal is ANDed with DT to produce the WG_EVEN signal the WFG signal is ANDed with DT to produce the WG_ODD signal The waveform generator s outputs can be connected to the WG_EVEN and WG_ODD signals See Configuring the Outputs on page 9 12 Output Disable From Protection Circuit 10 Bit Value WG_CONTROL To Other Bits 0
313. ding to the SFR s address For example writ ing to PA REG causes a bus cycle that writes to external memory location 1FFDH Because P3 REG and REG have no effect when EA is active the bus will float during long periods of inactivity such as during a BMOV or TIJMP instruction When is inactive ports 3 and 4 output the contents of the REG and P4 REG registers which reset to FFH placing the pins in a high impedance state Ports 3 and 4 will float unless you either connect external resistors to the pins or write zeros to the P3 REG and P4 REG registers 6 5 STANDARD OUTPUT ONLY PORT 6 Port 6 is an output only port that provides output pins for the waveform generator and pulse width modulator PWM The port 6 pins can be configured to operate either as port pins or as output pins for the waveform generator or pulse width modulator Table 6 2 lists the pins with their spe cial function signals and associated peripherals intel PORTS Table 6 14 Standard Output only Port Pins Port Pin Special function Special function Associated Signal s Signal Type Peripheral P6 0 WG1 Output Waveform generator P6 1 WG1 Output Waveform generator P6 2 WG2 Output Waveform generator P6 3 WG2 Output Waveform generator P6 4 WG3 Output Waveform generator P6 5 WG3 Output Waveform generator P6 6 PWMO Output PWM P6 7 PWM1 Output PWM Table 6 15 Output only Port Control Register Mnemon
314. e 8XC196MC MD MH USER S MANUAL intel Table B 3 8XC196MD Signals Arranged by Functional Categories Address amp Data Programming Control Input Output Input Output Cont d AD15 0 AINC P0 7 0 ACH7 0 P7 1 0 EPA5 4 CPVER P1 1 0 ACH9 8 P7 3 2 COMP5 4 Bus Control amp Status PACT P1 2 ACH10 T1CLK P7 6 4 ALE ADV PALE P1 3 ACH11 T1DIR P7 7 FREQOUT BHE WRH PBUS 15 0 P1 5 4 ACH13 12 BUSWIDTH PMODE 3 0 P1 7 6 INST PROG P2 3 0 EPA3 0 READY PVER P2 7 4 COMP3 0 RD P3 7 0 WR WRL Processor Control P4 7 0 CLKOUT P5 7 0 Power amp Ground EA P6 0 WG1 ANGND EXTINT P6 1 WG1 Voc NMI P6 2 WG2 Vop ONCE P6 3 WG2 VREE RESET P6 4 WG3 Vss XTAL1 P6 5 WG3 XTAL2 P6 7 6 PWM1 0 B 6 SIGNAL DESCRIPTIONS AD15 P4 7 PBU 014 P4 6 PBU AD13 P4 5 PBU CLKOUT o 16 AD12 P4 4 PBU AD11 P4 3 PBU AD10 P4 2 PBU 9 P4 1 PB AD8 P4 0 PB AD7 P3 7 PBI AD6 P3 6 PB AD5 P3 5 PB AD4 P3 4 PBI P3 3 2 2 PB AD1 P3 1 PBI 1 A P5 7 BUSWIDTH 10 F P5 2 WR WRL 8 H P5 5 BHE WRH A P5 3 RD P5 0 ALE ADV 2 P5 6 READY e P5 4 ONCE 84 EXTINT 77 5 P6 6 PWMO 76 Ea P6 7 PWM1 75 P2 6 COMP2 CPVER 83 Vss 82 5 XTAL1 81 E XTAL2 H P7 6 79 a P7 5 78 H P7 4 S 15 o 12 P2 5 COM
315. e 8XC196MC and MD PBUS 13 8 are multiplexed with AD13 8 and P4 5 0 PBUS15 14 are multiplexed with P1 2 1 On the 8XC196MH PBUS 11 8 are multiplexed with AD11 8 and P4 3 0 PBUS15 12 are multiplexed with P1 3 0 PMODE 3 0 Programming Mode Select Determines the programming mode PMODE is sampled after a device reset and must be static while the microcontroller is operating Table 16 7 on page 16 13 lists the PMODE values and programming modes PMODE 3 0 are multiplexed with P0 7 4 ACH7 4 On the 8XC196MH PMODE 2 is also is also multiplexed with T1CLK and PMODE 3 is also multiplexed with T1DIR B 19 8XC196MC MD MH USER S MANUAL intel Table B 6 Signal Descriptions Continued Name Type Description PROG Programming Start During programming a falling edge latches data on the PBUS and begins programming while a rising edge ends programming The current location is programmed with the same data as long as PROG remains asserted so the data on the PBUS must remain stable while PROG is active During a word dump a falling edge causes the contents of an OTPROM location to be output on the PBUS while a rising edge ends the data transfer On the 8XC196MC and MD PROG is multiplexed with P2 2 and EPA2 On the 8XC196MH PROG is multiplexed with P2 2 and EPA1 PVER Program Verification During slave or auto programming PVER is updated after each programming pulse A high output signal
316. e compare buffer contains a value that is compared with the WG_COMP3 1FC6H counter value The action that is performed when a match occurs depends on the operating mode 9 3 8XC196MC MD MH USER S MANUAL intel Table 9 2 Waveform Generator Control and Status Registers Continued Mnemonic Address Description WG CONTROL 1FCCH Waveform Generator Control The control register determines the waveform generator s operating mode starts and stops the counter specifies the dead time for all phases and indicates the current count direction WG COUNTER 1FCAH Waveform Generator Count Value The read only counter register reflects the current counter value WG OUTPUT 1FCOH Waveform Generator Output Control The output control register configures the waveform generator s outputs and selects their active polarity WG PROTECT 1FCEH Waveform Generator Protection The protection register enables and disables the protection circuitry and the outputs selects level sensitive or edge triggered interrupts and controls which value of the edge or level will trigger an interrupt request 8XC196MH only This register also selects the method for disabling the outputs inactive states or weak pull ups WG RELOAD 1FC8H Waveform Generator Reload Value The reload register contains a value that is compared with the counter value The actions performed based on this comparison depend on the operating mode
317. e high output signal is asserted only during external memory cycles ALE signals the start of an external bus cycle and indicates that valid address information is available on the system address data bus ALE differs from ADV in that it does not remain active during the entire bus cycle An external latch can use this signal to demultiplex the address from the address data bus ALE is multiplexed with P5 0 and ADV ANGND GND Analog Ground ANGND must be connected for A D converter and port 0 operation also Port 1 on the 8XC196MC and MD ANGND and Vs should be nominally at the same potential BCLK1 0 Baud Clock 0 and 1 MH only BCLKO and 1 are alternate clock sources for the baud rate generator input The maximum input frequency is Fyz4 4 4 BCLKO is multiplexed with P2 1 SCLKO and PALE BCLK1 is multiplexed with P2 7 and SCLK1 BHE Byte High Enable During 16 bit bus cycles this active low output signal is asserted for word and high byte reads and writes to external memory BHE indicates that valid data is being transferred over the upper half of the system data bus Use BHE in conjunction with ADO to determine which memory byte is being transferred over the system bus BHE ADO Byte s Accessed 0 0 both bytes 0 1 high byte only 1 0 low byte only BHE is multiplexed with P5 5 and WRH The chip configuration register 0 CCRO determines whether this pin functions as BHE or WRH CCRO 2 1 selects BHE
318. e interrupt service routines addresses The peripheral transac tion server PTS a microcoded hardware interrupt processor provides high speed low over head interrupt handling it does not modify the stack or the PSW You can configure most interrupts except NMI trap and unimplemented opcode to be serviced by the PTS instead of the interrupt controller The PTS supports seven special microcoded routines that enable it to complete specific tasks in much less time than an equivalent interrupt service routine can It can transfer bytes or words either individually or in blocks between any memory locations manage multiple analog to dig ital A D conversions and transmit and receive serial data in either asynchronous or synchro nous mode MC MD only PTS interrupts have a higher priority than standard interrupts and may temporarily suspend interrupt service routines A block of data called the PTS control block PTSCB contains the specific details for each PTS routine see Initializing the PTS Control Blocks on page 5 24 When a PTS interrupt occurs the priority encoder selects the appropriate vector and fetches the PTS control block PTSCB 5 1 8XC196MC MD MH USER S MANUAL intel Interrupt Pending or PTSSRV Bit Set NMI Yes Pending Return Yes PTS Enabled No Priority Encoder Yes Highest Priority Interrupt Encoder Highest Priority PTS Interrupt Yes No Res
319. e little effect on the duty cycle if the pulse is relatively wide however longer dead times with narrower pulses can affect the duty cycle Figure 9 14 No minimum pulse width is imposed by the hardware so itis possible to deassert an output for the entire period if the total dead time is greater than the pulse width For this reason software should ensure that the pulse width is at least 3 x Theap WG COUNT 1 1 1 1 1 WG_COUNT Dead Time Dead Time WG COMP T Increased Increased 7 Na Dead Time 1 m d _ P6 0 WG1 i i DT x WFG P6 1 WG1 No WFG1 Output DT x WFG Mode 0 OPO OP1 1 PH1 0 PH1 1 1 2 1 Power Output Driver Enabled C Dead Time A2660 01 Figure 9 14 Effect of Dead Time on Duty Cycle 9 20 intel WAVEFORM GENERATOR 9 7 2 EXTINT Interrupts and Protection Circuitry The protection register contains two bits disable protection DP and enable output EO that to gether enable and disable the waveform generator s outputs The EXTINT event generates a sin gle short pulse that clears the EO bit so if software sets the EO bit immediately following an EXTINT event the outputs will be disabled only for the time between the EXTINT event and the CPU write The CPU can immediately set the EO bit again even if the EXTINT signal remains asserted 9 8 PROGRAMMING EX
320. e next period Use the following duty cycle formula to calculate a desired duty cycle for given values of PWMx_CONTROL and PWM_PERIOD and then write these values to the appropriate registers Duty Cycle in Pulsewidth us where PWMx_CONTROL PWM_PERIOD Pulsewidth Tpwm 10 6 PWMx_CONTROL PWM_PERIOD 1 100 Duty Cycle x 100 8 bit value to load into the PWMx_CONTROL register 8 bit value to load into the PWM_PERIOD register width of each high pulse output period on the PWM pin in us intel PULSE WIDTH MODULATOR PWMx CONTROL Address Table 10 2 on page x 0 1 10 3 Reset State 00H The PWM control PWMx CONTROL register determines the duty cycle of the PWM x channel A zero loaded into this register causes the PWM to output a low continuously 0 duty cycle An FFH in this register causes the PWM to have its maximum duty cycle 99 696 duty cycle 7 0 PWM Duty Cycle Bit Number 7 0 PWM Duty Cycle This register controls the PWM duty cycle A zero loaded into this register causes the PWM to output a low continuously 0 duty cycle An FFH in this register causes the PWM to have its maximum duty cycle 99 6 duty cycle Function Figure 10 4 PWM Control PWMx_CONTROL Register 10 5 1 Sample Calculations For example assume that equals 16 MHz and the value written to the PWM_PERIOD reg ister is FFH thus the desired period of the PWM ou
321. e of 128 to 127 extended to 16 bits if Z 1 then PC lt PC 8 bit disp PSW Flag Settings Z N C V VT ST JGE JUMP IF SIGNED GREATER THAN OR EQUAL Tests the negative flag If the JGE cadd negative flag is set control passes to the next sequential instruction If the negative 11010110 disp clear this instruction adds to the program counter the offset between the end of this NOTE The displacement disp is sign instruction and the target label effecting the extended to 16 bits jump The offset must be in the range of 128 to 127 if N 0 then PC lt PC 8 bit disp PSW Flag Settings ST intel INSTRUCTION SET REFERENCE Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format JGT JUMP IF SIGNED GREATER THAN Tests both the zero flag and the negative flag If JGT cadd either flag is set control passes to the next sequential instruction If both flags are clear 11010010 disp this instruction adds to the program counter the offset between the end of this instruction NOTE The displacement disp is sign and the target label effecting the jump The extended to 16 bits offset must be in the range of 128 to 127 0 AND Z 0 then PC lt PC 8 bit disp PSW Flag Settings ST JH JUMP IF HIG
322. e service for the end of PTS interrupt request If an interrupt request occurs while interrupts are disabled the corresponding pending bit is set in the INT PEND or INT PENDI register PTS service is not useful for multiplexed interrupts because the PTS cannot readily determine the source of these interrupts 8XC196MC MD MH USER S MANUAL intel PTSSEL Address Reset State 0004H 0000H The PTS select PTSSEL register selects either a PTS microcode routine or a standard interrupt service routine for each interrupt request Setting a bit selects a PTS microcode routine clearing a bit selects a standard interrupt service routine When PTSCOUNT reaches zero hardware clears the corresponding PTSSEL bit The PTSSEL bit must be set manually to re enable the PTS channel 15 8 8XC196MC EXTINT COMP3 EPA3 7 0 2 EPA2 COMP1 EPA1 COMPO OVRTM 15 8 8XC196MD EXTINT PI EPA5 COMP4 4 COMP3 7 0 COMP2 2 1 1 OVRTM 15 8 8XC196MH EXTINT WG SPI RIO TH TIO 7 0 COMP3 COMP2 COMP1 EPA1 COMPO AD OVRTM Bit 2 Number Function 15 Reserved for compatibility with future devices write zero to this bit 14 07 Setting a bit causes the corresponding interrupt to be handled by a PTS microcode routine The PTS interrupt vector locations
323. e the pin output when the port pin function is selected PEx Pin Output 0 0 0 0 1 1 1 X PWM Output 10 3 PWM OPERATION The period register PWM PERIOD controls the output frequency of both PWM outputs Each control register PWMx CONTROL controls the duty cycle the pulsewidth stated as a percent age of the period of the corresponding PWM output Each control register contains an 8 bit value that is loaded into a buffer when the 8 bit counter rolls over from 00H to FFH The comparators compare the contents of the buffers to the counter value Since the value written to the control register is buffered you can write a new 8 bit value to PWVMx CONTROL at any time However the comparators do not recognize the new value until the counter has expired the remainder of the current 8 bit count The new value is used during the next PWM output period 10 3 8XC196MC MD MH USER S MANUAL intel The counter counts down to 00H at which time the PWM output is driven high the counter value is reloaded from the PERIOD register and the contents of the control registers are loaded into the buffers The PWM output remains high until the counter value matches the value in the buffer at which time the output is pulled low You can read the count register PWM COUNT to see the current value of the counter When the counter resets again 1 when an overflow oc curs the output is switched high Loading PVMx CONTROL with
324. e timer and timer 1 is the opposite timer A compare event reloading the waveform generator starting an A D conversion clearing setting or toggling an output pin and or resetting either timer occurs when the reference timer matches the time programmed in the event time register When a capture event falling edge rising edge or an edge change on the EPAx pin occurs the reference timer value is saved in the EPA event time register EPAx_TIME 6 CE Compare Enable Determines whether the EPA channel operates in capture or compare mode 0 capture mode 1 compare mode 5 4 1 0 EPA Mode Select In capture mode specifies the type of event that triggers an input capture In compare mode specifies the action that the EPA executes when the reference timer matches the event time 1 0 Capture Mode Event 0 0 no capture 0 1 capture on falling edge 1 0 capture on rising edge 1 1 capture on either edge 1 Compare Mode Action 0 0 no output 0 1 clear output pin 1 0 set output pin 1 1 toggle output pin C 18 intel REGISTERS EPAx CON EPAx CON Continued Address Table C 4 X 0 1 8XC196MH Reset State 0 3 8XC196MC x 0 5 8XC196MD The EPA control EPAx CON registers control the functions of their assigned capture compare channels 7 0 x 0 2 4 TB CE M1 0 WGR ROT ON RT 7 0 x 1 3 5 TB CE M1 0 RE AD ROT ON RT Bit Bit Function Nu
325. e timer value is saved in the EPA event time register EPAx_TIME 6 CE Compare Enable Determines whether the EPA channel operates in capture or compare mode 0 capture mode 1 compare mode 5 4 M1 0 EPA Mode Select In capture mode specifies the type of event that triggers an input capture In compare mode specifies the action that the EPA executes when the reference timer matches the event time 1 0 Capture Mode Event 0 0 no capture 0 1 capture on falling edge 1 0 capture on rising edge 1 1 capture on either edge 1 Compare Mode Action 0 no output 1 clear output pin 0 set output pin 1 toggle output pin Figure 11 10 EPA Control EPAx_CON Registers 11 19 8XC196MC MD MH USER S MANUAL intel EPAx CON Continued Address Table 11 3 on page 11 3 x 0 1 8XC196MH Reset State 00H x 0 3 8XC196MC x z 0 5 8XC196MD The EPA control EPAx CON registers control the functions of their assigned capture compare channels 7 0 x 0 2 4 TB CE M1 MO RE WGR ROT ON RT 7 0 x 1 3 5 TB CE M1 MO RE AD ROT ON RT Bit Bit 3 Number Mnemonic Function 3 RE Re enable Re enable applies to the compare mode only It allows a compare event to continue to execute each time the event time register EPAx_TIME matches the reference timer rather than only upon the first time match 0 compare function is disabled after a sing
326. e to the 8XC196MD The serial I O port is unique to the 8XC196MH 2798 02 Figure 2 1 8XC196Mx Block Diagram Memory Controller Register File RALU Prefetch Queue Microcode Engine Slave PC Register Address Register RAM ALU 9 Master Data Register Bus Controller A2797 01 Figure 2 2 Block Diagram of the Core 2 3 8XC196MC MD MH USER S MANUAL intel 2 3 4 CPU Control The CPU is controlled by the microcode engine which instructs the RALU to perform operations using bytes words or double words from either the 256 byte lower register file or through a win dow that directly accesses the upper register file See Chapter 4 Memory Partitions for more information about the register file and windowing CPU instructions move from the 4 byte prefetch queue in the memory controller into the RALU s instruction register The microcode en gine decodes the instructions and then generates the sequence of events that cause desired func tions to occur 2 3 2 Register File The register file is divided into an upper and a lower file In the lower register file the lowest 24 bytes are allocated to the CPU s special function registers SFRs and the stack pointer while the remainder is available as general purpose register RAM The upper register file contains only general purpose register RAM The register RAM can be accessed as bytes words or double words The RALU accesses the upper and lowe
327. e transmission will begin Data is shifted out with the least significant rightmost bit first Each time a timer match occurs between EPAO TIME and the EPAO channel generates an interrupt and the PTS outputs the next bit of data on the pin configured as TXD When PTSCOUNT decrements to zero the PTS calls the end of PTS interrupt Figure 5 26 The interrupt service routine should load the next data byte reload the PISCOUNT and PTSCONI registers clear bit to create the start bit for the next word to be transmitted select PTS service for EPAO and reload both the 0 CONTROL EPAO TIME registers 15 To determine when all bytes have been transmitted create a loop routine to check the status of the TXDDONE flag 5 53 8XC196MC MD MH USER S MANUAL intel End Of PTS Interrupt Save Critical Data Is PTS Cycle Completed Y Disable EPA Channel Clear Interrupt Request Bit T COUNT T COUNT 1 Set up next data transfer Load next data byte into DATA register Reload PTSCOUNT and PTSCON1 registers Create start bit clear TXD Select PTS service for EPA channel Re initialize the EPA channel Re initialize the EPA timer to initiate first bit transfer Load Critical Data A3276 01 Figure 5 26 Asynchronous SIO Transmit Mode End of PTS Interrupt Routine Flowchart 5 54 intel STANDARD AND PTS INTERRUPTS 5 6 6 4 Asynchronous SIO R
328. e valid until your software writes to Px MODE B 26 intel Registers APPENDIX C REGISTERS This appendix provides reference information about the device registers Table C 1 lists the mod ules and major components of the device with their related configuration and status registers Ta ble C 2 lists the registers arranged alphabetically by mnemonic along with their names addresses and reset values Following the tables individual descriptions of the registers are ar ranged alphabetically by mnemonic Table C 1 Modules and Related Registers A D Converter Chip Configuration CPU 8XC1 ENC X 0 3 8XC196MD x 0 5 AD_COMMAND CCRO ONES_REG COMPx_CON AD_RESULT CCR1 PSW COMPx TIME AD TEST GEN CON 8XC196MH SP EPAx CON AD TIME PPW or SP PPW ZERO REG EPAx TIME USFR Berta Ports Interrupts and PTS Memory Control FREQ_CNT Px DIR INT MASK WSR FREQ GEN INT MASK1 INT PEND Px INT PEND1 PI MASK PI PEND PTSSEL PTSSRV PWM Serial Port Timers Waveform Generator x 0 1 8XC196MH x 0 1 0 1 x 1 3 PWM_COUNT SBUFx_RX TxCONTROL WG_COMPx PWM_PERIOD SBUFx TX T1RELOAD WG_CONTROL PWMx_CONTROL SPx_BAUD TIMERx WG_COUNTER SPx_CON WATCHDOG WG_OUTPUT SPx_STATUS WG_PROTECT WG_RELOAD For the 8XC196MC x 2 5 for the 8XC196MD x 2 5 7 for the 8XC196MH x 1 2 5 tt For the 8 196 and 8XC196MH x 0 5 for the 8XC196MD x
329. eceive Mode Example In asynchronous serial I O ASIO receive mode an EPA channel is set up to capture the falling edge when the data start bit toggles on a port pin that is configured to function as the Receive Data signal RXD When the capture occurs the EPA generates a conventional interrupt which starts the asynchronous receive process This conventional interrupt service routine would be the same as the end of PTS interrupt service routine It changes the EPA channel to the compare mode and sets the time of the next compare to 1 5 bit times and enables the PTS At exactly 1 5 bit times from the beginning of the start bit the first PTS cycle samples the input data on RXD and shifts it into the DATA register Figure 5 27 If majority sampling is enabled an additional sample oc curs If the two samples differ a third sample occurs to determine which of the first two samples is correct The SAMPTIME register Figure 5 19 on page 5 38 controls the time between sam ples Majority sampling causes a substantial increase in PTS cycle execution time Table 5 4 on page 5 12 Conventional E Ven C y Interrupt 10 PTS Serviced Interrupts Interrupt N Interrupts LSB MSB eco un M Stan Stop 1 5 Bit Times N optional Parity Bit A3118 01 Figure 5 27 Asynchronous SIO Receive Timing The first PTS cycle must be started manually Initialize the RXD port and the SCK signal to the system required logic level before
330. ection External direction up down for timer 1 Timer 1 increments when T1DIR is high and decrements when it is low Also used in conjunction with T1CLK for quadrature counting mode On the 8XC196MC and MD T1DIR is multiplexed with P1 3 and ACH11 On the 8XC196MH T1DIR is multiplexed with 0 7 ACH7 and PMODE 3 TXD1 0 Transmit Serial Data 0 and 1 MH only In serial O modes 1 2 and 3 TXDO and 1 transmit serial port output data In mode 0 they are the serial clock outputs TXDO is multiplexed with P1 0 and TXD1 is multiplexed with P1 2 TXDO and 1 are not implemented on the 8XC196MC and MD Voc PWR Digital Supply Voltage Connect each Vec pin to the digital supply voltage Vop PWR Programming Voltage During programming the Vpp pin is typically at 12 5 V Vpp voltage Exceeding the maximum Vpp voltage specification can damage the device Vpp also causes the device to exit powerdown mode when it is driven low for at least 50 ns Use this method to exit powerdown only when using an external clock source because it enables the internal phase clocks but not the internal oscillator See Driving the Vpp Pin Low on page 14 6 On devices with no internal nonvolatile memory connect Vpp to Voc Veer PWR Reference Voltage for the A D Converter This pin also supplies operating voltage to both the analog portion of the A D converter and the logic used to read port 0 also port 1 in the 8XC196MC and 8XC196MD Vss GND Digital Circuit
331. ects a standard interrupt service routine When PTSCOUNT reaches zero hardware clears the corresponding PTSSEL bit The PTSSEL bit must be set manually to re enable the PTS channel 15 8 8XC196MC EXTINT COMP3 EPA3 7 0 COMP2 EPA2 COMP1 EPA1 COMPO AD OVRTM 15 8 8XC196MD EXTINT 5 4 4 7 0 2 2 COMP1 1 COMPO AD OVRTM 15 8 8XC196MH EXTINT WG SPI RIO TH TIO 7 0 COMP2 COMP1 EPA1 COMPO OVRTM Bit Number Function 15 Reserved for compatibility with future devices write zero to this bit 14 01 Setting a bit causes the corresponding interrupt to be handled by a PTS microcode routine The PTS interrupt vector locations are as follows Bit Mnemonic PTS Vector Bit Mnemonic PTS Vector EXTINT 205CH TIO MH 2050H PI MC 11 205AH COMP2 MC MD 204EH WG 205AH 204 5 MD 2058 EPA2 MD 204CH SPI 2058H COMP2 MH 204CH COMP4 MD 2056H 1 204 MH 2056H EPA1 2048H EPA4 MD 2054H COMPO 2046H RIO MH 2054H EPAO 2044H COMP3 MC MD 2052H AD 2042H TH MH 2052H 2040H EPA3 MC MD 2050H tt PTS service is not useful for multiplexed interrupts because the PTS cannot readily determine the source of these interrupts to these bits
332. ed Port Pin EPA EPA Signal Signal Description 8XC196MC 8XC196MD 8XC196MH gna s type P2 4 P2 4 P2 4 COMPO Output of the compare only channels 2 5 2 5 P2 5 1 2 6 2 6 P2 6 COMP2 P2 7 2 7 2 3 COMP3 7 2 COMP4 P7 3 5 Table 11 3 EPA Control and Status Registers Address Mnemonic Description _ 1F58H 1F58H 1F58H EPAx Compare Control COMP1_CON 1FSCH 1F5CH 1 5 these registers control the functions of the COMP2_CON 1F60H 1F60H 1F60H compare only channels COMP3_CON 1F64H 1F64H 1F4CH COMP4_CON 1F68H 5_ 1F6CH COMPO TIME 1F5AH 1F5AH 1F5AH EPAx Compare Time COME TIME 1 5 1F5SEH these registers contain the time at which an event COMP2_TIME TFBSH 1F62H 1F62H is to occur on the compare only channels COMP3_TIME 1F66H 1F66H 1F4EH COMP4_TIME 1F6AH COMP5_TIME 1F6EH _ 1F40H 1F40H 1F40H EPAx Capture Compare Control EPA1 CON 1 44 1 44 1F44H These registers control the functions of the EPA2 CON 1F48H 1F48H F capture compare channels EPA1 CON and EPA3 CON 1F4CH 1F4CH Tu CON require an extra byte because they EPA4 CON 1F50H s contain an additional bit for PWM remap mode EPAS_CON 1F54H These two registers must be addressed as words the others can be addressed as bytes EPAO TIME 1F42H 1F42H 1F42H
333. ed for compatibility with future devices write zeros to these bits C 8 intel REGISTERS AD TEST AD TEST Address 1FAEH E Reset State MC MD COH Reset State MH 88H The A D test AD TEST register specifies adjustments for DC offset errors 7 0 OFF1 OFFO Bit Bit i Number Mnemonic Function 7 5 Reserved for compatibility with future devices write zeros to these bits 4 OFF1 Offset This bit along with OFFO bit 2 allows you to set the zero offset point OFF1 OFFO 0 0 no adjustment 0 1 add 2 5 mV 1 0 subtract 2 5 mV 1 1 subtract 5 0 mV Reserved for compatibility with future devices write zero to this bit OFFO See bit 4 OFF1 1 0 Reserved for compatibility with future devices write zeros to these bits C 9 8XC196MC MD MH USER S MANUAL intel AD TIME AD TIME Address 1FAFH Reset State FFH The A D time AD_TIME register programs the sample window time and the conversion time for each bit This register programs the speed at which the A D can run not the speed at which it can convert correctly Consult the data sheet for recommended values Initialize the AD TIME register before initializing the AD COMMAND register Do not write to this register while a conversion is in progress the results are unpredictable 7 0 SAM2 1 CONV4 CONV3 CONV2 CONV1 CONVO
334. ed interrupts because the PTS cannot readily determine the source of these interrupts PTS Vector 205CH 205AH 205AH 2058H 2058H 2056H 2056H 2054H 2054H 2052H 2052H 2050H Bit Mnemonic TIO MH 2 MC MD COMP3 MH EPA2 MC MD 2 MH 1 1 EPAO AD OVRTM PTS Vector 2050H 204EH 204EH 204CH 204CH 204AH 2048H 2046H 2044H 2042H 2040H On the 8XC196MC device bits 10 12 are reserved These bits are undefined C 43 8XC196MC MD MH USER S MANUAL intel PWM_COUNT PWM_COUNT Address 1FB6H read only Reset State 00H The PWM count PWM_COUNT register provides the current value of the decremented period counter 7 0 PWM Count Value Bit Number Function 7 0 PWM Count Value This register contains the current value of the decremented period counter C 44 intel REGISTERS PWM PERIOD PWM PERIOD Address 1FB4H i Reset State 00H The PWM period PWM PERIOD register controls the period of the PWM outputs It contains a value that determines the number of state counts necessary for incrementing the PWM counter The value of PWM PERIOD is loaded into the PWM period count register whenever the count equals zero 7 0 PWM Period Bit Number Function 7 0 PWM Period This register controls the period of the PWM outputs The value of PWM_PERIOD is loaded into the PWM period count r
335. ed to zero and the end of PTS interrupt is requested Table 5 8 Command Data Table Example 1 Address Contents 300EH AD RESULT for ACH4 300CH Unused 0000H Dummy command 300AH AD RESULT for ACH5 3008H Unused AD COMMAND for ACH4 3006H AD RESULT for ACH6 3004H Unused AD COMMAND for ACH5 3002H AD RESULT for ACH7 3000H Unused AD COMMAND for ACH6 Table 5 9 A D Scan Mode PTSCB Example 1 Unused Unused PTSPTR 2 1FH 2 L PTSPTR1 H 30H 1 L 00H PTSCON CBH Mode 110 UPDT 1 PTSCOUNT 04H 5 36 intel STANDARD AND PTS INTERRUPTS 5 6 5 3 A D Scan Mode Example 2 Table 5 11 sets up a series of ten PTS cycles each of which reads a single A D channel and stores the result in a single location 3002H The bit PISCON 3 is cleared so that original con tents of PTSPTRI are restored after the cycle The command data table is shown in Table 5 10 Table 5 10 Command Data Table Example 2 Address Contents 3002H AD RESULT for ACHx 3000H Unused AD COMMAND for ACHx Table 5 11 A D Scan Mode PTSCB Example 2 Unused Unused PTSPTR2 1FH 2 L AAH PTSPTR1 PTSPTR1 L 00H PTSCON C3H Mode 110 UPDT 0 PTSCOUNT Software starts a conversion on channel x When the conversion is finished and
336. ediately or are synchronized with an event The synchronization bit is not buffered so changes to it take effect immediately You should initialize the synchroni zation to zero changes take effect immediately to ensure that the pins are in the desired states when the counter starts 9 3 5 Operating Modes The waveform generator can operate in a center aligned or an edge aligned mode In the center aligned modes the counter counts both up and down in the edge aligned modes it counts up only The center aligned modes generate PWM outputs that are more efficient for driving 3 phase AC induction motors while the edge aligned modes generate conventional PWM outputs Cen ter aligned outputs have less harmonic content than edge aligned outputs with effectively twice the carrier period The initial condition of the waveform generator is the same for all operating modes Following a system power up or reset the counter is stopped outputs are deasserted and all registers are cleared Values written to the registers take effect one half state time later The main differences between center aligned and edge aligned modes are the counter s initial value the count direction and the conditions that cause a change in the state ofthe outputs Table 9 3 summarizes the operation of the center aligned and edge aligned modes 8XC196MC MD MH USER S MANUAL Table 9 3 Operation in Center aligned and Edge aligned Modes Step Center aligned Mode
337. efore a new conversion starts If you read AD RESULT before the conversion is complete the result is not guaranteed to be accurate The conversion result is the ratio of the input voltage to the reference voltage Vin ANGND Vin ANGND RESULT 8 bit 255 x RESULT 10 bit 1023 x You can also read the interrupt pending register see Table 12 2 on page 12 2 to determine the Vee ANGND ANGND status of the A D interrupt AD RESULT Read Address 1FAAH Reset State MC MD FFCOH Reset State MH 7FCOH The A D result AD RESULT register consists of two bytes The high byte contains the eight most significant bits from the A D converter The low byte contains the two least significant bits from a ten bit A D conversion indicates the A D channel number that was used for the conversion and indicates whether a conversion is currently in progress 15 8 ADRLT9 ADRLT8 ADRLT7 ADRLT6 ADRLT5 ADRLT4 ADRLT3 ADRLT2 7 0 ADRLT1 ADRLTO STATUS 2 1 ie Function 15 6 ADRLT9 0 A D Result These bits contain the A D conversion result Reserved This bit is undefined STATUS A D Status Indicates the status of the A D converter Up to 8 state times are required to set this bit following a start command When testing this bit wait at least the 8 state times 0 A D is idle 1 A D conversion is
338. eg isters are identical with the exception of bit 2 For EPA channels 0 2 and 4 setting this bit enables an EPA event to cause a waveform generator reload For EPA channels 1 3 and 5 setting this bit enables an EPA event to cause an A D conversion To program a compare event always write to EPAx CON Figure 11 10 first to configure the EPA capture compare channel and then load the event time into EPAx TIME To program a capture event you need only write to EPAx CON Table 11 6 shows the effects of various combinations of EPAx CON bit settings for channels 1 3 or 5 Table 11 6 Example EPA Control Register Settings for Channels 1 3 or 5 Capture Mode MODE RE WGR ON RT 7 6 5 4 3 2 1 0 X 0 0 0 0 None X 0 0 1 X X X Capture on falling edges X 0 1 0 X X X Capture on rising edges X 0 1 1 X X X Capture on both edges X 0 xX 1 X 1 X Capture on falling edge and reset opposite timer X 0 1 X X 1 X Capture on rising edge and reset opposite timer X 0 0 1 1 X X Start A D conversion EPA1 3 5 or reload waveform generator 2 4 on falling edge X 0 1 0 1 X X Start A D conversion EPA1 3 5 or reload waveform generator 2 4 on rising edge Compare Mode WGR TB CE MODE RE un ROT ON RT Operation 7 6 5 4 3 2 1 0 X 1 0 0 X 0 None X 1
339. egister whenever the count equals zero C 45 8XC196MC MD MH USER S MANUAL intel PWMx CONTROL PWMx CONTROL Address 1FBOH 1FB2H 0 1 Reset State 00H The PWM control PWMx CONTROL register determines the duty cycle of the PWM x channel A zero loaded into this register causes the PWM to output a low continuously 0 duty cycle An FFH in this register causes the PWM to have its maximum duty cycle 99 696 duty cycle 7 0 PWM Duty Cycle Bit Number Function 7 0 PWM Duty Cycle This register controls the PWM duty cycle A zero loaded into this register causes the PWM to output a low continuously 096 duty cycle An FFH in this register causes the PWM to have its maximum duty cycle 99 696 duty cycle C 46 intel REGISTERS SBUFx RX SBUFx RX Address 1F80H 1F88H X 0 1 8XC196MH Reset State 00H The serial port receive buffer x SBUFx register contains data received from serial port x The serial port receiver is buffered and can begin receiving a second data byte before the first byte is read Data is held in the receive shift register until the last data bit is received then the data byte is loaded into SBUFx RX If data in the shift register is loaded into SBUFx RX before the previous byte is read the overflow error bit is set SPx STATUS 2 The data in SBUFx RX will always be the last byte received never a combination of the last two bytes
340. emain in mode 2 and are not interrupted 8XC196MC MD MH USER S MANUAL intel 7 44 PROGRAMMING THE SERIAL PORT To use the SIO port you must configure the port pins to serve as special function signals and set up the SIO channels 7 4 1 Configuring the Serial Port Pins Before you can use the serial port you must configure the associated port pins to serve as special function signals Table 7 1 on page 7 2 lists the pins associated with the serial port Table 7 2 on page 7 2 lists the port configuration registers and Chapter 6 I O Ports explains how to con figure the pins 7 4 2 Programming the Control Register The SPx CON register Figure 7 6 selects the communication mode and enables or disables the receiver parity checking and nine bit data transmissions Selecting a new mode resets the serial I O port and aborts any transmission or reception in progress on the channel SPx CON Address 1F83H 1 8 x 0 1 8 196 Reset State 00H The serial port control SPx_CON register selects the communications mode and enables or disables the receiver parity checking and nine bit data transmission 7 0 8XC196MH M2 DIR PAR TB8 REN PEN M1 MO Bit Bit i Number Mnemonic Function M2 See description for bits 0 and 1 DIR Synchronous Clock Direction This bit determines the direction of the clock during synchronous mode 0 output 1 input 5 PAR Parity Selection Bit
341. emented opcode and software trap are not prioritized they vector directly to the interrupt service routine when executed intel program memory protected instruction PSW PTS PTSCB PTS control block PTS cycle PTS interrupt PTS mode PTS routine PTS transfer PTS vector GLOSSARY A partition of memory where instructions can be stored for fetching and execution An instruction that prevents an interrupt from being acknowledged until after the next instruction executes The protected instructions are DI EI DPTS EPTS POPA POPF PUSHA and PUSHF Processor status word The high byte of the PSW is the status byte which contains one bit that globally enables or disables servicing of all maskable interrupts one bit that enables or disables the PTS and six Boolean flags that reflect the state of the current program The low byte of the PSW is the INT_MASK register A push or pop instruction saves or restores both bytes PSW INT MASK Peripheral transaction server The microcoded hardware interrupt processor See PTS control block A block of data required for each PTS interrupt The microcode executes the proper PTS routine based on the contents of the PTS control block The microcoded response to a single PTS interrupt request Any maskable interrupt that is assigned to the PTS for interrupt processing microcoded response that enables the PTS to complete a specific task quickly These task
342. emonic Description Reset High to First PALE Low PALE Pulse Width gt lt E Address Setup Time E x Address Hold Time PROG Low to Word Dump Valid Word Dump Data Hold Data Setup Time Data Hold Time PROG Pulse Width 5 o 9 X A x lt PROG High to Next PALE Low A A a a aAA a a PALE High to PROG Low 16 24 intel PROGRAMMING THE NONVOLATILE MEMORY Table 16 10 Timing Mnemonics Continued Mnemonic Description PROG High to Next PROG Low LETS PROG High to AINC Low AINC Pulse Width PVER Hold After AINC Low AINC Low to PROG Low PROG High to PVER Valid 16 9 AUTO PROGRAMMING MODE The auto programming mode is a low cost programming alternative Using this programming mode the device programs itself with data from an external EPROM external locations 4000H and above see Table 16 1 on page 16 3 A bank switching mechanism provided by port pins see Figure 16 12 supports auto programming of devices with more than 16 Kbytes of internal memory 16 9 1 Auto Programming Circuit and Memory Map Figure 16 12 shows the recommended circuit for auto programming mode Table 16 11 shows the 8XC196MC MD memory map and Table 16 11 shows the 8 196 auto programming mem ory
343. eneration The waveform generator s maximum frequency is 15 625 kHz for center aligned modes and 31 250 kHz for edge aligned modes There are three independent phases each of which has two programmable complementary out puts A programmable dead time generator prevents the complementary outputs from being ac tive at the same time The carrier period dead time and operating mode are the same for all three phases the duty cycle is independently programmable 8XC196MC MD MH USER S MANUAL intel Timebase Generator WG RELOAD 15 Buffer 16 Update WG_RELOAD WG_RELOAD 4 WG_COUNTER WG Interrupt Comparator WG_COUNTER WG_RELOAD Phase Driver One of Three Channels Dead time PEUT Phase amp j Circuitry 16 16 wa Control 16 16 kissed WG OUTPUT 4 Update OUTPUT Output Control 8 and Dead Time Output Disable 8 Protection EXTINT Interrupt Vector WG_PROTECT Circuitry 8 WG_CONTROL Mode Control Signals EXTINT Input Pin A2637 01 Figure 9 1 Waveform Generator Block Diagram intel WAVEFORM GENERATOR 9 2 WAVEFORM GENERATOR SIGNALS AND REGISTERS Table 9 1 describes the waveform generator s signals and Table 9 2 briefly describes the control and status registers Table 9 1 Waveform Generator Signals Port Waveform Pi
344. ented on the 8XC196MH EXTINT External Interrupt This programmable interrupt is controlled by the WG_PROTECT register This register controls whether the interrupt is edge triggered or sampled and whether a rising edge high level or falling edge low level activates the interrupt In powerdown mode asserting the EXTINT signal for at least 50 ns causes the device to resume normal operation The interrupt need not be enabled If the EXTINT interrupt is enabled the CPU executes the interrupt service routine Otherwise the CPU executes the instruction that immediately follows the command that invoked the power saving mode In idle mode asserting any enabled interrupt causes the device to resume normal operation 14 1 8XC196MC MD MH USER S MANUAL intel Table 14 1 Operating Mode Control Signals Continued Signal Port Pin Name Type Description P5 4 ONCE On circuit Emulation Holding ONCE low during the rising edge of RESET places the device into on circuit emulation ONCE mode This mode puts all pins except XTAL1 and XTAL2 into a high impedance state thereby isolating the device from other components in the system The value of ONCE is latched when the RESET pin goes inactive While the device is in ONCE mode you can debug the system using a clip on emulator To exit ONCE mode reset the device by pulling the RESET signal low To prevent inadvertent entry into ONCE mode either conf
345. ep 1 set the corresponding Px_REG bits Table 6 8 lists the control register values for each possible configuration For special function outputs the Px_REG value is irrelevant don t care because the associated peripheral controls the pin in special function mode However you must still write to Px_REG to initialize the pin For a bidirectional pin to function as an input either special function or port pin you must set Px_REG intel Table 6 8 Control Register Values for Each Configuration PORTS Desired Pin Configuration Configuration Register Settings Standard I O Signal DIR REG Complementary output driving 0 0 0 0 Complementary output driving 1 0 0 1 Open drain output strongly driving 0 1 0 0 Open drain output high impedance 1 0 1 Input 1 0 1 Special function signal DIR REG Complementary output output value controlled by peripheral 0 1 X Open drain output output value controlled by peripheral 1 1 X Input 1 1 1 t During reset and until the first write to MODE the pins are weakly held high 6 3 8 Bidirectional Port Pin Configuration Example Assume that you wish to configure the pins of a bidirectional port as shown in Table 6 9 Table 6 9 Port Configuration Example Port Pin s Configuration Data Px 0 Px 1 high impedance input high impedance Px 2 Px 3 open drain ou
346. equential instruction If the negative flag is set this instruction adds 11011110 disp to the program counter the offset between the end of this instruction and the target label NOTE The displacement disp is sign effecting the jump The offset must be in the extended to 16 bits range of 128 to 127 if N 2 1 then PC lt PC 8 bit disp PSW Flag Settings Z N C V VT ST JNC JUMP IF CARRY FLAG IS CLEAR Tests the carry flag If the flag is set control passes JNC cadd the next sequential instruction If the carry flag is clear this instruction adds to the 11010011 disp program counter the offset between the end of this instruction and the target label NOTE The displacement disp is sign effecting the jump The offset must be in the extended to 16 bits range of 128 to 127 if C 2 0 then PC lt PC 8 bit disp PSW Flag Settings Z N C V VT ST JNE JUMP IF NOT EQUAL Tests the zero flag If the flag is set control passes to the next JNE cadd sequential instruction If the zero flag is clear this instruction adds to the program counter 11010111 disp the offset between the end of this instruction and the target label effecting the jump The NOTE The displacement disp is sign offset must be in the range of 128 to 127 extended to 16 bits if Z 0 then PC lt PC 8 bit disp PSW Flag S
347. er controls the configuration of the waveform generator and PWM module pins Both the waveform generator and the PWM module share pins with port 6 Having these control bits in a single register enables you to configure all port 6 pins with a single write to OUTPUT 15 8 OP1 OPO SYNC PE7 PE6 PH3 2 PH2 2 PH1 2 7 0 P7 P6 PH3 1 PH3 0 PH2 1 PH2 0 PH1 1 PH1 0 Bit Bit Number Mnemonic 10 2 Phase 3 Function Selects either the port function or the waveform generator output function for pins P6 4 WG3 and P6 5 WG3 0 P6 4 P6 5 1 WG3 WG3 9 PH2 2 Phase 2 Function Selects either the port function or the waveform generator output function for pins P6 2 WG2 and P6 3 WG2 0 P6 2 P6 3 1 WG2 WG2 8 PH1 2 Phase 1 Function Selects either the port function or the waveform generator output function for pins P6 0 WG1 and P6 1 WG1 0 P6 0 P6 1 1 WG12 WG1 7 P7 P6 7 PWM1 Value Write the desired P6 7 PWM1 value to this bit 6 P6 P6 6 PWMO Value Write the desired P6 6 PWMO value to this bit 5 4 PH3 1 0 P6 4 WG3 P6 5 WG3 Value Write the desired output values to these bits See Table C 11 on page C 65 3 2 PH2 1 0 P6 2 WG2 P6 3 WG2 Values Write the desired output values to these bits See Table C 11 on page C 65 1 0 PH1 1 0 P6 0 WG1 P6 1 WG1 Values Write the desired output values to these bits See Table C 11 on page C 65 C 64
348. erate a WG interrupt request once at the end of each period when the counter is reloaded with 1 The protection circuitry controls the EXTINT interrupt Two bits in the protection register control the type of external event that will generate an interrupt request a falling or rising edge or a low or high level See Controlling the Protection Circuitry and EXTINT Interrupt Generation on page 9 15 The edge detection circuitry requires a signal to remain asserted for at least 2 state times to be considered a valid edge The sample circuitry requires a signal to remain asserted for at least 24 state times to be considered a valid level It samples the input level 3 times during this 24 state period and recognizes the signal as valid only if it is asserted for each sample Level sampling is useful for environments in which noise spikes might cause unintended interrupts if edge detection were used 8XC196MC MD MH USER S MANUAL intel To enable the interrupts set the corresponding mask bits in the mask register see Table 9 2 on page 9 3 and execute the EI instruction to enable interrupt servicing You can read the interrupt pending register to determine whether there are any pending interrupts Refer to Chapter 5 Stan dard and PTS Interrupts for details 9 7 DESIGN CONSIDERATIONS This section describes design and programming considerations for using the waveform generator 9 7 4 Dead Time and Duty Cycle Short dead times hav
349. erial Port Status 1F89 0000 0000 Reset value is FFH when pin is not driven Reset value is 80H if the EA is high if EAs is low ttt The CCRs are loaded with the contents of the chip configuration bytes CCBs after a device reset unless the device is entering programming modes see Entering Programming Modes on page 16 13 in which case the programming chip configuration bytes PCCBs are used The CCBs reside in internal nonvolatile memory at addresses 2018H CCBO and 201AH CCB1 C4 intel REGISTERS Table C 2 Register Name Address and Reset Status Continued Binary Reset Value 4 RegisterName IM T cos T1CONTROL Timer 1 Control 1F78 0000 0000 T2CONTROL Timer 2 Control 1F7C 0000 0000 T1RELOAD Timer 1 Reload 1F72 XXXX XXXX XXXX TIMER1 Timer 1 Value 1F7A 0000 0000 0000 0000 2 Timer 2 Value 1F7E 0000 0000 0000 0000 USFR MD 0000 0010 USFR MH UPROM Special Function 1FF6 WATCHDOG Watchdog Timer 000A XXXX XXXX WG_COMP1 Waveform Gen Phase Comp 1 1FC2 0000 0000 0000 0000 WG_COMP2 Waveform Gen Phase Comp 2 1FC4 0000 0000 0000 0000 WG_COMP3 Waveform Gen Phase Comp 3 1FC6 0000 0000 0000 0000 WG_CONTROL MC MD 0000 0000 1100 0000 WG_CONTROL MH Waveform Gen Control 1FCC 100070000 0006 0000 WG_COUNTER Waveform Gen Count 1 XXXX XXXX XXXX WG_OUTPUT Wavef
350. eripheral interrupt PI Setting INT_MASK1 5 enables PI Setting Pl MASK 5 enables WG SPO MH Serial Port 0 Error When set this bit indicates a pending serial port 0 error interrupt The serial port 0 and 1 error interrupts are associated with the serial port interrupt SPI Setting INT_MASK1 4 enables SPI Setting PILMASK 4 enables SPO Figure 5 12 Peripheral Interrupt Pending PEND Register 5 23 8XC196MC MD MH USER S MANUAL intel PI PEND Continued Address 1FBEH Reset State AAH When hardware detects a pending peripheral or timer interrupt it sets the corresponding bit in the interrupt pending INT PEND or INT PEND1 registers and the peripheral interrupt pending PEND register When the vector is taken the hardware clears the INT PEND INT PEND1 pending bit Reading this register clears all the PEND bits Software can generate an interrupt by setting a PEND bit 7 0 8XC196MC WG OVRTM2 OVRTM1 7 0 8XC196MD 5 WG OVRTM2 OVRTM1 7 0 8XC196MH SP1 SPO OVRTM2 OVRTM1 Bit Function Number Mnemonic 2 OVRTM2 Timer 2 Overflow Underflow When set this bit indicates a pending timer 2 overflow underflow interrupt The timer 2 and timer 1 overflow underflow interrupts are associated with the overflow underflow timer interrupt OVRTM Setting INT_MASK 0 enables O
351. ernal interrupt pin EXTINT low while the device is in idle mode 14 4 POWERDOWN MODE Powerdown mode places the device into a very low power state by disabling the internal oscilla tor and clock generators Internal logic holds the CPU and peripheral clocks at logic zero which causes the CPU to stop executing instructions the system bus control signals to become inactive the CLKOUT signal to become high and the peripherals to turn off Power consumption drops into the microwatt range refer to the datasheet for exact specifications is reduced to device leakage Tables in Appendix B list the values of the pins during powerdown mode see Table B 8 on page B 23 for the 8 196 and 8XC196MD or Table B 9 on page B 25 for the 8XC196MH If is maintained above the minimum specification the special function regis ters SFRs and register RAM retain their data 14 4 1 Enabling and Disabling Powerdown Mode The PD bit in the chip configuration register 0 CCRO 0 either enables or disables powerdown mode Because CCRO cannot be accessed by code the PD bit value is defined in chip configura tion byte 0 CCBO 0 Setting the PD bit enables powerdown mode and clearing it disables pow erdown CCRO is loaded from CCBO when the device returns from reset Refer to Operating Environment on page 16 17 for descriptions of the methods for programming the CCBs 14 5 8XC196MC MD MH USER S MANUAL intel 14 4 2 Entering Powerdown
352. ero offset error Specify the zero offset adjustment by writing the appropriate value to TEST This offset voltage is added to the resistor ladder and applies to all input channels Understand ing A D Conversion Errors on page 12 13 describes zero offset and other errors inherent in A D conversions AD TEST Address 1FAEH Reset State MC MD COH Reset State MH 88H The A D test AD TEST register specifies adjustments for DC offset errors 7 0 1 OFFO Bit Bit Number Mnemonic Function 7 5 Reserved for compatibility with future devices write zeros to these bits 4 OFF1 Offset This bit along with OFFO bit 2 allows you to set the zero offset point OFF1 OFFO 0 0 no adjustment 0 1 add 2 5 mV 1 0 subtract 2 5 mV 1 1 subtract 5 0 mV Reserved for compatibility with future devices write zero to this bit OFFO See bit 4 OFF1 1 0 Reserved for compatibility with future devices write zeros to these bits Figure 12 2 A D Test AD TEST Register 12 4 2 Programming the A D Result Register for Threshold Detection Only To use the threshold detection modes you must first write a value to the high byte of AD RESULT to set the desired reference threshold voltage 12 5 8XC196MC MD MH USER S MANUAL intel AD RESULT Write Address 1FAAH Reset State MC MD FFCOH Reset State MH 7FCOH The high byte of t
353. error will be less than 0 4 LSB in 10 bit conversion mode The use of in conjunction with Rsource forms a low pass filter that reduces noise input to the A D converter High Rgoyrcg resistance can also cause errors due to the input leakage I 11 1 is typically much lower than its specified maximum consult the datasheet for specifications The combined effect of I leakage and high Rgougcp resistance is calculated using the following formula Rgource X lL X 1024 error LSBs V REF where Rsource is the input source resistance in ohms li is the input leakage in amperes Veer is the reference voltage in volts External circuits with R ourcg resistance of 1 kilo ohm or lower and Vag equal to 5 0 volts will have a resultant error due to source impedance of 0 6 LSB or less 12 11 8XC196MC MD MH USER S MANUAL intel 12 6 1 2 Suggested A D Input Circuit The suggested A D input circuit shown in Figure 12 8 provides limited protection against over voltage conditions on the analog input Should the input voltage be driven significantly below ANGND or above diode D2 or D1 will forward bias at about 0 8 volts The device s input protection begins to turn on at approximately 0 5 volts beyond ANGND Vgg 2700 re sistor limits the current input to the analog input pin to a safe value less than 1 mA NOTE Driving any analog input more than 0 5 volts beyond ANGND or V begins to activate the i
354. ersus input voltage of an actual A D converter An actual characteristic may vary with temperature supply voltage and frequency conditions Analog to digital converter Arithmetic logic unit The part of the RALU that processes arithmetic and logical operations The act of making a signal active enabled The polarity high or low is defined by the signal name Active low signals are designated by a pound symbol suffix active high signals have no suffix To assert RD is to drive it low to assert ALE is to drive it high A decrease in amplitude voltage decay A binary digit A single bit operand that can take on the Boolean values true and false The property of a multiplexer which guarantees that a previously selected channel is deselected before a new channel is selected That is break before make ensures that the A D converter will not short inputs together Any 8 bit unit of data An unsigned 8 bit variable with values from 0 through 28 1 Glossary 1 8XC196MC MD MH USER S MANUAL CCBs CCRs channel to channel matching error characteristic clear code code center code transition code width crosstalk DC input leakage Glossary 2 intel Chip configuration bytes The chip configuration registers CCRs are loaded with the contents of the CCBs after a device reset unless the device is entering programming modes in which case the PCCBs are used Chip configur
355. es 14 3 IDLE MODE In idle mode the device s power consumption decreases to approximately 4096 of normal con sumption Internal logic holds the CPU clocks at logic zero causing the CPU to stop executing instructions Neither the peripheral clocks nor CLKOUT are affected so the special function reg isters SFRs and register RAM retain their data and the peripherals and interrupt system remain active Tables in Appendix B list the values of the pins during idle mode see Table B 8 on page B 23 for the 8XC196MC and 8XC196MD or Table B 9 on page B 25 for the 8 196 14 4 intel SPECIAL OPERATING MODES The device enters idle mode after executing the IDLPD 1 instruction Any enabled interrupt source either internal or external or a hardware reset can cause the device to exit idle mode When an interrupt occurs the CPU clocks restart and the CPU executes the corresponding inter rupt service or PTS routine When the routine is complete the CPU fetches and then executes the instruction that follows the IDLPD 1 instruction NOTE If enabled the watchdog timer continues to run in idle mode The device must be awakened before the counter overflows otherwise the timer will reset the device The watchdog timer interval is always 64K state times in the 8XC196MC MD but a longer interval can be selected in the 8XC196MH see Enabling the Watchdog Timer on page 13 12 To prevent an accidental return to full power hold the ext
356. es 16 1 16 33 algorithms 16 20 16 21 16 23 16 28 auto 16 2 entering 16 13 16 14 exiting 16 14 hardware requirements 16 13 pin functions 16 11 16 13 selecting 16 13 serial port 16 2 slave 16 1 Programming pulse width register 16 8 C 39 Programming voltages 13 1 14 2 16 13 B 21 calculating 16 15 PSW 2 4 3 11 C 40 flags and instructions A 5 PTS 2 4 2 6 2 11 5 1 A D scan mode 5 32 5 37 and A D converter 5 33 asynchronous serial I O receive mode 5 55 5 58 asynchronous serial I O transmit mode 5 50 5 54 block transfer mode 5 30 control block See PTSCB cycle execution time 5 12 cycle defined 5 30 initializing PTS control blocks 5 24 intel instructions A 51 A 57 interrupt latency 5 11 interrupt processing flow 5 2 routine defined 5 1 serial I O modes 5 37 5 58 single transfer mode 5 27 synchronous serial I O receive mode 5 47 5 50 synchronous serial I O transmit mode 5 43 5 46 vectors memory locations 4 3 See also PWM PTS select register 5 14 C 42 PTS service register 5 26 C 43 PTSCB 5 4 5 9 A D scan mode 5 33 block transfer mode 5 31 memory locations 4 3 PTSCON register 5 27 PTSCOUNT register 5 25 single transfer mode 5 28 PTSCBI serial I O mode 5 38 PTSCB2 serial I O mode 5 41 Pulse width modulator See PWM PUSH instruction A 3 A 29 A 45 A 49 A 54 PUSHA instruction A 2 A 30 A 46 A 49 A 54 PUSHF instruction A 2 A 30 A 46 A 49 A 54 PVER 1
357. es of PTS cycles The PTSCB in Table 5 6 sets up three PTS cycles that will transfer five bytes from memory loca tions 20 24H to 6000 6004 cycle 1 6005 6009 cycle 2 and 600A 600EH cycle 3 The source and destination are incremented after each byte transfer but the original source address is reloaded into PTSSRC at the end of each block transfer cycle In this routine the PTS always gets the first byte from location 20H Table 5 6 Block Transfer Mode PTSCB Unused PTSBLOCK 05H PTSDST H 60H PTSDST L 00H PTSSRC H 00H PTSSRC L 20H PTSCON 17H Mode 000 DI SI DU BW 1 SU 0 PTSCOUNT 03H 5 30 intel STANDARD AND PTS INTERRUPTS PTS Block Transfer Mode Control Block In block transfer mode the PTS control block contains a block size PTSBLOCK a source and destination address PTSSRC and PTSDST a control register PTSCON and a transfer count PTSCOUNT 7 0 Unused 0 0 0 0 0 0 0 0 7 0 PTSBLOCK PTS Block Size 15 8 PTSDST H PTS Destination Address high byte 7 0 PTSDST L PTS Destination Address low byte 15 8 PTSSRC H PTS Source Address high byte 7 0 PTSSRC L PTS Source Address low byte 7 0 PTSCON M2 M1 MO BW SU DU SI DI 7 0 PTSCOUNT Consecutive Block Transfers Register Location Function PTSBLOCK PTSCB 6 PTS Block Si
358. es the JQ JR KQ KR 272113 8XC196KT Quick Reference 272269 8XC196MC Quick Reference 272114 8XC196NP Quick Reference 272466 8XC196NT Quick Reference 272270 1 4 ELECTRONIC SUPPORT SYSTEMS Intel s FaxBack service and application BBS provide up to date technical information We also maintain several forums on CompuServe and offer a variety of information on the World Wide Web These systems are available 24 hours a day 7 days a week providing technical information whenever you need it 1 4 4 FaxBack Service FaxBack is an on demand publishing system that sends documents to your fax machine You can get product announcements change notifications product literature device characteristics de sign recommendations and quality and reliability information from FaxBack 24 hours a day 7 days a week 1 800 628 2283 U S and Canada 916 356 3105 U S Canada Japan Asia Pacific 44 0 1793 496646 Europe Think of the FaxBack service as a library of technical documents that you can access with your phone Just dial the telephone number and respond to the system prompts After you select a doc ument the system sends a copy to your fax machine Each document is assigned an order number and is listed in a subject catalog The first time you use FaxBack you should order the appropriate subject catalogs to get a complete listing of doc ument order numbers Catalogs are updated twice monthly In addition daily update catalogs list the title
359. es to MODE The default values of the control reg isters after reset configure the pins as high impedance inputs with weak pull ups To ensure that the ports are initialized correctly and that the weak pull ups are turned off follow this suggested initialization sequence 1 Write to Px_DIR to establish the individual pins as either inputs or outputs Outputs will drive the data that you specify in step 3 For a complementary output clear its Px_DIR bit For a high impedance input or an open drain output set its Px_DIR bit Open drain outputs require external pull ups Write to Px_MODE to select either I O or special function mode Writing to Px_MODE regardless of the value written turns off the weak pull ups Even if the entire port is to be used as I O its default configuration after reset you must write to Pc MODE to ensure that the weak pull ups are turned off For a standard I O pin clear its Px MODE bit In this mode the pin is driven as defined in steps 1 and 3 For a special function signal set its Px_MODE bit In this mode the associated peripheral controls the pin Write to Px_REG For output pins defined in step 1 write the data that is to be driven by the pins to the corresponding Px_REG bits For special function outputs the value is immaterial because the peripheral controls the pin However you must still write to Px_REG to initialize the pin For input pins defined in st
360. escriptions Continued Name Type Description P7 7 0 Port 7 MD only This is a standard 8 bit bidirectional port with Schmitt trigger inputs Port 7 is multiplexed as follows P7 0 EPA4 P7 1 EPA5 P7 2 COMP4 P7 3 COMP5 and P7 7 FREQOUT P7 6 4 are not multiplexed Port 7 is not implemented on the 8XC196MC and 8XC196MH PACT Programming Active During auto programming or ROM dump a low signal indicates that programming or dumping is in progress while a high signal indicates that the operation is complete PACT is multiplexed with P2 5 and COMP1 PALE Programming ALE During slave programming a falling edge causes the device to read command and address from the PBUS PALE is multiplexed with P2 1 and EPA1 MC MD and P2 1 SCLKO and BCLKO MH PBUS 15 0 VO Address Command Data Bus During slave programming ports 3 and 4 serve as a bidirectional port with open drain outputs to pass commands addresses and data to or from the device Slave programming requires external pull up resistors During auto programming and ROM dump ports 3 and 4 serve as a regular system bus to access external memory P4 6 and P4 7 are left unconnected P1 1 and P1 2 serve as the upper address lines Slave programming PBUS 7 0 are multiplexed with AD7 0 and P3 7 0 PBUS 15 8 are multiplexed with AD15 8 and P4 7 0 Auto programming On the 8XC196MC MC and MH PBUS 7 0 are multiplexed with AD7 0 and P3 7 0 On th
361. ess Title Order Number 8XC196KR KQ JR JQ Commercial Express CHMOS Microcontroller 270912 8XC196KT Commercial CHMOS Microcontroller 272266 87C196KT 87C196KS 20 MHz Advanced 16 Bit CHMOS Microcontroller 272513 8XC196MC Industrial Motor Control Microcontroller 272323 87C196MD Industrial Motor Control CHMOS Microcontroller 270946 8XC196NP Commercial CHMOS 16 Bit Microcontroller 272459 8XC196NT CHMOS Microcontroller with 1 Mbyte Linear Address Space 272267 80C196NU Commercial CHMOS 16 Bit Microcontroller 272644 Included in Embedded Microcontrollers handbook order number 270646 Table 1 4 MCS 96 Microcontroller Datasheets Automotive Title and Description Order Number 87C196CA 87C196CB 20 MHz Advanced 16 Bit CHMOS Microcontroller with 272405 Integrated CAN 2 0 87C196JT 20 MHz Advanced 16 Bit CHMOS Microcontroller 272529 87C196JV 20 MHz Advanced 16 Bit CHMOS Microcontroller 272580 87 196 87C196JV AJT 87C196JR JQ Advanced 16 Bit CHMOS 270827 Microcontroller 87C196KT 87C196KS Advanced 16 Bit CHMOS Microcontroller 270999 87C196KT KS 20 MHz Advanced 16 Bit CHMOS Microcontroller 272513 Included in Automotive Products handbook order number 231792 1 7 8XC196MC MD MH USER S MANUAL intel Table 1 5 MCS 96 Microcontroller Quick References Title and Description Order Number 8XC196KR Quick Reference includ
362. ess the next word location ke RESET ADDR2 PBUS DATA2 Ports 3 4 E Px PALE ja iL PL PROG t Pulse 1 ance PHIL Additional program pulses and verifications Measure from falling edge of last PROG pulse in sequence PVER A0121 02 Figure 16 9 Program Word Waveform 16 22 intel PROGRAMMING THE NONVOLATILE MEMORY From Address Command Decoder Lock Bits Enabled Get Data from OPTROM Write Data to PBUS Yes Write OFFFFH to PBUS To Address Command Decoder Increment Address by 2 A0189 03 Figure 16 10 Dump Word Routine 16 23 8XC196MC MD MH USER S MANUAL intel Figure 16 11 shows the timings of the dump word command PROG governs when the device drives the bus The timings before the dump word command are the same as those shown in Fig ure 16 9 In the dump word mode the AINC pin can remain active and toggling The PROG pin automatically increments the address RESET 4 ADDR2 PBUS ADDR COMMAND Ports 3 4 PALE PROG AINC 0122 02 Figure 16 11 Dump Word Waveform 16 8 5 Timing Mnemonics Table 16 10 defines the timing mnemonics used in the program word and dump word waveforms The datasheets include timing specifications for these signals Table 16 10 Timing Mnemonics Mn
363. estination integer operand 101111 baop wreg low byte DEST lt SRC if DEST 15 1 then high word DEST lt else high word DEST lt 0 end_if PSW Flag Settings LDBZE LOAD BYTE ZERO EXTENDED Zero DEST SRC extends the value of the source byte operand LDBZE wreg baop and loads it into the destination word operand 101011 aa wreg low byte DEST lt SRC high byte DEST lt 0 PSW Flag Settings LJMP LONG JUMP Adds to the program counter the offset between the end of this instruction and the target label effecting the jump The offset must be in the range of 32 768 to 11100111 disp low disp high 32 767 PC lt 16 bit disp PSW Flag Settings 24 intel INSTRUCTION SET REFERENCE Table A 6 Instruction Set Continued signed arithmetic and stores the 32 bit result into the destination long integer operand The sticky bit flag is undefined after the instruction is executed DEST lt DEST x SRC PSW Flag Settings 2 ST Mnemonic Operation Instruction Format MUL MULTIPLY INTEGERS Multiplies the source DEST SRC 2 operands and destination integer operands using MUL Ireg waop 11111110
364. et Continued Mnemonic Operation Instruction Format MULU MULTIPLY WORDS UNSIGNED Multiplies DEST SRC 2 operands the source and destination word operands MULU waop using unsigned arithmetic and stores the 32 bit result into the destination double word 011011 waop Ireg operand The sticky bit flag is undefined after the instruction is executed DEST lt DEST x SRC PSW Flag Settings MULU MULTIPLY WORDS UNSIGNED Multiplies DEST SRC1 SRC2 3 operands the two source word operands using MULU wreg waop unsigned arithmetic and stores the 32 bit result into the destination double word 010011 waop wreg Ireg operand The sticky bit flag is undefined after the instruction is executed DEST lt SRC1 x SRC2 PSW Flag Settings Z N C V VT ST MULUB MULTIPLY BYTES UNSIGNED Multiplies DEST SRC 2 operands the source and destination operands using MULUB wreg baop unsigned arithmetic and stores the word result into the destination operand The sticky 011111 wreg bit flag is undefined after the instruction is executed DEST lt DEST x SRC PSW Flag Settings Z N C V VT ST MULUB MULTIPLY BYTES UNSIGNED Multiplies DEST SRC1 SRC2 3 operands the two source byte operands using MULUB wreg breg baop
365. et INT_PEND x Bit Reset PTSSRV x Reset INT_PEND x Execute 1 PTS Cycle Bit Bit Microcoded Decrement PTSCOUNT Pe ce on Stack LUMP to Return ISR Execute Interrupt Service Routine Clear PTSSEL x Bit POP PG from Stack Set PTSSRV x Bit Return Return 0320 02 Figure 5 1 Flow Diagram for PTS and Standard Interrupts intel STANDARD AND PTS INTERRUPTS Figure 5 1 illustrates the interrupt processing flow In this flow diagram INT_MASK repre sents both the INT MASK and INT 5 registers and INT represents both the INT PEND and INT PENDI registers 5 2 INTERRUPT SIGNALS AND REGISTERS Table 5 1 describes the external interrupt signals and Table 5 2 describes the control and status registers for both the interrupt controller and PTS Table 5 1 Interrupt Signals Port Pin Interrupt Signal Type Description EXTINT External Interrupt This programmable interrupt is controlled by the WG_PROTECT register This register controls whether the interrupt is edge triggered or sampled and whether a rising edge high level or falling edge low level activates the interrupt In powerdown mode asserting the EXTINT signal for at least 50 ns causes the device to resume normal operation The interrupt need not be enabled If the EXTINT interrupt is enabled the CPU executes the interrupt service routine Otherwise the CPU executes the instru
366. ettings 5 20 intel INSTRUCTION SET REFERENCE Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format JNH JUMP IF NOT HIGHER UNSIGNED Tests both the zero flag and the carry flag If the JNH cadd carry flag is set and the zero flag is clear control passes to the next sequential 11010001 disp instruction If either the carry flag is clear or the zero flag is set this instruction adds to the NOTE The displacement disp is sign program counter the offset between the end extended to 16 bits of this instruction and the target label effecting the jump The offset must be in range of 128 to 127 if C 2 0 ORZ 1 then PC lt PC 8 bit disp PSW Flag Settings Z N C V VT ST JNST JUMP IF STICKY BIT FLAG IS CLEAR Tests the sticky bit flag If the flag is set control JNST cadd passes to the next sequential instruction If the sticky bit flag is clear this instruction adds 11010000 disp to the program counter the offset between the end of this instruction and the target label NOTE The displacement disp is sign effecting the jump The offset must be in extended to 16 bits range of 128 to 127 if ST then PC lt PC 8 bit disp PSW Flag Settings Z N C V VT ST JNV JUMP IF OVERFLOW FLAG IS CLEAR Tests the o
367. evel of the BUSWIDTH signal must be valid after CLKOUT falls Tev ALE Low to BUSWIDTH Setup Maximum time the external device has to assert or deassert BUSWIDTH after ALE falls Text BUSWIDTH Hold after ALE Low Minimum time the level of the BUSWIDTH signal must be valid after ALE falls Tyran All AC timings are referenced to Ty t This specification applies to the 8XC196MC MD microcontrollers only tt This specification applies to the 8XC196MH microcontroller only The BUSWIDTH signal can be used in numerous applications For example a system could store code in a 16 bit memory device and data in an 8 bit memory device The BUSWIDTH signal could be tied to the chip select input of the 8 bit memory device shown in Figure 15 13 on page 15 24 When BUSWIDTH is low it enables 8 bit bus mode and selects the 8 bit memory device When BUSWIDTH is high it enables 16 bit bus mode and deselects the 8 bit memory device 15 3 1 Timing Requirements for BUSWIDTH When using BUSWIDTH to dynamically change between 8 bit and 16 bit bus widths setup and hold timings must be met for proper operation see Figures 15 4 and 15 5 and Table 15 4 Be cause a decoded valid address is used to generate the BUSWIDTH signal the setup time is spec ified relative to the address being valid This specification indicates how much time an external device has to decode the valid address and generate a valid BUSWIDTH signal As sh
368. evice revisions in which case a pro gram that relies on a location in this range might not function properly Indirect or indexed Indirect indexed or Upper register file general purpose register RAM Windowed direct Direct indirect or indexed 4 1 3 Program Memory Program memory occupies a memory partition beginning at 2080H See Table 4 1 for the ending address for each device This entire partition is available for storing executable code and data The EA signal controls access to program memory Accesses to this address range are directed to internal memory if EA is held high and to external memory if EA is held low For devices without internal nonvolatile memory the EA signal must be tied low EA is latched at reset NOTE We recommend that you write FFH the opcode for the RST instruction to unused program memory locations This causes a device reset if a program unintentionally begins to execute in unused memory 4 2 ntel MEMORY PARTITIONS 4 1 4 Special purpose Memory Special purpose memory resides in locations 2000 207 Table 4 2 It contains several re served memory locations the chip configuration bytes CCBs and vectors for both peripheral transaction server PTS and standard interrupts Accesses to this address range are directed to internal memory if EA is held high and to external memory if EA is held low For devices with out internal nonvolatile memory the
369. exed with AD7 0 and PBUS 7 0 P4 7 0 yo Port 4 This is a memory mapped 8 bit bidirectional port with programmable open drain or complementary output modes The pins are shared with the multiplexed address data bus which has complementary drivers P4 7 0 are multiplexed with AD15 8 and PBUS15 8 P5 7 0 Port 5 This is a memory mapped 8 bit bidirectional port that is multiplexed with individually selectable control signals P5 4 is multiplexed with the ONCE function If this pin is held low during reset the device will enter ONCE mode so exercise caution if you use this pin for input If you choose to configure this pin as an input always hold it high during reset and ensure that your system meets the V specification see datasheet to prevent inadvertent entry into ONCE mode Port 5 is multiplexed as follows P5 0 ALE ADV P5 1 INST P5 2 WR WRL P5 3 RD P5 4 ONCE P5 5 BHE WRH P5 6 READY and P5 7 BUSWIDTH P6 7 0 O Port 6 This is a standard 8 bit output only port that is multiplexed with the special functions of the waveform generator and PWM peripherals The WG_OUT register configures the pins establishes the output polarity and controls whether changes to the outputs are synchronized with an event or take effect immediately Port 6 is multiplexed as follows P6 0 WG1 P6 1 WG1 P6 2 WG2 P6 3 WG2 P6 4 WG3 P6 5 WG3 P6 6 PWMO and P6 7 PWM1 B 18 intel SIGNAL DESCRIPTIONS Table B 6 Signal D
370. external programmer can use this information to determine the device type and operating conditions You should never write to these locations The voltages are calculated by using the following equation after converting the test ROM value to decimal 20 x test ROM value Voltage 256 20 x 64 20 x 160 Voc 40H 5 volts Vpp 0A0H 40H 256 pp 256 12 5 volts 16 15 8XC196MC MD MH USER S MANUAL Table 16 8 Device Signature Word and Programming Voltages lel Signature Word Programming Vec Programming Vpp Device Location Value Location Value Location Value 8XC196MC MD 0070H 8794H 0072H 40H 0073H 8XC196MH 0070H 87DEH 0072H 40H 0073H 16 8 2 Slave Programming Circuit and Memory Figure 16 5 shows the circuit diagram and Table 16 9 shows the memory map for slave program ming mode The external clock signal can be supplied by either a clock or a crystal Refer to the device datasheet for acceptable clock frequencies XTAL1 RESET NMI P4 7 0 P3 7 0 P2 6 P2 4 P2 2 2 1 2 0 Vngr P0 7 PMODE 3 P0 6 PMODE 2 P0 5 PMODE 1 4 0 ANGND 87C196 Device CLOCK RESET CPVER AINC PROG PALE PVER Voc 10ko Pullups Required P4 7 P3 0 A0256 03 16 16 Figure 16 5 Slave Programming Circuit intel PROGRAMMING THE NONVOLATILE MEMORY Table 16
371. f SFRs Also because some SFRs are cleared when read consider the implications of using an SFR as an operand in a read modify write instruction e g XORB 3 4 2 Addressing 32 bit Operands The 32 bit operands DOUBLE WORDs and LONG INTEGERs are formed by two adjacent 16 bit words in memory The least significant word of a DOUBLE WORD is always in the lower address even when the data is in the stack which means that the most significant word must be pushed into the stack first The address of a 32 bit operand is that of its least significant byte The hardware supports the 32 bit data types as operands in shift operations as dividends of 32 by 16 divide operations and as products of 16 by 16 multiply operations For these operations the 32 bit operand must reside in the lower register file and must be aligned at an address that is evenly divisible by four 3 4 3 Linking Subroutines Parameters are passed to subroutines via the stack Parameters are pushed into the stack from the rightmost parameter to the left The 8 bit parameters are pushed into the stack with the high order byte undefined The 32 bit parameters are pushed into the stack as two 16 bit values the most significant half of the parameter is pushed into the stack first As an example consider the fol lowing procedure void example procedure char paraml long param2 int param3 When this procedure executes at run time the stack will contain the parameters in the
372. f the PSW flags or a specified condition on conditional jump instruc tions Table A 4 defines the symbols used in Table A 6 to show the effect of each instruction on the PSW flags Table A 3 Effect of PSW Flags or Specified Conditions on Conditional Jump Instructions Instruction Jumps to Destination if Continues if DJNZ decremented byte 0 decremented byte 0 DJNZW decremented word 0 decremented word 0 JBC specified register bit 0 specified register bit 1 JBS specified register bit 1 specified register bit 0 JNC 0 1 JNH C 0ORZ 1 C 1ANDZ 0 JC 1 0 JH C 1ANDZ 0 C 0ORZ 1 JGE N 0 N 1 JGT N 0ANDZ 0 N 1ORZ 1 JLT N 1 N 0 JLE N 10ORZ 1 N 0ANDZ 0 JNST ST 0 ST 1 JST ST 1 ST 0 JNV V 0 V 1 JV 1 V 0 JNVT VT 0 VT 1 clears VT JVT VT 1 clears VT VT 0 JNE Z 0 Z 1 JE Z 1 Z 0 Table A 4 PSW Flag Setting Symbols Symbol Description instruction sets or clears the flag as appropriate The instruction does not modify the flag 2 instruction may clear the flag if it is appropriate but cannot set it T The instruction may set the flag if itis appropriate but cannot clear it 1 The instruction sets the flag 0 The instruction clears the flag The instruction leaves the flag in an indeterminate state A 5 8XC196MC MD MH USER S MANUAL intel Table A 5 defines the
373. following order param3 low word of param2 high word of param2 undefined paraml return address Stack Pointer intel PROGRAMMING CONSIDERATIONS If a procedure returns a value to the calling code as opposed to modifying more global variables the result is returned in the temporary storage space in this example starting at TMPREGO is viewed as either an 8 16 or 32bit variable depending on the type of the proce dure The standard calling convention adopted by the C programming language has several key fea tures e Procedures can always assume that the eight bytes of register file memory starting at can be used as temporary storage within the body of the procedure Code that calls a procedure must assume that the procedure modifies the eight bytes of register file memory starting at 1CH Code that calls a procedure must assume that the procedure modifies the processor status word PSW condition flags because procedures do not save and restore the PSW Function results from procedures are always returned in the variable TMPREGO The C programming language allows the definition of interrupt procedures which are executed when a predefined interrupt request occurs Interrupt procedures do not conform to the rules of normal procedures Parameters cannot be passed to these procedures and they cannot return re sults Since interrupt procedures can execute essentially at any time they m
374. g N Detector P7 7 2 2704 02 Figure 8 4 Infrared Remote Control Application Block Diagram y kHz EY Zero 2 ms One 4 ms A2703 01 Figure 8 5 Data Encoding Example This program example was designed to run on an 8XC196MD demo board It uses an EPA timer timer 1 and compare channel COMP3 to provide the timebase for the ones and zeros This pro gram and the others included in AP 483 Application Examples Using the SXCI96MC MD Mi crocontroller order number 272282 are available from the Intel BBS filename AP 483 EXE See Bulletin Board System BBS on page 1 9 for information about accessing the BBS debug nolist include c ecm 196mc mc inc Slist BAAS RAGE AAR RI RUE PROGRAM FREQ A96 This program transmits a block of data serially by gating the frequency generator on and off The carrier frequency is programmed for 40 kHz Ones are represented by a long 2 ms carrier burst followed by a long 2 ms pause no carrier Zeros are represented by a short 1 ms carrier burst 8 5 8XC196MC MD MH USER S MANUAL intel followed by a short 1 ms pause thus generating a MFM waveform This program is assembled to run on the MD demo board ARERR AL ALARA REE ARIEL EAR LOR EEE CONSTANT AND VARIABLE DECLARATIONS ou ue d Program equates This section defines the constants used by this program T
375. ggertt Writing this bit arms the A D converter The value that you write to it determines at what point a conversion is to start 0 EPA initiates conversion 1 start immediately 3 0 0 A D Channel Selection Write the A D conversion channel number to these bits While a threshold detection mode is selected for an analog input no other conversion can be started If another value is loaded into AD COMMAND the threshold detection mode is disabled and the new command is executed tt Itisthe act of writing to the GO bit rather than its value that starts a conversion Even if the GO bit has the desired value you must set it again to start a conversion immediately or clear it again to arm it for an EPA initiated conversion C 6 intel REGISTERS AD RESULT Read AD RESULT Read Address 1FAAH Reset State MC MD FFCOH Reset State MH 7FCOH The A D result AD RESULT register consists of two bytes The high byte contains the eight most significant bits from the A D converter The low byte contains the two least significant bits from a ten bit A D conversion indicates the A D channel number that was used for the conversion and indicates whether a conversion is currently in progress 15 8 ADRLT9 ADRLT8 ADRLT7 ADRLT6 ADRLT5 ADRLT4 ADRLT3 ADRLT2 7 0 ADRLT1 ADRLTO STATUS ACH3 ACH2 ACH1 ACHO Bit Bit Number Mnemonic
376. gnal indicates that an error occurred during one of the programming operations CPVER is multiplexed with P2 6 and COMP2 EA External Access This input determines whether memory accesses to special purpose and program memory partitions are directed to internal or external memory See Table 4 1 on page 4 2 for address ranges of special purpose and program memory partitions These accesses are directed to internal memory if EA is held high and to external memory if EA is held low For an access to any other memory location the value of EA is irrelevant EA also controls entry into the programming modes If EA is at Vpp voltage typically 12 5 V on the rising edge of RESET the microcontroller enters a programming mode NOTE Systems with EA tied inactive have idle time between external bus cycles When the address data bus is idle you can use ports 3 and 4 for I O Systems with EA tied active cannot use ports 3 and 4 as standard I O when EA is active these ports will function only as the address data bus EA is sampled and latched only on the rising edge of RESET Changing the level of EA after reset has no effect Always connect EA to Vss when using a microcontroller that has no internal nonvolatile memory B 15 8XC196MC MD MH USER S MANUAL intel Table B 6 Signal Descriptions Continued Name Type Description EPA3 0 MC 5 0 MD EPA1 0 MH Event Processor A
377. h Flash and RAM 15 23 8XC196MC MD MH USER S MANUAL intel Figure 15 13 shows a system that uses the dynamic bus width feature The CCR bits BWO and are set Code is executed from the two EPROMs and data is stored in the byte wide RAM The RAM is in high memory It is selected by driving AD15 high which also selects the 8 bit bus width mode by driving the BUSWIDTH signal low BUSWIDTH D7 0 8Kx8 8XC196 RAM AD7 0 AT 0 OE WEZ A3087 01 Figure 15 13 16 bit System with Dynamic Bus Width 15 24 intel INTERFACING WITH EXTERNAL MEMORY 15 5 2 Write Strobe Mode The write strobe mode eliminates the need to externally decode high and low byte writes to an external 16 bit RAM or flash device in 16 bit bus mode When the write strobe mode is selected the microcontroller generates WRL and WRH instead of WR and BHE WRL is asserted for all low byte writes even addresses and all word writes WRH is asserted for all high byte writes odd addresses and all word writes In the 8 bit bus mode WRH and WRL are asserted for both even and odd addresses Figure 15 14 shows write strobe mode timing ALE ALE AD15 0 Data Out AD15 8 Address High 16 bit Bus Cycle 8 bit Bus Cycle A3089 01 Figure 15 14 Write Strobe Mode 15 25 8XC196MC MD MH USER S MANUAL intel Figure 15 15 shows a 16 bit system with two EPROMs and two RAMs It is configured to use the write
378. hardware considerations 14 7 F FaxBack service 1 8 FE opcode and inhibiting interrupts 5 9 Floating point library 3 4 Formulas A D conversion result 12 9 12 13 Index 4 intel A D conversion time 12 7 A D error 12 11 A D sample time 12 7 A D series resistance 12 10 A D threshold voltage 12 5 A D voltage drop 12 11 capacitor size powerdown circuit 14 10 and PH2 frequency 2 8 programming pulse width OTPROM 16 8 programming voltage 16 15 SIO baud rate 7 13 state time 2 8 FPAL 96 3 4 FREQOUT B 16 Frequency generator 8 1 8 9 application example 8 4 8 9 data encoding example 8 5 block diagram 8 1 infrared remote control application 8 5 overview 8 1 8 2 programming frequency 8 3 output 8 3 registers 8 2 status 8 4 Frequency generator count register 8 4 C 22 Frequency register 8 3 C 23 H Handbooks ordering 1 6 Hardware A D converter considerations 12 10 12 13 addressing modes 3 5 auto programming circuit 16 26 device considerations 13 1 13 13 device reset 13 8 13 10 13 11 13 12 interrupt processor 2 6 5 1 memory protection 16 7 16 17 minimum configuration 13 1 NMI considerations 5 6 noise protection 13 4 pin reset status B 23 B 25 programming mode requirements 16 13 reset instruction 3 11 SIO port considerations 7 8 slave programming circuit 16 16 UPROM considerations 16 7 intel Hypertext manuals and datasheets downloading 1 10
379. he window selection register It also shows that the base address of the 64 byte memory area is 1FCOH To determine the offset subtract that base address from the address to be accessed 1FCCH 1FCOH 000CH Add the offset to the base address of the window in the lower reg ister file OOCOH from Table 4 12 The direct address is 00CCH 000CH 00 4 2 2 3 128 byte Windowing Example Assume that you wish to access location 1F42H the EPAO TIME register with register direct addressing through a 128 byte window Table 4 11 shows that you need to write 1EH to the win dow selection register It also shows that the base address of the 128 byte memory area is 1F00H To determine the offset subtract that base address from the address to be accessed 1F42H 1F00H 0042H Add the offset to the base address of the window in the lower register file 0080H from Table 4 12 The direct address is 00C2H 0042H 0080H 4 2 2 4 Unsupported Locations Windowing Example Assume that you wish to access location 1FF1H the P5 MODE register a memory mapped SFR with register direct addressing through a 128 byte window This location is in the range of addresses 1FEO 1FFFH that cannot be windowed Although you could set up the window by writing 1FH to the WSR reading this location through the window would return FFH all ones and writing to it would not change the contents However you could access the peripheral SFRs in the range of IF80 1FDFH
380. he A D result AD RESULT register can be written to set the reference voltage for the A D threshold detection modes 15 8 REFV7 REFV6 REFV5 REFV4 REFV3 REFV2 REFV1 REFVO 7 0 Bit Bit Number Mnemonic Function 15 8 REFV7 0 Reference Voltage These bits specify the threshold value This selects a reference voltage that is compared with an analog input pin When the voltage on the analog input pin crosses over detect high or under detect low the threshold value the A D conversion complete interrupt pending bit is set Use the following formula to determine the value to write to this register for a given threshold voltage cs desired threshold voltage x 256 BRUT Vaer ANGND 7 0 Reserved for compatibility with future devices write zeros to these bits Figure 12 3 A D Result AD_RESULT Register Write Format 12 4 3 Programming the A D Time Register Two parameters sample time and conversion time control the time required for an A D conver sion The sample time is the length of time that the analog input voltage is actually connected to the sample capacitor If this time is too short the sample capacitor will not charge completely If the sample time is too long the input voltage may change and cause conversion errors The con version time is the length of time required to convert the analog input voltage stored on the sample capacitor to a digital value The conversi
381. he EPA channels In capture mode the value of the reference timer is captured in EPAx_TIME when an input transition occurs Each event time register is buffered allowing the storage of two capture events at once In compare mode the EPA triggers a compare event when the reference timer matches the value in EPAx_TIME is not buffered for compare mode 15 0 EPA Timer Value Bit Number Function 15 0 EPA Timer Value When an EPA channel is configured for capture mode this register contains the value of the reference timer when the specified event occurred When an EPA channel is configured for compare mode write the compare event time to this register Table C 5 EPAx_TIME Addresses and Reset Values Register Address Reset Value EPAO TIME 8 196 1F42H XXXXH EPA1 TIME 8XC196Mx 1F46H XXXXH EPA2 TIME 8XC196MC MD 1F4AH XXXXH EPA3_TIME 8XC196MC MD 1F4EH XXXXH EPA4_TIME 8XC196MD 1F52H XXXXH EPA5 TIME 8XC196MD 1F56H XX00H C 21 8XC196MC MD MH USER S MANUAL intel FREQ_CNT FREQ_CNT Address 1FBAH 8XC196MD Reset State 00H down counter Read the frequency generator count FREQ_CNT register to determine the current value of the 7 0 8XC196MD Count Bit 2 Number Function 7 0 Count This register contains the current down counter value C 22 intel REGISTERS FREQ GEN FREQ GEN
382. he instruction following the IDLPD 2 instruction and the pending bit remains set until the interrupt is serviced or software clears the pending bit ere Internal Powerdown Signal I S NE E QUE WAND E M T T T T 1 Timeout Internal 21 0078 01 Figure 14 2 Power up Power down Sequence When Using External Interrupt When using an external interrupt signal to exit powerdown mode we recommend that you con nect the external RC circuit shown in Figure 14 3 to the V pin The discharging of the capacitor causes a delay that allows the oscillator to stabilize before the internal CPU and peripheral clocks are enabled 14 7 8XC196MC MD MH USER S MANUAL intel 8XC196 Device R4 1 MQ Typical T C4 1 Typical A0279 01 Figure 14 3 External RC Circuit During normal operation before entering powerdown mode an internal pull up holds the pin at When an external interrupt signal is asserted the internal oscillator circuitry is enabled and turns on a weak internal pull down This weak pull down causes the external capac itor to begin discharging at a typical rate of 200 uA When the pin voltage drops below the threshold voltage about 2 5 V the internal phase clocks are enabled and the device resumes code execution At this time the internal pull up transistor turns on and quickly pulls the pin
383. he interrupt request is detected and the time that it is acknowledged An interrupt request is acknowledged when the current instruction finishes executing If the interrupt request occurs during one of the last four state times of the instruction it may not be acknowledged until after the next instruction finishes This additional delay occurs because instructions are prefetched and prepared a few state times before they are executed Thus the maximum delay between interrupt request and ac knowledgment is four state times plus the execution time of the next instruction When a standard interrupt request is acknowledged the hardware clears the interrupt pending bit and forces a call to the address contained in the corresponding interrupt vector When a PTS in terrupt request is acknowledged the hardware immediately vectors to the PTSCB and begins ex ecuting the PTS routine 5 4 1 Situations that Increase Interrupt Latency If an interrupt request occurs while any of the following instructions are executing the interrupt will not be acknowledged until after the next instruction is executed the signed prefix opcode FE for the two byte signed multiply and divide instructions any of these eight protected instructions DI DPTS EPTS POPA POPF PUSHA PUSHF see Appendix A for descriptions of these instructions any of the read modify write instructions AND ANDB OR ORB XOR XORB Both the unimplemented opcode interrupt a
384. he unimplemented opcode interrupt prevents other inter rupt requests from being acknowledged until after the next instruction is executed 5 3 1 2 Software Trap The TRAP instruction opcode F7H causes an interrupt call that is vectored through location 2010H The TRAP instruction provides a single instruction interrupt that is useful when debug ging software or generating software interrupts The TRAP instruction prevents other interrupt requests from being acknowledged until after the next instruction is executed 5 3 1 3 NMI The external NMI pin generates a nonmaskable interrupt for implementation of critical interrupt routines NMI has the highest priority of all the prioritized interrupts It is passed directly from the transition detector to the priority encoder and it vectors indirectly through location 203EH The NMI pin is sampled during phase 2 CLKOUT high and is latched internally Because inter rupts are edge triggered only one interrupt is generated even if the pin is held high If your system does not use the NMI interrupt connect the NMI pin to to prevent spurious interrupts 5 3 2 External Interrupt Pin The protection circuitry in the waveform generator Figure 5 2 monitors the external interrupt EXTINT signal When it detects a valid event on the input it sumultaneously disables the wave form generator outputs and generates an EXTINT interrupt request Bits 2 and 3 in the waveform generator protection
385. he zero offset error and the zero offset adjustment allows you to compensate for it This feature can reduce or eliminate off chip compensation hardware Typ ically you would convert the test voltages and adjust for the zero offset error before performing conversions on an input channel The TEST register allows you to program a zero offset ad justment A threshold detection compares an input voltage to a programmed reference voltage and sets the A D interrupt pending bit when the input voltage crosses over or under the reference voltage A conversion can be started by a write to the AD COMMAND register or it can be initiated by the EPA which can provide equally spaced samples or synchronization with external events See Programming the EPA and Timer Counters on page 11 15 The A D scan mode of the pe ripheral transaction server PTS allows you to perform multiple conversions and store their re sults See A D Scan Mode on page 5 32 12 8 8XC196MC MD MH USER S MANUAL intel Once the A D converter receives the command to start a conversion a delay time elapses before sampling begins EPA initiated conversions begin after the capture compare event Immediate conversions those initiated directly by a write to AD COMMAND begin within three state times after the instruction is completed During this sample delay the hardware clears the suc cessive approximation register and selects the designated multiplexer channel Af
386. her devices requiring multiple PWM outputs See watchdog timer Any 16 bit unit of data An unsigned 16 bit variable with values from 0 through 216 1 A method for converting data to a larger format by filling the upper bit positions with zeros An ideal A D converter s first code transition occurs when the input voltage is 0 5 LSB Zero offset error is the difference between 0 5 LSB and the actual input voltage that triggers an A D converter s first code transition Glossary 11 intel Index intel defined 1 3 A 1 16 bit data bus read cycles 15 14 timing diagram 15 15 write cycles 15 14 8 bit data bus read cycles 15 16 timing diagram 15 17 write cycles 15 16 A A D command register 12 8 C 6 A D converter 2 11 12 1 12 18 actual characteristic 12 16 and port 0 reads 12 13 and PTS 5 32 5 37 block diagram 12 1 calculating result 12 9 12 13 calculating series resistance 12 10 characteristics 12 15 12 18 conversion time 12 6 determining status 12 9 errors 12 13 12 18 hardware considerations 12 10 12 13 ideal characteristic 12 15 12 16 input circuit suggested 12 12 input protection devices 12 12 interfacing with 12 10 12 13 interpreting results 12 9 interrupt 12 8 minimizing input source resistance 12 11 overview 12 3 12 4 programming 12 4 12 8 sample delay 12 4 sample time 12 6 sample window 12 4 SFRs 12 2 signals 12 2 starting with PTS 5 32 5 37 success
387. hey can be changed at assembly time as required REA AoA REAR ALAA ISAS IRURE ARERR zero_time equ 1000 21 ms zero_pause_time equ zero_time one_time equ 2000 2 ms one_pause_time equ one_time carrier freq equ 25 40 KHz buf size equ 8 Size of data buffer bytes fill char equ 10100011b initial data for buffer AAA LALA LAL LER UK SFR equates in a 32 byte window This section defines SFR locations as seen through a window to allow using compact read modify write instructions E A AA AAA AAAS ARE LAA ALA LARA p2_mode_w equ Of0H WSR 1FDOH p2_dir_w equ OF2H 1FD2H p2 reg w equ OF4H WSR 1FD4H p2_pin_w equ OF 6H WSR 1FD6H p7 mode equ Of1H WSR 1FD1H p7_dir_w equ OF3H WSR 1FD3H p reg w equ OF5H WSR 1FD5H p7_pin_w equ OF7H WSR 1FD7H timerl w equ OFAH WSR 7BH 1F7AH comp3 con w equ OEAH WSR 7BH 1F64H comp3 time w equ OE6H WSR 7BH 1F66H OE OR SARA RR ALARA Other SFR equates This section defines the locations of the frequency generator SFRs AAA AAA COR OK OK AAA freq gen equ 1FB8H freq cnt equ 1FBAH gt Variable storage area This section defines the variables used by this program 2 OK KC OK UK REAAAAREALA LEER
388. high until your software writes to PS_MODE If EA is low on reset external access either ALE or ADV is activated as a system control pin depending on the ALE bit of CCRO In either case the pin becomes a true complementary output This pin remains weakly held high until your software writes config uration data into 5 MODE This pin remains weakly held high until your software writes config uration data into 5 MODE If EA is high on reset internal access the pin is weakly held high until your software writes to 5 MODE If EA is low on reset external access RD is activated as a system control pin and the pin becomes a true complementary output This pin is weakly held high until your software writes to P5 MODE P5 4 is the enable pin for ONCE mode see Chapter 14 Special Operating Modes and one of the enable pins for Intel reserved test modes Because a low input during reset could cause the device to enter ONCE mode or a reserved test mode exercise caution if you use this pin for input Be certain that your system meets the V specification listed in the datasheet during reset to prevent inadvertent entry into ONCE mode or a test mode This pin is weakly held high until the CCB fetch is completed At that time the state of this pin depends on the value of the BWO bit of the CCRs If BWO is clear the pin remains weakly held high until your software writes to 5 MODE If BWO is set BHE is activated as a sys
389. hreshold voltage NOTE If powerdown is re entered and exited before charges to it will take less time for the voltage to ramp down to the threshold Therefore the device will take less time to exit powerdown For example assume that the oscillator needs at least 12 5 ms to discharge This 12 5 ms V is 2 5 V and the discharge current is 200 UA The minimum capacitor size is 1 _ 0 0125 0 0002 _ C 1 2 5 1 When using an external oscillator the value of C can be very small allowing rapid recovery from powerdown For example 100 pF capacitor discharges in 1 25 us 14 5 ONCE MODE On circuit emulation ONCE mode isolates the device from other components in the system to allow printed circuit board testing or debugging with a clip on emulator During ONCE mode all pins except XTAL1 XTAL2 and are weakly pulled high or low During ONCE mode RESET must be held high or the device will exit ONCE mode and enter the reset state 14 10 intel SPECIAL OPERATING MODES Holding the ONCE signal low during the rising edge of RESET causes the device to enter ONCE mode To prevent accidental entry into ONCE mode we highly recommend configuring this pin as an output If you choose to configure this pin as an input always hold it high during reset and ensure that your system meets the V specification see datasheet to prevent inadvert ent entry into ONCE mode Exit ONCE mode by asser
390. ht line code by us ing the interrupt pending register to signal the completion of a reception 8XC196MC MD MH USER S MANUAL intel During a reception the RI flag in SPx STATUS is set after the stop bit is sampled The RIx pend ing bit in the interrupt pending register is set immediately before the RI flag is set During a trans mission the TI flag is set immediately after the end of the last eighth data bit is transmitted The TIx pending bit in the interrupt pending register is generated when the TI flag in SPx STATUS is set TXD VT Nf OE OP OF RXD out Xe Ks RXD in 20 06 Expanded UL e NL ue es ff RXD out 4 3 X ee RXD in A A0109 02 Figure 7 3 Mode 0 Timing 7 3 1 2 Mode 4 Mode 4 is an enhanced synchronous mode that is similar to mode 0 in many ways but there are three main differences In mode 0 TXDx inputs or outputs the clock signal and RXDx transmits or receives data In mode 4 TXDx transmits data RXDx receives data and the SCLK pin inputs or outputs the clock signal For mode 4 a direction bit DIR was added to the SPx CON register This bit controls whether SCLKx outputs the internal shift clock or inputs an external shift clock n mode 0 RXDx must be enabled to start a transmission because it must transmit the data In mode 4 TXDx transmits the data so the RXDx status is unrelated to transmission
391. iZ Note 2 Vpp HiZ LoZ1 LoZ1 B 25 8XC196MC MD MH USER S MANUAL intel Table B 9 8XC196MH Default Signal Conditions Continued Alternate During Port Signals Functions pet Inactive Idle Powerdown Note 12 XTAL1 Osc input HiZ Osc input HiZ Osc input HiZ XTAL2 Osc output Osc output Note 5 LoZ0 1 LoZ0 1 NOTES 1 These pins also control test mode entry 2 If Disable Reset Out 0 is 1020 Else if Disable Reset Out 1 pin is HIZ 3 f EA 0 Port Port 4 If EA 1 Port and Port 4 ODIO 4 If EA 1 pin is WK1 If EA 0 P5 0 P5 3 and P5 5 are configured as outputs and function as ADV RD or BHE respectively 5 If XTAL1 1 pin is LoZO If XTAL1 0 pin is 1021 6 If P5_MODE 0 0 port is as programmed If P5 MODE 0 1 and CCR 3 1 ALE mode is LoZO If P5 MODE 0 1 and CCR 3 0 ADV mode pin is LoZ1 7 If P5_MODE 1 0 port is as programmed If 5 1 1 is 1020 8 IfP5 MODE y 0 port is as programmed If P5 MODE y 1 pin is LoZ1 9 I fP5 MODE y 0 port is as programmed If P5 MODE y 1 pin is 10 If Px MODE y 0 port is as programmed If Px MODE y 1 pin is as specified by the associated peripheral 11 If output port pin is as programmed If special function pin is as specified by the associated periph eral 12 The values in this column ar
392. ic Address Description WG_OUTPUT 1FCOH Port 6 Output Control Register This register controls the port 6 pins in I O mode Its functions differ when the port 6 pins are being used as waveform generator or PWM outputs 6 5 1 Output only Port Operation Figure 6 4 shows a simplified circuit schematic for port 6 Port 6 has a single configuration and control register WG OUTPUT Transistor Q1 can source at least 200 uA at 0 3 volts For pins P6 0 P6 5 transistor Q2 can sink at least 10 mA at 0 45 volts For pins P6 6 and P6 7 Q2 can sink at least 200 uA at 0 3 volts 6 5 2 Configuring Output only Port Pins Port 6 has a single configuration register OUTPUT Figure 6 5 This register controls the pin functions values and output polarity This register can be addressed either as a word or as separate bytes and it can be windowed The functions of this register are different for configuring general purpose outputs than for configuring waveform generator and PWM outputs 6 17 8XC196MC MD MH USER S MANUAL Internal Bus Q1 Output Pin Combinational Logic Q2 A2764 01 Figure 6 4 Output only Port OUTPUT Port 6 Address 1FCOH Reset State 0000H The port 6 output configuration WG OUTPUT register controls port 6 functions If you are using port 6 for general purpose outputs write COH for active high outputs or 00H for active low outputs to the high byte of WG OUTPUT
393. ic Functio 15 Z Zero Flag This flag is set to indicate that the result of an operation was zero For multiple precision calculations the zero flag cannot be set by the instruc tions that use the carry bit from the previous calculation e g ADDC SUBC However these instructions can clear the zero flag This ensures that the zero flag will reflect the result of the entire operation not just the last calculation For example if the result of adding together the lower words of two double words is zero the zero flag would be set When the upper words are added together using the ADDC instruction the flag remains set if the result is zero and is cleared if the result is not zero 14 N Negative Flag This flag is set to indicate that the result of an operation is negative The flag is correct even if an overflow occurs For all shift operations and the NORML instruction the flag is set to equal the most significant bit of the result even if the shift count is zero 13 V Overflow Flag This flag is set to indicate that the result of an operation is too large to be represented correctly in the available space For shift operations SHL SHLB and SHLL the flag is set if the most significant bit of the operand changes during the shift For divide operations the quotient is stored in the low order half of the destination operand and the remainder is stored in the high order half The overflow flag is set if the quotient is outside
394. ide sufficient reset time as long as rises quickly 13 10 intel MINIMUM HARDWARE CONSIDERATIONS RESET MCS 96 ii Microcontroller A0276 02 Figure 13 10 Minimum Reset Circuit Other devices in the system may not be reset because the capacitor will keep the voltage above Since RESET is asserted for only 16 state times it may be necessary to lengthen and buffer the system reset pulse Figure 13 11 shows an example of a system reset circuit In this example D2 creates a wired OR gate connection to the reset pin An internal reset system power up or SWI closing will generate the system reset signal RESET SW1 MCS 96 Microcontroller System reset signal to external circuitry Notes 1 D1 provides a faster cycle time for repetitive power on resets 2 Optional pull up for faster recovery A0277 03 Figure 13 11 Example of a System Reset Circuit 13 11 8XC196MC MD MH USER S MANUAL intel 13 6 2 Issuing the Reset RST Instruction The RST instruction opcode FFH resets the device by pulling RESET low for 16 state times It also clears the processor status word PSW sets the master program counter PC to 2080H and resets the special function registers SFRs See Table C 2 on page C 2 for the reset values of the SFRs Putting pull ups on the address data bus causes unimplemented areas of memory to be read as If unused internal OTPROM memory is set to
395. ify the default priorities of maskable interrupts by controlling the interrupt mask registers INT MASK and INT For example you can specify which interrupts if any can interrupt an interrupt service routine The following code shows one way to prevent all interrupts except EXTINT priority 14 from interrupting an A D conversion complete inter rupt service routine priority O1 SERIAL RI ISR PUSHA LDB INT MASK1 01000000B EI POPA RET CSEG AT 02002H DCW AD DONE ISR 5 18 this disables all interrupts Enable EXTINT only Enable interrupt servicing Service the AD_DONE interrupt Restore PSW INT MASK INT 5 WSR registers fill in interrupt table END Save PSW INT MASK INT MASK1 amp WSR amp intel STANDARD AND PTS INTERRUPTS Note that location 2002H in the interrupt vector table must be loaded with the value of the label AD DONE ISR before the interrupt request occurs and that the A D conversion complete inter rupt must be enabled for this routine to execute This routine like all interrupt service routines is handled in the following manner 1 After the hardware detects and prioritizes an interrupt request it generates and executes an interrupt call This pushes the program counter onto the stack and then loads it with the contents of the vector corresponding to the highest priority pending unmasked interrupt The hardware will not allow another i
396. igh signal indicates that all locations programmed correctly while a low signal indicates that an error occurred during one of the programming operations P2 7 PACT Auto Programming Active ROM During auto programming or ROM dump a low dump signal indicates that programming or dumping is in progress while a high signal indicates that the operation is complete P4 7 0 P3 7 0 PBUS Slave Address Command Data Bus During slave programming ports and 4 serve as a bidirectional port with open drain outputs to pass commands addresses and data to or from the device Slave programming requires external pull up resistors 4 7 0 MC MD P3 7 0 MC MD P1 3 0 MH 4 3 0 MH P3 7 0 MH PBUS VO Auto Address Command Data Bus ROM During auto programming and ROM dump ports 3 dump and 4 serve as a regular system bus to access external memory For the 8XC196MH P4 7 4 are left unconnected P1 3 0 serve as the upper address lines 16 12 intel PROGRAMMING THE NONVOLATILE MEMORY Table 16 6 Pin Descriptions Continued Special Program Port Pin function Type ming Description Signal Mode EA All External Access Controls program mode entry If EA is at Vpp voltage on the rising edge of RESETZ the device enters programming mode EA is sampled and latched only on the rising edge of RESET Changing the level of EA after reset has no effec
397. igure this pin as an output or hold it high during reset and ensure that your system meets the V specification see datasheet P2 6 Test mode VO Test mode entry entry If this pin is held low during reset the device will enter a reserved test mode so exercise caution if you use this pin for input If you choose to configure this pin as an input always hold it high during reset and ensure that your system meets the specification see datasheet to prevent inadvertent entry into a test mode RESET VO Reset A level sensitive reset input to and open drain system reset output from the microcontroller Either a falling edge on RESET or an internal reset turns on a pull down transistor connected to the RESET pin for 16 state times In the powerdown and idle modes asserting RESET causes the chip to reset and return to normal operating mode The 8XC196MH provides the option of preventing an internal reset from generating a reset on the external pin see Resetting the Device on page 13 8 After a device reset the first instruction fetch is from 2080H Vpp PWR Programming Voltage During programming the V is typically at 12 5 V voltage Exceeding the maximum Vpp voltage specification can damage the device Vpp also causes the device to exit powerdown mode when it is driven low for at least 50 ns Use this method to exit powerdown only when using an external clock source because it enables the inter
398. ile memory at addresses 2018H CCBO and 201AH CCBI 15 5 8XC196MC MD MH USER S MANUAL intel When the microcontroller returns from reset the bus controller fetches the CCBs and loads them into the CCRs From this point these CCR bit values define the chip configuration until the mi crocontroller is reset again The CCR bits are described in Figures 15 1 and 15 2 Refer to Chap ter 16 Programming the Nonvolatile Memory for descriptions of the methods for programming the CCBs intel INTERFACING WITH EXTERNAL MEMORY CCRO no direct accesst The chip configuration 0 CCRO register controls powerdown mode bus control signals and internal memory protection Three of its bits combine with two bits of CCR1 to control wait states and bus width 7 0 LOC1 LOCO IRC1 IRCO ALE WR BWO PD Bit Bit 2 Function Number Mnemonic 7 6 LOC1 0 Lock Bits These two bits control read and write access to the OTPROM during normal operation Refer to Controlling Access to the OTPROM During Normal Operation on page 16 4 for details LOC1 LOCO 0 0 read and write protect 0 1 read protect only 1 0 write protect only 1 1 no protection 5 4 IRC1 0 Internal Ready Control These two bits along with IRC2 CCR1 1 and the READY pin determine the number of wait states that can be inserted into the bus cycle While READY is held low wait states are inserted into the bus cycle until the pr
399. imer 2 control T2CONTROL register determines the clock source counting direction and count rate for timer 2 7 0 CE UD M2 M1 MO P2 P1 PO Bit Bit Function Number Mnemonic 7 CE Counter Enable This bit enables or disables the timer From reset the timers are disabled and not free running 0 disables timer 1 enables timer 6 UD Up Down This bit determines the timer counting direction in selected modes see mode bits M2 0 0 count down 1 count up 5 3 M2 0 EPA Clock Direction Mode Bits These bits determine the timer clocking source and direction source M2 1 0 Clock Source Direction Source 0 0 0 Fa i4 UD bit T2CONTROL 6 X 0 1 reserved 0 1 0 reserved 0 1 1 reserved 1 0 0 timer 1 overflow UD bit T2CONTROL 6 1 1 0 timer 1 overflow same as timer 1 1 1 1 reserved 2 0 P2 0 EPA Clock Prescaler Bits These bits determine the clock prescaler value P2 P1 PO Prescaler Resolution 0 0 0 divide by 1 disabled 250 ns 0 0 1 divide by 2 500 ns 0 1 0 divide by 4 1us 0 1 1 divide by 8 2 us 1 0 0 divide by 16 4us 1 0 1 divide by 32 8 us 1 1 0 divide by 64 16 us 1 1 1 reserved Resolution at 16 MHz Use the formula on page 11 6 to calculate the resolution at other frequencies C 55 8XC196MC MD MH USER S MANUAL intel TIMERx TIMERx Address 1F7AH x 1 2 Reset State 1F7EH 0000H This register contains the va
400. in progress 3 0 ACH3 0 A D Channel Number These bits indicate the A D channel number that was used for the conversion Figure 12 6 A D Result AD RESULT Register Read Format 12 9 8XC196MC MD MH USER S MANUAL intel 12 6 DESIGN CONSIDERATIONS This section describes considerations for the external interface circuitry and describes the errors that can occur in any A D converter The datasheet lists the absolute error specification which includes all deviations between the actual conversion process and an ideal converter However because the various components of error are important in many applications the datasheet also lists the specific error components This section describes those components For additional in formation and design techniques consult AP 406 MCS 96 Analog Acquisition Primer order number 270365 Application note AP 406 is also included in the Embedded Microcontrollers handbook 12 6 1 Designing External Interface Circuitry The external interface circuitry to an analog input is highly dependent upon the application and can affect the converter characteristics Factors such as input pin leakage sample capacitor size and multiplexer series resistance from the input pin to the sample capacitor must be considered in the external circuit s design These factors are idealized in Figure 12 7 Sample rox dS 1 1 1 1 1 Internal Re i 1 Rgource 1KQ 2pF O
401. indexed addressing ADD AX 1234H ZERO_REG lt MEM WORD 1234H 5678H ZERO_REG MEM WORD 5678H lt MEM WORD SP SP lt SP 2 3 8 intel PROGRAMMING CONSIDERATIONS 3 8 ASSEMBLY LANGUAGE ADDRESSING MODE SELECTIONS The assembly language simplifies the choice of addressing modes Use these features wherever possible 3 8 4 Direct Addressing The assembly language chooses between direct and zero indexed addressing depending on the memory location of the operand Simply refer to the operand by its symbolic name If the operand is in the lower register file the assembly language chooses a direct reference If the operand is elsewhere in memory it chooses a zero indexed reference 3 3 2 Indexed Addressing The assembly language chooses between short indexed and long indexed addressing depending on the value of the index expression If the value can be expressed in eight bits the assembly lan guage chooses a short indexed reference If the value is greater than eight bits it chooses a long indexed reference 3 4 SOFTWARE STANDARDS AND CONVENTIONS For a software project of any size it is a good idea to develop the program in modules and to es tablish standards that control communication between the modules These standards vary with the needs of the final application However all standards must include some mechanism for passing parameters to procedures and returning results from procedures We recommend
402. indicates successful programming of a location while a low signal indicates a detected error PVER is multiplexed with P2 0 and EPAO PWM1 0 Pulse Width Modulator Outputs These are PWM output pins with high current drive capability PWM1 0 are multiplexed with 6 7 6 RD Read Read signal output to external memory RD is asserted only during external memory reads RD is multiplexed with P5 3 READY Ready Input This active high input along with the chip configuration registers determine the number of wait states inserted into the bus cycle The chip configuration registers selects the maximum number of wait states 0 1 2 3 or infinite that can be inserted into the bus cycle While READY is low wait states are inserted into the bus cycle until the programmed number of wait states is reached If READY is pulled high before the programmed number of wait states is reached no additional wait states will be inserted into the bus cycle READY is multiplexed with P5 6 RESET level sensitive reset input to and open drain system reset output from the microcontroller Either a falling edge on RESET or an internal reset turns ona pull down transistor connected to the RESET pin for 16 state times In the powerdown and idle modes asserting RESET causes the chip to reset and return to normal operating mode The 8XC196MH provides the option of preventing an internal reset from generating
403. ing The interrupt bit is cleared when processing transfers to the corresponding interrupt vector The standard interrupt vector locations are as follows Bit Mnemonic Interrupt Standard Vector COMP2 MC MD EPA Compare Channel 2 200EH COMPS MH EPA Compare Channel 3 200EH EPA2 MC MD EPA Capture Compare Channel 2 200CH 2 EPA Compare Channel 2 200EH COMP1 EPA Compare Channel 1 200AH EPA1 EPA Capture Compare Channel 1 2008H COMPO EPA Compare Channel 0 2006H EPAO EPA Capture Compare Channel 0 2004H AD A D Conversion Complete 2002H OVRTM Overflow Underflow Timer 2000H t Timer 1 and timer 2 can generate the multiplexed overflow underflow interrupt Write to to enable the interrupt sources read PI_PEND to determine which source caused the interrupt Figure 5 10 Interrupt Pending INT_PEND Register 5 21 8XC196MC MD MH USER S MANUAL ntel INT_PEND1 Address Reset State 0012H 00H When hardware detects a pending interrupt it sets the corresponding bit in the interrupt pending INT_PEND or INT_PEND1 registers When the vector is taken the hardware clears the pending bit Software can generate an interrupt by setting the corresponding interrupt pending bit the 8XC196MD the waveform generator and the EPA compare channel 5 generate this interrupt Write to Pl to enable the interrupt s
404. ing WDE makes the watchdog timer inactive but you can activate it by clearing the watchdog register Once the watchdog is activated only a reset can disable it The 8XC196MC and 8XC196MD allow only one reset interval 64K state times This requires your software to interrupt itself every 65 535 state times to reset the watchdog The 8XC196MH allows you to choose a longer interval 13 12 intel MINIMUM HARDWARE CONSIDERATIONS You must write two consecutive bytes to the watchdog register location OAH to clear it For the 8XC196MC and MD the first byte must be 1EH and the second must For the 8XC196MH the first byte must also be 1EH however the second byte can be one of four values The second byte determines the reset interval Table 13 3 Only the values listed in the table are valid an invalid value will not clear the register so the counter will overflow and the watchdog will reset the device We recommend that you disable interrupts before writing to the watchdog register If an interrupt occurs between the two writes the watchdog register will not be cleared Table 13 3 Selecting the Watchdog Reset Interval 8XC196MH only First Byte Second Byte Reset Interval 1EH E1H 64K states 1EH A1H 128K states 2 x 64K 1EH 61H 256K states 4 x 64K 1EH 21H 512K states 8 x 64K NOTE 8XC196MH Only If the WDE bit of CCRI is cleared the watchdog is activated immediately after a system power
405. ing access to the nonvolatile memory See Chapter 16 Programming the Nonvolatile Memory for details 4 1 4 4 Chip Configuration Bytes CCBs The chip configuration bytes CCBs specify the operating environment They specify the bus width bus control mode and wait states They also control powerdown mode the watchdog tim er and nonvolatile memory protection The CCBs are the first bytes fetched from memory when the device leaves the reset state The post reset sequence loads the CCBs into the chip configuration registers CCRs Once they are loaded the CCRs cannot be changed until the next device reset Typically the CCBs are pro grammed once when the user program is compiled and are not redefined during normal operation Chip Configuration Registers and Chip Configuration Bytes on page 15 5 describes the CCBs and CCRs For devices with customer programmable nonvolatile memory the CCBs are loaded for normal operation but the PCCBs are loaded into the CCRs if the device is entering programming modes See Chapter 16 Programming the Nonvolatile Memory for details 4 1 5 Special function Registers SFRs These devices have both memory mapped SFRs and peripheral SFRs The memory mapped SFRs must be accessed using indirect or indexed addressing modes and they cannot be win dowed The peripheral SFRs are physically located in the on chip peripherals and they can be windowed see Windowing on page 4 12 Do not use reserved
406. instruction adds to the program counter the 00111666 breg disp offset between the end of this instruction and the target label effecting the jump The offset NOTE The displacement disp is sign must be in the range of 128 to 127 extended to 16 bits if specified bit 1 then PC lt PC 8 bit disp PSW Flag Settings Z N C V VT ST 8XC196MC MD MH USER S MANUAL intel Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format JC JUMP IF CARRY FLAG IS SET Tests the carry flag If the carry flag is clear control JC cadd passes to the next sequential instruction If the carry flag is set this instruction adds to 11011011 disp the program counter the offset between the end of this instruction and the target label NOTE The displacement disp is sign effecting the jump The offset must be in the extended to 16 bits range of 128 to 127 if C 1 then PC lt PC 8 bit disp PSW Flag Settings Z N C V VT ST JE JUMP IF EQUAL Tests the zero flag If the flag is clear control passes to the next JE cadd sequential instruction If the zero flag is set this instruction adds to the program counter 11011111 disp the offset between the end of this instruction and the target label effecting the jump The NOTE The displacement disp is sign offset must be in the rang
407. iority scheme and timing for standard and peripheral transaction server PTS interrupts It discusses the three special interrupts and the sev en PTS modes four of which are used with the EPA to provide a software serial I O channel for both synchronous and asynchronous transfers and receptions It also explains interrupt program ming and control 5 1 OVERVIEW OF INTERRUPTS The interrupt control circuitry within a microcontroller permits real time events to control pro gram flow When an event generates an interrupt the device suspends the execution of current instructions while it performs some service in response to the interrupt When the interrupt is ser viced program execution resumes at the point where the interrupt occurred An internal periph eral an external signal or an instruction can generate an interrupt request In the simplest case the device receives the request performs the service and returns to the task that was interrupted This microcontroller s flexible interrupt handling system has two main components the pro grammable interrupt controller and the peripheral transaction server PTS The programmable interrupt controller has a hardware priority scheme that can be modified by your software Inter rupts that go through the interrupt controller are serviced by interrupt service routines that you provide The upper and lower interrupt vectors in special purpose memory see Chapter 4 Memory Partitions contain th
408. is manual lists other documents that may be useful and explains how to access the support services we provide to help you com plete your design 1 4 MANUAL CONTENTS This manual contains several chapters and appendixes a glossary and an index This chapter Chapter 1 provides an overview of the manual This section summarizes the contents of the re maining chapters and appendixes The remainder of this chapter describes notational conventions and terminology used throughout the manual provides references to related documentation de scribes customer support services and explains how to access information and assistance Chapter 2 Architectural Overview provides an overview of the device hardware It de scribes the core internal timing internal peripherals and special operating modes Chapter 3 Programming Considerations provides an overview of the instruction set de scribes general standards and conventions and defines the operand types and addressing modes supported by the MCS9 96 microcontroller family For additional information about the instruc tion set see Appendix A Chapter 4 Memory Partitions describes the addressable memory space of the device It describes the memory partitions and explains how to use windows to increase the amount of memory that can be accessed with register direct instructions Chapter 5 Standard and PTS Interrupts describes the interrupt control circuitry priority
409. ister 10 9 D A Buffer Block 10 10 PWM to Analog Conversion Circuitry 10 10 EPA Block Diagtaim iet rre ord eie o e iei 11 2 EPA Timer GCount rs rec eU e Ee de e E UO E ie 11 6 Quadrature Mode Interface enne nnns 11 8 Quadrature Mode Timing and 1 A Single EPA Capture Compare 2 5000110411 10 EPA Simplified Input capture Structure 11 11 Valid EPA Input Events 11 11 Timer 1 Control TICONTROL 11 16 Timer 2 Control T2CONTROL 11 17 EPA Control EPAx CON Registers essen em emen 11 19 EPA Compare Control COMPx CON 11 22 A D Converter Block 12 1 A D Test AD TEST Register esee 12 5 xiii 8XC196MC MD MH USER S MANUAL intel Figure 12 3 12 4 12 5 12 6 12 7 12 8 12 9 12 10 12 11 13 1 13 2 13 3 13 4 13 5 13 6 13 7 13 8 13 9 13 10 13 11 14 1 14 2 14 3 14 4 15 1 15 2 15 3 15 4 15 5 15 6 15 7 15 8 15 9 15 10 15 11 15 12 15 13 15 14 15 15 15 16 15 17 15 18 15 19 15 20
410. isters Updated WG_RELOAD WG_RELOAD WG_RELOAD WG_RELOAD WG_RELOAD WG_COUNTER WG_COUNTER WG_COUNTER WG_COUNTER WG_COUNTER WG_COUNTER WG_RELOAD WG_COMPx WG_COMPx WG_COMPx WG_COMPx WG_COMPx WG OUTPUT WG OUTPUT WG_OUTPUT WG OUTPUT WG OUTPUT WG COUNTER 1 WG COMPx WG OUTPUT WG OUTPUT WG OUTPUT WG_RELOAD OUTPUT WG COUNTER EPA event WG COMPx WG OUTPUT t The OUTPUT register is updated under these conditions if its synchronization bit is set otherwise changes take effect immediately 9 8 intel WAVEFORM GENERATOR 9 3 5 1 Center aligned Modes In the center aligned modes the counter counts down from RELOAD value to 1 then counts back up from 1 to WG RELOAD When you write to the WG RELOAD register WG COUNTER is loaded with the reload value When you set the enable bit in the control reg ister the counter begins counting down and continues counting until it reaches 1 waits one state time and starts counting up until it reaches WG RELOAD At this point WG RELOAD is up dated and WG_COUNTER is reloaded with the updated value so a new reload value takes effect for the next cycle The counter resumes counting down from RELOAD to 1 This produces a symmetrical ascending and descending count illustrated by the triangular wave in Figure 9 4 with a period that is twice the WG RELOAD value Figure 9 5 shows the operation of outputs and interrupts in center aligned modes
411. it interrupt signal is generated when the TI flag is set 7 3 2 Asynchronous Modes Modes 1 2 and 3 Modes 1 2 and 3 are full duplex serial transmit receive modes meaning that they can transmit and receive data simultaneously Mode 1 is the standard 8 bit asynchronous mode used for nor mal serial communications Modes 2 and 3 are 9 bit asynchronous modes typically used for in terprocessor communications see Multiprocessor Communications on page 7 9 In mode 2 the serial port sets an interrupt pending bit only if the ninth data bit is set In mode 3 the serial port always sets an interrupt pending bit upon completion of a data transmission or reception When the serial port is configured for mode 1 2 or 3 writing to SBUFx TX causes the serial port to start transmitting data New data placed in SBUFx TX is transmitted only after the stop bit of the previous data has been sent A falling edge on the RXDx input causes the serial port to begin receiving data if RXDx is enabled Disabling RXDx stops a reception in progress and in hibits further receptions See Programming the Control Register on page 7 10 7 3 2 1 Mode 1 Mode 1 is the standard asynchronous communications mode The data frame used in this mode Figure 7 4 consists of ten bits a start bit 0 eight data bits LSB first and a stop bit 1 If parity is enabled a parity bit is sent instead of the eighth data bit and parity is checked on recep tion 8XC19
412. ive approximation algorithm 12 4 register SAR 12 4 terminal based characteristic 12 18 threshold detection modes 12 5 INDEX transfer function 12 15 12 18 zero offset adjustment 12 3 12 5 zero offset error 12 16 See also port 0 A D result register read 12 9 C 7 A D result register write 12 6 C 8 A D scan mode See PTS A D test register 12 5 C 9 A D time register 12 7 C 10 AC timing specifications 15 31 15 34 symbol explanations 15 33 Accumulator RALU 2 5 ACH13 0 B 13 AD COMMAND C 68 AD RESULT 12 9 C 68 AD TEST C 68 AD TIME C 68 AD15 0 B 13 ADD instruction A 2 A 7 A 41 A 42 A 47 A 52 ADDB instruction A 2 A 7 A 42 A 43 A 47 A 52 ADDC instruction A 2 A 7 A 44 A 47 A 52 ADDCB instruction A 2 A 8 A 44 A 47 A 52 Address space map 4 2 See also memory partitions Address valid strobe mode ALE ADV comparison 15 27 example system 15 28 15 29 signals 15 27 Address valid with write strobe mode example system 15 31 signals 15 30 Address data bus 2 6 multiplexing 15 10 15 17 Addressing modes 3 5 3 6 A 6 ADV B 13 AINC 16 12 B 14 ALE B 14 idle powerdown reset status B 23 B 25 Analog outputs generating 10 10 Analog to digital converter See A D converter Index 1 8XC196MC MD MH USER S MANUAL AND instruction A 2 A 8 A 41 A 42 A 48 A 53 ANDB instruction A 2 A 8 A 9 A 42 A 43 A 48 53 ANGND 12 5 13 1 B 14 ApBUILDER sof
413. ived Parity Error Received Bit 8 RPE is set if parity is disabled SPx_CON 2 0 and the ninth data bit received is high RB8 is set if parity is enabled SPx CON 2 1 and a parity error occurred Reading SPx_STATUS clears this bit 6 Receive Interrupt This bit is set when the last data bit is sampled Reading SPx_STATUS clears this bit 5 Transmit Interrupt This bit is set at the beginning of the stop bit transmission Reading SPx_STATUS clears this bit 4 FE Framing Error This bit is set if a stop bit is not found within the appropriate period of time Reading SPx_STATUS clears this bit 3 TXE SBUFx TX Empty This bit is set if the transmit buffer is empty and ready to accept up to two bytes It is cleared when a byte is written to SBUFx TX 2 OE Overrun Error This bit is set if data in the receive shift register is loaded into SBUFx RX before the previous bit is read Reading SPx STATUS clears this bit 1 0 Reserved for compatibility with future devices write zeros to these bits Figure 7 8 Serial Port Status SPx STATUS Register 7 15 8XC196MC MD MH USER S MANUAL intel The receiver checks for a valid stop bit Unless a stop bit is found within the appropriate time the framing error FE bit in the SPx STATUS register is set When the stop bit is detected the data in the receive shift register is loaded into SBUFx RX and the receive interrupt RI flag is
414. l Table 15 1 External Memory Interface Signals Continued Signal Name PortPin Type Description ALE P5 0 Address Latch Enable This active high output signal is asserted only during external memory cycles ALE signals the start of an external bus cycle and indicates that valid address information is available on the system address data bus ALE differs from ADV in that it does not remain active during the entire bus cycle An external latch can use this signal to demultiplex the address from the address data bus BHE P5 5 Byte High Enable During 16 bit bus cycles this active low output signal is asserted for word and high byte reads and writes to external memory BHE indicates that valid data is being transferred over the upper half of the System data bus Use BHE in conjunction with ADO to determine which memory byte is being transferred over the system bus BHE ADO Accessed 0 0 both bytes 0 1 high byte only 1 0 low byte only t The chip configuration register 0 CCRO determines whether this pin functions as BHE WRH CCRO 2 1 selects BHE CCRO 2 0 selects WRH BUSWIDTH P5 7 Bus Width Two chip configuration register bits CCRO 1 and CCR1 2 along with the BUSWIDTH pin control the data bus width When both CCR bits are set the BUSWIDTH signal selects the external data bus width When only one CCR bit is set the bus width is fixed at either 16 or 8 bits
415. l 2 EPA Compare Channel 2 EPA Compare Channel 1 EPA Capture Compare Channel 1 EPA Compare Channel 0 EPA Capture Compare Channel 0 A D Conversion Complete Overflow Underflow Timer Standard Vector 200EH 200EH 200CH 200EH 200AH 2008H 2006H 2004H 2002H 2000H 7 0 MC MD COMP2 EPA2 1 EPA1 COMPO EPAO AD OVRTM 7 0 MH COMP2 1 EPA1 COMPO EPAO AD OVRTM Bit Number Function 7 0 Any set bit indicates that the corresponding interrupt is pending The interrupt bit is cleared C 27 8XC196MC MD MH USER S MANUAL INT_PEND1 ntel INT_PEND1 Address Reset State 0012H 00H When hardware detects a pending interrupt it sets the corresponding bit in the interrupt pending INT_PEND or INT_PEND1 registers When the vector is taken the hardware clears the pending bit Software can generate an interrupt by setting the corresponding interrupt pending bit H On the 8XC196MD the waveform generator and the EPA compare channel 5 can generate this interrupt Write to Pl MASK to enable the interrupt sources read PEND to determine which source caused the interrupt On the 8XC196MC the waveform generator is the sole source for this interrupt SIO 0 and SIO 1 can generate this interrupt Write to MASK to enable the interrupt Sources read PEND to determine which source caused the interrupt 7 0
416. l Port Interrupts 7 14 vi intel CONTENTS 7 4 5 Determining Serial Port 4 7 15 CHAPTER 8 FREQUENCY GENERATOR 8 1 FUNCTIONAL OVERVIEW Er rc P 8 1 8 2 PROGRAMMING THE FREQUENCY GENERATOR 8 3 8 2 1 Configuring the Output tente ere ene Tee de ch 8 3 8 2 2 Programming the Frequency 8 3 8 2 3 Determining the Current Value of the Down counter 0000011 8 4 8 3 RETIA IB eae te eae 8 4 CHAPTER 9 WAVEFORM GENERATOR 9 1 WAVEFORM GENERATOR FUNCTIONAL 9 1 9 2 WAVEFORM GENERATOR SIGNALS AND 9 3 9 3 WAVEFORM GENERATOR 9 4 9 3 1 Timebase Generator 9 4 9 3 2 Phase Driver Channels 2 9 5 9 3 3 Control and Protection Circuitry 9 5 9 3 4 Register Buffering and Synchronization 9 6 9 3 5 Operating Modes 9 7 9 3 5 1 Center aligned Modes sees eene 9 3 5 2 Edge Aligned Modes te b n tb ente 9 10 9 4 PROGRAMMING THE WAVEFORM
417. l matching and random noise should be considered Fortunately one absolute error specification listed in datasheets de scribes the total of all deviations between the actual conversion process and an ideal converter However the various components of error are important in many applications An unavoidable error results from the conversion of a continuous voltage to an integer digital rep resentation This error called quantizing error is always 0 5 LSB Quantizing error is the only error seen in a perfect A D converter and it is obviously present in actual converters Figure 12 9 shows the transfer function for an ideal 3 bit A D converter 12 14 intel ANALOG TO DIGITAL CONVERTER FINAL CODE TRANSITION OCCURS WHEN THE APPLIED VOLTAGE IS EQUAL TO Vref 1 5 LSB ACTUAL CHARACTERISTIC OF AN IDEAL A D CONVERTER THE VOLTAGE CHANGE BETWEEN THE ADJACENT CODE TRANSITIONS THE CODE WIDTH IS 1 LSB 3009 LNdLNO FIRST CODE TRANSITION OCCURS WHEN THE APPLIED VOLTAGE IS EQUAL TO 1 2 LSB 1 2 1 2 3 4 5 6 6 1 2 7 8 INPUT VOLTAGE LSBs A0083 01 Figure 12 9 Ideal A D Conversion Characteristic Note that the ideal characteristic possesses unique qualities its first code transition occurs when the input voltage is 0 5 LSB its full scale code transition occurs when the input voltage equals the full scale reference voltage minus 1 5 LSB Va 1 5LSB and
418. l the external device raises the READY signal Each wait state adds one state time 2T 11 to the bus cycle After reset and until CCB1 is fetched the bus controller always inserts three wait states into bus cycles Then until P5 6 has been configured to operate as the READY signal the internal ready control bits IRC2 0 control the wait states 15 17 8XC196MC MD MH USER S MANUAL intel After the CCB1 fetch the internal ready control circuitry allows slow external memory devices to increase the length of the read and write bus cycles If the external memory device is not ready for access it pulls the READY signal low and holds it low until it is ready to complete the oper ation at which time it releases READY While READY is low the bus controller inserts wait states into the bus cycle The internal ready control bits CCRO 5 4 and CCR1 1 shown in Figures 15 1 15 2 define the maximum number of wait states 0 1 2 3 or infinite that will be inserted into the bus cycle While READY is low wait states are inserted into the bus cycle until the programmed number of wait states is reached If READY is pulled high before the programmed number of wait states is reached no additional wait states will be inserted into the bus cycle If you choose the infinite wait states option you must keep P5 6 configured as the READY signal Also be sure to add external hardware to count wait states and pull READY high within a
419. lag 01000000b get next byte done done for now flag 00100000b set get bit flag done flag 00H clear all flags 8 9 intel 9 Waveform Generator intel CHAPTER 9 WAVEFORM GENERATOR A waveform generator simplifies the task of generating synchronized pulse width modulated PWM outputs This waveform generator is optimized for motion control applications such as driving 3 phase AC induction motors 3 phase DC brushless motors or 4 phase stepping motors The waveform generator can produce three independent pairs of complementary PWM outputs that share a common carrier period dead time and operating mode Once it is initialized the waveform generator operates without CPU intervention unless you need to change a duty cycle This chapter describes the waveform generator and explains how to configure it For detailed de scriptions of the signals discussed in this chapter refer to Appendix B Signal Descriptions For additional information and application examples consult AP 483 Application Examples Using the 8XC 196MC MD Microcontroller order number 272282 9 1 WAVEFORM GENERATOR FUNCTIONAL OVERVIEW The waveform generator Figure 9 1 has three main parts a timebase generator phase driver channels and control circuitry The timebase generator establishes the carrier period the phase driver channels determine the duty cycle and the control circuitry determines the operating mode and controls interrupt g
420. le event 1 function always enabled 2 WGR Waveform Generator Reload A D Conversion AD The function of this bit depends on the EPA channel For EPA capture compare channels 0 2 4 The WGR bit allows you to use the EPA activities to cause the reload of new values in the waveform generator 0 action 1 enables waveform generator reload For EPA capture compare channels 1 3 5 The AD bit allows you to use the EPA activities to start an A D conversion that has been previously set up in the A D control registers 0 causes no A D action 1 starts an A D conversion on an output compare 11 20 Figure 11 10 EPA Control EPAx CON Registers Continued intel EVENT PROCESSOR ARRAY EPA EPAx CON Continued Address Table 11 3 on page 11 3 x 0 1 8XC196MH Reset State 00H x 0 3 8XC196MC x 0 5 8XC196MD The EPA control EPAx CON registers control the functions of their assigned capture compare channels 7 0 x 0 2 4 TB CE M1 0 RE WGR ROT ON RT 7 0 x 1 3 5 TB CE M1 0 RE AD ROT ON RT Bit Bit Function Number Mnemonic 1 ROT Reset Opposite Timer Controls different functions for capture and compare modes In Capture Mode 0 causes no action 1 resets the opposite timer In Compare Mode Selects the timer that is to be reset if the RT bit is set 0 selects the reference timer for possible reset 1 se
421. le printed documents please or der the literature catalog order number 210621 To order documents please call the Intel literature center for your area telephone numbers are listed on page 1 11 Intel s ApBUILDER software hypertext manuals and datasheets and electronic versions of ap plication notes and code examples are also available from the BBS see Bulletin Board System BBS on page 1 9 New information is available first from FaxBack and the BBS Refer to Electronic Support Systems on page 1 8 for details 8XC196MC MD MH USER S MANUAL intel Table 1 1 Handbooks and Product Information Title and Description Order Number Intel Embedded Quick Reference Guide 272439 Solutions for Embedded Applications Guide 240691 Data on Demand fact sheet 240952 Data on Demand annual subscription 6 issues Windows version 240897 Complete set of Intel handbooks on CD ROM Handbook Set handbooks and product overview 231003 Complete set of Intel s product line handbooks Contains datasheets application notes article reprints and other design information on microprocessors periph erals embedded controllers memory components single board computers microcommunications software development tools and operating systems Automotive Products 231792 Application notes and article reprints on topics including the MCS 51 and MCS 96 microcontrollers Documents in this handbook discuss hardware and soft
422. le uses new command and stores the conversion results at the new address 5 PTSCOUNT is decremented and the CPU returns to regular program execution When the next A D conversion complete interrupt occurs the cycle repeats When PTSCOUNT reaches zero hardware clears the corresponding PTSSEL bit and sets the PTSSRV bit which requests the end of PTS interrupt 5 6 5 2 A D Scan Mode Example 1 The command data table shown in Table 5 8 sets up a series of A D conversions beginning with channel 7 and ending with channel 4 Each table entry is a word two bytes Table 5 9 shows the corresponding PTSCB Software starts a conversion on channel 7 Upon completion of the conversion the A D conver sion complete interrupt initiates the A D scan mode routine Step 1 stores the channel 6 command in a temporary location and increments PTSPTRI to 3002H Step 2 stores the result of the channel 7 conversion in location 3002H and increments to 3004H Step 3 loads the channel 6 command from the temporary location into the AD COMMAND register to start the next con 5 85 8XC196MC MD MH USER S MANUAL intel version Step 4 updates PTSPTR1 PTSPTRI now points to 3004H and step 5 decrements PTSCOUNT to 3 The next cycle begins by storing the channel 5 command in the temporary lo cation During the last cycle PITSCOUNT 1 the dummy command is loaded into the COMMAND register and no conversion is performed PISCOUNT is decrement
423. lects the opposite timer for possible reset The TB bit bit 7 selects which is the reference timer and which is the opposite timer 0 ON RT Overwrite New Reset Timer The ON RT bit functions as overwrite new in capture mode and reset timer in compare mode In Capture Mode ON An overrun error is generated when an input capture occurs while the event time register EPAx TIME and its buffer are both full When an overrun occurs the ON bit determines whether old data is overwritten or new data is ignored 0 ignores new data 1 overwrites old data in the buffer In Compare Mode RT 0 disables the reset function 1 resets the ROT selected timer Figure 11 10 EPA Control EPAx_CON Registers Continued 11 21 8XC196MC MD MH USER S MANUAL intel 11 5 4 Programming the Compare only Channels To program a compare event you must first write to the COMPx CON register Figure 11 11 to configure the compare only channel and then load the event time into COMPx TIME COMPx CON has the same bits and settings as EPAx CON COMPx TIME is functionally iden tical to EPAx TIME COMPx CON Address See Table 11 3 on x 0 3 8XC196MC MH page 11 3 x 0 5 8XC196MD Reset State 00H The EPA compare control registers determine the function of the EPA compare channels 7 0 x 0 2 4 TB CE M1 0 RE WGR ROT RT 7 0 x 1 3 5 TB CE M1 0 RE AD RO
424. lent C Programming Language Equivalent BYTE BYTE unsigned char SHORT INTEGER BYTE char WORD WORD unsigned int INTEGER WORD int DOUBLE WORD LONG unsigned long LONG INTEGER LONG long 3 1 1 BIT Operands A BIT is a single bit variable that can have the Boolean values true and false The architec ture requires that BITs be addressed as components of BYTEs or WORDs It does not support the direct addressing of BITs 3 1 2 BYTE Operands A BYTE is an unsigned 8 bit variable that can take on values from 0 through 255 28 1 Arith metic and relational operators can be applied to BYTE operands but the result must be interpret ed in modulo 256 arithmetic Logical operations on BYTEs are applied bitwise Bits within BYTEs are labeled from 0 to 7 bit 0 is the least significant bit There are no alignment restric tions for BYTEs so they may be placed anywhere in the address space 3 1 SHORT INTEGER Operands A SHORT INTEGER is an 8 bit signed variable that can take on values from 128 27 through 127 27 1 Arithmetic operations that generate results outside the range of a SHORT INTEGER set the overflow flags in the processor status word PSW The numeric result is the same as the result of the equivalent operation on BYTE variables There are no alignment restric tions on SHORT INTEGERs so they may be placed anywhere in the address space 3 1 4 WORD Operands A WORD is an unsigned 16 bit variable that can
425. lock signal Up to 16 bits may be 5 37 8XC196MC MD MH USER S MANUAL intel transmitted or received including the parity and stop bits in the asynchronous modes The serial I O modes require two PTS control blocks to configure all options see Figures 5 19 and 5 20 These blocks need not be contiguous but they must each be located in register RAM on a quad word boundary See AP 483 Application Examples Using the 8XC196MC MD Microcontroller for application examples with code PTS Serial I O Mode Control Block 1 8XC196MC MD The PTS control block 1 contains pointers to both the second PTS control block PTSVEC and the EPA time register that sets the baud rate EPAREG It also contains a 16 bit value that is used to calculate the baud rate a control register PISCON and a consecutive PTS cycle count PTSCOUNT 15 8 PTSVEC H SIO PTSCB2 Base Address Pointer high byte 7 0 PTSVEC L SIO PTSCB2 Base Address Pointer low byte 15 8 BAUD H Baud Value high byte 7 0 BAUD L Baud Value low byte 15 8 EPAREG H EPA Time Register Address high byte 7 0 EPAREG L EPA Time Register Address low byte 7 0 PTSCON M2 M1 MO SA1 0 0 SAO MAJ 7 0 PTSCOUNT Consecutive PTS Cycles Register Location Function PTSVEC PTSCB1 6 SIO PTSCB2 Base Address Pointer This register contains the base address of the second PTS control block for serial I
426. long with IRC2 CCR1 1 and the READY pin determine the number of wait states that can be inserted into the bus cycle While READY is held low wait states are inserted into the bus cycle until the programmed number of wait states is reached If READY is pulled high before the programmed number of wait states is reached no additional wait states will be inserted into the bus cycle IRC2 IRC1 IRCO zero wait states illegal illegal wait state two wait states three wait states infinite If you choose the infinite wait states option you must keep P5 6 configured as the READY signal Also be sure to add external hardware to count wait states and pull READY high within a specified time Otherwise a defective external device could tie up the address data bus indefinitely ares SEOs The CCRs are loaded with the contents of the chip configuration bytes CCBs after reset unless the microcontroller is entering programming modes see Entering Programming Modes on page 16 13 in which case the programming chip configuration bytes PCCBs are used The CCBs reside in nonvolatile memory at addresses 2018H CCBO and 201AH CCB1 8XC196MC MD MH USER S MANUAL intel CCRO CCRO Continued no direct accesst The chip configuration 0 CCRO register controls powerdown mode bus control signals and internal memory protection Three of its bits combine with two bit
427. low signals are designated by a pound symbol suffix active high signals have no suffix To assert RD is to drive it low to assert ALE is to drive it high to deassert RD is to drive it high to deassert ALE is to drive it low The terms clear and set refer to the value of a bit or the act of giving it a value If a bit is clear its value is 0 clearing a bit gives it a 0 value If a bit is set its value is 1 setting a bit gives it a 1 value Instruction mnemonics are shown in upper case to avoid confusion In general you may use either upper case or lower case when programming Consult the manual for your assembler or compiler to determine its specific requirements Italics identify variables and introduce new terminology The context in which italics are used distinguishes between the two possible meanings Variables in registers and signal names are commonly represented by x and y where x represents the first variable and y represents the second variable For example in register Px_MODE y x represents the variable that identifies the specific port associated with the register and y represents the register bit variable 7 0 or 15 0 Variables must be replaced with the correct values when configuring or programming registers or identifying signals 8XC196MC MD MH USER S MANUAL intel numbers register bits register names reserved bits signal names Hexadecimal numbers are represented
428. lue of timer x This register can be written allowing timer x to be initialized to a value other than zero 15 0 Timer Value Bit Number Function 15 0 Timer Value Read the current timer x value from this register or write a new timer x value to this register C 56 intel REGISTERS USFR USFR Address 1FF6H Reset State MC MD 02H Reset State MH XXH The unerasable PROM USFR register contains two bits that disable external fetches of data and instructions and another that detects a failed oscillator These bits can be programmed but cannot be erased WARNING These bits can be programmed but can never be erased Programming these bits makes dynamic failure analysis impossible For this reason devices with programmed UPROM bits cannot be returned to Intel for failure analysis 7 0 DEI DED Bit Bit Number Mnemonic Function 7 4 Reserved for compatibility with future devices write zeros to these bits 3 DEI Disable External Instruction Fetch Setting this bit prevents the bus controller from executing external instruction fetches Any attempt to load an external address initiates a reset 2 DED Disable External Data Fetch Setting this bit prevents the bus controller from executing external data reads and writes Any attempt to access data through the bus controller initiates a reset 1 0 Reserved for com
429. m ory The automatic reset also gives extra protection against runaway code Programming the DED bit prevents the bus controller from executing external data reads and writes An attempt to access data through the bus controller causes the device to reset itself Set ting this bit disables ROM dump mode To program these bits write the correct value to the location shown in Table 16 4 using slave pro gramming mode During normal operation you can determine the values of these bits by reading the UPROM special function register Figure 16 1 16 6 intel PROGRAMMING THE NONVOLATILE MEMORY USFR erased The unerasable PROM USFR register contains two bits that disable external fetches of data and instructions and another that detects a failed oscillator These bits can be programmed but cannot be WARNING These bits can be programmed but can never be erased Programming these bits makes dynamic failure analysis impossible For this reason devices with programmed UPROM bits cannot be returned to Intel for failure analysis Address 1FF6H Reset State MC MD 02H Reset State MH XXH 7 0 DED Bit Bit Number Mnemonic Function 7 4 Reserved for compatibility with future devices write zeros to these bits 3 Disable External Instruction Fetch Setting this bit prevents the bus controller from executing external instruction fetches
430. mask bits in the interrupt mask registers and their servicing can be disabled by the global interrupt enable bit Each maskable interrupt can be assigned to the PTS for processing The property of successive approximation converters which guarantees that increasing input voltages produce adjacent codes of increasing value and that decreasing input voltages produce adjacent codes of decreasing value In other words a converter is monotonic if every code change represents an input voltage change in the same direction Large differ ential nonlinearity errors can cause the converter to exhibit nonmonotonic behavior Most significant bit of a byte or most significant byte of a word A field effect transistor with an n type conducting path channel Semiconductor material with introduced impurities doping causing it to have an excess of negatively charged carriers An A D converter has no missing codes if for every output code there is a unique input voltage range which produces that code only Large differential nonlinearity errors can cause the converter to miss codes The maximum deviation of code transitions of the terminal based characteristic from corre sponding code transitions of the ideal characteristic Glossary 5 8XC196MC MD MH USER S MANUAL nonmaskable interrupts nonvolatile memory npn transistor off isolation OTPROM p channel FET p type material PC PCCBs PIC prioritized in
431. mber Mnemonic 3 RE Re enable Re enable applies to the compare mode only It allows a compare event to continue to execute each time the event time register EPAx_TIME matches the reference timer rather than only upon the first time match 0 compare function is disabled after a single event 1 compare function always enabled 2 WGR Waveform Generator Reload A D Conversion AD The function of this bit depends on the EPA channel For EPA capture compare channels 0 2 4 The WGR bit allows you to use the EPA activities to cause the reload of new values in the waveform generator 0 no action 1 enables waveform generator reload For EPA capture compare channels 1 3 5 The AD bit allows you to use the EPA activities to start an A D conversion that has been previously set up in the A D control registers 0 causes A D action 1 starts an A D conversion on an output compare 1 ROT Reset Opposite Timer Controls different functions for capture and compare modes In Capture Mode 0 causes no action 1 resets the opposite timer In Compare Mode Selects the timer that is to be reset if the RT bit is set 0 selects the reference timer for possible reset 1 selects the opposite timer for possible reset The TB bit bit 7 selects which is the reference timer and which is the opposite timer 8XC196MC MD MH USER S MANUAL intel EPAx_CON Continued
432. me the value is reloaded from the register Each load toggles the D flip flop producing the 50 duty cycle output The count register FREQ reflects the current value of the down counter Table 8 1 describes the frequency generator s output signal and Table 8 2 describes the control and status registers Table 8 1 Frequency Generator Signal Port Frequency Frequency Pin Generator Generator Description Signal Signal Type P7 7 FREQOUT Frequency Generator Output This signal carries the output of the frequency generator Table 8 2 Frequency Generator Control and Status Registers Mnemonic Address Description FREQ_GEN 1FB8H Frequency The frequency register holds a programmed value that determines the output frequency This value is reloaded into the down counter each time the counter reaches 0 FREQ_CNT 1FBAH Count The read only counter register reflects the current counter value P7_DIR 1FD3H Port 7 Direction Bit 7 controls the direction of P7 7 FREQOUT Clear this bit to configure FREQOUT as a complementary output P7_MODE 1FD1H Port 7 Mode Bit 7 controls the mode general purpose or special function signal of P7 7 FREQOUT Set this bit to configure the pin for its FREQOUT function P7_PIN 1FD7H Port 7 Input Bit 7 reflects the current state of P7 7 FREQOUT regardless of its configu ration P7_REG 1FD5H Port 7 Data Output Bit 7 contains data to be driven out by
433. mming cycles restore PSW WSR and INT MASKs Figure 16 15 Run time Programming Code Example 16 33 intel Instruction Set Reference APPENDIX A INSTRUCTION SET REFERENCE This appendix provides reference information for the instruction set of the family of MCS 96 microcontrollers It defines the processor status word PSW flags describes each instruction shows the relationships between instructions and PSW flags and shows hexadecimal opcodes instruction lengths and execution times It includes the following tables Table A 1 on page A 2 is a map of the opcodes Table A 2 on page A 4 defines the processor status word PSW flags Table A 3 on page A 5 shows the effect of the PSW flags or a specified register bit on conditional jump instructions Table 4 on page 5 defines the symbols used in Table A 6 Table A 5 on page A 6 defines the variables used in Table A 6 to represent instruction operands Table A 6 beginning on page 7 lists the instructions alphabetically describes each of them and shows the effect of each instruction on the PSW flags Table A 7 beginning on page A 41 lists the instruction opcodes in hexadecimal order along with the corresponding instruction mnemonics Table A 8 on page A 47 lists instruction lengths and opcodes for each applicable addressing mode Table A 9 on page A 52 lists instruction execution times expressed in state times NOTE The symbol prefixes an immediate
434. mode 4 output FxTAL1 VALUE 5 Baud Rate x4 t For mode 0 receptions the BAUD_VALUE must be 0002H or greater Otherwise the resulting data in the receive shift register will be incorrect C 50 intel REGISTERS SPx CON SPx CON Address 1F83H 1 8 x 0 1 8 196 Reset State 00H The serial port control SPx_CON register selects the communications mode and enables or disables the receiver parity checking and nine bit data transmission 7 0 8XC196MH M2 DIR PAR TB8 REN PEN 1 MO Bit Bit Number Mnemonic Funcugn M2 See description for bits 0 and 1 DIR Synchronous Clock Direction This bit determines the direction of the clock during synchronous mode 0 output 1 input 5 PAR Parity Selection Bit This bit selects even or odd parity 0 even parity 1 odd parity 4 TB8 Transmit Ninth Data Bit This is the ninth data bit that will be transmitted in mode 2 or 3 This bit is cleared after each transmission so it must be set before SBUFx_TX is written When parity is enabled SPx_CON 2 1 this bit takes on the even parity value 3 REN Receive Enable Setting this bit enables receptions When this bit is set a falling edge on the RXDx pin starts a reception in mode 1 2 or 3 In mode 0 this bit must be clear for transmission to begin and must be set for reception to begin Clearing this bit stops a reception in
435. modes WG RELOAD 16 bit WG RELOAD value 2 WG_COMPx WG COMPx 16 bit WG_COMPx value x WG RELOAD 15 0 Reload Bit Number Function 15 0 Reload C 67 8XC196MC MD MH USER S MANUAL WSR intel WSR Address Reset State 0014H 00H The window selection register WSR maps sections of RAM into the top of the lower register file in 32 64 or 128 byte increments PUSHA saves this register on the stack and POPA restores it 7 0 W6 W5 WA W3 W2 W1 WO Bit Bit Function Number Mnemonic uncuo 7 Reserved for compatibility with future devices write zero to this bit 6 0 W6 0 Window Selection These bits specify the window size and number Table C 12 shows the WSR settings and direct addresses for windowable SFRs Table C 12 WSR Settings and Direct Addresses for Windowable SFRs 32 byte Windows 64 byte Windows 128 byte Windows 00 0 0 00 0 0080 0 Location Direct Direct Direct WSR Address WSR Address WSA Address AD_COMMAND 1FACH 7DH 00 00 1 00 AD_RESULT 1FAAH 7DH 00 00 1 00 AD TEST 1FAEH 7DH 00 00 1 00 AD TIME 1FAFH 7DH 00 00 1 OOAFH _ 1F58H 7AH 00 8 3DH 00D8H 1EH 00D8H C
436. ms with EA tied inactive have idle time between external bus cycles When the address da ta bus is idle you can use the ports for I O Like port 5 these ports use standard CMOS input buffers However ports 3 and 4 must be configured entirely as complementary or open drain ports their pins cannot be configured individually Systems with EA tied active cannot use ports 3 and 4 as standard I O when EA is active these ports will function only as the address data bus Table 6 11 lists the port 3 and 4 pins with their special function signals and associated peripher als Table 6 12 lists the registers that affect the function and indicate the status of ports 3 and 4 Table 6 11 Ports 3 and 4 Pins Special function Special function Port Pins Signal s Signal Type Associated Peripheral m AD7 0 VO Address data bus low byte P PBUS7 0 VO Programming bus low byte PAZO AD15 8 VO Address data bus high byte PBUS15 8 VO Programming bus high byte Table 6 12 Ports 3 and 4 Control and Status Registers Mnemonic Address Description P3 PIN 1FFEH Port x Input P4 PIN 1FFFH Each bit of Px PIN reflects the current state of the corresponding pin regardless of the pin configuration P3 REG 1FFCH Port x Data Output P4 REG 1FFDH Each bit of Px REG contains data to be driven out by the corresponding pin When the device requires access to external memory it takes control of the port and d
437. n The Output Polarities column shows the output polarities The drawings show a duty cycle of about 15 and for these cases the high portion of the waveforms increases as dead time increases Table 9 5 Output Configuration Output Values Output Polarities PHx 2 PHx 1 PHx 0 WG x WGx WGodt 1 0 0 Low Low Always Low Always Low 1 0 1 Low WG_EVEN Always Low 1 1 0 WG ODD Low Always Low 1 1 1 WG ODD WG EVEN NOTE This table assumes active high outputs 1 1 intel WAVEFORM GENERATOR WG OUTPUT Waveform Generator euin eset State The waveform generator output configuration WG_OUTPUT register controls the configuration of the waveform generator and PWM module pins Both the waveform generator and the PWM module share pins with port 6 Having these control bits in a single register enables you to configure all port 6 pins with a single write to WG_OUTPUT 15 8 1 SYNC PE7 PE6 PH3 2 PH2 2 PH1 2 7 0 P7 PH3 1 PH3 0 PH2 1 PH2 0 PH1 1 PH1 0 Bit Bit i Number Mnemonic Function 15 OP1 Output Polarity Selects the output polarity for negative phase outputs WG1 WG2 and WG3 0 active low outputs 1 active high outputs 14 OPO Output Polarity Selects the output polarity for positive phase outputs WG1 WG2 and WG3 0 active low outputs 1 active high outputs 13
438. n Figure 11 6 If enabled an interrupt is gen erated If a second event occurs before the CPU reads the first timer value in EPAx TIME the current timer value is loaded into the buffer and held there After the CPU reads the EPAx TIME register the contents of the capture buffer are automatically transferred into EPAx TIME and the EPA interrupt pending bit is set 11 10 intel EVENT PROCESSOR ARRAY EPA TIMERx Event Occurs at EPA Pin Capture Buffer EPA Interrupt Pending Bit Set EPAx TIME Read out Time Value A2458 02 Figure 11 6 EPA Simplified Input capture Structure If a third event occurs before the CPU reads the event time register the overwrite bit EPAx 0 determines how the EPA will handle the event If the bit is clear the EPA ignores the third event If the bit is set the third event time overwrites the second event time in the capture buffer Table 11 5 summarizes the possible actions when a valid event occurs NOTE In order for an event to be captured the signal must be stable for at least two state times both before and after the transition occurs Figure 11 7 Event 1 2 State 2 State Times Times Event 2 2 State 2 State Times Times A3130 01 Figure 11 7 Valid EPA Input Events 11 11 8XC196MC MD MH USER S MANUAL intel Table 11 5 Action Taken When a Valid Edge Occurs Status of PAD CONG Capture Buffer
439. n either auto or slave programming mode Once the security key is programmed you must provide a matching key to gain access to any programming mode For auto programming and ROM dump modes a matching security key must reside in ex ternal memory For slave programming mode you must program a matching security key into the appropriate OTPROM locations with the program word command The locations are not ac tually programmed but the data is compared to the internal security key WARNING If you leave the internal security key locations unprogrammed filled with FFFFH an unauthorized person could gain access to the OTPROM by using an external EPROM with an unprogrammed external security key location or by using slave programming mode 16 3 2 Controlling Fetches from External Memory Two UPROM bits disable external instruction fetches and external data fetches If you program the UPROM bits an attempt to fetch data or instructions from external memory causes a device reset You can program the UPROM bits using slave or UPROM 8XC196MH only program ming mode Programming the DEI bit prevents the bus controller from executing external instruction fetches An attempt to load the slave program counter with an external address causes the device to reset itself Because the slave program counter can be as much as four bytes ahead of the CPU program counter the bus controller might prevent code execution from the last four bytes of internal me
440. n individual signal is represented by the signal name followed by a number For example the EPA signals are named EPAO EPA1 EPA2 etc Port pins are represented by the port abbre viation a period and the pin number e g P1 0 P1 1 a range of pins is represented by Px y z e g P1 4 0 represents five port pins P1 4 P1 3 P1 2 P1 1 P1 0 A pound symbol appended to a signal name identifies an active low signal intel GUIDE TO THIS MANUAL units of measure The following abbreviations are used to represent units of measure A amps amperes DCV direct current volts Kbytes kilobytes kHz kilohertz kilo ohms mA milliamps milliamperes Mbytes megabytes MHz megahertz ms milliseconds mW milliwatts ns nanoseconds pF picofarads W watts V volts microamps microamperes microfarads us microseconds uW microwatts X Uppercase X no italics represents an unknown value or an irrelevant don t care state or condition The value may be either binary or hexadecimal depending on the context For example 2XAFH hex indicates that bits 11 8 are unknown 10XXB binary indicates that the two least significant bits are unknown 1 3 RELATED DOCUMENTS The tables in this section list additional documents that you may find useful in designing systems incorporating MCS 96 microcontrollers These are not comprehensive lists but are a representa tive sample of relevant documents For a complete list of availab
441. n internal reset turns on a pull down transistor connected to the RESET pin for 16 state times In the powerdown and idle modes asserting RESET causes the chip to reset and return to normal operating mode The 8XC196MH provides the option of preventing an internal reset from generating a reset on the external pin see Resetting the Device on page 13 8 After a device reset the first instruction fetch is from 2080H Voc PWR Digital Supply Voltage Connect each Vec pin to the digital supply voltage Type Description Vop PWR Programming Voltage During programming the V pin is typically at 12 5 V voltage Exceeding the maximum Vpp voltage specification can damage the device Vpp also causes the device to exit powerdown mode when it is driven low for at least 50 ns Use this method to exit powerdown only when using an external clock source because it enables the internal phase clocks but not the internal oscillator On devices with no internal nonvolatile memory connect Vpp to Voc Veer PWR Reference Voltage for the A D Converter This pin also supplies operating voltage to both the analog portion of the A D converter and the logic used to read port 0 also port 1 in the 8XC196MC 8XC196MD Vss GND Digital Circuit Ground Connect each Vss pin to ground through the lowest possible impedance path 13 1 8XC196MC MD MH USER S MANUAL intel Table 13 1 Minimum Required Signals
442. n transmit and receive data simultaneously The receiver is buffered so the reception of a second byte can begin before the first byte is read The transmitter is also buffered allowing continuous transmis sions The SIO port has two channels channels 0 and 1 with identical signals and registers See Chapter 7 Serial I O SIO Port for details 8XC196MC MD MH USER S MANUAL intel 2 5 3 Event Processor Array EPA and Timer Counters The event processor array EPA performs high speed input and output functions associated with its timer counters In the input mode the EPA monitors an input for signal transitions When an event occurs the EPA records the timer value associated with it This is a capture event In the output mode the EPA monitors a timer until its value matches that of a stored time value When a match occurs the EPA triggers an output event which can set clear or toggle an output pin This is a compare event Both capture and compare events can initiate interrupts which can be serviced by either the interrupt controller or the PTS Timer 1 and timer 2 are both 16 bit up down timer counters that can be clocked internally or ex ternally Each timer counter is called a timer if it is clocked internally and a counter if itis clocked externally See Chapter 11 Event Processor Array EPA for additional information on the EPA and timer counters 2 5 4 Pulse width Modulator PWM The output waveform from
443. nables the peripheral transaction server PTS PTS Enable PSW 2 lt 1 PSW Flag Settings Z N C V VT ST EPTS 11101101 EXT SIGN EXTEND INTEGER INTO LONG INTEGER Sign extends the low order word of the operand throughout the high order word of the operand if DEST 15 1 then high word DEST lt OFFFFH else high word DEST lt 0 end_if PSW Flag Settings 7 VT ST 0 0 EXT lreg 00000110 8XC196MC MD MH USER S MANUAL intel Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format EXTB SIGN EXTEND SHORT INTEGER INTO INTEGER Sign extends the low order byte EXTB ofthe operand throughout the high order byte of the operand 00010110 wreg if DEST 7 1 then high byte DEST OFFH else high byte DEST lt 0 end if wreg PSW Flag Settings Z N C V VT ST 0 IDLPD IDLE POWERDOWN Depending on the 8 bit value of the KEY operand this instruction IDLPD key causes the device to 11110110 key enter idle mode if KEY 1 enter powerdown mode if KEY 2 execute a reset sequence if KEY any value other than 1 or 2 The bus controller completes any prefetch cycle in progress before the CPU stops or resets if KEY 1 then enter idle else if KEY 2 then enter p
444. nal phase clocks but not the internal oscillator On devices with no internal nonvolatile memory connect Vpp to Vgc Table 14 2 Operating Mode Control and Status Registers Mnemonic Address Description CCRO 2018H Chip Configuration 0 Register Bit 0 of this register enables and disables powerdown mode INT MASK1 0013H Interrupt Mask 1 Bit 6 of this 8 bit register enables and disables masks the external interrupt EXTINT 14 2 intel SPECIAL OPERATING MODES Table 14 2 Operating Mode Control and Status Registers Continued Mnemonic Address Description P1_DIR MH 1F9BH Port x Direction P2_DIR 1FD2H Each bit of Px DIR controls the direction of the corresponding pin P5 DIR 1 Clearing a bit configures a pin as a complementary output setting P7_DIR MD 1FD3H a bit configures a pin as an input or open drain output Open drain outputs require external pull ups P1_MODE MH 1F99H Port x Mode P2 MODE 1FDOH Each bit of Px MODE controls whether the corresponding pin P5 MODE functions as a standard I O port as a special function P7 MODE MD 1FD1H signal Setting a bit configures a pin as a special function signal clearing a bit configures a pin as a standard port pin P1_REG MH 1F9DH Port x Data Output 08 For an input set the corresponding Px_REG bit P7 MD 1FD5H For an output write the data
445. nate functions Table 6 1 provides an overview of the device I O ports The remainder of this chapter describes the ports in more detail and explains how to configure the pins The chapters that cover the associated peripherals discuss using the pins for their special functions Table 6 1 Device I O Ports Port Bits Type Direction Associated Peripheral s A D converter MC MD Port 0 8 Standard Input only A D converter EPA MH A D converter EPA MC MD 5 0 Standard Input onl igital i 8 MD andar nput only 1 7 6 are digital input only Port 1 channels for the 8XC196MD 4 MH Standard Bidirectional SIO ein EPA and timers MC MD Port 2 8 Standard Bidirectional EPA and timers SIO MH Port 3 8 Memory mapped Bidirectional Address data bus Port 4 8 Memory mapped Bidirectional Address data bus Port 5 8 Memory mapped Bidirectional Bus control Port 6 8 Standard Output only PWM waveform generator EPA frequency generator Port 7 MD 8 Standard Bidirectional P7 6 4 are low speed input output pins only they have no peripheral functions 6 1 8XC196MC MD MH USER S MANUAL intel 6 2 INPUT ONLY PORTS 1 MC MD ONLY AND 0 Port 0 is an eight bit high impedance input only port that provides analog and digital inputs The input only pins can be read as digital inputs most of them are also inputs to the A D converter The input only ports differ from the other sta
446. nd BHE see Figure 15 10 ALE is asserted while the address is driven and it can be used to latch the address externally RD is asserted for every external memory read and WRi is asserted for every external memory write When asserted BHE selects the bank of mem ory that is addressed by the high byte of the data bus ALE ALE WR or RD WR or RD BHE Valid AD7 0 4 AddrLow Data Out 015 0 Data Out AD15 8 Address High 16 bit Bus Cycle 8 bit Bus Cycle A3077 01 Figure 15 10 Standard Bus Control When the microcontroller is configured to use a 16 bit bus separate low and high byte write sig nals must be generated for single byte writes Figure 15 11 shows a sample circuit that combines ADO to produce these signals WRL and WRH A similar pair of signals for read is unnecessary For a single byte read with the 16 bit bus both bytes are placed on the data bus and the processor discards the unwanted byte WRH WRL A3109 03 Figure 15 11 Decoding WRL and WRH 15 22 intel INTERFACING WITH EXTERNAL MEMORY Figure 15 12 shows an 8 bit system with both flash and RAM The flash is the lower half of mem ory and the RAM is the upper half This system configuration uses the most significant address bit AD15 as the chip select signal and ALE as the address latch signal AD15 AD14 8 8XC196 A3140 01 Figure 15 12 8 bit System wit
447. nd Starting the Counter The control register Figure 9 12 specifies the dead time and operating mode and enables and disables the counters A read only bit CS indicates the current count direction 9 17 8XC196MC MD MH USER S MANUAL intel WG CONTROL Address 1FCCH Reset State MC MD 00COH Reset State MH 8000H The waveform generator control WG CONTROL register controls the operating mode dead time and count direction and enables and disables the counter 15 8 M2 M1 MO CS EC DT9 DT8 7 0 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DTO Bit Bit Number Mnemonic Function 15 Reserved for compatibility with future devices write zero to this bit 14 12 M2 0 Operating Mode This field controls the waveform generator s operating mode M2 Mi MO Mode 0 0 0 0 center aligned update registers once 0 0 1 1 center aligned update registers twice 0 1 0 2 edge aligned update registers once 0 1 1 3 edge aligned update registers twice 1 1 1 4 8XC196MH only edge aligned update WG COMPx and WG_COUNTER only when WG COUNTER WG RELOAD 11 CS Counter Status This read only bit indicates whether the counter is counting up or counting down 0 down counting 1 up counting 10 EC Enable Counter This bit starts and stops the counter 0 disable stop counter 1 enable start counter 9 0 DT9 0 Dead time This field specifies the dead time for all three phases Use the
448. nd gives you the option to download them 1 43 CompuServe Forums The CompuServe forums provide a means for you to gather information share discoveries and debate issues Type go intel for access For information about CompuServe access and service fees call CompuServe at 1 800 848 8199 U S or 614 529 1340 outside the U S 1 10 intel GUIDE TO THIS MANUAL 1 4 4 World Wide Web We offer a variety of information through the World Wide Web URL http www intel com Se lect Embedded Design Products from the Intel home page 1 5 TECHNICAL SUPPORT In the U S and Canada technical support representatives are available to answer your questions between 5 a m and 5 p m PST You can also fax your questions to us Please include your voice telephone number and indicate whether you prefer a response by phone or by fax Outside the U S and Canada please contact your local distributor 1 800 628 8686 U S and Canada 916 356 7599 U S and Canada 916 356 6100 fax U S and Canada 1 6 PRODUCT LITERATURE You can order product literature from the following Intel literature centers 1 800 548 4725 U S and Canada 708 296 9333 U S from overseas 44 0 1793 431155 Europe U K 44 0 1793 421333 Germany 44 0 1793 421777 France 8 1 0 120 47 88 32 Japan fax only 1 11 intel Architectural Overview intel CHAPTER 2 ARCHITECTURAL OVERVIEW The 16 bit 8XC196MC 8XC196MD and 8XC196MH CHMOS microcontrolle
449. nd the software trap interrupt prevent other interrupt requests from being acknowledged until after the next instruction is executed 8XC196MC MD MH USER S MANUAL intel Each PTS cycle within a PTS routine cannot be interrupted A PTS cycle is the entire PTS re sponse to a single interrupt request In block transfer mode a PTS cycle consists of the transfer of an entire block of bytes or words This means a worst case latency of 500 states if you assume a block transfer of 32 words from one external memory location to another See Table 5 4 on page 5 12 for PTS cycle execution times 5 4 2 Calculating Latency The maximum latency occurs when the interrupt request occurs too late for acknowledgment fol lowing the current instruction The following worst case calculation assumes that the current in struction is not a protected instruction To calculate latency add the following terms Time for the current instruction to finish execution 4 state times If this is a protected instruction the instruction that follows it must also execute before the interrupt can be acknowledged Add the execution time of the instruction that follows a protected instruction Time for the next instruction to execute The longest instruction NORML takes 39 state times However the BMOV instruction could actually take longer if it is transferring a large block of data If your code contains routines that transfer large blocks of data you may get
450. ndard ports in that their pins can be used only as in puts to the digital or analog circuitry On the 8 196 and 8XC196MD port 1 is an input only port that serves the same purpose as port 0 The 8 196 implements five pins while the 8XC196MD implements all eight 8X C196MH On the 8XC196MH port 1 is a standard bidirectional port that shares pins with the serial I O port See Bidirectional Ports 1 MH Only 2 5 and 7 MD Only on page 6 4 Because port 0 and port 1 of the 8 196 MD is permanently configured as an input only port it has no configuration registers Its single register Px PIN can be read to determine the current state of the pin The register is byte addressable and can be windowed See Windowing on page 5 16 Table 6 2 lists the standard input only port pins and Table 6 3 describes the Px PIN status regis ter Table 6 2 Standard Input only Port Pins Port Pin Special function Special function Associated Signal s Signal Type Peripheral P0 5 0 ACH5 0 Input A D converter 504 ACH6 Input A D converter T1CLK MH Input EPA bo ACH7 Input A D converter T1DIR MH Input EPA P1 0 MC MD ACH8 Input A D converter P1 1 MC MD ACH9 Input A D converter 10 Input A D converter P1 2 MC MD Input EPA 11 Input A D converter P1 3 MC MD T1DIR Input EPA P1 4 MC MD ACH12 Input A D converter P1 5 MD ACH13
451. ndexed Addressing In a long indexed instruction you specify the base address as a 16 bit variable and the offset as an indirect address register a WORD The following instructions use long indexed addressing LD AX TABLE BX AX lt MEM_WORD TABLE AND lt AND MEM_WORD TABLE ST AX TABLE BX MEM WORD TABLE lt AX ADDB AL BL LOOKUP CX AL lt BL MEM BYTE LOOKUP CX The instruction LD AX TABLE BX loads AX with the contents of the memory location that re sides at address TABLE BX That is the instruction adds the contents of BX the offset to the constant TABLE the base address then loads AX with the contents of the resulting address For example if TABLE equals 4000H and BX contains 12H then AX is loaded with the contents of location 4012H Long indexed addressing is typically used to access elements in a table where TABLE is a constant that is the base address of the structure and BX is the scaled offset x el ement size in bytes into the structure 3 2 4 3 Zero indexed Addressing In a zero indexed instruction you specify the address as a 16 bit variable the offset is zero and you can express it in one of three ways 0 2 or nothing Each of the following load instructions loads AX with the contents of the variable THISVAR LD AX THISVAR 0 LD AX THISVAR ZERO REG LD AX THISVAR The following instructions also use zero
452. nfigurations 15 1 EXTERNAL MEMORY INTERFACE SIGNALS AND REGISTERS Table 15 1 lists the signals and Table 15 2 lists the registers that are mentioned in this chapter Many of the external memory interface signals are multiplexed with standard I O port signals as shown in the Port Pin column Table 15 3 gives the port register settings to configure the pins as external memory interface signals rather than standard I O port signals See Chapter 6 I O Ports to configure the pins as standard I O port signals Table 15 1 External Memory Interface Signals Signal 2 2 Port Pin Type Description AD15 0 P4 7 0 Address Data Lines P3 7 0 These pins provide a multiplexed address and data bus During the address phase of the bus cycle address bits 0 15 are presented the bus and can be latched using ALE or ADV During the data phase 8 or 16 bit data is transferred ADV P5 0 O Address Valid This active low output signal is asserted only during external memory accesses ADV indicates that valid address information is available on the system address data bus The signal remains low while a valid bus cycle is in progress and is returned high as soon as the bus cycle completes An external latch can use this signal to demultiplex the address from the address data bus A decoder can also use this signal to generate chip selects for external memory 15 1 8XC196MC MD MH USER S MANUAL inte
453. nput only port Port 0 pins should not be left floating These pins may individually be used as analog inputs ACH or digital inputs PO y While it is possible for the pins to function simultaneously as analog and digital inputs this is not recommended because reading port 0 while a conversion is in process can produce unreliable conversion results ANGND must be connected for port 0 to function Port 0 is multiplexed as follows PO 0 ACHO P0 1 ACH1 P0 2 ACH2 P0 3 ACH3 P0 4 ACH4 PMODE 0 P0 5 ACH5 PMODE 1 P0 6 ACH6 PMODE 2 MC MD P0 6 ACH6 T1CLK PMODE 2 MH P0 7 ACH7 PMODE 3 MC MD and P0 7 ACH7 T1DIR PMODE 3 MH P1 4 0 MC P1 7 0 MD Port 1 This is a high impedance input only port On the 8XC196MC and MD some port 1 pins may individually be used as analog inputs ACH or digital inputs P1 y While it is possible for the pins to function simultaneously as analog and digital inputs this is not recommended because reading port 1 while a conversion is in process can produce unreliable conversion results ANGND and Vger must be connected for port 1 to function Port 1 is multiplexed as follows P1 0 ACH8 P1 1 ACH9 P1 2 ACH10 T1CLK P1 3 ACH11 T1DIR P1 4 ACH12 and P1 5 ACH13 P1 6 and P1 7 are not multiplexed with any other signals P1 7 5 are not implemented on the 8XC196MC 1 3 0 MH Port 1 This is a standard bidirectional port that is multiplexed with indi
454. nput protection devices This drives current into the internal reference circuitry and substantially degrades the accuracy of A D conversions on all channels Di 1000 2700 N 0 005uF J ANGND Optional D2 8XC196 Device A0082 03 Figure 12 8 Suggested A D Input Circuit 12 6 1 3 Analog Ground and Reference Voltages Reference supply levels strongly influence the absolute accuracy of the conversion For this rea son we recommend that you tie the ANGND pin to the V pin as close to the device as possible using a minimum trace length In a noisy environment we highly recommend the use of a sepa rate analog ground plane that connects to at a single point as close to the device as possible May vary between 2 mA and 5 mA during a conversion To minimize the effect of this fluc tuation mount a 1 0 uF ceramic or tantalum bypass capacitor between and ANGND as close to the device as possible 12 12 intel ANALOG TO DIGITAL A D CONVERTER ANGND should be within about 50 mV of V should be well regulated and used only for the A D converter The Vt supply can be between 4 5 and 5 5 volts and must be able to source approximately 5 mA see the datasheet for actual specifications should be approx imately the same voltage as Vger and should power up at the same time to avoid poten tial latch up conditions on Large negative current spikes on the
455. nsfer function Glossary 10 intel Any of the three nonmaskable interrupts unimple mented opcode software trap or NMI A partition of memory used for storing the interrupt vectors PTS vectors chip configuration bytes and several reserved locations Any maskable interrupt that is assigned to the interrupt controller for processing by an interrupt service routine The basic time unit of the device the combined period of the two internal timing signals and PH2 The internal clock generator produces PH1 and PH2 by halving the frequency of the signal on XTALI The rising edges of the active high PH1 and PH2 signals generate CLKOUT the output of the internal clock generator Because the device can operate at many frequencies this manual defines time requirements in terms of state times rather than in specific units of time An A D conversion method that uses a binary search to arrive at the best digital representation of an analog input Change in the stated variable for each degree Centigrade of temperature change The change in a specification due to a change in temperature Temperature drift can be calculated by using the temperature coefficient for the specification An actual characteristic that has been translated and scaled to remove zero offset error and full scale error A terminal based characteristic resembles an actual characteristic with zero offset error and full scale error removed A graph of
456. nstruction 3 11 A 3 A 27 A 46 A 51 A 57 two byte See SKIP instruction NORML instruction 3 4 A 3 A 27 41 51 A 57 NOT instruction A 2 A 28 A 41 A 48 A 53 Notational conventions 1 3 1 4 NOTB instruction A 2 A 28 41 A 48 A 53 Numbers conventions 1 4 ONCE mode 2 11 14 10 entering 14 11 exiting 14 11 ONCE 14 2 B 17 Ones register C 29 Opcodes A 41 EE and unimplemented opcode interrupt A 3 A 46 FE and signed multiply and divide A 3 map A 2 reserved A 3 A 46 Operand types See data types Operands addressing 3 10 Operating modes 2 11 OR instruction A 2 A 28 A 43 A 48 A 53 intel ORB instruction A 2 A 28 A 43 A 48 A 53 Oscillator and powerdown mode 14 5 external crystal 13 6 on chip 13 5 OTPROM controlling access to internal memory 16 3 16 6 controlling fetches from external memory 16 6 16 7 memory map 16 2 programming 16 1 16 33 See also programming modes ROM dump mode 16 30 verifying 16 30 Overflow V flag A 4 A 5 A 21 A 22 Overflow trap VT flag 4 5 A 11 A 22 A 23 0 7 0 B 17 P0 7 4 and programming modes 16 14 PO PIN C 69 P1 3 0 B 17 P1 7 0 B 17 P1 DIR C 69 P1 MODE C 69 P1 PIN C 69 P1 REG C 69 P2 2 considerations 14 7 P2 7 0 B 18 P2 DIR C 69 P2 MODE C 69 P2 PIN C 69 P2 REG C 69 P3 7 0 B 18 P4 7 0 B 18 5 0 5 7 See also port 5 5 7 0 B 18 5 SFRs 6 6 P6 7 0 B 18 P6_DIR
457. nstruction is being fetched from external memory The signal remains high during the entire bus cycle of an external instruction fetch INST is low for data accesses including interrupt vector fetches and chip configuration byte reads INST is low during internal memory fetches INST is multiplexed with P5 1 NMI Nonmaskable Interrupt In normal operating mode a rising edge on NMI generates a nonmaskable interrupt NMI has the highest priority of all prioritized interrupts Assert NMI for greater than one state time to guarantee that it is recognized B 16 SIGNAL DESCRIPTIONS Table B 6 Signal Descriptions Continued Name Type Description ONCE On circuit Emulation Holding ONCE low during the rising edge of RESET places the device into on circuit emulation ONCE mode This mode puts all pins except XTAL1 and XTAL2 into a high impedance state thereby isolating the device from other components in the system The value of ONCE is latched when the RESET pin goes inactive While the device is in ONCE mode you can debug the system using a clip on emulator To exit ONCE mode reset the device by pulling the RESET signal low To prevent inadvertent entry into ONCE mode either configure this pin as an output or hold it high during reset and ensure that your system meets the Specification see datasheet ONCE is multiplexed with P5 4 P0 7 0 Port 0 This is a high impedance i
458. nstruction to specify two source registers and a separate destination register For example the following instruction multiplies two 16 bit vari ables and stores the 32 bit result in a third variable MUL RESULT FACTOR_1 FACTOR_2 multiply FACTOR 1 and FACTOR 2 and store answer in RESULT RESULT FACTOR 1 x FACTOR 2 An 80C186 microprocessor requires four instructions to accomplish the same operation The fol lowing example shows the equivalent code for an 80C186 microprocessor MOV AX FACTOR 1 move FACTOR 1 into accumulator AX AX FACTOR1 MUL FACTOR 2 multiply FACTOR 2 and AX DX AX lt AX x FACTOR 2 MOV RESULT AX move lower byte into RESULT RESULT lt MOV RESULT 2 DX move upper byte into RESULT 2 RESULT 2 lt DX 2 5 8XC196MC MD MH USER S MANUAL intel 2 3 4 Memory Interface Unit The RALU communicates with all memory except the register file and peripheral SFRs through the memory controller It communicates with the upper register file through the memory control ler except when windowing is used see Chapter 4 Memory Partitions The memory controller contains the prefetch queue the slave program counter slave PC address and data registers and the bus controller The bus controller drives the memory bus which consists of an internal memory bus and the ex ternal address data bus The bus controller receives memory access requests from either the RA
459. nt reloads WG_COUNTER which also causes a change in the duty cycle In mode 4 an EPA event reloads WG_OUTPUT but WG_COMPx and WG_COUNTER are reloaded only when the counter reaches the reload value 8XC196MC MD MH USER S MANUAL intel 9 4 PROGRAMMING THE WAVEFORM GENERATOR This section explains how to configure the waveform generator and determine its status 9 4 1 Configuring the Outputs The waveform generator s outputs are multiplexed with general purpose output port 6 so you must configure them as special function signals to use them as waveform generator outputs The WG_OUTPUT register Figure 9 8 configures the pins establishes the output polarity and con trols whether changes to the outputs are synchronized with an event or take effect immediately Four bits of WG_OUTPUT are unrelated to the waveform generator they configure the outputs for the pulse width modulator PWM peripheral which also shares pins with port 6 The P6 and PEG bits control the P6 6 PWMO pin and the P7 and bits control P6 7 PWMI pin Their placement in this register allows you to configure all the port 6 pins with a single write to WG OUTPUT Table 9 5 shows the bit combinations necessary to drive the waveform generator s outputs high or low or to connect them to the WG_EVEN ODD signal Note that PHx 2 is always set to select the waveform generator signal function clearing PHx 2 selects the general purpose I O port functio
460. nteger that determines the baud rate The maximum BAUD VALUE is 32 767 7FFFH In asynchronous modes 1 2 and 3 the minimum BAUD VALUE is 0000H when using XTAL1 and 0001H when using BCLKx In synchronous mode 0 the minimum BAUD VALUE is 0001H for transmissions and 0002H for receptions In synchronous mode 4 the minimum BAUD VALUE is 0001H for both transmissions and receptions 15 8 8XC196MH CLKSRC BV14 BV13 BV12 BV11 BV10 BV9 BV8 7 0 BV7 BV6 BV5 4 BV3 2 BV1 BVO Bit Bit Number Mnemonic 15 CLKSRC Serial Port Clock Source This bit determines whether the serial port is clocked from an internal or an external source 0 signal on the BCLKx pin external source 1 input frequency on the XTAL1 pin internal source Figure 7 7 Serial Port x Baud Rate SPx BAUD Register 7 12 intel SERIAL 1 0 SIO PORT SPx_BAUD Continued Address 1F84H 1F8CH x 0 1 8XC196MH Reset State 0000H The serial port baud rate x SPx BAUD register selects the serial port x baud rate and clock source The most significant bit selects the clock source The lower 15 bits represent BAUD VALUE an unsigned integer that determines the baud rate The maximum BAUD VALUE is 32 767 7FFFH In asynchronous modes 1 2 and 3 the minimum BAUD VALUE is 0000H when using XTAL1 and 0001H when using BCLKx In synchronous mode 0 the minimum BAUD VALUE is 0001H for transmissi
461. nterrupt call until after the first instruction of the interrupt service routine is executed 2 PUSHA instruction saves the contents of the PSW INT MASK INT and window selection register WSR onto the stack and then clears the PSW INT MASK and INT MASKI registers In addition to the arithmetic flags the PSW contains the global interrupt enable bit I and the PTS enable bit PSE By clearing the PSW and the interrupt mask registers PUSHA effectively masks all maskable interrupts disables standard interrupt servicing and disables the PTS Because PUSHA is a protected instruction it also inhibits interrupt calls until after the next instruction executes 3 The LDB INT MASKI instruction enables those interrupts that you choose to allow to interrupt the service routine In this example only EXTINT can interrupt the receive interrupt service routine By enabling or disabling interrupts the software establishes its own interrupt servicing priorities 4 The EI instruction re enables interrupt processing and inhibits interrupt calls until after the next instruction executes 5 The actual interrupt service routine executes within the priority structure established by the software 6 Attheend of the service routine the POPA instruction restores the original contents of the PSW INT MASK INT MASKI and WSR registers any changes made to these registers during the interrupt service routine are overwritten Because interr
462. o away when the XTAL1 input signal meets the V and V specifications listed in the datasheet If these specifications are met the pin capacitance will not exceed 20 pF 13 7 8XC196MC MD MH USER S MANUAL intel 13 6 RESETTING THE DEVICE Reset forces the device into a known state As soon as RESET is asserted the I O pins the con trol pins and the registers are driven to their reset states Tables in Appendix B list the reset states of the pins see Table B 8 on page B 23 for the 8 196 and 8XC196MD or Table B 9 on page B 25 for the 8XC196MH See Table C 2 on page C 2 for the reset values of the SFRs The device remains in its reset state until RESET is deasserted When RESET is deasserted the bus controller fetches the chip configuration bytes CCBs loads them into the chip configuration registers CCRs and then fetches the first instruction Figure 13 7 shows the reset sequence timing Depending upon when RESET is brought high the CLKOUT signal MC and MD only may become out of phase with the PHI internal clock When this occurs the clock generator immediately resynchronizes CLKOUT as shown in Case 2 Internal 7 Reset RESET Pin i Case 1 MC MD CLKOUT Only ALE 9 8 1 20H 20H TWeak 20 Bus parameters defined ready gt control bus width and bus timing modes take effect here Defaults to an 8 bit
463. ocations Only the amount of available memory limits the table size it can reside in internal or external RAM Table 5 7 A D Scan Mode Command Data Table Address Contents XXXX AH A D Result 2 XXXX 8H Unused A D Command 31 XXXX 6H A D Result 1 XXXX 4H Unused A D Command 2 XXXX 2H A D Result 011 XXXX Unused A D Command 1 t Write 0000H to prevent a new conversion at the end of the routine Result of the A D conversion that initiated the PTS routine To initiate A D scan mode enable the A D conversion complete interrupt and assign it to the PTS Software must initiate the first conversion When the A D finishes the first conversion and gen erates an A D conversion complete interrupt the interrupt vectors to the PTSCB and initiates the A D scan routine The PTS stores the conversion results loads a new command into AD COMMAND and then decrements the number in PISCOUNT As each additional conver sion complete interrupt occurs the PTS repeats the A D scan cycle it stores the conversion re sults loads the next conversion command into the AD COMMAND register and decrements PTSCOUNT The routine continues until PISCOUNT decrements to zero When this occurs hardware clears the enable bit in the PTSSEL register which disables PTS service and sets the PTSSRV bit which requests an end of PTS interrupt The interrupt service routine could process the conversion results and then re enable PTS
464. ock Control During Power saving 14 4 Power up and Power down Sequence When Using an External Interrupt 14 7 External RG CIFCUIL oiii tos ieee dent net citet Ig acne dere 7438 Typical Voltage on the Pin While Exiting 14 9 Chip Configuration 0 CCRO 15 7 Chip Configuration 1 CCR1 15 9 Multiplexing and Bus Width 15 11 BUSWIDTH Timing Diagram 8XC196MC MD 15 12 BUSWIDTH Timing Diagram 8 196 me 15 12 Timings for 16 bit BUSES niiina aaie neben tnn 15 15 Timings for 8 Dit BUS6S edere iret S Ra HR IRA 15 17 READY Timing Diagram One Wait State 8 196 MD 15 19 READY Timing Diagram One Wait State 8 196 15 20 Standard B s Gontrol ter etre repe 15 22 Decoding WRL and 15 22 8 bit System with Flash and RAM 15 23 16 bit System with Dynamic Bus 15 24 Write Strobe Mode s in eno ee 15 25 16 bit System with Writes to Byte wide e 15 26 Address Valid Strobe
465. ode The PPW_VALUE determines the programming pulse width 15 8 PPW15 PPW14 PPW13 PPW12 PPW11 PPW10 PPW9 PPW8 7 0 PPW7 PPW6 PPW5 PPW4 PPW3 PPW2 PPW1 PPWO Bit Bit Number Mnemonic Function 15 0 PPW15 0 PPW_VALUE This value establishes the programming pulse width for auto programming Use the appropriate formula to calculate the PPW_VALUE then write the result to the PPW register PPW VALUE for 8XC196MC MD 62 5 PPW_VALUE for 8XC196MH 25xF XTAL1 C 39 8XC196MC MD MH USER S MANUAL intel PSW PSW no direct access The processor status word PSW actually consists of two bytes The high byte is the status word which is described here the low byte is the INT MASK register The status word contains one bit PSW 1 that globally enables or disables servicing of all maskable interrupts one bit PSW 2 that enables or disables the peripheral transaction server PTS and six Boolean flags that reflect the state of a user s program The status word portion of the PSW cannot be accessed directly To access the status word push the value onto the stack PUSHF then pop the value to a register POP test reg The PUSHF and PUSHA instructions save the PSW in the system stack and then clear it POPF and POPA restore it 15 8 Z N V VT PSE ST See INT_MASK on page C 25 Bit Bit Number Mnemon
466. ode This field controls the waveform generator s operating mode M2 Mi MO Mode center aligned update registers once center aligned update registers twice edge aligned update registers once edge aligned update registers twice 8XC196MH only edge aligned update WG COMPx and WG_COUNTER only when WG COUNTER WG RELOAD oooo 11 CS Counter Status This read only bit indicates whether the counter is counting up or counting down 0 down counting 1 up counting 10 EC Enable Counter This bit starts and stops the counter 0 disable stop counter 1 enable start counter 9 0 DT9 0 Dead time This field specifies the dead time for all three phases Use the following formula to calculate the appropriate DT_VALUE xF 2 TpEAD DT VALUE 222 where Tbeap dead time in us FxrAL1 input frequency on XTAL1 pin in MHz C 60 intel REGISTERS WG COUNTER WG COUNTER Address 1FCAH z Reset State MC MD XXXXH Reset State MH 0000H You can read the waveform generator counter WG_COUNTER register to determine the current counter value 15 0 Counter Value Bit Number Function 15 0 Counter Value This register reflects the current counter value C 61 8XC196MC MD MH USER S MANUAL intel WG OUTPUT Port 6 ca The port 6 output configuration WG_OUTPUT register control
467. odes 1 and 3 setting this bit enables the parity function This bit must be cleared if mode 2 is used When this bit is set TB8 takes the parity value on transmissions and SPx_STATUS 7 becomes the receive parity error bit 1 0 1 0 Mode Selection These bits along with bit 7 select the communications mode 2 1 0 0 0 0 synchronous mode 0 X 0 1 mode 1 X 1 0 mode 2 X 1 1 mode 3 1 0 0 synchronous mode 4 Figure 7 6 Serial Port Control SPx CON Register Continued 8XC196MC MD MH USER S MANUAL intel 7 4 8 Programming the Baud Rate and Clock Source The SPx BAUD register Figure 7 7 selects the clock input for the baud rate generator and de fines the baud rate for all serial I O modes For mode 4 with SCLKx configured for input the baud rate generator is not used This register acts as a control register during write operations and as a down counter monitor during read operations WARNING Writing to the SPx BAUD register during a reception or transmission can corrupt the received or transmitted data Before writing to SPx BAUD check the SPx STATUS register to ensure that the reception or transmission is complete SPx BAUD Address 1F84H 1F8CH x 0 1 8XC196MH Reset State 0000H The serial port baud rate x SPx BAUD register selects the serial port x baud rate and clock source The most significant bit selects the clock source The lower 15 bits represent BAUD VALUE an unsigned i
468. ogrammed number of wait states is reached If READY is pulled high before the programmed number of wait states is reached no additional wait states will be inserted into the bus cycle IRC2 IRC1 IRCO zero wait states illegal illegal one wait state two wait states three wait states infinite If you choose the infinite wait states option you must keep P5 6 configured as the READY signal Also be sure to add external hardware to count wait states and pull READY high within a specified time Otherwise a defective external device could tie up the address data bus indefinitely The CCRs are loaded with the contents of the chip configuration bytes CCBs after reset unless the microcontroller is entering programming modes see Entering Programming Modes on page 16 13 in which case the programming chip configuration bytes PCCBs are used The CCBs reside in nonvolatile memory at addresses 2018H CCBO and 201AH 1 Figure 15 1 Chip Configuration 0 CCRO Register 15 7 8XC196MC MD MH USER S MANUAL intel CCRO Continued no direct accesst The chip configuration 0 CCRO register controls powerdown mode bus control signals and internal memory protection Three of its bits combine with two bits of CCR1 to control wait states and bus width 7 LOC1 LOCO IRC1 IRCO ALE WR BWO PD
469. ogress then goes high to indicate that the dump is complete 16 10 PCCB AND UPROM PROGRAMMING 8XC196MH ONLY The PCCB and UPROM programming modes are useful if you have auto programmed and veri fied the rest of the OTPROM array and now need to program only the PCCB and UPROM bits With slave programming mode you can program the PCCB and UPROM bits along with the rest of the array 16 30 intel PROGRAMMING THE NONVOLATILE MEMORY Figure 16 14 shows the recommended circuit for PCCB and UPROM programming In these cir cuits the PBUS holds data to be written to the OTPROM PALE begins programming and PVER drives an LED that lights to indicate successful programming 20 pF 20 pF I IL 100 XTAL1 XTAL2 RESET lt lt 5 0V e T Vec 1 0uF 74HC14 Opl READY P5 6 10 NMI alk BUSWIDTH PS 7 4 10kQ VREF p id Pullups Required P0 7 4 7 0 E s 4 o PMODE 0DH PCCB Mode Value Vec P2 1 PALE 10kQ Push to Program H P2 0 PVER 74HC14 87C196 Device Reset 1 kQ A3003 02 Figure 16 14 PCCB and UPROM Programming Circuit To enter either mode follow the standard power up sequence page 16 14 after setting the values listed in Table 16 13 If you want to program both the PCCB and the UPROM bits program one of them and complete the power down sequence Then reconfigure the PMODE and port 3 pins and repeat the power up sequence 16
470. om one location in wreg memory to another The instruction is identical to BMOV except that BMOVI is 11001101 wreg Ireg interruptible The source and destination addresses are calculated using the indirect NOTE The pointers are autoincre with autoincrement addressing mode A long mented during this instruction register PTRS addresses the source and However CNTREG is decre destination pointers which are stored in mented only when the instruction adjacent word registers The source pointer is interrupted When BMOVI is SRCPTR is the low word and the interrupted CNTREG is updated destination pointer DSTPTR is the high to store the interim word count at word of PTRS A word register CNTREG the time of the interrupt For this specifies the number of transfers The blocks reason you should always reload of word data can be located anywhere in CNTREG before starting a register RAM but should not overlap BMOVI COUNT lt CNTREG LOOP SRCPTR lt PTRS DSTPTR lt PTRS 2 DSTPTR lt SRCPTR PTRS lt SRCPTR 2 PTRS 2 lt DSTPTR 2 COUNT lt COUNT 1 if COUNT 0 then go to LOOP end if PSW Flag Settings Z N C V VI ST BR BRANCH INDIRECT Continues execution at DEST the address specified in the operand word BR wreg register 11100011 wreg PC lt DEST 9 PSW Flag Settings Z N C V VI ST CLR CLEAR WORD Clears the value of the DEST operand CLR wreg DEST lt 0 P
471. on 20H to an external memory location The PTS transfers the first word to location 6000H Then it increments and updates the destination address and decrements the PISCOUNT register it does not increment the source address When the second cycle begins the PTS moves a second word from location 20H to location 6002H When PTSCOUNT equals zero the PTS will have filled locations 6000 600FH and an end of PTS interrupt is generated 5 29 8XC196MC MD MH USER S MANUAL intel Table 5 5 Single Transfer Mode PTSCB Unused Unused PTSDST H 60H PTSDST L 00H PTSSRC H 00H PTSSRC L 20H PTSCON 85H Mode 100 BW 0 SI SU 0 DI DU 1 PTSCOUNT 09H 5 6 4 Block Transfer Mode In block transfer mode an interrupt causes the PTS to move a block of bytes or words from one memory location to another See AP 483 Application Examples Using the SXCI196MC MD Mi crocontroller for application examples with code Figure 5 17 shows the PTS control block for block transfer modes In this mode each PTS cycle consists of the transfer of an entire block of bytes or words Because a PTS cycle cannot be interrupted the block transfer mode can create long interrupt latency The worst case latency could be as high as 500 states if you assume a block transfer of 32 words from one external memory location to another using an 8 bit bus with no wait states See Table 5 4 on page 5 12 for execution tim
472. on PC board P0 1 ACH1 P3 5 PBUS 5 2 26 0 2 ACH2 AD4 P3 4 PBUS 4 E 27 0 3 AD3 P3 3 PBUS 3 28 0 4 0 AD2 P3 2 PBUS 2 29 P0 5 ACH5 PMODE 1 AD1 P3 1 PBUS 1 30 56 VREF ADO P3 0 PBUS 0 E131 55 ET ANGND NC r1 32 54 Ea P0 6 ACH6 T1CLK PMODE 2 st LO XO 00 O t 10 QN CO CO CO CO s sb Wb MB Mb LO L0 505 ONO 2202 2 29592 gt 5909922889 z zcF or iva 10 c S T CES ao P0 7 ACH7 T1IDIR PMODE 3 53 A2573 03 Figure B 7 8XC196MH 84 lead PLCC Package B 11 8XC196MC MD MH USER S MANUAL intel 80 P5 5 BHE WRH 79 P5 3 RD 78 P Vpp 77 FA P5 0 ALE ADV 76 B Vss 73 5 4 ONCE 72 71 H Vss 70 XTAL1 69 F XTAL2 75 P5 1 INST 68 FI NC 74 5 6 READY 65 P6 6 PWMO 67 ANC 66 E NC P5 2 WRit WRL 1 P5 7 BUSWIDTH 2 P4 7 AD15 PBUS 15 3 P4 6 AD14 PBUS 14 EF 4 P6 7 PWM1 P2 6 COMP2 CPVER P2 5 COMP1 PACT P2 4 COMPO AINC NC P4 5 AD13 PBUS 13 NC NC o7 P2 7 SCLK1 BCLK1 P44 AD12 PBUS 12 2 8 P2 3 COMP3 P4 3 AD11 PBUS 11
473. on time must be long enough for the comparator and cir cuitry to settle and resolve the voltage Excessively long conversion times allow the sample ca pacitor to discharge degrading accuracy The AD_TIME register Figure 12 4 specifies the A D sample and conversion times To avoid erroneous conversion results use the T and Tcony specifications on the datasheet to determine appropriate values 12 6 intel ANALOG TO DIGITAL A D CONVERTER AD TIME Address 1FAFH Reset State FFH The A D time TIME register programs the sample window time and the conversion time for each bit This register programs the speed at which the A D can run not the speed at which it can convert correctly Consult the data sheet for recommended values Initialize the AD TIME register before initializing the AD COMMAND register Do not write to this register while a conversion is in progress the results are unpredictable 7 0 SAM2 1 CONV4 CONV3 CONV2 CONV1 CONVO Bit Bit Function Number Mnemonic 7 5 SAM2 0 A D Sample Time These bits specify the sample time Use the following formula to compute the sample time TsamX 1 2 S 8 where SAM 1to7 Tsam the sample time in usec from the data sheet XTAL the input frequency on XTAL1 in MHz 4 0 CONV4 0 A D Convert Time These bits specify the conversion time for each bit Use the following f
474. on to link and locate the modules and to deter mine the proper windowing RL196 MOD1 0BJ MOD2 0BJ registers 100h O01ffh windowsize 32 The above linker controls tell the linker to use registers 0100 01 FFH for windowing and to use a window size of 32 bytes These two controls enable windowing The following is the map listing for the resultant output module MODI by default SEGMENT MAP FOR modi MOD1 TYPE BASE LENGTH RESERVED 0000H OO1AH STACK 001 0006H GAD KAX 0020H 00 OVRLY 0100H 0006H OVRLY 0106H 0006H 010CH 1F74H CODE 2080H 0011H CODE 2091H 0011H FLEE RP URGERE 20A2H DF5EH This listing shows the disassembled code 2080H C814 2082H 14814 2085H 44E4E2E0 2089H B21814 208CH 65020018 2090H FO 2091H C814 2093H 14814 2096H A4EAE8E6 209AH 21814 209 65020018 20A1H FO 4 18 ALIGNMENT WORD WORD WORD BYTE BYTE WSR 48H EOH E2H E4H H EAH MODULE NAME MOD2 MOD1 MOD2 MOD1 ntel MEMORY PARTITIONS The C compiler can also take advantage of this feature if the windows switch is enabled For details see the MCS 96 microcontroller architecture software products in the Development Tools Handbook 4 2 3 Windowing and Addressing Modes Once windowing is enabled the windowed locations can be accessed both through the window using direct 8 bit addressing and by the
475. ons 13 Definition of Status B 23 8XC196MC and MD Default Signal B 23 8XC196MH Default Signal B 25 Modules and Related C 1 Register Name Address and Reset Status sess O72 COMPx TIME Addresses and Reset C 17 CON Addresses and Reset 20 EPAx TIME Addresses and Reset C 21 DIR Addresses and Reset C 30 MODE Addresses and Reset C 31 Special function Signals for Ports 1 2 5 6 3 PIN Addresses and Reset C 33 REG Addresses and Reset C 34 Output nemen nennen nemen eren C 65 WSR Settings and Direct Addresses for Windowable C 68 intel Guide to This Manual intel CHAPTER 1 GUIDE TO THIS MANUAL This manual describes the 8 196 8XC196MD and 8XC196MH embedded microcontrol lers It is intended for use by both software and hardware designers familiar with the principles of microcontrollers This chapter describes what you ll find in th
476. ons and 0002H for receptions In synchronous mode 4 the minimum BAUD VALUE is 0001H for both transmissions and receptions 15 8 8XC196MH CLKSRC BV14 BV13 BV12 BV11 BV10 BV9 BV8 7 0 BV7 BV6 BV5 BV4 BV3 BV2 1 BVO Bit Bit A Number Mnemonic Function 14 0 BV14 0 These bits constitute the BAUD_VALUE Use the following equations to determine the BAUD_VALUE for a given baud rate Synchronous mode 0 1 FxTAL1 BCLKx BAUD_VALUE Baud Ratex2 Baud Rate Asynchronous modes 1 2 and 3 FxraLt BCLKx BAUD VALUE Baud Rate x 8 Synchronous mode 4 SCLKx output FxTAL1 BAUD VALUE Baud Ratex 4 t For mode 0 receptions the BAUD_VALUE must be 0002H or greater Otherwise the resulting data in the receive shift register will be incorrect Figure 7 7 Serial Port x Baud Rate SPx_BAUD Register Continued 7 13 8XC196MC MD MH USER S MANUAL intel CAUTION For mode 0 receptions the BAUD VALUE must be 0002H or greater Otherwise the resulting data in the receive shift register will be incorrect The reason for this restriction is that the receive shift register is clocked from an internal signal rather than the signal on TXDx Although these two signals are normally synchronized the internal signal generates one clock before the first pulse transmitted by TXDx and this first clock signal is not synchronized with TXDx This clock signal causes
477. onversion Waveform Generator Reload AD The function of this bit depends on the EPA channel For EPA capture compare channels 0 2 4 The WGR bit allows you to use the EPA activities to cause the reload of new values in the waveform generator 0 no action 1 enables waveform generator reload For EPA capture compare channels 1 3 5 The AD bit allows you to use the EPA activities to start an A D conversion that has been previously set up in the A D control registers 0 causes no A D action 1 starts A D conversion on an output compare 1 ROT Reset Opposite Timer Selects the timer that is to be reset if the RT bit is set 0 selects the reference timer for possible reset 1 selects the opposite timer for possible reset The state of the TB bit determines which timer is the reference timer and which timer is the opposite timer 0 RT Reset Timer This bit controls whether the timer selected by the ROT bit will be reset 1 resets the timer selected by the ROT bit 0 disables the reset function Figure 11 11 EPA Compare Control COMPx CON Registers Continued 11 6 ENABLING THE EPA INTERRUPTS To enable the interrupts set the corresponding bits in the INT MASK register Figure 5 7 on page 5 15 To enable the individual sources of the multiplexed PI MC MD SPI MH and OVRTM interrupts set the corresponding bits in the MASK register Figure 5 9 page 5 17 Chap
478. onverter and port operation Table 12 2 A D Control and Status Registers Mnemonic Address Description AD COMMAND 1FACH A D Command This register selects the A D channel controls whether the A D conversion starts immediately or is triggered by the EPA and selects the operating mode AD RESULT 1FAAH 1FABH A D Result For an A D conversion the high byte contains the eight MSBs from the conversion while the low byte contains the two LSBs from a 10 bit conversion undefined for an 8 bit conversion indicates which A D channel was used and indicates whether the channel is idle For a threshold detection calculate the value for the successive approximation register and write that value to the high byte of AD RESULT Clear the low byte or leave it in its default state AD TEST 1FAEH A D Conversion Test This register specifies adjustments for zero offset errors AD TIME 1FAFH A D Conversion Time This register defines the sample window time and the conversion time for each bit INT MASK 0008H Interrupt Mask The AD bit in this register enables or disables the A D interrupt Set the AD bit to enable the interrupt request INT PEND 0009H Interrupt Pending The AD bit in this register when set indicates that an A D interrupt request is pending 12 2 intel ANALOG TO DIGITAL A D CONVERTER Table 12 2 A D Control and Status Registers
479. or signed operands 3 1 10 Floating Point Operations The hardware does not directly support operations on REAL floating point variables Those op erations are supported by floating point libraries from third party tool vendors See the Develop ment Tools Handbook The performance of these operations is significantly improved by the NORML instruction and by the sticky bit ST flag in the processor status word PSW The NORML instruction normalizes a 32 bit variable the sticky bit ST flag can be used in conjunc tion with the carry C flag to achieve finer resolution in rounding intel PROGRAMMING CONSIDERATIONS 3 2 ADDRESSING MODES The instruction set uses four basic addressing modes direct immediate indirect with or without autoincrement indexed short long or zero indexed The stack pointer can be used with indirect addressing to access the top of the stack and it can also be used with short indexed addressing to access data within the stack The zero register can be used with long indexed addressing to access any memory location An instruction can contain only one immediate indirect or indexed reference any remaining op erands must be direct references This section describes the addressing modes as they are handled by the hardware An understand ing of these details will help programmers to take full advantage of the architecture The assembly language hides some of the details of how these addressing
480. or the 8XC196MC MD or 105E 105FH for the 8XC196MH Leave the external CCBO location 4018H unprogrammed 0FFFFH Place the appropriate CCB1 value at external location 401 AH Place the security key to be programmed in external EPROM locations 4020H 402FH for the 8 196 MD or 0020 002FH for the 8 196 Place the value 20H in external EPROM locations 4019H and 401BH for the reserved OTPROM locations that require this value Place the desired code in the remaining external EPROM locations 4000 7FFFH for the 8XC196MC MD or 2000 9FFFH for the 8 196 Execute the power up sequence page 16 14 to initiate auto programming When programming is complete execute the powerdown sequence page 16 14 before continuing to step 2 16 29 8XC196MC MD MH USER S MANUAL intel 2 Using another blank EPROM device follow these steps to program only CCBO Place the programming pulse width PPW in external locations 14H 15H Place the appropriate CCBO value in external location 4018H Place the security key to be verified in external EPROM locations 0020H 002FH This value must match the security key programmed in step 1 Leave the remaining EPROM locations unprogrammed 0FFFFH Execute the power up sequence page 16 14 to initiate auto programming When programming is complete follow the powerdown sequence page 16 14 At this point you can modify the
481. orm Gen Output Config 1FCO 0000 0000 0000 0000 WG_PROTECT MC MD 1111 0000 WG PROTECT MH Waveform Gen Protection 1FCE THE WG RELOAD Waveform Gen Reload 1FC8 0000 0000 0000 0000 WSR Window Selection 0014 0000 0000 ZERO_REG Zero Register 0000 0000 0000 0000 0000 Reset value is when pin is not driven Reset value is 80H if the EA pin is high if EA is low The CCRs are loaded with the contents of the chip configuration bytes CCBs after a device reset unless the device is entering programming modes see Entering Programming Modes on page 16 13 in which case the programming chip configuration bytes PCCBs are used The CCBs reside in internal nonvolatile memory at addresses 2018H CCBO and 201AH 1 5 8XC196MC MD MH USER S MANUAL intel AD COMMAND AD COMMAND Address 1FACH i Reset State 80H The A D command AD COMMAND register selects the A D channel number to be converted controls whether the A D converter starts immediately or with an EPA command and selects the conversion mode 7 0 M1 MO GO ACH3 ACH2 ACH1 ACHO Bit Bit Function Number Mnemonic Reserved for compatibility with future devices write zeros to these bits 6 5 M1 0 A D Modet These bits determine the A D mode M1 MO Mode 0 10 bit conversion 0 8 bit conversion 1 threshold detect high 1 threshold detect low 4 GO A D Conversion Tri
482. ormula to compute the conversion time FxraLi 2xB where CONV 2031 the conversion time in usec from the data sheet 1 the input frequency XTAL1 in MHz the number of bits to be converted 8 or 10 Figure 12 4 A D Time AD_TIME Register 12 4 4 Programming the A D Command Register The A D command register controls the operating mode the analog input channel and the con version trigger 12 7 8XC196MC MD MH USER S MANUAL intel AD COMMAND Address 1FACH Reset State 80H The A D command AD COMMAND register selects the A D channel number to be converted controls whether the A D converter starts immediately or with an EPA command and selects the conversion mode 7 0 M1 MO GO ACH3 ACH2 ACH1 ACHO Bit Bit Function Number Mnemonic unctio Reserved for compatibility with future devices write zeros to these bits 6 5 M1 0 A D Modet These bits determine the A D mode M1 MO Mode 0 0 10 bit conversion 0 1 8 bit conversion 1 0 threshold detect high 1 1 threshold detect low 4 GO A D Conversion Triggertt Writing this bit arms the A D converter The value that you write to it determines at what point a conversion is to start 0 EPA initiates conversion 1 start immediately 3 0 ACH3 0 A D Channel Selection Write the A D conversion channel number to these bits
483. ount Ireg either as an immediate value in the range of O or to 15 OFH inclusive or as the content of SHRL breg any register 10H OFFH with a value in the range of 0 to 31 1FH inclusive The left bits 00001100 breg Ireg of the result are filled with zeros The last bit shifted out is saved in the carry flag NOTES This instruction clears the Temp lt COUNT sticky bit flag at the beginning do while Temp 0 of the instruction If at any time Low order bit of DEST during the shift a 1 is shifted DEST lt DEST 2 into the carry flag and another Temp Temp 1 shift cycle occurs the instruc end while tion sets the sticky bit flag PSW Flag Settings In this operation DEST 2 rep 7 N resents unsigned division 0 0 SJMP SHORT JUMP Adds to the program counter the offset between the end of this instruction s up cadd and the target label effecting the jump The offset must be in the range of 1024 to 00100xxx disp low 1023 inclusive PC lt PC 11 bit disp NOTE The displacement disp is sign extended to 16 bits PSW Flag Settings SKIP TWO BYTE NO OPERATION Does nothing SKIP breg 00000000 breg A 36 intel INSTRUCTION SET REFERENCE Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format ST STORE WORD
484. ources read PI_PEND to determine which source caused the interrupt On the 8XC196MC the waveform generator is the sole source for this interrupt ttt SIO 0 and SIO 1 can generate this interrupt Write to to enable the interrupt sources read PI_PEND to determine which source caused the interrupt 7 0 8XC196MC NMI EXTINT COMP3 EPA3 7 0 8XC196MD NMI EXTINT 5 4 4 7 0 8 196 WG SPI Ri RIO TH TIO Bit Number Function 7 07 Setting a bit enables the corresponding interrupt The standard interrupt vector locations are as follows Bit Mnemonic Interrupt Standard Vector NMI Nonmaskable Interrupt 203EH EXTINT EXTINT pin 203CH MC MD Multiplexed Peripheral Interrupt 203AH WG MH Waveform Generator 203AH 5 MD EPA Capture Compare Channel 5 2038H SPI MH ttt Serial Port 2038H COMP4 MD EPA Compare Channel 4 2036H MH SIO 1 Receive 2036H EPA4 MD EPA Capture Compare Channel 4 2034H RIO MH SIO 0 Receive 2034H MC MD EPA Compare Channel 3 2032H MH SIO 1 Transmit 2032H EPA3 MC MD EPA Capture Compare Channel 3 2030H TIO MH SIO 0 Transmit 2030H t On the 8XC196MC device bits 4 3 are reserved These bits are undefined 5 22 Figure 5 11 Interrupt Pending 1 INT_PEND1 Register intel STANDARD AND PTS INTERRUPTS PI PEND Address 1FBEH Reset State AAH
485. owerdown else execute reset PSW Flag Settings Z N C V VT ST KEY 1 or2 KEY any value other than 10 2 0 0 0 0 0 0 INCREMENT WORD Increments the value of the word operand by 1 INC wreg DEST lt DEST 1 00000111 wreg PSW Flag Settings intel INSTRUCTION SET REFERENCE Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format INCB INCREMENT BYTE Increments the value of the byte operand by 1 INCB breg DEST lt DEST 1 00010111 breg PSW Flag Settings JBC JUMP IF BIT IS CLEAR Tests the specified bit If the bit is set control passes to the next breg bitno cadd sequential instruction If the bit is clear this instruction adds the program counter the 00110000 breg disp offset between the end of this instruction and the target label effecting the jump The offset NOTE The displacement disp is sign must be in the range of 128 to 127 extended to 16 bits if specified bit 0 then PC lt PC 8 bit disp PSW Flag Settings Z N C V VT ST JBS JUMP IF BIT IS SET Tests the specified bit If the bit is clear control passes to the next JBS breg bitno sequential instruction If the bit is set this
486. own in Figure 15 5 the 3XC196MH has an additional BUSWIDTH setup timing specification This specification Gy indicates how much time an external device has to generate a valid BUSWIDTH signal after ALE falls BUSWIDTH must be held valid until the minimum hold specification for 8 196 MD or Tj for 8 196 has been met Refer to the datasheet for the current T voy and specifications 15 13 8XC196MC MD MH USER S MANUAL intel 15 3 2 16 bit Bus Timings When the microcontroller is configured to operate in the 16 bit bus width mode lines AD15 0 form a 16 bit multiplexed address data bus Figure 15 6 shows an idealized timing diagram for the external read and write cycles Comprehensive timing specifications are shown in Figure 15 22 on page 15 32 The rising edge of the address latch enable ALE signal indicates that the microcontroller is driv ing an address onto the bus AD15 0 The microcontroller presents a valid address before ALE falls The ALE signal is used to strobe a transparent latch such as a 74AC373 which captures the address from AD15 0 and holds it while the bus controller puts data onto AD15 0 For 16 bit read cycles the bus controller floats the bus and then drives RD low so that it can receive data The external memory must put data Data In onto the bus before the rising edge of RD The datasheet specifies the maximum time the memory device has
487. p breg 8XC196MC MD MH USER S MANUAL intel Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format CMPL COMPARE LONG Compares the DEST SRC magnitudes of two double word long CMPL Direg Slreg operands The operands are specified usin the direct adding mode The flags are i 11000101 5 Dlreg altered but the operands remain unaffected If a borrow occurs the carry flag is cleared otherwise it is set DEST SRC PSW Flag Settings Z N C V VT ST 1 DEC DECREMENT WORD Decrements the value DEST of the operand by one DEC wreg DEST lt DEST 1 00000101 wreg PSW Flag Settings DECB DECREMENT BYTE Decrements the value DEST of the operand by one DECB breg DEST lt DEST 1 00010101 breg PSW Flag Settings DISABLE INTERRUPTS Disables interrupts Interrupt calls cannot occur after DI his instruction cepa 11111010 Interrupt Enable PSW 1 lt 0 PSW Flag Settings intel INSTRUCTION SET REFERENCE Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format DIV DIVIDE INTEGERS Divides the contents of the destination long integer operand by the contents of the sour
488. p23 EPA3 MC MD yo EPA COMPS 2 4 2 5 1 2 6 COMP2 MD 2 7 SCLK1 MH 1 0 SIO BCLK1 MH SIO P5 0 ALE ADV Bus controller P5 1 INST Bus controller P5 2 WR WRL Bus controller P5 3 RD Bus controller P5 4 ONCE Bus controller P5 5 BHE WRH Bus controller P5 6 READY Bus controller P5 7 BUSWIDTH Bus controller P7 0 MD EPA4 yo EPA P7 1 MD 5 yo EPA P7 2 MD COMP4 P7 3 5 P7 4 MD 7 5 MD P7 6 MD P7 7 MD FREQOUT Frequency generator PORTS 6 5 8XC196MC MD MH USER S MANUAL intel Table 6 5 lists the registers associated with the bidirectional ports Each port has three control reg isters MODE Px DIR and Px REG they can be both read and written The PIN regis ter is a status register that returns the logic level present on the pins it can only be read The registers for the standard ports are byte addressable and can be windowed The port 5 registers must be accessed using 16 bit addressing and cannot be windowed Bidirectional Port Consid erations on page 6 12 discusses special considerations for reading P2 REG 7 and P6 REG 7 4 Table 6 5 Bidirectional Port Control and Status Registers Mnemonic Address Description P1 DIR MH 1F9BH Port x Direction Bein
489. page 6 4 MC MD Bidirectional Port Pin Configurations on page 6 9 and Bidirectional Port Considerations on page 6 12 MH Port 2 Bidirectional Port Pin Configurations on page 6 9 and Bidirectional Port Considerations on page 6 12 Ports 3 and 4 Bidirectional Ports 3 and 4 Address Data Bus Operation on page 6 15 Port 5 Bidirectional Port Pin Configurations on page 6 9 and Bidirectional Port Considerations on page 6 12 Port 6 Configuring Output only Port Pins on page 6 17 Port 7 MD Bidirectional Port Pin Configurations on page 6 9 and Bidirectional Port Considerations on page 6 12 13 2 intel MINIMUM HARDWARE CONSIDERATIONS Note 1 20 pF 20 pF XTAL2 XTAL1 RESET Voc Note 2 NMI BUSWIDTH Port 5 Bus Control Note 4 Input only Port Pins Note 5 8XC196 Device Notes 1 See the datasheet for the oscillator frequency range Fxr4 4 and the crystal manufacturer s datasheet for recommended load capacitors 2 The number of and Vss pins varies with package type see datasheet Be sure to connect each pin to the supply voltage and each Vss pin to ground 3 Connect the RC network to Vpp only if powerdown mode will be used Otherwise connect Vpp to 4 No connection is required 5 Tie all input only port pins to Vas A2643 03 Figure 13 1 Minimum Hardware Connections 13 3 8XC196MC MD MH USER S MANUAL intel 13 2 APPLYING
490. pare channels or COMPx CON compare only channels an event time register EPAx TIME capture compare channels or COMPx TIME compare only channels and a timer input Figure 11 5 The con trol register selects the timer the mode and either the event to be captured or the event that is to occur The event time register holds the captured timer value in capture mode and the event time in compare mode See Programming the Capture Compare Channels on page 11 18 and Pro gramming the Compare only Channels on page 11 22 for configuration information Timer Counter Unit External clocking T1CLK with up to 6 bit prescaler clocking timer Quadrature clocking through T1CLK and T1DIR with up to 6 bit prescaler Clock on TIMER overflow TIMER2 Reload Waveform Generator Start A D 00 Control _ Mode Selection SE eae mue e ees Capture Compare uffer B A Compare Reset Timer 1 EPA2 and EPA4 EPA1 and 5 A0807 01 Figure 11 5 A Single EPA Capture Compare Channel 11 4 1 Operating in Capture Mode In capture mode when a valid event occurs on the pin the value of the selected timer 15 captured into a buffer The timer value is then transferred from the buffer to the EPAx TIME register which sets the EPA interrupt pending bit as shown i
491. patibility with future devices write zero to these bits C 57 8XC196MC MD MH USER S MANUAL intel WATCHDOG WATCHDOG Address OAH Reset State XXH Unless it is cleared every 64K state times the watchdog timer resets the device To clear the watchdog timer send followed immediately by E1H to location OAH Clearing this register the first time enables the watchdog with an initial value of 0000 which is incremented once every state time After it is enabled the watchdog can be disabled only by a reset The WDE bit bit 3 of CCR1 controls whether the watchdog is enabled immediately or is disabled until the first time it is cleared Clearing WDE activates the watchdog Setting WDE makes the watchdog timer inactive but you can activate it by clearing the watchdog register Once the watchdog is activated only a reset can disable it 7 0 Watchdog Timer Value Bit Number Function 7 0 Watchdog Timer Value This register contains the 8 most significant bits of the current value of the watchdog timer C 58 intel REGISTERS WG COMPx WG COMPx Address 1FC2H 1FC4H 1FC6H xz 1 3 Reset State 0000H The phase compare WG register controls the duty cycle of each phase Write a value to each phase compare register to specify the length of time that the associated outputs will remain asserted Changing the WG RELOAD value changes both
492. performed concurrently low word DEST lt DEST SRC high word DEST lt DEST MOD SRC PSW Flag Settings TR qe DEST SRC DIVU lreg waop 100011 waop 8XC196MC MD MH USER S MANUAL intel Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format DIVUB DIVIDE BYTES UNSIGNED This instruction DEST SRC divides the contents of the destination word piyvyB wreg baop operand by the contents of the source byte operand using unsigned arithmetic It stores 100111 baop wreg the quotient into the low order byte i e the byte with the lower address of the destination operand and the remainder into the high order byte The following two statements are performed concurrently low byte DEST lt DEST SRC high byte DEST lt DEST MOD SRC PSW Flag Settings zr ieee DJNZ DECREMENT AND JUMP IF NOT ZERO Decrements the value of the byte operand by DJNZ breg cadd 1 If the result is 0 control passes to the next sequential instruction If the result is not 0 11100000 breg disp the instruction adds to the program counter the offset between the end of this instruction ien le ei and the target label effecting the jump The NOTE PO a MP offset must be in the range of 128 to 127 COUNT lt COUNT 1 if COUNT
493. pin as a special function signal set In this way initialization fault recovery exception handling etc can be done without changing the operation of the associated peripheral intel EVENT PROCESSOR ARRAY EPA Table 11 3 EPA Control and Status Registers Continued Mnemonic Address MD MH Description MASK 1FBCH 1FBCH 1FBCH Peripheral Interrupt Mask The bits in this register enable and disable mask the timer 1 and 2 overflow underflow interrupt requests the waveform generator interrupt request MC MD the EPA compare only channel 5 interrupt request MD and the serial port error interrupts MH PI PEND 1FBEH 1FBEH 1FBEH Peripheral Interrupt Pending Any bit set indicates a pending interrupt request T1CONTROL 1F78H 1F78H 1F78H Timer 1 Control This register enables disables timer 1 controls whether it counts up or down selects the clock Source and direction and determines the clock prescaler setting T1RELOAD 1F72H 1F72H 1F72H Timer 1 Reload This register contains an initialization value for timer 1 A timer 1 overflow or underflows loads the T1RELOAD value into the 1 register if both quadrature clocking and the reload function are enabled T1 CONTROL 5 0 1 T2CONTROL 1F7CH 1F7CH 1F7CH Timer 2 Control This register enables disables timer 2 controls whether it co
494. progress and inhibits further receptions To avoid a partial or undesired reception clear this bit before clearing the RI flag in SPx_STATUS This can be handled in an interrupt environment by using software flags or in straight line code by using the interrupt pending register to signal the completion of a reception 2 PEN Parity Enable In modes 1 and 3 setting this bit enables the parity function This bit must be cleared if mode 2 is used When this bit is set TB8 takes the parity value on transmissions and SPx_STATUS 7 becomes the receive parity error bit 1 0 1 0 Mode Selection These bits along with bit 7 select the communications mode M2 1 0 0 0 0 synchronous mode 0 X 0 1 mode 1 X 1 0 mode 2 X 1 1 mode 3 1 0 0 synchronous mode 4 C 51 8XC196MC MD MH USER S MANUAL intel SPx STATUS SPx STATUS x 0 1 8XC196MH Address 1F81H 1F89H Reset State 00H The serial port status SPx STATUS register contains bits that indicate the status of serial port x 7 0 8XC196MH RPE RB8 RI TI FE TXE OE Bit Bit 2 Number Mnemonic Function 7 RPE RB8 Received Parity Error Received Bit 8 RPE is set if parity is disabled SPx CON 2 0 and the ninth data bit received is high RB8 is set if parity is enabled SPx CON 2 1 and a parity error occurred Reading SPx STATUS clears this bit 6 RI Receive Interrupt Thi
495. ps 66 ADD Indirect 2 ops 67 ADD Indexed 2 ops 68 SUB Direct 2 ops 69 SUB Immediate 2 ops 6A SUB Indirect 2 ops 6B SUB Indexed 2 ops 6C MULU Direct 2 ops 6D MULU Immediate 2 ops A 42 lel Table A 7 Instruction Opcodes Continued INSTRUCTION SET REFERENCE Hex Code Instruction Mnemonic 6E MULU Indirect 2 ops 6F MULU Indexed 2 ops 70 ANDB Direct 2 ops 71 ANDB Immediate 2 ops 72 ANDB Indirect 2 ops 73 ANDB Indexed 2 ops 74 ADDB Direct 2 ops 75 ADDB Immediate 2 ops 76 ADDB Indirect 2 ops 77 ADDB Indexed 2 ops 78 SUBB Direct 2 ops 79 SUBB Immediate 2 ops 7A SUBB Indirect 2 ops 7B SUBB Indexed 2 ops 7 MULUB Direct 2 ops 7D MULUB Immediate 2 ops 7E MULUB Indirect 2 ops 7F MULUB Indexed 2 ops 80 OR Direct 81 OR Immediate 82 OR Indirect 83 OR Indexed 84 XOR Direct 85 XOR Immediate 86 XOR Indirect 87 XOR Indexed 88 CMP Direct 89 CMP Immediate 8A CMP Indirect 8B CMP Indexed 8C DIVU Direct 8D DIVU Immediate 8E DIVU Indirect 8F DIVU Indexed 90 ORB Direct 91 ORB Immediate 92 ORB Indirect 93 ORB Indexed 94 XORB Direct 95 XORB Immediate 96 XORB Indirect A 43 8XC196MC MD MH USER S MANUAL Table A 7 Instruction Opcodes Continued
496. pt 3 11 5 4 5 6 5 9 Units of measure defined 1 5 Universal asynchronous receiver and transmitter See UART UPROM 16 6 programming 16 6 16 7 USFR 16 7 V 13 1 B 21 and programming modes 16 14 13 1 14 2 16 13 B 21 and programming modes 16 14 Vapp 12 5 13 1 B 21 13 1 B 21 and programming modes 16 14 W Wait states 15 17 15 20 controlling 15 18 Watchdog timer 2 11 3 11 3 12 13 9 13 12 and idle mode 14 5 selecting reset interval 13 13 Watchdog timer register C 58 Waveform generator 9 1 9 25 block diagram 9 2 control and protection circuitry 9 5 dead time INDEX and duty cycle 9 19 generator circuitry 9 5 design considerations 9 19 9 20 EXTINT interrupts and protection circuitry 9 21 interrupts 9 20 operating modes 9 7 9 11 center aligned 9 8 9 9 9 10 edge aligned 9 8 9 10 9 11 overview 9 1 phase driver channels 9 5 programming 9 12 9 20 carrier period 9 16 EXTINT interrupts 9 15 outputs 9 12 63 65 protection circuitry 9 15 programming example 9 21 9 25 protection circuitry 9 6 register buffering and synchronization 9 6 9 7 updates 9 8 registers 9 3 9 4 signals 9 3 status 9 19 timebase generator 9 4 Waveform generator control register 9 18 C 60 Waveform generator counter register 9 19 C 61 Waveform generator output configuration register 9 13 C 63 Waveform generator reload register 9 16 C 67 Waveform prote
497. r bytes ahead of the CPU program counter the bus controller might prevent code execution from the last four bytes of internal memory The interrupt vectors and CCBs are not read protected because interrupts can occur even when executing from external memory 16 3 1 2 Controlling Access to the OTPROM During Programming Modes For programming modes three levels of protection are available prohibit all programming prohibit all programming but permit authorized ROM dumps permit authorized ROM dumps auto programming and slave programming 16 4 intel PROGRAMMING THE NONVOLATILE MEMORY These protection levels are provided by the PCCBO lock bits the CCBO lock bits and the internal security key Table 16 3 When entering programming modes the reset sequence loads the PCCBs into the chip configuration registers It also loads CCBO into internal RAM to provide an additional level of security You can program the CCBs using any of the programming methods but only slave and PCCB programming modes permits access to the PCCBs and only slave and auto programming allow you to program the internal security key Table 16 3 Memory Protection Options for Programming Modes Genz Coons Security Key Programmed Protection Status 2 i 1 1 1 1 No No protection All programming modes allowed 1 X 0 X Yes All programming disabled ROM dump permitted with matching se
498. r didt br oe etae s 4 2 4 1 4 Special purpose Memory 459 4 1 4 1 Reserved Memory Locations 4 3 4 1 4 2 Interrupt and PTS Vectors 4 3 4 43 Security Key neto pter oppo ee o le eee 4 4 4 1 4 4 Chip Configuration Bytes 4 4 4 1 5 Special function Registers SFRS 4 4 intel CONTENTS 4 1 5 1 Memory mapped SERS niiair nnana ene rante den edente bd den 4 5 4 7 5 2 Peripheral metet d et dake Ea Etpe fa tie i 4 5 4 1 6 Register File Haee ecu ene Per ee rre eee 4 9 4 1 6 1 General purpose Register 4 10 4 1 6 2 Stack Pointer SP eee Cle n de ey a enters 4 10 4 1 6 3 CPU Special function Registers SFRS esed 4 2 4 12 4 2 1 Selecting a Aten Saeed 4 13 4 2 2 Addressing a Location Through a Window 2 4 14 4 2 2 1 32 Windowing Example emn 4 16 4 2 2 2 64 byte Windowing Example emen 4 16 4 2 2 3 128 byte Windowing Example ee Moe e te dco 4 2 24 Unsupported Locations Windowing Example 4 16 4 2 2 5 Using the Linker Locator to Set Up 4 17 4 2 3 Windowing and Addressing Modes 4 19 CHAPTER 5 STANDARD AND PTS INTERRUPTS 5 1 OVERVIEW
499. r receive data Figure 5 20 PTS Control Block 2 Serial I O Mode Continued 5 6 6 1 Synchronous SIO Transmit Mode Example In synchronous serial I O SSIO transmit mode an EPA channel controls the transmission baud rate by generating or capturing a serial clock signal SCK To generate the SCK signal configure the EPA channel in compare mode and set the output pin toggle option Whenever a match occurs between the EPA event time register and a timer register the EPA channel toggles SCK and gen erates an interrupt If an external source will provide the SCK signal configure the EPA channel in capture mode with capture on either edge set In this case the EPA channel generates an inter rupt whenever the SCK input toggles On every other EPA interrupt the PTS shifts a data bit out onto a port pin that is configured to function as the Transmit Data signal TXD PTSCONI Fig ure 5 19 on page 5 38 controls whether the transmission occurs on even or odd PTS cycles Be cause transmissions occur only on a rising or falling clock edge two PTS cycles occur for every one data bit transmission Figure 5 21 It takes 16 PTS cycles to transmit eight data bits In SSIO transmit mode only data bits can be transmitted parity and stop bits are not included End of PTS Conventional 16 PTS Serviced Interrupts inem V interrupts TL TL T m m m nm n nm rm m rnm rnm n Pen ee
500. r register files differently The lower register file is always directly accessible with direct addressing see Addressing Modes on page 3 5 The upper reg ister file is accessible with direct addressing only when windowing is enabled Windowing is a technique that maps blocks of the upper register file into a window in the lower register file See Chapter 4 Memory Partitions for more information about the register file and windowing 2 3 3 Register Arithmetic logic Unit RALU The RALU contains the microcode engine the 16 bit arithmetic logic unit ALU the master pro gram counter PC the processor status word PSW and several registers The registers in the RALU are the instruction register a constants register a bit select register a loop counter and three temporary registers the upper word lower word and second operand registers The PSW contains one bit PSW 1 that globally enables or disables servicing of all maskable in terrupts one bit PSW 2 that enables or disables the peripheral transaction server PTS and six Boolean flags that reflect the state of your program Appendix A Instruction Set Reference provides a detailed description of the PSW All registers except the 3 bit bit select register and the 6 bit loop counter are either 16 or 17 bits 16 bits plus a sign extension Some of these registers can reduce the ALU s workload by per forming simple operations intel ARCHITECTURAL OVERVIEW The R
501. r to PTS Execution NORMI J NORML Control Block Ims fers f 7 EXTINE nterrupt Routine Pending Set Cleared Interrupt Latency Time Response Time amp 43 State Times gt A0142 01 Figure 5 5 PTS Interrupt Response Time 8XC196MC MD MH USER S MANUAL Table 5 4 Execution Times for PTS Cycles PTS Mode Execution Time in State Times Single transfer mode register register memory registert memory memory 18 per byte or word transfer 1 21 per byte or word transfer 1 24 per byte or word transfer 1 Block transfer mode register register memory registert memory memory 13 7 per byte or word transfer 1 minimum 16 7 per byte or word transfer 1 minimum 19 7 per byte or word transfer 1 minimum A D scan mode register register register memory 21 25 ASIO receive mode MC MD only Majority disabled Majority enabled 24 2 if parity enabled 36 sample time second sample 36 7 sample time third sample 36 2 if parity enabled ASIO transmit mode MC MD only 29 3 if parity enabled SSIO receive mode MC MD only 29 receive data bit 21 no reception SSIO transmit mode MC MD only 30 transmit data bit 20 no transmission Register indicates an access to the register file or peripheral SFR Memory indicates an access to memory mapped register I O or memory See Table 4
502. rand Type 3 1 Equivalent Operand Types for Assembly and C Programming Languages 3 2 Definition of Temporary 3 6 Memory ie eee n ra e elie Seed 4 2 Special purpose Memory 0 4 3 Memory mapped SERS ace expri d eer geen oe He Ere 4 5 Peripheral SFRs 8 196 rete tiani tert 4 6 Peripheral SFRs 8 196 0 4 7 Peripheral SFRs 8XC196MH eese entente tenni 4 8 Register File Memory Addresses eee 4 10 ek cathe hiec riot nte tere abe an 4 11 Selecting a Window of Peripheral SFRs sse 4 13 Selecting a Window of the aad ee 4 14 Windows TE indes Halo Windowed Base Addresses 4 15 Interr pt Signals 5 3 Interrupt and PTS Control and Status 5 3 Interrupt Sources Vectors and 5 5 Execution Times for PTS 5 12 Single Transfer Mode esee tentent th
503. rating Analog Outputs PWM modules can generate a rectangular pulse train that varies in duty cycle and period Filter ing this output will create a smooth analog signal To make a signal swing over the desired analog range first buffer the signal and then filter it with either a simple RC network or an active filter Figure 10 7 is a block diagram of the type of circuit needed to create the smooth analog signal MCS 96 Buffer Filter Power Microcontroller to Make Passive Amp Output Swing or Analog PWM Rail Active Optional Output to Rail Optional A2391 01 Figure 10 7 D A Buffer Block Diagram Figure 10 8 shows a sample circuit used for low output currents less than 100 uA Consider temperature and power supply drift when selecting components for the external D A circuitry With proper components a highly accurate 8 bit D A converter can be made using the PWM Analog Output Hes 74 C Op Amp icrocontroller Buffer Consider both ripple and response time requirements when selecting R A2390 02 Figure 10 8 PWM to Analog Conversion Circuitry 10 10 intel I1 Event Processor Array EPA intel CHAPTER 11 EVENT PROCESSOR ARRAY EPA Control applications often require high speed event control For example the controller may need to periodically generate pulse width modulated outputs or an interrupt In another application the controller may monitor an input
504. re the result into the EPA time register This sets up the timing for the first interrupt and causes the first bit transmission to occur at the proper baud rate The following example uses P2 0 to output the data TXD and EPAO to control the baud rate It sets up an asynchronous serial I O PTS routine that transmits 16 bytes with eight data bits one parity bit and one stop bit at 9600 baud This example uses several user defined registers T COUNT defines the number of bytes to transfer and TXDDONE is a flag that is set when all bytes are transferred 1 Disable the interrupts and the PTS Use the DI instruction to disable all standard interrupts and the DPTS instruction to disable the PTS 2 Set up the stack pointer 3 Reset all interrupt mask registers Clear INT_MASK INT MASKland PI_MASK 4 Initialize P2 0 to function as TXD Clear P2_DIR 0 selects output Clear P2 MODE 0 selects LSIO function Set P2_REG 0 initializes TXD output to 1 5 51 8XC196MC MD MH USER S MANUAL intel 5 Initialize and enable the timer select up counting internal clock and prescaler disabled Set bits 6 and 7 Figure 11 8 on page 11 16 6 Initialize the PTSCB as shown in Table 5 15 Table 5 15 ASIO Transmit Mode PTSCBs PTSCB1 PTSCB2 PTSVEC H pointer to PTSCB2 Unused PTSVEC L pointer to PTSCB2 SAMPTIME unused BAUD H 01H 9600 baud at 16 MHz
505. rect location 1 start stop bit 1 000165 mask 1 10 shift to correct location temp1 combine into temp 1 dead time p1 03ffh mask to 10 bits 1 combine into temp WG_CONTROL 0 Store WG_CONTROL KKKKKKKKKKKKKKKKKKKKKKKK D and WG_COMPx registers kk ck ck ck ck ck ck KKK KKK KKK KKK KK KK oad WG_RELOAD 0 pl _ 1 0 2 _ 2 0 p3 WG_COMP3 0 ptions get sample control bit and shl 1 shl or ra and shl or 1 or stb ret tem tem tem tem tem tem tem tem tem tem tem tem tem tem 0001h 3 pl it 1 00015 1 2 p templ pl dp pl 0001h pl 1 temp1 1 pl 000185 p templ shi WAVEFORM GENERATOR k ft to correct location interrupt type bit mas shi k ft to correct location combine into temp disable protection bit mas shi k ft to correct location combine into temp ena mas ble output bit k combine into temp p WG PROTECT 0 store byte into WG PROTECT DRA EEK EKA EERE interrupt routine for PERE L ERE AE col see eol Baa Be Aa cseg at Ofla0h pusha call call call call popa ret end wgout loadregs protect wgcon demo board PI interrupt update W
506. repeats the pulse until PROG is deasserted In slave programming mode the PALE signal controls the pulse width In all cases the pulse width must be at least 100 us for successful programming 16 10 intel PROGRAMMING THE NONVOLATILE MEMORY 16 6 PROGRAMMING MODE PINS Figure 16 4 illustrates the signals used in programming and Table 16 6 describes them The EA and PMODE pins combine to control entry into programming modes You must configure the PMODE P0 7 4 pins to select the desired programming mode see Table 16 7 on page 16 13 Each programming routine configures the port 2 pins to operate as the appropriate spe cial function signals Ports 3 and 4 automatically serve as the PBUS during programming Programming Voltage PMODE 3 0 Vpp P0 7 4 8XC196 Device P4 7 0 P3 7 0 PBUS P2 7 PACT P2 6 CPVER P2 4 AINC P2 2 PROG P2 1 PALE P2 0 PVER A2839 02 Figure 16 4 Pin Functions in Programming Modes Table 16 6 Pin Descriptions Special Program Port Pin function Type ming Description Signal Mode 7 4 PMODE 3 All Programming Mode Select 0 Determines the programming mode PMODE is sampled after a device reset and must be static while the part is operating Table 16 7 on page 16 13 lists the PMODE values and programming modes P2 0 PVER Slave Programming Verification Auto During slave or auto programming PVER is updated after each p
507. ring the address phase of the bus cycle address bits 0 15 are presented on the bus and can be latched using ALE or ADV During the data phase 8 or 16 bit data is trans ferred AD7 0 are multiplexed with P3 7 0 and PBUS 7 0 AD15 8 are multiplexed with P4 7 0 and PBUS 15 8 ADV Address Valid This active low output signal is asserted only during external memory accesses ADV indicates that valid address information is available on the system address data bus The signal remains low while a valid bus cycle is in progress and is returned high as soon as the bus cycle completes An external latch can use this signal to demultiplex the address from the address data bus A decoder can also use this signal to generate chip selects for external memory ADV is multiplexed with P5 0 and ALE B 13 8XC196MC MD MH USER S MANUAL intel Table B 6 Signal Descriptions Continued Name Type Description AINC Auto Increment During slave programming this active low input enables the auto increment feature Auto increment allows reading or writing of sequential OTPROM locations without requiring address transactions across the PBUS for each read or write AINC is sampled after each location is programmed or dumped If AINC is asserted the address is incremented and the next data word is programmed or dumped AING is multiplexed with P2 4 and COMPO ALE Address Latch Enable This activ
508. ripheral interrupt mask Pl MASK register enables or disables masks interrupt requests associated with the peripheral interrupt the serial port interrupt SPI and the overflow underflow timer interrupt OVRTM 7 0 8XC196MC WG OVRTM2 OVRTM1 7 0 8XC196MD 5 WG OVRTM2 OVRTM1 7 0 8XC196MH SP1 SPO OVRTM2 OVRTM1 sta ince Function 7 5 3 1 Reserved for compatibility with future devices write zeros to these bits 6 MC Reserved for compatibility with future devices write zero to this bit COMP5 EPA Compare Channel 5 Setting this bit enables the EPA compare channel 5 interrupt The EPA compare channel 5 and the waveform generator interrupts are associated with the peripheral interrupt Pl Setting INT_MASK1 5 enables SP1 MH Serial Port 1 Error Setting this bit enables the serial port 1 error interrupt The serial port 1 and serial port 0 error interrupts are associated with the serial port interrupt Setting INT_MASK1 4 enables SPI 4 WG MC MD Waveform Generator Setting this bit enables the waveform generator interrupt The waveform generator and the EPA compare channel 5 interrupts are associated with the peripheral interrupt Pl Setting INT_MASK1 5 enables SPO MH Serial Port 0 Error Setting this bit enables the serial port 0 error interrupt The serial port 0 and serial port
509. riting these locations through a window has no effect Table 4 12 Windowed Base Addresses WSR Windowed Base Address Base Address in Lower Register File Window Size 32 byte 00 64 byte 00COH 128 byte 0080H 4 15 8XC196MC MD MH USER S MANUAL intel Appendix C includes a table of the windowable SFRs with the WSR values and direct addresses for each window size The following examples explain how to determine the WSR value and di rect address for any windowable location An additional example shows how to set up a window by using the linker locator 4 2 2 1 32 byte Windowing Example Assume that you wish to access location 014BH a location in the upper register file used for gen eral purpose register RAM with register direct addressing through a 32 byte window Table 4 11 on page 4 15 shows that you need to write 4AH to the window selection register It also shows that the base address of the 32 byte memory area is 0140H To determine the offset subtract that base address from the address to be accessed 014BH 0140H 000BH Add the offset to the base address of the window in the lower register file 00 from Table 4 12 The direct ad dress is OOEBH 000BH 00 4 2 2 2 64 byte Windowing Example Assume that you wish to access CONTROL register location IFCCH with register di rect addressing through a 64 byte window Table 4 11 shows that you need to write 3FH to t
510. rives the address data bit onto the pin The address data bit replaces your output during this time When the external access is completed the device restores your data onto the pin 6 14 intel PORTS 6 4 1 Bidirectional Ports and 4 Address Data Bus Operation Figure 6 3 shows the ports 3 and 4 logic During reset the active low level of RESET turns off and Q2 and turns on transistor which weakly pulls the pin high Q1 can source at least 3 mA at 0 7 volts Q2 can sink at least 3 mA at 0 45 volts and can source approximately 10 uA at 1 0 volts Consult the datasheet for exact specifications During normal opera tion an internal control signal BUS CONTROL SELECT controls the port When the microcontroller needs to access external memory it clears BUS CONTROL SELECT which selects address data as the input to the multiplexer Address data then drives Q1 and Q2 as complementary outputs When external memory access is not required the microcontroller sets BUS CONTROL SE LECT which selects Px REG as the input to the multiplexer Px REG then drives Q1 and Q2 as open drain outputs Open drain outputs require external pull up resistors In this configuration a port pin can be used as an input The signal on the pin is latched in the Px_PIN register The pins can be read making it easy to see which pins are driven low by the microcontroller and which are driven high by external dri
511. rocontroller Systems for Electrically Noisy Environments 210313 AP 155 Oscillators for Microcontrollers 111 230659 AR 375 Motor Controllers Take the Single Chip Route article reprint 270056 Included in Automotive Products handbook order number 231792 Included in Embedded Applications handbook order number 270648 ttt Included in Automotive Products and Embedded Applications handbooks 1 6 intel GUIDE TO THIS MANUAL Table 1 2 Application Notes Application Briefs and Article Reprints Continued Title Order Number 406 MCS 96 Analog Acquisition Primer ttt 270365 AP 445 8XC196KR Peripherals A User s Point of View 270873 AP 449 A Comparison of the Event Processor Array EPA and High Speed 270968 Input Output HSIO Unit AP 475 Using the 8XC196NT 11 272315 AP 477 Low Voltage Embedded Design 272324 AP 483 Application Examples Using the 8XC196MC MD Microcontroller 272282 AP 700 Intel Fuzzy Logic Tool Simplifies ABS Design 1 272595 AP 711 EMI Design Techniques for Microcontrollers in Automotive Applications 272324 AP 715 Interfacing an Serial EEPROM to an MCS 96 Microcontroller 272680 Included in Automotive Products handbook order number 231792 tt Included in Embedded Applications handbook order number 270648 tit Included in Automotive Products and Embedded Applications handbooks Table 1 3 MCS 96 Microcontroller Datasheets Commercial Expr
512. rogramming pulse A high output signal indicates successful programming of a location while a low signal indicates a detected error P2 1 PALE Slave Programming ALE Input During slave programming a falling edge causes the device to read acommand and address from the PBUS 16 11 8XC196MC MD MH USER S MANUAL intel Table 16 6 Pin Descriptions Continued Port Pin Special Program function Type ming Description Signal Mode P2 2 PROG Slave Programming During programming a falling edge latches data on the PBUS and begins programming while a rising edge ends programming The current location is programmed with the same data as long as PROG remains asserted so the data on the PBUS must remain stable while PROG is active During a word dump a falling edge causes the contents of an OTPROM location to be output on the PBUS while a rising edge ends the data transfer P2 4 AINC Slave Auto increment During slave programming this active low input enables the auto increment feature Auto increment allows reading or writing of sequential OTPROM locations without requiring address transactions across the PBUS for each read or write AINC is sampled after each location is programmed or dumped If AINC is asserted the address is incremented and the next data word is programmed or dumped P2 6 CPVER Slave Cumulative Program Verification During slave programming a h
513. rovide access to the peripheral SFRs Table 4 6 on page 4 8 Table 4 6 on page 4 8 and Table 4 6 on page 4 8 list the peripheral SFRs of the 8 196 8XC196MD and 8XC196MH respectively Locations that are omitted from the tables are reserved The pe ripheral SFRs are I O control registers they are physically located in the on chip peripherals These peripheral SFRs can be windowed and they can be addressed either as words or bytes ex cept as noted in the tables The peripheral SFRs are accessed directly without using the memory controller so instructions that operate on these SFRs execute as they would if they were operating on the register file 8XC196MC MD MH USER S MANUAL Table 4 4 Peripheral SFRs 8XC196MC intel Port 2 SFRs EPA and Timer SFRs Address High Odd Byte Low Even Byte Address High Odd Byte Low Even Byte 1FDEH Reserved Reserved HF7EH 2 2 L 1F7CH Reserved T2CONTROL 1FD6H Reserved P2 PIN HF7AH TIMER TIMER L 1FD4H Reserved P2_REG 1F78H Reserved T1CONTROL 1FD2H Reserved P2 DIR 1F76H Reserved Reserved 1FDOH Reserved P2 MODE 1F74H Reserved Reserved Waveform Generator SFRs 1F72H T1RELOAD H T1RELOAD L Address High Odd Byte Low Even Byte 1F70H Reserved Reserved 1FCEH Reserved PROTECT 1FCCH WG_CONT
514. rray Capture Compare Channels High speed input output signals for the EPA capture compare channels EPA5 0 are multiplexed as follows EPAO P2 0 PVER EPA1 P2 1 PALE MC MD EPA1 P2 2 PROG MH EPA2 P2 2 PROG EPA3 P2 3 EPA4 P7 0 and 5 7 1 5 4 are not implemented on the 8XC196MC and EPA5 2 not implemented on the 8XC196MH EXTINT External Interrupt This programmable interrupt is controlled by the WG_PROTECT register This register controls whether the interrupt is edge triggered or sampled and whether a rising edge high level or falling edge low level activates the interrupt In powerdown mode asserting the EXTINT signal for at least 50 ns causes the device to resume normal operation The interrupt need not be enabled If the EXTINT interrupt is enabled the CPU executes the interrupt service routine Otherwise the CPU executes the instruction that immediately follows the command that invoked the power saving mode In idle mode asserting any enabled interrupt causes the device to resume normal operation FREQOUT MD only Frequency Generator Output A fixed 50 duty cycle waveform that can vary in frequency from 4 KHz to 1 MHz assuming Fyz4 16 MHz FREQOUT is multiplexed with P7 7 FREQOUT is not implemented on the 8XC196MC or MH INST Instruction Fetch This active high output signal is valid only during external memory bus cycles When high INST indicates that an i
515. rs are designed to handle high speed calculations and fast input output I O operations They share a common architecture and instruction set with other members of the MCS 96 microcontroller family NOTE This manual describes a family of microcontrollers For brevity the name 8 196 is used when the discussion applies to all family members When information applies to specific microcontrollers individual product names are used 2 1 TYPICAL APPLICATIONS MCS 96 microcontrollers are typically used for high speed event control systems Commercial applications include modems motor control systems printers photocopiers air conditioner con trol systems disk drives and medical instruments Automotive customers use MCS 96 microcon trollers in engine control systems airbags suspension systems and antilock braking systems ABS 2 2 MICROCONTROLLER FEATURES Table 2 1 lists the features of each member of the 8XC196Mx family 8XC196MC MD MH USER S MANUAL intel Table 2 1 Features of the 8XC196Mx Product Family OTPROM Register SIO PWM External Device Pins HOM Ports Channels Interrupt Bytes Bytes Pins Pins Note 3 Note 4 Channels Pins Note 1 Note 2 8XC196MH 84 32K 744 52 6 2 8 8 1 8XC196MH 80 32K 744 52 6 2 8 8 1 8XC196MH 64 32K 744 50 6 2 7 8 1 8XC196MC 84 16K 488 53 8 0 8 13 1 8 196 80 16 488 53 8 0 8 13 1 8 196 64 16 488 49 7
516. rt receive error interrupt You must read the PEND register to determine which channel generated the interrupt P1 DIR 1F9BH Port 1 Direction This register selects the direction of each port 1pin Set P1 DIR 1 and P1 DIR S to configure RXDO P1 1 and RXD1 P1 3 as high impedance inputs open drain outputs and clear P1 DIR 0 and P1 DIR 2 to configure TXDO P1 0 and TXD1 P1 2 as comple mentary outputs P1 MODE 1F99H Port 1 Mode This register selects either the general purpose input output function or the peripheral function for each pin of port 1 Set Pl MODE 3 0 to configure TXDO P1 0 TXD1 P1 2 RXDO P1 1 and RXD1 P1 3 for the SIO port P1 PIN 1F9FH Port 1 Pin State Four bits of this register contain the values of the TXDO P1 0 RXDO P1 1 TXD1 P1 2 and RXD1 P1 3 pins Read P1 PIN to determine the current value of the TXDx and RXDx pins P1 REG 1F9DH Port 1 Output Data This register holds data to be driven out on the pins of port 1 Set P1 REG 1 and P1 REG 3 for the RXDx pins Set P1 REG 0 and P1 REG 2 for the TXDx pins P2 DIR 1FD2H Port 2 Direction This register selects the direction of each port 2 pin To use BCLKx as the baud rate generator clock source for modes 0 3 or to use mode 4 in which case is the shift clock set P2 DIR 1 and P2 DIR 7 to configure SCLKOZ BCLKO P2 1 and SCLK1 BCLK1 P2 7 as high impedance inputs open drain outputs P2 MODE 1FDOH Port 2 Mode This register sele
517. ruction and the target label extended to 16 bits effecting the jump The offset must be in range of 128 to 127 if VT 2 1 then PC lt PC 8 bit disp PSW Flag Settings Z N C V VT ST 0 LCALL LONG CALL Pushes the contents of the program counter the return address onto cadd the stack then adds to the program counter the offset between the end of this instruction 11101111 disp low disp high and the target label effecting the call The offset must be in the range of 32 768 to 32 767 SP lt SP 2 SP lt PC PC lt PC 16 bit disp PSW Flag Settings LD LOAD WORD Loads the value of the source DEST SRC word operand into the destination operand LD DEST lt SRC wreg waop 101000aa waop wreg PSW Flag Settings LDB LOAD BYTE Loads the value of the source DEST SRC byte operand into the destination operand LDB breg baop DEST lt SRC 101100aa baop breg PSW Flag Settings 2 V VT ST A 23 8XC196MC MD MH USER S MANUAL intel Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format LDBSE LOAD BYTE SIGN EXTENDED Sign DEST SRC extends the value of the source short LDBSE wreg baop integer operand and loads it into the d
518. rved COMPO CON 1FBEH Reserved PEND 1F56H EPA5 TIME H 5 TIME L 1FBCH Reserved PI MASK 1F54H Reserved EPA5 CON 1FBAH Reserved FREQ CNT 1F52H 4 TIME 4 TIME L 1FB8H Reserved FREQ GEN 1F50H Reserved EPA4 CON 1FB6H Reserved PWM COUNT 1F4EH TIME EPAS3 TIME L 1FB4H Reserved PWM_PERIOD 1F4CH Reserved EPA3_CON 1FB2H Reserved PWM1_CONTROL 1F4AH EPA2_TIME H EPA2_TIME L 1FBOH Reserved PWMO CONTROL 1F48H Reserved EPA2 CON A D SFRs 1F46H EPA1 TIME H EPA1 TIME L Address High Odd Byte Low Even Byte 1F44H Reserved EPA1 CON 1FAEH AD TIME AD TEST 1F42H EPAO TIME H EPAO TIME L 1FACH Reserved AD COMMAND 1F40H Reserved EPAO CON 1FAAH AD RESULT H AD RESULT L 1FA8H P1 PIN PO PIN 1F80H Reserved Reserved Must be addressed as a word 4 7 8XC196MC MD MH USER S MANUAL Table 4 6 Peripheral SFRs 8XC196MH intel Port 0 and 2 SFRs Port 1 SFRs Address High Odd Byte Low Even Byte Address High Odd Byte Low Even Byte 1FDEH Reserved Reserved 1F9EH P1_PIN Reserved 1FDCH Reserved Reserved 1F9CH P1_REG Reserved 1FDAH Reserved PO_PIN 1F9AH P1_DIR Reserved 1FD8H Reserved Reserved 1F98H P1_MODE Reserved 1FD6H Reserved P2_PIN 1FD4H Reserved P2_REG Serial
519. ry 15 4 Index 9 8XC196MC MD MH USER S MANUAL FREQ_CNT 8 4 C 22 FREQ_GEN 8 3 C 23 GEN_CON 13 9 C 24 grouped by modules C 1 INT_MASK 5 15 C 25 INT MASKI 5 16 7 2 C 26 INT PEND 5 21 7 3 C 27 INT PENDI 5 22 7 3 28 naming conventions 1 4 ONES REG C 29 PO PIN 6 3 6 4 MODE considerations 6 12 P1 PIN 6 3 6 4 7 3 P2 MODE considerations 6 12 P2 REG considerations 6 12 P5 MODE considerations 6 12 6 13 PI MASK 5 17 7 4 C 35 PI PEND 5 23 7 4 C 37 PPW 16 8 C 39 PSW C 40 PTSSEL 5 14 C 42 PTSSRV 5 26 C 43 PWM COUNT 10 8 C 44 PWM PERIOD 10 6 45 PWMx CONTROL 10 7 C 46 Px DIR 6 6 6 9 6 10 6 11 C 30 Px MODE 6 6 6 9 6 10 6 11 C 31 Px PIN 6 2 6 6 6 7 6 9 6 14 6 16 C 33 Px REG 6 6 6 9 6 10 6 11 6 14 6 16 C 34 RALU 2 4 2 5 4 10 reset values and addresses C 2 SBUFO RX 7 4 SBUFO TX 7 4 SBUFI RX 7 4 SBUFI TX 7 4 SBUFx C 47 SBUFx TX C 48 SP C 49 SP PPW 16 8 SPO BAUD 7 4 SPO CON 7 4 SPO STATUS 7 4 SPI 7 4 Index 10 SPI CON 7 4 SPI STATUS 7 4 SPx BAUD 7 12 C 50 SPx CON 7 10 C 51 SPx STAUS 7 15 C 52 TICONTROL 11 16 C 53 TIRELOAD C 54 T2CONTROL 11 17 C 55 TIMERx C 56 USFR 16 7 C 57 using 3 9 WATCHDOG C 58 WG_COMPx 9 17 C 59 WG CONTROL 9 18 C 60 WG_COUNTER 9 19 C 61 WG OUTPUT port 6 6 17 6 18 C 62 WG OUTPUT waveform generator 9 13 C 63 WG_PROTECT 9 15 C 66 WG RELOAD
520. s Edge aligned Modes Load WG_COUNTER with WG_RELOAD Leave outputs deasserted Load WG_COUNTER with 0001H Leave outputs deasserted 2 When counter is enabled begin counting down When counter is enabled begin counting up When WG_COUNTER reaches 1 wait 1 state Assert outputs when up count begins then begin counting up Assert outputs when up count begins 3 When WG_COUNTER reaches the When WG_COUNTER reaches the WG_COMP x value during the up count deassert value deassert the corresponding the corresponding phase s outputs and continue phase s outputs and continue counting up counting up 4 When WG_COUNTER reaches the When WG_COUNTER reaches the WG_RELOAD value begin counting down WG_RELOAD value update WG_RELOAD and go to step 1 5 When WG_COUNTER reaches the WG COMPx value during the down count assert the corresponding phase s outputs and continue counting down 6 When WG_COUNTER reaches 1 deassert outputs update WG_RELOAD and go to step 1 The main differences between the center aligned modes and among the edge aligned modes are the events that control register updates Table 9 4 lists the events that can cause register updates and the registers that are updated in each mode Table 9 4 Register Updates Center aligned Modes Edge aligned Modes Mode 4 Event Mode 0 Mode 1 Mode 2 Mode 3 MH Only Registers Updated Reg
521. s Writing to SBUFx starts a transmission regardless of whether RXDx is enabled In mode 4 SCLKx outputs a set of eight clock pulses while TXDx transmits data or SCLKx accepts a set of eight clock pulses while RXDx receives data Data is transferred eight bits at a time with the least significant bit first When SCLKx is in output mode its timing is identical to that of TXDx shown in Figure 7 3 When is in input mode the input shift clock signal is internally synchronized with the internal clock intel SERIAL 1 0 SIO PORT In mode 4 writing to SBUFx_TX starts a transmission regardless of whether RXDx is enabled However RXDx must be enabled to allow a reception If RXDx is enabled either a rising edge on the RXDx input or clearing the receive interrupt RI flag starts a reception Disabling RXDx stops a reception in progress and inhibits further receptions To avoid a partial or undesired complete reception disable RXDx before clearing the RI flag This can be handled in an interrupt environment by using software flags or in straight line code by using the interrupt pending register to signal the completion of a reception During a reception the RI flag is set one clock bit time after the last data bit is received The re ceive interrupt signal is generated immediately before the RI flag is set During a transmission the TI flag is set immediately after the end of the last eighth data bit is transmitted The transm
522. s 4 3 Italics defined 1 3 J JBC instruction A 2 A 5 A 17 A 41 A 50 A 56 JBS instruction A 3 A 5 A 17 A 41 A 50 A 56 JC instruction A 3 A 5 A 18 A 45 A 50 A 56 JE instruction A 3 A 5 A 18 A 45 A 50 A 56 JGE instruction A 2 A 5 A 18 A 45 A 50 A 56 JGT instruction A 2 A 5 A 19 A 45 A 50 A 56 JH instruction A 3 A 5 A 19 A 45 A 50 A 56 JLE instruction A 3 A 5 A 19 A 45 A 50 A 56 JLT instruction A 3 A 5 A 20 A 45 A 50 A 56 JNC instruction A 2 A 5 A 20 A 45 A 50 A 56 JNE instruction A 2 A 5 A 20 A 45 A 50 A 56 JNH instruction A 2 A 5 A 21 A 45 A 50 A 56 JNST instruction A 2 A 5 A 21 A 45 A 50 A 56 JNV instruction A 2 A 5 A 21 A 45 A 50 A 56 JNVT instruction A 2 A 5 A 22 A 45 A 50 A 56 JST instruction A 3 A 5 A 22 A 45 A 50 A 56 Jump instructions A 55 conditional A 5 A 50 A 56 unconditional A 49 JV instruction A 3 A 5 A 22 A 45 A 50 A 56 Index 5 8XC196MC MD MH USER S MANUAL JVT instruction A 3 A 5 A 23 A 45 A 50 A 56 L Latency See bus hold protocol interrupts LCALL instruction A 3 A 23 A 45 A 50 A 56 LD instruction 2 A 23 A 44 49 55 LDB instruction A 2 A 23 A 44 A 49 A 55 LDBSE instruction A 3 A 24 A 44 A 49 A 55 LDBZE instruction A 3 A 24 A 44 A 49 A 55 Level sensitive input B 13 Literature 1 11 LJMP instruction A 2 A 24 A 49 A 55 Logical instructions A 48 A 53 LONG
523. s bit is set when the last data bit is sampled Reading SPx STATUS clears this bit 5 TI Transmit Interrupt This bit is set at the beginning of the stop bit transmission Reading SPx STATUS clears this bit 4 FE Framing Error This bit is set if a stop bit is not found within the appropriate period of time Reading SPx STATUS clears this bit 3 TXE SBUFx TX Empty This bit is set if the transmit buffer is empty and ready to accept up to two bytes It is cleared when a byte is written to SBUFx TX 2 OE Overrun Error This bit is set if data in the receive shift register is loaded into SBUFx RX before the previous bit is read Reading SPx STATUS clears this bit 1 0 Reserved for compatibility with future devices write zeros to these bits C 52 intel REGISTERS T1CONTROL T1CONTROL Address 1F78H Reset State 00H The timer 1 control T1 CONTROL register determines the clock source counting direction and count rate for timer 1 7 0 CE UD M2 M1 MO P2 P1 PO Bit Bit _ Function Number Mnemonic aneto 7 CE Counter Enable This bit enables or disables the timer From reset the timers are disabled and not free running 0 disables timer 1 enables timer 6 UD Up Down This bit determines the timer counting direction in selected modes see mode bits M2 0 0 count down 1 count up 5 3 M2 0 EPA Clock Direction Mode Bits These bits determine the timer clocking sour
524. s include transferring a single byte or word transferring a block of bytes or words managing multiple A D conver sions and generating PWM outputs The entire microcoded response to multiple PTS interrupt requests The PTS routine is controlled by the contents of the PTS control block The movement of a single byte or word from the source memory location to the destination memory location A location in special purpose memory that holds the starting address of a PTS control block Glossary 7 8XC196MC MD MH USER S MANUAL PWM quantizing error RALU repeatability error reserved memory resolution sample capacitor sample delay sample delay uncertainty Glossary 8 intel Pulse width modulated outputs The 8XC196Mx devices have several options for producing PWM outputs the generic pulse width modulator modules the waveform generator and the EPA with or without the PTS 8XC196MD also has a frequency generator that produces PWM outputs An unavoidable A D conversion error that results simply from the conversion of a continuous voltage to its integer digital representation Quantizing error is always 0 5 LSB and is the only error present in an ideal A D converter Register arithmetic logic unit A part of the CPU that consists of the ALU the PSW the master PC the microcode engine a loop counter and six registers The difference between corresponding code transitions from different ac
525. s of CCR1 to control wait states and bus width 7 LOC1 LOCO IRC1 IRCO ALE WR BWO PD Bit Number Bit Mnemonic Function ALE WR Address Valid Strobe and Write Strobe These bits define which bus control signals will be generated during external read and write cycles ALE WR 0 0 address valid with write strobe mode ADV RD WRL WRH 0 1 address valid strobe mode ADV RD WR BHE 1 0 write strobe mode ALE RD WRL WRH 1 1 standard bus control mode ALE RD WR BHE BWO Buswidth Control This bit along with the BW1 bit CCR1 2 selects the bus width BW1 BWO 0 0 illegal 0 1 16 bit only 1 0 8 bit only 1 1 BUSWIDTH pin controlled PD Powerdown Enable Controls whether the IDLPD 2 instruction causes the microcontroller to enter powerdown mode If your design uses powerdown mode set this bit when you program the CCBs If it does not clearing this bit when you program the CCBs will prevent accidental entry into powerdown mode 0 disable powerdown mode 1 enable powerdown mode The CCRs are loaded with the contents of the chip configuration bytes CCBs after reset unless the microcontroller is entering programming modes see Entering Programming Modes on page 16 13 in which case the programming chip configuration bytes PCCBs are used The CCBs reside in nonvolatile memory at addresses 2018H CCBO and 201AH
526. s or dec rements by one count on each rising edge and each falling edge Because the TICLK and TIDIR inputs are sampled by the internal phase clocks transitions must be separated by at least two state times for proper operation The count is clocked by PH2 which is PH1 delayed by one half pe riod The sequence of the signal edges and levels controls the count direction Refer to Figure 11 4 and Table 11 4 for sequencing information A typical source of quadrature encoded signals is a shaft angle decoder shown in Figure 11 3 Its output signals X and Y are input to TICLK and TIDIR which in turn output signals X internal and Y internal These signals are used in Figure 11 4 and Table 11 4 to describe the direction of the shaft In the default quadrature clocking mode software must reload the register when timer 1 overflows or underflows In mode 2 TICONTROL 2 0 1 timer 1 automatically loads the value from the TIRELOAD register into the TIMERI register when an overflow or underflow occurs Mode 2 is useful for interfacing to an incremental shaft encoder that turns in only one di rection For this application initialize TIRELOAD with a value that is one less than the encoder s resolution This method allows timer 1 to track the absolute position of the shaft encoder with no software overhead 8XC196MC MD MH USER S MANUAL intel MCS 96 Microcontroller PH2 PH1 X internal Optical Reader Y internal A15
527. s port 6 functions If you are using port 6 for general purpose outputs write COH for active high outputs or OOH for active low outputs to the high byte of WG_OUTPUT and write the desired pin values to the low byte 15 8 1 7 6 5 4 M3 2 M1 0 7 0 D7 D6 D5 D4 D3 D2 D1 DO Bit Bit Function Number Mnemonic unctio 15 14 OP1 0 Output Polarity These bits select the output polarity of the port 6 pins 0 active low outputs 1 active high outputs 13 Reserved for compatibility with future devices write zero to this bit 12 8 M7 0 Mode These bits select either the peripheral function or general purpose output function of the port 6 pins Clear these bits for general purpose output 7 0 D7 0 Data In general purpose output mode these bits hold the values to be driven out on the pins Write the desired values to these bits bits 7 0 correspond to pins P6 7 0 C 62 intel REGISTERS WG OUTPUT Waveform Generator OUTPUT Waveform Generator bokan eset State The waveform generator output configuration WG_OUTPUT register controls the configuration of the waveform generator and PWM module pins Both the waveform generator and the PWM module share pins with port 6 Having these control bits in a single register enables you to configure all port 6 pins with a single write to WG_OUTPUT
528. se the following formula and round the result to the next higher integer PPW VALUE for 8XC196MC MD 62 5 x FyzA4 PPW VALUE for 8XC196MH 25 where PPW_VALUE is a 16 bit word is the input frequency on XTAL1 in MHz PPW no direct access The programming pulse width PPW register is loaded from the external EPROM locations 14H and 15H for the 8XC196MC and MD locations 4014H and 4015H for the 8 196 in auto programming mode The PPW_VALUE determines the programming pulse width 15 8 15 PPWi4 PPW13 PPW12 PPW11 PPW10 PPW9 PPW8 7 0 PPW7 PPW6 PPW5 PPW4 PPW3 PPW2 PPW1 PPWO Bit Bit Number Mnemonic Function 15 0 PPW15 0 PPW VALUE This value establishes the programming pulse width for auto programming Use the appropriate formula to calculate the PPW VALUE then write the result to the PPW register Table 16 5 shows the calculations and results for 8 MHz and 16 MHz operation PPW VALUE for 8XC196MC MD 62 5 4 PPW VALUE for 8XC196MH 25 xFyrAL1 Figure 16 2 Programming Pulse Width PPW Register The examples in Table 16 5 calculate the required minimum pulse width 100 us for the 8 196 and 250 us for the 8 196 MD for an 8 MHz and a 16 MHz crystal 16 8 intel PROGRAMMING THE NONVOLATILE MEMORY Table 16 5 Example PPW VALUE Calculations F 8XC196MC MD 8XC196MH XrAL1 Two 250 pys pulses
529. se width Modulator PWM 2 10 2 5 5 Frequency Generator 2 2 10 2 5 6 Waveform Generator sess ens 2 10 2 5 7 Analog to digital Converter 2 11 2 5 8 _ Watchdog Timer bert abre 2 11 2 6 SPECIAL OPERATING 2 11 2 6 1 Reducing Power Consumption 2 2 11 2 6 2 Testing the Printed Circuit Board sese 2 11 2 6 3 Programming the Nonvolatile Memory seem 2 12 8XC196MC MD MH USER S MANUAL intel CHAPTER 3 PROGRAMMING CONSIDERATIONS 3 1 OVERVIEW OF THE INSTRUCTION nennen 3 1 3 1 1 BIT Operarids c ehe d rcp bee E cle dae tas 3 2 3 1 2 BY TE Operands uat Rp REL en hes 3 2 3 1 3 SHORT INTEGER Operands nei eris pte yi ite oa nent aee e 3 2 9 54 WORD Operands nC ial a b 3 2 3 1 5 Ph peorttitor estt 3 3 3 1 6 DOUBLE WORD Operands eiie te eve Paci deett 3 3 3 1 7 LONG INTEGER Operands siriarren meer e cem ete dnte 3 4 3 1 8 Converting Operands ecrire enciende een A 3 1 9 Conditional JUMPS iere 3 4 3 1 10 Floating Point Operations iden in eid tie tp pede t 3 4 3 2 ADDRESSING MODES senem 3 5 3 2 1 Direct Addressing ee eB URBES
530. selects WRH WRL Write During 16 bit bus cycles this active low output signal is asserted for low byte writes and word writes to external memory During 8 bit bus cycles WRL is asserted for all write operations WRL is multiplexed with P5 2 and WR The chip configuration register 0 CCRO determines whether this pin functions as WR or WRL CCRO 2 1 selects WR CCRO 2 0 selects WRL XTAL1 Input Crystal Resonator or External Clock Input Input to the on chip oscillator and the internal clock generators The internal clock generators provide the peripheral clocks CPU clock and CLKOUT signal MC MD only When using an external clock source instead of the on chip oscillator connect the clock input to XTAL1 The external clock signal must meet the specification for XTAL1 see datasheet XTAL2 Inverted Output for the Crystal Resonator Output of the on chip oscillator inverter Leave XTAL2 floating when the design uses an external clock source instead of the on chip oscillator B 4 DEFAULT CONDITIONS Table B 8 lists the values of the signals of the 8 196 and 8XC196MD during various oper ating conditions The shaded rows indicate those signals that are available only on the B 22 SIGNAL DESCRIPTIONS intel 8XC196MD Table B 9 lists the same information for the 8XC196MH Table B 7 defines the symbols used to represent the pin status Refer to the DC Characteri
531. service for the A D conversion complete interrupt Because the lower six bits of the AD RESULT regis ter contain status information the end of PTS interrupt service routine could shift the results data to the right six times to leave only the conversion results in the memory locations See AP 483 Application Examples Using the SXC 196MC MD Microcontroller for application examples with code 5 34 intel STANDARD AND PTS INTERRUPTS 5 6 5 1 A D Scan Mode Cycles Software must start the first A D conversion After the A D conversion complete interrupt ini tiates the PTS routine the following actions occur 1 The PTS reads the first command from address X XXX stores it in a temporary location and increments the PTSPTRI register twice PTSPTR1 now points to the first blank location in the command data table address XXXX 2 2 The PTS reads the AD RESULT register stores the results of the first conversion into location XXXX 2 in the command data table and increments the PTSPTRI register twice now points to XXXX 4 3 The PTS loads the command from the temporary location into the AD COMMAND register This completes the first A D scan cycle and initiates the next A D conversion 4 IfUPDT 3 is clear the original address is reloaded into the PTSPTRI register The next cycle uses the same command and overwrites previous data If UPDT is set the updated address remains in PISPTR1 and the next cyc
532. set If this happens before the previous byte in SBUFx RX is read the overrun error OE bit is set SBUFx RX always contains the latest byte received it is never a combination of the last two bytes The receive interrupt RI flag indicates whether an incoming data byte has been received The transmit interrupt TI flag indicates whether a data byte has finished transmitting These flags also set the corresponding bits in the interrupt pending register A reception or transmission sets the RI or TI flag in SPx STATUS and the corresponding interrupt pending bit However a soft ware write to the RI or TI flag in SPx STATUS has no effect on the interrupt pending bits and does not cause an interrupt Similarly reading SPx STATUS clears the RI and TI flags but does not clear the corresponding interrupt pending bits The RI and TI flags in the SPx STATUS and the corresponding interrupt pending bits can be set even if the RIx and TIx interrupts are masked The transmitter empty bit is set if SBUFEx TX and its buffer are empty and ready to accept up to two bytes TXE is cleared as soon as a byte is written to SBUFx TX One byte may be writ ten if TI alone is set By definition if TXE has just been set a transmission has completed and TI is set The received parity error RPE flag or the received bit 8 RB8 flag applies for parity enabled or disabled respectively If parity is enabled RPE is set if a parity error is detected If parity is
533. set this instruction adds to the program counter the offset between the end of this instruction and the target label effecting the jump The offset must be in range of 128 to 127 if ST 1 then PC lt PC 8 bit disp PSW Flag Settings Z N C V VT ST JST cadd 11011000 disp NOTE The displacement disp is sign extended to 16 bits JV JUMP IF OVERFLOW FLAG IS SET Tests the overflow flag If the flag is clear control passes to the next sequential instruction If the overflow flag is set this instruction adds to the program counter the offset between the end of this instruction and the target label effecting the jump The offset must be in range of 128 to 127 if V 2 1 then PC lt PC 8 bit disp PSW Flag Settings Z N C V VT ST JV cadd 11011101 disp NOTE The displacement disp is sign extended to 16 bits A 22 intel INSTRUCTION SET REFERENCE Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format JVT JUMP IF OVERFLOW TRAP FLAG IS SET Tests the overflow trap flag If the flag is clear cadd control passes to the next sequential 1 If the overflow trap flag is set this 11011100 disp instruction clears the flag and adds to the program counter the offset between the end NOTE The displacement disp is sign of this inst
534. signal to determine the status of an external device The event processor array EPA was designed to reduce the CPU overhead associated with these types of event control This chapter describes the EPA and its timers and explains how to configure and program them 11 1 EPA FUNCTIONAL OVERVIEW The EPA performs input and output functions associated with two timer counters timer 1 and timer 2 Figure 11 1 Inthe input mode the EPA monitors an input pin for an event a rising edge a falling edge or an edge in either direction When the event occurs the EPA records the value of the timer counter so that the event is tagged with a time This is called an input capture Input captures are buffered to allow two captures before an overrun occurs In the output mode the EPA monitors a timer counter and compares its value with a value stored in aregister When the timer counter value matches the stored value the EPA can trigger an event a timer reset an A D conversion a waveform generator reload or an output event set a pin clear a pin toggle a pin or take no action This is called an output compare Each input capture or an output compare sets an interrupt pending bit This bit can optionally cause an interrupt Table 11 1 lists the capture compare and compare only channels for each de vice in the 8XC196Mx family Table 11 1 EPA Channels Device Capture Compare Channels Compare only Channels 8XC196MC EPA3 0 COMP3 0 8X
535. spec ified time Otherwise a defective external device could tie up the address data bus indefinitely Setup and hold timings must be met when using the READY signal to insert wait states into a bus cycle see Figures 15 8 and 15 9 and Table 15 5 Because a decoded valid address is used to generate the READY signal the setup time is specified relative to the address being valid This specification T yyy indicates how much time the external device has to decode the address and assert READY after the address is valid As shown in Figure 15 9 the 8XC196MH has addi tional READY setup timing specification This specification yy indicates how much time an external device has to deassert the READY signal after ALE falls The READY signal must be held low until the minimum timing specification is met Do not exceed the maximum yy or specification or additional unwanted wait states might be added Refer to the datasheets for the current T y y Tc and yy specifications 15 18 intel INTERFACING WITH EXTERNAL MEMORY rip EN camo E S 1 CLYX max ALE min READY RD AD15 0 Address Out read WR AD15 0 Address Out Data Out Address write The CLKOUT pin is available only on the 8XC196MC MD A3165 01 Figure 15 8 READY Timing Diagram One Wait State 8 196 MD 15 19 8
536. stal and the device When designing an external oscillator circuit consider the effects of parasitic board capacitance extended oper ating temperatures and crystal specifications Consult the manufacturer s datasheet for perfor mance specifications and required capacitor values With high quality components 20 pF load capacitors C are usually adequate for frequencies above 1 MHz Noise spikes on the XTAL1 or XTAL2 pin can cause a miscount in the internal clock generating circuitry Capacitive coupling between the crystal oscillator and traces carrying fast rising digital signals can introduce noise spikes To reduce this coupling mount the crystal oscillator and ca pacitors near the device and use short direct traces to connect to XTALI XTAL2 and To further reduce the effects of noise use grounded guard rings around the oscillator circuitry and ground the metallic crystal case 96 Microcontroller X XTAL2 Quartz Crystal Note Mount the crystal and capacitors close to the device using short direct traces to XTAL1 XTAL2 and Vss When using a crystal 1 2 20 pF When using a ceramic resonator consult the manufacturer for recommended oscillator circuitry A0273 03 Figure 13 4 External Crystal Connections In cost sensitive applications you may choose to use a ceramic resonator instead of a crystal os cillator Ceramic resonators may require slightly different load capacitor values an
537. starting a reception e Add the contents of the timer register to the Baud_value Figure 5 19 on page 5 38 and store the result into the EPA time register This sets up the timing for the first interrupt and causes the first interrupt to occur at the proper baud rate The following example uses EPAO to capture the start bit and P2 0 to receive the data RXD It sets up an asynchronous serial I O PTS routine that receives 16 bytes each with eight data bits and a parity bit This example uses several user defined registers R COUNT defines the number of bytes to receive and RXDDONE is a flag that is set when all bytes are received 1 Disable the interrupts and the PTS Use the DI instruction to disable all standard interrupts and the DPTS instruction to disable the PTS 5 55 8XC196MC MD MH USER S MANUAL intel Set up the stack pointer Reset all interrupt mask registers Clear INT MASK INT MASKland PI MASK Initialize P2 0 to function as the RXD signal Set P2 0 selects input Clear P2 MODE 0 selects LSIO function Set P2 REG 0 initializes input to 1 Initialize and enable the timer select up counting internal clock and prescaler disabled Set TICONTRODL bits 6 and 7 Figure 11 8 on page 11 16 Initialize the PTSCB as shown in Table 5 16 Table 5 16 ASIO Receive Mode PTSCBs PTSCB1 PTSCB2 PTSVEC H pointer to PTSCB2 Unused PTSVEC L pointer
538. stics table in the datasheet for actual specifications for Vor and Table B 7 Definition of Status Symbols Symbol Definition Symbol Definition 0 Voltage less than or equal to Vo Vi MDO Medium pull down 1 Voltage greater than or equal to Voy Vin MD1 Medium pull up HiZ High impedance WKO Weak pull down 1070 Low impedance strongly driven low WK1 Weak pull up LoZ1 Low impedance strongly driven high ODIO Open drain I O Table B 8 8XC196MC and MD Default Signal Conditions Altern Durin Upon RESET Port Signals ee RESETE pm Idle Powerdown P0 7 0 ACH7 0 HiZ HiZ HiZ P1 1 0 ACH9 8 HiZ HiZ HiZ P1 2 ACH10 T1CLK HiZ HiZ HiZ P1 3 ACH11 T1DIR HiZ HiZ HiZ P1 4 ACH12 HiZ HiZ HiZ P1 5 Note 15 ACH13 HiZ HiZ HiZ P1 7 6 Note 15 HiZ HiZ HiZ P2 0 EPAO WK1 Note 1 WK1 Note 12 Note 12 P2 1 EPA1 WK1 WK1 Note 12 Note 12 P2 3 2 EPA3 2 WK1 WK1 Note 12 Note 12 P2 6 4 COMP2 0 WK1 WK1 except Note 12 Note 12 2 5 LZ Note 1 P2 7 COMP3 WK1 WK1 Note 12 Note 12 P3 7 0 AD7 0 WK1 HiZ Note 3 Note 3 P4 7 0 AD15 8 WK1 HiZ Note 3 Note 3 P5 0 ADV ALE WK1 Note 1 WK1 Note 4 Note 8 Note 8 P5 1 INST WK1 WK1 Note 9 Note 9 P5 2 WR WRL WK1 Note 1 WK1 Note 10 Note 10 P5 3 RD WK1 Note 1 WK1 Note 4 Note 10 Note 10 P5 4 ONCE MD1 LZ Note 1
539. stination word operand to the right as SHRA wreg count many times as specified by the count operand The count may be specified either 00001010 count wreg as an immediate value in the range of O to 15 or OFH inclusive or as the content of any SHRA wreg breg register 10H OFFH with a value in the range of 0 to 31 1FH inclusive If the 00001010 breg wreg original high order bit value was 0 zeros are shifted in If the value was 1 ones are NOTES This instruction clears the shifted in The last bit shifted out is saved in sticky bit flag at the beginning the carry flag of the instruction If at any time Temp lt COUNT during the shift a 1 is shifted do while Temp 0 into the carry flag and another C lt Low order bit of DEST shift cycle occurs the instruc DEST lt DEST 2 tion sets the sticky bit flag Temp lt Temp 1 end while In this operation DEST 2 rep resents signed division PSW Flag Settings Z N C V VT ST 0 v SHRAB ARITHMETIC RIGHT SHIFT BYTE Shifts the SHRAB breg count 00011010 count breg or SHRAB breg breg 00011010 breg breg NOTES This instruction clears the sticky bit flag at the beginning of the instruction If at any time during the shift a 1 is shifted into the carry flag and another shift cycle occurs the instruc tion sets the sticky bit flag In this operation DEST 2 rep resents signed division
540. strobe mode ALE latches the address AD15 is the chip select signal for the memory devices WRL is asserted during low byte writes and word writes WRH is asserted during high byte writes and word writes Note that the RAM devices do not use ADO WRL and WRH de termine whether the low byte ADO 0 or high byte ADO 1 is selected Vcc BUSWIDTH AD15 8 ALE 8XC196 A3090 01 Figure 15 15 16 bit System with Writes to Byte wide RAMs 15 26 intel INTERFACING WITH EXTERNAL MEMORY 15 5 3 Address Valid Strobe Mode When the address valid strobe mode is selected the microcontroller generates the address valid signal ADV instead of the address latch enable signal ALE ADV is asserted after an exter nal address is valid see Figure 15 16 This signal can be used to latch the valid address and si multaneously enable an external memory device See the examples in Figures 15 18 and 15 19 ADV ADV WR or RD WR or RD 52547222 CAUSE Addr BHE Valid AD7 0 Data Out AD15 0 Data Out AD15 8 Address High 16 bit Bus Cycle 8 bit Bus Cycle A3092 02 Figure 15 16 Address Valid Strobe Mode The difference between ALE and ADV is that ADV is asserted for the entire bus cycle not just to latch the address Figure 15 17 shows the difference between ALE and ADV for a single read or write cycle Note that for back to back bus access the ADV function will look identical to the ALE
541. subtraction operation generates a borrow the carry flag is cleared Value of Bits Shifted 0 lt VeLSB 1 gt LSB Normally the result is rounded up if the carry flag is set The sticky bit flag allows a finer resolution in the rounding decision 5 Value of Bits Shifted 0 0 1 gt 0 and lt LSB 0 2 LSB 1 gt Ye LSB and lt 1 LSB The negative flag is set to indicate that the result of an operation is negative The flag is correct even if an overflow occurs For all shift operations and the NORML instruction the flag is set to equal the most significant bit of the result even if the shift count is zero ST The sticky bit flag is set to indicate that during a right shift a 1 has been shifted into the carry flag and then shifted out This bit is undefined after a multiply operation The sticky bit flag can be used with the carry flag to allow finer resolution in rounding decisions See the description of the carry C flag for details The overflow flag is set to indicate that the result of an operation is too large to be represented correctly in the available space For shift operations the flag is set if the most significant bit of the operand changes during the shift For divide operations the quotient is stored in the low order half of the destination operand and the remainder is stored in the high order half The overflow flag is set if the quotient is outside the range
542. t Vpp All Programming Voltage During programming the V pin is typically at 12 5V Vpp voltage Exceeding the maximum Vpp voltage specification can damage the device 16 7 ENTERING PROGRAMMING MODES To execute programs properly the device must have these minimum hardware connections XTALI driven unused input pins strapped and power and grounds applied Follow the operating conditions specified in the datasheet Place the device into programming mode by applying V pp voltage 12 5 V to EA during the rising edge of RESET 16 7 1 Selecting the Programming Mode The PMODE P0 7 4 value controls the programming mode PMODE is sampled on the rising edge of RESET You must reset the device to switch programming modes Table 16 7 lists the PMODE value for each programming mode All other PMODE values are reserved Table 16 7 PMODE Values HER S Programming Mode 5 Slave programming 6 ROM dump 9 UPROM programming MH only C Auto programming D PCCB programming MH only 16 13 8XC196MC MD MH USER S MANUAL intel 16 7 2 Power up Power down Sequences When you are ready to begin programming follow these power up and power down procedures WARNING Failure to observe these warnings will cause permanent device damage Voltage must not be applied to while is low The voltage must be within 1 volt of while is less than 4 5 volts Vpp must not
543. t P1 1 RXDO VO Receive Serial Data P1 3 RXD1 In modes 1 2 3 and 4 RXDx receives serial port input data In mode 0 it functions as an input or an open drain output for data P2 1 SCLKO BCLKO Baud Clock P2 7 SCLK1 BCLK1 can provide an external clock source for the baud rate generator input Shift Clock In mode 4 only SCLKx are bidirectional shift clock signals that synchronize the serial data transfer The DIR bit in the SP CON register controls the direction of SCLKx DIR 0 causes to output the internal shift clock DIR 1 allows an external shift clock to be input on SCLKx Table 7 2 Serial Port Control and Status Registers Mnemonic Address Description INT MASK1 0013H Interrupt Mask 1 Setting the TIx bit enables the transmit interrupt clearing the bit disables masks the interrupt Setting the RIx bit enables the receive interrupt clearing the bit disables masks the interrupt Setting the SPE bit enables the serial port receive error interrupt 7 2 intel SERIAL SIO PORT Table 7 2 Serial Port Control and Status Registers Continued Mnemonic Address Description INT_PEND1 0012H Interrupt Pending 1 When set the TIx bit indicates a pending transmit interrupt When set the RIx bit indicates a pending receive interrupt When set the SPE bit indicates a pending serial po
544. t 5 uses a standard input buffer because of the high speeds required for bus control functions The signals are latched into the Px PIN sample latch and output onto the internal bus when the Px PIN register is read The falling edge of RESET turns on transistor Q3 which remains on for about 300 ns causing the pin to change rapidly to its reset state The active low level of RESET turns on transistor Q4 which weakly holds the pin high Q4 can source approximately 10 LA consult the datasheet for exact specifications Q4 remains on weakly holding the pin high until your software writes to the Px MODE register NOTE 8XC196MC MD Only P2 7 is an exception After reset P2 7 carries the CLKOUT signal half the crystal input frequency rather than being held high When CLKOUT is selected it is always a complementary output 8XC196MC MD MH USER S MANUAL intel Internal Bus SFDATA Qi I O Pin 1500 to 2000 1 Read Port 1 Clock 300ns Delay RESET gt lt RESET Any Write to Px_MODE A0238 04 Figure 6 2 Bidirectional Port Structure intel PORTS Table 6 6 Logic Table for Bidirectional Ports Mode Configuration Complementary Output gor Input Px MODE 0 0 0 0 Px DIR 0 0 1 1 SFDIR X X X X SFDATA X X X X Px REG 0 1 0 1 Note 2 1 Q1 off on off off Q2 on off on off Note 2 off Px PIN 0 1 X Note 3 high impe
545. ta bus EA is sampled and latched only on the rising edge of RESET Changing the level of EA after reset has no effect Always connect EA to Vss when using microcontroller that has no internal nonvolatile memory INST P5 1 Instruction Fetch This active high output signal is valid only during external memory bus cycles When high INST indicates that an instruction is being fetched from external memory The signal remains high during the entire bus cycle of an external instruction fetch INST is low for data accesses including interrupt vector fetches and chip configuration byte reads INST is low during internal memory fetches RD P5 3 Read Read signal output to external memory RD is asserted only during external memory reads READY P5 6 Ready Input This active high input along with the chip configuration registers determine the number of wait states inserted into the bus cycle The chip configuration registers selects the maximum number of wait states 0 1 2 3 or infinite that can be inserted into the bus cycle While READY is low wait states are inserted into the bus cycle until the programmed number of wait states is reached If READY is pulled high before the programmed number of wait states is reached no additional wait states will be inserted into the bus cycle WR 5 2 Write This active low output indicates that an external write is occurring This signal is
546. take on values from 0 through 65 535 216 1 Arithmetic and relational operators can be applied to WORD operands but the result must be in terpreted in modulo 65536 arithmetic Logical operations on WORDs are applied bitwise Bits within WORDs are labeled from 0 to 15 bit 0 is the least significant bit intel PROGRAMMING CONSIDERATIONS WORDS must be aligned at even byte boundaries in the address space The least significant byte of the WORD is in the even byte address and the most significant byte is in the next higher odd address The address of a WORD is that of its least significant byte the even byte address WORD operations to odd addresses are not guaranteed to operate in a consistent manner 3 1 5 INTEGER Operands An INTEGER is a 16 bit signed variable that can take on values from 32 768 215 through 432 767 2151 Arithmetic operations that generate results outside the range of an INTEGER set the overflow flags in the processor status word PSW The numeric result is the same as the result of the equivalent operation on WORD variables INTEGERs must be aligned at even byte boundaries in the address space The least significant byte of the INTEGER is in the even byte address and the most significant byte is in the next high er odd address The address of an INTEGER is that of its least significant byte the even byte address INTEGER operations to odd addresses are not guaranteed to operate in a consistent manner
547. tel COMPx CON COMPx CON Continued x z 0 3 8XC196MC MH x 0 5 8XC196MD Address Table C 3 Reset State The EPA compare control COMPx CON registers determine the function of the EPA compare channels x 0 2 4 x 1 3 5 TB CE M1 MO RE WGR ROT RT TB CE M1 MO RE AD ROT RT 2 WGR A D Conversion Waveform Generator Reload The function of this bit depends on the EPA channel For EPA capture compare channels 0 2 4 The WGR bit allows you to use the EPA activities to cause the reload of new values in the waveform generator 0 no action 1 enables waveform generator reload For EPA capture compare channels 1 3 5 The AD bit allows you to use the EPA activities to start an A D conversion that has been previously set up in the A D control registers 0 causes no A D action 1 2 starts an A D conversion on an output compare ROT Reset Opposite Timer Selects the timer that is to be reset if the RT bit is set 0 selects the reference timer for possible reset 1 selects the opposite timer for possible reset The state of the TB bit determines which timer is the reference timer and which timer is the opposite timer RT Reset Timer This bit controls whether the timer selected by the ROT bit will be reset 1 resets the timer selected by the ROT bit 0 disables the reset function intel REGISTERS COMPx TI
548. tem control pin and the pin becomes a true complementary output This pin remains weakly held high until the CCB fetch is completed At that time the state of this pin depends on the value of the IRC2 bits of the CCRs If IRCO IRC2 are all set 111B READY is activated as a system control pin This prevents the insertion of infinite wait states upon the first access to external memory For any other values of IRCO IRC2 the pin is configured as I O upon reset NOTE If IRCO IRC2 of the CCB are all set activating READY as a system control pin and P5 MODE 6 is cleared config uring the pin as I O an external memory access may cause the processor to lock up This pin remains weakly held high until your software writes config uration data into 5 MODE 8XC196MC MD MH USER S MANUAL intel 6 4 BIDIRECTIONAL PORTS 3 AND 4 ADDRESS DATA BUS Ports 3 and 4 are eight bit bidirectional memory mapped I O ports They can be addressed only with indirect or indexed addressing and cannot be windowed Ports 3 and 4 provide the multi plexed address data bus In programming modes ports 3 and 4 serve as the programming bus PBUS Port 5 supplies the bus control signals During external memory bus cycles the processor takes control of ports 3 and 4 and automatical ly configures them as complementary output ports for driving address data or as inputs for read ing data For this reason these ports have no mode registers Syste
549. ter 5 Standard and PTS Interrupts discusses the interrupts in greater detail 11 23 8XC196MC MD MH USER S MANUAL intel 11 7 DETERMINING EVENT STATUS In compare mode an interrupt pending bit is set each time a match occurs on an enabled event even if the interrupt is specifically masked in the mask register In capture mode an interrupt pending bit is set each time a programmed event is captured and the event time moves from the capture buffer to the EPAx TIME register The pending bits are located in the INT PEND and INT PENDI registers Figure 5 7 on page 5 15 and Figure 5 11 on page 5 22 The pending bits for the multiplexed interrupts those that share the PI interrupt are located in the PEND register Figure 5 12 on page 5 23 Timer overflows underflows also set interrupt pending bits Even if an interrupt is masked software can poll the interrupt pending registers to determine whether an event has occurred 11 24 intel 12 Analog to digital Converter lt PageNum gt 38 intel CHAPTER 12 ANALOG TO DIGITAL A D CONVERTER The analog to digital A D converter can convert an analog input voltage to a digital value and set the A D interrupt pending bit when it stores the result It can also monitor a pin and set the A D interrupt pending bit when the input voltage crosses over or under a programmed threshold voltage This chapter describes the A D converter and explains how to program it 12 1 A D CO
550. ter the sample delay the device connects the multiplexer output to the sample capacitor for the specified sample time After this sample window closes it disconnects the multiplexer output from the sample ca pacitor so that changes on the input pin will not alter the stored charge while the conversion is in progress The device then zeros the comparator and begins the conversion The A D converter uses a successive approximation algorithm to perform the analog to digital conversion The converter hardware consists of a 256 resistor ladder a comparator coupling ca pacitors and a 10 bit successive approximation register SAR with logic that guides the process The resistive ladder provides 20 mV steps 5 12 volts while capacitive coupling creates 5 mV steps within the 20 mV ladder voltages Therefore 1024 internal reference voltage levels are available for comparison against the analog input to generate a 10 bit conversion result In 8 bit conversion mode only the resistive ladder is used providing 256 internal reference voltage levels The successive approximation conversion compares a sequence of reference voltages to the ana log input performing a binary search for the reference voltage that most closely matches the in put The gt full scale reference voltage is the first tested This corresponds to a 10 bit result where the most significant bit is zero and all other bits are ones 0111111111B If the analog input was less
551. terrupt Glossary 6 intel Interrupts that cannot be masked disabled and cannot be assigned to the PTS for processing The nonmaskable interrupts are unimplemented opcode software trap and NMI Read only memory that retains its contents when power is removed Many MCS 96 microcontrollers are available with either masked ROM EPROM or OTPROM Consult the Automotive Products or Embedded Microcontrollers databook to determine which type of memory is available for a specific device A transistor consisting of one part p type material and two parts n type material The ability of an A D converter to reject isolate the signal on a deselected off output One time programmable read only memory Similar to EPROM but it comes in an unwindowed package and cannot be erased A field effect transistor with a p type conducting path Semiconductor material with introduced impurities doping causing it to have an excess of positively charged carriers Program counter Programming chip configuration bytes which are loaded into the chip configuration registers CCRs when the device is entering programming modes otherwise the CCBs are used Programmable interrupt controller The module responsible for handling interrupts that are to be serviced by interrupt service routines that you provide Also called simply the interrupt controller Any maskable interrupt or nonmaskable NMI Two of the nonmaskable interrupts unimpl
552. th of time output data is valid before the microcontroller deasserts WR Address high byte Hold after RD High Minimum time the high byte of the address when using an 8 bit data bus is valid after the microcontroller deasserts RD BHE INST Hold after RD High Minimum time these signals are valid after the microcontroller deasserts RD RD High to ALE High Time between the microcontroller deasserting RD and the next ALE pulse Maximum time the memory system has to put data on the bus before the next address cycle RD Low to Address Float Time after the microcontroller deasserts RD until it stops driving the address on the bus Tray RD Low to RD High RD pulse width The CLKOUT pin is available only on the 8XC196MC MD microcontrollers 15 34 intel INTERFACING WITH EXTERNAL MEMORY Table 15 9 Microcontroller Meets These Specifications Continued Symbol Definition Address high byte Hold after WR High Minimum time the high byte of the address when using an 8 bit data bus is valid after the microcontroller deasserts WR Twugx BHE INST Hold after WR High Minimum time these signals are valid after the microcontroller deasserts WR WRi High to ALE High Time between the microcontroller deasserting WR and next ALE pulse Maximum time the memory system has to get data off the bus before the next address cycle
553. than the test voltage bit 10 of the SAR is left at zero and a new test voltage of full scale 0011111111B is tried If the analog input was greater than the test voltage bit 9 of SAR is set Bit 8 is then cleared for the next test 0101111111B This binary search continues until 10 or 8 tests have occurred at which time the valid conversion result resides in the RESULT register where it can be read by software The result is equal to the ratio of the input voltage divided by the analog supply voltage If the ratio is 1 00 the result will be all ones 12 4 PROGRAMMING THE A D CONVERTER The following A D converter parameters are programmable conversion input input channel zero offset adjustment no adjustment plus 2 5 mV minus 2 5 mV or minus 5 0 mV conversion times sample window time and conversion time for each bit operating mode 8 or 10 bit conversion or 8 bit high or low threshold detection conversion trigger immediate or EPA starts This section describes the A D converter s registers and explains how to program them 12 4 intel ANALOG TO DIGITAL A D CONVERTER 12 41 Programming the A D Test Register The AD TEST register Figure 12 2 analog specifies an offset voltage to be applied to the resis tor ladder To use the zero offset adjustment first perform two conversions one on ANGND and one on With the results of these conversions use a software routine to calculate the z
554. the PCCBs and UPROM bits by using an EPROM programmer In this mode ports 3 and 4 serve as the PBUS transferring commands addresses and data The least significant bit of the PBUS P3 0 controls the command 1 program word 0 dump word and the remaining 15 bits contain the address of the word to be programmed or dumped Some port 2 pins provide handshaking signals The AINC signal controls whether the address is automatically incremented enabling programming or dumping sequential OTPROM locations This speeds up the programming process since it eliminates the need to generate and decode each sequential address NOTE If a glitch or reset occurs during programming of the security key an unknown security key might accidentally be written rendering the device inaccessible for further programming To prevent this possibility during slave programming program the rest of the OTPROM array before you program the CCB security lock bits CCB0 6 and 7 16 8 1 Reading the Signature Word and Programming Voltages The signature word identifies the device the programming voltages specify the Vy and volt ages required for programming This information resides in the test ROM at locations 2070H 2072H and 2073H however these locations are remapped to 0070H 0072H and 0073H You can use the dump word command in slave programming mode to read the signature word and pro gramming voltages at the locations shown in Table 16 8 The
555. the carrier period and the duty cycle because the outputs remain asserted for a constant length of time while the counter takes longer to cycle To change the carrier period without changing the duty cycle you must proportionally change both WG RELOAD and WG_COMP x at the same time immediately after the interrupt 15 Compare Bit Number Function 15 0 Compare These bits determine the length of time that the associated outputs are asserted Use the following formulas to calculate output assertion time and duty cycle T multiplier x NG COMPx OUTPUT F XTAL1 Duty vea Syce WG RELOAD where Toutput total time output is asserted us input frequency XTAL1 in MHz multiplier 4 for center aligned modes 2 for edge aligned modes WG_RELOAD 16 bit WG_RELOAD value gt WG_COMPx WG_COMPx 16 bit WG_COMPx value lt WG_RELOAD C 59 8XC196MC MD MH USER S MANUAL intel WG CONTROL WG CONTROL Address 1FCCH Reset State MC MD 00COH Reset State MH 8000H The waveform generator control WG CONTROL register controls the operating mode dead time and count direction and enables and disables the counter 15 M2 M1 Mo cs EC DT9 DT8 0 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DTO rbai Function 15 E Reserved for compatibility with future devices write zero to this bit 14 12 M2 0 Operating M
556. the interrupt controller The PTS can transfer bytes or words either individually or in blocks between any memory loca tions manage multiple analog to digital A D conversions and can generate pulse width mod ulated PWM signals The 8XC196MC and 8XC196MD have additional modes that allow asynchronous or synchronous serial communication PTS interrupts have a higher priority than standard interrupts and may temporarily suspend interrupt service routines See Chapter 5 Stan dard and PTS Interrupts for more information intel ARCHITECTURAL OVERVIEW 2 4 INTERNAL TIMING The clock circuitry Figure 2 3 receives an input clock signal XTAL 1 provided by an external crystal or oscillator and divides the frequency by two The clock generators accept the divided input frequency from the divide by two circuit and produce two nonoverlapping internal timing signals PH1 and PH2 These signals are active when high Disable Clock Input Powerdown Divide by two Circuit Disable Clocks Powerdown XTAL2 Peripheral Clocks PH1 PH2 Jerkour CPU Clocks PH1 PH2 Clock Disable Generators Oscillator Powerdown Disable Clocks Idle Powerdown NOTE The CLKOUT pin is unique to the 8XC196MC and MD A3115 02 Figure 2 3 Clock Circuitry The rising edges of PH1 and PH2 generate the internal CLKOUT signal Figure 2 4 The clock circuitry routes separate internal clock signals to the
557. the interrupt sources read PEND to determine which source caused the interrupt SIO 0 and SIO 1 can generate this interrupt Write to to enable the interrupt sources read PI_PEND to determine which source caused the interrupt restores it 7 0 8XC196MC NMI EXTINT COMP3 EPA3 7 0 8XC196MD NMI EXTINT 5 4 4 7 0 8 196 WG SPI RIO TH TIO Bit Number Function 7 07 Setting a bit enables the corresponding interrupt The standard interrupt vector locations are as follows Bit Mnemonic Interrupt Standard Vector NMI Nonmaskable Interrupt 203EH EXTINT EXTINT pin 203CH MC MD Multiplexed Peripheral Interrupt 203AH WG Waveform Generator 203AH EPA5 MD EPA Capture Compare Channel 5 2038H SPI MH i Serial Port 2038H COMP4 MD EPA Compare Channel 4 2036H MH SIO 1 Receive 2036H EPA4 MD EPA Capture Compare Channel 4 2034H RIO MH SIO 0 Receive 2034H MC EPA Compare Channel 3 2032H MH SIO 1 Transmit 2032H EPA3 MC MD EPA Capture Compare Channel 3 2030H TIO MH SIO 0 Transmit 2030H these bits On the 8XC196MC device bits 4 3 are reserved For compatibility with future devices write zeros to 5 16 Figure 5 8 Interrupt Mask 1 INT_MASK1 Register intel STANDARD AND PTS INTERRUPTS PI MASK Address 1FBCH Reset State AAH The pe
558. the range for the low order half of the destination operand Chapter 3 Programming Considerations defines the operands and possible values for each See the PSW flag descriptions in Appendix A for details C 40 intel REGISTERS PSW PSW Continued no direct access The processor status word PSW actually consists of two bytes The high byte is the status word which is described here the low byte is the INT MASK register The status word contains one bit PSW 1 that globally enables or disables servicing of all maskable interrupts one bit PSW 2 that enables or disables the peripheral transaction server PTS and six Boolean flags that reflect the state of a user s program The status word portion of the PSW cannot be accessed directly To access the status word push the value onto the stack PUSHF then pop the value to a register POP test reg The PUSHF and PUSHA instructions save the PSW in the system stack and then clear it POPF and POPA restore it 15 8 2 V VT PSE ST See INT_MASK on page C 25 Bit Bit Function Number Mnemonic uneto 12 VT Overflow trap Flag This flag is set when the overflow flag is set but it is cleared only by the CLRVT JVT and JNVT instructions This allows testing for a possible overflow at the end of a sequence of related arithmetic operations which is generally more efficient than testing the overflo
559. the special purpose memory and program memory partitions locations 2000H and above see Table 4 1 on page 4 2 The EA signal controls ac cess to these memory partitions Accesses to these partitions are directed to internal memory if EA is held high and to external memory if EA is held low For devices without internal non volatile memory the EA signal must be tied low EA is latched at reset 8XC196MC MD MH USER S MANUAL intel Table 4 1 Memory Map Device and Hex Address Range Description Addressing Modes MH FFFF FFFF External device memory or I O connected to the 6000 A000 address data bus 5FFF 9FFF Program memory internal nonvolatile or external 2080 2080 memory see Note 1 207F 207F Special purpose memory internal nonvolatile or 2000 2000 external memory Indirect or indexed Indirect or indexed Indirect or indexed 1FFF 1FFF i 1FEO 1FEO Memory mapped SFRs Indirect or indexed 1FDF 1FDF Indirect indexed or 1 00 1 00 Peripheral SFRs windowed direct 1EFF 1EFF External device memory or I O connected to the 0200 0300 address data bus future SFR expansion see Note 2 01FF 02 0100 0100 OOFF OOFF Lower register file general purpose register RAM 0000 0000 stack pointer and CPU SFRs NOTES 1 After a reset the device fetches its first instruction from 2080H 2 content or function of these locations may change in future d
560. then execution from any unused mem ory locations will reset the device 13 6 3 Issuing an Illegal IDLPD Key Operand The device resets itself if an illegal key operand is used with the idle powerdown IDLPD com mand The legal keys are 1 for idle mode and 2 for powerdown mode If any other value is used the device executes a reset sequence See Appendix A for a description of the IDLPD com mand 13 6 4 Generating Wait States The 8 196 devices can interface with a variety of external memory devices With slower external devices this requires inserting wait states to lengthen the bus cycle An external device can use the READY input to request wait states in addition to the wait states that are generated internally by the 8 196 device The READY signal must be held valid until the for the 8 196 MD or for the 8XC196MH timing specification is met Do not exceed the maximum for the 8 196 MD or for the 8XC196MH specification or additional unwanted wait states might be added see Chapter 15 Wait States Ready Control for a detailed explanation 13 6 5 Enabling the Watchdog Timer The watchdog timer WDT is a 16 bit counter that resets the device when the counter overflows The WDE bit bit 3 of CCRI controls whether the watchdog is enabled immediately or is dis abled until the first time it is cleared Clearing WDE activates the watchdog Sett
561. ther the reception occurs on even or odd PTS cycles Because receptions occur only on a rising or falling clock edge two PTS cycles occur for every one data bit reception Figure 5 23 It takes 16 PTS cycles to receive eight data bits SSIO receptions do not include parity or stop bits End of PTS Conventional 16 PTS Serviced Interrupts interrupt N interrupts TL TL TL T m Tm AA A NA A A A M Input Data Sampled on Rising Clock Edge Port pin Bit 7 LSB MSB A3121 01 Figure 5 23 Synchronous SIO Receive Timing If the SCK signal is generated by the EPA channel the first PTS cycle must be started manually Initialize the RXD port pin and the SCK signal to the system required logic level before starting a reception Add the contents of the timer register to the Baud value Figure 5 19 on page 5 38 and store the result into the EPA time register This sets up the timing for the first interrupt and causes the first interrupt to occur at the proper baud rate 5 47 8XC196MC MD MH USER S MANUAL intel The following example uses EPAO to capture the SCK signal and P2 3 to receive the data RXD It sets up a synchronous serial I O PTS routine that receives 16 bytes with eight data bits Because this example uses an external serial clock input the TIMER and BAUD registers are not used The external clock source controls the baud rate This example uses several user defined regis ters R COUNT defines the
562. timer 2 7 0 CE UD M2 M1 MO P2 P1 PO Bit Bit Function Number Mnemonic 7 CE Counter Enable This bit enables or disables the timer From reset the timers are disabled and not free running 0 disables timer 1 enables timer 6 UD Up Down This bit determines the timer counting direction in selected modes see mode bits M2 0 0 count down 1 count up 5 3 M2 0 EPA Clock Direction Mode Bits These bits determine the timer clocking source and direction source M2 1 0 Clock Source Direction Source 0 0 0 1 4 UD bit T2CONTROL 6 X 0 1 reserved 0 1 0 reserved 0 1 1 reserved 1 0 0 timer 1 overflow UD bit T2CONTROL 6 1 1 0 timer 1 overflow same as timer 1 1 1 1 reserved 2 0 P2 0 EPA Clock Prescaler Bits These bits determine the clock prescaler value P2 PO Prescaler Resolution 0 0 0 divide by 1 disabled 250 ns 0 0 1 divide by 2 500 ns 0 1 0 divide by 4 1 us 0 1 1 divide by 8 2 us 1 0 0 divide by 16 4us 1 0 1 divide by 32 8 us 1 1 0 divide by 64 16 us 1 1 1 reserved T Resolution at 16 MHz Use the formula on page 11 6 to calculate the resolution at other frequencies Figure 11 9 Timer 2 Control T2ZCONTROL Register 11 17 8XC196MC MD MH USER S MANUAL intel 11 5 3 Programming the Capture Compare Channels The EPAx CON register controls the function of its assigned capture compare channel The r
563. timing mode Two of its bits combine with three bits of CCRO to control wait states and bus width no direct access WDE BW1 IRC2 0 Bit Number Bit Mnemonic Function IRC2 Ready Control This bit along with IRCO CCRO 4 IRC1 CCRO 5 and the READY determine the number of wait states that can be inserted into the bus cycle While READY is held low wait states are inserted into the bus cycle until the programmed number of wait states is reached If READY is pulled high before the programmed number of wait states is reached no additional wait states will be inserted into the bus cycle IRC2 IRC1 IRCO zero wait states illegal illegal one wait state two wait states three wait states infinite If you choose the infinite wait states option you must keep P5 6 configured as the READY signal Also be sure to add external hardware to count wait states and pull READY high within a specified time Otherwise a defective external device could tie up the address data bus indefinitely 4 1 41 41 4090 300 x0 0 0 Reserved for compatibility with future devices write zero to this bit The CCRs are loaded with the contents of the chip configuration bytes CCBs after reset unless the microcontroller is entering programming modes see Entering Programming Modes on page 16 13 in which case the programming chip configuration bytes P
564. ting the RESET signal and allowing the ONCE pin to float or be pulled high Normal operations resume when RESET goes high 14 6 RESERVED TEST MODES A special test mode entry pin P2 6 is provided for Intel s in house testing only These test modes can be entered accidentally if you configure the test mode entry pin as an input and hold it low during the rising edge of RESET To prevent accidental entry into an unsupported test mode we highly recommend configuring the test mode entry pin as an output If you choose to configure this pin as an input always hold it high during reset and ensure that your system meets specification see datasheet to prevent inadvertent entry into an unsupported test mode 14 11 intel 15 Interfacing with External Memory intel CHAPTER 15 INTERFACING WITH EXTERNAL MEMORY The microcontroller can interface with a variety of external memory devices It supports either a fixed 8 bit data bus width a fixed 16 bit data bus width or a dynamic 8 bit 16 bit data bus width internal control of wait states for slow external memory devices and several bus control modes These features provide a great deal of flexibility when interfacing with external memory systems In addition to describing the signals and registers related to external memory this chapter discuss es the process of fetching the chip configuration bytes and configuring the external bus It also provides examples of external memory co
565. tions 2 6 1 Reducing Power Consumption In idle mode the CPU stops executing instructions but the peripheral clocks remain active Pow er consumption drops to about 40 of normal execution mode consumption Either a hardware reset or any enabled interrupt source will bring the microcontroller out of idle mode In powerdown mode all internal clocks are frozen at logic state zero and the internal oscillator is shut off The register file and most peripherals retain their data if V is maintained Power con sumption drops into the uW range 2 6 2 Testing the Printed Circuit Board The on circuit emulation ONCE mode electrically isolates the microcontroller from the system By invoking the ONCE mode you can test the printed circuit board while the microcontroller is soldered onto the board 8XC196MC MD MH USER S MANUAL intel 2 6 3 Programming the Nonvolatile Memory MCS 96 microcontrollers that have internal OTPROM provide several programming options Slave programming allows a master EPROM programmer to program and verify one or more slave MCS 96 microcontrollers Programming vendors and Intel distributors typically use this mode to program a large number of microcontrollers with a customer s code and data Auto programming allows an MCS 96 microcontroller to program itself with code and data located in an external memory device Customers typically use this low cost method to program a small number of microcontrollers
566. to minimize noise during A D conversions Even if the A D converter will not be used Vy and ANGND must be connected to provide power to port 0 On the 8XC196MC and MD they also provide power to port 1 Refer to Analog Ground and Reference Voltages on page 12 12 for a detailed discussion of A D power and ground recommendations Multilayer printed circuit boards with separate and ground planes also help to minimize noise For more information on noise protection refer to AP 125 Designing Microcontroller Sys tems for Noisy Environments and AP 711 EMI Design Techniques for Microcontrollers in Auto motive Applications 13 4 THE ON CHIP OSCILLATOR CIRCUITRY The on chip oscillator circuit Figure 13 3 consists of a crystal controlled positive reactance os cillator In this application the crystal operates in a parallel resonance mode The feedback resis tor Rf consists of paralleled n channel and p channel FETs controlled by the internal powerdown signal In powerdown mode Rf acts as an open and the output drivers are disabled which disables the oscillator Both the XTAL1 and XTAL2 pins have built in electrostatic discharge ESD pro tection To internal circuitry XTAL2 Output XTAL1 Input Oscillator Enable from powerdown circuitry A0076 03 Figure 13 3 On chip Oscillator Circuit 18 5 8XC196MC MD MH USER S MANUAL intel Figure 13 4 shows the connections between the external cry
567. tput setting a bit configures a pin as an input or open drain output Open drain outputs require external pull ups P2 MODE P7_MODE 1FDOH 1FDOH 1FD1H 1FDOH Port x Mode Each bit of Px_MODE controls whether the corre sponding pin functions as a standard I O port pin or as a special function signal Setting a bit configures a pin as a special function signal clearing a bit configures as a standard port pin PO PIN P1 PIN P2 PIN P7 PIN 1FA8H 1FA9H 1FD6H 1 1FA9H 1FD6H 1FD7H 1FDAH 1F9FH 1FD6H Port x Input Each bit of Px PIN reflects the current state of the corresponding pin regardless of the pin configu ration P2 REG P7 REG 1FD4H 1FD4H 1FD5H 1FD4H Port x Data Output For an input set the corresponding Px_REG bit For an output write the data to be driven out by each pin to the corresponding bit of Px_REG When is configured as standard I O Px_MODE y 0 the result of a CPU write to Px_REG is immediately visible on the pin When a pin is configured as a special function signal Px_MODE y 1 the associated on chip peripheral or off chip component controls the pin The CPU can still write to Px_REG but the pin is unaffected until it is switched back to its standard I O function This feature allows software to configure a pin as standard I O clear initialize or overwrite the pin value then configure the
568. tput 0 Px 4 open drain output 1 assuming external pull up Px 5 Px 6 complementary output 0 Px 7 complementary output 1 To do so you could use the following example code segment Table 6 10 shows the state of each pin after reset and after execution of each line of the example code LDB Px_DIR 00011111B LDB 00000000B LDB Px_REG 10010011B 8XC196MC MD MH USER S MANUAL intel Table 6 10 Port Pin States After Reset and After Example Code Execution Action or Code Resulting Pin States Px 7 Px 6 Px 5 Px 4 Px 3 Px 2 Px 1 Px 0 Reset wk1 wk1 wk1 wk1 wk1 wk1 wk1 wk1 LDB Px_DIR 00011111B 1 1 1 wk1 wk1 wk1 wk1 wk1 LDB Px_MODE 00000000B 1 1 1 HZ1 HZ1 HZ1 HZ1 HZ1 LDB Px REG 10010011B 1 0 0 HZ1 0 0 HZ1 HZ1 t wk1 weakly pulled high HZ1 high impedance actually a 1 with an external pull up 6 3 4 Bidirectional Port Considerations This section outlines special considerations for using the pins of these ports Port 1 8 196 Port 2 2 7 Port 5 After reset your software must configure the device to match the external system This is accomplished by writing appropriate config uration data into MODE Writing to MODE not only configures the pins but also turns off the transistor that weakly holds the pins high Q4 in Figure 6 2 on page 6 8 For this reason even if port 1 is to be used as it
569. tput waveform is 8 19 ms If PWMx CONTROL equals 8AH 138 decimal the pulsewidth is held high for 4 42 ms and low for 3 77 ms of the total 8 19 ms period resulting in a duty cycle of approximately 54 10 5 2 Reading the Current Value of the Down counter You can read COUNT register to find the current value of the down counter see Fig ure 10 5 10 7 8XC196MC MD MH USER S MANUAL intel PWM COUNT Address 1FB6H read only Reset State 00H The PWM count PWM COUNT register provides the current value of the decremented period counter 7 0 PWM Count Value Bit Number Function 7 0 PWM Count Value This register contains the current value of the decremented period counter Figure 10 5 PWM Count PWM COUNT Register 10 5 3 Enabling the PWM Outputs Each PWM output is multiplexed with a port pin so you must configure it as a special function output signal before using the PWM function To determine whether the corresponding pin func tions as a standard I O port pin or as a PWM output you must make the proper selections by writ ing to the OUTPUT register see Figure 10 6 Table 10 4 shows the alternate port function along with the register setting that selects the PWM output instead of the port function Table 10 4 PWM Output Alternate Functions PWM Output Alternate Port Function PWM Output Enabled When PWMO P6 6 WG_OUT 11 1 1 6 7
570. tual characteristics taken from the same converter on the same channel with the same temperature voltage and frequency conditions The amount of repeatability error depends on the comparator s ability to resolve very similar voltages and the extent to which random noise contributes to the error A memory location that is reserved for factory use or for future expansion Do not use a reserved memory location except to initialize it with FFH The number of input voltage levels that an A D converter can unambiguously distinguish between The number of useful bits of information that the converter can return A small 2 3 pF capacitor used in the A D converter circuitry to store the input voltage on the selected input channel The time period between the time that A D converter receives the start conversion signal and the time that the sample capacitor is connected to the selected channel The variation in the sample delay intel sample time sample time uncertainty sample window sampled inputs SAR set SFR SHORT INTEGER sign extension sink current source current SP GLOSSARY The period of time that the sample window is open That is the length of time that the input channel is actually connected to the sample capacitor The variation in the sample time The period of time that begins when the sample capacitor is attached to a selected channel of an A D converter and ends when the sample c
571. tware downloading 1 10 Application notes ordering 1 6 Arithmetic instructions A 47 A 48 A 52 A 53 Assert defined 1 3 Auto programming mode 16 25 16 28 algorithm 16 28 circuit 16 25 16 26 memory map 16 27 PCCB 16 27 security key programming 16 29 Baud rate SIO port 7 12 7 14 Baud rate generator SIO port 7 12 BAUD_VALUE 7 13 BCLK1 0 B 14 BCLKx 7 2 BHE B 14 BIT defined 3 2 Bit test instructions A 17 Block diagram A D converter 12 1 address data bus 6 15 clock circuitry 2 7 core and peripherals 2 3 EPA 11 2 frequency generator 8 1 infrared remote control application 8 5 ports 6 3 6 8 6 15 6 16 SIO port 7 1 waveform generator 9 2 Block transfer mode See PTS BMOV instruction 2 9 A 45 A 49 BMOVI instruction A 3 9 10 A 45 A 49 BR indirect instruction A 2 A 10 A 49 A 55 Bulletin board system BBS 1 9 Bus controller 2 6 16 6 Bus control modes 15 21 15 31 address valid strobe 15 27 15 29 address valid with write strobe 15 30 15 31 Index 2 standard 15 22 15 24 write strobe 15 25 15 26 Bus control signals 15 21 Bus width modes 16 bit data bus 15 14 8 bit data bus 15 16 dynamic data bus 15 13 dynamic example 15 24 BUSWIDTH 16 25 16 27 B 15 idle powerdown reset status B 23 B 25 timing 15 11 definitions 15 13 diagram 15 12 requirements 15 13 BYTE defined 3 2 C Call instructions A 50 A 55 A 56 Carry C flag 3 4 A 4 A 5 A
572. unsigned Table 3 1 Operand Type Definitions Note 1 No of Addressing Operand Type Bits Signed Possible Values Restrictions BIT 1 No True 1 or False 0 As components of bytes BYTE No 0 through 28 1 0 through 255 None SHORT INTEGER Yes 27 through 27 1 None 128 through 127 WORD 16 No 0 through 216 1 Even byte address 0 through 65 535 INTEGER 16 Yes 215 through 215 1 Even byte address 32 768 through 32 767 DOUBLE WORD 32 No 0 through 232 1 An address in the lower Note 1 0 through 4 294 967 295 register file that is evenly divisible by four Note 2 LONG INTEGER 32 Yes 231 through 231 1 An address in the lower 2 147 483 648 through 2 147 483 647 register file that is evenly divisible by four Note 2 NOTES 1 32 bit variables are supported only as the operand in shift operati ons as the dividend in 32 by 16 divide operations and as the product of 16 by 16 multiply operations 2 For consistency with third party software you should adopt the C programming conventions for addressing 32 bit operands For more information refer to page 3 9 3 1 8XC196MC MD MH USER S MANUAL intel Table 3 2 lists the equivalent operand type names for both C programming and assembly lan guage Table 3 2 Equivalent Operand Types for Assembly and C Programming Languages Operand Types Assembly Language Equiva
573. unting up from 0001H to WG_RELOAD This produces a smoothly ascending count illustrated by the sawtooth wave in Figure 9 6 with a period that is equal to the WG_RELOAD value Figure 9 7 shows the operation of outputs and interrupts in edge aligned modes In mode 2 the registers are updated only once during the carrier period when the counter reaches the reload value In mode 3 the registers are also updated when an EPA peripheral function event occurs You must configure an EPA channel for this function See Chapter 11 Event Processor Array for information intel WAVEFORM GENERATOR WG RELOAD EPA Event WG RELOAD Updated Mode 3 Only Value NO TRIES gis Counter N i Enabled ey WG_COUNTER Value 1 Carrier Period Reset Write to WG_RELOAD A2639 01 Figure 9 6 Edge aligned Modes Counter Operation WG_COMPx EPA Event WG_COUNTER Carrier WG COUNTER gt WG_COMP i Period WG Interrupt 1 P6 0 WG1 Note Carrier period and duty cycle both i change since WG_COMPXx is not changed P6 1 WG1 Mode OPO OP1 1 PH1 0 PH1 1 1 2 1 A2653 01 Figure 9 7 Edge aligned Modes Output Operation 8XC196MH only The 8XC196MH device has an additional edge aligned mode mode 4 This mode prevents the output jitter that can occur in mode 3 when an EPA eve
574. unts up or down selects the clock Source and direction and determines the clock prescaler setting TIMER1 1F7AH 1F7AH 1F7AH Timer 1 Value This register contains the current value of timer 1 TIMER2 1F7EH 1F7EH 1F7EH Timer 2 Value This register contains the current value of timer 2 11 3 TIMER COUNTER FUNCTIONAL OVERVIEW The EPA has two 16 bit up down timer counters timer 1 and timer 2 which can be clocked in ternally or externally Each is called a timer if it is clocked internally and a counter if it is clocked externally Figure 11 2 illustrates the timer counter structure 8XC196MC MD MH USER S MANUAL intel T2CONTROL 2 0 Timer 2 Prescaler Module Overflow Timer 1 Overflow Underflow Underflow T2CONTROL 6 TIMERE Direction OVRTM Interrupt T1CONTROL 2 0 1 4 Timer 1 Prescaler Module Overflow Underflow Quadrature Count T1DIR T1CONTROL 6 Direction Quadrature Direction A3131 01 Figure 11 2 EPA Timer Counters The timer counters can be used as time bases for input captures output compares and pro grammed interrupts software timers When a counter increments from FFFEH to FFFFH or dec rements from 0001H to 0000H the counter overflow underflow interrupt pending bit is set This bit can optionally cause an interrupt The clock source direction control source count direction and resol
575. up or a device reset You must clear the watchdog register within 64K state times after a system power up or a device reset At that time you can choose a longer interval for subsequent watchdog resets If enabled the watchdog continues to run in idle mode The device must be awakened before the end of the reset interval to clear the watchdog otherwise the watchdog will reset the device which causes it to exit idle mode 18 13 intel 14 Special Operating Modes intel CHAPTER 14 SPECIAL OPERATING MODES The 8XC196MC MD and MH provide two power saving modes idle and powerdown They also provide an on circuit emulation ONCE mode that electrically isolates the device from the other system components This chapter describes each mode and explains how to enter and exit each Refer to Appendix A for descriptions of the instructions discussed in this chapter to Ap pendix B for descriptions of signal status during each mode and to Appendix C for details about the registers 14 4 SPECIAL OPERATING MODE SIGNALS AND REGISTERS Table 14 1 lists the signals and Table 14 2 lists the registers that are mentioned in this chapter Table 14 1 Operating Mode Control Signals Signal Port Pin Description P2 7 CLKOUT Clock Output MC MD Output of the internal clock generator The CLKOUT frequency is 2 only the oscillator input frequency CLKOUT has a 50 duty cycle CLKOUT is not implem
576. upt calls cannot occur immediately following a POPA instruction the last instruction RET will execute before another interrupt call can occur Notice that the preamble and exit code for this routine do not save or restore register RAM The interrupt service routine is assumed to allocate its own private set of registers from the lower reg ister file The general purpose register RAM in the lower register file makes this quite practical In addition the RAM in the upper register file is available via windowing see Windowing on page 4 12 5 19 8XC196MC MD MH USER S MANUAL intel 5 5 2 Determining the Source of an Interrupt When hardware detects an interrupt it sets the corresponding bit in the INT PEND or INT PENDI register Figures 5 10 and 5 11 It sets the bit even if the individual interrupt is disabled masked Hardware clears the pending bit when the program vectors to the interrupt ser vice routine The interrupt service routine can read INT PEND and INT PENDI to determine which interrupts are pending Software can generate an interrupt by setting a bit in INT PEND or INT PENDI register We recommend the use of the read modify write instructions such as AND and OR to modify these registers ANDB INT PEND 11111110B Clears the OVRTM pending bit ORB PEND 00000001B Sets the OVRTM pending bit Other methods could result in a partial interrupt cycle For example an interrupt could occur dur ing
577. use one pause next nextl all_done done end s jmp orp 1 ldb orb 1 1 ldb 1 1 1 1 1 1 jne orb sjmp orb s jmp ldb popa ret FREQUENCY GENERATOR buf_cnt 0 see if last byte has been sent dec buf cnt no all done buf cnt decrement byte count flag 11011111b shift_reg 1 send_one clear get bit flag shift MSB into carry flag send one else send zero flag 00000001b wsr 7BH comp3_con_w 01000000b comp3_time_w timerl_w zero_time wsr 7EH p7_mode_w 10000000b wsr zero_reg done zero s flag Set up EPA Start FREQOUT flag 00000010b wsr 7BH comp3_con_w 01000000b comp3_time_w timerl_w one_time wsr 7EH p7_mode_w 10000000b wsr zero_reg done one s flag Set up EPA start FREQOUT flag 11111110b turn off zero flag wsr 7EH p7_mode_w 01111111b turn off FREQOUT wsr 7BH set up EPA comp3_con_w 01000000b comp3_time_w timerl_w zero_pause_time wsr zero_reg next flag 11111101b turn off one flag wsr 7EH p7_mode_w 01111111b turn off FREQOUT wsr 7BH set up EPA comp3_con_w 01000000b comp3_time_w timerl_w one_pause_time wsr zero_reg bit cnt decrement bit count bit cnt 400H check if 8 bits sent nextl get next bit f
578. ust be aligned on an address that is evenly divisible by 2 The value must be in the range of 00 FEH XXX The three high order bits of displacement The Dor S prefix is used only when it could be unclear whether a variable refers to a destination or a Source register A 6 intel INSTRUCTION SET REFERENCE Table A 6 Instruction Set Mnemonic Operation Instruction Format ADD ADD WORDS Adds the source and DEST SRC 2 operands destination word operands and stores the ADD wreg waop sum into the destination operand DEST lt DEST SRC PSW Flag Settings 2 V VT ST 011001 waop wreg ADD 3 operands ADD WORDS Adds the two source word operands and stores the sum into the destination operand DEST lt SRC1 SRC2 PSW Flag Settings 2 V VT ST Vi vi I7111 DEST SRC1 SRC2 ADD Dwreg Swreg waop 010001 waop Swreg Dwreg ADDB 2 operands ADD BYTES Adds the source and destination byte operands and stores the sum into the destination operand DEST lt DEST SRC PSW Flag Settings 2 V VT ST DEST SRC ADDB breg baop 011101 breg ADDB 3 operands ADD BYTES Adds the two source byte operands and stores the sum into the destination operand DEST lt SRC1 SRC
579. ust be located on a quad word boundary in the internal register file 5 4 intel STANDARD AND PTS INTERRUPTS Table 5 3 Interrupt Sources Vectors and Priorities ee PTS Service Interrupt Source Mnemonic o 5 gt 5 gt 9 5 9 5 2 gt 2 gt Nonmaskable Interrupt NMI INT15 203EH 30 EXTINT Pin EXTINT INT14 203CH 14 PTS14 205CH 29 WF Gen MC PI WF Gen amp EPA Comp 5 MD PI INT13 203AH 13 PTS13 205AH 28 Waveform Generator MH WG Reserved MC EPA Cap Comp 5 MD 5 12 2038 12 PTS12 2058 27 100 amp 1 Receive Err MH SPI Reserved MC EPA Compare 4 MD COMP4 INT11 2036H 11 PTS11 2056H 26 SIO1 Receive MH RI1 Reserved MC EPA Cap Comp 4 MD EPA4 INT10 2034H 10 PTS10 2054H 25 100 Receive MH RIO DOMOS 09 2032H 09 509 2052H 24 SIO1 Transmit MH 218 ERAS 08 2030H 08 508 2050 23 5 0 Transmit MH TIO Unimplemented Opcode 2012H Software TRAP Instruction 2010 mE mE EPA Copt dE niis INTO7 200EH 07 507 204EH 22 EPA Compare 3 MH COMP3 omy MG MD EPA2 06 200 06 506 204 21 2 2 1 1 INTO5 200AH 05 505 204AH 20 EPA Capture Compare 1 EPA1 04 2008 04 50
580. ust save and restore both the PSW and TMPREGO 3 5 SOFTWARE PROTECTION FEATURES AND GUIDELINES The device has several features to assist in recovering from hardware and software errors The unimplemented opcode interrupt provides protection from executing unimplemented opcodes The hardware reset instruction RST can cause a reset if the program counter goes out of bounds The RST instruction opcode is FFH so the processor will reset itself if it tries to fetch an instruc tion from unprogrammed locations in nonvolatile memory or from bus lines that have been pulled high The watchdog timer WDT can also reset the device in the event of a hardware or software error We recommend that you fill unused areas of code with NOPs and periodic jumps to an error rou tine or RST instruction This is particularly important in the code surrounding lookup tables since accidentally executing from lookup tables will cause undesired results Wherever space allows surround each table with seven NOPs because the longest device instruction has seven bytes and a RST or a jump to an error routine Since RST is one byte instruction the NOPs are unneces sary if RSTs are used instead of jumps to an error routine This will help to ensure a speedy re covery from a software error 8XC196MC MD MH USER S MANUAL intel When using the watchdog timer WDT for software protection we recommend that you reset the WDT from only one place in code reducing the ch
581. ution of the input capture or output compare are all programmable see Programming the Timers on page 11 15 The maximum count rate is one half the internal clock rate or Fyz411 4 see Internal Timing on page 2 7 This provides a minimum resolution for an input capture or output compare of 250 ns at 16 MHz 4x prescaler divisor resolution XTAL1 intel EVENT PROCESSOR ARRAY EPA where prescaler divisor is the clock prescaler divisor from the registers see Timer 1 Control T1 CONTROL Register on page 11 16 and Timer 2 Control T2CONTROL Register on page 11 17 Fyra is the input frequency on XTAL1 11 3 1 Cascade Mode Timer 2 Only Timer 2 can be used in cascade mode In this mode the timer 1 overflow output is used as the timer 2 clock input Either the direction control bit of the timer 2 control register or the direction control assigned to timer 1 controls the count direction This method called cascading can pro vide a slow clock for idle mode timeout control or for slow pulse width modulation PWM ap plications see Generating a Low speed PWM Output on page 11 13 11 3 2 Quadrature Clocking Modes Timer 1 can be used in two quadrature clocking modes Both modes use the TICLK and T1DIR pins as quadrature inputs as shown in Figure 11 3 External quadrature encoded signals two sig nals at the same frequency that differ in phase by 90 are input and the timer increment
582. vailable from the application BBS and a BBS user s guide The BBS file listing is also available from FaxBack catalog number 6 see page 1 8 for phone num bers and a description of the FaxBack service 1 800 897 2536 U S and Canada only Any customer with a modem and computer can access the BBS The system provides automatic configuration support for 1200 through 19200 baud modems Typical modem settings are 14400 baud no parity 8 data bits and 1 stop bit 14400 8 1 To access the BBS just dial the telephone number and respond to the system prompts During your first session the system asks you to register with the system operator by entering your name and location The system operator will set up your access account within 24 hours At that time you can access the files on the BBS NOTE If you encounter any difficulty accessing the high speed modem try the dedicated 2400 baud modem Use these modem settings 2400 N 8 1 8XC196MC MD MH USER S MANUAL intel 1 4 2 1 How to Find MCS 96 Microcontroller Files on the BBS Application notes utilities and product literature are available from the BBS To access the files complete these steps 1 EnterF from the BBS Main menu The BBS displays the Intel Apps Files menu 2 Type L and press Enter The BBS displays the list of areas and prompts for the area number 3 Type 12 and press Enter to select MCS 96 Family The BBS displays a list of subject
583. ve or temp1 temp combine ld temp phl get phl bits and temp 0004h mask for phl 2 shl temp 6h move or temp1 temp combine Ta temp p7 get p7 bit and temp 40001h mask shl temp 7 move to correct location 9 23 8XC196MC MD MH USER S MANUAL intel 1 shl or 1 shl or 1 shl or 1 or st ret templ temp combine temp p6 get bit temp 0001h mask temp 6 move to correct location templ temp combine temp ph3 get ph3 bits again temp 0003h mask for ph3 0 amp 1 temp 4h move temp1 temp combinel temp ph2 get ph2 bits again temp 0003h mask for ph2 0 amp 1 temp 2h move templ temp combine temp phl get phl bits again temp 0003h mask for ph3 0 amp 1 templ temp combine don t need to move templ WG 01 now store it AAA AAA KU form WG CONTROL value S EHE to eub ko Kb OU ROAR wgcon 1 shl 1 shl or ld and or st ret tem tem tem tem tem tem tem tem tem tem tem load the WG_RELOA GU RE KU REO UR KO eo e loadregs st st st st ret rel com com com RIAA AAR load WG_PROTECT AL EAA GAA AAR protect ldtemp es 9 24 p mode get mode 0003h mask p 12 shift to cor
584. verflow flag If the flag is set JNV cadd control passes to the next sequential instruction If the overflow is clear this 11010101 disp instruction adds to the program counter the offset between the end of this instruction and NOTE The displacement disp is sign the target label effecting the jump The offset extended to 16 bits must be in range of 128 to 127 if V 2 0 then PC lt PC 8 bit disp PSW Flag Settings Z N C V VT ST A 21 8XC196MC MD MH USER S MANUAL Table A 6 Instruction Set Continued lel Mnemonic Operation Instruction Format JNVT JUMP IF OVERFLOW TRAP FLAG IS CLEAR Tests the overflow trap flag If the flag is set this instruction clears the flag and passes control to the next sequential instruction If the overflow trap flag is clear this instruction adds to the program counter the offset between the end of this instruction and the target label effecting the jump The offset must be in range of 128 to 127 if VT 0 then PC lt PC 8 bit disp PSW Flag Settings Z N C V VT ST 0 JNVT cadd 11010100 disp NOTE The displacement disp is sign extended to 16 bits JST JUMP IF STICKY BIT FLAG IS SET Tests the sticky bit flag If the flag is clear control passes to the next sequential instruction If the sticky bit flag is
585. vers Table 6 13 is a logic table for ports 3 and 4 as I O Internal Bus Address Data Pin BUS CONTROL SELECT RESET 0 Address Data 1 A3116 01 Figure 6 3 Address Data Bus Ports 3 and 4 Structure 8XC196MC MD MH USER S MANUAL intel Table 6 13 Logic Table for Ports and 4 as Open drain I O Configuration Open drain Px REG 0 1 Q1 off off Q2 on off Px PIN 0 high impedance 6 4 2 Using Ports and 4 as I O To use a port pin as an output write the output data to the corresponding Px REG bit When the device requires access to external memory it takes control of the port and drives the address data bit onto the pin The address data bit replaces your output during this time When the external ac cess is completed the device restores your data onto the pin To use a port pin as an input set the corresponding Px REG bit to drive the pin to a high imped ance state You may then read the pin s input value in the Px PIN register When the device re quires access to external memory it takes control of the port You must configure the input source to avoid contention on the bus 6 4 3 Design Considerations for Ports and 4 When EA is active ports 3 and 4 will function only as the address data bus In these circum stances an instruction that operates on P3 REG or P4 REG causes a bus cycle that reads from or writes to the external memory location correspon
586. vidually selectable special function signals On the 8XC196MH port 1 is multiplexed as follows P1 0 TXDO P1 1 RXDO P1 2 TXD1 and P1 3 RXD1 8XC196MC MD MH USER S MANUAL intel Table B 6 Signal Descriptions Continued Name Type Description P2 7 0 yo Port 2 This is a standard 8 bit bidirectional port that is multiplexed with individually selectable special function signals P2 6 is multiplexed with a special test mode entry function If this pin is held low during reset the device will enter a reserved test mode so exercise caution if you use this pin for input If you choose to configure this pin as an input always hold it high during reset and ensure that your system meets the specification see datasheet to prevent inadvertent entry into ONCE mode On the 8XC196MC and MD port 2 is multiplexed as follows P2 0 EPAO PVER P2 1 EPA1 PALE P2 2 EPA2 PROG P2 3 EPA3 2 4 P2 5 COMP1 PACT P2 6 COMP2 CPVER and P2 7 COMP3 On the 8XC196MH port 2 is multiplexed as follows 2 0 P2 1 SCLKO BCLKO PALE P2 2 EPA1 PROG P2 3 COMP3 P2 4 COMPO AINC P2 5 COMP 1 PACT P2 6 COMP2 CPVER and P2 7 SCLK1 BCLK1 P3 7 0 VO Port This is a memory mapped 8 bit bidirectional port with programmable open drain or complementary output modes The pins are shared with the multiplexed address data bus which has complementary drivers P3 7 0 are multipl
587. w DEST lt DEST SRC 1 0 PSW Flag Settings Z N C V VT ST 38 intel INSTRUCTION SET REFERENCE Table A 6 Instruction Set Continued Mnemonic Operation Instruction Format TIJMP TABLE INDIRECT JUMP Causes execution to continue at an address selected from a table of addresses The first word register TBASE contains the 16 bit address of the beginning of the jump table TBASE can be located in RAM up to FEH without windowing or above FFH with windowing The jump table itself can be placed at any nonreserved memory location word boundary The second word register INDEX contains the 16 bit address that points to a register containing a 7 bit value This value is used to calculate the offset into the jump table Like TBASE INDEX can be located in RAM up to FEH without windowing or above FFH with windowing Note that the 16 bit address contained in INDEX is absolute it disregards any windowing that may be in effect when the TIJMP instruction is executed The byte operand MASK is 7 bit immediate data to mask INDEX MASK is ANDed with INDEX to determine the offset OFFSET OFFSET is multiplied by two then added to the base address TBASE to determine the destination address DEST X INDEX AND MASK OFFSET 2 x OFFSET TBASE DEST X PC lt DEST X PSW Flag Settings ST
588. w flag after each operation 11 Carry Flag This flag is set to indicate an arithmetic carry or the last bit shifted out of an operand It is cleared if a subtraction operation generates a borrow Normally the result is rounded up if the carry flag is set The sticky bit flag allows a finer resolution in the rounding decision See the PSW flag descriptions in Appendix A for details 10 PSE PTS Enable This bit globally enables or disables the peripheral transaction server PTS The EPTS instruction sets this bit DPTS clears it 0 disable PTS 1 enable PTS 9 Interrupt Disable Global This bit globally enables or disables the servicing of all maskable interrupts The bits in INT MASK and INT_MASK1 individually enable or disable the interrupts The EI instruction sets this bit DI clears it 0 disable interrupt servicing 1 enable interrupt servicing 8 ST Sticky Bit Flag This flag is set to indicate that during a right shift a 1 was shifted into the carry flag and then shifted out It can be used with the carry flag to allow finer resolution in rounding decisions C 41 8XC196MC MD MH USER S MANUAL PTSSEL intel PTSSEL Address Reset State 0004H 0000H The PTS select PTSSEL register selects either a PTS microcode routine or a standard interrupt service routine for each interrupt request Setting a bit selects a PTS microcode routine clearing a bit sel
589. ware implementations and present helpful design techniques Embedded Applications handbook 2 volume set 270648 Datasheets architecture descriptions and application notes on topics including flash memory devices networking chips and MCS 51 and MCS 96 microcon trollers Documents in this handbook discuss hardware and software implementa tions and present helpful design techniques Embeaded Microcontrollers 270646 Datasheets and architecture descriptions for Intel s three industry standard micro controllers the MCS 48 MCS 51 and MCS 96 microcontrollers Peripheral Components 296467 Comprehensive information on Intel s peripheral components including datasheets application notes and technical briefs Flash Memory 2 volume set 210830 A collection of datasheets and application notes devoted to techniques and information to help design semiconductor memory into an application or system Packaging 240800 Detailed information on the manufacturing applications and attributes of a variety of semiconductor packages Development Tools Handbook 272326 Information on third party hardware and software tools that support Intel s embedded microcontrollers Included in handbook set order number 231003 Table 1 2 Application Notes Application Briefs and Article Reprints Title Order Number AB 71 Using the SIO on the 8XC196MH application brief 272594 AP 125 Designing Mic
590. watchdog timer and selects the bus timing mode Two of its bits combine with three bits of CCRO to control wait states and bus width P5 DIR 1FF3H Port 5 Direction Each bit of P5_DIR controls the direction of the corresponding pin Clearing a bit configures a pin as a complementary output setting a bit configures a pin as an input or open drain output Open drain outputs require external pull ups P5 MODE 1FF1H Port 5 Mode Each bit of MODE controls whether the corresponding pin functions as a standard I O port pin or as a special function signal Setting a bit configures a pin as a special function signal clearing a bit configures a pin as a standard port pin P5 PIN 1FF7H Port 5 Input Each bit of P5 PIN reflects the current state of the corresponding pin regardless of the pin configuration 15 4 intel INTERFACING WITH EXTERNAL MEMORY Table 15 2 External Memory Interface Registers Continued Register us Address Description P5 REG 1FF5H Port 5 Data Output For an input regardless of the pin s configuration set the corresponding P5 REG bit For an output write the data to be driven out by each pin to the corre sponding bit of P5 REG When pin is configured as standard I O P5 MODE y 0 the result of a CPU write to P5 REG is immediately visible on the pin When a pin is configured as a special function signal P5 MODE y 1 the associated on chip peripheral or off chip
591. wed direct ad dress as follows 1 Subtract the base address of the area to be remapped from Table 4 11 on page 4 15 from the address of the desired location This gives you the offset of that particular location 2 Add the offset to the base address of the window from Table 4 12 on page 4 15 The result is the windowed direct address Appendix C includes a table of the windowable SFRs with the WSR values and windowed direct addresses for each window size Examples beginning on page 4 16 explain how to determine the WSR value and windowed direct address for any windowable location An additional example shows how to set up a window by using the linker locator ntel MEMORY PARTITIONS Table 4 11 Windows Base WSR Value WSR Value T for Address for 32 byte Window for 64 byte Window Window 00E0 00FFH 00C0 00FFH MON ones Peripheral SFRs 1FEOH 7FH Note 1FCOH 7EH 3FH Note 1 7DH 1F80H 7CH 3EH 1FH Note 1F60H 7BH 1F40H 7AH 3DH 1F20H 79H 1F00H 78H 3CH 1EH 02E0H 57H 02 0 56H 2BH 02A0H 55H 0280H 54H 2AH 15H 0260H 53H 0240H 52H 29H 0220H 51H 0200H 50H 28H 14H 01E0H 4FH 01COH 4EH 27H 01A0H 4DH 0180H 4CH 26H 13H 0160H 4BH 0140H 4AH 25H 0120H 49H 0100H 48H 24H 12H NOTE Locations 1FEO 1FFFH contain memory mapped SFRs that cannot be accessed through window Reading these locations through a window returns FFH w
592. window closes The ability of the A D converter to reject an input on its selected channel after the sample window closes Field effect transistor The 8XC196MD peripheral that generates outputs with a fixed 50 duty cycle and a programmable frequency The frequency generator can be used for infrared transmission Glossary 3 8XC196MC MD MH USER S MANUAL full scale error hold latency ideal characteristic input leakage input series resistance integer INTEGER interrupt controller interrupt latency interrupt service routine interrupt vector ISR linearity errors LONG INTEGER Glossary 4 intel The difference between the ideal and actual input voltage corresponding to the final full scale code transition of an A D converter The time it takes the microcontroller to assert HLDA after an external device asserts HOLD The characteristic of an ideal A D converter An ideal characteristic is unique its first code transition occurs when the input voltage is 0 5 LSB its full scale final code transition occurs when the input voltage is 1 5 LSB less than the full scale reference and its code widths are all exactly 1 0 LSB These properties result in a conversion without zero offset full scale or linearity errors Quantizing error is the only error seen in an ideal A D converter Current leakage from an input pin to power or ground The effective series resistance from an analog input pin
593. with each successive reception PTSCON1 PTSCB2 3 PTS Control Bits Synchronous Mode TRC Transmit Receive Control 0 transmit or receive data during even numbered PTS cycles 1 transmit or receive data during odd numbered PTS cycles Initialize this bit at the start of every transmission or reception Asynchronous Mode RPAR Receive Parity Control and Status Initialize this bit as indicated before beginning a reception 0 TPAR bit is set to select even parity 1 TPAR bit is cleared to select odd parity If this bit is set at the end of a reception a parity error has occurred PEN Parity Enable 0 disble parity 1 enable parity FE Framing Error Flag 0 stop bit was 1 1 stop bit was 0 Clear this bit at the start of every reception Transmit Parity Control 0 even parity 1 odd parity Figure 5 20 PTS Control Block 2 Serial I O Mode Continued 5 42 intel STANDARD AND PTS INTERRUPTS PTS Serial I O Mode Control Block 2 Continued 8XC196MC MD Register Location Function PORTMASK PTSCB2 2 Port Mask Register Select the port signal that will function as the transmit data TXD or receive data RXD signal by setting the corresponding bit Clear all other bits to mask those signals PORTREG PTSCB2 0 Port Address Pointer This 16 bit register contains the address of the port that will be used to transmit o
594. word transfer DI PTSDST Autoincrement 0 do not increment the contents of PTSDST after each byte or word transfer 1 increment the contents of PTSDST after each byte or word transfer PTSCOUNT PTSCB 0 Consecutive Block Transfers Defines the number of blocks that will be transferred during the block transfer routine Each block transfer is one PTS cycle Maximum number is 255 Figure 5 17 PTS Control Block Block Transfer Mode Continued 5 6 5 Scan Mode In the A D scan mode the PTS causes the A D converter to perform multiple conversions on one or more channels and then stores the results in a table in memory Figure 5 19 shows the PTS con trol block for A D scan mode 5 32 intel STANDARD AND PTS INTERRUPTS PTS A D Scan Mode Control Block In A D scan mode the PTS causes the A D converter to perform multiple conversions on one or more channels and then stores the results The control block contains pointers to both the AD RESULT register PTSPTR1 and a table of A D conversion commands and results PTSPTR2 a control register PTSCON and an A D conversion count PTSCOUNT 7 0 Unused 0 0 0 0 0 0 0 0 7 0 Unused 0 0 0 0 0 0 0 0 15 8 PTSPTR2 H Pointer 2 Value high byte 7 0 PTSPTR2 L Pointer 2 Value low byte 15 8 PTSPTR1 H Pointer 1 Value high byte 7 0 PTSPTR1 L Pointer 1
595. write the pin value then configure the as a special function signal set MODE y In this way initial ization fault recovery exception handling etc can be done without changing the operation of the associated peripheral 6 3 1 Bidirectional Port Operation Figure 6 2 shows the logic for driving the output transistors Q1 and Q2 Q1 can source at least 3 mA at 0 7 volts Q2 can sink at least 3 mA at 0 45 volts Consult the datasheet for spec ifications 6 6 intel PORTS In I O mode selected by clearing Px_MODE y REG and Px DIR are input to the multiplex ers These signals combine to drive the gates of Q1 and Q2 so that the output is high low or high impedance Table 6 6 is a logic table for I O operation of these ports In special function mode selected by setting MODE y SFDIR and SFDATA are input to the multiplexers These signals combine to drive the gates of Q1 and Q2 so that the output is high low or high impedance Special function output signals clear SFDIR special function input sig nals set SFDIR Table 6 7 is a logic table for special function operation of these ports Even if a pin is to be used in special function mode you must still initialize the pin as an input or output by writing to Px DIR Resistor R1 provides ESD protection for the pin Input signals are buffered The standard ports use Schmitt triggered buffers for improved noise immunity Por
596. x 2 5 7 8XC196MD 1 2 5 8XC196MH Each bit of the port x mode Px_MODE register controls whether the corresponding pin functions as a Address Table C 7 Reset State standard I O port or as a special function signal 7 0 1 MH 2 PIN1 7 0 X 2 5 6 PIN5 PIN4 2 PIN1 PINO 7 0 xz 7 MD PIN7 PIN6 PIN5 PIN4 2 PIN1 PINO Bit Bit Number Mnemonic Function 7 07 PIN7 0 Port x Pin y Mode This bit determines the mode of the corresponding port pin 0 standard I O port pin 1 special function signal Table C 8 lists the special function signals for each pin The bits shown as dashes are reserved for compatibility with future devices write zeros to these bits Table C 7 Px MODE Addresses and Reset Values Register Address Reset Value P1 MODE 8XC196MH 1F99H 00H P2 MODE 8XC196Mx 1FDOH 00H P5 MODE 8XC196MC MD 1FF1H FFH when pin is not driven P5 MODE 8XC196MH 1FF1H 80H if the EA pin is high A9H if EA is low P7 MODE 8XC196MD 1FD1H 00H C 31 8XC196MC MD MH USER S MANUAL Px_MODE Table C 8 Special function Signals for Ports 1 2 5 6 Port 1 Port 2 Port 2 8 196 8XC196MC MD 8XC196MH Pin oe e Pin gar Hala Pin
597. y a Reserved each location must contain FFH 201B Reserved must contain 20H 201A CCB1 2019 Reserved must contain 20H 2018 CCBO Reserved each location must contain 2013 2000 Lower interrupt vectors 16 3 SECURITY FEATURES Several security features enable you to control access to both internal and external memory Read and write protection bits in the chip configuration register CCRO combined with a security key allow various levels of internal memory protection Two UPROM bits disable fetches of instruc tions and data from external memory See Figure 16 1 on page 16 7 for more information 16 3 1 Controlling Access to Internal Memory The lock bits in the chip configuration register CCRO control access to the OTPROM The reset sequence loads the CCRs from the CCBs for normal operation and from the PCCBs when enter ing programming modes You can program the CCBs using any of the programming methods but only slave and PCCB programming modes allow you to program the PCCBs The developers have made a substantial effort to provide an adequate program protection scheme However Intel cannot and does not guarantee that these protection methods will always prevent unauthorized access NOTE 16 3 8XC196MC MD MH USER S MANUAL intel 16 3 1 1 Controlling Access to the OTPROM During Normal Operation During normal operation the lock bits in CCBO control read and write accesses to the OTPROM
598. y 5 mV 1024 If such a converter is specified to have a maximum differential nonlinearity of 2 LSBs 10 mV the maximum code width will be no greater than 10 mV larger than ideal or 15 mV Because the A D converter has no missing codes the minimum code width will always be greater than 1 negative one The differential nonlinearity error on a particular code width is compen sated for by other code widths in the transfer function such that 1024 unique steps occur The actual code widths in this converter typically vary from 2 5 mV to 7 5 mV Nonlinearity is the worst case deviation of code transitions from the corresponding code transi tions of the ideal characteristic Nonlinearity describes the extent to which differential nonlinear ities can add up to produce an overall maximum departure from a linear characteristic If the differential nonlinearity errors are too large it is possible for an A D converter to miss codes or to exhibit non monotonic behavior Neither behavior is desirable in a closed loop system A con verter has no missing codes if there exists for each output code a unique input voltage range that produces that code only A converter is monotonic if every subsequent code change represents an input voltage change in the same direction Differential nonlinearity and nonlinearity are quantified by measuring the terminal based linear ity errors A terminal based characteristic results when an actual characteristi
599. y 16 divide operations and as the product of 16 by 16 multiply operations For these operations a LONG INTEGER variable must reside in the lower register file and must be aligned at an address that is evenly di visible by four The address of a LONG INTEGER is that of its least significant byte the even byte address LONG INTEGER operations that are not directly supported can be easily implemented with two INTEGER operations See the example in DOUBLE WORD Operands on page 3 3 3 1 8 Converting Operands The instruction set supports conversions between the operand types The LDBZE load byte zero extended instruction converts a BYTE to a WORD CLR clear converts a WORD to a DOUBLE WORD by clearing writing zeros to the upper WORD of the DOUBLE WORD LDBSE load byte sign extended converts a SHORT INTEGER into an INTEGER EXT sign extend converts an INTEGER to a LONG INTEGER 3 1 9 Conditional Jumps The instructions for addition subtraction and comparison do not distinguish between unsigned BYTE WORD and signed SHORT INTEGER INTEGER operands However the condition al jump instructions allow you to treat the results of these operations as signed or unsigned quan tities For example the CMP compare instruction is used to compare both signed and unsigned 16 bit quantities Following a compare operation you can use the JH jump if higher instruction for unsigned operands or the JGT jump if greater than instruction f
600. ycle The reload register RELOAD and the phase compare registers WG_COMPx control the carrier period and duty cycle Write a value to the reload register Figure 9 10 to establish the carrier period Write a value to each phase compare register to specify the length of time that the associated outputs will remain asserted WG RELOAD Address 1FC8H B Reset State 0000H The waveform generator reload WG RELOAD register and the phase compare registers COMP control the carrier period and duty cycle Write a value to the reload register to establish the carrier period Changing the WG RELOAD value changes both the carrier period and the duty cycle because the outputs remain asserted for a constant length of time while the counter takes longer to cycle To change the carrier period without changing the duty cycle you must proportionally change both WG RELOAD and WG COMPx at the same time immediately after the interrupt 15 0 Reload Bit i Number Function 15 0 Reload This register determines the carrier period Use the following formulas to calculate carrier period and duty cycle T multiplier x WG RELOAD CARRIER FyTAL1 But indo ee WG RELOAD s where TeaRRIER carrier period in us Fra input frequency on XTAL1 in MHz multiplier 4forcenter aligned modes 2 for edge aligned modes WG RELOAD 16 bit WG RELOAD value gt COMPx WG COMPx 16 bit WG_
601. ystem us ing an external 16 bit data bus Figure 15 20 shows the timing The RD signal not shown is similar to WRL and WRH The example system of Figure 15 21 uses address valid with write strobe to access byte wide RAMs with a 16 bit data bus ADV ADV AD15 0 Data Out AD15 8 Address High 16 bit Bus Cycle 8 bit Bus Cycle A3096 02 Figure 15 20 Timings of Address Valid with Write Strobe Mode 15 30 intel INTERFACING WITH EXTERNAL MEMORY Voc BUSWIDTH AD15 8 ADV 8XC196 AD7 0 A3097 01 Figure 15 21 16 bit System with RAM 15 6 SYSTEM BUS AC TIMING SPECIFICATIONS Refer to the latest datasheet for the AC timings to make sure your system meets specifications The major external bus timing specifications are shown in Figure 15 22 15 31 8XC196MC MD MH USER S MANUAL intel XTAL1 CLKOUT ALE ADV RD AD15 0 read WR AD15 0 write BHE INST AD15 8 8 bit mode gt Tavi Address Out TRHAX Address Out The CLKOUT pin is available only on the 8XC196MC MD A3166 01 15 32 Figure 15 22 System Bus Timing intel INTERFACING WITH EXTERNAL MEMORY 15 6 1 Explanation of AC Symbols Each symbol consists of two pairs of letters prefixed by for time The ch
602. yte Window 128 byte Window 00E0 00FFH 00C0 00FFH 0080 00FFH Port 2 Waveform generator 7EH 3FH Port 7 MD only Peripheral interrupts Pulse width modulator 1FH A D converter 7DH Frequency generator MD only 3EH Reset control MH only Port 1 MH only Serial I O port MH only Timer 1 2 2 3 7BH EPA compare 0 5 MD EPA compare 0 2 MH EPA capture compare 0 3 MC 3DH 1EH EPA compare 0 1 MC EPA capture compare 0 5 MD 7AH EPA capture compare 0 1 MH EPA compare 3 MH 4 13 8XC196MC MD MH USER S MANUAL intel Table 4 10 Selecting a Window of the Upper Register File 2 WSR Val WSR Val WSR Val ar it for 3 s Window for sie Window for 00 0 00 00C0 00FFH 0080 00FFH 8XC196MH Only 02 0 02 57H 02C0 02DFH 56H 2BH 02 0 02 55H 0280 029 54H 2AH 15H 0260 027FH 53H 0240 025FH 52H 29H 0220 023FH 51H 0200 021 50H 28H 14H 8XC196MC 8XC196MD and 8XC196MH 01 0 01 4FH 01C0 01DFH 4EH 27H 01 0 01 4DH 0180 019 4CH 26H 13H 0160 017 4 0140 015FH 4AH 25H 0120 013FH 49H 0100 011 48 24H 12H 4 2 2 Addressing a Location Through a Window After you have selected the desired window you need to know the windowed direct address of the memory location the address in the lower register file Calculate the windo
603. ze Specifies the number of bytes or words in each block Valid values are 1 32 inclusive PTSDST PTSCB 4 PTS Destination Address Write the destination memory location to this register A valid address is any unreserved memory location however it must point to an even address if word transfers are selected PTSSRC PTSCB 2 PTS Source Address Write the source memory location to this register A valid address is any unreserved memory location however it must point to an even address if word transfers are selected Figure 5 17 PTS Control Block Block Transfer Mode 5 81 8XC196MC MD MH USER S MANUAL intel PTS Block Transfer Mode Control Block Continued Register Location Function PTSCON PTSCB 1 PTS Control Bits M2 0 PTS Mode These bits select the PTS mode M2 1 0 0 0 0 block transfer mode BW Byte Word Transfer 0 word transfer 1 byte transfer SU Update PTSSRC 0 reload original PTS source address after each block transfer is complete 1 retain current PTS source address after each block transfer is complete DU Update PTSDST 0 reload original PTS destination address after each block transfer is complete 1 retain current PTS destination address after each block transfer is complete Sl PTSSRC Autoincrement 0 do not increment the contents of PTSSRC after each byte or word transfer 1 increment the contents of PTSSRC after each byte or

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